1 // Bitcasts between 512-bit vector types. Return the original type since
2 // no instruction is needed for the conversion
3 let Predicates = [HasAVX512] in {
4 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
5 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
6 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
7 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
8 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
9 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
10 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
11 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
12 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
13 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
14 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
15 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
16 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
18 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
19 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
20 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
21 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
22 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
23 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
24 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
25 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
26 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
27 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
28 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
29 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
30 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
31 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
32 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
33 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
34 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
35 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
36 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
37 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
38 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
39 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
40 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
41 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
42 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
43 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
44 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
45 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
46 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
47 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
49 // Bitcasts between 256-bit vector types. Return the original type since
50 // no instruction is needed for the conversion
51 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
52 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
53 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
54 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
55 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
56 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
57 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
58 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
59 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
60 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
61 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
62 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
63 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
64 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
65 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
66 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
67 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
68 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
69 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
70 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
71 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
72 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
73 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
74 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
75 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
76 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
77 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
78 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
79 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
80 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
84 // AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
87 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
88 isPseudo = 1, Predicates = [HasAVX512] in {
89 def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
90 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
93 let Predicates = [HasAVX512] in {
94 def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
95 def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
96 def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
99 //===----------------------------------------------------------------------===//
100 // AVX-512 - VECTOR INSERT
103 let hasSideEffects = 0, ExeDomain = SSEPackedSingle in {
104 def VINSERTF32x4rr : AVX512AIi8<0x18, MRMSrcReg, (outs VR512:$dst),
105 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
106 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
107 []>, EVEX_4V, EVEX_V512;
109 def VINSERTF32x4rm : AVX512AIi8<0x18, MRMSrcMem, (outs VR512:$dst),
110 (ins VR512:$src1, f128mem:$src2, i8imm:$src3),
111 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
112 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
115 // -- 64x4 fp form --
116 let hasSideEffects = 0, ExeDomain = SSEPackedDouble in {
117 def VINSERTF64x4rr : AVX512AIi8<0x1a, MRMSrcReg, (outs VR512:$dst),
118 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
119 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
120 []>, EVEX_4V, EVEX_V512, VEX_W;
122 def VINSERTF64x4rm : AVX512AIi8<0x1a, MRMSrcMem, (outs VR512:$dst),
123 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
124 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
125 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
127 // -- 32x4 integer form --
128 let hasSideEffects = 0 in {
129 def VINSERTI32x4rr : AVX512AIi8<0x38, MRMSrcReg, (outs VR512:$dst),
130 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
131 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
132 []>, EVEX_4V, EVEX_V512;
134 def VINSERTI32x4rm : AVX512AIi8<0x38, MRMSrcMem, (outs VR512:$dst),
135 (ins VR512:$src1, i128mem:$src2, i8imm:$src3),
136 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
137 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
141 let hasSideEffects = 0 in {
143 def VINSERTI64x4rr : AVX512AIi8<0x3a, MRMSrcReg, (outs VR512:$dst),
144 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
145 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
146 []>, EVEX_4V, EVEX_V512, VEX_W;
148 def VINSERTI64x4rm : AVX512AIi8<0x3a, MRMSrcMem, (outs VR512:$dst),
149 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
150 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
151 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
154 def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (v4f32 VR128X:$src2),
155 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
156 (INSERT_get_vinsert128_imm VR512:$ins))>;
157 def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (v2f64 VR128X:$src2),
158 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
159 (INSERT_get_vinsert128_imm VR512:$ins))>;
160 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v2i64 VR128X:$src2),
161 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
162 (INSERT_get_vinsert128_imm VR512:$ins))>;
163 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v4i32 VR128X:$src2),
164 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
165 (INSERT_get_vinsert128_imm VR512:$ins))>;
167 def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (loadv4f32 addr:$src2),
168 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
169 (INSERT_get_vinsert128_imm VR512:$ins))>;
170 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1),
171 (bc_v4i32 (loadv2i64 addr:$src2)),
172 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
173 (INSERT_get_vinsert128_imm VR512:$ins))>;
174 def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (loadv2f64 addr:$src2),
175 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
176 (INSERT_get_vinsert128_imm VR512:$ins))>;
177 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (loadv2i64 addr:$src2),
178 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
179 (INSERT_get_vinsert128_imm VR512:$ins))>;
181 def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (v8f32 VR256X:$src2),
182 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
183 (INSERT_get_vinsert256_imm VR512:$ins))>;
184 def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (v4f64 VR256X:$src2),
185 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
186 (INSERT_get_vinsert256_imm VR512:$ins))>;
187 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v4i64 VR256X:$src2),
188 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
189 (INSERT_get_vinsert256_imm VR512:$ins))>;
190 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v8i32 VR256X:$src2),
191 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
192 (INSERT_get_vinsert256_imm VR512:$ins))>;
194 def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (loadv8f32 addr:$src2),
195 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
196 (INSERT_get_vinsert256_imm VR512:$ins))>;
197 def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (loadv4f64 addr:$src2),
198 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
199 (INSERT_get_vinsert256_imm VR512:$ins))>;
200 def : Pat<(vinsert256_insert:$ins (v8i64 VR512:$src1), (loadv4i64 addr:$src2),
201 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
202 (INSERT_get_vinsert256_imm VR512:$ins))>;
203 def : Pat<(vinsert256_insert:$ins (v16i32 VR512:$src1),
204 (bc_v8i32 (loadv4i64 addr:$src2)),
205 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
206 (INSERT_get_vinsert256_imm VR512:$ins))>;
208 // vinsertps - insert f32 to XMM
209 def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
210 (ins VR128X:$src1, VR128X:$src2, u32u8imm:$src3),
211 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
212 [(set VR128X:$dst, (X86insertps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
214 def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
215 (ins VR128X:$src1, f32mem:$src2, u32u8imm:$src3),
216 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
217 [(set VR128X:$dst, (X86insertps VR128X:$src1,
218 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
219 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
221 //===----------------------------------------------------------------------===//
222 // AVX-512 VECTOR EXTRACT
224 let hasSideEffects = 0, ExeDomain = SSEPackedSingle in {
226 def VEXTRACTF32x4rr : AVX512AIi8<0x19, MRMDestReg, (outs VR128X:$dst),
227 (ins VR512:$src1, i8imm:$src2),
228 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
229 []>, EVEX, EVEX_V512;
230 def VEXTRACTF32x4mr : AVX512AIi8<0x19, MRMDestMem, (outs),
231 (ins f128mem:$dst, VR512:$src1, i8imm:$src2),
232 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
233 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
236 def VEXTRACTF64x4rr : AVX512AIi8<0x1b, MRMDestReg, (outs VR256X:$dst),
237 (ins VR512:$src1, i8imm:$src2),
238 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
239 []>, EVEX, EVEX_V512, VEX_W;
241 def VEXTRACTF64x4mr : AVX512AIi8<0x1b, MRMDestMem, (outs),
242 (ins f256mem:$dst, VR512:$src1, i8imm:$src2),
243 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
244 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
247 let hasSideEffects = 0 in {
249 def VEXTRACTI32x4rr : AVX512AIi8<0x39, MRMDestReg, (outs VR128X:$dst),
250 (ins VR512:$src1, i8imm:$src2),
251 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
252 []>, EVEX, EVEX_V512;
253 def VEXTRACTI32x4mr : AVX512AIi8<0x39, MRMDestMem, (outs),
254 (ins i128mem:$dst, VR512:$src1, i8imm:$src2),
255 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
256 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
259 def VEXTRACTI64x4rr : AVX512AIi8<0x3b, MRMDestReg, (outs VR256X:$dst),
260 (ins VR512:$src1, i8imm:$src2),
261 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
262 []>, EVEX, EVEX_V512, VEX_W;
264 def VEXTRACTI64x4mr : AVX512AIi8<0x3b, MRMDestMem, (outs),
265 (ins i256mem:$dst, VR512:$src1, i8imm:$src2),
266 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
267 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
270 def : Pat<(vextract128_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
271 (v4f32 (VEXTRACTF32x4rr VR512:$src1,
272 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
274 def : Pat<(vextract128_extract:$ext VR512:$src1, (iPTR imm)),
275 (v4i32 (VEXTRACTF32x4rr VR512:$src1,
276 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
278 def : Pat<(vextract128_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
279 (v2f64 (VEXTRACTF32x4rr VR512:$src1,
280 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
282 def : Pat<(vextract128_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
283 (v2i64 (VEXTRACTI32x4rr VR512:$src1,
284 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
287 def : Pat<(vextract256_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
288 (v8f32 (VEXTRACTF64x4rr VR512:$src1,
289 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
291 def : Pat<(vextract256_extract:$ext (v16i32 VR512:$src1), (iPTR imm)),
292 (v8i32 (VEXTRACTI64x4rr VR512:$src1,
293 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
295 def : Pat<(vextract256_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
296 (v4f64 (VEXTRACTF64x4rr VR512:$src1,
297 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
299 def : Pat<(vextract256_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
300 (v4i64 (VEXTRACTI64x4rr VR512:$src1,
301 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
303 // A 256-bit subvector extract from the first 512-bit vector position
304 // is a subregister copy that needs no instruction.
305 def : Pat<(v8i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
306 (v8i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_ymm))>;
307 def : Pat<(v8f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
308 (v8f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_ymm))>;
309 def : Pat<(v4i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
310 (v4i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_ymm))>;
311 def : Pat<(v4f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
312 (v4f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_ymm))>;
315 def : Pat<(v4i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
316 (v4i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm))>;
317 def : Pat<(v2i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
318 (v2i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm))>;
319 def : Pat<(v2f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
320 (v2f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
321 def : Pat<(v4f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
322 (v4f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
325 // A 128-bit subvector insert to the first 512-bit vector position
326 // is a subregister copy that needs no instruction.
327 def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
328 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
329 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
331 def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
332 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
333 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
335 def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
336 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
337 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
339 def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
340 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
341 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
344 def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
345 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
346 def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
347 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
348 def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
349 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
350 def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
351 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
353 // vextractps - extract 32 bits from XMM
354 def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
355 (ins VR128X:$src1, u32u8imm:$src2),
356 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
357 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
360 def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
361 (ins f32mem:$dst, VR128X:$src1, u32u8imm:$src2),
362 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
363 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
364 addr:$dst)]>, EVEX, EVEX_CD8<32, CD8VT1>;
366 //===---------------------------------------------------------------------===//
369 multiclass avx512_fp_broadcast<bits<8> opc, string OpcodeStr,
370 RegisterClass DestRC,
371 RegisterClass SrcRC, X86MemOperand x86memop> {
372 def rr : AVX5128I<opc, MRMSrcReg, (outs DestRC:$dst), (ins SrcRC:$src),
373 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
375 def rm : AVX5128I<opc, MRMSrcMem, (outs DestRC:$dst), (ins x86memop:$src),
376 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),[]>, EVEX;
378 let ExeDomain = SSEPackedSingle in {
379 defm VBROADCASTSSZ : avx512_fp_broadcast<0x18, "vbroadcastss", VR512,
381 EVEX_V512, EVEX_CD8<32, CD8VT1>;
384 let ExeDomain = SSEPackedDouble in {
385 defm VBROADCASTSDZ : avx512_fp_broadcast<0x19, "vbroadcastsd", VR512,
387 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
390 def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
391 (VBROADCASTSSZrm addr:$src)>;
392 def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
393 (VBROADCASTSDZrm addr:$src)>;
395 def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
396 (VBROADCASTSSZrm addr:$src)>;
397 def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
398 (VBROADCASTSDZrm addr:$src)>;
400 multiclass avx512_int_broadcast_reg<bits<8> opc, string OpcodeStr,
401 RegisterClass SrcRC, RegisterClass KRC> {
402 def Zrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins SrcRC:$src),
403 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
404 []>, EVEX, EVEX_V512;
405 def Zkrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst),
406 (ins KRC:$mask, SrcRC:$src),
407 !strconcat(OpcodeStr,
408 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
409 []>, EVEX, EVEX_V512, EVEX_KZ;
412 defm VPBROADCASTDr : avx512_int_broadcast_reg<0x7C, "vpbroadcastd", GR32, VK16WM>;
413 defm VPBROADCASTQr : avx512_int_broadcast_reg<0x7C, "vpbroadcastq", GR64, VK8WM>,
416 def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
417 (VPBROADCASTDrZkrr VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
419 def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
420 (VPBROADCASTQrZkrr VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
422 def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
423 (VPBROADCASTDrZrr GR32:$src)>;
424 def : Pat<(v16i32 (X86VBroadcastm VK16WM:$mask, (i32 GR32:$src))),
425 (VPBROADCASTDrZkrr VK16WM:$mask, GR32:$src)>;
426 def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
427 (VPBROADCASTQrZrr GR64:$src)>;
428 def : Pat<(v8i64 (X86VBroadcastm VK8WM:$mask, (i64 GR64:$src))),
429 (VPBROADCASTQrZkrr VK8WM:$mask, GR64:$src)>;
431 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_i32_512 (i32 GR32:$src))),
432 (VPBROADCASTDrZrr GR32:$src)>;
433 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_i64_512 (i64 GR64:$src))),
434 (VPBROADCASTQrZrr GR64:$src)>;
436 def : Pat<(v16i32 (int_x86_avx512_mask_pbroadcast_d_gpr_512 (i32 GR32:$src),
437 (v16i32 immAllZerosV), (i16 GR16:$mask))),
438 (VPBROADCASTDrZkrr (COPY_TO_REGCLASS GR16:$mask, VK16WM), GR32:$src)>;
439 def : Pat<(v8i64 (int_x86_avx512_mask_pbroadcast_q_gpr_512 (i64 GR64:$src),
440 (bc_v8i64 (v16i32 immAllZerosV)), (i8 GR8:$mask))),
441 (VPBROADCASTQrZkrr (COPY_TO_REGCLASS GR8:$mask, VK8WM), GR64:$src)>;
443 multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr,
444 X86MemOperand x86memop, PatFrag ld_frag,
445 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
447 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
448 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
450 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
451 def krr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
453 !strconcat(OpcodeStr,
454 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
456 (OpVT (X86VBroadcastm KRC:$mask, (SrcVT VR128X:$src))))]>,
459 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
460 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
462 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
463 def krm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
465 !strconcat(OpcodeStr,
466 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
467 [(set DstRC:$dst, (OpVT (X86VBroadcastm KRC:$mask,
468 (ld_frag addr:$src))))]>, EVEX, EVEX_KZ;
472 defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem,
473 loadi32, VR512, v16i32, v4i32, VK16WM>,
474 EVEX_V512, EVEX_CD8<32, CD8VT1>;
475 defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem,
476 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W,
477 EVEX_CD8<64, CD8VT1>;
479 multiclass avx512_int_subvec_broadcast_rm<bits<8> opc, string OpcodeStr,
480 X86MemOperand x86memop, PatFrag ld_frag,
483 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins x86memop:$src),
484 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
486 def krm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins KRC:$mask,
488 !strconcat(OpcodeStr,
489 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
494 defm VBROADCASTI32X4 : avx512_int_subvec_broadcast_rm<0x5a, "vbroadcasti32x4",
495 i128mem, loadv2i64, VK16WM>,
496 EVEX_V512, EVEX_CD8<32, CD8VT4>;
497 defm VBROADCASTI64X4 : avx512_int_subvec_broadcast_rm<0x5b, "vbroadcasti64x4",
498 i256mem, loadv4i64, VK16WM>, VEX_W,
499 EVEX_V512, EVEX_CD8<64, CD8VT4>;
501 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_512 (v4i32 VR128X:$src))),
502 (VPBROADCASTDZrr VR128X:$src)>;
503 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_512 (v2i64 VR128X:$src))),
504 (VPBROADCASTQZrr VR128X:$src)>;
506 def : Pat<(v16f32 (X86VBroadcast (v4f32 VR128X:$src))),
507 (VBROADCASTSSZrr VR128X:$src)>;
508 def : Pat<(v8f64 (X86VBroadcast (v2f64 VR128X:$src))),
509 (VBROADCASTSDZrr VR128X:$src)>;
511 def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))),
512 (VBROADCASTSSZrr VR128X:$src)>;
513 def : Pat<(v8f64 (int_x86_avx512_vbroadcast_sd_pd_512 (v2f64 VR128X:$src))),
514 (VBROADCASTSDZrr VR128X:$src)>;
516 // Provide fallback in case the load node that is used in the patterns above
517 // is used by additional users, which prevents the pattern selection.
518 def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
519 (VBROADCASTSSZrr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
520 def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
521 (VBROADCASTSDZrr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
524 let Predicates = [HasAVX512] in {
525 def : Pat<(v8i32 (X86VBroadcastm (v8i1 VK8WM:$mask), (loadi32 addr:$src))),
527 (v16i32 (VPBROADCASTDZkrm (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
528 addr:$src)), sub_ymm)>;
530 //===----------------------------------------------------------------------===//
531 // AVX-512 BROADCAST MASK TO VECTOR REGISTER
534 multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
535 RegisterClass DstRC, RegisterClass KRC,
536 ValueType OpVT, ValueType SrcVT> {
537 def rr : AVX512XS8I<opc, MRMDestReg, (outs DstRC:$dst), (ins KRC:$src),
538 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
542 let Predicates = [HasCDI] in {
543 defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d", VR512,
544 VK16, v16i32, v16i1>, EVEX_V512;
545 defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q", VR512,
546 VK8, v8i64, v8i1>, EVEX_V512, VEX_W;
549 //===----------------------------------------------------------------------===//
552 // -- immediate form --
553 multiclass avx512_perm_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
554 SDNode OpNode, PatFrag mem_frag,
555 X86MemOperand x86memop, ValueType OpVT> {
556 def ri : AVX512AIi8<opc, MRMSrcReg, (outs RC:$dst),
557 (ins RC:$src1, i8imm:$src2),
558 !strconcat(OpcodeStr,
559 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
561 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
563 def mi : AVX512AIi8<opc, MRMSrcMem, (outs RC:$dst),
564 (ins x86memop:$src1, i8imm:$src2),
565 !strconcat(OpcodeStr,
566 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
568 (OpVT (OpNode (mem_frag addr:$src1),
569 (i8 imm:$src2))))]>, EVEX;
572 defm VPERMQZ : avx512_perm_imm<0x00, "vpermq", VR512, X86VPermi, memopv8i64,
573 i512mem, v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
574 let ExeDomain = SSEPackedDouble in
575 defm VPERMPDZ : avx512_perm_imm<0x01, "vpermpd", VR512, X86VPermi, memopv8f64,
576 f512mem, v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
578 // -- VPERM - register form --
579 multiclass avx512_perm<bits<8> opc, string OpcodeStr, RegisterClass RC,
580 PatFrag mem_frag, X86MemOperand x86memop, ValueType OpVT> {
582 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
583 (ins RC:$src1, RC:$src2),
584 !strconcat(OpcodeStr,
585 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
587 (OpVT (X86VPermv RC:$src1, RC:$src2)))]>, EVEX_4V;
589 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
590 (ins RC:$src1, x86memop:$src2),
591 !strconcat(OpcodeStr,
592 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
594 (OpVT (X86VPermv RC:$src1, (mem_frag addr:$src2))))]>,
598 defm VPERMDZ : avx512_perm<0x36, "vpermd", VR512, memopv16i32, i512mem,
599 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
600 defm VPERMQZ : avx512_perm<0x36, "vpermq", VR512, memopv8i64, i512mem,
601 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
602 let ExeDomain = SSEPackedSingle in
603 defm VPERMPSZ : avx512_perm<0x16, "vpermps", VR512, memopv16f32, f512mem,
604 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
605 let ExeDomain = SSEPackedDouble in
606 defm VPERMPDZ : avx512_perm<0x16, "vpermpd", VR512, memopv8f64, f512mem,
607 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
609 // -- VPERM2I - 3 source operands form --
610 multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr, RegisterClass RC,
611 PatFrag mem_frag, X86MemOperand x86memop,
612 SDNode OpNode, ValueType OpVT> {
613 let Constraints = "$src1 = $dst" in {
614 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
615 (ins RC:$src1, RC:$src2, RC:$src3),
616 !strconcat(OpcodeStr,
617 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
619 (OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)))]>,
622 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
623 (ins RC:$src1, RC:$src2, x86memop:$src3),
624 !strconcat(OpcodeStr,
625 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
627 (OpVT (OpNode RC:$src1, RC:$src2,
628 (mem_frag addr:$src3))))]>, EVEX_4V;
631 defm VPERMI2D : avx512_perm_3src<0x76, "vpermi2d", VR512, memopv16i32, i512mem,
632 X86VPermiv3, v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
633 defm VPERMI2Q : avx512_perm_3src<0x76, "vpermi2q", VR512, memopv8i64, i512mem,
634 X86VPermiv3, v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
635 defm VPERMI2PS : avx512_perm_3src<0x77, "vpermi2ps", VR512, memopv16f32, i512mem,
636 X86VPermiv3, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
637 defm VPERMI2PD : avx512_perm_3src<0x77, "vpermi2pd", VR512, memopv8f64, i512mem,
638 X86VPermiv3, v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
640 defm VPERMT2D : avx512_perm_3src<0x7E, "vpermt2d", VR512, memopv16i32, i512mem,
641 X86VPermv3, v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
642 defm VPERMT2Q : avx512_perm_3src<0x7E, "vpermt2q", VR512, memopv8i64, i512mem,
643 X86VPermv3, v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
644 defm VPERMT2PS : avx512_perm_3src<0x7F, "vpermt2ps", VR512, memopv16f32, i512mem,
645 X86VPermv3, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
646 defm VPERMT2PD : avx512_perm_3src<0x7F, "vpermt2pd", VR512, memopv8f64, i512mem,
647 X86VPermv3, v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
649 def : Pat<(v16f32 (int_x86_avx512_mask_vpermt_ps_512 (v16i32 VR512:$idx),
650 (v16f32 VR512:$src1), (v16f32 VR512:$src2), (i16 -1))),
651 (VPERMT2PSrr VR512:$src1, VR512:$idx, VR512:$src2)>;
653 def : Pat<(v16i32 (int_x86_avx512_mask_vpermt_d_512 (v16i32 VR512:$idx),
654 (v16i32 VR512:$src1), (v16i32 VR512:$src2), (i16 -1))),
655 (VPERMT2Drr VR512:$src1, VR512:$idx, VR512:$src2)>;
657 def : Pat<(v8f64 (int_x86_avx512_mask_vpermt_pd_512 (v8i64 VR512:$idx),
658 (v8f64 VR512:$src1), (v8f64 VR512:$src2), (i8 -1))),
659 (VPERMT2PDrr VR512:$src1, VR512:$idx, VR512:$src2)>;
661 def : Pat<(v8i64 (int_x86_avx512_mask_vpermt_q_512 (v8i64 VR512:$idx),
662 (v8i64 VR512:$src1), (v8i64 VR512:$src2), (i8 -1))),
663 (VPERMT2Qrr VR512:$src1, VR512:$idx, VR512:$src2)>;
664 //===----------------------------------------------------------------------===//
665 // AVX-512 - BLEND using mask
667 multiclass avx512_blendmask<bits<8> opc, string OpcodeStr,
668 RegisterClass KRC, RegisterClass RC,
669 X86MemOperand x86memop, PatFrag mem_frag,
670 SDNode OpNode, ValueType vt> {
671 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
672 (ins KRC:$mask, RC:$src1, RC:$src2),
673 !strconcat(OpcodeStr,
674 " \t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
675 [(set RC:$dst, (OpNode KRC:$mask, (vt RC:$src2),
676 (vt RC:$src1)))]>, EVEX_4V, EVEX_K;
678 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
679 (ins KRC:$mask, RC:$src1, x86memop:$src2),
680 !strconcat(OpcodeStr,
681 " \t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
682 []>, EVEX_4V, EVEX_K;
685 let ExeDomain = SSEPackedSingle in
686 defm VBLENDMPSZ : avx512_blendmask<0x65, "vblendmps",
687 VK16WM, VR512, f512mem,
688 memopv16f32, vselect, v16f32>,
689 EVEX_CD8<32, CD8VF>, EVEX_V512;
690 let ExeDomain = SSEPackedDouble in
691 defm VBLENDMPDZ : avx512_blendmask<0x65, "vblendmpd",
692 VK8WM, VR512, f512mem,
693 memopv8f64, vselect, v8f64>,
694 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
696 def : Pat<(v16f32 (int_x86_avx512_mask_blend_ps_512 (v16f32 VR512:$src1),
697 (v16f32 VR512:$src2), (i16 GR16:$mask))),
698 (VBLENDMPSZrr (COPY_TO_REGCLASS GR16:$mask, VK16WM),
699 VR512:$src1, VR512:$src2)>;
701 def : Pat<(v8f64 (int_x86_avx512_mask_blend_pd_512 (v8f64 VR512:$src1),
702 (v8f64 VR512:$src2), (i8 GR8:$mask))),
703 (VBLENDMPDZrr (COPY_TO_REGCLASS GR8:$mask, VK8WM),
704 VR512:$src1, VR512:$src2)>;
706 defm VPBLENDMDZ : avx512_blendmask<0x64, "vpblendmd",
707 VK16WM, VR512, f512mem,
708 memopv16i32, vselect, v16i32>,
709 EVEX_CD8<32, CD8VF>, EVEX_V512;
711 defm VPBLENDMQZ : avx512_blendmask<0x64, "vpblendmq",
712 VK8WM, VR512, f512mem,
713 memopv8i64, vselect, v8i64>,
714 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
716 def : Pat<(v16i32 (int_x86_avx512_mask_blend_d_512 (v16i32 VR512:$src1),
717 (v16i32 VR512:$src2), (i16 GR16:$mask))),
718 (VPBLENDMDZrr (COPY_TO_REGCLASS GR16:$mask, VK16),
719 VR512:$src1, VR512:$src2)>;
721 def : Pat<(v8i64 (int_x86_avx512_mask_blend_q_512 (v8i64 VR512:$src1),
722 (v8i64 VR512:$src2), (i8 GR8:$mask))),
723 (VPBLENDMQZrr (COPY_TO_REGCLASS GR8:$mask, VK8),
724 VR512:$src1, VR512:$src2)>;
726 let Predicates = [HasAVX512] in {
727 def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
728 (v8f32 VR256X:$src2))),
730 (v16f32 (VBLENDMPSZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
731 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
732 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
734 def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
735 (v8i32 VR256X:$src2))),
737 (v16i32 (VPBLENDMDZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
738 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
739 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
741 //===----------------------------------------------------------------------===//
742 // Compare Instructions
743 //===----------------------------------------------------------------------===//
745 // avx512_cmp_scalar - AVX512 CMPSS and CMPSD
746 multiclass avx512_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
747 Operand CC, SDNode OpNode, ValueType VT,
748 PatFrag ld_frag, string asm, string asm_alt> {
749 def rr : AVX512Ii8<0xC2, MRMSrcReg,
750 (outs VK1:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
751 [(set VK1:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
752 IIC_SSE_ALU_F32S_RR>, EVEX_4V;
753 def rm : AVX512Ii8<0xC2, MRMSrcMem,
754 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
755 [(set VK1:$dst, (OpNode (VT RC:$src1),
756 (ld_frag addr:$src2), imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
757 let isAsmParserOnly = 1, hasSideEffects = 0 in {
758 def rri_alt : AVX512Ii8<0xC2, MRMSrcReg,
759 (outs VK1:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
760 asm_alt, [], IIC_SSE_ALU_F32S_RR>, EVEX_4V;
761 def rmi_alt : AVX512Ii8<0xC2, MRMSrcMem,
762 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
763 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
767 let Predicates = [HasAVX512] in {
768 defm VCMPSSZ : avx512_cmp_scalar<FR32X, f32mem, AVXCC, X86cmpms, f32, loadf32,
769 "vcmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
770 "vcmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
772 defm VCMPSDZ : avx512_cmp_scalar<FR64X, f64mem, AVXCC, X86cmpms, f64, loadf64,
773 "vcmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
774 "vcmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
778 multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, RegisterClass KRC,
779 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
780 SDNode OpNode, ValueType vt> {
781 def rr : AVX512BI<opc, MRMSrcReg,
782 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
783 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
784 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
785 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
786 def rm : AVX512BI<opc, MRMSrcMem,
787 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
788 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
789 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2)))],
790 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
793 defm VPCMPEQDZ : avx512_icmp_packed<0x76, "vpcmpeqd", VK16, VR512, i512mem,
794 memopv16i32, X86pcmpeqm, v16i32>, EVEX_V512,
796 defm VPCMPEQQZ : avx512_icmp_packed<0x29, "vpcmpeqq", VK8, VR512, i512mem,
797 memopv8i64, X86pcmpeqm, v8i64>, T8PD, EVEX_V512,
798 VEX_W, EVEX_CD8<64, CD8VF>;
800 defm VPCMPGTDZ : avx512_icmp_packed<0x66, "vpcmpgtd", VK16, VR512, i512mem,
801 memopv16i32, X86pcmpgtm, v16i32>, EVEX_V512,
803 defm VPCMPGTQZ : avx512_icmp_packed<0x37, "vpcmpgtq", VK8, VR512, i512mem,
804 memopv8i64, X86pcmpgtm, v8i64>, T8PD, EVEX_V512,
805 VEX_W, EVEX_CD8<64, CD8VF>;
807 def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
808 (COPY_TO_REGCLASS (VPCMPGTDZrr
809 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
810 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
812 def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
813 (COPY_TO_REGCLASS (VPCMPEQDZrr
814 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
815 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
817 multiclass avx512_icmp_cc<bits<8> opc, RegisterClass KRC,
818 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
819 SDNode OpNode, ValueType vt, Operand CC, string Suffix> {
820 def rri : AVX512AIi8<opc, MRMSrcReg,
821 (outs KRC:$dst), (ins RC:$src1, RC:$src2, CC:$cc),
822 !strconcat("vpcmp${cc}", Suffix,
823 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
824 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2), imm:$cc))],
825 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
826 def rmi : AVX512AIi8<opc, MRMSrcMem,
827 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc),
828 !strconcat("vpcmp${cc}", Suffix,
829 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
830 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2),
831 imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
832 // Accept explicit immediate argument form instead of comparison code.
833 let isAsmParserOnly = 1, hasSideEffects = 0 in {
834 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
835 (outs KRC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
836 !strconcat("vpcmp", Suffix,
837 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
838 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
839 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
840 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
841 !strconcat("vpcmp", Suffix,
842 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
843 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
847 defm VPCMPDZ : avx512_icmp_cc<0x1F, VK16, VR512, i512mem, memopv16i32,
848 X86cmpm, v16i32, AVXCC, "d">,
849 EVEX_V512, EVEX_CD8<32, CD8VF>;
850 defm VPCMPUDZ : avx512_icmp_cc<0x1E, VK16, VR512, i512mem, memopv16i32,
851 X86cmpmu, v16i32, AVXCC, "ud">,
852 EVEX_V512, EVEX_CD8<32, CD8VF>;
854 defm VPCMPQZ : avx512_icmp_cc<0x1F, VK8, VR512, i512mem, memopv8i64,
855 X86cmpm, v8i64, AVXCC, "q">,
856 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
857 defm VPCMPUQZ : avx512_icmp_cc<0x1E, VK8, VR512, i512mem, memopv8i64,
858 X86cmpmu, v8i64, AVXCC, "uq">,
859 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
861 // avx512_cmp_packed - compare packed instructions
862 multiclass avx512_cmp_packed<RegisterClass KRC, RegisterClass RC,
863 X86MemOperand x86memop, ValueType vt,
864 string suffix, Domain d> {
865 def rri : AVX512PIi8<0xC2, MRMSrcReg,
866 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
867 !strconcat("vcmp${cc}", suffix,
868 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
869 [(set KRC:$dst, (X86cmpm (vt RC:$src1), (vt RC:$src2), imm:$cc))], d>;
870 def rrib: AVX512PIi8<0xC2, MRMSrcReg,
871 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
872 !strconcat("vcmp${cc}", suffix,
873 " \t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
875 def rmi : AVX512PIi8<0xC2, MRMSrcMem,
876 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, AVXCC:$cc),
877 !strconcat("vcmp${cc}", suffix,
878 " \t{$src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
880 (X86cmpm (vt RC:$src1), (memop addr:$src2), imm:$cc))], d>;
882 // Accept explicit immediate argument form instead of comparison code.
883 let isAsmParserOnly = 1, hasSideEffects = 0 in {
884 def rri_alt : AVX512PIi8<0xC2, MRMSrcReg,
885 (outs KRC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
886 !strconcat("vcmp", suffix,
887 " \t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
888 def rmi_alt : AVX512PIi8<0xC2, MRMSrcMem,
889 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
890 !strconcat("vcmp", suffix,
891 " \t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
895 defm VCMPPSZ : avx512_cmp_packed<VK16, VR512, f512mem, v16f32,
896 "ps", SSEPackedSingle>, PS, EVEX_4V, EVEX_V512,
898 defm VCMPPDZ : avx512_cmp_packed<VK8, VR512, f512mem, v8f64,
899 "pd", SSEPackedDouble>, PD, EVEX_4V, VEX_W, EVEX_V512,
902 def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
903 (COPY_TO_REGCLASS (VCMPPSZrri
904 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
905 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
907 def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
908 (COPY_TO_REGCLASS (VPCMPDZrri
909 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
910 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
912 def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
913 (COPY_TO_REGCLASS (VPCMPUDZrri
914 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
915 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
918 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
919 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
921 (COPY_TO_REGCLASS (VCMPPSZrrib VR512:$src1, VR512:$src2,
922 (I8Imm imm:$cc)), GR16)>;
924 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
925 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
927 (COPY_TO_REGCLASS (VCMPPDZrrib VR512:$src1, VR512:$src2,
928 (I8Imm imm:$cc)), GR8)>;
930 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
931 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
933 (COPY_TO_REGCLASS (VCMPPSZrri VR512:$src1, VR512:$src2,
934 (I8Imm imm:$cc)), GR16)>;
936 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
937 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
939 (COPY_TO_REGCLASS (VCMPPDZrri VR512:$src1, VR512:$src2,
940 (I8Imm imm:$cc)), GR8)>;
942 // Mask register copy, including
943 // - copy between mask registers
944 // - load/store mask registers
945 // - copy from GPR to mask register and vice versa
947 multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
948 string OpcodeStr, RegisterClass KRC,
949 ValueType vt, X86MemOperand x86memop> {
950 let hasSideEffects = 0 in {
951 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
952 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
954 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
955 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
956 [(set KRC:$dst, (vt (load addr:$src)))]>;
958 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
959 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
963 multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
965 RegisterClass KRC, RegisterClass GRC> {
966 let hasSideEffects = 0 in {
967 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
968 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
969 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
970 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
974 let Predicates = [HasAVX512] in {
975 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16mem>,
977 defm KMOVW : avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
981 let Predicates = [HasAVX512] in {
982 // GR16 from/to 16-bit mask
983 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
984 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
985 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
986 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
988 // Store kreg in memory
989 def : Pat<(store (v16i1 VK16:$src), addr:$dst),
990 (KMOVWmk addr:$dst, VK16:$src)>;
992 def : Pat<(store VK8:$src, addr:$dst),
993 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>;
995 def : Pat<(i1 (load addr:$src)),
996 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK1)>;
998 def : Pat<(v8i1 (load addr:$src)),
999 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK8)>;
1001 def : Pat<(i1 (trunc (i32 GR32:$src))),
1002 (COPY_TO_REGCLASS (KMOVWkr (AND32ri $src, (i32 1))), VK1)>;
1004 def : Pat<(i1 (trunc (i8 GR8:$src))),
1006 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit), (i32 1))),
1008 def : Pat<(i1 (trunc (i16 GR16:$src))),
1010 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), $src, sub_16bit), (i32 1))),
1013 def : Pat<(i32 (zext VK1:$src)),
1014 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1))>;
1015 def : Pat<(i8 (zext VK1:$src)),
1018 (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)), sub_8bit)>;
1019 def : Pat<(i64 (zext VK1:$src)),
1020 (AND64ri8 (SUBREG_TO_REG (i64 0),
1021 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_32bit), (i64 1))>;
1022 def : Pat<(i16 (zext VK1:$src)),
1024 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)),
1026 def : Pat<(v16i1 (scalar_to_vector VK1:$src)),
1027 (COPY_TO_REGCLASS VK1:$src, VK16)>;
1028 def : Pat<(v8i1 (scalar_to_vector VK1:$src)),
1029 (COPY_TO_REGCLASS VK1:$src, VK8)>;
1031 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1032 let Predicates = [HasAVX512] in {
1033 // GR from/to 8-bit mask without native support
1034 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1036 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
1038 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1040 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
1043 def : Pat<(i1 (X86Vextract VK16:$src, (iPTR 0))),
1044 (COPY_TO_REGCLASS VK16:$src, VK1)>;
1045 def : Pat<(i1 (X86Vextract VK8:$src, (iPTR 0))),
1046 (COPY_TO_REGCLASS VK8:$src, VK1)>;
1050 // Mask unary operation
1052 multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
1053 RegisterClass KRC, SDPatternOperator OpNode> {
1054 let Predicates = [HasAVX512] in
1055 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1056 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
1057 [(set KRC:$dst, (OpNode KRC:$src))]>;
1060 multiclass avx512_mask_unop_w<bits<8> opc, string OpcodeStr,
1061 SDPatternOperator OpNode> {
1062 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1066 defm KNOT : avx512_mask_unop_w<0x44, "knot", not>;
1068 multiclass avx512_mask_unop_int<string IntName, string InstName> {
1069 let Predicates = [HasAVX512] in
1070 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1072 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1073 (v16i1 (COPY_TO_REGCLASS GR16:$src, VK16))), GR16)>;
1075 defm : avx512_mask_unop_int<"knot", "KNOT">;
1077 def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
1078 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
1079 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
1081 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
1082 def : Pat<(not VK8:$src),
1084 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
1086 // Mask binary operation
1087 // - KAND, KANDN, KOR, KXNOR, KXOR
1088 multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
1089 RegisterClass KRC, SDPatternOperator OpNode> {
1090 let Predicates = [HasAVX512] in
1091 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1092 !strconcat(OpcodeStr,
1093 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1094 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
1097 multiclass avx512_mask_binop_w<bits<8> opc, string OpcodeStr,
1098 SDPatternOperator OpNode> {
1099 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1103 def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
1104 def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
1106 let isCommutable = 1 in {
1107 defm KAND : avx512_mask_binop_w<0x41, "kand", and>;
1108 let isCommutable = 0 in
1109 defm KANDN : avx512_mask_binop_w<0x42, "kandn", andn>;
1110 defm KOR : avx512_mask_binop_w<0x45, "kor", or>;
1111 defm KXNOR : avx512_mask_binop_w<0x46, "kxnor", xnor>;
1112 defm KXOR : avx512_mask_binop_w<0x47, "kxor", xor>;
1115 def : Pat<(xor VK1:$src1, VK1:$src2),
1116 (COPY_TO_REGCLASS (KXORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1117 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1119 def : Pat<(or VK1:$src1, VK1:$src2),
1120 (COPY_TO_REGCLASS (KORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1121 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1123 def : Pat<(and VK1:$src1, VK1:$src2),
1124 (COPY_TO_REGCLASS (KANDWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1125 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1127 multiclass avx512_mask_binop_int<string IntName, string InstName> {
1128 let Predicates = [HasAVX512] in
1129 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1130 (i16 GR16:$src1), (i16 GR16:$src2)),
1131 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1132 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1133 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1136 defm : avx512_mask_binop_int<"kand", "KAND">;
1137 defm : avx512_mask_binop_int<"kandn", "KANDN">;
1138 defm : avx512_mask_binop_int<"kor", "KOR">;
1139 defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
1140 defm : avx512_mask_binop_int<"kxor", "KXOR">;
1142 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
1143 multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
1144 let Predicates = [HasAVX512] in
1145 def : Pat<(OpNode VK8:$src1, VK8:$src2),
1147 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
1148 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
1151 defm : avx512_binop_pat<and, KANDWrr>;
1152 defm : avx512_binop_pat<andn, KANDNWrr>;
1153 defm : avx512_binop_pat<or, KORWrr>;
1154 defm : avx512_binop_pat<xnor, KXNORWrr>;
1155 defm : avx512_binop_pat<xor, KXORWrr>;
1158 multiclass avx512_mask_unpck<bits<8> opc, string OpcodeStr,
1159 RegisterClass KRC> {
1160 let Predicates = [HasAVX512] in
1161 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1162 !strconcat(OpcodeStr,
1163 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1166 multiclass avx512_mask_unpck_bw<bits<8> opc, string OpcodeStr> {
1167 defm BW : avx512_mask_unpck<opc, !strconcat(OpcodeStr, "bw"), VK16>,
1171 defm KUNPCK : avx512_mask_unpck_bw<0x4b, "kunpck">;
1172 def : Pat<(v16i1 (concat_vectors (v8i1 VK8:$src1), (v8i1 VK8:$src2))),
1173 (KUNPCKBWrr (COPY_TO_REGCLASS VK8:$src2, VK16),
1174 (COPY_TO_REGCLASS VK8:$src1, VK16))>;
1177 multiclass avx512_mask_unpck_int<string IntName, string InstName> {
1178 let Predicates = [HasAVX512] in
1179 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_bw")
1180 (i16 GR16:$src1), (i16 GR16:$src2)),
1181 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"BWrr")
1182 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1183 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1185 defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
1188 multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1190 let Predicates = [HasAVX512], Defs = [EFLAGS] in
1191 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
1192 !strconcat(OpcodeStr, " \t{$src2, $src1|$src1, $src2}"),
1193 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
1196 multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1197 defm W : avx512_mask_testop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1201 defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
1203 def : Pat<(X86cmp VK1:$src1, (i1 0)),
1204 (KORTESTWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1205 (COPY_TO_REGCLASS VK1:$src1, VK16))>;
1208 multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1210 let Predicates = [HasAVX512] in
1211 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, i8imm:$imm),
1212 !strconcat(OpcodeStr,
1213 " \t{$imm, $src, $dst|$dst, $src, $imm}"),
1214 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
1217 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
1219 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1223 defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86vshli>;
1224 defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86vsrli>;
1226 // Mask setting all 0s or 1s
1227 multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
1228 let Predicates = [HasAVX512] in
1229 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
1230 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
1231 [(set KRC:$dst, (VT Val))]>;
1234 multiclass avx512_mask_setop_w<PatFrag Val> {
1235 defm B : avx512_mask_setop<VK8, v8i1, Val>;
1236 defm W : avx512_mask_setop<VK16, v16i1, Val>;
1239 defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
1240 defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
1242 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1243 let Predicates = [HasAVX512] in {
1244 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
1245 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
1246 def : Pat<(i1 0), (COPY_TO_REGCLASS (KSET0W), VK1)>;
1247 def : Pat<(i1 1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
1248 def : Pat<(i1 -1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
1250 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
1251 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
1253 def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
1254 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
1256 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
1257 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
1259 def : Pat<(v8i1 (X86vshli VK8:$src, (i8 imm:$imm))),
1260 (v8i1 (COPY_TO_REGCLASS (KSHIFTLWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>;
1262 def : Pat<(v8i1 (X86vsrli VK8:$src, (i8 imm:$imm))),
1263 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>;
1264 //===----------------------------------------------------------------------===//
1265 // AVX-512 - Aligned and unaligned load and store
1268 multiclass avx512_load<bits<8> opc, RegisterClass RC, RegisterClass KRC,
1269 X86MemOperand x86memop, PatFrag ld_frag,
1270 string asm, Domain d,
1271 ValueType vt, bit IsReMaterializable = 1> {
1272 let hasSideEffects = 0 in {
1273 def rr : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1274 !strconcat(asm, " \t{$src, $dst|$dst, $src}"), [], d>,
1276 def rrkz : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
1278 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
1279 [], d>, EVEX, EVEX_KZ;
1281 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
1282 def rm : AVX512PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1283 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
1284 [(set (vt RC:$dst), (ld_frag addr:$src))], d>, EVEX;
1285 let Constraints = "$src1 = $dst", hasSideEffects = 0 in {
1286 def rrk : AVX512PI<opc, MRMSrcReg, (outs RC:$dst),
1287 (ins RC:$src1, KRC:$mask, RC:$src2),
1289 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>,
1292 def rmk : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1293 (ins RC:$src1, KRC:$mask, x86memop:$src2),
1295 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
1296 [], d>, EVEX, EVEX_K;
1299 def rmkz : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1300 (ins KRC:$mask, x86memop:$src2),
1302 " \t{$src2, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src2}"),
1303 [], d>, EVEX, EVEX_KZ;
1306 multiclass avx512_store<bits<8> opc, RegisterClass RC, RegisterClass KRC,
1307 X86MemOperand x86memop, PatFrag store_frag,
1308 string asm, Domain d, ValueType vt> {
1309 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1310 def rr_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst), (ins RC:$src),
1311 !strconcat(asm, " \t{$src, $dst|$dst, $src}"), [], d>,
1313 let Constraints = "$src1 = $dst" in
1314 def alt_rrk : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
1315 (ins RC:$src1, KRC:$mask, RC:$src2),
1317 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>,
1319 def alt_rrkz : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
1320 (ins KRC:$mask, RC:$src),
1322 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
1323 [], d>, EVEX, EVEX_KZ;
1325 let mayStore = 1 in {
1326 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
1327 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
1328 [(store_frag (vt RC:$src), addr:$dst)], d>, EVEX;
1329 def mrk : AVX512PI<opc, MRMDestMem, (outs),
1330 (ins x86memop:$dst, KRC:$mask, RC:$src),
1332 " \t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
1333 [], d>, EVEX, EVEX_K;
1334 def mrkz : AVX512PI<opc, MRMDestMem, (outs),
1335 (ins x86memop:$dst, KRC:$mask, RC:$src),
1337 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
1338 [], d>, EVEX, EVEX_KZ;
1342 defm VMOVAPSZ : avx512_load<0x28, VR512, VK16WM, f512mem, alignedloadv16f32,
1343 "vmovaps", SSEPackedSingle, v16f32>,
1344 avx512_store<0x29, VR512, VK16WM, f512mem, alignedstore512,
1345 "vmovaps", SSEPackedSingle, v16f32>,
1346 PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
1347 defm VMOVAPDZ : avx512_load<0x28, VR512, VK8WM, f512mem, alignedloadv8f64,
1348 "vmovapd", SSEPackedDouble, v8f64>,
1349 avx512_store<0x29, VR512, VK8WM, f512mem, alignedstore512,
1350 "vmovapd", SSEPackedDouble, v8f64>,
1351 PD, EVEX_V512, VEX_W,
1352 EVEX_CD8<64, CD8VF>;
1353 defm VMOVUPSZ : avx512_load<0x10, VR512, VK16WM, f512mem, loadv16f32,
1354 "vmovups", SSEPackedSingle, v16f32>,
1355 avx512_store<0x11, VR512, VK16WM, f512mem, store,
1356 "vmovups", SSEPackedSingle, v16f32>,
1357 PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
1358 defm VMOVUPDZ : avx512_load<0x10, VR512, VK8WM, f512mem, loadv8f64,
1359 "vmovupd", SSEPackedDouble, v8f64, 0>,
1360 avx512_store<0x11, VR512, VK8WM, f512mem, store,
1361 "vmovupd", SSEPackedDouble, v8f64>,
1362 PD, EVEX_V512, VEX_W,
1363 EVEX_CD8<64, CD8VF>;
1364 def: Pat<(v8f64 (int_x86_avx512_mask_loadu_pd_512 addr:$ptr,
1365 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
1366 (VMOVUPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
1368 def: Pat<(v16f32 (int_x86_avx512_mask_loadu_ps_512 addr:$ptr,
1369 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
1370 (VMOVUPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
1372 def: Pat<(int_x86_avx512_mask_storeu_ps_512 addr:$ptr, (v16f32 VR512:$src),
1374 (VMOVUPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
1376 def: Pat<(int_x86_avx512_mask_storeu_pd_512 addr:$ptr, (v8f64 VR512:$src),
1378 (VMOVUPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
1381 defm VMOVDQA32: avx512_load<0x6F, VR512, VK16WM, i512mem, alignedloadv16i32,
1382 "vmovdqa32", SSEPackedInt, v16i32>,
1383 avx512_store<0x7F, VR512, VK16WM, i512mem, alignedstore512,
1384 "vmovdqa32", SSEPackedInt, v16i32>,
1385 PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
1386 defm VMOVDQA64: avx512_load<0x6F, VR512, VK8WM, i512mem, alignedloadv8i64,
1387 "vmovdqa64", SSEPackedInt, v8i64>,
1388 avx512_store<0x7F, VR512, VK8WM, i512mem, alignedstore512,
1389 "vmovdqa64", SSEPackedInt, v8i64>,
1390 PD, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
1391 defm VMOVDQU32: avx512_load<0x6F, VR512, VK16WM, i512mem, load,
1392 "vmovdqu32", SSEPackedInt, v16i32>,
1393 avx512_store<0x7F, VR512, VK16WM, i512mem, store,
1394 "vmovdqu32", SSEPackedInt, v16i32>,
1395 XS, EVEX_V512, EVEX_CD8<32, CD8VF>;
1396 defm VMOVDQU64: avx512_load<0x6F, VR512, VK8WM, i512mem, load,
1397 "vmovdqu64", SSEPackedInt, v8i64>,
1398 avx512_store<0x7F, VR512, VK8WM, i512mem, store,
1399 "vmovdqu64", SSEPackedInt, v8i64>,
1400 XS, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
1402 def: Pat<(v16i32 (int_x86_avx512_mask_loadu_d_512 addr:$ptr,
1403 (v16i32 immAllZerosV), GR16:$mask)),
1404 (VMOVDQU32rmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
1406 def: Pat<(v8i64 (int_x86_avx512_mask_loadu_q_512 addr:$ptr,
1407 (bc_v8i64 (v16i32 immAllZerosV)), GR8:$mask)),
1408 (VMOVDQU64rmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
1410 def: Pat<(int_x86_avx512_mask_storeu_d_512 addr:$ptr, (v16i32 VR512:$src),
1412 (VMOVDQU32mrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
1414 def: Pat<(int_x86_avx512_mask_storeu_q_512 addr:$ptr, (v8i64 VR512:$src),
1416 (VMOVDQU64mrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
1419 let AddedComplexity = 20 in {
1420 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src),
1421 (bc_v8i64 (v16i32 immAllZerosV)))),
1422 (VMOVDQU64rrkz VK8WM:$mask, VR512:$src)>;
1424 def : Pat<(v8i64 (vselect VK8WM:$mask, (bc_v8i64 (v16i32 immAllZerosV)),
1425 (v8i64 VR512:$src))),
1426 (VMOVDQU64rrkz (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$mask, VK16)),
1429 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src),
1430 (v16i32 immAllZerosV))),
1431 (VMOVDQU32rrkz VK16WM:$mask, VR512:$src)>;
1433 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 immAllZerosV),
1434 (v16i32 VR512:$src))),
1435 (VMOVDQU32rrkz (KNOTWrr VK16WM:$mask), VR512:$src)>;
1437 def : Pat<(v16f32 (vselect VK16WM:$mask, (v16f32 VR512:$src1),
1438 (v16f32 VR512:$src2))),
1439 (VMOVUPSZrrk VR512:$src2, VK16WM:$mask, VR512:$src1)>;
1440 def : Pat<(v8f64 (vselect VK8WM:$mask, (v8f64 VR512:$src1),
1441 (v8f64 VR512:$src2))),
1442 (VMOVUPDZrrk VR512:$src2, VK8WM:$mask, VR512:$src1)>;
1443 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src1),
1444 (v16i32 VR512:$src2))),
1445 (VMOVDQU32rrk VR512:$src2, VK16WM:$mask, VR512:$src1)>;
1446 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src1),
1447 (v8i64 VR512:$src2))),
1448 (VMOVDQU64rrk VR512:$src2, VK8WM:$mask, VR512:$src1)>;
1450 // Move Int Doubleword to Packed Double Int
1452 def VMOVDI2PDIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
1453 "vmovd\t{$src, $dst|$dst, $src}",
1455 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
1457 def VMOVDI2PDIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
1458 "vmovd\t{$src, $dst|$dst, $src}",
1460 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
1461 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1462 def VMOV64toPQIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
1463 "vmovq\t{$src, $dst|$dst, $src}",
1465 (v2i64 (scalar_to_vector GR64:$src)))],
1466 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
1467 let isCodeGenOnly = 1 in {
1468 def VMOV64toSDZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
1469 "vmovq\t{$src, $dst|$dst, $src}",
1470 [(set FR64:$dst, (bitconvert GR64:$src))],
1471 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
1472 def VMOVSDto64Zrr : AVX512BI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
1473 "vmovq\t{$src, $dst|$dst, $src}",
1474 [(set GR64:$dst, (bitconvert FR64:$src))],
1475 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
1477 def VMOVSDto64Zmr : AVX512BI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
1478 "vmovq\t{$src, $dst|$dst, $src}",
1479 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
1480 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
1481 EVEX_CD8<64, CD8VT1>;
1483 // Move Int Doubleword to Single Scalar
1485 let isCodeGenOnly = 1 in {
1486 def VMOVDI2SSZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
1487 "vmovd\t{$src, $dst|$dst, $src}",
1488 [(set FR32X:$dst, (bitconvert GR32:$src))],
1489 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
1491 def VMOVDI2SSZrm : AVX512BI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
1492 "vmovd\t{$src, $dst|$dst, $src}",
1493 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
1494 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1497 // Move doubleword from xmm register to r/m32
1499 def VMOVPDI2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
1500 "vmovd\t{$src, $dst|$dst, $src}",
1501 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
1502 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
1504 def VMOVPDI2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
1505 (ins i32mem:$dst, VR128X:$src),
1506 "vmovd\t{$src, $dst|$dst, $src}",
1507 [(store (i32 (vector_extract (v4i32 VR128X:$src),
1508 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
1509 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1511 // Move quadword from xmm1 register to r/m64
1513 def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
1514 "vmovq\t{$src, $dst|$dst, $src}",
1515 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
1517 IIC_SSE_MOVD_ToGP>, PD, EVEX, VEX_LIG, VEX_W,
1518 Requires<[HasAVX512, In64BitMode]>;
1520 def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
1521 (ins i64mem:$dst, VR128X:$src),
1522 "vmovq\t{$src, $dst|$dst, $src}",
1523 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
1524 addr:$dst)], IIC_SSE_MOVDQ>,
1525 EVEX, PD, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>,
1526 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
1528 // Move Scalar Single to Double Int
1530 let isCodeGenOnly = 1 in {
1531 def VMOVSS2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst),
1533 "vmovd\t{$src, $dst|$dst, $src}",
1534 [(set GR32:$dst, (bitconvert FR32X:$src))],
1535 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
1536 def VMOVSS2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
1537 (ins i32mem:$dst, FR32X:$src),
1538 "vmovd\t{$src, $dst|$dst, $src}",
1539 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
1540 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1543 // Move Quadword Int to Packed Quadword Int
1545 def VMOVQI2PQIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst),
1547 "vmovq\t{$src, $dst|$dst, $src}",
1549 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
1550 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
1552 //===----------------------------------------------------------------------===//
1553 // AVX-512 MOVSS, MOVSD
1554 //===----------------------------------------------------------------------===//
1556 multiclass avx512_move_scalar <string asm, RegisterClass RC,
1557 SDNode OpNode, ValueType vt,
1558 X86MemOperand x86memop, PatFrag mem_pat> {
1559 let hasSideEffects = 0 in {
1560 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
1561 !strconcat(asm, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1562 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
1563 (scalar_to_vector RC:$src2))))],
1564 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
1565 let Constraints = "$src1 = $dst" in
1566 def rrk : SI<0x10, MRMSrcReg, (outs VR128X:$dst),
1567 (ins VR128X:$src1, VK1WM:$mask, RC:$src2, RC:$src3),
1569 " \t{$src3, $src2, $dst {${mask}}|$dst {${mask}}, $src2, $src3}"),
1570 [], IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG, EVEX_K;
1571 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1572 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
1573 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
1575 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
1576 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
1577 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
1579 } //hasSideEffects = 0
1582 let ExeDomain = SSEPackedSingle in
1583 defm VMOVSSZ : avx512_move_scalar<"movss", FR32X, X86Movss, v4f32, f32mem,
1584 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
1586 let ExeDomain = SSEPackedDouble in
1587 defm VMOVSDZ : avx512_move_scalar<"movsd", FR64X, X86Movsd, v2f64, f64mem,
1588 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
1590 def : Pat<(f32 (X86select VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))),
1591 (COPY_TO_REGCLASS (VMOVSSZrrk (COPY_TO_REGCLASS FR32X:$src2, VR128X),
1592 VK1WM:$mask, (f32 (IMPLICIT_DEF)), FR32X:$src1), FR32X)>;
1594 def : Pat<(f64 (X86select VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))),
1595 (COPY_TO_REGCLASS (VMOVSDZrrk (COPY_TO_REGCLASS FR64X:$src2, VR128X),
1596 VK1WM:$mask, (f64 (IMPLICIT_DEF)), FR64X:$src1), FR64X)>;
1598 // For the disassembler
1599 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
1600 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
1601 (ins VR128X:$src1, FR32X:$src2),
1602 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1604 XS, EVEX_4V, VEX_LIG;
1605 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
1606 (ins VR128X:$src1, FR64X:$src2),
1607 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1609 XD, EVEX_4V, VEX_LIG, VEX_W;
1612 let Predicates = [HasAVX512] in {
1613 let AddedComplexity = 15 in {
1614 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
1615 // MOVS{S,D} to the lower bits.
1616 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
1617 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
1618 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
1619 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
1620 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
1621 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
1622 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
1623 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
1625 // Move low f32 and clear high bits.
1626 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
1627 (SUBREG_TO_REG (i32 0),
1628 (VMOVSSZrr (v4f32 (V_SET0)),
1629 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
1630 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
1631 (SUBREG_TO_REG (i32 0),
1632 (VMOVSSZrr (v4i32 (V_SET0)),
1633 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
1636 let AddedComplexity = 20 in {
1637 // MOVSSrm zeros the high parts of the register; represent this
1638 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
1639 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
1640 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1641 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
1642 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1643 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
1644 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1646 // MOVSDrm zeros the high parts of the register; represent this
1647 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
1648 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
1649 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1650 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
1651 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1652 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
1653 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1654 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
1655 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1656 def : Pat<(v2f64 (X86vzload addr:$src)),
1657 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1659 // Represent the same patterns above but in the form they appear for
1661 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
1662 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
1663 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
1664 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
1665 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
1666 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
1667 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
1668 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
1669 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
1671 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
1672 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
1673 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
1674 FR32X:$src)), sub_xmm)>;
1675 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
1676 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
1677 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
1678 FR64X:$src)), sub_xmm)>;
1679 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
1680 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
1681 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
1683 // Move low f64 and clear high bits.
1684 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
1685 (SUBREG_TO_REG (i32 0),
1686 (VMOVSDZrr (v2f64 (V_SET0)),
1687 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
1689 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
1690 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
1691 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
1693 // Extract and store.
1694 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
1696 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
1697 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
1699 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
1701 // Shuffle with VMOVSS
1702 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
1703 (VMOVSSZrr (v4i32 VR128X:$src1),
1704 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
1705 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
1706 (VMOVSSZrr (v4f32 VR128X:$src1),
1707 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
1710 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
1711 (SUBREG_TO_REG (i32 0),
1712 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
1713 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
1715 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
1716 (SUBREG_TO_REG (i32 0),
1717 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
1718 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
1721 // Shuffle with VMOVSD
1722 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
1723 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1724 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
1725 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1726 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
1727 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1728 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
1729 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1732 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
1733 (SUBREG_TO_REG (i32 0),
1734 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
1735 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
1737 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
1738 (SUBREG_TO_REG (i32 0),
1739 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
1740 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
1743 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
1744 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1745 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
1746 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1747 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
1748 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1749 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
1750 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1753 let AddedComplexity = 15 in
1754 def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
1756 "vmovq\t{$src, $dst|$dst, $src}",
1757 [(set VR128X:$dst, (v2i64 (X86vzmovl
1758 (v2i64 VR128X:$src))))],
1759 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
1761 let AddedComplexity = 20 in
1762 def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
1764 "vmovq\t{$src, $dst|$dst, $src}",
1765 [(set VR128X:$dst, (v2i64 (X86vzmovl
1766 (loadv2i64 addr:$src))))],
1767 IIC_SSE_MOVDQ>, EVEX, VEX_W,
1768 EVEX_CD8<8, CD8VT8>;
1770 let Predicates = [HasAVX512] in {
1771 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
1772 let AddedComplexity = 20 in {
1773 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
1774 (VMOVDI2PDIZrm addr:$src)>;
1775 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
1776 (VMOV64toPQIZrr GR64:$src)>;
1777 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
1778 (VMOVDI2PDIZrr GR32:$src)>;
1780 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
1781 (VMOVDI2PDIZrm addr:$src)>;
1782 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
1783 (VMOVDI2PDIZrm addr:$src)>;
1784 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
1785 (VMOVZPQILo2PQIZrm addr:$src)>;
1786 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
1787 (VMOVZPQILo2PQIZrr VR128X:$src)>;
1788 def : Pat<(v2i64 (X86vzload addr:$src)),
1789 (VMOVZPQILo2PQIZrm addr:$src)>;
1792 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
1793 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
1794 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
1795 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
1796 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
1797 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
1798 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
1801 def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
1802 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
1804 def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
1805 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
1807 def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
1808 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
1810 def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
1811 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
1813 //===----------------------------------------------------------------------===//
1814 // AVX-512 - Non-temporals
1815 //===----------------------------------------------------------------------===//
1817 def VMOVNTDQAZrm : AVX5128I<0x2A, MRMSrcMem, (outs VR512:$dst),
1819 "vmovntdqa\t{$src, $dst|$dst, $src}",
1821 (int_x86_avx512_movntdqa addr:$src))]>,
1822 EVEX, EVEX_V512, EVEX_CD8<64, CD8VF>;
1824 // Prefer non-temporal over temporal versions
1825 let AddedComplexity = 400, SchedRW = [WriteStore] in {
1827 def VMOVNTPSZmr : AVX512PSI<0x2B, MRMDestMem, (outs),
1828 (ins f512mem:$dst, VR512:$src),
1829 "vmovntps\t{$src, $dst|$dst, $src}",
1830 [(alignednontemporalstore (v16f32 VR512:$src),
1833 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1835 def VMOVNTPDZmr : AVX512PDI<0x2B, MRMDestMem, (outs),
1836 (ins f512mem:$dst, VR512:$src),
1837 "vmovntpd\t{$src, $dst|$dst, $src}",
1838 [(alignednontemporalstore (v8f64 VR512:$src),
1841 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1844 def VMOVNTDQZmr : AVX512BI<0xE7, MRMDestMem, (outs),
1845 (ins i512mem:$dst, VR512:$src),
1846 "vmovntdq\t{$src, $dst|$dst, $src}",
1847 [(alignednontemporalstore (v8i64 VR512:$src),
1850 EVEX, EVEX_V512, EVEX_CD8<64, CD8VF>;
1853 //===----------------------------------------------------------------------===//
1854 // AVX-512 - Integer arithmetic
1856 multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
1857 ValueType OpVT, RegisterClass KRC,
1858 RegisterClass RC, PatFrag memop_frag,
1859 X86MemOperand x86memop, PatFrag scalar_mfrag,
1860 X86MemOperand x86scalar_mop, string BrdcstStr,
1861 OpndItins itins, bit IsCommutable = 0> {
1862 let isCommutable = IsCommutable in
1863 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1864 (ins RC:$src1, RC:$src2),
1865 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1866 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
1868 let AddedComplexity = 30 in {
1869 let Constraints = "$src0 = $dst" in
1870 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1871 (ins RC:$src0, KRC:$mask, RC:$src1, RC:$src2),
1872 !strconcat(OpcodeStr,
1873 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
1874 [(set RC:$dst, (OpVT (vselect KRC:$mask,
1875 (OpNode (OpVT RC:$src1), (OpVT RC:$src2)),
1877 itins.rr>, EVEX_4V, EVEX_K;
1878 def rrkz : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1879 (ins KRC:$mask, RC:$src1, RC:$src2),
1880 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst {${mask}} {z}" ,
1881 "|$dst {${mask}} {z}, $src1, $src2}"),
1882 [(set RC:$dst, (OpVT (vselect KRC:$mask,
1883 (OpNode (OpVT RC:$src1), (OpVT RC:$src2)),
1884 (OpVT immAllZerosV))))],
1885 itins.rr>, EVEX_4V, EVEX_KZ;
1888 let mayLoad = 1 in {
1889 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1890 (ins RC:$src1, x86memop:$src2),
1891 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1892 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (memop_frag addr:$src2))))],
1894 let AddedComplexity = 30 in {
1895 let Constraints = "$src0 = $dst" in
1896 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1897 (ins RC:$src0, KRC:$mask, RC:$src1, x86memop:$src2),
1898 !strconcat(OpcodeStr,
1899 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
1900 [(set RC:$dst, (OpVT (vselect KRC:$mask,
1901 (OpNode (OpVT RC:$src1), (memop_frag addr:$src2)),
1903 itins.rm>, EVEX_4V, EVEX_K;
1904 def rmkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1905 (ins KRC:$mask, RC:$src1, x86memop:$src2),
1906 !strconcat(OpcodeStr,
1907 " \t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
1908 [(set RC:$dst, (OpVT (vselect KRC:$mask,
1909 (OpNode (OpVT RC:$src1), (memop_frag addr:$src2)),
1910 (OpVT immAllZerosV))))],
1911 itins.rm>, EVEX_4V, EVEX_KZ;
1913 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1914 (ins RC:$src1, x86scalar_mop:$src2),
1915 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
1916 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
1917 [(set RC:$dst, (OpNode RC:$src1,
1918 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2)))))],
1919 itins.rm>, EVEX_4V, EVEX_B;
1920 let AddedComplexity = 30 in {
1921 let Constraints = "$src0 = $dst" in
1922 def rmbk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1923 (ins RC:$src0, KRC:$mask, RC:$src1, x86scalar_mop:$src2),
1924 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
1925 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}",
1927 [(set RC:$dst, (OpVT (vselect KRC:$mask,
1928 (OpNode (OpVT RC:$src1),
1929 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2)))),
1931 itins.rm>, EVEX_4V, EVEX_B, EVEX_K;
1932 def rmbkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1933 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
1934 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
1935 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
1937 [(set RC:$dst, (OpVT (vselect KRC:$mask,
1938 (OpNode (OpVT RC:$src1),
1939 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2)))),
1940 (OpVT immAllZerosV))))],
1941 itins.rm>, EVEX_4V, EVEX_B, EVEX_KZ;
1946 multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr, ValueType DstVT,
1947 ValueType SrcVT, RegisterClass KRC, RegisterClass RC,
1948 PatFrag memop_frag, X86MemOperand x86memop,
1949 PatFrag scalar_mfrag, X86MemOperand x86scalar_mop,
1950 string BrdcstStr, OpndItins itins, bit IsCommutable = 0> {
1951 let isCommutable = IsCommutable in
1953 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1954 (ins RC:$src1, RC:$src2),
1955 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1957 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1958 (ins KRC:$mask, RC:$src1, RC:$src2),
1959 !strconcat(OpcodeStr,
1960 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
1961 [], itins.rr>, EVEX_4V, EVEX_K;
1962 def rrkz : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1963 (ins KRC:$mask, RC:$src1, RC:$src2),
1964 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst {${mask}} {z}" ,
1965 "|$dst {${mask}} {z}, $src1, $src2}"),
1966 [], itins.rr>, EVEX_4V, EVEX_KZ;
1968 let mayLoad = 1 in {
1969 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1970 (ins RC:$src1, x86memop:$src2),
1971 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1973 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1974 (ins KRC:$mask, RC:$src1, x86memop:$src2),
1975 !strconcat(OpcodeStr,
1976 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
1977 [], itins.rm>, EVEX_4V, EVEX_K;
1978 def rmkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1979 (ins KRC:$mask, RC:$src1, x86memop:$src2),
1980 !strconcat(OpcodeStr,
1981 " \t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
1982 [], itins.rm>, EVEX_4V, EVEX_KZ;
1983 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1984 (ins RC:$src1, x86scalar_mop:$src2),
1985 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
1986 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
1987 [], itins.rm>, EVEX_4V, EVEX_B;
1988 def rmbk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1989 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
1990 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
1991 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}",
1993 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_K;
1994 def rmbkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1995 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
1996 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
1997 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
1999 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_KZ;
2003 defm VPADDDZ : avx512_binop_rm<0xFE, "vpaddd", add, v16i32, VK16WM, VR512,
2004 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2005 SSE_INTALU_ITINS_P, 1>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2007 defm VPSUBDZ : avx512_binop_rm<0xFA, "vpsubd", sub, v16i32, VK16WM, VR512,
2008 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2009 SSE_INTALU_ITINS_P, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2011 defm VPMULLDZ : avx512_binop_rm<0x40, "vpmulld", mul, v16i32, VK16WM, VR512,
2012 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2013 SSE_INTALU_ITINS_P, 1>, T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2015 defm VPADDQZ : avx512_binop_rm<0xD4, "vpaddq", add, v8i64, VK8WM, VR512,
2016 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2017 SSE_INTALU_ITINS_P, 1>, EVEX_CD8<64, CD8VF>, EVEX_V512, VEX_W;
2019 defm VPSUBQZ : avx512_binop_rm<0xFB, "vpsubq", sub, v8i64, VK8WM, VR512,
2020 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2021 SSE_INTALU_ITINS_P, 0>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2023 defm VPMULDQZ : avx512_binop_rm2<0x28, "vpmuldq", v8i64, v16i32, VK8WM, VR512,
2024 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2025 SSE_INTALU_ITINS_P, 1>, T8PD, EVEX_V512,
2026 EVEX_CD8<64, CD8VF>, VEX_W;
2028 defm VPMULUDQZ : avx512_binop_rm2<0xF4, "vpmuludq", v8i64, v16i32, VK8WM, VR512,
2029 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2030 SSE_INTMUL_ITINS_P, 1>, EVEX_V512, EVEX_CD8<64, CD8VF>, VEX_W;
2032 def : Pat<(v8i64 (X86pmuludq (v16i32 VR512:$src1), (v16i32 VR512:$src2))),
2033 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
2035 def : Pat<(v8i64 (int_x86_avx512_mask_pmulu_dq_512 (v16i32 VR512:$src1),
2036 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2037 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
2038 def : Pat<(v8i64 (int_x86_avx512_mask_pmul_dq_512 (v16i32 VR512:$src1),
2039 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2040 (VPMULDQZrr VR512:$src1, VR512:$src2)>;
2042 defm VPMAXUDZ : avx512_binop_rm<0x3F, "vpmaxud", X86umax, v16i32, VK16WM, VR512,
2043 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2044 SSE_INTALU_ITINS_P, 1>,
2045 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2046 defm VPMAXUQZ : avx512_binop_rm<0x3F, "vpmaxuq", X86umax, v8i64, VK8WM, VR512,
2047 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2048 SSE_INTALU_ITINS_P, 0>,
2049 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2051 defm VPMAXSDZ : avx512_binop_rm<0x3D, "vpmaxsd", X86smax, v16i32, VK16WM, VR512,
2052 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2053 SSE_INTALU_ITINS_P, 1>,
2054 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2055 defm VPMAXSQZ : avx512_binop_rm<0x3D, "vpmaxsq", X86smax, v8i64, VK8WM, VR512,
2056 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2057 SSE_INTALU_ITINS_P, 0>,
2058 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2060 defm VPMINUDZ : avx512_binop_rm<0x3B, "vpminud", X86umin, v16i32, VK16WM, VR512,
2061 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2062 SSE_INTALU_ITINS_P, 1>,
2063 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2064 defm VPMINUQZ : avx512_binop_rm<0x3B, "vpminuq", X86umin, v8i64, VK8WM, VR512,
2065 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2066 SSE_INTALU_ITINS_P, 0>,
2067 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2069 defm VPMINSDZ : avx512_binop_rm<0x39, "vpminsd", X86smin, v16i32, VK16WM, VR512,
2070 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2071 SSE_INTALU_ITINS_P, 1>,
2072 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2073 defm VPMINSQZ : avx512_binop_rm<0x39, "vpminsq", X86smin, v8i64, VK8WM, VR512,
2074 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2075 SSE_INTALU_ITINS_P, 0>,
2076 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2078 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxs_d_512 (v16i32 VR512:$src1),
2079 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2080 (VPMAXSDZrr VR512:$src1, VR512:$src2)>;
2081 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxu_d_512 (v16i32 VR512:$src1),
2082 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2083 (VPMAXUDZrr VR512:$src1, VR512:$src2)>;
2084 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxs_q_512 (v8i64 VR512:$src1),
2085 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2086 (VPMAXSQZrr VR512:$src1, VR512:$src2)>;
2087 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxu_q_512 (v8i64 VR512:$src1),
2088 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2089 (VPMAXUQZrr VR512:$src1, VR512:$src2)>;
2090 def : Pat <(v16i32 (int_x86_avx512_mask_pmins_d_512 (v16i32 VR512:$src1),
2091 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2092 (VPMINSDZrr VR512:$src1, VR512:$src2)>;
2093 def : Pat <(v16i32 (int_x86_avx512_mask_pminu_d_512 (v16i32 VR512:$src1),
2094 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2095 (VPMINUDZrr VR512:$src1, VR512:$src2)>;
2096 def : Pat <(v8i64 (int_x86_avx512_mask_pmins_q_512 (v8i64 VR512:$src1),
2097 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2098 (VPMINSQZrr VR512:$src1, VR512:$src2)>;
2099 def : Pat <(v8i64 (int_x86_avx512_mask_pminu_q_512 (v8i64 VR512:$src1),
2100 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2101 (VPMINUQZrr VR512:$src1, VR512:$src2)>;
2102 //===----------------------------------------------------------------------===//
2103 // AVX-512 - Unpack Instructions
2104 //===----------------------------------------------------------------------===//
2106 multiclass avx512_unpack_fp<bits<8> opc, SDNode OpNode, ValueType vt,
2107 PatFrag mem_frag, RegisterClass RC,
2108 X86MemOperand x86memop, string asm,
2110 def rr : AVX512PI<opc, MRMSrcReg,
2111 (outs RC:$dst), (ins RC:$src1, RC:$src2),
2113 (vt (OpNode RC:$src1, RC:$src2)))],
2115 def rm : AVX512PI<opc, MRMSrcMem,
2116 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2118 (vt (OpNode RC:$src1,
2119 (bitconvert (mem_frag addr:$src2)))))],
2123 defm VUNPCKHPSZ: avx512_unpack_fp<0x15, X86Unpckh, v16f32, memopv8f64,
2124 VR512, f512mem, "vunpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2125 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
2126 defm VUNPCKHPDZ: avx512_unpack_fp<0x15, X86Unpckh, v8f64, memopv8f64,
2127 VR512, f512mem, "vunpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2128 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2129 defm VUNPCKLPSZ: avx512_unpack_fp<0x14, X86Unpckl, v16f32, memopv8f64,
2130 VR512, f512mem, "vunpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2131 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
2132 defm VUNPCKLPDZ: avx512_unpack_fp<0x14, X86Unpckl, v8f64, memopv8f64,
2133 VR512, f512mem, "vunpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2134 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2136 multiclass avx512_unpack_int<bits<8> opc, string OpcodeStr, SDNode OpNode,
2137 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
2138 X86MemOperand x86memop> {
2139 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2140 (ins RC:$src1, RC:$src2),
2141 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2142 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
2143 IIC_SSE_UNPCK>, EVEX_4V;
2144 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2145 (ins RC:$src1, x86memop:$src2),
2146 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2147 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1),
2148 (bitconvert (memop_frag addr:$src2)))))],
2149 IIC_SSE_UNPCK>, EVEX_4V;
2151 defm VPUNPCKLDQZ : avx512_unpack_int<0x62, "vpunpckldq", X86Unpckl, v16i32,
2152 VR512, memopv16i32, i512mem>, EVEX_V512,
2153 EVEX_CD8<32, CD8VF>;
2154 defm VPUNPCKLQDQZ : avx512_unpack_int<0x6C, "vpunpcklqdq", X86Unpckl, v8i64,
2155 VR512, memopv8i64, i512mem>, EVEX_V512,
2156 VEX_W, EVEX_CD8<64, CD8VF>;
2157 defm VPUNPCKHDQZ : avx512_unpack_int<0x6A, "vpunpckhdq", X86Unpckh, v16i32,
2158 VR512, memopv16i32, i512mem>, EVEX_V512,
2159 EVEX_CD8<32, CD8VF>;
2160 defm VPUNPCKHQDQZ : avx512_unpack_int<0x6D, "vpunpckhqdq", X86Unpckh, v8i64,
2161 VR512, memopv8i64, i512mem>, EVEX_V512,
2162 VEX_W, EVEX_CD8<64, CD8VF>;
2163 //===----------------------------------------------------------------------===//
2167 multiclass avx512_pshuf_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
2168 SDNode OpNode, PatFrag mem_frag,
2169 X86MemOperand x86memop, ValueType OpVT> {
2170 def ri : AVX512Ii8<opc, MRMSrcReg, (outs RC:$dst),
2171 (ins RC:$src1, i8imm:$src2),
2172 !strconcat(OpcodeStr,
2173 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2175 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
2177 def mi : AVX512Ii8<opc, MRMSrcMem, (outs RC:$dst),
2178 (ins x86memop:$src1, i8imm:$src2),
2179 !strconcat(OpcodeStr,
2180 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2182 (OpVT (OpNode (mem_frag addr:$src1),
2183 (i8 imm:$src2))))]>, EVEX;
2186 defm VPSHUFDZ : avx512_pshuf_imm<0x70, "vpshufd", VR512, X86PShufd, memopv16i32,
2187 i512mem, v16i32>, PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2189 let ExeDomain = SSEPackedSingle in
2190 defm VPERMILPSZ : avx512_pshuf_imm<0x04, "vpermilps", VR512, X86VPermilp,
2191 memopv16f32, i512mem, v16f32>, TAPD, EVEX_V512,
2192 EVEX_CD8<32, CD8VF>;
2193 let ExeDomain = SSEPackedDouble in
2194 defm VPERMILPDZ : avx512_pshuf_imm<0x05, "vpermilpd", VR512, X86VPermilp,
2195 memopv8f64, i512mem, v8f64>, TAPD, EVEX_V512,
2196 VEX_W, EVEX_CD8<32, CD8VF>;
2198 def : Pat<(v16i32 (X86VPermilp VR512:$src1, (i8 imm:$imm))),
2199 (VPERMILPSZri VR512:$src1, imm:$imm)>;
2200 def : Pat<(v8i64 (X86VPermilp VR512:$src1, (i8 imm:$imm))),
2201 (VPERMILPDZri VR512:$src1, imm:$imm)>;
2203 //===----------------------------------------------------------------------===//
2204 // AVX-512 Logical Instructions
2205 //===----------------------------------------------------------------------===//
2207 defm VPANDDZ : avx512_binop_rm<0xDB, "vpandd", and, v16i32, VK16WM, VR512, memopv16i32,
2208 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
2209 EVEX_V512, EVEX_CD8<32, CD8VF>;
2210 defm VPANDQZ : avx512_binop_rm<0xDB, "vpandq", and, v8i64, VK8WM, VR512, memopv8i64,
2211 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
2212 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2213 defm VPORDZ : avx512_binop_rm<0xEB, "vpord", or, v16i32, VK16WM, VR512, memopv16i32,
2214 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
2215 EVEX_V512, EVEX_CD8<32, CD8VF>;
2216 defm VPORQZ : avx512_binop_rm<0xEB, "vporq", or, v8i64, VK8WM, VR512, memopv8i64,
2217 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
2218 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2219 defm VPXORDZ : avx512_binop_rm<0xEF, "vpxord", xor, v16i32, VK16WM, VR512, memopv16i32,
2220 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
2221 EVEX_V512, EVEX_CD8<32, CD8VF>;
2222 defm VPXORQZ : avx512_binop_rm<0xEF, "vpxorq", xor, v8i64, VK8WM, VR512, memopv8i64,
2223 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
2224 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2225 defm VPANDNDZ : avx512_binop_rm<0xDF, "vpandnd", X86andnp, v16i32, VK16WM, VR512,
2226 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2227 SSE_BIT_ITINS_P, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2228 defm VPANDNQZ : avx512_binop_rm<0xDF, "vpandnq", X86andnp, v8i64, VK8WM, VR512,
2229 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2230 SSE_BIT_ITINS_P, 0>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2232 //===----------------------------------------------------------------------===//
2233 // AVX-512 FP arithmetic
2234 //===----------------------------------------------------------------------===//
2236 multiclass avx512_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
2238 defm SSZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"), OpNode, FR32X,
2239 f32mem, itins.s, 0>, XS, EVEX_4V, VEX_LIG,
2240 EVEX_CD8<32, CD8VT1>;
2241 defm SDZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"), OpNode, FR64X,
2242 f64mem, itins.d, 0>, XD, VEX_W, EVEX_4V, VEX_LIG,
2243 EVEX_CD8<64, CD8VT1>;
2246 let isCommutable = 1 in {
2247 defm VADD : avx512_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>;
2248 defm VMUL : avx512_binop_s<0x59, "mul", fmul, SSE_ALU_ITINS_S>;
2249 defm VMIN : avx512_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>;
2250 defm VMAX : avx512_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>;
2252 let isCommutable = 0 in {
2253 defm VSUB : avx512_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>;
2254 defm VDIV : avx512_binop_s<0x5E, "div", fdiv, SSE_ALU_ITINS_S>;
2257 multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
2259 RegisterClass RC, ValueType vt,
2260 X86MemOperand x86memop, PatFrag mem_frag,
2261 X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2263 Domain d, OpndItins itins, bit commutable> {
2264 let isCommutable = commutable in {
2265 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
2266 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2267 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
2270 def rrk: PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src1, RC:$src2),
2271 !strconcat(OpcodeStr,
2272 " \t{$src2, $src1, $dst {${mask}} |$dst {${mask}}, $src1, $src2}"),
2273 [], itins.rr, d>, EVEX_4V, EVEX_K;
2275 def rrkz: PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src1, RC:$src2),
2276 !strconcat(OpcodeStr,
2277 " \t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2278 [], itins.rr, d>, EVEX_4V, EVEX_KZ;
2281 let mayLoad = 1 in {
2282 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2283 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2284 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
2285 itins.rm, d>, EVEX_4V;
2287 def rmb : PI<opc, MRMSrcMem, (outs RC:$dst),
2288 (ins RC:$src1, x86scalar_mop:$src2),
2289 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2290 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
2291 [(set RC:$dst, (OpNode RC:$src1,
2292 (vt (X86VBroadcast (scalar_mfrag addr:$src2)))))],
2293 itins.rm, d>, EVEX_4V, EVEX_B;
2295 def rmk : PI<opc, MRMSrcMem, (outs RC:$dst),
2296 (ins KRC:$mask, RC:$src1, x86memop:$src2), !strconcat(OpcodeStr,
2297 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2298 [], itins.rm, d>, EVEX_4V, EVEX_K;
2300 def rmkz : PI<opc, MRMSrcMem, (outs RC:$dst),
2301 (ins KRC:$mask, RC:$src1, x86memop:$src2), !strconcat(OpcodeStr,
2302 "\t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2303 [], itins.rm, d>, EVEX_4V, EVEX_KZ;
2305 def rmbk : PI<opc, MRMSrcMem, (outs RC:$dst),
2306 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2), !strconcat(OpcodeStr,
2307 " \t{${src2}", BrdcstStr,
2308 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}", BrdcstStr, "}"),
2309 [], itins.rm, d>, EVEX_4V, EVEX_B, EVEX_K;
2311 def rmbkz : PI<opc, MRMSrcMem, (outs RC:$dst),
2312 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2), !strconcat(OpcodeStr,
2313 " \t{${src2}", BrdcstStr,
2314 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
2316 [], itins.rm, d>, EVEX_4V, EVEX_B, EVEX_KZ;
2320 defm VADDPSZ : avx512_fp_packed<0x58, "addps", fadd, VK16WM, VR512, v16f32, f512mem,
2321 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2322 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2324 defm VADDPDZ : avx512_fp_packed<0x58, "addpd", fadd, VK8WM, VR512, v8f64, f512mem,
2325 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2326 SSE_ALU_ITINS_P.d, 1>,
2327 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2329 defm VMULPSZ : avx512_fp_packed<0x59, "mulps", fmul, VK16WM, VR512, v16f32, f512mem,
2330 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2331 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2332 defm VMULPDZ : avx512_fp_packed<0x59, "mulpd", fmul, VK8WM, VR512, v8f64, f512mem,
2333 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2334 SSE_ALU_ITINS_P.d, 1>,
2335 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2337 defm VMINPSZ : avx512_fp_packed<0x5D, "minps", X86fmin, VK16WM, VR512, v16f32, f512mem,
2338 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2339 SSE_ALU_ITINS_P.s, 1>,
2340 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2341 defm VMAXPSZ : avx512_fp_packed<0x5F, "maxps", X86fmax, VK16WM, VR512, v16f32, f512mem,
2342 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2343 SSE_ALU_ITINS_P.s, 1>,
2344 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2346 defm VMINPDZ : avx512_fp_packed<0x5D, "minpd", X86fmin, VK8WM, VR512, v8f64, f512mem,
2347 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2348 SSE_ALU_ITINS_P.d, 1>,
2349 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2350 defm VMAXPDZ : avx512_fp_packed<0x5F, "maxpd", X86fmax, VK8WM, VR512, v8f64, f512mem,
2351 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2352 SSE_ALU_ITINS_P.d, 1>,
2353 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2355 defm VSUBPSZ : avx512_fp_packed<0x5C, "subps", fsub, VK16WM, VR512, v16f32, f512mem,
2356 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2357 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2358 defm VDIVPSZ : avx512_fp_packed<0x5E, "divps", fdiv, VK16WM, VR512, v16f32, f512mem,
2359 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2360 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2362 defm VSUBPDZ : avx512_fp_packed<0x5C, "subpd", fsub, VK8WM, VR512, v8f64, f512mem,
2363 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2364 SSE_ALU_ITINS_P.d, 0>,
2365 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2366 defm VDIVPDZ : avx512_fp_packed<0x5E, "divpd", fdiv, VK8WM, VR512, v8f64, f512mem,
2367 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2368 SSE_ALU_ITINS_P.d, 0>,
2369 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2371 def : Pat<(v16f32 (int_x86_avx512_mask_max_ps_512 (v16f32 VR512:$src1),
2372 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
2373 (i16 -1), FROUND_CURRENT)),
2374 (VMAXPSZrr VR512:$src1, VR512:$src2)>;
2376 def : Pat<(v8f64 (int_x86_avx512_mask_max_pd_512 (v8f64 VR512:$src1),
2377 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
2378 (i8 -1), FROUND_CURRENT)),
2379 (VMAXPDZrr VR512:$src1, VR512:$src2)>;
2381 def : Pat<(v16f32 (int_x86_avx512_mask_min_ps_512 (v16f32 VR512:$src1),
2382 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
2383 (i16 -1), FROUND_CURRENT)),
2384 (VMINPSZrr VR512:$src1, VR512:$src2)>;
2386 def : Pat<(v8f64 (int_x86_avx512_mask_min_pd_512 (v8f64 VR512:$src1),
2387 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
2388 (i8 -1), FROUND_CURRENT)),
2389 (VMINPDZrr VR512:$src1, VR512:$src2)>;
2390 //===----------------------------------------------------------------------===//
2391 // AVX-512 VPTESTM instructions
2392 //===----------------------------------------------------------------------===//
2394 multiclass avx512_vptest<bits<8> opc, string OpcodeStr, RegisterClass KRC,
2395 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
2396 SDNode OpNode, ValueType vt> {
2397 def rr : AVX512PI<opc, MRMSrcReg,
2398 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
2399 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2400 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
2401 SSEPackedInt>, EVEX_4V;
2402 def rm : AVX512PI<opc, MRMSrcMem,
2403 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
2404 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2405 [(set KRC:$dst, (OpNode (vt RC:$src1),
2406 (bitconvert (memop_frag addr:$src2))))], SSEPackedInt>, EVEX_4V;
2409 defm VPTESTMDZ : avx512_vptest<0x27, "vptestmd", VK16, VR512, f512mem,
2410 memopv16i32, X86testm, v16i32>, T8PD, EVEX_V512,
2411 EVEX_CD8<32, CD8VF>;
2412 defm VPTESTMQZ : avx512_vptest<0x27, "vptestmq", VK8, VR512, f512mem,
2413 memopv8i64, X86testm, v8i64>, T8PD, EVEX_V512, VEX_W,
2414 EVEX_CD8<64, CD8VF>;
2416 let Predicates = [HasCDI] in {
2417 defm VPTESTNMDZ : avx512_vptest<0x27, "vptestnmd", VK16, VR512, f512mem,
2418 memopv16i32, X86testnm, v16i32>, T8XS, EVEX_V512,
2419 EVEX_CD8<32, CD8VF>;
2420 defm VPTESTNMQZ : avx512_vptest<0x27, "vptestnmq", VK8, VR512, f512mem,
2421 memopv8i64, X86testnm, v8i64>, T8XS, EVEX_V512, VEX_W,
2422 EVEX_CD8<64, CD8VF>;
2425 def : Pat <(i16 (int_x86_avx512_mask_ptestm_d_512 (v16i32 VR512:$src1),
2426 (v16i32 VR512:$src2), (i16 -1))),
2427 (COPY_TO_REGCLASS (VPTESTMDZrr VR512:$src1, VR512:$src2), GR16)>;
2429 def : Pat <(i8 (int_x86_avx512_mask_ptestm_q_512 (v8i64 VR512:$src1),
2430 (v8i64 VR512:$src2), (i8 -1))),
2431 (COPY_TO_REGCLASS (VPTESTMQZrr VR512:$src1, VR512:$src2), GR8)>;
2432 //===----------------------------------------------------------------------===//
2433 // AVX-512 Shift instructions
2434 //===----------------------------------------------------------------------===//
2435 multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
2436 string OpcodeStr, SDNode OpNode, RegisterClass RC,
2437 ValueType vt, X86MemOperand x86memop, PatFrag mem_frag,
2438 RegisterClass KRC> {
2439 def ri : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
2440 (ins RC:$src1, i8imm:$src2),
2441 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2442 [(set RC:$dst, (vt (OpNode RC:$src1, (i8 imm:$src2))))],
2443 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
2444 def rik : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
2445 (ins KRC:$mask, RC:$src1, i8imm:$src2),
2446 !strconcat(OpcodeStr,
2447 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2448 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
2449 def mi: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
2450 (ins x86memop:$src1, i8imm:$src2),
2451 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2452 [(set RC:$dst, (OpNode (mem_frag addr:$src1),
2453 (i8 imm:$src2)))], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
2454 def mik: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
2455 (ins KRC:$mask, x86memop:$src1, i8imm:$src2),
2456 !strconcat(OpcodeStr,
2457 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2458 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
2461 multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2462 RegisterClass RC, ValueType vt, ValueType SrcVT,
2463 PatFrag bc_frag, RegisterClass KRC> {
2464 // src2 is always 128-bit
2465 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2466 (ins RC:$src1, VR128X:$src2),
2467 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2468 [(set RC:$dst, (vt (OpNode RC:$src1, (SrcVT VR128X:$src2))))],
2469 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
2470 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2471 (ins KRC:$mask, RC:$src1, VR128X:$src2),
2472 !strconcat(OpcodeStr,
2473 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2474 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
2475 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2476 (ins RC:$src1, i128mem:$src2),
2477 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2478 [(set RC:$dst, (vt (OpNode RC:$src1,
2479 (bc_frag (memopv2i64 addr:$src2)))))],
2480 SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
2481 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2482 (ins KRC:$mask, RC:$src1, i128mem:$src2),
2483 !strconcat(OpcodeStr,
2484 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2485 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
2488 defm VPSRLDZ : avx512_shift_rmi<0x72, MRM2r, MRM2m, "vpsrld", X86vsrli,
2489 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
2490 EVEX_V512, EVEX_CD8<32, CD8VF>;
2491 defm VPSRLDZ : avx512_shift_rrm<0xD2, "vpsrld", X86vsrl,
2492 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2493 EVEX_CD8<32, CD8VQ>;
2495 defm VPSRLQZ : avx512_shift_rmi<0x73, MRM2r, MRM2m, "vpsrlq", X86vsrli,
2496 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2497 EVEX_CD8<64, CD8VF>, VEX_W;
2498 defm VPSRLQZ : avx512_shift_rrm<0xD3, "vpsrlq", X86vsrl,
2499 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2500 EVEX_CD8<64, CD8VQ>, VEX_W;
2502 defm VPSLLDZ : avx512_shift_rmi<0x72, MRM6r, MRM6m, "vpslld", X86vshli,
2503 VR512, v16i32, i512mem, memopv16i32, VK16WM>, EVEX_V512,
2504 EVEX_CD8<32, CD8VF>;
2505 defm VPSLLDZ : avx512_shift_rrm<0xF2, "vpslld", X86vshl,
2506 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2507 EVEX_CD8<32, CD8VQ>;
2509 defm VPSLLQZ : avx512_shift_rmi<0x73, MRM6r, MRM6m, "vpsllq", X86vshli,
2510 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2511 EVEX_CD8<64, CD8VF>, VEX_W;
2512 defm VPSLLQZ : avx512_shift_rrm<0xF3, "vpsllq", X86vshl,
2513 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2514 EVEX_CD8<64, CD8VQ>, VEX_W;
2516 defm VPSRADZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsrad", X86vsrai,
2517 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
2518 EVEX_V512, EVEX_CD8<32, CD8VF>;
2519 defm VPSRADZ : avx512_shift_rrm<0xE2, "vpsrad", X86vsra,
2520 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2521 EVEX_CD8<32, CD8VQ>;
2523 defm VPSRAQZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsraq", X86vsrai,
2524 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2525 EVEX_CD8<64, CD8VF>, VEX_W;
2526 defm VPSRAQZ : avx512_shift_rrm<0xE2, "vpsraq", X86vsra,
2527 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2528 EVEX_CD8<64, CD8VQ>, VEX_W;
2530 //===-------------------------------------------------------------------===//
2531 // Variable Bit Shifts
2532 //===-------------------------------------------------------------------===//
2533 multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
2534 RegisterClass RC, ValueType vt,
2535 X86MemOperand x86memop, PatFrag mem_frag> {
2536 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
2537 (ins RC:$src1, RC:$src2),
2538 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2540 (vt (OpNode RC:$src1, (vt RC:$src2))))]>,
2542 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
2543 (ins RC:$src1, x86memop:$src2),
2544 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2546 (vt (OpNode RC:$src1, (mem_frag addr:$src2))))]>,
2550 defm VPSLLVDZ : avx512_var_shift<0x47, "vpsllvd", shl, VR512, v16i32,
2551 i512mem, memopv16i32>, EVEX_V512,
2552 EVEX_CD8<32, CD8VF>;
2553 defm VPSLLVQZ : avx512_var_shift<0x47, "vpsllvq", shl, VR512, v8i64,
2554 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2555 EVEX_CD8<64, CD8VF>;
2556 defm VPSRLVDZ : avx512_var_shift<0x45, "vpsrlvd", srl, VR512, v16i32,
2557 i512mem, memopv16i32>, EVEX_V512,
2558 EVEX_CD8<32, CD8VF>;
2559 defm VPSRLVQZ : avx512_var_shift<0x45, "vpsrlvq", srl, VR512, v8i64,
2560 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2561 EVEX_CD8<64, CD8VF>;
2562 defm VPSRAVDZ : avx512_var_shift<0x46, "vpsravd", sra, VR512, v16i32,
2563 i512mem, memopv16i32>, EVEX_V512,
2564 EVEX_CD8<32, CD8VF>;
2565 defm VPSRAVQZ : avx512_var_shift<0x46, "vpsravq", sra, VR512, v8i64,
2566 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2567 EVEX_CD8<64, CD8VF>;
2569 //===----------------------------------------------------------------------===//
2570 // AVX-512 - MOVDDUP
2571 //===----------------------------------------------------------------------===//
2573 multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT,
2574 X86MemOperand x86memop, PatFrag memop_frag> {
2575 def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
2576 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
2577 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX;
2578 def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2579 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
2581 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX;
2584 defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, memopv8f64>,
2585 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
2586 def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
2587 (VMOVDDUPZrm addr:$src)>;
2589 //===---------------------------------------------------------------------===//
2590 // Replicate Single FP - MOVSHDUP and MOVSLDUP
2591 //===---------------------------------------------------------------------===//
2592 multiclass avx512_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
2593 ValueType vt, RegisterClass RC, PatFrag mem_frag,
2594 X86MemOperand x86memop> {
2595 def rr : AVX512XSI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
2596 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
2597 [(set RC:$dst, (vt (OpNode RC:$src)))]>, EVEX;
2599 def rm : AVX512XSI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2600 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
2601 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>, EVEX;
2604 defm VMOVSHDUPZ : avx512_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
2605 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
2606 EVEX_CD8<32, CD8VF>;
2607 defm VMOVSLDUPZ : avx512_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
2608 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
2609 EVEX_CD8<32, CD8VF>;
2611 def : Pat<(v16i32 (X86Movshdup VR512:$src)), (VMOVSHDUPZrr VR512:$src)>;
2612 def : Pat<(v16i32 (X86Movshdup (memopv16i32 addr:$src))),
2613 (VMOVSHDUPZrm addr:$src)>;
2614 def : Pat<(v16i32 (X86Movsldup VR512:$src)), (VMOVSLDUPZrr VR512:$src)>;
2615 def : Pat<(v16i32 (X86Movsldup (memopv16i32 addr:$src))),
2616 (VMOVSLDUPZrm addr:$src)>;
2618 //===----------------------------------------------------------------------===//
2619 // Move Low to High and High to Low packed FP Instructions
2620 //===----------------------------------------------------------------------===//
2621 def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
2622 (ins VR128X:$src1, VR128X:$src2),
2623 "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2624 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
2625 IIC_SSE_MOV_LH>, EVEX_4V;
2626 def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
2627 (ins VR128X:$src1, VR128X:$src2),
2628 "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2629 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
2630 IIC_SSE_MOV_LH>, EVEX_4V;
2632 let Predicates = [HasAVX512] in {
2634 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
2635 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
2636 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
2637 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
2640 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
2641 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
2644 //===----------------------------------------------------------------------===//
2645 // FMA - Fused Multiply Operations
2647 let Constraints = "$src1 = $dst" in {
2648 multiclass avx512_fma3p_rm<bits<8> opc, string OpcodeStr,
2649 RegisterClass RC, X86MemOperand x86memop,
2650 PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2651 string BrdcstStr, SDNode OpNode, ValueType OpVT> {
2652 def r: AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
2653 (ins RC:$src1, RC:$src2, RC:$src3),
2654 !strconcat(OpcodeStr," \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2655 [(set RC:$dst, (OpVT(OpNode RC:$src1, RC:$src2, RC:$src3)))]>;
2658 def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2659 (ins RC:$src1, RC:$src2, x86memop:$src3),
2660 !strconcat(OpcodeStr, " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2661 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2,
2662 (mem_frag addr:$src3))))]>;
2663 def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2664 (ins RC:$src1, RC:$src2, x86scalar_mop:$src3),
2665 !strconcat(OpcodeStr, " \t{${src3}", BrdcstStr,
2666 ", $src2, $dst|$dst, $src2, ${src3}", BrdcstStr, "}"),
2667 [(set RC:$dst, (OpNode RC:$src1, RC:$src2,
2668 (OpVT (X86VBroadcast (scalar_mfrag addr:$src3)))))]>, EVEX_B;
2670 } // Constraints = "$src1 = $dst"
2672 let ExeDomain = SSEPackedSingle in {
2673 defm VFMADD213PSZ : avx512_fma3p_rm<0xA8, "vfmadd213ps", VR512, f512mem,
2674 memopv16f32, f32mem, loadf32, "{1to16}",
2675 X86Fmadd, v16f32>, EVEX_V512,
2676 EVEX_CD8<32, CD8VF>;
2677 defm VFMSUB213PSZ : avx512_fma3p_rm<0xAA, "vfmsub213ps", VR512, f512mem,
2678 memopv16f32, f32mem, loadf32, "{1to16}",
2679 X86Fmsub, v16f32>, EVEX_V512,
2680 EVEX_CD8<32, CD8VF>;
2681 defm VFMADDSUB213PSZ : avx512_fma3p_rm<0xA6, "vfmaddsub213ps", VR512, f512mem,
2682 memopv16f32, f32mem, loadf32, "{1to16}",
2683 X86Fmaddsub, v16f32>,
2684 EVEX_V512, EVEX_CD8<32, CD8VF>;
2685 defm VFMSUBADD213PSZ : avx512_fma3p_rm<0xA7, "vfmsubadd213ps", VR512, f512mem,
2686 memopv16f32, f32mem, loadf32, "{1to16}",
2687 X86Fmsubadd, v16f32>,
2688 EVEX_V512, EVEX_CD8<32, CD8VF>;
2689 defm VFNMADD213PSZ : avx512_fma3p_rm<0xAC, "vfnmadd213ps", VR512, f512mem,
2690 memopv16f32, f32mem, loadf32, "{1to16}",
2691 X86Fnmadd, v16f32>, EVEX_V512,
2692 EVEX_CD8<32, CD8VF>;
2693 defm VFNMSUB213PSZ : avx512_fma3p_rm<0xAE, "vfnmsub213ps", VR512, f512mem,
2694 memopv16f32, f32mem, loadf32, "{1to16}",
2695 X86Fnmsub, v16f32>, EVEX_V512,
2696 EVEX_CD8<32, CD8VF>;
2698 let ExeDomain = SSEPackedDouble in {
2699 defm VFMADD213PDZ : avx512_fma3p_rm<0xA8, "vfmadd213pd", VR512, f512mem,
2700 memopv8f64, f64mem, loadf64, "{1to8}",
2701 X86Fmadd, v8f64>, EVEX_V512,
2702 VEX_W, EVEX_CD8<64, CD8VF>;
2703 defm VFMSUB213PDZ : avx512_fma3p_rm<0xAA, "vfmsub213pd", VR512, f512mem,
2704 memopv8f64, f64mem, loadf64, "{1to8}",
2705 X86Fmsub, v8f64>, EVEX_V512, VEX_W,
2706 EVEX_CD8<64, CD8VF>;
2707 defm VFMADDSUB213PDZ : avx512_fma3p_rm<0xA6, "vfmaddsub213pd", VR512, f512mem,
2708 memopv8f64, f64mem, loadf64, "{1to8}",
2709 X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
2710 EVEX_CD8<64, CD8VF>;
2711 defm VFMSUBADD213PDZ : avx512_fma3p_rm<0xA7, "vfmsubadd213pd", VR512, f512mem,
2712 memopv8f64, f64mem, loadf64, "{1to8}",
2713 X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
2714 EVEX_CD8<64, CD8VF>;
2715 defm VFNMADD213PDZ : avx512_fma3p_rm<0xAC, "vfnmadd213pd", VR512, f512mem,
2716 memopv8f64, f64mem, loadf64, "{1to8}",
2717 X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
2718 EVEX_CD8<64, CD8VF>;
2719 defm VFNMSUB213PDZ : avx512_fma3p_rm<0xAE, "vfnmsub213pd", VR512, f512mem,
2720 memopv8f64, f64mem, loadf64, "{1to8}",
2721 X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
2722 EVEX_CD8<64, CD8VF>;
2725 let Constraints = "$src1 = $dst" in {
2726 multiclass avx512_fma3p_m132<bits<8> opc, string OpcodeStr,
2727 RegisterClass RC, X86MemOperand x86memop,
2728 PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2729 string BrdcstStr, SDNode OpNode, ValueType OpVT> {
2731 def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2732 (ins RC:$src1, RC:$src3, x86memop:$src2),
2733 !strconcat(OpcodeStr, " \t{$src2, $src3, $dst|$dst, $src3, $src2}"),
2734 [(set RC:$dst, (OpVT (OpNode RC:$src1, (mem_frag addr:$src2), RC:$src3)))]>;
2735 def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2736 (ins RC:$src1, RC:$src3, x86scalar_mop:$src2),
2737 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2738 ", $src3, $dst|$dst, $src3, ${src2}", BrdcstStr, "}"),
2739 [(set RC:$dst, (OpNode RC:$src1,
2740 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2))), RC:$src3))]>, EVEX_B;
2742 } // Constraints = "$src1 = $dst"
2745 let ExeDomain = SSEPackedSingle in {
2746 defm VFMADD132PSZ : avx512_fma3p_m132<0x98, "vfmadd132ps", VR512, f512mem,
2747 memopv16f32, f32mem, loadf32, "{1to16}",
2748 X86Fmadd, v16f32>, EVEX_V512,
2749 EVEX_CD8<32, CD8VF>;
2750 defm VFMSUB132PSZ : avx512_fma3p_m132<0x9A, "vfmsub132ps", VR512, f512mem,
2751 memopv16f32, f32mem, loadf32, "{1to16}",
2752 X86Fmsub, v16f32>, EVEX_V512,
2753 EVEX_CD8<32, CD8VF>;
2754 defm VFMADDSUB132PSZ : avx512_fma3p_m132<0x96, "vfmaddsub132ps", VR512, f512mem,
2755 memopv16f32, f32mem, loadf32, "{1to16}",
2756 X86Fmaddsub, v16f32>,
2757 EVEX_V512, EVEX_CD8<32, CD8VF>;
2758 defm VFMSUBADD132PSZ : avx512_fma3p_m132<0x97, "vfmsubadd132ps", VR512, f512mem,
2759 memopv16f32, f32mem, loadf32, "{1to16}",
2760 X86Fmsubadd, v16f32>,
2761 EVEX_V512, EVEX_CD8<32, CD8VF>;
2762 defm VFNMADD132PSZ : avx512_fma3p_m132<0x9C, "vfnmadd132ps", VR512, f512mem,
2763 memopv16f32, f32mem, loadf32, "{1to16}",
2764 X86Fnmadd, v16f32>, EVEX_V512,
2765 EVEX_CD8<32, CD8VF>;
2766 defm VFNMSUB132PSZ : avx512_fma3p_m132<0x9E, "vfnmsub132ps", VR512, f512mem,
2767 memopv16f32, f32mem, loadf32, "{1to16}",
2768 X86Fnmsub, v16f32>, EVEX_V512,
2769 EVEX_CD8<32, CD8VF>;
2771 let ExeDomain = SSEPackedDouble in {
2772 defm VFMADD132PDZ : avx512_fma3p_m132<0x98, "vfmadd132pd", VR512, f512mem,
2773 memopv8f64, f64mem, loadf64, "{1to8}",
2774 X86Fmadd, v8f64>, EVEX_V512,
2775 VEX_W, EVEX_CD8<64, CD8VF>;
2776 defm VFMSUB132PDZ : avx512_fma3p_m132<0x9A, "vfmsub132pd", VR512, f512mem,
2777 memopv8f64, f64mem, loadf64, "{1to8}",
2778 X86Fmsub, v8f64>, EVEX_V512, VEX_W,
2779 EVEX_CD8<64, CD8VF>;
2780 defm VFMADDSUB132PDZ : avx512_fma3p_m132<0x96, "vfmaddsub132pd", VR512, f512mem,
2781 memopv8f64, f64mem, loadf64, "{1to8}",
2782 X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
2783 EVEX_CD8<64, CD8VF>;
2784 defm VFMSUBADD132PDZ : avx512_fma3p_m132<0x97, "vfmsubadd132pd", VR512, f512mem,
2785 memopv8f64, f64mem, loadf64, "{1to8}",
2786 X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
2787 EVEX_CD8<64, CD8VF>;
2788 defm VFNMADD132PDZ : avx512_fma3p_m132<0x9C, "vfnmadd132pd", VR512, f512mem,
2789 memopv8f64, f64mem, loadf64, "{1to8}",
2790 X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
2791 EVEX_CD8<64, CD8VF>;
2792 defm VFNMSUB132PDZ : avx512_fma3p_m132<0x9E, "vfnmsub132pd", VR512, f512mem,
2793 memopv8f64, f64mem, loadf64, "{1to8}",
2794 X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
2795 EVEX_CD8<64, CD8VF>;
2799 let Constraints = "$src1 = $dst" in {
2800 multiclass avx512_fma3s_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2801 RegisterClass RC, ValueType OpVT,
2802 X86MemOperand x86memop, Operand memop,
2804 let isCommutable = 1 in
2805 def r : AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
2806 (ins RC:$src1, RC:$src2, RC:$src3),
2807 !strconcat(OpcodeStr,
2808 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2810 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
2812 def m : AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2813 (ins RC:$src1, RC:$src2, f128mem:$src3),
2814 !strconcat(OpcodeStr,
2815 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2817 (OpVT (OpNode RC:$src2, RC:$src1,
2818 (mem_frag addr:$src3))))]>;
2821 } // Constraints = "$src1 = $dst"
2823 defm VFMADDSSZ : avx512_fma3s_rm<0xA9, "vfmadd213ss", X86Fmadd, FR32X,
2824 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2825 defm VFMADDSDZ : avx512_fma3s_rm<0xA9, "vfmadd213sd", X86Fmadd, FR64X,
2826 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2827 defm VFMSUBSSZ : avx512_fma3s_rm<0xAB, "vfmsub213ss", X86Fmsub, FR32X,
2828 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2829 defm VFMSUBSDZ : avx512_fma3s_rm<0xAB, "vfmsub213sd", X86Fmsub, FR64X,
2830 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2831 defm VFNMADDSSZ : avx512_fma3s_rm<0xAD, "vfnmadd213ss", X86Fnmadd, FR32X,
2832 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2833 defm VFNMADDSDZ : avx512_fma3s_rm<0xAD, "vfnmadd213sd", X86Fnmadd, FR64X,
2834 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2835 defm VFNMSUBSSZ : avx512_fma3s_rm<0xAF, "vfnmsub213ss", X86Fnmsub, FR32X,
2836 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2837 defm VFNMSUBSDZ : avx512_fma3s_rm<0xAF, "vfnmsub213sd", X86Fnmsub, FR64X,
2838 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2840 //===----------------------------------------------------------------------===//
2841 // AVX-512 Scalar convert from sign integer to float/double
2842 //===----------------------------------------------------------------------===//
2844 multiclass avx512_vcvtsi<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2845 X86MemOperand x86memop, string asm> {
2846 let hasSideEffects = 0 in {
2847 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
2848 !strconcat(asm," \t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
2851 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
2852 (ins DstRC:$src1, x86memop:$src),
2853 !strconcat(asm," \t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
2855 } // hasSideEffects = 0
2857 let Predicates = [HasAVX512] in {
2858 defm VCVTSI2SSZ : avx512_vcvtsi<0x2A, GR32, FR32X, i32mem, "cvtsi2ss{l}">,
2859 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2860 defm VCVTSI642SSZ : avx512_vcvtsi<0x2A, GR64, FR32X, i64mem, "cvtsi2ss{q}">,
2861 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2862 defm VCVTSI2SDZ : avx512_vcvtsi<0x2A, GR32, FR64X, i32mem, "cvtsi2sd{l}">,
2863 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2864 defm VCVTSI642SDZ : avx512_vcvtsi<0x2A, GR64, FR64X, i64mem, "cvtsi2sd{q}">,
2865 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2867 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
2868 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2869 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
2870 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2871 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
2872 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2873 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
2874 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2876 def : Pat<(f32 (sint_to_fp GR32:$src)),
2877 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
2878 def : Pat<(f32 (sint_to_fp GR64:$src)),
2879 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
2880 def : Pat<(f64 (sint_to_fp GR32:$src)),
2881 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
2882 def : Pat<(f64 (sint_to_fp GR64:$src)),
2883 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
2885 defm VCVTUSI2SSZ : avx512_vcvtsi<0x7B, GR32, FR32X, i32mem, "cvtusi2ss{l}">,
2886 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2887 defm VCVTUSI642SSZ : avx512_vcvtsi<0x7B, GR64, FR32X, i64mem, "cvtusi2ss{q}">,
2888 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2889 defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, GR32, FR64X, i32mem, "cvtusi2sd{l}">,
2890 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2891 defm VCVTUSI642SDZ : avx512_vcvtsi<0x7B, GR64, FR64X, i64mem, "cvtusi2sd{q}">,
2892 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2894 def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
2895 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2896 def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
2897 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2898 def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
2899 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2900 def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
2901 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2903 def : Pat<(f32 (uint_to_fp GR32:$src)),
2904 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
2905 def : Pat<(f32 (uint_to_fp GR64:$src)),
2906 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
2907 def : Pat<(f64 (uint_to_fp GR32:$src)),
2908 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
2909 def : Pat<(f64 (uint_to_fp GR64:$src)),
2910 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
2913 //===----------------------------------------------------------------------===//
2914 // AVX-512 Scalar convert from float/double to integer
2915 //===----------------------------------------------------------------------===//
2916 multiclass avx512_cvt_s_int<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2917 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
2919 let hasSideEffects = 0 in {
2920 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2921 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
2922 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG,
2923 Requires<[HasAVX512]>;
2925 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
2926 !strconcat(asm," \t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG,
2927 Requires<[HasAVX512]>;
2928 } // hasSideEffects = 0
2930 let Predicates = [HasAVX512] in {
2931 // Convert float/double to signed/unsigned int 32/64
2932 defm VCVTSS2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
2933 ssmem, sse_load_f32, "cvtss2si">,
2934 XS, EVEX_CD8<32, CD8VT1>;
2935 defm VCVTSS2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse_cvtss2si64,
2936 ssmem, sse_load_f32, "cvtss2si">,
2937 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
2938 defm VCVTSS2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtss2usi,
2939 ssmem, sse_load_f32, "cvtss2usi">,
2940 XS, EVEX_CD8<32, CD8VT1>;
2941 defm VCVTSS2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
2942 int_x86_avx512_cvtss2usi64, ssmem,
2943 sse_load_f32, "cvtss2usi">, XS, VEX_W,
2944 EVEX_CD8<32, CD8VT1>;
2945 defm VCVTSD2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
2946 sdmem, sse_load_f64, "cvtsd2si">,
2947 XD, EVEX_CD8<64, CD8VT1>;
2948 defm VCVTSD2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse2_cvtsd2si64,
2949 sdmem, sse_load_f64, "cvtsd2si">,
2950 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
2951 defm VCVTSD2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtsd2usi,
2952 sdmem, sse_load_f64, "cvtsd2usi">,
2953 XD, EVEX_CD8<64, CD8VT1>;
2954 defm VCVTSD2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
2955 int_x86_avx512_cvtsd2usi64, sdmem,
2956 sse_load_f64, "cvtsd2usi">, XD, VEX_W,
2957 EVEX_CD8<64, CD8VT1>;
2959 let isCodeGenOnly = 1 in {
2960 defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2961 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
2962 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
2963 defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2964 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
2965 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
2966 defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2967 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
2968 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
2969 defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2970 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
2971 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
2973 defm Int_VCVTUSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2974 int_x86_avx512_cvtusi2ss, i32mem, loadi32, "cvtusi2ss{l}",
2975 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
2976 defm Int_VCVTUSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2977 int_x86_avx512_cvtusi642ss, i64mem, loadi64, "cvtusi2ss{q}",
2978 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
2979 defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2980 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}",
2981 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
2982 defm Int_VCVTUSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2983 int_x86_avx512_cvtusi642sd, i64mem, loadi64, "cvtusi2sd{q}",
2984 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
2985 } // isCodeGenOnly = 1
2987 // Convert float/double to signed/unsigned int 32/64 with truncation
2988 let isCodeGenOnly = 1 in {
2989 defm Int_VCVTTSS2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse_cvttss2si,
2990 ssmem, sse_load_f32, "cvttss2si">,
2991 XS, EVEX_CD8<32, CD8VT1>;
2992 defm Int_VCVTTSS2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
2993 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
2994 "cvttss2si">, XS, VEX_W,
2995 EVEX_CD8<32, CD8VT1>;
2996 defm Int_VCVTTSD2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse2_cvttsd2si,
2997 sdmem, sse_load_f64, "cvttsd2si">, XD,
2998 EVEX_CD8<64, CD8VT1>;
2999 defm Int_VCVTTSD2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
3000 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
3001 "cvttsd2si">, XD, VEX_W,
3002 EVEX_CD8<64, CD8VT1>;
3003 defm Int_VCVTTSS2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
3004 int_x86_avx512_cvttss2usi, ssmem, sse_load_f32,
3005 "cvttss2usi">, XS, EVEX_CD8<32, CD8VT1>;
3006 defm Int_VCVTTSS2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
3007 int_x86_avx512_cvttss2usi64, ssmem,
3008 sse_load_f32, "cvttss2usi">, XS, VEX_W,
3009 EVEX_CD8<32, CD8VT1>;
3010 defm Int_VCVTTSD2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
3011 int_x86_avx512_cvttsd2usi,
3012 sdmem, sse_load_f64, "cvttsd2usi">, XD,
3013 EVEX_CD8<64, CD8VT1>;
3014 defm Int_VCVTTSD2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
3015 int_x86_avx512_cvttsd2usi64, sdmem,
3016 sse_load_f64, "cvttsd2usi">, XD, VEX_W,
3017 EVEX_CD8<64, CD8VT1>;
3018 } // isCodeGenOnly = 1
3020 multiclass avx512_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3021 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
3023 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3024 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3025 [(set DstRC:$dst, (OpNode SrcRC:$src))]>, EVEX;
3026 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3027 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3028 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>, EVEX;
3031 defm VCVTTSS2SIZ : avx512_cvt_s<0x2C, FR32X, GR32, fp_to_sint, f32mem,
3032 loadf32, "cvttss2si">, XS,
3033 EVEX_CD8<32, CD8VT1>;
3034 defm VCVTTSS2USIZ : avx512_cvt_s<0x78, FR32X, GR32, fp_to_uint, f32mem,
3035 loadf32, "cvttss2usi">, XS,
3036 EVEX_CD8<32, CD8VT1>;
3037 defm VCVTTSS2SI64Z : avx512_cvt_s<0x2C, FR32X, GR64, fp_to_sint, f32mem,
3038 loadf32, "cvttss2si">, XS, VEX_W,
3039 EVEX_CD8<32, CD8VT1>;
3040 defm VCVTTSS2USI64Z : avx512_cvt_s<0x78, FR32X, GR64, fp_to_uint, f32mem,
3041 loadf32, "cvttss2usi">, XS, VEX_W,
3042 EVEX_CD8<32, CD8VT1>;
3043 defm VCVTTSD2SIZ : avx512_cvt_s<0x2C, FR64X, GR32, fp_to_sint, f64mem,
3044 loadf64, "cvttsd2si">, XD,
3045 EVEX_CD8<64, CD8VT1>;
3046 defm VCVTTSD2USIZ : avx512_cvt_s<0x78, FR64X, GR32, fp_to_uint, f64mem,
3047 loadf64, "cvttsd2usi">, XD,
3048 EVEX_CD8<64, CD8VT1>;
3049 defm VCVTTSD2SI64Z : avx512_cvt_s<0x2C, FR64X, GR64, fp_to_sint, f64mem,
3050 loadf64, "cvttsd2si">, XD, VEX_W,
3051 EVEX_CD8<64, CD8VT1>;
3052 defm VCVTTSD2USI64Z : avx512_cvt_s<0x78, FR64X, GR64, fp_to_uint, f64mem,
3053 loadf64, "cvttsd2usi">, XD, VEX_W,
3054 EVEX_CD8<64, CD8VT1>;
3056 //===----------------------------------------------------------------------===//
3057 // AVX-512 Convert form float to double and back
3058 //===----------------------------------------------------------------------===//
3059 let hasSideEffects = 0 in {
3060 def VCVTSS2SDZrr : AVX512XSI<0x5A, MRMSrcReg, (outs FR64X:$dst),
3061 (ins FR32X:$src1, FR32X:$src2),
3062 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3063 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
3065 def VCVTSS2SDZrm : AVX512XSI<0x5A, MRMSrcMem, (outs FR64X:$dst),
3066 (ins FR32X:$src1, f32mem:$src2),
3067 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3068 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
3069 EVEX_CD8<32, CD8VT1>;
3071 // Convert scalar double to scalar single
3072 def VCVTSD2SSZrr : AVX512XDI<0x5A, MRMSrcReg, (outs FR32X:$dst),
3073 (ins FR64X:$src1, FR64X:$src2),
3074 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3075 []>, EVEX_4V, VEX_LIG, VEX_W, Sched<[WriteCvtF2F]>;
3077 def VCVTSD2SSZrm : AVX512XDI<0x5A, MRMSrcMem, (outs FR32X:$dst),
3078 (ins FR64X:$src1, f64mem:$src2),
3079 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3080 []>, EVEX_4V, VEX_LIG, VEX_W,
3081 Sched<[WriteCvtF2FLd, ReadAfterLd]>, EVEX_CD8<64, CD8VT1>;
3084 def : Pat<(f64 (fextend FR32X:$src)), (VCVTSS2SDZrr FR32X:$src, FR32X:$src)>,
3085 Requires<[HasAVX512]>;
3086 def : Pat<(fextend (loadf32 addr:$src)),
3087 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512]>;
3089 def : Pat<(extloadf32 addr:$src),
3090 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>,
3091 Requires<[HasAVX512, OptForSize]>;
3093 def : Pat<(extloadf32 addr:$src),
3094 (VCVTSS2SDZrr (f32 (IMPLICIT_DEF)), (VMOVSSZrm addr:$src))>,
3095 Requires<[HasAVX512, OptForSpeed]>;
3097 def : Pat<(f32 (fround FR64X:$src)), (VCVTSD2SSZrr FR64X:$src, FR64X:$src)>,
3098 Requires<[HasAVX512]>;
3100 multiclass avx512_vcvt_fp_with_rc<bits<8> opc, string asm, RegisterClass SrcRC,
3101 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
3102 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
3104 let hasSideEffects = 0 in {
3105 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3106 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3108 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
3109 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
3110 !strconcat(asm," \t{$rc, $src, $dst|$dst, $src, $rc}"),
3111 [], d>, EVEX, EVEX_B, EVEX_RC;
3113 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3114 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3116 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
3117 } // hasSideEffects = 0
3120 multiclass avx512_vcvt_fp<bits<8> opc, string asm, RegisterClass SrcRC,
3121 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
3122 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
3124 let hasSideEffects = 0 in {
3125 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3126 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3128 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
3130 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3131 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3133 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
3134 } // hasSideEffects = 0
3137 defm VCVTPD2PSZ : avx512_vcvt_fp_with_rc<0x5A, "vcvtpd2ps", VR512, VR256X, fround,
3138 memopv8f64, f512mem, v8f32, v8f64,
3139 SSEPackedSingle>, EVEX_V512, VEX_W, PD,
3140 EVEX_CD8<64, CD8VF>;
3142 defm VCVTPS2PDZ : avx512_vcvt_fp<0x5A, "vcvtps2pd", VR256X, VR512, fextend,
3143 memopv4f64, f256mem, v8f64, v8f32,
3144 SSEPackedDouble>, EVEX_V512, PS,
3145 EVEX_CD8<32, CD8VH>;
3146 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
3147 (VCVTPS2PDZrm addr:$src)>;
3149 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
3150 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), (i32 FROUND_CURRENT))),
3151 (VCVTPD2PSZrr VR512:$src)>;
3153 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
3154 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), imm:$rc)),
3155 (VCVTPD2PSZrrb VR512:$src, imm:$rc)>;
3157 //===----------------------------------------------------------------------===//
3158 // AVX-512 Vector convert from sign integer to float/double
3159 //===----------------------------------------------------------------------===//
3161 defm VCVTDQ2PSZ : avx512_vcvt_fp_with_rc<0x5B, "vcvtdq2ps", VR512, VR512, sint_to_fp,
3162 memopv8i64, i512mem, v16f32, v16i32,
3163 SSEPackedSingle>, EVEX_V512, PS,
3164 EVEX_CD8<32, CD8VF>;
3166 defm VCVTDQ2PDZ : avx512_vcvt_fp<0xE6, "vcvtdq2pd", VR256X, VR512, sint_to_fp,
3167 memopv4i64, i256mem, v8f64, v8i32,
3168 SSEPackedDouble>, EVEX_V512, XS,
3169 EVEX_CD8<32, CD8VH>;
3171 defm VCVTTPS2DQZ : avx512_vcvt_fp<0x5B, "vcvttps2dq", VR512, VR512, fp_to_sint,
3172 memopv16f32, f512mem, v16i32, v16f32,
3173 SSEPackedSingle>, EVEX_V512, XS,
3174 EVEX_CD8<32, CD8VF>;
3176 defm VCVTTPD2DQZ : avx512_vcvt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint,
3177 memopv8f64, f512mem, v8i32, v8f64,
3178 SSEPackedDouble>, EVEX_V512, PD, VEX_W,
3179 EVEX_CD8<64, CD8VF>;
3181 defm VCVTTPS2UDQZ : avx512_vcvt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint,
3182 memopv16f32, f512mem, v16i32, v16f32,
3183 SSEPackedSingle>, EVEX_V512, PS,
3184 EVEX_CD8<32, CD8VF>;
3186 // cvttps2udq (src, 0, mask-all-ones, sae-current)
3187 def : Pat<(v16i32 (int_x86_avx512_mask_cvttps2udq_512 (v16f32 VR512:$src),
3188 (v16i32 immAllZerosV), (i16 -1), FROUND_CURRENT)),
3189 (VCVTTPS2UDQZrr VR512:$src)>;
3191 defm VCVTTPD2UDQZ : avx512_vcvt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint,
3192 memopv8f64, f512mem, v8i32, v8f64,
3193 SSEPackedDouble>, EVEX_V512, PS, VEX_W,
3194 EVEX_CD8<64, CD8VF>;
3196 // cvttpd2udq (src, 0, mask-all-ones, sae-current)
3197 def : Pat<(v8i32 (int_x86_avx512_mask_cvttpd2udq_512 (v8f64 VR512:$src),
3198 (v8i32 immAllZerosV), (i8 -1), FROUND_CURRENT)),
3199 (VCVTTPD2UDQZrr VR512:$src)>;
3201 defm VCVTUDQ2PDZ : avx512_vcvt_fp<0x7A, "vcvtudq2pd", VR256X, VR512, uint_to_fp,
3202 memopv4i64, f256mem, v8f64, v8i32,
3203 SSEPackedDouble>, EVEX_V512, XS,
3204 EVEX_CD8<32, CD8VH>;
3206 defm VCVTUDQ2PSZ : avx512_vcvt_fp_with_rc<0x7A, "vcvtudq2ps", VR512, VR512, uint_to_fp,
3207 memopv16i32, f512mem, v16f32, v16i32,
3208 SSEPackedSingle>, EVEX_V512, XD,
3209 EVEX_CD8<32, CD8VF>;
3211 def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
3212 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
3213 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
3215 def : Pat<(v4i32 (fp_to_uint (v4f32 VR128X:$src1))),
3216 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
3217 (v16f32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
3219 def : Pat<(v8f32 (uint_to_fp (v8i32 VR256X:$src1))),
3220 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
3221 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
3223 def : Pat<(v4f32 (uint_to_fp (v4i32 VR128X:$src1))),
3224 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
3225 (v16i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
3227 def : Pat<(v4f64 (uint_to_fp (v4i32 VR128X:$src1))),
3228 (EXTRACT_SUBREG (v8f64 (VCVTUDQ2PDZrr
3229 (v8i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_ymm)>;
3231 def : Pat<(v16f32 (int_x86_avx512_mask_cvtdq2ps_512 (v16i32 VR512:$src),
3232 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
3233 (VCVTDQ2PSZrrb VR512:$src, imm:$rc)>;
3234 def : Pat<(v8f64 (int_x86_avx512_mask_cvtdq2pd_512 (v8i32 VR256X:$src),
3235 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3236 (VCVTDQ2PDZrr VR256X:$src)>;
3237 def : Pat<(v16f32 (int_x86_avx512_mask_cvtudq2ps_512 (v16i32 VR512:$src),
3238 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
3239 (VCVTUDQ2PSZrrb VR512:$src, imm:$rc)>;
3240 def : Pat<(v8f64 (int_x86_avx512_mask_cvtudq2pd_512 (v8i32 VR256X:$src),
3241 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3242 (VCVTUDQ2PDZrr VR256X:$src)>;
3244 multiclass avx512_vcvt_fp2int<bits<8> opc, string asm, RegisterClass SrcRC,
3245 RegisterClass DstRC, PatFrag mem_frag,
3246 X86MemOperand x86memop, Domain d> {
3247 let hasSideEffects = 0 in {
3248 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3249 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3251 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
3252 !strconcat(asm," \t{$rc, $src, $dst|$dst, $src, $rc}"),
3253 [], d>, EVEX, EVEX_B, EVEX_RC;
3255 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3256 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3258 } // hasSideEffects = 0
3261 defm VCVTPS2DQZ : avx512_vcvt_fp2int<0x5B, "vcvtps2dq", VR512, VR512,
3262 memopv16f32, f512mem, SSEPackedSingle>, PD,
3263 EVEX_V512, EVEX_CD8<32, CD8VF>;
3264 defm VCVTPD2DQZ : avx512_vcvt_fp2int<0xE6, "vcvtpd2dq", VR512, VR256X,
3265 memopv8f64, f512mem, SSEPackedDouble>, XD, VEX_W,
3266 EVEX_V512, EVEX_CD8<64, CD8VF>;
3268 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2dq_512 (v16f32 VR512:$src),
3269 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
3270 (VCVTPS2DQZrrb VR512:$src, imm:$rc)>;
3272 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2dq_512 (v8f64 VR512:$src),
3273 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
3274 (VCVTPD2DQZrrb VR512:$src, imm:$rc)>;
3276 defm VCVTPS2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtps2udq", VR512, VR512,
3277 memopv16f32, f512mem, SSEPackedSingle>,
3278 PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
3279 defm VCVTPD2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtpd2udq", VR512, VR256X,
3280 memopv8f64, f512mem, SSEPackedDouble>, VEX_W,
3281 PS, EVEX_V512, EVEX_CD8<64, CD8VF>;
3283 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2udq_512 (v16f32 VR512:$src),
3284 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
3285 (VCVTPS2UDQZrrb VR512:$src, imm:$rc)>;
3287 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2udq_512 (v8f64 VR512:$src),
3288 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
3289 (VCVTPD2UDQZrrb VR512:$src, imm:$rc)>;
3291 let Predicates = [HasAVX512] in {
3292 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
3293 (VCVTPD2PSZrm addr:$src)>;
3294 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
3295 (VCVTPS2PDZrm addr:$src)>;
3298 //===----------------------------------------------------------------------===//
3299 // Half precision conversion instructions
3300 //===----------------------------------------------------------------------===//
3301 multiclass avx512_cvtph2ps<RegisterClass destRC, RegisterClass srcRC,
3302 X86MemOperand x86memop> {
3303 def rr : AVX5128I<0x13, MRMSrcReg, (outs destRC:$dst), (ins srcRC:$src),
3304 "vcvtph2ps\t{$src, $dst|$dst, $src}",
3306 let hasSideEffects = 0, mayLoad = 1 in
3307 def rm : AVX5128I<0x13, MRMSrcMem, (outs destRC:$dst), (ins x86memop:$src),
3308 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, EVEX;
3311 multiclass avx512_cvtps2ph<RegisterClass destRC, RegisterClass srcRC,
3312 X86MemOperand x86memop> {
3313 def rr : AVX512AIi8<0x1D, MRMDestReg, (outs destRC:$dst),
3314 (ins srcRC:$src1, i32i8imm:$src2),
3315 "vcvtps2ph \t{$src2, $src1, $dst|$dst, $src1, $src2}",
3317 let hasSideEffects = 0, mayStore = 1 in
3318 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
3319 (ins x86memop:$dst, srcRC:$src1, i32i8imm:$src2),
3320 "vcvtps2ph \t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, EVEX;
3323 defm VCVTPH2PSZ : avx512_cvtph2ps<VR512, VR256X, f256mem>, EVEX_V512,
3324 EVEX_CD8<32, CD8VH>;
3325 defm VCVTPS2PHZ : avx512_cvtps2ph<VR256X, VR512, f256mem>, EVEX_V512,
3326 EVEX_CD8<32, CD8VH>;
3328 def : Pat<(v16i16 (int_x86_avx512_mask_vcvtps2ph_512 (v16f32 VR512:$src),
3329 imm:$rc, (bc_v16i16(v8i32 immAllZerosV)), (i16 -1))),
3330 (VCVTPS2PHZrr VR512:$src, imm:$rc)>;
3332 def : Pat<(v16f32 (int_x86_avx512_mask_vcvtph2ps_512 (v16i16 VR256X:$src),
3333 (bc_v16f32(v16i32 immAllZerosV)), (i16 -1), (i32 FROUND_CURRENT))),
3334 (VCVTPH2PSZrr VR256X:$src)>;
3336 let Defs = [EFLAGS], Predicates = [HasAVX512] in {
3337 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
3338 "ucomiss">, PS, EVEX, VEX_LIG,
3339 EVEX_CD8<32, CD8VT1>;
3340 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
3341 "ucomisd">, PD, EVEX,
3342 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3343 let Pattern = []<dag> in {
3344 defm VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, undef, v4f32, f128mem, load,
3345 "comiss">, PS, EVEX, VEX_LIG,
3346 EVEX_CD8<32, CD8VT1>;
3347 defm VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, undef, v2f64, f128mem, load,
3348 "comisd">, PD, EVEX,
3349 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3351 let isCodeGenOnly = 1 in {
3352 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
3353 load, "ucomiss">, PS, EVEX, VEX_LIG,
3354 EVEX_CD8<32, CD8VT1>;
3355 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
3356 load, "ucomisd">, PD, EVEX,
3357 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3359 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
3360 load, "comiss">, PS, EVEX, VEX_LIG,
3361 EVEX_CD8<32, CD8VT1>;
3362 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
3363 load, "comisd">, PD, EVEX,
3364 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3368 /// avx512_fp14_s rcp14ss, rcp14sd, rsqrt14ss, rsqrt14sd
3369 multiclass avx512_fp14_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
3370 X86MemOperand x86memop> {
3371 let hasSideEffects = 0 in {
3372 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3373 (ins RC:$src1, RC:$src2),
3374 !strconcat(OpcodeStr,
3375 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3376 let mayLoad = 1 in {
3377 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3378 (ins RC:$src1, x86memop:$src2),
3379 !strconcat(OpcodeStr,
3380 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3385 defm VRCP14SS : avx512_fp14_s<0x4D, "vrcp14ss", FR32X, f32mem>,
3386 EVEX_CD8<32, CD8VT1>;
3387 defm VRCP14SD : avx512_fp14_s<0x4D, "vrcp14sd", FR64X, f64mem>,
3388 VEX_W, EVEX_CD8<64, CD8VT1>;
3389 defm VRSQRT14SS : avx512_fp14_s<0x4F, "vrsqrt14ss", FR32X, f32mem>,
3390 EVEX_CD8<32, CD8VT1>;
3391 defm VRSQRT14SD : avx512_fp14_s<0x4F, "vrsqrt14sd", FR64X, f64mem>,
3392 VEX_W, EVEX_CD8<64, CD8VT1>;
3394 def : Pat <(v4f32 (int_x86_avx512_rcp14_ss (v4f32 VR128X:$src1),
3395 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
3396 (COPY_TO_REGCLASS (VRCP14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3397 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3399 def : Pat <(v2f64 (int_x86_avx512_rcp14_sd (v2f64 VR128X:$src1),
3400 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
3401 (COPY_TO_REGCLASS (VRCP14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3402 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3404 def : Pat <(v4f32 (int_x86_avx512_rsqrt14_ss (v4f32 VR128X:$src1),
3405 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
3406 (COPY_TO_REGCLASS (VRSQRT14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3407 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3409 def : Pat <(v2f64 (int_x86_avx512_rsqrt14_sd (v2f64 VR128X:$src1),
3410 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
3411 (COPY_TO_REGCLASS (VRSQRT14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3412 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3414 /// avx512_fp14_p rcp14ps, rcp14pd, rsqrt14ps, rsqrt14pd
3415 multiclass avx512_fp14_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3416 RegisterClass RC, X86MemOperand x86memop,
3417 PatFrag mem_frag, ValueType OpVt> {
3418 def r : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3419 !strconcat(OpcodeStr,
3420 " \t{$src, $dst|$dst, $src}"),
3421 [(set RC:$dst, (OpVt (OpNode RC:$src)))]>,
3423 def m : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3424 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3425 [(set RC:$dst, (OpVt (OpNode (mem_frag addr:$src))))]>,
3428 defm VRSQRT14PSZ : avx512_fp14_p<0x4E, "vrsqrt14ps", X86frsqrt, VR512, f512mem,
3429 memopv16f32, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
3430 defm VRSQRT14PDZ : avx512_fp14_p<0x4E, "vrsqrt14pd", X86frsqrt, VR512, f512mem,
3431 memopv8f64, v8f64>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3432 defm VRCP14PSZ : avx512_fp14_p<0x4C, "vrcp14ps", X86frcp, VR512, f512mem,
3433 memopv16f32, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
3434 defm VRCP14PDZ : avx512_fp14_p<0x4C, "vrcp14pd", X86frcp, VR512, f512mem,
3435 memopv8f64, v8f64>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3437 def : Pat <(v16f32 (int_x86_avx512_rsqrt14_ps_512 (v16f32 VR512:$src),
3438 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
3439 (VRSQRT14PSZr VR512:$src)>;
3440 def : Pat <(v8f64 (int_x86_avx512_rsqrt14_pd_512 (v8f64 VR512:$src),
3441 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3442 (VRSQRT14PDZr VR512:$src)>;
3444 def : Pat <(v16f32 (int_x86_avx512_rcp14_ps_512 (v16f32 VR512:$src),
3445 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
3446 (VRCP14PSZr VR512:$src)>;
3447 def : Pat <(v8f64 (int_x86_avx512_rcp14_pd_512 (v8f64 VR512:$src),
3448 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3449 (VRCP14PDZr VR512:$src)>;
3451 /// avx512_fp28_s rcp28ss, rcp28sd, rsqrt28ss, rsqrt28sd
3452 multiclass avx512_fp28_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
3453 X86MemOperand x86memop> {
3454 let hasSideEffects = 0, Predicates = [HasERI] in {
3455 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3456 (ins RC:$src1, RC:$src2),
3457 !strconcat(OpcodeStr,
3458 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3459 def rrb : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3460 (ins RC:$src1, RC:$src2),
3461 !strconcat(OpcodeStr,
3462 " \t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
3463 []>, EVEX_4V, EVEX_B;
3464 let mayLoad = 1 in {
3465 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3466 (ins RC:$src1, x86memop:$src2),
3467 !strconcat(OpcodeStr,
3468 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3473 defm VRCP28SS : avx512_fp28_s<0xCB, "vrcp28ss", FR32X, f32mem>,
3474 EVEX_CD8<32, CD8VT1>;
3475 defm VRCP28SD : avx512_fp28_s<0xCB, "vrcp28sd", FR64X, f64mem>,
3476 VEX_W, EVEX_CD8<64, CD8VT1>;
3477 defm VRSQRT28SS : avx512_fp28_s<0xCD, "vrsqrt28ss", FR32X, f32mem>,
3478 EVEX_CD8<32, CD8VT1>;
3479 defm VRSQRT28SD : avx512_fp28_s<0xCD, "vrsqrt28sd", FR64X, f64mem>,
3480 VEX_W, EVEX_CD8<64, CD8VT1>;
3482 def : Pat <(v4f32 (int_x86_avx512_rcp28_ss (v4f32 VR128X:$src1),
3483 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1),
3485 (COPY_TO_REGCLASS (VRCP28SSrrb (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3486 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3488 def : Pat <(v2f64 (int_x86_avx512_rcp28_sd (v2f64 VR128X:$src1),
3489 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1),
3491 (COPY_TO_REGCLASS (VRCP28SDrrb (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3492 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3494 def : Pat <(v4f32 (int_x86_avx512_rsqrt28_ss (v4f32 VR128X:$src1),
3495 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1),
3497 (COPY_TO_REGCLASS (VRSQRT28SSrrb (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3498 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3500 def : Pat <(v2f64 (int_x86_avx512_rsqrt28_sd (v2f64 VR128X:$src1),
3501 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1),
3503 (COPY_TO_REGCLASS (VRSQRT28SDrrb (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3504 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3506 /// avx512_fp28_p rcp28ps, rcp28pd, rsqrt28ps, rsqrt28pd
3507 multiclass avx512_fp28_p<bits<8> opc, string OpcodeStr,
3508 RegisterClass RC, X86MemOperand x86memop> {
3509 let hasSideEffects = 0, Predicates = [HasERI] in {
3510 def r : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3511 !strconcat(OpcodeStr,
3512 " \t{$src, $dst|$dst, $src}"),
3514 def rb : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3515 !strconcat(OpcodeStr,
3516 " \t{{sae}, $src, $dst|$dst, $src, {sae}}"),
3518 def m : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3519 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3523 defm VRSQRT28PSZ : avx512_fp28_p<0xCC, "vrsqrt28ps", VR512, f512mem>,
3524 EVEX_V512, EVEX_CD8<32, CD8VF>;
3525 defm VRSQRT28PDZ : avx512_fp28_p<0xCC, "vrsqrt28pd", VR512, f512mem>,
3526 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3527 defm VRCP28PSZ : avx512_fp28_p<0xCA, "vrcp28ps", VR512, f512mem>,
3528 EVEX_V512, EVEX_CD8<32, CD8VF>;
3529 defm VRCP28PDZ : avx512_fp28_p<0xCA, "vrcp28pd", VR512, f512mem>,
3530 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3532 def : Pat <(v16f32 (int_x86_avx512_rsqrt28_ps (v16f32 VR512:$src),
3533 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_NO_EXC)),
3534 (VRSQRT28PSZrb VR512:$src)>;
3535 def : Pat <(v8f64 (int_x86_avx512_rsqrt28_pd (v8f64 VR512:$src),
3536 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_NO_EXC)),
3537 (VRSQRT28PDZrb VR512:$src)>;
3539 def : Pat <(v16f32 (int_x86_avx512_rcp28_ps (v16f32 VR512:$src),
3540 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_NO_EXC)),
3541 (VRCP28PSZrb VR512:$src)>;
3542 def : Pat <(v8f64 (int_x86_avx512_rcp28_pd (v8f64 VR512:$src),
3543 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_NO_EXC)),
3544 (VRCP28PDZrb VR512:$src)>;
3546 multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
3547 Intrinsic V16F32Int, Intrinsic V8F64Int,
3548 OpndItins itins_s, OpndItins itins_d> {
3549 def PSZrr :AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3550 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3551 [(set VR512:$dst, (v16f32 (OpNode VR512:$src)))], itins_s.rr>,
3555 def PSZrm : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3556 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3558 (OpNode (v16f32 (bitconvert (memopv16f32 addr:$src)))))],
3559 itins_s.rm>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
3561 def PDZrr : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3562 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3563 [(set VR512:$dst, (v8f64 (OpNode VR512:$src)))], itins_d.rr>,
3567 def PDZrm : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3568 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3569 [(set VR512:$dst, (OpNode
3570 (v8f64 (bitconvert (memopv16f32 addr:$src)))))],
3571 itins_d.rm>, EVEX, EVEX_V512, EVEX_CD8<64, CD8VF>;
3573 let isCodeGenOnly = 1 in {
3574 def PSZr_Int : AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3575 !strconcat(OpcodeStr,
3576 "ps\t{$src, $dst|$dst, $src}"),
3577 [(set VR512:$dst, (V16F32Int VR512:$src))]>,
3579 def PSZm_Int : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3580 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3582 (V16F32Int (memopv16f32 addr:$src)))]>, EVEX,
3583 EVEX_V512, EVEX_CD8<32, CD8VF>;
3584 def PDZr_Int : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3585 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3586 [(set VR512:$dst, (V8F64Int VR512:$src))]>,
3587 EVEX, EVEX_V512, VEX_W;
3588 def PDZm_Int : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3589 !strconcat(OpcodeStr,
3590 "pd\t{$src, $dst|$dst, $src}"),
3591 [(set VR512:$dst, (V8F64Int (memopv8f64 addr:$src)))]>,
3592 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3593 } // isCodeGenOnly = 1
3596 multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,
3597 Intrinsic F32Int, Intrinsic F64Int,
3598 OpndItins itins_s, OpndItins itins_d> {
3599 def SSZr : SI<opc, MRMSrcReg, (outs FR32X:$dst),
3600 (ins FR32X:$src1, FR32X:$src2),
3601 !strconcat(OpcodeStr,
3602 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3603 [], itins_s.rr>, XS, EVEX_4V;
3604 let isCodeGenOnly = 1 in
3605 def SSZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
3606 (ins VR128X:$src1, VR128X:$src2),
3607 !strconcat(OpcodeStr,
3608 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3610 (F32Int VR128X:$src1, VR128X:$src2))],
3611 itins_s.rr>, XS, EVEX_4V;
3612 let mayLoad = 1 in {
3613 def SSZm : SI<opc, MRMSrcMem, (outs FR32X:$dst),
3614 (ins FR32X:$src1, f32mem:$src2),
3615 !strconcat(OpcodeStr,
3616 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3617 [], itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
3618 let isCodeGenOnly = 1 in
3619 def SSZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
3620 (ins VR128X:$src1, ssmem:$src2),
3621 !strconcat(OpcodeStr,
3622 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3624 (F32Int VR128X:$src1, sse_load_f32:$src2))],
3625 itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
3627 def SDZr : SI<opc, MRMSrcReg, (outs FR64X:$dst),
3628 (ins FR64X:$src1, FR64X:$src2),
3629 !strconcat(OpcodeStr,
3630 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
3632 let isCodeGenOnly = 1 in
3633 def SDZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
3634 (ins VR128X:$src1, VR128X:$src2),
3635 !strconcat(OpcodeStr,
3636 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3638 (F64Int VR128X:$src1, VR128X:$src2))],
3639 itins_s.rr>, XD, EVEX_4V, VEX_W;
3640 let mayLoad = 1 in {
3641 def SDZm : SI<opc, MRMSrcMem, (outs FR64X:$dst),
3642 (ins FR64X:$src1, f64mem:$src2),
3643 !strconcat(OpcodeStr,
3644 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
3645 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
3646 let isCodeGenOnly = 1 in
3647 def SDZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
3648 (ins VR128X:$src1, sdmem:$src2),
3649 !strconcat(OpcodeStr,
3650 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3652 (F64Int VR128X:$src1, sse_load_f64:$src2))]>,
3653 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
3658 defm VSQRT : avx512_sqrt_scalar<0x51, "sqrt",
3659 int_x86_avx512_sqrt_ss, int_x86_avx512_sqrt_sd,
3660 SSE_SQRTSS, SSE_SQRTSD>,
3661 avx512_sqrt_packed<0x51, "vsqrt", fsqrt,
3662 int_x86_avx512_sqrt_ps_512, int_x86_avx512_sqrt_pd_512,
3663 SSE_SQRTPS, SSE_SQRTPD>;
3665 let Predicates = [HasAVX512] in {
3666 def : Pat<(f32 (fsqrt FR32X:$src)),
3667 (VSQRTSSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3668 def : Pat<(f32 (fsqrt (load addr:$src))),
3669 (VSQRTSSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
3670 Requires<[OptForSize]>;
3671 def : Pat<(f64 (fsqrt FR64X:$src)),
3672 (VSQRTSDZr (f64 (IMPLICIT_DEF)), FR64X:$src)>;
3673 def : Pat<(f64 (fsqrt (load addr:$src))),
3674 (VSQRTSDZm (f64 (IMPLICIT_DEF)), addr:$src)>,
3675 Requires<[OptForSize]>;
3677 def : Pat<(f32 (X86frsqrt FR32X:$src)),
3678 (VRSQRT14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3679 def : Pat<(f32 (X86frsqrt (load addr:$src))),
3680 (VRSQRT14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
3681 Requires<[OptForSize]>;
3683 def : Pat<(f32 (X86frcp FR32X:$src)),
3684 (VRCP14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3685 def : Pat<(f32 (X86frcp (load addr:$src))),
3686 (VRCP14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
3687 Requires<[OptForSize]>;
3689 def : Pat<(int_x86_sse_sqrt_ss VR128X:$src),
3690 (COPY_TO_REGCLASS (VSQRTSSZr (f32 (IMPLICIT_DEF)),
3691 (COPY_TO_REGCLASS VR128X:$src, FR32)),
3693 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
3694 (VSQRTSSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3696 def : Pat<(int_x86_sse2_sqrt_sd VR128X:$src),
3697 (COPY_TO_REGCLASS (VSQRTSDZr (f64 (IMPLICIT_DEF)),
3698 (COPY_TO_REGCLASS VR128X:$src, FR64)),
3700 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
3701 (VSQRTSDZm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
3705 multiclass avx512_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
3706 X86MemOperand x86memop, RegisterClass RC,
3707 PatFrag mem_frag32, PatFrag mem_frag64,
3708 Intrinsic V4F32Int, Intrinsic V2F64Int,
3710 let ExeDomain = SSEPackedSingle in {
3711 // Intrinsic operation, reg.
3712 // Vector intrinsic operation, reg
3713 def PSr : AVX512AIi8<opcps, MRMSrcReg,
3714 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
3715 !strconcat(OpcodeStr,
3716 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3717 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>;
3719 // Vector intrinsic operation, mem
3720 def PSm : AVX512AIi8<opcps, MRMSrcMem,
3721 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
3722 !strconcat(OpcodeStr,
3723 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3725 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
3726 EVEX_CD8<32, VForm>;
3727 } // ExeDomain = SSEPackedSingle
3729 let ExeDomain = SSEPackedDouble in {
3730 // Vector intrinsic operation, reg
3731 def PDr : AVX512AIi8<opcpd, MRMSrcReg,
3732 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
3733 !strconcat(OpcodeStr,
3734 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3735 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>;
3737 // Vector intrinsic operation, mem
3738 def PDm : AVX512AIi8<opcpd, MRMSrcMem,
3739 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
3740 !strconcat(OpcodeStr,
3741 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3743 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
3744 EVEX_CD8<64, VForm>;
3745 } // ExeDomain = SSEPackedDouble
3748 multiclass avx512_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
3752 let ExeDomain = GenericDomain in {
3754 let hasSideEffects = 0 in
3755 def SSr : AVX512AIi8<opcss, MRMSrcReg,
3756 (outs FR32X:$dst), (ins FR32X:$src1, FR32X:$src2, i32i8imm:$src3),
3757 !strconcat(OpcodeStr,
3758 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3761 // Intrinsic operation, reg.
3762 let isCodeGenOnly = 1 in
3763 def SSr_Int : AVX512AIi8<opcss, MRMSrcReg,
3764 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
3765 !strconcat(OpcodeStr,
3766 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3767 [(set VR128X:$dst, (F32Int VR128X:$src1, VR128X:$src2, imm:$src3))]>;
3769 // Intrinsic operation, mem.
3770 def SSm : AVX512AIi8<opcss, MRMSrcMem, (outs VR128X:$dst),
3771 (ins VR128X:$src1, ssmem:$src2, i32i8imm:$src3),
3772 !strconcat(OpcodeStr,
3773 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3774 [(set VR128X:$dst, (F32Int VR128X:$src1,
3775 sse_load_f32:$src2, imm:$src3))]>,
3776 EVEX_CD8<32, CD8VT1>;
3779 let hasSideEffects = 0 in
3780 def SDr : AVX512AIi8<opcsd, MRMSrcReg,
3781 (outs FR64X:$dst), (ins FR64X:$src1, FR64X:$src2, i32i8imm:$src3),
3782 !strconcat(OpcodeStr,
3783 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3786 // Intrinsic operation, reg.
3787 let isCodeGenOnly = 1 in
3788 def SDr_Int : AVX512AIi8<opcsd, MRMSrcReg,
3789 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
3790 !strconcat(OpcodeStr,
3791 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3792 [(set VR128X:$dst, (F64Int VR128X:$src1, VR128X:$src2, imm:$src3))]>,
3795 // Intrinsic operation, mem.
3796 def SDm : AVX512AIi8<opcsd, MRMSrcMem,
3797 (outs VR128X:$dst), (ins VR128X:$src1, sdmem:$src2, i32i8imm:$src3),
3798 !strconcat(OpcodeStr,
3799 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3801 (F64Int VR128X:$src1, sse_load_f64:$src2, imm:$src3))]>,
3802 VEX_W, EVEX_CD8<64, CD8VT1>;
3803 } // ExeDomain = GenericDomain
3806 multiclass avx512_rndscale<bits<8> opc, string OpcodeStr,
3807 X86MemOperand x86memop, RegisterClass RC,
3808 PatFrag mem_frag, Domain d> {
3809 let ExeDomain = d in {
3810 // Intrinsic operation, reg.
3811 // Vector intrinsic operation, reg
3812 def r : AVX512AIi8<opc, MRMSrcReg,
3813 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
3814 !strconcat(OpcodeStr,
3815 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3818 // Vector intrinsic operation, mem
3819 def m : AVX512AIi8<opc, MRMSrcMem,
3820 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
3821 !strconcat(OpcodeStr,
3822 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3828 defm VRNDSCALEPSZ : avx512_rndscale<0x08, "vrndscaleps", f512mem, VR512,
3829 memopv16f32, SSEPackedSingle>, EVEX_V512,
3830 EVEX_CD8<32, CD8VF>;
3832 def : Pat<(v16f32 (int_x86_avx512_mask_rndscale_ps_512 (v16f32 VR512:$src1),
3833 imm:$src2, (v16f32 VR512:$src1), (i16 -1),
3835 (VRNDSCALEPSZr VR512:$src1, imm:$src2)>;
3838 defm VRNDSCALEPDZ : avx512_rndscale<0x09, "vrndscalepd", f512mem, VR512,
3839 memopv8f64, SSEPackedDouble>, EVEX_V512,
3840 VEX_W, EVEX_CD8<64, CD8VF>;
3842 def : Pat<(v8f64 (int_x86_avx512_mask_rndscale_pd_512 (v8f64 VR512:$src1),
3843 imm:$src2, (v8f64 VR512:$src1), (i8 -1),
3845 (VRNDSCALEPDZr VR512:$src1, imm:$src2)>;
3847 multiclass avx512_rndscale_scalar<bits<8> opc, string OpcodeStr,
3848 Operand x86memop, RegisterClass RC, Domain d> {
3849 let ExeDomain = d in {
3850 def r : AVX512AIi8<opc, MRMSrcReg,
3851 (outs RC:$dst), (ins RC:$src1, RC:$src2, i32i8imm:$src3),
3852 !strconcat(OpcodeStr,
3853 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3856 def m : AVX512AIi8<opc, MRMSrcMem,
3857 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i32i8imm:$src3),
3858 !strconcat(OpcodeStr,
3859 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3864 defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", ssmem, FR32X,
3865 SSEPackedSingle>, EVEX_CD8<32, CD8VT1>;
3867 defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", sdmem, FR64X,
3868 SSEPackedDouble>, EVEX_CD8<64, CD8VT1>;
3870 def : Pat<(ffloor FR32X:$src),
3871 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x1))>;
3872 def : Pat<(f64 (ffloor FR64X:$src)),
3873 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x1))>;
3874 def : Pat<(f32 (fnearbyint FR32X:$src)),
3875 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0xC))>;
3876 def : Pat<(f64 (fnearbyint FR64X:$src)),
3877 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0xC))>;
3878 def : Pat<(f32 (fceil FR32X:$src)),
3879 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x2))>;
3880 def : Pat<(f64 (fceil FR64X:$src)),
3881 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x2))>;
3882 def : Pat<(f32 (frint FR32X:$src)),
3883 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x4))>;
3884 def : Pat<(f64 (frint FR64X:$src)),
3885 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x4))>;
3886 def : Pat<(f32 (ftrunc FR32X:$src)),
3887 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x3))>;
3888 def : Pat<(f64 (ftrunc FR64X:$src)),
3889 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x3))>;
3891 def : Pat<(v16f32 (ffloor VR512:$src)),
3892 (VRNDSCALEPSZr VR512:$src, (i32 0x1))>;
3893 def : Pat<(v16f32 (fnearbyint VR512:$src)),
3894 (VRNDSCALEPSZr VR512:$src, (i32 0xC))>;
3895 def : Pat<(v16f32 (fceil VR512:$src)),
3896 (VRNDSCALEPSZr VR512:$src, (i32 0x2))>;
3897 def : Pat<(v16f32 (frint VR512:$src)),
3898 (VRNDSCALEPSZr VR512:$src, (i32 0x4))>;
3899 def : Pat<(v16f32 (ftrunc VR512:$src)),
3900 (VRNDSCALEPSZr VR512:$src, (i32 0x3))>;
3902 def : Pat<(v8f64 (ffloor VR512:$src)),
3903 (VRNDSCALEPDZr VR512:$src, (i32 0x1))>;
3904 def : Pat<(v8f64 (fnearbyint VR512:$src)),
3905 (VRNDSCALEPDZr VR512:$src, (i32 0xC))>;
3906 def : Pat<(v8f64 (fceil VR512:$src)),
3907 (VRNDSCALEPDZr VR512:$src, (i32 0x2))>;
3908 def : Pat<(v8f64 (frint VR512:$src)),
3909 (VRNDSCALEPDZr VR512:$src, (i32 0x4))>;
3910 def : Pat<(v8f64 (ftrunc VR512:$src)),
3911 (VRNDSCALEPDZr VR512:$src, (i32 0x3))>;
3913 //-------------------------------------------------
3914 // Integer truncate and extend operations
3915 //-------------------------------------------------
3917 multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr,
3918 RegisterClass dstRC, RegisterClass srcRC,
3919 RegisterClass KRC, X86MemOperand x86memop> {
3920 def rr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
3922 !strconcat(OpcodeStr," \t{$src, $dst|$dst, $src}"),
3925 def rrk : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
3926 (ins KRC:$mask, srcRC:$src),
3927 !strconcat(OpcodeStr,
3928 " \t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
3931 def rrkz : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
3932 (ins KRC:$mask, srcRC:$src),
3933 !strconcat(OpcodeStr,
3934 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
3937 def mr : AVX512XS8I<opc, MRMDestMem, (outs), (ins x86memop:$dst, srcRC:$src),
3938 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3941 def mrk : AVX512XS8I<opc, MRMDestMem, (outs),
3942 (ins x86memop:$dst, KRC:$mask, srcRC:$src),
3943 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}}|${dst} {${mask}}, $src}"),
3947 defm VPMOVQB : avx512_trunc_sat<0x32, "vpmovqb", VR128X, VR512, VK8WM,
3948 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3949 defm VPMOVSQB : avx512_trunc_sat<0x22, "vpmovsqb", VR128X, VR512, VK8WM,
3950 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3951 defm VPMOVUSQB : avx512_trunc_sat<0x12, "vpmovusqb", VR128X, VR512, VK8WM,
3952 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3953 defm VPMOVQW : avx512_trunc_sat<0x34, "vpmovqw", VR128X, VR512, VK8WM,
3954 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3955 defm VPMOVSQW : avx512_trunc_sat<0x24, "vpmovsqw", VR128X, VR512, VK8WM,
3956 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3957 defm VPMOVUSQW : avx512_trunc_sat<0x14, "vpmovusqw", VR128X, VR512, VK8WM,
3958 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3959 defm VPMOVQD : avx512_trunc_sat<0x35, "vpmovqd", VR256X, VR512, VK8WM,
3960 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3961 defm VPMOVSQD : avx512_trunc_sat<0x25, "vpmovsqd", VR256X, VR512, VK8WM,
3962 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3963 defm VPMOVUSQD : avx512_trunc_sat<0x15, "vpmovusqd", VR256X, VR512, VK8WM,
3964 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3965 defm VPMOVDW : avx512_trunc_sat<0x33, "vpmovdw", VR256X, VR512, VK16WM,
3966 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3967 defm VPMOVSDW : avx512_trunc_sat<0x23, "vpmovsdw", VR256X, VR512, VK16WM,
3968 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3969 defm VPMOVUSDW : avx512_trunc_sat<0x13, "vpmovusdw", VR256X, VR512, VK16WM,
3970 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3971 defm VPMOVDB : avx512_trunc_sat<0x31, "vpmovdb", VR128X, VR512, VK16WM,
3972 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3973 defm VPMOVSDB : avx512_trunc_sat<0x21, "vpmovsdb", VR128X, VR512, VK16WM,
3974 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3975 defm VPMOVUSDB : avx512_trunc_sat<0x11, "vpmovusdb", VR128X, VR512, VK16WM,
3976 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3978 def : Pat<(v16i8 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQBrr VR512:$src)>;
3979 def : Pat<(v8i16 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQWrr VR512:$src)>;
3980 def : Pat<(v16i16 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDWrr VR512:$src)>;
3981 def : Pat<(v16i8 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDBrr VR512:$src)>;
3982 def : Pat<(v8i32 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQDrr VR512:$src)>;
3984 def : Pat<(v16i8 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
3985 (VPMOVDBrrkz VK16WM:$mask, VR512:$src)>;
3986 def : Pat<(v16i16 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
3987 (VPMOVDWrrkz VK16WM:$mask, VR512:$src)>;
3988 def : Pat<(v8i16 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
3989 (VPMOVQWrrkz VK8WM:$mask, VR512:$src)>;
3990 def : Pat<(v8i32 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
3991 (VPMOVQDrrkz VK8WM:$mask, VR512:$src)>;
3994 multiclass avx512_extend<bits<8> opc, string OpcodeStr, RegisterClass KRC,
3995 RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode,
3996 PatFrag mem_frag, X86MemOperand x86memop,
3997 ValueType OpVT, ValueType InVT> {
3999 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4001 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4002 [(set DstRC:$dst, (OpVT (OpNode (InVT SrcRC:$src))))]>, EVEX;
4004 def rrk : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4005 (ins KRC:$mask, SrcRC:$src),
4006 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
4009 def rrkz : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4010 (ins KRC:$mask, SrcRC:$src),
4011 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4014 let mayLoad = 1 in {
4015 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4016 (ins x86memop:$src),
4017 !strconcat(OpcodeStr," \t{$src, $dst|$dst, $src}"),
4019 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))]>,
4022 def rmk : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4023 (ins KRC:$mask, x86memop:$src),
4024 !strconcat(OpcodeStr," \t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
4028 def rmkz : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4029 (ins KRC:$mask, x86memop:$src),
4030 !strconcat(OpcodeStr," \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4036 defm VPMOVZXBDZ: avx512_extend<0x31, "vpmovzxbd", VK16WM, VR512, VR128X, X86vzext,
4037 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
4039 defm VPMOVZXBQZ: avx512_extend<0x32, "vpmovzxbq", VK8WM, VR512, VR128X, X86vzext,
4040 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
4042 defm VPMOVZXWDZ: avx512_extend<0x33, "vpmovzxwd", VK16WM, VR512, VR256X, X86vzext,
4043 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
4044 EVEX_CD8<16, CD8VH>;
4045 defm VPMOVZXWQZ: avx512_extend<0x34, "vpmovzxwq", VK8WM, VR512, VR128X, X86vzext,
4046 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
4047 EVEX_CD8<16, CD8VQ>;
4048 defm VPMOVZXDQZ: avx512_extend<0x35, "vpmovzxdq", VK8WM, VR512, VR256X, X86vzext,
4049 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
4050 EVEX_CD8<32, CD8VH>;
4052 defm VPMOVSXBDZ: avx512_extend<0x21, "vpmovsxbd", VK16WM, VR512, VR128X, X86vsext,
4053 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
4055 defm VPMOVSXBQZ: avx512_extend<0x22, "vpmovsxbq", VK8WM, VR512, VR128X, X86vsext,
4056 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
4058 defm VPMOVSXWDZ: avx512_extend<0x23, "vpmovsxwd", VK16WM, VR512, VR256X, X86vsext,
4059 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
4060 EVEX_CD8<16, CD8VH>;
4061 defm VPMOVSXWQZ: avx512_extend<0x24, "vpmovsxwq", VK8WM, VR512, VR128X, X86vsext,
4062 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
4063 EVEX_CD8<16, CD8VQ>;
4064 defm VPMOVSXDQZ: avx512_extend<0x25, "vpmovsxdq", VK8WM, VR512, VR256X, X86vsext,
4065 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
4066 EVEX_CD8<32, CD8VH>;
4068 //===----------------------------------------------------------------------===//
4069 // GATHER - SCATTER Operations
4071 multiclass avx512_gather<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4072 RegisterClass RC, X86MemOperand memop> {
4074 Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb" in
4075 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst, KRC:$mask_wb),
4076 (ins RC:$src1, KRC:$mask, memop:$src2),
4077 !strconcat(OpcodeStr,
4078 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4082 let ExeDomain = SSEPackedDouble in {
4083 defm VGATHERDPDZ : avx512_gather<0x92, "vgatherdpd", VK8WM, VR512, vy64xmem>,
4084 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4085 defm VGATHERQPDZ : avx512_gather<0x93, "vgatherqpd", VK8WM, VR512, vz64mem>,
4086 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4089 let ExeDomain = SSEPackedSingle in {
4090 defm VGATHERDPSZ : avx512_gather<0x92, "vgatherdps", VK16WM, VR512, vz32mem>,
4091 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4092 defm VGATHERQPSZ : avx512_gather<0x93, "vgatherqps", VK8WM, VR256X, vz64mem>,
4093 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4096 defm VPGATHERDQZ : avx512_gather<0x90, "vpgatherdq", VK8WM, VR512, vy64xmem>,
4097 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4098 defm VPGATHERDDZ : avx512_gather<0x90, "vpgatherdd", VK16WM, VR512, vz32mem>,
4099 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4101 defm VPGATHERQQZ : avx512_gather<0x91, "vpgatherqq", VK8WM, VR512, vz64mem>,
4102 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4103 defm VPGATHERQDZ : avx512_gather<0x91, "vpgatherqd", VK8WM, VR256X, vz64mem>,
4104 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4106 multiclass avx512_scatter<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4107 RegisterClass RC, X86MemOperand memop> {
4108 let mayStore = 1, Constraints = "$mask = $mask_wb" in
4109 def mr : AVX5128I<opc, MRMDestMem, (outs KRC:$mask_wb),
4110 (ins memop:$dst, KRC:$mask, RC:$src2),
4111 !strconcat(OpcodeStr,
4112 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4116 let ExeDomain = SSEPackedDouble in {
4117 defm VSCATTERDPDZ : avx512_scatter<0xA2, "vscatterdpd", VK8WM, VR512, vy64xmem>,
4118 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4119 defm VSCATTERQPDZ : avx512_scatter<0xA3, "vscatterqpd", VK8WM, VR512, vz64mem>,
4120 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4123 let ExeDomain = SSEPackedSingle in {
4124 defm VSCATTERDPSZ : avx512_scatter<0xA2, "vscatterdps", VK16WM, VR512, vz32mem>,
4125 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4126 defm VSCATTERQPSZ : avx512_scatter<0xA3, "vscatterqps", VK8WM, VR256X, vz64mem>,
4127 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4130 defm VPSCATTERDQZ : avx512_scatter<0xA0, "vpscatterdq", VK8WM, VR512, vy64xmem>,
4131 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4132 defm VPSCATTERDDZ : avx512_scatter<0xA0, "vpscatterdd", VK16WM, VR512, vz32mem>,
4133 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4135 defm VPSCATTERQQZ : avx512_scatter<0xA1, "vpscatterqq", VK8WM, VR512, vz64mem>,
4136 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4137 defm VPSCATTERQDZ : avx512_scatter<0xA1, "vpscatterqd", VK8WM, VR256X, vz64mem>,
4138 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4141 multiclass avx512_gather_scatter_prefetch<bits<8> opc, Format F, string OpcodeStr,
4142 RegisterClass KRC, X86MemOperand memop> {
4143 let Predicates = [HasPFI], hasSideEffects = 1 in
4144 def m : AVX5128I<opc, F, (outs), (ins KRC:$mask, memop:$src),
4145 !strconcat(OpcodeStr, " \t{$src {${mask}}|{${mask}}, $src}"),
4149 defm VGATHERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dps",
4150 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4152 defm VGATHERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qps",
4153 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4155 defm VGATHERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dpd",
4156 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4158 defm VGATHERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qpd",
4159 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4161 defm VGATHERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dps",
4162 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4164 defm VGATHERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qps",
4165 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4167 defm VGATHERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dpd",
4168 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4170 defm VGATHERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qpd",
4171 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4173 defm VSCATTERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dps",
4174 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4176 defm VSCATTERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qps",
4177 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4179 defm VSCATTERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dpd",
4180 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4182 defm VSCATTERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qpd",
4183 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4185 defm VSCATTERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dps",
4186 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4188 defm VSCATTERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qps",
4189 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4191 defm VSCATTERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dpd",
4192 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4194 defm VSCATTERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qpd",
4195 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4196 //===----------------------------------------------------------------------===//
4197 // VSHUFPS - VSHUFPD Operations
4199 multiclass avx512_shufp<RegisterClass RC, X86MemOperand x86memop,
4200 ValueType vt, string OpcodeStr, PatFrag mem_frag,
4202 def rmi : AVX512PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
4203 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
4204 !strconcat(OpcodeStr,
4205 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4206 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
4207 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
4208 EVEX_4V, Sched<[WriteShuffleLd, ReadAfterLd]>;
4209 def rri : AVX512PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
4210 (ins RC:$src1, RC:$src2, i8imm:$src3),
4211 !strconcat(OpcodeStr,
4212 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4213 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
4214 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
4215 EVEX_4V, Sched<[WriteShuffle]>;
4218 defm VSHUFPSZ : avx512_shufp<VR512, f512mem, v16f32, "vshufps", memopv16f32,
4219 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
4220 defm VSHUFPDZ : avx512_shufp<VR512, f512mem, v8f64, "vshufpd", memopv8f64,
4221 SSEPackedDouble>, PD, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4223 def : Pat<(v16i32 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4224 (VSHUFPSZrri VR512:$src1, VR512:$src2, imm:$imm)>;
4225 def : Pat<(v16i32 (X86Shufp VR512:$src1,
4226 (memopv16i32 addr:$src2), (i8 imm:$imm))),
4227 (VSHUFPSZrmi VR512:$src1, addr:$src2, imm:$imm)>;
4229 def : Pat<(v8i64 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4230 (VSHUFPDZrri VR512:$src1, VR512:$src2, imm:$imm)>;
4231 def : Pat<(v8i64 (X86Shufp VR512:$src1,
4232 (memopv8i64 addr:$src2), (i8 imm:$imm))),
4233 (VSHUFPDZrmi VR512:$src1, addr:$src2, imm:$imm)>;
4235 multiclass avx512_alignr<string OpcodeStr, RegisterClass RC,
4236 X86MemOperand x86memop> {
4237 def rri : AVX512AIi8<0x03, MRMSrcReg, (outs RC:$dst),
4238 (ins RC:$src1, RC:$src2, i8imm:$src3),
4239 !strconcat(OpcodeStr,
4240 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4243 def rmi : AVX512AIi8<0x03, MRMSrcMem, (outs RC:$dst),
4244 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
4245 !strconcat(OpcodeStr,
4246 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4249 defm VALIGND : avx512_alignr<"valignd", VR512, i512mem>,
4250 EVEX_V512, EVEX_CD8<32, CD8VF>;
4251 defm VALIGNQ : avx512_alignr<"valignq", VR512, i512mem>,
4252 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4254 def : Pat<(v16f32 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4255 (VALIGNDrri VR512:$src2, VR512:$src1, imm:$imm)>;
4256 def : Pat<(v8f64 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4257 (VALIGNQrri VR512:$src2, VR512:$src1, imm:$imm)>;
4258 def : Pat<(v16i32 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4259 (VALIGNDrri VR512:$src2, VR512:$src1, imm:$imm)>;
4260 def : Pat<(v8i64 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4261 (VALIGNQrri VR512:$src2, VR512:$src1, imm:$imm)>;
4263 // Helper fragments to match sext vXi1 to vXiY.
4264 def v16i1sextv16i32 : PatLeaf<(v16i32 (X86vsrai VR512:$src, (i8 31)))>;
4265 def v8i1sextv8i64 : PatLeaf<(v8i64 (X86vsrai VR512:$src, (i8 63)))>;
4267 multiclass avx512_vpabs<bits<8> opc, string OpcodeStr, ValueType OpVT,
4268 RegisterClass KRC, RegisterClass RC,
4269 X86MemOperand x86memop, X86MemOperand x86scalar_mop,
4271 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4272 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4274 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
4275 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
4277 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
4278 !strconcat(OpcodeStr,
4279 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4281 let mayLoad = 1 in {
4282 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4283 (ins x86memop:$src),
4284 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4286 def rmk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4287 (ins KRC:$mask, x86memop:$src),
4288 !strconcat(OpcodeStr,
4289 " \t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
4291 def rmkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4292 (ins KRC:$mask, x86memop:$src),
4293 !strconcat(OpcodeStr,
4294 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4296 def rmb : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4297 (ins x86scalar_mop:$src),
4298 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4299 ", $dst|$dst, ${src}", BrdcstStr, "}"),
4301 def rmbk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4302 (ins KRC:$mask, x86scalar_mop:$src),
4303 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4304 ", $dst {${mask}}|$dst {${mask}}, ${src}", BrdcstStr, "}"),
4305 []>, EVEX, EVEX_B, EVEX_K;
4306 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4307 (ins KRC:$mask, x86scalar_mop:$src),
4308 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4309 ", $dst {${mask}} {z}|$dst {${mask}} {z}, ${src}",
4311 []>, EVEX, EVEX_B, EVEX_KZ;
4315 defm VPABSDZ : avx512_vpabs<0x1E, "vpabsd", v16i32, VK16WM, VR512,
4316 i512mem, i32mem, "{1to16}">, EVEX_V512,
4317 EVEX_CD8<32, CD8VF>;
4318 defm VPABSQZ : avx512_vpabs<0x1F, "vpabsq", v8i64, VK8WM, VR512,
4319 i512mem, i64mem, "{1to8}">, EVEX_V512, VEX_W,
4320 EVEX_CD8<64, CD8VF>;
4323 (bc_v16i32 (v16i1sextv16i32)),
4324 (bc_v16i32 (add (v16i32 VR512:$src), (v16i1sextv16i32)))),
4325 (VPABSDZrr VR512:$src)>;
4327 (bc_v8i64 (v8i1sextv8i64)),
4328 (bc_v8i64 (add (v8i64 VR512:$src), (v8i1sextv8i64)))),
4329 (VPABSQZrr VR512:$src)>;
4331 def : Pat<(v16i32 (int_x86_avx512_mask_pabs_d_512 (v16i32 VR512:$src),
4332 (v16i32 immAllZerosV), (i16 -1))),
4333 (VPABSDZrr VR512:$src)>;
4334 def : Pat<(v8i64 (int_x86_avx512_mask_pabs_q_512 (v8i64 VR512:$src),
4335 (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
4336 (VPABSQZrr VR512:$src)>;
4338 multiclass avx512_conflict<bits<8> opc, string OpcodeStr,
4339 RegisterClass RC, RegisterClass KRC,
4340 X86MemOperand x86memop,
4341 X86MemOperand x86scalar_mop, string BrdcstStr> {
4342 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4344 !strconcat(OpcodeStr, " \t{$src, ${dst} |${dst}, $src}"),
4346 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4347 (ins x86memop:$src),
4348 !strconcat(OpcodeStr, " \t{$src, ${dst}|${dst}, $src}"),
4350 def rmb : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4351 (ins x86scalar_mop:$src),
4352 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4353 ", ${dst}|${dst}, ${src}", BrdcstStr, "}"),
4355 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4356 (ins KRC:$mask, RC:$src),
4357 !strconcat(OpcodeStr,
4358 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
4360 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4361 (ins KRC:$mask, x86memop:$src),
4362 !strconcat(OpcodeStr,
4363 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
4365 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4366 (ins KRC:$mask, x86scalar_mop:$src),
4367 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4368 ", ${dst} {${mask}} {z}|${dst} {${mask}} {z}, ${src}",
4370 []>, EVEX, EVEX_KZ, EVEX_B;
4372 let Constraints = "$src1 = $dst" in {
4373 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4374 (ins RC:$src1, KRC:$mask, RC:$src2),
4375 !strconcat(OpcodeStr,
4376 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4378 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4379 (ins RC:$src1, KRC:$mask, x86memop:$src2),
4380 !strconcat(OpcodeStr,
4381 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4383 def rmbk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4384 (ins RC:$src1, KRC:$mask, x86scalar_mop:$src2),
4385 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
4386 ", ${dst} {${mask}}|${dst} {${mask}}, ${src2}", BrdcstStr, "}"),
4387 []>, EVEX, EVEX_K, EVEX_B;
4391 let Predicates = [HasCDI] in {
4392 defm VPCONFLICTD : avx512_conflict<0xC4, "vpconflictd", VR512, VK16WM,
4393 i512mem, i32mem, "{1to16}">,
4394 EVEX_V512, EVEX_CD8<32, CD8VF>;
4397 defm VPCONFLICTQ : avx512_conflict<0xC4, "vpconflictq", VR512, VK8WM,
4398 i512mem, i64mem, "{1to8}">,
4399 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
4403 def : Pat<(int_x86_avx512_mask_conflict_d_512 VR512:$src2, VR512:$src1,
4405 (VPCONFLICTDrrk VR512:$src1,
4406 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
4408 def : Pat<(int_x86_avx512_mask_conflict_q_512 VR512:$src2, VR512:$src1,
4410 (VPCONFLICTQrrk VR512:$src1,
4411 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
4413 let Predicates = [HasCDI] in {
4414 defm VPLZCNTD : avx512_conflict<0x44, "vplzcntd", VR512, VK16WM,
4415 i512mem, i32mem, "{1to16}">,
4416 EVEX_V512, EVEX_CD8<32, CD8VF>;
4419 defm VPLZCNTQ : avx512_conflict<0x44, "vplzcntq", VR512, VK8WM,
4420 i512mem, i64mem, "{1to8}">,
4421 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
4425 def : Pat<(int_x86_avx512_mask_lzcnt_d_512 VR512:$src2, VR512:$src1,
4427 (VPLZCNTDrrk VR512:$src1,
4428 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
4430 def : Pat<(int_x86_avx512_mask_lzcnt_q_512 VR512:$src2, VR512:$src1,
4432 (VPLZCNTQrrk VR512:$src1,
4433 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
4435 def : Pat<(v16i32 (ctlz (memopv16i32 addr:$src))),
4436 (VPLZCNTDrm addr:$src)>;
4437 def : Pat<(v16i32 (ctlz (v16i32 VR512:$src))),
4438 (VPLZCNTDrr VR512:$src)>;
4439 def : Pat<(v8i64 (ctlz (memopv8i64 addr:$src))),
4440 (VPLZCNTQrm addr:$src)>;
4441 def : Pat<(v8i64 (ctlz (v8i64 VR512:$src))),
4442 (VPLZCNTQrr VR512:$src)>;
4444 def : Pat<(store (i1 -1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
4445 def : Pat<(store (i1 1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
4446 def : Pat<(store (i1 0), addr:$dst), (MOV8mi addr:$dst, (i8 0))>;
4448 def : Pat<(store VK1:$src, addr:$dst),
4449 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK1:$src, VK16))>;
4451 def truncstorei1 : PatFrag<(ops node:$val, node:$ptr),
4452 (truncstore node:$val, node:$ptr), [{
4453 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
4456 def : Pat<(truncstorei1 GR8:$src, addr:$dst),
4457 (MOV8mr addr:$dst, GR8:$src)>;