1 // Group template arguments that can be derived from the vector type (EltNum x
2 // EltVT). These are things like the register class for the writemask, etc.
3 // The idea is to pass one of these as the template argument rather than the
4 // individual arguments.
5 // The template is also used for scalar types, in this case numelts is 1.
6 class X86VectorVTInfo<int numelts, ValueType eltvt, RegisterClass rc,
9 ValueType EltVT = eltvt;
10 int NumElts = numelts;
12 // Corresponding mask register class.
13 RegisterClass KRC = !cast<RegisterClass>("VK" # NumElts);
15 // Corresponding write-mask register class.
16 RegisterClass KRCWM = !cast<RegisterClass>("VK" # NumElts # "WM");
18 // The GPR register class that can hold the write mask. Use GR8 for fewer
19 // than 8 elements. Use shift-right and equal to work around the lack of
22 !cast<RegisterClass>("GR" #
23 !if (!eq (!srl(NumElts, 3), 0), 8, NumElts));
25 // Suffix used in the instruction mnemonic.
26 string Suffix = suffix;
28 // VTName is a string name for vector VT. For vector types it will be
29 // v # NumElts # EltVT, so for vector of 8 elements of i32 it will be v8i32
30 // It is a little bit complex for scalar types, where NumElts = 1.
31 // In this case we build v4f32 or v2f64
32 string VTName = "v" # !if (!eq (NumElts, 1),
33 !if (!eq (EltVT.Size, 32), 4,
34 !if (!eq (EltVT.Size, 64), 2, NumElts)), NumElts) # EltVT;
37 ValueType VT = !cast<ValueType>(VTName);
39 string EltTypeName = !cast<string>(EltVT);
40 // Size of the element type in bits, e.g. 32 for v16i32.
41 string EltSizeName = !subst("i", "", !subst("f", "", EltTypeName));
42 int EltSize = EltVT.Size;
44 // "i" for integer types and "f" for floating-point types
45 string TypeVariantName = !subst(EltSizeName, "", EltTypeName);
47 // Size of RC in bits, e.g. 512 for VR512.
50 // The corresponding memory operand, e.g. i512mem for VR512.
51 X86MemOperand MemOp = !cast<X86MemOperand>(TypeVariantName # Size # "mem");
52 X86MemOperand ScalarMemOp = !cast<X86MemOperand>(EltVT # "mem");
55 // Note: For 128/256-bit integer VT we choose loadv2i64/loadv4i64
56 // due to load promotion during legalization
57 PatFrag LdFrag = !cast<PatFrag>("load" #
58 !if (!eq (TypeVariantName, "i"),
59 !if (!eq (Size, 128), "v2i64",
60 !if (!eq (Size, 256), "v4i64",
62 PatFrag ScalarLdFrag = !cast<PatFrag>("load" # EltVT);
64 // Load patterns used for memory operands. We only have this defined in
65 // case of i64 element types for sub-512 integer vectors. For now, keep
66 // MemOpFrag undefined in these cases.
68 !if (!eq (NumElts#EltTypeName, "1f32"), !cast<PatFrag>("memopfsf32"),
69 !if (!eq (NumElts#EltTypeName, "1f64"), !cast<PatFrag>("memopfsf64"),
70 !if (!eq (TypeVariantName, "f"), !cast<PatFrag>("memop" # VTName),
71 !if (!eq (EltTypeName, "i64"), !cast<PatFrag>("memop" # VTName),
72 !if (!eq (VTName, "v16i32"), !cast<PatFrag>("memop" # VTName), ?)))));
74 // The corresponding float type, e.g. v16f32 for v16i32
75 // Note: For EltSize < 32, FloatVT is illegal and TableGen
76 // fails to compile, so we choose FloatVT = VT
77 ValueType FloatVT = !cast<ValueType>(
78 !if (!eq (!srl(EltSize,5),0),
80 !if (!eq(TypeVariantName, "i"),
81 "v" # NumElts # "f" # EltSize,
84 // The string to specify embedded broadcast in assembly.
85 string BroadcastStr = "{1to" # NumElts # "}";
87 // 8-bit compressed displacement tuple/subvector format. This is only
88 // defined for NumElts <= 8.
89 CD8VForm CD8TupleForm = !if (!eq (!srl(NumElts, 4), 0),
90 !cast<CD8VForm>("CD8VT" # NumElts), ?);
92 SubRegIndex SubRegIdx = !if (!eq (Size, 128), sub_xmm,
93 !if (!eq (Size, 256), sub_ymm, ?));
95 Domain ExeDomain = !if (!eq (EltTypeName, "f32"), SSEPackedSingle,
96 !if (!eq (EltTypeName, "f64"), SSEPackedDouble,
99 // A vector type of the same width with element type i32. This is used to
100 // create the canonical constant zero node ImmAllZerosV.
101 ValueType i32VT = !cast<ValueType>("v" # !srl(Size, 5) # "i32");
102 dag ImmAllZerosV = (VT (bitconvert (i32VT immAllZerosV)));
105 def v64i8_info : X86VectorVTInfo<64, i8, VR512, "b">;
106 def v32i16_info : X86VectorVTInfo<32, i16, VR512, "w">;
107 def v16i32_info : X86VectorVTInfo<16, i32, VR512, "d">;
108 def v8i64_info : X86VectorVTInfo<8, i64, VR512, "q">;
109 def v16f32_info : X86VectorVTInfo<16, f32, VR512, "ps">;
110 def v8f64_info : X86VectorVTInfo<8, f64, VR512, "pd">;
112 // "x" in v32i8x_info means RC = VR256X
113 def v32i8x_info : X86VectorVTInfo<32, i8, VR256X, "b">;
114 def v16i16x_info : X86VectorVTInfo<16, i16, VR256X, "w">;
115 def v8i32x_info : X86VectorVTInfo<8, i32, VR256X, "d">;
116 def v4i64x_info : X86VectorVTInfo<4, i64, VR256X, "q">;
117 def v8f32x_info : X86VectorVTInfo<8, f32, VR256X, "ps">;
118 def v4f64x_info : X86VectorVTInfo<4, f64, VR256X, "pd">;
120 def v16i8x_info : X86VectorVTInfo<16, i8, VR128X, "b">;
121 def v8i16x_info : X86VectorVTInfo<8, i16, VR128X, "w">;
122 def v4i32x_info : X86VectorVTInfo<4, i32, VR128X, "d">;
123 def v2i64x_info : X86VectorVTInfo<2, i64, VR128X, "q">;
124 def v4f32x_info : X86VectorVTInfo<4, f32, VR128X, "ps">;
125 def v2f64x_info : X86VectorVTInfo<2, f64, VR128X, "pd">;
127 // We map scalar types to the smallest (128-bit) vector type
128 // with the appropriate element type. This allows to use the same masking logic.
129 def f32x_info : X86VectorVTInfo<1, f32, VR128X, "ss">;
130 def f64x_info : X86VectorVTInfo<1, f64, VR128X, "sd">;
132 class AVX512VLVectorVTInfo<X86VectorVTInfo i512, X86VectorVTInfo i256,
133 X86VectorVTInfo i128> {
134 X86VectorVTInfo info512 = i512;
135 X86VectorVTInfo info256 = i256;
136 X86VectorVTInfo info128 = i128;
139 def avx512vl_i8_info : AVX512VLVectorVTInfo<v64i8_info, v32i8x_info,
141 def avx512vl_i16_info : AVX512VLVectorVTInfo<v32i16_info, v16i16x_info,
143 def avx512vl_i32_info : AVX512VLVectorVTInfo<v16i32_info, v8i32x_info,
145 def avx512vl_i64_info : AVX512VLVectorVTInfo<v8i64_info, v4i64x_info,
147 def avx512vl_f32_info : AVX512VLVectorVTInfo<v16f32_info, v8f32x_info,
149 def avx512vl_f64_info : AVX512VLVectorVTInfo<v8f64_info, v4f64x_info,
152 // This multiclass generates the masking variants from the non-masking
153 // variant. It only provides the assembly pieces for the masking variants.
154 // It assumes custom ISel patterns for masking which can be provided as
155 // template arguments.
156 multiclass AVX512_maskable_custom<bits<8> O, Format F,
158 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
160 string AttSrcAsm, string IntelSrcAsm,
162 list<dag> MaskingPattern,
163 list<dag> ZeroMaskingPattern,
165 string MaskingConstraint = "",
166 InstrItinClass itin = NoItinerary,
167 bit IsCommutable = 0> {
168 let isCommutable = IsCommutable in
169 def NAME: AVX512<O, F, Outs, Ins,
170 OpcodeStr#"\t{"#AttSrcAsm#", $dst "#Round#"|"#
171 "$dst "#Round#", "#IntelSrcAsm#"}",
174 // Prefer over VMOV*rrk Pat<>
175 let AddedComplexity = 20 in
176 def NAME#k: AVX512<O, F, Outs, MaskingIns,
177 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}}"#Round#"|"#
178 "$dst {${mask}}"#Round#", "#IntelSrcAsm#"}",
179 MaskingPattern, itin>,
181 // In case of the 3src subclass this is overridden with a let.
182 string Constraints = MaskingConstraint;
184 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
185 def NAME#kz: AVX512<O, F, Outs, ZeroMaskingIns,
186 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}} {z}"#Round#"|"#
187 "$dst {${mask}} {z}"#Round#", "#IntelSrcAsm#"}",
194 // Common base class of AVX512_maskable and AVX512_maskable_3src.
195 multiclass AVX512_maskable_common<bits<8> O, Format F, X86VectorVTInfo _,
197 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
199 string AttSrcAsm, string IntelSrcAsm,
200 dag RHS, dag MaskingRHS,
201 SDNode Select = vselect, string Round = "",
202 string MaskingConstraint = "",
203 InstrItinClass itin = NoItinerary,
204 bit IsCommutable = 0> :
205 AVX512_maskable_custom<O, F, Outs, Ins, MaskingIns, ZeroMaskingIns, OpcodeStr,
206 AttSrcAsm, IntelSrcAsm,
207 [(set _.RC:$dst, RHS)],
208 [(set _.RC:$dst, MaskingRHS)],
210 (Select _.KRCWM:$mask, RHS, _.ImmAllZerosV))],
211 Round, MaskingConstraint, NoItinerary, IsCommutable>;
213 // This multiclass generates the unconditional/non-masking, the masking and
214 // the zero-masking variant of the vector instruction. In the masking case, the
215 // perserved vector elements come from a new dummy input operand tied to $dst.
216 multiclass AVX512_maskable<bits<8> O, Format F, X86VectorVTInfo _,
217 dag Outs, dag Ins, string OpcodeStr,
218 string AttSrcAsm, string IntelSrcAsm,
219 dag RHS, string Round = "",
220 InstrItinClass itin = NoItinerary,
221 bit IsCommutable = 0> :
222 AVX512_maskable_common<O, F, _, Outs, Ins,
223 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
224 !con((ins _.KRCWM:$mask), Ins),
225 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
226 (vselect _.KRCWM:$mask, RHS, _.RC:$src0), vselect,
227 Round, "$src0 = $dst", itin, IsCommutable>;
229 // This multiclass generates the unconditional/non-masking, the masking and
230 // the zero-masking variant of the scalar instruction.
231 multiclass AVX512_maskable_scalar<bits<8> O, Format F, X86VectorVTInfo _,
232 dag Outs, dag Ins, string OpcodeStr,
233 string AttSrcAsm, string IntelSrcAsm,
234 dag RHS, string Round = "",
235 InstrItinClass itin = NoItinerary,
236 bit IsCommutable = 0> :
237 AVX512_maskable_common<O, F, _, Outs, Ins,
238 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
239 !con((ins _.KRCWM:$mask), Ins),
240 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
241 (X86select _.KRCWM:$mask, RHS, _.RC:$src0), X86select,
242 Round, "$src0 = $dst", itin, IsCommutable>;
244 // Similar to AVX512_maskable but in this case one of the source operands
245 // ($src1) is already tied to $dst so we just use that for the preserved
246 // vector elements. NOTE that the NonTiedIns (the ins dag) should exclude
248 multiclass AVX512_maskable_3src<bits<8> O, Format F, X86VectorVTInfo _,
249 dag Outs, dag NonTiedIns, string OpcodeStr,
250 string AttSrcAsm, string IntelSrcAsm,
252 AVX512_maskable_common<O, F, _, Outs,
253 !con((ins _.RC:$src1), NonTiedIns),
254 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
255 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
256 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
257 (vselect _.KRCWM:$mask, RHS, _.RC:$src1)>;
260 multiclass AVX512_maskable_in_asm<bits<8> O, Format F, X86VectorVTInfo _,
263 string AttSrcAsm, string IntelSrcAsm,
265 AVX512_maskable_custom<O, F, Outs, Ins,
266 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
267 !con((ins _.KRCWM:$mask), Ins),
268 OpcodeStr, AttSrcAsm, IntelSrcAsm, Pattern, [], [], "",
271 // Bitcasts between 512-bit vector types. Return the original type since
272 // no instruction is needed for the conversion
273 let Predicates = [HasAVX512] in {
274 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
275 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
276 def : Pat<(v8f64 (bitconvert (v32i16 VR512:$src))), (v8f64 VR512:$src)>;
277 def : Pat<(v8f64 (bitconvert (v64i8 VR512:$src))), (v8f64 VR512:$src)>;
278 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
279 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
280 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
281 def : Pat<(v16f32 (bitconvert (v32i16 VR512:$src))), (v16f32 VR512:$src)>;
282 def : Pat<(v16f32 (bitconvert (v64i8 VR512:$src))), (v16f32 VR512:$src)>;
283 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
284 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
285 def : Pat<(v8i64 (bitconvert (v32i16 VR512:$src))), (v8i64 VR512:$src)>;
286 def : Pat<(v8i64 (bitconvert (v64i8 VR512:$src))), (v8i64 VR512:$src)>;
287 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
288 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
289 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
290 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
291 def : Pat<(v16i32 (bitconvert (v32i16 VR512:$src))), (v16i32 VR512:$src)>;
292 def : Pat<(v16i32 (bitconvert (v64i8 VR512:$src))), (v16i32 VR512:$src)>;
293 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
294 def : Pat<(v32i16 (bitconvert (v8i64 VR512:$src))), (v32i16 VR512:$src)>;
295 def : Pat<(v32i16 (bitconvert (v16i32 VR512:$src))), (v32i16 VR512:$src)>;
296 def : Pat<(v32i16 (bitconvert (v64i8 VR512:$src))), (v32i16 VR512:$src)>;
297 def : Pat<(v32i16 (bitconvert (v8f64 VR512:$src))), (v32i16 VR512:$src)>;
298 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
299 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
300 def : Pat<(v64i8 (bitconvert (v8i64 VR512:$src))), (v64i8 VR512:$src)>;
301 def : Pat<(v64i8 (bitconvert (v16i32 VR512:$src))), (v64i8 VR512:$src)>;
302 def : Pat<(v64i8 (bitconvert (v32i16 VR512:$src))), (v64i8 VR512:$src)>;
303 def : Pat<(v64i8 (bitconvert (v8f64 VR512:$src))), (v64i8 VR512:$src)>;
304 def : Pat<(v64i8 (bitconvert (v16f32 VR512:$src))), (v64i8 VR512:$src)>;
306 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
307 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
308 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
309 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
310 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
311 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
312 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
313 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
314 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
315 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
316 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
317 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
318 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
319 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
320 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
321 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
322 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
323 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
324 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
325 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
326 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
327 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
328 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
329 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
330 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
331 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
332 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
333 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
334 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
335 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
337 // Bitcasts between 256-bit vector types. Return the original type since
338 // no instruction is needed for the conversion
339 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
340 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
341 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
342 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
343 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
344 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
345 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
346 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
347 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
348 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
349 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
350 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
351 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
352 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
353 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
354 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
355 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
356 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
357 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
358 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
359 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
360 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
361 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
362 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
363 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
364 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
365 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
366 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
367 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
368 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
372 // AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
375 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
376 isPseudo = 1, Predicates = [HasAVX512] in {
377 def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
378 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
381 let Predicates = [HasAVX512] in {
382 def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
383 def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
384 def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
387 //===----------------------------------------------------------------------===//
388 // AVX-512 - VECTOR INSERT
391 multiclass vinsert_for_size_no_alt<int Opcode,
392 X86VectorVTInfo From, X86VectorVTInfo To,
393 PatFrag vinsert_insert,
394 SDNodeXForm INSERT_get_vinsert_imm> {
395 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
396 def rr : AVX512AIi8<Opcode, MRMSrcReg, (outs VR512:$dst),
397 (ins VR512:$src1, From.RC:$src2, u8imm:$src3),
398 "vinsert" # From.EltTypeName # "x" # From.NumElts #
399 "\t{$src3, $src2, $src1, $dst|"
400 "$dst, $src1, $src2, $src3}",
401 [(set To.RC:$dst, (vinsert_insert:$src3 (To.VT VR512:$src1),
402 (From.VT From.RC:$src2),
407 def rm : AVX512AIi8<Opcode, MRMSrcMem, (outs VR512:$dst),
408 (ins VR512:$src1, From.MemOp:$src2, u8imm:$src3),
409 "vinsert" # From.EltTypeName # "x" # From.NumElts #
410 "\t{$src3, $src2, $src1, $dst|"
411 "$dst, $src1, $src2, $src3}",
413 EVEX_4V, EVEX_V512, EVEX_CD8<From.EltSize, From.CD8TupleForm>;
417 multiclass vinsert_for_size<int Opcode,
418 X86VectorVTInfo From, X86VectorVTInfo To,
419 X86VectorVTInfo AltFrom, X86VectorVTInfo AltTo,
420 PatFrag vinsert_insert,
421 SDNodeXForm INSERT_get_vinsert_imm> :
422 vinsert_for_size_no_alt<Opcode, From, To,
423 vinsert_insert, INSERT_get_vinsert_imm> {
424 // Codegen pattern with the alternative types, e.g. v2i64 -> v8i64 for
425 // vinserti32x4. Only add this if 64x2 and friends are not supported
426 // natively via AVX512DQ.
427 let Predicates = [NoDQI] in
428 def : Pat<(vinsert_insert:$ins
429 (AltTo.VT VR512:$src1), (AltFrom.VT From.RC:$src2), (iPTR imm)),
430 (AltTo.VT (!cast<Instruction>(NAME # From.EltSize # "x4rr")
431 VR512:$src1, From.RC:$src2,
432 (INSERT_get_vinsert_imm VR512:$ins)))>;
435 multiclass vinsert_for_type<ValueType EltVT32, int Opcode128,
436 ValueType EltVT64, int Opcode256> {
437 defm NAME # "32x4" : vinsert_for_size<Opcode128,
438 X86VectorVTInfo< 4, EltVT32, VR128X>,
439 X86VectorVTInfo<16, EltVT32, VR512>,
440 X86VectorVTInfo< 2, EltVT64, VR128X>,
441 X86VectorVTInfo< 8, EltVT64, VR512>,
443 INSERT_get_vinsert128_imm>;
444 let Predicates = [HasDQI] in
445 defm NAME # "64x2" : vinsert_for_size_no_alt<Opcode128,
446 X86VectorVTInfo< 2, EltVT64, VR128X>,
447 X86VectorVTInfo< 8, EltVT64, VR512>,
449 INSERT_get_vinsert128_imm>, VEX_W;
450 defm NAME # "64x4" : vinsert_for_size<Opcode256,
451 X86VectorVTInfo< 4, EltVT64, VR256X>,
452 X86VectorVTInfo< 8, EltVT64, VR512>,
453 X86VectorVTInfo< 8, EltVT32, VR256>,
454 X86VectorVTInfo<16, EltVT32, VR512>,
456 INSERT_get_vinsert256_imm>, VEX_W;
457 let Predicates = [HasDQI] in
458 defm NAME # "32x8" : vinsert_for_size_no_alt<Opcode256,
459 X86VectorVTInfo< 8, EltVT32, VR256X>,
460 X86VectorVTInfo<16, EltVT32, VR512>,
462 INSERT_get_vinsert256_imm>;
465 defm VINSERTF : vinsert_for_type<f32, 0x18, f64, 0x1a>;
466 defm VINSERTI : vinsert_for_type<i32, 0x38, i64, 0x3a>;
468 // vinsertps - insert f32 to XMM
469 def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
470 (ins VR128X:$src1, VR128X:$src2, u8imm:$src3),
471 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
472 [(set VR128X:$dst, (X86insertps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
474 def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
475 (ins VR128X:$src1, f32mem:$src2, u8imm:$src3),
476 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
477 [(set VR128X:$dst, (X86insertps VR128X:$src1,
478 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
479 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
481 //===----------------------------------------------------------------------===//
482 // AVX-512 VECTOR EXTRACT
485 multiclass vextract_for_size<int Opcode,
486 X86VectorVTInfo From, X86VectorVTInfo To,
487 X86VectorVTInfo AltFrom, X86VectorVTInfo AltTo,
488 PatFrag vextract_extract,
489 SDNodeXForm EXTRACT_get_vextract_imm> {
490 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
491 defm rr : AVX512_maskable_in_asm<Opcode, MRMDestReg, To, (outs To.RC:$dst),
492 (ins VR512:$src1, u8imm:$idx),
493 "vextract" # To.EltTypeName # "x4",
494 "$idx, $src1", "$src1, $idx",
495 [(set To.RC:$dst, (vextract_extract:$idx (From.VT VR512:$src1),
497 AVX512AIi8Base, EVEX, EVEX_V512;
499 def rm : AVX512AIi8<Opcode, MRMDestMem, (outs),
500 (ins To.MemOp:$dst, VR512:$src1, u8imm:$src2),
501 "vextract" # To.EltTypeName # "x4\t{$src2, $src1, $dst|"
502 "$dst, $src1, $src2}",
503 []>, EVEX, EVEX_V512, EVEX_CD8<To.EltSize, CD8VT4>;
506 // Codegen pattern with the alternative types, e.g. v8i64 -> v2i64 for
508 def : Pat<(vextract_extract:$ext (AltFrom.VT VR512:$src1), (iPTR imm)),
509 (AltTo.VT (!cast<Instruction>(NAME # To.EltSize # "x4rr")
511 (EXTRACT_get_vextract_imm To.RC:$ext)))>;
513 // A 128/256-bit subvector extract from the first 512-bit vector position is
514 // a subregister copy that needs no instruction.
515 def : Pat<(To.VT (extract_subvector (From.VT VR512:$src), (iPTR 0))),
517 (EXTRACT_SUBREG (From.VT VR512:$src), To.SubRegIdx))>;
519 // And for the alternative types.
520 def : Pat<(AltTo.VT (extract_subvector (AltFrom.VT VR512:$src), (iPTR 0))),
522 (EXTRACT_SUBREG (AltFrom.VT VR512:$src), AltTo.SubRegIdx))>;
524 // Intrinsic call with masking.
525 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
527 VR512:$src1, (iPTR imm:$idx), To.RC:$src0, GR8:$mask),
528 (!cast<Instruction>(NAME # To.EltSize # "x4rrk") To.RC:$src0,
529 (v4i1 (COPY_TO_REGCLASS GR8:$mask, VK4WM)),
530 VR512:$src1, imm:$idx)>;
532 // Intrinsic call with zero-masking.
533 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
535 VR512:$src1, (iPTR imm:$idx), To.ImmAllZerosV, GR8:$mask),
536 (!cast<Instruction>(NAME # To.EltSize # "x4rrkz")
537 (v4i1 (COPY_TO_REGCLASS GR8:$mask, VK4WM)),
538 VR512:$src1, imm:$idx)>;
540 // Intrinsic call without masking.
541 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
543 VR512:$src1, (iPTR imm:$idx), To.ImmAllZerosV, (i8 -1)),
544 (!cast<Instruction>(NAME # To.EltSize # "x4rr")
545 VR512:$src1, imm:$idx)>;
548 multiclass vextract_for_type<ValueType EltVT32, int Opcode32,
549 ValueType EltVT64, int Opcode64> {
550 defm NAME # "32x4" : vextract_for_size<Opcode32,
551 X86VectorVTInfo<16, EltVT32, VR512>,
552 X86VectorVTInfo< 4, EltVT32, VR128X>,
553 X86VectorVTInfo< 8, EltVT64, VR512>,
554 X86VectorVTInfo< 2, EltVT64, VR128X>,
556 EXTRACT_get_vextract128_imm>;
557 defm NAME # "64x4" : vextract_for_size<Opcode64,
558 X86VectorVTInfo< 8, EltVT64, VR512>,
559 X86VectorVTInfo< 4, EltVT64, VR256X>,
560 X86VectorVTInfo<16, EltVT32, VR512>,
561 X86VectorVTInfo< 8, EltVT32, VR256>,
563 EXTRACT_get_vextract256_imm>, VEX_W;
566 defm VEXTRACTF : vextract_for_type<f32, 0x19, f64, 0x1b>;
567 defm VEXTRACTI : vextract_for_type<i32, 0x39, i64, 0x3b>;
569 // A 128-bit subvector insert to the first 512-bit vector position
570 // is a subregister copy that needs no instruction.
571 def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
572 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
573 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
575 def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
576 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
577 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
579 def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
580 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
581 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
583 def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
584 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
585 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
588 def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
589 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
590 def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
591 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
592 def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
593 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
594 def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
595 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
597 // vextractps - extract 32 bits from XMM
598 def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
599 (ins VR128X:$src1, u8imm:$src2),
600 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
601 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
604 def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
605 (ins f32mem:$dst, VR128X:$src1, u8imm:$src2),
606 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
607 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
608 addr:$dst)]>, EVEX, EVEX_CD8<32, CD8VT1>;
610 //===---------------------------------------------------------------------===//
613 multiclass avx512_fp_broadcast<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
614 ValueType svt, X86VectorVTInfo _> {
615 defm r : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
616 (ins SrcRC:$src), "vbroadcast"## !subst("p", "s", _.Suffix),
617 "$src", "$src", (_.VT (OpNode (svt SrcRC:$src)))>,
621 defm m : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
622 (ins _.ScalarMemOp:$src),
623 "vbroadcast"##!subst("p", "s", _.Suffix), "$src", "$src",
624 (_.VT (OpNode (_.ScalarLdFrag addr:$src)))>,
629 multiclass avx512_fp_broadcast_vl<bits<8> opc, SDNode OpNode,
630 AVX512VLVectorVTInfo _> {
631 defm Z : avx512_fp_broadcast<opc, OpNode, VR128X, _.info128.VT, _.info512>,
634 let Predicates = [HasVLX] in {
635 defm Z256 : avx512_fp_broadcast<opc, OpNode, VR128X, _.info128.VT, _.info256>,
640 let ExeDomain = SSEPackedSingle in {
641 defm VBROADCASTSS : avx512_fp_broadcast_vl<0x18, X86VBroadcast,
642 avx512vl_f32_info>, EVEX_CD8<32, CD8VT1>;
643 let Predicates = [HasVLX] in {
644 defm VBROADCASTSSZ128 : avx512_fp_broadcast<0x18, X86VBroadcast, VR128X,
645 v4f32, v4f32x_info>, EVEX_V128,
646 EVEX_CD8<32, CD8VT1>;
650 let ExeDomain = SSEPackedDouble in {
651 defm VBROADCASTSD : avx512_fp_broadcast_vl<0x19, X86VBroadcast,
652 avx512vl_f64_info>, VEX_W, EVEX_CD8<64, CD8VT1>;
655 // avx512_broadcast_pat introduces patterns for broadcast with a scalar argument.
656 // Later, we can canonize broadcast instructions before ISel phase and
657 // eliminate additional patterns on ISel.
658 // SrcRC_v and SrcRC_s are RegisterClasses for vector and scalar
659 // representations of source
660 multiclass avx512_broadcast_pat<string InstName, SDNode OpNode,
661 X86VectorVTInfo _, RegisterClass SrcRC_v,
662 RegisterClass SrcRC_s> {
663 def : Pat<(_.VT (OpNode (_.EltVT SrcRC_s:$src))),
664 (!cast<Instruction>(InstName##"r")
665 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
667 let AddedComplexity = 30 in {
668 def : Pat<(_.VT (vselect _.KRCWM:$mask,
669 (OpNode (_.EltVT SrcRC_s:$src)), _.RC:$src0)),
670 (!cast<Instruction>(InstName##"rk") _.RC:$src0, _.KRCWM:$mask,
671 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
673 def : Pat<(_.VT(vselect _.KRCWM:$mask,
674 (OpNode (_.EltVT SrcRC_s:$src)), _.ImmAllZerosV)),
675 (!cast<Instruction>(InstName##"rkz") _.KRCWM:$mask,
676 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
680 defm : avx512_broadcast_pat<"VBROADCASTSSZ", X86VBroadcast, v16f32_info,
682 defm : avx512_broadcast_pat<"VBROADCASTSDZ", X86VBroadcast, v8f64_info,
685 let Predicates = [HasVLX] in {
686 defm : avx512_broadcast_pat<"VBROADCASTSSZ256", X86VBroadcast,
687 v8f32x_info, VR128X, FR32X>;
688 defm : avx512_broadcast_pat<"VBROADCASTSSZ128", X86VBroadcast,
689 v4f32x_info, VR128X, FR32X>;
690 defm : avx512_broadcast_pat<"VBROADCASTSDZ256", X86VBroadcast,
691 v4f64x_info, VR128X, FR64X>;
694 def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
695 (VBROADCASTSSZm addr:$src)>;
696 def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
697 (VBROADCASTSDZm addr:$src)>;
699 def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
700 (VBROADCASTSSZm addr:$src)>;
701 def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
702 (VBROADCASTSDZm addr:$src)>;
704 multiclass avx512_int_broadcast_reg<bits<8> opc, X86VectorVTInfo _,
705 RegisterClass SrcRC> {
706 defm r : AVX512_maskable_in_asm<opc, MRMSrcReg, _, (outs _.RC:$dst),
707 (ins SrcRC:$src), "vpbroadcast"##_.Suffix,
708 "$src", "$src", []>, T8PD, EVEX;
711 multiclass avx512_int_broadcast_reg_vl<bits<8> opc, AVX512VLVectorVTInfo _,
712 RegisterClass SrcRC, Predicate prd> {
713 let Predicates = [prd] in
714 defm Z : avx512_int_broadcast_reg<opc, _.info512, SrcRC>, EVEX_V512;
715 let Predicates = [prd, HasVLX] in {
716 defm Z256 : avx512_int_broadcast_reg<opc, _.info256, SrcRC>, EVEX_V256;
717 defm Z128 : avx512_int_broadcast_reg<opc, _.info128, SrcRC>, EVEX_V128;
721 defm VPBROADCASTBr : avx512_int_broadcast_reg_vl<0x7A, avx512vl_i8_info, GR32,
723 defm VPBROADCASTWr : avx512_int_broadcast_reg_vl<0x7B, avx512vl_i16_info, GR32,
725 defm VPBROADCASTDr : avx512_int_broadcast_reg_vl<0x7C, avx512vl_i32_info, GR32,
727 defm VPBROADCASTQr : avx512_int_broadcast_reg_vl<0x7C, avx512vl_i64_info, GR64,
730 def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
731 (VPBROADCASTDrZrkz VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
733 def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
734 (VPBROADCASTQrZrkz VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
736 def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
737 (VPBROADCASTDrZr GR32:$src)>;
738 def : Pat<(v16i32 (X86VBroadcastm VK16WM:$mask, (i32 GR32:$src))),
739 (VPBROADCASTDrZrkz VK16WM:$mask, GR32:$src)>;
740 def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
741 (VPBROADCASTQrZr GR64:$src)>;
742 def : Pat<(v8i64 (X86VBroadcastm VK8WM:$mask, (i64 GR64:$src))),
743 (VPBROADCASTQrZrkz VK8WM:$mask, GR64:$src)>;
745 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_i32_512 (i32 GR32:$src))),
746 (VPBROADCASTDrZr GR32:$src)>;
747 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_i64_512 (i64 GR64:$src))),
748 (VPBROADCASTQrZr GR64:$src)>;
750 def : Pat<(v16i32 (int_x86_avx512_mask_pbroadcast_d_gpr_512 (i32 GR32:$src),
751 (v16i32 immAllZerosV), (i16 GR16:$mask))),
752 (VPBROADCASTDrZrkz (COPY_TO_REGCLASS GR16:$mask, VK16WM), GR32:$src)>;
753 def : Pat<(v8i64 (int_x86_avx512_mask_pbroadcast_q_gpr_512 (i64 GR64:$src),
754 (bc_v8i64 (v16i32 immAllZerosV)), (i8 GR8:$mask))),
755 (VPBROADCASTQrZrkz (COPY_TO_REGCLASS GR8:$mask, VK8WM), GR64:$src)>;
757 multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr,
758 X86MemOperand x86memop, PatFrag ld_frag,
759 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
761 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
762 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
764 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
765 def krr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
767 !strconcat(OpcodeStr,
768 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
770 (OpVT (X86VBroadcastm KRC:$mask, (SrcVT VR128X:$src))))]>,
773 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
774 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
776 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
777 def krm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
779 !strconcat(OpcodeStr,
780 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
781 [(set DstRC:$dst, (OpVT (X86VBroadcastm KRC:$mask,
782 (ld_frag addr:$src))))]>, EVEX, EVEX_KZ;
786 defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem,
787 loadi32, VR512, v16i32, v4i32, VK16WM>,
788 EVEX_V512, EVEX_CD8<32, CD8VT1>;
789 defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem,
790 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W,
791 EVEX_CD8<64, CD8VT1>;
793 multiclass avx512_int_subvec_broadcast_rm<bits<8> opc, string OpcodeStr,
794 X86MemOperand x86memop, PatFrag ld_frag,
797 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins x86memop:$src),
798 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
800 def krm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins KRC:$mask,
802 !strconcat(OpcodeStr,
803 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
808 defm VBROADCASTI32X4 : avx512_int_subvec_broadcast_rm<0x5a, "vbroadcasti32x4",
809 i128mem, loadv2i64, VK16WM>,
810 EVEX_V512, EVEX_CD8<32, CD8VT4>;
811 defm VBROADCASTI64X4 : avx512_int_subvec_broadcast_rm<0x5b, "vbroadcasti64x4",
812 i256mem, loadv4i64, VK16WM>, VEX_W,
813 EVEX_V512, EVEX_CD8<64, CD8VT4>;
815 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_512 (v4i32 VR128X:$src))),
816 (VPBROADCASTDZrr VR128X:$src)>;
817 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_512 (v2i64 VR128X:$src))),
818 (VPBROADCASTQZrr VR128X:$src)>;
820 def : Pat<(v16f32 (X86VBroadcast (v16f32 VR512:$src))),
821 (VBROADCASTSSZr (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
822 def : Pat<(v8f64 (X86VBroadcast (v8f64 VR512:$src))),
823 (VBROADCASTSDZr (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
825 def : Pat<(v16i32 (X86VBroadcast (v16i32 VR512:$src))),
826 (VPBROADCASTDZrr (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm))>;
827 def : Pat<(v8i64 (X86VBroadcast (v8i64 VR512:$src))),
828 (VPBROADCASTQZrr (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm))>;
830 def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))),
831 (VBROADCASTSSZr VR128X:$src)>;
832 def : Pat<(v8f64 (int_x86_avx512_vbroadcast_sd_pd_512 (v2f64 VR128X:$src))),
833 (VBROADCASTSDZr VR128X:$src)>;
835 // Provide fallback in case the load node that is used in the patterns above
836 // is used by additional users, which prevents the pattern selection.
837 def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
838 (VBROADCASTSSZr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
839 def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
840 (VBROADCASTSDZr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
843 let Predicates = [HasAVX512] in {
844 def : Pat<(v8i32 (X86VBroadcastm (v8i1 VK8WM:$mask), (loadi32 addr:$src))),
846 (v16i32 (VPBROADCASTDZkrm (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
847 addr:$src)), sub_ymm)>;
849 //===----------------------------------------------------------------------===//
850 // AVX-512 BROADCAST MASK TO VECTOR REGISTER
853 multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
855 let Predicates = [HasCDI] in
856 def Zrr : AVX512XS8I<opc, MRMSrcReg, (outs VR512:$dst), (ins KRC:$src),
857 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
858 []>, EVEX, EVEX_V512;
860 let Predicates = [HasCDI, HasVLX] in {
861 def Z128rr : AVX512XS8I<opc, MRMSrcReg, (outs VR128:$dst), (ins KRC:$src),
862 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
863 []>, EVEX, EVEX_V128;
864 def Z256rr : AVX512XS8I<opc, MRMSrcReg, (outs VR256:$dst), (ins KRC:$src),
865 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
866 []>, EVEX, EVEX_V256;
870 let Predicates = [HasCDI] in {
871 defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d",
873 defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q",
877 //===----------------------------------------------------------------------===//
880 // -- immediate form --
881 multiclass avx512_perm_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
883 let ExeDomain = _.ExeDomain in {
884 def ri : AVX512AIi8<opc, MRMSrcReg, (outs _.RC:$dst),
885 (ins _.RC:$src1, u8imm:$src2),
886 !strconcat(OpcodeStr,
887 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
889 (_.VT (OpNode _.RC:$src1, (i8 imm:$src2))))]>,
891 def mi : AVX512AIi8<opc, MRMSrcMem, (outs _.RC:$dst),
892 (ins _.MemOp:$src1, u8imm:$src2),
893 !strconcat(OpcodeStr,
894 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
896 (_.VT (OpNode (_.MemOpFrag addr:$src1),
898 EVEX, EVEX_CD8<_.EltSize, CD8VF>;
902 multiclass avx512_permil<bits<8> OpcImm, bits<8> OpcVar, X86VectorVTInfo _,
903 X86VectorVTInfo Ctrl> :
904 avx512_perm_imm<OpcImm, "vpermil" # _.Suffix, X86VPermilpi, _> {
905 let ExeDomain = _.ExeDomain in {
906 def rr : AVX5128I<OpcVar, MRMSrcReg, (outs _.RC:$dst),
907 (ins _.RC:$src1, _.RC:$src2),
908 !strconcat("vpermil" # _.Suffix,
909 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
911 (_.VT (X86VPermilpv _.RC:$src1,
912 (Ctrl.VT Ctrl.RC:$src2))))]>,
914 def rm : AVX5128I<OpcVar, MRMSrcMem, (outs _.RC:$dst),
915 (ins _.RC:$src1, Ctrl.MemOp:$src2),
916 !strconcat("vpermil" # _.Suffix,
917 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
919 (_.VT (X86VPermilpv _.RC:$src1,
920 (Ctrl.VT (Ctrl.MemOpFrag addr:$src2)))))]>,
925 defm VPERMQZ : avx512_perm_imm<0x00, "vpermq", X86VPermi, v8i64_info>,
927 defm VPERMPDZ : avx512_perm_imm<0x01, "vpermpd", X86VPermi, v8f64_info>,
930 defm VPERMILPSZ : avx512_permil<0x04, 0x0C, v16f32_info, v16i32_info>,
932 defm VPERMILPDZ : avx512_permil<0x05, 0x0D, v8f64_info, v8i64_info>,
935 def : Pat<(v16i32 (X86VPermilpi VR512:$src1, (i8 imm:$imm))),
936 (VPERMILPSZri VR512:$src1, imm:$imm)>;
937 def : Pat<(v8i64 (X86VPermilpi VR512:$src1, (i8 imm:$imm))),
938 (VPERMILPDZri VR512:$src1, imm:$imm)>;
940 // -- VPERM - register form --
941 multiclass avx512_perm<bits<8> opc, string OpcodeStr, RegisterClass RC,
942 PatFrag mem_frag, X86MemOperand x86memop, ValueType OpVT> {
944 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
945 (ins RC:$src1, RC:$src2),
946 !strconcat(OpcodeStr,
947 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
949 (OpVT (X86VPermv RC:$src1, RC:$src2)))]>, EVEX_4V;
951 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
952 (ins RC:$src1, x86memop:$src2),
953 !strconcat(OpcodeStr,
954 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
956 (OpVT (X86VPermv RC:$src1, (mem_frag addr:$src2))))]>,
960 defm VPERMDZ : avx512_perm<0x36, "vpermd", VR512, memopv16i32, i512mem,
961 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
962 defm VPERMQZ : avx512_perm<0x36, "vpermq", VR512, memopv8i64, i512mem,
963 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
964 let ExeDomain = SSEPackedSingle in
965 defm VPERMPSZ : avx512_perm<0x16, "vpermps", VR512, memopv16f32, f512mem,
966 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
967 let ExeDomain = SSEPackedDouble in
968 defm VPERMPDZ : avx512_perm<0x16, "vpermpd", VR512, memopv8f64, f512mem,
969 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
971 // -- VPERM2I - 3 source operands form --
972 multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr, RegisterClass RC,
973 PatFrag mem_frag, X86MemOperand x86memop,
974 SDNode OpNode, ValueType OpVT, RegisterClass KRC> {
975 let Constraints = "$src1 = $dst" in {
976 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
977 (ins RC:$src1, RC:$src2, RC:$src3),
978 !strconcat(OpcodeStr,
979 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
981 (OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)))]>,
984 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
985 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
986 !strconcat(OpcodeStr,
987 "\t{$src3, $src2, $dst {${mask}}|"
988 "$dst {${mask}}, $src2, $src3}"),
989 [(set RC:$dst, (OpVT (vselect KRC:$mask,
990 (OpNode RC:$src1, RC:$src2,
995 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
996 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
997 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
998 !strconcat(OpcodeStr,
999 "\t{$src3, $src2, $dst {${mask}} {z} |",
1000 "$dst {${mask}} {z}, $src2, $src3}"),
1001 [(set RC:$dst, (OpVT (vselect KRC:$mask,
1002 (OpNode RC:$src1, RC:$src2,
1005 (v16i32 immAllZerosV))))))]>,
1008 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
1009 (ins RC:$src1, RC:$src2, x86memop:$src3),
1010 !strconcat(OpcodeStr,
1011 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
1013 (OpVT (OpNode RC:$src1, RC:$src2,
1014 (mem_frag addr:$src3))))]>, EVEX_4V;
1016 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
1017 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
1018 !strconcat(OpcodeStr,
1019 "\t{$src3, $src2, $dst {${mask}}|"
1020 "$dst {${mask}}, $src2, $src3}"),
1022 (OpVT (vselect KRC:$mask,
1023 (OpNode RC:$src1, RC:$src2,
1024 (mem_frag addr:$src3)),
1028 let AddedComplexity = 10 in // Prefer over the rrkz variant
1029 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
1030 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
1031 !strconcat(OpcodeStr,
1032 "\t{$src3, $src2, $dst {${mask}} {z}|"
1033 "$dst {${mask}} {z}, $src2, $src3}"),
1035 (OpVT (vselect KRC:$mask,
1036 (OpNode RC:$src1, RC:$src2,
1037 (mem_frag addr:$src3)),
1039 (v16i32 immAllZerosV))))))]>,
1043 defm VPERMI2D : avx512_perm_3src<0x76, "vpermi2d", VR512, memopv16i32,
1044 i512mem, X86VPermiv3, v16i32, VK16WM>,
1045 EVEX_V512, EVEX_CD8<32, CD8VF>;
1046 defm VPERMI2Q : avx512_perm_3src<0x76, "vpermi2q", VR512, memopv8i64,
1047 i512mem, X86VPermiv3, v8i64, VK8WM>,
1048 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1049 defm VPERMI2PS : avx512_perm_3src<0x77, "vpermi2ps", VR512, memopv16f32,
1050 i512mem, X86VPermiv3, v16f32, VK16WM>,
1051 EVEX_V512, EVEX_CD8<32, CD8VF>;
1052 defm VPERMI2PD : avx512_perm_3src<0x77, "vpermi2pd", VR512, memopv8f64,
1053 i512mem, X86VPermiv3, v8f64, VK8WM>,
1054 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1056 multiclass avx512_perm_table_3src<bits<8> opc, string Suffix, RegisterClass RC,
1057 PatFrag mem_frag, X86MemOperand x86memop,
1058 SDNode OpNode, ValueType OpVT, RegisterClass KRC,
1059 ValueType MaskVT, RegisterClass MRC> :
1060 avx512_perm_3src<opc, "vpermt2"##Suffix, RC, mem_frag, x86memop, OpNode,
1062 def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512")
1063 VR512:$idx, VR512:$src1, VR512:$src2, -1)),
1064 (!cast<Instruction>(NAME#rr) VR512:$src1, VR512:$idx, VR512:$src2)>;
1066 def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512")
1067 VR512:$idx, VR512:$src1, VR512:$src2, MRC:$mask)),
1068 (!cast<Instruction>(NAME#rrk) VR512:$src1,
1069 (MaskVT (COPY_TO_REGCLASS MRC:$mask, KRC)), VR512:$idx, VR512:$src2)>;
1072 defm VPERMT2D : avx512_perm_table_3src<0x7E, "d", VR512, memopv16i32, i512mem,
1073 X86VPermv3, v16i32, VK16WM, v16i1, GR16>,
1074 EVEX_V512, EVEX_CD8<32, CD8VF>;
1075 defm VPERMT2Q : avx512_perm_table_3src<0x7E, "q", VR512, memopv8i64, i512mem,
1076 X86VPermv3, v8i64, VK8WM, v8i1, GR8>,
1077 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1078 defm VPERMT2PS : avx512_perm_table_3src<0x7F, "ps", VR512, memopv16f32, i512mem,
1079 X86VPermv3, v16f32, VK16WM, v16i1, GR16>,
1080 EVEX_V512, EVEX_CD8<32, CD8VF>;
1081 defm VPERMT2PD : avx512_perm_table_3src<0x7F, "pd", VR512, memopv8f64, i512mem,
1082 X86VPermv3, v8f64, VK8WM, v8i1, GR8>,
1083 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1085 //===----------------------------------------------------------------------===//
1086 // AVX-512 - BLEND using mask
1088 multiclass avx512_blendmask<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
1089 let ExeDomain = _.ExeDomain in {
1090 def rr : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1091 (ins _.RC:$src1, _.RC:$src2),
1092 !strconcat(OpcodeStr,
1093 "\t{$src2, $src1, ${dst} |${dst}, $src1, $src2}"),
1095 def rrk : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1096 (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1097 !strconcat(OpcodeStr,
1098 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
1099 [(set _.RC:$dst, (X86select _.KRCWM:$mask, (_.VT _.RC:$src1),
1100 (_.VT _.RC:$src2)))]>, EVEX_4V, EVEX_K;
1101 def rrkz : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1102 (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1103 !strconcat(OpcodeStr,
1104 "\t{$src2, $src1, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src1, $src2}"),
1105 []>, EVEX_4V, EVEX_KZ;
1106 let mayLoad = 1 in {
1107 def rm : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1108 (ins _.RC:$src1, _.MemOp:$src2),
1109 !strconcat(OpcodeStr,
1110 "\t{$src2, $src1, ${dst} |${dst}, $src1, $src2}"),
1111 []>, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
1112 def rmk : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1113 (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1114 !strconcat(OpcodeStr,
1115 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
1116 [(set _.RC:$dst, (X86select _.KRCWM:$mask, (_.VT _.RC:$src1),
1117 (_.VT (bitconvert (_.LdFrag addr:$src2)))))]>,
1118 EVEX_4V, EVEX_K, EVEX_CD8<_.EltSize, CD8VF>;
1119 def rmkz : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1120 (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1121 !strconcat(OpcodeStr,
1122 "\t{$src2, $src1, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src1, $src2}"),
1123 []>, EVEX_4V, EVEX_KZ, EVEX_CD8<_.EltSize, CD8VF>;
1127 multiclass avx512_blendmask_rmb<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
1129 def rmbk : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1130 (ins _.KRCWM:$mask, _.RC:$src1, _.ScalarMemOp:$src2),
1131 !strconcat(OpcodeStr,
1132 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1133 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1134 [(set _.RC:$dst,(X86select _.KRCWM:$mask, (_.VT _.RC:$src1),
1135 (X86VBroadcast (_.ScalarLdFrag addr:$src2))))]>,
1136 EVEX_4V, EVEX_K, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
1138 def rmb : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1139 (ins _.RC:$src1, _.ScalarMemOp:$src2),
1140 !strconcat(OpcodeStr,
1141 "\t{${src2}", _.BroadcastStr, ", $src1, $dst|",
1142 "$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1143 []>, EVEX_4V, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
1147 multiclass blendmask_dq <bits<8> opc, string OpcodeStr,
1148 AVX512VLVectorVTInfo VTInfo> {
1149 defm Z : avx512_blendmask <opc, OpcodeStr, VTInfo.info512>,
1150 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info512>, EVEX_V512;
1152 let Predicates = [HasVLX] in {
1153 defm Z256 : avx512_blendmask<opc, OpcodeStr, VTInfo.info256>,
1154 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info256>, EVEX_V256;
1155 defm Z128 : avx512_blendmask<opc, OpcodeStr, VTInfo.info128>,
1156 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info128>, EVEX_V128;
1160 multiclass blendmask_bw <bits<8> opc, string OpcodeStr,
1161 AVX512VLVectorVTInfo VTInfo> {
1162 let Predicates = [HasBWI] in
1163 defm Z : avx512_blendmask <opc, OpcodeStr, VTInfo.info512>, EVEX_V512;
1165 let Predicates = [HasBWI, HasVLX] in {
1166 defm Z256 : avx512_blendmask <opc, OpcodeStr, VTInfo.info256>, EVEX_V256;
1167 defm Z128 : avx512_blendmask <opc, OpcodeStr, VTInfo.info128>, EVEX_V128;
1172 defm VBLENDMPS : blendmask_dq <0x65, "vblendmps", avx512vl_f32_info>;
1173 defm VBLENDMPD : blendmask_dq <0x65, "vblendmpd", avx512vl_f64_info>, VEX_W;
1174 defm VPBLENDMD : blendmask_dq <0x64, "vpblendmd", avx512vl_i32_info>;
1175 defm VPBLENDMQ : blendmask_dq <0x64, "vpblendmq", avx512vl_i64_info>, VEX_W;
1176 defm VPBLENDMB : blendmask_bw <0x66, "vpblendmb", avx512vl_i8_info>;
1177 defm VPBLENDMW : blendmask_bw <0x66, "vpblendmw", avx512vl_i16_info>, VEX_W;
1180 let Predicates = [HasAVX512] in {
1181 def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
1182 (v8f32 VR256X:$src2))),
1184 (v16f32 (VBLENDMPSZrrk (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1185 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1186 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1188 def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
1189 (v8i32 VR256X:$src2))),
1191 (v16i32 (VPBLENDMDZrrk (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1192 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1193 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1195 //===----------------------------------------------------------------------===//
1196 // Compare Instructions
1197 //===----------------------------------------------------------------------===//
1199 // avx512_cmp_scalar - AVX512 CMPSS and CMPSD
1200 multiclass avx512_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
1201 SDNode OpNode, ValueType VT,
1202 PatFrag ld_frag, string Suffix> {
1203 def rr : AVX512Ii8<0xC2, MRMSrcReg,
1204 (outs VK1:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
1205 !strconcat("vcmp${cc}", Suffix,
1206 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1207 [(set VK1:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
1208 IIC_SSE_ALU_F32S_RR>, EVEX_4V;
1209 def rm : AVX512Ii8<0xC2, MRMSrcMem,
1210 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, AVXCC:$cc),
1211 !strconcat("vcmp${cc}", Suffix,
1212 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1213 [(set VK1:$dst, (OpNode (VT RC:$src1),
1214 (ld_frag addr:$src2), imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1215 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1216 def rri_alt : AVX512Ii8<0xC2, MRMSrcReg,
1217 (outs VK1:$dst), (ins RC:$src1, RC:$src2, u8imm:$cc),
1218 !strconcat("vcmp", Suffix,
1219 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
1220 [], IIC_SSE_ALU_F32S_RR>, EVEX_4V;
1222 def rmi_alt : AVX512Ii8<0xC2, MRMSrcMem,
1223 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, u8imm:$cc),
1224 !strconcat("vcmp", Suffix,
1225 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
1226 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1230 let Predicates = [HasAVX512] in {
1231 defm VCMPSSZ : avx512_cmp_scalar<FR32X, f32mem, X86cmpms, f32, loadf32, "ss">,
1233 defm VCMPSDZ : avx512_cmp_scalar<FR64X, f64mem, X86cmpms, f64, loadf64, "sd">,
1237 multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
1238 X86VectorVTInfo _> {
1239 def rr : AVX512BI<opc, MRMSrcReg,
1240 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2),
1241 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1242 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2)))],
1243 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1245 def rm : AVX512BI<opc, MRMSrcMem,
1246 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2),
1247 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1248 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1249 (_.VT (bitconvert (_.LdFrag addr:$src2)))))],
1250 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1251 def rrk : AVX512BI<opc, MRMSrcReg,
1252 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1253 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1254 "$dst {${mask}}, $src1, $src2}"),
1255 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1256 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))))],
1257 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1259 def rmk : AVX512BI<opc, MRMSrcMem,
1260 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1261 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1262 "$dst {${mask}}, $src1, $src2}"),
1263 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1264 (OpNode (_.VT _.RC:$src1),
1266 (_.LdFrag addr:$src2))))))],
1267 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1270 multiclass avx512_icmp_packed_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
1271 X86VectorVTInfo _> :
1272 avx512_icmp_packed<opc, OpcodeStr, OpNode, _> {
1273 let mayLoad = 1 in {
1274 def rmb : AVX512BI<opc, MRMSrcMem,
1275 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2),
1276 !strconcat(OpcodeStr, "\t{${src2}", _.BroadcastStr, ", $src1, $dst",
1277 "|$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1278 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1279 (X86VBroadcast (_.ScalarLdFrag addr:$src2))))],
1280 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1281 def rmbk : AVX512BI<opc, MRMSrcMem,
1282 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1283 _.ScalarMemOp:$src2),
1284 !strconcat(OpcodeStr,
1285 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1286 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1287 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1288 (OpNode (_.VT _.RC:$src1),
1290 (_.ScalarLdFrag addr:$src2)))))],
1291 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1295 multiclass avx512_icmp_packed_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
1296 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1297 let Predicates = [prd] in
1298 defm Z : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info512>,
1301 let Predicates = [prd, HasVLX] in {
1302 defm Z256 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info256>,
1304 defm Z128 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info128>,
1309 multiclass avx512_icmp_packed_rmb_vl<bits<8> opc, string OpcodeStr,
1310 SDNode OpNode, AVX512VLVectorVTInfo VTInfo,
1312 let Predicates = [prd] in
1313 defm Z : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info512>,
1316 let Predicates = [prd, HasVLX] in {
1317 defm Z256 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info256>,
1319 defm Z128 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info128>,
1324 defm VPCMPEQB : avx512_icmp_packed_vl<0x74, "vpcmpeqb", X86pcmpeqm,
1325 avx512vl_i8_info, HasBWI>,
1328 defm VPCMPEQW : avx512_icmp_packed_vl<0x75, "vpcmpeqw", X86pcmpeqm,
1329 avx512vl_i16_info, HasBWI>,
1330 EVEX_CD8<16, CD8VF>;
1332 defm VPCMPEQD : avx512_icmp_packed_rmb_vl<0x76, "vpcmpeqd", X86pcmpeqm,
1333 avx512vl_i32_info, HasAVX512>,
1334 EVEX_CD8<32, CD8VF>;
1336 defm VPCMPEQQ : avx512_icmp_packed_rmb_vl<0x29, "vpcmpeqq", X86pcmpeqm,
1337 avx512vl_i64_info, HasAVX512>,
1338 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1340 defm VPCMPGTB : avx512_icmp_packed_vl<0x64, "vpcmpgtb", X86pcmpgtm,
1341 avx512vl_i8_info, HasBWI>,
1344 defm VPCMPGTW : avx512_icmp_packed_vl<0x65, "vpcmpgtw", X86pcmpgtm,
1345 avx512vl_i16_info, HasBWI>,
1346 EVEX_CD8<16, CD8VF>;
1348 defm VPCMPGTD : avx512_icmp_packed_rmb_vl<0x66, "vpcmpgtd", X86pcmpgtm,
1349 avx512vl_i32_info, HasAVX512>,
1350 EVEX_CD8<32, CD8VF>;
1352 defm VPCMPGTQ : avx512_icmp_packed_rmb_vl<0x37, "vpcmpgtq", X86pcmpgtm,
1353 avx512vl_i64_info, HasAVX512>,
1354 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1356 def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1357 (COPY_TO_REGCLASS (VPCMPGTDZrr
1358 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1359 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1361 def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1362 (COPY_TO_REGCLASS (VPCMPEQDZrr
1363 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1364 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1366 multiclass avx512_icmp_cc<bits<8> opc, string Suffix, SDNode OpNode,
1367 X86VectorVTInfo _> {
1368 def rri : AVX512AIi8<opc, MRMSrcReg,
1369 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, AVX512ICC:$cc),
1370 !strconcat("vpcmp${cc}", Suffix,
1371 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1372 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1374 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1376 def rmi : AVX512AIi8<opc, MRMSrcMem,
1377 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, AVX512ICC:$cc),
1378 !strconcat("vpcmp${cc}", Suffix,
1379 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1380 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1381 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1383 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1384 def rrik : AVX512AIi8<opc, MRMSrcReg,
1385 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1387 !strconcat("vpcmp${cc}", Suffix,
1388 "\t{$src2, $src1, $dst {${mask}}|",
1389 "$dst {${mask}}, $src1, $src2}"),
1390 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1391 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1393 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1395 def rmik : AVX512AIi8<opc, MRMSrcMem,
1396 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1398 !strconcat("vpcmp${cc}", Suffix,
1399 "\t{$src2, $src1, $dst {${mask}}|",
1400 "$dst {${mask}}, $src1, $src2}"),
1401 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1402 (OpNode (_.VT _.RC:$src1),
1403 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1405 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1407 // Accept explicit immediate argument form instead of comparison code.
1408 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1409 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
1410 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1411 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1412 "$dst, $src1, $src2, $cc}"),
1413 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1415 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
1416 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, u8imm:$cc),
1417 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1418 "$dst, $src1, $src2, $cc}"),
1419 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1420 def rrik_alt : AVX512AIi8<opc, MRMSrcReg,
1421 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1423 !strconcat("vpcmp", Suffix,
1424 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1425 "$dst {${mask}}, $src1, $src2, $cc}"),
1426 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1428 def rmik_alt : AVX512AIi8<opc, MRMSrcMem,
1429 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1431 !strconcat("vpcmp", Suffix,
1432 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1433 "$dst {${mask}}, $src1, $src2, $cc}"),
1434 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1438 multiclass avx512_icmp_cc_rmb<bits<8> opc, string Suffix, SDNode OpNode,
1439 X86VectorVTInfo _> :
1440 avx512_icmp_cc<opc, Suffix, OpNode, _> {
1441 def rmib : AVX512AIi8<opc, MRMSrcMem,
1442 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1444 !strconcat("vpcmp${cc}", Suffix,
1445 "\t{${src2}", _.BroadcastStr, ", $src1, $dst|",
1446 "$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1447 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1448 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1450 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1451 def rmibk : AVX512AIi8<opc, MRMSrcMem,
1452 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1453 _.ScalarMemOp:$src2, AVX512ICC:$cc),
1454 !strconcat("vpcmp${cc}", Suffix,
1455 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1456 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1457 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1458 (OpNode (_.VT _.RC:$src1),
1459 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1461 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1463 // Accept explicit immediate argument form instead of comparison code.
1464 let isAsmParserOnly = 1, hasSideEffects = 0, mayLoad = 1 in {
1465 def rmib_alt : AVX512AIi8<opc, MRMSrcMem,
1466 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1468 !strconcat("vpcmp", Suffix,
1469 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst|",
1470 "$dst, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1471 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1472 def rmibk_alt : AVX512AIi8<opc, MRMSrcMem,
1473 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1474 _.ScalarMemOp:$src2, u8imm:$cc),
1475 !strconcat("vpcmp", Suffix,
1476 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1477 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1478 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1482 multiclass avx512_icmp_cc_vl<bits<8> opc, string Suffix, SDNode OpNode,
1483 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1484 let Predicates = [prd] in
1485 defm Z : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info512>, EVEX_V512;
1487 let Predicates = [prd, HasVLX] in {
1488 defm Z256 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info256>, EVEX_V256;
1489 defm Z128 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info128>, EVEX_V128;
1493 multiclass avx512_icmp_cc_rmb_vl<bits<8> opc, string Suffix, SDNode OpNode,
1494 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1495 let Predicates = [prd] in
1496 defm Z : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info512>,
1499 let Predicates = [prd, HasVLX] in {
1500 defm Z256 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info256>,
1502 defm Z128 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info128>,
1507 defm VPCMPB : avx512_icmp_cc_vl<0x3F, "b", X86cmpm, avx512vl_i8_info,
1508 HasBWI>, EVEX_CD8<8, CD8VF>;
1509 defm VPCMPUB : avx512_icmp_cc_vl<0x3E, "ub", X86cmpmu, avx512vl_i8_info,
1510 HasBWI>, EVEX_CD8<8, CD8VF>;
1512 defm VPCMPW : avx512_icmp_cc_vl<0x3F, "w", X86cmpm, avx512vl_i16_info,
1513 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1514 defm VPCMPUW : avx512_icmp_cc_vl<0x3E, "uw", X86cmpmu, avx512vl_i16_info,
1515 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1517 defm VPCMPD : avx512_icmp_cc_rmb_vl<0x1F, "d", X86cmpm, avx512vl_i32_info,
1518 HasAVX512>, EVEX_CD8<32, CD8VF>;
1519 defm VPCMPUD : avx512_icmp_cc_rmb_vl<0x1E, "ud", X86cmpmu, avx512vl_i32_info,
1520 HasAVX512>, EVEX_CD8<32, CD8VF>;
1522 defm VPCMPQ : avx512_icmp_cc_rmb_vl<0x1F, "q", X86cmpm, avx512vl_i64_info,
1523 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1524 defm VPCMPUQ : avx512_icmp_cc_rmb_vl<0x1E, "uq", X86cmpmu, avx512vl_i64_info,
1525 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1527 // avx512_cmp_packed - compare packed instructions
1528 multiclass avx512_cmp_packed<RegisterClass KRC, RegisterClass RC,
1529 X86MemOperand x86memop, ValueType vt,
1530 string suffix, Domain d> {
1531 def rri : AVX512PIi8<0xC2, MRMSrcReg,
1532 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
1533 !strconcat("vcmp${cc}", suffix,
1534 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1535 [(set KRC:$dst, (X86cmpm (vt RC:$src1), (vt RC:$src2), imm:$cc))], d>;
1536 let hasSideEffects = 0 in
1537 def rrib: AVX512PIi8<0xC2, MRMSrcReg,
1538 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
1539 !strconcat("vcmp${cc}", suffix,
1540 "\t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
1542 def rmi : AVX512PIi8<0xC2, MRMSrcMem,
1543 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, AVXCC:$cc),
1544 !strconcat("vcmp${cc}", suffix,
1545 "\t{$src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
1547 (X86cmpm (vt RC:$src1), (memop addr:$src2), imm:$cc))], d>;
1549 // Accept explicit immediate argument form instead of comparison code.
1550 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1551 def rri_alt : AVX512PIi8<0xC2, MRMSrcReg,
1552 (outs KRC:$dst), (ins RC:$src1, RC:$src2, u8imm:$cc),
1553 !strconcat("vcmp", suffix,
1554 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
1556 def rmi_alt : AVX512PIi8<0xC2, MRMSrcMem,
1557 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, u8imm:$cc),
1558 !strconcat("vcmp", suffix,
1559 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
1563 defm VCMPPSZ : avx512_cmp_packed<VK16, VR512, f512mem, v16f32,
1564 "ps", SSEPackedSingle>, PS, EVEX_4V, EVEX_V512,
1565 EVEX_CD8<32, CD8VF>;
1566 defm VCMPPDZ : avx512_cmp_packed<VK8, VR512, f512mem, v8f64,
1567 "pd", SSEPackedDouble>, PD, EVEX_4V, VEX_W, EVEX_V512,
1568 EVEX_CD8<64, CD8VF>;
1570 def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
1571 (COPY_TO_REGCLASS (VCMPPSZrri
1572 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1573 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1575 def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1576 (COPY_TO_REGCLASS (VPCMPDZrri
1577 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1578 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1580 def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1581 (COPY_TO_REGCLASS (VPCMPUDZrri
1582 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1583 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1586 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
1587 (v16f32 VR512:$src2), i8immZExt5:$cc, (i16 -1),
1589 (COPY_TO_REGCLASS (VCMPPSZrrib VR512:$src1, VR512:$src2,
1590 (I8Imm imm:$cc)), GR16)>;
1592 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
1593 (v8f64 VR512:$src2), i8immZExt5:$cc, (i8 -1),
1595 (COPY_TO_REGCLASS (VCMPPDZrrib VR512:$src1, VR512:$src2,
1596 (I8Imm imm:$cc)), GR8)>;
1598 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
1599 (v16f32 VR512:$src2), i8immZExt5:$cc, (i16 -1),
1601 (COPY_TO_REGCLASS (VCMPPSZrri VR512:$src1, VR512:$src2,
1602 (I8Imm imm:$cc)), GR16)>;
1604 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
1605 (v8f64 VR512:$src2), i8immZExt5:$cc, (i8 -1),
1607 (COPY_TO_REGCLASS (VCMPPDZrri VR512:$src1, VR512:$src2,
1608 (I8Imm imm:$cc)), GR8)>;
1610 // Mask register copy, including
1611 // - copy between mask registers
1612 // - load/store mask registers
1613 // - copy from GPR to mask register and vice versa
1615 multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
1616 string OpcodeStr, RegisterClass KRC,
1617 ValueType vvt, ValueType ivt, X86MemOperand x86memop> {
1618 let hasSideEffects = 0 in {
1619 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1620 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1622 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
1623 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1624 [(set KRC:$dst, (vvt (bitconvert (ivt (load addr:$src)))))]>;
1626 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
1627 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1628 [(store KRC:$src, addr:$dst)]>;
1632 multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
1634 RegisterClass KRC, RegisterClass GRC> {
1635 let hasSideEffects = 0 in {
1636 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
1637 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1638 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
1639 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1643 let Predicates = [HasDQI] in
1644 defm KMOVB : avx512_mask_mov<0x90, 0x90, 0x91, "kmovb", VK8, v8i1, i8,
1646 avx512_mask_mov_gpr<0x92, 0x93, "kmovb", VK8, GR32>,
1649 let Predicates = [HasAVX512] in
1650 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16,
1652 avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
1655 let Predicates = [HasBWI] in {
1656 defm KMOVD : avx512_mask_mov<0x90, 0x90, 0x91, "kmovd", VK32, v32i1, i32,
1657 i32mem>, VEX, PD, VEX_W;
1658 defm KMOVD : avx512_mask_mov_gpr<0x92, 0x93, "kmovd", VK32, GR32>,
1662 let Predicates = [HasBWI] in {
1663 defm KMOVQ : avx512_mask_mov<0x90, 0x90, 0x91, "kmovq", VK64, v64i1, i64,
1664 i64mem>, VEX, PS, VEX_W;
1665 defm KMOVQ : avx512_mask_mov_gpr<0x92, 0x93, "kmovq", VK64, GR64>,
1669 // GR from/to mask register
1670 let Predicates = [HasDQI] in {
1671 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1672 (KMOVBkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit))>;
1673 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1674 (EXTRACT_SUBREG (KMOVBrk VK8:$src), sub_8bit)>;
1676 let Predicates = [HasAVX512] in {
1677 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
1678 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
1679 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
1680 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
1682 let Predicates = [HasBWI] in {
1683 def : Pat<(v32i1 (bitconvert (i32 GR32:$src))), (KMOVDkr GR32:$src)>;
1684 def : Pat<(i32 (bitconvert (v32i1 VK32:$src))), (KMOVDrk VK32:$src)>;
1686 let Predicates = [HasBWI] in {
1687 def : Pat<(v64i1 (bitconvert (i64 GR64:$src))), (KMOVQkr GR64:$src)>;
1688 def : Pat<(i64 (bitconvert (v64i1 VK64:$src))), (KMOVQrk VK64:$src)>;
1692 let Predicates = [HasDQI] in {
1693 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
1694 (KMOVBmk addr:$dst, VK8:$src)>;
1696 let Predicates = [HasAVX512] in {
1697 def : Pat<(store (i16 (bitconvert (v16i1 VK16:$src))), addr:$dst),
1698 (KMOVWmk addr:$dst, VK16:$src)>;
1699 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
1700 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>;
1701 def : Pat<(i1 (load addr:$src)),
1702 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK1)>;
1703 def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
1704 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK8)>;
1706 let Predicates = [HasBWI] in {
1707 def : Pat<(store (i32 (bitconvert (v32i1 VK32:$src))), addr:$dst),
1708 (KMOVDmk addr:$dst, VK32:$src)>;
1710 let Predicates = [HasBWI] in {
1711 def : Pat<(store (i64 (bitconvert (v64i1 VK64:$src))), addr:$dst),
1712 (KMOVQmk addr:$dst, VK64:$src)>;
1715 let Predicates = [HasAVX512] in {
1716 def : Pat<(i1 (trunc (i64 GR64:$src))),
1717 (COPY_TO_REGCLASS (KMOVWkr (AND32ri (EXTRACT_SUBREG $src, sub_32bit),
1720 def : Pat<(i1 (trunc (i32 GR32:$src))),
1721 (COPY_TO_REGCLASS (KMOVWkr (AND32ri $src, (i32 1))), VK1)>;
1723 def : Pat<(i1 (trunc (i8 GR8:$src))),
1725 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit), (i32 1))),
1727 def : Pat<(i1 (trunc (i16 GR16:$src))),
1729 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), $src, sub_16bit), (i32 1))),
1732 def : Pat<(i32 (zext VK1:$src)),
1733 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1))>;
1734 def : Pat<(i8 (zext VK1:$src)),
1737 (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)), sub_8bit)>;
1738 def : Pat<(i64 (zext VK1:$src)),
1739 (AND64ri8 (SUBREG_TO_REG (i64 0),
1740 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_32bit), (i64 1))>;
1741 def : Pat<(i16 (zext VK1:$src)),
1743 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)),
1745 def : Pat<(v16i1 (scalar_to_vector VK1:$src)),
1746 (COPY_TO_REGCLASS VK1:$src, VK16)>;
1747 def : Pat<(v8i1 (scalar_to_vector VK1:$src)),
1748 (COPY_TO_REGCLASS VK1:$src, VK8)>;
1750 let Predicates = [HasBWI] in {
1751 def : Pat<(v32i1 (scalar_to_vector VK1:$src)),
1752 (COPY_TO_REGCLASS VK1:$src, VK32)>;
1753 def : Pat<(v64i1 (scalar_to_vector VK1:$src)),
1754 (COPY_TO_REGCLASS VK1:$src, VK64)>;
1758 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1759 let Predicates = [HasAVX512] in {
1760 // GR from/to 8-bit mask without native support
1761 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1763 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
1765 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1767 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
1770 def : Pat<(i1 (X86Vextract VK16:$src, (iPTR 0))),
1771 (COPY_TO_REGCLASS VK16:$src, VK1)>;
1772 def : Pat<(i1 (X86Vextract VK8:$src, (iPTR 0))),
1773 (COPY_TO_REGCLASS VK8:$src, VK1)>;
1775 let Predicates = [HasBWI] in {
1776 def : Pat<(i1 (X86Vextract VK32:$src, (iPTR 0))),
1777 (COPY_TO_REGCLASS VK32:$src, VK1)>;
1778 def : Pat<(i1 (X86Vextract VK64:$src, (iPTR 0))),
1779 (COPY_TO_REGCLASS VK64:$src, VK1)>;
1782 // Mask unary operation
1784 multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
1785 RegisterClass KRC, SDPatternOperator OpNode,
1787 let Predicates = [prd] in
1788 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1789 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1790 [(set KRC:$dst, (OpNode KRC:$src))]>;
1793 multiclass avx512_mask_unop_all<bits<8> opc, string OpcodeStr,
1794 SDPatternOperator OpNode> {
1795 defm B : avx512_mask_unop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
1797 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
1798 HasAVX512>, VEX, PS;
1799 defm D : avx512_mask_unop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
1800 HasBWI>, VEX, PD, VEX_W;
1801 defm Q : avx512_mask_unop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
1802 HasBWI>, VEX, PS, VEX_W;
1805 defm KNOT : avx512_mask_unop_all<0x44, "knot", not>;
1807 multiclass avx512_mask_unop_int<string IntName, string InstName> {
1808 let Predicates = [HasAVX512] in
1809 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1811 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1812 (v16i1 (COPY_TO_REGCLASS GR16:$src, VK16))), GR16)>;
1814 defm : avx512_mask_unop_int<"knot", "KNOT">;
1816 let Predicates = [HasDQI] in
1817 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)), (KNOTBrr VK8:$src1)>;
1818 let Predicates = [HasAVX512] in
1819 def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
1820 let Predicates = [HasBWI] in
1821 def : Pat<(xor VK32:$src1, (v32i1 immAllOnesV)), (KNOTDrr VK32:$src1)>;
1822 let Predicates = [HasBWI] in
1823 def : Pat<(xor VK64:$src1, (v64i1 immAllOnesV)), (KNOTQrr VK64:$src1)>;
1825 // KNL does not support KMOVB, 8-bit mask is promoted to 16-bit
1826 let Predicates = [HasAVX512] in {
1827 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
1828 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
1830 def : Pat<(not VK8:$src),
1832 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
1835 // Mask binary operation
1836 // - KAND, KANDN, KOR, KXNOR, KXOR
1837 multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
1838 RegisterClass KRC, SDPatternOperator OpNode,
1840 let Predicates = [prd] in
1841 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1842 !strconcat(OpcodeStr,
1843 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1844 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
1847 multiclass avx512_mask_binop_all<bits<8> opc, string OpcodeStr,
1848 SDPatternOperator OpNode> {
1849 defm B : avx512_mask_binop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
1850 HasDQI>, VEX_4V, VEX_L, PD;
1851 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
1852 HasAVX512>, VEX_4V, VEX_L, PS;
1853 defm D : avx512_mask_binop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
1854 HasBWI>, VEX_4V, VEX_L, VEX_W, PD;
1855 defm Q : avx512_mask_binop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
1856 HasBWI>, VEX_4V, VEX_L, VEX_W, PS;
1859 def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
1860 def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
1862 let isCommutable = 1 in {
1863 defm KAND : avx512_mask_binop_all<0x41, "kand", and>;
1864 defm KOR : avx512_mask_binop_all<0x45, "kor", or>;
1865 defm KXNOR : avx512_mask_binop_all<0x46, "kxnor", xnor>;
1866 defm KXOR : avx512_mask_binop_all<0x47, "kxor", xor>;
1868 let isCommutable = 0 in
1869 defm KANDN : avx512_mask_binop_all<0x42, "kandn", andn>;
1871 def : Pat<(xor VK1:$src1, VK1:$src2),
1872 (COPY_TO_REGCLASS (KXORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1873 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1875 def : Pat<(or VK1:$src1, VK1:$src2),
1876 (COPY_TO_REGCLASS (KORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1877 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1879 def : Pat<(and VK1:$src1, VK1:$src2),
1880 (COPY_TO_REGCLASS (KANDWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1881 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1883 multiclass avx512_mask_binop_int<string IntName, string InstName> {
1884 let Predicates = [HasAVX512] in
1885 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1886 (i16 GR16:$src1), (i16 GR16:$src2)),
1887 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1888 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1889 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1892 defm : avx512_mask_binop_int<"kand", "KAND">;
1893 defm : avx512_mask_binop_int<"kandn", "KANDN">;
1894 defm : avx512_mask_binop_int<"kor", "KOR">;
1895 defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
1896 defm : avx512_mask_binop_int<"kxor", "KXOR">;
1898 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
1899 multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
1900 let Predicates = [HasAVX512] in
1901 def : Pat<(OpNode VK8:$src1, VK8:$src2),
1903 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
1904 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
1907 defm : avx512_binop_pat<and, KANDWrr>;
1908 defm : avx512_binop_pat<andn, KANDNWrr>;
1909 defm : avx512_binop_pat<or, KORWrr>;
1910 defm : avx512_binop_pat<xnor, KXNORWrr>;
1911 defm : avx512_binop_pat<xor, KXORWrr>;
1914 multiclass avx512_mask_unpck<bits<8> opc, string OpcodeStr,
1915 RegisterClass KRC> {
1916 let Predicates = [HasAVX512] in
1917 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1918 !strconcat(OpcodeStr,
1919 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1922 multiclass avx512_mask_unpck_bw<bits<8> opc, string OpcodeStr> {
1923 defm BW : avx512_mask_unpck<opc, !strconcat(OpcodeStr, "bw"), VK16>,
1927 defm KUNPCK : avx512_mask_unpck_bw<0x4b, "kunpck">;
1928 def : Pat<(v16i1 (concat_vectors (v8i1 VK8:$src1), (v8i1 VK8:$src2))),
1929 (KUNPCKBWrr (COPY_TO_REGCLASS VK8:$src2, VK16),
1930 (COPY_TO_REGCLASS VK8:$src1, VK16))>;
1933 multiclass avx512_mask_unpck_int<string IntName, string InstName> {
1934 let Predicates = [HasAVX512] in
1935 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_bw")
1936 (i16 GR16:$src1), (i16 GR16:$src2)),
1937 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"BWrr")
1938 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1939 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1941 defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
1944 multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1946 let Predicates = [HasAVX512], Defs = [EFLAGS] in
1947 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
1948 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
1949 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
1952 multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1953 defm W : avx512_mask_testop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1955 let Predicates = [HasDQI] in
1956 defm B : avx512_mask_testop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode>,
1958 let Predicates = [HasBWI] in {
1959 defm Q : avx512_mask_testop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode>,
1961 defm D : avx512_mask_testop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode>,
1966 defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
1968 def : Pat<(X86cmp VK1:$src1, (i1 0)),
1969 (KORTESTWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1970 (COPY_TO_REGCLASS VK1:$src1, VK16))>, Requires<[HasAVX512, NoDQI]>;
1972 def : Pat<(X86cmp VK1:$src1, (i1 0)),
1973 (KORTESTBrr (COPY_TO_REGCLASS VK1:$src1, VK8),
1974 (COPY_TO_REGCLASS VK1:$src1, VK8))>, Requires<[HasDQI]>;
1977 multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1979 let Predicates = [HasAVX512] in
1980 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, u8imm:$imm),
1981 !strconcat(OpcodeStr,
1982 "\t{$imm, $src, $dst|$dst, $src, $imm}"),
1983 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
1986 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
1988 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1990 let Predicates = [HasDQI] in
1991 defm B : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "b"), VK8, OpNode>,
1993 let Predicates = [HasBWI] in {
1994 defm Q : avx512_mask_shiftop<opc2, !strconcat(OpcodeStr, "q"), VK64, OpNode>,
1996 let Predicates = [HasDQI] in
1997 defm D : avx512_mask_shiftop<opc2, !strconcat(OpcodeStr, "d"), VK32, OpNode>,
2002 defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86vshli>;
2003 defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86vsrli>;
2005 // Mask setting all 0s or 1s
2006 multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
2007 let Predicates = [HasAVX512] in
2008 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
2009 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
2010 [(set KRC:$dst, (VT Val))]>;
2013 multiclass avx512_mask_setop_w<PatFrag Val> {
2014 defm B : avx512_mask_setop<VK8, v8i1, Val>;
2015 defm W : avx512_mask_setop<VK16, v16i1, Val>;
2018 defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
2019 defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
2021 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
2022 let Predicates = [HasAVX512] in {
2023 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
2024 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
2025 def : Pat<(i1 0), (COPY_TO_REGCLASS (KSET0W), VK1)>;
2026 def : Pat<(i1 1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
2027 def : Pat<(i1 -1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
2029 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
2030 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
2032 def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
2033 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
2035 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
2036 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
2038 let Predicates = [HasVLX] in {
2039 def : Pat<(v8i1 (insert_subvector undef, (v4i1 VK4:$src), (iPTR 0))),
2040 (v8i1 (COPY_TO_REGCLASS VK4:$src, VK8))>;
2041 def : Pat<(v8i1 (insert_subvector undef, (v2i1 VK2:$src), (iPTR 0))),
2042 (v8i1 (COPY_TO_REGCLASS VK2:$src, VK8))>;
2043 def : Pat<(v4i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
2044 (v4i1 (COPY_TO_REGCLASS VK8:$src, VK4))>;
2045 def : Pat<(v2i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
2046 (v2i1 (COPY_TO_REGCLASS VK8:$src, VK2))>;
2049 def : Pat<(v8i1 (X86vshli VK8:$src, (i8 imm:$imm))),
2050 (v8i1 (COPY_TO_REGCLASS
2051 (KSHIFTLWri (COPY_TO_REGCLASS VK8:$src, VK16),
2052 (I8Imm $imm)), VK8))>, Requires<[HasAVX512, NoDQI]>;
2054 def : Pat<(v8i1 (X86vsrli VK8:$src, (i8 imm:$imm))),
2055 (v8i1 (COPY_TO_REGCLASS
2056 (KSHIFTRWri (COPY_TO_REGCLASS VK8:$src, VK16),
2057 (I8Imm $imm)), VK8))>, Requires<[HasAVX512, NoDQI]>;
2058 //===----------------------------------------------------------------------===//
2059 // AVX-512 - Aligned and unaligned load and store
2062 multiclass avx512_load<bits<8> opc, string OpcodeStr, PatFrag ld_frag,
2063 RegisterClass KRC, RegisterClass RC,
2064 ValueType vt, ValueType zvt, X86MemOperand memop,
2065 Domain d, bit IsReMaterializable = 1> {
2066 let hasSideEffects = 0 in {
2067 def rr : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
2068 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [],
2070 def rrkz : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
2071 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
2072 "${dst} {${mask}} {z}, $src}"), [], d>, EVEX, EVEX_KZ;
2074 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable,
2075 SchedRW = [WriteLoad] in
2076 def rm : AVX512PI<opc, MRMSrcMem, (outs RC:$dst), (ins memop:$src),
2077 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2078 [(set RC:$dst, (vt (bitconvert (ld_frag addr:$src))))],
2081 let AddedComplexity = 20 in {
2082 let Constraints = "$src0 = $dst", hasSideEffects = 0 in {
2083 let hasSideEffects = 0 in
2084 def rrk : AVX512PI<opc, MRMSrcReg, (outs RC:$dst),
2085 (ins RC:$src0, KRC:$mask, RC:$src1),
2086 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
2087 "${dst} {${mask}}, $src1}"),
2088 [(set RC:$dst, (vt (vselect KRC:$mask,
2092 let mayLoad = 1, SchedRW = [WriteLoad] in
2093 def rmk : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
2094 (ins RC:$src0, KRC:$mask, memop:$src1),
2095 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
2096 "${dst} {${mask}}, $src1}"),
2099 (vt (bitconvert (ld_frag addr:$src1))),
2103 let mayLoad = 1, SchedRW = [WriteLoad] in
2104 def rmkz : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
2105 (ins KRC:$mask, memop:$src),
2106 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
2107 "${dst} {${mask}} {z}, $src}"),
2110 (vt (bitconvert (ld_frag addr:$src))),
2111 (vt (bitconvert (zvt immAllZerosV))))))],
2116 multiclass avx512_load_vl<bits<8> opc, string OpcodeStr, string ld_pat,
2117 string elty, string elsz, string vsz512,
2118 string vsz256, string vsz128, Domain d,
2119 Predicate prd, bit IsReMaterializable = 1> {
2120 let Predicates = [prd] in
2121 defm Z : avx512_load<opc, OpcodeStr,
2122 !cast<PatFrag>(ld_pat##"v"##vsz512##elty##elsz),
2123 !cast<RegisterClass>("VK"##vsz512##"WM"), VR512,
2124 !cast<ValueType>("v"##vsz512##elty##elsz), v16i32,
2125 !cast<X86MemOperand>(elty##"512mem"), d,
2126 IsReMaterializable>, EVEX_V512;
2128 let Predicates = [prd, HasVLX] in {
2129 defm Z256 : avx512_load<opc, OpcodeStr,
2130 !cast<PatFrag>(ld_pat##!if(!eq(elty,"f"),
2131 "v"##vsz256##elty##elsz, "v4i64")),
2132 !cast<RegisterClass>("VK"##vsz256##"WM"), VR256X,
2133 !cast<ValueType>("v"##vsz256##elty##elsz), v8i32,
2134 !cast<X86MemOperand>(elty##"256mem"), d,
2135 IsReMaterializable>, EVEX_V256;
2137 defm Z128 : avx512_load<opc, OpcodeStr,
2138 !cast<PatFrag>(ld_pat##!if(!eq(elty,"f"),
2139 "v"##vsz128##elty##elsz, "v2i64")),
2140 !cast<RegisterClass>("VK"##vsz128##"WM"), VR128X,
2141 !cast<ValueType>("v"##vsz128##elty##elsz), v4i32,
2142 !cast<X86MemOperand>(elty##"128mem"), d,
2143 IsReMaterializable>, EVEX_V128;
2148 multiclass avx512_store<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2149 ValueType OpVT, RegisterClass KRC, RegisterClass RC,
2150 X86MemOperand memop, Domain d> {
2151 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
2152 def rr_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst), (ins RC:$src),
2153 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [], d>,
2155 let Constraints = "$src1 = $dst" in
2156 def rrk_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
2157 (ins RC:$src1, KRC:$mask, RC:$src2),
2158 !strconcat(OpcodeStr,
2159 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>,
2161 def rrkz_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
2162 (ins KRC:$mask, RC:$src),
2163 !strconcat(OpcodeStr,
2164 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
2165 [], d>, EVEX, EVEX_KZ;
2167 let mayStore = 1 in {
2168 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
2169 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2170 [(st_frag (OpVT RC:$src), addr:$dst)], d>, EVEX;
2171 def mrk : AVX512PI<opc, MRMDestMem, (outs),
2172 (ins memop:$dst, KRC:$mask, RC:$src),
2173 !strconcat(OpcodeStr,
2174 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
2175 [], d>, EVEX, EVEX_K;
2180 multiclass avx512_store_vl<bits<8> opc, string OpcodeStr, string st_pat,
2181 string st_suff_512, string st_suff_256,
2182 string st_suff_128, string elty, string elsz,
2183 string vsz512, string vsz256, string vsz128,
2184 Domain d, Predicate prd> {
2185 let Predicates = [prd] in
2186 defm Z : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_512),
2187 !cast<ValueType>("v"##vsz512##elty##elsz),
2188 !cast<RegisterClass>("VK"##vsz512##"WM"), VR512,
2189 !cast<X86MemOperand>(elty##"512mem"), d>, EVEX_V512;
2191 let Predicates = [prd, HasVLX] in {
2192 defm Z256 : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_256),
2193 !cast<ValueType>("v"##vsz256##elty##elsz),
2194 !cast<RegisterClass>("VK"##vsz256##"WM"), VR256X,
2195 !cast<X86MemOperand>(elty##"256mem"), d>, EVEX_V256;
2197 defm Z128 : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_128),
2198 !cast<ValueType>("v"##vsz128##elty##elsz),
2199 !cast<RegisterClass>("VK"##vsz128##"WM"), VR128X,
2200 !cast<X86MemOperand>(elty##"128mem"), d>, EVEX_V128;
2204 defm VMOVAPS : avx512_load_vl<0x28, "vmovaps", "alignedload", "f", "32",
2205 "16", "8", "4", SSEPackedSingle, HasAVX512>,
2206 avx512_store_vl<0x29, "vmovaps", "alignedstore",
2207 "512", "256", "", "f", "32", "16", "8", "4",
2208 SSEPackedSingle, HasAVX512>,
2209 PS, EVEX_CD8<32, CD8VF>;
2211 defm VMOVAPD : avx512_load_vl<0x28, "vmovapd", "alignedload", "f", "64",
2212 "8", "4", "2", SSEPackedDouble, HasAVX512>,
2213 avx512_store_vl<0x29, "vmovapd", "alignedstore",
2214 "512", "256", "", "f", "64", "8", "4", "2",
2215 SSEPackedDouble, HasAVX512>,
2216 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2218 defm VMOVUPS : avx512_load_vl<0x10, "vmovups", "load", "f", "32",
2219 "16", "8", "4", SSEPackedSingle, HasAVX512>,
2220 avx512_store_vl<0x11, "vmovups", "store", "", "", "", "f", "32",
2221 "16", "8", "4", SSEPackedSingle, HasAVX512>,
2222 PS, EVEX_CD8<32, CD8VF>;
2224 defm VMOVUPD : avx512_load_vl<0x10, "vmovupd", "load", "f", "64",
2225 "8", "4", "2", SSEPackedDouble, HasAVX512, 0>,
2226 avx512_store_vl<0x11, "vmovupd", "store", "", "", "", "f", "64",
2227 "8", "4", "2", SSEPackedDouble, HasAVX512>,
2228 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2230 def: Pat<(v8f64 (int_x86_avx512_mask_loadu_pd_512 addr:$ptr,
2231 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
2232 (VMOVUPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2234 def: Pat<(v16f32 (int_x86_avx512_mask_loadu_ps_512 addr:$ptr,
2235 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
2236 (VMOVUPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2238 def: Pat<(v8f64 (int_x86_avx512_mask_load_pd_512 addr:$ptr,
2239 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
2240 (VMOVAPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2242 def: Pat<(v16f32 (int_x86_avx512_mask_load_ps_512 addr:$ptr,
2243 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
2244 (VMOVAPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2246 def: Pat<(v8f64 (int_x86_avx512_mask_load_pd_512 addr:$ptr,
2247 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
2248 (VMOVAPDZrm addr:$ptr)>;
2250 def: Pat<(v16f32 (int_x86_avx512_mask_load_ps_512 addr:$ptr,
2251 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
2252 (VMOVAPSZrm addr:$ptr)>;
2254 def: Pat<(int_x86_avx512_mask_storeu_ps_512 addr:$ptr, (v16f32 VR512:$src),
2256 (VMOVUPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2258 def: Pat<(int_x86_avx512_mask_storeu_pd_512 addr:$ptr, (v8f64 VR512:$src),
2260 (VMOVUPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2263 def: Pat<(int_x86_avx512_mask_store_ps_512 addr:$ptr, (v16f32 VR512:$src),
2265 (VMOVAPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2267 def: Pat<(int_x86_avx512_mask_store_pd_512 addr:$ptr, (v8f64 VR512:$src),
2269 (VMOVAPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2272 def: Pat<(masked_store addr:$ptr, VK8WM:$mask, (v8f32 VR256:$src)),
2273 (VMOVUPSZmrk addr:$ptr,
2274 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)),
2275 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256:$src, sub_ymm))>;
2277 def: Pat<(v8f32 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2278 (v8f32 (EXTRACT_SUBREG (v16f32 (VMOVUPSZrmkz
2279 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2281 def: Pat<(masked_store addr:$ptr, VK16WM:$mask, (v16f32 VR512:$src)),
2282 (VMOVUPSZmrk addr:$ptr, VK16WM:$mask, VR512:$src)>;
2284 def: Pat<(masked_store addr:$ptr, VK8WM:$mask, (v8f64 VR512:$src)),
2285 (VMOVUPDZmrk addr:$ptr, VK8WM:$mask, VR512:$src)>;
2287 def: Pat<(v16f32 (masked_load addr:$ptr, VK16WM:$mask, undef)),
2288 (VMOVUPSZrmkz VK16WM:$mask, addr:$ptr)>;
2290 def: Pat<(v16f32 (masked_load addr:$ptr, VK16WM:$mask,
2291 (bc_v16f32 (v16i32 immAllZerosV)))),
2292 (VMOVUPSZrmkz VK16WM:$mask, addr:$ptr)>;
2294 def: Pat<(v16f32 (masked_load addr:$ptr, VK16WM:$mask, (v16f32 VR512:$src0))),
2295 (VMOVUPSZrmk VR512:$src0, VK16WM:$mask, addr:$ptr)>;
2297 def: Pat<(v8f64 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2298 (VMOVUPDZrmkz VK8WM:$mask, addr:$ptr)>;
2300 def: Pat<(v8f64 (masked_load addr:$ptr, VK8WM:$mask,
2301 (bc_v8f64 (v16i32 immAllZerosV)))),
2302 (VMOVUPDZrmkz VK8WM:$mask, addr:$ptr)>;
2304 def: Pat<(v8f64 (masked_load addr:$ptr, VK8WM:$mask, (v8f64 VR512:$src0))),
2305 (VMOVUPDZrmk VR512:$src0, VK8WM:$mask, addr:$ptr)>;
2307 def: Pat<(v8f32 (masked_load addr:$ptr, VK8WM:$mask, (v8f32 VR256:$src0))),
2308 (v8f32 (EXTRACT_SUBREG (v16f32 (VMOVUPSZrmk
2309 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256:$src0, sub_ymm),
2310 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2312 defm VMOVDQA32 : avx512_load_vl<0x6F, "vmovdqa32", "alignedload", "i", "32",
2313 "16", "8", "4", SSEPackedInt, HasAVX512>,
2314 avx512_store_vl<0x7F, "vmovdqa32", "alignedstore",
2315 "512", "256", "", "i", "32", "16", "8", "4",
2316 SSEPackedInt, HasAVX512>,
2317 PD, EVEX_CD8<32, CD8VF>;
2319 defm VMOVDQA64 : avx512_load_vl<0x6F, "vmovdqa64", "alignedload", "i", "64",
2320 "8", "4", "2", SSEPackedInt, HasAVX512>,
2321 avx512_store_vl<0x7F, "vmovdqa64", "alignedstore",
2322 "512", "256", "", "i", "64", "8", "4", "2",
2323 SSEPackedInt, HasAVX512>,
2324 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2326 defm VMOVDQU8 : avx512_load_vl<0x6F, "vmovdqu8", "load", "i", "8",
2327 "64", "32", "16", SSEPackedInt, HasBWI>,
2328 avx512_store_vl<0x7F, "vmovdqu8", "store", "", "", "",
2329 "i", "8", "64", "32", "16", SSEPackedInt,
2330 HasBWI>, XD, EVEX_CD8<8, CD8VF>;
2332 defm VMOVDQU16 : avx512_load_vl<0x6F, "vmovdqu16", "load", "i", "16",
2333 "32", "16", "8", SSEPackedInt, HasBWI>,
2334 avx512_store_vl<0x7F, "vmovdqu16", "store", "", "", "",
2335 "i", "16", "32", "16", "8", SSEPackedInt,
2336 HasBWI>, XD, VEX_W, EVEX_CD8<16, CD8VF>;
2338 defm VMOVDQU32 : avx512_load_vl<0x6F, "vmovdqu32", "load", "i", "32",
2339 "16", "8", "4", SSEPackedInt, HasAVX512>,
2340 avx512_store_vl<0x7F, "vmovdqu32", "store", "", "", "",
2341 "i", "32", "16", "8", "4", SSEPackedInt,
2342 HasAVX512>, XS, EVEX_CD8<32, CD8VF>;
2344 defm VMOVDQU64 : avx512_load_vl<0x6F, "vmovdqu64", "load", "i", "64",
2345 "8", "4", "2", SSEPackedInt, HasAVX512>,
2346 avx512_store_vl<0x7F, "vmovdqu64", "store", "", "", "",
2347 "i", "64", "8", "4", "2", SSEPackedInt,
2348 HasAVX512>, XS, VEX_W, EVEX_CD8<64, CD8VF>;
2350 def: Pat<(v16i32 (int_x86_avx512_mask_loadu_d_512 addr:$ptr,
2351 (v16i32 immAllZerosV), GR16:$mask)),
2352 (VMOVDQU32Zrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2354 def: Pat<(v8i64 (int_x86_avx512_mask_loadu_q_512 addr:$ptr,
2355 (bc_v8i64 (v16i32 immAllZerosV)), GR8:$mask)),
2356 (VMOVDQU64Zrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2358 def: Pat<(int_x86_avx512_mask_storeu_d_512 addr:$ptr, (v16i32 VR512:$src),
2360 (VMOVDQU32Zmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2362 def: Pat<(int_x86_avx512_mask_storeu_q_512 addr:$ptr, (v8i64 VR512:$src),
2364 (VMOVDQU64Zmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2367 let AddedComplexity = 20 in {
2368 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src),
2369 (bc_v8i64 (v16i32 immAllZerosV)))),
2370 (VMOVDQU64Zrrkz VK8WM:$mask, VR512:$src)>;
2372 def : Pat<(v8i64 (vselect VK8WM:$mask, (bc_v8i64 (v16i32 immAllZerosV)),
2373 (v8i64 VR512:$src))),
2374 (VMOVDQU64Zrrkz (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$mask, VK16)),
2377 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src),
2378 (v16i32 immAllZerosV))),
2379 (VMOVDQU32Zrrkz VK16WM:$mask, VR512:$src)>;
2381 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 immAllZerosV),
2382 (v16i32 VR512:$src))),
2383 (VMOVDQU32Zrrkz (KNOTWrr VK16WM:$mask), VR512:$src)>;
2386 def: Pat<(v16i32 (masked_load addr:$ptr, VK16WM:$mask, (v16i32 immAllZerosV))),
2387 (VMOVDQU32Zrmkz VK16WM:$mask, addr:$ptr)>;
2389 def: Pat<(v16i32 (masked_load addr:$ptr, VK16WM:$mask, undef)),
2390 (VMOVDQU32Zrmkz VK16WM:$mask, addr:$ptr)>;
2392 def: Pat<(v16i32 (masked_load addr:$ptr, VK16WM:$mask, (v16i32 VR512:$src0))),
2393 (VMOVDQU32Zrmk VR512:$src0, VK16WM:$mask, addr:$ptr)>;
2395 def: Pat<(v8i64 (masked_load addr:$ptr, VK8WM:$mask,
2396 (bc_v8i64 (v16i32 immAllZerosV)))),
2397 (VMOVDQU64Zrmkz VK8WM:$mask, addr:$ptr)>;
2399 def: Pat<(v8i64 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2400 (VMOVDQU64Zrmkz VK8WM:$mask, addr:$ptr)>;
2402 def: Pat<(v8i64 (masked_load addr:$ptr, VK8WM:$mask, (v8i64 VR512:$src0))),
2403 (VMOVDQU64Zrmk VR512:$src0, VK8WM:$mask, addr:$ptr)>;
2405 def: Pat<(masked_store addr:$ptr, VK16WM:$mask, (v16i32 VR512:$src)),
2406 (VMOVDQU32Zmrk addr:$ptr, VK16WM:$mask, VR512:$src)>;
2408 def: Pat<(masked_store addr:$ptr, VK8WM:$mask, (v8i64 VR512:$src)),
2409 (VMOVDQU64Zmrk addr:$ptr, VK8WM:$mask, VR512:$src)>;
2412 def: Pat<(masked_store addr:$ptr, VK8WM:$mask, (v8i32 VR256:$src)),
2413 (VMOVDQU32Z256mrk addr:$ptr, VK8WM:$mask, VR256:$src)>;
2416 def: Pat<(masked_store addr:$ptr, VK8WM:$mask, (v8i32 VR256:$src)),
2417 (VMOVDQU32Zmrk addr:$ptr,
2418 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)),
2419 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256:$src, sub_ymm))>;
2421 def: Pat<(v8i32 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2422 (v8i32 (EXTRACT_SUBREG (v16i32 (VMOVDQU32Zrmkz
2423 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2426 // Move Int Doubleword to Packed Double Int
2428 def VMOVDI2PDIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
2429 "vmovd\t{$src, $dst|$dst, $src}",
2431 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
2433 def VMOVDI2PDIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
2434 "vmovd\t{$src, $dst|$dst, $src}",
2436 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
2437 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2438 def VMOV64toPQIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
2439 "vmovq\t{$src, $dst|$dst, $src}",
2441 (v2i64 (scalar_to_vector GR64:$src)))],
2442 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
2443 let isCodeGenOnly = 1 in {
2444 def VMOV64toSDZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
2445 "vmovq\t{$src, $dst|$dst, $src}",
2446 [(set FR64:$dst, (bitconvert GR64:$src))],
2447 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
2448 def VMOVSDto64Zrr : AVX512BI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
2449 "vmovq\t{$src, $dst|$dst, $src}",
2450 [(set GR64:$dst, (bitconvert FR64:$src))],
2451 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
2453 def VMOVSDto64Zmr : AVX512BI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
2454 "vmovq\t{$src, $dst|$dst, $src}",
2455 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
2456 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
2457 EVEX_CD8<64, CD8VT1>;
2459 // Move Int Doubleword to Single Scalar
2461 let isCodeGenOnly = 1 in {
2462 def VMOVDI2SSZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
2463 "vmovd\t{$src, $dst|$dst, $src}",
2464 [(set FR32X:$dst, (bitconvert GR32:$src))],
2465 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
2467 def VMOVDI2SSZrm : AVX512BI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
2468 "vmovd\t{$src, $dst|$dst, $src}",
2469 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
2470 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2473 // Move doubleword from xmm register to r/m32
2475 def VMOVPDI2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
2476 "vmovd\t{$src, $dst|$dst, $src}",
2477 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
2478 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
2480 def VMOVPDI2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
2481 (ins i32mem:$dst, VR128X:$src),
2482 "vmovd\t{$src, $dst|$dst, $src}",
2483 [(store (i32 (vector_extract (v4i32 VR128X:$src),
2484 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
2485 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2487 // Move quadword from xmm1 register to r/m64
2489 def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
2490 "vmovq\t{$src, $dst|$dst, $src}",
2491 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
2493 IIC_SSE_MOVD_ToGP>, PD, EVEX, VEX_LIG, VEX_W,
2494 Requires<[HasAVX512, In64BitMode]>;
2496 def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
2497 (ins i64mem:$dst, VR128X:$src),
2498 "vmovq\t{$src, $dst|$dst, $src}",
2499 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
2500 addr:$dst)], IIC_SSE_MOVDQ>,
2501 EVEX, PD, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>,
2502 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
2504 // Move Scalar Single to Double Int
2506 let isCodeGenOnly = 1 in {
2507 def VMOVSS2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst),
2509 "vmovd\t{$src, $dst|$dst, $src}",
2510 [(set GR32:$dst, (bitconvert FR32X:$src))],
2511 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
2512 def VMOVSS2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
2513 (ins i32mem:$dst, FR32X:$src),
2514 "vmovd\t{$src, $dst|$dst, $src}",
2515 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
2516 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2519 // Move Quadword Int to Packed Quadword Int
2521 def VMOVQI2PQIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst),
2523 "vmovq\t{$src, $dst|$dst, $src}",
2525 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
2526 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2528 //===----------------------------------------------------------------------===//
2529 // AVX-512 MOVSS, MOVSD
2530 //===----------------------------------------------------------------------===//
2532 multiclass avx512_move_scalar <string asm, RegisterClass RC,
2533 SDNode OpNode, ValueType vt,
2534 X86MemOperand x86memop, PatFrag mem_pat> {
2535 let hasSideEffects = 0 in {
2536 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
2537 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2538 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
2539 (scalar_to_vector RC:$src2))))],
2540 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
2541 let Constraints = "$src1 = $dst" in
2542 def rrk : SI<0x10, MRMSrcReg, (outs VR128X:$dst),
2543 (ins VR128X:$src1, VK1WM:$mask, RC:$src2, RC:$src3),
2545 "\t{$src3, $src2, $dst {${mask}}|$dst {${mask}}, $src2, $src3}"),
2546 [], IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG, EVEX_K;
2547 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2548 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2549 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
2551 let mayStore = 1 in {
2552 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
2553 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2554 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
2556 def mrk: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, VK1WM:$mask, RC:$src),
2557 !strconcat(asm, "\t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
2558 [], IIC_SSE_MOV_S_MR>,
2559 EVEX, VEX_LIG, EVEX_K;
2561 } //hasSideEffects = 0
2564 let ExeDomain = SSEPackedSingle in
2565 defm VMOVSSZ : avx512_move_scalar<"movss", FR32X, X86Movss, v4f32, f32mem,
2566 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
2568 let ExeDomain = SSEPackedDouble in
2569 defm VMOVSDZ : avx512_move_scalar<"movsd", FR64X, X86Movsd, v2f64, f64mem,
2570 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
2572 def : Pat<(f32 (X86select VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))),
2573 (COPY_TO_REGCLASS (VMOVSSZrrk (COPY_TO_REGCLASS FR32X:$src2, VR128X),
2574 VK1WM:$mask, (f32 (IMPLICIT_DEF)), FR32X:$src1), FR32X)>;
2576 def : Pat<(f64 (X86select VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))),
2577 (COPY_TO_REGCLASS (VMOVSDZrrk (COPY_TO_REGCLASS FR64X:$src2, VR128X),
2578 VK1WM:$mask, (f64 (IMPLICIT_DEF)), FR64X:$src1), FR64X)>;
2580 def : Pat<(int_x86_avx512_mask_store_ss addr:$dst, VR128X:$src, GR8:$mask),
2581 (VMOVSSZmrk addr:$dst, (i1 (COPY_TO_REGCLASS GR8:$mask, VK1WM)),
2582 (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2584 // For the disassembler
2585 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
2586 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2587 (ins VR128X:$src1, FR32X:$src2),
2588 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
2590 XS, EVEX_4V, VEX_LIG;
2591 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2592 (ins VR128X:$src1, FR64X:$src2),
2593 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
2595 XD, EVEX_4V, VEX_LIG, VEX_W;
2598 let Predicates = [HasAVX512] in {
2599 let AddedComplexity = 15 in {
2600 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
2601 // MOVS{S,D} to the lower bits.
2602 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
2603 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
2604 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
2605 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2606 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
2607 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2608 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
2609 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
2611 // Move low f32 and clear high bits.
2612 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
2613 (SUBREG_TO_REG (i32 0),
2614 (VMOVSSZrr (v4f32 (V_SET0)),
2615 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
2616 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
2617 (SUBREG_TO_REG (i32 0),
2618 (VMOVSSZrr (v4i32 (V_SET0)),
2619 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
2622 let AddedComplexity = 20 in {
2623 // MOVSSrm zeros the high parts of the register; represent this
2624 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2625 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
2626 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2627 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
2628 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2629 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
2630 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2632 // MOVSDrm zeros the high parts of the register; represent this
2633 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2634 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
2635 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2636 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
2637 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2638 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
2639 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2640 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
2641 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2642 def : Pat<(v2f64 (X86vzload addr:$src)),
2643 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2645 // Represent the same patterns above but in the form they appear for
2647 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2648 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
2649 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
2650 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2651 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
2652 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
2653 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2654 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
2655 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
2657 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2658 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
2659 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
2660 FR32X:$src)), sub_xmm)>;
2661 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2662 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
2663 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
2664 FR64X:$src)), sub_xmm)>;
2665 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
2666 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
2667 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
2669 // Move low f64 and clear high bits.
2670 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
2671 (SUBREG_TO_REG (i32 0),
2672 (VMOVSDZrr (v2f64 (V_SET0)),
2673 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
2675 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
2676 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
2677 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
2679 // Extract and store.
2680 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
2682 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
2683 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
2685 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
2687 // Shuffle with VMOVSS
2688 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
2689 (VMOVSSZrr (v4i32 VR128X:$src1),
2690 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
2691 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
2692 (VMOVSSZrr (v4f32 VR128X:$src1),
2693 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
2696 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
2697 (SUBREG_TO_REG (i32 0),
2698 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
2699 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
2701 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
2702 (SUBREG_TO_REG (i32 0),
2703 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
2704 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
2707 // Shuffle with VMOVSD
2708 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
2709 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2710 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
2711 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2712 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
2713 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2714 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
2715 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2718 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
2719 (SUBREG_TO_REG (i32 0),
2720 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
2721 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
2723 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
2724 (SUBREG_TO_REG (i32 0),
2725 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
2726 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
2729 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
2730 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2731 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
2732 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2733 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
2734 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2735 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
2736 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2739 let AddedComplexity = 15 in
2740 def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
2742 "vmovq\t{$src, $dst|$dst, $src}",
2743 [(set VR128X:$dst, (v2i64 (X86vzmovl
2744 (v2i64 VR128X:$src))))],
2745 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
2747 let AddedComplexity = 20 in
2748 def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
2750 "vmovq\t{$src, $dst|$dst, $src}",
2751 [(set VR128X:$dst, (v2i64 (X86vzmovl
2752 (loadv2i64 addr:$src))))],
2753 IIC_SSE_MOVDQ>, EVEX, VEX_W,
2754 EVEX_CD8<8, CD8VT8>;
2756 let Predicates = [HasAVX512] in {
2757 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
2758 let AddedComplexity = 20 in {
2759 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
2760 (VMOVDI2PDIZrm addr:$src)>;
2761 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
2762 (VMOV64toPQIZrr GR64:$src)>;
2763 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
2764 (VMOVDI2PDIZrr GR32:$src)>;
2766 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
2767 (VMOVDI2PDIZrm addr:$src)>;
2768 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
2769 (VMOVDI2PDIZrm addr:$src)>;
2770 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
2771 (VMOVZPQILo2PQIZrm addr:$src)>;
2772 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
2773 (VMOVZPQILo2PQIZrr VR128X:$src)>;
2774 def : Pat<(v2i64 (X86vzload addr:$src)),
2775 (VMOVZPQILo2PQIZrm addr:$src)>;
2778 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
2779 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2780 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
2781 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
2782 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
2783 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
2784 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
2787 def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
2788 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
2790 def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
2791 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
2793 def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
2794 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
2796 def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
2797 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
2799 //===----------------------------------------------------------------------===//
2800 // AVX-512 - Non-temporals
2801 //===----------------------------------------------------------------------===//
2802 let SchedRW = [WriteLoad] in {
2803 def VMOVNTDQAZrm : AVX512PI<0x2A, MRMSrcMem, (outs VR512:$dst),
2804 (ins i512mem:$src), "vmovntdqa\t{$src, $dst|$dst, $src}",
2805 [(set VR512:$dst, (int_x86_avx512_movntdqa addr:$src))],
2806 SSEPackedInt>, EVEX, T8PD, EVEX_V512,
2807 EVEX_CD8<64, CD8VF>;
2809 let Predicates = [HasAVX512, HasVLX] in {
2810 def VMOVNTDQAZ256rm : AVX512PI<0x2A, MRMSrcMem, (outs VR256X:$dst),
2812 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
2813 SSEPackedInt>, EVEX, T8PD, EVEX_V256,
2814 EVEX_CD8<64, CD8VF>;
2816 def VMOVNTDQAZ128rm : AVX512PI<0x2A, MRMSrcMem, (outs VR128X:$dst),
2818 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
2819 SSEPackedInt>, EVEX, T8PD, EVEX_V128,
2820 EVEX_CD8<64, CD8VF>;
2824 multiclass avx512_movnt<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2825 ValueType OpVT, RegisterClass RC, X86MemOperand memop,
2826 Domain d, InstrItinClass itin = IIC_SSE_MOVNT> {
2827 let SchedRW = [WriteStore], mayStore = 1,
2828 AddedComplexity = 400 in
2829 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
2830 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2831 [(st_frag (OpVT RC:$src), addr:$dst)], d, itin>, EVEX;
2834 multiclass avx512_movnt_vl<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2835 string elty, string elsz, string vsz512,
2836 string vsz256, string vsz128, Domain d,
2837 Predicate prd, InstrItinClass itin = IIC_SSE_MOVNT> {
2838 let Predicates = [prd] in
2839 defm Z : avx512_movnt<opc, OpcodeStr, st_frag,
2840 !cast<ValueType>("v"##vsz512##elty##elsz), VR512,
2841 !cast<X86MemOperand>(elty##"512mem"), d, itin>,
2844 let Predicates = [prd, HasVLX] in {
2845 defm Z256 : avx512_movnt<opc, OpcodeStr, st_frag,
2846 !cast<ValueType>("v"##vsz256##elty##elsz), VR256X,
2847 !cast<X86MemOperand>(elty##"256mem"), d, itin>,
2850 defm Z128 : avx512_movnt<opc, OpcodeStr, st_frag,
2851 !cast<ValueType>("v"##vsz128##elty##elsz), VR128X,
2852 !cast<X86MemOperand>(elty##"128mem"), d, itin>,
2857 defm VMOVNTDQ : avx512_movnt_vl<0xE7, "vmovntdq", alignednontemporalstore,
2858 "i", "64", "8", "4", "2", SSEPackedInt,
2859 HasAVX512>, PD, EVEX_CD8<64, CD8VF>;
2861 defm VMOVNTPD : avx512_movnt_vl<0x2B, "vmovntpd", alignednontemporalstore,
2862 "f", "64", "8", "4", "2", SSEPackedDouble,
2863 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2865 defm VMOVNTPS : avx512_movnt_vl<0x2B, "vmovntps", alignednontemporalstore,
2866 "f", "32", "16", "8", "4", SSEPackedSingle,
2867 HasAVX512>, PS, EVEX_CD8<32, CD8VF>;
2869 //===----------------------------------------------------------------------===//
2870 // AVX-512 - Integer arithmetic
2872 multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2873 X86VectorVTInfo _, OpndItins itins,
2874 bit IsCommutable = 0> {
2875 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
2876 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
2877 "$src2, $src1", "$src1, $src2",
2878 (_.VT (OpNode _.RC:$src1, _.RC:$src2)),
2879 "", itins.rr, IsCommutable>,
2880 AVX512BIBase, EVEX_4V;
2883 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
2884 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
2885 "$src2, $src1", "$src1, $src2",
2886 (_.VT (OpNode _.RC:$src1,
2887 (bitconvert (_.LdFrag addr:$src2)))),
2889 AVX512BIBase, EVEX_4V;
2892 multiclass avx512_binop_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
2893 X86VectorVTInfo _, OpndItins itins,
2894 bit IsCommutable = 0> :
2895 avx512_binop_rm<opc, OpcodeStr, OpNode, _, itins, IsCommutable> {
2897 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
2898 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
2899 "${src2}"##_.BroadcastStr##", $src1",
2900 "$src1, ${src2}"##_.BroadcastStr,
2901 (_.VT (OpNode _.RC:$src1,
2903 (_.ScalarLdFrag addr:$src2)))),
2905 AVX512BIBase, EVEX_4V, EVEX_B;
2908 multiclass avx512_binop_rm_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
2909 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
2910 Predicate prd, bit IsCommutable = 0> {
2911 let Predicates = [prd] in
2912 defm Z : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
2913 IsCommutable>, EVEX_V512;
2915 let Predicates = [prd, HasVLX] in {
2916 defm Z256 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
2917 IsCommutable>, EVEX_V256;
2918 defm Z128 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
2919 IsCommutable>, EVEX_V128;
2923 multiclass avx512_binop_rmb_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
2924 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
2925 Predicate prd, bit IsCommutable = 0> {
2926 let Predicates = [prd] in
2927 defm Z : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
2928 IsCommutable>, EVEX_V512;
2930 let Predicates = [prd, HasVLX] in {
2931 defm Z256 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
2932 IsCommutable>, EVEX_V256;
2933 defm Z128 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
2934 IsCommutable>, EVEX_V128;
2938 multiclass avx512_binop_rm_vl_q<bits<8> opc, string OpcodeStr, SDNode OpNode,
2939 OpndItins itins, Predicate prd,
2940 bit IsCommutable = 0> {
2941 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i64_info,
2942 itins, prd, IsCommutable>,
2943 VEX_W, EVEX_CD8<64, CD8VF>;
2946 multiclass avx512_binop_rm_vl_d<bits<8> opc, string OpcodeStr, SDNode OpNode,
2947 OpndItins itins, Predicate prd,
2948 bit IsCommutable = 0> {
2949 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i32_info,
2950 itins, prd, IsCommutable>, EVEX_CD8<32, CD8VF>;
2953 multiclass avx512_binop_rm_vl_w<bits<8> opc, string OpcodeStr, SDNode OpNode,
2954 OpndItins itins, Predicate prd,
2955 bit IsCommutable = 0> {
2956 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i16_info,
2957 itins, prd, IsCommutable>, EVEX_CD8<16, CD8VF>;
2960 multiclass avx512_binop_rm_vl_b<bits<8> opc, string OpcodeStr, SDNode OpNode,
2961 OpndItins itins, Predicate prd,
2962 bit IsCommutable = 0> {
2963 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i8_info,
2964 itins, prd, IsCommutable>, EVEX_CD8<8, CD8VF>;
2967 multiclass avx512_binop_rm_vl_dq<bits<8> opc_d, bits<8> opc_q, string OpcodeStr,
2968 SDNode OpNode, OpndItins itins, Predicate prd,
2969 bit IsCommutable = 0> {
2970 defm Q : avx512_binop_rm_vl_q<opc_q, OpcodeStr, OpNode, itins, prd,
2973 defm D : avx512_binop_rm_vl_d<opc_d, OpcodeStr, OpNode, itins, prd,
2977 multiclass avx512_binop_rm_vl_bw<bits<8> opc_b, bits<8> opc_w, string OpcodeStr,
2978 SDNode OpNode, OpndItins itins, Predicate prd,
2979 bit IsCommutable = 0> {
2980 defm W : avx512_binop_rm_vl_w<opc_w, OpcodeStr, OpNode, itins, prd,
2983 defm B : avx512_binop_rm_vl_b<opc_b, OpcodeStr, OpNode, itins, prd,
2987 multiclass avx512_binop_rm_vl_all<bits<8> opc_b, bits<8> opc_w,
2988 bits<8> opc_d, bits<8> opc_q,
2989 string OpcodeStr, SDNode OpNode,
2990 OpndItins itins, bit IsCommutable = 0> {
2991 defm NAME : avx512_binop_rm_vl_dq<opc_d, opc_q, OpcodeStr, OpNode,
2992 itins, HasAVX512, IsCommutable>,
2993 avx512_binop_rm_vl_bw<opc_b, opc_w, OpcodeStr, OpNode,
2994 itins, HasBWI, IsCommutable>;
2997 multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr, ValueType DstVT,
2998 ValueType SrcVT, RegisterClass KRC, RegisterClass RC,
2999 PatFrag memop_frag, X86MemOperand x86memop,
3000 PatFrag scalar_mfrag, X86MemOperand x86scalar_mop,
3001 string BrdcstStr, OpndItins itins, bit IsCommutable = 0> {
3002 let isCommutable = IsCommutable in
3004 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
3005 (ins RC:$src1, RC:$src2),
3006 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3008 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
3009 (ins KRC:$mask, RC:$src1, RC:$src2),
3010 !strconcat(OpcodeStr,
3011 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
3012 [], itins.rr>, EVEX_4V, EVEX_K;
3013 def rrkz : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
3014 (ins KRC:$mask, RC:$src1, RC:$src2),
3015 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}} {z}" ,
3016 "|$dst {${mask}} {z}, $src1, $src2}"),
3017 [], itins.rr>, EVEX_4V, EVEX_KZ;
3019 let mayLoad = 1 in {
3020 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
3021 (ins RC:$src1, x86memop:$src2),
3022 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3024 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
3025 (ins KRC:$mask, RC:$src1, x86memop:$src2),
3026 !strconcat(OpcodeStr,
3027 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
3028 [], itins.rm>, EVEX_4V, EVEX_K;
3029 def rmkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
3030 (ins KRC:$mask, RC:$src1, x86memop:$src2),
3031 !strconcat(OpcodeStr,
3032 "\t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
3033 [], itins.rm>, EVEX_4V, EVEX_KZ;
3034 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
3035 (ins RC:$src1, x86scalar_mop:$src2),
3036 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
3037 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
3038 [], itins.rm>, EVEX_4V, EVEX_B;
3039 def rmbk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
3040 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
3041 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
3042 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}",
3044 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_K;
3045 def rmbkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
3046 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
3047 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
3048 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
3050 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_KZ;
3054 defm VPADD : avx512_binop_rm_vl_all<0xFC, 0xFD, 0xFE, 0xD4, "vpadd", add,
3055 SSE_INTALU_ITINS_P, 1>;
3056 defm VPSUB : avx512_binop_rm_vl_all<0xF8, 0xF9, 0xFA, 0xFB, "vpsub", sub,
3057 SSE_INTALU_ITINS_P, 0>;
3058 defm VPMULLD : avx512_binop_rm_vl_d<0x40, "vpmull", mul,
3059 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3060 defm VPMULLW : avx512_binop_rm_vl_w<0xD5, "vpmull", mul,
3061 SSE_INTALU_ITINS_P, HasBWI, 1>;
3062 defm VPMULLQ : avx512_binop_rm_vl_q<0x40, "vpmull", mul,
3063 SSE_INTALU_ITINS_P, HasDQI, 1>, T8PD;
3065 defm VPMULDQZ : avx512_binop_rm2<0x28, "vpmuldq", v8i64, v16i32, VK8WM, VR512,
3066 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
3067 SSE_INTALU_ITINS_P, 1>, T8PD, EVEX_V512,
3068 EVEX_CD8<64, CD8VF>, VEX_W;
3070 defm VPMULUDQZ : avx512_binop_rm2<0xF4, "vpmuludq", v8i64, v16i32, VK8WM, VR512,
3071 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
3072 SSE_INTMUL_ITINS_P, 1>, EVEX_V512, EVEX_CD8<64, CD8VF>, VEX_W;
3074 def : Pat<(v8i64 (X86pmuludq (v16i32 VR512:$src1), (v16i32 VR512:$src2))),
3075 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
3077 def : Pat<(v8i64 (int_x86_avx512_mask_pmulu_dq_512 (v16i32 VR512:$src1),
3078 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
3079 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
3080 def : Pat<(v8i64 (int_x86_avx512_mask_pmul_dq_512 (v16i32 VR512:$src1),
3081 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
3082 (VPMULDQZrr VR512:$src1, VR512:$src2)>;
3084 defm VPMAXSB : avx512_binop_rm_vl_b<0x3C, "vpmaxs", X86smax,
3085 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3086 defm VPMAXSW : avx512_binop_rm_vl_w<0xEE, "vpmaxs", X86smax,
3087 SSE_INTALU_ITINS_P, HasBWI, 1>;
3088 defm VPMAXS : avx512_binop_rm_vl_dq<0x3D, 0x3D, "vpmaxs", X86smax,
3089 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3091 defm VPMAXUB : avx512_binop_rm_vl_b<0xDE, "vpmaxu", X86umax,
3092 SSE_INTALU_ITINS_P, HasBWI, 1>;
3093 defm VPMAXUW : avx512_binop_rm_vl_w<0x3E, "vpmaxu", X86umax,
3094 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3095 defm VPMAXU : avx512_binop_rm_vl_dq<0x3F, 0x3F, "vpmaxu", X86umax,
3096 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3098 defm VPMINSB : avx512_binop_rm_vl_b<0x38, "vpmins", X86smin,
3099 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3100 defm VPMINSW : avx512_binop_rm_vl_w<0xEA, "vpmins", X86smin,
3101 SSE_INTALU_ITINS_P, HasBWI, 1>;
3102 defm VPMINS : avx512_binop_rm_vl_dq<0x39, 0x39, "vpmins", X86smin,
3103 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3105 defm VPMINUB : avx512_binop_rm_vl_b<0xDA, "vpminu", X86umin,
3106 SSE_INTALU_ITINS_P, HasBWI, 1>;
3107 defm VPMINUW : avx512_binop_rm_vl_w<0x3A, "vpminu", X86umin,
3108 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3109 defm VPMINU : avx512_binop_rm_vl_dq<0x3B, 0x3B, "vpminu", X86umin,
3110 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3112 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxs_d_512 (v16i32 VR512:$src1),
3113 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
3114 (VPMAXSDZrr VR512:$src1, VR512:$src2)>;
3115 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxu_d_512 (v16i32 VR512:$src1),
3116 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
3117 (VPMAXUDZrr VR512:$src1, VR512:$src2)>;
3118 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxs_q_512 (v8i64 VR512:$src1),
3119 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
3120 (VPMAXSQZrr VR512:$src1, VR512:$src2)>;
3121 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxu_q_512 (v8i64 VR512:$src1),
3122 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
3123 (VPMAXUQZrr VR512:$src1, VR512:$src2)>;
3124 def : Pat <(v16i32 (int_x86_avx512_mask_pmins_d_512 (v16i32 VR512:$src1),
3125 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
3126 (VPMINSDZrr VR512:$src1, VR512:$src2)>;
3127 def : Pat <(v16i32 (int_x86_avx512_mask_pminu_d_512 (v16i32 VR512:$src1),
3128 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
3129 (VPMINUDZrr VR512:$src1, VR512:$src2)>;
3130 def : Pat <(v8i64 (int_x86_avx512_mask_pmins_q_512 (v8i64 VR512:$src1),
3131 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
3132 (VPMINSQZrr VR512:$src1, VR512:$src2)>;
3133 def : Pat <(v8i64 (int_x86_avx512_mask_pminu_q_512 (v8i64 VR512:$src1),
3134 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
3135 (VPMINUQZrr VR512:$src1, VR512:$src2)>;
3136 //===----------------------------------------------------------------------===//
3137 // AVX-512 - Unpack Instructions
3138 //===----------------------------------------------------------------------===//
3140 multiclass avx512_unpack_fp<bits<8> opc, SDNode OpNode, ValueType vt,
3141 PatFrag mem_frag, RegisterClass RC,
3142 X86MemOperand x86memop, string asm,
3144 def rr : AVX512PI<opc, MRMSrcReg,
3145 (outs RC:$dst), (ins RC:$src1, RC:$src2),
3147 (vt (OpNode RC:$src1, RC:$src2)))],
3149 def rm : AVX512PI<opc, MRMSrcMem,
3150 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
3152 (vt (OpNode RC:$src1,
3153 (bitconvert (mem_frag addr:$src2)))))],
3157 defm VUNPCKHPSZ: avx512_unpack_fp<0x15, X86Unpckh, v16f32, memopv8f64,
3158 VR512, f512mem, "vunpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3159 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
3160 defm VUNPCKHPDZ: avx512_unpack_fp<0x15, X86Unpckh, v8f64, memopv8f64,
3161 VR512, f512mem, "vunpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3162 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3163 defm VUNPCKLPSZ: avx512_unpack_fp<0x14, X86Unpckl, v16f32, memopv8f64,
3164 VR512, f512mem, "vunpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3165 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
3166 defm VUNPCKLPDZ: avx512_unpack_fp<0x14, X86Unpckl, v8f64, memopv8f64,
3167 VR512, f512mem, "vunpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3168 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3170 multiclass avx512_unpack_int<bits<8> opc, string OpcodeStr, SDNode OpNode,
3171 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
3172 X86MemOperand x86memop> {
3173 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
3174 (ins RC:$src1, RC:$src2),
3175 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3176 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
3177 IIC_SSE_UNPCK>, EVEX_4V;
3178 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
3179 (ins RC:$src1, x86memop:$src2),
3180 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3181 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1),
3182 (bitconvert (memop_frag addr:$src2)))))],
3183 IIC_SSE_UNPCK>, EVEX_4V;
3185 defm VPUNPCKLDQZ : avx512_unpack_int<0x62, "vpunpckldq", X86Unpckl, v16i32,
3186 VR512, memopv16i32, i512mem>, EVEX_V512,
3187 EVEX_CD8<32, CD8VF>;
3188 defm VPUNPCKLQDQZ : avx512_unpack_int<0x6C, "vpunpcklqdq", X86Unpckl, v8i64,
3189 VR512, memopv8i64, i512mem>, EVEX_V512,
3190 VEX_W, EVEX_CD8<64, CD8VF>;
3191 defm VPUNPCKHDQZ : avx512_unpack_int<0x6A, "vpunpckhdq", X86Unpckh, v16i32,
3192 VR512, memopv16i32, i512mem>, EVEX_V512,
3193 EVEX_CD8<32, CD8VF>;
3194 defm VPUNPCKHQDQZ : avx512_unpack_int<0x6D, "vpunpckhqdq", X86Unpckh, v8i64,
3195 VR512, memopv8i64, i512mem>, EVEX_V512,
3196 VEX_W, EVEX_CD8<64, CD8VF>;
3197 //===----------------------------------------------------------------------===//
3201 multiclass avx512_pshuf_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
3202 SDNode OpNode, PatFrag mem_frag,
3203 X86MemOperand x86memop, ValueType OpVT> {
3204 def ri : AVX512Ii8<opc, MRMSrcReg, (outs RC:$dst),
3205 (ins RC:$src1, u8imm:$src2),
3206 !strconcat(OpcodeStr,
3207 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3209 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
3211 def mi : AVX512Ii8<opc, MRMSrcMem, (outs RC:$dst),
3212 (ins x86memop:$src1, u8imm:$src2),
3213 !strconcat(OpcodeStr,
3214 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3216 (OpVT (OpNode (mem_frag addr:$src1),
3217 (i8 imm:$src2))))]>, EVEX;
3220 defm VPSHUFDZ : avx512_pshuf_imm<0x70, "vpshufd", VR512, X86PShufd, memopv16i32,
3221 i512mem, v16i32>, PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
3223 //===----------------------------------------------------------------------===//
3224 // AVX-512 Logical Instructions
3225 //===----------------------------------------------------------------------===//
3227 defm VPAND : avx512_binop_rm_vl_dq<0xDB, 0xDB, "vpand", and,
3228 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3229 defm VPOR : avx512_binop_rm_vl_dq<0xEB, 0xEB, "vpor", or,
3230 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3231 defm VPXOR : avx512_binop_rm_vl_dq<0xEF, 0xEF, "vpxor", xor,
3232 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3233 defm VPANDN : avx512_binop_rm_vl_dq<0xDF, 0xDF, "vpandn", X86andnp,
3234 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3236 //===----------------------------------------------------------------------===//
3237 // AVX-512 FP arithmetic
3238 //===----------------------------------------------------------------------===//
3240 multiclass avx512_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
3242 defm SSZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"), OpNode, FR32X,
3243 f32mem, itins.s, 0>, XS, EVEX_4V, VEX_LIG,
3244 EVEX_CD8<32, CD8VT1>;
3245 defm SDZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"), OpNode, FR64X,
3246 f64mem, itins.d, 0>, XD, VEX_W, EVEX_4V, VEX_LIG,
3247 EVEX_CD8<64, CD8VT1>;
3250 let isCommutable = 1 in {
3251 defm VADD : avx512_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>;
3252 defm VMUL : avx512_binop_s<0x59, "mul", fmul, SSE_ALU_ITINS_S>;
3253 defm VMIN : avx512_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>;
3254 defm VMAX : avx512_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>;
3256 let isCommutable = 0 in {
3257 defm VSUB : avx512_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>;
3258 defm VDIV : avx512_binop_s<0x5E, "div", fdiv, SSE_ALU_ITINS_S>;
3261 multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
3262 X86VectorVTInfo _, bit IsCommutable> {
3263 defm rr: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3264 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3265 "$src2, $src1", "$src1, $src2",
3266 (_.VT (OpNode _.RC:$src1, _.RC:$src2))>, EVEX_4V;
3267 let mayLoad = 1 in {
3268 defm rm: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3269 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
3270 "$src2, $src1", "$src1, $src2",
3271 (OpNode _.RC:$src1, (_.LdFrag addr:$src2))>, EVEX_4V;
3272 defm rmb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3273 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
3274 "${src2}"##_.BroadcastStr##", $src1",
3275 "$src1, ${src2}"##_.BroadcastStr,
3276 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3277 (_.ScalarLdFrag addr:$src2))))>,
3282 multiclass avx512_fp_binop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3283 bit IsCommutable = 0> {
3284 defm PSZ : avx512_fp_packed<opc, OpcodeStr, OpNode, v16f32_info,
3285 IsCommutable>, EVEX_V512, PS,
3286 EVEX_CD8<32, CD8VF>;
3287 defm PDZ : avx512_fp_packed<opc, OpcodeStr, OpNode, v8f64_info,
3288 IsCommutable>, EVEX_V512, PD, VEX_W,
3289 EVEX_CD8<64, CD8VF>;
3291 // Define only if AVX512VL feature is present.
3292 let Predicates = [HasVLX] in {
3293 defm PSZ128 : avx512_fp_packed<opc, OpcodeStr, OpNode, v4f32x_info,
3294 IsCommutable>, EVEX_V128, PS,
3295 EVEX_CD8<32, CD8VF>;
3296 defm PSZ256 : avx512_fp_packed<opc, OpcodeStr, OpNode, v8f32x_info,
3297 IsCommutable>, EVEX_V256, PS,
3298 EVEX_CD8<32, CD8VF>;
3299 defm PDZ128 : avx512_fp_packed<opc, OpcodeStr, OpNode, v2f64x_info,
3300 IsCommutable>, EVEX_V128, PD, VEX_W,
3301 EVEX_CD8<64, CD8VF>;
3302 defm PDZ256 : avx512_fp_packed<opc, OpcodeStr, OpNode, v4f64x_info,
3303 IsCommutable>, EVEX_V256, PD, VEX_W,
3304 EVEX_CD8<64, CD8VF>;
3308 defm VADD : avx512_fp_binop_p<0x58, "vadd", fadd, 1>;
3309 defm VMUL : avx512_fp_binop_p<0x59, "vmul", fmul, 1>;
3310 defm VMIN : avx512_fp_binop_p<0x5D, "vmin", X86fmin, 1>;
3311 defm VMAX : avx512_fp_binop_p<0x5F, "vmax", X86fmax, 1>;
3312 defm VSUB : avx512_fp_binop_p<0x5C, "vsub", fsub>;
3313 defm VDIV : avx512_fp_binop_p<0x5E, "vdiv", fdiv>;
3315 def : Pat<(v16f32 (int_x86_avx512_mask_max_ps_512 (v16f32 VR512:$src1),
3316 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
3317 (i16 -1), FROUND_CURRENT)),
3318 (VMAXPSZrr VR512:$src1, VR512:$src2)>;
3320 def : Pat<(v8f64 (int_x86_avx512_mask_max_pd_512 (v8f64 VR512:$src1),
3321 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
3322 (i8 -1), FROUND_CURRENT)),
3323 (VMAXPDZrr VR512:$src1, VR512:$src2)>;
3325 def : Pat<(v16f32 (int_x86_avx512_mask_min_ps_512 (v16f32 VR512:$src1),
3326 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
3327 (i16 -1), FROUND_CURRENT)),
3328 (VMINPSZrr VR512:$src1, VR512:$src2)>;
3330 def : Pat<(v8f64 (int_x86_avx512_mask_min_pd_512 (v8f64 VR512:$src1),
3331 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
3332 (i8 -1), FROUND_CURRENT)),
3333 (VMINPDZrr VR512:$src1, VR512:$src2)>;
3334 //===----------------------------------------------------------------------===//
3335 // AVX-512 VPTESTM instructions
3336 //===----------------------------------------------------------------------===//
3338 multiclass avx512_vptest<bits<8> opc, string OpcodeStr, RegisterClass KRC,
3339 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
3340 SDNode OpNode, ValueType vt> {
3341 def rr : AVX512PI<opc, MRMSrcReg,
3342 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
3343 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3344 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
3345 SSEPackedInt>, EVEX_4V;
3346 def rm : AVX512PI<opc, MRMSrcMem,
3347 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
3348 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3349 [(set KRC:$dst, (OpNode (vt RC:$src1),
3350 (bitconvert (memop_frag addr:$src2))))], SSEPackedInt>, EVEX_4V;
3353 defm VPTESTMDZ : avx512_vptest<0x27, "vptestmd", VK16, VR512, f512mem,
3354 memopv16i32, X86testm, v16i32>, T8PD, EVEX_V512,
3355 EVEX_CD8<32, CD8VF>;
3356 defm VPTESTMQZ : avx512_vptest<0x27, "vptestmq", VK8, VR512, f512mem,
3357 memopv8i64, X86testm, v8i64>, T8PD, EVEX_V512, VEX_W,
3358 EVEX_CD8<64, CD8VF>;
3360 let Predicates = [HasCDI] in {
3361 defm VPTESTNMDZ : avx512_vptest<0x27, "vptestnmd", VK16, VR512, f512mem,
3362 memopv16i32, X86testnm, v16i32>, T8XS, EVEX_V512,
3363 EVEX_CD8<32, CD8VF>;
3364 defm VPTESTNMQZ : avx512_vptest<0x27, "vptestnmq", VK8, VR512, f512mem,
3365 memopv8i64, X86testnm, v8i64>, T8XS, EVEX_V512, VEX_W,
3366 EVEX_CD8<64, CD8VF>;
3369 def : Pat <(i16 (int_x86_avx512_mask_ptestm_d_512 (v16i32 VR512:$src1),
3370 (v16i32 VR512:$src2), (i16 -1))),
3371 (COPY_TO_REGCLASS (VPTESTMDZrr VR512:$src1, VR512:$src2), GR16)>;
3373 def : Pat <(i8 (int_x86_avx512_mask_ptestm_q_512 (v8i64 VR512:$src1),
3374 (v8i64 VR512:$src2), (i8 -1))),
3375 (COPY_TO_REGCLASS (VPTESTMQZrr VR512:$src1, VR512:$src2), GR8)>;
3377 //===----------------------------------------------------------------------===//
3378 // AVX-512 Shift instructions
3379 //===----------------------------------------------------------------------===//
3380 multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
3381 string OpcodeStr, SDNode OpNode, X86VectorVTInfo _> {
3382 defm ri : AVX512_maskable<opc, ImmFormR, _, (outs _.RC:$dst),
3383 (ins _.RC:$src1, u8imm:$src2), OpcodeStr,
3384 "$src2, $src1", "$src1, $src2",
3385 (_.VT (OpNode _.RC:$src1, (i8 imm:$src2))),
3386 " ", SSE_INTSHIFT_ITINS_P.rr>, AVX512BIi8Base, EVEX_4V;
3387 defm mi : AVX512_maskable<opc, ImmFormM, _, (outs _.RC:$dst),
3388 (ins _.MemOp:$src1, u8imm:$src2), OpcodeStr,
3389 "$src2, $src1", "$src1, $src2",
3390 (_.VT (OpNode (_.MemOpFrag addr:$src1), (i8 imm:$src2))),
3391 " ", SSE_INTSHIFT_ITINS_P.rm>, AVX512BIi8Base, EVEX_4V;
3394 multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3395 ValueType SrcVT, PatFrag bc_frag, X86VectorVTInfo _> {
3396 // src2 is always 128-bit
3397 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3398 (ins _.RC:$src1, VR128X:$src2), OpcodeStr,
3399 "$src2, $src1", "$src1, $src2",
3400 (_.VT (OpNode _.RC:$src1, (SrcVT VR128X:$src2))),
3401 " ", SSE_INTSHIFT_ITINS_P.rr>, AVX512BIBase, EVEX_4V;
3402 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3403 (ins _.RC:$src1, i128mem:$src2), OpcodeStr,
3404 "$src2, $src1", "$src1, $src2",
3405 (_.VT (OpNode _.RC:$src1, (bc_frag (memopv2i64 addr:$src2)))),
3406 " ", SSE_INTSHIFT_ITINS_P.rm>, AVX512BIBase, EVEX_4V;
3409 multiclass avx512_shift_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
3410 ValueType SrcVT, PatFrag bc_frag, X86VectorVTInfo _> {
3411 defm Z : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag, _>, EVEX_V512;
3414 multiclass avx512_shift_types<bits<8> opcd, bits<8> opcq, string OpcodeStr,
3416 defm D : avx512_shift_sizes<opcd, OpcodeStr#"d", OpNode, v4i32, bc_v4i32,
3417 v16i32_info>, EVEX_CD8<32, CD8VQ>;
3418 defm Q : avx512_shift_sizes<opcq, OpcodeStr#"q", OpNode, v2i64, bc_v2i64,
3419 v8i64_info>, EVEX_CD8<64, CD8VQ>, VEX_W;
3422 defm VPSRLDZ : avx512_shift_rmi<0x72, MRM2r, MRM2m, "vpsrld", X86vsrli,
3424 EVEX_V512, EVEX_CD8<32, CD8VF>;
3425 defm VPSRLQZ : avx512_shift_rmi<0x73, MRM2r, MRM2m, "vpsrlq", X86vsrli,
3426 v8i64_info>, EVEX_V512,
3427 EVEX_CD8<64, CD8VF>, VEX_W;
3429 defm VPSLLDZ : avx512_shift_rmi<0x72, MRM6r, MRM6m, "vpslld", X86vshli,
3430 v16i32_info>, EVEX_V512,
3431 EVEX_CD8<32, CD8VF>;
3432 defm VPSLLQZ : avx512_shift_rmi<0x73, MRM6r, MRM6m, "vpsllq", X86vshli,
3433 v8i64_info>, EVEX_V512,
3434 EVEX_CD8<64, CD8VF>, VEX_W;
3436 defm VPSRADZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsrad", X86vsrai,
3438 EVEX_V512, EVEX_CD8<32, CD8VF>;
3439 defm VPSRAQZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsraq", X86vsrai,
3440 v8i64_info>, EVEX_V512,
3441 EVEX_CD8<64, CD8VF>, VEX_W;
3443 defm VPSLL : avx512_shift_types<0xF2, 0xF3, "vpsll", X86vshl>;
3444 defm VPSRA : avx512_shift_types<0xE2, 0xE2, "vpsra", X86vsra>;
3445 defm VPSRL : avx512_shift_types<0xD2, 0xD3, "vpsrl", X86vsrl>;
3447 //===-------------------------------------------------------------------===//
3448 // Variable Bit Shifts
3449 //===-------------------------------------------------------------------===//
3450 multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
3451 X86VectorVTInfo _> {
3452 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3453 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3454 "$src2, $src1", "$src1, $src2",
3455 (_.VT (OpNode _.RC:$src1, (_.VT _.RC:$src2))),
3456 " ", SSE_INTSHIFT_ITINS_P.rr>, AVX5128IBase, EVEX_4V;
3457 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3458 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
3459 "$src2, $src1", "$src1, $src2",
3460 (_.VT (OpNode _.RC:$src1, (_.MemOpFrag addr:$src2))),
3461 " ", SSE_INTSHIFT_ITINS_P.rm>, AVX5128IBase, EVEX_4V;
3464 multiclass avx512_var_shift_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
3465 AVX512VLVectorVTInfo _> {
3466 defm Z : avx512_var_shift<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
3469 multiclass avx512_var_shift_types<bits<8> opc, string OpcodeStr,
3471 defm D : avx512_var_shift_sizes<opc, OpcodeStr#"d", OpNode,
3472 avx512vl_i32_info>, EVEX_CD8<32, CD8VQ>;
3473 defm Q : avx512_var_shift_sizes<opc, OpcodeStr#"q", OpNode,
3474 avx512vl_i64_info>, EVEX_CD8<64, CD8VQ>, VEX_W;
3477 defm VPSLLV : avx512_var_shift_types<0x47, "vpsllv", shl>;
3478 defm VPSRAV : avx512_var_shift_types<0x46, "vpsrav", sra>;
3479 defm VPSRLV : avx512_var_shift_types<0x45, "vpsrlv", srl>;
3481 //===----------------------------------------------------------------------===//
3482 // AVX-512 - MOVDDUP
3483 //===----------------------------------------------------------------------===//
3485 multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT,
3486 X86MemOperand x86memop, PatFrag memop_frag> {
3487 def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3488 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3489 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX;
3490 def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3491 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3493 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX;
3496 defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, memopv8f64>,
3497 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3498 def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
3499 (VMOVDDUPZrm addr:$src)>;
3501 //===---------------------------------------------------------------------===//
3502 // Replicate Single FP - MOVSHDUP and MOVSLDUP
3503 //===---------------------------------------------------------------------===//
3504 multiclass avx512_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
3505 ValueType vt, RegisterClass RC, PatFrag mem_frag,
3506 X86MemOperand x86memop> {
3507 def rr : AVX512XSI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3508 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3509 [(set RC:$dst, (vt (OpNode RC:$src)))]>, EVEX;
3511 def rm : AVX512XSI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3512 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3513 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>, EVEX;
3516 defm VMOVSHDUPZ : avx512_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
3517 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
3518 EVEX_CD8<32, CD8VF>;
3519 defm VMOVSLDUPZ : avx512_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
3520 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
3521 EVEX_CD8<32, CD8VF>;
3523 def : Pat<(v16i32 (X86Movshdup VR512:$src)), (VMOVSHDUPZrr VR512:$src)>;
3524 def : Pat<(v16i32 (X86Movshdup (memopv16i32 addr:$src))),
3525 (VMOVSHDUPZrm addr:$src)>;
3526 def : Pat<(v16i32 (X86Movsldup VR512:$src)), (VMOVSLDUPZrr VR512:$src)>;
3527 def : Pat<(v16i32 (X86Movsldup (memopv16i32 addr:$src))),
3528 (VMOVSLDUPZrm addr:$src)>;
3530 //===----------------------------------------------------------------------===//
3531 // Move Low to High and High to Low packed FP Instructions
3532 //===----------------------------------------------------------------------===//
3533 def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
3534 (ins VR128X:$src1, VR128X:$src2),
3535 "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3536 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
3537 IIC_SSE_MOV_LH>, EVEX_4V;
3538 def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
3539 (ins VR128X:$src1, VR128X:$src2),
3540 "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3541 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
3542 IIC_SSE_MOV_LH>, EVEX_4V;
3544 let Predicates = [HasAVX512] in {
3546 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
3547 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
3548 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
3549 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
3552 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
3553 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
3556 //===----------------------------------------------------------------------===//
3557 // FMA - Fused Multiply Operations
3560 let Constraints = "$src1 = $dst" in {
3561 // Omitting the parameter OpNode (= null_frag) disables ISel pattern matching.
3562 multiclass avx512_fma3p_rm<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
3563 SDPatternOperator OpNode = null_frag> {
3564 defm r: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
3565 (ins _.RC:$src2, _.RC:$src3),
3566 OpcodeStr, "$src3, $src2", "$src2, $src3",
3567 (_.VT (OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3))>,
3571 defm m: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
3572 (ins _.RC:$src2, _.MemOp:$src3),
3573 OpcodeStr, "$src3, $src2", "$src2, $src3",
3574 (_.VT (OpNode _.RC:$src1, _.RC:$src2, (_.LdFrag addr:$src3)))>,
3577 defm mb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
3578 (ins _.RC:$src2, _.ScalarMemOp:$src3),
3579 OpcodeStr, !strconcat("${src3}", _.BroadcastStr,", $src2"), !strconcat("$src2, ${src3}", _.BroadcastStr ),
3580 (OpNode _.RC:$src1, _.RC:$src2,(_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3))))>,
3581 AVX512FMA3Base, EVEX_B;
3583 } // Constraints = "$src1 = $dst"
3585 let Constraints = "$src1 = $dst" in {
3586 // Omitting the parameter OpNode (= null_frag) disables ISel pattern matching.
3587 multiclass avx512_fma3_round_rrb<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
3588 SDPatternOperator OpNode> {
3589 defm rb: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
3590 (ins _.RC:$src2, _.RC:$src3, AVX512RC:$rc),
3591 OpcodeStr, "$rc, $src3, $src2", "$src2, $src3, $rc",
3592 (_.VT ( OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3, (i32 imm:$rc)))>,
3593 AVX512FMA3Base, EVEX_B, EVEX_RC;
3595 } // Constraints = "$src1 = $dst"
3597 multiclass avx512_fma3_round_forms<bits<8> opc213, string OpcodeStr,
3598 X86VectorVTInfo VTI, SDPatternOperator OpNode> {
3599 defm v213r : avx512_fma3_round_rrb<opc213, !strconcat(OpcodeStr, "213", VTI.Suffix),
3600 VTI, OpNode>, EVEX_CD8<VTI.EltSize, CD8VF>;
3603 multiclass avx512_fma3p_forms<bits<8> opc213, bits<8> opc231,
3604 string OpcodeStr, X86VectorVTInfo VTI,
3605 SDPatternOperator OpNode> {
3606 defm v213r : avx512_fma3p_rm<opc213, !strconcat(OpcodeStr, "213", VTI.Suffix),
3607 VTI, OpNode>, EVEX_CD8<VTI.EltSize, CD8VF>;
3609 defm v231r : avx512_fma3p_rm<opc231, !strconcat(OpcodeStr, "231", VTI.Suffix),
3610 VTI>, EVEX_CD8<VTI.EltSize, CD8VF>;
3613 multiclass avx512_fma3p<bits<8> opc213, bits<8> opc231,
3615 SDPatternOperator OpNode,
3616 SDPatternOperator OpNodeRnd> {
3617 let ExeDomain = SSEPackedSingle in {
3618 defm NAME##PSZ : avx512_fma3p_forms<opc213, opc231, OpcodeStr,
3619 v16f32_info, OpNode>,
3620 avx512_fma3_round_forms<opc213, OpcodeStr,
3621 v16f32_info, OpNodeRnd>, EVEX_V512;
3622 defm NAME##PSZ256 : avx512_fma3p_forms<opc213, opc231, OpcodeStr,
3623 v8f32x_info, OpNode>, EVEX_V256;
3624 defm NAME##PSZ128 : avx512_fma3p_forms<opc213, opc231, OpcodeStr,
3625 v4f32x_info, OpNode>, EVEX_V128;
3627 let ExeDomain = SSEPackedDouble in {
3628 defm NAME##PDZ : avx512_fma3p_forms<opc213, opc231, OpcodeStr,
3629 v8f64_info, OpNode>,
3630 avx512_fma3_round_forms<opc213, OpcodeStr,
3631 v8f64_info, OpNodeRnd>, EVEX_V512, VEX_W;
3632 defm NAME##PDZ256 : avx512_fma3p_forms<opc213, opc231, OpcodeStr,
3633 v4f64x_info, OpNode>, EVEX_V256, VEX_W;
3634 defm NAME##PDZ128 : avx512_fma3p_forms<opc213, opc231, OpcodeStr,
3635 v2f64x_info, OpNode>, EVEX_V128, VEX_W;
3639 defm VFMADD : avx512_fma3p<0xA8, 0xB8, "vfmadd", X86Fmadd, X86FmaddRnd>;
3640 defm VFMSUB : avx512_fma3p<0xAA, 0xBA, "vfmsub", X86Fmsub, X86FmsubRnd>;
3641 defm VFMADDSUB : avx512_fma3p<0xA6, 0xB6, "vfmaddsub", X86Fmaddsub, X86FmaddsubRnd>;
3642 defm VFMSUBADD : avx512_fma3p<0xA7, 0xB7, "vfmsubadd", X86Fmsubadd, X86FmsubaddRnd>;
3643 defm VFNMADD : avx512_fma3p<0xAC, 0xBC, "vfnmadd", X86Fnmadd, X86FnmaddRnd>;
3644 defm VFNMSUB : avx512_fma3p<0xAE, 0xBE, "vfnmsub", X86Fnmsub, X86FnmsubRnd>;
3646 let Constraints = "$src1 = $dst" in {
3647 multiclass avx512_fma3p_m132<bits<8> opc, string OpcodeStr, SDNode OpNode,
3648 X86VectorVTInfo _> {
3650 def m: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3651 (ins _.RC:$src1, _.RC:$src3, _.MemOp:$src2),
3652 !strconcat(OpcodeStr, "\t{$src2, $src3, $dst|$dst, $src3, $src2}"),
3653 [(set _.RC:$dst, (_.VT (OpNode _.RC:$src1, (_.MemOpFrag addr:$src2),
3655 def mb: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3656 (ins _.RC:$src1, _.RC:$src3, _.ScalarMemOp:$src2),
3657 !strconcat(OpcodeStr, "\t{${src2}", _.BroadcastStr,
3658 ", $src3, $dst|$dst, $src3, ${src2}", _.BroadcastStr, "}"),
3660 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3661 (_.ScalarLdFrag addr:$src2))),
3662 _.RC:$src3))]>, EVEX_B;
3664 } // Constraints = "$src1 = $dst"
3667 multiclass avx512_fma3p_m132_f<bits<8> opc,
3671 let ExeDomain = SSEPackedSingle in {
3672 defm NAME##PSZ : avx512_fma3p_m132<opc, OpcodeStr##ps,
3673 OpNode,v16f32_info>, EVEX_V512, EVEX_CD8<32, CD8VF>;
3674 defm NAME##PSZ256 : avx512_fma3p_m132<opc, OpcodeStr##ps,
3675 OpNode, v8f32x_info>, EVEX_V256, EVEX_CD8<32, CD8VF>;
3676 defm NAME##PSZ128 : avx512_fma3p_m132<opc, OpcodeStr##ps,
3677 OpNode, v4f32x_info>, EVEX_V128, EVEX_CD8<32, CD8VF>;
3679 let ExeDomain = SSEPackedDouble in {
3680 defm NAME##PDZ : avx512_fma3p_m132<opc, OpcodeStr##pd,
3681 OpNode, v8f64_info>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VF>;
3682 defm NAME##PDZ256 : avx512_fma3p_m132<opc, OpcodeStr##pd,
3683 OpNode, v4f64x_info>, EVEX_V256, VEX_W, EVEX_CD8<32, CD8VF>;
3684 defm NAME##PDZ128 : avx512_fma3p_m132<opc, OpcodeStr##pd,
3685 OpNode, v2f64x_info>, EVEX_V128, VEX_W, EVEX_CD8<32, CD8VF>;
3689 defm VFMADD132 : avx512_fma3p_m132_f<0x98, "vfmadd132", X86Fmadd>;
3690 defm VFMSUB132 : avx512_fma3p_m132_f<0x9A, "vfmsub132", X86Fmsub>;
3691 defm VFMADDSUB132 : avx512_fma3p_m132_f<0x96, "vfmaddsub132", X86Fmaddsub>;
3692 defm VFMSUBADD132 : avx512_fma3p_m132_f<0x97, "vfmsubadd132", X86Fmsubadd>;
3693 defm VFNMADD132 : avx512_fma3p_m132_f<0x9C, "vfnmadd132", X86Fnmadd>;
3694 defm VFNMSUB132 : avx512_fma3p_m132_f<0x9E, "vfnmsub132", X86Fnmsub>;
3698 let Constraints = "$src1 = $dst" in {
3699 multiclass avx512_fma3s_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3700 RegisterClass RC, ValueType OpVT,
3701 X86MemOperand x86memop, Operand memop,
3703 let isCommutable = 1 in
3704 def r : AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
3705 (ins RC:$src1, RC:$src2, RC:$src3),
3706 !strconcat(OpcodeStr,
3707 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3709 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
3711 def m : AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
3712 (ins RC:$src1, RC:$src2, f128mem:$src3),
3713 !strconcat(OpcodeStr,
3714 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3716 (OpVT (OpNode RC:$src2, RC:$src1,
3717 (mem_frag addr:$src3))))]>;
3720 } // Constraints = "$src1 = $dst"
3722 defm VFMADDSSZ : avx512_fma3s_rm<0xA9, "vfmadd213ss", X86Fmadd, FR32X,
3723 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3724 defm VFMADDSDZ : avx512_fma3s_rm<0xA9, "vfmadd213sd", X86Fmadd, FR64X,
3725 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3726 defm VFMSUBSSZ : avx512_fma3s_rm<0xAB, "vfmsub213ss", X86Fmsub, FR32X,
3727 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3728 defm VFMSUBSDZ : avx512_fma3s_rm<0xAB, "vfmsub213sd", X86Fmsub, FR64X,
3729 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3730 defm VFNMADDSSZ : avx512_fma3s_rm<0xAD, "vfnmadd213ss", X86Fnmadd, FR32X,
3731 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3732 defm VFNMADDSDZ : avx512_fma3s_rm<0xAD, "vfnmadd213sd", X86Fnmadd, FR64X,
3733 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3734 defm VFNMSUBSSZ : avx512_fma3s_rm<0xAF, "vfnmsub213ss", X86Fnmsub, FR32X,
3735 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3736 defm VFNMSUBSDZ : avx512_fma3s_rm<0xAF, "vfnmsub213sd", X86Fnmsub, FR64X,
3737 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3739 //===----------------------------------------------------------------------===//
3740 // AVX-512 Scalar convert from sign integer to float/double
3741 //===----------------------------------------------------------------------===//
3743 multiclass avx512_vcvtsi<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3744 X86MemOperand x86memop, string asm> {
3745 let hasSideEffects = 0 in {
3746 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
3747 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
3750 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
3751 (ins DstRC:$src1, x86memop:$src),
3752 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
3754 } // hasSideEffects = 0
3756 let Predicates = [HasAVX512] in {
3757 defm VCVTSI2SSZ : avx512_vcvtsi<0x2A, GR32, FR32X, i32mem, "cvtsi2ss{l}">,
3758 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3759 defm VCVTSI642SSZ : avx512_vcvtsi<0x2A, GR64, FR32X, i64mem, "cvtsi2ss{q}">,
3760 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3761 defm VCVTSI2SDZ : avx512_vcvtsi<0x2A, GR32, FR64X, i32mem, "cvtsi2sd{l}">,
3762 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3763 defm VCVTSI642SDZ : avx512_vcvtsi<0x2A, GR64, FR64X, i64mem, "cvtsi2sd{q}">,
3764 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3766 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
3767 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3768 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
3769 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3770 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
3771 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3772 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
3773 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3775 def : Pat<(f32 (sint_to_fp GR32:$src)),
3776 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
3777 def : Pat<(f32 (sint_to_fp GR64:$src)),
3778 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
3779 def : Pat<(f64 (sint_to_fp GR32:$src)),
3780 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
3781 def : Pat<(f64 (sint_to_fp GR64:$src)),
3782 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
3784 defm VCVTUSI2SSZ : avx512_vcvtsi<0x7B, GR32, FR32X, i32mem, "cvtusi2ss{l}">,
3785 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3786 defm VCVTUSI642SSZ : avx512_vcvtsi<0x7B, GR64, FR32X, i64mem, "cvtusi2ss{q}">,
3787 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3788 defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, GR32, FR64X, i32mem, "cvtusi2sd{l}">,
3789 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3790 defm VCVTUSI642SDZ : avx512_vcvtsi<0x7B, GR64, FR64X, i64mem, "cvtusi2sd{q}">,
3791 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3793 def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
3794 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3795 def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
3796 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3797 def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
3798 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3799 def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
3800 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3802 def : Pat<(f32 (uint_to_fp GR32:$src)),
3803 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
3804 def : Pat<(f32 (uint_to_fp GR64:$src)),
3805 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
3806 def : Pat<(f64 (uint_to_fp GR32:$src)),
3807 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
3808 def : Pat<(f64 (uint_to_fp GR64:$src)),
3809 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
3812 //===----------------------------------------------------------------------===//
3813 // AVX-512 Scalar convert from float/double to integer
3814 //===----------------------------------------------------------------------===//
3815 multiclass avx512_cvt_s_int<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3816 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
3818 let hasSideEffects = 0 in {
3819 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3820 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
3821 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG,
3822 Requires<[HasAVX512]>;
3824 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
3825 !strconcat(asm,"\t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG,
3826 Requires<[HasAVX512]>;
3827 } // hasSideEffects = 0
3829 let Predicates = [HasAVX512] in {
3830 // Convert float/double to signed/unsigned int 32/64
3831 defm VCVTSS2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
3832 ssmem, sse_load_f32, "cvtss2si">,
3833 XS, EVEX_CD8<32, CD8VT1>;
3834 defm VCVTSS2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse_cvtss2si64,
3835 ssmem, sse_load_f32, "cvtss2si">,
3836 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
3837 defm VCVTSS2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtss2usi,
3838 ssmem, sse_load_f32, "cvtss2usi">,
3839 XS, EVEX_CD8<32, CD8VT1>;
3840 defm VCVTSS2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
3841 int_x86_avx512_cvtss2usi64, ssmem,
3842 sse_load_f32, "cvtss2usi">, XS, VEX_W,
3843 EVEX_CD8<32, CD8VT1>;
3844 defm VCVTSD2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
3845 sdmem, sse_load_f64, "cvtsd2si">,
3846 XD, EVEX_CD8<64, CD8VT1>;
3847 defm VCVTSD2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse2_cvtsd2si64,
3848 sdmem, sse_load_f64, "cvtsd2si">,
3849 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
3850 defm VCVTSD2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtsd2usi,
3851 sdmem, sse_load_f64, "cvtsd2usi">,
3852 XD, EVEX_CD8<64, CD8VT1>;
3853 defm VCVTSD2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
3854 int_x86_avx512_cvtsd2usi64, sdmem,
3855 sse_load_f64, "cvtsd2usi">, XD, VEX_W,
3856 EVEX_CD8<64, CD8VT1>;
3858 let isCodeGenOnly = 1 in {
3859 defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3860 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
3861 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
3862 defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3863 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
3864 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
3865 defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3866 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
3867 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
3868 defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3869 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
3870 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
3872 defm Int_VCVTUSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3873 int_x86_avx512_cvtusi2ss, i32mem, loadi32, "cvtusi2ss{l}",
3874 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
3875 defm Int_VCVTUSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3876 int_x86_avx512_cvtusi642ss, i64mem, loadi64, "cvtusi2ss{q}",
3877 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
3878 defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3879 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}",
3880 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
3881 defm Int_VCVTUSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3882 int_x86_avx512_cvtusi642sd, i64mem, loadi64, "cvtusi2sd{q}",
3883 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
3884 } // isCodeGenOnly = 1
3886 // Convert float/double to signed/unsigned int 32/64 with truncation
3887 let isCodeGenOnly = 1 in {
3888 defm Int_VCVTTSS2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse_cvttss2si,
3889 ssmem, sse_load_f32, "cvttss2si">,
3890 XS, EVEX_CD8<32, CD8VT1>;
3891 defm Int_VCVTTSS2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
3892 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
3893 "cvttss2si">, XS, VEX_W,
3894 EVEX_CD8<32, CD8VT1>;
3895 defm Int_VCVTTSD2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse2_cvttsd2si,
3896 sdmem, sse_load_f64, "cvttsd2si">, XD,
3897 EVEX_CD8<64, CD8VT1>;
3898 defm Int_VCVTTSD2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
3899 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
3900 "cvttsd2si">, XD, VEX_W,
3901 EVEX_CD8<64, CD8VT1>;
3902 defm Int_VCVTTSS2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
3903 int_x86_avx512_cvttss2usi, ssmem, sse_load_f32,
3904 "cvttss2usi">, XS, EVEX_CD8<32, CD8VT1>;
3905 defm Int_VCVTTSS2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
3906 int_x86_avx512_cvttss2usi64, ssmem,
3907 sse_load_f32, "cvttss2usi">, XS, VEX_W,
3908 EVEX_CD8<32, CD8VT1>;
3909 defm Int_VCVTTSD2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
3910 int_x86_avx512_cvttsd2usi,
3911 sdmem, sse_load_f64, "cvttsd2usi">, XD,
3912 EVEX_CD8<64, CD8VT1>;
3913 defm Int_VCVTTSD2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
3914 int_x86_avx512_cvttsd2usi64, sdmem,
3915 sse_load_f64, "cvttsd2usi">, XD, VEX_W,
3916 EVEX_CD8<64, CD8VT1>;
3917 } // isCodeGenOnly = 1
3919 multiclass avx512_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3920 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
3922 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3923 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
3924 [(set DstRC:$dst, (OpNode SrcRC:$src))]>, EVEX;
3925 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3926 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
3927 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>, EVEX;
3930 defm VCVTTSS2SIZ : avx512_cvt_s<0x2C, FR32X, GR32, fp_to_sint, f32mem,
3931 loadf32, "cvttss2si">, XS,
3932 EVEX_CD8<32, CD8VT1>;
3933 defm VCVTTSS2USIZ : avx512_cvt_s<0x78, FR32X, GR32, fp_to_uint, f32mem,
3934 loadf32, "cvttss2usi">, XS,
3935 EVEX_CD8<32, CD8VT1>;
3936 defm VCVTTSS2SI64Z : avx512_cvt_s<0x2C, FR32X, GR64, fp_to_sint, f32mem,
3937 loadf32, "cvttss2si">, XS, VEX_W,
3938 EVEX_CD8<32, CD8VT1>;
3939 defm VCVTTSS2USI64Z : avx512_cvt_s<0x78, FR32X, GR64, fp_to_uint, f32mem,
3940 loadf32, "cvttss2usi">, XS, VEX_W,
3941 EVEX_CD8<32, CD8VT1>;
3942 defm VCVTTSD2SIZ : avx512_cvt_s<0x2C, FR64X, GR32, fp_to_sint, f64mem,
3943 loadf64, "cvttsd2si">, XD,
3944 EVEX_CD8<64, CD8VT1>;
3945 defm VCVTTSD2USIZ : avx512_cvt_s<0x78, FR64X, GR32, fp_to_uint, f64mem,
3946 loadf64, "cvttsd2usi">, XD,
3947 EVEX_CD8<64, CD8VT1>;
3948 defm VCVTTSD2SI64Z : avx512_cvt_s<0x2C, FR64X, GR64, fp_to_sint, f64mem,
3949 loadf64, "cvttsd2si">, XD, VEX_W,
3950 EVEX_CD8<64, CD8VT1>;
3951 defm VCVTTSD2USI64Z : avx512_cvt_s<0x78, FR64X, GR64, fp_to_uint, f64mem,
3952 loadf64, "cvttsd2usi">, XD, VEX_W,
3953 EVEX_CD8<64, CD8VT1>;
3955 //===----------------------------------------------------------------------===//
3956 // AVX-512 Convert form float to double and back
3957 //===----------------------------------------------------------------------===//
3958 let hasSideEffects = 0 in {
3959 def VCVTSS2SDZrr : AVX512XSI<0x5A, MRMSrcReg, (outs FR64X:$dst),
3960 (ins FR32X:$src1, FR32X:$src2),
3961 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3962 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
3964 def VCVTSS2SDZrm : AVX512XSI<0x5A, MRMSrcMem, (outs FR64X:$dst),
3965 (ins FR32X:$src1, f32mem:$src2),
3966 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3967 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
3968 EVEX_CD8<32, CD8VT1>;
3970 // Convert scalar double to scalar single
3971 def VCVTSD2SSZrr : AVX512XDI<0x5A, MRMSrcReg, (outs FR32X:$dst),
3972 (ins FR64X:$src1, FR64X:$src2),
3973 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3974 []>, EVEX_4V, VEX_LIG, VEX_W, Sched<[WriteCvtF2F]>;
3976 def VCVTSD2SSZrm : AVX512XDI<0x5A, MRMSrcMem, (outs FR32X:$dst),
3977 (ins FR64X:$src1, f64mem:$src2),
3978 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3979 []>, EVEX_4V, VEX_LIG, VEX_W,
3980 Sched<[WriteCvtF2FLd, ReadAfterLd]>, EVEX_CD8<64, CD8VT1>;
3983 def : Pat<(f64 (fextend FR32X:$src)), (VCVTSS2SDZrr FR32X:$src, FR32X:$src)>,
3984 Requires<[HasAVX512]>;
3985 def : Pat<(fextend (loadf32 addr:$src)),
3986 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512]>;
3988 def : Pat<(extloadf32 addr:$src),
3989 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>,
3990 Requires<[HasAVX512, OptForSize]>;
3992 def : Pat<(extloadf32 addr:$src),
3993 (VCVTSS2SDZrr (f32 (IMPLICIT_DEF)), (VMOVSSZrm addr:$src))>,
3994 Requires<[HasAVX512, OptForSpeed]>;
3996 def : Pat<(f32 (fround FR64X:$src)), (VCVTSD2SSZrr FR64X:$src, FR64X:$src)>,
3997 Requires<[HasAVX512]>;
3999 multiclass avx512_vcvt_fp_with_rc<bits<8> opc, string asm, RegisterClass SrcRC,
4000 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
4001 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
4003 let hasSideEffects = 0 in {
4004 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
4005 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4007 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
4008 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
4009 !strconcat(asm,"\t{$rc, $src, $dst|$dst, $src, $rc}"),
4010 [], d>, EVEX, EVEX_B, EVEX_RC;
4012 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
4013 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4015 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
4016 } // hasSideEffects = 0
4019 multiclass avx512_vcvt_fp<bits<8> opc, string asm, RegisterClass SrcRC,
4020 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
4021 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
4023 let hasSideEffects = 0 in {
4024 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
4025 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4027 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
4029 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
4030 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4032 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
4033 } // hasSideEffects = 0
4036 defm VCVTPD2PSZ : avx512_vcvt_fp_with_rc<0x5A, "vcvtpd2ps", VR512, VR256X, fround,
4037 memopv8f64, f512mem, v8f32, v8f64,
4038 SSEPackedSingle>, EVEX_V512, VEX_W, PD,
4039 EVEX_CD8<64, CD8VF>;
4041 defm VCVTPS2PDZ : avx512_vcvt_fp<0x5A, "vcvtps2pd", VR256X, VR512, fextend,
4042 memopv4f64, f256mem, v8f64, v8f32,
4043 SSEPackedDouble>, EVEX_V512, PS,
4044 EVEX_CD8<32, CD8VH>;
4045 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
4046 (VCVTPS2PDZrm addr:$src)>;
4048 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
4049 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), (i32 FROUND_CURRENT))),
4050 (VCVTPD2PSZrr VR512:$src)>;
4052 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
4053 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), imm:$rc)),
4054 (VCVTPD2PSZrrb VR512:$src, imm:$rc)>;
4056 //===----------------------------------------------------------------------===//
4057 // AVX-512 Vector convert from sign integer to float/double
4058 //===----------------------------------------------------------------------===//
4060 defm VCVTDQ2PSZ : avx512_vcvt_fp_with_rc<0x5B, "vcvtdq2ps", VR512, VR512, sint_to_fp,
4061 memopv8i64, i512mem, v16f32, v16i32,
4062 SSEPackedSingle>, EVEX_V512, PS,
4063 EVEX_CD8<32, CD8VF>;
4065 defm VCVTDQ2PDZ : avx512_vcvt_fp<0xE6, "vcvtdq2pd", VR256X, VR512, sint_to_fp,
4066 memopv4i64, i256mem, v8f64, v8i32,
4067 SSEPackedDouble>, EVEX_V512, XS,
4068 EVEX_CD8<32, CD8VH>;
4070 defm VCVTTPS2DQZ : avx512_vcvt_fp<0x5B, "vcvttps2dq", VR512, VR512, fp_to_sint,
4071 memopv16f32, f512mem, v16i32, v16f32,
4072 SSEPackedSingle>, EVEX_V512, XS,
4073 EVEX_CD8<32, CD8VF>;
4075 defm VCVTTPD2DQZ : avx512_vcvt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint,
4076 memopv8f64, f512mem, v8i32, v8f64,
4077 SSEPackedDouble>, EVEX_V512, PD, VEX_W,
4078 EVEX_CD8<64, CD8VF>;
4080 defm VCVTTPS2UDQZ : avx512_vcvt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint,
4081 memopv16f32, f512mem, v16i32, v16f32,
4082 SSEPackedSingle>, EVEX_V512, PS,
4083 EVEX_CD8<32, CD8VF>;
4085 // cvttps2udq (src, 0, mask-all-ones, sae-current)
4086 def : Pat<(v16i32 (int_x86_avx512_mask_cvttps2udq_512 (v16f32 VR512:$src),
4087 (v16i32 immAllZerosV), (i16 -1), FROUND_CURRENT)),
4088 (VCVTTPS2UDQZrr VR512:$src)>;
4090 defm VCVTTPD2UDQZ : avx512_vcvt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint,
4091 memopv8f64, f512mem, v8i32, v8f64,
4092 SSEPackedDouble>, EVEX_V512, PS, VEX_W,
4093 EVEX_CD8<64, CD8VF>;
4095 // cvttpd2udq (src, 0, mask-all-ones, sae-current)
4096 def : Pat<(v8i32 (int_x86_avx512_mask_cvttpd2udq_512 (v8f64 VR512:$src),
4097 (v8i32 immAllZerosV), (i8 -1), FROUND_CURRENT)),
4098 (VCVTTPD2UDQZrr VR512:$src)>;
4100 defm VCVTUDQ2PDZ : avx512_vcvt_fp<0x7A, "vcvtudq2pd", VR256X, VR512, uint_to_fp,
4101 memopv4i64, f256mem, v8f64, v8i32,
4102 SSEPackedDouble>, EVEX_V512, XS,
4103 EVEX_CD8<32, CD8VH>;
4105 defm VCVTUDQ2PSZ : avx512_vcvt_fp_with_rc<0x7A, "vcvtudq2ps", VR512, VR512, uint_to_fp,
4106 memopv16i32, f512mem, v16f32, v16i32,
4107 SSEPackedSingle>, EVEX_V512, XD,
4108 EVEX_CD8<32, CD8VF>;
4110 def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
4111 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
4112 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
4114 def : Pat<(v4i32 (fp_to_uint (v4f32 VR128X:$src1))),
4115 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
4116 (v16f32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
4118 def : Pat<(v8f32 (uint_to_fp (v8i32 VR256X:$src1))),
4119 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
4120 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
4122 def : Pat<(v4f32 (uint_to_fp (v4i32 VR128X:$src1))),
4123 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
4124 (v16i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
4126 def : Pat<(v4f64 (uint_to_fp (v4i32 VR128X:$src1))),
4127 (EXTRACT_SUBREG (v8f64 (VCVTUDQ2PDZrr
4128 (v8i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_ymm)>;
4130 def : Pat<(v16f32 (int_x86_avx512_mask_cvtdq2ps_512 (v16i32 VR512:$src),
4131 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
4132 (VCVTDQ2PSZrrb VR512:$src, imm:$rc)>;
4133 def : Pat<(v8f64 (int_x86_avx512_mask_cvtdq2pd_512 (v8i32 VR256X:$src),
4134 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4135 (VCVTDQ2PDZrr VR256X:$src)>;
4136 def : Pat<(v16f32 (int_x86_avx512_mask_cvtudq2ps_512 (v16i32 VR512:$src),
4137 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
4138 (VCVTUDQ2PSZrrb VR512:$src, imm:$rc)>;
4139 def : Pat<(v8f64 (int_x86_avx512_mask_cvtudq2pd_512 (v8i32 VR256X:$src),
4140 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4141 (VCVTUDQ2PDZrr VR256X:$src)>;
4143 multiclass avx512_vcvt_fp2int<bits<8> opc, string asm, RegisterClass SrcRC,
4144 RegisterClass DstRC, PatFrag mem_frag,
4145 X86MemOperand x86memop, Domain d> {
4146 let hasSideEffects = 0 in {
4147 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
4148 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4150 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
4151 !strconcat(asm,"\t{$rc, $src, $dst|$dst, $src, $rc}"),
4152 [], d>, EVEX, EVEX_B, EVEX_RC;
4154 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
4155 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4157 } // hasSideEffects = 0
4160 defm VCVTPS2DQZ : avx512_vcvt_fp2int<0x5B, "vcvtps2dq", VR512, VR512,
4161 memopv16f32, f512mem, SSEPackedSingle>, PD,
4162 EVEX_V512, EVEX_CD8<32, CD8VF>;
4163 defm VCVTPD2DQZ : avx512_vcvt_fp2int<0xE6, "vcvtpd2dq", VR512, VR256X,
4164 memopv8f64, f512mem, SSEPackedDouble>, XD, VEX_W,
4165 EVEX_V512, EVEX_CD8<64, CD8VF>;
4167 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2dq_512 (v16f32 VR512:$src),
4168 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
4169 (VCVTPS2DQZrrb VR512:$src, imm:$rc)>;
4171 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2dq_512 (v8f64 VR512:$src),
4172 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
4173 (VCVTPD2DQZrrb VR512:$src, imm:$rc)>;
4175 defm VCVTPS2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtps2udq", VR512, VR512,
4176 memopv16f32, f512mem, SSEPackedSingle>,
4177 PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
4178 defm VCVTPD2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtpd2udq", VR512, VR256X,
4179 memopv8f64, f512mem, SSEPackedDouble>, VEX_W,
4180 PS, EVEX_V512, EVEX_CD8<64, CD8VF>;
4182 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2udq_512 (v16f32 VR512:$src),
4183 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
4184 (VCVTPS2UDQZrrb VR512:$src, imm:$rc)>;
4186 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2udq_512 (v8f64 VR512:$src),
4187 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
4188 (VCVTPD2UDQZrrb VR512:$src, imm:$rc)>;
4190 let Predicates = [HasAVX512] in {
4191 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
4192 (VCVTPD2PSZrm addr:$src)>;
4193 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
4194 (VCVTPS2PDZrm addr:$src)>;
4197 //===----------------------------------------------------------------------===//
4198 // Half precision conversion instructions
4199 //===----------------------------------------------------------------------===//
4200 multiclass avx512_cvtph2ps<RegisterClass destRC, RegisterClass srcRC,
4201 X86MemOperand x86memop> {
4202 def rr : AVX5128I<0x13, MRMSrcReg, (outs destRC:$dst), (ins srcRC:$src),
4203 "vcvtph2ps\t{$src, $dst|$dst, $src}",
4205 let hasSideEffects = 0, mayLoad = 1 in
4206 def rm : AVX5128I<0x13, MRMSrcMem, (outs destRC:$dst), (ins x86memop:$src),
4207 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, EVEX;
4210 multiclass avx512_cvtps2ph<RegisterClass destRC, RegisterClass srcRC,
4211 X86MemOperand x86memop> {
4212 def rr : AVX512AIi8<0x1D, MRMDestReg, (outs destRC:$dst),
4213 (ins srcRC:$src1, i32u8imm:$src2),
4214 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4216 let hasSideEffects = 0, mayStore = 1 in
4217 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
4218 (ins x86memop:$dst, srcRC:$src1, i32u8imm:$src2),
4219 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, EVEX;
4222 defm VCVTPH2PSZ : avx512_cvtph2ps<VR512, VR256X, f256mem>, EVEX_V512,
4223 EVEX_CD8<32, CD8VH>;
4224 defm VCVTPS2PHZ : avx512_cvtps2ph<VR256X, VR512, f256mem>, EVEX_V512,
4225 EVEX_CD8<32, CD8VH>;
4227 def : Pat<(v16i16 (int_x86_avx512_mask_vcvtps2ph_512 (v16f32 VR512:$src),
4228 imm:$rc, (bc_v16i16(v8i32 immAllZerosV)), (i16 -1))),
4229 (VCVTPS2PHZrr VR512:$src, imm:$rc)>;
4231 def : Pat<(v16f32 (int_x86_avx512_mask_vcvtph2ps_512 (v16i16 VR256X:$src),
4232 (bc_v16f32(v16i32 immAllZerosV)), (i16 -1), (i32 FROUND_CURRENT))),
4233 (VCVTPH2PSZrr VR256X:$src)>;
4235 let Defs = [EFLAGS], Predicates = [HasAVX512] in {
4236 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
4237 "ucomiss">, PS, EVEX, VEX_LIG,
4238 EVEX_CD8<32, CD8VT1>;
4239 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
4240 "ucomisd">, PD, EVEX,
4241 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4242 let Pattern = []<dag> in {
4243 defm VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, undef, v4f32, f128mem, load,
4244 "comiss">, PS, EVEX, VEX_LIG,
4245 EVEX_CD8<32, CD8VT1>;
4246 defm VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, undef, v2f64, f128mem, load,
4247 "comisd">, PD, EVEX,
4248 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4250 let isCodeGenOnly = 1 in {
4251 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
4252 load, "ucomiss">, PS, EVEX, VEX_LIG,
4253 EVEX_CD8<32, CD8VT1>;
4254 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
4255 load, "ucomisd">, PD, EVEX,
4256 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4258 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
4259 load, "comiss">, PS, EVEX, VEX_LIG,
4260 EVEX_CD8<32, CD8VT1>;
4261 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
4262 load, "comisd">, PD, EVEX,
4263 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4267 /// avx512_fp14_s rcp14ss, rcp14sd, rsqrt14ss, rsqrt14sd
4268 multiclass avx512_fp14_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
4269 X86MemOperand x86memop> {
4270 let hasSideEffects = 0 in {
4271 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4272 (ins RC:$src1, RC:$src2),
4273 !strconcat(OpcodeStr,
4274 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
4275 let mayLoad = 1 in {
4276 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4277 (ins RC:$src1, x86memop:$src2),
4278 !strconcat(OpcodeStr,
4279 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
4284 defm VRCP14SS : avx512_fp14_s<0x4D, "vrcp14ss", FR32X, f32mem>,
4285 EVEX_CD8<32, CD8VT1>;
4286 defm VRCP14SD : avx512_fp14_s<0x4D, "vrcp14sd", FR64X, f64mem>,
4287 VEX_W, EVEX_CD8<64, CD8VT1>;
4288 defm VRSQRT14SS : avx512_fp14_s<0x4F, "vrsqrt14ss", FR32X, f32mem>,
4289 EVEX_CD8<32, CD8VT1>;
4290 defm VRSQRT14SD : avx512_fp14_s<0x4F, "vrsqrt14sd", FR64X, f64mem>,
4291 VEX_W, EVEX_CD8<64, CD8VT1>;
4293 def : Pat <(v4f32 (int_x86_avx512_rcp14_ss (v4f32 VR128X:$src1),
4294 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
4295 (COPY_TO_REGCLASS (VRCP14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4296 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
4298 def : Pat <(v2f64 (int_x86_avx512_rcp14_sd (v2f64 VR128X:$src1),
4299 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
4300 (COPY_TO_REGCLASS (VRCP14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4301 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
4303 def : Pat <(v4f32 (int_x86_avx512_rsqrt14_ss (v4f32 VR128X:$src1),
4304 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
4305 (COPY_TO_REGCLASS (VRSQRT14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4306 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
4308 def : Pat <(v2f64 (int_x86_avx512_rsqrt14_sd (v2f64 VR128X:$src1),
4309 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
4310 (COPY_TO_REGCLASS (VRSQRT14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4311 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
4313 /// avx512_fp14_p rcp14ps, rcp14pd, rsqrt14ps, rsqrt14pd
4314 multiclass avx512_fp14_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
4315 X86VectorVTInfo _> {
4316 defm r: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4317 (ins _.RC:$src), OpcodeStr, "$src", "$src",
4318 (_.FloatVT (OpNode _.RC:$src))>, EVEX, T8PD;
4319 let mayLoad = 1 in {
4320 defm m: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4321 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4323 (bitconvert (_.LdFrag addr:$src))))>, EVEX, T8PD;
4324 defm mb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4325 (ins _.ScalarMemOp:$src), OpcodeStr,
4326 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
4328 (X86VBroadcast (_.ScalarLdFrag addr:$src))))>,
4333 multiclass avx512_fp14_p_vl_all<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4334 defm PSZ : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"), OpNode, v16f32_info>,
4335 EVEX_V512, EVEX_CD8<32, CD8VF>;
4336 defm PDZ : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"), OpNode, v8f64_info>,
4337 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
4339 // Define only if AVX512VL feature is present.
4340 let Predicates = [HasVLX] in {
4341 defm PSZ128 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"),
4342 OpNode, v4f32x_info>,
4343 EVEX_V128, EVEX_CD8<32, CD8VF>;
4344 defm PSZ256 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"),
4345 OpNode, v8f32x_info>,
4346 EVEX_V256, EVEX_CD8<32, CD8VF>;
4347 defm PDZ128 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"),
4348 OpNode, v2f64x_info>,
4349 EVEX_V128, VEX_W, EVEX_CD8<64, CD8VF>;
4350 defm PDZ256 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"),
4351 OpNode, v4f64x_info>,
4352 EVEX_V256, VEX_W, EVEX_CD8<64, CD8VF>;
4356 defm VRSQRT14 : avx512_fp14_p_vl_all<0x4E, "vrsqrt14", X86frsqrt>;
4357 defm VRCP14 : avx512_fp14_p_vl_all<0x4C, "vrcp14", X86frcp>;
4359 def : Pat <(v16f32 (int_x86_avx512_rsqrt14_ps_512 (v16f32 VR512:$src),
4360 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
4361 (VRSQRT14PSZr VR512:$src)>;
4362 def : Pat <(v8f64 (int_x86_avx512_rsqrt14_pd_512 (v8f64 VR512:$src),
4363 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4364 (VRSQRT14PDZr VR512:$src)>;
4366 def : Pat <(v16f32 (int_x86_avx512_rcp14_ps_512 (v16f32 VR512:$src),
4367 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
4368 (VRCP14PSZr VR512:$src)>;
4369 def : Pat <(v8f64 (int_x86_avx512_rcp14_pd_512 (v8f64 VR512:$src),
4370 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4371 (VRCP14PDZr VR512:$src)>;
4373 /// avx512_fp28_s rcp28ss, rcp28sd, rsqrt28ss, rsqrt28sd
4374 multiclass avx512_fp28_s<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
4377 defm r : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4378 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
4379 "$src2, $src1", "$src1, $src2",
4380 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
4381 (i32 FROUND_CURRENT))>;
4383 defm rb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4384 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
4385 "$src2, $src1", "$src1, $src2",
4386 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
4387 (i32 FROUND_NO_EXC)), "{sae}">, EVEX_B;
4389 defm m : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
4390 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
4391 "$src2, $src1", "$src1, $src2",
4392 (OpNode (_.VT _.RC:$src1),
4393 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
4394 (i32 FROUND_CURRENT))>;
4397 multiclass avx512_eri_s<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4398 defm SS : avx512_fp28_s<opc, OpcodeStr#"ss", f32x_info, OpNode>,
4399 EVEX_CD8<32, CD8VT1>;
4400 defm SD : avx512_fp28_s<opc, OpcodeStr#"sd", f64x_info, OpNode>,
4401 EVEX_CD8<64, CD8VT1>, VEX_W;
4404 let hasSideEffects = 0, Predicates = [HasERI] in {
4405 defm VRCP28 : avx512_eri_s<0xCB, "vrcp28", X86rcp28s>, T8PD, EVEX_4V;
4406 defm VRSQRT28 : avx512_eri_s<0xCD, "vrsqrt28", X86rsqrt28s>, T8PD, EVEX_4V;
4408 /// avx512_fp28_p rcp28ps, rcp28pd, rsqrt28ps, rsqrt28pd
4410 multiclass avx512_fp28_p<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
4413 defm r : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4414 (ins _.RC:$src), OpcodeStr, "$src", "$src",
4415 (OpNode (_.VT _.RC:$src), (i32 FROUND_CURRENT))>;
4417 defm rb : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4418 (ins _.RC:$src), OpcodeStr,
4420 (OpNode (_.VT _.RC:$src), (i32 FROUND_NO_EXC)),
4423 defm m : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4424 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4426 (bitconvert (_.LdFrag addr:$src))),
4427 (i32 FROUND_CURRENT))>;
4429 defm mb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4430 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4432 (X86VBroadcast (_.ScalarLdFrag addr:$src))),
4433 (i32 FROUND_CURRENT))>, EVEX_B;
4436 multiclass avx512_eri<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4437 defm PS : avx512_fp28_p<opc, OpcodeStr#"ps", v16f32_info, OpNode>,
4438 EVEX_CD8<32, CD8VF>;
4439 defm PD : avx512_fp28_p<opc, OpcodeStr#"pd", v8f64_info, OpNode>,
4440 VEX_W, EVEX_CD8<32, CD8VF>;
4443 let Predicates = [HasERI], hasSideEffects = 0 in {
4445 defm VRSQRT28 : avx512_eri<0xCC, "vrsqrt28", X86rsqrt28>, EVEX, EVEX_V512, T8PD;
4446 defm VRCP28 : avx512_eri<0xCA, "vrcp28", X86rcp28>, EVEX, EVEX_V512, T8PD;
4447 defm VEXP2 : avx512_eri<0xC8, "vexp2", X86exp2>, EVEX, EVEX_V512, T8PD;
4450 multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr,
4451 SDNode OpNode, X86VectorVTInfo _>{
4452 defm r: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4453 (ins _.RC:$src), OpcodeStr, "$src", "$src",
4454 (_.FloatVT (OpNode _.RC:$src))>, EVEX;
4455 let mayLoad = 1 in {
4456 defm m: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4457 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4459 (bitconvert (_.LdFrag addr:$src))))>, EVEX;
4461 defm mb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4462 (ins _.ScalarMemOp:$src), OpcodeStr,
4463 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
4465 (X86VBroadcast (_.ScalarLdFrag addr:$src))))>,
4470 multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,
4471 Intrinsic F32Int, Intrinsic F64Int,
4472 OpndItins itins_s, OpndItins itins_d> {
4473 def SSZr : SI<opc, MRMSrcReg, (outs FR32X:$dst),
4474 (ins FR32X:$src1, FR32X:$src2),
4475 !strconcat(OpcodeStr,
4476 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4477 [], itins_s.rr>, XS, EVEX_4V;
4478 let isCodeGenOnly = 1 in
4479 def SSZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
4480 (ins VR128X:$src1, VR128X:$src2),
4481 !strconcat(OpcodeStr,
4482 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4484 (F32Int VR128X:$src1, VR128X:$src2))],
4485 itins_s.rr>, XS, EVEX_4V;
4486 let mayLoad = 1 in {
4487 def SSZm : SI<opc, MRMSrcMem, (outs FR32X:$dst),
4488 (ins FR32X:$src1, f32mem:$src2),
4489 !strconcat(OpcodeStr,
4490 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4491 [], itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
4492 let isCodeGenOnly = 1 in
4493 def SSZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
4494 (ins VR128X:$src1, ssmem:$src2),
4495 !strconcat(OpcodeStr,
4496 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4498 (F32Int VR128X:$src1, sse_load_f32:$src2))],
4499 itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
4501 def SDZr : SI<opc, MRMSrcReg, (outs FR64X:$dst),
4502 (ins FR64X:$src1, FR64X:$src2),
4503 !strconcat(OpcodeStr,
4504 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
4506 let isCodeGenOnly = 1 in
4507 def SDZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
4508 (ins VR128X:$src1, VR128X:$src2),
4509 !strconcat(OpcodeStr,
4510 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4512 (F64Int VR128X:$src1, VR128X:$src2))],
4513 itins_s.rr>, XD, EVEX_4V, VEX_W;
4514 let mayLoad = 1 in {
4515 def SDZm : SI<opc, MRMSrcMem, (outs FR64X:$dst),
4516 (ins FR64X:$src1, f64mem:$src2),
4517 !strconcat(OpcodeStr,
4518 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
4519 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
4520 let isCodeGenOnly = 1 in
4521 def SDZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
4522 (ins VR128X:$src1, sdmem:$src2),
4523 !strconcat(OpcodeStr,
4524 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4526 (F64Int VR128X:$src1, sse_load_f64:$src2))]>,
4527 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
4531 multiclass avx512_sqrt_packed_all<bits<8> opc, string OpcodeStr,
4533 defm PSZ : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
4535 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
4536 defm PDZ : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
4538 EVEX_V512, VEX_W, PD, EVEX_CD8<64, CD8VF>;
4539 // Define only if AVX512VL feature is present.
4540 let Predicates = [HasVLX] in {
4541 defm PSZ128 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"),
4542 OpNode, v4f32x_info>,
4543 EVEX_V128, PS, EVEX_CD8<32, CD8VF>;
4544 defm PSZ256 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"),
4545 OpNode, v8f32x_info>,
4546 EVEX_V256, PS, EVEX_CD8<32, CD8VF>;
4547 defm PDZ128 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"),
4548 OpNode, v2f64x_info>,
4549 EVEX_V128, VEX_W, PD, EVEX_CD8<64, CD8VF>;
4550 defm PDZ256 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"),
4551 OpNode, v4f64x_info>,
4552 EVEX_V256, VEX_W, PD, EVEX_CD8<64, CD8VF>;
4556 defm VSQRT : avx512_sqrt_packed_all<0x51, "vsqrt", fsqrt>;
4558 defm VSQRT : avx512_sqrt_scalar<0x51, "sqrt",
4559 int_x86_avx512_sqrt_ss, int_x86_avx512_sqrt_sd,
4560 SSE_SQRTSS, SSE_SQRTSD>;
4562 let Predicates = [HasAVX512] in {
4563 def : Pat<(v16f32 (int_x86_avx512_sqrt_ps_512 (v16f32 VR512:$src1),
4564 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_CURRENT)),
4565 (VSQRTPSZr VR512:$src1)>;
4566 def : Pat<(v8f64 (int_x86_avx512_sqrt_pd_512 (v8f64 VR512:$src1),
4567 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_CURRENT)),
4568 (VSQRTPDZr VR512:$src1)>;
4570 def : Pat<(f32 (fsqrt FR32X:$src)),
4571 (VSQRTSSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
4572 def : Pat<(f32 (fsqrt (load addr:$src))),
4573 (VSQRTSSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
4574 Requires<[OptForSize]>;
4575 def : Pat<(f64 (fsqrt FR64X:$src)),
4576 (VSQRTSDZr (f64 (IMPLICIT_DEF)), FR64X:$src)>;
4577 def : Pat<(f64 (fsqrt (load addr:$src))),
4578 (VSQRTSDZm (f64 (IMPLICIT_DEF)), addr:$src)>,
4579 Requires<[OptForSize]>;
4581 def : Pat<(f32 (X86frsqrt FR32X:$src)),
4582 (VRSQRT14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
4583 def : Pat<(f32 (X86frsqrt (load addr:$src))),
4584 (VRSQRT14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
4585 Requires<[OptForSize]>;
4587 def : Pat<(f32 (X86frcp FR32X:$src)),
4588 (VRCP14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
4589 def : Pat<(f32 (X86frcp (load addr:$src))),
4590 (VRCP14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
4591 Requires<[OptForSize]>;
4593 def : Pat<(int_x86_sse_sqrt_ss VR128X:$src),
4594 (COPY_TO_REGCLASS (VSQRTSSZr (f32 (IMPLICIT_DEF)),
4595 (COPY_TO_REGCLASS VR128X:$src, FR32)),
4597 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
4598 (VSQRTSSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
4600 def : Pat<(int_x86_sse2_sqrt_sd VR128X:$src),
4601 (COPY_TO_REGCLASS (VSQRTSDZr (f64 (IMPLICIT_DEF)),
4602 (COPY_TO_REGCLASS VR128X:$src, FR64)),
4604 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
4605 (VSQRTSDZm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
4609 multiclass avx512_rndscale<bits<8> opc, string OpcodeStr,
4610 X86MemOperand x86memop, RegisterClass RC,
4611 PatFrag mem_frag, Domain d> {
4612 let ExeDomain = d in {
4613 // Intrinsic operation, reg.
4614 // Vector intrinsic operation, reg
4615 def r : AVX512AIi8<opc, MRMSrcReg,
4616 (outs RC:$dst), (ins RC:$src1, i32u8imm:$src2),
4617 !strconcat(OpcodeStr,
4618 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4621 // Vector intrinsic operation, mem
4622 def m : AVX512AIi8<opc, MRMSrcMem,
4623 (outs RC:$dst), (ins x86memop:$src1, i32u8imm:$src2),
4624 !strconcat(OpcodeStr,
4625 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4631 defm VRNDSCALEPSZ : avx512_rndscale<0x08, "vrndscaleps", f512mem, VR512,
4632 memopv16f32, SSEPackedSingle>, EVEX_V512,
4633 EVEX_CD8<32, CD8VF>;
4635 def : Pat<(v16f32 (int_x86_avx512_mask_rndscale_ps_512 (v16f32 VR512:$src1),
4636 imm:$src2, (v16f32 VR512:$src1), (i16 -1),
4638 (VRNDSCALEPSZr VR512:$src1, imm:$src2)>;
4641 defm VRNDSCALEPDZ : avx512_rndscale<0x09, "vrndscalepd", f512mem, VR512,
4642 memopv8f64, SSEPackedDouble>, EVEX_V512,
4643 VEX_W, EVEX_CD8<64, CD8VF>;
4645 def : Pat<(v8f64 (int_x86_avx512_mask_rndscale_pd_512 (v8f64 VR512:$src1),
4646 imm:$src2, (v8f64 VR512:$src1), (i8 -1),
4648 (VRNDSCALEPDZr VR512:$src1, imm:$src2)>;
4650 multiclass avx512_rndscale_scalar<bits<8> opc, string OpcodeStr,
4651 Operand x86memop, RegisterClass RC, Domain d> {
4652 let ExeDomain = d in {
4653 def r : AVX512AIi8<opc, MRMSrcReg,
4654 (outs RC:$dst), (ins RC:$src1, RC:$src2, i32u8imm:$src3),
4655 !strconcat(OpcodeStr,
4656 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4659 def m : AVX512AIi8<opc, MRMSrcMem,
4660 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i32u8imm:$src3),
4661 !strconcat(OpcodeStr,
4662 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4667 defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", ssmem, FR32X,
4668 SSEPackedSingle>, EVEX_CD8<32, CD8VT1>;
4670 defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", sdmem, FR64X,
4671 SSEPackedDouble>, EVEX_CD8<64, CD8VT1>;
4673 let Predicates = [HasAVX512] in {
4674 def : Pat<(ffloor FR32X:$src),
4675 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x1))>;
4676 def : Pat<(f64 (ffloor FR64X:$src)),
4677 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x1))>;
4678 def : Pat<(f32 (fnearbyint FR32X:$src)),
4679 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0xC))>;
4680 def : Pat<(f64 (fnearbyint FR64X:$src)),
4681 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0xC))>;
4682 def : Pat<(f32 (fceil FR32X:$src)),
4683 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x2))>;
4684 def : Pat<(f64 (fceil FR64X:$src)),
4685 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x2))>;
4686 def : Pat<(f32 (frint FR32X:$src)),
4687 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x4))>;
4688 def : Pat<(f64 (frint FR64X:$src)),
4689 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x4))>;
4690 def : Pat<(f32 (ftrunc FR32X:$src)),
4691 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x3))>;
4692 def : Pat<(f64 (ftrunc FR64X:$src)),
4693 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x3))>;
4696 def : Pat<(v16f32 (ffloor VR512:$src)),
4697 (VRNDSCALEPSZr VR512:$src, (i32 0x1))>;
4698 def : Pat<(v16f32 (fnearbyint VR512:$src)),
4699 (VRNDSCALEPSZr VR512:$src, (i32 0xC))>;
4700 def : Pat<(v16f32 (fceil VR512:$src)),
4701 (VRNDSCALEPSZr VR512:$src, (i32 0x2))>;
4702 def : Pat<(v16f32 (frint VR512:$src)),
4703 (VRNDSCALEPSZr VR512:$src, (i32 0x4))>;
4704 def : Pat<(v16f32 (ftrunc VR512:$src)),
4705 (VRNDSCALEPSZr VR512:$src, (i32 0x3))>;
4707 def : Pat<(v8f64 (ffloor VR512:$src)),
4708 (VRNDSCALEPDZr VR512:$src, (i32 0x1))>;
4709 def : Pat<(v8f64 (fnearbyint VR512:$src)),
4710 (VRNDSCALEPDZr VR512:$src, (i32 0xC))>;
4711 def : Pat<(v8f64 (fceil VR512:$src)),
4712 (VRNDSCALEPDZr VR512:$src, (i32 0x2))>;
4713 def : Pat<(v8f64 (frint VR512:$src)),
4714 (VRNDSCALEPDZr VR512:$src, (i32 0x4))>;
4715 def : Pat<(v8f64 (ftrunc VR512:$src)),
4716 (VRNDSCALEPDZr VR512:$src, (i32 0x3))>;
4718 //-------------------------------------------------
4719 // Integer truncate and extend operations
4720 //-------------------------------------------------
4722 multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr,
4723 RegisterClass dstRC, RegisterClass srcRC,
4724 RegisterClass KRC, X86MemOperand x86memop> {
4725 def rr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4727 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
4730 def rrk : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4731 (ins KRC:$mask, srcRC:$src),
4732 !strconcat(OpcodeStr,
4733 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
4736 def rrkz : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4737 (ins KRC:$mask, srcRC:$src),
4738 !strconcat(OpcodeStr,
4739 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
4742 def mr : AVX512XS8I<opc, MRMDestMem, (outs), (ins x86memop:$dst, srcRC:$src),
4743 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4746 def mrk : AVX512XS8I<opc, MRMDestMem, (outs),
4747 (ins x86memop:$dst, KRC:$mask, srcRC:$src),
4748 !strconcat(OpcodeStr, "\t{$src, $dst {${mask}}|${dst} {${mask}}, $src}"),
4752 defm VPMOVQB : avx512_trunc_sat<0x32, "vpmovqb", VR128X, VR512, VK8WM,
4753 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4754 defm VPMOVSQB : avx512_trunc_sat<0x22, "vpmovsqb", VR128X, VR512, VK8WM,
4755 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4756 defm VPMOVUSQB : avx512_trunc_sat<0x12, "vpmovusqb", VR128X, VR512, VK8WM,
4757 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4758 defm VPMOVQW : avx512_trunc_sat<0x34, "vpmovqw", VR128X, VR512, VK8WM,
4759 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4760 defm VPMOVSQW : avx512_trunc_sat<0x24, "vpmovsqw", VR128X, VR512, VK8WM,
4761 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4762 defm VPMOVUSQW : avx512_trunc_sat<0x14, "vpmovusqw", VR128X, VR512, VK8WM,
4763 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4764 defm VPMOVQD : avx512_trunc_sat<0x35, "vpmovqd", VR256X, VR512, VK8WM,
4765 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4766 defm VPMOVSQD : avx512_trunc_sat<0x25, "vpmovsqd", VR256X, VR512, VK8WM,
4767 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4768 defm VPMOVUSQD : avx512_trunc_sat<0x15, "vpmovusqd", VR256X, VR512, VK8WM,
4769 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4770 defm VPMOVDW : avx512_trunc_sat<0x33, "vpmovdw", VR256X, VR512, VK16WM,
4771 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4772 defm VPMOVSDW : avx512_trunc_sat<0x23, "vpmovsdw", VR256X, VR512, VK16WM,
4773 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4774 defm VPMOVUSDW : avx512_trunc_sat<0x13, "vpmovusdw", VR256X, VR512, VK16WM,
4775 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4776 defm VPMOVDB : avx512_trunc_sat<0x31, "vpmovdb", VR128X, VR512, VK16WM,
4777 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4778 defm VPMOVSDB : avx512_trunc_sat<0x21, "vpmovsdb", VR128X, VR512, VK16WM,
4779 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4780 defm VPMOVUSDB : avx512_trunc_sat<0x11, "vpmovusdb", VR128X, VR512, VK16WM,
4781 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4783 def : Pat<(v16i8 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQBrr VR512:$src)>;
4784 def : Pat<(v8i16 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQWrr VR512:$src)>;
4785 def : Pat<(v16i16 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDWrr VR512:$src)>;
4786 def : Pat<(v16i8 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDBrr VR512:$src)>;
4787 def : Pat<(v8i32 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQDrr VR512:$src)>;
4789 def : Pat<(v16i8 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
4790 (VPMOVDBrrkz VK16WM:$mask, VR512:$src)>;
4791 def : Pat<(v16i16 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
4792 (VPMOVDWrrkz VK16WM:$mask, VR512:$src)>;
4793 def : Pat<(v8i16 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
4794 (VPMOVQWrrkz VK8WM:$mask, VR512:$src)>;
4795 def : Pat<(v8i32 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
4796 (VPMOVQDrrkz VK8WM:$mask, VR512:$src)>;
4799 multiclass avx512_extend<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4800 RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode,
4801 PatFrag mem_frag, X86MemOperand x86memop,
4802 ValueType OpVT, ValueType InVT> {
4804 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4806 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4807 [(set DstRC:$dst, (OpVT (OpNode (InVT SrcRC:$src))))]>, EVEX;
4809 def rrk : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4810 (ins KRC:$mask, SrcRC:$src),
4811 !strconcat(OpcodeStr, "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
4814 def rrkz : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4815 (ins KRC:$mask, SrcRC:$src),
4816 !strconcat(OpcodeStr, "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4819 let mayLoad = 1 in {
4820 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4821 (ins x86memop:$src),
4822 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
4824 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))]>,
4827 def rmk : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4828 (ins KRC:$mask, x86memop:$src),
4829 !strconcat(OpcodeStr,"\t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
4833 def rmkz : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4834 (ins KRC:$mask, x86memop:$src),
4835 !strconcat(OpcodeStr,"\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4841 defm VPMOVZXBDZ: avx512_extend<0x31, "vpmovzxbd", VK16WM, VR512, VR128X, X86vzext,
4842 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
4844 defm VPMOVZXBQZ: avx512_extend<0x32, "vpmovzxbq", VK8WM, VR512, VR128X, X86vzext,
4845 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
4847 defm VPMOVZXWDZ: avx512_extend<0x33, "vpmovzxwd", VK16WM, VR512, VR256X, X86vzext,
4848 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
4849 EVEX_CD8<16, CD8VH>;
4850 defm VPMOVZXWQZ: avx512_extend<0x34, "vpmovzxwq", VK8WM, VR512, VR128X, X86vzext,
4851 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
4852 EVEX_CD8<16, CD8VQ>;
4853 defm VPMOVZXDQZ: avx512_extend<0x35, "vpmovzxdq", VK8WM, VR512, VR256X, X86vzext,
4854 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
4855 EVEX_CD8<32, CD8VH>;
4857 defm VPMOVSXBDZ: avx512_extend<0x21, "vpmovsxbd", VK16WM, VR512, VR128X, X86vsext,
4858 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
4860 defm VPMOVSXBQZ: avx512_extend<0x22, "vpmovsxbq", VK8WM, VR512, VR128X, X86vsext,
4861 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
4863 defm VPMOVSXWDZ: avx512_extend<0x23, "vpmovsxwd", VK16WM, VR512, VR256X, X86vsext,
4864 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
4865 EVEX_CD8<16, CD8VH>;
4866 defm VPMOVSXWQZ: avx512_extend<0x24, "vpmovsxwq", VK8WM, VR512, VR128X, X86vsext,
4867 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
4868 EVEX_CD8<16, CD8VQ>;
4869 defm VPMOVSXDQZ: avx512_extend<0x25, "vpmovsxdq", VK8WM, VR512, VR256X, X86vsext,
4870 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
4871 EVEX_CD8<32, CD8VH>;
4873 //===----------------------------------------------------------------------===//
4874 // GATHER - SCATTER Operations
4876 multiclass avx512_gather<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4877 RegisterClass RC, X86MemOperand memop> {
4879 Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb" in
4880 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst, KRC:$mask_wb),
4881 (ins RC:$src1, KRC:$mask, memop:$src2),
4882 !strconcat(OpcodeStr,
4883 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4887 let ExeDomain = SSEPackedDouble in {
4888 defm VGATHERDPDZ : avx512_gather<0x92, "vgatherdpd", VK8WM, VR512, vy64xmem>,
4889 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4890 defm VGATHERQPDZ : avx512_gather<0x93, "vgatherqpd", VK8WM, VR512, vz64mem>,
4891 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4894 let ExeDomain = SSEPackedSingle in {
4895 defm VGATHERDPSZ : avx512_gather<0x92, "vgatherdps", VK16WM, VR512, vz32mem>,
4896 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4897 defm VGATHERQPSZ : avx512_gather<0x93, "vgatherqps", VK8WM, VR256X, vz64mem>,
4898 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4901 defm VPGATHERDQZ : avx512_gather<0x90, "vpgatherdq", VK8WM, VR512, vy64xmem>,
4902 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4903 defm VPGATHERDDZ : avx512_gather<0x90, "vpgatherdd", VK16WM, VR512, vz32mem>,
4904 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4906 defm VPGATHERQQZ : avx512_gather<0x91, "vpgatherqq", VK8WM, VR512, vz64mem>,
4907 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4908 defm VPGATHERQDZ : avx512_gather<0x91, "vpgatherqd", VK8WM, VR256X, vz64mem>,
4909 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4911 multiclass avx512_scatter<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4912 RegisterClass RC, X86MemOperand memop> {
4913 let mayStore = 1, Constraints = "$mask = $mask_wb" in
4914 def mr : AVX5128I<opc, MRMDestMem, (outs KRC:$mask_wb),
4915 (ins memop:$dst, KRC:$mask, RC:$src2),
4916 !strconcat(OpcodeStr,
4917 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4921 let ExeDomain = SSEPackedDouble in {
4922 defm VSCATTERDPDZ : avx512_scatter<0xA2, "vscatterdpd", VK8WM, VR512, vy64xmem>,
4923 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4924 defm VSCATTERQPDZ : avx512_scatter<0xA3, "vscatterqpd", VK8WM, VR512, vz64mem>,
4925 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4928 let ExeDomain = SSEPackedSingle in {
4929 defm VSCATTERDPSZ : avx512_scatter<0xA2, "vscatterdps", VK16WM, VR512, vz32mem>,
4930 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4931 defm VSCATTERQPSZ : avx512_scatter<0xA3, "vscatterqps", VK8WM, VR256X, vz64mem>,
4932 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4935 defm VPSCATTERDQZ : avx512_scatter<0xA0, "vpscatterdq", VK8WM, VR512, vy64xmem>,
4936 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4937 defm VPSCATTERDDZ : avx512_scatter<0xA0, "vpscatterdd", VK16WM, VR512, vz32mem>,
4938 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4940 defm VPSCATTERQQZ : avx512_scatter<0xA1, "vpscatterqq", VK8WM, VR512, vz64mem>,
4941 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4942 defm VPSCATTERQDZ : avx512_scatter<0xA1, "vpscatterqd", VK8WM, VR256X, vz64mem>,
4943 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4946 multiclass avx512_gather_scatter_prefetch<bits<8> opc, Format F, string OpcodeStr,
4947 RegisterClass KRC, X86MemOperand memop> {
4948 let Predicates = [HasPFI], hasSideEffects = 1 in
4949 def m : AVX5128I<opc, F, (outs), (ins KRC:$mask, memop:$src),
4950 !strconcat(OpcodeStr, "\t{$src {${mask}}|{${mask}}, $src}"),
4954 defm VGATHERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dps",
4955 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4957 defm VGATHERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qps",
4958 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4960 defm VGATHERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dpd",
4961 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4963 defm VGATHERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qpd",
4964 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4966 defm VGATHERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dps",
4967 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4969 defm VGATHERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qps",
4970 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4972 defm VGATHERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dpd",
4973 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4975 defm VGATHERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qpd",
4976 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4978 defm VSCATTERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dps",
4979 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4981 defm VSCATTERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qps",
4982 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4984 defm VSCATTERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dpd",
4985 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4987 defm VSCATTERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qpd",
4988 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4990 defm VSCATTERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dps",
4991 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4993 defm VSCATTERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qps",
4994 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4996 defm VSCATTERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dpd",
4997 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4999 defm VSCATTERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qpd",
5000 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
5001 //===----------------------------------------------------------------------===//
5002 // VSHUFPS - VSHUFPD Operations
5004 multiclass avx512_shufp<RegisterClass RC, X86MemOperand x86memop,
5005 ValueType vt, string OpcodeStr, PatFrag mem_frag,
5007 def rmi : AVX512PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
5008 (ins RC:$src1, x86memop:$src2, u8imm:$src3),
5009 !strconcat(OpcodeStr,
5010 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5011 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
5012 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
5013 EVEX_4V, Sched<[WriteShuffleLd, ReadAfterLd]>;
5014 def rri : AVX512PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
5015 (ins RC:$src1, RC:$src2, u8imm:$src3),
5016 !strconcat(OpcodeStr,
5017 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5018 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
5019 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
5020 EVEX_4V, Sched<[WriteShuffle]>;
5023 defm VSHUFPSZ : avx512_shufp<VR512, f512mem, v16f32, "vshufps", memopv16f32,
5024 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
5025 defm VSHUFPDZ : avx512_shufp<VR512, f512mem, v8f64, "vshufpd", memopv8f64,
5026 SSEPackedDouble>, PD, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
5028 def : Pat<(v16i32 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
5029 (VSHUFPSZrri VR512:$src1, VR512:$src2, imm:$imm)>;
5030 def : Pat<(v16i32 (X86Shufp VR512:$src1,
5031 (memopv16i32 addr:$src2), (i8 imm:$imm))),
5032 (VSHUFPSZrmi VR512:$src1, addr:$src2, imm:$imm)>;
5034 def : Pat<(v8i64 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
5035 (VSHUFPDZrri VR512:$src1, VR512:$src2, imm:$imm)>;
5036 def : Pat<(v8i64 (X86Shufp VR512:$src1,
5037 (memopv8i64 addr:$src2), (i8 imm:$imm))),
5038 (VSHUFPDZrmi VR512:$src1, addr:$src2, imm:$imm)>;
5040 multiclass avx512_valign<X86VectorVTInfo _> {
5041 defm rri : AVX512_maskable<0x03, MRMSrcReg, _, (outs _.RC:$dst),
5042 (ins _.RC:$src1, _.RC:$src2, u8imm:$src3),
5044 "$src3, $src2, $src1", "$src1, $src2, $src3",
5045 (_.VT (X86VAlign _.RC:$src2, _.RC:$src1,
5047 AVX512AIi8Base, EVEX_4V;
5049 // Also match valign of packed floats.
5050 def : Pat<(_.FloatVT (X86VAlign _.RC:$src1, _.RC:$src2, (i8 imm:$imm))),
5051 (!cast<Instruction>(NAME##rri) _.RC:$src2, _.RC:$src1, imm:$imm)>;
5054 def rmi : AVX512AIi8<0x03, MRMSrcMem, (outs _.RC:$dst),
5055 (ins _.RC:$src1, _.MemOp:$src2, u8imm:$src3),
5056 !strconcat("valign"##_.Suffix,
5057 "\t{$src3, $src2, $src1, $dst|"
5058 "$dst, $src1, $src2, $src3}"),
5061 defm VALIGND : avx512_valign<v16i32_info>, EVEX_V512, EVEX_CD8<32, CD8VF>;
5062 defm VALIGNQ : avx512_valign<v8i64_info>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
5064 // Helper fragments to match sext vXi1 to vXiY.
5065 def v16i1sextv16i32 : PatLeaf<(v16i32 (X86vsrai VR512:$src, (i8 31)))>;
5066 def v8i1sextv8i64 : PatLeaf<(v8i64 (X86vsrai VR512:$src, (i8 63)))>;
5068 multiclass avx512_vpabs<bits<8> opc, string OpcodeStr, ValueType OpVT,
5069 RegisterClass KRC, RegisterClass RC,
5070 X86MemOperand x86memop, X86MemOperand x86scalar_mop,
5072 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
5073 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5075 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
5076 !strconcat(OpcodeStr, "\t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
5078 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
5079 !strconcat(OpcodeStr,
5080 "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
5082 let mayLoad = 1 in {
5083 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5084 (ins x86memop:$src),
5085 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5087 def rmk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5088 (ins KRC:$mask, x86memop:$src),
5089 !strconcat(OpcodeStr,
5090 "\t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
5092 def rmkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5093 (ins KRC:$mask, x86memop:$src),
5094 !strconcat(OpcodeStr,
5095 "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
5097 def rmb : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5098 (ins x86scalar_mop:$src),
5099 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5100 ", $dst|$dst, ${src}", BrdcstStr, "}"),
5102 def rmbk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5103 (ins KRC:$mask, x86scalar_mop:$src),
5104 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5105 ", $dst {${mask}}|$dst {${mask}}, ${src}", BrdcstStr, "}"),
5106 []>, EVEX, EVEX_B, EVEX_K;
5107 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5108 (ins KRC:$mask, x86scalar_mop:$src),
5109 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5110 ", $dst {${mask}} {z}|$dst {${mask}} {z}, ${src}",
5112 []>, EVEX, EVEX_B, EVEX_KZ;
5116 defm VPABSDZ : avx512_vpabs<0x1E, "vpabsd", v16i32, VK16WM, VR512,
5117 i512mem, i32mem, "{1to16}">, EVEX_V512,
5118 EVEX_CD8<32, CD8VF>;
5119 defm VPABSQZ : avx512_vpabs<0x1F, "vpabsq", v8i64, VK8WM, VR512,
5120 i512mem, i64mem, "{1to8}">, EVEX_V512, VEX_W,
5121 EVEX_CD8<64, CD8VF>;
5124 (bc_v16i32 (v16i1sextv16i32)),
5125 (bc_v16i32 (add (v16i32 VR512:$src), (v16i1sextv16i32)))),
5126 (VPABSDZrr VR512:$src)>;
5128 (bc_v8i64 (v8i1sextv8i64)),
5129 (bc_v8i64 (add (v8i64 VR512:$src), (v8i1sextv8i64)))),
5130 (VPABSQZrr VR512:$src)>;
5132 def : Pat<(v16i32 (int_x86_avx512_mask_pabs_d_512 (v16i32 VR512:$src),
5133 (v16i32 immAllZerosV), (i16 -1))),
5134 (VPABSDZrr VR512:$src)>;
5135 def : Pat<(v8i64 (int_x86_avx512_mask_pabs_q_512 (v8i64 VR512:$src),
5136 (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
5137 (VPABSQZrr VR512:$src)>;
5139 multiclass avx512_conflict<bits<8> opc, string OpcodeStr,
5140 RegisterClass RC, RegisterClass KRC,
5141 X86MemOperand x86memop,
5142 X86MemOperand x86scalar_mop, string BrdcstStr> {
5143 let hasSideEffects = 0 in {
5144 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
5146 !strconcat(OpcodeStr, "\t{$src, ${dst} |${dst}, $src}"),
5149 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5150 (ins x86memop:$src),
5151 !strconcat(OpcodeStr, "\t{$src, ${dst}|${dst}, $src}"),
5154 def rmb : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5155 (ins x86scalar_mop:$src),
5156 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5157 ", ${dst}|${dst}, ${src}", BrdcstStr, "}"),
5159 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
5160 (ins KRC:$mask, RC:$src),
5161 !strconcat(OpcodeStr,
5162 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
5165 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5166 (ins KRC:$mask, x86memop:$src),
5167 !strconcat(OpcodeStr,
5168 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
5171 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5172 (ins KRC:$mask, x86scalar_mop:$src),
5173 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5174 ", ${dst} {${mask}} {z}|${dst} {${mask}} {z}, ${src}",
5176 []>, EVEX, EVEX_KZ, EVEX_B;
5178 let Constraints = "$src1 = $dst" in {
5179 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
5180 (ins RC:$src1, KRC:$mask, RC:$src2),
5181 !strconcat(OpcodeStr,
5182 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
5185 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5186 (ins RC:$src1, KRC:$mask, x86memop:$src2),
5187 !strconcat(OpcodeStr,
5188 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
5191 def rmbk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5192 (ins RC:$src1, KRC:$mask, x86scalar_mop:$src2),
5193 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
5194 ", ${dst} {${mask}}|${dst} {${mask}}, ${src2}", BrdcstStr, "}"),
5195 []>, EVEX, EVEX_K, EVEX_B;
5200 let Predicates = [HasCDI] in {
5201 defm VPCONFLICTD : avx512_conflict<0xC4, "vpconflictd", VR512, VK16WM,
5202 i512mem, i32mem, "{1to16}">,
5203 EVEX_V512, EVEX_CD8<32, CD8VF>;
5206 defm VPCONFLICTQ : avx512_conflict<0xC4, "vpconflictq", VR512, VK8WM,
5207 i512mem, i64mem, "{1to8}">,
5208 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
5212 def : Pat<(int_x86_avx512_mask_conflict_d_512 VR512:$src2, VR512:$src1,
5214 (VPCONFLICTDrrk VR512:$src1,
5215 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
5217 def : Pat<(int_x86_avx512_mask_conflict_q_512 VR512:$src2, VR512:$src1,
5219 (VPCONFLICTQrrk VR512:$src1,
5220 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
5222 let Predicates = [HasCDI] in {
5223 defm VPLZCNTD : avx512_conflict<0x44, "vplzcntd", VR512, VK16WM,
5224 i512mem, i32mem, "{1to16}">,
5225 EVEX_V512, EVEX_CD8<32, CD8VF>;
5228 defm VPLZCNTQ : avx512_conflict<0x44, "vplzcntq", VR512, VK8WM,
5229 i512mem, i64mem, "{1to8}">,
5230 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
5234 def : Pat<(int_x86_avx512_mask_lzcnt_d_512 VR512:$src2, VR512:$src1,
5236 (VPLZCNTDrrk VR512:$src1,
5237 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
5239 def : Pat<(int_x86_avx512_mask_lzcnt_q_512 VR512:$src2, VR512:$src1,
5241 (VPLZCNTQrrk VR512:$src1,
5242 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
5244 def : Pat<(v16i32 (ctlz (memopv16i32 addr:$src))),
5245 (VPLZCNTDrm addr:$src)>;
5246 def : Pat<(v16i32 (ctlz (v16i32 VR512:$src))),
5247 (VPLZCNTDrr VR512:$src)>;
5248 def : Pat<(v8i64 (ctlz (memopv8i64 addr:$src))),
5249 (VPLZCNTQrm addr:$src)>;
5250 def : Pat<(v8i64 (ctlz (v8i64 VR512:$src))),
5251 (VPLZCNTQrr VR512:$src)>;
5253 def : Pat<(store (i1 -1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
5254 def : Pat<(store (i1 1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
5255 def : Pat<(store (i1 0), addr:$dst), (MOV8mi addr:$dst, (i8 0))>;
5257 def : Pat<(store VK1:$src, addr:$dst),
5259 (EXTRACT_SUBREG (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)),
5260 sub_8bit))>, Requires<[HasAVX512, NoDQI]>;
5262 def : Pat<(store VK8:$src, addr:$dst),
5264 (EXTRACT_SUBREG (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
5265 sub_8bit))>, Requires<[HasAVX512, NoDQI]>;
5267 def truncstorei1 : PatFrag<(ops node:$val, node:$ptr),
5268 (truncstore node:$val, node:$ptr), [{
5269 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
5272 def : Pat<(truncstorei1 GR8:$src, addr:$dst),
5273 (MOV8mr addr:$dst, GR8:$src)>;
5275 multiclass cvt_by_vec_width<bits<8> opc, X86VectorVTInfo Vec, string OpcodeStr > {
5276 def rr : AVX512XS8I<opc, MRMDestReg, (outs Vec.RC:$dst), (ins Vec.KRC:$src),
5277 !strconcat(OpcodeStr##Vec.Suffix, "\t{$src, $dst|$dst, $src}"),
5278 [(set Vec.RC:$dst, (Vec.VT (X86vsext Vec.KRC:$src)))]>, EVEX;
5281 multiclass cvt_mask_by_elt_width<bits<8> opc, AVX512VLVectorVTInfo VTInfo,
5282 string OpcodeStr, Predicate prd> {
5283 let Predicates = [prd] in
5284 defm Z : cvt_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
5286 let Predicates = [prd, HasVLX] in {
5287 defm Z256 : cvt_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
5288 defm Z128 : cvt_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
5292 multiclass avx512_convert_mask_to_vector<string OpcodeStr> {
5293 defm NAME##B : cvt_mask_by_elt_width<0x28, avx512vl_i8_info, OpcodeStr,
5295 defm NAME##W : cvt_mask_by_elt_width<0x28, avx512vl_i16_info, OpcodeStr,
5297 defm NAME##D : cvt_mask_by_elt_width<0x38, avx512vl_i32_info, OpcodeStr,
5299 defm NAME##Q : cvt_mask_by_elt_width<0x38, avx512vl_i64_info, OpcodeStr,
5303 defm VPMOVM2 : avx512_convert_mask_to_vector<"vpmovm2">;
5305 //===----------------------------------------------------------------------===//
5306 // AVX-512 - COMPRESS and EXPAND
5308 multiclass compress_by_vec_width<bits<8> opc, X86VectorVTInfo _,
5310 def rrkz : AVX5128I<opc, MRMDestReg, (outs _.RC:$dst),
5311 (ins _.KRCWM:$mask, _.RC:$src),
5312 OpcodeStr # "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}",
5313 [(set _.RC:$dst, (_.VT (X86compress _.KRCWM:$mask, _.RC:$src,
5314 _.ImmAllZerosV)))]>, EVEX_KZ;
5316 let Constraints = "$src0 = $dst" in
5317 def rrk : AVX5128I<opc, MRMDestReg, (outs _.RC:$dst),
5318 (ins _.RC:$src0, _.KRCWM:$mask, _.RC:$src),
5319 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
5320 [(set _.RC:$dst, (_.VT (X86compress _.KRCWM:$mask, _.RC:$src,
5321 _.RC:$src0)))]>, EVEX_K;
5323 let mayStore = 1 in {
5324 def mrk : AVX5128I<opc, MRMDestMem, (outs),
5325 (ins _.MemOp:$dst, _.KRCWM:$mask, _.RC:$src),
5326 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
5327 [(store (_.VT (X86compress _.KRCWM:$mask, _.RC:$src, undef)),
5329 EVEX_K, EVEX_CD8<_.EltSize, CD8VT1>;
5333 multiclass compress_by_elt_width<bits<8> opc, string OpcodeStr,
5334 AVX512VLVectorVTInfo VTInfo> {
5335 defm Z : compress_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
5337 let Predicates = [HasVLX] in {
5338 defm Z256 : compress_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
5339 defm Z128 : compress_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
5343 defm VPCOMPRESSD : compress_by_elt_width <0x8B, "vpcompressd", avx512vl_i32_info>,
5345 defm VPCOMPRESSQ : compress_by_elt_width <0x8B, "vpcompressq", avx512vl_i64_info>,
5347 defm VCOMPRESSPS : compress_by_elt_width <0x8A, "vcompressps", avx512vl_f32_info>,
5349 defm VCOMPRESSPD : compress_by_elt_width <0x8A, "vcompresspd", avx512vl_f64_info>,
5353 multiclass expand_by_vec_width<bits<8> opc, X86VectorVTInfo _,
5355 def rrkz : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
5356 (ins _.KRCWM:$mask, _.RC:$src),
5357 OpcodeStr # "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}",
5358 [(set _.RC:$dst, (_.VT (X86expand _.KRCWM:$mask, (_.VT _.RC:$src),
5359 _.ImmAllZerosV)))]>, EVEX_KZ;
5361 let Constraints = "$src0 = $dst" in
5362 def rrk : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
5363 (ins _.RC:$src0, _.KRCWM:$mask, _.RC:$src),
5364 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
5365 [(set _.RC:$dst, (_.VT (X86expand _.KRCWM:$mask,
5366 (_.VT _.RC:$src), _.RC:$src0)))]>, EVEX_K;
5368 let mayLoad = 1, Constraints = "$src0 = $dst" in
5369 def rmk : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
5370 (ins _.RC:$src0, _.KRCWM:$mask, _.MemOp:$src),
5371 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
5372 [(set _.RC:$dst, (_.VT (X86expand _.KRCWM:$mask,
5374 (_.LdFrag addr:$src))),
5376 EVEX_K, EVEX_CD8<_.EltSize, CD8VT1>;
5379 def rmkz : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
5380 (ins _.KRCWM:$mask, _.MemOp:$src),
5381 OpcodeStr # "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}",
5382 [(set _.RC:$dst, (_.VT (X86expand _.KRCWM:$mask,
5383 (_.VT (bitconvert (_.LdFrag addr:$src))),
5384 _.ImmAllZerosV)))]>,
5385 EVEX_KZ, EVEX_CD8<_.EltSize, CD8VT1>;
5389 multiclass expand_by_elt_width<bits<8> opc, string OpcodeStr,
5390 AVX512VLVectorVTInfo VTInfo> {
5391 defm Z : expand_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
5393 let Predicates = [HasVLX] in {
5394 defm Z256 : expand_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
5395 defm Z128 : expand_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
5399 defm VPEXPANDD : expand_by_elt_width <0x89, "vpexpandd", avx512vl_i32_info>,
5401 defm VPEXPANDQ : expand_by_elt_width <0x89, "vpexpandq", avx512vl_i64_info>,
5403 defm VEXPANDPS : expand_by_elt_width <0x88, "vexpandps", avx512vl_f32_info>,
5405 defm VEXPANDPD : expand_by_elt_width <0x88, "vexpandpd", avx512vl_f64_info>,