1 //===-- X86InstrAVX512.td - AVX512 Instruction Set ---------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 AVX512 instruction set, defining the
11 // instructions, and properties of the instructions which are needed for code
12 // generation, machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 // Group template arguments that can be derived from the vector type (EltNum x
17 // EltVT). These are things like the register class for the writemask, etc.
18 // The idea is to pass one of these as the template argument rather than the
19 // individual arguments.
20 // The template is also used for scalar types, in this case numelts is 1.
21 class X86VectorVTInfo<int numelts, ValueType eltvt, RegisterClass rc,
23 RegisterClass RC = rc;
24 ValueType EltVT = eltvt;
25 int NumElts = numelts;
27 // Corresponding mask register class.
28 RegisterClass KRC = !cast<RegisterClass>("VK" # NumElts);
30 // Corresponding write-mask register class.
31 RegisterClass KRCWM = !cast<RegisterClass>("VK" # NumElts # "WM");
33 // The GPR register class that can hold the write mask. Use GR8 for fewer
34 // than 8 elements. Use shift-right and equal to work around the lack of
37 !cast<RegisterClass>("GR" #
38 !if (!eq (!srl(NumElts, 3), 0), 8, NumElts));
40 // Suffix used in the instruction mnemonic.
41 string Suffix = suffix;
43 // VTName is a string name for vector VT. For vector types it will be
44 // v # NumElts # EltVT, so for vector of 8 elements of i32 it will be v8i32
45 // It is a little bit complex for scalar types, where NumElts = 1.
46 // In this case we build v4f32 or v2f64
47 string VTName = "v" # !if (!eq (NumElts, 1),
48 !if (!eq (EltVT.Size, 32), 4,
49 !if (!eq (EltVT.Size, 64), 2, NumElts)), NumElts) # EltVT;
52 ValueType VT = !cast<ValueType>(VTName);
54 string EltTypeName = !cast<string>(EltVT);
55 // Size of the element type in bits, e.g. 32 for v16i32.
56 string EltSizeName = !subst("i", "", !subst("f", "", EltTypeName));
57 int EltSize = EltVT.Size;
59 // "i" for integer types and "f" for floating-point types
60 string TypeVariantName = !subst(EltSizeName, "", EltTypeName);
62 // Size of RC in bits, e.g. 512 for VR512.
65 // The corresponding memory operand, e.g. i512mem for VR512.
66 X86MemOperand MemOp = !cast<X86MemOperand>(TypeVariantName # Size # "mem");
67 X86MemOperand ScalarMemOp = !cast<X86MemOperand>(EltVT # "mem");
70 // Note: For 128/256-bit integer VT we choose loadv2i64/loadv4i64
71 // due to load promotion during legalization
72 PatFrag LdFrag = !cast<PatFrag>("load" #
73 !if (!eq (TypeVariantName, "i"),
74 !if (!eq (Size, 128), "v2i64",
75 !if (!eq (Size, 256), "v4i64",
78 PatFrag AlignedLdFrag = !cast<PatFrag>("alignedload" #
79 !if (!eq (TypeVariantName, "i"),
80 !if (!eq (Size, 128), "v2i64",
81 !if (!eq (Size, 256), "v4i64",
83 !if (!eq (EltSize, 64), "v8i64", "v16i32"),
86 PatFrag ScalarLdFrag = !cast<PatFrag>("load" # EltVT);
88 // The corresponding float type, e.g. v16f32 for v16i32
89 // Note: For EltSize < 32, FloatVT is illegal and TableGen
90 // fails to compile, so we choose FloatVT = VT
91 ValueType FloatVT = !cast<ValueType>(
92 !if (!eq (!srl(EltSize,5),0),
94 !if (!eq(TypeVariantName, "i"),
95 "v" # NumElts # "f" # EltSize,
98 // The string to specify embedded broadcast in assembly.
99 string BroadcastStr = "{1to" # NumElts # "}";
101 // 8-bit compressed displacement tuple/subvector format. This is only
102 // defined for NumElts <= 8.
103 CD8VForm CD8TupleForm = !if (!eq (!srl(NumElts, 4), 0),
104 !cast<CD8VForm>("CD8VT" # NumElts), ?);
106 SubRegIndex SubRegIdx = !if (!eq (Size, 128), sub_xmm,
107 !if (!eq (Size, 256), sub_ymm, ?));
109 Domain ExeDomain = !if (!eq (EltTypeName, "f32"), SSEPackedSingle,
110 !if (!eq (EltTypeName, "f64"), SSEPackedDouble,
113 RegisterClass FRC = !if (!eq (EltTypeName, "f32"), FR32X, FR64X);
115 // A vector type of the same width with element type i32. This is used to
116 // create the canonical constant zero node ImmAllZerosV.
117 ValueType i32VT = !cast<ValueType>("v" # !srl(Size, 5) # "i32");
118 dag ImmAllZerosV = (VT (bitconvert (i32VT immAllZerosV)));
120 string ZSuffix = !if (!eq (Size, 128), "Z128",
121 !if (!eq (Size, 256), "Z256", "Z"));
124 def v64i8_info : X86VectorVTInfo<64, i8, VR512, "b">;
125 def v32i16_info : X86VectorVTInfo<32, i16, VR512, "w">;
126 def v16i32_info : X86VectorVTInfo<16, i32, VR512, "d">;
127 def v8i64_info : X86VectorVTInfo<8, i64, VR512, "q">;
128 def v16f32_info : X86VectorVTInfo<16, f32, VR512, "ps">;
129 def v8f64_info : X86VectorVTInfo<8, f64, VR512, "pd">;
131 // "x" in v32i8x_info means RC = VR256X
132 def v32i8x_info : X86VectorVTInfo<32, i8, VR256X, "b">;
133 def v16i16x_info : X86VectorVTInfo<16, i16, VR256X, "w">;
134 def v8i32x_info : X86VectorVTInfo<8, i32, VR256X, "d">;
135 def v4i64x_info : X86VectorVTInfo<4, i64, VR256X, "q">;
136 def v8f32x_info : X86VectorVTInfo<8, f32, VR256X, "ps">;
137 def v4f64x_info : X86VectorVTInfo<4, f64, VR256X, "pd">;
139 def v16i8x_info : X86VectorVTInfo<16, i8, VR128X, "b">;
140 def v8i16x_info : X86VectorVTInfo<8, i16, VR128X, "w">;
141 def v4i32x_info : X86VectorVTInfo<4, i32, VR128X, "d">;
142 def v2i64x_info : X86VectorVTInfo<2, i64, VR128X, "q">;
143 def v4f32x_info : X86VectorVTInfo<4, f32, VR128X, "ps">;
144 def v2f64x_info : X86VectorVTInfo<2, f64, VR128X, "pd">;
146 // We map scalar types to the smallest (128-bit) vector type
147 // with the appropriate element type. This allows to use the same masking logic.
148 def f32x_info : X86VectorVTInfo<1, f32, VR128X, "ss">;
149 def f64x_info : X86VectorVTInfo<1, f64, VR128X, "sd">;
151 class AVX512VLVectorVTInfo<X86VectorVTInfo i512, X86VectorVTInfo i256,
152 X86VectorVTInfo i128> {
153 X86VectorVTInfo info512 = i512;
154 X86VectorVTInfo info256 = i256;
155 X86VectorVTInfo info128 = i128;
158 def avx512vl_i8_info : AVX512VLVectorVTInfo<v64i8_info, v32i8x_info,
160 def avx512vl_i16_info : AVX512VLVectorVTInfo<v32i16_info, v16i16x_info,
162 def avx512vl_i32_info : AVX512VLVectorVTInfo<v16i32_info, v8i32x_info,
164 def avx512vl_i64_info : AVX512VLVectorVTInfo<v8i64_info, v4i64x_info,
166 def avx512vl_f32_info : AVX512VLVectorVTInfo<v16f32_info, v8f32x_info,
168 def avx512vl_f64_info : AVX512VLVectorVTInfo<v8f64_info, v4f64x_info,
171 // This multiclass generates the masking variants from the non-masking
172 // variant. It only provides the assembly pieces for the masking variants.
173 // It assumes custom ISel patterns for masking which can be provided as
174 // template arguments.
175 multiclass AVX512_maskable_custom<bits<8> O, Format F,
177 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
179 string AttSrcAsm, string IntelSrcAsm,
181 list<dag> MaskingPattern,
182 list<dag> ZeroMaskingPattern,
183 string MaskingConstraint = "",
184 InstrItinClass itin = NoItinerary,
185 bit IsCommutable = 0> {
186 let isCommutable = IsCommutable in
187 def NAME: AVX512<O, F, Outs, Ins,
188 OpcodeStr#"\t{"#AttSrcAsm#", $dst|"#
189 "$dst , "#IntelSrcAsm#"}",
192 // Prefer over VMOV*rrk Pat<>
193 let AddedComplexity = 20 in
194 def NAME#k: AVX512<O, F, Outs, MaskingIns,
195 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}}|"#
196 "$dst {${mask}}, "#IntelSrcAsm#"}",
197 MaskingPattern, itin>,
199 // In case of the 3src subclass this is overridden with a let.
200 string Constraints = MaskingConstraint;
202 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
203 def NAME#kz: AVX512<O, F, Outs, ZeroMaskingIns,
204 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}} {z}|"#
205 "$dst {${mask}} {z}, "#IntelSrcAsm#"}",
212 // Common base class of AVX512_maskable and AVX512_maskable_3src.
213 multiclass AVX512_maskable_common<bits<8> O, Format F, X86VectorVTInfo _,
215 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
217 string AttSrcAsm, string IntelSrcAsm,
218 dag RHS, dag MaskingRHS,
219 SDNode Select = vselect,
220 string MaskingConstraint = "",
221 InstrItinClass itin = NoItinerary,
222 bit IsCommutable = 0> :
223 AVX512_maskable_custom<O, F, Outs, Ins, MaskingIns, ZeroMaskingIns, OpcodeStr,
224 AttSrcAsm, IntelSrcAsm,
225 [(set _.RC:$dst, RHS)],
226 [(set _.RC:$dst, MaskingRHS)],
228 (Select _.KRCWM:$mask, RHS, _.ImmAllZerosV))],
229 MaskingConstraint, NoItinerary, IsCommutable>;
231 // This multiclass generates the unconditional/non-masking, the masking and
232 // the zero-masking variant of the vector instruction. In the masking case, the
233 // perserved vector elements come from a new dummy input operand tied to $dst.
234 multiclass AVX512_maskable<bits<8> O, Format F, X86VectorVTInfo _,
235 dag Outs, dag Ins, string OpcodeStr,
236 string AttSrcAsm, string IntelSrcAsm,
238 InstrItinClass itin = NoItinerary,
239 bit IsCommutable = 0> :
240 AVX512_maskable_common<O, F, _, Outs, Ins,
241 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
242 !con((ins _.KRCWM:$mask), Ins),
243 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
244 (vselect _.KRCWM:$mask, RHS, _.RC:$src0), vselect,
245 "$src0 = $dst", itin, IsCommutable>;
247 // This multiclass generates the unconditional/non-masking, the masking and
248 // the zero-masking variant of the scalar instruction.
249 multiclass AVX512_maskable_scalar<bits<8> O, Format F, X86VectorVTInfo _,
250 dag Outs, dag Ins, string OpcodeStr,
251 string AttSrcAsm, string IntelSrcAsm,
253 InstrItinClass itin = NoItinerary,
254 bit IsCommutable = 0> :
255 AVX512_maskable_common<O, F, _, Outs, Ins,
256 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
257 !con((ins _.KRCWM:$mask), Ins),
258 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
259 (X86select _.KRCWM:$mask, RHS, _.RC:$src0), X86select,
260 "$src0 = $dst", itin, IsCommutable>;
262 // Similar to AVX512_maskable but in this case one of the source operands
263 // ($src1) is already tied to $dst so we just use that for the preserved
264 // vector elements. NOTE that the NonTiedIns (the ins dag) should exclude
266 multiclass AVX512_maskable_3src<bits<8> O, Format F, X86VectorVTInfo _,
267 dag Outs, dag NonTiedIns, string OpcodeStr,
268 string AttSrcAsm, string IntelSrcAsm,
270 AVX512_maskable_common<O, F, _, Outs,
271 !con((ins _.RC:$src1), NonTiedIns),
272 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
273 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
274 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
275 (vselect _.KRCWM:$mask, RHS, _.RC:$src1)>;
277 multiclass AVX512_maskable_3src_scalar<bits<8> O, Format F, X86VectorVTInfo _,
278 dag Outs, dag NonTiedIns, string OpcodeStr,
279 string AttSrcAsm, string IntelSrcAsm,
281 AVX512_maskable_common<O, F, _, Outs,
282 !con((ins _.RC:$src1), NonTiedIns),
283 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
284 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
285 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
286 (X86select _.KRCWM:$mask, RHS, _.RC:$src1)>;
288 multiclass AVX512_maskable_in_asm<bits<8> O, Format F, X86VectorVTInfo _,
291 string AttSrcAsm, string IntelSrcAsm,
293 AVX512_maskable_custom<O, F, Outs, Ins,
294 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
295 !con((ins _.KRCWM:$mask), Ins),
296 OpcodeStr, AttSrcAsm, IntelSrcAsm, Pattern, [], [],
300 // Instruction with mask that puts result in mask register,
301 // like "compare" and "vptest"
302 multiclass AVX512_maskable_custom_cmp<bits<8> O, Format F,
304 dag Ins, dag MaskingIns,
306 string AttSrcAsm, string IntelSrcAsm,
308 list<dag> MaskingPattern,
310 InstrItinClass itin = NoItinerary> {
311 def NAME: AVX512<O, F, Outs, Ins,
312 OpcodeStr#"\t{"#AttSrcAsm#", $dst "#Round#"|"#
313 "$dst "#Round#", "#IntelSrcAsm#"}",
316 def NAME#k: AVX512<O, F, Outs, MaskingIns,
317 OpcodeStr#"\t{"#Round#AttSrcAsm#", $dst {${mask}}|"#
318 "$dst {${mask}}, "#IntelSrcAsm#Round#"}",
319 MaskingPattern, itin>, EVEX_K;
322 multiclass AVX512_maskable_common_cmp<bits<8> O, Format F, X86VectorVTInfo _,
324 dag Ins, dag MaskingIns,
326 string AttSrcAsm, string IntelSrcAsm,
327 dag RHS, dag MaskingRHS,
329 InstrItinClass itin = NoItinerary> :
330 AVX512_maskable_custom_cmp<O, F, Outs, Ins, MaskingIns, OpcodeStr,
331 AttSrcAsm, IntelSrcAsm,
332 [(set _.KRC:$dst, RHS)],
333 [(set _.KRC:$dst, MaskingRHS)],
336 multiclass AVX512_maskable_cmp<bits<8> O, Format F, X86VectorVTInfo _,
337 dag Outs, dag Ins, string OpcodeStr,
338 string AttSrcAsm, string IntelSrcAsm,
339 dag RHS, string Round = "",
340 InstrItinClass itin = NoItinerary> :
341 AVX512_maskable_common_cmp<O, F, _, Outs, Ins,
342 !con((ins _.KRCWM:$mask), Ins),
343 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
344 (and _.KRCWM:$mask, RHS),
347 multiclass AVX512_maskable_cmp_alt<bits<8> O, Format F, X86VectorVTInfo _,
348 dag Outs, dag Ins, string OpcodeStr,
349 string AttSrcAsm, string IntelSrcAsm> :
350 AVX512_maskable_custom_cmp<O, F, Outs,
351 Ins, !con((ins _.KRCWM:$mask),Ins), OpcodeStr,
352 AttSrcAsm, IntelSrcAsm,
353 [],[],"", NoItinerary>;
355 // Bitcasts between 512-bit vector types. Return the original type since
356 // no instruction is needed for the conversion
357 let Predicates = [HasAVX512] in {
358 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
359 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
360 def : Pat<(v8f64 (bitconvert (v32i16 VR512:$src))), (v8f64 VR512:$src)>;
361 def : Pat<(v8f64 (bitconvert (v64i8 VR512:$src))), (v8f64 VR512:$src)>;
362 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
363 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
364 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
365 def : Pat<(v16f32 (bitconvert (v32i16 VR512:$src))), (v16f32 VR512:$src)>;
366 def : Pat<(v16f32 (bitconvert (v64i8 VR512:$src))), (v16f32 VR512:$src)>;
367 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
368 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
369 def : Pat<(v8i64 (bitconvert (v32i16 VR512:$src))), (v8i64 VR512:$src)>;
370 def : Pat<(v8i64 (bitconvert (v64i8 VR512:$src))), (v8i64 VR512:$src)>;
371 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
372 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
373 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
374 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
375 def : Pat<(v16i32 (bitconvert (v32i16 VR512:$src))), (v16i32 VR512:$src)>;
376 def : Pat<(v16i32 (bitconvert (v64i8 VR512:$src))), (v16i32 VR512:$src)>;
377 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
378 def : Pat<(v32i16 (bitconvert (v8i64 VR512:$src))), (v32i16 VR512:$src)>;
379 def : Pat<(v32i16 (bitconvert (v16i32 VR512:$src))), (v32i16 VR512:$src)>;
380 def : Pat<(v32i16 (bitconvert (v64i8 VR512:$src))), (v32i16 VR512:$src)>;
381 def : Pat<(v32i16 (bitconvert (v8f64 VR512:$src))), (v32i16 VR512:$src)>;
382 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
383 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
384 def : Pat<(v64i8 (bitconvert (v8i64 VR512:$src))), (v64i8 VR512:$src)>;
385 def : Pat<(v64i8 (bitconvert (v16i32 VR512:$src))), (v64i8 VR512:$src)>;
386 def : Pat<(v64i8 (bitconvert (v32i16 VR512:$src))), (v64i8 VR512:$src)>;
387 def : Pat<(v64i8 (bitconvert (v8f64 VR512:$src))), (v64i8 VR512:$src)>;
388 def : Pat<(v64i8 (bitconvert (v16f32 VR512:$src))), (v64i8 VR512:$src)>;
390 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
391 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
392 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
393 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
394 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
395 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
396 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
397 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
398 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
399 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
400 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
401 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
402 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
403 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
404 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
405 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
406 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
407 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
408 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
409 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
410 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
411 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
412 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
413 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
414 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
415 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
416 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
417 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
418 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
419 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
421 // Bitcasts between 256-bit vector types. Return the original type since
422 // no instruction is needed for the conversion
423 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
424 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
425 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
426 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
427 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
428 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
429 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
430 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
431 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
432 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
433 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
434 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
435 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
436 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
437 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
438 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
439 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
440 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
441 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
442 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
443 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
444 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
445 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
446 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
447 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
448 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
449 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
450 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
451 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
452 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
456 // AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
459 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
460 isPseudo = 1, Predicates = [HasAVX512] in {
461 def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
462 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
465 let Predicates = [HasAVX512] in {
466 def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
467 def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
468 def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
471 //===----------------------------------------------------------------------===//
472 // AVX-512 - VECTOR INSERT
475 multiclass vinsert_for_size_no_alt<int Opcode,
476 X86VectorVTInfo From, X86VectorVTInfo To,
477 PatFrag vinsert_insert,
478 SDNodeXForm INSERT_get_vinsert_imm> {
479 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
480 def rr : AVX512AIi8<Opcode, MRMSrcReg, (outs VR512:$dst),
481 (ins VR512:$src1, From.RC:$src2, u8imm:$src3),
482 "vinsert" # From.EltTypeName # "x" # From.NumElts #
483 "\t{$src3, $src2, $src1, $dst|"
484 "$dst, $src1, $src2, $src3}",
485 [(set To.RC:$dst, (vinsert_insert:$src3 (To.VT VR512:$src1),
486 (From.VT From.RC:$src2),
491 def rm : AVX512AIi8<Opcode, MRMSrcMem, (outs VR512:$dst),
492 (ins VR512:$src1, From.MemOp:$src2, u8imm:$src3),
493 "vinsert" # From.EltTypeName # "x" # From.NumElts #
494 "\t{$src3, $src2, $src1, $dst|"
495 "$dst, $src1, $src2, $src3}",
497 EVEX_4V, EVEX_V512, EVEX_CD8<From.EltSize, From.CD8TupleForm>;
501 multiclass vinsert_for_size<int Opcode,
502 X86VectorVTInfo From, X86VectorVTInfo To,
503 X86VectorVTInfo AltFrom, X86VectorVTInfo AltTo,
504 PatFrag vinsert_insert,
505 SDNodeXForm INSERT_get_vinsert_imm> :
506 vinsert_for_size_no_alt<Opcode, From, To,
507 vinsert_insert, INSERT_get_vinsert_imm> {
508 // Codegen pattern with the alternative types, e.g. v2i64 -> v8i64 for
509 // vinserti32x4. Only add this if 64x2 and friends are not supported
510 // natively via AVX512DQ.
511 let Predicates = [NoDQI] in
512 def : Pat<(vinsert_insert:$ins
513 (AltTo.VT VR512:$src1), (AltFrom.VT From.RC:$src2), (iPTR imm)),
514 (AltTo.VT (!cast<Instruction>(NAME # From.EltSize # "x4rr")
515 VR512:$src1, From.RC:$src2,
516 (INSERT_get_vinsert_imm VR512:$ins)))>;
519 multiclass vinsert_for_type<ValueType EltVT32, int Opcode128,
520 ValueType EltVT64, int Opcode256> {
521 defm NAME # "32x4" : vinsert_for_size<Opcode128,
522 X86VectorVTInfo< 4, EltVT32, VR128X>,
523 X86VectorVTInfo<16, EltVT32, VR512>,
524 X86VectorVTInfo< 2, EltVT64, VR128X>,
525 X86VectorVTInfo< 8, EltVT64, VR512>,
527 INSERT_get_vinsert128_imm>;
528 let Predicates = [HasDQI] in
529 defm NAME # "64x2" : vinsert_for_size_no_alt<Opcode128,
530 X86VectorVTInfo< 2, EltVT64, VR128X>,
531 X86VectorVTInfo< 8, EltVT64, VR512>,
533 INSERT_get_vinsert128_imm>, VEX_W;
534 defm NAME # "64x4" : vinsert_for_size<Opcode256,
535 X86VectorVTInfo< 4, EltVT64, VR256X>,
536 X86VectorVTInfo< 8, EltVT64, VR512>,
537 X86VectorVTInfo< 8, EltVT32, VR256>,
538 X86VectorVTInfo<16, EltVT32, VR512>,
540 INSERT_get_vinsert256_imm>, VEX_W;
541 let Predicates = [HasDQI] in
542 defm NAME # "32x8" : vinsert_for_size_no_alt<Opcode256,
543 X86VectorVTInfo< 8, EltVT32, VR256X>,
544 X86VectorVTInfo<16, EltVT32, VR512>,
546 INSERT_get_vinsert256_imm>;
549 defm VINSERTF : vinsert_for_type<f32, 0x18, f64, 0x1a>;
550 defm VINSERTI : vinsert_for_type<i32, 0x38, i64, 0x3a>;
552 // vinsertps - insert f32 to XMM
553 def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
554 (ins VR128X:$src1, VR128X:$src2, u8imm:$src3),
555 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
556 [(set VR128X:$dst, (X86insertps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
558 def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
559 (ins VR128X:$src1, f32mem:$src2, u8imm:$src3),
560 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
561 [(set VR128X:$dst, (X86insertps VR128X:$src1,
562 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
563 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
565 //===----------------------------------------------------------------------===//
566 // AVX-512 VECTOR EXTRACT
569 multiclass vextract_for_size_first_position_lowering<X86VectorVTInfo From,
570 X86VectorVTInfo To> {
571 // A subvector extract from the first vector position is
572 // a subregister copy that needs no instruction.
573 def NAME # To.NumElts:
574 Pat<(To.VT (extract_subvector (From.VT From.RC:$src),(iPTR 0))),
575 (To.VT (EXTRACT_SUBREG (From.VT From.RC:$src), To.SubRegIdx))>;
578 multiclass vextract_for_size<int Opcode,
579 X86VectorVTInfo From, X86VectorVTInfo To,
580 PatFrag vextract_extract> :
581 vextract_for_size_first_position_lowering<From, To> {
583 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
584 // use AVX512_maskable_in_asm (AVX512_maskable can't be used due to
585 // vextract_extract), we interesting only in patterns without mask,
586 // intrinsics pattern match generated bellow.
587 defm rr : AVX512_maskable_in_asm<Opcode, MRMDestReg, To, (outs To.RC:$dst),
588 (ins From.RC:$src1, i32u8imm:$idx),
589 "vextract" # To.EltTypeName # "x" # To.NumElts,
590 "$idx, $src1", "$src1, $idx",
591 [(set To.RC:$dst, (vextract_extract:$idx (From.VT From.RC:$src1),
593 AVX512AIi8Base, EVEX;
594 let mayStore = 1 in {
595 def rm : AVX512AIi8<Opcode, MRMDestMem, (outs),
596 (ins To.MemOp:$dst, From.RC:$src1, i32u8imm:$src2),
597 "vextract" # To.EltTypeName # "x" # To.NumElts #
598 "\t{$src2, $src1, $dst|$dst, $src1, $src2}",
601 def rmk : AVX512AIi8<Opcode, MRMDestMem, (outs),
602 (ins To.MemOp:$dst, To.KRCWM:$mask,
603 From.RC:$src1, i32u8imm:$src2),
604 "vextract" # To.EltTypeName # "x" # To.NumElts #
605 "\t{$src2, $src1, $dst {${mask}}|"
606 "$dst {${mask}}, $src1, $src2}",
611 // Intrinsic call with masking.
612 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
613 "x" # To.NumElts # "_" # From.Size)
614 From.RC:$src1, (iPTR imm:$idx), To.RC:$src0, To.MRC:$mask),
615 (!cast<Instruction>(NAME # To.EltSize # "x" # To.NumElts #
616 From.ZSuffix # "rrk")
618 (COPY_TO_REGCLASS To.MRC:$mask, To.KRCWM),
619 From.RC:$src1, imm:$idx)>;
621 // Intrinsic call with zero-masking.
622 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
623 "x" # To.NumElts # "_" # From.Size)
624 From.RC:$src1, (iPTR imm:$idx), To.ImmAllZerosV, To.MRC:$mask),
625 (!cast<Instruction>(NAME # To.EltSize # "x" # To.NumElts #
626 From.ZSuffix # "rrkz")
627 (COPY_TO_REGCLASS To.MRC:$mask, To.KRCWM),
628 From.RC:$src1, imm:$idx)>;
630 // Intrinsic call without masking.
631 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
632 "x" # To.NumElts # "_" # From.Size)
633 From.RC:$src1, (iPTR imm:$idx), To.ImmAllZerosV, (i8 -1)),
634 (!cast<Instruction>(NAME # To.EltSize # "x" # To.NumElts #
636 From.RC:$src1, imm:$idx)>;
639 // This multiclass generates patterns for matching vextract with common types
640 // (X86VectorVTInfo From , X86VectorVTInfo To) and alternative types
641 // (X86VectorVTInfo AltFrom, X86VectorVTInfo AltTo)
642 multiclass vextract_for_size_all<int Opcode,
643 X86VectorVTInfo From, X86VectorVTInfo To,
644 X86VectorVTInfo AltFrom, X86VectorVTInfo AltTo,
645 PatFrag vextract_extract,
646 SDNodeXForm EXTRACT_get_vextract_imm> :
647 vextract_for_size<Opcode, From, To, vextract_extract>,
648 vextract_for_size_first_position_lowering<AltFrom, AltTo> {
650 // Codegen pattern with the alternative types.
651 // Only add this if operation not supported natively via AVX512DQ
652 let Predicates = [NoDQI] in
653 def : Pat<(vextract_extract:$ext (AltFrom.VT AltFrom.RC:$src1), (iPTR imm)),
654 (AltTo.VT (!cast<Instruction>(NAME # To.EltSize # "x" #
655 To.NumElts # From.ZSuffix # "rr")
657 (EXTRACT_get_vextract_imm To.RC:$ext)))>;
660 multiclass vextract_for_type<ValueType EltVT32, int Opcode128,
661 ValueType EltVT64, int Opcode256> {
662 defm NAME # "32x4Z" : vextract_for_size_all<Opcode128,
663 X86VectorVTInfo<16, EltVT32, VR512>,
664 X86VectorVTInfo< 4, EltVT32, VR128X>,
665 X86VectorVTInfo< 8, EltVT64, VR512>,
666 X86VectorVTInfo< 2, EltVT64, VR128X>,
668 EXTRACT_get_vextract128_imm>,
669 EVEX_V512, EVEX_CD8<32, CD8VT4>;
670 defm NAME # "64x4Z" : vextract_for_size_all<Opcode256,
671 X86VectorVTInfo< 8, EltVT64, VR512>,
672 X86VectorVTInfo< 4, EltVT64, VR256X>,
673 X86VectorVTInfo<16, EltVT32, VR512>,
674 X86VectorVTInfo< 8, EltVT32, VR256>,
676 EXTRACT_get_vextract256_imm>,
677 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VT4>;
678 let Predicates = [HasVLX] in
679 defm NAME # "32x4Z256" : vextract_for_size_all<Opcode128,
680 X86VectorVTInfo< 8, EltVT32, VR256X>,
681 X86VectorVTInfo< 4, EltVT32, VR128X>,
682 X86VectorVTInfo< 4, EltVT64, VR256X>,
683 X86VectorVTInfo< 2, EltVT64, VR128X>,
685 EXTRACT_get_vextract128_imm>,
686 EVEX_V256, EVEX_CD8<32, CD8VT4>;
687 let Predicates = [HasVLX, HasDQI] in
688 defm NAME # "64x2Z256" : vextract_for_size<Opcode128,
689 X86VectorVTInfo< 4, EltVT64, VR256X>,
690 X86VectorVTInfo< 2, EltVT64, VR128X>,
691 vextract128_extract>,
692 VEX_W, EVEX_V256, EVEX_CD8<64, CD8VT2>;
693 let Predicates = [HasDQI] in {
694 defm NAME # "64x2Z" : vextract_for_size<Opcode128,
695 X86VectorVTInfo< 8, EltVT64, VR512>,
696 X86VectorVTInfo< 2, EltVT64, VR128X>,
697 vextract128_extract>,
698 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VT2>;
699 defm NAME # "32x8Z" : vextract_for_size<Opcode256,
700 X86VectorVTInfo<16, EltVT32, VR512>,
701 X86VectorVTInfo< 8, EltVT32, VR256X>,
702 vextract256_extract>,
703 EVEX_V512, EVEX_CD8<32, CD8VT8>;
707 defm VEXTRACTF : vextract_for_type<f32, 0x19, f64, 0x1b>;
708 defm VEXTRACTI : vextract_for_type<i32, 0x39, i64, 0x3b>;
710 // A 128-bit subvector insert to the first 512-bit vector position
711 // is a subregister copy that needs no instruction.
712 def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
713 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
714 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
716 def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
717 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
718 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
720 def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
721 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
722 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
724 def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
725 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
726 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
729 def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
730 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
731 def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
732 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
733 def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
734 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
735 def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
736 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
738 // vextractps - extract 32 bits from XMM
739 def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
740 (ins VR128X:$src1, u8imm:$src2),
741 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
742 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
745 def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
746 (ins f32mem:$dst, VR128X:$src1, u8imm:$src2),
747 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
748 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
749 addr:$dst)]>, EVEX, EVEX_CD8<32, CD8VT1>;
751 //===---------------------------------------------------------------------===//
754 multiclass avx512_fp_broadcast<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
755 ValueType svt, X86VectorVTInfo _> {
756 defm r : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
757 (ins SrcRC:$src), "vbroadcast"## !subst("p", "s", _.Suffix),
758 "$src", "$src", (_.VT (OpNode (svt SrcRC:$src)))>,
762 defm m : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
763 (ins _.ScalarMemOp:$src),
764 "vbroadcast"##!subst("p", "s", _.Suffix), "$src", "$src",
765 (_.VT (OpNode (_.ScalarLdFrag addr:$src)))>,
770 multiclass avx512_fp_broadcast_vl<bits<8> opc, SDNode OpNode,
771 AVX512VLVectorVTInfo _> {
772 defm Z : avx512_fp_broadcast<opc, OpNode, VR128X, _.info128.VT, _.info512>,
775 let Predicates = [HasVLX] in {
776 defm Z256 : avx512_fp_broadcast<opc, OpNode, VR128X, _.info128.VT, _.info256>,
781 let ExeDomain = SSEPackedSingle in {
782 defm VBROADCASTSS : avx512_fp_broadcast_vl<0x18, X86VBroadcast,
783 avx512vl_f32_info>, EVEX_CD8<32, CD8VT1>;
784 let Predicates = [HasVLX] in {
785 defm VBROADCASTSSZ128 : avx512_fp_broadcast<0x18, X86VBroadcast, VR128X,
786 v4f32, v4f32x_info>, EVEX_V128,
787 EVEX_CD8<32, CD8VT1>;
791 let ExeDomain = SSEPackedDouble in {
792 defm VBROADCASTSD : avx512_fp_broadcast_vl<0x19, X86VBroadcast,
793 avx512vl_f64_info>, VEX_W, EVEX_CD8<64, CD8VT1>;
796 // avx512_broadcast_pat introduces patterns for broadcast with a scalar argument.
797 // Later, we can canonize broadcast instructions before ISel phase and
798 // eliminate additional patterns on ISel.
799 // SrcRC_v and SrcRC_s are RegisterClasses for vector and scalar
800 // representations of source
801 multiclass avx512_broadcast_pat<string InstName, SDNode OpNode,
802 X86VectorVTInfo _, RegisterClass SrcRC_v,
803 RegisterClass SrcRC_s> {
804 def : Pat<(_.VT (OpNode (_.EltVT SrcRC_s:$src))),
805 (!cast<Instruction>(InstName##"r")
806 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
808 let AddedComplexity = 30 in {
809 def : Pat<(_.VT (vselect _.KRCWM:$mask,
810 (OpNode (_.EltVT SrcRC_s:$src)), _.RC:$src0)),
811 (!cast<Instruction>(InstName##"rk") _.RC:$src0, _.KRCWM:$mask,
812 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
814 def : Pat<(_.VT(vselect _.KRCWM:$mask,
815 (OpNode (_.EltVT SrcRC_s:$src)), _.ImmAllZerosV)),
816 (!cast<Instruction>(InstName##"rkz") _.KRCWM:$mask,
817 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
821 defm : avx512_broadcast_pat<"VBROADCASTSSZ", X86VBroadcast, v16f32_info,
823 defm : avx512_broadcast_pat<"VBROADCASTSDZ", X86VBroadcast, v8f64_info,
826 let Predicates = [HasVLX] in {
827 defm : avx512_broadcast_pat<"VBROADCASTSSZ256", X86VBroadcast,
828 v8f32x_info, VR128X, FR32X>;
829 defm : avx512_broadcast_pat<"VBROADCASTSSZ128", X86VBroadcast,
830 v4f32x_info, VR128X, FR32X>;
831 defm : avx512_broadcast_pat<"VBROADCASTSDZ256", X86VBroadcast,
832 v4f64x_info, VR128X, FR64X>;
835 def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
836 (VBROADCASTSSZm addr:$src)>;
837 def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
838 (VBROADCASTSDZm addr:$src)>;
840 def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
841 (VBROADCASTSSZm addr:$src)>;
842 def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
843 (VBROADCASTSDZm addr:$src)>;
845 multiclass avx512_int_broadcast_reg<bits<8> opc, X86VectorVTInfo _,
846 RegisterClass SrcRC> {
847 defm r : AVX512_maskable_in_asm<opc, MRMSrcReg, _, (outs _.RC:$dst),
848 (ins SrcRC:$src), "vpbroadcast"##_.Suffix,
849 "$src", "$src", []>, T8PD, EVEX;
852 multiclass avx512_int_broadcast_reg_vl<bits<8> opc, AVX512VLVectorVTInfo _,
853 RegisterClass SrcRC, Predicate prd> {
854 let Predicates = [prd] in
855 defm Z : avx512_int_broadcast_reg<opc, _.info512, SrcRC>, EVEX_V512;
856 let Predicates = [prd, HasVLX] in {
857 defm Z256 : avx512_int_broadcast_reg<opc, _.info256, SrcRC>, EVEX_V256;
858 defm Z128 : avx512_int_broadcast_reg<opc, _.info128, SrcRC>, EVEX_V128;
862 defm VPBROADCASTBr : avx512_int_broadcast_reg_vl<0x7A, avx512vl_i8_info, GR32,
864 defm VPBROADCASTWr : avx512_int_broadcast_reg_vl<0x7B, avx512vl_i16_info, GR32,
866 defm VPBROADCASTDr : avx512_int_broadcast_reg_vl<0x7C, avx512vl_i32_info, GR32,
868 defm VPBROADCASTQr : avx512_int_broadcast_reg_vl<0x7C, avx512vl_i64_info, GR64,
871 def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
872 (VPBROADCASTDrZrkz VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
874 def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
875 (VPBROADCASTQrZrkz VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
877 def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
878 (VPBROADCASTDrZr GR32:$src)>;
879 def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
880 (VPBROADCASTQrZr GR64:$src)>;
882 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_i32_512 (i32 GR32:$src))),
883 (VPBROADCASTDrZr GR32:$src)>;
884 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_i64_512 (i64 GR64:$src))),
885 (VPBROADCASTQrZr GR64:$src)>;
887 def : Pat<(v16i32 (int_x86_avx512_mask_pbroadcast_d_gpr_512 (i32 GR32:$src),
888 (v16i32 immAllZerosV), (i16 GR16:$mask))),
889 (VPBROADCASTDrZrkz (COPY_TO_REGCLASS GR16:$mask, VK16WM), GR32:$src)>;
890 def : Pat<(v8i64 (int_x86_avx512_mask_pbroadcast_q_gpr_512 (i64 GR64:$src),
891 (bc_v8i64 (v16i32 immAllZerosV)), (i8 GR8:$mask))),
892 (VPBROADCASTQrZrkz (COPY_TO_REGCLASS GR8:$mask, VK8WM), GR64:$src)>;
894 multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr,
895 X86MemOperand x86memop, PatFrag ld_frag,
896 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
898 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
899 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
901 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
902 def rrk : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
904 !strconcat(OpcodeStr,
905 "\t{$src, ${dst} {${mask}} |${dst} {${mask}}, $src}"),
907 def rrkz : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
909 !strconcat(OpcodeStr,
910 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
913 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
914 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
916 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
917 def rmk : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
919 !strconcat(OpcodeStr,
920 "\t{$src, ${dst} {${mask}}|${dst} {${mask}} , $src}"),
922 def rmkz : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
924 !strconcat(OpcodeStr,
925 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
926 [(set DstRC:$dst, (OpVT (vselect KRC:$mask,
927 (X86VBroadcast (ld_frag addr:$src)),
928 (OpVT (bitconvert (v16i32 immAllZerosV))))))]>, EVEX, EVEX_KZ;
932 defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem,
933 loadi32, VR512, v16i32, v4i32, VK16WM>,
934 EVEX_V512, EVEX_CD8<32, CD8VT1>;
935 defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem,
936 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W,
937 EVEX_CD8<64, CD8VT1>;
939 multiclass avx512_subvec_broadcast_rm<bits<8> opc, string OpcodeStr,
940 X86VectorVTInfo _Dst, X86VectorVTInfo _Src> {
942 def rm : AVX5128I<opc, MRMSrcMem, (outs _Dst.RC:$dst), (ins _Src.MemOp:$src),
943 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
945 (_Dst.VT (X86SubVBroadcast
946 (_Src.VT (bitconvert (_Src.LdFrag addr:$src))))))]>, EVEX;
947 def rmk : AVX5128I<opc, MRMSrcMem, (outs _Dst.RC:$dst), (ins _Dst.KRCWM:$mask,
949 !strconcat(OpcodeStr,
950 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
952 def rmkz : AVX5128I<opc, MRMSrcMem, (outs _Dst.RC:$dst), (ins _Dst.KRCWM:$mask,
954 !strconcat(OpcodeStr,
955 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
960 defm VBROADCASTI32X4 : avx512_subvec_broadcast_rm<0x5a, "vbroadcasti32x4",
961 v16i32_info, v4i32x_info>,
962 EVEX_V512, EVEX_CD8<32, CD8VT4>;
963 defm VBROADCASTF32X4 : avx512_subvec_broadcast_rm<0x1a, "vbroadcastf32x4",
964 v16f32_info, v4f32x_info>,
965 EVEX_V512, EVEX_CD8<32, CD8VT4>;
966 defm VBROADCASTI64X4 : avx512_subvec_broadcast_rm<0x5b, "vbroadcasti64x4",
967 v8i64_info, v4i64x_info>, VEX_W,
968 EVEX_V512, EVEX_CD8<64, CD8VT4>;
969 defm VBROADCASTF64X4 : avx512_subvec_broadcast_rm<0x1b, "vbroadcastf64x4",
970 v8f64_info, v4f64x_info>, VEX_W,
971 EVEX_V512, EVEX_CD8<64, CD8VT4>;
973 let Predicates = [HasVLX] in {
974 defm VBROADCASTI32X4Z256 : avx512_subvec_broadcast_rm<0x5a, "vbroadcasti32x4",
975 v8i32x_info, v4i32x_info>,
976 EVEX_V256, EVEX_CD8<32, CD8VT4>;
977 defm VBROADCASTF32X4Z256 : avx512_subvec_broadcast_rm<0x1a, "vbroadcastf32x4",
978 v8f32x_info, v4f32x_info>,
979 EVEX_V256, EVEX_CD8<32, CD8VT4>;
981 let Predicates = [HasVLX, HasDQI] in {
982 defm VBROADCASTI64X2Z128 : avx512_subvec_broadcast_rm<0x5a, "vbroadcasti64x2",
983 v4i64x_info, v2i64x_info>, VEX_W,
984 EVEX_V256, EVEX_CD8<64, CD8VT2>;
985 defm VBROADCASTF64X2Z128 : avx512_subvec_broadcast_rm<0x1a, "vbroadcastf64x2",
986 v4f64x_info, v2f64x_info>, VEX_W,
987 EVEX_V256, EVEX_CD8<64, CD8VT2>;
989 let Predicates = [HasDQI] in {
990 defm VBROADCASTI64X2 : avx512_subvec_broadcast_rm<0x5a, "vbroadcasti64x2",
991 v8i64_info, v2i64x_info>, VEX_W,
992 EVEX_V512, EVEX_CD8<64, CD8VT2>;
993 defm VBROADCASTI32X8 : avx512_subvec_broadcast_rm<0x5b, "vbroadcasti32x8",
994 v16i32_info, v8i32x_info>,
995 EVEX_V512, EVEX_CD8<32, CD8VT8>;
996 defm VBROADCASTF64X2 : avx512_subvec_broadcast_rm<0x1a, "vbroadcastf64x2",
997 v8f64_info, v2f64x_info>, VEX_W,
998 EVEX_V512, EVEX_CD8<64, CD8VT2>;
999 defm VBROADCASTF32X8 : avx512_subvec_broadcast_rm<0x1b, "vbroadcastf32x8",
1000 v16f32_info, v8f32x_info>,
1001 EVEX_V512, EVEX_CD8<32, CD8VT8>;
1004 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_512 (v4i32 VR128X:$src))),
1005 (VPBROADCASTDZrr VR128X:$src)>;
1006 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_512 (v2i64 VR128X:$src))),
1007 (VPBROADCASTQZrr VR128X:$src)>;
1009 def : Pat<(v16f32 (X86VBroadcast (v16f32 VR512:$src))),
1010 (VBROADCASTSSZr (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
1011 def : Pat<(v16f32 (X86VBroadcast (v8f32 VR256X:$src))),
1012 (VBROADCASTSSZr (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm))>;
1014 def : Pat<(v8f64 (X86VBroadcast (v8f64 VR512:$src))),
1015 (VBROADCASTSDZr (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
1016 def : Pat<(v8f64 (X86VBroadcast (v4f64 VR256X:$src))),
1017 (VBROADCASTSDZr (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm))>;
1019 def : Pat<(v16i32 (X86VBroadcast (v16i32 VR512:$src))),
1020 (VPBROADCASTDZrr (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm))>;
1021 def : Pat<(v16i32 (X86VBroadcast (v8i32 VR256X:$src))),
1022 (VPBROADCASTDZrr (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm))>;
1024 def : Pat<(v8i64 (X86VBroadcast (v8i64 VR512:$src))),
1025 (VPBROADCASTQZrr (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm))>;
1026 def : Pat<(v8i64 (X86VBroadcast (v4i64 VR256X:$src))),
1027 (VPBROADCASTQZrr (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm))>;
1029 def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))),
1030 (VBROADCASTSSZr VR128X:$src)>;
1031 def : Pat<(v8f64 (int_x86_avx512_vbroadcast_sd_pd_512 (v2f64 VR128X:$src))),
1032 (VBROADCASTSDZr VR128X:$src)>;
1034 // Provide fallback in case the load node that is used in the patterns above
1035 // is used by additional users, which prevents the pattern selection.
1036 def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
1037 (VBROADCASTSSZr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
1038 def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
1039 (VBROADCASTSDZr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
1042 //===----------------------------------------------------------------------===//
1043 // AVX-512 BROADCAST MASK TO VECTOR REGISTER
1046 multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
1047 RegisterClass KRC> {
1048 let Predicates = [HasCDI] in
1049 def Zrr : AVX512XS8I<opc, MRMSrcReg, (outs VR512:$dst), (ins KRC:$src),
1050 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1051 []>, EVEX, EVEX_V512;
1053 let Predicates = [HasCDI, HasVLX] in {
1054 def Z128rr : AVX512XS8I<opc, MRMSrcReg, (outs VR128:$dst), (ins KRC:$src),
1055 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1056 []>, EVEX, EVEX_V128;
1057 def Z256rr : AVX512XS8I<opc, MRMSrcReg, (outs VR256:$dst), (ins KRC:$src),
1058 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1059 []>, EVEX, EVEX_V256;
1063 let Predicates = [HasCDI] in {
1064 defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d",
1066 defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q",
1070 //===----------------------------------------------------------------------===//
1073 // -- immediate form --
1074 multiclass avx512_perm_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
1075 X86VectorVTInfo _> {
1076 let ExeDomain = _.ExeDomain in {
1077 def ri : AVX512AIi8<opc, MRMSrcReg, (outs _.RC:$dst),
1078 (ins _.RC:$src1, u8imm:$src2),
1079 !strconcat(OpcodeStr,
1080 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1082 (_.VT (OpNode _.RC:$src1, (i8 imm:$src2))))]>,
1084 def mi : AVX512AIi8<opc, MRMSrcMem, (outs _.RC:$dst),
1085 (ins _.MemOp:$src1, u8imm:$src2),
1086 !strconcat(OpcodeStr,
1087 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1089 (_.VT (OpNode (_.LdFrag addr:$src1),
1090 (i8 imm:$src2))))]>,
1091 EVEX, EVEX_CD8<_.EltSize, CD8VF>;
1095 multiclass avx512_permil<bits<8> OpcImm, bits<8> OpcVar, X86VectorVTInfo _,
1096 X86VectorVTInfo Ctrl> :
1097 avx512_perm_imm<OpcImm, "vpermil" # _.Suffix, X86VPermilpi, _> {
1098 let ExeDomain = _.ExeDomain in {
1099 def rr : AVX5128I<OpcVar, MRMSrcReg, (outs _.RC:$dst),
1100 (ins _.RC:$src1, _.RC:$src2),
1101 !strconcat("vpermil" # _.Suffix,
1102 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1104 (_.VT (X86VPermilpv _.RC:$src1,
1105 (Ctrl.VT Ctrl.RC:$src2))))]>,
1107 def rm : AVX5128I<OpcVar, MRMSrcMem, (outs _.RC:$dst),
1108 (ins _.RC:$src1, Ctrl.MemOp:$src2),
1109 !strconcat("vpermil" # _.Suffix,
1110 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1112 (_.VT (X86VPermilpv _.RC:$src1,
1113 (Ctrl.VT (Ctrl.LdFrag addr:$src2)))))]>,
1117 defm VPERMILPSZ : avx512_permil<0x04, 0x0C, v16f32_info, v16i32_info>,
1119 defm VPERMILPDZ : avx512_permil<0x05, 0x0D, v8f64_info, v8i64_info>,
1122 def : Pat<(v16i32 (X86VPermilpi VR512:$src1, (i8 imm:$imm))),
1123 (VPERMILPSZri VR512:$src1, imm:$imm)>;
1124 def : Pat<(v8i64 (X86VPermilpi VR512:$src1, (i8 imm:$imm))),
1125 (VPERMILPDZri VR512:$src1, imm:$imm)>;
1127 // -- VPERM2I - 3 source operands form --
1128 multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr,
1129 SDNode OpNode, X86VectorVTInfo _> {
1130 let Constraints = "$src1 = $dst" in {
1131 defm rr: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
1132 (ins _.RC:$src2, _.RC:$src3),
1133 OpcodeStr, "$src3, $src2", "$src2, $src3",
1134 (_.VT (OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3))>, EVEX_4V,
1138 defm rm: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
1139 (ins _.RC:$src2, _.MemOp:$src3),
1140 OpcodeStr, "$src3, $src2", "$src2, $src3",
1141 (_.VT (OpNode _.RC:$src1, _.RC:$src2,
1142 (_.VT (bitconvert (_.LdFrag addr:$src3)))))>,
1143 EVEX_4V, AVX5128IBase;
1146 multiclass avx512_perm_3src_mb<bits<8> opc, string OpcodeStr,
1147 SDNode OpNode, X86VectorVTInfo _> {
1148 let mayLoad = 1, Constraints = "$src1 = $dst" in
1149 defm rmb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
1150 (ins _.RC:$src2, _.ScalarMemOp:$src3),
1151 OpcodeStr, !strconcat("${src3}", _.BroadcastStr,", $src2"),
1152 !strconcat("$src2, ${src3}", _.BroadcastStr ),
1153 (_.VT (OpNode _.RC:$src1,
1154 _.RC:$src2,(_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3)))))>,
1155 AVX5128IBase, EVEX_4V, EVEX_B;
1158 multiclass avx512_perm_3src_sizes<bits<8> opc, string OpcodeStr,
1159 SDNode OpNode, AVX512VLVectorVTInfo VTInfo> {
1160 let Predicates = [HasAVX512] in
1161 defm NAME: avx512_perm_3src<opc, OpcodeStr, OpNode, VTInfo.info512>,
1162 avx512_perm_3src_mb<opc, OpcodeStr, OpNode, VTInfo.info512>, EVEX_V512;
1163 let Predicates = [HasVLX] in {
1164 defm NAME#128: avx512_perm_3src<opc, OpcodeStr, OpNode, VTInfo.info128>,
1165 avx512_perm_3src_mb<opc, OpcodeStr, OpNode, VTInfo.info128>,
1167 defm NAME#256: avx512_perm_3src<opc, OpcodeStr, OpNode, VTInfo.info256>,
1168 avx512_perm_3src_mb<opc, OpcodeStr, OpNode, VTInfo.info256>,
1172 multiclass avx512_perm_3src_sizes_w<bits<8> opc, string OpcodeStr,
1173 SDNode OpNode, AVX512VLVectorVTInfo VTInfo> {
1174 let Predicates = [HasBWI] in
1175 defm NAME: avx512_perm_3src<opc, OpcodeStr, OpNode, VTInfo.info512>,
1176 avx512_perm_3src_mb<opc, OpcodeStr, OpNode, VTInfo.info512>,
1178 let Predicates = [HasBWI, HasVLX] in {
1179 defm NAME#128: avx512_perm_3src<opc, OpcodeStr, OpNode, VTInfo.info128>,
1180 avx512_perm_3src_mb<opc, OpcodeStr, OpNode, VTInfo.info128>,
1182 defm NAME#256: avx512_perm_3src<opc, OpcodeStr, OpNode, VTInfo.info256>,
1183 avx512_perm_3src_mb<opc, OpcodeStr, OpNode, VTInfo.info256>,
1187 defm VPERMI2D : avx512_perm_3src_sizes<0x76, "vpermi2d", X86VPermiv3,
1188 avx512vl_i32_info>, EVEX_CD8<32, CD8VF>;
1189 defm VPERMI2Q : avx512_perm_3src_sizes<0x76, "vpermi2q", X86VPermiv3,
1190 avx512vl_i64_info>, VEX_W, EVEX_CD8<64, CD8VF>;
1191 defm VPERMI2PS : avx512_perm_3src_sizes<0x77, "vpermi2ps", X86VPermiv3,
1192 avx512vl_f32_info>, EVEX_CD8<32, CD8VF>;
1193 defm VPERMI2PD : avx512_perm_3src_sizes<0x77, "vpermi2pd", X86VPermiv3,
1194 avx512vl_f64_info>, VEX_W, EVEX_CD8<64, CD8VF>;
1196 defm VPERMT2D : avx512_perm_3src_sizes<0x7E, "vpermt2d", X86VPermv3,
1197 avx512vl_i32_info>, EVEX_CD8<32, CD8VF>;
1198 defm VPERMT2Q : avx512_perm_3src_sizes<0x7E, "vpermt2q", X86VPermv3,
1199 avx512vl_i64_info>, VEX_W, EVEX_CD8<64, CD8VF>;
1200 defm VPERMT2PS : avx512_perm_3src_sizes<0x7F, "vpermt2ps", X86VPermv3,
1201 avx512vl_f32_info>, EVEX_CD8<32, CD8VF>;
1202 defm VPERMT2PD : avx512_perm_3src_sizes<0x7F, "vpermt2pd", X86VPermv3,
1203 avx512vl_f64_info>, VEX_W, EVEX_CD8<64, CD8VF>;
1205 defm VPERMT2W : avx512_perm_3src_sizes_w<0x7D, "vpermt2w", X86VPermv3,
1206 avx512vl_i16_info>, VEX_W, EVEX_CD8<16, CD8VF>;
1207 defm VPERMI2W : avx512_perm_3src_sizes_w<0x75, "vpermi2w", X86VPermiv3,
1208 avx512vl_i16_info>, VEX_W, EVEX_CD8<16, CD8VF>;
1210 //===----------------------------------------------------------------------===//
1211 // AVX-512 - BLEND using mask
1213 multiclass avx512_blendmask<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
1214 let ExeDomain = _.ExeDomain in {
1215 def rr : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1216 (ins _.RC:$src1, _.RC:$src2),
1217 !strconcat(OpcodeStr,
1218 "\t{$src2, $src1, ${dst} |${dst}, $src1, $src2}"),
1220 def rrk : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1221 (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1222 !strconcat(OpcodeStr,
1223 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
1224 [(set _.RC:$dst, (X86select _.KRCWM:$mask, (_.VT _.RC:$src1),
1225 (_.VT _.RC:$src2)))]>, EVEX_4V, EVEX_K;
1226 def rrkz : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1227 (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1228 !strconcat(OpcodeStr,
1229 "\t{$src2, $src1, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src1, $src2}"),
1230 []>, EVEX_4V, EVEX_KZ;
1231 let mayLoad = 1 in {
1232 def rm : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1233 (ins _.RC:$src1, _.MemOp:$src2),
1234 !strconcat(OpcodeStr,
1235 "\t{$src2, $src1, ${dst} |${dst}, $src1, $src2}"),
1236 []>, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
1237 def rmk : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1238 (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1239 !strconcat(OpcodeStr,
1240 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
1241 [(set _.RC:$dst, (X86select _.KRCWM:$mask, (_.VT _.RC:$src1),
1242 (_.VT (bitconvert (_.LdFrag addr:$src2)))))]>,
1243 EVEX_4V, EVEX_K, EVEX_CD8<_.EltSize, CD8VF>;
1244 def rmkz : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1245 (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1246 !strconcat(OpcodeStr,
1247 "\t{$src2, $src1, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src1, $src2}"),
1248 []>, EVEX_4V, EVEX_KZ, EVEX_CD8<_.EltSize, CD8VF>;
1252 multiclass avx512_blendmask_rmb<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
1254 def rmbk : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1255 (ins _.KRCWM:$mask, _.RC:$src1, _.ScalarMemOp:$src2),
1256 !strconcat(OpcodeStr,
1257 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1258 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1259 [(set _.RC:$dst,(X86select _.KRCWM:$mask, (_.VT _.RC:$src1),
1260 (X86VBroadcast (_.ScalarLdFrag addr:$src2))))]>,
1261 EVEX_4V, EVEX_K, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
1263 def rmb : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1264 (ins _.RC:$src1, _.ScalarMemOp:$src2),
1265 !strconcat(OpcodeStr,
1266 "\t{${src2}", _.BroadcastStr, ", $src1, $dst|",
1267 "$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1268 []>, EVEX_4V, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
1272 multiclass blendmask_dq <bits<8> opc, string OpcodeStr,
1273 AVX512VLVectorVTInfo VTInfo> {
1274 defm Z : avx512_blendmask <opc, OpcodeStr, VTInfo.info512>,
1275 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info512>, EVEX_V512;
1277 let Predicates = [HasVLX] in {
1278 defm Z256 : avx512_blendmask<opc, OpcodeStr, VTInfo.info256>,
1279 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info256>, EVEX_V256;
1280 defm Z128 : avx512_blendmask<opc, OpcodeStr, VTInfo.info128>,
1281 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info128>, EVEX_V128;
1285 multiclass blendmask_bw <bits<8> opc, string OpcodeStr,
1286 AVX512VLVectorVTInfo VTInfo> {
1287 let Predicates = [HasBWI] in
1288 defm Z : avx512_blendmask <opc, OpcodeStr, VTInfo.info512>, EVEX_V512;
1290 let Predicates = [HasBWI, HasVLX] in {
1291 defm Z256 : avx512_blendmask <opc, OpcodeStr, VTInfo.info256>, EVEX_V256;
1292 defm Z128 : avx512_blendmask <opc, OpcodeStr, VTInfo.info128>, EVEX_V128;
1297 defm VBLENDMPS : blendmask_dq <0x65, "vblendmps", avx512vl_f32_info>;
1298 defm VBLENDMPD : blendmask_dq <0x65, "vblendmpd", avx512vl_f64_info>, VEX_W;
1299 defm VPBLENDMD : blendmask_dq <0x64, "vpblendmd", avx512vl_i32_info>;
1300 defm VPBLENDMQ : blendmask_dq <0x64, "vpblendmq", avx512vl_i64_info>, VEX_W;
1301 defm VPBLENDMB : blendmask_bw <0x66, "vpblendmb", avx512vl_i8_info>;
1302 defm VPBLENDMW : blendmask_bw <0x66, "vpblendmw", avx512vl_i16_info>, VEX_W;
1305 let Predicates = [HasAVX512] in {
1306 def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
1307 (v8f32 VR256X:$src2))),
1309 (v16f32 (VBLENDMPSZrrk (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1310 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1311 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1313 def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
1314 (v8i32 VR256X:$src2))),
1316 (v16i32 (VPBLENDMDZrrk (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1317 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1318 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1320 //===----------------------------------------------------------------------===//
1321 // Compare Instructions
1322 //===----------------------------------------------------------------------===//
1324 // avx512_cmp_scalar - AVX512 CMPSS and CMPSD
1325 multiclass avx512_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
1326 SDNode OpNode, ValueType VT,
1327 PatFrag ld_frag, string Suffix> {
1328 def rr : AVX512Ii8<0xC2, MRMSrcReg,
1329 (outs VK1:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
1330 !strconcat("vcmp${cc}", Suffix,
1331 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1332 [(set VK1:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
1333 IIC_SSE_ALU_F32S_RR>, EVEX_4V;
1334 def rm : AVX512Ii8<0xC2, MRMSrcMem,
1335 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, AVXCC:$cc),
1336 !strconcat("vcmp${cc}", Suffix,
1337 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1338 [(set VK1:$dst, (OpNode (VT RC:$src1),
1339 (ld_frag addr:$src2), imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1340 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1341 def rri_alt : AVX512Ii8<0xC2, MRMSrcReg,
1342 (outs VK1:$dst), (ins RC:$src1, RC:$src2, u8imm:$cc),
1343 !strconcat("vcmp", Suffix,
1344 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
1345 [], IIC_SSE_ALU_F32S_RR>, EVEX_4V;
1347 def rmi_alt : AVX512Ii8<0xC2, MRMSrcMem,
1348 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, u8imm:$cc),
1349 !strconcat("vcmp", Suffix,
1350 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
1351 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1355 let Predicates = [HasAVX512] in {
1356 defm VCMPSSZ : avx512_cmp_scalar<FR32X, f32mem, X86cmpms, f32, loadf32, "ss">,
1358 defm VCMPSDZ : avx512_cmp_scalar<FR64X, f64mem, X86cmpms, f64, loadf64, "sd">,
1362 multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
1363 X86VectorVTInfo _> {
1364 def rr : AVX512BI<opc, MRMSrcReg,
1365 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2),
1366 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1367 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2)))],
1368 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1370 def rm : AVX512BI<opc, MRMSrcMem,
1371 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2),
1372 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1373 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1374 (_.VT (bitconvert (_.LdFrag addr:$src2)))))],
1375 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1376 def rrk : AVX512BI<opc, MRMSrcReg,
1377 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1378 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1379 "$dst {${mask}}, $src1, $src2}"),
1380 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1381 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))))],
1382 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1384 def rmk : AVX512BI<opc, MRMSrcMem,
1385 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1386 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1387 "$dst {${mask}}, $src1, $src2}"),
1388 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1389 (OpNode (_.VT _.RC:$src1),
1391 (_.LdFrag addr:$src2))))))],
1392 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1395 multiclass avx512_icmp_packed_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
1396 X86VectorVTInfo _> :
1397 avx512_icmp_packed<opc, OpcodeStr, OpNode, _> {
1398 let mayLoad = 1 in {
1399 def rmb : AVX512BI<opc, MRMSrcMem,
1400 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2),
1401 !strconcat(OpcodeStr, "\t{${src2}", _.BroadcastStr, ", $src1, $dst",
1402 "|$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1403 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1404 (X86VBroadcast (_.ScalarLdFrag addr:$src2))))],
1405 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1406 def rmbk : AVX512BI<opc, MRMSrcMem,
1407 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1408 _.ScalarMemOp:$src2),
1409 !strconcat(OpcodeStr,
1410 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1411 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1412 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1413 (OpNode (_.VT _.RC:$src1),
1415 (_.ScalarLdFrag addr:$src2)))))],
1416 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1420 multiclass avx512_icmp_packed_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
1421 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1422 let Predicates = [prd] in
1423 defm Z : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info512>,
1426 let Predicates = [prd, HasVLX] in {
1427 defm Z256 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info256>,
1429 defm Z128 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info128>,
1434 multiclass avx512_icmp_packed_rmb_vl<bits<8> opc, string OpcodeStr,
1435 SDNode OpNode, AVX512VLVectorVTInfo VTInfo,
1437 let Predicates = [prd] in
1438 defm Z : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info512>,
1441 let Predicates = [prd, HasVLX] in {
1442 defm Z256 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info256>,
1444 defm Z128 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info128>,
1449 defm VPCMPEQB : avx512_icmp_packed_vl<0x74, "vpcmpeqb", X86pcmpeqm,
1450 avx512vl_i8_info, HasBWI>,
1453 defm VPCMPEQW : avx512_icmp_packed_vl<0x75, "vpcmpeqw", X86pcmpeqm,
1454 avx512vl_i16_info, HasBWI>,
1455 EVEX_CD8<16, CD8VF>;
1457 defm VPCMPEQD : avx512_icmp_packed_rmb_vl<0x76, "vpcmpeqd", X86pcmpeqm,
1458 avx512vl_i32_info, HasAVX512>,
1459 EVEX_CD8<32, CD8VF>;
1461 defm VPCMPEQQ : avx512_icmp_packed_rmb_vl<0x29, "vpcmpeqq", X86pcmpeqm,
1462 avx512vl_i64_info, HasAVX512>,
1463 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1465 defm VPCMPGTB : avx512_icmp_packed_vl<0x64, "vpcmpgtb", X86pcmpgtm,
1466 avx512vl_i8_info, HasBWI>,
1469 defm VPCMPGTW : avx512_icmp_packed_vl<0x65, "vpcmpgtw", X86pcmpgtm,
1470 avx512vl_i16_info, HasBWI>,
1471 EVEX_CD8<16, CD8VF>;
1473 defm VPCMPGTD : avx512_icmp_packed_rmb_vl<0x66, "vpcmpgtd", X86pcmpgtm,
1474 avx512vl_i32_info, HasAVX512>,
1475 EVEX_CD8<32, CD8VF>;
1477 defm VPCMPGTQ : avx512_icmp_packed_rmb_vl<0x37, "vpcmpgtq", X86pcmpgtm,
1478 avx512vl_i64_info, HasAVX512>,
1479 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1481 def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1482 (COPY_TO_REGCLASS (VPCMPGTDZrr
1483 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1484 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1486 def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1487 (COPY_TO_REGCLASS (VPCMPEQDZrr
1488 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1489 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1491 multiclass avx512_icmp_cc<bits<8> opc, string Suffix, SDNode OpNode,
1492 X86VectorVTInfo _> {
1493 def rri : AVX512AIi8<opc, MRMSrcReg,
1494 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, AVX512ICC:$cc),
1495 !strconcat("vpcmp${cc}", Suffix,
1496 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1497 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1499 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1501 def rmi : AVX512AIi8<opc, MRMSrcMem,
1502 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, AVX512ICC:$cc),
1503 !strconcat("vpcmp${cc}", Suffix,
1504 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1505 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1506 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1508 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1509 def rrik : AVX512AIi8<opc, MRMSrcReg,
1510 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1512 !strconcat("vpcmp${cc}", Suffix,
1513 "\t{$src2, $src1, $dst {${mask}}|",
1514 "$dst {${mask}}, $src1, $src2}"),
1515 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1516 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1518 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1520 def rmik : AVX512AIi8<opc, MRMSrcMem,
1521 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1523 !strconcat("vpcmp${cc}", Suffix,
1524 "\t{$src2, $src1, $dst {${mask}}|",
1525 "$dst {${mask}}, $src1, $src2}"),
1526 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1527 (OpNode (_.VT _.RC:$src1),
1528 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1530 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1532 // Accept explicit immediate argument form instead of comparison code.
1533 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1534 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
1535 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1536 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1537 "$dst, $src1, $src2, $cc}"),
1538 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1540 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
1541 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, u8imm:$cc),
1542 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1543 "$dst, $src1, $src2, $cc}"),
1544 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1545 def rrik_alt : AVX512AIi8<opc, MRMSrcReg,
1546 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1548 !strconcat("vpcmp", Suffix,
1549 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1550 "$dst {${mask}}, $src1, $src2, $cc}"),
1551 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1553 def rmik_alt : AVX512AIi8<opc, MRMSrcMem,
1554 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1556 !strconcat("vpcmp", Suffix,
1557 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1558 "$dst {${mask}}, $src1, $src2, $cc}"),
1559 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1563 multiclass avx512_icmp_cc_rmb<bits<8> opc, string Suffix, SDNode OpNode,
1564 X86VectorVTInfo _> :
1565 avx512_icmp_cc<opc, Suffix, OpNode, _> {
1566 def rmib : AVX512AIi8<opc, MRMSrcMem,
1567 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1569 !strconcat("vpcmp${cc}", Suffix,
1570 "\t{${src2}", _.BroadcastStr, ", $src1, $dst|",
1571 "$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1572 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1573 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1575 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1576 def rmibk : AVX512AIi8<opc, MRMSrcMem,
1577 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1578 _.ScalarMemOp:$src2, AVX512ICC:$cc),
1579 !strconcat("vpcmp${cc}", Suffix,
1580 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1581 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1582 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1583 (OpNode (_.VT _.RC:$src1),
1584 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1586 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1588 // Accept explicit immediate argument form instead of comparison code.
1589 let isAsmParserOnly = 1, hasSideEffects = 0, mayLoad = 1 in {
1590 def rmib_alt : AVX512AIi8<opc, MRMSrcMem,
1591 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1593 !strconcat("vpcmp", Suffix,
1594 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst|",
1595 "$dst, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1596 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1597 def rmibk_alt : AVX512AIi8<opc, MRMSrcMem,
1598 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1599 _.ScalarMemOp:$src2, u8imm:$cc),
1600 !strconcat("vpcmp", Suffix,
1601 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1602 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1603 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1607 multiclass avx512_icmp_cc_vl<bits<8> opc, string Suffix, SDNode OpNode,
1608 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1609 let Predicates = [prd] in
1610 defm Z : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info512>, EVEX_V512;
1612 let Predicates = [prd, HasVLX] in {
1613 defm Z256 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info256>, EVEX_V256;
1614 defm Z128 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info128>, EVEX_V128;
1618 multiclass avx512_icmp_cc_rmb_vl<bits<8> opc, string Suffix, SDNode OpNode,
1619 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1620 let Predicates = [prd] in
1621 defm Z : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info512>,
1624 let Predicates = [prd, HasVLX] in {
1625 defm Z256 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info256>,
1627 defm Z128 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info128>,
1632 defm VPCMPB : avx512_icmp_cc_vl<0x3F, "b", X86cmpm, avx512vl_i8_info,
1633 HasBWI>, EVEX_CD8<8, CD8VF>;
1634 defm VPCMPUB : avx512_icmp_cc_vl<0x3E, "ub", X86cmpmu, avx512vl_i8_info,
1635 HasBWI>, EVEX_CD8<8, CD8VF>;
1637 defm VPCMPW : avx512_icmp_cc_vl<0x3F, "w", X86cmpm, avx512vl_i16_info,
1638 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1639 defm VPCMPUW : avx512_icmp_cc_vl<0x3E, "uw", X86cmpmu, avx512vl_i16_info,
1640 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1642 defm VPCMPD : avx512_icmp_cc_rmb_vl<0x1F, "d", X86cmpm, avx512vl_i32_info,
1643 HasAVX512>, EVEX_CD8<32, CD8VF>;
1644 defm VPCMPUD : avx512_icmp_cc_rmb_vl<0x1E, "ud", X86cmpmu, avx512vl_i32_info,
1645 HasAVX512>, EVEX_CD8<32, CD8VF>;
1647 defm VPCMPQ : avx512_icmp_cc_rmb_vl<0x1F, "q", X86cmpm, avx512vl_i64_info,
1648 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1649 defm VPCMPUQ : avx512_icmp_cc_rmb_vl<0x1E, "uq", X86cmpmu, avx512vl_i64_info,
1650 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1652 multiclass avx512_vcmp_common<X86VectorVTInfo _> {
1654 defm rri : AVX512_maskable_cmp<0xC2, MRMSrcReg, _,
1655 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2,AVXCC:$cc),
1656 "vcmp${cc}"#_.Suffix,
1657 "$src2, $src1", "$src1, $src2",
1658 (X86cmpm (_.VT _.RC:$src1),
1662 let mayLoad = 1 in {
1663 defm rmi : AVX512_maskable_cmp<0xC2, MRMSrcMem, _,
1664 (outs _.KRC:$dst),(ins _.RC:$src1, _.MemOp:$src2, AVXCC:$cc),
1665 "vcmp${cc}"#_.Suffix,
1666 "$src2, $src1", "$src1, $src2",
1667 (X86cmpm (_.VT _.RC:$src1),
1668 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1671 defm rmbi : AVX512_maskable_cmp<0xC2, MRMSrcMem, _,
1673 (ins _.RC:$src1, _.ScalarMemOp:$src2, AVXCC:$cc),
1674 "vcmp${cc}"#_.Suffix,
1675 "${src2}"##_.BroadcastStr##", $src1",
1676 "$src1, ${src2}"##_.BroadcastStr,
1677 (X86cmpm (_.VT _.RC:$src1),
1678 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src2))),
1681 // Accept explicit immediate argument form instead of comparison code.
1682 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1683 defm rri_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcReg, _,
1685 (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1687 "$cc, $src2, $src1", "$src1, $src2, $cc">;
1689 let mayLoad = 1 in {
1690 defm rmi_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcMem, _,
1692 (ins _.RC:$src1, _.MemOp:$src2, u8imm:$cc),
1694 "$cc, $src2, $src1", "$src1, $src2, $cc">;
1696 defm rmbi_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcMem, _,
1698 (ins _.RC:$src1, _.ScalarMemOp:$src2, u8imm:$cc),
1700 "$cc, ${src2}"##_.BroadcastStr##", $src1",
1701 "$src1, ${src2}"##_.BroadcastStr##", $cc">,EVEX_B;
1706 multiclass avx512_vcmp_sae<X86VectorVTInfo _> {
1707 // comparison code form (VCMP[EQ/LT/LE/...]
1708 defm rrib : AVX512_maskable_cmp<0xC2, MRMSrcReg, _,
1709 (outs _.KRC:$dst),(ins _.RC:$src1, _.RC:$src2, AVXCC:$cc),
1710 "vcmp${cc}"#_.Suffix,
1711 "{sae}, $src2, $src1", "$src1, $src2,{sae}",
1712 (X86cmpmRnd (_.VT _.RC:$src1),
1715 (i32 FROUND_NO_EXC))>, EVEX_B;
1717 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1718 defm rrib_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcReg, _,
1720 (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1722 "$cc,{sae}, $src2, $src1",
1723 "$src1, $src2,{sae}, $cc">, EVEX_B;
1727 multiclass avx512_vcmp<AVX512VLVectorVTInfo _> {
1728 let Predicates = [HasAVX512] in {
1729 defm Z : avx512_vcmp_common<_.info512>,
1730 avx512_vcmp_sae<_.info512>, EVEX_V512;
1733 let Predicates = [HasAVX512,HasVLX] in {
1734 defm Z128 : avx512_vcmp_common<_.info128>, EVEX_V128;
1735 defm Z256 : avx512_vcmp_common<_.info256>, EVEX_V256;
1739 defm VCMPPD : avx512_vcmp<avx512vl_f64_info>,
1740 AVX512PDIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
1741 defm VCMPPS : avx512_vcmp<avx512vl_f32_info>,
1742 AVX512PSIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
1744 def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
1745 (COPY_TO_REGCLASS (VCMPPSZrri
1746 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1747 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1749 def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1750 (COPY_TO_REGCLASS (VPCMPDZrri
1751 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1752 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1754 def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1755 (COPY_TO_REGCLASS (VPCMPUDZrri
1756 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1757 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1760 //-----------------------------------------------------------------
1761 // Mask register copy, including
1762 // - copy between mask registers
1763 // - load/store mask registers
1764 // - copy from GPR to mask register and vice versa
1766 multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
1767 string OpcodeStr, RegisterClass KRC,
1768 ValueType vvt, X86MemOperand x86memop> {
1769 let hasSideEffects = 0 in {
1770 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1771 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1773 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
1774 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1775 [(set KRC:$dst, (vvt (load addr:$src)))]>;
1777 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
1778 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1779 [(store KRC:$src, addr:$dst)]>;
1783 multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
1785 RegisterClass KRC, RegisterClass GRC> {
1786 let hasSideEffects = 0 in {
1787 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
1788 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1789 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
1790 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1794 let Predicates = [HasDQI] in
1795 defm KMOVB : avx512_mask_mov<0x90, 0x90, 0x91, "kmovb", VK8, v8i1, i8mem>,
1796 avx512_mask_mov_gpr<0x92, 0x93, "kmovb", VK8, GR32>,
1799 let Predicates = [HasAVX512] in
1800 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16mem>,
1801 avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
1804 let Predicates = [HasBWI] in {
1805 defm KMOVD : avx512_mask_mov<0x90, 0x90, 0x91, "kmovd", VK32, v32i1,i32mem>,
1807 defm KMOVD : avx512_mask_mov_gpr<0x92, 0x93, "kmovd", VK32, GR32>,
1811 let Predicates = [HasBWI] in {
1812 defm KMOVQ : avx512_mask_mov<0x90, 0x90, 0x91, "kmovq", VK64, v64i1, i64mem>,
1814 defm KMOVQ : avx512_mask_mov_gpr<0x92, 0x93, "kmovq", VK64, GR64>,
1818 // GR from/to mask register
1819 let Predicates = [HasDQI] in {
1820 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1821 (KMOVBkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit))>;
1822 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1823 (EXTRACT_SUBREG (KMOVBrk VK8:$src), sub_8bit)>;
1825 let Predicates = [HasAVX512] in {
1826 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
1827 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
1828 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
1829 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
1831 let Predicates = [HasBWI] in {
1832 def : Pat<(v32i1 (bitconvert (i32 GR32:$src))), (KMOVDkr GR32:$src)>;
1833 def : Pat<(i32 (bitconvert (v32i1 VK32:$src))), (KMOVDrk VK32:$src)>;
1835 let Predicates = [HasBWI] in {
1836 def : Pat<(v64i1 (bitconvert (i64 GR64:$src))), (KMOVQkr GR64:$src)>;
1837 def : Pat<(i64 (bitconvert (v64i1 VK64:$src))), (KMOVQrk VK64:$src)>;
1841 let Predicates = [HasDQI] in {
1842 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
1843 (KMOVBmk addr:$dst, VK8:$src)>;
1844 def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
1845 (KMOVBkm addr:$src)>;
1847 def : Pat<(store VK4:$src, addr:$dst),
1848 (KMOVBmk addr:$dst, (COPY_TO_REGCLASS VK4:$src, VK8))>;
1849 def : Pat<(store VK2:$src, addr:$dst),
1850 (KMOVBmk addr:$dst, (COPY_TO_REGCLASS VK2:$src, VK8))>;
1852 let Predicates = [HasAVX512, NoDQI] in {
1853 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
1854 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>;
1855 def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
1856 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK8)>;
1858 let Predicates = [HasAVX512] in {
1859 def : Pat<(store (i16 (bitconvert (v16i1 VK16:$src))), addr:$dst),
1860 (KMOVWmk addr:$dst, VK16:$src)>;
1861 def : Pat<(i1 (load addr:$src)),
1862 (COPY_TO_REGCLASS (AND16ri (i16 (SUBREG_TO_REG (i32 0),
1863 (MOV8rm addr:$src), sub_8bit)),
1865 def : Pat<(v16i1 (bitconvert (i16 (load addr:$src)))),
1866 (KMOVWkm addr:$src)>;
1868 let Predicates = [HasBWI] in {
1869 def : Pat<(store (i32 (bitconvert (v32i1 VK32:$src))), addr:$dst),
1870 (KMOVDmk addr:$dst, VK32:$src)>;
1871 def : Pat<(v32i1 (bitconvert (i32 (load addr:$src)))),
1872 (KMOVDkm addr:$src)>;
1874 let Predicates = [HasBWI] in {
1875 def : Pat<(store (i64 (bitconvert (v64i1 VK64:$src))), addr:$dst),
1876 (KMOVQmk addr:$dst, VK64:$src)>;
1877 def : Pat<(v64i1 (bitconvert (i64 (load addr:$src)))),
1878 (KMOVQkm addr:$src)>;
1881 let Predicates = [HasAVX512] in {
1882 def : Pat<(i1 (trunc (i64 GR64:$src))),
1883 (COPY_TO_REGCLASS (KMOVWkr (AND32ri (EXTRACT_SUBREG $src, sub_32bit),
1886 def : Pat<(i1 (trunc (i32 GR32:$src))),
1887 (COPY_TO_REGCLASS (KMOVWkr (AND32ri $src, (i32 1))), VK1)>;
1889 def : Pat<(i1 (trunc (i8 GR8:$src))),
1891 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit), (i32 1))),
1893 def : Pat<(i1 (trunc (i16 GR16:$src))),
1895 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), $src, sub_16bit), (i32 1))),
1898 def : Pat<(i32 (zext VK1:$src)),
1899 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1))>;
1900 def : Pat<(i32 (anyext VK1:$src)),
1901 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16))>;
1902 def : Pat<(i8 (zext VK1:$src)),
1905 (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)), sub_8bit)>;
1906 def : Pat<(i64 (zext VK1:$src)),
1907 (AND64ri8 (SUBREG_TO_REG (i64 0),
1908 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_32bit), (i64 1))>;
1909 def : Pat<(i16 (zext VK1:$src)),
1911 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)),
1913 def : Pat<(v16i1 (scalar_to_vector VK1:$src)),
1914 (COPY_TO_REGCLASS VK1:$src, VK16)>;
1915 def : Pat<(v8i1 (scalar_to_vector VK1:$src)),
1916 (COPY_TO_REGCLASS VK1:$src, VK8)>;
1918 let Predicates = [HasBWI] in {
1919 def : Pat<(v32i1 (scalar_to_vector VK1:$src)),
1920 (COPY_TO_REGCLASS VK1:$src, VK32)>;
1921 def : Pat<(v64i1 (scalar_to_vector VK1:$src)),
1922 (COPY_TO_REGCLASS VK1:$src, VK64)>;
1926 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1927 let Predicates = [HasAVX512, NoDQI] in {
1928 // GR from/to 8-bit mask without native support
1929 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1931 (KMOVWkr (MOVZX32rr8 GR8 :$src)), VK8)>;
1932 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1934 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
1938 let Predicates = [HasAVX512] in {
1939 def : Pat<(i1 (X86Vextract VK16:$src, (iPTR 0))),
1940 (COPY_TO_REGCLASS VK16:$src, VK1)>;
1941 def : Pat<(i1 (X86Vextract VK8:$src, (iPTR 0))),
1942 (COPY_TO_REGCLASS VK8:$src, VK1)>;
1944 let Predicates = [HasBWI] in {
1945 def : Pat<(i1 (X86Vextract VK32:$src, (iPTR 0))),
1946 (COPY_TO_REGCLASS VK32:$src, VK1)>;
1947 def : Pat<(i1 (X86Vextract VK64:$src, (iPTR 0))),
1948 (COPY_TO_REGCLASS VK64:$src, VK1)>;
1951 // Mask unary operation
1953 multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
1954 RegisterClass KRC, SDPatternOperator OpNode,
1956 let Predicates = [prd] in
1957 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1958 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1959 [(set KRC:$dst, (OpNode KRC:$src))]>;
1962 multiclass avx512_mask_unop_all<bits<8> opc, string OpcodeStr,
1963 SDPatternOperator OpNode> {
1964 defm B : avx512_mask_unop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
1966 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
1967 HasAVX512>, VEX, PS;
1968 defm D : avx512_mask_unop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
1969 HasBWI>, VEX, PD, VEX_W;
1970 defm Q : avx512_mask_unop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
1971 HasBWI>, VEX, PS, VEX_W;
1974 defm KNOT : avx512_mask_unop_all<0x44, "knot", not>;
1976 multiclass avx512_mask_unop_int<string IntName, string InstName> {
1977 let Predicates = [HasAVX512] in
1978 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1980 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1981 (v16i1 (COPY_TO_REGCLASS GR16:$src, VK16))), GR16)>;
1983 defm : avx512_mask_unop_int<"knot", "KNOT">;
1985 let Predicates = [HasDQI] in
1986 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)), (KNOTBrr VK8:$src1)>;
1987 let Predicates = [HasAVX512] in
1988 def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
1989 let Predicates = [HasBWI] in
1990 def : Pat<(xor VK32:$src1, (v32i1 immAllOnesV)), (KNOTDrr VK32:$src1)>;
1991 let Predicates = [HasBWI] in
1992 def : Pat<(xor VK64:$src1, (v64i1 immAllOnesV)), (KNOTQrr VK64:$src1)>;
1994 // KNL does not support KMOVB, 8-bit mask is promoted to 16-bit
1995 let Predicates = [HasAVX512, NoDQI] in {
1996 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
1997 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
1998 def : Pat<(not VK8:$src),
2000 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
2002 def : Pat<(xor VK4:$src1, (v4i1 immAllOnesV)),
2003 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK4:$src1, VK16)), VK4)>;
2004 def : Pat<(xor VK2:$src1, (v2i1 immAllOnesV)),
2005 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK2:$src1, VK16)), VK2)>;
2007 // Mask binary operation
2008 // - KAND, KANDN, KOR, KXNOR, KXOR
2009 multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
2010 RegisterClass KRC, SDPatternOperator OpNode,
2011 Predicate prd, bit IsCommutable> {
2012 let Predicates = [prd], isCommutable = IsCommutable in
2013 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
2014 !strconcat(OpcodeStr,
2015 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2016 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
2019 multiclass avx512_mask_binop_all<bits<8> opc, string OpcodeStr,
2020 SDPatternOperator OpNode, bit IsCommutable,
2021 Predicate prdW = HasAVX512> {
2022 defm B : avx512_mask_binop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
2023 HasDQI, IsCommutable>, VEX_4V, VEX_L, PD;
2024 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
2025 prdW, IsCommutable>, VEX_4V, VEX_L, PS;
2026 defm D : avx512_mask_binop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
2027 HasBWI, IsCommutable>, VEX_4V, VEX_L, VEX_W, PD;
2028 defm Q : avx512_mask_binop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
2029 HasBWI, IsCommutable>, VEX_4V, VEX_L, VEX_W, PS;
2032 def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
2033 def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
2035 defm KAND : avx512_mask_binop_all<0x41, "kand", and, 1>;
2036 defm KOR : avx512_mask_binop_all<0x45, "kor", or, 1>;
2037 defm KXNOR : avx512_mask_binop_all<0x46, "kxnor", xnor, 1>;
2038 defm KXOR : avx512_mask_binop_all<0x47, "kxor", xor, 1>;
2039 defm KANDN : avx512_mask_binop_all<0x42, "kandn", andn, 0>;
2040 defm KADD : avx512_mask_binop_all<0x4A, "kadd", add, 1, HasDQI>;
2042 multiclass avx512_mask_binop_int<string IntName, string InstName> {
2043 let Predicates = [HasAVX512] in
2044 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
2045 (i16 GR16:$src1), (i16 GR16:$src2)),
2046 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
2047 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
2048 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
2051 defm : avx512_mask_binop_int<"kand", "KAND">;
2052 defm : avx512_mask_binop_int<"kandn", "KANDN">;
2053 defm : avx512_mask_binop_int<"kor", "KOR">;
2054 defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
2055 defm : avx512_mask_binop_int<"kxor", "KXOR">;
2057 multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
2058 // With AVX512F, 8-bit mask is promoted to 16-bit mask,
2059 // for the DQI set, this type is legal and KxxxB instruction is used
2060 let Predicates = [NoDQI] in
2061 def : Pat<(OpNode VK8:$src1, VK8:$src2),
2063 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
2064 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
2066 // All types smaller than 8 bits require conversion anyway
2067 def : Pat<(OpNode VK1:$src1, VK1:$src2),
2068 (COPY_TO_REGCLASS (Inst
2069 (COPY_TO_REGCLASS VK1:$src1, VK16),
2070 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
2071 def : Pat<(OpNode VK2:$src1, VK2:$src2),
2072 (COPY_TO_REGCLASS (Inst
2073 (COPY_TO_REGCLASS VK2:$src1, VK16),
2074 (COPY_TO_REGCLASS VK2:$src2, VK16)), VK1)>;
2075 def : Pat<(OpNode VK4:$src1, VK4:$src2),
2076 (COPY_TO_REGCLASS (Inst
2077 (COPY_TO_REGCLASS VK4:$src1, VK16),
2078 (COPY_TO_REGCLASS VK4:$src2, VK16)), VK1)>;
2081 defm : avx512_binop_pat<and, KANDWrr>;
2082 defm : avx512_binop_pat<andn, KANDNWrr>;
2083 defm : avx512_binop_pat<or, KORWrr>;
2084 defm : avx512_binop_pat<xnor, KXNORWrr>;
2085 defm : avx512_binop_pat<xor, KXORWrr>;
2087 def : Pat<(xor (xor VK16:$src1, VK16:$src2), (v16i1 immAllOnesV)),
2088 (KXNORWrr VK16:$src1, VK16:$src2)>;
2089 def : Pat<(xor (xor VK8:$src1, VK8:$src2), (v8i1 immAllOnesV)),
2090 (KXNORBrr VK8:$src1, VK8:$src2)>, Requires<[HasDQI]>;
2091 def : Pat<(xor (xor VK32:$src1, VK32:$src2), (v32i1 immAllOnesV)),
2092 (KXNORDrr VK32:$src1, VK32:$src2)>, Requires<[HasBWI]>;
2093 def : Pat<(xor (xor VK64:$src1, VK64:$src2), (v64i1 immAllOnesV)),
2094 (KXNORQrr VK64:$src1, VK64:$src2)>, Requires<[HasBWI]>;
2096 let Predicates = [NoDQI] in
2097 def : Pat<(xor (xor VK8:$src1, VK8:$src2), (v8i1 immAllOnesV)),
2098 (COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK8:$src1, VK16),
2099 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
2101 def : Pat<(xor (xor VK4:$src1, VK4:$src2), (v4i1 immAllOnesV)),
2102 (COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK4:$src1, VK16),
2103 (COPY_TO_REGCLASS VK4:$src2, VK16)), VK4)>;
2105 def : Pat<(xor (xor VK2:$src1, VK2:$src2), (v2i1 immAllOnesV)),
2106 (COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK2:$src1, VK16),
2107 (COPY_TO_REGCLASS VK2:$src2, VK16)), VK2)>;
2109 def : Pat<(xor (xor VK1:$src1, VK1:$src2), (i1 1)),
2110 (COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
2111 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
2114 multiclass avx512_mask_unpck<string Suffix,RegisterClass KRC, ValueType VT,
2115 RegisterClass KRCSrc, Predicate prd> {
2116 let Predicates = [prd] in {
2117 def rr : I<0x4b, MRMSrcReg, (outs KRC:$dst),
2118 (ins KRC:$src1, KRC:$src2),
2119 "kunpck"#Suffix#"\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
2122 def : Pat<(VT (concat_vectors KRCSrc:$src1, KRCSrc:$src2)),
2123 (!cast<Instruction>(NAME##rr)
2124 (COPY_TO_REGCLASS KRCSrc:$src2, KRC),
2125 (COPY_TO_REGCLASS KRCSrc:$src1, KRC))>;
2129 defm KUNPCKBW : avx512_mask_unpck<"bw", VK16, v16i1, VK8, HasAVX512>, PD;
2130 defm KUNPCKWD : avx512_mask_unpck<"wd", VK32, v32i1, VK16, HasBWI>, PS;
2131 defm KUNPCKDQ : avx512_mask_unpck<"dq", VK64, v64i1, VK32, HasBWI>, PS, VEX_W;
2133 multiclass avx512_mask_unpck_int<string IntName, string InstName> {
2134 let Predicates = [HasAVX512] in
2135 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_bw")
2136 (i16 GR16:$src1), (i16 GR16:$src2)),
2137 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"BWrr")
2138 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
2139 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
2141 defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
2144 multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
2145 SDNode OpNode, Predicate prd> {
2146 let Predicates = [prd], Defs = [EFLAGS] in
2147 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
2148 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2149 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
2152 multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode,
2153 Predicate prdW = HasAVX512> {
2154 defm B : avx512_mask_testop<opc, OpcodeStr#"b", VK8, OpNode, HasDQI>,
2156 defm W : avx512_mask_testop<opc, OpcodeStr#"w", VK16, OpNode, prdW>,
2158 defm Q : avx512_mask_testop<opc, OpcodeStr#"q", VK64, OpNode, HasBWI>,
2160 defm D : avx512_mask_testop<opc, OpcodeStr#"d", VK32, OpNode, HasBWI>,
2164 defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
2165 defm KTEST : avx512_mask_testop_w<0x99, "ktest", X86ktest, HasDQI>;
2168 multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
2170 let Predicates = [HasAVX512] in
2171 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, u8imm:$imm),
2172 !strconcat(OpcodeStr,
2173 "\t{$imm, $src, $dst|$dst, $src, $imm}"),
2174 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
2177 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
2179 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
2181 let Predicates = [HasDQI] in
2182 defm B : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "b"), VK8, OpNode>,
2184 let Predicates = [HasBWI] in {
2185 defm Q : avx512_mask_shiftop<opc2, !strconcat(OpcodeStr, "q"), VK64, OpNode>,
2187 let Predicates = [HasDQI] in
2188 defm D : avx512_mask_shiftop<opc2, !strconcat(OpcodeStr, "d"), VK32, OpNode>,
2193 defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86vshli>;
2194 defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86vsrli>;
2196 // Mask setting all 0s or 1s
2197 multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
2198 let Predicates = [HasAVX512] in
2199 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
2200 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
2201 [(set KRC:$dst, (VT Val))]>;
2204 multiclass avx512_mask_setop_w<PatFrag Val> {
2205 defm B : avx512_mask_setop<VK8, v8i1, Val>;
2206 defm W : avx512_mask_setop<VK16, v16i1, Val>;
2207 defm D : avx512_mask_setop<VK32, v32i1, Val>;
2208 defm Q : avx512_mask_setop<VK64, v64i1, Val>;
2211 defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
2212 defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
2214 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
2215 let Predicates = [HasAVX512] in {
2216 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
2217 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
2218 def : Pat<(v4i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK4)>;
2219 def : Pat<(v2i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK2)>;
2220 def : Pat<(i1 0), (COPY_TO_REGCLASS (KSET0W), VK1)>;
2221 def : Pat<(i1 1), (COPY_TO_REGCLASS (KSHIFTRWri (KSET1W), (i8 15)), VK1)>;
2222 def : Pat<(i1 -1), (COPY_TO_REGCLASS (KSHIFTRWri (KSET1W), (i8 15)), VK1)>;
2224 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
2225 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
2227 def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
2228 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
2230 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
2231 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
2233 def : Pat<(v32i1 (extract_subvector (v64i1 VK64:$src), (iPTR 0))),
2234 (v32i1 (COPY_TO_REGCLASS VK64:$src, VK32))>;
2236 def : Pat<(v32i1 (extract_subvector (v64i1 VK64:$src), (iPTR 32))),
2237 (v32i1 (COPY_TO_REGCLASS (KSHIFTRQri VK64:$src, (i8 32)), VK32))>;
2239 let Predicates = [HasVLX] in {
2240 def : Pat<(v8i1 (insert_subvector undef, (v4i1 VK4:$src), (iPTR 0))),
2241 (v8i1 (COPY_TO_REGCLASS VK4:$src, VK8))>;
2242 def : Pat<(v8i1 (insert_subvector undef, (v2i1 VK2:$src), (iPTR 0))),
2243 (v8i1 (COPY_TO_REGCLASS VK2:$src, VK8))>;
2244 def : Pat<(v4i1 (insert_subvector undef, (v2i1 VK2:$src), (iPTR 0))),
2245 (v4i1 (COPY_TO_REGCLASS VK2:$src, VK4))>;
2246 def : Pat<(v4i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
2247 (v4i1 (COPY_TO_REGCLASS VK8:$src, VK4))>;
2248 def : Pat<(v2i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
2249 (v2i1 (COPY_TO_REGCLASS VK8:$src, VK2))>;
2252 def : Pat<(v8i1 (X86vshli VK8:$src, (i8 imm:$imm))),
2253 (v8i1 (COPY_TO_REGCLASS
2254 (KSHIFTLWri (COPY_TO_REGCLASS VK8:$src, VK16),
2255 (I8Imm $imm)), VK8))>, Requires<[HasAVX512, NoDQI]>;
2257 def : Pat<(v8i1 (X86vsrli VK8:$src, (i8 imm:$imm))),
2258 (v8i1 (COPY_TO_REGCLASS
2259 (KSHIFTRWri (COPY_TO_REGCLASS VK8:$src, VK16),
2260 (I8Imm $imm)), VK8))>, Requires<[HasAVX512, NoDQI]>;
2262 def : Pat<(v4i1 (X86vshli VK4:$src, (i8 imm:$imm))),
2263 (v4i1 (COPY_TO_REGCLASS
2264 (KSHIFTLWri (COPY_TO_REGCLASS VK4:$src, VK16),
2265 (I8Imm $imm)), VK4))>, Requires<[HasAVX512]>;
2267 def : Pat<(v4i1 (X86vsrli VK4:$src, (i8 imm:$imm))),
2268 (v4i1 (COPY_TO_REGCLASS
2269 (KSHIFTRWri (COPY_TO_REGCLASS VK4:$src, VK16),
2270 (I8Imm $imm)), VK4))>, Requires<[HasAVX512]>;
2272 //===----------------------------------------------------------------------===//
2273 // AVX-512 - Aligned and unaligned load and store
2277 multiclass avx512_load<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
2278 PatFrag ld_frag, PatFrag mload,
2279 bit IsReMaterializable = 1> {
2280 let hasSideEffects = 0 in {
2281 def rr : AVX512PI<opc, MRMSrcReg, (outs _.RC:$dst), (ins _.RC:$src),
2282 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [],
2284 def rrkz : AVX512PI<opc, MRMSrcReg, (outs _.RC:$dst),
2285 (ins _.KRCWM:$mask, _.RC:$src),
2286 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
2287 "${dst} {${mask}} {z}, $src}"), [], _.ExeDomain>,
2290 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable,
2291 SchedRW = [WriteLoad] in
2292 def rm : AVX512PI<opc, MRMSrcMem, (outs _.RC:$dst), (ins _.MemOp:$src),
2293 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2294 [(set _.RC:$dst, (_.VT (bitconvert (ld_frag addr:$src))))],
2297 let Constraints = "$src0 = $dst" in {
2298 def rrk : AVX512PI<opc, MRMSrcReg, (outs _.RC:$dst),
2299 (ins _.RC:$src0, _.KRCWM:$mask, _.RC:$src1),
2300 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
2301 "${dst} {${mask}}, $src1}"),
2302 [(set _.RC:$dst, (_.VT (vselect _.KRCWM:$mask,
2304 (_.VT _.RC:$src0))))], _.ExeDomain>,
2306 let mayLoad = 1, SchedRW = [WriteLoad] in
2307 def rmk : AVX512PI<opc, MRMSrcMem, (outs _.RC:$dst),
2308 (ins _.RC:$src0, _.KRCWM:$mask, _.MemOp:$src1),
2309 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
2310 "${dst} {${mask}}, $src1}"),
2311 [(set _.RC:$dst, (_.VT
2312 (vselect _.KRCWM:$mask,
2313 (_.VT (bitconvert (ld_frag addr:$src1))),
2314 (_.VT _.RC:$src0))))], _.ExeDomain>, EVEX, EVEX_K;
2316 let mayLoad = 1, SchedRW = [WriteLoad] in
2317 def rmkz : AVX512PI<opc, MRMSrcMem, (outs _.RC:$dst),
2318 (ins _.KRCWM:$mask, _.MemOp:$src),
2319 OpcodeStr #"\t{$src, ${dst} {${mask}} {z}|"#
2320 "${dst} {${mask}} {z}, $src}",
2321 [(set _.RC:$dst, (_.VT (vselect _.KRCWM:$mask,
2322 (_.VT (bitconvert (ld_frag addr:$src))), _.ImmAllZerosV)))],
2323 _.ExeDomain>, EVEX, EVEX_KZ;
2325 def : Pat<(_.VT (mload addr:$ptr, _.KRCWM:$mask, undef)),
2326 (!cast<Instruction>(NAME#_.ZSuffix##rmkz) _.KRCWM:$mask, addr:$ptr)>;
2328 def : Pat<(_.VT (mload addr:$ptr, _.KRCWM:$mask, _.ImmAllZerosV)),
2329 (!cast<Instruction>(NAME#_.ZSuffix##rmkz) _.KRCWM:$mask, addr:$ptr)>;
2331 def : Pat<(_.VT (mload addr:$ptr, _.KRCWM:$mask, (_.VT _.RC:$src0))),
2332 (!cast<Instruction>(NAME#_.ZSuffix##rmk) _.RC:$src0,
2333 _.KRCWM:$mask, addr:$ptr)>;
2336 multiclass avx512_alignedload_vl<bits<8> opc, string OpcodeStr,
2337 AVX512VLVectorVTInfo _,
2339 bit IsReMaterializable = 1> {
2340 let Predicates = [prd] in
2341 defm Z : avx512_load<opc, OpcodeStr, _.info512, _.info512.AlignedLdFrag,
2342 masked_load_aligned512, IsReMaterializable>, EVEX_V512;
2344 let Predicates = [prd, HasVLX] in {
2345 defm Z256 : avx512_load<opc, OpcodeStr, _.info256, _.info256.AlignedLdFrag,
2346 masked_load_aligned256, IsReMaterializable>, EVEX_V256;
2347 defm Z128 : avx512_load<opc, OpcodeStr, _.info128, _.info128.AlignedLdFrag,
2348 masked_load_aligned128, IsReMaterializable>, EVEX_V128;
2352 multiclass avx512_load_vl<bits<8> opc, string OpcodeStr,
2353 AVX512VLVectorVTInfo _,
2355 bit IsReMaterializable = 1> {
2356 let Predicates = [prd] in
2357 defm Z : avx512_load<opc, OpcodeStr, _.info512, _.info512.LdFrag,
2358 masked_load_unaligned, IsReMaterializable>, EVEX_V512;
2360 let Predicates = [prd, HasVLX] in {
2361 defm Z256 : avx512_load<opc, OpcodeStr, _.info256, _.info256.LdFrag,
2362 masked_load_unaligned, IsReMaterializable>, EVEX_V256;
2363 defm Z128 : avx512_load<opc, OpcodeStr, _.info128, _.info128.LdFrag,
2364 masked_load_unaligned, IsReMaterializable>, EVEX_V128;
2368 multiclass avx512_store<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
2369 PatFrag st_frag, PatFrag mstore> {
2370 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
2371 def rr_alt : AVX512PI<opc, MRMDestReg, (outs _.RC:$dst), (ins _.RC:$src),
2372 OpcodeStr # "\t{$src, $dst|$dst, $src}", [],
2374 let Constraints = "$src1 = $dst" in
2375 def rrk_alt : AVX512PI<opc, MRMDestReg, (outs _.RC:$dst),
2376 (ins _.RC:$src1, _.KRCWM:$mask, _.RC:$src2),
2378 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}",
2379 [], _.ExeDomain>, EVEX, EVEX_K;
2380 def rrkz_alt : AVX512PI<opc, MRMDestReg, (outs _.RC:$dst),
2381 (ins _.KRCWM:$mask, _.RC:$src),
2383 "\t{$src, ${dst} {${mask}} {z}|" #
2384 "${dst} {${mask}} {z}, $src}",
2385 [], _.ExeDomain>, EVEX, EVEX_KZ;
2387 let mayStore = 1 in {
2388 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins _.MemOp:$dst, _.RC:$src),
2389 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2390 [(st_frag (_.VT _.RC:$src), addr:$dst)], _.ExeDomain>, EVEX;
2391 def mrk : AVX512PI<opc, MRMDestMem, (outs),
2392 (ins _.MemOp:$dst, _.KRCWM:$mask, _.RC:$src),
2393 OpcodeStr # "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}",
2394 [], _.ExeDomain>, EVEX, EVEX_K;
2397 def: Pat<(mstore addr:$ptr, _.KRCWM:$mask, (_.VT _.RC:$src)),
2398 (!cast<Instruction>(NAME#_.ZSuffix##mrk) addr:$ptr,
2399 _.KRCWM:$mask, _.RC:$src)>;
2403 multiclass avx512_store_vl< bits<8> opc, string OpcodeStr,
2404 AVX512VLVectorVTInfo _, Predicate prd> {
2405 let Predicates = [prd] in
2406 defm Z : avx512_store<opc, OpcodeStr, _.info512, store,
2407 masked_store_unaligned>, EVEX_V512;
2409 let Predicates = [prd, HasVLX] in {
2410 defm Z256 : avx512_store<opc, OpcodeStr, _.info256, store,
2411 masked_store_unaligned>, EVEX_V256;
2412 defm Z128 : avx512_store<opc, OpcodeStr, _.info128, store,
2413 masked_store_unaligned>, EVEX_V128;
2417 multiclass avx512_alignedstore_vl<bits<8> opc, string OpcodeStr,
2418 AVX512VLVectorVTInfo _, Predicate prd> {
2419 let Predicates = [prd] in
2420 defm Z : avx512_store<opc, OpcodeStr, _.info512, alignedstore512,
2421 masked_store_aligned512>, EVEX_V512;
2423 let Predicates = [prd, HasVLX] in {
2424 defm Z256 : avx512_store<opc, OpcodeStr, _.info256, alignedstore256,
2425 masked_store_aligned256>, EVEX_V256;
2426 defm Z128 : avx512_store<opc, OpcodeStr, _.info128, alignedstore,
2427 masked_store_aligned128>, EVEX_V128;
2431 defm VMOVAPS : avx512_alignedload_vl<0x28, "vmovaps", avx512vl_f32_info,
2433 avx512_alignedstore_vl<0x29, "vmovaps", avx512vl_f32_info,
2434 HasAVX512>, PS, EVEX_CD8<32, CD8VF>;
2436 defm VMOVAPD : avx512_alignedload_vl<0x28, "vmovapd", avx512vl_f64_info,
2438 avx512_alignedstore_vl<0x29, "vmovapd", avx512vl_f64_info,
2439 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2441 defm VMOVUPS : avx512_load_vl<0x10, "vmovups", avx512vl_f32_info, HasAVX512>,
2442 avx512_store_vl<0x11, "vmovups", avx512vl_f32_info, HasAVX512>,
2443 PS, EVEX_CD8<32, CD8VF>;
2445 defm VMOVUPD : avx512_load_vl<0x10, "vmovupd", avx512vl_f64_info, HasAVX512, 0>,
2446 avx512_store_vl<0x11, "vmovupd", avx512vl_f64_info, HasAVX512>,
2447 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2449 def: Pat<(v8f64 (int_x86_avx512_mask_loadu_pd_512 addr:$ptr,
2450 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
2451 (VMOVUPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2453 def: Pat<(v16f32 (int_x86_avx512_mask_loadu_ps_512 addr:$ptr,
2454 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
2455 (VMOVUPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2457 def: Pat<(v8f64 (int_x86_avx512_mask_load_pd_512 addr:$ptr,
2458 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
2459 (VMOVAPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2461 def: Pat<(v16f32 (int_x86_avx512_mask_load_ps_512 addr:$ptr,
2462 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
2463 (VMOVAPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2465 def: Pat<(v8f64 (int_x86_avx512_mask_load_pd_512 addr:$ptr,
2466 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
2467 (VMOVAPDZrm addr:$ptr)>;
2469 def: Pat<(v16f32 (int_x86_avx512_mask_load_ps_512 addr:$ptr,
2470 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
2471 (VMOVAPSZrm addr:$ptr)>;
2473 def: Pat<(int_x86_avx512_mask_storeu_ps_512 addr:$ptr, (v16f32 VR512:$src),
2475 (VMOVUPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2477 def: Pat<(int_x86_avx512_mask_storeu_pd_512 addr:$ptr, (v8f64 VR512:$src),
2479 (VMOVUPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2482 def: Pat<(int_x86_avx512_mask_store_ps_512 addr:$ptr, (v16f32 VR512:$src),
2484 (VMOVAPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2486 def: Pat<(int_x86_avx512_mask_store_pd_512 addr:$ptr, (v8f64 VR512:$src),
2488 (VMOVAPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2491 let Predicates = [HasAVX512, NoVLX] in {
2492 def: Pat<(X86mstore addr:$ptr, VK8WM:$mask, (v8f32 VR256:$src)),
2493 (VMOVUPSZmrk addr:$ptr,
2494 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)),
2495 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256:$src, sub_ymm))>;
2497 def: Pat<(v8f32 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2498 (v8f32 (EXTRACT_SUBREG (v16f32 (VMOVUPSZrmkz
2499 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2501 def: Pat<(v8f32 (masked_load addr:$ptr, VK8WM:$mask, (v8f32 VR256:$src0))),
2502 (v8f32 (EXTRACT_SUBREG (v16f32 (VMOVUPSZrmk
2503 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256:$src0, sub_ymm),
2504 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2507 defm VMOVDQA32 : avx512_alignedload_vl<0x6F, "vmovdqa32", avx512vl_i32_info,
2509 avx512_alignedstore_vl<0x7F, "vmovdqa32", avx512vl_i32_info,
2510 HasAVX512>, PD, EVEX_CD8<32, CD8VF>;
2512 defm VMOVDQA64 : avx512_alignedload_vl<0x6F, "vmovdqa64", avx512vl_i64_info,
2514 avx512_alignedstore_vl<0x7F, "vmovdqa64", avx512vl_i64_info,
2515 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2517 defm VMOVDQU8 : avx512_load_vl<0x6F, "vmovdqu8", avx512vl_i8_info, HasBWI>,
2518 avx512_store_vl<0x7F, "vmovdqu8", avx512vl_i8_info,
2519 HasBWI>, XD, EVEX_CD8<8, CD8VF>;
2521 defm VMOVDQU16 : avx512_load_vl<0x6F, "vmovdqu16", avx512vl_i16_info, HasBWI>,
2522 avx512_store_vl<0x7F, "vmovdqu16", avx512vl_i16_info,
2523 HasBWI>, XD, VEX_W, EVEX_CD8<16, CD8VF>;
2525 defm VMOVDQU32 : avx512_load_vl<0x6F, "vmovdqu32", avx512vl_i32_info, HasAVX512>,
2526 avx512_store_vl<0x7F, "vmovdqu32", avx512vl_i32_info,
2527 HasAVX512>, XS, EVEX_CD8<32, CD8VF>;
2529 defm VMOVDQU64 : avx512_load_vl<0x6F, "vmovdqu64", avx512vl_i64_info, HasAVX512>,
2530 avx512_store_vl<0x7F, "vmovdqu64", avx512vl_i64_info,
2531 HasAVX512>, XS, VEX_W, EVEX_CD8<64, CD8VF>;
2533 def: Pat<(v16i32 (int_x86_avx512_mask_loadu_d_512 addr:$ptr,
2534 (v16i32 immAllZerosV), GR16:$mask)),
2535 (VMOVDQU32Zrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2537 def: Pat<(v8i64 (int_x86_avx512_mask_loadu_q_512 addr:$ptr,
2538 (bc_v8i64 (v16i32 immAllZerosV)), GR8:$mask)),
2539 (VMOVDQU64Zrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2541 def: Pat<(int_x86_avx512_mask_storeu_d_512 addr:$ptr, (v16i32 VR512:$src),
2543 (VMOVDQU32Zmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2545 def: Pat<(int_x86_avx512_mask_storeu_q_512 addr:$ptr, (v8i64 VR512:$src),
2547 (VMOVDQU64Zmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2550 let AddedComplexity = 20 in {
2551 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src),
2552 (bc_v8i64 (v16i32 immAllZerosV)))),
2553 (VMOVDQU64Zrrkz VK8WM:$mask, VR512:$src)>;
2555 def : Pat<(v8i64 (vselect VK8WM:$mask, (bc_v8i64 (v16i32 immAllZerosV)),
2556 (v8i64 VR512:$src))),
2557 (VMOVDQU64Zrrkz (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$mask, VK16)),
2560 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src),
2561 (v16i32 immAllZerosV))),
2562 (VMOVDQU32Zrrkz VK16WM:$mask, VR512:$src)>;
2564 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 immAllZerosV),
2565 (v16i32 VR512:$src))),
2566 (VMOVDQU32Zrrkz (KNOTWrr VK16WM:$mask), VR512:$src)>;
2569 let Predicates = [HasAVX512, NoVLX] in {
2570 def: Pat<(X86mstore addr:$ptr, VK8WM:$mask, (v8i32 VR256:$src)),
2571 (VMOVDQU32Zmrk addr:$ptr,
2572 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)),
2573 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256:$src, sub_ymm))>;
2575 def: Pat<(v8i32 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2576 (v8i32 (EXTRACT_SUBREG (v16i32 (VMOVDQU32Zrmkz
2577 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2580 // Move Int Doubleword to Packed Double Int
2582 def VMOVDI2PDIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
2583 "vmovd\t{$src, $dst|$dst, $src}",
2585 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
2587 def VMOVDI2PDIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
2588 "vmovd\t{$src, $dst|$dst, $src}",
2590 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
2591 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2592 def VMOV64toPQIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
2593 "vmovq\t{$src, $dst|$dst, $src}",
2595 (v2i64 (scalar_to_vector GR64:$src)))],
2596 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
2597 let isCodeGenOnly = 1 in {
2598 def VMOV64toSDZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
2599 "vmovq\t{$src, $dst|$dst, $src}",
2600 [(set FR64:$dst, (bitconvert GR64:$src))],
2601 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
2602 def VMOVSDto64Zrr : AVX512BI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
2603 "vmovq\t{$src, $dst|$dst, $src}",
2604 [(set GR64:$dst, (bitconvert FR64:$src))],
2605 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
2607 def VMOVSDto64Zmr : AVX512BI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
2608 "vmovq\t{$src, $dst|$dst, $src}",
2609 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
2610 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
2611 EVEX_CD8<64, CD8VT1>;
2613 // Move Int Doubleword to Single Scalar
2615 let isCodeGenOnly = 1 in {
2616 def VMOVDI2SSZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
2617 "vmovd\t{$src, $dst|$dst, $src}",
2618 [(set FR32X:$dst, (bitconvert GR32:$src))],
2619 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
2621 def VMOVDI2SSZrm : AVX512BI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
2622 "vmovd\t{$src, $dst|$dst, $src}",
2623 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
2624 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2627 // Move doubleword from xmm register to r/m32
2629 def VMOVPDI2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
2630 "vmovd\t{$src, $dst|$dst, $src}",
2631 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
2632 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
2634 def VMOVPDI2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
2635 (ins i32mem:$dst, VR128X:$src),
2636 "vmovd\t{$src, $dst|$dst, $src}",
2637 [(store (i32 (vector_extract (v4i32 VR128X:$src),
2638 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
2639 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2641 // Move quadword from xmm1 register to r/m64
2643 def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
2644 "vmovq\t{$src, $dst|$dst, $src}",
2645 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
2647 IIC_SSE_MOVD_ToGP>, PD, EVEX, VEX_LIG, VEX_W,
2648 Requires<[HasAVX512, In64BitMode]>;
2650 def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
2651 (ins i64mem:$dst, VR128X:$src),
2652 "vmovq\t{$src, $dst|$dst, $src}",
2653 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
2654 addr:$dst)], IIC_SSE_MOVDQ>,
2655 EVEX, PD, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>,
2656 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
2658 // Move Scalar Single to Double Int
2660 let isCodeGenOnly = 1 in {
2661 def VMOVSS2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst),
2663 "vmovd\t{$src, $dst|$dst, $src}",
2664 [(set GR32:$dst, (bitconvert FR32X:$src))],
2665 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
2666 def VMOVSS2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
2667 (ins i32mem:$dst, FR32X:$src),
2668 "vmovd\t{$src, $dst|$dst, $src}",
2669 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
2670 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2673 // Move Quadword Int to Packed Quadword Int
2675 def VMOVQI2PQIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst),
2677 "vmovq\t{$src, $dst|$dst, $src}",
2679 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
2680 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2682 //===----------------------------------------------------------------------===//
2683 // AVX-512 MOVSS, MOVSD
2684 //===----------------------------------------------------------------------===//
2686 multiclass avx512_move_scalar <string asm, RegisterClass RC,
2687 SDNode OpNode, ValueType vt,
2688 X86MemOperand x86memop, PatFrag mem_pat> {
2689 let hasSideEffects = 0 in {
2690 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
2691 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2692 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
2693 (scalar_to_vector RC:$src2))))],
2694 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
2695 let Constraints = "$src1 = $dst" in
2696 def rrk : SI<0x10, MRMSrcReg, (outs VR128X:$dst),
2697 (ins VR128X:$src1, VK1WM:$mask, RC:$src2, RC:$src3),
2699 "\t{$src3, $src2, $dst {${mask}}|$dst {${mask}}, $src2, $src3}"),
2700 [], IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG, EVEX_K;
2701 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2702 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2703 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
2705 let mayStore = 1 in {
2706 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
2707 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2708 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
2710 def mrk: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, VK1WM:$mask, RC:$src),
2711 !strconcat(asm, "\t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
2712 [], IIC_SSE_MOV_S_MR>,
2713 EVEX, VEX_LIG, EVEX_K;
2715 } //hasSideEffects = 0
2718 let ExeDomain = SSEPackedSingle in
2719 defm VMOVSSZ : avx512_move_scalar<"movss", FR32X, X86Movss, v4f32, f32mem,
2720 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
2722 let ExeDomain = SSEPackedDouble in
2723 defm VMOVSDZ : avx512_move_scalar<"movsd", FR64X, X86Movsd, v2f64, f64mem,
2724 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
2726 def : Pat<(f32 (X86select VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))),
2727 (COPY_TO_REGCLASS (VMOVSSZrrk (COPY_TO_REGCLASS FR32X:$src2, VR128X),
2728 VK1WM:$mask, (f32 (IMPLICIT_DEF)), FR32X:$src1), FR32X)>;
2730 def : Pat<(f64 (X86select VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))),
2731 (COPY_TO_REGCLASS (VMOVSDZrrk (COPY_TO_REGCLASS FR64X:$src2, VR128X),
2732 VK1WM:$mask, (f64 (IMPLICIT_DEF)), FR64X:$src1), FR64X)>;
2734 def : Pat<(int_x86_avx512_mask_store_ss addr:$dst, VR128X:$src, GR8:$mask),
2735 (VMOVSSZmrk addr:$dst, (i1 (COPY_TO_REGCLASS GR8:$mask, VK1WM)),
2736 (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2738 // For the disassembler
2739 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
2740 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2741 (ins VR128X:$src1, FR32X:$src2),
2742 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
2744 XS, EVEX_4V, VEX_LIG;
2745 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2746 (ins VR128X:$src1, FR64X:$src2),
2747 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
2749 XD, EVEX_4V, VEX_LIG, VEX_W;
2752 let Predicates = [HasAVX512] in {
2753 let AddedComplexity = 15 in {
2754 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
2755 // MOVS{S,D} to the lower bits.
2756 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
2757 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
2758 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
2759 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2760 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
2761 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2762 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
2763 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
2765 // Move low f32 and clear high bits.
2766 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
2767 (SUBREG_TO_REG (i32 0),
2768 (VMOVSSZrr (v4f32 (V_SET0)),
2769 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
2770 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
2771 (SUBREG_TO_REG (i32 0),
2772 (VMOVSSZrr (v4i32 (V_SET0)),
2773 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
2776 let AddedComplexity = 20 in {
2777 // MOVSSrm zeros the high parts of the register; represent this
2778 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2779 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
2780 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2781 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
2782 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2783 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
2784 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2786 // MOVSDrm zeros the high parts of the register; represent this
2787 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2788 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
2789 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2790 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
2791 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2792 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
2793 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2794 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
2795 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2796 def : Pat<(v2f64 (X86vzload addr:$src)),
2797 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2799 // Represent the same patterns above but in the form they appear for
2801 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2802 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
2803 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
2804 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2805 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
2806 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
2807 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2808 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
2809 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
2811 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2812 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
2813 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
2814 FR32X:$src)), sub_xmm)>;
2815 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2816 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
2817 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
2818 FR64X:$src)), sub_xmm)>;
2819 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
2820 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
2821 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
2823 // Move low f64 and clear high bits.
2824 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
2825 (SUBREG_TO_REG (i32 0),
2826 (VMOVSDZrr (v2f64 (V_SET0)),
2827 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
2829 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
2830 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
2831 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
2833 // Extract and store.
2834 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
2836 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
2837 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
2839 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
2841 // Shuffle with VMOVSS
2842 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
2843 (VMOVSSZrr (v4i32 VR128X:$src1),
2844 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
2845 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
2846 (VMOVSSZrr (v4f32 VR128X:$src1),
2847 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
2850 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
2851 (SUBREG_TO_REG (i32 0),
2852 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
2853 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
2855 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
2856 (SUBREG_TO_REG (i32 0),
2857 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
2858 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
2861 // Shuffle with VMOVSD
2862 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
2863 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2864 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
2865 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2866 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
2867 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2868 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
2869 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2872 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
2873 (SUBREG_TO_REG (i32 0),
2874 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
2875 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
2877 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
2878 (SUBREG_TO_REG (i32 0),
2879 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
2880 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
2883 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
2884 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2885 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
2886 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2887 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
2888 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2889 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
2890 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2893 let AddedComplexity = 15 in
2894 def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
2896 "vmovq\t{$src, $dst|$dst, $src}",
2897 [(set VR128X:$dst, (v2i64 (X86vzmovl
2898 (v2i64 VR128X:$src))))],
2899 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
2901 let AddedComplexity = 20 in
2902 def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
2904 "vmovq\t{$src, $dst|$dst, $src}",
2905 [(set VR128X:$dst, (v2i64 (X86vzmovl
2906 (loadv2i64 addr:$src))))],
2907 IIC_SSE_MOVDQ>, EVEX, VEX_W,
2908 EVEX_CD8<8, CD8VT8>;
2910 let Predicates = [HasAVX512] in {
2911 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
2912 let AddedComplexity = 20 in {
2913 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
2914 (VMOVDI2PDIZrm addr:$src)>;
2915 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
2916 (VMOV64toPQIZrr GR64:$src)>;
2917 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
2918 (VMOVDI2PDIZrr GR32:$src)>;
2920 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
2921 (VMOVDI2PDIZrm addr:$src)>;
2922 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
2923 (VMOVDI2PDIZrm addr:$src)>;
2924 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
2925 (VMOVZPQILo2PQIZrm addr:$src)>;
2926 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
2927 (VMOVZPQILo2PQIZrr VR128X:$src)>;
2928 def : Pat<(v2i64 (X86vzload addr:$src)),
2929 (VMOVZPQILo2PQIZrm addr:$src)>;
2932 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
2933 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2934 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
2935 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
2936 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
2937 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
2938 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
2941 def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
2942 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
2944 def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
2945 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
2947 def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
2948 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
2950 def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
2951 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
2953 //===----------------------------------------------------------------------===//
2954 // AVX-512 - Non-temporals
2955 //===----------------------------------------------------------------------===//
2956 let SchedRW = [WriteLoad] in {
2957 def VMOVNTDQAZrm : AVX512PI<0x2A, MRMSrcMem, (outs VR512:$dst),
2958 (ins i512mem:$src), "vmovntdqa\t{$src, $dst|$dst, $src}",
2959 [(set VR512:$dst, (int_x86_avx512_movntdqa addr:$src))],
2960 SSEPackedInt>, EVEX, T8PD, EVEX_V512,
2961 EVEX_CD8<64, CD8VF>;
2963 let Predicates = [HasAVX512, HasVLX] in {
2964 def VMOVNTDQAZ256rm : AVX512PI<0x2A, MRMSrcMem, (outs VR256X:$dst),
2966 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
2967 SSEPackedInt>, EVEX, T8PD, EVEX_V256,
2968 EVEX_CD8<64, CD8VF>;
2970 def VMOVNTDQAZ128rm : AVX512PI<0x2A, MRMSrcMem, (outs VR128X:$dst),
2972 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
2973 SSEPackedInt>, EVEX, T8PD, EVEX_V128,
2974 EVEX_CD8<64, CD8VF>;
2978 multiclass avx512_movnt<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2979 ValueType OpVT, RegisterClass RC, X86MemOperand memop,
2980 Domain d, InstrItinClass itin = IIC_SSE_MOVNT> {
2981 let SchedRW = [WriteStore], mayStore = 1,
2982 AddedComplexity = 400 in
2983 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
2984 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2985 [(st_frag (OpVT RC:$src), addr:$dst)], d, itin>, EVEX;
2988 multiclass avx512_movnt_vl<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2989 string elty, string elsz, string vsz512,
2990 string vsz256, string vsz128, Domain d,
2991 Predicate prd, InstrItinClass itin = IIC_SSE_MOVNT> {
2992 let Predicates = [prd] in
2993 defm Z : avx512_movnt<opc, OpcodeStr, st_frag,
2994 !cast<ValueType>("v"##vsz512##elty##elsz), VR512,
2995 !cast<X86MemOperand>(elty##"512mem"), d, itin>,
2998 let Predicates = [prd, HasVLX] in {
2999 defm Z256 : avx512_movnt<opc, OpcodeStr, st_frag,
3000 !cast<ValueType>("v"##vsz256##elty##elsz), VR256X,
3001 !cast<X86MemOperand>(elty##"256mem"), d, itin>,
3004 defm Z128 : avx512_movnt<opc, OpcodeStr, st_frag,
3005 !cast<ValueType>("v"##vsz128##elty##elsz), VR128X,
3006 !cast<X86MemOperand>(elty##"128mem"), d, itin>,
3011 defm VMOVNTDQ : avx512_movnt_vl<0xE7, "vmovntdq", alignednontemporalstore,
3012 "i", "64", "8", "4", "2", SSEPackedInt,
3013 HasAVX512>, PD, EVEX_CD8<64, CD8VF>;
3015 defm VMOVNTPD : avx512_movnt_vl<0x2B, "vmovntpd", alignednontemporalstore,
3016 "f", "64", "8", "4", "2", SSEPackedDouble,
3017 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
3019 defm VMOVNTPS : avx512_movnt_vl<0x2B, "vmovntps", alignednontemporalstore,
3020 "f", "32", "16", "8", "4", SSEPackedSingle,
3021 HasAVX512>, PS, EVEX_CD8<32, CD8VF>;
3023 //===----------------------------------------------------------------------===//
3024 // AVX-512 - Integer arithmetic
3026 multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3027 X86VectorVTInfo _, OpndItins itins,
3028 bit IsCommutable = 0> {
3029 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3030 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3031 "$src2, $src1", "$src1, $src2",
3032 (_.VT (OpNode _.RC:$src1, _.RC:$src2)),
3033 itins.rr, IsCommutable>,
3034 AVX512BIBase, EVEX_4V;
3037 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3038 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
3039 "$src2, $src1", "$src1, $src2",
3040 (_.VT (OpNode _.RC:$src1,
3041 (bitconvert (_.LdFrag addr:$src2)))),
3043 AVX512BIBase, EVEX_4V;
3046 multiclass avx512_binop_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
3047 X86VectorVTInfo _, OpndItins itins,
3048 bit IsCommutable = 0> :
3049 avx512_binop_rm<opc, OpcodeStr, OpNode, _, itins, IsCommutable> {
3051 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3052 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
3053 "${src2}"##_.BroadcastStr##", $src1",
3054 "$src1, ${src2}"##_.BroadcastStr,
3055 (_.VT (OpNode _.RC:$src1,
3057 (_.ScalarLdFrag addr:$src2)))),
3059 AVX512BIBase, EVEX_4V, EVEX_B;
3062 multiclass avx512_binop_rm_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
3063 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
3064 Predicate prd, bit IsCommutable = 0> {
3065 let Predicates = [prd] in
3066 defm Z : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
3067 IsCommutable>, EVEX_V512;
3069 let Predicates = [prd, HasVLX] in {
3070 defm Z256 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
3071 IsCommutable>, EVEX_V256;
3072 defm Z128 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
3073 IsCommutable>, EVEX_V128;
3077 multiclass avx512_binop_rmb_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
3078 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
3079 Predicate prd, bit IsCommutable = 0> {
3080 let Predicates = [prd] in
3081 defm Z : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
3082 IsCommutable>, EVEX_V512;
3084 let Predicates = [prd, HasVLX] in {
3085 defm Z256 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
3086 IsCommutable>, EVEX_V256;
3087 defm Z128 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
3088 IsCommutable>, EVEX_V128;
3092 multiclass avx512_binop_rm_vl_q<bits<8> opc, string OpcodeStr, SDNode OpNode,
3093 OpndItins itins, Predicate prd,
3094 bit IsCommutable = 0> {
3095 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i64_info,
3096 itins, prd, IsCommutable>,
3097 VEX_W, EVEX_CD8<64, CD8VF>;
3100 multiclass avx512_binop_rm_vl_d<bits<8> opc, string OpcodeStr, SDNode OpNode,
3101 OpndItins itins, Predicate prd,
3102 bit IsCommutable = 0> {
3103 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i32_info,
3104 itins, prd, IsCommutable>, EVEX_CD8<32, CD8VF>;
3107 multiclass avx512_binop_rm_vl_w<bits<8> opc, string OpcodeStr, SDNode OpNode,
3108 OpndItins itins, Predicate prd,
3109 bit IsCommutable = 0> {
3110 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i16_info,
3111 itins, prd, IsCommutable>, EVEX_CD8<16, CD8VF>;
3114 multiclass avx512_binop_rm_vl_b<bits<8> opc, string OpcodeStr, SDNode OpNode,
3115 OpndItins itins, Predicate prd,
3116 bit IsCommutable = 0> {
3117 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i8_info,
3118 itins, prd, IsCommutable>, EVEX_CD8<8, CD8VF>;
3121 multiclass avx512_binop_rm_vl_dq<bits<8> opc_d, bits<8> opc_q, string OpcodeStr,
3122 SDNode OpNode, OpndItins itins, Predicate prd,
3123 bit IsCommutable = 0> {
3124 defm Q : avx512_binop_rm_vl_q<opc_q, OpcodeStr#"q", OpNode, itins, prd,
3127 defm D : avx512_binop_rm_vl_d<opc_d, OpcodeStr#"d", OpNode, itins, prd,
3131 multiclass avx512_binop_rm_vl_bw<bits<8> opc_b, bits<8> opc_w, string OpcodeStr,
3132 SDNode OpNode, OpndItins itins, Predicate prd,
3133 bit IsCommutable = 0> {
3134 defm W : avx512_binop_rm_vl_w<opc_w, OpcodeStr#"w", OpNode, itins, prd,
3137 defm B : avx512_binop_rm_vl_b<opc_b, OpcodeStr#"b", OpNode, itins, prd,
3141 multiclass avx512_binop_rm_vl_all<bits<8> opc_b, bits<8> opc_w,
3142 bits<8> opc_d, bits<8> opc_q,
3143 string OpcodeStr, SDNode OpNode,
3144 OpndItins itins, bit IsCommutable = 0> {
3145 defm NAME : avx512_binop_rm_vl_dq<opc_d, opc_q, OpcodeStr, OpNode,
3146 itins, HasAVX512, IsCommutable>,
3147 avx512_binop_rm_vl_bw<opc_b, opc_w, OpcodeStr, OpNode,
3148 itins, HasBWI, IsCommutable>;
3151 multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr, OpndItins itins,
3152 SDNode OpNode,X86VectorVTInfo _Src,
3153 X86VectorVTInfo _Dst, bit IsCommutable = 0> {
3154 defm rr : AVX512_maskable<opc, MRMSrcReg, _Dst, (outs _Dst.RC:$dst),
3155 (ins _Src.RC:$src1, _Src.RC:$src2), OpcodeStr,
3156 "$src2, $src1","$src1, $src2",
3158 (_Src.VT _Src.RC:$src1),
3159 (_Src.VT _Src.RC:$src2))),
3160 itins.rr, IsCommutable>,
3161 AVX512BIBase, EVEX_4V;
3162 let mayLoad = 1 in {
3163 defm rm : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3164 (ins _Src.RC:$src1, _Src.MemOp:$src2), OpcodeStr,
3165 "$src2, $src1", "$src1, $src2",
3166 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1),
3167 (bitconvert (_Src.LdFrag addr:$src2)))),
3169 AVX512BIBase, EVEX_4V;
3171 defm rmb : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3172 (ins _Src.RC:$src1, _Dst.ScalarMemOp:$src2),
3174 "${src2}"##_Dst.BroadcastStr##", $src1",
3175 "$src1, ${src2}"##_Dst.BroadcastStr,
3176 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1), (bitconvert
3177 (_Dst.VT (X86VBroadcast
3178 (_Dst.ScalarLdFrag addr:$src2)))))),
3180 AVX512BIBase, EVEX_4V, EVEX_B;
3184 defm VPADD : avx512_binop_rm_vl_all<0xFC, 0xFD, 0xFE, 0xD4, "vpadd", add,
3185 SSE_INTALU_ITINS_P, 1>;
3186 defm VPSUB : avx512_binop_rm_vl_all<0xF8, 0xF9, 0xFA, 0xFB, "vpsub", sub,
3187 SSE_INTALU_ITINS_P, 0>;
3188 defm VPADDS : avx512_binop_rm_vl_bw<0xEC, 0xED, "vpadds", X86adds,
3189 SSE_INTALU_ITINS_P, HasBWI, 1>;
3190 defm VPSUBS : avx512_binop_rm_vl_bw<0xE8, 0xE9, "vpsubs", X86subs,
3191 SSE_INTALU_ITINS_P, HasBWI, 0>;
3192 defm VPADDUS : avx512_binop_rm_vl_bw<0xDC, 0xDD, "vpaddus", X86addus,
3193 SSE_INTALU_ITINS_P, HasBWI, 1>;
3194 defm VPSUBUS : avx512_binop_rm_vl_bw<0xD8, 0xD9, "vpsubus", X86subus,
3195 SSE_INTALU_ITINS_P, HasBWI, 0>;
3196 defm VPMULLD : avx512_binop_rm_vl_d<0x40, "vpmulld", mul,
3197 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3198 defm VPMULLW : avx512_binop_rm_vl_w<0xD5, "vpmullw", mul,
3199 SSE_INTALU_ITINS_P, HasBWI, 1>;
3200 defm VPMULLQ : avx512_binop_rm_vl_q<0x40, "vpmullq", mul,
3201 SSE_INTALU_ITINS_P, HasDQI, 1>, T8PD;
3202 defm VPMULHW : avx512_binop_rm_vl_w<0xE5, "vpmulhw", mulhs, SSE_INTALU_ITINS_P,
3204 defm VPMULHUW : avx512_binop_rm_vl_w<0xE4, "vpmulhuw", mulhu, SSE_INTMUL_ITINS_P,
3206 defm VPMULHRSW : avx512_binop_rm_vl_w<0x0B, "vpmulhrsw", X86mulhrs, SSE_INTMUL_ITINS_P,
3208 defm VPAVG : avx512_binop_rm_vl_bw<0xE0, 0xE3, "vpavg", X86avg,
3209 SSE_INTALU_ITINS_P, HasBWI, 1>;
3211 multiclass avx512_binop_all<bits<8> opc, string OpcodeStr, OpndItins itins,
3212 SDNode OpNode, bit IsCommutable = 0> {
3214 defm NAME#Z : avx512_binop_rm2<opc, OpcodeStr, itins, OpNode,
3215 v16i32_info, v8i64_info, IsCommutable>,
3216 EVEX_V512, EVEX_CD8<64, CD8VF>, VEX_W;
3217 let Predicates = [HasVLX] in {
3218 defm NAME#Z256 : avx512_binop_rm2<opc, OpcodeStr, itins, OpNode,
3219 v8i32x_info, v4i64x_info, IsCommutable>,
3220 EVEX_V256, EVEX_CD8<64, CD8VF>, VEX_W;
3221 defm NAME#Z128 : avx512_binop_rm2<opc, OpcodeStr, itins, OpNode,
3222 v4i32x_info, v2i64x_info, IsCommutable>,
3223 EVEX_V128, EVEX_CD8<64, CD8VF>, VEX_W;
3227 defm VPMULDQ : avx512_binop_all<0x28, "vpmuldq", SSE_INTALU_ITINS_P,
3229 defm VPMULUDQ : avx512_binop_all<0xF4, "vpmuludq", SSE_INTMUL_ITINS_P,
3232 multiclass avx512_packs_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
3233 X86VectorVTInfo _Src, X86VectorVTInfo _Dst> {
3234 let mayLoad = 1 in {
3235 defm rmb : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3236 (ins _Src.RC:$src1, _Src.ScalarMemOp:$src2),
3238 "${src2}"##_Src.BroadcastStr##", $src1",
3239 "$src1, ${src2}"##_Src.BroadcastStr,
3240 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1), (bitconvert
3241 (_Src.VT (X86VBroadcast
3242 (_Src.ScalarLdFrag addr:$src2))))))>,
3243 EVEX_4V, EVEX_B, EVEX_CD8<_Src.EltSize, CD8VF>;
3247 multiclass avx512_packs_rm<bits<8> opc, string OpcodeStr,
3248 SDNode OpNode,X86VectorVTInfo _Src,
3249 X86VectorVTInfo _Dst> {
3250 defm rr : AVX512_maskable<opc, MRMSrcReg, _Dst, (outs _Dst.RC:$dst),
3251 (ins _Src.RC:$src1, _Src.RC:$src2), OpcodeStr,
3252 "$src2, $src1","$src1, $src2",
3254 (_Src.VT _Src.RC:$src1),
3255 (_Src.VT _Src.RC:$src2)))>,
3256 EVEX_CD8<_Src.EltSize, CD8VF>, EVEX_4V;
3257 let mayLoad = 1 in {
3258 defm rm : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3259 (ins _Src.RC:$src1, _Src.MemOp:$src2), OpcodeStr,
3260 "$src2, $src1", "$src1, $src2",
3261 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1),
3262 (bitconvert (_Src.LdFrag addr:$src2))))>,
3263 EVEX_4V, EVEX_CD8<_Src.EltSize, CD8VF>;
3267 multiclass avx512_packs_all_i32_i16<bits<8> opc, string OpcodeStr,
3269 defm NAME#Z : avx512_packs_rm<opc, OpcodeStr, OpNode, v16i32_info,
3271 avx512_packs_rmb<opc, OpcodeStr, OpNode, v16i32_info,
3272 v32i16_info>, EVEX_V512;
3273 let Predicates = [HasVLX] in {
3274 defm NAME#Z256 : avx512_packs_rm<opc, OpcodeStr, OpNode, v8i32x_info,
3276 avx512_packs_rmb<opc, OpcodeStr, OpNode, v8i32x_info,
3277 v16i16x_info>, EVEX_V256;
3278 defm NAME#Z128 : avx512_packs_rm<opc, OpcodeStr, OpNode, v4i32x_info,
3280 avx512_packs_rmb<opc, OpcodeStr, OpNode, v4i32x_info,
3281 v8i16x_info>, EVEX_V128;
3284 multiclass avx512_packs_all_i16_i8<bits<8> opc, string OpcodeStr,
3286 defm NAME#Z : avx512_packs_rm<opc, OpcodeStr, OpNode, v32i16_info,
3287 v64i8_info>, EVEX_V512;
3288 let Predicates = [HasVLX] in {
3289 defm NAME#Z256 : avx512_packs_rm<opc, OpcodeStr, OpNode, v16i16x_info,
3290 v32i8x_info>, EVEX_V256;
3291 defm NAME#Z128 : avx512_packs_rm<opc, OpcodeStr, OpNode, v8i16x_info,
3292 v16i8x_info>, EVEX_V128;
3296 multiclass avx512_vpmadd<bits<8> opc, string OpcodeStr,
3297 SDNode OpNode, AVX512VLVectorVTInfo _Src,
3298 AVX512VLVectorVTInfo _Dst> {
3299 defm NAME#Z : avx512_packs_rm<opc, OpcodeStr, OpNode, _Src.info512,
3300 _Dst.info512>, EVEX_V512;
3301 let Predicates = [HasVLX] in {
3302 defm NAME#Z256 : avx512_packs_rm<opc, OpcodeStr, OpNode, _Src.info256,
3303 _Dst.info256>, EVEX_V256;
3304 defm NAME#Z128 : avx512_packs_rm<opc, OpcodeStr, OpNode, _Src.info128,
3305 _Dst.info128>, EVEX_V128;
3309 let Predicates = [HasBWI] in {
3310 defm VPACKSSDW : avx512_packs_all_i32_i16<0x6B, "vpackssdw", X86Packss>, PD;
3311 defm VPACKUSDW : avx512_packs_all_i32_i16<0x2b, "vpackusdw", X86Packus>, T8PD;
3312 defm VPACKSSWB : avx512_packs_all_i16_i8 <0x63, "vpacksswb", X86Packss>, AVX512BIBase, VEX_W;
3313 defm VPACKUSWB : avx512_packs_all_i16_i8 <0x67, "vpackuswb", X86Packus>, AVX512BIBase, VEX_W;
3315 defm VPMADDUBSW : avx512_vpmadd<0x04, "vpmaddubsw", X86vpmaddubsw,
3316 avx512vl_i8_info, avx512vl_i16_info>, AVX512BIBase, T8PD;
3317 defm VPMADDWD : avx512_vpmadd<0xF5, "vpmaddwd", X86vpmaddwd,
3318 avx512vl_i16_info, avx512vl_i32_info>, AVX512BIBase;
3321 defm VPMAXSB : avx512_binop_rm_vl_b<0x3C, "vpmaxsb", smax,
3322 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3323 defm VPMAXSW : avx512_binop_rm_vl_w<0xEE, "vpmaxsw", smax,
3324 SSE_INTALU_ITINS_P, HasBWI, 1>;
3325 defm VPMAXS : avx512_binop_rm_vl_dq<0x3D, 0x3D, "vpmaxs", smax,
3326 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3328 defm VPMAXUB : avx512_binop_rm_vl_b<0xDE, "vpmaxub", umax,
3329 SSE_INTALU_ITINS_P, HasBWI, 1>;
3330 defm VPMAXUW : avx512_binop_rm_vl_w<0x3E, "vpmaxuw", umax,
3331 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3332 defm VPMAXU : avx512_binop_rm_vl_dq<0x3F, 0x3F, "vpmaxu", umax,
3333 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3335 defm VPMINSB : avx512_binop_rm_vl_b<0x38, "vpminsb", smin,
3336 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3337 defm VPMINSW : avx512_binop_rm_vl_w<0xEA, "vpminsw", smin,
3338 SSE_INTALU_ITINS_P, HasBWI, 1>;
3339 defm VPMINS : avx512_binop_rm_vl_dq<0x39, 0x39, "vpmins", smin,
3340 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3342 defm VPMINUB : avx512_binop_rm_vl_b<0xDA, "vpminub", umin,
3343 SSE_INTALU_ITINS_P, HasBWI, 1>;
3344 defm VPMINUW : avx512_binop_rm_vl_w<0x3A, "vpminuw", umin,
3345 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3346 defm VPMINU : avx512_binop_rm_vl_dq<0x3B, 0x3B, "vpminu", umin,
3347 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3348 //===----------------------------------------------------------------------===//
3349 // AVX-512 Logical Instructions
3350 //===----------------------------------------------------------------------===//
3352 defm VPAND : avx512_binop_rm_vl_dq<0xDB, 0xDB, "vpand", and,
3353 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3354 defm VPOR : avx512_binop_rm_vl_dq<0xEB, 0xEB, "vpor", or,
3355 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3356 defm VPXOR : avx512_binop_rm_vl_dq<0xEF, 0xEF, "vpxor", xor,
3357 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3358 defm VPANDN : avx512_binop_rm_vl_dq<0xDF, 0xDF, "vpandn", X86andnp,
3359 SSE_INTALU_ITINS_P, HasAVX512, 0>;
3361 //===----------------------------------------------------------------------===//
3362 // AVX-512 FP arithmetic
3363 //===----------------------------------------------------------------------===//
3364 multiclass avx512_fp_scalar<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
3365 SDNode OpNode, SDNode VecNode, OpndItins itins,
3368 defm rr_Int : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
3369 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3370 "$src2, $src1", "$src1, $src2",
3371 (VecNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
3372 (i32 FROUND_CURRENT)),
3373 itins.rr, IsCommutable>;
3375 defm rm_Int : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
3376 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
3377 "$src2, $src1", "$src1, $src2",
3378 (VecNode (_.VT _.RC:$src1),
3379 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
3380 (i32 FROUND_CURRENT)),
3381 itins.rm, IsCommutable>;
3382 let isCodeGenOnly = 1, isCommutable = IsCommutable,
3383 Predicates = [HasAVX512] in {
3384 def rr : I< opc, MRMSrcReg, (outs _.FRC:$dst),
3385 (ins _.FRC:$src1, _.FRC:$src2),
3386 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3387 [(set _.FRC:$dst, (OpNode _.FRC:$src1, _.FRC:$src2))],
3389 def rm : I< opc, MRMSrcMem, (outs _.FRC:$dst),
3390 (ins _.FRC:$src1, _.ScalarMemOp:$src2),
3391 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3392 [(set _.FRC:$dst, (OpNode _.FRC:$src1,
3393 (_.ScalarLdFrag addr:$src2)))], itins.rr>;
3397 multiclass avx512_fp_scalar_round<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
3398 SDNode VecNode, OpndItins itins, bit IsCommutable = 0> {
3400 defm rrb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
3401 (ins _.RC:$src1, _.RC:$src2, AVX512RC:$rc), OpcodeStr,
3402 "$rc, $src2, $src1", "$src1, $src2, $rc",
3403 (VecNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
3404 (i32 imm:$rc)), itins.rr, IsCommutable>,
3407 multiclass avx512_fp_scalar_sae<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
3408 SDNode VecNode, OpndItins itins, bit IsCommutable> {
3410 defm rrb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
3411 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3412 "{sae}, $src2, $src1", "$src1, $src2, {sae}",
3413 (VecNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
3414 (i32 FROUND_NO_EXC))>, EVEX_B;
3417 multiclass avx512_binop_s_round<bits<8> opc, string OpcodeStr, SDNode OpNode,
3419 SizeItins itins, bit IsCommutable> {
3420 defm SSZ : avx512_fp_scalar<opc, OpcodeStr#"ss", f32x_info, OpNode, VecNode,
3421 itins.s, IsCommutable>,
3422 avx512_fp_scalar_round<opc, OpcodeStr#"ss", f32x_info, VecNode,
3423 itins.s, IsCommutable>,
3424 XS, EVEX_4V, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3425 defm SDZ : avx512_fp_scalar<opc, OpcodeStr#"sd", f64x_info, OpNode, VecNode,
3426 itins.d, IsCommutable>,
3427 avx512_fp_scalar_round<opc, OpcodeStr#"sd", f64x_info, VecNode,
3428 itins.d, IsCommutable>,
3429 XD, VEX_W, EVEX_4V, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3432 multiclass avx512_binop_s_sae<bits<8> opc, string OpcodeStr, SDNode OpNode,
3434 SizeItins itins, bit IsCommutable> {
3435 defm SSZ : avx512_fp_scalar<opc, OpcodeStr#"ss", f32x_info, OpNode, VecNode,
3436 itins.s, IsCommutable>,
3437 avx512_fp_scalar_sae<opc, OpcodeStr#"ss", f32x_info, VecNode,
3438 itins.s, IsCommutable>,
3439 XS, EVEX_4V, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3440 defm SDZ : avx512_fp_scalar<opc, OpcodeStr#"sd", f64x_info, OpNode, VecNode,
3441 itins.d, IsCommutable>,
3442 avx512_fp_scalar_sae<opc, OpcodeStr#"sd", f64x_info, VecNode,
3443 itins.d, IsCommutable>,
3444 XD, VEX_W, EVEX_4V, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3446 defm VADD : avx512_binop_s_round<0x58, "vadd", fadd, X86faddRnd, SSE_ALU_ITINS_S, 1>;
3447 defm VMUL : avx512_binop_s_round<0x59, "vmul", fmul, X86fmulRnd, SSE_ALU_ITINS_S, 1>;
3448 defm VSUB : avx512_binop_s_round<0x5C, "vsub", fsub, X86fsubRnd, SSE_ALU_ITINS_S, 0>;
3449 defm VDIV : avx512_binop_s_round<0x5E, "vdiv", fdiv, X86fdivRnd, SSE_ALU_ITINS_S, 0>;
3450 defm VMIN : avx512_binop_s_sae <0x5D, "vmin", X86fmin, X86fminRnd, SSE_ALU_ITINS_S, 1>;
3451 defm VMAX : avx512_binop_s_sae <0x5F, "vmax", X86fmax, X86fmaxRnd, SSE_ALU_ITINS_S, 1>;
3453 multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
3454 X86VectorVTInfo _, bit IsCommutable> {
3455 defm rr: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3456 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3457 "$src2, $src1", "$src1, $src2",
3458 (_.VT (OpNode _.RC:$src1, _.RC:$src2))>, EVEX_4V;
3459 let mayLoad = 1 in {
3460 defm rm: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3461 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
3462 "$src2, $src1", "$src1, $src2",
3463 (OpNode _.RC:$src1, (_.LdFrag addr:$src2))>, EVEX_4V;
3464 defm rmb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3465 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
3466 "${src2}"##_.BroadcastStr##", $src1",
3467 "$src1, ${src2}"##_.BroadcastStr,
3468 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3469 (_.ScalarLdFrag addr:$src2))))>,
3474 multiclass avx512_fp_round_packed<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd,
3475 X86VectorVTInfo _> {
3476 defm rb: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3477 (ins _.RC:$src1, _.RC:$src2, AVX512RC:$rc), OpcodeStr##_.Suffix,
3478 "$rc, $src2, $src1", "$src1, $src2, $rc",
3479 (_.VT (OpNodeRnd _.RC:$src1, _.RC:$src2, (i32 imm:$rc)))>,
3480 EVEX_4V, EVEX_B, EVEX_RC;
3484 multiclass avx512_fp_sae_packed<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd,
3485 X86VectorVTInfo _> {
3486 defm rb: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3487 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3488 "{sae}, $src2, $src1", "$src1, $src2, {sae}",
3489 (_.VT (OpNodeRnd _.RC:$src1, _.RC:$src2, (i32 FROUND_NO_EXC)))>,
3493 multiclass avx512_fp_binop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3494 bit IsCommutable = 0> {
3495 defm PSZ : avx512_fp_packed<opc, OpcodeStr, OpNode, v16f32_info,
3496 IsCommutable>, EVEX_V512, PS,
3497 EVEX_CD8<32, CD8VF>;
3498 defm PDZ : avx512_fp_packed<opc, OpcodeStr, OpNode, v8f64_info,
3499 IsCommutable>, EVEX_V512, PD, VEX_W,
3500 EVEX_CD8<64, CD8VF>;
3502 // Define only if AVX512VL feature is present.
3503 let Predicates = [HasVLX] in {
3504 defm PSZ128 : avx512_fp_packed<opc, OpcodeStr, OpNode, v4f32x_info,
3505 IsCommutable>, EVEX_V128, PS,
3506 EVEX_CD8<32, CD8VF>;
3507 defm PSZ256 : avx512_fp_packed<opc, OpcodeStr, OpNode, v8f32x_info,
3508 IsCommutable>, EVEX_V256, PS,
3509 EVEX_CD8<32, CD8VF>;
3510 defm PDZ128 : avx512_fp_packed<opc, OpcodeStr, OpNode, v2f64x_info,
3511 IsCommutable>, EVEX_V128, PD, VEX_W,
3512 EVEX_CD8<64, CD8VF>;
3513 defm PDZ256 : avx512_fp_packed<opc, OpcodeStr, OpNode, v4f64x_info,
3514 IsCommutable>, EVEX_V256, PD, VEX_W,
3515 EVEX_CD8<64, CD8VF>;
3519 multiclass avx512_fp_binop_p_round<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd> {
3520 defm PSZ : avx512_fp_round_packed<opc, OpcodeStr, OpNodeRnd, v16f32_info>,
3521 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
3522 defm PDZ : avx512_fp_round_packed<opc, OpcodeStr, OpNodeRnd, v8f64_info>,
3523 EVEX_V512, PD, VEX_W,EVEX_CD8<64, CD8VF>;
3526 multiclass avx512_fp_binop_p_sae<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd> {
3527 defm PSZ : avx512_fp_sae_packed<opc, OpcodeStr, OpNodeRnd, v16f32_info>,
3528 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
3529 defm PDZ : avx512_fp_sae_packed<opc, OpcodeStr, OpNodeRnd, v8f64_info>,
3530 EVEX_V512, PD, VEX_W,EVEX_CD8<64, CD8VF>;
3533 defm VADD : avx512_fp_binop_p<0x58, "vadd", fadd, 1>,
3534 avx512_fp_binop_p_round<0x58, "vadd", X86faddRnd>;
3535 defm VMUL : avx512_fp_binop_p<0x59, "vmul", fmul, 1>,
3536 avx512_fp_binop_p_round<0x59, "vmul", X86fmulRnd>;
3537 defm VSUB : avx512_fp_binop_p<0x5C, "vsub", fsub>,
3538 avx512_fp_binop_p_round<0x5C, "vsub", X86fsubRnd>;
3539 defm VDIV : avx512_fp_binop_p<0x5E, "vdiv", fdiv>,
3540 avx512_fp_binop_p_round<0x5E, "vdiv", X86fdivRnd>;
3541 defm VMIN : avx512_fp_binop_p<0x5D, "vmin", X86fmin, 1>,
3542 avx512_fp_binop_p_sae<0x5D, "vmin", X86fminRnd>;
3543 defm VMAX : avx512_fp_binop_p<0x5F, "vmax", X86fmax, 1>,
3544 avx512_fp_binop_p_sae<0x5F, "vmax", X86fmaxRnd>;
3545 let Predicates = [HasDQI] in {
3546 defm VAND : avx512_fp_binop_p<0x54, "vand", X86fand, 1>;
3547 defm VANDN : avx512_fp_binop_p<0x55, "vandn", X86fandn, 0>;
3548 defm VOR : avx512_fp_binop_p<0x56, "vor", X86for, 1>;
3549 defm VXOR : avx512_fp_binop_p<0x57, "vxor", X86fxor, 1>;
3552 multiclass avx512_fp_scalef_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3553 X86VectorVTInfo _> {
3554 defm rr: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3555 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3556 "$src2, $src1", "$src1, $src2",
3557 (_.VT (OpNode _.RC:$src1, _.RC:$src2, (i32 FROUND_CURRENT)))>, EVEX_4V;
3558 let mayLoad = 1 in {
3559 defm rm: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3560 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
3561 "$src2, $src1", "$src1, $src2",
3562 (OpNode _.RC:$src1, (_.LdFrag addr:$src2), (i32 FROUND_CURRENT))>, EVEX_4V;
3563 defm rmb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3564 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
3565 "${src2}"##_.BroadcastStr##", $src1",
3566 "$src1, ${src2}"##_.BroadcastStr,
3567 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3568 (_.ScalarLdFrag addr:$src2))), (i32 FROUND_CURRENT))>,
3573 multiclass avx512_fp_scalef_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
3574 X86VectorVTInfo _> {
3575 defm rr: AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
3576 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3577 "$src2, $src1", "$src1, $src2",
3578 (_.VT (OpNode _.RC:$src1, _.RC:$src2, (i32 FROUND_CURRENT)))>;
3579 let mayLoad = 1 in {
3580 defm rm: AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
3581 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
3582 "$src2, $src1", "$src1, $src2",
3583 (OpNode _.RC:$src1, (_.LdFrag addr:$src2), (i32 FROUND_CURRENT))>;
3587 multiclass avx512_fp_scalef_all<bits<8> opc, bits<8> opcScaler, string OpcodeStr, SDNode OpNode> {
3588 defm PSZ : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v16f32_info>,
3589 avx512_fp_round_packed<opc, OpcodeStr, OpNode, v16f32_info>,
3590 EVEX_V512, EVEX_CD8<32, CD8VF>;
3591 defm PDZ : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v8f64_info>,
3592 avx512_fp_round_packed<opc, OpcodeStr, OpNode, v8f64_info>,
3593 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3594 defm SSZ128 : avx512_fp_scalef_scalar<opcScaler, OpcodeStr, OpNode, f32x_info>,
3595 avx512_fp_scalar_round<opcScaler, OpcodeStr##"ss", f32x_info, OpNode, SSE_ALU_ITINS_S.s>,
3596 EVEX_4V,EVEX_CD8<32, CD8VT1>;
3597 defm SDZ128 : avx512_fp_scalef_scalar<opcScaler, OpcodeStr, OpNode, f64x_info>,
3598 avx512_fp_scalar_round<opcScaler, OpcodeStr##"sd", f64x_info, OpNode, SSE_ALU_ITINS_S.d>,
3599 EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
3601 // Define only if AVX512VL feature is present.
3602 let Predicates = [HasVLX] in {
3603 defm PSZ128 : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v4f32x_info>,
3604 EVEX_V128, EVEX_CD8<32, CD8VF>;
3605 defm PSZ256 : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v8f32x_info>,
3606 EVEX_V256, EVEX_CD8<32, CD8VF>;
3607 defm PDZ128 : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v2f64x_info>,
3608 EVEX_V128, VEX_W, EVEX_CD8<64, CD8VF>;
3609 defm PDZ256 : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v4f64x_info>,
3610 EVEX_V256, VEX_W, EVEX_CD8<64, CD8VF>;
3613 defm VSCALEF : avx512_fp_scalef_all<0x2C, 0x2D, "vscalef", X86scalef>, T8PD;
3615 //===----------------------------------------------------------------------===//
3616 // AVX-512 VPTESTM instructions
3617 //===----------------------------------------------------------------------===//
3619 multiclass avx512_vptest<bits<8> opc, string OpcodeStr, SDNode OpNode,
3620 X86VectorVTInfo _> {
3621 defm rr : AVX512_maskable_cmp<opc, MRMSrcReg, _, (outs _.KRC:$dst),
3622 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3623 "$src2, $src1", "$src1, $src2",
3624 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))>,
3627 defm rm : AVX512_maskable_cmp<opc, MRMSrcMem, _, (outs _.KRC:$dst),
3628 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
3629 "$src2, $src1", "$src1, $src2",
3630 (OpNode (_.VT _.RC:$src1),
3631 (_.VT (bitconvert (_.LdFrag addr:$src2))))>,
3633 EVEX_CD8<_.EltSize, CD8VF>;
3636 multiclass avx512_vptest_mb<bits<8> opc, string OpcodeStr, SDNode OpNode,
3637 X86VectorVTInfo _> {
3639 defm rmb : AVX512_maskable_cmp<opc, MRMSrcMem, _, (outs _.KRC:$dst),
3640 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
3641 "${src2}"##_.BroadcastStr##", $src1",
3642 "$src1, ${src2}"##_.BroadcastStr,
3643 (OpNode (_.VT _.RC:$src1), (_.VT (X86VBroadcast
3644 (_.ScalarLdFrag addr:$src2))))>,
3645 EVEX_B, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
3647 multiclass avx512_vptest_dq_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
3648 AVX512VLVectorVTInfo _> {
3649 let Predicates = [HasAVX512] in
3650 defm Z : avx512_vptest<opc, OpcodeStr, OpNode, _.info512>,
3651 avx512_vptest_mb<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
3653 let Predicates = [HasAVX512, HasVLX] in {
3654 defm Z256 : avx512_vptest<opc, OpcodeStr, OpNode, _.info256>,
3655 avx512_vptest_mb<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
3656 defm Z128 : avx512_vptest<opc, OpcodeStr, OpNode, _.info128>,
3657 avx512_vptest_mb<opc, OpcodeStr, OpNode, _.info128>, EVEX_V128;
3661 multiclass avx512_vptest_dq<bits<8> opc, string OpcodeStr, SDNode OpNode> {
3662 defm D : avx512_vptest_dq_sizes<opc, OpcodeStr#"d", OpNode,
3664 defm Q : avx512_vptest_dq_sizes<opc, OpcodeStr#"q", OpNode,
3665 avx512vl_i64_info>, VEX_W;
3668 multiclass avx512_vptest_wb<bits<8> opc, string OpcodeStr,
3670 let Predicates = [HasBWI] in {
3671 defm WZ: avx512_vptest<opc, OpcodeStr#"w", OpNode, v32i16_info>,
3673 defm BZ: avx512_vptest<opc, OpcodeStr#"b", OpNode, v64i8_info>,
3676 let Predicates = [HasVLX, HasBWI] in {
3678 defm WZ256: avx512_vptest<opc, OpcodeStr#"w", OpNode, v16i16x_info>,
3680 defm WZ128: avx512_vptest<opc, OpcodeStr#"w", OpNode, v8i16x_info>,
3682 defm BZ256: avx512_vptest<opc, OpcodeStr#"b", OpNode, v32i8x_info>,
3684 defm BZ128: avx512_vptest<opc, OpcodeStr#"b", OpNode, v16i8x_info>,
3689 multiclass avx512_vptest_all_forms<bits<8> opc_wb, bits<8> opc_dq, string OpcodeStr,
3691 avx512_vptest_wb <opc_wb, OpcodeStr, OpNode>,
3692 avx512_vptest_dq<opc_dq, OpcodeStr, OpNode>;
3694 defm VPTESTM : avx512_vptest_all_forms<0x26, 0x27, "vptestm", X86testm>, T8PD;
3695 defm VPTESTNM : avx512_vptest_all_forms<0x26, 0x27, "vptestnm", X86testnm>, T8XS;
3697 def : Pat <(i16 (int_x86_avx512_mask_ptestm_d_512 (v16i32 VR512:$src1),
3698 (v16i32 VR512:$src2), (i16 -1))),
3699 (COPY_TO_REGCLASS (VPTESTMDZrr VR512:$src1, VR512:$src2), GR16)>;
3701 def : Pat <(i8 (int_x86_avx512_mask_ptestm_q_512 (v8i64 VR512:$src1),
3702 (v8i64 VR512:$src2), (i8 -1))),
3703 (COPY_TO_REGCLASS (VPTESTMQZrr VR512:$src1, VR512:$src2), GR8)>;
3705 //===----------------------------------------------------------------------===//
3706 // AVX-512 Shift instructions
3707 //===----------------------------------------------------------------------===//
3708 multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
3709 string OpcodeStr, SDNode OpNode, X86VectorVTInfo _> {
3710 defm ri : AVX512_maskable<opc, ImmFormR, _, (outs _.RC:$dst),
3711 (ins _.RC:$src1, u8imm:$src2), OpcodeStr,
3712 "$src2, $src1", "$src1, $src2",
3713 (_.VT (OpNode _.RC:$src1, (i8 imm:$src2))),
3714 SSE_INTSHIFT_ITINS_P.rr>;
3716 defm mi : AVX512_maskable<opc, ImmFormM, _, (outs _.RC:$dst),
3717 (ins _.MemOp:$src1, u8imm:$src2), OpcodeStr,
3718 "$src2, $src1", "$src1, $src2",
3719 (_.VT (OpNode (_.VT (bitconvert (_.LdFrag addr:$src1))),
3721 SSE_INTSHIFT_ITINS_P.rm>;
3724 multiclass avx512_shift_rmbi<bits<8> opc, Format ImmFormM,
3725 string OpcodeStr, SDNode OpNode, X86VectorVTInfo _> {
3727 defm mbi : AVX512_maskable<opc, ImmFormM, _, (outs _.RC:$dst),
3728 (ins _.ScalarMemOp:$src1, u8imm:$src2), OpcodeStr,
3729 "$src2, ${src1}"##_.BroadcastStr, "${src1}"##_.BroadcastStr##", $src2",
3730 (_.VT (OpNode (X86VBroadcast (_.ScalarLdFrag addr:$src1)), (i8 imm:$src2))),
3731 SSE_INTSHIFT_ITINS_P.rm>, EVEX_B;
3734 multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3735 ValueType SrcVT, PatFrag bc_frag, X86VectorVTInfo _> {
3736 // src2 is always 128-bit
3737 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3738 (ins _.RC:$src1, VR128X:$src2), OpcodeStr,
3739 "$src2, $src1", "$src1, $src2",
3740 (_.VT (OpNode _.RC:$src1, (SrcVT VR128X:$src2))),
3741 SSE_INTSHIFT_ITINS_P.rr>, AVX512BIBase, EVEX_4V;
3742 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3743 (ins _.RC:$src1, i128mem:$src2), OpcodeStr,
3744 "$src2, $src1", "$src1, $src2",
3745 (_.VT (OpNode _.RC:$src1, (bc_frag (loadv2i64 addr:$src2)))),
3746 SSE_INTSHIFT_ITINS_P.rm>, AVX512BIBase,
3750 multiclass avx512_shift_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
3751 ValueType SrcVT, PatFrag bc_frag,
3752 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
3753 let Predicates = [prd] in
3754 defm Z : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag,
3755 VTInfo.info512>, EVEX_V512,
3756 EVEX_CD8<VTInfo.info512.EltSize, CD8VQ> ;
3757 let Predicates = [prd, HasVLX] in {
3758 defm Z256 : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag,
3759 VTInfo.info256>, EVEX_V256,
3760 EVEX_CD8<VTInfo.info256.EltSize, CD8VH>;
3761 defm Z128 : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag,
3762 VTInfo.info128>, EVEX_V128,
3763 EVEX_CD8<VTInfo.info128.EltSize, CD8VF>;
3767 multiclass avx512_shift_types<bits<8> opcd, bits<8> opcq, bits<8> opcw,
3768 string OpcodeStr, SDNode OpNode> {
3769 defm D : avx512_shift_sizes<opcd, OpcodeStr#"d", OpNode, v4i32, bc_v4i32,
3770 avx512vl_i32_info, HasAVX512>;
3771 defm Q : avx512_shift_sizes<opcq, OpcodeStr#"q", OpNode, v2i64, bc_v2i64,
3772 avx512vl_i64_info, HasAVX512>, VEX_W;
3773 defm W : avx512_shift_sizes<opcw, OpcodeStr#"w", OpNode, v8i16, bc_v8i16,
3774 avx512vl_i16_info, HasBWI>;
3777 multiclass avx512_shift_rmi_sizes<bits<8> opc, Format ImmFormR, Format ImmFormM,
3778 string OpcodeStr, SDNode OpNode,
3779 AVX512VLVectorVTInfo VTInfo> {
3780 let Predicates = [HasAVX512] in
3781 defm Z: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3783 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
3784 VTInfo.info512>, EVEX_V512;
3785 let Predicates = [HasAVX512, HasVLX] in {
3786 defm Z256: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3788 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
3789 VTInfo.info256>, EVEX_V256;
3790 defm Z128: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3792 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
3793 VTInfo.info128>, EVEX_V128;
3797 multiclass avx512_shift_rmi_w<bits<8> opcw,
3798 Format ImmFormR, Format ImmFormM,
3799 string OpcodeStr, SDNode OpNode> {
3800 let Predicates = [HasBWI] in
3801 defm WZ: avx512_shift_rmi<opcw, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3802 v32i16_info>, EVEX_V512;
3803 let Predicates = [HasVLX, HasBWI] in {
3804 defm WZ256: avx512_shift_rmi<opcw, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3805 v16i16x_info>, EVEX_V256;
3806 defm WZ128: avx512_shift_rmi<opcw, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3807 v8i16x_info>, EVEX_V128;
3811 multiclass avx512_shift_rmi_dq<bits<8> opcd, bits<8> opcq,
3812 Format ImmFormR, Format ImmFormM,
3813 string OpcodeStr, SDNode OpNode> {
3814 defm D: avx512_shift_rmi_sizes<opcd, ImmFormR, ImmFormM, OpcodeStr#"d", OpNode,
3815 avx512vl_i32_info>, EVEX_CD8<32, CD8VF>;
3816 defm Q: avx512_shift_rmi_sizes<opcq, ImmFormR, ImmFormM, OpcodeStr#"q", OpNode,
3817 avx512vl_i64_info>, EVEX_CD8<64, CD8VF>, VEX_W;
3820 defm VPSRL : avx512_shift_rmi_dq<0x72, 0x73, MRM2r, MRM2m, "vpsrl", X86vsrli>,
3821 avx512_shift_rmi_w<0x71, MRM2r, MRM2m, "vpsrlw", X86vsrli>, AVX512BIi8Base, EVEX_4V;
3823 defm VPSLL : avx512_shift_rmi_dq<0x72, 0x73, MRM6r, MRM6m, "vpsll", X86vshli>,
3824 avx512_shift_rmi_w<0x71, MRM6r, MRM6m, "vpsllw", X86vshli>, AVX512BIi8Base, EVEX_4V;
3826 defm VPSRA : avx512_shift_rmi_dq<0x72, 0x72, MRM4r, MRM4m, "vpsra", X86vsrai>,
3827 avx512_shift_rmi_w<0x71, MRM4r, MRM4m, "vpsraw", X86vsrai>, AVX512BIi8Base, EVEX_4V;
3829 defm VPROR : avx512_shift_rmi_dq<0x72, 0x72, MRM0r, MRM0m, "vpror", rotr>, AVX512BIi8Base, EVEX_4V;
3830 defm VPROL : avx512_shift_rmi_dq<0x72, 0x72, MRM1r, MRM1m, "vprol", rotl>, AVX512BIi8Base, EVEX_4V;
3832 defm VPSLL : avx512_shift_types<0xF2, 0xF3, 0xF1, "vpsll", X86vshl>;
3833 defm VPSRA : avx512_shift_types<0xE2, 0xE2, 0xE1, "vpsra", X86vsra>;
3834 defm VPSRL : avx512_shift_types<0xD2, 0xD3, 0xD1, "vpsrl", X86vsrl>;
3836 //===-------------------------------------------------------------------===//
3837 // Variable Bit Shifts
3838 //===-------------------------------------------------------------------===//
3839 multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
3840 X86VectorVTInfo _> {
3841 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3842 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3843 "$src2, $src1", "$src1, $src2",
3844 (_.VT (OpNode _.RC:$src1, (_.VT _.RC:$src2))),
3845 SSE_INTSHIFT_ITINS_P.rr>, AVX5128IBase, EVEX_4V;
3847 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3848 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
3849 "$src2, $src1", "$src1, $src2",
3850 (_.VT (OpNode _.RC:$src1,
3851 (_.VT (bitconvert (_.LdFrag addr:$src2))))),
3852 SSE_INTSHIFT_ITINS_P.rm>, AVX5128IBase, EVEX_4V,
3853 EVEX_CD8<_.EltSize, CD8VF>;
3856 multiclass avx512_var_shift_mb<bits<8> opc, string OpcodeStr, SDNode OpNode,
3857 X86VectorVTInfo _> {
3859 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3860 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
3861 "${src2}"##_.BroadcastStr##", $src1",
3862 "$src1, ${src2}"##_.BroadcastStr,
3863 (_.VT (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3864 (_.ScalarLdFrag addr:$src2))))),
3865 SSE_INTSHIFT_ITINS_P.rm>, AVX5128IBase, EVEX_B,
3866 EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
3868 multiclass avx512_var_shift_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
3869 AVX512VLVectorVTInfo _> {
3870 let Predicates = [HasAVX512] in
3871 defm Z : avx512_var_shift<opc, OpcodeStr, OpNode, _.info512>,
3872 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
3874 let Predicates = [HasAVX512, HasVLX] in {
3875 defm Z256 : avx512_var_shift<opc, OpcodeStr, OpNode, _.info256>,
3876 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
3877 defm Z128 : avx512_var_shift<opc, OpcodeStr, OpNode, _.info128>,
3878 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info128>, EVEX_V128;
3882 multiclass avx512_var_shift_types<bits<8> opc, string OpcodeStr,
3884 defm D : avx512_var_shift_sizes<opc, OpcodeStr#"d", OpNode,
3886 defm Q : avx512_var_shift_sizes<opc, OpcodeStr#"q", OpNode,
3887 avx512vl_i64_info>, VEX_W;
3890 multiclass avx512_var_shift_w<bits<8> opc, string OpcodeStr,
3892 let Predicates = [HasBWI] in
3893 defm WZ: avx512_var_shift<opc, OpcodeStr, OpNode, v32i16_info>,
3895 let Predicates = [HasVLX, HasBWI] in {
3897 defm WZ256: avx512_var_shift<opc, OpcodeStr, OpNode, v16i16x_info>,
3899 defm WZ128: avx512_var_shift<opc, OpcodeStr, OpNode, v8i16x_info>,
3904 defm VPSLLV : avx512_var_shift_types<0x47, "vpsllv", shl>,
3905 avx512_var_shift_w<0x12, "vpsllvw", shl>;
3906 defm VPSRAV : avx512_var_shift_types<0x46, "vpsrav", sra>,
3907 avx512_var_shift_w<0x11, "vpsravw", sra>;
3908 defm VPSRLV : avx512_var_shift_types<0x45, "vpsrlv", srl>,
3909 avx512_var_shift_w<0x10, "vpsrlvw", srl>;
3910 defm VPRORV : avx512_var_shift_types<0x14, "vprorv", rotr>;
3911 defm VPROLV : avx512_var_shift_types<0x15, "vprolv", rotl>;
3913 //===-------------------------------------------------------------------===//
3914 // 1-src variable permutation VPERMW/D/Q
3915 //===-------------------------------------------------------------------===//
3916 multiclass avx512_vperm_dq_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
3917 AVX512VLVectorVTInfo _> {
3918 let Predicates = [HasAVX512] in
3919 defm Z : avx512_var_shift<opc, OpcodeStr, OpNode, _.info512>,
3920 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
3922 let Predicates = [HasAVX512, HasVLX] in
3923 defm Z256 : avx512_var_shift<opc, OpcodeStr, OpNode, _.info256>,
3924 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
3927 multiclass avx512_vpermi_dq_sizes<bits<8> opc, Format ImmFormR, Format ImmFormM,
3928 string OpcodeStr, SDNode OpNode,
3929 AVX512VLVectorVTInfo VTInfo> {
3930 let Predicates = [HasAVX512] in
3931 defm Z: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3933 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
3934 VTInfo.info512>, EVEX_V512;
3935 let Predicates = [HasAVX512, HasVLX] in
3936 defm Z256: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3938 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
3939 VTInfo.info256>, EVEX_V256;
3943 defm VPERM : avx512_var_shift_w<0x8D, "vpermw", X86VPermv>;
3945 defm VPERMD : avx512_vperm_dq_sizes<0x36, "vpermd", X86VPermv,
3947 defm VPERMQ : avx512_vperm_dq_sizes<0x36, "vpermq", X86VPermv,
3948 avx512vl_i64_info>, VEX_W;
3949 defm VPERMPS : avx512_vperm_dq_sizes<0x16, "vpermps", X86VPermv,
3951 defm VPERMPD : avx512_vperm_dq_sizes<0x16, "vpermpd", X86VPermv,
3952 avx512vl_f64_info>, VEX_W;
3954 defm VPERMQ : avx512_vpermi_dq_sizes<0x00, MRMSrcReg, MRMSrcMem, "vpermq",
3955 X86VPermi, avx512vl_i64_info>,
3956 EVEX, AVX512AIi8Base, EVEX_CD8<64, CD8VF>, VEX_W;
3957 defm VPERMPD : avx512_vpermi_dq_sizes<0x01, MRMSrcReg, MRMSrcMem, "vpermpd",
3958 X86VPermi, avx512vl_f64_info>,
3959 EVEX, AVX512AIi8Base, EVEX_CD8<64, CD8VF>, VEX_W;
3961 //===----------------------------------------------------------------------===//
3962 // AVX-512 - VPSHUFD, VPSHUFLW, VPSHUFHW
3963 //===----------------------------------------------------------------------===//
3965 defm VPSHUFD : avx512_shift_rmi_sizes<0x70, MRMSrcReg, MRMSrcMem, "vpshufd",
3966 X86PShufd, avx512vl_i32_info>,
3967 EVEX, AVX512BIi8Base, EVEX_CD8<32, CD8VF>;
3968 defm VPSHUFH : avx512_shift_rmi_w<0x70, MRMSrcReg, MRMSrcMem, "vpshufhw",
3969 X86PShufhw>, EVEX, AVX512XSIi8Base, VEX_W;
3970 defm VPSHUFL : avx512_shift_rmi_w<0x70, MRMSrcReg, MRMSrcMem, "vpshuflw",
3971 X86PShuflw>, EVEX, AVX512XDIi8Base, VEX_W;
3973 multiclass avx512_pshufb_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode> {
3974 let Predicates = [HasBWI] in
3975 defm Z: avx512_var_shift<opc, OpcodeStr, OpNode, v64i8_info>, EVEX_V512;
3977 let Predicates = [HasVLX, HasBWI] in {
3978 defm Z256: avx512_var_shift<opc, OpcodeStr, OpNode, v32i8x_info>, EVEX_V256;
3979 defm Z128: avx512_var_shift<opc, OpcodeStr, OpNode, v16i8x_info>, EVEX_V128;
3983 defm VPSHUFB: avx512_pshufb_sizes<0x00, "vpshufb", X86pshufb>;
3985 //===----------------------------------------------------------------------===//
3986 // AVX-512 - MOVDDUP
3987 //===----------------------------------------------------------------------===//
3989 multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT,
3990 X86MemOperand x86memop, PatFrag memop_frag> {
3991 def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3992 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3993 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX;
3994 def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3995 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3997 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX;
4000 defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, loadv8f64>,
4001 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4002 def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
4003 (VMOVDDUPZrm addr:$src)>;
4005 //===---------------------------------------------------------------------===//
4006 // Replicate Single FP - MOVSHDUP and MOVSLDUP
4007 //===---------------------------------------------------------------------===//
4008 multiclass avx512_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
4009 ValueType vt, RegisterClass RC, PatFrag mem_frag,
4010 X86MemOperand x86memop> {
4011 def rr : AVX512XSI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4012 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4013 [(set RC:$dst, (vt (OpNode RC:$src)))]>, EVEX;
4015 def rm : AVX512XSI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
4016 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4017 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>, EVEX;
4020 defm VMOVSHDUPZ : avx512_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
4021 v16f32, VR512, loadv16f32, f512mem>, EVEX_V512,
4022 EVEX_CD8<32, CD8VF>;
4023 defm VMOVSLDUPZ : avx512_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
4024 v16f32, VR512, loadv16f32, f512mem>, EVEX_V512,
4025 EVEX_CD8<32, CD8VF>;
4027 def : Pat<(v16i32 (X86Movshdup VR512:$src)), (VMOVSHDUPZrr VR512:$src)>;
4028 def : Pat<(v16i32 (X86Movshdup (loadv16i32 addr:$src))),
4029 (VMOVSHDUPZrm addr:$src)>;
4030 def : Pat<(v16i32 (X86Movsldup VR512:$src)), (VMOVSLDUPZrr VR512:$src)>;
4031 def : Pat<(v16i32 (X86Movsldup (loadv16i32 addr:$src))),
4032 (VMOVSLDUPZrm addr:$src)>;
4034 //===----------------------------------------------------------------------===//
4035 // Move Low to High and High to Low packed FP Instructions
4036 //===----------------------------------------------------------------------===//
4037 def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
4038 (ins VR128X:$src1, VR128X:$src2),
4039 "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4040 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
4041 IIC_SSE_MOV_LH>, EVEX_4V;
4042 def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
4043 (ins VR128X:$src1, VR128X:$src2),
4044 "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4045 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
4046 IIC_SSE_MOV_LH>, EVEX_4V;
4048 let Predicates = [HasAVX512] in {
4050 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
4051 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
4052 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
4053 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
4056 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
4057 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
4060 //===----------------------------------------------------------------------===//
4061 // FMA - Fused Multiply Operations
4064 let Constraints = "$src1 = $dst" in {
4065 multiclass avx512_fma3p_213_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
4066 X86VectorVTInfo _> {
4067 defm r: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4068 (ins _.RC:$src2, _.RC:$src3),
4069 OpcodeStr, "$src3, $src2", "$src2, $src3",
4070 (_.VT (OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3))>,
4073 let mayLoad = 1 in {
4074 defm m: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4075 (ins _.RC:$src2, _.MemOp:$src3),
4076 OpcodeStr, "$src3, $src2", "$src2, $src3",
4077 (_.VT (OpNode _.RC:$src1, _.RC:$src2, (_.LdFrag addr:$src3)))>,
4080 defm mb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4081 (ins _.RC:$src2, _.ScalarMemOp:$src3),
4082 OpcodeStr, !strconcat("${src3}", _.BroadcastStr,", $src2"),
4083 !strconcat("$src2, ${src3}", _.BroadcastStr ),
4085 _.RC:$src2,(_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3))))>,
4086 AVX512FMA3Base, EVEX_B;
4090 multiclass avx512_fma3_213_round<bits<8> opc, string OpcodeStr, SDNode OpNode,
4091 X86VectorVTInfo _> {
4092 defm rb: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4093 (ins _.RC:$src2, _.RC:$src3, AVX512RC:$rc),
4094 OpcodeStr, "$rc, $src3, $src2", "$src2, $src3, $rc",
4095 (_.VT ( OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3, (i32 imm:$rc)))>,
4096 AVX512FMA3Base, EVEX_B, EVEX_RC;
4098 } // Constraints = "$src1 = $dst"
4100 multiclass avx512_fma3p_213_common<bits<8> opc, string OpcodeStr, SDNode OpNode,
4101 SDNode OpNodeRnd, AVX512VLVectorVTInfo _> {
4102 let Predicates = [HasAVX512] in {
4103 defm Z : avx512_fma3p_213_rm<opc, OpcodeStr, OpNode, _.info512>,
4104 avx512_fma3_213_round<opc, OpcodeStr, OpNodeRnd, _.info512>,
4105 EVEX_V512, EVEX_CD8<_.info512.EltSize, CD8VF>;
4107 let Predicates = [HasVLX, HasAVX512] in {
4108 defm Z256 : avx512_fma3p_213_rm<opc, OpcodeStr, OpNode, _.info256>,
4109 EVEX_V256, EVEX_CD8<_.info256.EltSize, CD8VF>;
4110 defm Z128 : avx512_fma3p_213_rm<opc, OpcodeStr, OpNode, _.info128>,
4111 EVEX_V128, EVEX_CD8<_.info128.EltSize, CD8VF>;
4115 multiclass avx512_fma3p_213_f<bits<8> opc, string OpcodeStr, SDNode OpNode,
4116 SDNode OpNodeRnd > {
4117 defm PS : avx512_fma3p_213_common<opc, OpcodeStr#"ps", OpNode, OpNodeRnd,
4119 defm PD : avx512_fma3p_213_common<opc, OpcodeStr#"pd", OpNode, OpNodeRnd,
4120 avx512vl_f64_info>, VEX_W;
4123 defm VFMADD213 : avx512_fma3p_213_f<0xA8, "vfmadd213", X86Fmadd, X86FmaddRnd>;
4124 defm VFMSUB213 : avx512_fma3p_213_f<0xAA, "vfmsub213", X86Fmsub, X86FmsubRnd>;
4125 defm VFMADDSUB213 : avx512_fma3p_213_f<0xA6, "vfmaddsub213", X86Fmaddsub, X86FmaddsubRnd>;
4126 defm VFMSUBADD213 : avx512_fma3p_213_f<0xA7, "vfmsubadd213", X86Fmsubadd, X86FmsubaddRnd>;
4127 defm VFNMADD213 : avx512_fma3p_213_f<0xAC, "vfnmadd213", X86Fnmadd, X86FnmaddRnd>;
4128 defm VFNMSUB213 : avx512_fma3p_213_f<0xAE, "vfnmsub213", X86Fnmsub, X86FnmsubRnd>;
4131 let Constraints = "$src1 = $dst" in {
4132 multiclass avx512_fma3p_231_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
4133 X86VectorVTInfo _> {
4134 defm r: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4135 (ins _.RC:$src2, _.RC:$src3),
4136 OpcodeStr, "$src3, $src2", "$src2, $src3",
4137 (_.VT (OpNode _.RC:$src2, _.RC:$src3, _.RC:$src1))>,
4140 let mayLoad = 1 in {
4141 defm m: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4142 (ins _.RC:$src2, _.MemOp:$src3),
4143 OpcodeStr, "$src3, $src2", "$src2, $src3",
4144 (_.VT (OpNode _.RC:$src2, (_.LdFrag addr:$src3), _.RC:$src1))>,
4147 defm mb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4148 (ins _.RC:$src2, _.ScalarMemOp:$src3),
4149 OpcodeStr, "${src3}"##_.BroadcastStr##", $src2",
4150 "$src2, ${src3}"##_.BroadcastStr,
4151 (_.VT (OpNode _.RC:$src2,
4152 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src3))),
4153 _.RC:$src1))>, AVX512FMA3Base, EVEX_B;
4157 multiclass avx512_fma3_231_round<bits<8> opc, string OpcodeStr, SDNode OpNode,
4158 X86VectorVTInfo _> {
4159 defm rb: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4160 (ins _.RC:$src2, _.RC:$src3, AVX512RC:$rc),
4161 OpcodeStr, "$rc, $src3, $src2", "$src2, $src3, $rc",
4162 (_.VT ( OpNode _.RC:$src2, _.RC:$src3, _.RC:$src1, (i32 imm:$rc)))>,
4163 AVX512FMA3Base, EVEX_B, EVEX_RC;
4165 } // Constraints = "$src1 = $dst"
4167 multiclass avx512_fma3p_231_common<bits<8> opc, string OpcodeStr, SDNode OpNode,
4168 SDNode OpNodeRnd, AVX512VLVectorVTInfo _> {
4169 let Predicates = [HasAVX512] in {
4170 defm Z : avx512_fma3p_231_rm<opc, OpcodeStr, OpNode, _.info512>,
4171 avx512_fma3_231_round<opc, OpcodeStr, OpNodeRnd, _.info512>,
4172 EVEX_V512, EVEX_CD8<_.info512.EltSize, CD8VF>;
4174 let Predicates = [HasVLX, HasAVX512] in {
4175 defm Z256 : avx512_fma3p_231_rm<opc, OpcodeStr, OpNode, _.info256>,
4176 EVEX_V256, EVEX_CD8<_.info256.EltSize, CD8VF>;
4177 defm Z128 : avx512_fma3p_231_rm<opc, OpcodeStr, OpNode, _.info128>,
4178 EVEX_V128, EVEX_CD8<_.info128.EltSize, CD8VF>;
4182 multiclass avx512_fma3p_231_f<bits<8> opc, string OpcodeStr, SDNode OpNode,
4183 SDNode OpNodeRnd > {
4184 defm PS : avx512_fma3p_231_common<opc, OpcodeStr#"ps", OpNode, OpNodeRnd,
4186 defm PD : avx512_fma3p_231_common<opc, OpcodeStr#"pd", OpNode, OpNodeRnd,
4187 avx512vl_f64_info>, VEX_W;
4190 defm VFMADD231 : avx512_fma3p_231_f<0xB8, "vfmadd231", X86Fmadd, X86FmaddRnd>;
4191 defm VFMSUB231 : avx512_fma3p_231_f<0xBA, "vfmsub231", X86Fmsub, X86FmsubRnd>;
4192 defm VFMADDSUB231 : avx512_fma3p_231_f<0xB6, "vfmaddsub231", X86Fmaddsub, X86FmaddsubRnd>;
4193 defm VFMSUBADD231 : avx512_fma3p_231_f<0xB7, "vfmsubadd231", X86Fmsubadd, X86FmsubaddRnd>;
4194 defm VFNMADD231 : avx512_fma3p_231_f<0xBC, "vfnmadd231", X86Fnmadd, X86FnmaddRnd>;
4195 defm VFNMSUB231 : avx512_fma3p_231_f<0xBE, "vfnmsub231", X86Fnmsub, X86FnmsubRnd>;
4197 let Constraints = "$src1 = $dst" in {
4198 multiclass avx512_fma3p_132_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
4199 X86VectorVTInfo _> {
4200 defm r: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4201 (ins _.RC:$src3, _.RC:$src2),
4202 OpcodeStr, "$src2, $src3", "$src3, $src2",
4203 (_.VT (OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3))>,
4206 let mayLoad = 1 in {
4207 defm m: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4208 (ins _.RC:$src3, _.MemOp:$src2),
4209 OpcodeStr, "$src2, $src3", "$src3, $src2",
4210 (_.VT (OpNode _.RC:$src1, (_.LdFrag addr:$src2), _.RC:$src3))>,
4213 defm mb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4214 (ins _.RC:$src3, _.ScalarMemOp:$src2),
4215 OpcodeStr, "${src2}"##_.BroadcastStr##", $src3",
4216 "$src3, ${src2}"##_.BroadcastStr,
4217 (_.VT (OpNode _.RC:$src1,
4218 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src2))),
4219 _.RC:$src3))>, AVX512FMA3Base, EVEX_B;
4223 multiclass avx512_fma3_132_round<bits<8> opc, string OpcodeStr, SDNode OpNode,
4224 X86VectorVTInfo _> {
4225 defm rb: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4226 (ins _.RC:$src3, _.RC:$src2, AVX512RC:$rc),
4227 OpcodeStr, "$rc, $src2, $src3", "$src3, $src2, $rc",
4228 (_.VT ( OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3, (i32 imm:$rc)))>,
4229 AVX512FMA3Base, EVEX_B, EVEX_RC;
4231 } // Constraints = "$src1 = $dst"
4233 multiclass avx512_fma3p_132_common<bits<8> opc, string OpcodeStr, SDNode OpNode,
4234 SDNode OpNodeRnd, AVX512VLVectorVTInfo _> {
4235 let Predicates = [HasAVX512] in {
4236 defm Z : avx512_fma3p_132_rm<opc, OpcodeStr, OpNode, _.info512>,
4237 avx512_fma3_132_round<opc, OpcodeStr, OpNodeRnd, _.info512>,
4238 EVEX_V512, EVEX_CD8<_.info512.EltSize, CD8VF>;
4240 let Predicates = [HasVLX, HasAVX512] in {
4241 defm Z256 : avx512_fma3p_132_rm<opc, OpcodeStr, OpNode, _.info256>,
4242 EVEX_V256, EVEX_CD8<_.info256.EltSize, CD8VF>;
4243 defm Z128 : avx512_fma3p_132_rm<opc, OpcodeStr, OpNode, _.info128>,
4244 EVEX_V128, EVEX_CD8<_.info128.EltSize, CD8VF>;
4248 multiclass avx512_fma3p_132_f<bits<8> opc, string OpcodeStr, SDNode OpNode,
4249 SDNode OpNodeRnd > {
4250 defm PS : avx512_fma3p_132_common<opc, OpcodeStr#"ps", OpNode, OpNodeRnd,
4252 defm PD : avx512_fma3p_132_common<opc, OpcodeStr#"pd", OpNode, OpNodeRnd,
4253 avx512vl_f64_info>, VEX_W;
4256 defm VFMADD132 : avx512_fma3p_132_f<0x98, "vfmadd132", X86Fmadd, X86FmaddRnd>;
4257 defm VFMSUB132 : avx512_fma3p_132_f<0x9A, "vfmsub132", X86Fmsub, X86FmsubRnd>;
4258 defm VFMADDSUB132 : avx512_fma3p_132_f<0x96, "vfmaddsub132", X86Fmaddsub, X86FmaddsubRnd>;
4259 defm VFMSUBADD132 : avx512_fma3p_132_f<0x97, "vfmsubadd132", X86Fmsubadd, X86FmsubaddRnd>;
4260 defm VFNMADD132 : avx512_fma3p_132_f<0x9C, "vfnmadd132", X86Fnmadd, X86FnmaddRnd>;
4261 defm VFNMSUB132 : avx512_fma3p_132_f<0x9E, "vfnmsub132", X86Fnmsub, X86FnmsubRnd>;
4264 let Constraints = "$src1 = $dst" in {
4265 multiclass avx512_fma3s_common<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
4266 dag RHS_VEC_r, dag RHS_VEC_m, dag RHS_VEC_rb,
4267 dag RHS_r, dag RHS_m > {
4268 defm r_Int: AVX512_maskable_3src_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4269 (ins _.RC:$src2, _.RC:$src3), OpcodeStr,
4270 "$src3, $src2", "$src2, $src3", RHS_VEC_r>, AVX512FMA3Base;
4273 defm m_Int: AVX512_maskable_3src_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
4274 (ins _.RC:$src2, _.MemOp:$src3), OpcodeStr,
4275 "$src3, $src2", "$src2, $src3", RHS_VEC_m>, AVX512FMA3Base;
4277 defm rb_Int: AVX512_maskable_3src_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4278 (ins _.RC:$src2, _.RC:$src3, AVX512RC:$rc),
4279 OpcodeStr, "$rc, $src3, $src2", "$src2, $src3, $rc", RHS_VEC_rb>,
4280 AVX512FMA3Base, EVEX_B, EVEX_RC;
4282 let isCodeGenOnly = 1 in {
4283 def r : AVX512FMA3<opc, MRMSrcReg, (outs _.FRC:$dst),
4284 (ins _.FRC:$src1, _.FRC:$src2, _.FRC:$src3),
4285 !strconcat(OpcodeStr,
4286 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4289 def m : AVX512FMA3<opc, MRMSrcMem, (outs _.FRC:$dst),
4290 (ins _.FRC:$src1, _.FRC:$src2, _.ScalarMemOp:$src3),
4291 !strconcat(OpcodeStr,
4292 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4294 }// isCodeGenOnly = 1
4296 }// Constraints = "$src1 = $dst"
4298 multiclass avx512_fma3s_all<bits<8> opc213, bits<8> opc231, bits<8> opc132,
4299 string OpcodeStr, SDNode OpNode, SDNode OpNodeRnd, X86VectorVTInfo _ ,
4302 defm NAME#213#SUFF: avx512_fma3s_common<opc213, OpcodeStr#"213"#_.Suffix , _ ,
4303 (_.VT (OpNode _.RC:$src2, _.RC:$src1, _.RC:$src3)),
4304 (_.VT (OpNode _.RC:$src2, _.RC:$src1,
4305 (_.VT (scalar_to_vector(_.ScalarLdFrag addr:$src3))))),
4306 (_.VT ( OpNodeRnd _.RC:$src2, _.RC:$src1, _.RC:$src3,
4308 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src2, _.FRC:$src1,
4310 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src2, _.FRC:$src1,
4311 (_.ScalarLdFrag addr:$src3))))>;
4313 defm NAME#231#SUFF: avx512_fma3s_common<opc231, OpcodeStr#"231"#_.Suffix , _ ,
4314 (_.VT (OpNode _.RC:$src2, _.RC:$src3, _.RC:$src1)),
4315 (_.VT (OpNode _.RC:$src2,
4316 (_.VT (scalar_to_vector(_.ScalarLdFrag addr:$src3))),
4318 (_.VT ( OpNodeRnd _.RC:$src2, _.RC:$src3, _.RC:$src1,
4320 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src2, _.FRC:$src3,
4322 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src2,
4323 (_.ScalarLdFrag addr:$src3), _.FRC:$src1)))>;
4325 defm NAME#132#SUFF: avx512_fma3s_common<opc132, OpcodeStr#"132"#_.Suffix , _ ,
4326 (_.VT (OpNode _.RC:$src1, _.RC:$src3, _.RC:$src2)),
4327 (_.VT (OpNode _.RC:$src1,
4328 (_.VT (scalar_to_vector(_.ScalarLdFrag addr:$src3))),
4330 (_.VT ( OpNodeRnd _.RC:$src1, _.RC:$src3, _.RC:$src2,
4332 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src1, _.FRC:$src3,
4334 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src1,
4335 (_.ScalarLdFrag addr:$src3), _.FRC:$src2)))>;
4338 multiclass avx512_fma3s<bits<8> opc213, bits<8> opc231, bits<8> opc132,
4339 string OpcodeStr, SDNode OpNode, SDNode OpNodeRnd>{
4340 let Predicates = [HasAVX512] in {
4341 defm NAME : avx512_fma3s_all<opc213, opc231, opc132, OpcodeStr, OpNode,
4342 OpNodeRnd, f32x_info, "SS">,
4343 EVEX_CD8<32, CD8VT1>, VEX_LIG;
4344 defm NAME : avx512_fma3s_all<opc213, opc231, opc132, OpcodeStr, OpNode,
4345 OpNodeRnd, f64x_info, "SD">,
4346 EVEX_CD8<64, CD8VT1>, VEX_LIG, VEX_W;
4350 defm VFMADD : avx512_fma3s<0xA9, 0xB9, 0x99, "vfmadd", X86Fmadd, X86FmaddRnd>;
4351 defm VFMSUB : avx512_fma3s<0xAB, 0xBB, 0x9B, "vfmsub", X86Fmsub, X86FmsubRnd>;
4352 defm VFNMADD : avx512_fma3s<0xAD, 0xBD, 0x9D, "vfnmadd", X86Fnmadd, X86FnmaddRnd>;
4353 defm VFNMSUB : avx512_fma3s<0xAF, 0xBF, 0x9F, "vfnmsub", X86Fnmsub, X86FnmsubRnd>;
4355 //===----------------------------------------------------------------------===//
4356 // AVX-512 Scalar convert from sign integer to float/double
4357 //===----------------------------------------------------------------------===//
4359 multiclass avx512_vcvtsi<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
4360 X86VectorVTInfo DstVT, X86MemOperand x86memop,
4361 PatFrag ld_frag, string asm> {
4362 let hasSideEffects = 0 in {
4363 def rr : SI<opc, MRMSrcReg, (outs DstVT.FRC:$dst),
4364 (ins DstVT.FRC:$src1, SrcRC:$src),
4365 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
4368 def rm : SI<opc, MRMSrcMem, (outs DstVT.FRC:$dst),
4369 (ins DstVT.FRC:$src1, x86memop:$src),
4370 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
4372 } // hasSideEffects = 0
4373 let isCodeGenOnly = 1 in {
4374 def rr_Int : SI<opc, MRMSrcReg, (outs DstVT.RC:$dst),
4375 (ins DstVT.RC:$src1, SrcRC:$src2),
4376 !strconcat(asm,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4377 [(set DstVT.RC:$dst,
4378 (OpNode (DstVT.VT DstVT.RC:$src1),
4380 (i32 FROUND_CURRENT)))]>, EVEX_4V;
4382 def rm_Int : SI<opc, MRMSrcMem, (outs DstVT.RC:$dst),
4383 (ins DstVT.RC:$src1, x86memop:$src2),
4384 !strconcat(asm,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4385 [(set DstVT.RC:$dst,
4386 (OpNode (DstVT.VT DstVT.RC:$src1),
4387 (ld_frag addr:$src2),
4388 (i32 FROUND_CURRENT)))]>, EVEX_4V;
4389 }//isCodeGenOnly = 1
4392 multiclass avx512_vcvtsi_round<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
4393 X86VectorVTInfo DstVT, string asm> {
4394 def rrb_Int : SI<opc, MRMSrcReg, (outs DstVT.RC:$dst),
4395 (ins DstVT.RC:$src1, SrcRC:$src2, AVX512RC:$rc),
4397 "\t{$src2, $rc, $src1, $dst|$dst, $src1, $rc, $src2}"),
4398 [(set DstVT.RC:$dst,
4399 (OpNode (DstVT.VT DstVT.RC:$src1),
4401 (i32 imm:$rc)))]>, EVEX_4V, EVEX_B, EVEX_RC;
4404 multiclass avx512_vcvtsi_common<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
4405 X86VectorVTInfo DstVT, X86MemOperand x86memop,
4406 PatFrag ld_frag, string asm> {
4407 defm NAME : avx512_vcvtsi_round<opc, OpNode, SrcRC, DstVT, asm>,
4408 avx512_vcvtsi<opc, OpNode, SrcRC, DstVT, x86memop, ld_frag, asm>,
4412 let Predicates = [HasAVX512] in {
4413 defm VCVTSI2SSZ : avx512_vcvtsi_common<0x2A, X86SintToFpRnd, GR32,
4414 v4f32x_info, i32mem, loadi32, "cvtsi2ss{l}">,
4415 XS, EVEX_CD8<32, CD8VT1>;
4416 defm VCVTSI642SSZ: avx512_vcvtsi_common<0x2A, X86SintToFpRnd, GR64,
4417 v4f32x_info, i64mem, loadi64, "cvtsi2ss{q}">,
4418 XS, VEX_W, EVEX_CD8<64, CD8VT1>;
4419 defm VCVTSI2SDZ : avx512_vcvtsi_common<0x2A, X86SintToFpRnd, GR32,
4420 v2f64x_info, i32mem, loadi32, "cvtsi2sd{l}">,
4421 XD, EVEX_CD8<32, CD8VT1>;
4422 defm VCVTSI642SDZ: avx512_vcvtsi_common<0x2A, X86SintToFpRnd, GR64,
4423 v2f64x_info, i64mem, loadi64, "cvtsi2sd{q}">,
4424 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
4426 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
4427 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
4428 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
4429 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
4430 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
4431 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
4432 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
4433 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
4435 def : Pat<(f32 (sint_to_fp GR32:$src)),
4436 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
4437 def : Pat<(f32 (sint_to_fp GR64:$src)),
4438 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
4439 def : Pat<(f64 (sint_to_fp GR32:$src)),
4440 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
4441 def : Pat<(f64 (sint_to_fp GR64:$src)),
4442 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
4444 defm VCVTUSI2SSZ : avx512_vcvtsi_common<0x7B, X86UintToFpRnd, GR32,
4445 v4f32x_info, i32mem, loadi32,
4446 "cvtusi2ss{l}">, XS, EVEX_CD8<32, CD8VT1>;
4447 defm VCVTUSI642SSZ : avx512_vcvtsi_common<0x7B, X86UintToFpRnd, GR64,
4448 v4f32x_info, i64mem, loadi64, "cvtusi2ss{q}">,
4449 XS, VEX_W, EVEX_CD8<64, CD8VT1>;
4450 defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, X86UintToFpRnd, GR32, v2f64x_info,
4451 i32mem, loadi32, "cvtusi2sd{l}">,
4452 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
4453 defm VCVTUSI642SDZ : avx512_vcvtsi_common<0x7B, X86UintToFpRnd, GR64,
4454 v2f64x_info, i64mem, loadi64, "cvtusi2sd{q}">,
4455 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
4457 def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
4458 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
4459 def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
4460 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
4461 def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
4462 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
4463 def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
4464 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
4466 def : Pat<(f32 (uint_to_fp GR32:$src)),
4467 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
4468 def : Pat<(f32 (uint_to_fp GR64:$src)),
4469 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
4470 def : Pat<(f64 (uint_to_fp GR32:$src)),
4471 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
4472 def : Pat<(f64 (uint_to_fp GR64:$src)),
4473 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
4476 //===----------------------------------------------------------------------===//
4477 // AVX-512 Scalar convert from float/double to integer
4478 //===----------------------------------------------------------------------===//
4479 multiclass avx512_cvt_s_int<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
4480 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
4482 let hasSideEffects = 0 in {
4483 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
4484 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4485 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG,
4486 Requires<[HasAVX512]>;
4488 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
4489 !strconcat(asm,"\t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG,
4490 Requires<[HasAVX512]>;
4491 } // hasSideEffects = 0
4493 let Predicates = [HasAVX512] in {
4494 // Convert float/double to signed/unsigned int 32/64
4495 defm VCVTSS2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
4496 ssmem, sse_load_f32, "cvtss2si">,
4497 XS, EVEX_CD8<32, CD8VT1>;
4498 defm VCVTSS2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse_cvtss2si64,
4499 ssmem, sse_load_f32, "cvtss2si">,
4500 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
4501 defm VCVTSS2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtss2usi,
4502 ssmem, sse_load_f32, "cvtss2usi">,
4503 XS, EVEX_CD8<32, CD8VT1>;
4504 defm VCVTSS2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
4505 int_x86_avx512_cvtss2usi64, ssmem,
4506 sse_load_f32, "cvtss2usi">, XS, VEX_W,
4507 EVEX_CD8<32, CD8VT1>;
4508 defm VCVTSD2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
4509 sdmem, sse_load_f64, "cvtsd2si">,
4510 XD, EVEX_CD8<64, CD8VT1>;
4511 defm VCVTSD2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse2_cvtsd2si64,
4512 sdmem, sse_load_f64, "cvtsd2si">,
4513 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
4514 defm VCVTSD2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtsd2usi,
4515 sdmem, sse_load_f64, "cvtsd2usi">,
4516 XD, EVEX_CD8<64, CD8VT1>;
4517 defm VCVTSD2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
4518 int_x86_avx512_cvtsd2usi64, sdmem,
4519 sse_load_f64, "cvtsd2usi">, XD, VEX_W,
4520 EVEX_CD8<64, CD8VT1>;
4522 let isCodeGenOnly = 1 in {
4523 defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
4524 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
4525 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
4526 defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
4527 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
4528 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
4529 defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
4530 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
4531 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
4532 defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
4533 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
4534 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
4536 defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
4537 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}",
4538 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
4539 } // isCodeGenOnly = 1
4541 // Convert float/double to signed/unsigned int 32/64 with truncation
4542 let isCodeGenOnly = 1 in {
4543 defm Int_VCVTTSS2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse_cvttss2si,
4544 ssmem, sse_load_f32, "cvttss2si">,
4545 XS, EVEX_CD8<32, CD8VT1>;
4546 defm Int_VCVTTSS2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
4547 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
4548 "cvttss2si">, XS, VEX_W,
4549 EVEX_CD8<32, CD8VT1>;
4550 defm Int_VCVTTSD2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse2_cvttsd2si,
4551 sdmem, sse_load_f64, "cvttsd2si">, XD,
4552 EVEX_CD8<64, CD8VT1>;
4553 defm Int_VCVTTSD2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
4554 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
4555 "cvttsd2si">, XD, VEX_W,
4556 EVEX_CD8<64, CD8VT1>;
4557 defm Int_VCVTTSS2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
4558 int_x86_avx512_cvttss2usi, ssmem, sse_load_f32,
4559 "cvttss2usi">, XS, EVEX_CD8<32, CD8VT1>;
4560 defm Int_VCVTTSS2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
4561 int_x86_avx512_cvttss2usi64, ssmem,
4562 sse_load_f32, "cvttss2usi">, XS, VEX_W,
4563 EVEX_CD8<32, CD8VT1>;
4564 defm Int_VCVTTSD2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
4565 int_x86_avx512_cvttsd2usi,
4566 sdmem, sse_load_f64, "cvttsd2usi">, XD,
4567 EVEX_CD8<64, CD8VT1>;
4568 defm Int_VCVTTSD2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
4569 int_x86_avx512_cvttsd2usi64, sdmem,
4570 sse_load_f64, "cvttsd2usi">, XD, VEX_W,
4571 EVEX_CD8<64, CD8VT1>;
4572 } // isCodeGenOnly = 1
4574 multiclass avx512_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
4575 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
4577 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
4578 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4579 [(set DstRC:$dst, (OpNode SrcRC:$src))]>, EVEX;
4580 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
4581 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4582 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>, EVEX;
4585 defm VCVTTSS2SIZ : avx512_cvt_s<0x2C, FR32X, GR32, fp_to_sint, f32mem,
4586 loadf32, "cvttss2si">, XS,
4587 EVEX_CD8<32, CD8VT1>;
4588 defm VCVTTSS2USIZ : avx512_cvt_s<0x78, FR32X, GR32, fp_to_uint, f32mem,
4589 loadf32, "cvttss2usi">, XS,
4590 EVEX_CD8<32, CD8VT1>;
4591 defm VCVTTSS2SI64Z : avx512_cvt_s<0x2C, FR32X, GR64, fp_to_sint, f32mem,
4592 loadf32, "cvttss2si">, XS, VEX_W,
4593 EVEX_CD8<32, CD8VT1>;
4594 defm VCVTTSS2USI64Z : avx512_cvt_s<0x78, FR32X, GR64, fp_to_uint, f32mem,
4595 loadf32, "cvttss2usi">, XS, VEX_W,
4596 EVEX_CD8<32, CD8VT1>;
4597 defm VCVTTSD2SIZ : avx512_cvt_s<0x2C, FR64X, GR32, fp_to_sint, f64mem,
4598 loadf64, "cvttsd2si">, XD,
4599 EVEX_CD8<64, CD8VT1>;
4600 defm VCVTTSD2USIZ : avx512_cvt_s<0x78, FR64X, GR32, fp_to_uint, f64mem,
4601 loadf64, "cvttsd2usi">, XD,
4602 EVEX_CD8<64, CD8VT1>;
4603 defm VCVTTSD2SI64Z : avx512_cvt_s<0x2C, FR64X, GR64, fp_to_sint, f64mem,
4604 loadf64, "cvttsd2si">, XD, VEX_W,
4605 EVEX_CD8<64, CD8VT1>;
4606 defm VCVTTSD2USI64Z : avx512_cvt_s<0x78, FR64X, GR64, fp_to_uint, f64mem,
4607 loadf64, "cvttsd2usi">, XD, VEX_W,
4608 EVEX_CD8<64, CD8VT1>;
4610 //===----------------------------------------------------------------------===//
4611 // AVX-512 Convert form float to double and back
4612 //===----------------------------------------------------------------------===//
4613 let hasSideEffects = 0 in {
4614 def VCVTSS2SDZrr : AVX512XSI<0x5A, MRMSrcReg, (outs FR64X:$dst),
4615 (ins FR32X:$src1, FR32X:$src2),
4616 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4617 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
4619 def VCVTSS2SDZrm : AVX512XSI<0x5A, MRMSrcMem, (outs FR64X:$dst),
4620 (ins FR32X:$src1, f32mem:$src2),
4621 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4622 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
4623 EVEX_CD8<32, CD8VT1>;
4625 // Convert scalar double to scalar single
4626 def VCVTSD2SSZrr : AVX512XDI<0x5A, MRMSrcReg, (outs FR32X:$dst),
4627 (ins FR64X:$src1, FR64X:$src2),
4628 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4629 []>, EVEX_4V, VEX_LIG, VEX_W, Sched<[WriteCvtF2F]>;
4631 def VCVTSD2SSZrm : AVX512XDI<0x5A, MRMSrcMem, (outs FR32X:$dst),
4632 (ins FR64X:$src1, f64mem:$src2),
4633 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4634 []>, EVEX_4V, VEX_LIG, VEX_W,
4635 Sched<[WriteCvtF2FLd, ReadAfterLd]>, EVEX_CD8<64, CD8VT1>;
4638 def : Pat<(f64 (fextend FR32X:$src)), (VCVTSS2SDZrr FR32X:$src, FR32X:$src)>,
4639 Requires<[HasAVX512]>;
4640 def : Pat<(fextend (loadf32 addr:$src)),
4641 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512]>;
4643 def : Pat<(extloadf32 addr:$src),
4644 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>,
4645 Requires<[HasAVX512, OptForSize]>;
4647 def : Pat<(extloadf32 addr:$src),
4648 (VCVTSS2SDZrr (f32 (IMPLICIT_DEF)), (VMOVSSZrm addr:$src))>,
4649 Requires<[HasAVX512, OptForSpeed]>;
4651 def : Pat<(f32 (fround FR64X:$src)), (VCVTSD2SSZrr FR64X:$src, FR64X:$src)>,
4652 Requires<[HasAVX512]>;
4654 //===----------------------------------------------------------------------===//
4655 // AVX-512 Vector convert from signed/unsigned integer to float/double
4656 // and from float/double to signed/unsigned integer
4657 //===----------------------------------------------------------------------===//
4659 multiclass avx512_vcvt_fp<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
4660 X86VectorVTInfo _Src, SDNode OpNode,
4661 string Broadcast = _.BroadcastStr,
4662 string Alias = ""> {
4664 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4665 (ins _Src.RC:$src), OpcodeStr, "$src", "$src",
4666 (_.VT (OpNode (_Src.VT _Src.RC:$src)))>, EVEX;
4668 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4669 (ins _Src.MemOp:$src), OpcodeStr#Alias, "$src", "$src",
4670 (_.VT (OpNode (_Src.VT
4671 (bitconvert (_Src.LdFrag addr:$src)))))>, EVEX;
4673 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4674 (ins _Src.MemOp:$src), OpcodeStr,
4675 "${src}"##Broadcast, "${src}"##Broadcast,
4676 (_.VT (OpNode (_Src.VT
4677 (X86VBroadcast (_Src.ScalarLdFrag addr:$src)))
4680 // Coversion with SAE - suppress all exceptions
4681 multiclass avx512_vcvt_fp_sae<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
4682 X86VectorVTInfo _Src, SDNode OpNodeRnd> {
4683 defm rrb : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4684 (ins _Src.RC:$src), OpcodeStr,
4685 "{sae}, $src", "$src, {sae}",
4686 (_.VT (OpNodeRnd (_Src.VT _Src.RC:$src),
4687 (i32 FROUND_NO_EXC)))>,
4691 // Conversion with rounding control (RC)
4692 multiclass avx512_vcvt_fp_rc<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
4693 X86VectorVTInfo _Src, SDNode OpNodeRnd> {
4694 defm rrb : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4695 (ins _Src.RC:$src, AVX512RC:$rc), OpcodeStr,
4696 "$rc, $src", "$src, $rc",
4697 (_.VT (OpNodeRnd (_Src.VT _Src.RC:$src), (i32 imm:$rc)))>,
4698 EVEX, EVEX_B, EVEX_RC;
4701 // Extend Float to Double
4702 multiclass avx512_cvtps2pd<bits<8> opc, string OpcodeStr> {
4703 let Predicates = [HasAVX512] in {
4704 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f64_info, v8f32x_info, fextend>,
4705 avx512_vcvt_fp_sae<opc, OpcodeStr, v8f64_info, v8f32x_info,
4706 X86vfpextRnd>, EVEX_V512;
4708 let Predicates = [HasVLX] in {
4709 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2f64x_info, v4f32x_info,
4710 X86vfpext, "{1to2}">, EVEX_V128;
4711 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f64x_info, v4f32x_info, fextend>,
4716 // Truncate Double to Float
4717 multiclass avx512_cvtpd2ps<bits<8> opc, string OpcodeStr> {
4718 let Predicates = [HasAVX512] in {
4719 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f32x_info, v8f64_info, fround>,
4720 avx512_vcvt_fp_rc<opc, OpcodeStr, v8f32x_info, v8f64_info,
4721 X86vfproundRnd>, EVEX_V512;
4723 let Predicates = [HasVLX] in {
4724 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v2f64x_info,
4725 X86vfpround, "{1to2}", "{x}">, EVEX_V128;
4726 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v4f64x_info, fround,
4727 "{1to4}", "{y}">, EVEX_V256;
4731 defm VCVTPD2PS : avx512_cvtpd2ps<0x5A, "vcvtpd2ps">,
4732 VEX_W, PD, EVEX_CD8<64, CD8VF>;
4733 defm VCVTPS2PD : avx512_cvtps2pd<0x5A, "vcvtps2pd">,
4734 PS, EVEX_CD8<32, CD8VH>;
4736 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
4737 (VCVTPS2PDZrm addr:$src)>;
4739 let Predicates = [HasVLX] in {
4740 def : Pat<(v4f64 (extloadv4f32 addr:$src)),
4741 (VCVTPS2PDZ256rm addr:$src)>;
4744 // Convert Signed/Unsigned Doubleword to Double
4745 multiclass avx512_cvtdq2pd<bits<8> opc, string OpcodeStr, SDNode OpNode,
4747 // No rounding in this op
4748 let Predicates = [HasAVX512] in
4749 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f64_info, v8i32x_info, OpNode>,
4752 let Predicates = [HasVLX] in {
4753 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2f64x_info, v4i32x_info,
4754 OpNode128, "{1to2}">, EVEX_V128;
4755 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f64x_info, v4i32x_info, OpNode>,
4760 // Convert Signed/Unsigned Doubleword to Float
4761 multiclass avx512_cvtdq2ps<bits<8> opc, string OpcodeStr, SDNode OpNode,
4763 let Predicates = [HasAVX512] in
4764 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v16f32_info, v16i32_info, OpNode>,
4765 avx512_vcvt_fp_rc<opc, OpcodeStr, v16f32_info, v16i32_info,
4766 OpNodeRnd>, EVEX_V512;
4768 let Predicates = [HasVLX] in {
4769 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v4i32x_info, OpNode>,
4771 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v8f32x_info, v8i32x_info, OpNode>,
4776 // Convert Float to Signed/Unsigned Doubleword with truncation
4777 multiclass avx512_cvttps2dq<bits<8> opc, string OpcodeStr,
4778 SDNode OpNode, SDNode OpNodeRnd> {
4779 let Predicates = [HasAVX512] in {
4780 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v16i32_info, v16f32_info, OpNode>,
4781 avx512_vcvt_fp_sae<opc, OpcodeStr, v16i32_info, v16f32_info,
4782 OpNodeRnd>, EVEX_V512;
4784 let Predicates = [HasVLX] in {
4785 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v4f32x_info, OpNode>,
4787 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v8i32x_info, v8f32x_info, OpNode>,
4792 // Convert Float to Signed/Unsigned Doubleword
4793 multiclass avx512_cvtps2dq<bits<8> opc, string OpcodeStr,
4794 SDNode OpNode, SDNode OpNodeRnd> {
4795 let Predicates = [HasAVX512] in {
4796 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v16i32_info, v16f32_info, OpNode>,
4797 avx512_vcvt_fp_rc<opc, OpcodeStr, v16i32_info, v16f32_info,
4798 OpNodeRnd>, EVEX_V512;
4800 let Predicates = [HasVLX] in {
4801 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v4f32x_info, OpNode>,
4803 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v8i32x_info, v8f32x_info, OpNode>,
4808 // Convert Double to Signed/Unsigned Doubleword with truncation
4809 multiclass avx512_cvttpd2dq<bits<8> opc, string OpcodeStr,
4810 SDNode OpNode, SDNode OpNodeRnd> {
4811 let Predicates = [HasAVX512] in {
4812 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i32x_info, v8f64_info, OpNode>,
4813 avx512_vcvt_fp_sae<opc, OpcodeStr, v8i32x_info, v8f64_info,
4814 OpNodeRnd>, EVEX_V512;
4816 let Predicates = [HasVLX] in {
4817 // we need "x"/"y" suffixes in order to distinguish between 128 and 256
4818 // memory forms of these instructions in Asm Parcer. They have the same
4819 // dest type - 'v4i32x_info'. We also specify the broadcast string explicitly
4820 // due to the same reason.
4821 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v2f64x_info, OpNode,
4822 "{1to2}", "{x}">, EVEX_V128;
4823 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v4f64x_info, OpNode,
4824 "{1to4}", "{y}">, EVEX_V256;
4828 // Convert Double to Signed/Unsigned Doubleword
4829 multiclass avx512_cvtpd2dq<bits<8> opc, string OpcodeStr,
4830 SDNode OpNode, SDNode OpNodeRnd> {
4831 let Predicates = [HasAVX512] in {
4832 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i32x_info, v8f64_info, OpNode>,
4833 avx512_vcvt_fp_rc<opc, OpcodeStr, v8i32x_info, v8f64_info,
4834 OpNodeRnd>, EVEX_V512;
4836 let Predicates = [HasVLX] in {
4837 // we need "x"/"y" suffixes in order to distinguish between 128 and 256
4838 // memory forms of these instructions in Asm Parcer. They have the same
4839 // dest type - 'v4i32x_info'. We also specify the broadcast string explicitly
4840 // due to the same reason.
4841 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v2f64x_info, OpNode,
4842 "{1to2}", "{x}">, EVEX_V128;
4843 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v4f64x_info, OpNode,
4844 "{1to4}", "{y}">, EVEX_V256;
4848 // Convert Double to Signed/Unsigned Quardword
4849 multiclass avx512_cvtpd2qq<bits<8> opc, string OpcodeStr,
4850 SDNode OpNode, SDNode OpNodeRnd> {
4851 let Predicates = [HasDQI] in {
4852 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i64_info, v8f64_info, OpNode>,
4853 avx512_vcvt_fp_rc<opc, OpcodeStr, v8i64_info, v8f64_info,
4854 OpNodeRnd>, EVEX_V512;
4856 let Predicates = [HasDQI, HasVLX] in {
4857 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2i64x_info, v2f64x_info, OpNode>,
4859 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i64x_info, v4f64x_info, OpNode>,
4864 // Convert Double to Signed/Unsigned Quardword with truncation
4865 multiclass avx512_cvttpd2qq<bits<8> opc, string OpcodeStr,
4866 SDNode OpNode, SDNode OpNodeRnd> {
4867 let Predicates = [HasDQI] in {
4868 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i64_info, v8f64_info, OpNode>,
4869 avx512_vcvt_fp_sae<opc, OpcodeStr, v8i64_info, v8f64_info,
4870 OpNodeRnd>, EVEX_V512;
4872 let Predicates = [HasDQI, HasVLX] in {
4873 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2i64x_info, v2f64x_info, OpNode>,
4875 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i64x_info, v4f64x_info, OpNode>,
4880 // Convert Signed/Unsigned Quardword to Double
4881 multiclass avx512_cvtqq2pd<bits<8> opc, string OpcodeStr,
4882 SDNode OpNode, SDNode OpNodeRnd> {
4883 let Predicates = [HasDQI] in {
4884 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f64_info, v8i64_info, OpNode>,
4885 avx512_vcvt_fp_rc<opc, OpcodeStr, v8f64_info, v8i64_info,
4886 OpNodeRnd>, EVEX_V512;
4888 let Predicates = [HasDQI, HasVLX] in {
4889 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2f64x_info, v2i64x_info, OpNode>,
4891 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f64x_info, v4i64x_info, OpNode>,
4896 // Convert Float to Signed/Unsigned Quardword
4897 multiclass avx512_cvtps2qq<bits<8> opc, string OpcodeStr,
4898 SDNode OpNode, SDNode OpNodeRnd> {
4899 let Predicates = [HasDQI] in {
4900 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i64_info, v8f32x_info, OpNode>,
4901 avx512_vcvt_fp_rc<opc, OpcodeStr, v8i64_info, v8f32x_info,
4902 OpNodeRnd>, EVEX_V512;
4904 let Predicates = [HasDQI, HasVLX] in {
4905 // Explicitly specified broadcast string, since we take only 2 elements
4906 // from v4f32x_info source
4907 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2i64x_info, v4f32x_info, OpNode,
4908 "{1to2}">, EVEX_V128;
4909 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i64x_info, v4f32x_info, OpNode>,
4914 // Convert Float to Signed/Unsigned Quardword with truncation
4915 multiclass avx512_cvttps2qq<bits<8> opc, string OpcodeStr,
4916 SDNode OpNode, SDNode OpNodeRnd> {
4917 let Predicates = [HasDQI] in {
4918 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i64_info, v8f32x_info, OpNode>,
4919 avx512_vcvt_fp_sae<opc, OpcodeStr, v8i64_info, v8f32x_info,
4920 OpNodeRnd>, EVEX_V512;
4922 let Predicates = [HasDQI, HasVLX] in {
4923 // Explicitly specified broadcast string, since we take only 2 elements
4924 // from v4f32x_info source
4925 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2i64x_info, v4f32x_info, OpNode,
4926 "{1to2}">, EVEX_V128;
4927 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i64x_info, v4f32x_info, OpNode>,
4932 // Convert Signed/Unsigned Quardword to Float
4933 multiclass avx512_cvtqq2ps<bits<8> opc, string OpcodeStr,
4934 SDNode OpNode, SDNode OpNodeRnd> {
4935 let Predicates = [HasDQI] in {
4936 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f32x_info, v8i64_info, OpNode>,
4937 avx512_vcvt_fp_rc<opc, OpcodeStr, v8f32x_info, v8i64_info,
4938 OpNodeRnd>, EVEX_V512;
4940 let Predicates = [HasDQI, HasVLX] in {
4941 // we need "x"/"y" suffixes in order to distinguish between 128 and 256
4942 // memory forms of these instructions in Asm Parcer. They have the same
4943 // dest type - 'v4i32x_info'. We also specify the broadcast string explicitly
4944 // due to the same reason.
4945 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v2i64x_info, OpNode,
4946 "{1to2}", "{x}">, EVEX_V128;
4947 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v4i64x_info, OpNode,
4948 "{1to4}", "{y}">, EVEX_V256;
4952 defm VCVTDQ2PD : avx512_cvtdq2pd<0xE6, "vcvtdq2pd", sint_to_fp, X86cvtdq2pd>, XS,
4953 EVEX_CD8<32, CD8VH>;
4955 defm VCVTDQ2PS : avx512_cvtdq2ps<0x5B, "vcvtdq2ps", sint_to_fp,
4957 PS, EVEX_CD8<32, CD8VF>;
4959 defm VCVTTPS2DQ : avx512_cvttps2dq<0x5B, "vcvttps2dq", fp_to_sint,
4961 XS, EVEX_CD8<32, CD8VF>;
4963 defm VCVTTPD2DQ : avx512_cvttpd2dq<0xE6, "vcvttpd2dq", fp_to_sint,
4965 PD, VEX_W, EVEX_CD8<64, CD8VF>;
4967 defm VCVTTPS2UDQ : avx512_cvttps2dq<0x78, "vcvttps2udq", fp_to_uint,
4968 X86VFpToUintRnd>, PS,
4969 EVEX_CD8<32, CD8VF>;
4971 defm VCVTTPD2UDQ : avx512_cvttpd2dq<0x78, "vcvttpd2udq", fp_to_uint,
4972 X86VFpToUintRnd>, PS, VEX_W,
4973 EVEX_CD8<64, CD8VF>;
4975 defm VCVTUDQ2PD : avx512_cvtdq2pd<0x7A, "vcvtudq2pd", uint_to_fp, X86cvtudq2pd>,
4976 XS, EVEX_CD8<32, CD8VH>;
4978 defm VCVTUDQ2PS : avx512_cvtdq2ps<0x7A, "vcvtudq2ps", uint_to_fp,
4979 X86VUintToFpRnd>, XD,
4980 EVEX_CD8<32, CD8VF>;
4982 defm VCVTPS2DQ : avx512_cvtps2dq<0x5B, "vcvtps2dq", X86cvtps2Int,
4983 X86cvtps2IntRnd>, PD, EVEX_CD8<32, CD8VF>;
4985 defm VCVTPD2DQ : avx512_cvtpd2dq<0xE6, "vcvtpd2dq", X86cvtpd2Int,
4986 X86cvtpd2IntRnd>, XD, VEX_W,
4987 EVEX_CD8<64, CD8VF>;
4989 defm VCVTPS2UDQ : avx512_cvtps2dq<0x79, "vcvtps2udq", X86cvtps2UInt,
4991 PS, EVEX_CD8<32, CD8VF>;
4992 defm VCVTPD2UDQ : avx512_cvtpd2dq<0x79, "vcvtpd2udq", X86cvtpd2UInt,
4993 X86cvtpd2UIntRnd>, VEX_W,
4994 PS, EVEX_CD8<64, CD8VF>;
4996 defm VCVTPD2QQ : avx512_cvtpd2qq<0x7B, "vcvtpd2qq", X86cvtpd2Int,
4997 X86cvtpd2IntRnd>, VEX_W,
4998 PD, EVEX_CD8<64, CD8VF>;
5000 defm VCVTPS2QQ : avx512_cvtps2qq<0x7B, "vcvtps2qq", X86cvtps2Int,
5001 X86cvtps2IntRnd>, PD, EVEX_CD8<32, CD8VH>;
5003 defm VCVTPD2UQQ : avx512_cvtpd2qq<0x79, "vcvtpd2uqq", X86cvtpd2UInt,
5004 X86cvtpd2UIntRnd>, VEX_W,
5005 PD, EVEX_CD8<64, CD8VF>;
5007 defm VCVTPS2UQQ : avx512_cvtps2qq<0x79, "vcvtps2uqq", X86cvtps2UInt,
5008 X86cvtps2UIntRnd>, PD, EVEX_CD8<32, CD8VH>;
5010 defm VCVTTPD2QQ : avx512_cvttpd2qq<0x7A, "vcvttpd2qq", fp_to_sint,
5011 X86VFpToSlongRnd>, VEX_W,
5012 PD, EVEX_CD8<64, CD8VF>;
5014 defm VCVTTPS2QQ : avx512_cvttps2qq<0x7A, "vcvttps2qq", fp_to_sint,
5015 X86VFpToSlongRnd>, PD, EVEX_CD8<32, CD8VH>;
5017 defm VCVTTPD2UQQ : avx512_cvttpd2qq<0x78, "vcvttpd2uqq", fp_to_uint,
5018 X86VFpToUlongRnd>, VEX_W,
5019 PD, EVEX_CD8<64, CD8VF>;
5021 defm VCVTTPS2UQQ : avx512_cvttps2qq<0x78, "vcvttps2uqq", fp_to_uint,
5022 X86VFpToUlongRnd>, PD, EVEX_CD8<32, CD8VH>;
5024 defm VCVTQQ2PD : avx512_cvtqq2pd<0xE6, "vcvtqq2pd", sint_to_fp,
5025 X86VSlongToFpRnd>, VEX_W, XS, EVEX_CD8<64, CD8VF>;
5027 defm VCVTUQQ2PD : avx512_cvtqq2pd<0x7A, "vcvtuqq2pd", uint_to_fp,
5028 X86VUlongToFpRnd>, VEX_W, XS, EVEX_CD8<64, CD8VF>;
5030 defm VCVTQQ2PS : avx512_cvtqq2ps<0x5B, "vcvtqq2ps", sint_to_fp,
5031 X86VSlongToFpRnd>, VEX_W, PS, EVEX_CD8<64, CD8VF>;
5033 defm VCVTUQQ2PS : avx512_cvtqq2ps<0x7A, "vcvtuqq2ps", uint_to_fp,
5034 X86VUlongToFpRnd>, VEX_W, XD, EVEX_CD8<64, CD8VF>;
5036 let Predicates = [NoVLX] in {
5037 def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
5038 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
5039 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
5041 def : Pat<(v4i32 (fp_to_uint (v4f32 VR128X:$src1))),
5042 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
5043 (v16f32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
5045 def : Pat<(v8f32 (uint_to_fp (v8i32 VR256X:$src1))),
5046 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
5047 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
5049 def : Pat<(v4f32 (uint_to_fp (v4i32 VR128X:$src1))),
5050 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
5051 (v16i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
5053 def : Pat<(v4f64 (uint_to_fp (v4i32 VR128X:$src1))),
5054 (EXTRACT_SUBREG (v8f64 (VCVTUDQ2PDZrr
5055 (v8i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_ymm)>;
5058 let Predicates = [HasAVX512] in {
5059 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
5060 (VCVTPD2PSZrm addr:$src)>;
5061 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
5062 (VCVTPS2PDZrm addr:$src)>;
5065 //===----------------------------------------------------------------------===//
5066 // Half precision conversion instructions
5067 //===----------------------------------------------------------------------===//
5068 multiclass avx512_cvtph2ps<RegisterClass destRC, RegisterClass srcRC,
5069 X86MemOperand x86memop> {
5070 def rr : AVX5128I<0x13, MRMSrcReg, (outs destRC:$dst), (ins srcRC:$src),
5071 "vcvtph2ps\t{$src, $dst|$dst, $src}",
5073 let hasSideEffects = 0, mayLoad = 1 in
5074 def rm : AVX5128I<0x13, MRMSrcMem, (outs destRC:$dst), (ins x86memop:$src),
5075 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, EVEX;
5078 multiclass avx512_cvtps2ph<RegisterClass destRC, RegisterClass srcRC,
5079 X86MemOperand x86memop> {
5080 def rr : AVX512AIi8<0x1D, MRMDestReg, (outs destRC:$dst),
5081 (ins srcRC:$src1, i32u8imm:$src2),
5082 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5084 let hasSideEffects = 0, mayStore = 1 in
5085 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
5086 (ins x86memop:$dst, srcRC:$src1, i32u8imm:$src2),
5087 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, EVEX;
5090 defm VCVTPH2PSZ : avx512_cvtph2ps<VR512, VR256X, f256mem>, EVEX_V512,
5091 EVEX_CD8<32, CD8VH>;
5092 defm VCVTPS2PHZ : avx512_cvtps2ph<VR256X, VR512, f256mem>, EVEX_V512,
5093 EVEX_CD8<32, CD8VH>;
5095 def : Pat<(v16i16 (int_x86_avx512_mask_vcvtps2ph_512 (v16f32 VR512:$src),
5096 imm:$rc, (bc_v16i16(v8i32 immAllZerosV)), (i16 -1))),
5097 (VCVTPS2PHZrr VR512:$src, imm:$rc)>;
5099 def : Pat<(v16f32 (int_x86_avx512_mask_vcvtph2ps_512 (v16i16 VR256X:$src),
5100 (bc_v16f32(v16i32 immAllZerosV)), (i16 -1), (i32 FROUND_CURRENT))),
5101 (VCVTPH2PSZrr VR256X:$src)>;
5103 let Defs = [EFLAGS], Predicates = [HasAVX512] in {
5104 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
5105 "ucomiss">, PS, EVEX, VEX_LIG,
5106 EVEX_CD8<32, CD8VT1>;
5107 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
5108 "ucomisd">, PD, EVEX,
5109 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
5110 let Pattern = []<dag> in {
5111 defm VCOMISSZ : sse12_ord_cmp<0x2F, FR32X, undef, f32, f32mem, loadf32,
5112 "comiss">, PS, EVEX, VEX_LIG,
5113 EVEX_CD8<32, CD8VT1>;
5114 defm VCOMISDZ : sse12_ord_cmp<0x2F, FR64X, undef, f64, f64mem, loadf64,
5115 "comisd">, PD, EVEX,
5116 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
5118 let isCodeGenOnly = 1 in {
5119 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
5120 load, "ucomiss">, PS, EVEX, VEX_LIG,
5121 EVEX_CD8<32, CD8VT1>;
5122 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
5123 load, "ucomisd">, PD, EVEX,
5124 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
5126 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
5127 load, "comiss">, PS, EVEX, VEX_LIG,
5128 EVEX_CD8<32, CD8VT1>;
5129 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
5130 load, "comisd">, PD, EVEX,
5131 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
5135 /// avx512_fp14_s rcp14ss, rcp14sd, rsqrt14ss, rsqrt14sd
5136 multiclass avx512_fp14_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
5137 X86MemOperand x86memop> {
5138 let hasSideEffects = 0 in {
5139 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
5140 (ins RC:$src1, RC:$src2),
5141 !strconcat(OpcodeStr,
5142 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
5143 let mayLoad = 1 in {
5144 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5145 (ins RC:$src1, x86memop:$src2),
5146 !strconcat(OpcodeStr,
5147 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
5152 defm VRCP14SS : avx512_fp14_s<0x4D, "vrcp14ss", FR32X, f32mem>,
5153 EVEX_CD8<32, CD8VT1>;
5154 defm VRCP14SD : avx512_fp14_s<0x4D, "vrcp14sd", FR64X, f64mem>,
5155 VEX_W, EVEX_CD8<64, CD8VT1>;
5156 defm VRSQRT14SS : avx512_fp14_s<0x4F, "vrsqrt14ss", FR32X, f32mem>,
5157 EVEX_CD8<32, CD8VT1>;
5158 defm VRSQRT14SD : avx512_fp14_s<0x4F, "vrsqrt14sd", FR64X, f64mem>,
5159 VEX_W, EVEX_CD8<64, CD8VT1>;
5161 def : Pat <(v4f32 (int_x86_avx512_rcp14_ss (v4f32 VR128X:$src1),
5162 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
5163 (COPY_TO_REGCLASS (VRCP14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
5164 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
5166 def : Pat <(v2f64 (int_x86_avx512_rcp14_sd (v2f64 VR128X:$src1),
5167 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
5168 (COPY_TO_REGCLASS (VRCP14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
5169 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
5171 def : Pat <(v4f32 (int_x86_avx512_rsqrt14_ss (v4f32 VR128X:$src1),
5172 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
5173 (COPY_TO_REGCLASS (VRSQRT14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
5174 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
5176 def : Pat <(v2f64 (int_x86_avx512_rsqrt14_sd (v2f64 VR128X:$src1),
5177 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
5178 (COPY_TO_REGCLASS (VRSQRT14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
5179 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
5181 /// avx512_fp14_p rcp14ps, rcp14pd, rsqrt14ps, rsqrt14pd
5182 multiclass avx512_fp14_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
5183 X86VectorVTInfo _> {
5184 defm r: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5185 (ins _.RC:$src), OpcodeStr, "$src", "$src",
5186 (_.FloatVT (OpNode _.RC:$src))>, EVEX, T8PD;
5187 let mayLoad = 1 in {
5188 defm m: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5189 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
5191 (bitconvert (_.LdFrag addr:$src))))>, EVEX, T8PD;
5192 defm mb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5193 (ins _.ScalarMemOp:$src), OpcodeStr,
5194 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
5196 (X86VBroadcast (_.ScalarLdFrag addr:$src))))>,
5201 multiclass avx512_fp14_p_vl_all<bits<8> opc, string OpcodeStr, SDNode OpNode> {
5202 defm PSZ : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"), OpNode, v16f32_info>,
5203 EVEX_V512, EVEX_CD8<32, CD8VF>;
5204 defm PDZ : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"), OpNode, v8f64_info>,
5205 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
5207 // Define only if AVX512VL feature is present.
5208 let Predicates = [HasVLX] in {
5209 defm PSZ128 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"),
5210 OpNode, v4f32x_info>,
5211 EVEX_V128, EVEX_CD8<32, CD8VF>;
5212 defm PSZ256 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"),
5213 OpNode, v8f32x_info>,
5214 EVEX_V256, EVEX_CD8<32, CD8VF>;
5215 defm PDZ128 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"),
5216 OpNode, v2f64x_info>,
5217 EVEX_V128, VEX_W, EVEX_CD8<64, CD8VF>;
5218 defm PDZ256 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"),
5219 OpNode, v4f64x_info>,
5220 EVEX_V256, VEX_W, EVEX_CD8<64, CD8VF>;
5224 defm VRSQRT14 : avx512_fp14_p_vl_all<0x4E, "vrsqrt14", X86frsqrt>;
5225 defm VRCP14 : avx512_fp14_p_vl_all<0x4C, "vrcp14", X86frcp>;
5227 def : Pat <(v16f32 (int_x86_avx512_rsqrt14_ps_512 (v16f32 VR512:$src),
5228 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
5229 (VRSQRT14PSZr VR512:$src)>;
5230 def : Pat <(v8f64 (int_x86_avx512_rsqrt14_pd_512 (v8f64 VR512:$src),
5231 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
5232 (VRSQRT14PDZr VR512:$src)>;
5234 def : Pat <(v16f32 (int_x86_avx512_rcp14_ps_512 (v16f32 VR512:$src),
5235 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
5236 (VRCP14PSZr VR512:$src)>;
5237 def : Pat <(v8f64 (int_x86_avx512_rcp14_pd_512 (v8f64 VR512:$src),
5238 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
5239 (VRCP14PDZr VR512:$src)>;
5241 /// avx512_fp28_s rcp28ss, rcp28sd, rsqrt28ss, rsqrt28sd
5242 multiclass avx512_fp28_s<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
5245 defm r : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5246 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
5247 "$src2, $src1", "$src1, $src2",
5248 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
5249 (i32 FROUND_CURRENT))>;
5251 defm rb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5252 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
5253 "{sae}, $src2, $src1", "$src1, $src2, {sae}",
5254 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
5255 (i32 FROUND_NO_EXC))>, EVEX_B;
5257 defm m : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
5258 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
5259 "$src2, $src1", "$src1, $src2",
5260 (OpNode (_.VT _.RC:$src1),
5261 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
5262 (i32 FROUND_CURRENT))>;
5265 multiclass avx512_eri_s<bits<8> opc, string OpcodeStr, SDNode OpNode> {
5266 defm SS : avx512_fp28_s<opc, OpcodeStr#"ss", f32x_info, OpNode>,
5267 EVEX_CD8<32, CD8VT1>;
5268 defm SD : avx512_fp28_s<opc, OpcodeStr#"sd", f64x_info, OpNode>,
5269 EVEX_CD8<64, CD8VT1>, VEX_W;
5272 let hasSideEffects = 0, Predicates = [HasERI] in {
5273 defm VRCP28 : avx512_eri_s<0xCB, "vrcp28", X86rcp28s>, T8PD, EVEX_4V;
5274 defm VRSQRT28 : avx512_eri_s<0xCD, "vrsqrt28", X86rsqrt28s>, T8PD, EVEX_4V;
5277 defm VGETEXP : avx512_eri_s<0x43, "vgetexp", X86fgetexpRnds>, T8PD, EVEX_4V;
5278 /// avx512_fp28_p rcp28ps, rcp28pd, rsqrt28ps, rsqrt28pd
5280 multiclass avx512_fp28_p<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5283 defm r : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5284 (ins _.RC:$src), OpcodeStr, "$src", "$src",
5285 (OpNode (_.VT _.RC:$src), (i32 FROUND_CURRENT))>;
5287 defm m : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5288 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
5290 (bitconvert (_.LdFrag addr:$src))),
5291 (i32 FROUND_CURRENT))>;
5293 defm mb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5294 (ins _.MemOp:$src), OpcodeStr,
5295 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
5297 (X86VBroadcast (_.ScalarLdFrag addr:$src))),
5298 (i32 FROUND_CURRENT))>, EVEX_B;
5300 multiclass avx512_fp28_p_round<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5302 defm rb : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5303 (ins _.RC:$src), OpcodeStr,
5304 "{sae}, $src", "$src, {sae}",
5305 (OpNode (_.VT _.RC:$src), (i32 FROUND_NO_EXC))>, EVEX_B;
5308 multiclass avx512_eri<bits<8> opc, string OpcodeStr, SDNode OpNode> {
5309 defm PS : avx512_fp28_p<opc, OpcodeStr#"ps", v16f32_info, OpNode>,
5310 avx512_fp28_p_round<opc, OpcodeStr#"ps", v16f32_info, OpNode>,
5311 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
5312 defm PD : avx512_fp28_p<opc, OpcodeStr#"pd", v8f64_info, OpNode>,
5313 avx512_fp28_p_round<opc, OpcodeStr#"pd", v8f64_info, OpNode>,
5314 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
5317 multiclass avx512_fp_unaryop_packed<bits<8> opc, string OpcodeStr,
5319 // Define only if AVX512VL feature is present.
5320 let Predicates = [HasVLX] in {
5321 defm PSZ128 : avx512_fp28_p<opc, OpcodeStr#"ps", v4f32x_info, OpNode>,
5322 EVEX_V128, T8PD, EVEX_CD8<32, CD8VF>;
5323 defm PSZ256 : avx512_fp28_p<opc, OpcodeStr#"ps", v8f32x_info, OpNode>,
5324 EVEX_V256, T8PD, EVEX_CD8<32, CD8VF>;
5325 defm PDZ128 : avx512_fp28_p<opc, OpcodeStr#"pd", v2f64x_info, OpNode>,
5326 EVEX_V128, VEX_W, T8PD, EVEX_CD8<64, CD8VF>;
5327 defm PDZ256 : avx512_fp28_p<opc, OpcodeStr#"pd", v4f64x_info, OpNode>,
5328 EVEX_V256, VEX_W, T8PD, EVEX_CD8<64, CD8VF>;
5331 let Predicates = [HasERI], hasSideEffects = 0 in {
5333 defm VRSQRT28 : avx512_eri<0xCC, "vrsqrt28", X86rsqrt28>, EVEX;
5334 defm VRCP28 : avx512_eri<0xCA, "vrcp28", X86rcp28>, EVEX;
5335 defm VEXP2 : avx512_eri<0xC8, "vexp2", X86exp2>, EVEX;
5337 defm VGETEXP : avx512_eri<0x42, "vgetexp", X86fgetexpRnd>,
5338 avx512_fp_unaryop_packed<0x42, "vgetexp", X86fgetexpRnd> , EVEX;
5340 multiclass avx512_sqrt_packed_round<bits<8> opc, string OpcodeStr,
5341 SDNode OpNodeRnd, X86VectorVTInfo _>{
5342 defm rb: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5343 (ins _.RC:$src, AVX512RC:$rc), OpcodeStr, "$rc, $src", "$src, $rc",
5344 (_.VT (OpNodeRnd _.RC:$src, (i32 imm:$rc)))>,
5345 EVEX, EVEX_B, EVEX_RC;
5348 multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr,
5349 SDNode OpNode, X86VectorVTInfo _>{
5350 defm r: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5351 (ins _.RC:$src), OpcodeStr, "$src", "$src",
5352 (_.FloatVT (OpNode _.RC:$src))>, EVEX;
5353 let mayLoad = 1 in {
5354 defm m: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5355 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
5357 (bitconvert (_.LdFrag addr:$src))))>, EVEX;
5359 defm mb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5360 (ins _.ScalarMemOp:$src), OpcodeStr,
5361 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
5363 (X86VBroadcast (_.ScalarLdFrag addr:$src))))>,
5368 multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,
5369 Intrinsic F32Int, Intrinsic F64Int,
5370 OpndItins itins_s, OpndItins itins_d> {
5371 def SSZr : SI<opc, MRMSrcReg, (outs FR32X:$dst),
5372 (ins FR32X:$src1, FR32X:$src2),
5373 !strconcat(OpcodeStr,
5374 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5375 [], itins_s.rr>, XS, EVEX_4V;
5376 let isCodeGenOnly = 1 in
5377 def SSZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
5378 (ins VR128X:$src1, VR128X:$src2),
5379 !strconcat(OpcodeStr,
5380 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5382 (F32Int VR128X:$src1, VR128X:$src2))],
5383 itins_s.rr>, XS, EVEX_4V;
5384 let mayLoad = 1 in {
5385 def SSZm : SI<opc, MRMSrcMem, (outs FR32X:$dst),
5386 (ins FR32X:$src1, f32mem:$src2),
5387 !strconcat(OpcodeStr,
5388 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5389 [], itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
5390 let isCodeGenOnly = 1 in
5391 def SSZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
5392 (ins VR128X:$src1, ssmem:$src2),
5393 !strconcat(OpcodeStr,
5394 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5396 (F32Int VR128X:$src1, sse_load_f32:$src2))],
5397 itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
5399 def SDZr : SI<opc, MRMSrcReg, (outs FR64X:$dst),
5400 (ins FR64X:$src1, FR64X:$src2),
5401 !strconcat(OpcodeStr,
5402 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
5404 let isCodeGenOnly = 1 in
5405 def SDZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
5406 (ins VR128X:$src1, VR128X:$src2),
5407 !strconcat(OpcodeStr,
5408 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5410 (F64Int VR128X:$src1, VR128X:$src2))],
5411 itins_s.rr>, XD, EVEX_4V, VEX_W;
5412 let mayLoad = 1 in {
5413 def SDZm : SI<opc, MRMSrcMem, (outs FR64X:$dst),
5414 (ins FR64X:$src1, f64mem:$src2),
5415 !strconcat(OpcodeStr,
5416 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
5417 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
5418 let isCodeGenOnly = 1 in
5419 def SDZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
5420 (ins VR128X:$src1, sdmem:$src2),
5421 !strconcat(OpcodeStr,
5422 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5424 (F64Int VR128X:$src1, sse_load_f64:$src2))]>,
5425 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
5429 multiclass avx512_sqrt_packed_all<bits<8> opc, string OpcodeStr,
5431 defm PSZ : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
5433 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
5434 defm PDZ : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
5436 EVEX_V512, VEX_W, PD, EVEX_CD8<64, CD8VF>;
5437 // Define only if AVX512VL feature is present.
5438 let Predicates = [HasVLX] in {
5439 defm PSZ128 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"),
5440 OpNode, v4f32x_info>,
5441 EVEX_V128, PS, EVEX_CD8<32, CD8VF>;
5442 defm PSZ256 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"),
5443 OpNode, v8f32x_info>,
5444 EVEX_V256, PS, EVEX_CD8<32, CD8VF>;
5445 defm PDZ128 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"),
5446 OpNode, v2f64x_info>,
5447 EVEX_V128, VEX_W, PD, EVEX_CD8<64, CD8VF>;
5448 defm PDZ256 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"),
5449 OpNode, v4f64x_info>,
5450 EVEX_V256, VEX_W, PD, EVEX_CD8<64, CD8VF>;
5454 multiclass avx512_sqrt_packed_all_round<bits<8> opc, string OpcodeStr,
5456 defm PSZ : avx512_sqrt_packed_round<opc, !strconcat(OpcodeStr, "ps"), OpNodeRnd,
5457 v16f32_info>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
5458 defm PDZ : avx512_sqrt_packed_round<opc, !strconcat(OpcodeStr, "pd"), OpNodeRnd,
5459 v8f64_info>, EVEX_V512, VEX_W, PD, EVEX_CD8<64, CD8VF>;
5462 defm VSQRT : avx512_sqrt_packed_all<0x51, "vsqrt", fsqrt>,
5463 avx512_sqrt_packed_all_round<0x51, "vsqrt", X86fsqrtRnd>;
5465 defm VSQRT : avx512_sqrt_scalar<0x51, "sqrt",
5466 int_x86_avx512_sqrt_ss, int_x86_avx512_sqrt_sd,
5467 SSE_SQRTSS, SSE_SQRTSD>;
5469 let Predicates = [HasAVX512] in {
5470 def : Pat<(f32 (fsqrt FR32X:$src)),
5471 (VSQRTSSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
5472 def : Pat<(f32 (fsqrt (load addr:$src))),
5473 (VSQRTSSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
5474 Requires<[OptForSize]>;
5475 def : Pat<(f64 (fsqrt FR64X:$src)),
5476 (VSQRTSDZr (f64 (IMPLICIT_DEF)), FR64X:$src)>;
5477 def : Pat<(f64 (fsqrt (load addr:$src))),
5478 (VSQRTSDZm (f64 (IMPLICIT_DEF)), addr:$src)>,
5479 Requires<[OptForSize]>;
5481 def : Pat<(f32 (X86frsqrt FR32X:$src)),
5482 (VRSQRT14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
5483 def : Pat<(f32 (X86frsqrt (load addr:$src))),
5484 (VRSQRT14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
5485 Requires<[OptForSize]>;
5487 def : Pat<(f32 (X86frcp FR32X:$src)),
5488 (VRCP14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
5489 def : Pat<(f32 (X86frcp (load addr:$src))),
5490 (VRCP14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
5491 Requires<[OptForSize]>;
5493 def : Pat<(int_x86_sse_sqrt_ss VR128X:$src),
5494 (COPY_TO_REGCLASS (VSQRTSSZr (f32 (IMPLICIT_DEF)),
5495 (COPY_TO_REGCLASS VR128X:$src, FR32)),
5497 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
5498 (VSQRTSSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
5500 def : Pat<(int_x86_sse2_sqrt_sd VR128X:$src),
5501 (COPY_TO_REGCLASS (VSQRTSDZr (f64 (IMPLICIT_DEF)),
5502 (COPY_TO_REGCLASS VR128X:$src, FR64)),
5504 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
5505 (VSQRTSDZm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
5509 avx512_rndscale_scalar<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
5511 let ExeDomain = _.ExeDomain in {
5512 defm r : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5513 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3), OpcodeStr,
5514 "$src3, $src2, $src1", "$src1, $src2, $src3",
5515 (_.VT (X86RndScales (_.VT _.RC:$src1), (_.VT _.RC:$src2),
5516 (i32 imm:$src3), (i32 FROUND_CURRENT)))>;
5518 defm rb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5519 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3), OpcodeStr,
5520 "$src3, {sae}, $src2, $src1", "$src1, $src2, {sae}, $src3",
5521 (_.VT (X86RndScales (_.VT _.RC:$src1), (_.VT _.RC:$src2),
5522 (i32 imm:$src3), (i32 FROUND_NO_EXC)))>, EVEX_B;
5525 defm m : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
5526 (ins _.RC:$src1, _.MemOp:$src2, i32u8imm:$src3), OpcodeStr,
5527 "$src3, $src2, $src1", "$src1, $src2, $src3",
5528 (_.VT (X86RndScales (_.VT _.RC:$src1),
5529 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
5530 (i32 imm:$src3), (i32 FROUND_CURRENT)))>;
5532 let Predicates = [HasAVX512] in {
5533 def : Pat<(ffloor _.FRC:$src), (COPY_TO_REGCLASS
5534 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5535 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x1))), _.FRC)>;
5536 def : Pat<(fceil _.FRC:$src), (COPY_TO_REGCLASS
5537 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5538 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x2))), _.FRC)>;
5539 def : Pat<(ftrunc _.FRC:$src), (COPY_TO_REGCLASS
5540 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5541 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x3))), _.FRC)>;
5542 def : Pat<(frint _.FRC:$src), (COPY_TO_REGCLASS
5543 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5544 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x4))), _.FRC)>;
5545 def : Pat<(fnearbyint _.FRC:$src), (COPY_TO_REGCLASS
5546 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5547 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0xc))), _.FRC)>;
5549 def : Pat<(ffloor (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
5550 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
5551 addr:$src, (i32 0x1))), _.FRC)>;
5552 def : Pat<(fceil (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
5553 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
5554 addr:$src, (i32 0x2))), _.FRC)>;
5555 def : Pat<(ftrunc (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
5556 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
5557 addr:$src, (i32 0x3))), _.FRC)>;
5558 def : Pat<(frint (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
5559 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
5560 addr:$src, (i32 0x4))), _.FRC)>;
5561 def : Pat<(fnearbyint (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
5562 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
5563 addr:$src, (i32 0xc))), _.FRC)>;
5567 defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", f32x_info>,
5568 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VT1>;
5570 defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", f64x_info>, VEX_W,
5571 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VT1>;
5573 //-------------------------------------------------
5574 // Integer truncate and extend operations
5575 //-------------------------------------------------
5577 multiclass avx512_trunc_common<bits<8> opc, string OpcodeStr, SDNode OpNode,
5578 X86VectorVTInfo SrcInfo, X86VectorVTInfo DestInfo,
5579 X86MemOperand x86memop> {
5581 defm rr : AVX512_maskable<opc, MRMDestReg, DestInfo, (outs DestInfo.RC:$dst),
5582 (ins SrcInfo.RC:$src1), OpcodeStr ,"$src1", "$src1",
5583 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1)))>,
5586 // for intrinsic patter match
5587 def : Pat<(DestInfo.VT (X86select DestInfo.KRCWM:$mask,
5588 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1))),
5590 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##rrkz) DestInfo.KRCWM:$mask ,
5593 def : Pat<(DestInfo.VT (X86select DestInfo.KRCWM:$mask,
5594 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1))),
5595 DestInfo.ImmAllZerosV)),
5596 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##rrkz) DestInfo.KRCWM:$mask ,
5599 def : Pat<(DestInfo.VT (X86select DestInfo.KRCWM:$mask,
5600 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1))),
5601 DestInfo.RC:$src0)),
5602 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##rrk) DestInfo.RC:$src0,
5603 DestInfo.KRCWM:$mask ,
5606 let mayStore = 1 in {
5607 def mr : AVX512XS8I<opc, MRMDestMem, (outs),
5608 (ins x86memop:$dst, SrcInfo.RC:$src),
5609 OpcodeStr # "\t{$src, $dst |$dst, $src}",
5612 def mrk : AVX512XS8I<opc, MRMDestMem, (outs),
5613 (ins x86memop:$dst, SrcInfo.KRCWM:$mask, SrcInfo.RC:$src),
5614 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
5619 multiclass avx512_trunc_mr_lowering<X86VectorVTInfo SrcInfo,
5620 X86VectorVTInfo DestInfo,
5621 PatFrag truncFrag, PatFrag mtruncFrag > {
5623 def : Pat<(truncFrag (SrcInfo.VT SrcInfo.RC:$src), addr:$dst),
5624 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##mr)
5625 addr:$dst, SrcInfo.RC:$src)>;
5627 def : Pat<(mtruncFrag addr:$dst, SrcInfo.KRCWM:$mask,
5628 (SrcInfo.VT SrcInfo.RC:$src)),
5629 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##mrk)
5630 addr:$dst, SrcInfo.KRCWM:$mask, SrcInfo.RC:$src)>;
5633 multiclass avx512_trunc_sat_mr_lowering<X86VectorVTInfo SrcInfo,
5634 X86VectorVTInfo DestInfo, string sat > {
5636 def: Pat<(!cast<Intrinsic>("int_x86_avx512_mask_pmov"#sat#"_"#SrcInfo.Suffix#
5637 DestInfo.Suffix#"_mem_"#SrcInfo.Size)
5638 addr:$ptr, (SrcInfo.VT SrcInfo.RC:$src), SrcInfo.MRC:$mask),
5639 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##mrk) addr:$ptr,
5640 (COPY_TO_REGCLASS SrcInfo.MRC:$mask, SrcInfo.KRCWM),
5641 (SrcInfo.VT SrcInfo.RC:$src))>;
5643 def: Pat<(!cast<Intrinsic>("int_x86_avx512_mask_pmov"#sat#"_"#SrcInfo.Suffix#
5644 DestInfo.Suffix#"_mem_"#SrcInfo.Size)
5645 addr:$ptr, (SrcInfo.VT SrcInfo.RC:$src), -1),
5646 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##mr) addr:$ptr,
5647 (SrcInfo.VT SrcInfo.RC:$src))>;
5650 multiclass avx512_trunc<bits<8> opc, string OpcodeStr, SDNode OpNode,
5651 AVX512VLVectorVTInfo VTSrcInfo, X86VectorVTInfo DestInfoZ128,
5652 X86VectorVTInfo DestInfoZ256, X86VectorVTInfo DestInfoZ,
5653 X86MemOperand x86memopZ128, X86MemOperand x86memopZ256,
5654 X86MemOperand x86memopZ, PatFrag truncFrag, PatFrag mtruncFrag,
5655 Predicate prd = HasAVX512>{
5657 let Predicates = [HasVLX, prd] in {
5658 defm Z128: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info128,
5659 DestInfoZ128, x86memopZ128>,
5660 avx512_trunc_mr_lowering<VTSrcInfo.info128, DestInfoZ128,
5661 truncFrag, mtruncFrag>, EVEX_V128;
5663 defm Z256: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info256,
5664 DestInfoZ256, x86memopZ256>,
5665 avx512_trunc_mr_lowering<VTSrcInfo.info256, DestInfoZ256,
5666 truncFrag, mtruncFrag>, EVEX_V256;
5668 let Predicates = [prd] in
5669 defm Z: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info512,
5670 DestInfoZ, x86memopZ>,
5671 avx512_trunc_mr_lowering<VTSrcInfo.info512, DestInfoZ,
5672 truncFrag, mtruncFrag>, EVEX_V512;
5675 multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr, SDNode OpNode,
5676 AVX512VLVectorVTInfo VTSrcInfo, X86VectorVTInfo DestInfoZ128,
5677 X86VectorVTInfo DestInfoZ256, X86VectorVTInfo DestInfoZ,
5678 X86MemOperand x86memopZ128, X86MemOperand x86memopZ256,
5679 X86MemOperand x86memopZ, string sat, Predicate prd = HasAVX512>{
5681 let Predicates = [HasVLX, prd] in {
5682 defm Z128: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info128,
5683 DestInfoZ128, x86memopZ128>,
5684 avx512_trunc_sat_mr_lowering<VTSrcInfo.info128, DestInfoZ128,
5687 defm Z256: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info256,
5688 DestInfoZ256, x86memopZ256>,
5689 avx512_trunc_sat_mr_lowering<VTSrcInfo.info256, DestInfoZ256,
5692 let Predicates = [prd] in
5693 defm Z: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info512,
5694 DestInfoZ, x86memopZ>,
5695 avx512_trunc_sat_mr_lowering<VTSrcInfo.info512, DestInfoZ,
5699 multiclass avx512_trunc_qb<bits<8> opc, string OpcodeStr, SDNode OpNode> {
5700 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i64_info,
5701 v16i8x_info, v16i8x_info, v16i8x_info, i16mem, i32mem, i64mem,
5702 truncstorevi8, masked_truncstorevi8>, EVEX_CD8<8, CD8VO>;
5704 multiclass avx512_trunc_sat_qb<bits<8> opc, string sat, SDNode OpNode> {
5705 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"qb", OpNode, avx512vl_i64_info,
5706 v16i8x_info, v16i8x_info, v16i8x_info, i16mem, i32mem, i64mem,
5707 sat>, EVEX_CD8<8, CD8VO>;
5710 multiclass avx512_trunc_qw<bits<8> opc, string OpcodeStr, SDNode OpNode> {
5711 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i64_info,
5712 v8i16x_info, v8i16x_info, v8i16x_info, i32mem, i64mem, i128mem,
5713 truncstorevi16, masked_truncstorevi16>, EVEX_CD8<16, CD8VQ>;
5715 multiclass avx512_trunc_sat_qw<bits<8> opc, string sat, SDNode OpNode> {
5716 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"qw", OpNode, avx512vl_i64_info,
5717 v8i16x_info, v8i16x_info, v8i16x_info, i32mem, i64mem, i128mem,
5718 sat>, EVEX_CD8<16, CD8VQ>;
5721 multiclass avx512_trunc_qd<bits<8> opc, string OpcodeStr, SDNode OpNode> {
5722 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i64_info,
5723 v4i32x_info, v4i32x_info, v8i32x_info, i64mem, i128mem, i256mem,
5724 truncstorevi32, masked_truncstorevi32>, EVEX_CD8<32, CD8VH>;
5726 multiclass avx512_trunc_sat_qd<bits<8> opc, string sat, SDNode OpNode> {
5727 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"qd", OpNode, avx512vl_i64_info,
5728 v4i32x_info, v4i32x_info, v8i32x_info, i64mem, i128mem, i256mem,
5729 sat>, EVEX_CD8<32, CD8VH>;
5732 multiclass avx512_trunc_db<bits<8> opc, string OpcodeStr, SDNode OpNode> {
5733 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i32_info,
5734 v16i8x_info, v16i8x_info, v16i8x_info, i32mem, i64mem, i128mem,
5735 truncstorevi8, masked_truncstorevi8>, EVEX_CD8<8, CD8VQ>;
5737 multiclass avx512_trunc_sat_db<bits<8> opc, string sat, SDNode OpNode> {
5738 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"db", OpNode, avx512vl_i32_info,
5739 v16i8x_info, v16i8x_info, v16i8x_info, i32mem, i64mem, i128mem,
5740 sat>, EVEX_CD8<8, CD8VQ>;
5743 multiclass avx512_trunc_dw<bits<8> opc, string OpcodeStr, SDNode OpNode> {
5744 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i32_info,
5745 v8i16x_info, v8i16x_info, v16i16x_info, i64mem, i128mem, i256mem,
5746 truncstorevi16, masked_truncstorevi16>, EVEX_CD8<16, CD8VH>;
5748 multiclass avx512_trunc_sat_dw<bits<8> opc, string sat, SDNode OpNode> {
5749 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"dw", OpNode, avx512vl_i32_info,
5750 v8i16x_info, v8i16x_info, v16i16x_info, i64mem, i128mem, i256mem,
5751 sat>, EVEX_CD8<16, CD8VH>;
5754 multiclass avx512_trunc_wb<bits<8> opc, string OpcodeStr, SDNode OpNode> {
5755 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i16_info,
5756 v16i8x_info, v16i8x_info, v32i8x_info, i64mem, i128mem, i256mem,
5757 truncstorevi8, masked_truncstorevi8,HasBWI>, EVEX_CD8<16, CD8VH>;
5759 multiclass avx512_trunc_sat_wb<bits<8> opc, string sat, SDNode OpNode> {
5760 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"wb", OpNode, avx512vl_i16_info,
5761 v16i8x_info, v16i8x_info, v32i8x_info, i64mem, i128mem, i256mem,
5762 sat, HasBWI>, EVEX_CD8<16, CD8VH>;
5765 defm VPMOVQB : avx512_trunc_qb<0x32, "vpmovqb", X86vtrunc>;
5766 defm VPMOVSQB : avx512_trunc_sat_qb<0x22, "s", X86vtruncs>;
5767 defm VPMOVUSQB : avx512_trunc_sat_qb<0x12, "us", X86vtruncus>;
5769 defm VPMOVQW : avx512_trunc_qw<0x34, "vpmovqw", X86vtrunc>;
5770 defm VPMOVSQW : avx512_trunc_sat_qw<0x24, "s", X86vtruncs>;
5771 defm VPMOVUSQW : avx512_trunc_sat_qw<0x14, "us", X86vtruncus>;
5773 defm VPMOVQD : avx512_trunc_qd<0x35, "vpmovqd", X86vtrunc>;
5774 defm VPMOVSQD : avx512_trunc_sat_qd<0x25, "s", X86vtruncs>;
5775 defm VPMOVUSQD : avx512_trunc_sat_qd<0x15, "us", X86vtruncus>;
5777 defm VPMOVDB : avx512_trunc_db<0x31, "vpmovdb", X86vtrunc>;
5778 defm VPMOVSDB : avx512_trunc_sat_db<0x21, "s", X86vtruncs>;
5779 defm VPMOVUSDB : avx512_trunc_sat_db<0x11, "us", X86vtruncus>;
5781 defm VPMOVDW : avx512_trunc_dw<0x33, "vpmovdw", X86vtrunc>;
5782 defm VPMOVSDW : avx512_trunc_sat_dw<0x23, "s", X86vtruncs>;
5783 defm VPMOVUSDW : avx512_trunc_sat_dw<0x13, "us", X86vtruncus>;
5785 defm VPMOVWB : avx512_trunc_wb<0x30, "vpmovwb", X86vtrunc>;
5786 defm VPMOVSWB : avx512_trunc_sat_wb<0x20, "s", X86vtruncs>;
5787 defm VPMOVUSWB : avx512_trunc_sat_wb<0x10, "us", X86vtruncus>;
5789 multiclass avx512_extend_common<bits<8> opc, string OpcodeStr,
5790 X86VectorVTInfo DestInfo, X86VectorVTInfo SrcInfo,
5791 X86MemOperand x86memop, PatFrag LdFrag, SDNode OpNode>{
5793 defm rr : AVX512_maskable<opc, MRMSrcReg, DestInfo, (outs DestInfo.RC:$dst),
5794 (ins SrcInfo.RC:$src), OpcodeStr ,"$src", "$src",
5795 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src)))>,
5798 let mayLoad = 1 in {
5799 defm rm : AVX512_maskable<opc, MRMSrcMem, DestInfo, (outs DestInfo.RC:$dst),
5800 (ins x86memop:$src), OpcodeStr ,"$src", "$src",
5801 (DestInfo.VT (LdFrag addr:$src))>,
5806 multiclass avx512_extend_BW<bits<8> opc, string OpcodeStr, SDNode OpNode,
5807 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi8")> {
5808 let Predicates = [HasVLX, HasBWI] in {
5809 defm Z128: avx512_extend_common<opc, OpcodeStr, v8i16x_info,
5810 v16i8x_info, i64mem, LdFrag, OpNode>,
5811 EVEX_CD8<8, CD8VH>, T8PD, EVEX_V128;
5813 defm Z256: avx512_extend_common<opc, OpcodeStr, v16i16x_info,
5814 v16i8x_info, i128mem, LdFrag, OpNode>,
5815 EVEX_CD8<8, CD8VH>, T8PD, EVEX_V256;
5817 let Predicates = [HasBWI] in {
5818 defm Z : avx512_extend_common<opc, OpcodeStr, v32i16_info,
5819 v32i8x_info, i256mem, LdFrag, OpNode>,
5820 EVEX_CD8<8, CD8VH>, T8PD, EVEX_V512;
5824 multiclass avx512_extend_BD<bits<8> opc, string OpcodeStr, SDNode OpNode,
5825 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi8")> {
5826 let Predicates = [HasVLX, HasAVX512] in {
5827 defm Z128: avx512_extend_common<opc, OpcodeStr, v4i32x_info,
5828 v16i8x_info, i32mem, LdFrag, OpNode>,
5829 EVEX_CD8<8, CD8VQ>, T8PD, EVEX_V128;
5831 defm Z256: avx512_extend_common<opc, OpcodeStr, v8i32x_info,
5832 v16i8x_info, i64mem, LdFrag, OpNode>,
5833 EVEX_CD8<8, CD8VQ>, T8PD, EVEX_V256;
5835 let Predicates = [HasAVX512] in {
5836 defm Z : avx512_extend_common<opc, OpcodeStr, v16i32_info,
5837 v16i8x_info, i128mem, LdFrag, OpNode>,
5838 EVEX_CD8<8, CD8VQ>, T8PD, EVEX_V512;
5842 multiclass avx512_extend_BQ<bits<8> opc, string OpcodeStr, SDNode OpNode,
5843 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi8")> {
5844 let Predicates = [HasVLX, HasAVX512] in {
5845 defm Z128: avx512_extend_common<opc, OpcodeStr, v2i64x_info,
5846 v16i8x_info, i16mem, LdFrag, OpNode>,
5847 EVEX_CD8<8, CD8VO>, T8PD, EVEX_V128;
5849 defm Z256: avx512_extend_common<opc, OpcodeStr, v4i64x_info,
5850 v16i8x_info, i32mem, LdFrag, OpNode>,
5851 EVEX_CD8<8, CD8VO>, T8PD, EVEX_V256;
5853 let Predicates = [HasAVX512] in {
5854 defm Z : avx512_extend_common<opc, OpcodeStr, v8i64_info,
5855 v16i8x_info, i64mem, LdFrag, OpNode>,
5856 EVEX_CD8<8, CD8VO>, T8PD, EVEX_V512;
5860 multiclass avx512_extend_WD<bits<8> opc, string OpcodeStr, SDNode OpNode,
5861 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi16")> {
5862 let Predicates = [HasVLX, HasAVX512] in {
5863 defm Z128: avx512_extend_common<opc, OpcodeStr, v4i32x_info,
5864 v8i16x_info, i64mem, LdFrag, OpNode>,
5865 EVEX_CD8<16, CD8VH>, T8PD, EVEX_V128;
5867 defm Z256: avx512_extend_common<opc, OpcodeStr, v8i32x_info,
5868 v8i16x_info, i128mem, LdFrag, OpNode>,
5869 EVEX_CD8<16, CD8VH>, T8PD, EVEX_V256;
5871 let Predicates = [HasAVX512] in {
5872 defm Z : avx512_extend_common<opc, OpcodeStr, v16i32_info,
5873 v16i16x_info, i256mem, LdFrag, OpNode>,
5874 EVEX_CD8<16, CD8VH>, T8PD, EVEX_V512;
5878 multiclass avx512_extend_WQ<bits<8> opc, string OpcodeStr, SDNode OpNode,
5879 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi16")> {
5880 let Predicates = [HasVLX, HasAVX512] in {
5881 defm Z128: avx512_extend_common<opc, OpcodeStr, v2i64x_info,
5882 v8i16x_info, i32mem, LdFrag, OpNode>,
5883 EVEX_CD8<16, CD8VQ>, T8PD, EVEX_V128;
5885 defm Z256: avx512_extend_common<opc, OpcodeStr, v4i64x_info,
5886 v8i16x_info, i64mem, LdFrag, OpNode>,
5887 EVEX_CD8<16, CD8VQ>, T8PD, EVEX_V256;
5889 let Predicates = [HasAVX512] in {
5890 defm Z : avx512_extend_common<opc, OpcodeStr, v8i64_info,
5891 v8i16x_info, i128mem, LdFrag, OpNode>,
5892 EVEX_CD8<16, CD8VQ>, T8PD, EVEX_V512;
5896 multiclass avx512_extend_DQ<bits<8> opc, string OpcodeStr, SDNode OpNode,
5897 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi32")> {
5899 let Predicates = [HasVLX, HasAVX512] in {
5900 defm Z128: avx512_extend_common<opc, OpcodeStr, v2i64x_info,
5901 v4i32x_info, i64mem, LdFrag, OpNode>,
5902 EVEX_CD8<32, CD8VH>, T8PD, EVEX_V128;
5904 defm Z256: avx512_extend_common<opc, OpcodeStr, v4i64x_info,
5905 v4i32x_info, i128mem, LdFrag, OpNode>,
5906 EVEX_CD8<32, CD8VH>, T8PD, EVEX_V256;
5908 let Predicates = [HasAVX512] in {
5909 defm Z : avx512_extend_common<opc, OpcodeStr, v8i64_info,
5910 v8i32x_info, i256mem, LdFrag, OpNode>,
5911 EVEX_CD8<32, CD8VH>, T8PD, EVEX_V512;
5915 defm VPMOVZXBW : avx512_extend_BW<0x30, "vpmovzxbw", X86vzext, "z">;
5916 defm VPMOVZXBD : avx512_extend_BD<0x31, "vpmovzxbd", X86vzext, "z">;
5917 defm VPMOVZXBQ : avx512_extend_BQ<0x32, "vpmovzxbq", X86vzext, "z">;
5918 defm VPMOVZXWD : avx512_extend_WD<0x33, "vpmovzxwd", X86vzext, "z">;
5919 defm VPMOVZXWQ : avx512_extend_WQ<0x34, "vpmovzxwq", X86vzext, "z">;
5920 defm VPMOVZXDQ : avx512_extend_DQ<0x35, "vpmovzxdq", X86vzext, "z">;
5923 defm VPMOVSXBW: avx512_extend_BW<0x20, "vpmovsxbw", X86vsext, "s">;
5924 defm VPMOVSXBD: avx512_extend_BD<0x21, "vpmovsxbd", X86vsext, "s">;
5925 defm VPMOVSXBQ: avx512_extend_BQ<0x22, "vpmovsxbq", X86vsext, "s">;
5926 defm VPMOVSXWD: avx512_extend_WD<0x23, "vpmovsxwd", X86vsext, "s">;
5927 defm VPMOVSXWQ: avx512_extend_WQ<0x24, "vpmovsxwq", X86vsext, "s">;
5928 defm VPMOVSXDQ: avx512_extend_DQ<0x25, "vpmovsxdq", X86vsext, "s">;
5930 //===----------------------------------------------------------------------===//
5931 // GATHER - SCATTER Operations
5933 multiclass avx512_gather<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5934 X86MemOperand memop, PatFrag GatherNode> {
5935 let Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb",
5936 ExeDomain = _.ExeDomain in
5937 def rm : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst, _.KRCWM:$mask_wb),
5938 (ins _.RC:$src1, _.KRCWM:$mask, memop:$src2),
5939 !strconcat(OpcodeStr#_.Suffix,
5940 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
5941 [(set _.RC:$dst, _.KRCWM:$mask_wb,
5942 (GatherNode (_.VT _.RC:$src1), _.KRCWM:$mask,
5943 vectoraddr:$src2))]>, EVEX, EVEX_K,
5944 EVEX_CD8<_.EltSize, CD8VT1>;
5947 multiclass avx512_gather_q_pd<bits<8> dopc, bits<8> qopc,
5948 AVX512VLVectorVTInfo _, string OpcodeStr, string SUFF> {
5949 defm NAME##D##SUFF##Z: avx512_gather<dopc, OpcodeStr##"d", _.info512,
5950 vy32xmem, mgatherv8i32>, EVEX_V512, VEX_W;
5951 defm NAME##Q##SUFF##Z: avx512_gather<qopc, OpcodeStr##"q", _.info512,
5952 vz64mem, mgatherv8i64>, EVEX_V512, VEX_W;
5953 let Predicates = [HasVLX] in {
5954 defm NAME##D##SUFF##Z256: avx512_gather<dopc, OpcodeStr##"d", _.info256,
5955 vx32xmem, mgatherv4i32>, EVEX_V256, VEX_W;
5956 defm NAME##Q##SUFF##Z256: avx512_gather<qopc, OpcodeStr##"q", _.info256,
5957 vy64xmem, mgatherv4i64>, EVEX_V256, VEX_W;
5958 defm NAME##D##SUFF##Z128: avx512_gather<dopc, OpcodeStr##"d", _.info128,
5959 vx32xmem, mgatherv4i32>, EVEX_V128, VEX_W;
5960 defm NAME##Q##SUFF##Z128: avx512_gather<qopc, OpcodeStr##"q", _.info128,
5961 vx64xmem, mgatherv2i64>, EVEX_V128, VEX_W;
5965 multiclass avx512_gather_d_ps<bits<8> dopc, bits<8> qopc,
5966 AVX512VLVectorVTInfo _, string OpcodeStr, string SUFF> {
5967 defm NAME##D##SUFF##Z: avx512_gather<dopc, OpcodeStr##"d", _.info512, vz32mem,
5968 mgatherv16i32>, EVEX_V512;
5969 defm NAME##Q##SUFF##Z: avx512_gather<qopc, OpcodeStr##"q", _.info256, vz64mem,
5970 mgatherv8i64>, EVEX_V512;
5971 let Predicates = [HasVLX] in {
5972 defm NAME##D##SUFF##Z256: avx512_gather<dopc, OpcodeStr##"d", _.info256,
5973 vy32xmem, mgatherv8i32>, EVEX_V256;
5974 defm NAME##Q##SUFF##Z256: avx512_gather<qopc, OpcodeStr##"q", _.info128,
5975 vy64xmem, mgatherv4i64>, EVEX_V256;
5976 defm NAME##D##SUFF##Z128: avx512_gather<dopc, OpcodeStr##"d", _.info128,
5977 vx32xmem, mgatherv4i32>, EVEX_V128;
5978 defm NAME##Q##SUFF##Z128: avx512_gather<qopc, OpcodeStr##"q", _.info128,
5979 vx64xmem, mgatherv2i64>, EVEX_V128;
5984 defm VGATHER : avx512_gather_q_pd<0x92, 0x93, avx512vl_f64_info, "vgather", "PD">,
5985 avx512_gather_d_ps<0x92, 0x93, avx512vl_f32_info, "vgather", "PS">;
5987 defm VPGATHER : avx512_gather_q_pd<0x90, 0x91, avx512vl_i64_info, "vpgather", "Q">,
5988 avx512_gather_d_ps<0x90, 0x91, avx512vl_i32_info, "vpgather", "D">;
5990 multiclass avx512_scatter<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5991 X86MemOperand memop, PatFrag ScatterNode> {
5993 let mayStore = 1, Constraints = "$mask = $mask_wb", ExeDomain = _.ExeDomain in
5995 def mr : AVX5128I<opc, MRMDestMem, (outs _.KRCWM:$mask_wb),
5996 (ins memop:$dst, _.KRCWM:$mask, _.RC:$src),
5997 !strconcat(OpcodeStr#_.Suffix,
5998 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
5999 [(set _.KRCWM:$mask_wb, (ScatterNode (_.VT _.RC:$src),
6000 _.KRCWM:$mask, vectoraddr:$dst))]>,
6001 EVEX, EVEX_K, EVEX_CD8<_.EltSize, CD8VT1>;
6004 multiclass avx512_scatter_q_pd<bits<8> dopc, bits<8> qopc,
6005 AVX512VLVectorVTInfo _, string OpcodeStr, string SUFF> {
6006 defm NAME##D##SUFF##Z: avx512_scatter<dopc, OpcodeStr##"d", _.info512,
6007 vy32xmem, mscatterv8i32>, EVEX_V512, VEX_W;
6008 defm NAME##Q##SUFF##Z: avx512_scatter<qopc, OpcodeStr##"q", _.info512,
6009 vz64mem, mscatterv8i64>, EVEX_V512, VEX_W;
6010 let Predicates = [HasVLX] in {
6011 defm NAME##D##SUFF##Z256: avx512_scatter<dopc, OpcodeStr##"d", _.info256,
6012 vx32xmem, mscatterv4i32>, EVEX_V256, VEX_W;
6013 defm NAME##Q##SUFF##Z256: avx512_scatter<qopc, OpcodeStr##"q", _.info256,
6014 vy64xmem, mscatterv4i64>, EVEX_V256, VEX_W;
6015 defm NAME##D##SUFF##Z128: avx512_scatter<dopc, OpcodeStr##"d", _.info128,
6016 vx32xmem, mscatterv4i32>, EVEX_V128, VEX_W;
6017 defm NAME##Q##SUFF##Z128: avx512_scatter<qopc, OpcodeStr##"q", _.info128,
6018 vx64xmem, mscatterv2i64>, EVEX_V128, VEX_W;
6022 multiclass avx512_scatter_d_ps<bits<8> dopc, bits<8> qopc,
6023 AVX512VLVectorVTInfo _, string OpcodeStr, string SUFF> {
6024 defm NAME##D##SUFF##Z: avx512_scatter<dopc, OpcodeStr##"d", _.info512, vz32mem,
6025 mscatterv16i32>, EVEX_V512;
6026 defm NAME##Q##SUFF##Z: avx512_scatter<qopc, OpcodeStr##"q", _.info256, vz64mem,
6027 mscatterv8i64>, EVEX_V512;
6028 let Predicates = [HasVLX] in {
6029 defm NAME##D##SUFF##Z256: avx512_scatter<dopc, OpcodeStr##"d", _.info256,
6030 vy32xmem, mscatterv8i32>, EVEX_V256;
6031 defm NAME##Q##SUFF##Z256: avx512_scatter<qopc, OpcodeStr##"q", _.info128,
6032 vy64xmem, mscatterv4i64>, EVEX_V256;
6033 defm NAME##D##SUFF##Z128: avx512_scatter<dopc, OpcodeStr##"d", _.info128,
6034 vx32xmem, mscatterv4i32>, EVEX_V128;
6035 defm NAME##Q##SUFF##Z128: avx512_scatter<qopc, OpcodeStr##"q", _.info128,
6036 vx64xmem, mscatterv2i64>, EVEX_V128;
6040 defm VSCATTER : avx512_scatter_q_pd<0xA2, 0xA3, avx512vl_f64_info, "vscatter", "PD">,
6041 avx512_scatter_d_ps<0xA2, 0xA3, avx512vl_f32_info, "vscatter", "PS">;
6043 defm VPSCATTER : avx512_scatter_q_pd<0xA0, 0xA1, avx512vl_i64_info, "vpscatter", "Q">,
6044 avx512_scatter_d_ps<0xA0, 0xA1, avx512vl_i32_info, "vpscatter", "D">;
6047 multiclass avx512_gather_scatter_prefetch<bits<8> opc, Format F, string OpcodeStr,
6048 RegisterClass KRC, X86MemOperand memop> {
6049 let Predicates = [HasPFI], hasSideEffects = 1 in
6050 def m : AVX5128I<opc, F, (outs), (ins KRC:$mask, memop:$src),
6051 !strconcat(OpcodeStr, "\t{$src {${mask}}|{${mask}}, $src}"),
6055 defm VGATHERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dps",
6056 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
6058 defm VGATHERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qps",
6059 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
6061 defm VGATHERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dpd",
6062 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
6064 defm VGATHERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qpd",
6065 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
6067 defm VGATHERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dps",
6068 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
6070 defm VGATHERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qps",
6071 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
6073 defm VGATHERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dpd",
6074 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
6076 defm VGATHERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qpd",
6077 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
6079 defm VSCATTERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dps",
6080 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
6082 defm VSCATTERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qps",
6083 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
6085 defm VSCATTERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dpd",
6086 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
6088 defm VSCATTERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qpd",
6089 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
6091 defm VSCATTERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dps",
6092 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
6094 defm VSCATTERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qps",
6095 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
6097 defm VSCATTERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dpd",
6098 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
6100 defm VSCATTERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qpd",
6101 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
6103 // Helper fragments to match sext vXi1 to vXiY.
6104 def v16i1sextv16i32 : PatLeaf<(v16i32 (X86vsrai VR512:$src, (i8 31)))>;
6105 def v8i1sextv8i64 : PatLeaf<(v8i64 (X86vsrai VR512:$src, (i8 63)))>;
6107 def : Pat<(store (i1 -1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
6108 def : Pat<(store (i1 1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
6109 def : Pat<(store (i1 0), addr:$dst), (MOV8mi addr:$dst, (i8 0))>;
6111 def : Pat<(store VK1:$src, addr:$dst),
6113 (EXTRACT_SUBREG (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)),
6114 sub_8bit))>, Requires<[HasAVX512, NoDQI]>;
6116 def : Pat<(store VK8:$src, addr:$dst),
6118 (EXTRACT_SUBREG (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
6119 sub_8bit))>, Requires<[HasAVX512, NoDQI]>;
6121 def truncstorei1 : PatFrag<(ops node:$val, node:$ptr),
6122 (truncstore node:$val, node:$ptr), [{
6123 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
6126 def : Pat<(truncstorei1 GR8:$src, addr:$dst),
6127 (MOV8mr addr:$dst, GR8:$src)>;
6129 multiclass cvt_by_vec_width<bits<8> opc, X86VectorVTInfo Vec, string OpcodeStr > {
6130 def rr : AVX512XS8I<opc, MRMSrcReg, (outs Vec.RC:$dst), (ins Vec.KRC:$src),
6131 !strconcat(OpcodeStr##Vec.Suffix, "\t{$src, $dst|$dst, $src}"),
6132 [(set Vec.RC:$dst, (Vec.VT (X86vsext Vec.KRC:$src)))]>, EVEX;
6135 multiclass cvt_mask_by_elt_width<bits<8> opc, AVX512VLVectorVTInfo VTInfo,
6136 string OpcodeStr, Predicate prd> {
6137 let Predicates = [prd] in
6138 defm Z : cvt_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
6140 let Predicates = [prd, HasVLX] in {
6141 defm Z256 : cvt_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
6142 defm Z128 : cvt_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
6146 multiclass avx512_convert_mask_to_vector<string OpcodeStr> {
6147 defm NAME##B : cvt_mask_by_elt_width<0x28, avx512vl_i8_info, OpcodeStr,
6149 defm NAME##W : cvt_mask_by_elt_width<0x28, avx512vl_i16_info, OpcodeStr,
6151 defm NAME##D : cvt_mask_by_elt_width<0x38, avx512vl_i32_info, OpcodeStr,
6153 defm NAME##Q : cvt_mask_by_elt_width<0x38, avx512vl_i64_info, OpcodeStr,
6157 defm VPMOVM2 : avx512_convert_mask_to_vector<"vpmovm2">;
6159 multiclass convert_vector_to_mask_common<bits<8> opc, X86VectorVTInfo _, string OpcodeStr > {
6160 def rr : AVX512XS8I<opc, MRMSrcReg, (outs _.KRC:$dst), (ins _.RC:$src),
6161 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6162 [(set _.KRC:$dst, (trunc (_.VT _.RC:$src)))]>, EVEX;
6165 multiclass avx512_convert_vector_to_mask<bits<8> opc, string OpcodeStr,
6166 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
6167 let Predicates = [prd] in
6168 defm Z : convert_vector_to_mask_common <opc, VTInfo.info512, OpcodeStr>,
6171 let Predicates = [prd, HasVLX] in {
6172 defm Z256 : convert_vector_to_mask_common<opc, VTInfo.info256, OpcodeStr>,
6174 defm Z128 : convert_vector_to_mask_common<opc, VTInfo.info128, OpcodeStr>,
6179 defm VPMOVB2M : avx512_convert_vector_to_mask<0x29, "vpmovb2m",
6180 avx512vl_i8_info, HasBWI>;
6181 defm VPMOVW2M : avx512_convert_vector_to_mask<0x29, "vpmovw2m",
6182 avx512vl_i16_info, HasBWI>, VEX_W;
6183 defm VPMOVD2M : avx512_convert_vector_to_mask<0x39, "vpmovd2m",
6184 avx512vl_i32_info, HasDQI>;
6185 defm VPMOVQ2M : avx512_convert_vector_to_mask<0x39, "vpmovq2m",
6186 avx512vl_i64_info, HasDQI>, VEX_W;
6188 //===----------------------------------------------------------------------===//
6189 // AVX-512 - COMPRESS and EXPAND
6192 multiclass compress_by_vec_width<bits<8> opc, X86VectorVTInfo _,
6194 defm rr : AVX512_maskable<opc, MRMDestReg, _, (outs _.RC:$dst),
6195 (ins _.RC:$src1), OpcodeStr, "$src1", "$src1",
6196 (_.VT (X86compress _.RC:$src1))>, AVX5128IBase;
6198 let mayStore = 1 in {
6199 def mr : AVX5128I<opc, MRMDestMem, (outs),
6200 (ins _.MemOp:$dst, _.RC:$src),
6201 OpcodeStr # "\t{$src, $dst |$dst, $src}",
6202 []>, EVEX_CD8<_.EltSize, CD8VT1>;
6204 def mrk : AVX5128I<opc, MRMDestMem, (outs),
6205 (ins _.MemOp:$dst, _.KRCWM:$mask, _.RC:$src),
6206 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
6207 [(store (_.VT (vselect _.KRCWM:$mask,
6208 (_.VT (X86compress _.RC:$src)), _.ImmAllZerosV)),
6210 EVEX_K, EVEX_CD8<_.EltSize, CD8VT1>;
6214 multiclass compress_by_elt_width<bits<8> opc, string OpcodeStr,
6215 AVX512VLVectorVTInfo VTInfo> {
6216 defm Z : compress_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
6218 let Predicates = [HasVLX] in {
6219 defm Z256 : compress_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
6220 defm Z128 : compress_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
6224 defm VPCOMPRESSD : compress_by_elt_width <0x8B, "vpcompressd", avx512vl_i32_info>,
6226 defm VPCOMPRESSQ : compress_by_elt_width <0x8B, "vpcompressq", avx512vl_i64_info>,
6228 defm VCOMPRESSPS : compress_by_elt_width <0x8A, "vcompressps", avx512vl_f32_info>,
6230 defm VCOMPRESSPD : compress_by_elt_width <0x8A, "vcompresspd", avx512vl_f64_info>,
6234 multiclass expand_by_vec_width<bits<8> opc, X86VectorVTInfo _,
6236 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6237 (ins _.RC:$src1), OpcodeStr, "$src1", "$src1",
6238 (_.VT (X86expand _.RC:$src1))>, AVX5128IBase;
6241 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6242 (ins _.MemOp:$src1), OpcodeStr, "$src1", "$src1",
6243 (_.VT (X86expand (_.VT (bitconvert
6244 (_.LdFrag addr:$src1)))))>,
6245 AVX5128IBase, EVEX_CD8<_.EltSize, CD8VT1>;
6248 multiclass expand_by_elt_width<bits<8> opc, string OpcodeStr,
6249 AVX512VLVectorVTInfo VTInfo> {
6250 defm Z : expand_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
6252 let Predicates = [HasVLX] in {
6253 defm Z256 : expand_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
6254 defm Z128 : expand_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
6258 defm VPEXPANDD : expand_by_elt_width <0x89, "vpexpandd", avx512vl_i32_info>,
6260 defm VPEXPANDQ : expand_by_elt_width <0x89, "vpexpandq", avx512vl_i64_info>,
6262 defm VEXPANDPS : expand_by_elt_width <0x88, "vexpandps", avx512vl_f32_info>,
6264 defm VEXPANDPD : expand_by_elt_width <0x88, "vexpandpd", avx512vl_f64_info>,
6267 //handle instruction reg_vec1 = op(reg_vec,imm)
6269 // op(broadcast(eltVt),imm)
6270 //all instruction created with FROUND_CURRENT
6271 multiclass avx512_unary_fp_packed_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6273 defm rri : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6274 (ins _.RC:$src1, i32u8imm:$src2),
6275 OpcodeStr##_.Suffix, "$src2, $src1", "$src2, $src2",
6276 (OpNode (_.VT _.RC:$src1),
6278 (i32 FROUND_CURRENT))>;
6279 let mayLoad = 1 in {
6280 defm rmi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6281 (ins _.MemOp:$src1, i32u8imm:$src2),
6282 OpcodeStr##_.Suffix, "$src2, $src1", "$src1, $src2",
6283 (OpNode (_.VT (bitconvert (_.LdFrag addr:$src1))),
6285 (i32 FROUND_CURRENT))>;
6286 defm rmbi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6287 (ins _.ScalarMemOp:$src1, i32u8imm:$src2),
6288 OpcodeStr##_.Suffix, "$src2, ${src1}"##_.BroadcastStr,
6289 "${src1}"##_.BroadcastStr##", $src2",
6290 (OpNode (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src1))),
6292 (i32 FROUND_CURRENT))>, EVEX_B;
6296 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm),{sae}
6297 multiclass avx512_unary_fp_sae_packed_imm<bits<8> opc, string OpcodeStr,
6298 SDNode OpNode, X86VectorVTInfo _>{
6299 defm rrib : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6300 (ins _.RC:$src1, i32u8imm:$src2),
6301 OpcodeStr##_.Suffix, "$src2,{sae}, $src1",
6302 "$src1, {sae}, $src2",
6303 (OpNode (_.VT _.RC:$src1),
6305 (i32 FROUND_NO_EXC))>, EVEX_B;
6308 multiclass avx512_common_unary_fp_sae_packed_imm<string OpcodeStr,
6309 AVX512VLVectorVTInfo _, bits<8> opc, SDNode OpNode, Predicate prd>{
6310 let Predicates = [prd] in {
6311 defm Z : avx512_unary_fp_packed_imm<opc, OpcodeStr, OpNode, _.info512>,
6312 avx512_unary_fp_sae_packed_imm<opc, OpcodeStr, OpNode, _.info512>,
6315 let Predicates = [prd, HasVLX] in {
6316 defm Z128 : avx512_unary_fp_packed_imm<opc, OpcodeStr, OpNode, _.info128>,
6318 defm Z256 : avx512_unary_fp_packed_imm<opc, OpcodeStr, OpNode, _.info256>,
6323 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm)
6324 // op(reg_vec2,mem_vec,imm)
6325 // op(reg_vec2,broadcast(eltVt),imm)
6326 //all instruction created with FROUND_CURRENT
6327 multiclass avx512_fp_packed_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6329 defm rri : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6330 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3),
6331 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6332 (OpNode (_.VT _.RC:$src1),
6335 (i32 FROUND_CURRENT))>;
6336 let mayLoad = 1 in {
6337 defm rmi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6338 (ins _.RC:$src1, _.MemOp:$src2, i32u8imm:$src3),
6339 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6340 (OpNode (_.VT _.RC:$src1),
6341 (_.VT (bitconvert (_.LdFrag addr:$src2))),
6343 (i32 FROUND_CURRENT))>;
6344 defm rmbi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6345 (ins _.RC:$src1, _.ScalarMemOp:$src2, i32u8imm:$src3),
6346 OpcodeStr, "$src3, ${src2}"##_.BroadcastStr##", $src1",
6347 "$src1, ${src2}"##_.BroadcastStr##", $src3",
6348 (OpNode (_.VT _.RC:$src1),
6349 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src2))),
6351 (i32 FROUND_CURRENT))>, EVEX_B;
6355 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm)
6356 // op(reg_vec2,mem_vec,imm)
6357 multiclass avx512_3Op_rm_imm8<bits<8> opc, string OpcodeStr, SDNode OpNode,
6358 X86VectorVTInfo DestInfo, X86VectorVTInfo SrcInfo>{
6360 defm rri : AVX512_maskable<opc, MRMSrcReg, DestInfo, (outs DestInfo.RC:$dst),
6361 (ins SrcInfo.RC:$src1, SrcInfo.RC:$src2, u8imm:$src3),
6362 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6363 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1),
6364 (SrcInfo.VT SrcInfo.RC:$src2),
6367 defm rmi : AVX512_maskable<opc, MRMSrcMem, DestInfo, (outs DestInfo.RC:$dst),
6368 (ins SrcInfo.RC:$src1, SrcInfo.MemOp:$src2, u8imm:$src3),
6369 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6370 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1),
6371 (SrcInfo.VT (bitconvert
6372 (SrcInfo.LdFrag addr:$src2))),
6376 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm)
6377 // op(reg_vec2,mem_vec,imm)
6378 // op(reg_vec2,broadcast(eltVt),imm)
6379 multiclass avx512_3Op_imm8<bits<8> opc, string OpcodeStr, SDNode OpNode,
6381 avx512_3Op_rm_imm8<opc, OpcodeStr, OpNode, _, _>{
6384 defm rmbi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6385 (ins _.RC:$src1, _.ScalarMemOp:$src2, u8imm:$src3),
6386 OpcodeStr, "$src3, ${src2}"##_.BroadcastStr##", $src1",
6387 "$src1, ${src2}"##_.BroadcastStr##", $src3",
6388 (OpNode (_.VT _.RC:$src1),
6389 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src2))),
6390 (i8 imm:$src3))>, EVEX_B;
6393 //handle scalar instruction reg_vec1 = op(reg_vec2,reg_vec3,imm)
6394 // op(reg_vec2,mem_scalar,imm)
6395 //all instruction created with FROUND_CURRENT
6396 multiclass avx512_fp_scalar_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6397 X86VectorVTInfo _> {
6399 defm rri : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
6400 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3),
6401 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6402 (OpNode (_.VT _.RC:$src1),
6405 (i32 FROUND_CURRENT))>;
6406 let mayLoad = 1 in {
6407 defm rmi : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
6408 (ins _.RC:$src1, _.MemOp:$src2, i32u8imm:$src3),
6409 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6410 (OpNode (_.VT _.RC:$src1),
6411 (_.VT (scalar_to_vector
6412 (_.ScalarLdFrag addr:$src2))),
6414 (i32 FROUND_CURRENT))>;
6416 let isAsmParserOnly = 1 in {
6417 defm rmi_alt :AVX512_maskable_in_asm<opc, MRMSrcMem, _, (outs _.FRC:$dst),
6418 (ins _.FRC:$src1, _.ScalarMemOp:$src2, u8imm:$src3),
6419 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6425 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm),{sae}
6426 multiclass avx512_fp_sae_packed_imm<bits<8> opc, string OpcodeStr,
6427 SDNode OpNode, X86VectorVTInfo _>{
6428 defm rrib : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6429 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3),
6430 OpcodeStr, "$src3,{sae}, $src2, $src1",
6431 "$src1, $src2,{sae}, $src3",
6432 (OpNode (_.VT _.RC:$src1),
6435 (i32 FROUND_NO_EXC))>, EVEX_B;
6437 //handle scalar instruction reg_vec1 = op(reg_vec2,reg_vec3,imm),{sae}
6438 multiclass avx512_fp_sae_scalar_imm<bits<8> opc, string OpcodeStr,
6439 SDNode OpNode, X86VectorVTInfo _> {
6440 defm NAME#rrib : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
6441 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3),
6442 OpcodeStr, "$src3,{sae}, $src2, $src1",
6443 "$src1, $src2,{sae}, $src3",
6444 (OpNode (_.VT _.RC:$src1),
6447 (i32 FROUND_NO_EXC))>, EVEX_B;
6450 multiclass avx512_common_fp_sae_packed_imm<string OpcodeStr,
6451 AVX512VLVectorVTInfo _, bits<8> opc, SDNode OpNode, Predicate prd>{
6452 let Predicates = [prd] in {
6453 defm Z : avx512_fp_packed_imm<opc, OpcodeStr, OpNode, _.info512>,
6454 avx512_fp_sae_packed_imm<opc, OpcodeStr, OpNode, _.info512>,
6458 let Predicates = [prd, HasVLX] in {
6459 defm Z128 : avx512_fp_packed_imm<opc, OpcodeStr, OpNode, _.info128>,
6461 defm Z256 : avx512_fp_packed_imm<opc, OpcodeStr, OpNode, _.info256>,
6466 multiclass avx512_common_3Op_rm_imm8<bits<8> opc, SDNode OpNode, string OpStr,
6467 AVX512VLVectorVTInfo DestInfo, AVX512VLVectorVTInfo SrcInfo>{
6468 let Predicates = [HasBWI] in {
6469 defm Z : avx512_3Op_rm_imm8<opc, OpStr, OpNode, DestInfo.info512,
6470 SrcInfo.info512>, EVEX_V512, AVX512AIi8Base, EVEX_4V;
6472 let Predicates = [HasBWI, HasVLX] in {
6473 defm Z128 : avx512_3Op_rm_imm8<opc, OpStr, OpNode, DestInfo.info128,
6474 SrcInfo.info128>, EVEX_V128, AVX512AIi8Base, EVEX_4V;
6475 defm Z256 : avx512_3Op_rm_imm8<opc, OpStr, OpNode, DestInfo.info256,
6476 SrcInfo.info256>, EVEX_V256, AVX512AIi8Base, EVEX_4V;
6480 multiclass avx512_common_3Op_imm8<string OpcodeStr, AVX512VLVectorVTInfo _,
6481 bits<8> opc, SDNode OpNode>{
6482 let Predicates = [HasAVX512] in {
6483 defm Z : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
6485 let Predicates = [HasAVX512, HasVLX] in {
6486 defm Z128 : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info128>, EVEX_V128;
6487 defm Z256 : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
6491 multiclass avx512_common_fp_sae_scalar_imm<string OpcodeStr,
6492 X86VectorVTInfo _, bits<8> opc, SDNode OpNode, Predicate prd>{
6493 let Predicates = [prd] in {
6494 defm Z128 : avx512_fp_scalar_imm<opc, OpcodeStr, OpNode, _>,
6495 avx512_fp_sae_scalar_imm<opc, OpcodeStr, OpNode, _>;
6499 multiclass avx512_common_unary_fp_sae_packed_imm_all<string OpcodeStr,
6500 bits<8> opcPs, bits<8> opcPd, SDNode OpNode, Predicate prd>{
6501 defm PS : avx512_common_unary_fp_sae_packed_imm<OpcodeStr, avx512vl_f32_info,
6502 opcPs, OpNode, prd>, EVEX_CD8<32, CD8VF>;
6503 defm PD : avx512_common_unary_fp_sae_packed_imm<OpcodeStr, avx512vl_f64_info,
6504 opcPd, OpNode, prd>, EVEX_CD8<64, CD8VF>, VEX_W;
6507 defm VFIXUPIMMPD : avx512_common_fp_sae_packed_imm<"vfixupimmpd",
6508 avx512vl_f64_info, 0x54, X86VFixupimm, HasAVX512>,
6509 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
6510 defm VFIXUPIMMPS : avx512_common_fp_sae_packed_imm<"vfixupimmps",
6511 avx512vl_f32_info, 0x54, X86VFixupimm, HasAVX512>,
6512 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
6514 defm VFIXUPIMMSD: avx512_common_fp_sae_scalar_imm<"vfixupimmsd", f64x_info,
6515 0x55, X86VFixupimm, HasAVX512>,
6516 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
6517 defm VFIXUPIMMSS: avx512_common_fp_sae_scalar_imm<"vfixupimmss", f32x_info,
6518 0x55, X86VFixupimm, HasAVX512>,
6519 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>;
6521 defm VREDUCE : avx512_common_unary_fp_sae_packed_imm_all<"vreduce", 0x56, 0x56,
6522 X86VReduce, HasDQI>, AVX512AIi8Base, EVEX;
6523 defm VRNDSCALE : avx512_common_unary_fp_sae_packed_imm_all<"vrndscale", 0x08, 0x09,
6524 X86VRndScale, HasAVX512>, AVX512AIi8Base, EVEX;
6525 defm VGETMANT : avx512_common_unary_fp_sae_packed_imm_all<"vgetmant", 0x26, 0x26,
6526 X86VGetMant, HasAVX512>, AVX512AIi8Base, EVEX;
6529 defm VRANGEPD : avx512_common_fp_sae_packed_imm<"vrangepd", avx512vl_f64_info,
6530 0x50, X86VRange, HasDQI>,
6531 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
6532 defm VRANGEPS : avx512_common_fp_sae_packed_imm<"vrangeps", avx512vl_f32_info,
6533 0x50, X86VRange, HasDQI>,
6534 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
6536 defm VRANGESD: avx512_common_fp_sae_scalar_imm<"vrangesd", f64x_info,
6537 0x51, X86VRange, HasDQI>,
6538 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
6539 defm VRANGESS: avx512_common_fp_sae_scalar_imm<"vrangess", f32x_info,
6540 0x51, X86VRange, HasDQI>,
6541 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>;
6543 defm VREDUCESD: avx512_common_fp_sae_scalar_imm<"vreducesd", f64x_info,
6544 0x57, X86Reduces, HasDQI>,
6545 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
6546 defm VREDUCESS: avx512_common_fp_sae_scalar_imm<"vreducess", f32x_info,
6547 0x57, X86Reduces, HasDQI>,
6548 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>;
6550 defm VGETMANTSD: avx512_common_fp_sae_scalar_imm<"vgetmantsd", f64x_info,
6551 0x27, X86GetMants, HasAVX512>,
6552 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
6553 defm VGETMANTSS: avx512_common_fp_sae_scalar_imm<"vgetmantss", f32x_info,
6554 0x27, X86GetMants, HasAVX512>,
6555 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>;
6557 multiclass avx512_shuff_packed_128<string OpcodeStr, AVX512VLVectorVTInfo _,
6558 bits<8> opc, SDNode OpNode = X86Shuf128>{
6559 let Predicates = [HasAVX512] in {
6560 defm Z : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
6563 let Predicates = [HasAVX512, HasVLX] in {
6564 defm Z256 : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
6567 let Predicates = [HasAVX512] in {
6568 def : Pat<(v16f32 (ffloor VR512:$src)),
6569 (VRNDSCALEPSZrri VR512:$src, (i32 0x1))>;
6570 def : Pat<(v16f32 (fnearbyint VR512:$src)),
6571 (VRNDSCALEPSZrri VR512:$src, (i32 0xC))>;
6572 def : Pat<(v16f32 (fceil VR512:$src)),
6573 (VRNDSCALEPSZrri VR512:$src, (i32 0x2))>;
6574 def : Pat<(v16f32 (frint VR512:$src)),
6575 (VRNDSCALEPSZrri VR512:$src, (i32 0x4))>;
6576 def : Pat<(v16f32 (ftrunc VR512:$src)),
6577 (VRNDSCALEPSZrri VR512:$src, (i32 0x3))>;
6579 def : Pat<(v8f64 (ffloor VR512:$src)),
6580 (VRNDSCALEPDZrri VR512:$src, (i32 0x1))>;
6581 def : Pat<(v8f64 (fnearbyint VR512:$src)),
6582 (VRNDSCALEPDZrri VR512:$src, (i32 0xC))>;
6583 def : Pat<(v8f64 (fceil VR512:$src)),
6584 (VRNDSCALEPDZrri VR512:$src, (i32 0x2))>;
6585 def : Pat<(v8f64 (frint VR512:$src)),
6586 (VRNDSCALEPDZrri VR512:$src, (i32 0x4))>;
6587 def : Pat<(v8f64 (ftrunc VR512:$src)),
6588 (VRNDSCALEPDZrri VR512:$src, (i32 0x3))>;
6591 defm VSHUFF32X4 : avx512_shuff_packed_128<"vshuff32x4",avx512vl_f32_info, 0x23>,
6592 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
6593 defm VSHUFF64X2 : avx512_shuff_packed_128<"vshuff64x2",avx512vl_f64_info, 0x23>,
6594 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
6595 defm VSHUFI32X4 : avx512_shuff_packed_128<"vshufi32x4",avx512vl_i32_info, 0x43>,
6596 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
6597 defm VSHUFI64X2 : avx512_shuff_packed_128<"vshufi64x2",avx512vl_i64_info, 0x43>,
6598 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
6600 multiclass avx512_valign<string OpcodeStr, AVX512VLVectorVTInfo VTInfo_I,
6601 AVX512VLVectorVTInfo VTInfo_FP>{
6602 defm NAME: avx512_common_3Op_imm8<OpcodeStr, VTInfo_I, 0x03, X86VAlign>,
6603 AVX512AIi8Base, EVEX_4V;
6604 let isCodeGenOnly = 1 in {
6605 defm NAME#_FP: avx512_common_3Op_imm8<OpcodeStr, VTInfo_FP, 0x03, X86VAlign>,
6606 AVX512AIi8Base, EVEX_4V;
6610 defm VALIGND: avx512_valign<"valignd", avx512vl_i32_info, avx512vl_f32_info>,
6611 EVEX_CD8<32, CD8VF>;
6612 defm VALIGNQ: avx512_valign<"valignq", avx512vl_i64_info, avx512vl_f64_info>,
6613 EVEX_CD8<64, CD8VF>, VEX_W;
6615 multiclass avx512_vpalign_lowering<X86VectorVTInfo _ , list<Predicate> p>{
6616 let Predicates = p in
6617 def NAME#_.VTName#rri:
6618 Pat<(_.VT (X86PAlignr _.RC:$src1, _.RC:$src2, (i8 imm:$imm))),
6619 (!cast<Instruction>(NAME#_.ZSuffix#rri)
6620 _.RC:$src1, _.RC:$src2, imm:$imm)>;
6623 multiclass avx512_vpalign_lowering_common<AVX512VLVectorVTInfo _>:
6624 avx512_vpalign_lowering<_.info512, [HasBWI]>,
6625 avx512_vpalign_lowering<_.info128, [HasBWI, HasVLX]>,
6626 avx512_vpalign_lowering<_.info256, [HasBWI, HasVLX]>;
6628 defm VPALIGN: avx512_common_3Op_rm_imm8<0x0F, X86PAlignr, "vpalignr" ,
6629 avx512vl_i8_info, avx512vl_i8_info>,
6630 avx512_vpalign_lowering_common<avx512vl_i16_info>,
6631 avx512_vpalign_lowering_common<avx512vl_i32_info>,
6632 avx512_vpalign_lowering_common<avx512vl_f32_info>,
6633 avx512_vpalign_lowering_common<avx512vl_i64_info>,
6634 avx512_vpalign_lowering_common<avx512vl_f64_info>,
6637 defm VDBPSADBW: avx512_common_3Op_rm_imm8<0x42, X86dbpsadbw, "vdbpsadbw" ,
6638 avx512vl_i16_info, avx512vl_i8_info>, EVEX_CD8<8, CD8VF>;
6640 multiclass avx512_unary_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6641 X86VectorVTInfo _> {
6642 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6643 (ins _.RC:$src1), OpcodeStr##_.Suffix,
6645 (_.VT (OpNode _.RC:$src1))>, EVEX, AVX5128IBase;
6648 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6649 (ins _.MemOp:$src1), OpcodeStr##_.Suffix,
6651 (_.VT (OpNode (bitconvert (_.LdFrag addr:$src1))))>,
6652 EVEX, AVX5128IBase, EVEX_CD8<_.EltSize, CD8VF>;
6655 multiclass avx512_unary_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
6656 X86VectorVTInfo _> :
6657 avx512_unary_rm<opc, OpcodeStr, OpNode, _> {
6659 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6660 (ins _.ScalarMemOp:$src1), OpcodeStr##_.Suffix,
6661 "${src1}"##_.BroadcastStr,
6662 "${src1}"##_.BroadcastStr,
6663 (_.VT (OpNode (X86VBroadcast
6664 (_.ScalarLdFrag addr:$src1))))>,
6665 EVEX, AVX5128IBase, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
6668 multiclass avx512_unary_rm_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
6669 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
6670 let Predicates = [prd] in
6671 defm Z : avx512_unary_rm<opc, OpcodeStr, OpNode, VTInfo.info512>, EVEX_V512;
6673 let Predicates = [prd, HasVLX] in {
6674 defm Z256 : avx512_unary_rm<opc, OpcodeStr, OpNode, VTInfo.info256>,
6676 defm Z128 : avx512_unary_rm<opc, OpcodeStr, OpNode, VTInfo.info128>,
6681 multiclass avx512_unary_rmb_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
6682 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
6683 let Predicates = [prd] in
6684 defm Z : avx512_unary_rmb<opc, OpcodeStr, OpNode, VTInfo.info512>,
6687 let Predicates = [prd, HasVLX] in {
6688 defm Z256 : avx512_unary_rmb<opc, OpcodeStr, OpNode, VTInfo.info256>,
6690 defm Z128 : avx512_unary_rmb<opc, OpcodeStr, OpNode, VTInfo.info128>,
6695 multiclass avx512_unary_rm_vl_dq<bits<8> opc_d, bits<8> opc_q, string OpcodeStr,
6696 SDNode OpNode, Predicate prd> {
6697 defm Q : avx512_unary_rmb_vl<opc_q, OpcodeStr, OpNode, avx512vl_i64_info,
6699 defm D : avx512_unary_rmb_vl<opc_d, OpcodeStr, OpNode, avx512vl_i32_info, prd>;
6702 multiclass avx512_unary_rm_vl_bw<bits<8> opc_b, bits<8> opc_w, string OpcodeStr,
6703 SDNode OpNode, Predicate prd> {
6704 defm W : avx512_unary_rm_vl<opc_w, OpcodeStr, OpNode, avx512vl_i16_info, prd>;
6705 defm B : avx512_unary_rm_vl<opc_b, OpcodeStr, OpNode, avx512vl_i8_info, prd>;
6708 multiclass avx512_unary_rm_vl_all<bits<8> opc_b, bits<8> opc_w,
6709 bits<8> opc_d, bits<8> opc_q,
6710 string OpcodeStr, SDNode OpNode> {
6711 defm NAME : avx512_unary_rm_vl_dq<opc_d, opc_q, OpcodeStr, OpNode,
6713 avx512_unary_rm_vl_bw<opc_b, opc_w, OpcodeStr, OpNode,
6717 defm VPABS : avx512_unary_rm_vl_all<0x1C, 0x1D, 0x1E, 0x1F, "vpabs", X86Abs>;
6720 (bc_v16i32 (v16i1sextv16i32)),
6721 (bc_v16i32 (add (v16i32 VR512:$src), (v16i1sextv16i32)))),
6722 (VPABSDZrr VR512:$src)>;
6724 (bc_v8i64 (v8i1sextv8i64)),
6725 (bc_v8i64 (add (v8i64 VR512:$src), (v8i1sextv8i64)))),
6726 (VPABSQZrr VR512:$src)>;
6728 multiclass avx512_ctlz<bits<8> opc, string OpcodeStr, Predicate prd>{
6730 defm NAME : avx512_unary_rm_vl_dq<opc, opc, OpcodeStr, ctlz, prd>;
6731 let isCodeGenOnly = 1 in
6732 defm NAME#_UNDEF : avx512_unary_rm_vl_dq<opc, opc, OpcodeStr,
6733 ctlz_zero_undef, prd>;
6736 defm VPLZCNT : avx512_ctlz<0x44, "vplzcnt", HasCDI>;
6737 defm VPCONFLICT : avx512_unary_rm_vl_dq<0xC4, 0xC4, "vpconflict", X86Conflict, HasCDI>;
6739 //===----------------------------------------------------------------------===//
6740 // AVX-512 - Unpack Instructions
6741 //===----------------------------------------------------------------------===//
6742 defm VUNPCKH : avx512_fp_binop_p<0x15, "vunpckh", X86Unpckh>;
6743 defm VUNPCKL : avx512_fp_binop_p<0x14, "vunpckl", X86Unpckl>;
6745 defm VPUNPCKLBW : avx512_binop_rm_vl_b<0x60, "vpunpcklbw", X86Unpckl,
6746 SSE_INTALU_ITINS_P, HasBWI>;
6747 defm VPUNPCKHBW : avx512_binop_rm_vl_b<0x68, "vpunpckhbw", X86Unpckh,
6748 SSE_INTALU_ITINS_P, HasBWI>;
6749 defm VPUNPCKLWD : avx512_binop_rm_vl_w<0x61, "vpunpcklwd", X86Unpckl,
6750 SSE_INTALU_ITINS_P, HasBWI>;
6751 defm VPUNPCKHWD : avx512_binop_rm_vl_w<0x69, "vpunpckhwd", X86Unpckh,
6752 SSE_INTALU_ITINS_P, HasBWI>;
6754 defm VPUNPCKLDQ : avx512_binop_rm_vl_d<0x62, "vpunpckldq", X86Unpckl,
6755 SSE_INTALU_ITINS_P, HasAVX512>;
6756 defm VPUNPCKHDQ : avx512_binop_rm_vl_d<0x6A, "vpunpckhdq", X86Unpckh,
6757 SSE_INTALU_ITINS_P, HasAVX512>;
6758 defm VPUNPCKLQDQ : avx512_binop_rm_vl_q<0x6C, "vpunpcklqdq", X86Unpckl,
6759 SSE_INTALU_ITINS_P, HasAVX512>;
6760 defm VPUNPCKHQDQ : avx512_binop_rm_vl_q<0x6D, "vpunpckhqdq", X86Unpckh,
6761 SSE_INTALU_ITINS_P, HasAVX512>;
6762 //===----------------------------------------------------------------------===//
6763 // VSHUFPS - VSHUFPD Operations
6764 //===----------------------------------------------------------------------===//
6765 multiclass avx512_shufp<string OpcodeStr, AVX512VLVectorVTInfo VTInfo_I,
6766 AVX512VLVectorVTInfo VTInfo_FP>{
6767 defm NAME: avx512_common_3Op_imm8<OpcodeStr, VTInfo_FP, 0xC6, X86Shufp>,
6768 EVEX_CD8<VTInfo_FP.info512.EltSize, CD8VF>,
6769 AVX512AIi8Base, EVEX_4V;
6770 let isCodeGenOnly = 1 in {
6771 defm NAME#_I: avx512_common_3Op_imm8<OpcodeStr, VTInfo_I, 0xC6, X86Shufp>,
6772 EVEX_CD8<VTInfo_I.info512.EltSize, CD8VF>,
6773 AVX512AIi8Base, EVEX_4V;
6777 defm VSHUFPS: avx512_shufp<"vshufps", avx512vl_i32_info, avx512vl_f32_info>, PS;
6778 defm VSHUFPD: avx512_shufp<"vshufpd", avx512vl_i64_info, avx512vl_f64_info>, PD, VEX_W;
6779 //===----------------------------------------------------------------------===//
6780 // AVX-512 - Byte shift Left/Right
6781 //===----------------------------------------------------------------------===//
6783 multiclass avx512_shift_packed<bits<8> opc, SDNode OpNode, Format MRMr,
6784 Format MRMm, string OpcodeStr, X86VectorVTInfo _>{
6785 def rr : AVX512<opc, MRMr,
6786 (outs _.RC:$dst), (ins _.RC:$src1, u8imm:$src2),
6787 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6788 [(set _.RC:$dst,(_.VT (OpNode _.RC:$src1, (i8 imm:$src2))))]>;
6790 def rm : AVX512<opc, MRMm,
6791 (outs _.RC:$dst), (ins _.MemOp:$src1, u8imm:$src2),
6792 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6793 [(set _.RC:$dst,(_.VT (OpNode
6794 (_.LdFrag addr:$src1), (i8 imm:$src2))))]>;
6797 multiclass avx512_shift_packed_all<bits<8> opc, SDNode OpNode, Format MRMr,
6798 Format MRMm, string OpcodeStr, Predicate prd>{
6799 let Predicates = [prd] in
6800 defm Z512 : avx512_shift_packed<opc, OpNode, MRMr, MRMm,
6801 OpcodeStr, v8i64_info>, EVEX_V512;
6802 let Predicates = [prd, HasVLX] in {
6803 defm Z256 : avx512_shift_packed<opc, OpNode, MRMr, MRMm,
6804 OpcodeStr, v4i64x_info>, EVEX_V256;
6805 defm Z128 : avx512_shift_packed<opc, OpNode, MRMr, MRMm,
6806 OpcodeStr, v2i64x_info>, EVEX_V128;
6809 defm VPSLLDQ : avx512_shift_packed_all<0x73, X86vshldq, MRM7r, MRM7m, "vpslldq",
6810 HasBWI>, AVX512PDIi8Base, EVEX_4V;
6811 defm VPSRLDQ : avx512_shift_packed_all<0x73, X86vshrdq, MRM3r, MRM3m, "vpsrldq",
6812 HasBWI>, AVX512PDIi8Base, EVEX_4V;
6815 multiclass avx512_psadbw_packed<bits<8> opc, SDNode OpNode,
6816 string OpcodeStr, X86VectorVTInfo _src>{
6817 def rr : AVX512BI<opc, MRMSrcReg,
6818 (outs _src.RC:$dst), (ins _src.RC:$src1, _src.RC:$src2),
6819 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6820 [(set _src.RC:$dst,(_src.VT
6821 (OpNode _src.RC:$src1, _src.RC:$src2)))]>;
6823 def rm : AVX512BI<opc, MRMSrcMem,
6824 (outs _src.RC:$dst), (ins _src.RC:$src1, _src.MemOp:$src2),
6825 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6826 [(set _src.RC:$dst,(_src.VT
6827 (OpNode _src.RC:$src1,
6828 (_src.VT (bitconvert
6829 (_src.LdFrag addr:$src2))))))]>;
6832 multiclass avx512_psadbw_packed_all<bits<8> opc, SDNode OpNode,
6833 string OpcodeStr, Predicate prd> {
6834 let Predicates = [prd] in
6835 defm Z512 : avx512_psadbw_packed<opc, OpNode, OpcodeStr, v64i8_info>,
6837 let Predicates = [prd, HasVLX] in {
6838 defm Z256 : avx512_psadbw_packed<opc, OpNode, OpcodeStr, v32i8x_info>,
6840 defm Z128 : avx512_psadbw_packed<opc, OpNode, OpcodeStr, v16i8x_info>,
6845 defm VPSADBW : avx512_psadbw_packed_all<0xf6, X86psadbw, "vpsadbw",