1 // Bitcasts between 512-bit vector types. Return the original type since
2 // no instruction is needed for the conversion
3 let Predicates = [HasAVX512] in {
4 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
5 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
6 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
7 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
8 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
9 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
10 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
11 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
12 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
13 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
14 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
15 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
16 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
18 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
19 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
20 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
21 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
22 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
23 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
24 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
25 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
26 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
27 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
28 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
29 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
30 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
31 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
32 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
33 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
34 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
35 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
36 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
37 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
38 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
39 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
40 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
41 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
42 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
43 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
44 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
45 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
46 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
47 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
49 // Bitcasts between 256-bit vector types. Return the original type since
50 // no instruction is needed for the conversion
51 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
52 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
53 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
54 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
55 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
56 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
57 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
58 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
59 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
60 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
61 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
62 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
63 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
64 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
65 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
66 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
67 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
68 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
69 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
70 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
71 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
72 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
73 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
74 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
75 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
76 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
77 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
78 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
79 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
80 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
84 // AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
87 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
88 isPseudo = 1, Predicates = [HasAVX512] in {
89 def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
90 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
93 def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
94 def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
95 def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
96 def : Pat<(v16f32 immAllZerosV), (AVX512_512_SET0)>;
98 //===----------------------------------------------------------------------===//
99 // AVX-512 - VECTOR INSERT
102 let hasSideEffects = 0, ExeDomain = SSEPackedSingle in {
103 def VINSERTF32x4rr : AVX512AIi8<0x18, MRMSrcReg, (outs VR512:$dst),
104 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
105 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
106 []>, EVEX_4V, EVEX_V512;
108 def VINSERTF32x4rm : AVX512AIi8<0x18, MRMSrcMem, (outs VR512:$dst),
109 (ins VR512:$src1, f128mem:$src2, i8imm:$src3),
110 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
111 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
114 // -- 64x4 fp form --
115 let hasSideEffects = 0, ExeDomain = SSEPackedDouble in {
116 def VINSERTF64x4rr : AVX512AIi8<0x1a, MRMSrcReg, (outs VR512:$dst),
117 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
118 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
119 []>, EVEX_4V, EVEX_V512, VEX_W;
121 def VINSERTF64x4rm : AVX512AIi8<0x1a, MRMSrcMem, (outs VR512:$dst),
122 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
123 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
124 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
126 // -- 32x4 integer form --
127 let hasSideEffects = 0 in {
128 def VINSERTI32x4rr : AVX512AIi8<0x38, MRMSrcReg, (outs VR512:$dst),
129 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
130 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
131 []>, EVEX_4V, EVEX_V512;
133 def VINSERTI32x4rm : AVX512AIi8<0x38, MRMSrcMem, (outs VR512:$dst),
134 (ins VR512:$src1, i128mem:$src2, i8imm:$src3),
135 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
136 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
140 let hasSideEffects = 0 in {
142 def VINSERTI64x4rr : AVX512AIi8<0x3a, MRMSrcReg, (outs VR512:$dst),
143 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
144 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
145 []>, EVEX_4V, EVEX_V512, VEX_W;
147 def VINSERTI64x4rm : AVX512AIi8<0x3a, MRMSrcMem, (outs VR512:$dst),
148 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
149 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
150 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
153 def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (v4f32 VR128X:$src2),
154 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
155 (INSERT_get_vinsert128_imm VR512:$ins))>;
156 def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (v2f64 VR128X:$src2),
157 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
158 (INSERT_get_vinsert128_imm VR512:$ins))>;
159 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v2i64 VR128X:$src2),
160 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
161 (INSERT_get_vinsert128_imm VR512:$ins))>;
162 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v4i32 VR128X:$src2),
163 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
164 (INSERT_get_vinsert128_imm VR512:$ins))>;
166 def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (loadv4f32 addr:$src2),
167 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
168 (INSERT_get_vinsert128_imm VR512:$ins))>;
169 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1),
170 (bc_v4i32 (loadv2i64 addr:$src2)),
171 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
172 (INSERT_get_vinsert128_imm VR512:$ins))>;
173 def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (loadv2f64 addr:$src2),
174 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
175 (INSERT_get_vinsert128_imm VR512:$ins))>;
176 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (loadv2i64 addr:$src2),
177 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
178 (INSERT_get_vinsert128_imm VR512:$ins))>;
180 def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (v8f32 VR256X:$src2),
181 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
182 (INSERT_get_vinsert256_imm VR512:$ins))>;
183 def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (v4f64 VR256X:$src2),
184 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
185 (INSERT_get_vinsert256_imm VR512:$ins))>;
186 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v4i64 VR256X:$src2),
187 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
188 (INSERT_get_vinsert256_imm VR512:$ins))>;
189 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v8i32 VR256X:$src2),
190 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
191 (INSERT_get_vinsert256_imm VR512:$ins))>;
193 def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (loadv8f32 addr:$src2),
194 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
195 (INSERT_get_vinsert256_imm VR512:$ins))>;
196 def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (loadv4f64 addr:$src2),
197 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
198 (INSERT_get_vinsert256_imm VR512:$ins))>;
199 def : Pat<(vinsert256_insert:$ins (v8i64 VR512:$src1), (loadv4i64 addr:$src2),
200 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
201 (INSERT_get_vinsert256_imm VR512:$ins))>;
202 def : Pat<(vinsert256_insert:$ins (v16i32 VR512:$src1),
203 (bc_v8i32 (loadv4i64 addr:$src2)),
204 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
205 (INSERT_get_vinsert256_imm VR512:$ins))>;
207 // vinsertps - insert f32 to XMM
208 def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
209 (ins VR128X:$src1, VR128X:$src2, u32u8imm:$src3),
210 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
211 [(set VR128X:$dst, (X86insrtps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
213 def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
214 (ins VR128X:$src1, f32mem:$src2, u32u8imm:$src3),
215 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
216 [(set VR128X:$dst, (X86insrtps VR128X:$src1,
217 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
218 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
220 //===----------------------------------------------------------------------===//
221 // AVX-512 VECTOR EXTRACT
223 let hasSideEffects = 0, ExeDomain = SSEPackedSingle in {
225 def VEXTRACTF32x4rr : AVX512AIi8<0x19, MRMDestReg, (outs VR128X:$dst),
226 (ins VR512:$src1, i8imm:$src2),
227 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
228 []>, EVEX, EVEX_V512;
229 def VEXTRACTF32x4mr : AVX512AIi8<0x19, MRMDestMem, (outs),
230 (ins f128mem:$dst, VR512:$src1, i8imm:$src2),
231 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
232 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
235 def VEXTRACTF64x4rr : AVX512AIi8<0x1b, MRMDestReg, (outs VR256X:$dst),
236 (ins VR512:$src1, i8imm:$src2),
237 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
238 []>, EVEX, EVEX_V512, VEX_W;
240 def VEXTRACTF64x4mr : AVX512AIi8<0x1b, MRMDestMem, (outs),
241 (ins f256mem:$dst, VR512:$src1, i8imm:$src2),
242 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
243 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
246 let hasSideEffects = 0 in {
248 def VEXTRACTI32x4rr : AVX512AIi8<0x39, MRMDestReg, (outs VR128X:$dst),
249 (ins VR512:$src1, i8imm:$src2),
250 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
251 []>, EVEX, EVEX_V512;
252 def VEXTRACTI32x4mr : AVX512AIi8<0x39, MRMDestMem, (outs),
253 (ins i128mem:$dst, VR512:$src1, i8imm:$src2),
254 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
255 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
258 def VEXTRACTI64x4rr : AVX512AIi8<0x3b, MRMDestReg, (outs VR256X:$dst),
259 (ins VR512:$src1, i8imm:$src2),
260 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
261 []>, EVEX, EVEX_V512, VEX_W;
263 def VEXTRACTI64x4mr : AVX512AIi8<0x3b, MRMDestMem, (outs),
264 (ins i256mem:$dst, VR512:$src1, i8imm:$src2),
265 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
266 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
269 def : Pat<(vextract128_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
270 (v4f32 (VEXTRACTF32x4rr VR512:$src1,
271 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
273 def : Pat<(vextract128_extract:$ext VR512:$src1, (iPTR imm)),
274 (v4i32 (VEXTRACTF32x4rr VR512:$src1,
275 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
277 def : Pat<(vextract128_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
278 (v2f64 (VEXTRACTF32x4rr VR512:$src1,
279 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
281 def : Pat<(vextract128_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
282 (v2i64 (VEXTRACTI32x4rr VR512:$src1,
283 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
286 def : Pat<(vextract256_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
287 (v8f32 (VEXTRACTF64x4rr VR512:$src1,
288 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
290 def : Pat<(vextract256_extract:$ext (v16i32 VR512:$src1), (iPTR imm)),
291 (v8i32 (VEXTRACTI64x4rr VR512:$src1,
292 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
294 def : Pat<(vextract256_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
295 (v4f64 (VEXTRACTF64x4rr VR512:$src1,
296 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
298 def : Pat<(vextract256_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
299 (v4i64 (VEXTRACTI64x4rr VR512:$src1,
300 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
302 // A 256-bit subvector extract from the first 512-bit vector position
303 // is a subregister copy that needs no instruction.
304 def : Pat<(v8i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
305 (v8i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_ymm))>;
306 def : Pat<(v8f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
307 (v8f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_ymm))>;
308 def : Pat<(v4i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
309 (v4i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_ymm))>;
310 def : Pat<(v4f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
311 (v4f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_ymm))>;
314 def : Pat<(v4i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
315 (v4i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm))>;
316 def : Pat<(v2i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
317 (v2i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm))>;
318 def : Pat<(v2f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
319 (v2f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
320 def : Pat<(v4f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
321 (v4f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
324 // A 128-bit subvector insert to the first 512-bit vector position
325 // is a subregister copy that needs no instruction.
326 def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
327 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
328 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
330 def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
331 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
332 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
334 def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
335 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
336 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
338 def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
339 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
340 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
343 def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
344 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
345 def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
346 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
347 def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
348 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
349 def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
350 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
352 // vextractps - extract 32 bits from XMM
353 def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
354 (ins VR128X:$src1, u32u8imm:$src2),
355 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
356 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
359 def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
360 (ins f32mem:$dst, VR128X:$src1, u32u8imm:$src2),
361 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
362 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
365 //===---------------------------------------------------------------------===//
368 multiclass avx512_fp_broadcast<bits<8> opc, string OpcodeStr,
369 RegisterClass DestRC,
370 RegisterClass SrcRC, X86MemOperand x86memop> {
371 def rr : AVX5128I<opc, MRMSrcReg, (outs DestRC:$dst), (ins SrcRC:$src),
372 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
374 def rm : AVX5128I<opc, MRMSrcMem, (outs DestRC:$dst), (ins x86memop:$src),
375 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),[]>, EVEX;
377 let ExeDomain = SSEPackedSingle in {
378 defm VBROADCASTSSZ : avx512_fp_broadcast<0x18, "vbroadcastss", VR512,
380 EVEX_V512, EVEX_CD8<32, CD8VT1>;
383 let ExeDomain = SSEPackedDouble in {
384 defm VBROADCASTSDZ : avx512_fp_broadcast<0x19, "vbroadcastsd", VR512,
386 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
389 def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
390 (VBROADCASTSSZrm addr:$src)>;
391 def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
392 (VBROADCASTSDZrm addr:$src)>;
394 def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
395 (VBROADCASTSSZrm addr:$src)>;
396 def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
397 (VBROADCASTSDZrm addr:$src)>;
399 multiclass avx512_int_broadcast_reg<bits<8> opc, string OpcodeStr,
400 RegisterClass SrcRC, RegisterClass KRC> {
401 def Zrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins SrcRC:$src),
402 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
403 []>, EVEX, EVEX_V512;
404 def Zkrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst),
405 (ins KRC:$mask, SrcRC:$src),
406 !strconcat(OpcodeStr,
407 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
408 []>, EVEX, EVEX_V512, EVEX_KZ;
411 defm VPBROADCASTDr : avx512_int_broadcast_reg<0x7C, "vpbroadcastd", GR32, VK16WM>;
412 defm VPBROADCASTQr : avx512_int_broadcast_reg<0x7C, "vpbroadcastq", GR64, VK8WM>,
415 def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
416 (VPBROADCASTDrZkrr VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
418 def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
419 (VPBROADCASTQrZkrr VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
421 def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
422 (VPBROADCASTDrZrr GR32:$src)>;
423 def : Pat<(v16i32 (X86VBroadcastm VK16WM:$mask, (i32 GR32:$src))),
424 (VPBROADCASTDrZkrr VK16WM:$mask, GR32:$src)>;
425 def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
426 (VPBROADCASTQrZrr GR64:$src)>;
427 def : Pat<(v8i64 (X86VBroadcastm VK8WM:$mask, (i64 GR64:$src))),
428 (VPBROADCASTQrZkrr VK8WM:$mask, GR64:$src)>;
430 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_i32_512 (i32 GR32:$src))),
431 (VPBROADCASTDrZrr GR32:$src)>;
432 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_i64_512 (i64 GR64:$src))),
433 (VPBROADCASTQrZrr GR64:$src)>;
435 def : Pat<(v16i32 (int_x86_avx512_mask_pbroadcast_d_gpr_512 (i32 GR32:$src),
436 (v16i32 immAllZerosV), (i16 GR16:$mask))),
437 (VPBROADCASTDrZkrr (COPY_TO_REGCLASS GR16:$mask, VK16WM), GR32:$src)>;
438 def : Pat<(v8i64 (int_x86_avx512_mask_pbroadcast_q_gpr_512 (i64 GR64:$src),
439 (bc_v8i64 (v16i32 immAllZerosV)), (i8 GR8:$mask))),
440 (VPBROADCASTQrZkrr (COPY_TO_REGCLASS GR8:$mask, VK8WM), GR64:$src)>;
442 multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr,
443 X86MemOperand x86memop, PatFrag ld_frag,
444 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
446 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
447 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
449 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
450 def krr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
452 !strconcat(OpcodeStr,
453 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
455 (OpVT (X86VBroadcastm KRC:$mask, (SrcVT VR128X:$src))))]>,
458 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
459 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
461 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
462 def krm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
464 !strconcat(OpcodeStr,
465 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
466 [(set DstRC:$dst, (OpVT (X86VBroadcastm KRC:$mask,
467 (ld_frag addr:$src))))]>, EVEX, EVEX_KZ;
471 defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem,
472 loadi32, VR512, v16i32, v4i32, VK16WM>,
473 EVEX_V512, EVEX_CD8<32, CD8VT1>;
474 defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem,
475 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W,
476 EVEX_CD8<64, CD8VT1>;
478 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_512 (v4i32 VR128X:$src))),
479 (VPBROADCASTDZrr VR128X:$src)>;
480 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_512 (v2i64 VR128X:$src))),
481 (VPBROADCASTQZrr VR128X:$src)>;
483 def : Pat<(v16f32 (X86VBroadcast (v4f32 VR128X:$src))),
484 (VBROADCASTSSZrr VR128X:$src)>;
485 def : Pat<(v8f64 (X86VBroadcast (v2f64 VR128X:$src))),
486 (VBROADCASTSDZrr VR128X:$src)>;
488 def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))),
489 (VBROADCASTSSZrr VR128X:$src)>;
490 def : Pat<(v8f64 (int_x86_avx512_vbroadcast_sd_pd_512 (v2f64 VR128X:$src))),
491 (VBROADCASTSDZrr VR128X:$src)>;
493 // Provide fallback in case the load node that is used in the patterns above
494 // is used by additional users, which prevents the pattern selection.
495 def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
496 (VBROADCASTSSZrr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
497 def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
498 (VBROADCASTSDZrr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
501 let Predicates = [HasAVX512] in {
502 def : Pat<(v8i32 (X86VBroadcastm (v8i1 VK8WM:$mask), (loadi32 addr:$src))),
504 (v16i32 (VPBROADCASTDZkrm (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
505 addr:$src)), sub_ymm)>;
507 //===----------------------------------------------------------------------===//
508 // AVX-512 BROADCAST MASK TO VECTOR REGISTER
511 multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
512 RegisterClass DstRC, RegisterClass KRC,
513 ValueType OpVT, ValueType SrcVT> {
514 def rr : AVX512XS8I<opc, MRMDestReg, (outs DstRC:$dst), (ins KRC:$src),
515 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
519 defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d", VR512,
520 VK16, v16i32, v16i1>, EVEX_V512;
521 defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q", VR512,
522 VK8, v8i64, v8i1>, EVEX_V512, VEX_W;
524 //===----------------------------------------------------------------------===//
527 // -- immediate form --
528 multiclass avx512_perm_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
529 SDNode OpNode, PatFrag mem_frag,
530 X86MemOperand x86memop, ValueType OpVT> {
531 def ri : AVX512AIi8<opc, MRMSrcReg, (outs RC:$dst),
532 (ins RC:$src1, i8imm:$src2),
533 !strconcat(OpcodeStr,
534 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
536 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
538 def mi : AVX512AIi8<opc, MRMSrcMem, (outs RC:$dst),
539 (ins x86memop:$src1, i8imm:$src2),
540 !strconcat(OpcodeStr,
541 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
543 (OpVT (OpNode (mem_frag addr:$src1),
544 (i8 imm:$src2))))]>, EVEX;
547 defm VPERMQZ : avx512_perm_imm<0x00, "vpermq", VR512, X86VPermi, memopv8i64,
548 i512mem, v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
549 let ExeDomain = SSEPackedDouble in
550 defm VPERMPDZ : avx512_perm_imm<0x01, "vpermpd", VR512, X86VPermi, memopv8f64,
551 f512mem, v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
553 // -- VPERM - register form --
554 multiclass avx512_perm<bits<8> opc, string OpcodeStr, RegisterClass RC,
555 PatFrag mem_frag, X86MemOperand x86memop, ValueType OpVT> {
557 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
558 (ins RC:$src1, RC:$src2),
559 !strconcat(OpcodeStr,
560 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
562 (OpVT (X86VPermv RC:$src1, RC:$src2)))]>, EVEX_4V;
564 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
565 (ins RC:$src1, x86memop:$src2),
566 !strconcat(OpcodeStr,
567 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
569 (OpVT (X86VPermv RC:$src1, (mem_frag addr:$src2))))]>,
573 defm VPERMDZ : avx512_perm<0x36, "vpermd", VR512, memopv16i32, i512mem,
574 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
575 defm VPERMQZ : avx512_perm<0x36, "vpermq", VR512, memopv8i64, i512mem,
576 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
577 let ExeDomain = SSEPackedSingle in
578 defm VPERMPSZ : avx512_perm<0x16, "vpermps", VR512, memopv16f32, f512mem,
579 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
580 let ExeDomain = SSEPackedDouble in
581 defm VPERMPDZ : avx512_perm<0x16, "vpermpd", VR512, memopv8f64, f512mem,
582 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
584 // -- VPERM2I - 3 source operands form --
585 multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr, RegisterClass RC,
586 PatFrag mem_frag, X86MemOperand x86memop,
587 SDNode OpNode, ValueType OpVT> {
588 let Constraints = "$src1 = $dst" in {
589 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
590 (ins RC:$src1, RC:$src2, RC:$src3),
591 !strconcat(OpcodeStr,
592 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
594 (OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)))]>,
597 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
598 (ins RC:$src1, RC:$src2, x86memop:$src3),
599 !strconcat(OpcodeStr,
600 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
602 (OpVT (OpNode RC:$src1, RC:$src2,
603 (mem_frag addr:$src3))))]>, EVEX_4V;
606 defm VPERMI2D : avx512_perm_3src<0x76, "vpermi2d", VR512, memopv16i32, i512mem,
607 X86VPermiv3, v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
608 defm VPERMI2Q : avx512_perm_3src<0x76, "vpermi2q", VR512, memopv8i64, i512mem,
609 X86VPermiv3, v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
610 defm VPERMI2PS : avx512_perm_3src<0x77, "vpermi2ps", VR512, memopv16f32, i512mem,
611 X86VPermiv3, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
612 defm VPERMI2PD : avx512_perm_3src<0x77, "vpermi2pd", VR512, memopv8f64, i512mem,
613 X86VPermiv3, v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
615 defm VPERM2D : avx512_perm_3src<0x7E, "vperm2d", VR512, memopv16i32, i512mem,
616 X86VPermv3, v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
617 defm VPERM2Q : avx512_perm_3src<0x7E, "vperm2q", VR512, memopv8i64, i512mem,
618 X86VPermv3, v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
619 defm VPERM2PS : avx512_perm_3src<0x7F, "vperm2ps", VR512, memopv16f32, i512mem,
620 X86VPermv3, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
621 defm VPERM2PD : avx512_perm_3src<0x7F, "vperm2pd", VR512, memopv8f64, i512mem,
622 X86VPermv3, v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
623 //===----------------------------------------------------------------------===//
624 // AVX-512 - BLEND using mask
626 multiclass avx512_blendmask<bits<8> opc, string OpcodeStr,
627 RegisterClass KRC, RegisterClass RC,
628 X86MemOperand x86memop, PatFrag mem_frag,
629 SDNode OpNode, ValueType vt> {
630 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
631 (ins KRC:$mask, RC:$src1, RC:$src2),
632 !strconcat(OpcodeStr,
633 " \t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
634 [(set RC:$dst, (OpNode KRC:$mask, (vt RC:$src2),
635 (vt RC:$src1)))]>, EVEX_4V, EVEX_K;
637 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
638 (ins KRC:$mask, RC:$src1, x86memop:$src2),
639 !strconcat(OpcodeStr,
640 " \t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
641 []>, EVEX_4V, EVEX_K;
644 let ExeDomain = SSEPackedSingle in
645 defm VBLENDMPSZ : avx512_blendmask<0x65, "vblendmps",
646 VK16WM, VR512, f512mem,
647 memopv16f32, vselect, v16f32>,
648 EVEX_CD8<32, CD8VF>, EVEX_V512;
649 let ExeDomain = SSEPackedDouble in
650 defm VBLENDMPDZ : avx512_blendmask<0x65, "vblendmpd",
651 VK8WM, VR512, f512mem,
652 memopv8f64, vselect, v8f64>,
653 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
655 def : Pat<(v16f32 (int_x86_avx512_mask_blend_ps_512 (v16f32 VR512:$src1),
656 (v16f32 VR512:$src2), (i16 GR16:$mask))),
657 (VBLENDMPSZrr (COPY_TO_REGCLASS GR16:$mask, VK16WM),
658 VR512:$src1, VR512:$src2)>;
660 def : Pat<(v8f64 (int_x86_avx512_mask_blend_pd_512 (v8f64 VR512:$src1),
661 (v8f64 VR512:$src2), (i8 GR8:$mask))),
662 (VBLENDMPDZrr (COPY_TO_REGCLASS GR8:$mask, VK8WM),
663 VR512:$src1, VR512:$src2)>;
665 defm VPBLENDMDZ : avx512_blendmask<0x64, "vpblendmd",
666 VK16WM, VR512, f512mem,
667 memopv16i32, vselect, v16i32>,
668 EVEX_CD8<32, CD8VF>, EVEX_V512;
670 defm VPBLENDMQZ : avx512_blendmask<0x64, "vpblendmq",
671 VK8WM, VR512, f512mem,
672 memopv8i64, vselect, v8i64>,
673 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
675 def : Pat<(v16i32 (int_x86_avx512_mask_blend_d_512 (v16i32 VR512:$src1),
676 (v16i32 VR512:$src2), (i16 GR16:$mask))),
677 (VPBLENDMDZrr (COPY_TO_REGCLASS GR16:$mask, VK16),
678 VR512:$src1, VR512:$src2)>;
680 def : Pat<(v8i64 (int_x86_avx512_mask_blend_q_512 (v8i64 VR512:$src1),
681 (v8i64 VR512:$src2), (i8 GR8:$mask))),
682 (VPBLENDMQZrr (COPY_TO_REGCLASS GR8:$mask, VK8),
683 VR512:$src1, VR512:$src2)>;
685 let Predicates = [HasAVX512] in {
686 def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
687 (v8f32 VR256X:$src2))),
689 (v16f32 (VBLENDMPSZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
690 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
691 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
693 def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
694 (v8i32 VR256X:$src2))),
696 (v16i32 (VPBLENDMDZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
697 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
698 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
700 //===----------------------------------------------------------------------===//
701 // Compare Instructions
702 //===----------------------------------------------------------------------===//
704 // avx512_cmp_scalar - AVX512 CMPSS and CMPSD
705 multiclass avx512_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
706 Operand CC, SDNode OpNode, ValueType VT,
707 PatFrag ld_frag, string asm, string asm_alt> {
708 def rr : AVX512Ii8<0xC2, MRMSrcReg,
709 (outs VK1:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
710 [(set VK1:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
711 IIC_SSE_ALU_F32S_RR>, EVEX_4V;
712 def rm : AVX512Ii8<0xC2, MRMSrcMem,
713 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
714 [(set VK1:$dst, (OpNode (VT RC:$src1),
715 (ld_frag addr:$src2), imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
716 let isAsmParserOnly = 1, hasSideEffects = 0 in {
717 def rri_alt : AVX512Ii8<0xC2, MRMSrcReg,
718 (outs VK1:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
719 asm_alt, [], IIC_SSE_ALU_F32S_RR>, EVEX_4V;
720 def rmi_alt : AVX512Ii8<0xC2, MRMSrcMem,
721 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
722 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
726 let Predicates = [HasAVX512] in {
727 defm VCMPSSZ : avx512_cmp_scalar<FR32X, f32mem, AVXCC, X86cmpms, f32, loadf32,
728 "vcmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
729 "vcmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
731 defm VCMPSDZ : avx512_cmp_scalar<FR64X, f64mem, AVXCC, X86cmpms, f64, loadf64,
732 "vcmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
733 "vcmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
737 multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, RegisterClass KRC,
738 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
739 SDNode OpNode, ValueType vt> {
740 def rr : AVX512BI<opc, MRMSrcReg,
741 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
742 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
743 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
744 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
745 def rm : AVX512BI<opc, MRMSrcMem,
746 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
747 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
748 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2)))],
749 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
752 defm VPCMPEQDZ : avx512_icmp_packed<0x76, "vpcmpeqd", VK16, VR512, i512mem,
753 memopv16i32, X86pcmpeqm, v16i32>, EVEX_V512;
754 defm VPCMPEQQZ : avx512_icmp_packed<0x29, "vpcmpeqq", VK8, VR512, i512mem,
755 memopv8i64, X86pcmpeqm, v8i64>, T8PD, EVEX_V512, VEX_W;
757 defm VPCMPGTDZ : avx512_icmp_packed<0x66, "vpcmpgtd", VK16, VR512, i512mem,
758 memopv16i32, X86pcmpgtm, v16i32>, EVEX_V512;
759 defm VPCMPGTQZ : avx512_icmp_packed<0x37, "vpcmpgtq", VK8, VR512, i512mem,
760 memopv8i64, X86pcmpgtm, v8i64>, T8PD, EVEX_V512, VEX_W;
762 def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
763 (COPY_TO_REGCLASS (VPCMPGTDZrr
764 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
765 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
767 def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
768 (COPY_TO_REGCLASS (VPCMPEQDZrr
769 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
770 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
772 multiclass avx512_icmp_cc<bits<8> opc, RegisterClass KRC,
773 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
774 SDNode OpNode, ValueType vt, Operand CC, string asm,
776 def rri : AVX512AIi8<opc, MRMSrcReg,
777 (outs KRC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
778 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2), imm:$cc))],
779 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
780 def rmi : AVX512AIi8<opc, MRMSrcMem,
781 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
782 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2),
783 imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
784 // Accept explicit immediate argument form instead of comparison code.
785 let isAsmParserOnly = 1, hasSideEffects = 0 in {
786 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
787 (outs KRC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
788 asm_alt, [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
789 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
790 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
791 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
795 defm VPCMPDZ : avx512_icmp_cc<0x1F, VK16, VR512, i512mem, memopv16i32,
796 X86cmpm, v16i32, AVXCC,
797 "vpcmp${cc}d\t{$src2, $src1, $dst|$dst, $src1, $src2}",
798 "vpcmpd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
799 EVEX_V512, EVEX_CD8<32, CD8VF>;
800 defm VPCMPUDZ : avx512_icmp_cc<0x1E, VK16, VR512, i512mem, memopv16i32,
801 X86cmpmu, v16i32, AVXCC,
802 "vpcmp${cc}ud\t{$src2, $src1, $dst|$dst, $src1, $src2}",
803 "vpcmpud\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
804 EVEX_V512, EVEX_CD8<32, CD8VF>;
806 defm VPCMPQZ : avx512_icmp_cc<0x1F, VK8, VR512, i512mem, memopv8i64,
807 X86cmpm, v8i64, AVXCC,
808 "vpcmp${cc}q\t{$src2, $src1, $dst|$dst, $src1, $src2}",
809 "vpcmpq\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
810 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
811 defm VPCMPUQZ : avx512_icmp_cc<0x1E, VK8, VR512, i512mem, memopv8i64,
812 X86cmpmu, v8i64, AVXCC,
813 "vpcmp${cc}uq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
814 "vpcmpuq\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
815 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
817 // avx512_cmp_packed - sse 1 & 2 compare packed instructions
818 multiclass avx512_cmp_packed<RegisterClass KRC, RegisterClass RC,
819 X86MemOperand x86memop, ValueType vt,
820 string suffix, Domain d> {
821 def rri : AVX512PIi8<0xC2, MRMSrcReg,
822 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
823 !strconcat("vcmp${cc}", suffix,
824 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
825 [(set KRC:$dst, (X86cmpm (vt RC:$src1), (vt RC:$src2), imm:$cc))], d>;
826 def rrib: AVX512PIi8<0xC2, MRMSrcReg,
827 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
828 !strconcat("vcmp${cc}", suffix,
829 " \t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
831 def rmi : AVX512PIi8<0xC2, MRMSrcMem,
832 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, AVXCC:$cc),
833 !strconcat("vcmp${cc}", suffix,
834 " \t{$src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
836 (X86cmpm (vt RC:$src1), (memop addr:$src2), imm:$cc))], d>;
838 // Accept explicit immediate argument form instead of comparison code.
839 let isAsmParserOnly = 1, hasSideEffects = 0 in {
840 def rri_alt : AVX512PIi8<0xC2, MRMSrcReg,
841 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
842 !strconcat("vcmp", suffix,
843 " \t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
844 def rmi_alt : AVX512PIi8<0xC2, MRMSrcMem,
845 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
846 !strconcat("vcmp", suffix,
847 " \t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
851 defm VCMPPSZ : avx512_cmp_packed<VK16, VR512, f512mem, v16f32,
852 "ps", SSEPackedSingle>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VF>;
853 defm VCMPPDZ : avx512_cmp_packed<VK8, VR512, f512mem, v8f64,
854 "pd", SSEPackedDouble>, PD, EVEX_4V, VEX_W, EVEX_V512,
857 def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
858 (COPY_TO_REGCLASS (VCMPPSZrri
859 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
860 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
862 def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
863 (COPY_TO_REGCLASS (VPCMPDZrri
864 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
865 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
867 def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
868 (COPY_TO_REGCLASS (VPCMPUDZrri
869 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
870 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
873 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
874 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
876 (COPY_TO_REGCLASS (VCMPPSZrrib VR512:$src1, VR512:$src2,
877 (I8Imm imm:$cc)), GR16)>;
879 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
880 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
882 (COPY_TO_REGCLASS (VCMPPDZrrib VR512:$src1, VR512:$src2,
883 (I8Imm imm:$cc)), GR8)>;
885 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
886 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
888 (COPY_TO_REGCLASS (VCMPPSZrri VR512:$src1, VR512:$src2,
889 (I8Imm imm:$cc)), GR16)>;
891 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
892 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
894 (COPY_TO_REGCLASS (VCMPPDZrri VR512:$src1, VR512:$src2,
895 (I8Imm imm:$cc)), GR8)>;
897 // Mask register copy, including
898 // - copy between mask registers
899 // - load/store mask registers
900 // - copy from GPR to mask register and vice versa
902 multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
903 string OpcodeStr, RegisterClass KRC,
904 ValueType vt, X86MemOperand x86memop> {
905 let hasSideEffects = 0 in {
906 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
907 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
909 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
910 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
911 [(set KRC:$dst, (vt (load addr:$src)))]>;
913 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
914 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
918 multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
920 RegisterClass KRC, RegisterClass GRC> {
921 let hasSideEffects = 0 in {
922 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
923 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
924 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
925 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
929 let Predicates = [HasAVX512] in {
930 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16mem>,
932 defm KMOVW : avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
936 let Predicates = [HasAVX512] in {
937 // GR16 from/to 16-bit mask
938 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
939 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
940 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
941 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
943 // Store kreg in memory
944 def : Pat<(store (v16i1 VK16:$src), addr:$dst),
945 (KMOVWmk addr:$dst, VK16:$src)>;
947 def : Pat<(store VK8:$src, addr:$dst),
948 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>;
950 def : Pat<(i1 (load addr:$src)),
951 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK1)>;
953 def : Pat<(v8i1 (load addr:$src)),
954 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK8)>;
956 def : Pat<(i1 (trunc (i32 GR32:$src))),
957 (COPY_TO_REGCLASS (KMOVWkr $src), VK1)>;
959 def : Pat<(i1 (trunc (i8 GR8:$src))),
961 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)), VK1)>;
963 def : Pat<(i32 (zext VK1:$src)), (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16))>;
964 def : Pat<(i8 (zext VK1:$src)),
966 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_8bit)>;
967 def : Pat<(i64 (zext VK1:$src)),
968 (SUBREG_TO_REG (i64 0),
969 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_32bit)>;
972 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
973 let Predicates = [HasAVX512] in {
974 // GR from/to 8-bit mask without native support
975 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
977 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
979 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
981 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
984 def : Pat<(i1 (extractelt VK16:$src, (iPTR 0))),
985 (COPY_TO_REGCLASS VK16:$src, VK1)>;
986 def : Pat<(i1 (extractelt VK8:$src, (iPTR 0))),
987 (COPY_TO_REGCLASS VK8:$src, VK1)>;
991 // Mask unary operation
993 multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
994 RegisterClass KRC, SDPatternOperator OpNode> {
995 let Predicates = [HasAVX512] in
996 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
997 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
998 [(set KRC:$dst, (OpNode KRC:$src))]>;
1001 multiclass avx512_mask_unop_w<bits<8> opc, string OpcodeStr,
1002 SDPatternOperator OpNode> {
1003 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1007 defm KNOT : avx512_mask_unop_w<0x44, "knot", not>;
1009 multiclass avx512_mask_unop_int<string IntName, string InstName> {
1010 let Predicates = [HasAVX512] in
1011 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1013 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1014 (v16i1 (COPY_TO_REGCLASS GR16:$src, VK16))), GR16)>;
1016 defm : avx512_mask_unop_int<"knot", "KNOT">;
1018 def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
1019 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
1020 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
1022 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
1023 def : Pat<(not VK8:$src),
1025 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
1027 // Mask binary operation
1028 // - KAND, KANDN, KOR, KXNOR, KXOR
1029 multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
1030 RegisterClass KRC, SDPatternOperator OpNode> {
1031 let Predicates = [HasAVX512] in
1032 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1033 !strconcat(OpcodeStr,
1034 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1035 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
1038 multiclass avx512_mask_binop_w<bits<8> opc, string OpcodeStr,
1039 SDPatternOperator OpNode> {
1040 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1044 def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
1045 def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
1047 let isCommutable = 1 in {
1048 defm KAND : avx512_mask_binop_w<0x41, "kand", and>;
1049 let isCommutable = 0 in
1050 defm KANDN : avx512_mask_binop_w<0x42, "kandn", andn>;
1051 defm KOR : avx512_mask_binop_w<0x45, "kor", or>;
1052 defm KXNOR : avx512_mask_binop_w<0x46, "kxnor", xnor>;
1053 defm KXOR : avx512_mask_binop_w<0x47, "kxor", xor>;
1056 def : Pat<(xor VK1:$src1, VK1:$src2),
1057 (COPY_TO_REGCLASS (KXORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1058 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1060 def : Pat<(or VK1:$src1, VK1:$src2),
1061 (COPY_TO_REGCLASS (KORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1062 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1064 def : Pat<(not VK1:$src),
1065 (COPY_TO_REGCLASS (KXORWrr (COPY_TO_REGCLASS VK1:$src, VK16),
1066 (COPY_TO_REGCLASS (VCMPSSZrr (f32 (IMPLICIT_DEF)),
1067 (f32 (IMPLICIT_DEF)), (i8 0)), VK16)), VK1)>;
1069 def : Pat<(and VK1:$src1, VK1:$src2),
1070 (COPY_TO_REGCLASS (KANDWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1071 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1073 multiclass avx512_mask_binop_int<string IntName, string InstName> {
1074 let Predicates = [HasAVX512] in
1075 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1076 (i16 GR16:$src1), (i16 GR16:$src2)),
1077 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1078 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1079 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1082 defm : avx512_mask_binop_int<"kand", "KAND">;
1083 defm : avx512_mask_binop_int<"kandn", "KANDN">;
1084 defm : avx512_mask_binop_int<"kor", "KOR">;
1085 defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
1086 defm : avx512_mask_binop_int<"kxor", "KXOR">;
1088 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
1089 multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
1090 let Predicates = [HasAVX512] in
1091 def : Pat<(OpNode VK8:$src1, VK8:$src2),
1093 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
1094 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
1097 defm : avx512_binop_pat<and, KANDWrr>;
1098 defm : avx512_binop_pat<andn, KANDNWrr>;
1099 defm : avx512_binop_pat<or, KORWrr>;
1100 defm : avx512_binop_pat<xnor, KXNORWrr>;
1101 defm : avx512_binop_pat<xor, KXORWrr>;
1104 multiclass avx512_mask_unpck<bits<8> opc, string OpcodeStr,
1105 RegisterClass KRC> {
1106 let Predicates = [HasAVX512] in
1107 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1108 !strconcat(OpcodeStr,
1109 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1112 multiclass avx512_mask_unpck_bw<bits<8> opc, string OpcodeStr> {
1113 defm BW : avx512_mask_unpck<opc, !strconcat(OpcodeStr, "bw"), VK16>,
1117 defm KUNPCK : avx512_mask_unpck_bw<0x4b, "kunpck">;
1118 def : Pat<(v16i1 (concat_vectors (v8i1 VK8:$src1), (v8i1 VK8:$src2))),
1119 (KUNPCKBWrr (COPY_TO_REGCLASS VK8:$src2, VK16),
1120 (COPY_TO_REGCLASS VK8:$src1, VK16))>;
1123 multiclass avx512_mask_unpck_int<string IntName, string InstName> {
1124 let Predicates = [HasAVX512] in
1125 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_bw")
1126 (i16 GR16:$src1), (i16 GR16:$src2)),
1127 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"BWrr")
1128 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1129 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1131 defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
1134 multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1136 let Predicates = [HasAVX512], Defs = [EFLAGS] in
1137 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
1138 !strconcat(OpcodeStr, " \t{$src2, $src1|$src1, $src2}"),
1139 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
1142 multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1143 defm W : avx512_mask_testop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1147 defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
1149 def : Pat<(X86cmp VK1:$src1, (i1 0)),
1150 (KORTESTWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1151 (COPY_TO_REGCLASS VK1:$src1, VK16))>;
1154 multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1156 let Predicates = [HasAVX512] in
1157 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, i8imm:$imm),
1158 !strconcat(OpcodeStr,
1159 " \t{$imm, $src, $dst|$dst, $src, $imm}"),
1160 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
1163 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
1165 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1169 defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86vshli>;
1170 defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86vsrli>;
1172 // Mask setting all 0s or 1s
1173 multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
1174 let Predicates = [HasAVX512] in
1175 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
1176 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
1177 [(set KRC:$dst, (VT Val))]>;
1180 multiclass avx512_mask_setop_w<PatFrag Val> {
1181 defm B : avx512_mask_setop<VK8, v8i1, Val>;
1182 defm W : avx512_mask_setop<VK16, v16i1, Val>;
1185 defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
1186 defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
1188 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1189 let Predicates = [HasAVX512] in {
1190 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
1191 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
1192 def : Pat<(i1 0), (COPY_TO_REGCLASS (KSET0W), VK1)>;
1193 def : Pat<(i1 1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
1194 def : Pat<(i1 -1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
1196 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
1197 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
1199 def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
1200 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
1202 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
1203 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
1205 //===----------------------------------------------------------------------===//
1206 // AVX-512 - Aligned and unaligned load and store
1209 multiclass avx512_mov_packed<bits<8> opc, RegisterClass RC, RegisterClass KRC,
1210 X86MemOperand x86memop, PatFrag ld_frag,
1211 string asm, Domain d, bit IsReMaterializable = 1> {
1212 let hasSideEffects = 0 in
1213 def rr : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1214 !strconcat(asm, " \t{$src, $dst|$dst, $src}"), [], d>,
1216 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
1217 def rm : AVX512PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1218 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
1219 [(set RC:$dst, (ld_frag addr:$src))], d>, EVEX;
1220 let Constraints = "$src1 = $dst" in {
1221 def rrk : AVX512PI<opc, MRMSrcReg, (outs RC:$dst),
1222 (ins RC:$src1, KRC:$mask, RC:$src2),
1224 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>,
1226 def rmk : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1227 (ins RC:$src1, KRC:$mask, x86memop:$src2),
1229 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
1230 [], d>, EVEX, EVEX_K;
1234 defm VMOVAPSZ : avx512_mov_packed<0x28, VR512, VK16WM, f512mem, alignedloadv16f32,
1235 "vmovaps", SSEPackedSingle>,
1236 EVEX_V512, EVEX_CD8<32, CD8VF>;
1237 defm VMOVAPDZ : avx512_mov_packed<0x28, VR512, VK8WM, f512mem, alignedloadv8f64,
1238 "vmovapd", SSEPackedDouble>,
1239 PD, EVEX_V512, VEX_W,
1240 EVEX_CD8<64, CD8VF>;
1241 defm VMOVUPSZ : avx512_mov_packed<0x10, VR512, VK16WM, f512mem, loadv16f32,
1242 "vmovups", SSEPackedSingle>,
1243 EVEX_V512, EVEX_CD8<32, CD8VF>;
1244 defm VMOVUPDZ : avx512_mov_packed<0x10, VR512, VK8WM, f512mem, loadv8f64,
1245 "vmovupd", SSEPackedDouble, 0>,
1246 PD, EVEX_V512, VEX_W,
1247 EVEX_CD8<64, CD8VF>;
1248 def VMOVAPSZmr : AVX512PI<0x29, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1249 "vmovaps\t{$src, $dst|$dst, $src}",
1250 [(alignedstore512 (v16f32 VR512:$src), addr:$dst)],
1251 SSEPackedSingle>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1252 def VMOVAPDZmr : AVX512PI<0x29, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1253 "vmovapd\t{$src, $dst|$dst, $src}",
1254 [(alignedstore512 (v8f64 VR512:$src), addr:$dst)],
1255 SSEPackedDouble>, EVEX, EVEX_V512,
1256 PD, VEX_W, EVEX_CD8<64, CD8VF>;
1257 def VMOVUPSZmr : AVX512PI<0x11, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1258 "vmovups\t{$src, $dst|$dst, $src}",
1259 [(store (v16f32 VR512:$src), addr:$dst)],
1260 SSEPackedSingle>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1261 def VMOVUPDZmr : AVX512PI<0x11, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1262 "vmovupd\t{$src, $dst|$dst, $src}",
1263 [(store (v8f64 VR512:$src), addr:$dst)],
1264 SSEPackedDouble>, EVEX, EVEX_V512,
1265 PD, VEX_W, EVEX_CD8<64, CD8VF>;
1267 let hasSideEffects = 0 in {
1268 def VMOVDQA32rr : AVX512BI<0x6F, MRMSrcReg, (outs VR512:$dst),
1270 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
1272 def VMOVDQA64rr : AVX512BI<0x6F, MRMSrcReg, (outs VR512:$dst),
1274 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
1275 EVEX, EVEX_V512, VEX_W;
1276 let mayStore = 1 in {
1277 def VMOVDQA32mr : AVX512BI<0x7F, MRMDestMem, (outs),
1278 (ins i512mem:$dst, VR512:$src),
1279 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
1280 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1281 def VMOVDQA64mr : AVX512BI<0x7F, MRMDestMem, (outs),
1282 (ins i512mem:$dst, VR512:$src),
1283 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
1284 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1286 let mayLoad = 1 in {
1287 def VMOVDQA32rm : AVX512BI<0x6F, MRMSrcMem, (outs VR512:$dst),
1289 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
1290 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1291 def VMOVDQA64rm : AVX512BI<0x6F, MRMSrcMem, (outs VR512:$dst),
1293 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
1294 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1298 // 512-bit aligned load/store
1299 def : Pat<(alignedloadv8i64 addr:$src), (VMOVDQA64rm addr:$src)>;
1300 def : Pat<(alignedloadv16i32 addr:$src), (VMOVDQA32rm addr:$src)>;
1302 def : Pat<(alignedstore512 (v8i64 VR512:$src), addr:$dst),
1303 (VMOVDQA64mr addr:$dst, VR512:$src)>;
1304 def : Pat<(alignedstore512 (v16i32 VR512:$src), addr:$dst),
1305 (VMOVDQA32mr addr:$dst, VR512:$src)>;
1307 multiclass avx512_mov_int<bits<8> load_opc, bits<8> store_opc, string asm,
1308 RegisterClass RC, RegisterClass KRC,
1309 PatFrag ld_frag, X86MemOperand x86memop> {
1310 let hasSideEffects = 0 in
1311 def rr : AVX512XSI<load_opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1312 !strconcat(asm, " \t{$src, $dst|$dst, $src}"), []>, EVEX;
1313 let canFoldAsLoad = 1 in
1314 def rm : AVX512XSI<load_opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1315 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
1316 [(set RC:$dst, (ld_frag addr:$src))]>, EVEX;
1318 def mr : AVX512XSI<store_opc, MRMDestMem, (outs),
1319 (ins x86memop:$dst, VR512:$src),
1320 !strconcat(asm, " \t{$src, $dst|$dst, $src}"), []>, EVEX;
1321 let Constraints = "$src1 = $dst" in {
1322 def rrk : AVX512XSI<load_opc, MRMSrcReg, (outs RC:$dst),
1323 (ins RC:$src1, KRC:$mask, RC:$src2),
1325 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), []>,
1327 def rmk : AVX512XSI<load_opc, MRMSrcMem, (outs RC:$dst),
1328 (ins RC:$src1, KRC:$mask, x86memop:$src2),
1330 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
1335 defm VMOVDQU32 : avx512_mov_int<0x6F, 0x7F, "vmovdqu32", VR512, VK16WM,
1336 memopv16i32, i512mem>,
1337 EVEX_V512, EVEX_CD8<32, CD8VF>;
1338 defm VMOVDQU64 : avx512_mov_int<0x6F, 0x7F, "vmovdqu64", VR512, VK8WM,
1339 memopv8i64, i512mem>,
1340 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1342 // 512-bit unaligned load/store
1343 def : Pat<(loadv8i64 addr:$src), (VMOVDQU64rm addr:$src)>;
1344 def : Pat<(loadv16i32 addr:$src), (VMOVDQU32rm addr:$src)>;
1346 def : Pat<(store (v8i64 VR512:$src), addr:$dst),
1347 (VMOVDQU64mr addr:$dst, VR512:$src)>;
1348 def : Pat<(store (v16i32 VR512:$src), addr:$dst),
1349 (VMOVDQU32mr addr:$dst, VR512:$src)>;
1351 let AddedComplexity = 20 in {
1352 def : Pat<(v16f32 (vselect VK16WM:$mask, (v16f32 VR512:$src1),
1353 (v16f32 VR512:$src2))),
1354 (VMOVUPSZrrk VR512:$src2, VK16WM:$mask, VR512:$src1)>;
1355 def : Pat<(v8f64 (vselect VK8WM:$mask, (v8f64 VR512:$src1),
1356 (v8f64 VR512:$src2))),
1357 (VMOVUPDZrrk VR512:$src2, VK8WM:$mask, VR512:$src1)>;
1358 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src1),
1359 (v16i32 VR512:$src2))),
1360 (VMOVDQU32rrk VR512:$src2, VK16WM:$mask, VR512:$src1)>;
1361 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src1),
1362 (v8i64 VR512:$src2))),
1363 (VMOVDQU64rrk VR512:$src2, VK8WM:$mask, VR512:$src1)>;
1365 // Move Int Doubleword to Packed Double Int
1367 def VMOVDI2PDIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
1368 "vmovd\t{$src, $dst|$dst, $src}",
1370 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
1372 def VMOVDI2PDIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
1373 "vmovd\t{$src, $dst|$dst, $src}",
1375 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
1376 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1377 def VMOV64toPQIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
1378 "vmovq\t{$src, $dst|$dst, $src}",
1380 (v2i64 (scalar_to_vector GR64:$src)))],
1381 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
1382 let isCodeGenOnly = 1 in {
1383 def VMOV64toSDZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
1384 "vmovq\t{$src, $dst|$dst, $src}",
1385 [(set FR64:$dst, (bitconvert GR64:$src))],
1386 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
1387 def VMOVSDto64Zrr : AVX512BI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
1388 "vmovq\t{$src, $dst|$dst, $src}",
1389 [(set GR64:$dst, (bitconvert FR64:$src))],
1390 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
1392 def VMOVSDto64Zmr : AVX512BI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
1393 "vmovq\t{$src, $dst|$dst, $src}",
1394 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
1395 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
1396 EVEX_CD8<64, CD8VT1>;
1398 // Move Int Doubleword to Single Scalar
1400 let isCodeGenOnly = 1 in {
1401 def VMOVDI2SSZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
1402 "vmovd\t{$src, $dst|$dst, $src}",
1403 [(set FR32X:$dst, (bitconvert GR32:$src))],
1404 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
1406 def VMOVDI2SSZrm : AVX512BI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
1407 "vmovd\t{$src, $dst|$dst, $src}",
1408 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
1409 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1412 // Move doubleword from xmm register to r/m32
1414 def VMOVPDI2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
1415 "vmovd\t{$src, $dst|$dst, $src}",
1416 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
1417 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
1419 def VMOVPDI2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
1420 (ins i32mem:$dst, VR128X:$src),
1421 "vmovd\t{$src, $dst|$dst, $src}",
1422 [(store (i32 (vector_extract (v4i32 VR128X:$src),
1423 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
1424 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1426 // Move quadword from xmm1 register to r/m64
1428 def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
1429 "vmovq\t{$src, $dst|$dst, $src}",
1430 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
1432 IIC_SSE_MOVD_ToGP>, PD, EVEX, VEX_LIG, VEX_W,
1433 Requires<[HasAVX512, In64BitMode]>;
1435 def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
1436 (ins i64mem:$dst, VR128X:$src),
1437 "vmovq\t{$src, $dst|$dst, $src}",
1438 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
1439 addr:$dst)], IIC_SSE_MOVDQ>,
1440 EVEX, PD, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>,
1441 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
1443 // Move Scalar Single to Double Int
1445 let isCodeGenOnly = 1 in {
1446 def VMOVSS2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst),
1448 "vmovd\t{$src, $dst|$dst, $src}",
1449 [(set GR32:$dst, (bitconvert FR32X:$src))],
1450 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
1451 def VMOVSS2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
1452 (ins i32mem:$dst, FR32X:$src),
1453 "vmovd\t{$src, $dst|$dst, $src}",
1454 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
1455 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1458 // Move Quadword Int to Packed Quadword Int
1460 def VMOVQI2PQIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst),
1462 "vmovq\t{$src, $dst|$dst, $src}",
1464 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
1465 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
1467 //===----------------------------------------------------------------------===//
1468 // AVX-512 MOVSS, MOVSD
1469 //===----------------------------------------------------------------------===//
1471 multiclass avx512_move_scalar <string asm, RegisterClass RC,
1472 SDNode OpNode, ValueType vt,
1473 X86MemOperand x86memop, PatFrag mem_pat> {
1474 let hasSideEffects = 0 in {
1475 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
1476 !strconcat(asm, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1477 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
1478 (scalar_to_vector RC:$src2))))],
1479 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
1480 let Constraints = "$src1 = $dst" in
1481 def rrk : SI<0x10, MRMSrcReg, (outs VR128X:$dst),
1482 (ins VR128X:$src1, VK1WM:$mask, RC:$src2, RC:$src3),
1484 " \t{$src3, $src2, $dst {${mask}}|$dst {${mask}}, $src2, $src3}"),
1485 [], IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG, EVEX_K;
1486 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1487 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
1488 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
1490 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
1491 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
1492 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
1494 } //hasSideEffects = 0
1497 let ExeDomain = SSEPackedSingle in
1498 defm VMOVSSZ : avx512_move_scalar<"movss", FR32X, X86Movss, v4f32, f32mem,
1499 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
1501 let ExeDomain = SSEPackedDouble in
1502 defm VMOVSDZ : avx512_move_scalar<"movsd", FR64X, X86Movsd, v2f64, f64mem,
1503 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
1505 def : Pat<(f32 (X86select VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))),
1506 (COPY_TO_REGCLASS (VMOVSSZrrk (COPY_TO_REGCLASS FR32X:$src2, VR128X),
1507 VK1WM:$mask, (f32 (IMPLICIT_DEF)), FR32X:$src1), FR32X)>;
1509 def : Pat<(f64 (X86select VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))),
1510 (COPY_TO_REGCLASS (VMOVSDZrrk (COPY_TO_REGCLASS FR64X:$src2, VR128X),
1511 VK1WM:$mask, (f64 (IMPLICIT_DEF)), FR64X:$src1), FR64X)>;
1513 // For the disassembler
1514 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
1515 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
1516 (ins VR128X:$src1, FR32X:$src2),
1517 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1519 XS, EVEX_4V, VEX_LIG;
1520 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
1521 (ins VR128X:$src1, FR64X:$src2),
1522 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1524 XD, EVEX_4V, VEX_LIG, VEX_W;
1527 let Predicates = [HasAVX512] in {
1528 let AddedComplexity = 15 in {
1529 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
1530 // MOVS{S,D} to the lower bits.
1531 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
1532 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
1533 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
1534 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
1535 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
1536 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
1537 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
1538 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
1540 // Move low f32 and clear high bits.
1541 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
1542 (SUBREG_TO_REG (i32 0),
1543 (VMOVSSZrr (v4f32 (V_SET0)),
1544 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
1545 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
1546 (SUBREG_TO_REG (i32 0),
1547 (VMOVSSZrr (v4i32 (V_SET0)),
1548 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
1551 let AddedComplexity = 20 in {
1552 // MOVSSrm zeros the high parts of the register; represent this
1553 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
1554 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
1555 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1556 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
1557 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1558 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
1559 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1561 // MOVSDrm zeros the high parts of the register; represent this
1562 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
1563 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
1564 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1565 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
1566 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1567 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
1568 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1569 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
1570 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1571 def : Pat<(v2f64 (X86vzload addr:$src)),
1572 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1574 // Represent the same patterns above but in the form they appear for
1576 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
1577 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
1578 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
1579 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
1580 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
1581 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
1582 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
1583 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
1584 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
1586 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
1587 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
1588 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
1589 FR32X:$src)), sub_xmm)>;
1590 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
1591 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
1592 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
1593 FR64X:$src)), sub_xmm)>;
1594 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
1595 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
1596 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
1598 // Move low f64 and clear high bits.
1599 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
1600 (SUBREG_TO_REG (i32 0),
1601 (VMOVSDZrr (v2f64 (V_SET0)),
1602 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
1604 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
1605 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
1606 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
1608 // Extract and store.
1609 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
1611 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
1612 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
1614 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
1616 // Shuffle with VMOVSS
1617 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
1618 (VMOVSSZrr (v4i32 VR128X:$src1),
1619 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
1620 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
1621 (VMOVSSZrr (v4f32 VR128X:$src1),
1622 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
1625 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
1626 (SUBREG_TO_REG (i32 0),
1627 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
1628 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
1630 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
1631 (SUBREG_TO_REG (i32 0),
1632 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
1633 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
1636 // Shuffle with VMOVSD
1637 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
1638 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1639 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
1640 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1641 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
1642 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1643 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
1644 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1647 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
1648 (SUBREG_TO_REG (i32 0),
1649 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
1650 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
1652 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
1653 (SUBREG_TO_REG (i32 0),
1654 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
1655 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
1658 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
1659 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1660 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
1661 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1662 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
1663 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1664 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
1665 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1668 let AddedComplexity = 15 in
1669 def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
1671 "vmovq\t{$src, $dst|$dst, $src}",
1672 [(set VR128X:$dst, (v2i64 (X86vzmovl
1673 (v2i64 VR128X:$src))))],
1674 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
1676 let AddedComplexity = 20 in
1677 def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
1679 "vmovq\t{$src, $dst|$dst, $src}",
1680 [(set VR128X:$dst, (v2i64 (X86vzmovl
1681 (loadv2i64 addr:$src))))],
1682 IIC_SSE_MOVDQ>, EVEX, VEX_W,
1683 EVEX_CD8<8, CD8VT8>;
1685 let Predicates = [HasAVX512] in {
1686 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
1687 let AddedComplexity = 20 in {
1688 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
1689 (VMOVDI2PDIZrm addr:$src)>;
1690 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
1691 (VMOV64toPQIZrr GR64:$src)>;
1692 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
1693 (VMOVDI2PDIZrr GR32:$src)>;
1695 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
1696 (VMOVDI2PDIZrm addr:$src)>;
1697 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
1698 (VMOVDI2PDIZrm addr:$src)>;
1699 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
1700 (VMOVZPQILo2PQIZrm addr:$src)>;
1701 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
1702 (VMOVZPQILo2PQIZrr VR128X:$src)>;
1703 def : Pat<(v2i64 (X86vzload addr:$src)),
1704 (VMOVZPQILo2PQIZrm addr:$src)>;
1707 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
1708 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
1709 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
1710 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
1711 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
1712 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
1713 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
1716 def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
1717 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
1719 def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
1720 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
1722 def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
1723 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
1725 def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
1726 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
1728 //===----------------------------------------------------------------------===//
1729 // AVX-512 - Integer arithmetic
1731 multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
1732 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
1733 X86MemOperand x86memop, PatFrag scalar_mfrag,
1734 X86MemOperand x86scalar_mop, string BrdcstStr,
1735 OpndItins itins, bit IsCommutable = 0> {
1736 let isCommutable = IsCommutable in
1737 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1738 (ins RC:$src1, RC:$src2),
1739 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1740 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
1742 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1743 (ins RC:$src1, x86memop:$src2),
1744 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1745 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (memop_frag addr:$src2))))],
1747 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1748 (ins RC:$src1, x86scalar_mop:$src2),
1749 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
1750 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
1751 [(set RC:$dst, (OpNode RC:$src1,
1752 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2)))))],
1753 itins.rm>, EVEX_4V, EVEX_B;
1755 multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr,
1756 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
1757 PatFrag memop_frag, X86MemOperand x86memop,
1759 bit IsCommutable = 0> {
1760 let isCommutable = IsCommutable in
1761 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1762 (ins RC:$src1, RC:$src2),
1763 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1764 []>, EVEX_4V, VEX_W;
1765 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1766 (ins RC:$src1, x86memop:$src2),
1767 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1768 []>, EVEX_4V, VEX_W;
1771 defm VPADDDZ : avx512_binop_rm<0xFE, "vpaddd", add, v16i32, VR512, memopv16i32,
1772 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1773 EVEX_V512, EVEX_CD8<32, CD8VF>;
1775 defm VPSUBDZ : avx512_binop_rm<0xFA, "vpsubd", sub, v16i32, VR512, memopv16i32,
1776 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 0>,
1777 EVEX_V512, EVEX_CD8<32, CD8VF>;
1779 defm VPMULLDZ : avx512_binop_rm<0x40, "vpmulld", mul, v16i32, VR512, memopv16i32,
1780 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1781 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
1783 defm VPADDQZ : avx512_binop_rm<0xD4, "vpaddq", add, v8i64, VR512, memopv8i64,
1784 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 1>,
1785 EVEX_CD8<64, CD8VF>, EVEX_V512, VEX_W;
1787 defm VPSUBQZ : avx512_binop_rm<0xFB, "vpsubq", sub, v8i64, VR512, memopv8i64,
1788 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1789 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1791 defm VPMULDQZ : avx512_binop_rm2<0x28, "vpmuldq", v8i64, v16i32,
1792 VR512, memopv8i64, i512mem, SSE_INTALU_ITINS_P, 1>, T8PD,
1793 EVEX_V512, EVEX_CD8<64, CD8VF>;
1795 defm VPMULUDQZ : avx512_binop_rm2<0xF4, "vpmuludq", v8i64, v16i32,
1796 VR512, memopv8i64, i512mem, SSE_INTMUL_ITINS_P, 1>, EVEX_V512,
1797 EVEX_CD8<64, CD8VF>;
1799 def : Pat<(v8i64 (X86pmuludq (v16i32 VR512:$src1), (v16i32 VR512:$src2))),
1800 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
1802 def : Pat<(v8i64 (int_x86_avx512_mask_pmulu_dq_512 (v16i32 VR512:$src1),
1803 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
1804 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
1805 def : Pat<(v8i64 (int_x86_avx512_mask_pmul_dq_512 (v16i32 VR512:$src1),
1806 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
1807 (VPMULDQZrr VR512:$src1, VR512:$src2)>;
1809 defm VPMAXUDZ : avx512_binop_rm<0x3F, "vpmaxud", X86umax, v16i32, VR512, memopv16i32,
1810 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1811 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
1812 defm VPMAXUQZ : avx512_binop_rm<0x3F, "vpmaxuq", X86umax, v8i64, VR512, memopv8i64,
1813 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1814 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1816 defm VPMAXSDZ : avx512_binop_rm<0x3D, "vpmaxsd", X86smax, v16i32, VR512, memopv16i32,
1817 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1818 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
1819 defm VPMAXSQZ : avx512_binop_rm<0x3D, "vpmaxsq", X86smax, v8i64, VR512, memopv8i64,
1820 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1821 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1823 defm VPMINUDZ : avx512_binop_rm<0x3B, "vpminud", X86umin, v16i32, VR512, memopv16i32,
1824 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1825 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
1826 defm VPMINUQZ : avx512_binop_rm<0x3B, "vpminuq", X86umin, v8i64, VR512, memopv8i64,
1827 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1828 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1830 defm VPMINSDZ : avx512_binop_rm<0x39, "vpminsd", X86smin, v16i32, VR512, memopv16i32,
1831 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1832 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
1833 defm VPMINSQZ : avx512_binop_rm<0x39, "vpminsq", X86smin, v8i64, VR512, memopv8i64,
1834 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1835 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1837 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxs_d_512 (v16i32 VR512:$src1),
1838 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
1839 (VPMAXSDZrr VR512:$src1, VR512:$src2)>;
1840 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxu_d_512 (v16i32 VR512:$src1),
1841 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
1842 (VPMAXUDZrr VR512:$src1, VR512:$src2)>;
1843 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxs_q_512 (v8i64 VR512:$src1),
1844 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
1845 (VPMAXSQZrr VR512:$src1, VR512:$src2)>;
1846 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxu_q_512 (v8i64 VR512:$src1),
1847 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
1848 (VPMAXUQZrr VR512:$src1, VR512:$src2)>;
1849 def : Pat <(v16i32 (int_x86_avx512_mask_pmins_d_512 (v16i32 VR512:$src1),
1850 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
1851 (VPMINSDZrr VR512:$src1, VR512:$src2)>;
1852 def : Pat <(v16i32 (int_x86_avx512_mask_pminu_d_512 (v16i32 VR512:$src1),
1853 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
1854 (VPMINUDZrr VR512:$src1, VR512:$src2)>;
1855 def : Pat <(v8i64 (int_x86_avx512_mask_pmins_q_512 (v8i64 VR512:$src1),
1856 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
1857 (VPMINSQZrr VR512:$src1, VR512:$src2)>;
1858 def : Pat <(v8i64 (int_x86_avx512_mask_pminu_q_512 (v8i64 VR512:$src1),
1859 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
1860 (VPMINUQZrr VR512:$src1, VR512:$src2)>;
1861 //===----------------------------------------------------------------------===//
1862 // AVX-512 - Unpack Instructions
1863 //===----------------------------------------------------------------------===//
1865 multiclass avx512_unpack_fp<bits<8> opc, SDNode OpNode, ValueType vt,
1866 PatFrag mem_frag, RegisterClass RC,
1867 X86MemOperand x86memop, string asm,
1869 def rr : AVX512PI<opc, MRMSrcReg,
1870 (outs RC:$dst), (ins RC:$src1, RC:$src2),
1872 (vt (OpNode RC:$src1, RC:$src2)))],
1874 def rm : AVX512PI<opc, MRMSrcMem,
1875 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
1877 (vt (OpNode RC:$src1,
1878 (bitconvert (mem_frag addr:$src2)))))],
1882 defm VUNPCKHPSZ: avx512_unpack_fp<0x15, X86Unpckh, v16f32, memopv8f64,
1883 VR512, f512mem, "vunpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1884 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1885 defm VUNPCKHPDZ: avx512_unpack_fp<0x15, X86Unpckh, v8f64, memopv8f64,
1886 VR512, f512mem, "vunpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1887 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1888 defm VUNPCKLPSZ: avx512_unpack_fp<0x14, X86Unpckl, v16f32, memopv8f64,
1889 VR512, f512mem, "vunpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1890 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1891 defm VUNPCKLPDZ: avx512_unpack_fp<0x14, X86Unpckl, v8f64, memopv8f64,
1892 VR512, f512mem, "vunpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1893 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1895 multiclass avx512_unpack_int<bits<8> opc, string OpcodeStr, SDNode OpNode,
1896 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
1897 X86MemOperand x86memop> {
1898 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1899 (ins RC:$src1, RC:$src2),
1900 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1901 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
1902 IIC_SSE_UNPCK>, EVEX_4V;
1903 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1904 (ins RC:$src1, x86memop:$src2),
1905 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1906 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1),
1907 (bitconvert (memop_frag addr:$src2)))))],
1908 IIC_SSE_UNPCK>, EVEX_4V;
1910 defm VPUNPCKLDQZ : avx512_unpack_int<0x62, "vpunpckldq", X86Unpckl, v16i32,
1911 VR512, memopv16i32, i512mem>, EVEX_V512,
1912 EVEX_CD8<32, CD8VF>;
1913 defm VPUNPCKLQDQZ : avx512_unpack_int<0x6C, "vpunpcklqdq", X86Unpckl, v8i64,
1914 VR512, memopv8i64, i512mem>, EVEX_V512,
1915 VEX_W, EVEX_CD8<64, CD8VF>;
1916 defm VPUNPCKHDQZ : avx512_unpack_int<0x6A, "vpunpckhdq", X86Unpckh, v16i32,
1917 VR512, memopv16i32, i512mem>, EVEX_V512,
1918 EVEX_CD8<32, CD8VF>;
1919 defm VPUNPCKHQDQZ : avx512_unpack_int<0x6D, "vpunpckhqdq", X86Unpckh, v8i64,
1920 VR512, memopv8i64, i512mem>, EVEX_V512,
1921 VEX_W, EVEX_CD8<64, CD8VF>;
1922 //===----------------------------------------------------------------------===//
1926 multiclass avx512_pshuf_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
1927 SDNode OpNode, PatFrag mem_frag,
1928 X86MemOperand x86memop, ValueType OpVT> {
1929 def ri : AVX512Ii8<opc, MRMSrcReg, (outs RC:$dst),
1930 (ins RC:$src1, i8imm:$src2),
1931 !strconcat(OpcodeStr,
1932 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1934 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
1936 def mi : AVX512Ii8<opc, MRMSrcMem, (outs RC:$dst),
1937 (ins x86memop:$src1, i8imm:$src2),
1938 !strconcat(OpcodeStr,
1939 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1941 (OpVT (OpNode (mem_frag addr:$src1),
1942 (i8 imm:$src2))))]>, EVEX;
1945 defm VPSHUFDZ : avx512_pshuf_imm<0x70, "vpshufd", VR512, X86PShufd, memopv16i32,
1946 i512mem, v16i32>, PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
1948 let ExeDomain = SSEPackedSingle in
1949 defm VPERMILPSZ : avx512_pshuf_imm<0x04, "vpermilps", VR512, X86VPermilp,
1950 memopv16f32, i512mem, v16f32>, TAPD, EVEX_V512,
1951 EVEX_CD8<32, CD8VF>;
1952 let ExeDomain = SSEPackedDouble in
1953 defm VPERMILPDZ : avx512_pshuf_imm<0x05, "vpermilpd", VR512, X86VPermilp,
1954 memopv8f64, i512mem, v8f64>, TAPD, EVEX_V512,
1955 VEX_W, EVEX_CD8<32, CD8VF>;
1957 def : Pat<(v16i32 (X86VPermilp VR512:$src1, (i8 imm:$imm))),
1958 (VPERMILPSZri VR512:$src1, imm:$imm)>;
1959 def : Pat<(v8i64 (X86VPermilp VR512:$src1, (i8 imm:$imm))),
1960 (VPERMILPDZri VR512:$src1, imm:$imm)>;
1962 //===----------------------------------------------------------------------===//
1963 // AVX-512 Logical Instructions
1964 //===----------------------------------------------------------------------===//
1966 defm VPANDDZ : avx512_binop_rm<0xDB, "vpandd", and, v16i32, VR512, memopv16i32,
1967 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
1968 EVEX_V512, EVEX_CD8<32, CD8VF>;
1969 defm VPANDQZ : avx512_binop_rm<0xDB, "vpandq", and, v8i64, VR512, memopv8i64,
1970 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
1971 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1972 defm VPORDZ : avx512_binop_rm<0xEB, "vpord", or, v16i32, VR512, memopv16i32,
1973 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
1974 EVEX_V512, EVEX_CD8<32, CD8VF>;
1975 defm VPORQZ : avx512_binop_rm<0xEB, "vporq", or, v8i64, VR512, memopv8i64,
1976 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
1977 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1978 defm VPXORDZ : avx512_binop_rm<0xEF, "vpxord", xor, v16i32, VR512, memopv16i32,
1979 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
1980 EVEX_V512, EVEX_CD8<32, CD8VF>;
1981 defm VPXORQZ : avx512_binop_rm<0xEF, "vpxorq", xor, v8i64, VR512, memopv8i64,
1982 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
1983 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1984 defm VPANDNDZ : avx512_binop_rm<0xDF, "vpandnd", X86andnp, v16i32, VR512,
1985 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
1986 SSE_BIT_ITINS_P, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1987 defm VPANDNQZ : avx512_binop_rm<0xDF, "vpandnq", X86andnp, v8i64, VR512, memopv8i64,
1988 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 0>,
1989 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1991 //===----------------------------------------------------------------------===//
1992 // AVX-512 FP arithmetic
1993 //===----------------------------------------------------------------------===//
1995 multiclass avx512_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
1997 defm SSZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"), OpNode, FR32X,
1998 f32mem, itins.s, 0>, XS, EVEX_4V, VEX_LIG,
1999 EVEX_CD8<32, CD8VT1>;
2000 defm SDZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"), OpNode, FR64X,
2001 f64mem, itins.d, 0>, XD, VEX_W, EVEX_4V, VEX_LIG,
2002 EVEX_CD8<64, CD8VT1>;
2005 let isCommutable = 1 in {
2006 defm VADD : avx512_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>;
2007 defm VMUL : avx512_binop_s<0x59, "mul", fmul, SSE_ALU_ITINS_S>;
2008 defm VMIN : avx512_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>;
2009 defm VMAX : avx512_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>;
2011 let isCommutable = 0 in {
2012 defm VSUB : avx512_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>;
2013 defm VDIV : avx512_binop_s<0x5E, "div", fdiv, SSE_ALU_ITINS_S>;
2016 multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
2017 RegisterClass RC, ValueType vt,
2018 X86MemOperand x86memop, PatFrag mem_frag,
2019 X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2021 Domain d, OpndItins itins, bit commutable> {
2022 let isCommutable = commutable in
2023 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
2024 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2025 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
2027 let mayLoad = 1 in {
2028 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2029 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2030 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
2031 itins.rm, d>, EVEX_4V, TB;
2032 def rmb : PI<opc, MRMSrcMem, (outs RC:$dst),
2033 (ins RC:$src1, x86scalar_mop:$src2),
2034 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2035 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
2036 [(set RC:$dst, (OpNode RC:$src1,
2037 (vt (X86VBroadcast (scalar_mfrag addr:$src2)))))],
2038 itins.rm, d>, EVEX_4V, EVEX_B, TB;
2042 defm VADDPSZ : avx512_fp_packed<0x58, "addps", fadd, VR512, v16f32, f512mem,
2043 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2044 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2046 defm VADDPDZ : avx512_fp_packed<0x58, "addpd", fadd, VR512, v8f64, f512mem,
2047 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2048 SSE_ALU_ITINS_P.d, 1>,
2049 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2051 defm VMULPSZ : avx512_fp_packed<0x59, "mulps", fmul, VR512, v16f32, f512mem,
2052 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2053 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2054 defm VMULPDZ : avx512_fp_packed<0x59, "mulpd", fmul, VR512, v8f64, f512mem,
2055 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2056 SSE_ALU_ITINS_P.d, 1>,
2057 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2059 defm VMINPSZ : avx512_fp_packed<0x5D, "minps", X86fmin, VR512, v16f32, f512mem,
2060 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2061 SSE_ALU_ITINS_P.s, 1>,
2062 EVEX_V512, EVEX_CD8<32, CD8VF>;
2063 defm VMAXPSZ : avx512_fp_packed<0x5F, "maxps", X86fmax, VR512, v16f32, f512mem,
2064 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2065 SSE_ALU_ITINS_P.s, 1>,
2066 EVEX_V512, EVEX_CD8<32, CD8VF>;
2068 defm VMINPDZ : avx512_fp_packed<0x5D, "minpd", X86fmin, VR512, v8f64, f512mem,
2069 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2070 SSE_ALU_ITINS_P.d, 1>,
2071 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2072 defm VMAXPDZ : avx512_fp_packed<0x5F, "maxpd", X86fmax, VR512, v8f64, f512mem,
2073 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2074 SSE_ALU_ITINS_P.d, 1>,
2075 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2077 defm VSUBPSZ : avx512_fp_packed<0x5C, "subps", fsub, VR512, v16f32, f512mem,
2078 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2079 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2080 defm VDIVPSZ : avx512_fp_packed<0x5E, "divps", fdiv, VR512, v16f32, f512mem,
2081 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2082 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2084 defm VSUBPDZ : avx512_fp_packed<0x5C, "subpd", fsub, VR512, v8f64, f512mem,
2085 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2086 SSE_ALU_ITINS_P.d, 0>,
2087 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2088 defm VDIVPDZ : avx512_fp_packed<0x5E, "divpd", fdiv, VR512, v8f64, f512mem,
2089 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2090 SSE_ALU_ITINS_P.d, 0>,
2091 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2093 def : Pat<(v16f32 (int_x86_avx512_mask_max_ps_512 (v16f32 VR512:$src1),
2094 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
2095 (i16 -1), FROUND_CURRENT)),
2096 (VMAXPSZrr VR512:$src1, VR512:$src2)>;
2098 def : Pat<(v8f64 (int_x86_avx512_mask_max_pd_512 (v8f64 VR512:$src1),
2099 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
2100 (i8 -1), FROUND_CURRENT)),
2101 (VMAXPDZrr VR512:$src1, VR512:$src2)>;
2103 def : Pat<(v16f32 (int_x86_avx512_mask_min_ps_512 (v16f32 VR512:$src1),
2104 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
2105 (i16 -1), FROUND_CURRENT)),
2106 (VMINPSZrr VR512:$src1, VR512:$src2)>;
2108 def : Pat<(v8f64 (int_x86_avx512_mask_min_pd_512 (v8f64 VR512:$src1),
2109 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
2110 (i8 -1), FROUND_CURRENT)),
2111 (VMINPDZrr VR512:$src1, VR512:$src2)>;
2112 //===----------------------------------------------------------------------===//
2113 // AVX-512 VPTESTM instructions
2114 //===----------------------------------------------------------------------===//
2116 multiclass avx512_vptest<bits<8> opc, string OpcodeStr, RegisterClass KRC,
2117 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
2118 SDNode OpNode, ValueType vt> {
2119 def rr : AVX5128I<opc, MRMSrcReg,
2120 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
2121 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2122 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))]>, EVEX_4V;
2123 def rm : AVX5128I<opc, MRMSrcMem,
2124 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
2125 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2126 [(set KRC:$dst, (OpNode (vt RC:$src1),
2127 (bitconvert (memop_frag addr:$src2))))]>, EVEX_4V;
2130 defm VPTESTMDZ : avx512_vptest<0x27, "vptestmd", VK16, VR512, f512mem,
2131 memopv16i32, X86testm, v16i32>, EVEX_V512,
2132 EVEX_CD8<32, CD8VF>;
2133 defm VPTESTMQZ : avx512_vptest<0x27, "vptestmq", VK8, VR512, f512mem,
2134 memopv8i64, X86testm, v8i64>, EVEX_V512, VEX_W,
2135 EVEX_CD8<64, CD8VF>;
2137 def : Pat <(i16 (int_x86_avx512_mask_ptestm_d_512 (v16i32 VR512:$src1),
2138 (v16i32 VR512:$src2), (i16 -1))),
2139 (COPY_TO_REGCLASS (VPTESTMDZrr VR512:$src1, VR512:$src2), GR16)>;
2141 def : Pat <(i8 (int_x86_avx512_mask_ptestm_q_512 (v8i64 VR512:$src1),
2142 (v8i64 VR512:$src2), (i8 -1))),
2143 (COPY_TO_REGCLASS (VPTESTMDZrr VR512:$src1, VR512:$src2), GR8)>;
2144 //===----------------------------------------------------------------------===//
2145 // AVX-512 Shift instructions
2146 //===----------------------------------------------------------------------===//
2147 multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
2148 string OpcodeStr, SDNode OpNode, RegisterClass RC,
2149 ValueType vt, X86MemOperand x86memop, PatFrag mem_frag,
2150 RegisterClass KRC> {
2151 def ri : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
2152 (ins RC:$src1, i8imm:$src2),
2153 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2154 [(set RC:$dst, (vt (OpNode RC:$src1, (i8 imm:$src2))))],
2155 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
2156 def rik : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
2157 (ins KRC:$mask, RC:$src1, i8imm:$src2),
2158 !strconcat(OpcodeStr,
2159 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2160 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
2161 def mi: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
2162 (ins x86memop:$src1, i8imm:$src2),
2163 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2164 [(set RC:$dst, (OpNode (mem_frag addr:$src1),
2165 (i8 imm:$src2)))], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
2166 def mik: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
2167 (ins KRC:$mask, x86memop:$src1, i8imm:$src2),
2168 !strconcat(OpcodeStr,
2169 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2170 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
2173 multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2174 RegisterClass RC, ValueType vt, ValueType SrcVT,
2175 PatFrag bc_frag, RegisterClass KRC> {
2176 // src2 is always 128-bit
2177 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2178 (ins RC:$src1, VR128X:$src2),
2179 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2180 [(set RC:$dst, (vt (OpNode RC:$src1, (SrcVT VR128X:$src2))))],
2181 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
2182 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2183 (ins KRC:$mask, RC:$src1, VR128X:$src2),
2184 !strconcat(OpcodeStr,
2185 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2186 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
2187 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2188 (ins RC:$src1, i128mem:$src2),
2189 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2190 [(set RC:$dst, (vt (OpNode RC:$src1,
2191 (bc_frag (memopv2i64 addr:$src2)))))],
2192 SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
2193 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2194 (ins KRC:$mask, RC:$src1, i128mem:$src2),
2195 !strconcat(OpcodeStr,
2196 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2197 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
2200 defm VPSRLDZ : avx512_shift_rmi<0x72, MRM2r, MRM2m, "vpsrld", X86vsrli,
2201 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
2202 EVEX_V512, EVEX_CD8<32, CD8VF>;
2203 defm VPSRLDZ : avx512_shift_rrm<0xD2, "vpsrld", X86vsrl,
2204 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2205 EVEX_CD8<32, CD8VQ>;
2207 defm VPSRLQZ : avx512_shift_rmi<0x73, MRM2r, MRM2m, "vpsrlq", X86vsrli,
2208 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2209 EVEX_CD8<64, CD8VF>, VEX_W;
2210 defm VPSRLQZ : avx512_shift_rrm<0xD3, "vpsrlq", X86vsrl,
2211 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2212 EVEX_CD8<64, CD8VQ>, VEX_W;
2214 defm VPSLLDZ : avx512_shift_rmi<0x72, MRM6r, MRM6m, "vpslld", X86vshli,
2215 VR512, v16i32, i512mem, memopv16i32, VK16WM>, EVEX_V512,
2216 EVEX_CD8<32, CD8VF>;
2217 defm VPSLLDZ : avx512_shift_rrm<0xF2, "vpslld", X86vshl,
2218 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2219 EVEX_CD8<32, CD8VQ>;
2221 defm VPSLLQZ : avx512_shift_rmi<0x73, MRM6r, MRM6m, "vpsllq", X86vshli,
2222 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2223 EVEX_CD8<64, CD8VF>, VEX_W;
2224 defm VPSLLQZ : avx512_shift_rrm<0xF3, "vpsllq", X86vshl,
2225 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2226 EVEX_CD8<64, CD8VQ>, VEX_W;
2228 defm VPSRADZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsrad", X86vsrai,
2229 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
2230 EVEX_V512, EVEX_CD8<32, CD8VF>;
2231 defm VPSRADZ : avx512_shift_rrm<0xE2, "vpsrad", X86vsra,
2232 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2233 EVEX_CD8<32, CD8VQ>;
2235 defm VPSRAQZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsraq", X86vsrai,
2236 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2237 EVEX_CD8<64, CD8VF>, VEX_W;
2238 defm VPSRAQZ : avx512_shift_rrm<0xE2, "vpsraq", X86vsra,
2239 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2240 EVEX_CD8<64, CD8VQ>, VEX_W;
2242 //===-------------------------------------------------------------------===//
2243 // Variable Bit Shifts
2244 //===-------------------------------------------------------------------===//
2245 multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
2246 RegisterClass RC, ValueType vt,
2247 X86MemOperand x86memop, PatFrag mem_frag> {
2248 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
2249 (ins RC:$src1, RC:$src2),
2250 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2252 (vt (OpNode RC:$src1, (vt RC:$src2))))]>,
2254 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
2255 (ins RC:$src1, x86memop:$src2),
2256 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2258 (vt (OpNode RC:$src1, (mem_frag addr:$src2))))]>,
2262 defm VPSLLVDZ : avx512_var_shift<0x47, "vpsllvd", shl, VR512, v16i32,
2263 i512mem, memopv16i32>, EVEX_V512,
2264 EVEX_CD8<32, CD8VF>;
2265 defm VPSLLVQZ : avx512_var_shift<0x47, "vpsllvq", shl, VR512, v8i64,
2266 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2267 EVEX_CD8<64, CD8VF>;
2268 defm VPSRLVDZ : avx512_var_shift<0x45, "vpsrlvd", srl, VR512, v16i32,
2269 i512mem, memopv16i32>, EVEX_V512,
2270 EVEX_CD8<32, CD8VF>;
2271 defm VPSRLVQZ : avx512_var_shift<0x45, "vpsrlvq", srl, VR512, v8i64,
2272 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2273 EVEX_CD8<64, CD8VF>;
2274 defm VPSRAVDZ : avx512_var_shift<0x46, "vpsravd", sra, VR512, v16i32,
2275 i512mem, memopv16i32>, EVEX_V512,
2276 EVEX_CD8<32, CD8VF>;
2277 defm VPSRAVQZ : avx512_var_shift<0x46, "vpsravq", sra, VR512, v8i64,
2278 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2279 EVEX_CD8<64, CD8VF>;
2281 //===----------------------------------------------------------------------===//
2282 // AVX-512 - MOVDDUP
2283 //===----------------------------------------------------------------------===//
2285 multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT,
2286 X86MemOperand x86memop, PatFrag memop_frag> {
2287 def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
2288 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
2289 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX;
2290 def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2291 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
2293 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX;
2296 defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, memopv8f64>,
2297 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
2298 def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
2299 (VMOVDDUPZrm addr:$src)>;
2301 //===---------------------------------------------------------------------===//
2302 // Replicate Single FP - MOVSHDUP and MOVSLDUP
2303 //===---------------------------------------------------------------------===//
2304 multiclass avx512_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
2305 ValueType vt, RegisterClass RC, PatFrag mem_frag,
2306 X86MemOperand x86memop> {
2307 def rr : AVX512XSI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
2308 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
2309 [(set RC:$dst, (vt (OpNode RC:$src)))]>, EVEX;
2311 def rm : AVX512XSI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2312 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
2313 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>, EVEX;
2316 defm VMOVSHDUPZ : avx512_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
2317 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
2318 EVEX_CD8<32, CD8VF>;
2319 defm VMOVSLDUPZ : avx512_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
2320 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
2321 EVEX_CD8<32, CD8VF>;
2323 def : Pat<(v16i32 (X86Movshdup VR512:$src)), (VMOVSHDUPZrr VR512:$src)>;
2324 def : Pat<(v16i32 (X86Movshdup (memopv16i32 addr:$src))),
2325 (VMOVSHDUPZrm addr:$src)>;
2326 def : Pat<(v16i32 (X86Movsldup VR512:$src)), (VMOVSLDUPZrr VR512:$src)>;
2327 def : Pat<(v16i32 (X86Movsldup (memopv16i32 addr:$src))),
2328 (VMOVSLDUPZrm addr:$src)>;
2330 //===----------------------------------------------------------------------===//
2331 // Move Low to High and High to Low packed FP Instructions
2332 //===----------------------------------------------------------------------===//
2333 def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
2334 (ins VR128X:$src1, VR128X:$src2),
2335 "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2336 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
2337 IIC_SSE_MOV_LH>, EVEX_4V;
2338 def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
2339 (ins VR128X:$src1, VR128X:$src2),
2340 "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2341 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
2342 IIC_SSE_MOV_LH>, EVEX_4V;
2344 let Predicates = [HasAVX512] in {
2346 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
2347 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
2348 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
2349 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
2352 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
2353 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
2356 //===----------------------------------------------------------------------===//
2357 // FMA - Fused Multiply Operations
2359 let Constraints = "$src1 = $dst" in {
2360 multiclass avx512_fma3p_rm<bits<8> opc, string OpcodeStr,
2361 RegisterClass RC, X86MemOperand x86memop,
2362 PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2363 string BrdcstStr, SDNode OpNode, ValueType OpVT> {
2364 def r: AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
2365 (ins RC:$src1, RC:$src2, RC:$src3),
2366 !strconcat(OpcodeStr," \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2367 [(set RC:$dst, (OpVT(OpNode RC:$src1, RC:$src2, RC:$src3)))]>;
2370 def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2371 (ins RC:$src1, RC:$src2, x86memop:$src3),
2372 !strconcat(OpcodeStr, " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2373 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2,
2374 (mem_frag addr:$src3))))]>;
2375 def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2376 (ins RC:$src1, RC:$src2, x86scalar_mop:$src3),
2377 !strconcat(OpcodeStr, " \t{${src3}", BrdcstStr,
2378 ", $src2, $dst|$dst, $src2, ${src3}", BrdcstStr, "}"),
2379 [(set RC:$dst, (OpNode RC:$src1, RC:$src2,
2380 (OpVT (X86VBroadcast (scalar_mfrag addr:$src3)))))]>, EVEX_B;
2382 } // Constraints = "$src1 = $dst"
2384 let ExeDomain = SSEPackedSingle in {
2385 defm VFMADD213PSZ : avx512_fma3p_rm<0xA8, "vfmadd213ps", VR512, f512mem,
2386 memopv16f32, f32mem, loadf32, "{1to16}",
2387 X86Fmadd, v16f32>, EVEX_V512,
2388 EVEX_CD8<32, CD8VF>;
2389 defm VFMSUB213PSZ : avx512_fma3p_rm<0xAA, "vfmsub213ps", VR512, f512mem,
2390 memopv16f32, f32mem, loadf32, "{1to16}",
2391 X86Fmsub, v16f32>, EVEX_V512,
2392 EVEX_CD8<32, CD8VF>;
2393 defm VFMADDSUB213PSZ : avx512_fma3p_rm<0xA6, "vfmaddsub213ps", VR512, f512mem,
2394 memopv16f32, f32mem, loadf32, "{1to16}",
2395 X86Fmaddsub, v16f32>,
2396 EVEX_V512, EVEX_CD8<32, CD8VF>;
2397 defm VFMSUBADD213PSZ : avx512_fma3p_rm<0xA7, "vfmsubadd213ps", VR512, f512mem,
2398 memopv16f32, f32mem, loadf32, "{1to16}",
2399 X86Fmsubadd, v16f32>,
2400 EVEX_V512, EVEX_CD8<32, CD8VF>;
2401 defm VFNMADD213PSZ : avx512_fma3p_rm<0xAC, "vfnmadd213ps", VR512, f512mem,
2402 memopv16f32, f32mem, loadf32, "{1to16}",
2403 X86Fnmadd, v16f32>, EVEX_V512,
2404 EVEX_CD8<32, CD8VF>;
2405 defm VFNMSUB213PSZ : avx512_fma3p_rm<0xAE, "vfnmsub213ps", VR512, f512mem,
2406 memopv16f32, f32mem, loadf32, "{1to16}",
2407 X86Fnmsub, v16f32>, EVEX_V512,
2408 EVEX_CD8<32, CD8VF>;
2410 let ExeDomain = SSEPackedDouble in {
2411 defm VFMADD213PDZ : avx512_fma3p_rm<0xA8, "vfmadd213pd", VR512, f512mem,
2412 memopv8f64, f64mem, loadf64, "{1to8}",
2413 X86Fmadd, v8f64>, EVEX_V512,
2414 VEX_W, EVEX_CD8<64, CD8VF>;
2415 defm VFMSUB213PDZ : avx512_fma3p_rm<0xAA, "vfmsub213pd", VR512, f512mem,
2416 memopv8f64, f64mem, loadf64, "{1to8}",
2417 X86Fmsub, v8f64>, EVEX_V512, VEX_W,
2418 EVEX_CD8<64, CD8VF>;
2419 defm VFMADDSUB213PDZ : avx512_fma3p_rm<0xA6, "vfmaddsub213pd", VR512, f512mem,
2420 memopv8f64, f64mem, loadf64, "{1to8}",
2421 X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
2422 EVEX_CD8<64, CD8VF>;
2423 defm VFMSUBADD213PDZ : avx512_fma3p_rm<0xA7, "vfmsubadd213pd", VR512, f512mem,
2424 memopv8f64, f64mem, loadf64, "{1to8}",
2425 X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
2426 EVEX_CD8<64, CD8VF>;
2427 defm VFNMADD213PDZ : avx512_fma3p_rm<0xAC, "vfnmadd213pd", VR512, f512mem,
2428 memopv8f64, f64mem, loadf64, "{1to8}",
2429 X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
2430 EVEX_CD8<64, CD8VF>;
2431 defm VFNMSUB213PDZ : avx512_fma3p_rm<0xAE, "vfnmsub213pd", VR512, f512mem,
2432 memopv8f64, f64mem, loadf64, "{1to8}",
2433 X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
2434 EVEX_CD8<64, CD8VF>;
2437 let Constraints = "$src1 = $dst" in {
2438 multiclass avx512_fma3p_m132<bits<8> opc, string OpcodeStr,
2439 RegisterClass RC, X86MemOperand x86memop,
2440 PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2441 string BrdcstStr, SDNode OpNode, ValueType OpVT> {
2443 def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2444 (ins RC:$src1, RC:$src3, x86memop:$src2),
2445 !strconcat(OpcodeStr, " \t{$src2, $src3, $dst|$dst, $src3, $src2}"),
2446 [(set RC:$dst, (OpVT (OpNode RC:$src1, (mem_frag addr:$src2), RC:$src3)))]>;
2447 def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2448 (ins RC:$src1, RC:$src3, x86scalar_mop:$src2),
2449 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2450 ", $src3, $dst|$dst, $src3, ${src2}", BrdcstStr, "}"),
2451 [(set RC:$dst, (OpNode RC:$src1,
2452 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2))), RC:$src3))]>, EVEX_B;
2454 } // Constraints = "$src1 = $dst"
2457 let ExeDomain = SSEPackedSingle in {
2458 defm VFMADD132PSZ : avx512_fma3p_m132<0x98, "vfmadd132ps", VR512, f512mem,
2459 memopv16f32, f32mem, loadf32, "{1to16}",
2460 X86Fmadd, v16f32>, EVEX_V512,
2461 EVEX_CD8<32, CD8VF>;
2462 defm VFMSUB132PSZ : avx512_fma3p_m132<0x9A, "vfmsub132ps", VR512, f512mem,
2463 memopv16f32, f32mem, loadf32, "{1to16}",
2464 X86Fmsub, v16f32>, EVEX_V512,
2465 EVEX_CD8<32, CD8VF>;
2466 defm VFMADDSUB132PSZ : avx512_fma3p_m132<0x96, "vfmaddsub132ps", VR512, f512mem,
2467 memopv16f32, f32mem, loadf32, "{1to16}",
2468 X86Fmaddsub, v16f32>,
2469 EVEX_V512, EVEX_CD8<32, CD8VF>;
2470 defm VFMSUBADD132PSZ : avx512_fma3p_m132<0x97, "vfmsubadd132ps", VR512, f512mem,
2471 memopv16f32, f32mem, loadf32, "{1to16}",
2472 X86Fmsubadd, v16f32>,
2473 EVEX_V512, EVEX_CD8<32, CD8VF>;
2474 defm VFNMADD132PSZ : avx512_fma3p_m132<0x9C, "vfnmadd132ps", VR512, f512mem,
2475 memopv16f32, f32mem, loadf32, "{1to16}",
2476 X86Fnmadd, v16f32>, EVEX_V512,
2477 EVEX_CD8<32, CD8VF>;
2478 defm VFNMSUB132PSZ : avx512_fma3p_m132<0x9E, "vfnmsub132ps", VR512, f512mem,
2479 memopv16f32, f32mem, loadf32, "{1to16}",
2480 X86Fnmsub, v16f32>, EVEX_V512,
2481 EVEX_CD8<32, CD8VF>;
2483 let ExeDomain = SSEPackedDouble in {
2484 defm VFMADD132PDZ : avx512_fma3p_m132<0x98, "vfmadd132pd", VR512, f512mem,
2485 memopv8f64, f64mem, loadf64, "{1to8}",
2486 X86Fmadd, v8f64>, EVEX_V512,
2487 VEX_W, EVEX_CD8<64, CD8VF>;
2488 defm VFMSUB132PDZ : avx512_fma3p_m132<0x9A, "vfmsub132pd", VR512, f512mem,
2489 memopv8f64, f64mem, loadf64, "{1to8}",
2490 X86Fmsub, v8f64>, EVEX_V512, VEX_W,
2491 EVEX_CD8<64, CD8VF>;
2492 defm VFMADDSUB132PDZ : avx512_fma3p_m132<0x96, "vfmaddsub132pd", VR512, f512mem,
2493 memopv8f64, f64mem, loadf64, "{1to8}",
2494 X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
2495 EVEX_CD8<64, CD8VF>;
2496 defm VFMSUBADD132PDZ : avx512_fma3p_m132<0x97, "vfmsubadd132pd", VR512, f512mem,
2497 memopv8f64, f64mem, loadf64, "{1to8}",
2498 X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
2499 EVEX_CD8<64, CD8VF>;
2500 defm VFNMADD132PDZ : avx512_fma3p_m132<0x9C, "vfnmadd132pd", VR512, f512mem,
2501 memopv8f64, f64mem, loadf64, "{1to8}",
2502 X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
2503 EVEX_CD8<64, CD8VF>;
2504 defm VFNMSUB132PDZ : avx512_fma3p_m132<0x9E, "vfnmsub132pd", VR512, f512mem,
2505 memopv8f64, f64mem, loadf64, "{1to8}",
2506 X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
2507 EVEX_CD8<64, CD8VF>;
2511 let Constraints = "$src1 = $dst" in {
2512 multiclass avx512_fma3s_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2513 RegisterClass RC, ValueType OpVT,
2514 X86MemOperand x86memop, Operand memop,
2516 let isCommutable = 1 in
2517 def r : AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
2518 (ins RC:$src1, RC:$src2, RC:$src3),
2519 !strconcat(OpcodeStr,
2520 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2522 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
2524 def m : AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2525 (ins RC:$src1, RC:$src2, f128mem:$src3),
2526 !strconcat(OpcodeStr,
2527 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2529 (OpVT (OpNode RC:$src2, RC:$src1,
2530 (mem_frag addr:$src3))))]>;
2533 } // Constraints = "$src1 = $dst"
2535 defm VFMADDSSZ : avx512_fma3s_rm<0xA9, "vfmadd213ss", X86Fmadd, FR32X,
2536 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2537 defm VFMADDSDZ : avx512_fma3s_rm<0xA9, "vfmadd213sd", X86Fmadd, FR64X,
2538 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2539 defm VFMSUBSSZ : avx512_fma3s_rm<0xAB, "vfmsub213ss", X86Fmsub, FR32X,
2540 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2541 defm VFMSUBSDZ : avx512_fma3s_rm<0xAB, "vfmsub213sd", X86Fmsub, FR64X,
2542 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2543 defm VFNMADDSSZ : avx512_fma3s_rm<0xAD, "vfnmadd213ss", X86Fnmadd, FR32X,
2544 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2545 defm VFNMADDSDZ : avx512_fma3s_rm<0xAD, "vfnmadd213sd", X86Fnmadd, FR64X,
2546 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2547 defm VFNMSUBSSZ : avx512_fma3s_rm<0xAF, "vfnmsub213ss", X86Fnmsub, FR32X,
2548 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2549 defm VFNMSUBSDZ : avx512_fma3s_rm<0xAF, "vfnmsub213sd", X86Fnmsub, FR64X,
2550 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2552 //===----------------------------------------------------------------------===//
2553 // AVX-512 Scalar convert from sign integer to float/double
2554 //===----------------------------------------------------------------------===//
2556 multiclass avx512_vcvtsi<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2557 X86MemOperand x86memop, string asm> {
2558 let hasSideEffects = 0 in {
2559 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
2560 !strconcat(asm," \t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
2563 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
2564 (ins DstRC:$src1, x86memop:$src),
2565 !strconcat(asm," \t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
2567 } // hasSideEffects = 0
2569 let Predicates = [HasAVX512] in {
2570 defm VCVTSI2SSZ : avx512_vcvtsi<0x2A, GR32, FR32X, i32mem, "cvtsi2ss{l}">,
2571 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2572 defm VCVTSI642SSZ : avx512_vcvtsi<0x2A, GR64, FR32X, i64mem, "cvtsi2ss{q}">,
2573 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2574 defm VCVTSI2SDZ : avx512_vcvtsi<0x2A, GR32, FR64X, i32mem, "cvtsi2sd{l}">,
2575 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2576 defm VCVTSI642SDZ : avx512_vcvtsi<0x2A, GR64, FR64X, i64mem, "cvtsi2sd{q}">,
2577 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2579 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
2580 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2581 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
2582 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2583 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
2584 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2585 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
2586 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2588 def : Pat<(f32 (sint_to_fp GR32:$src)),
2589 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
2590 def : Pat<(f32 (sint_to_fp GR64:$src)),
2591 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
2592 def : Pat<(f64 (sint_to_fp GR32:$src)),
2593 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
2594 def : Pat<(f64 (sint_to_fp GR64:$src)),
2595 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
2597 defm VCVTUSI2SSZ : avx512_vcvtsi<0x7B, GR32, FR32X, i32mem, "cvtusi2ss{l}">,
2598 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2599 defm VCVTUSI642SSZ : avx512_vcvtsi<0x7B, GR64, FR32X, i64mem, "cvtusi2ss{q}">,
2600 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2601 defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, GR32, FR64X, i32mem, "cvtusi2sd{l}">,
2602 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2603 defm VCVTUSI642SDZ : avx512_vcvtsi<0x7B, GR64, FR64X, i64mem, "cvtusi2sd{q}">,
2604 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2606 def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
2607 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2608 def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
2609 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2610 def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
2611 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2612 def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
2613 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2615 def : Pat<(f32 (uint_to_fp GR32:$src)),
2616 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
2617 def : Pat<(f32 (uint_to_fp GR64:$src)),
2618 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
2619 def : Pat<(f64 (uint_to_fp GR32:$src)),
2620 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
2621 def : Pat<(f64 (uint_to_fp GR64:$src)),
2622 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
2625 //===----------------------------------------------------------------------===//
2626 // AVX-512 Scalar convert from float/double to integer
2627 //===----------------------------------------------------------------------===//
2628 multiclass avx512_cvt_s_int<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2629 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
2631 let hasSideEffects = 0 in {
2632 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2633 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
2634 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG,
2635 Requires<[HasAVX512]>;
2637 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
2638 !strconcat(asm," \t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG,
2639 Requires<[HasAVX512]>;
2640 } // hasSideEffects = 0
2642 let Predicates = [HasAVX512] in {
2643 // Convert float/double to signed/unsigned int 32/64
2644 defm VCVTSS2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
2645 ssmem, sse_load_f32, "cvtss2si">,
2646 XS, EVEX_CD8<32, CD8VT1>;
2647 defm VCVTSS2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse_cvtss2si64,
2648 ssmem, sse_load_f32, "cvtss2si">,
2649 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
2650 defm VCVTSS2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtss2usi,
2651 ssmem, sse_load_f32, "cvtss2usi">,
2652 XS, EVEX_CD8<32, CD8VT1>;
2653 defm VCVTSS2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
2654 int_x86_avx512_cvtss2usi64, ssmem,
2655 sse_load_f32, "cvtss2usi">, XS, VEX_W,
2656 EVEX_CD8<32, CD8VT1>;
2657 defm VCVTSD2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
2658 sdmem, sse_load_f64, "cvtsd2si">,
2659 XD, EVEX_CD8<64, CD8VT1>;
2660 defm VCVTSD2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse2_cvtsd2si64,
2661 sdmem, sse_load_f64, "cvtsd2si">,
2662 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
2663 defm VCVTSD2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtsd2usi,
2664 sdmem, sse_load_f64, "cvtsd2usi">,
2665 XD, EVEX_CD8<64, CD8VT1>;
2666 defm VCVTSD2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
2667 int_x86_avx512_cvtsd2usi64, sdmem,
2668 sse_load_f64, "cvtsd2usi">, XD, VEX_W,
2669 EVEX_CD8<64, CD8VT1>;
2671 let isCodeGenOnly = 1 in {
2672 defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2673 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
2674 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
2675 defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2676 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
2677 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
2678 defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2679 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
2680 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
2681 defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2682 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
2683 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
2685 defm Int_VCVTUSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2686 int_x86_avx512_cvtusi2ss, i32mem, loadi32, "cvtusi2ss{l}",
2687 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
2688 defm Int_VCVTUSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2689 int_x86_avx512_cvtusi642ss, i64mem, loadi64, "cvtusi2ss{q}",
2690 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
2691 defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2692 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}",
2693 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
2694 defm Int_VCVTUSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2695 int_x86_avx512_cvtusi642sd, i64mem, loadi64, "cvtusi2sd{q}",
2696 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
2697 } // isCodeGenOnly = 1
2699 // Convert float/double to signed/unsigned int 32/64 with truncation
2700 let isCodeGenOnly = 1 in {
2701 defm Int_VCVTTSS2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse_cvttss2si,
2702 ssmem, sse_load_f32, "cvttss2si">,
2703 XS, EVEX_CD8<32, CD8VT1>;
2704 defm Int_VCVTTSS2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
2705 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
2706 "cvttss2si">, XS, VEX_W,
2707 EVEX_CD8<32, CD8VT1>;
2708 defm Int_VCVTTSD2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse2_cvttsd2si,
2709 sdmem, sse_load_f64, "cvttsd2si">, XD,
2710 EVEX_CD8<64, CD8VT1>;
2711 defm Int_VCVTTSD2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
2712 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
2713 "cvttsd2si">, XD, VEX_W,
2714 EVEX_CD8<64, CD8VT1>;
2715 defm Int_VCVTTSS2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
2716 int_x86_avx512_cvttss2usi, ssmem, sse_load_f32,
2717 "cvttss2usi">, XS, EVEX_CD8<32, CD8VT1>;
2718 defm Int_VCVTTSS2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
2719 int_x86_avx512_cvttss2usi64, ssmem,
2720 sse_load_f32, "cvttss2usi">, XS, VEX_W,
2721 EVEX_CD8<32, CD8VT1>;
2722 defm Int_VCVTTSD2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
2723 int_x86_avx512_cvttsd2usi,
2724 sdmem, sse_load_f64, "cvttsd2usi">, XD,
2725 EVEX_CD8<64, CD8VT1>;
2726 defm Int_VCVTTSD2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
2727 int_x86_avx512_cvttsd2usi64, sdmem,
2728 sse_load_f64, "cvttsd2usi">, XD, VEX_W,
2729 EVEX_CD8<64, CD8VT1>;
2730 } // isCodeGenOnly = 1
2732 multiclass avx512_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2733 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
2735 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2736 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
2737 [(set DstRC:$dst, (OpNode SrcRC:$src))]>, EVEX;
2738 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
2739 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
2740 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>, EVEX;
2743 defm VCVTTSS2SIZ : avx512_cvt_s<0x2C, FR32X, GR32, fp_to_sint, f32mem,
2744 loadf32, "cvttss2si">, XS,
2745 EVEX_CD8<32, CD8VT1>;
2746 defm VCVTTSS2USIZ : avx512_cvt_s<0x78, FR32X, GR32, fp_to_uint, f32mem,
2747 loadf32, "cvttss2usi">, XS,
2748 EVEX_CD8<32, CD8VT1>;
2749 defm VCVTTSS2SI64Z : avx512_cvt_s<0x2C, FR32X, GR64, fp_to_sint, f32mem,
2750 loadf32, "cvttss2si">, XS, VEX_W,
2751 EVEX_CD8<32, CD8VT1>;
2752 defm VCVTTSS2USI64Z : avx512_cvt_s<0x78, FR32X, GR64, fp_to_uint, f32mem,
2753 loadf32, "cvttss2usi">, XS, VEX_W,
2754 EVEX_CD8<32, CD8VT1>;
2755 defm VCVTTSD2SIZ : avx512_cvt_s<0x2C, FR64X, GR32, fp_to_sint, f64mem,
2756 loadf64, "cvttsd2si">, XD,
2757 EVEX_CD8<64, CD8VT1>;
2758 defm VCVTTSD2USIZ : avx512_cvt_s<0x78, FR64X, GR32, fp_to_uint, f64mem,
2759 loadf64, "cvttsd2usi">, XD,
2760 EVEX_CD8<64, CD8VT1>;
2761 defm VCVTTSD2SI64Z : avx512_cvt_s<0x2C, FR64X, GR64, fp_to_sint, f64mem,
2762 loadf64, "cvttsd2si">, XD, VEX_W,
2763 EVEX_CD8<64, CD8VT1>;
2764 defm VCVTTSD2USI64Z : avx512_cvt_s<0x78, FR64X, GR64, fp_to_uint, f64mem,
2765 loadf64, "cvttsd2usi">, XD, VEX_W,
2766 EVEX_CD8<64, CD8VT1>;
2768 //===----------------------------------------------------------------------===//
2769 // AVX-512 Convert form float to double and back
2770 //===----------------------------------------------------------------------===//
2771 let hasSideEffects = 0 in {
2772 def VCVTSS2SDZrr : AVX512XSI<0x5A, MRMSrcReg, (outs FR64X:$dst),
2773 (ins FR32X:$src1, FR32X:$src2),
2774 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2775 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
2777 def VCVTSS2SDZrm : AVX512XSI<0x5A, MRMSrcMem, (outs FR64X:$dst),
2778 (ins FR32X:$src1, f32mem:$src2),
2779 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2780 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
2781 EVEX_CD8<32, CD8VT1>;
2783 // Convert scalar double to scalar single
2784 def VCVTSD2SSZrr : AVX512XDI<0x5A, MRMSrcReg, (outs FR32X:$dst),
2785 (ins FR64X:$src1, FR64X:$src2),
2786 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2787 []>, EVEX_4V, VEX_LIG, VEX_W, Sched<[WriteCvtF2F]>;
2789 def VCVTSD2SSZrm : AVX512XDI<0x5A, MRMSrcMem, (outs FR32X:$dst),
2790 (ins FR64X:$src1, f64mem:$src2),
2791 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2792 []>, EVEX_4V, VEX_LIG, VEX_W,
2793 Sched<[WriteCvtF2FLd, ReadAfterLd]>, EVEX_CD8<64, CD8VT1>;
2796 def : Pat<(f64 (fextend FR32X:$src)), (VCVTSS2SDZrr FR32X:$src, FR32X:$src)>,
2797 Requires<[HasAVX512]>;
2798 def : Pat<(fextend (loadf32 addr:$src)),
2799 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512]>;
2801 def : Pat<(extloadf32 addr:$src),
2802 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>,
2803 Requires<[HasAVX512, OptForSize]>;
2805 def : Pat<(extloadf32 addr:$src),
2806 (VCVTSS2SDZrr (f32 (IMPLICIT_DEF)), (VMOVSSZrm addr:$src))>,
2807 Requires<[HasAVX512, OptForSpeed]>;
2809 def : Pat<(f32 (fround FR64X:$src)), (VCVTSD2SSZrr FR64X:$src, FR64X:$src)>,
2810 Requires<[HasAVX512]>;
2812 multiclass avx512_vcvt_fp_with_rc<bits<8> opc, string asm, RegisterClass SrcRC,
2813 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
2814 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
2816 let hasSideEffects = 0 in {
2817 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2818 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
2820 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
2821 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
2822 !strconcat(asm," \t{$rc, $src, $dst|$dst, $src, $rc}"),
2823 [], d>, EVEX, EVEX_B, EVEX_RC;
2825 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
2826 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
2828 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
2829 } // hasSideEffects = 0
2832 multiclass avx512_vcvt_fp<bits<8> opc, string asm, RegisterClass SrcRC,
2833 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
2834 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
2836 let hasSideEffects = 0 in {
2837 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2838 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
2840 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
2842 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
2843 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
2845 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
2846 } // hasSideEffects = 0
2849 defm VCVTPD2PSZ : avx512_vcvt_fp_with_rc<0x5A, "vcvtpd2ps", VR512, VR256X, fround,
2850 memopv8f64, f512mem, v8f32, v8f64,
2851 SSEPackedSingle>, EVEX_V512, VEX_W, PD,
2852 EVEX_CD8<64, CD8VF>;
2854 defm VCVTPS2PDZ : avx512_vcvt_fp<0x5A, "vcvtps2pd", VR256X, VR512, fextend,
2855 memopv4f64, f256mem, v8f64, v8f32,
2856 SSEPackedDouble>, EVEX_V512, EVEX_CD8<32, CD8VH>;
2857 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
2858 (VCVTPS2PDZrm addr:$src)>;
2860 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
2861 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), (i32 FROUND_CURRENT))),
2862 (VCVTPD2PSZrr VR512:$src)>;
2864 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
2865 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), imm:$rc)),
2866 (VCVTPD2PSZrrb VR512:$src, imm:$rc)>;
2868 //===----------------------------------------------------------------------===//
2869 // AVX-512 Vector convert from sign integer to float/double
2870 //===----------------------------------------------------------------------===//
2872 defm VCVTDQ2PSZ : avx512_vcvt_fp_with_rc<0x5B, "vcvtdq2ps", VR512, VR512, sint_to_fp,
2873 memopv8i64, i512mem, v16f32, v16i32,
2874 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2876 defm VCVTDQ2PDZ : avx512_vcvt_fp<0xE6, "vcvtdq2pd", VR256X, VR512, sint_to_fp,
2877 memopv4i64, i256mem, v8f64, v8i32,
2878 SSEPackedDouble>, EVEX_V512, XS,
2879 EVEX_CD8<32, CD8VH>;
2881 defm VCVTTPS2DQZ : avx512_vcvt_fp<0x5B, "vcvttps2dq", VR512, VR512, fp_to_sint,
2882 memopv16f32, f512mem, v16i32, v16f32,
2883 SSEPackedSingle>, EVEX_V512, XS,
2884 EVEX_CD8<32, CD8VF>;
2886 defm VCVTTPD2DQZ : avx512_vcvt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint,
2887 memopv8f64, f512mem, v8i32, v8f64,
2888 SSEPackedDouble>, EVEX_V512, PD, VEX_W,
2889 EVEX_CD8<64, CD8VF>;
2891 defm VCVTTPS2UDQZ : avx512_vcvt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint,
2892 memopv16f32, f512mem, v16i32, v16f32,
2893 SSEPackedSingle>, EVEX_V512,
2894 EVEX_CD8<32, CD8VF>;
2896 // cvttps2udq (src, 0, mask-all-ones, sae-current)
2897 def : Pat<(v16i32 (int_x86_avx512_mask_cvttps2udq_512 (v16f32 VR512:$src),
2898 (v16i32 immAllZerosV), (i16 -1), FROUND_CURRENT)),
2899 (VCVTTPS2UDQZrr VR512:$src)>;
2901 defm VCVTTPD2UDQZ : avx512_vcvt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint,
2902 memopv8f64, f512mem, v8i32, v8f64,
2903 SSEPackedDouble>, EVEX_V512, VEX_W,
2904 EVEX_CD8<64, CD8VF>;
2906 // cvttpd2udq (src, 0, mask-all-ones, sae-current)
2907 def : Pat<(v8i32 (int_x86_avx512_mask_cvttpd2udq_512 (v8f64 VR512:$src),
2908 (v8i32 immAllZerosV), (i8 -1), FROUND_CURRENT)),
2909 (VCVTTPD2UDQZrr VR512:$src)>;
2911 defm VCVTUDQ2PDZ : avx512_vcvt_fp<0x7A, "vcvtudq2pd", VR256X, VR512, uint_to_fp,
2912 memopv4i64, f256mem, v8f64, v8i32,
2913 SSEPackedDouble>, EVEX_V512, XS,
2914 EVEX_CD8<32, CD8VH>;
2916 defm VCVTUDQ2PSZ : avx512_vcvt_fp_with_rc<0x7A, "vcvtudq2ps", VR512, VR512, uint_to_fp,
2917 memopv16i32, f512mem, v16f32, v16i32,
2918 SSEPackedSingle>, EVEX_V512, XD,
2919 EVEX_CD8<32, CD8VF>;
2921 def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
2922 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
2923 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
2926 def : Pat<(v16f32 (int_x86_avx512_mask_cvtdq2ps_512 (v16i32 VR512:$src),
2927 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
2928 (VCVTDQ2PSZrrb VR512:$src, imm:$rc)>;
2929 def : Pat<(v8f64 (int_x86_avx512_mask_cvtdq2pd_512 (v8i32 VR256X:$src),
2930 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
2931 (VCVTDQ2PDZrr VR256X:$src)>;
2932 def : Pat<(v16f32 (int_x86_avx512_mask_cvtudq2ps_512 (v16i32 VR512:$src),
2933 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
2934 (VCVTUDQ2PSZrrb VR512:$src, imm:$rc)>;
2935 def : Pat<(v8f64 (int_x86_avx512_mask_cvtudq2pd_512 (v8i32 VR256X:$src),
2936 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
2937 (VCVTUDQ2PDZrr VR256X:$src)>;
2939 multiclass avx512_vcvt_fp2int<bits<8> opc, string asm, RegisterClass SrcRC,
2940 RegisterClass DstRC, PatFrag mem_frag,
2941 X86MemOperand x86memop, Domain d> {
2942 let hasSideEffects = 0 in {
2943 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2944 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
2946 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
2947 !strconcat(asm," \t{$rc, $src, $dst|$dst, $src, $rc}"),
2948 [], d>, EVEX, EVEX_B, EVEX_RC;
2950 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
2951 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
2953 } // hasSideEffects = 0
2956 defm VCVTPS2DQZ : avx512_vcvt_fp2int<0x5B, "vcvtps2dq", VR512, VR512,
2957 memopv16f32, f512mem, SSEPackedSingle>, PD,
2958 EVEX_V512, EVEX_CD8<32, CD8VF>;
2959 defm VCVTPD2DQZ : avx512_vcvt_fp2int<0xE6, "vcvtpd2dq", VR512, VR256X,
2960 memopv8f64, f512mem, SSEPackedDouble>, XD, VEX_W,
2961 EVEX_V512, EVEX_CD8<64, CD8VF>;
2963 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2dq_512 (v16f32 VR512:$src),
2964 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
2965 (VCVTPS2DQZrrb VR512:$src, imm:$rc)>;
2967 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2dq_512 (v8f64 VR512:$src),
2968 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
2969 (VCVTPD2DQZrrb VR512:$src, imm:$rc)>;
2971 defm VCVTPS2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtps2udq", VR512, VR512,
2972 memopv16f32, f512mem, SSEPackedSingle>,
2973 EVEX_V512, EVEX_CD8<32, CD8VF>;
2974 defm VCVTPD2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtpd2udq", VR512, VR256X,
2975 memopv8f64, f512mem, SSEPackedDouble>, VEX_W,
2976 EVEX_V512, EVEX_CD8<64, CD8VF>;
2978 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2udq_512 (v16f32 VR512:$src),
2979 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
2980 (VCVTPS2UDQZrrb VR512:$src, imm:$rc)>;
2982 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2udq_512 (v8f64 VR512:$src),
2983 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
2984 (VCVTPD2UDQZrrb VR512:$src, imm:$rc)>;
2986 let Predicates = [HasAVX512] in {
2987 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
2988 (VCVTPD2PSZrm addr:$src)>;
2989 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
2990 (VCVTPS2PDZrm addr:$src)>;
2993 //===----------------------------------------------------------------------===//
2994 // Half precision conversion instructions
2995 //===----------------------------------------------------------------------===//
2996 multiclass avx512_f16c_ph2ps<RegisterClass destRC, RegisterClass srcRC,
2997 X86MemOperand x86memop, Intrinsic Int> {
2998 def rr : AVX5128I<0x13, MRMSrcReg, (outs destRC:$dst), (ins srcRC:$src),
2999 "vcvtph2ps\t{$src, $dst|$dst, $src}",
3000 [(set destRC:$dst, (Int srcRC:$src))]>, EVEX;
3001 let hasSideEffects = 0, mayLoad = 1 in
3002 def rm : AVX5128I<0x13, MRMSrcMem, (outs destRC:$dst), (ins x86memop:$src),
3003 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, EVEX;
3006 multiclass avx512_f16c_ps2ph<RegisterClass destRC, RegisterClass srcRC,
3007 X86MemOperand x86memop, Intrinsic Int> {
3008 def rr : AVX512AIi8<0x1D, MRMDestReg, (outs destRC:$dst),
3009 (ins srcRC:$src1, i32i8imm:$src2),
3010 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3011 [(set destRC:$dst, (Int srcRC:$src1, imm:$src2))]>, EVEX;
3012 let hasSideEffects = 0, mayStore = 1 in
3013 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
3014 (ins x86memop:$dst, srcRC:$src1, i32i8imm:$src2),
3015 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, EVEX;
3018 defm VCVTPH2PSZ : avx512_f16c_ph2ps<VR512, VR256X, f256mem,
3019 int_x86_avx512_vcvtph2ps_512>, EVEX_V512,
3020 EVEX_CD8<32, CD8VH>;
3021 defm VCVTPS2PHZ : avx512_f16c_ps2ph<VR256X, VR512, f256mem,
3022 int_x86_avx512_vcvtps2ph_512>, EVEX_V512,
3023 EVEX_CD8<32, CD8VH>;
3025 let Defs = [EFLAGS], Predicates = [HasAVX512] in {
3026 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
3027 "ucomiss">, TB, EVEX, VEX_LIG,
3028 EVEX_CD8<32, CD8VT1>;
3029 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
3030 "ucomisd">, PD, EVEX,
3031 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3032 let Pattern = []<dag> in {
3033 defm VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, undef, v4f32, f128mem, load,
3034 "comiss">, TB, EVEX, VEX_LIG,
3035 EVEX_CD8<32, CD8VT1>;
3036 defm VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, undef, v2f64, f128mem, load,
3037 "comisd">, PD, EVEX,
3038 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3040 let isCodeGenOnly = 1 in {
3041 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
3042 load, "ucomiss">, TB, EVEX, VEX_LIG,
3043 EVEX_CD8<32, CD8VT1>;
3044 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
3045 load, "ucomisd">, PD, EVEX,
3046 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3048 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
3049 load, "comiss">, TB, EVEX, VEX_LIG,
3050 EVEX_CD8<32, CD8VT1>;
3051 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
3052 load, "comisd">, PD, EVEX,
3053 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3057 /// avx512_fp14_s rcp14ss, rcp14sd, rsqrt14ss, rsqrt14sd
3058 multiclass avx512_fp14_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
3059 X86MemOperand x86memop> {
3060 let hasSideEffects = 0 in {
3061 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3062 (ins RC:$src1, RC:$src2),
3063 !strconcat(OpcodeStr,
3064 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3065 let mayLoad = 1 in {
3066 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3067 (ins RC:$src1, x86memop:$src2),
3068 !strconcat(OpcodeStr,
3069 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3074 defm VRCP14SS : avx512_fp14_s<0x4D, "vrcp14ss", FR32X, f32mem>,
3075 EVEX_CD8<32, CD8VT1>;
3076 defm VRCP14SD : avx512_fp14_s<0x4D, "vrcp14sd", FR64X, f64mem>,
3077 VEX_W, EVEX_CD8<64, CD8VT1>;
3078 defm VRSQRT14SS : avx512_fp14_s<0x4F, "vrsqrt14ss", FR32X, f32mem>,
3079 EVEX_CD8<32, CD8VT1>;
3080 defm VRSQRT14SD : avx512_fp14_s<0x4F, "vrsqrt14sd", FR64X, f64mem>,
3081 VEX_W, EVEX_CD8<64, CD8VT1>;
3083 def : Pat <(v4f32 (int_x86_avx512_rcp14_ss (v4f32 VR128X:$src1),
3084 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
3085 (COPY_TO_REGCLASS (VRCP14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3086 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3088 def : Pat <(v2f64 (int_x86_avx512_rcp14_sd (v2f64 VR128X:$src1),
3089 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
3090 (COPY_TO_REGCLASS (VRCP14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3091 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3093 def : Pat <(v4f32 (int_x86_avx512_rsqrt14_ss (v4f32 VR128X:$src1),
3094 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
3095 (COPY_TO_REGCLASS (VRSQRT14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3096 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3098 def : Pat <(v2f64 (int_x86_avx512_rsqrt14_sd (v2f64 VR128X:$src1),
3099 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
3100 (COPY_TO_REGCLASS (VRSQRT14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3101 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3103 /// avx512_fp14_p rcp14ps, rcp14pd, rsqrt14ps, rsqrt14pd
3104 multiclass avx512_fp14_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3105 RegisterClass RC, X86MemOperand x86memop,
3106 PatFrag mem_frag, ValueType OpVt> {
3107 def r : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3108 !strconcat(OpcodeStr,
3109 " \t{$src, $dst|$dst, $src}"),
3110 [(set RC:$dst, (OpVt (OpNode RC:$src)))]>,
3112 def m : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3113 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3114 [(set RC:$dst, (OpVt (OpNode (mem_frag addr:$src))))]>,
3117 defm VRSQRT14PSZ : avx512_fp14_p<0x4E, "vrsqrt14ps", X86frsqrt, VR512, f512mem,
3118 memopv16f32, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
3119 defm VRSQRT14PDZ : avx512_fp14_p<0x4E, "vrsqrt14pd", X86frsqrt, VR512, f512mem,
3120 memopv8f64, v8f64>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3121 defm VRCP14PSZ : avx512_fp14_p<0x4C, "vrcp14ps", X86frcp, VR512, f512mem,
3122 memopv16f32, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
3123 defm VRCP14PDZ : avx512_fp14_p<0x4C, "vrcp14pd", X86frcp, VR512, f512mem,
3124 memopv8f64, v8f64>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3126 def : Pat <(v16f32 (int_x86_avx512_rsqrt14_ps_512 (v16f32 VR512:$src),
3127 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
3128 (VRSQRT14PSZr VR512:$src)>;
3129 def : Pat <(v8f64 (int_x86_avx512_rsqrt14_pd_512 (v8f64 VR512:$src),
3130 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3131 (VRSQRT14PDZr VR512:$src)>;
3133 def : Pat <(v16f32 (int_x86_avx512_rcp14_ps_512 (v16f32 VR512:$src),
3134 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
3135 (VRCP14PSZr VR512:$src)>;
3136 def : Pat <(v8f64 (int_x86_avx512_rcp14_pd_512 (v8f64 VR512:$src),
3137 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3138 (VRCP14PDZr VR512:$src)>;
3140 /// avx512_fp28_s rcp28ss, rcp28sd, rsqrt28ss, rsqrt28sd
3141 multiclass avx512_fp28_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
3142 X86MemOperand x86memop> {
3143 let hasSideEffects = 0, Predicates = [HasERI] in {
3144 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3145 (ins RC:$src1, RC:$src2),
3146 !strconcat(OpcodeStr,
3147 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3148 def rrb : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3149 (ins RC:$src1, RC:$src2),
3150 !strconcat(OpcodeStr,
3151 " \t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
3152 []>, EVEX_4V, EVEX_B;
3153 let mayLoad = 1 in {
3154 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3155 (ins RC:$src1, x86memop:$src2),
3156 !strconcat(OpcodeStr,
3157 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3162 defm VRCP28SS : avx512_fp28_s<0xCB, "vrcp28ss", FR32X, f32mem>,
3163 EVEX_CD8<32, CD8VT1>;
3164 defm VRCP28SD : avx512_fp28_s<0xCB, "vrcp28sd", FR64X, f64mem>,
3165 VEX_W, EVEX_CD8<64, CD8VT1>;
3166 defm VRSQRT28SS : avx512_fp28_s<0xCD, "vrsqrt28ss", FR32X, f32mem>,
3167 EVEX_CD8<32, CD8VT1>;
3168 defm VRSQRT28SD : avx512_fp28_s<0xCD, "vrsqrt28sd", FR64X, f64mem>,
3169 VEX_W, EVEX_CD8<64, CD8VT1>;
3171 def : Pat <(v4f32 (int_x86_avx512_rcp28_ss (v4f32 VR128X:$src1),
3172 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1),
3174 (COPY_TO_REGCLASS (VRCP28SSrrb (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3175 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3177 def : Pat <(v2f64 (int_x86_avx512_rcp28_sd (v2f64 VR128X:$src1),
3178 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1),
3180 (COPY_TO_REGCLASS (VRCP28SDrrb (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3181 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3183 def : Pat <(v4f32 (int_x86_avx512_rsqrt28_ss (v4f32 VR128X:$src1),
3184 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1),
3186 (COPY_TO_REGCLASS (VRSQRT28SSrrb (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3187 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3189 def : Pat <(v2f64 (int_x86_avx512_rsqrt28_sd (v2f64 VR128X:$src1),
3190 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1),
3192 (COPY_TO_REGCLASS (VRSQRT28SDrrb (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3193 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3195 /// avx512_fp28_p rcp28ps, rcp28pd, rsqrt28ps, rsqrt28pd
3196 multiclass avx512_fp28_p<bits<8> opc, string OpcodeStr,
3197 RegisterClass RC, X86MemOperand x86memop> {
3198 let hasSideEffects = 0, Predicates = [HasERI] in {
3199 def r : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3200 !strconcat(OpcodeStr,
3201 " \t{$src, $dst|$dst, $src}"),
3203 def rb : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3204 !strconcat(OpcodeStr,
3205 " \t{{sae}, $src, $dst|$dst, $src, {sae}}"),
3207 def m : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3208 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3212 defm VRSQRT28PSZ : avx512_fp28_p<0xCC, "vrsqrt28ps", VR512, f512mem>,
3213 EVEX_V512, EVEX_CD8<32, CD8VF>;
3214 defm VRSQRT28PDZ : avx512_fp28_p<0xCC, "vrsqrt28pd", VR512, f512mem>,
3215 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3216 defm VRCP28PSZ : avx512_fp28_p<0xCA, "vrcp28ps", VR512, f512mem>,
3217 EVEX_V512, EVEX_CD8<32, CD8VF>;
3218 defm VRCP28PDZ : avx512_fp28_p<0xCA, "vrcp28pd", VR512, f512mem>,
3219 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3221 def : Pat <(v16f32 (int_x86_avx512_rsqrt28_ps (v16f32 VR512:$src),
3222 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_NO_EXC)),
3223 (VRSQRT28PSZrb VR512:$src)>;
3224 def : Pat <(v8f64 (int_x86_avx512_rsqrt28_pd (v8f64 VR512:$src),
3225 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_NO_EXC)),
3226 (VRSQRT28PDZrb VR512:$src)>;
3228 def : Pat <(v16f32 (int_x86_avx512_rcp28_ps (v16f32 VR512:$src),
3229 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_NO_EXC)),
3230 (VRCP28PSZrb VR512:$src)>;
3231 def : Pat <(v8f64 (int_x86_avx512_rcp28_pd (v8f64 VR512:$src),
3232 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_NO_EXC)),
3233 (VRCP28PDZrb VR512:$src)>;
3235 multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
3236 Intrinsic V16F32Int, Intrinsic V8F64Int,
3237 OpndItins itins_s, OpndItins itins_d> {
3238 def PSZrr :AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3239 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3240 [(set VR512:$dst, (v16f32 (OpNode VR512:$src)))], itins_s.rr>,
3244 def PSZrm : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3245 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3247 (OpNode (v16f32 (bitconvert (memopv16f32 addr:$src)))))],
3248 itins_s.rm>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
3250 def PDZrr : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3251 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3252 [(set VR512:$dst, (v8f64 (OpNode VR512:$src)))], itins_d.rr>,
3256 def PDZrm : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3257 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3258 [(set VR512:$dst, (OpNode
3259 (v8f64 (bitconvert (memopv16f32 addr:$src)))))],
3260 itins_d.rm>, EVEX, EVEX_V512, EVEX_CD8<64, CD8VF>;
3262 let isCodeGenOnly = 1 in {
3263 def PSZr_Int : AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3264 !strconcat(OpcodeStr,
3265 "ps\t{$src, $dst|$dst, $src}"),
3266 [(set VR512:$dst, (V16F32Int VR512:$src))]>,
3268 def PSZm_Int : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3269 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3271 (V16F32Int (memopv16f32 addr:$src)))]>, EVEX,
3272 EVEX_V512, EVEX_CD8<32, CD8VF>;
3273 def PDZr_Int : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3274 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3275 [(set VR512:$dst, (V8F64Int VR512:$src))]>,
3276 EVEX, EVEX_V512, VEX_W;
3277 def PDZm_Int : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3278 !strconcat(OpcodeStr,
3279 "pd\t{$src, $dst|$dst, $src}"),
3280 [(set VR512:$dst, (V8F64Int (memopv8f64 addr:$src)))]>,
3281 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3282 } // isCodeGenOnly = 1
3285 multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,
3286 Intrinsic F32Int, Intrinsic F64Int,
3287 OpndItins itins_s, OpndItins itins_d> {
3288 def SSZr : SI<opc, MRMSrcReg, (outs FR32X:$dst),
3289 (ins FR32X:$src1, FR32X:$src2),
3290 !strconcat(OpcodeStr,
3291 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3292 [], itins_s.rr>, XS, EVEX_4V;
3293 let isCodeGenOnly = 1 in
3294 def SSZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
3295 (ins VR128X:$src1, VR128X:$src2),
3296 !strconcat(OpcodeStr,
3297 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3299 (F32Int VR128X:$src1, VR128X:$src2))],
3300 itins_s.rr>, XS, EVEX_4V;
3301 let mayLoad = 1 in {
3302 def SSZm : SI<opc, MRMSrcMem, (outs FR32X:$dst),
3303 (ins FR32X:$src1, f32mem:$src2),
3304 !strconcat(OpcodeStr,
3305 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3306 [], itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
3307 let isCodeGenOnly = 1 in
3308 def SSZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
3309 (ins VR128X:$src1, ssmem:$src2),
3310 !strconcat(OpcodeStr,
3311 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3313 (F32Int VR128X:$src1, sse_load_f32:$src2))],
3314 itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
3316 def SDZr : SI<opc, MRMSrcReg, (outs FR64X:$dst),
3317 (ins FR64X:$src1, FR64X:$src2),
3318 !strconcat(OpcodeStr,
3319 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
3321 let isCodeGenOnly = 1 in
3322 def SDZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
3323 (ins VR128X:$src1, VR128X:$src2),
3324 !strconcat(OpcodeStr,
3325 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3327 (F64Int VR128X:$src1, VR128X:$src2))],
3328 itins_s.rr>, XD, EVEX_4V, VEX_W;
3329 let mayLoad = 1 in {
3330 def SDZm : SI<opc, MRMSrcMem, (outs FR64X:$dst),
3331 (ins FR64X:$src1, f64mem:$src2),
3332 !strconcat(OpcodeStr,
3333 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
3334 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
3335 let isCodeGenOnly = 1 in
3336 def SDZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
3337 (ins VR128X:$src1, sdmem:$src2),
3338 !strconcat(OpcodeStr,
3339 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3341 (F64Int VR128X:$src1, sse_load_f64:$src2))]>,
3342 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
3347 defm VSQRT : avx512_sqrt_scalar<0x51, "sqrt",
3348 int_x86_avx512_sqrt_ss, int_x86_avx512_sqrt_sd,
3349 SSE_SQRTSS, SSE_SQRTSD>,
3350 avx512_sqrt_packed<0x51, "vsqrt", fsqrt,
3351 int_x86_avx512_sqrt_ps_512, int_x86_avx512_sqrt_pd_512,
3352 SSE_SQRTPS, SSE_SQRTPD>;
3354 let Predicates = [HasAVX512] in {
3355 def : Pat<(f32 (fsqrt FR32X:$src)),
3356 (VSQRTSSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3357 def : Pat<(f32 (fsqrt (load addr:$src))),
3358 (VSQRTSSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
3359 Requires<[OptForSize]>;
3360 def : Pat<(f64 (fsqrt FR64X:$src)),
3361 (VSQRTSDZr (f64 (IMPLICIT_DEF)), FR64X:$src)>;
3362 def : Pat<(f64 (fsqrt (load addr:$src))),
3363 (VSQRTSDZm (f64 (IMPLICIT_DEF)), addr:$src)>,
3364 Requires<[OptForSize]>;
3366 def : Pat<(f32 (X86frsqrt FR32X:$src)),
3367 (VRSQRT14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3368 def : Pat<(f32 (X86frsqrt (load addr:$src))),
3369 (VRSQRT14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
3370 Requires<[OptForSize]>;
3372 def : Pat<(f32 (X86frcp FR32X:$src)),
3373 (VRCP14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3374 def : Pat<(f32 (X86frcp (load addr:$src))),
3375 (VRCP14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
3376 Requires<[OptForSize]>;
3378 def : Pat<(int_x86_sse_sqrt_ss VR128X:$src),
3379 (COPY_TO_REGCLASS (VSQRTSSZr (f32 (IMPLICIT_DEF)),
3380 (COPY_TO_REGCLASS VR128X:$src, FR32)),
3382 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
3383 (VSQRTSSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3385 def : Pat<(int_x86_sse2_sqrt_sd VR128X:$src),
3386 (COPY_TO_REGCLASS (VSQRTSDZr (f64 (IMPLICIT_DEF)),
3387 (COPY_TO_REGCLASS VR128X:$src, FR64)),
3389 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
3390 (VSQRTSDZm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
3394 multiclass avx512_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
3395 X86MemOperand x86memop, RegisterClass RC,
3396 PatFrag mem_frag32, PatFrag mem_frag64,
3397 Intrinsic V4F32Int, Intrinsic V2F64Int,
3399 let ExeDomain = SSEPackedSingle in {
3400 // Intrinsic operation, reg.
3401 // Vector intrinsic operation, reg
3402 def PSr : AVX512AIi8<opcps, MRMSrcReg,
3403 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
3404 !strconcat(OpcodeStr,
3405 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3406 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>;
3408 // Vector intrinsic operation, mem
3409 def PSm : AVX512AIi8<opcps, MRMSrcMem,
3410 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
3411 !strconcat(OpcodeStr,
3412 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3414 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
3415 EVEX_CD8<32, VForm>;
3416 } // ExeDomain = SSEPackedSingle
3418 let ExeDomain = SSEPackedDouble in {
3419 // Vector intrinsic operation, reg
3420 def PDr : AVX512AIi8<opcpd, MRMSrcReg,
3421 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
3422 !strconcat(OpcodeStr,
3423 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3424 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>;
3426 // Vector intrinsic operation, mem
3427 def PDm : AVX512AIi8<opcpd, MRMSrcMem,
3428 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
3429 !strconcat(OpcodeStr,
3430 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3432 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
3433 EVEX_CD8<64, VForm>;
3434 } // ExeDomain = SSEPackedDouble
3437 multiclass avx512_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
3441 let ExeDomain = GenericDomain in {
3443 let hasSideEffects = 0 in
3444 def SSr : AVX512AIi8<opcss, MRMSrcReg,
3445 (outs FR32X:$dst), (ins FR32X:$src1, FR32X:$src2, i32i8imm:$src3),
3446 !strconcat(OpcodeStr,
3447 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3450 // Intrinsic operation, reg.
3451 let isCodeGenOnly = 1 in
3452 def SSr_Int : AVX512AIi8<opcss, MRMSrcReg,
3453 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
3454 !strconcat(OpcodeStr,
3455 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3456 [(set VR128X:$dst, (F32Int VR128X:$src1, VR128X:$src2, imm:$src3))]>;
3458 // Intrinsic operation, mem.
3459 def SSm : AVX512AIi8<opcss, MRMSrcMem, (outs VR128X:$dst),
3460 (ins VR128X:$src1, ssmem:$src2, i32i8imm:$src3),
3461 !strconcat(OpcodeStr,
3462 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3463 [(set VR128X:$dst, (F32Int VR128X:$src1,
3464 sse_load_f32:$src2, imm:$src3))]>,
3465 EVEX_CD8<32, CD8VT1>;
3468 let hasSideEffects = 0 in
3469 def SDr : AVX512AIi8<opcsd, MRMSrcReg,
3470 (outs FR64X:$dst), (ins FR64X:$src1, FR64X:$src2, i32i8imm:$src3),
3471 !strconcat(OpcodeStr,
3472 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3475 // Intrinsic operation, reg.
3476 let isCodeGenOnly = 1 in
3477 def SDr_Int : AVX512AIi8<opcsd, MRMSrcReg,
3478 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
3479 !strconcat(OpcodeStr,
3480 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3481 [(set VR128X:$dst, (F64Int VR128X:$src1, VR128X:$src2, imm:$src3))]>,
3484 // Intrinsic operation, mem.
3485 def SDm : AVX512AIi8<opcsd, MRMSrcMem,
3486 (outs VR128X:$dst), (ins VR128X:$src1, sdmem:$src2, i32i8imm:$src3),
3487 !strconcat(OpcodeStr,
3488 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3490 (F64Int VR128X:$src1, sse_load_f64:$src2, imm:$src3))]>,
3491 VEX_W, EVEX_CD8<64, CD8VT1>;
3492 } // ExeDomain = GenericDomain
3495 multiclass avx512_rndscale<bits<8> opc, string OpcodeStr,
3496 X86MemOperand x86memop, RegisterClass RC,
3497 PatFrag mem_frag, Domain d> {
3498 let ExeDomain = d in {
3499 // Intrinsic operation, reg.
3500 // Vector intrinsic operation, reg
3501 def r : AVX512AIi8<opc, MRMSrcReg,
3502 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
3503 !strconcat(OpcodeStr,
3504 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3507 // Vector intrinsic operation, mem
3508 def m : AVX512AIi8<opc, MRMSrcMem,
3509 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
3510 !strconcat(OpcodeStr,
3511 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3517 defm VRNDSCALEPSZ : avx512_rndscale<0x08, "vrndscaleps", f512mem, VR512,
3518 memopv16f32, SSEPackedSingle>, EVEX_V512,
3519 EVEX_CD8<32, CD8VF>;
3521 def : Pat<(v16f32 (int_x86_avx512_mask_rndscale_ps_512 (v16f32 VR512:$src1),
3522 imm:$src2, (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1),
3524 (VRNDSCALEPSZr VR512:$src1, imm:$src2)>;
3527 defm VRNDSCALEPDZ : avx512_rndscale<0x09, "vrndscalepd", f512mem, VR512,
3528 memopv8f64, SSEPackedDouble>, EVEX_V512,
3529 VEX_W, EVEX_CD8<64, CD8VF>;
3531 def : Pat<(v8f64 (int_x86_avx512_mask_rndscale_pd_512 (v8f64 VR512:$src1),
3532 imm:$src2, (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1),
3534 (VRNDSCALEPDZr VR512:$src1, imm:$src2)>;
3536 multiclass avx512_rndscale_scalar<bits<8> opc, string OpcodeStr,
3537 Operand x86memop, RegisterClass RC, Domain d> {
3538 let ExeDomain = d in {
3539 def r : AVX512AIi8<opc, MRMSrcReg,
3540 (outs RC:$dst), (ins RC:$src1, RC:$src2, i32i8imm:$src3),
3541 !strconcat(OpcodeStr,
3542 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3545 def m : AVX512AIi8<opc, MRMSrcMem,
3546 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i32i8imm:$src3),
3547 !strconcat(OpcodeStr,
3548 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3553 defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", ssmem, FR32X,
3554 SSEPackedSingle>, EVEX_CD8<32, CD8VT1>;
3556 defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", sdmem, FR64X,
3557 SSEPackedDouble>, EVEX_CD8<64, CD8VT1>;
3559 def : Pat<(ffloor FR32X:$src),
3560 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x1))>;
3561 def : Pat<(f64 (ffloor FR64X:$src)),
3562 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x1))>;
3563 def : Pat<(f32 (fnearbyint FR32X:$src)),
3564 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0xC))>;
3565 def : Pat<(f64 (fnearbyint FR64X:$src)),
3566 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0xC))>;
3567 def : Pat<(f32 (fceil FR32X:$src)),
3568 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x2))>;
3569 def : Pat<(f64 (fceil FR64X:$src)),
3570 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x2))>;
3571 def : Pat<(f32 (frint FR32X:$src)),
3572 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x4))>;
3573 def : Pat<(f64 (frint FR64X:$src)),
3574 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x4))>;
3575 def : Pat<(f32 (ftrunc FR32X:$src)),
3576 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x3))>;
3577 def : Pat<(f64 (ftrunc FR64X:$src)),
3578 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x3))>;
3580 def : Pat<(v16f32 (ffloor VR512:$src)),
3581 (VRNDSCALEPSZr VR512:$src, (i32 0x1))>;
3582 def : Pat<(v16f32 (fnearbyint VR512:$src)),
3583 (VRNDSCALEPSZr VR512:$src, (i32 0xC))>;
3584 def : Pat<(v16f32 (fceil VR512:$src)),
3585 (VRNDSCALEPSZr VR512:$src, (i32 0x2))>;
3586 def : Pat<(v16f32 (frint VR512:$src)),
3587 (VRNDSCALEPSZr VR512:$src, (i32 0x4))>;
3588 def : Pat<(v16f32 (ftrunc VR512:$src)),
3589 (VRNDSCALEPSZr VR512:$src, (i32 0x3))>;
3591 def : Pat<(v8f64 (ffloor VR512:$src)),
3592 (VRNDSCALEPDZr VR512:$src, (i32 0x1))>;
3593 def : Pat<(v8f64 (fnearbyint VR512:$src)),
3594 (VRNDSCALEPDZr VR512:$src, (i32 0xC))>;
3595 def : Pat<(v8f64 (fceil VR512:$src)),
3596 (VRNDSCALEPDZr VR512:$src, (i32 0x2))>;
3597 def : Pat<(v8f64 (frint VR512:$src)),
3598 (VRNDSCALEPDZr VR512:$src, (i32 0x4))>;
3599 def : Pat<(v8f64 (ftrunc VR512:$src)),
3600 (VRNDSCALEPDZr VR512:$src, (i32 0x3))>;
3602 //-------------------------------------------------
3603 // Integer truncate and extend operations
3604 //-------------------------------------------------
3606 multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr,
3607 RegisterClass dstRC, RegisterClass srcRC,
3608 RegisterClass KRC, X86MemOperand x86memop> {
3609 def rr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
3611 !strconcat(OpcodeStr," \t{$src, $dst|$dst, $src}"),
3614 def krr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
3615 (ins KRC:$mask, srcRC:$src),
3616 !strconcat(OpcodeStr,
3617 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
3620 def mr : AVX512XS8I<opc, MRMDestMem, (outs), (ins x86memop:$dst, srcRC:$src),
3621 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3624 defm VPMOVQB : avx512_trunc_sat<0x32, "vpmovqb", VR128X, VR512, VK8WM,
3625 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3626 defm VPMOVSQB : avx512_trunc_sat<0x22, "vpmovsqb", VR128X, VR512, VK8WM,
3627 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3628 defm VPMOVUSQB : avx512_trunc_sat<0x12, "vpmovusqb", VR128X, VR512, VK8WM,
3629 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3630 defm VPMOVQW : avx512_trunc_sat<0x34, "vpmovqw", VR128X, VR512, VK8WM,
3631 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3632 defm VPMOVSQW : avx512_trunc_sat<0x24, "vpmovsqw", VR128X, VR512, VK8WM,
3633 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3634 defm VPMOVUSQW : avx512_trunc_sat<0x14, "vpmovusqw", VR128X, VR512, VK8WM,
3635 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3636 defm VPMOVQD : avx512_trunc_sat<0x35, "vpmovqd", VR256X, VR512, VK8WM,
3637 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3638 defm VPMOVSQD : avx512_trunc_sat<0x25, "vpmovsqd", VR256X, VR512, VK8WM,
3639 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3640 defm VPMOVUSQD : avx512_trunc_sat<0x15, "vpmovusqd", VR256X, VR512, VK8WM,
3641 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3642 defm VPMOVDW : avx512_trunc_sat<0x33, "vpmovdw", VR256X, VR512, VK16WM,
3643 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3644 defm VPMOVSDW : avx512_trunc_sat<0x23, "vpmovsdw", VR256X, VR512, VK16WM,
3645 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3646 defm VPMOVUSDW : avx512_trunc_sat<0x13, "vpmovusdw", VR256X, VR512, VK16WM,
3647 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3648 defm VPMOVDB : avx512_trunc_sat<0x31, "vpmovdb", VR128X, VR512, VK16WM,
3649 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3650 defm VPMOVSDB : avx512_trunc_sat<0x21, "vpmovsdb", VR128X, VR512, VK16WM,
3651 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3652 defm VPMOVUSDB : avx512_trunc_sat<0x11, "vpmovusdb", VR128X, VR512, VK16WM,
3653 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3655 def : Pat<(v16i8 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQBrr VR512:$src)>;
3656 def : Pat<(v8i16 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQWrr VR512:$src)>;
3657 def : Pat<(v16i16 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDWrr VR512:$src)>;
3658 def : Pat<(v16i8 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDBrr VR512:$src)>;
3659 def : Pat<(v8i32 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQDrr VR512:$src)>;
3661 def : Pat<(v16i8 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
3662 (VPMOVDBkrr VK16WM:$mask, VR512:$src)>;
3663 def : Pat<(v16i16 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
3664 (VPMOVDWkrr VK16WM:$mask, VR512:$src)>;
3665 def : Pat<(v8i16 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
3666 (VPMOVQWkrr VK8WM:$mask, VR512:$src)>;
3667 def : Pat<(v8i32 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
3668 (VPMOVQDkrr VK8WM:$mask, VR512:$src)>;
3671 multiclass avx512_extend<bits<8> opc, string OpcodeStr, RegisterClass DstRC,
3672 RegisterClass SrcRC, SDNode OpNode, PatFrag mem_frag,
3673 X86MemOperand x86memop, ValueType OpVT, ValueType InVT> {
3675 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
3677 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3678 [(set DstRC:$dst, (OpVT (OpNode (InVT SrcRC:$src))))]>, EVEX;
3679 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
3680 (ins x86memop:$src),
3681 !strconcat(OpcodeStr," \t{$src, $dst|$dst, $src}"),
3683 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))]>,
3687 defm VPMOVZXBDZ: avx512_extend<0x31, "vpmovzxbd", VR512, VR128X, X86vzext,
3688 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
3690 defm VPMOVZXBQZ: avx512_extend<0x32, "vpmovzxbq", VR512, VR128X, X86vzext,
3691 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
3693 defm VPMOVZXWDZ: avx512_extend<0x33, "vpmovzxwd", VR512, VR256X, X86vzext,
3694 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
3695 EVEX_CD8<16, CD8VH>;
3696 defm VPMOVZXWQZ: avx512_extend<0x34, "vpmovzxwq", VR512, VR128X, X86vzext,
3697 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
3698 EVEX_CD8<16, CD8VQ>;
3699 defm VPMOVZXDQZ: avx512_extend<0x35, "vpmovzxdq", VR512, VR256X, X86vzext,
3700 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
3701 EVEX_CD8<32, CD8VH>;
3703 defm VPMOVSXBDZ: avx512_extend<0x21, "vpmovsxbd", VR512, VR128X, X86vsext,
3704 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
3706 defm VPMOVSXBQZ: avx512_extend<0x22, "vpmovsxbq", VR512, VR128X, X86vsext,
3707 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
3709 defm VPMOVSXWDZ: avx512_extend<0x23, "vpmovsxwd", VR512, VR256X, X86vsext,
3710 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
3711 EVEX_CD8<16, CD8VH>;
3712 defm VPMOVSXWQZ: avx512_extend<0x24, "vpmovsxwq", VR512, VR128X, X86vsext,
3713 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
3714 EVEX_CD8<16, CD8VQ>;
3715 defm VPMOVSXDQZ: avx512_extend<0x25, "vpmovsxdq", VR512, VR256X, X86vsext,
3716 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
3717 EVEX_CD8<32, CD8VH>;
3719 //===----------------------------------------------------------------------===//
3720 // GATHER - SCATTER Operations
3722 multiclass avx512_gather<bits<8> opc, string OpcodeStr, RegisterClass KRC,
3723 RegisterClass RC, X86MemOperand memop> {
3725 Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb" in
3726 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst, KRC:$mask_wb),
3727 (ins RC:$src1, KRC:$mask, memop:$src2),
3728 !strconcat(OpcodeStr,
3729 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3732 defm VGATHERDPDZ : avx512_gather<0x92, "vgatherdpd", VK8WM, VR512, vy64xmem>,
3733 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3734 defm VGATHERDPSZ : avx512_gather<0x92, "vgatherdps", VK16WM, VR512, vz32mem>,
3735 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3737 defm VGATHERQPDZ : avx512_gather<0x93, "vgatherqpd", VK8WM, VR512, vz64mem>,
3738 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3739 defm VGATHERQPSZ : avx512_gather<0x93, "vgatherqps", VK8WM, VR256X, vz64mem>,
3740 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3742 defm VPGATHERDQZ : avx512_gather<0x90, "vpgatherdq", VK8WM, VR512, vy64xmem>,
3743 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3744 defm VPGATHERDDZ : avx512_gather<0x90, "vpgatherdd", VK16WM, VR512, vz32mem>,
3745 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3747 defm VPGATHERQQZ : avx512_gather<0x91, "vpgatherqq", VK8WM, VR512, vz64mem>,
3748 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3749 defm VPGATHERQDZ : avx512_gather<0x91, "vpgatherqd", VK8WM, VR256X, vz64mem>,
3750 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3752 multiclass avx512_scatter<bits<8> opc, string OpcodeStr, RegisterClass KRC,
3753 RegisterClass RC, X86MemOperand memop> {
3754 let mayStore = 1, Constraints = "$mask = $mask_wb" in
3755 def mr : AVX5128I<opc, MRMDestMem, (outs KRC:$mask_wb),
3756 (ins memop:$dst, KRC:$mask, RC:$src2),
3757 !strconcat(OpcodeStr,
3758 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3762 defm VSCATTERDPDZ : avx512_scatter<0xA2, "vscatterdpd", VK8WM, VR512, vy64xmem>,
3763 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3764 defm VSCATTERDPSZ : avx512_scatter<0xA2, "vscatterdps", VK16WM, VR512, vz32mem>,
3765 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3767 defm VSCATTERQPDZ : avx512_scatter<0xA3, "vscatterqpd", VK8WM, VR512, vz64mem>,
3768 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3769 defm VSCATTERQPSZ : avx512_scatter<0xA3, "vscatterqps", VK8WM, VR256X, vz64mem>,
3770 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3772 defm VPSCATTERDQZ : avx512_scatter<0xA0, "vpscatterdq", VK8WM, VR512, vy64xmem>,
3773 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3774 defm VPSCATTERDDZ : avx512_scatter<0xA0, "vpscatterdd", VK16WM, VR512, vz32mem>,
3775 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3777 defm VPSCATTERQQZ : avx512_scatter<0xA1, "vpscatterqq", VK8WM, VR512, vz64mem>,
3778 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3779 defm VPSCATTERQDZ : avx512_scatter<0xA1, "vpscatterqd", VK8WM, VR256X, vz64mem>,
3780 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3782 //===----------------------------------------------------------------------===//
3783 // VSHUFPS - VSHUFPD Operations
3785 multiclass avx512_shufp<RegisterClass RC, X86MemOperand x86memop,
3786 ValueType vt, string OpcodeStr, PatFrag mem_frag,
3788 def rmi : AVX512PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
3789 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
3790 !strconcat(OpcodeStr,
3791 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3792 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
3793 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
3794 EVEX_4V, Sched<[WriteShuffleLd, ReadAfterLd]>;
3795 def rri : AVX512PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
3796 (ins RC:$src1, RC:$src2, i8imm:$src3),
3797 !strconcat(OpcodeStr,
3798 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3799 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
3800 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
3801 EVEX_4V, Sched<[WriteShuffle]>;
3804 defm VSHUFPSZ : avx512_shufp<VR512, f512mem, v16f32, "vshufps", memopv16f32,
3805 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
3806 defm VSHUFPDZ : avx512_shufp<VR512, f512mem, v8f64, "vshufpd", memopv8f64,
3807 SSEPackedDouble>, PD, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3809 def : Pat<(v16i32 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3810 (VSHUFPSZrri VR512:$src1, VR512:$src2, imm:$imm)>;
3811 def : Pat<(v16i32 (X86Shufp VR512:$src1,
3812 (memopv16i32 addr:$src2), (i8 imm:$imm))),
3813 (VSHUFPSZrmi VR512:$src1, addr:$src2, imm:$imm)>;
3815 def : Pat<(v8i64 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3816 (VSHUFPDZrri VR512:$src1, VR512:$src2, imm:$imm)>;
3817 def : Pat<(v8i64 (X86Shufp VR512:$src1,
3818 (memopv8i64 addr:$src2), (i8 imm:$imm))),
3819 (VSHUFPDZrmi VR512:$src1, addr:$src2, imm:$imm)>;
3821 multiclass avx512_alignr<string OpcodeStr, RegisterClass RC,
3822 X86MemOperand x86memop> {
3823 def rri : AVX512AIi8<0x03, MRMSrcReg, (outs RC:$dst),
3824 (ins RC:$src1, RC:$src2, i8imm:$src3),
3825 !strconcat(OpcodeStr,
3826 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3829 def rmi : AVX512AIi8<0x03, MRMSrcMem, (outs RC:$dst),
3830 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
3831 !strconcat(OpcodeStr,
3832 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3835 defm VALIGND : avx512_alignr<"valignd", VR512, i512mem>,
3836 EVEX_V512, EVEX_CD8<32, CD8VF>;
3837 defm VALIGNQ : avx512_alignr<"valignq", VR512, i512mem>,
3838 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3840 def : Pat<(v16f32 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3841 (VALIGNDrri VR512:$src2, VR512:$src1, imm:$imm)>;
3842 def : Pat<(v8f64 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3843 (VALIGNQrri VR512:$src2, VR512:$src1, imm:$imm)>;
3844 def : Pat<(v16i32 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3845 (VALIGNDrri VR512:$src2, VR512:$src1, imm:$imm)>;
3846 def : Pat<(v8i64 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3847 (VALIGNQrri VR512:$src2, VR512:$src1, imm:$imm)>;
3849 multiclass avx512_vpabs<bits<8> opc, string OpcodeStr, RegisterClass RC,
3850 X86MemOperand x86memop> {
3851 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3852 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>,
3854 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
3855 (ins x86memop:$src),
3856 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>,
3860 defm VPABSD : avx512_vpabs<0x1E, "vpabsd", VR512, i512mem>, EVEX_V512,
3861 EVEX_CD8<32, CD8VF>;
3862 defm VPABSQ : avx512_vpabs<0x1F, "vpabsq", VR512, i512mem>, EVEX_V512, VEX_W,
3863 EVEX_CD8<64, CD8VF>;
3865 def : Pat<(v16i32 (int_x86_avx512_mask_pabs_d_512 (v16i32 VR512:$src),
3866 (v16i32 immAllZerosV), (i16 -1))),
3867 (VPABSDrr VR512:$src)>;
3868 def : Pat<(v8i64 (int_x86_avx512_mask_pabs_q_512 (v8i64 VR512:$src),
3869 (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
3870 (VPABSQrr VR512:$src)>;
3872 multiclass avx512_conflict<bits<8> opc, string OpcodeStr,
3873 RegisterClass RC, RegisterClass KRC,
3874 X86MemOperand x86memop,
3875 X86MemOperand x86scalar_mop, string BrdcstStr> {
3876 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3878 !strconcat(OpcodeStr, " \t{$src, ${dst} |${dst}, $src}"),
3880 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3881 (ins x86memop:$src),
3882 !strconcat(OpcodeStr, " \t{$src, ${dst}|${dst}, $src}"),
3884 def rmb : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3885 (ins x86scalar_mop:$src),
3886 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
3887 ", ${dst}|${dst}, ${src}", BrdcstStr, "}"),
3889 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3890 (ins KRC:$mask, RC:$src),
3891 !strconcat(OpcodeStr,
3892 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
3894 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3895 (ins KRC:$mask, x86memop:$src),
3896 !strconcat(OpcodeStr,
3897 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
3899 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3900 (ins KRC:$mask, x86scalar_mop:$src),
3901 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
3902 ", ${dst} {${mask}} {z}|${dst} {${mask}} {z}, ${src}",
3904 []>, EVEX, EVEX_KZ, EVEX_B;
3906 let Constraints = "$src1 = $dst" in {
3907 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3908 (ins RC:$src1, KRC:$mask, RC:$src2),
3909 !strconcat(OpcodeStr,
3910 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3912 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3913 (ins RC:$src1, KRC:$mask, x86memop:$src2),
3914 !strconcat(OpcodeStr,
3915 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3917 def rmbk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3918 (ins RC:$src1, KRC:$mask, x86scalar_mop:$src2),
3919 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
3920 ", ${dst} {${mask}}|${dst} {${mask}}, ${src2}", BrdcstStr, "}"),
3921 []>, EVEX, EVEX_K, EVEX_B;
3925 let Predicates = [HasCDI] in {
3926 defm VPCONFLICTD : avx512_conflict<0xC4, "vpconflictd", VR512, VK16WM,
3927 i512mem, i32mem, "{1to16}">,
3928 EVEX_V512, EVEX_CD8<32, CD8VF>;
3931 defm VPCONFLICTQ : avx512_conflict<0xC4, "vpconflictq", VR512, VK8WM,
3932 i512mem, i64mem, "{1to8}">,
3933 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3937 def : Pat<(int_x86_avx512_mask_conflict_d_512 VR512:$src2, VR512:$src1,
3939 (VPCONFLICTDrrk VR512:$src1,
3940 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
3942 def : Pat<(int_x86_avx512_mask_conflict_q_512 VR512:$src2, VR512:$src1,
3944 (VPCONFLICTQrrk VR512:$src1,
3945 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;