1 //====- X86Instr64bit.td - Describe X86-64 Instructions ----*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86-64 instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // Operand Definitions.
20 // 64-bits but only 32 bits are significant.
21 def i64i32imm : Operand<i64>;
23 // 64-bits but only 32 bits are significant, and those bits are treated as being
25 def i64i32imm_pcrel : Operand<i64> {
26 let PrintMethod = "print_pcrel_imm";
30 // 64-bits but only 8 bits are significant.
31 def i64i8imm : Operand<i64> {
32 let ParserMatchClass = ImmSExt8AsmOperand;
35 def lea64mem : Operand<i64> {
36 let PrintMethod = "printlea64mem";
37 let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm);
38 let ParserMatchClass = X86MemAsmOperand;
41 def lea64_32mem : Operand<i32> {
42 let PrintMethod = "printlea64_32mem";
43 let AsmOperandLowerMethod = "lower_lea64_32mem";
44 let MIOperandInfo = (ops GR32, i8imm, GR32_NOSP, i32imm);
45 let ParserMatchClass = X86MemAsmOperand;
48 //===----------------------------------------------------------------------===//
49 // Complex Pattern Definitions.
51 def lea64addr : ComplexPattern<i64, 4, "SelectLEAAddr",
52 [add, sub, mul, X86mul_imm, shl, or, frameindex,
55 def tls64addr : ComplexPattern<i64, 4, "SelectTLSADDRAddr",
56 [tglobaltlsaddr], []>;
58 //===----------------------------------------------------------------------===//
62 def i64immSExt8 : PatLeaf<(i64 imm), [{
63 // i64immSExt8 predicate - True if the 64-bit immediate fits in a 8-bit
64 // sign extended field.
65 return (int64_t)N->getZExtValue() == (int8_t)N->getZExtValue();
68 def i64immSExt32 : PatLeaf<(i64 imm), [{
69 // i64immSExt32 predicate - True if the 64-bit immediate fits in a 32-bit
70 // sign extended field.
71 return (int64_t)N->getZExtValue() == (int32_t)N->getZExtValue();
74 def i64immZExt32 : PatLeaf<(i64 imm), [{
75 // i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit
76 // unsignedsign extended field.
77 return (uint64_t)N->getZExtValue() == (uint32_t)N->getZExtValue();
80 def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>;
81 def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>;
82 def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>;
84 def zextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (zextloadi1 node:$ptr))>;
85 def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>;
86 def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>;
87 def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>;
89 def extloadi64i1 : PatFrag<(ops node:$ptr), (i64 (extloadi1 node:$ptr))>;
90 def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>;
91 def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>;
92 def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>;
94 //===----------------------------------------------------------------------===//
95 // Instruction list...
98 // ADJCALLSTACKDOWN/UP implicitly use/def RSP because they may be expanded into
99 // a stack adjustment and the codegen must know that they may modify the stack
100 // pointer before prolog-epilog rewriting occurs.
101 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
102 // sub / add which can clobber EFLAGS.
103 let Defs = [RSP, EFLAGS], Uses = [RSP] in {
104 def ADJCALLSTACKDOWN64 : I<0, Pseudo, (outs), (ins i32imm:$amt),
106 [(X86callseq_start timm:$amt)]>,
107 Requires<[In64BitMode]>;
108 def ADJCALLSTACKUP64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
110 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
111 Requires<[In64BitMode]>;
114 //===----------------------------------------------------------------------===//
115 // Call Instructions...
118 // All calls clobber the non-callee saved registers. RSP is marked as
119 // a use to prevent stack-pointer assignments that appear immediately
120 // before calls from potentially appearing dead. Uses for argument
121 // registers are added manually.
122 let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
123 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
124 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
125 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
126 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
129 // NOTE: this pattern doesn't match "X86call imm", because we do not know
130 // that the offset between an arbitrary immediate and the call will fit in
131 // the 32-bit pcrel field that we have.
132 def CALL64pcrel32 : Ii32<0xE8, RawFrm,
133 (outs), (ins i64i32imm_pcrel:$dst, variable_ops),
135 Requires<[In64BitMode, NotWin64]>;
136 def CALL64r : I<0xFF, MRM2r, (outs), (ins GR64:$dst, variable_ops),
137 "call\t{*}$dst", [(X86call GR64:$dst)]>,
138 Requires<[NotWin64]>;
139 def CALL64m : I<0xFF, MRM2m, (outs), (ins i64mem:$dst, variable_ops),
140 "call\t{*}$dst", [(X86call (loadi64 addr:$dst))]>,
141 Requires<[NotWin64]>;
143 def FARCALL64 : RI<0xFF, MRM3m, (outs), (ins opaque80mem:$dst),
144 "lcall{q}\t{*}$dst", []>;
147 // FIXME: We need to teach codegen about single list of call-clobbered registers.
149 // All calls clobber the non-callee saved registers. RSP is marked as
150 // a use to prevent stack-pointer assignments that appear immediately
151 // before calls from potentially appearing dead. Uses for argument
152 // registers are added manually.
153 let Defs = [RAX, RCX, RDX, R8, R9, R10, R11,
154 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
155 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
156 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, EFLAGS],
158 def WINCALL64pcrel32 : I<0xE8, RawFrm,
159 (outs), (ins i64i32imm_pcrel:$dst, variable_ops),
162 def WINCALL64r : I<0xFF, MRM2r, (outs), (ins GR64:$dst, variable_ops),
164 [(X86call GR64:$dst)]>, Requires<[IsWin64]>;
165 def WINCALL64m : I<0xFF, MRM2m, (outs), (ins i64mem:$dst, variable_ops),
167 [(X86call (loadi64 addr:$dst))]>, Requires<[IsWin64]>;
171 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
172 def TCRETURNdi64 : I<0, Pseudo, (outs), (ins i64imm:$dst, i32imm:$offset,
174 "#TC_RETURN $dst $offset",
177 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
178 def TCRETURNri64 : I<0, Pseudo, (outs), (ins GR64:$dst, i32imm:$offset,
180 "#TC_RETURN $dst $offset",
184 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
185 def TAILJMPr64 : I<0xFF, MRM4r, (outs), (ins GR64:$dst),
186 "jmp{q}\t{*}$dst # TAILCALL",
190 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
191 def JMP64r : I<0xFF, MRM4r, (outs), (ins GR64:$dst), "jmp{q}\t{*}$dst",
192 [(brind GR64:$dst)]>;
193 def JMP64m : I<0xFF, MRM4m, (outs), (ins i64mem:$dst), "jmp{q}\t{*}$dst",
194 [(brind (loadi64 addr:$dst))]>;
195 def FARJMP64 : RI<0xFF, MRM5m, (outs), (ins opaque80mem:$dst),
196 "ljmp{q}\t{*}$dst", []>;
199 //===----------------------------------------------------------------------===//
200 // EH Pseudo Instructions
202 let isTerminator = 1, isReturn = 1, isBarrier = 1,
204 def EH_RETURN64 : I<0xC3, RawFrm, (outs), (ins GR64:$addr),
205 "ret\t#eh_return, addr: $addr",
206 [(X86ehret GR64:$addr)]>;
210 //===----------------------------------------------------------------------===//
211 // Miscellaneous Instructions...
213 let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, neverHasSideEffects = 1 in
214 def LEAVE64 : I<0xC9, RawFrm,
215 (outs), (ins), "leave", []>;
216 let Defs = [RSP], Uses = [RSP], neverHasSideEffects=1 in {
218 def POP64r : I<0x58, AddRegFrm,
219 (outs GR64:$reg), (ins), "pop{q}\t$reg", []>;
220 def POP64rmr: I<0x8F, MRM0r, (outs GR64:$reg), (ins), "pop{q}\t$reg", []>;
221 def POP64rmm: I<0x8F, MRM0m, (outs i64mem:$dst), (ins), "pop{q}\t$dst", []>;
223 let mayStore = 1 in {
224 def PUSH64r : I<0x50, AddRegFrm,
225 (outs), (ins GR64:$reg), "push{q}\t$reg", []>;
226 def PUSH64rmr: I<0xFF, MRM6r, (outs), (ins GR64:$reg), "push{q}\t$reg", []>;
227 def PUSH64rmm: I<0xFF, MRM6m, (outs), (ins i64mem:$src), "push{q}\t$src", []>;
231 let Defs = [RSP], Uses = [RSP], neverHasSideEffects = 1, mayStore = 1 in {
232 def PUSH64i8 : Ii8<0x6a, RawFrm, (outs), (ins i8imm:$imm),
233 "push{q}\t$imm", []>;
234 def PUSH64i16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
235 "push{q}\t$imm", []>;
236 def PUSH64i32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
237 "push{q}\t$imm", []>;
240 let Defs = [RSP, EFLAGS], Uses = [RSP], mayLoad = 1 in
241 def POPFQ : I<0x9D, RawFrm, (outs), (ins), "popf", []>, REX_W;
242 let Defs = [RSP], Uses = [RSP, EFLAGS], mayStore = 1 in
243 def PUSHFQ : I<0x9C, RawFrm, (outs), (ins), "pushf", []>;
245 def LEA64_32r : I<0x8D, MRMSrcMem,
246 (outs GR32:$dst), (ins lea64_32mem:$src),
247 "lea{l}\t{$src|$dst}, {$dst|$src}",
248 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In64BitMode]>;
250 let isReMaterializable = 1 in
251 def LEA64r : RI<0x8D, MRMSrcMem, (outs GR64:$dst), (ins lea64mem:$src),
252 "lea{q}\t{$src|$dst}, {$dst|$src}",
253 [(set GR64:$dst, lea64addr:$src)]>;
255 let isTwoAddress = 1 in
256 def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src),
258 [(set GR64:$dst, (bswap GR64:$src))]>, TB;
260 // Bit scan instructions.
261 let Defs = [EFLAGS] in {
262 def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
263 "bsf{q}\t{$src, $dst|$dst, $src}",
264 [(set GR64:$dst, (X86bsf GR64:$src)), (implicit EFLAGS)]>, TB;
265 def BSF64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
266 "bsf{q}\t{$src, $dst|$dst, $src}",
267 [(set GR64:$dst, (X86bsf (loadi64 addr:$src))),
268 (implicit EFLAGS)]>, TB;
270 def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
271 "bsr{q}\t{$src, $dst|$dst, $src}",
272 [(set GR64:$dst, (X86bsr GR64:$src)), (implicit EFLAGS)]>, TB;
273 def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
274 "bsr{q}\t{$src, $dst|$dst, $src}",
275 [(set GR64:$dst, (X86bsr (loadi64 addr:$src))),
276 (implicit EFLAGS)]>, TB;
280 let Defs = [RCX,RDI,RSI], Uses = [RCX,RDI,RSI] in
281 def REP_MOVSQ : RI<0xA5, RawFrm, (outs), (ins), "{rep;movsq|rep movsq}",
282 [(X86rep_movs i64)]>, REP;
283 let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI] in
284 def REP_STOSQ : RI<0xAB, RawFrm, (outs), (ins), "{rep;stosq|rep stosq}",
285 [(X86rep_stos i64)]>, REP;
287 // Fast system-call instructions
288 def SYSEXIT64 : RI<0x35, RawFrm,
289 (outs), (ins), "sysexit", []>, TB;
291 //===----------------------------------------------------------------------===//
292 // Move Instructions...
295 let neverHasSideEffects = 1 in
296 def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
297 "mov{q}\t{$src, $dst|$dst, $src}", []>;
299 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
300 def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src),
301 "movabs{q}\t{$src, $dst|$dst, $src}",
302 [(set GR64:$dst, imm:$src)]>;
303 def MOV64ri32 : RIi32<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src),
304 "mov{q}\t{$src, $dst|$dst, $src}",
305 [(set GR64:$dst, i64immSExt32:$src)]>;
308 let canFoldAsLoad = 1 in
309 def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
310 "mov{q}\t{$src, $dst|$dst, $src}",
311 [(set GR64:$dst, (load addr:$src))]>;
313 def MOV64mr : RI<0x89, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
314 "mov{q}\t{$src, $dst|$dst, $src}",
315 [(store GR64:$src, addr:$dst)]>;
316 def MOV64mi32 : RIi32<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src),
317 "mov{q}\t{$src, $dst|$dst, $src}",
318 [(store i64immSExt32:$src, addr:$dst)]>;
320 def MOV64o8a : RIi8<0xA0, RawFrm, (outs), (ins i8imm:$src),
321 "mov{q}\t{$src, %rax|%rax, $src}", []>;
322 def MOV64o32a : RIi32<0xA1, RawFrm, (outs), (ins i32imm:$src),
323 "mov{q}\t{$src, %rax|%rax, $src}", []>;
324 def MOV64ao8 : RIi8<0xA2, RawFrm, (outs i8imm:$dst), (ins),
325 "mov{q}\t{%rax, $dst|$dst, %rax}", []>;
326 def MOV64ao32 : RIi32<0xA3, RawFrm, (outs i32imm:$dst), (ins),
327 "mov{q}\t{%rax, $dst|$dst, %rax}", []>;
329 // Sign/Zero extenders
331 // MOVSX64rr8 always has a REX prefix and it has an 8-bit register
332 // operand, which makes it a rare instruction with an 8-bit register
333 // operand that can never access an h register. If support for h registers
334 // were generalized, this would require a special register class.
335 def MOVSX64rr8 : RI<0xBE, MRMSrcReg, (outs GR64:$dst), (ins GR8 :$src),
336 "movs{bq|x}\t{$src, $dst|$dst, $src}",
337 [(set GR64:$dst, (sext GR8:$src))]>, TB;
338 def MOVSX64rm8 : RI<0xBE, MRMSrcMem, (outs GR64:$dst), (ins i8mem :$src),
339 "movs{bq|x}\t{$src, $dst|$dst, $src}",
340 [(set GR64:$dst, (sextloadi64i8 addr:$src))]>, TB;
341 def MOVSX64rr16: RI<0xBF, MRMSrcReg, (outs GR64:$dst), (ins GR16:$src),
342 "movs{wq|x}\t{$src, $dst|$dst, $src}",
343 [(set GR64:$dst, (sext GR16:$src))]>, TB;
344 def MOVSX64rm16: RI<0xBF, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
345 "movs{wq|x}\t{$src, $dst|$dst, $src}",
346 [(set GR64:$dst, (sextloadi64i16 addr:$src))]>, TB;
347 def MOVSX64rr32: RI<0x63, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src),
348 "movs{lq|xd}\t{$src, $dst|$dst, $src}",
349 [(set GR64:$dst, (sext GR32:$src))]>;
350 def MOVSX64rm32: RI<0x63, MRMSrcMem, (outs GR64:$dst), (ins i32mem:$src),
351 "movs{lq|xd}\t{$src, $dst|$dst, $src}",
352 [(set GR64:$dst, (sextloadi64i32 addr:$src))]>;
354 // Use movzbl instead of movzbq when the destination is a register; it's
355 // equivalent due to implicit zero-extending, and it has a smaller encoding.
356 def MOVZX64rr8 : I<0xB6, MRMSrcReg, (outs GR64:$dst), (ins GR8 :$src),
357 "movz{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
358 [(set GR64:$dst, (zext GR8:$src))]>, TB;
359 def MOVZX64rm8 : I<0xB6, MRMSrcMem, (outs GR64:$dst), (ins i8mem :$src),
360 "movz{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
361 [(set GR64:$dst, (zextloadi64i8 addr:$src))]>, TB;
362 // Use movzwl instead of movzwq when the destination is a register; it's
363 // equivalent due to implicit zero-extending, and it has a smaller encoding.
364 def MOVZX64rr16: I<0xB7, MRMSrcReg, (outs GR64:$dst), (ins GR16:$src),
365 "movz{wl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
366 [(set GR64:$dst, (zext GR16:$src))]>, TB;
367 def MOVZX64rm16: I<0xB7, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
368 "movz{wl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
369 [(set GR64:$dst, (zextloadi64i16 addr:$src))]>, TB;
371 // There's no movzlq instruction, but movl can be used for this purpose, using
372 // implicit zero-extension. The preferred way to do 32-bit-to-64-bit zero
373 // extension on x86-64 is to use a SUBREG_TO_REG to utilize implicit
374 // zero-extension, however this isn't possible when the 32-bit value is
375 // defined by a truncate or is copied from something where the high bits aren't
376 // necessarily all zero. In such cases, we fall back to these explicit zext
378 def MOVZX64rr32 : I<0x89, MRMDestReg, (outs GR64:$dst), (ins GR32:$src),
379 "mov{l}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
380 [(set GR64:$dst, (zext GR32:$src))]>;
381 def MOVZX64rm32 : I<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i32mem:$src),
382 "mov{l}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
383 [(set GR64:$dst, (zextloadi64i32 addr:$src))]>;
385 // Any instruction that defines a 32-bit result leaves the high half of the
386 // register. Truncate can be lowered to EXTRACT_SUBREG, and CopyFromReg may
387 // be copying from a truncate, but any other 32-bit operation will zero-extend
389 def def32 : PatLeaf<(i32 GR32:$src), [{
390 return N->getOpcode() != ISD::TRUNCATE &&
391 N->getOpcode() != TargetInstrInfo::EXTRACT_SUBREG &&
392 N->getOpcode() != ISD::CopyFromReg;
395 // In the case of a 32-bit def that is known to implicitly zero-extend,
396 // we can use a SUBREG_TO_REG.
397 def : Pat<(i64 (zext def32:$src)),
398 (SUBREG_TO_REG (i64 0), GR32:$src, x86_subreg_32bit)>;
400 let neverHasSideEffects = 1 in {
401 let Defs = [RAX], Uses = [EAX] in
402 def CDQE : RI<0x98, RawFrm, (outs), (ins),
403 "{cltq|cdqe}", []>; // RAX = signext(EAX)
405 let Defs = [RAX,RDX], Uses = [RAX] in
406 def CQO : RI<0x99, RawFrm, (outs), (ins),
407 "{cqto|cqo}", []>; // RDX:RAX = signext(RAX)
410 //===----------------------------------------------------------------------===//
411 // Arithmetic Instructions...
414 let Defs = [EFLAGS] in {
416 def ADD64i32 : RI<0x05, RawFrm, (outs), (ins i32imm:$src),
417 "add{q}\t{$src, %rax|%rax, $src}", []>;
419 let isTwoAddress = 1 in {
420 let isConvertibleToThreeAddress = 1 in {
421 let isCommutable = 1 in
422 // Register-Register Addition
423 def ADD64rr : RI<0x01, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
424 "add{q}\t{$src2, $dst|$dst, $src2}",
425 [(set GR64:$dst, (add GR64:$src1, GR64:$src2)),
428 // Register-Integer Addition
429 def ADD64ri8 : RIi8<0x83, MRM0r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
430 "add{q}\t{$src2, $dst|$dst, $src2}",
431 [(set GR64:$dst, (add GR64:$src1, i64immSExt8:$src2)),
433 def ADD64ri32 : RIi32<0x81, MRM0r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
434 "add{q}\t{$src2, $dst|$dst, $src2}",
435 [(set GR64:$dst, (add GR64:$src1, i64immSExt32:$src2)),
437 } // isConvertibleToThreeAddress
439 // Register-Memory Addition
440 def ADD64rm : RI<0x03, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
441 "add{q}\t{$src2, $dst|$dst, $src2}",
442 [(set GR64:$dst, (add GR64:$src1, (load addr:$src2))),
446 // Memory-Register Addition
447 def ADD64mr : RI<0x01, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
448 "add{q}\t{$src2, $dst|$dst, $src2}",
449 [(store (add (load addr:$dst), GR64:$src2), addr:$dst),
451 def ADD64mi8 : RIi8<0x83, MRM0m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
452 "add{q}\t{$src2, $dst|$dst, $src2}",
453 [(store (add (load addr:$dst), i64immSExt8:$src2), addr:$dst),
455 def ADD64mi32 : RIi32<0x81, MRM0m, (outs), (ins i64mem:$dst, i64i32imm :$src2),
456 "add{q}\t{$src2, $dst|$dst, $src2}",
457 [(store (add (load addr:$dst), i64immSExt32:$src2), addr:$dst),
460 let Uses = [EFLAGS] in {
461 let isTwoAddress = 1 in {
462 let isCommutable = 1 in
463 def ADC64rr : RI<0x11, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
464 "adc{q}\t{$src2, $dst|$dst, $src2}",
465 [(set GR64:$dst, (adde GR64:$src1, GR64:$src2))]>;
467 def ADC64rm : RI<0x13, MRMSrcMem , (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
468 "adc{q}\t{$src2, $dst|$dst, $src2}",
469 [(set GR64:$dst, (adde GR64:$src1, (load addr:$src2)))]>;
471 def ADC64ri8 : RIi8<0x83, MRM2r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
472 "adc{q}\t{$src2, $dst|$dst, $src2}",
473 [(set GR64:$dst, (adde GR64:$src1, i64immSExt8:$src2))]>;
474 def ADC64ri32 : RIi32<0x81, MRM2r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
475 "adc{q}\t{$src2, $dst|$dst, $src2}",
476 [(set GR64:$dst, (adde GR64:$src1, i64immSExt32:$src2))]>;
479 def ADC64mr : RI<0x11, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
480 "adc{q}\t{$src2, $dst|$dst, $src2}",
481 [(store (adde (load addr:$dst), GR64:$src2), addr:$dst)]>;
482 def ADC64mi8 : RIi8<0x83, MRM2m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
483 "adc{q}\t{$src2, $dst|$dst, $src2}",
484 [(store (adde (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>;
485 def ADC64mi32 : RIi32<0x81, MRM2m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
486 "adc{q}\t{$src2, $dst|$dst, $src2}",
487 [(store (adde (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>;
490 let isTwoAddress = 1 in {
491 // Register-Register Subtraction
492 def SUB64rr : RI<0x29, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
493 "sub{q}\t{$src2, $dst|$dst, $src2}",
494 [(set GR64:$dst, (sub GR64:$src1, GR64:$src2)),
497 // Register-Memory Subtraction
498 def SUB64rm : RI<0x2B, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
499 "sub{q}\t{$src2, $dst|$dst, $src2}",
500 [(set GR64:$dst, (sub GR64:$src1, (load addr:$src2))),
503 // Register-Integer Subtraction
504 def SUB64ri8 : RIi8<0x83, MRM5r, (outs GR64:$dst),
505 (ins GR64:$src1, i64i8imm:$src2),
506 "sub{q}\t{$src2, $dst|$dst, $src2}",
507 [(set GR64:$dst, (sub GR64:$src1, i64immSExt8:$src2)),
509 def SUB64ri32 : RIi32<0x81, MRM5r, (outs GR64:$dst),
510 (ins GR64:$src1, i64i32imm:$src2),
511 "sub{q}\t{$src2, $dst|$dst, $src2}",
512 [(set GR64:$dst, (sub GR64:$src1, i64immSExt32:$src2)),
516 // Memory-Register Subtraction
517 def SUB64mr : RI<0x29, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
518 "sub{q}\t{$src2, $dst|$dst, $src2}",
519 [(store (sub (load addr:$dst), GR64:$src2), addr:$dst),
522 // Memory-Integer Subtraction
523 def SUB64mi8 : RIi8<0x83, MRM5m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
524 "sub{q}\t{$src2, $dst|$dst, $src2}",
525 [(store (sub (load addr:$dst), i64immSExt8:$src2),
528 def SUB64mi32 : RIi32<0x81, MRM5m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
529 "sub{q}\t{$src2, $dst|$dst, $src2}",
530 [(store (sub (load addr:$dst), i64immSExt32:$src2),
534 let Uses = [EFLAGS] in {
535 let isTwoAddress = 1 in {
536 def SBB64rr : RI<0x19, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
537 "sbb{q}\t{$src2, $dst|$dst, $src2}",
538 [(set GR64:$dst, (sube GR64:$src1, GR64:$src2))]>;
540 def SBB64rm : RI<0x1B, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
541 "sbb{q}\t{$src2, $dst|$dst, $src2}",
542 [(set GR64:$dst, (sube GR64:$src1, (load addr:$src2)))]>;
544 def SBB64ri8 : RIi8<0x83, MRM3r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
545 "sbb{q}\t{$src2, $dst|$dst, $src2}",
546 [(set GR64:$dst, (sube GR64:$src1, i64immSExt8:$src2))]>;
547 def SBB64ri32 : RIi32<0x81, MRM3r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
548 "sbb{q}\t{$src2, $dst|$dst, $src2}",
549 [(set GR64:$dst, (sube GR64:$src1, i64immSExt32:$src2))]>;
552 def SBB64mr : RI<0x19, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
553 "sbb{q}\t{$src2, $dst|$dst, $src2}",
554 [(store (sube (load addr:$dst), GR64:$src2), addr:$dst)]>;
555 def SBB64mi8 : RIi8<0x83, MRM3m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
556 "sbb{q}\t{$src2, $dst|$dst, $src2}",
557 [(store (sube (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>;
558 def SBB64mi32 : RIi32<0x81, MRM3m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
559 "sbb{q}\t{$src2, $dst|$dst, $src2}",
560 [(store (sube (load addr:$dst), i64immSExt32:$src2), addr:$dst)]>;
564 // Unsigned multiplication
565 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], neverHasSideEffects = 1 in {
566 def MUL64r : RI<0xF7, MRM4r, (outs), (ins GR64:$src),
567 "mul{q}\t$src", []>; // RAX,RDX = RAX*GR64
569 def MUL64m : RI<0xF7, MRM4m, (outs), (ins i64mem:$src),
570 "mul{q}\t$src", []>; // RAX,RDX = RAX*[mem64]
572 // Signed multiplication
573 def IMUL64r : RI<0xF7, MRM5r, (outs), (ins GR64:$src),
574 "imul{q}\t$src", []>; // RAX,RDX = RAX*GR64
576 def IMUL64m : RI<0xF7, MRM5m, (outs), (ins i64mem:$src),
577 "imul{q}\t$src", []>; // RAX,RDX = RAX*[mem64]
580 let Defs = [EFLAGS] in {
581 let isTwoAddress = 1 in {
582 let isCommutable = 1 in
583 // Register-Register Signed Integer Multiplication
584 def IMUL64rr : RI<0xAF, MRMSrcReg, (outs GR64:$dst),
585 (ins GR64:$src1, GR64:$src2),
586 "imul{q}\t{$src2, $dst|$dst, $src2}",
587 [(set GR64:$dst, (mul GR64:$src1, GR64:$src2)),
588 (implicit EFLAGS)]>, TB;
590 // Register-Memory Signed Integer Multiplication
591 def IMUL64rm : RI<0xAF, MRMSrcMem, (outs GR64:$dst),
592 (ins GR64:$src1, i64mem:$src2),
593 "imul{q}\t{$src2, $dst|$dst, $src2}",
594 [(set GR64:$dst, (mul GR64:$src1, (load addr:$src2))),
595 (implicit EFLAGS)]>, TB;
598 // Suprisingly enough, these are not two address instructions!
600 // Register-Integer Signed Integer Multiplication
601 def IMUL64rri8 : RIi8<0x6B, MRMSrcReg, // GR64 = GR64*I8
602 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
603 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
604 [(set GR64:$dst, (mul GR64:$src1, i64immSExt8:$src2)),
606 def IMUL64rri32 : RIi32<0x69, MRMSrcReg, // GR64 = GR64*I32
607 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
608 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
609 [(set GR64:$dst, (mul GR64:$src1, i64immSExt32:$src2)),
612 // Memory-Integer Signed Integer Multiplication
613 def IMUL64rmi8 : RIi8<0x6B, MRMSrcMem, // GR64 = [mem64]*I8
614 (outs GR64:$dst), (ins i64mem:$src1, i64i8imm: $src2),
615 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
616 [(set GR64:$dst, (mul (load addr:$src1),
619 def IMUL64rmi32 : RIi32<0x69, MRMSrcMem, // GR64 = [mem64]*I32
620 (outs GR64:$dst), (ins i64mem:$src1, i64i32imm:$src2),
621 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
622 [(set GR64:$dst, (mul (load addr:$src1),
623 i64immSExt32:$src2)),
627 // Unsigned division / remainder
628 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in {
629 def DIV64r : RI<0xF7, MRM6r, (outs), (ins GR64:$src), // RDX:RAX/r64 = RAX,RDX
631 // Signed division / remainder
632 def IDIV64r: RI<0xF7, MRM7r, (outs), (ins GR64:$src), // RDX:RAX/r64 = RAX,RDX
633 "idiv{q}\t$src", []>;
635 def DIV64m : RI<0xF7, MRM6m, (outs), (ins i64mem:$src), // RDX:RAX/[mem64] = RAX,RDX
637 def IDIV64m: RI<0xF7, MRM7m, (outs), (ins i64mem:$src), // RDX:RAX/[mem64] = RAX,RDX
638 "idiv{q}\t$src", []>;
642 // Unary instructions
643 let Defs = [EFLAGS], CodeSize = 2 in {
644 let isTwoAddress = 1 in
645 def NEG64r : RI<0xF7, MRM3r, (outs GR64:$dst), (ins GR64:$src), "neg{q}\t$dst",
646 [(set GR64:$dst, (ineg GR64:$src)),
648 def NEG64m : RI<0xF7, MRM3m, (outs), (ins i64mem:$dst), "neg{q}\t$dst",
649 [(store (ineg (loadi64 addr:$dst)), addr:$dst),
652 let isTwoAddress = 1, isConvertibleToThreeAddress = 1 in
653 def INC64r : RI<0xFF, MRM0r, (outs GR64:$dst), (ins GR64:$src), "inc{q}\t$dst",
654 [(set GR64:$dst, (add GR64:$src, 1)),
656 def INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst), "inc{q}\t$dst",
657 [(store (add (loadi64 addr:$dst), 1), addr:$dst),
660 let isTwoAddress = 1, isConvertibleToThreeAddress = 1 in
661 def DEC64r : RI<0xFF, MRM1r, (outs GR64:$dst), (ins GR64:$src), "dec{q}\t$dst",
662 [(set GR64:$dst, (add GR64:$src, -1)),
664 def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst",
665 [(store (add (loadi64 addr:$dst), -1), addr:$dst),
668 // In 64-bit mode, single byte INC and DEC cannot be encoded.
669 let isTwoAddress = 1, isConvertibleToThreeAddress = 1 in {
670 // Can transform into LEA.
671 def INC64_16r : I<0xFF, MRM0r, (outs GR16:$dst), (ins GR16:$src), "inc{w}\t$dst",
672 [(set GR16:$dst, (add GR16:$src, 1)),
674 OpSize, Requires<[In64BitMode]>;
675 def INC64_32r : I<0xFF, MRM0r, (outs GR32:$dst), (ins GR32:$src), "inc{l}\t$dst",
676 [(set GR32:$dst, (add GR32:$src, 1)),
678 Requires<[In64BitMode]>;
679 def DEC64_16r : I<0xFF, MRM1r, (outs GR16:$dst), (ins GR16:$src), "dec{w}\t$dst",
680 [(set GR16:$dst, (add GR16:$src, -1)),
682 OpSize, Requires<[In64BitMode]>;
683 def DEC64_32r : I<0xFF, MRM1r, (outs GR32:$dst), (ins GR32:$src), "dec{l}\t$dst",
684 [(set GR32:$dst, (add GR32:$src, -1)),
686 Requires<[In64BitMode]>;
687 } // isConvertibleToThreeAddress
689 // These are duplicates of their 32-bit counterparts. Only needed so X86 knows
690 // how to unfold them.
691 let isTwoAddress = 0, CodeSize = 2 in {
692 def INC64_16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
693 [(store (add (loadi16 addr:$dst), 1), addr:$dst),
695 OpSize, Requires<[In64BitMode]>;
696 def INC64_32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
697 [(store (add (loadi32 addr:$dst), 1), addr:$dst),
699 Requires<[In64BitMode]>;
700 def DEC64_16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
701 [(store (add (loadi16 addr:$dst), -1), addr:$dst),
703 OpSize, Requires<[In64BitMode]>;
704 def DEC64_32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
705 [(store (add (loadi32 addr:$dst), -1), addr:$dst),
707 Requires<[In64BitMode]>;
709 } // Defs = [EFLAGS], CodeSize
712 let Defs = [EFLAGS] in {
713 // Shift instructions
714 let isTwoAddress = 1 in {
716 def SHL64rCL : RI<0xD3, MRM4r, (outs GR64:$dst), (ins GR64:$src),
717 "shl{q}\t{%cl, $dst|$dst, %CL}",
718 [(set GR64:$dst, (shl GR64:$src, CL))]>;
719 let isConvertibleToThreeAddress = 1 in // Can transform into LEA.
720 def SHL64ri : RIi8<0xC1, MRM4r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
721 "shl{q}\t{$src2, $dst|$dst, $src2}",
722 [(set GR64:$dst, (shl GR64:$src1, (i8 imm:$src2)))]>;
723 // NOTE: We don't use shifts of a register by one, because 'add reg,reg' is
728 def SHL64mCL : RI<0xD3, MRM4m, (outs), (ins i64mem:$dst),
729 "shl{q}\t{%cl, $dst|$dst, %CL}",
730 [(store (shl (loadi64 addr:$dst), CL), addr:$dst)]>;
731 def SHL64mi : RIi8<0xC1, MRM4m, (outs), (ins i64mem:$dst, i8imm:$src),
732 "shl{q}\t{$src, $dst|$dst, $src}",
733 [(store (shl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
734 def SHL64m1 : RI<0xD1, MRM4m, (outs), (ins i64mem:$dst),
736 [(store (shl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
738 let isTwoAddress = 1 in {
740 def SHR64rCL : RI<0xD3, MRM5r, (outs GR64:$dst), (ins GR64:$src),
741 "shr{q}\t{%cl, $dst|$dst, %CL}",
742 [(set GR64:$dst, (srl GR64:$src, CL))]>;
743 def SHR64ri : RIi8<0xC1, MRM5r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
744 "shr{q}\t{$src2, $dst|$dst, $src2}",
745 [(set GR64:$dst, (srl GR64:$src1, (i8 imm:$src2)))]>;
746 def SHR64r1 : RI<0xD1, MRM5r, (outs GR64:$dst), (ins GR64:$src1),
748 [(set GR64:$dst, (srl GR64:$src1, (i8 1)))]>;
752 def SHR64mCL : RI<0xD3, MRM5m, (outs), (ins i64mem:$dst),
753 "shr{q}\t{%cl, $dst|$dst, %CL}",
754 [(store (srl (loadi64 addr:$dst), CL), addr:$dst)]>;
755 def SHR64mi : RIi8<0xC1, MRM5m, (outs), (ins i64mem:$dst, i8imm:$src),
756 "shr{q}\t{$src, $dst|$dst, $src}",
757 [(store (srl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
758 def SHR64m1 : RI<0xD1, MRM5m, (outs), (ins i64mem:$dst),
760 [(store (srl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
762 let isTwoAddress = 1 in {
764 def SAR64rCL : RI<0xD3, MRM7r, (outs GR64:$dst), (ins GR64:$src),
765 "sar{q}\t{%cl, $dst|$dst, %CL}",
766 [(set GR64:$dst, (sra GR64:$src, CL))]>;
767 def SAR64ri : RIi8<0xC1, MRM7r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
768 "sar{q}\t{$src2, $dst|$dst, $src2}",
769 [(set GR64:$dst, (sra GR64:$src1, (i8 imm:$src2)))]>;
770 def SAR64r1 : RI<0xD1, MRM7r, (outs GR64:$dst), (ins GR64:$src1),
772 [(set GR64:$dst, (sra GR64:$src1, (i8 1)))]>;
776 def SAR64mCL : RI<0xD3, MRM7m, (outs), (ins i64mem:$dst),
777 "sar{q}\t{%cl, $dst|$dst, %CL}",
778 [(store (sra (loadi64 addr:$dst), CL), addr:$dst)]>;
779 def SAR64mi : RIi8<0xC1, MRM7m, (outs), (ins i64mem:$dst, i8imm:$src),
780 "sar{q}\t{$src, $dst|$dst, $src}",
781 [(store (sra (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
782 def SAR64m1 : RI<0xD1, MRM7m, (outs), (ins i64mem:$dst),
784 [(store (sra (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
786 // Rotate instructions
787 let isTwoAddress = 1 in {
789 def ROL64rCL : RI<0xD3, MRM0r, (outs GR64:$dst), (ins GR64:$src),
790 "rol{q}\t{%cl, $dst|$dst, %CL}",
791 [(set GR64:$dst, (rotl GR64:$src, CL))]>;
792 def ROL64ri : RIi8<0xC1, MRM0r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
793 "rol{q}\t{$src2, $dst|$dst, $src2}",
794 [(set GR64:$dst, (rotl GR64:$src1, (i8 imm:$src2)))]>;
795 def ROL64r1 : RI<0xD1, MRM0r, (outs GR64:$dst), (ins GR64:$src1),
797 [(set GR64:$dst, (rotl GR64:$src1, (i8 1)))]>;
801 def ROL64mCL : I<0xD3, MRM0m, (outs), (ins i64mem:$dst),
802 "rol{q}\t{%cl, $dst|$dst, %CL}",
803 [(store (rotl (loadi64 addr:$dst), CL), addr:$dst)]>;
804 def ROL64mi : RIi8<0xC1, MRM0m, (outs), (ins i64mem:$dst, i8imm:$src),
805 "rol{q}\t{$src, $dst|$dst, $src}",
806 [(store (rotl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
807 def ROL64m1 : RI<0xD1, MRM0m, (outs), (ins i64mem:$dst),
809 [(store (rotl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
811 let isTwoAddress = 1 in {
813 def ROR64rCL : RI<0xD3, MRM1r, (outs GR64:$dst), (ins GR64:$src),
814 "ror{q}\t{%cl, $dst|$dst, %CL}",
815 [(set GR64:$dst, (rotr GR64:$src, CL))]>;
816 def ROR64ri : RIi8<0xC1, MRM1r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
817 "ror{q}\t{$src2, $dst|$dst, $src2}",
818 [(set GR64:$dst, (rotr GR64:$src1, (i8 imm:$src2)))]>;
819 def ROR64r1 : RI<0xD1, MRM1r, (outs GR64:$dst), (ins GR64:$src1),
821 [(set GR64:$dst, (rotr GR64:$src1, (i8 1)))]>;
825 def ROR64mCL : RI<0xD3, MRM1m, (outs), (ins i64mem:$dst),
826 "ror{q}\t{%cl, $dst|$dst, %CL}",
827 [(store (rotr (loadi64 addr:$dst), CL), addr:$dst)]>;
828 def ROR64mi : RIi8<0xC1, MRM1m, (outs), (ins i64mem:$dst, i8imm:$src),
829 "ror{q}\t{$src, $dst|$dst, $src}",
830 [(store (rotr (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
831 def ROR64m1 : RI<0xD1, MRM1m, (outs), (ins i64mem:$dst),
833 [(store (rotr (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
835 // Double shift instructions (generalizations of rotate)
836 let isTwoAddress = 1 in {
838 def SHLD64rrCL : RI<0xA5, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
839 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
840 [(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2, CL))]>, TB;
841 def SHRD64rrCL : RI<0xAD, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
842 "shrd{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
843 [(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2, CL))]>, TB;
846 let isCommutable = 1 in { // FIXME: Update X86InstrInfo::commuteInstruction
847 def SHLD64rri8 : RIi8<0xA4, MRMDestReg,
848 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2, i8imm:$src3),
849 "shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
850 [(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2,
853 def SHRD64rri8 : RIi8<0xAC, MRMDestReg,
854 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2, i8imm:$src3),
855 "shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
856 [(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2,
863 def SHLD64mrCL : RI<0xA5, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
864 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
865 [(store (X86shld (loadi64 addr:$dst), GR64:$src2, CL),
867 def SHRD64mrCL : RI<0xAD, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
868 "shrd{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
869 [(store (X86shrd (loadi64 addr:$dst), GR64:$src2, CL),
872 def SHLD64mri8 : RIi8<0xA4, MRMDestMem,
873 (outs), (ins i64mem:$dst, GR64:$src2, i8imm:$src3),
874 "shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
875 [(store (X86shld (loadi64 addr:$dst), GR64:$src2,
876 (i8 imm:$src3)), addr:$dst)]>,
878 def SHRD64mri8 : RIi8<0xAC, MRMDestMem,
879 (outs), (ins i64mem:$dst, GR64:$src2, i8imm:$src3),
880 "shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
881 [(store (X86shrd (loadi64 addr:$dst), GR64:$src2,
882 (i8 imm:$src3)), addr:$dst)]>,
886 //===----------------------------------------------------------------------===//
887 // Logical Instructions...
890 let isTwoAddress = 1 , AddedComplexity = 15 in
891 def NOT64r : RI<0xF7, MRM2r, (outs GR64:$dst), (ins GR64:$src), "not{q}\t$dst",
892 [(set GR64:$dst, (not GR64:$src))]>;
893 def NOT64m : RI<0xF7, MRM2m, (outs), (ins i64mem:$dst), "not{q}\t$dst",
894 [(store (not (loadi64 addr:$dst)), addr:$dst)]>;
896 let Defs = [EFLAGS] in {
897 def AND64i32 : RI<0x25, RawFrm, (outs), (ins i32imm:$src),
898 "and{q}\t{$src, %rax|%rax, $src}", []>;
900 let isTwoAddress = 1 in {
901 let isCommutable = 1 in
902 def AND64rr : RI<0x21, MRMDestReg,
903 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
904 "and{q}\t{$src2, $dst|$dst, $src2}",
905 [(set GR64:$dst, (and GR64:$src1, GR64:$src2)),
907 def AND64rm : RI<0x23, MRMSrcMem,
908 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
909 "and{q}\t{$src2, $dst|$dst, $src2}",
910 [(set GR64:$dst, (and GR64:$src1, (load addr:$src2))),
912 def AND64ri8 : RIi8<0x83, MRM4r,
913 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
914 "and{q}\t{$src2, $dst|$dst, $src2}",
915 [(set GR64:$dst, (and GR64:$src1, i64immSExt8:$src2)),
917 def AND64ri32 : RIi32<0x81, MRM4r,
918 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
919 "and{q}\t{$src2, $dst|$dst, $src2}",
920 [(set GR64:$dst, (and GR64:$src1, i64immSExt32:$src2)),
924 def AND64mr : RI<0x21, MRMDestMem,
925 (outs), (ins i64mem:$dst, GR64:$src),
926 "and{q}\t{$src, $dst|$dst, $src}",
927 [(store (and (load addr:$dst), GR64:$src), addr:$dst),
929 def AND64mi8 : RIi8<0x83, MRM4m,
930 (outs), (ins i64mem:$dst, i64i8imm :$src),
931 "and{q}\t{$src, $dst|$dst, $src}",
932 [(store (and (load addr:$dst), i64immSExt8:$src), addr:$dst),
934 def AND64mi32 : RIi32<0x81, MRM4m,
935 (outs), (ins i64mem:$dst, i64i32imm:$src),
936 "and{q}\t{$src, $dst|$dst, $src}",
937 [(store (and (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst),
940 let isTwoAddress = 1 in {
941 let isCommutable = 1 in
942 def OR64rr : RI<0x09, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
943 "or{q}\t{$src2, $dst|$dst, $src2}",
944 [(set GR64:$dst, (or GR64:$src1, GR64:$src2)),
946 def OR64rm : RI<0x0B, MRMSrcMem , (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
947 "or{q}\t{$src2, $dst|$dst, $src2}",
948 [(set GR64:$dst, (or GR64:$src1, (load addr:$src2))),
950 def OR64ri8 : RIi8<0x83, MRM1r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
951 "or{q}\t{$src2, $dst|$dst, $src2}",
952 [(set GR64:$dst, (or GR64:$src1, i64immSExt8:$src2)),
954 def OR64ri32 : RIi32<0x81, MRM1r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
955 "or{q}\t{$src2, $dst|$dst, $src2}",
956 [(set GR64:$dst, (or GR64:$src1, i64immSExt32:$src2)),
960 def OR64mr : RI<0x09, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
961 "or{q}\t{$src, $dst|$dst, $src}",
962 [(store (or (load addr:$dst), GR64:$src), addr:$dst),
964 def OR64mi8 : RIi8<0x83, MRM1m, (outs), (ins i64mem:$dst, i64i8imm:$src),
965 "or{q}\t{$src, $dst|$dst, $src}",
966 [(store (or (load addr:$dst), i64immSExt8:$src), addr:$dst),
968 def OR64mi32 : RIi32<0x81, MRM1m, (outs), (ins i64mem:$dst, i64i32imm:$src),
969 "or{q}\t{$src, $dst|$dst, $src}",
970 [(store (or (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst),
973 let isTwoAddress = 1 in {
974 let isCommutable = 1 in
975 def XOR64rr : RI<0x31, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
976 "xor{q}\t{$src2, $dst|$dst, $src2}",
977 [(set GR64:$dst, (xor GR64:$src1, GR64:$src2)),
979 def XOR64rm : RI<0x33, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
980 "xor{q}\t{$src2, $dst|$dst, $src2}",
981 [(set GR64:$dst, (xor GR64:$src1, (load addr:$src2))),
983 def XOR64ri8 : RIi8<0x83, MRM6r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
984 "xor{q}\t{$src2, $dst|$dst, $src2}",
985 [(set GR64:$dst, (xor GR64:$src1, i64immSExt8:$src2)),
987 def XOR64ri32 : RIi32<0x81, MRM6r,
988 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
989 "xor{q}\t{$src2, $dst|$dst, $src2}",
990 [(set GR64:$dst, (xor GR64:$src1, i64immSExt32:$src2)),
994 def XOR64mr : RI<0x31, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
995 "xor{q}\t{$src, $dst|$dst, $src}",
996 [(store (xor (load addr:$dst), GR64:$src), addr:$dst),
998 def XOR64mi8 : RIi8<0x83, MRM6m, (outs), (ins i64mem:$dst, i64i8imm :$src),
999 "xor{q}\t{$src, $dst|$dst, $src}",
1000 [(store (xor (load addr:$dst), i64immSExt8:$src), addr:$dst),
1001 (implicit EFLAGS)]>;
1002 def XOR64mi32 : RIi32<0x81, MRM6m, (outs), (ins i64mem:$dst, i64i32imm:$src),
1003 "xor{q}\t{$src, $dst|$dst, $src}",
1004 [(store (xor (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst),
1005 (implicit EFLAGS)]>;
1006 } // Defs = [EFLAGS]
1008 //===----------------------------------------------------------------------===//
1009 // Comparison Instructions...
1012 // Integer comparison
1013 let Defs = [EFLAGS] in {
1014 def TEST64i32 : RI<0xa9, RawFrm, (outs), (ins i32imm:$src),
1015 "test{q}\t{$src, %rax|%rax, $src}", []>;
1016 let isCommutable = 1 in
1017 def TEST64rr : RI<0x85, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1018 "test{q}\t{$src2, $src1|$src1, $src2}",
1019 [(X86cmp (and GR64:$src1, GR64:$src2), 0),
1020 (implicit EFLAGS)]>;
1021 def TEST64rm : RI<0x85, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2),
1022 "test{q}\t{$src2, $src1|$src1, $src2}",
1023 [(X86cmp (and GR64:$src1, (loadi64 addr:$src2)), 0),
1024 (implicit EFLAGS)]>;
1025 def TEST64ri32 : RIi32<0xF7, MRM0r, (outs),
1026 (ins GR64:$src1, i64i32imm:$src2),
1027 "test{q}\t{$src2, $src1|$src1, $src2}",
1028 [(X86cmp (and GR64:$src1, i64immSExt32:$src2), 0),
1029 (implicit EFLAGS)]>;
1030 def TEST64mi32 : RIi32<0xF7, MRM0m, (outs),
1031 (ins i64mem:$src1, i64i32imm:$src2),
1032 "test{q}\t{$src2, $src1|$src1, $src2}",
1033 [(X86cmp (and (loadi64 addr:$src1), i64immSExt32:$src2), 0),
1034 (implicit EFLAGS)]>;
1037 def CMP64i32 : RI<0x3D, RawFrm, (outs), (ins i32imm:$src),
1038 "cmp{q}\t{$src, %rax|%rax, $src}", []>;
1039 def CMP64rr : RI<0x39, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1040 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1041 [(X86cmp GR64:$src1, GR64:$src2),
1042 (implicit EFLAGS)]>;
1043 def CMP64mr : RI<0x39, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1044 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1045 [(X86cmp (loadi64 addr:$src1), GR64:$src2),
1046 (implicit EFLAGS)]>;
1047 def CMP64rm : RI<0x3B, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2),
1048 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1049 [(X86cmp GR64:$src1, (loadi64 addr:$src2)),
1050 (implicit EFLAGS)]>;
1051 def CMP64ri8 : RIi8<0x83, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1052 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1053 [(X86cmp GR64:$src1, i64immSExt8:$src2),
1054 (implicit EFLAGS)]>;
1055 def CMP64ri32 : RIi32<0x81, MRM7r, (outs), (ins GR64:$src1, i64i32imm:$src2),
1056 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1057 [(X86cmp GR64:$src1, i64immSExt32:$src2),
1058 (implicit EFLAGS)]>;
1059 def CMP64mi8 : RIi8<0x83, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1060 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1061 [(X86cmp (loadi64 addr:$src1), i64immSExt8:$src2),
1062 (implicit EFLAGS)]>;
1063 def CMP64mi32 : RIi32<0x81, MRM7m, (outs),
1064 (ins i64mem:$src1, i64i32imm:$src2),
1065 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1066 [(X86cmp (loadi64 addr:$src1), i64immSExt32:$src2),
1067 (implicit EFLAGS)]>;
1068 } // Defs = [EFLAGS]
1071 // TODO: BTC, BTR, and BTS
1072 let Defs = [EFLAGS] in {
1073 def BT64rr : RI<0xA3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1074 "bt{q}\t{$src2, $src1|$src1, $src2}",
1075 [(X86bt GR64:$src1, GR64:$src2),
1076 (implicit EFLAGS)]>, TB;
1078 // Unlike with the register+register form, the memory+register form of the
1079 // bt instruction does not ignore the high bits of the index. From ISel's
1080 // perspective, this is pretty bizarre. Disable these instructions for now.
1081 //def BT64mr : RI<0xA3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1082 // "bt{q}\t{$src2, $src1|$src1, $src2}",
1083 // [(X86bt (loadi64 addr:$src1), GR64:$src2),
1084 // (implicit EFLAGS)]>, TB;
1086 def BT64ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1087 "bt{q}\t{$src2, $src1|$src1, $src2}",
1088 [(X86bt GR64:$src1, i64immSExt8:$src2),
1089 (implicit EFLAGS)]>, TB;
1090 // Note that these instructions don't need FastBTMem because that
1091 // only applies when the other operand is in a register. When it's
1092 // an immediate, bt is still fast.
1093 def BT64mi8 : Ii8<0xBA, MRM4m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1094 "bt{q}\t{$src2, $src1|$src1, $src2}",
1095 [(X86bt (loadi64 addr:$src1), i64immSExt8:$src2),
1096 (implicit EFLAGS)]>, TB;
1097 } // Defs = [EFLAGS]
1099 // Conditional moves
1100 let Uses = [EFLAGS], isTwoAddress = 1 in {
1101 let isCommutable = 1 in {
1102 def CMOVB64rr : RI<0x42, MRMSrcReg, // if <u, GR64 = GR64
1103 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1104 "cmovb\t{$src2, $dst|$dst, $src2}",
1105 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1106 X86_COND_B, EFLAGS))]>, TB;
1107 def CMOVAE64rr: RI<0x43, MRMSrcReg, // if >=u, GR64 = GR64
1108 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1109 "cmovae\t{$src2, $dst|$dst, $src2}",
1110 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1111 X86_COND_AE, EFLAGS))]>, TB;
1112 def CMOVE64rr : RI<0x44, MRMSrcReg, // if ==, GR64 = GR64
1113 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1114 "cmove\t{$src2, $dst|$dst, $src2}",
1115 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1116 X86_COND_E, EFLAGS))]>, TB;
1117 def CMOVNE64rr: RI<0x45, MRMSrcReg, // if !=, GR64 = GR64
1118 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1119 "cmovne\t{$src2, $dst|$dst, $src2}",
1120 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1121 X86_COND_NE, EFLAGS))]>, TB;
1122 def CMOVBE64rr: RI<0x46, MRMSrcReg, // if <=u, GR64 = GR64
1123 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1124 "cmovbe\t{$src2, $dst|$dst, $src2}",
1125 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1126 X86_COND_BE, EFLAGS))]>, TB;
1127 def CMOVA64rr : RI<0x47, MRMSrcReg, // if >u, GR64 = GR64
1128 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1129 "cmova\t{$src2, $dst|$dst, $src2}",
1130 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1131 X86_COND_A, EFLAGS))]>, TB;
1132 def CMOVL64rr : RI<0x4C, MRMSrcReg, // if <s, GR64 = GR64
1133 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1134 "cmovl\t{$src2, $dst|$dst, $src2}",
1135 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1136 X86_COND_L, EFLAGS))]>, TB;
1137 def CMOVGE64rr: RI<0x4D, MRMSrcReg, // if >=s, GR64 = GR64
1138 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1139 "cmovge\t{$src2, $dst|$dst, $src2}",
1140 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1141 X86_COND_GE, EFLAGS))]>, TB;
1142 def CMOVLE64rr: RI<0x4E, MRMSrcReg, // if <=s, GR64 = GR64
1143 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1144 "cmovle\t{$src2, $dst|$dst, $src2}",
1145 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1146 X86_COND_LE, EFLAGS))]>, TB;
1147 def CMOVG64rr : RI<0x4F, MRMSrcReg, // if >s, GR64 = GR64
1148 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1149 "cmovg\t{$src2, $dst|$dst, $src2}",
1150 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1151 X86_COND_G, EFLAGS))]>, TB;
1152 def CMOVS64rr : RI<0x48, MRMSrcReg, // if signed, GR64 = GR64
1153 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1154 "cmovs\t{$src2, $dst|$dst, $src2}",
1155 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1156 X86_COND_S, EFLAGS))]>, TB;
1157 def CMOVNS64rr: RI<0x49, MRMSrcReg, // if !signed, GR64 = GR64
1158 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1159 "cmovns\t{$src2, $dst|$dst, $src2}",
1160 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1161 X86_COND_NS, EFLAGS))]>, TB;
1162 def CMOVP64rr : RI<0x4A, MRMSrcReg, // if parity, GR64 = GR64
1163 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1164 "cmovp\t{$src2, $dst|$dst, $src2}",
1165 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1166 X86_COND_P, EFLAGS))]>, TB;
1167 def CMOVNP64rr : RI<0x4B, MRMSrcReg, // if !parity, GR64 = GR64
1168 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1169 "cmovnp\t{$src2, $dst|$dst, $src2}",
1170 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1171 X86_COND_NP, EFLAGS))]>, TB;
1172 def CMOVO64rr : RI<0x40, MRMSrcReg, // if overflow, GR64 = GR64
1173 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1174 "cmovo\t{$src2, $dst|$dst, $src2}",
1175 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1176 X86_COND_O, EFLAGS))]>, TB;
1177 def CMOVNO64rr : RI<0x41, MRMSrcReg, // if !overflow, GR64 = GR64
1178 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1179 "cmovno\t{$src2, $dst|$dst, $src2}",
1180 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1181 X86_COND_NO, EFLAGS))]>, TB;
1182 } // isCommutable = 1
1184 def CMOVB64rm : RI<0x42, MRMSrcMem, // if <u, GR64 = [mem64]
1185 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1186 "cmovb\t{$src2, $dst|$dst, $src2}",
1187 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1188 X86_COND_B, EFLAGS))]>, TB;
1189 def CMOVAE64rm: RI<0x43, MRMSrcMem, // if >=u, GR64 = [mem64]
1190 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1191 "cmovae\t{$src2, $dst|$dst, $src2}",
1192 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1193 X86_COND_AE, EFLAGS))]>, TB;
1194 def CMOVE64rm : RI<0x44, MRMSrcMem, // if ==, GR64 = [mem64]
1195 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1196 "cmove\t{$src2, $dst|$dst, $src2}",
1197 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1198 X86_COND_E, EFLAGS))]>, TB;
1199 def CMOVNE64rm: RI<0x45, MRMSrcMem, // if !=, GR64 = [mem64]
1200 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1201 "cmovne\t{$src2, $dst|$dst, $src2}",
1202 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1203 X86_COND_NE, EFLAGS))]>, TB;
1204 def CMOVBE64rm: RI<0x46, MRMSrcMem, // if <=u, GR64 = [mem64]
1205 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1206 "cmovbe\t{$src2, $dst|$dst, $src2}",
1207 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1208 X86_COND_BE, EFLAGS))]>, TB;
1209 def CMOVA64rm : RI<0x47, MRMSrcMem, // if >u, GR64 = [mem64]
1210 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1211 "cmova\t{$src2, $dst|$dst, $src2}",
1212 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1213 X86_COND_A, EFLAGS))]>, TB;
1214 def CMOVL64rm : RI<0x4C, MRMSrcMem, // if <s, GR64 = [mem64]
1215 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1216 "cmovl\t{$src2, $dst|$dst, $src2}",
1217 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1218 X86_COND_L, EFLAGS))]>, TB;
1219 def CMOVGE64rm: RI<0x4D, MRMSrcMem, // if >=s, GR64 = [mem64]
1220 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1221 "cmovge\t{$src2, $dst|$dst, $src2}",
1222 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1223 X86_COND_GE, EFLAGS))]>, TB;
1224 def CMOVLE64rm: RI<0x4E, MRMSrcMem, // if <=s, GR64 = [mem64]
1225 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1226 "cmovle\t{$src2, $dst|$dst, $src2}",
1227 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1228 X86_COND_LE, EFLAGS))]>, TB;
1229 def CMOVG64rm : RI<0x4F, MRMSrcMem, // if >s, GR64 = [mem64]
1230 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1231 "cmovg\t{$src2, $dst|$dst, $src2}",
1232 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1233 X86_COND_G, EFLAGS))]>, TB;
1234 def CMOVS64rm : RI<0x48, MRMSrcMem, // if signed, GR64 = [mem64]
1235 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1236 "cmovs\t{$src2, $dst|$dst, $src2}",
1237 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1238 X86_COND_S, EFLAGS))]>, TB;
1239 def CMOVNS64rm: RI<0x49, MRMSrcMem, // if !signed, GR64 = [mem64]
1240 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1241 "cmovns\t{$src2, $dst|$dst, $src2}",
1242 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1243 X86_COND_NS, EFLAGS))]>, TB;
1244 def CMOVP64rm : RI<0x4A, MRMSrcMem, // if parity, GR64 = [mem64]
1245 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1246 "cmovp\t{$src2, $dst|$dst, $src2}",
1247 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1248 X86_COND_P, EFLAGS))]>, TB;
1249 def CMOVNP64rm : RI<0x4B, MRMSrcMem, // if !parity, GR64 = [mem64]
1250 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1251 "cmovnp\t{$src2, $dst|$dst, $src2}",
1252 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1253 X86_COND_NP, EFLAGS))]>, TB;
1254 def CMOVO64rm : RI<0x40, MRMSrcMem, // if overflow, GR64 = [mem64]
1255 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1256 "cmovo\t{$src2, $dst|$dst, $src2}",
1257 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1258 X86_COND_O, EFLAGS))]>, TB;
1259 def CMOVNO64rm : RI<0x41, MRMSrcMem, // if !overflow, GR64 = [mem64]
1260 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1261 "cmovno\t{$src2, $dst|$dst, $src2}",
1262 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1263 X86_COND_NO, EFLAGS))]>, TB;
1266 //===----------------------------------------------------------------------===//
1267 // Conversion Instructions...
1270 // f64 -> signed i64
1271 def Int_CVTSD2SI64rr: RSDI<0x2D, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1272 "cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1274 (int_x86_sse2_cvtsd2si64 VR128:$src))]>;
1275 def Int_CVTSD2SI64rm: RSDI<0x2D, MRMSrcMem, (outs GR64:$dst), (ins f128mem:$src),
1276 "cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1277 [(set GR64:$dst, (int_x86_sse2_cvtsd2si64
1278 (load addr:$src)))]>;
1279 def CVTTSD2SI64rr: RSDI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins FR64:$src),
1280 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1281 [(set GR64:$dst, (fp_to_sint FR64:$src))]>;
1282 def CVTTSD2SI64rm: RSDI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f64mem:$src),
1283 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1284 [(set GR64:$dst, (fp_to_sint (loadf64 addr:$src)))]>;
1285 def Int_CVTTSD2SI64rr: RSDI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1286 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1288 (int_x86_sse2_cvttsd2si64 VR128:$src))]>;
1289 def Int_CVTTSD2SI64rm: RSDI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f128mem:$src),
1290 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1292 (int_x86_sse2_cvttsd2si64
1293 (load addr:$src)))]>;
1295 // Signed i64 -> f64
1296 def CVTSI2SD64rr: RSDI<0x2A, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
1297 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
1298 [(set FR64:$dst, (sint_to_fp GR64:$src))]>;
1299 def CVTSI2SD64rm: RSDI<0x2A, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
1300 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
1301 [(set FR64:$dst, (sint_to_fp (loadi64 addr:$src)))]>;
1303 let isTwoAddress = 1 in {
1304 def Int_CVTSI2SD64rr: RSDI<0x2A, MRMSrcReg,
1305 (outs VR128:$dst), (ins VR128:$src1, GR64:$src2),
1306 "cvtsi2sd{q}\t{$src2, $dst|$dst, $src2}",
1308 (int_x86_sse2_cvtsi642sd VR128:$src1,
1310 def Int_CVTSI2SD64rm: RSDI<0x2A, MRMSrcMem,
1311 (outs VR128:$dst), (ins VR128:$src1, i64mem:$src2),
1312 "cvtsi2sd{q}\t{$src2, $dst|$dst, $src2}",
1314 (int_x86_sse2_cvtsi642sd VR128:$src1,
1315 (loadi64 addr:$src2)))]>;
1318 // Signed i64 -> f32
1319 def CVTSI2SS64rr: RSSI<0x2A, MRMSrcReg, (outs FR32:$dst), (ins GR64:$src),
1320 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
1321 [(set FR32:$dst, (sint_to_fp GR64:$src))]>;
1322 def CVTSI2SS64rm: RSSI<0x2A, MRMSrcMem, (outs FR32:$dst), (ins i64mem:$src),
1323 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
1324 [(set FR32:$dst, (sint_to_fp (loadi64 addr:$src)))]>;
1326 let isTwoAddress = 1 in {
1327 def Int_CVTSI2SS64rr : RSSI<0x2A, MRMSrcReg,
1328 (outs VR128:$dst), (ins VR128:$src1, GR64:$src2),
1329 "cvtsi2ss{q}\t{$src2, $dst|$dst, $src2}",
1331 (int_x86_sse_cvtsi642ss VR128:$src1,
1333 def Int_CVTSI2SS64rm : RSSI<0x2A, MRMSrcMem,
1334 (outs VR128:$dst), (ins VR128:$src1, i64mem:$src2),
1335 "cvtsi2ss{q}\t{$src2, $dst|$dst, $src2}",
1337 (int_x86_sse_cvtsi642ss VR128:$src1,
1338 (loadi64 addr:$src2)))]>;
1341 // f32 -> signed i64
1342 def Int_CVTSS2SI64rr: RSSI<0x2D, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1343 "cvtss2si{q}\t{$src, $dst|$dst, $src}",
1345 (int_x86_sse_cvtss2si64 VR128:$src))]>;
1346 def Int_CVTSS2SI64rm: RSSI<0x2D, MRMSrcMem, (outs GR64:$dst), (ins f32mem:$src),
1347 "cvtss2si{q}\t{$src, $dst|$dst, $src}",
1348 [(set GR64:$dst, (int_x86_sse_cvtss2si64
1349 (load addr:$src)))]>;
1350 def CVTTSS2SI64rr: RSSI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins FR32:$src),
1351 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1352 [(set GR64:$dst, (fp_to_sint FR32:$src))]>;
1353 def CVTTSS2SI64rm: RSSI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f32mem:$src),
1354 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1355 [(set GR64:$dst, (fp_to_sint (loadf32 addr:$src)))]>;
1356 def Int_CVTTSS2SI64rr: RSSI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1357 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1359 (int_x86_sse_cvttss2si64 VR128:$src))]>;
1360 def Int_CVTTSS2SI64rm: RSSI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f32mem:$src),
1361 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1363 (int_x86_sse_cvttss2si64 (load addr:$src)))]>;
1365 //===----------------------------------------------------------------------===//
1366 // Alias Instructions
1367 //===----------------------------------------------------------------------===//
1369 // Alias instructions that map movr0 to xor. Use xorl instead of xorq; it's
1370 // equivalent due to implicit zero-extending, and it sometimes has a smaller
1372 // FIXME: AddedComplexity gives this a higher priority than MOV64ri32. Remove
1373 // when we have a better way to specify isel priority.
1374 let AddedComplexity = 1 in
1376 (SUBREG_TO_REG (i64 0), (MOV32r0), x86_subreg_32bit)>;
1379 // Materialize i64 constant where top 32-bits are zero.
1380 let AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1 in
1381 def MOV64ri64i32 : Ii32<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64i32imm:$src),
1382 "mov{l}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
1383 [(set GR64:$dst, i64immZExt32:$src)]>;
1385 //===----------------------------------------------------------------------===//
1386 // Thread Local Storage Instructions
1387 //===----------------------------------------------------------------------===//
1389 // All calls clobber the non-callee saved registers. RSP is marked as
1390 // a use to prevent stack-pointer assignments that appear immediately
1391 // before calls from potentially appearing dead.
1392 let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
1393 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
1394 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
1395 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
1396 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
1398 def TLS_addr64 : I<0, Pseudo, (outs), (ins lea64mem:$sym),
1400 "leaq\t$sym(%rip), %rdi; "
1403 "call\t__tls_get_addr@PLT",
1404 [(X86tlsaddr tls64addr:$sym)]>,
1405 Requires<[In64BitMode]>;
1407 let AddedComplexity = 5, isCodeGenOnly = 1 in
1408 def MOV64GSrm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1409 "movq\t%gs:$src, $dst",
1410 [(set GR64:$dst, (gsload addr:$src))]>, SegGS;
1412 let AddedComplexity = 5, isCodeGenOnly = 1 in
1413 def MOV64FSrm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1414 "movq\t%fs:$src, $dst",
1415 [(set GR64:$dst, (fsload addr:$src))]>, SegFS;
1417 //===----------------------------------------------------------------------===//
1418 // Atomic Instructions
1419 //===----------------------------------------------------------------------===//
1421 let Defs = [RAX, EFLAGS], Uses = [RAX] in {
1422 def LCMPXCHG64 : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$ptr, GR64:$swap),
1424 "cmpxchgq\t$swap,$ptr",
1425 [(X86cas addr:$ptr, GR64:$swap, 8)]>, TB, LOCK;
1428 let Constraints = "$val = $dst" in {
1429 let Defs = [EFLAGS] in
1430 def LXADD64 : RI<0xC1, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$ptr,GR64:$val),
1433 [(set GR64:$dst, (atomic_load_add_64 addr:$ptr, GR64:$val))]>,
1436 def XCHG64rm : RI<0x87, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$ptr,GR64:$val),
1438 [(set GR64:$dst, (atomic_swap_64 addr:$ptr, GR64:$val))]>;
1441 // Optimized codegen when the non-memory output is not used.
1442 // FIXME: Use normal add / sub instructions and add lock prefix dynamically.
1443 def LOCK_ADD64mr : RI<0x03, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
1445 "add{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1446 def LOCK_ADD64mi8 : RIi8<0x83, MRM0m, (outs),
1447 (ins i64mem:$dst, i64i8imm :$src2),
1449 "add{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1450 def LOCK_ADD64mi32 : RIi32<0x81, MRM0m, (outs),
1451 (ins i64mem:$dst, i64i32imm :$src2),
1453 "add{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1454 def LOCK_SUB64mr : RI<0x29, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
1456 "sub{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1457 def LOCK_SUB64mi8 : RIi8<0x83, MRM5m, (outs),
1458 (ins i64mem:$dst, i64i8imm :$src2),
1460 "sub{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1461 def LOCK_SUB64mi32 : RIi32<0x81, MRM5m, (outs),
1462 (ins i64mem:$dst, i64i32imm:$src2),
1464 "sub{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1465 def LOCK_INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst),
1467 "inc{q}\t$dst", []>, LOCK;
1468 def LOCK_DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst),
1470 "dec{q}\t$dst", []>, LOCK;
1472 // Atomic exchange, and, or, xor
1473 let Constraints = "$val = $dst", Defs = [EFLAGS],
1474 usesCustomDAGSchedInserter = 1 in {
1475 def ATOMAND64 : I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1476 "#ATOMAND64 PSEUDO!",
1477 [(set GR64:$dst, (atomic_load_and_64 addr:$ptr, GR64:$val))]>;
1478 def ATOMOR64 : I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1479 "#ATOMOR64 PSEUDO!",
1480 [(set GR64:$dst, (atomic_load_or_64 addr:$ptr, GR64:$val))]>;
1481 def ATOMXOR64 : I<0, Pseudo,(outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1482 "#ATOMXOR64 PSEUDO!",
1483 [(set GR64:$dst, (atomic_load_xor_64 addr:$ptr, GR64:$val))]>;
1484 def ATOMNAND64 : I<0, Pseudo,(outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1485 "#ATOMNAND64 PSEUDO!",
1486 [(set GR64:$dst, (atomic_load_nand_64 addr:$ptr, GR64:$val))]>;
1487 def ATOMMIN64: I<0, Pseudo, (outs GR64:$dst), (ins i64mem:$ptr, GR64:$val),
1488 "#ATOMMIN64 PSEUDO!",
1489 [(set GR64:$dst, (atomic_load_min_64 addr:$ptr, GR64:$val))]>;
1490 def ATOMMAX64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1491 "#ATOMMAX64 PSEUDO!",
1492 [(set GR64:$dst, (atomic_load_max_64 addr:$ptr, GR64:$val))]>;
1493 def ATOMUMIN64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1494 "#ATOMUMIN64 PSEUDO!",
1495 [(set GR64:$dst, (atomic_load_umin_64 addr:$ptr, GR64:$val))]>;
1496 def ATOMUMAX64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1497 "#ATOMUMAX64 PSEUDO!",
1498 [(set GR64:$dst, (atomic_load_umax_64 addr:$ptr, GR64:$val))]>;
1501 //===----------------------------------------------------------------------===//
1502 // Non-Instruction Patterns
1503 //===----------------------------------------------------------------------===//
1505 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable when not in small
1506 // code model mode, should use 'movabs'. FIXME: This is really a hack, the
1507 // 'movabs' predicate should handle this sort of thing.
1508 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
1509 (MOV64ri tconstpool :$dst)>, Requires<[FarData]>;
1510 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
1511 (MOV64ri tjumptable :$dst)>, Requires<[FarData]>;
1512 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
1513 (MOV64ri tglobaladdr :$dst)>, Requires<[FarData]>;
1514 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
1515 (MOV64ri texternalsym:$dst)>, Requires<[FarData]>;
1517 // In static codegen with small code model, we can get the address of a label
1518 // into a register with 'movl'. FIXME: This is a hack, the 'imm' predicate of
1519 // the MOV64ri64i32 should accept these.
1520 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
1521 (MOV64ri64i32 tconstpool :$dst)>, Requires<[SmallCode]>;
1522 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
1523 (MOV64ri64i32 tjumptable :$dst)>, Requires<[SmallCode]>;
1524 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
1525 (MOV64ri64i32 tglobaladdr :$dst)>, Requires<[SmallCode]>;
1526 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
1527 (MOV64ri64i32 texternalsym:$dst)>, Requires<[SmallCode]>;
1529 // In kernel code model, we can get the address of a label
1530 // into a register with 'movq'. FIXME: This is a hack, the 'imm' predicate of
1531 // the MOV64ri32 should accept these.
1532 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
1533 (MOV64ri32 tconstpool :$dst)>, Requires<[KernelCode]>;
1534 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
1535 (MOV64ri32 tjumptable :$dst)>, Requires<[KernelCode]>;
1536 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
1537 (MOV64ri32 tglobaladdr :$dst)>, Requires<[KernelCode]>;
1538 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
1539 (MOV64ri32 texternalsym:$dst)>, Requires<[KernelCode]>;
1541 // If we have small model and -static mode, it is safe to store global addresses
1542 // directly as immediates. FIXME: This is really a hack, the 'imm' predicate
1543 // for MOV64mi32 should handle this sort of thing.
1544 def : Pat<(store (i64 (X86Wrapper tconstpool:$src)), addr:$dst),
1545 (MOV64mi32 addr:$dst, tconstpool:$src)>,
1546 Requires<[NearData, IsStatic]>;
1547 def : Pat<(store (i64 (X86Wrapper tjumptable:$src)), addr:$dst),
1548 (MOV64mi32 addr:$dst, tjumptable:$src)>,
1549 Requires<[NearData, IsStatic]>;
1550 def : Pat<(store (i64 (X86Wrapper tglobaladdr:$src)), addr:$dst),
1551 (MOV64mi32 addr:$dst, tglobaladdr:$src)>,
1552 Requires<[NearData, IsStatic]>;
1553 def : Pat<(store (i64 (X86Wrapper texternalsym:$src)), addr:$dst),
1554 (MOV64mi32 addr:$dst, texternalsym:$src)>,
1555 Requires<[NearData, IsStatic]>;
1558 // Direct PC relative function call for small code model. 32-bit displacement
1559 // sign extended to 64-bit.
1560 def : Pat<(X86call (i64 tglobaladdr:$dst)),
1561 (CALL64pcrel32 tglobaladdr:$dst)>, Requires<[NotWin64]>;
1562 def : Pat<(X86call (i64 texternalsym:$dst)),
1563 (CALL64pcrel32 texternalsym:$dst)>, Requires<[NotWin64]>;
1565 def : Pat<(X86call (i64 tglobaladdr:$dst)),
1566 (WINCALL64pcrel32 tglobaladdr:$dst)>, Requires<[IsWin64]>;
1567 def : Pat<(X86call (i64 texternalsym:$dst)),
1568 (WINCALL64pcrel32 texternalsym:$dst)>, Requires<[IsWin64]>;
1571 def : Pat<(X86tcret GR64:$dst, imm:$off),
1572 (TCRETURNri64 GR64:$dst, imm:$off)>;
1574 def : Pat<(X86tcret (i64 tglobaladdr:$dst), imm:$off),
1575 (TCRETURNdi64 texternalsym:$dst, imm:$off)>;
1577 def : Pat<(X86tcret (i64 texternalsym:$dst), imm:$off),
1578 (TCRETURNdi64 texternalsym:$dst, imm:$off)>;
1582 // TEST R,R is smaller than CMP R,0
1583 def : Pat<(parallel (X86cmp GR64:$src1, 0), (implicit EFLAGS)),
1584 (TEST64rr GR64:$src1, GR64:$src1)>;
1586 // Conditional moves with folded loads with operands swapped and conditions
1588 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_B, EFLAGS),
1589 (CMOVAE64rm GR64:$src2, addr:$src1)>;
1590 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_AE, EFLAGS),
1591 (CMOVB64rm GR64:$src2, addr:$src1)>;
1592 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_E, EFLAGS),
1593 (CMOVNE64rm GR64:$src2, addr:$src1)>;
1594 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NE, EFLAGS),
1595 (CMOVE64rm GR64:$src2, addr:$src1)>;
1596 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_BE, EFLAGS),
1597 (CMOVA64rm GR64:$src2, addr:$src1)>;
1598 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_A, EFLAGS),
1599 (CMOVBE64rm GR64:$src2, addr:$src1)>;
1600 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_L, EFLAGS),
1601 (CMOVGE64rm GR64:$src2, addr:$src1)>;
1602 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_GE, EFLAGS),
1603 (CMOVL64rm GR64:$src2, addr:$src1)>;
1604 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_LE, EFLAGS),
1605 (CMOVG64rm GR64:$src2, addr:$src1)>;
1606 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_G, EFLAGS),
1607 (CMOVLE64rm GR64:$src2, addr:$src1)>;
1608 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_P, EFLAGS),
1609 (CMOVNP64rm GR64:$src2, addr:$src1)>;
1610 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NP, EFLAGS),
1611 (CMOVP64rm GR64:$src2, addr:$src1)>;
1612 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_S, EFLAGS),
1613 (CMOVNS64rm GR64:$src2, addr:$src1)>;
1614 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NS, EFLAGS),
1615 (CMOVS64rm GR64:$src2, addr:$src1)>;
1616 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_O, EFLAGS),
1617 (CMOVNO64rm GR64:$src2, addr:$src1)>;
1618 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NO, EFLAGS),
1619 (CMOVO64rm GR64:$src2, addr:$src1)>;
1621 // zextload bool -> zextload byte
1622 def : Pat<(zextloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>;
1625 // When extloading from 16-bit and smaller memory locations into 64-bit registers,
1626 // use zero-extending loads so that the entire 64-bit register is defined, avoiding
1627 // partial-register updates.
1628 def : Pat<(extloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>;
1629 def : Pat<(extloadi64i8 addr:$src), (MOVZX64rm8 addr:$src)>;
1630 def : Pat<(extloadi64i16 addr:$src), (MOVZX64rm16 addr:$src)>;
1631 // For other extloads, use subregs, since the high contents of the register are
1632 // defined after an extload.
1633 def : Pat<(extloadi64i32 addr:$src),
1634 (SUBREG_TO_REG (i64 0), (MOV32rm addr:$src),
1637 // anyext. Define these to do an explicit zero-extend to
1638 // avoid partial-register updates.
1639 def : Pat<(i64 (anyext GR8 :$src)), (MOVZX64rr8 GR8 :$src)>;
1640 def : Pat<(i64 (anyext GR16:$src)), (MOVZX64rr16 GR16 :$src)>;
1641 def : Pat<(i64 (anyext GR32:$src)),
1642 (SUBREG_TO_REG (i64 0), GR32:$src, x86_subreg_32bit)>;
1644 //===----------------------------------------------------------------------===//
1646 //===----------------------------------------------------------------------===//
1648 // Odd encoding trick: -128 fits into an 8-bit immediate field while
1649 // +128 doesn't, so in this special case use a sub instead of an add.
1650 def : Pat<(add GR64:$src1, 128),
1651 (SUB64ri8 GR64:$src1, -128)>;
1652 def : Pat<(store (add (loadi64 addr:$dst), 128), addr:$dst),
1653 (SUB64mi8 addr:$dst, -128)>;
1655 // The same trick applies for 32-bit immediate fields in 64-bit
1657 def : Pat<(add GR64:$src1, 0x0000000080000000),
1658 (SUB64ri32 GR64:$src1, 0xffffffff80000000)>;
1659 def : Pat<(store (add (loadi64 addr:$dst), 0x00000000800000000), addr:$dst),
1660 (SUB64mi32 addr:$dst, 0xffffffff80000000)>;
1662 // r & (2^32-1) ==> movz
1663 def : Pat<(and GR64:$src, 0x00000000FFFFFFFF),
1664 (MOVZX64rr32 (EXTRACT_SUBREG GR64:$src, x86_subreg_32bit))>;
1665 // r & (2^16-1) ==> movz
1666 def : Pat<(and GR64:$src, 0xffff),
1667 (MOVZX64rr16 (i16 (EXTRACT_SUBREG GR64:$src, x86_subreg_16bit)))>;
1668 // r & (2^8-1) ==> movz
1669 def : Pat<(and GR64:$src, 0xff),
1670 (MOVZX64rr8 (i8 (EXTRACT_SUBREG GR64:$src, x86_subreg_8bit)))>;
1671 // r & (2^8-1) ==> movz
1672 def : Pat<(and GR32:$src1, 0xff),
1673 (MOVZX32rr8 (EXTRACT_SUBREG GR32:$src1, x86_subreg_8bit))>,
1674 Requires<[In64BitMode]>;
1675 // r & (2^8-1) ==> movz
1676 def : Pat<(and GR16:$src1, 0xff),
1677 (MOVZX16rr8 (i8 (EXTRACT_SUBREG GR16:$src1, x86_subreg_8bit)))>,
1678 Requires<[In64BitMode]>;
1680 // sext_inreg patterns
1681 def : Pat<(sext_inreg GR64:$src, i32),
1682 (MOVSX64rr32 (EXTRACT_SUBREG GR64:$src, x86_subreg_32bit))>;
1683 def : Pat<(sext_inreg GR64:$src, i16),
1684 (MOVSX64rr16 (EXTRACT_SUBREG GR64:$src, x86_subreg_16bit))>;
1685 def : Pat<(sext_inreg GR64:$src, i8),
1686 (MOVSX64rr8 (EXTRACT_SUBREG GR64:$src, x86_subreg_8bit))>;
1687 def : Pat<(sext_inreg GR32:$src, i8),
1688 (MOVSX32rr8 (EXTRACT_SUBREG GR32:$src, x86_subreg_8bit))>,
1689 Requires<[In64BitMode]>;
1690 def : Pat<(sext_inreg GR16:$src, i8),
1691 (MOVSX16rr8 (i8 (EXTRACT_SUBREG GR16:$src, x86_subreg_8bit)))>,
1692 Requires<[In64BitMode]>;
1695 def : Pat<(i32 (trunc GR64:$src)),
1696 (EXTRACT_SUBREG GR64:$src, x86_subreg_32bit)>;
1697 def : Pat<(i16 (trunc GR64:$src)),
1698 (EXTRACT_SUBREG GR64:$src, x86_subreg_16bit)>;
1699 def : Pat<(i8 (trunc GR64:$src)),
1700 (EXTRACT_SUBREG GR64:$src, x86_subreg_8bit)>;
1701 def : Pat<(i8 (trunc GR32:$src)),
1702 (EXTRACT_SUBREG GR32:$src, x86_subreg_8bit)>,
1703 Requires<[In64BitMode]>;
1704 def : Pat<(i8 (trunc GR16:$src)),
1705 (EXTRACT_SUBREG GR16:$src, x86_subreg_8bit)>,
1706 Requires<[In64BitMode]>;
1708 // h-register tricks.
1709 // For now, be conservative on x86-64 and use an h-register extract only if the
1710 // value is immediately zero-extended or stored, which are somewhat common
1711 // cases. This uses a bunch of code to prevent a register requiring a REX prefix
1712 // from being allocated in the same instruction as the h register, as there's
1713 // currently no way to describe this requirement to the register allocator.
1715 // h-register extract and zero-extend.
1716 def : Pat<(and (srl_su GR64:$src, (i8 8)), (i64 255)),
1720 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR64:$src, GR64_ABCD),
1721 x86_subreg_8bit_hi)),
1723 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
1725 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_ABCD),
1726 x86_subreg_8bit_hi))>,
1727 Requires<[In64BitMode]>;
1728 def : Pat<(srl_su GR16:$src, (i8 8)),
1731 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
1732 x86_subreg_8bit_hi)),
1734 Requires<[In64BitMode]>;
1735 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
1737 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
1738 x86_subreg_8bit_hi))>,
1739 Requires<[In64BitMode]>;
1740 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
1742 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
1743 x86_subreg_8bit_hi))>,
1744 Requires<[In64BitMode]>;
1745 def : Pat<(i64 (zext (srl_su GR16:$src, (i8 8)))),
1749 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
1750 x86_subreg_8bit_hi)),
1752 def : Pat<(i64 (anyext (srl_su GR16:$src, (i8 8)))),
1756 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
1757 x86_subreg_8bit_hi)),
1760 // h-register extract and store.
1761 def : Pat<(store (i8 (trunc_su (srl_su GR64:$src, (i8 8)))), addr:$dst),
1764 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR64:$src, GR64_ABCD),
1765 x86_subreg_8bit_hi))>;
1766 def : Pat<(store (i8 (trunc_su (srl_su GR32:$src, (i8 8)))), addr:$dst),
1769 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_ABCD),
1770 x86_subreg_8bit_hi))>,
1771 Requires<[In64BitMode]>;
1772 def : Pat<(store (i8 (trunc_su (srl_su GR16:$src, (i8 8)))), addr:$dst),
1775 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
1776 x86_subreg_8bit_hi))>,
1777 Requires<[In64BitMode]>;
1779 // (shl x, 1) ==> (add x, x)
1780 def : Pat<(shl GR64:$src1, (i8 1)), (ADD64rr GR64:$src1, GR64:$src1)>;
1782 // (shl x (and y, 63)) ==> (shl x, y)
1783 def : Pat<(shl GR64:$src1, (and CL:$amt, 63)),
1784 (SHL64rCL GR64:$src1)>;
1785 def : Pat<(store (shl (loadi64 addr:$dst), (and CL:$amt, 63)), addr:$dst),
1786 (SHL64mCL addr:$dst)>;
1788 def : Pat<(srl GR64:$src1, (and CL:$amt, 63)),
1789 (SHR64rCL GR64:$src1)>;
1790 def : Pat<(store (srl (loadi64 addr:$dst), (and CL:$amt, 63)), addr:$dst),
1791 (SHR64mCL addr:$dst)>;
1793 def : Pat<(sra GR64:$src1, (and CL:$amt, 63)),
1794 (SAR64rCL GR64:$src1)>;
1795 def : Pat<(store (sra (loadi64 addr:$dst), (and CL:$amt, 63)), addr:$dst),
1796 (SAR64mCL addr:$dst)>;
1798 // (or (x >> c) | (y << (64 - c))) ==> (shrd64 x, y, c)
1799 def : Pat<(or (srl GR64:$src1, CL:$amt),
1800 (shl GR64:$src2, (sub 64, CL:$amt))),
1801 (SHRD64rrCL GR64:$src1, GR64:$src2)>;
1803 def : Pat<(store (or (srl (loadi64 addr:$dst), CL:$amt),
1804 (shl GR64:$src2, (sub 64, CL:$amt))), addr:$dst),
1805 (SHRD64mrCL addr:$dst, GR64:$src2)>;
1807 def : Pat<(or (srl GR64:$src1, (i8 (trunc RCX:$amt))),
1808 (shl GR64:$src2, (i8 (trunc (sub 64, RCX:$amt))))),
1809 (SHRD64rrCL GR64:$src1, GR64:$src2)>;
1811 def : Pat<(store (or (srl (loadi64 addr:$dst), (i8 (trunc RCX:$amt))),
1812 (shl GR64:$src2, (i8 (trunc (sub 64, RCX:$amt))))),
1814 (SHRD64mrCL addr:$dst, GR64:$src2)>;
1816 def : Pat<(shrd GR64:$src1, (i8 imm:$amt1), GR64:$src2, (i8 imm:$amt2)),
1817 (SHRD64rri8 GR64:$src1, GR64:$src2, (i8 imm:$amt1))>;
1819 def : Pat<(store (shrd (loadi64 addr:$dst), (i8 imm:$amt1),
1820 GR64:$src2, (i8 imm:$amt2)), addr:$dst),
1821 (SHRD64mri8 addr:$dst, GR64:$src2, (i8 imm:$amt1))>;
1823 // (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
1824 def : Pat<(or (shl GR64:$src1, CL:$amt),
1825 (srl GR64:$src2, (sub 64, CL:$amt))),
1826 (SHLD64rrCL GR64:$src1, GR64:$src2)>;
1828 def : Pat<(store (or (shl (loadi64 addr:$dst), CL:$amt),
1829 (srl GR64:$src2, (sub 64, CL:$amt))), addr:$dst),
1830 (SHLD64mrCL addr:$dst, GR64:$src2)>;
1832 def : Pat<(or (shl GR64:$src1, (i8 (trunc RCX:$amt))),
1833 (srl GR64:$src2, (i8 (trunc (sub 64, RCX:$amt))))),
1834 (SHLD64rrCL GR64:$src1, GR64:$src2)>;
1836 def : Pat<(store (or (shl (loadi64 addr:$dst), (i8 (trunc RCX:$amt))),
1837 (srl GR64:$src2, (i8 (trunc (sub 64, RCX:$amt))))),
1839 (SHLD64mrCL addr:$dst, GR64:$src2)>;
1841 def : Pat<(shld GR64:$src1, (i8 imm:$amt1), GR64:$src2, (i8 imm:$amt2)),
1842 (SHLD64rri8 GR64:$src1, GR64:$src2, (i8 imm:$amt1))>;
1844 def : Pat<(store (shld (loadi64 addr:$dst), (i8 imm:$amt1),
1845 GR64:$src2, (i8 imm:$amt2)), addr:$dst),
1846 (SHLD64mri8 addr:$dst, GR64:$src2, (i8 imm:$amt1))>;
1848 // X86 specific add which produces a flag.
1849 def : Pat<(addc GR64:$src1, GR64:$src2),
1850 (ADD64rr GR64:$src1, GR64:$src2)>;
1851 def : Pat<(addc GR64:$src1, (load addr:$src2)),
1852 (ADD64rm GR64:$src1, addr:$src2)>;
1853 def : Pat<(addc GR64:$src1, i64immSExt8:$src2),
1854 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
1855 def : Pat<(addc GR64:$src1, i64immSExt32:$src2),
1856 (ADD64ri32 GR64:$src1, imm:$src2)>;
1858 def : Pat<(subc GR64:$src1, GR64:$src2),
1859 (SUB64rr GR64:$src1, GR64:$src2)>;
1860 def : Pat<(subc GR64:$src1, (load addr:$src2)),
1861 (SUB64rm GR64:$src1, addr:$src2)>;
1862 def : Pat<(subc GR64:$src1, i64immSExt8:$src2),
1863 (SUB64ri8 GR64:$src1, i64immSExt8:$src2)>;
1864 def : Pat<(subc GR64:$src1, imm:$src2),
1865 (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>;
1867 //===----------------------------------------------------------------------===//
1868 // EFLAGS-defining Patterns
1869 //===----------------------------------------------------------------------===//
1871 // Register-Register Addition with EFLAGS result
1872 def : Pat<(parallel (X86add_flag GR64:$src1, GR64:$src2),
1874 (ADD64rr GR64:$src1, GR64:$src2)>;
1876 // Register-Integer Addition with EFLAGS result
1877 def : Pat<(parallel (X86add_flag GR64:$src1, i64immSExt8:$src2),
1879 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
1880 def : Pat<(parallel (X86add_flag GR64:$src1, i64immSExt32:$src2),
1882 (ADD64ri32 GR64:$src1, i64immSExt32:$src2)>;
1884 // Register-Memory Addition with EFLAGS result
1885 def : Pat<(parallel (X86add_flag GR64:$src1, (loadi64 addr:$src2)),
1887 (ADD64rm GR64:$src1, addr:$src2)>;
1889 // Memory-Register Addition with EFLAGS result
1890 def : Pat<(parallel (store (X86add_flag (loadi64 addr:$dst), GR64:$src2),
1893 (ADD64mr addr:$dst, GR64:$src2)>;
1894 def : Pat<(parallel (store (X86add_flag (loadi64 addr:$dst), i64immSExt8:$src2),
1897 (ADD64mi8 addr:$dst, i64immSExt8:$src2)>;
1898 def : Pat<(parallel (store (X86add_flag (loadi64 addr:$dst), i64immSExt32:$src2),
1901 (ADD64mi32 addr:$dst, i64immSExt32:$src2)>;
1903 // Register-Register Subtraction with EFLAGS result
1904 def : Pat<(parallel (X86sub_flag GR64:$src1, GR64:$src2),
1906 (SUB64rr GR64:$src1, GR64:$src2)>;
1908 // Register-Memory Subtraction with EFLAGS result
1909 def : Pat<(parallel (X86sub_flag GR64:$src1, (loadi64 addr:$src2)),
1911 (SUB64rm GR64:$src1, addr:$src2)>;
1913 // Register-Integer Subtraction with EFLAGS result
1914 def : Pat<(parallel (X86sub_flag GR64:$src1, i64immSExt8:$src2),
1916 (SUB64ri8 GR64:$src1, i64immSExt8:$src2)>;
1917 def : Pat<(parallel (X86sub_flag GR64:$src1, i64immSExt32:$src2),
1919 (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>;
1921 // Memory-Register Subtraction with EFLAGS result
1922 def : Pat<(parallel (store (X86sub_flag (loadi64 addr:$dst), GR64:$src2),
1925 (SUB64mr addr:$dst, GR64:$src2)>;
1927 // Memory-Integer Subtraction with EFLAGS result
1928 def : Pat<(parallel (store (X86sub_flag (loadi64 addr:$dst), i64immSExt8:$src2),
1931 (SUB64mi8 addr:$dst, i64immSExt8:$src2)>;
1932 def : Pat<(parallel (store (X86sub_flag (loadi64 addr:$dst), i64immSExt32:$src2),
1935 (SUB64mi32 addr:$dst, i64immSExt32:$src2)>;
1937 // Register-Register Signed Integer Multiplication with EFLAGS result
1938 def : Pat<(parallel (X86smul_flag GR64:$src1, GR64:$src2),
1940 (IMUL64rr GR64:$src1, GR64:$src2)>;
1942 // Register-Memory Signed Integer Multiplication with EFLAGS result
1943 def : Pat<(parallel (X86smul_flag GR64:$src1, (loadi64 addr:$src2)),
1945 (IMUL64rm GR64:$src1, addr:$src2)>;
1947 // Register-Integer Signed Integer Multiplication with EFLAGS result
1948 def : Pat<(parallel (X86smul_flag GR64:$src1, i64immSExt8:$src2),
1950 (IMUL64rri8 GR64:$src1, i64immSExt8:$src2)>;
1951 def : Pat<(parallel (X86smul_flag GR64:$src1, i64immSExt32:$src2),
1953 (IMUL64rri32 GR64:$src1, i64immSExt32:$src2)>;
1955 // Memory-Integer Signed Integer Multiplication with EFLAGS result
1956 def : Pat<(parallel (X86smul_flag (loadi64 addr:$src1), i64immSExt8:$src2),
1958 (IMUL64rmi8 addr:$src1, i64immSExt8:$src2)>;
1959 def : Pat<(parallel (X86smul_flag (loadi64 addr:$src1), i64immSExt32:$src2),
1961 (IMUL64rmi32 addr:$src1, i64immSExt32:$src2)>;
1963 // INC and DEC with EFLAGS result. Note that these do not set CF.
1964 def : Pat<(parallel (X86inc_flag GR16:$src), (implicit EFLAGS)),
1965 (INC64_16r GR16:$src)>, Requires<[In64BitMode]>;
1966 def : Pat<(parallel (store (i16 (X86inc_flag (loadi16 addr:$dst))), addr:$dst),
1968 (INC64_16m addr:$dst)>, Requires<[In64BitMode]>;
1969 def : Pat<(parallel (X86dec_flag GR16:$src), (implicit EFLAGS)),
1970 (DEC64_16r GR16:$src)>, Requires<[In64BitMode]>;
1971 def : Pat<(parallel (store (i16 (X86dec_flag (loadi16 addr:$dst))), addr:$dst),
1973 (DEC64_16m addr:$dst)>, Requires<[In64BitMode]>;
1975 def : Pat<(parallel (X86inc_flag GR32:$src), (implicit EFLAGS)),
1976 (INC64_32r GR32:$src)>, Requires<[In64BitMode]>;
1977 def : Pat<(parallel (store (i32 (X86inc_flag (loadi32 addr:$dst))), addr:$dst),
1979 (INC64_32m addr:$dst)>, Requires<[In64BitMode]>;
1980 def : Pat<(parallel (X86dec_flag GR32:$src), (implicit EFLAGS)),
1981 (DEC64_32r GR32:$src)>, Requires<[In64BitMode]>;
1982 def : Pat<(parallel (store (i32 (X86dec_flag (loadi32 addr:$dst))), addr:$dst),
1984 (DEC64_32m addr:$dst)>, Requires<[In64BitMode]>;
1986 def : Pat<(parallel (X86inc_flag GR64:$src), (implicit EFLAGS)),
1987 (INC64r GR64:$src)>;
1988 def : Pat<(parallel (store (i64 (X86inc_flag (loadi64 addr:$dst))), addr:$dst),
1990 (INC64m addr:$dst)>;
1991 def : Pat<(parallel (X86dec_flag GR64:$src), (implicit EFLAGS)),
1992 (DEC64r GR64:$src)>;
1993 def : Pat<(parallel (store (i64 (X86dec_flag (loadi64 addr:$dst))), addr:$dst),
1995 (DEC64m addr:$dst)>;
1997 //===----------------------------------------------------------------------===//
1998 // X86-64 SSE Instructions
1999 //===----------------------------------------------------------------------===//
2001 // Move instructions...
2003 def MOV64toPQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
2004 "mov{d|q}\t{$src, $dst|$dst, $src}",
2006 (v2i64 (scalar_to_vector GR64:$src)))]>;
2007 def MOVPQIto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
2008 "mov{d|q}\t{$src, $dst|$dst, $src}",
2009 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
2012 def MOV64toSDrr : RPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
2013 "mov{d|q}\t{$src, $dst|$dst, $src}",
2014 [(set FR64:$dst, (bitconvert GR64:$src))]>;
2015 def MOV64toSDrm : RPDI<0x6E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
2016 "movq\t{$src, $dst|$dst, $src}",
2017 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>;
2019 def MOVSDto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
2020 "mov{d|q}\t{$src, $dst|$dst, $src}",
2021 [(set GR64:$dst, (bitconvert FR64:$src))]>;
2022 def MOVSDto64mr : RPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
2023 "movq\t{$src, $dst|$dst, $src}",
2024 [(store (i64 (bitconvert FR64:$src)), addr:$dst)]>;
2026 //===----------------------------------------------------------------------===//
2027 // X86-64 SSE4.1 Instructions
2028 //===----------------------------------------------------------------------===//
2030 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
2031 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
2032 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
2033 (ins VR128:$src1, i32i8imm:$src2),
2034 !strconcat(OpcodeStr,
2035 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2037 (extractelt (v2i64 VR128:$src1), imm:$src2))]>, OpSize, REX_W;
2038 def mr : SS4AIi8<opc, MRMDestMem, (outs),
2039 (ins i64mem:$dst, VR128:$src1, i32i8imm:$src2),
2040 !strconcat(OpcodeStr,
2041 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2042 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
2043 addr:$dst)]>, OpSize, REX_W;
2046 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
2048 let isTwoAddress = 1 in {
2049 multiclass SS41I_insert64<bits<8> opc, string OpcodeStr> {
2050 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
2051 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
2052 !strconcat(OpcodeStr,
2053 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2055 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
2057 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
2058 (ins VR128:$src1, i64mem:$src2, i32i8imm:$src3),
2059 !strconcat(OpcodeStr,
2060 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2062 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
2063 imm:$src3)))]>, OpSize, REX_W;
2067 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">;
2069 // -disable-16bit support.
2070 def : Pat<(truncstorei16 (i64 imm:$src), addr:$dst),
2071 (MOV16mi addr:$dst, imm:$src)>;
2072 def : Pat<(truncstorei16 GR64:$src, addr:$dst),
2073 (MOV16mr addr:$dst, (EXTRACT_SUBREG GR64:$src, x86_subreg_16bit))>;
2074 def : Pat<(i64 (sextloadi16 addr:$dst)),
2075 (MOVSX64rm16 addr:$dst)>;
2076 def : Pat<(i64 (zextloadi16 addr:$dst)),
2077 (MOVZX64rm16 addr:$dst)>;
2078 def : Pat<(i64 (extloadi16 addr:$dst)),
2079 (MOVZX64rm16 addr:$dst)>;