1 //====- X86Instr64bit.td - Describe X86-64 Instructions ----*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86-64 instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // Operand Definitions.
20 // 64-bits but only 32 bits are significant.
21 def i64i32imm : Operand<i64>;
23 // 64-bits but only 32 bits are significant, and those bits are treated as being
25 def i64i32imm_pcrel : Operand<i64> {
26 let PrintMethod = "print_pcrel_imm";
30 // 64-bits but only 8 bits are significant.
31 def i64i8imm : Operand<i64> {
32 let ParserMatchClass = ImmSExt8AsmOperand;
35 def lea64mem : Operand<i64> {
36 let PrintMethod = "printlea64mem";
37 let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm);
38 let ParserMatchClass = X86MemAsmOperand;
41 def lea64_32mem : Operand<i32> {
42 let PrintMethod = "printlea64_32mem";
43 let AsmOperandLowerMethod = "lower_lea64_32mem";
44 let MIOperandInfo = (ops GR32, i8imm, GR32_NOSP, i32imm);
45 let ParserMatchClass = X86MemAsmOperand;
48 //===----------------------------------------------------------------------===//
49 // Complex Pattern Definitions.
51 def lea64addr : ComplexPattern<i64, 4, "SelectLEAAddr",
52 [add, sub, mul, X86mul_imm, shl, or, frameindex,
55 def tls64addr : ComplexPattern<i64, 4, "SelectTLSADDRAddr",
56 [tglobaltlsaddr], []>;
58 //===----------------------------------------------------------------------===//
62 def i64immSExt8 : PatLeaf<(i64 imm), [{
63 // i64immSExt8 predicate - True if the 64-bit immediate fits in a 8-bit
64 // sign extended field.
65 return (int64_t)N->getZExtValue() == (int8_t)N->getZExtValue();
68 def i64immSExt32 : PatLeaf<(i64 imm), [{
69 // i64immSExt32 predicate - True if the 64-bit immediate fits in a 32-bit
70 // sign extended field.
71 return (int64_t)N->getZExtValue() == (int32_t)N->getZExtValue();
74 def i64immZExt32 : PatLeaf<(i64 imm), [{
75 // i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit
76 // unsignedsign extended field.
77 return (uint64_t)N->getZExtValue() == (uint32_t)N->getZExtValue();
80 def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>;
81 def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>;
82 def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>;
84 def zextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (zextloadi1 node:$ptr))>;
85 def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>;
86 def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>;
87 def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>;
89 def extloadi64i1 : PatFrag<(ops node:$ptr), (i64 (extloadi1 node:$ptr))>;
90 def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>;
91 def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>;
92 def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>;
94 //===----------------------------------------------------------------------===//
95 // Instruction list...
98 // ADJCALLSTACKDOWN/UP implicitly use/def RSP because they may be expanded into
99 // a stack adjustment and the codegen must know that they may modify the stack
100 // pointer before prolog-epilog rewriting occurs.
101 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
102 // sub / add which can clobber EFLAGS.
103 let Defs = [RSP, EFLAGS], Uses = [RSP] in {
104 def ADJCALLSTACKDOWN64 : I<0, Pseudo, (outs), (ins i32imm:$amt),
106 [(X86callseq_start timm:$amt)]>,
107 Requires<[In64BitMode]>;
108 def ADJCALLSTACKUP64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
110 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
111 Requires<[In64BitMode]>;
114 //===----------------------------------------------------------------------===//
115 // Call Instructions...
118 // All calls clobber the non-callee saved registers. RSP is marked as
119 // a use to prevent stack-pointer assignments that appear immediately
120 // before calls from potentially appearing dead. Uses for argument
121 // registers are added manually.
122 let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
123 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
124 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
125 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
126 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
129 // NOTE: this pattern doesn't match "X86call imm", because we do not know
130 // that the offset between an arbitrary immediate and the call will fit in
131 // the 32-bit pcrel field that we have.
132 def CALL64pcrel32 : Ii32<0xE8, RawFrm,
133 (outs), (ins i64i32imm_pcrel:$dst, variable_ops),
135 Requires<[In64BitMode, NotWin64]>;
136 def CALL64r : I<0xFF, MRM2r, (outs), (ins GR64:$dst, variable_ops),
137 "call\t{*}$dst", [(X86call GR64:$dst)]>,
138 Requires<[NotWin64]>;
139 def CALL64m : I<0xFF, MRM2m, (outs), (ins i64mem:$dst, variable_ops),
140 "call\t{*}$dst", [(X86call (loadi64 addr:$dst))]>,
141 Requires<[NotWin64]>;
143 def FARCALL64 : RI<0xFF, MRM3m, (outs), (ins opaque80mem:$dst),
144 "lcall{q}\t{*}$dst", []>;
147 // FIXME: We need to teach codegen about single list of call-clobbered registers.
149 // All calls clobber the non-callee saved registers. RSP is marked as
150 // a use to prevent stack-pointer assignments that appear immediately
151 // before calls from potentially appearing dead. Uses for argument
152 // registers are added manually.
153 let Defs = [RAX, RCX, RDX, R8, R9, R10, R11,
154 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
155 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
156 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, EFLAGS],
158 def WINCALL64pcrel32 : I<0xE8, RawFrm,
159 (outs), (ins i64i32imm_pcrel:$dst, variable_ops),
162 def WINCALL64r : I<0xFF, MRM2r, (outs), (ins GR64:$dst, variable_ops),
164 [(X86call GR64:$dst)]>, Requires<[IsWin64]>;
165 def WINCALL64m : I<0xFF, MRM2m, (outs), (ins i64mem:$dst, variable_ops),
167 [(X86call (loadi64 addr:$dst))]>, Requires<[IsWin64]>;
171 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
172 def TCRETURNdi64 : I<0, Pseudo, (outs), (ins i64imm:$dst, i32imm:$offset,
174 "#TC_RETURN $dst $offset",
177 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
178 def TCRETURNri64 : I<0, Pseudo, (outs), (ins GR64:$dst, i32imm:$offset,
180 "#TC_RETURN $dst $offset",
184 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
185 def TAILJMPr64 : I<0xFF, MRM4r, (outs), (ins GR64:$dst),
186 "jmp{q}\t{*}$dst # TAILCALL",
190 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
191 def JMP64r : I<0xFF, MRM4r, (outs), (ins GR64:$dst), "jmp{q}\t{*}$dst",
192 [(brind GR64:$dst)]>;
193 def JMP64m : I<0xFF, MRM4m, (outs), (ins i64mem:$dst), "jmp{q}\t{*}$dst",
194 [(brind (loadi64 addr:$dst))]>;
195 def FARJMP64 : RI<0xFF, MRM5m, (outs), (ins opaque80mem:$dst),
196 "ljmp{q}\t{*}$dst", []>;
199 //===----------------------------------------------------------------------===//
200 // EH Pseudo Instructions
202 let isTerminator = 1, isReturn = 1, isBarrier = 1,
204 def EH_RETURN64 : I<0xC3, RawFrm, (outs), (ins GR64:$addr),
205 "ret\t#eh_return, addr: $addr",
206 [(X86ehret GR64:$addr)]>;
210 //===----------------------------------------------------------------------===//
211 // Miscellaneous Instructions...
213 let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, neverHasSideEffects = 1 in
214 def LEAVE64 : I<0xC9, RawFrm,
215 (outs), (ins), "leave", []>;
216 let Defs = [RSP], Uses = [RSP], neverHasSideEffects=1 in {
218 def POP64r : I<0x58, AddRegFrm,
219 (outs GR64:$reg), (ins), "pop{q}\t$reg", []>;
220 def POP64rmr: I<0x8F, MRM0r, (outs GR64:$reg), (ins), "pop{q}\t$reg", []>;
221 def POP64rmm: I<0x8F, MRM0m, (outs i64mem:$dst), (ins), "pop{q}\t$dst", []>;
223 let mayStore = 1 in {
224 def PUSH64r : I<0x50, AddRegFrm,
225 (outs), (ins GR64:$reg), "push{q}\t$reg", []>;
226 def PUSH64rmr: I<0xFF, MRM6r, (outs), (ins GR64:$reg), "push{q}\t$reg", []>;
227 def PUSH64rmm: I<0xFF, MRM6m, (outs), (ins i64mem:$src), "push{q}\t$src", []>;
231 let Defs = [RSP], Uses = [RSP], neverHasSideEffects = 1, mayStore = 1 in {
232 def PUSH64i8 : Ii8<0x6a, RawFrm, (outs), (ins i8imm:$imm),
233 "push{q}\t$imm", []>;
234 def PUSH64i16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
235 "push{q}\t$imm", []>;
236 def PUSH64i32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
237 "push{q}\t$imm", []>;
240 let Defs = [RSP, EFLAGS], Uses = [RSP], mayLoad = 1 in
241 def POPFQ : I<0x9D, RawFrm, (outs), (ins), "popf", []>, REX_W;
242 let Defs = [RSP], Uses = [RSP, EFLAGS], mayStore = 1 in
243 def PUSHFQ : I<0x9C, RawFrm, (outs), (ins), "pushf", []>;
245 def LEA64_32r : I<0x8D, MRMSrcMem,
246 (outs GR32:$dst), (ins lea64_32mem:$src),
247 "lea{l}\t{$src|$dst}, {$dst|$src}",
248 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In64BitMode]>;
250 let isReMaterializable = 1 in
251 def LEA64r : RI<0x8D, MRMSrcMem, (outs GR64:$dst), (ins lea64mem:$src),
252 "lea{q}\t{$src|$dst}, {$dst|$src}",
253 [(set GR64:$dst, lea64addr:$src)]>;
255 let isTwoAddress = 1 in
256 def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src),
258 [(set GR64:$dst, (bswap GR64:$src))]>, TB;
260 // Bit scan instructions.
261 let Defs = [EFLAGS] in {
262 def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
263 "bsf{q}\t{$src, $dst|$dst, $src}",
264 [(set GR64:$dst, (X86bsf GR64:$src)), (implicit EFLAGS)]>, TB;
265 def BSF64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
266 "bsf{q}\t{$src, $dst|$dst, $src}",
267 [(set GR64:$dst, (X86bsf (loadi64 addr:$src))),
268 (implicit EFLAGS)]>, TB;
270 def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
271 "bsr{q}\t{$src, $dst|$dst, $src}",
272 [(set GR64:$dst, (X86bsr GR64:$src)), (implicit EFLAGS)]>, TB;
273 def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
274 "bsr{q}\t{$src, $dst|$dst, $src}",
275 [(set GR64:$dst, (X86bsr (loadi64 addr:$src))),
276 (implicit EFLAGS)]>, TB;
280 let Defs = [RCX,RDI,RSI], Uses = [RCX,RDI,RSI] in
281 def REP_MOVSQ : RI<0xA5, RawFrm, (outs), (ins), "{rep;movsq|rep movsq}",
282 [(X86rep_movs i64)]>, REP;
283 let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI] in
284 def REP_STOSQ : RI<0xAB, RawFrm, (outs), (ins), "{rep;stosq|rep stosq}",
285 [(X86rep_stos i64)]>, REP;
287 def SCAS64 : RI<0xAF, RawFrm, (outs), (ins), "scas{q}", []>;
289 def CMPS64 : RI<0xA7, RawFrm, (outs), (ins), "cmps{q}", []>;
291 // Fast system-call instructions
292 def SYSEXIT64 : RI<0x35, RawFrm,
293 (outs), (ins), "sysexit", []>, TB;
295 //===----------------------------------------------------------------------===//
296 // Move Instructions...
299 let neverHasSideEffects = 1 in
300 def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
301 "mov{q}\t{$src, $dst|$dst, $src}", []>;
303 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
304 def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src),
305 "movabs{q}\t{$src, $dst|$dst, $src}",
306 [(set GR64:$dst, imm:$src)]>;
307 def MOV64ri32 : RIi32<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src),
308 "mov{q}\t{$src, $dst|$dst, $src}",
309 [(set GR64:$dst, i64immSExt32:$src)]>;
312 let canFoldAsLoad = 1 in
313 def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
314 "mov{q}\t{$src, $dst|$dst, $src}",
315 [(set GR64:$dst, (load addr:$src))]>;
317 def MOV64mr : RI<0x89, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
318 "mov{q}\t{$src, $dst|$dst, $src}",
319 [(store GR64:$src, addr:$dst)]>;
320 def MOV64mi32 : RIi32<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src),
321 "mov{q}\t{$src, $dst|$dst, $src}",
322 [(store i64immSExt32:$src, addr:$dst)]>;
324 def MOV64o8a : RIi8<0xA0, RawFrm, (outs), (ins i8imm:$src),
325 "mov{q}\t{$src, %rax|%rax, $src}", []>;
326 def MOV64o32a : RIi32<0xA1, RawFrm, (outs), (ins i32imm:$src),
327 "mov{q}\t{$src, %rax|%rax, $src}", []>;
328 def MOV64ao8 : RIi8<0xA2, RawFrm, (outs i8imm:$dst), (ins),
329 "mov{q}\t{%rax, $dst|$dst, %rax}", []>;
330 def MOV64ao32 : RIi32<0xA3, RawFrm, (outs i32imm:$dst), (ins),
331 "mov{q}\t{%rax, $dst|$dst, %rax}", []>;
333 // Moves to and from segment registers
334 def MOV64rs : RI<0x8C, MRMDestReg, (outs GR64:$dst), (ins SEGMENT_REG:$src),
335 "mov{w}\t{$src, $dst|$dst, $src}", []>;
336 def MOV64ms : RI<0x8C, MRMDestMem, (outs i64mem:$dst), (ins SEGMENT_REG:$src),
337 "mov{w}\t{$src, $dst|$dst, $src}", []>;
338 def MOV64sr : RI<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR64:$src),
339 "mov{w}\t{$src, $dst|$dst, $src}", []>;
340 def MOV64sm : RI<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i64mem:$src),
341 "mov{w}\t{$src, $dst|$dst, $src}", []>;
343 // Sign/Zero extenders
345 // MOVSX64rr8 always has a REX prefix and it has an 8-bit register
346 // operand, which makes it a rare instruction with an 8-bit register
347 // operand that can never access an h register. If support for h registers
348 // were generalized, this would require a special register class.
349 def MOVSX64rr8 : RI<0xBE, MRMSrcReg, (outs GR64:$dst), (ins GR8 :$src),
350 "movs{bq|x}\t{$src, $dst|$dst, $src}",
351 [(set GR64:$dst, (sext GR8:$src))]>, TB;
352 def MOVSX64rm8 : RI<0xBE, MRMSrcMem, (outs GR64:$dst), (ins i8mem :$src),
353 "movs{bq|x}\t{$src, $dst|$dst, $src}",
354 [(set GR64:$dst, (sextloadi64i8 addr:$src))]>, TB;
355 def MOVSX64rr16: RI<0xBF, MRMSrcReg, (outs GR64:$dst), (ins GR16:$src),
356 "movs{wq|x}\t{$src, $dst|$dst, $src}",
357 [(set GR64:$dst, (sext GR16:$src))]>, TB;
358 def MOVSX64rm16: RI<0xBF, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
359 "movs{wq|x}\t{$src, $dst|$dst, $src}",
360 [(set GR64:$dst, (sextloadi64i16 addr:$src))]>, TB;
361 def MOVSX64rr32: RI<0x63, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src),
362 "movs{lq|xd}\t{$src, $dst|$dst, $src}",
363 [(set GR64:$dst, (sext GR32:$src))]>;
364 def MOVSX64rm32: RI<0x63, MRMSrcMem, (outs GR64:$dst), (ins i32mem:$src),
365 "movs{lq|xd}\t{$src, $dst|$dst, $src}",
366 [(set GR64:$dst, (sextloadi64i32 addr:$src))]>;
368 // Use movzbl instead of movzbq when the destination is a register; it's
369 // equivalent due to implicit zero-extending, and it has a smaller encoding.
370 def MOVZX64rr8 : I<0xB6, MRMSrcReg, (outs GR64:$dst), (ins GR8 :$src),
371 "movz{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
372 [(set GR64:$dst, (zext GR8:$src))]>, TB;
373 def MOVZX64rm8 : I<0xB6, MRMSrcMem, (outs GR64:$dst), (ins i8mem :$src),
374 "movz{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
375 [(set GR64:$dst, (zextloadi64i8 addr:$src))]>, TB;
376 // Use movzwl instead of movzwq when the destination is a register; it's
377 // equivalent due to implicit zero-extending, and it has a smaller encoding.
378 def MOVZX64rr16: I<0xB7, MRMSrcReg, (outs GR64:$dst), (ins GR16:$src),
379 "movz{wl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
380 [(set GR64:$dst, (zext GR16:$src))]>, TB;
381 def MOVZX64rm16: I<0xB7, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
382 "movz{wl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
383 [(set GR64:$dst, (zextloadi64i16 addr:$src))]>, TB;
385 // There's no movzlq instruction, but movl can be used for this purpose, using
386 // implicit zero-extension. The preferred way to do 32-bit-to-64-bit zero
387 // extension on x86-64 is to use a SUBREG_TO_REG to utilize implicit
388 // zero-extension, however this isn't possible when the 32-bit value is
389 // defined by a truncate or is copied from something where the high bits aren't
390 // necessarily all zero. In such cases, we fall back to these explicit zext
392 def MOVZX64rr32 : I<0x89, MRMDestReg, (outs GR64:$dst), (ins GR32:$src),
393 "mov{l}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
394 [(set GR64:$dst, (zext GR32:$src))]>;
395 def MOVZX64rm32 : I<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i32mem:$src),
396 "mov{l}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
397 [(set GR64:$dst, (zextloadi64i32 addr:$src))]>;
399 // Any instruction that defines a 32-bit result leaves the high half of the
400 // register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may
401 // be copying from a truncate. And x86's cmov doesn't do anything if the
402 // condition is false. But any other 32-bit operation will zero-extend
404 def def32 : PatLeaf<(i32 GR32:$src), [{
405 return N->getOpcode() != ISD::TRUNCATE &&
406 N->getOpcode() != TargetInstrInfo::EXTRACT_SUBREG &&
407 N->getOpcode() != ISD::CopyFromReg &&
408 N->getOpcode() != X86ISD::CMOV;
411 // In the case of a 32-bit def that is known to implicitly zero-extend,
412 // we can use a SUBREG_TO_REG.
413 def : Pat<(i64 (zext def32:$src)),
414 (SUBREG_TO_REG (i64 0), GR32:$src, x86_subreg_32bit)>;
416 let neverHasSideEffects = 1 in {
417 let Defs = [RAX], Uses = [EAX] in
418 def CDQE : RI<0x98, RawFrm, (outs), (ins),
419 "{cltq|cdqe}", []>; // RAX = signext(EAX)
421 let Defs = [RAX,RDX], Uses = [RAX] in
422 def CQO : RI<0x99, RawFrm, (outs), (ins),
423 "{cqto|cqo}", []>; // RDX:RAX = signext(RAX)
426 //===----------------------------------------------------------------------===//
427 // Arithmetic Instructions...
430 let Defs = [EFLAGS] in {
432 def ADD64i32 : RI<0x05, RawFrm, (outs), (ins i32imm:$src),
433 "add{q}\t{$src, %rax|%rax, $src}", []>;
435 let isTwoAddress = 1 in {
436 let isConvertibleToThreeAddress = 1 in {
437 let isCommutable = 1 in
438 // Register-Register Addition
439 def ADD64rr : RI<0x01, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
440 "add{q}\t{$src2, $dst|$dst, $src2}",
441 [(set GR64:$dst, (add GR64:$src1, GR64:$src2)),
444 // Register-Integer Addition
445 def ADD64ri8 : RIi8<0x83, MRM0r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
446 "add{q}\t{$src2, $dst|$dst, $src2}",
447 [(set GR64:$dst, (add GR64:$src1, i64immSExt8:$src2)),
449 def ADD64ri32 : RIi32<0x81, MRM0r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
450 "add{q}\t{$src2, $dst|$dst, $src2}",
451 [(set GR64:$dst, (add GR64:$src1, i64immSExt32:$src2)),
453 } // isConvertibleToThreeAddress
455 // Register-Memory Addition
456 def ADD64rm : RI<0x03, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
457 "add{q}\t{$src2, $dst|$dst, $src2}",
458 [(set GR64:$dst, (add GR64:$src1, (load addr:$src2))),
462 // Memory-Register Addition
463 def ADD64mr : RI<0x01, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
464 "add{q}\t{$src2, $dst|$dst, $src2}",
465 [(store (add (load addr:$dst), GR64:$src2), addr:$dst),
467 def ADD64mi8 : RIi8<0x83, MRM0m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
468 "add{q}\t{$src2, $dst|$dst, $src2}",
469 [(store (add (load addr:$dst), i64immSExt8:$src2), addr:$dst),
471 def ADD64mi32 : RIi32<0x81, MRM0m, (outs), (ins i64mem:$dst, i64i32imm :$src2),
472 "add{q}\t{$src2, $dst|$dst, $src2}",
473 [(store (add (load addr:$dst), i64immSExt32:$src2), addr:$dst),
476 let Uses = [EFLAGS] in {
478 def ADC64i32 : RI<0x15, RawFrm, (outs), (ins i32imm:$src),
479 "adc{q}\t{$src, %rax|%rax, $src}", []>;
481 let isTwoAddress = 1 in {
482 let isCommutable = 1 in
483 def ADC64rr : RI<0x11, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
484 "adc{q}\t{$src2, $dst|$dst, $src2}",
485 [(set GR64:$dst, (adde GR64:$src1, GR64:$src2))]>;
487 def ADC64rm : RI<0x13, MRMSrcMem , (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
488 "adc{q}\t{$src2, $dst|$dst, $src2}",
489 [(set GR64:$dst, (adde GR64:$src1, (load addr:$src2)))]>;
491 def ADC64ri8 : RIi8<0x83, MRM2r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
492 "adc{q}\t{$src2, $dst|$dst, $src2}",
493 [(set GR64:$dst, (adde GR64:$src1, i64immSExt8:$src2))]>;
494 def ADC64ri32 : RIi32<0x81, MRM2r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
495 "adc{q}\t{$src2, $dst|$dst, $src2}",
496 [(set GR64:$dst, (adde GR64:$src1, i64immSExt32:$src2))]>;
499 def ADC64mr : RI<0x11, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
500 "adc{q}\t{$src2, $dst|$dst, $src2}",
501 [(store (adde (load addr:$dst), GR64:$src2), addr:$dst)]>;
502 def ADC64mi8 : RIi8<0x83, MRM2m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
503 "adc{q}\t{$src2, $dst|$dst, $src2}",
504 [(store (adde (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>;
505 def ADC64mi32 : RIi32<0x81, MRM2m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
506 "adc{q}\t{$src2, $dst|$dst, $src2}",
507 [(store (adde (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>;
510 let isTwoAddress = 1 in {
511 // Register-Register Subtraction
512 def SUB64rr : RI<0x29, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
513 "sub{q}\t{$src2, $dst|$dst, $src2}",
514 [(set GR64:$dst, (sub GR64:$src1, GR64:$src2)),
517 // Register-Memory Subtraction
518 def SUB64rm : RI<0x2B, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
519 "sub{q}\t{$src2, $dst|$dst, $src2}",
520 [(set GR64:$dst, (sub GR64:$src1, (load addr:$src2))),
523 // Register-Integer Subtraction
524 def SUB64ri8 : RIi8<0x83, MRM5r, (outs GR64:$dst),
525 (ins GR64:$src1, i64i8imm:$src2),
526 "sub{q}\t{$src2, $dst|$dst, $src2}",
527 [(set GR64:$dst, (sub GR64:$src1, i64immSExt8:$src2)),
529 def SUB64ri32 : RIi32<0x81, MRM5r, (outs GR64:$dst),
530 (ins GR64:$src1, i64i32imm:$src2),
531 "sub{q}\t{$src2, $dst|$dst, $src2}",
532 [(set GR64:$dst, (sub GR64:$src1, i64immSExt32:$src2)),
536 def SUB64i32 : RI<0x2D, RawFrm, (outs), (ins i32imm:$src),
537 "sub{q}\t{$src, %rax|%rax, $src}", []>;
539 // Memory-Register Subtraction
540 def SUB64mr : RI<0x29, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
541 "sub{q}\t{$src2, $dst|$dst, $src2}",
542 [(store (sub (load addr:$dst), GR64:$src2), addr:$dst),
545 // Memory-Integer Subtraction
546 def SUB64mi8 : RIi8<0x83, MRM5m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
547 "sub{q}\t{$src2, $dst|$dst, $src2}",
548 [(store (sub (load addr:$dst), i64immSExt8:$src2),
551 def SUB64mi32 : RIi32<0x81, MRM5m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
552 "sub{q}\t{$src2, $dst|$dst, $src2}",
553 [(store (sub (load addr:$dst), i64immSExt32:$src2),
557 let Uses = [EFLAGS] in {
558 let isTwoAddress = 1 in {
559 def SBB64rr : RI<0x19, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
560 "sbb{q}\t{$src2, $dst|$dst, $src2}",
561 [(set GR64:$dst, (sube GR64:$src1, GR64:$src2))]>;
563 def SBB64rm : RI<0x1B, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
564 "sbb{q}\t{$src2, $dst|$dst, $src2}",
565 [(set GR64:$dst, (sube GR64:$src1, (load addr:$src2)))]>;
567 def SBB64ri8 : RIi8<0x83, MRM3r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
568 "sbb{q}\t{$src2, $dst|$dst, $src2}",
569 [(set GR64:$dst, (sube GR64:$src1, i64immSExt8:$src2))]>;
570 def SBB64ri32 : RIi32<0x81, MRM3r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
571 "sbb{q}\t{$src2, $dst|$dst, $src2}",
572 [(set GR64:$dst, (sube GR64:$src1, i64immSExt32:$src2))]>;
575 def SBB64i32 : RI<0x1D, RawFrm, (outs), (ins i32imm:$src),
576 "sbb{q}\t{$src, %rax|%rax, $src}", []>;
578 def SBB64mr : RI<0x19, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
579 "sbb{q}\t{$src2, $dst|$dst, $src2}",
580 [(store (sube (load addr:$dst), GR64:$src2), addr:$dst)]>;
581 def SBB64mi8 : RIi8<0x83, MRM3m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
582 "sbb{q}\t{$src2, $dst|$dst, $src2}",
583 [(store (sube (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>;
584 def SBB64mi32 : RIi32<0x81, MRM3m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
585 "sbb{q}\t{$src2, $dst|$dst, $src2}",
586 [(store (sube (load addr:$dst), i64immSExt32:$src2), addr:$dst)]>;
590 // Unsigned multiplication
591 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], neverHasSideEffects = 1 in {
592 def MUL64r : RI<0xF7, MRM4r, (outs), (ins GR64:$src),
593 "mul{q}\t$src", []>; // RAX,RDX = RAX*GR64
595 def MUL64m : RI<0xF7, MRM4m, (outs), (ins i64mem:$src),
596 "mul{q}\t$src", []>; // RAX,RDX = RAX*[mem64]
598 // Signed multiplication
599 def IMUL64r : RI<0xF7, MRM5r, (outs), (ins GR64:$src),
600 "imul{q}\t$src", []>; // RAX,RDX = RAX*GR64
602 def IMUL64m : RI<0xF7, MRM5m, (outs), (ins i64mem:$src),
603 "imul{q}\t$src", []>; // RAX,RDX = RAX*[mem64]
606 let Defs = [EFLAGS] in {
607 let isTwoAddress = 1 in {
608 let isCommutable = 1 in
609 // Register-Register Signed Integer Multiplication
610 def IMUL64rr : RI<0xAF, MRMSrcReg, (outs GR64:$dst),
611 (ins GR64:$src1, GR64:$src2),
612 "imul{q}\t{$src2, $dst|$dst, $src2}",
613 [(set GR64:$dst, (mul GR64:$src1, GR64:$src2)),
614 (implicit EFLAGS)]>, TB;
616 // Register-Memory Signed Integer Multiplication
617 def IMUL64rm : RI<0xAF, MRMSrcMem, (outs GR64:$dst),
618 (ins GR64:$src1, i64mem:$src2),
619 "imul{q}\t{$src2, $dst|$dst, $src2}",
620 [(set GR64:$dst, (mul GR64:$src1, (load addr:$src2))),
621 (implicit EFLAGS)]>, TB;
624 // Suprisingly enough, these are not two address instructions!
626 // Register-Integer Signed Integer Multiplication
627 def IMUL64rri8 : RIi8<0x6B, MRMSrcReg, // GR64 = GR64*I8
628 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
629 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
630 [(set GR64:$dst, (mul GR64:$src1, i64immSExt8:$src2)),
632 def IMUL64rri32 : RIi32<0x69, MRMSrcReg, // GR64 = GR64*I32
633 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
634 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
635 [(set GR64:$dst, (mul GR64:$src1, i64immSExt32:$src2)),
638 // Memory-Integer Signed Integer Multiplication
639 def IMUL64rmi8 : RIi8<0x6B, MRMSrcMem, // GR64 = [mem64]*I8
640 (outs GR64:$dst), (ins i64mem:$src1, i64i8imm: $src2),
641 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
642 [(set GR64:$dst, (mul (load addr:$src1),
645 def IMUL64rmi32 : RIi32<0x69, MRMSrcMem, // GR64 = [mem64]*I32
646 (outs GR64:$dst), (ins i64mem:$src1, i64i32imm:$src2),
647 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
648 [(set GR64:$dst, (mul (load addr:$src1),
649 i64immSExt32:$src2)),
653 // Unsigned division / remainder
654 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in {
655 def DIV64r : RI<0xF7, MRM6r, (outs), (ins GR64:$src), // RDX:RAX/r64 = RAX,RDX
657 // Signed division / remainder
658 def IDIV64r: RI<0xF7, MRM7r, (outs), (ins GR64:$src), // RDX:RAX/r64 = RAX,RDX
659 "idiv{q}\t$src", []>;
661 def DIV64m : RI<0xF7, MRM6m, (outs), (ins i64mem:$src), // RDX:RAX/[mem64] = RAX,RDX
663 def IDIV64m: RI<0xF7, MRM7m, (outs), (ins i64mem:$src), // RDX:RAX/[mem64] = RAX,RDX
664 "idiv{q}\t$src", []>;
668 // Unary instructions
669 let Defs = [EFLAGS], CodeSize = 2 in {
670 let isTwoAddress = 1 in
671 def NEG64r : RI<0xF7, MRM3r, (outs GR64:$dst), (ins GR64:$src), "neg{q}\t$dst",
672 [(set GR64:$dst, (ineg GR64:$src)),
674 def NEG64m : RI<0xF7, MRM3m, (outs), (ins i64mem:$dst), "neg{q}\t$dst",
675 [(store (ineg (loadi64 addr:$dst)), addr:$dst),
678 let isTwoAddress = 1, isConvertibleToThreeAddress = 1 in
679 def INC64r : RI<0xFF, MRM0r, (outs GR64:$dst), (ins GR64:$src), "inc{q}\t$dst",
680 [(set GR64:$dst, (add GR64:$src, 1)),
682 def INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst), "inc{q}\t$dst",
683 [(store (add (loadi64 addr:$dst), 1), addr:$dst),
686 let isTwoAddress = 1, isConvertibleToThreeAddress = 1 in
687 def DEC64r : RI<0xFF, MRM1r, (outs GR64:$dst), (ins GR64:$src), "dec{q}\t$dst",
688 [(set GR64:$dst, (add GR64:$src, -1)),
690 def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst",
691 [(store (add (loadi64 addr:$dst), -1), addr:$dst),
694 // In 64-bit mode, single byte INC and DEC cannot be encoded.
695 let isTwoAddress = 1, isConvertibleToThreeAddress = 1 in {
696 // Can transform into LEA.
697 def INC64_16r : I<0xFF, MRM0r, (outs GR16:$dst), (ins GR16:$src), "inc{w}\t$dst",
698 [(set GR16:$dst, (add GR16:$src, 1)),
700 OpSize, Requires<[In64BitMode]>;
701 def INC64_32r : I<0xFF, MRM0r, (outs GR32:$dst), (ins GR32:$src), "inc{l}\t$dst",
702 [(set GR32:$dst, (add GR32:$src, 1)),
704 Requires<[In64BitMode]>;
705 def DEC64_16r : I<0xFF, MRM1r, (outs GR16:$dst), (ins GR16:$src), "dec{w}\t$dst",
706 [(set GR16:$dst, (add GR16:$src, -1)),
708 OpSize, Requires<[In64BitMode]>;
709 def DEC64_32r : I<0xFF, MRM1r, (outs GR32:$dst), (ins GR32:$src), "dec{l}\t$dst",
710 [(set GR32:$dst, (add GR32:$src, -1)),
712 Requires<[In64BitMode]>;
713 } // isConvertibleToThreeAddress
715 // These are duplicates of their 32-bit counterparts. Only needed so X86 knows
716 // how to unfold them.
717 let isTwoAddress = 0, CodeSize = 2 in {
718 def INC64_16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
719 [(store (add (loadi16 addr:$dst), 1), addr:$dst),
721 OpSize, Requires<[In64BitMode]>;
722 def INC64_32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
723 [(store (add (loadi32 addr:$dst), 1), addr:$dst),
725 Requires<[In64BitMode]>;
726 def DEC64_16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
727 [(store (add (loadi16 addr:$dst), -1), addr:$dst),
729 OpSize, Requires<[In64BitMode]>;
730 def DEC64_32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
731 [(store (add (loadi32 addr:$dst), -1), addr:$dst),
733 Requires<[In64BitMode]>;
735 } // Defs = [EFLAGS], CodeSize
738 let Defs = [EFLAGS] in {
739 // Shift instructions
740 let isTwoAddress = 1 in {
742 def SHL64rCL : RI<0xD3, MRM4r, (outs GR64:$dst), (ins GR64:$src),
743 "shl{q}\t{%cl, $dst|$dst, %CL}",
744 [(set GR64:$dst, (shl GR64:$src, CL))]>;
745 let isConvertibleToThreeAddress = 1 in // Can transform into LEA.
746 def SHL64ri : RIi8<0xC1, MRM4r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
747 "shl{q}\t{$src2, $dst|$dst, $src2}",
748 [(set GR64:$dst, (shl GR64:$src1, (i8 imm:$src2)))]>;
749 // NOTE: We don't use shifts of a register by one, because 'add reg,reg' is
754 def SHL64mCL : RI<0xD3, MRM4m, (outs), (ins i64mem:$dst),
755 "shl{q}\t{%cl, $dst|$dst, %CL}",
756 [(store (shl (loadi64 addr:$dst), CL), addr:$dst)]>;
757 def SHL64mi : RIi8<0xC1, MRM4m, (outs), (ins i64mem:$dst, i8imm:$src),
758 "shl{q}\t{$src, $dst|$dst, $src}",
759 [(store (shl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
760 def SHL64m1 : RI<0xD1, MRM4m, (outs), (ins i64mem:$dst),
762 [(store (shl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
764 let isTwoAddress = 1 in {
766 def SHR64rCL : RI<0xD3, MRM5r, (outs GR64:$dst), (ins GR64:$src),
767 "shr{q}\t{%cl, $dst|$dst, %CL}",
768 [(set GR64:$dst, (srl GR64:$src, CL))]>;
769 def SHR64ri : RIi8<0xC1, MRM5r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
770 "shr{q}\t{$src2, $dst|$dst, $src2}",
771 [(set GR64:$dst, (srl GR64:$src1, (i8 imm:$src2)))]>;
772 def SHR64r1 : RI<0xD1, MRM5r, (outs GR64:$dst), (ins GR64:$src1),
774 [(set GR64:$dst, (srl GR64:$src1, (i8 1)))]>;
778 def SHR64mCL : RI<0xD3, MRM5m, (outs), (ins i64mem:$dst),
779 "shr{q}\t{%cl, $dst|$dst, %CL}",
780 [(store (srl (loadi64 addr:$dst), CL), addr:$dst)]>;
781 def SHR64mi : RIi8<0xC1, MRM5m, (outs), (ins i64mem:$dst, i8imm:$src),
782 "shr{q}\t{$src, $dst|$dst, $src}",
783 [(store (srl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
784 def SHR64m1 : RI<0xD1, MRM5m, (outs), (ins i64mem:$dst),
786 [(store (srl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
788 let isTwoAddress = 1 in {
790 def SAR64rCL : RI<0xD3, MRM7r, (outs GR64:$dst), (ins GR64:$src),
791 "sar{q}\t{%cl, $dst|$dst, %CL}",
792 [(set GR64:$dst, (sra GR64:$src, CL))]>;
793 def SAR64ri : RIi8<0xC1, MRM7r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
794 "sar{q}\t{$src2, $dst|$dst, $src2}",
795 [(set GR64:$dst, (sra GR64:$src1, (i8 imm:$src2)))]>;
796 def SAR64r1 : RI<0xD1, MRM7r, (outs GR64:$dst), (ins GR64:$src1),
798 [(set GR64:$dst, (sra GR64:$src1, (i8 1)))]>;
802 def SAR64mCL : RI<0xD3, MRM7m, (outs), (ins i64mem:$dst),
803 "sar{q}\t{%cl, $dst|$dst, %CL}",
804 [(store (sra (loadi64 addr:$dst), CL), addr:$dst)]>;
805 def SAR64mi : RIi8<0xC1, MRM7m, (outs), (ins i64mem:$dst, i8imm:$src),
806 "sar{q}\t{$src, $dst|$dst, $src}",
807 [(store (sra (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
808 def SAR64m1 : RI<0xD1, MRM7m, (outs), (ins i64mem:$dst),
810 [(store (sra (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
812 // Rotate instructions
813 let isTwoAddress = 1 in {
815 def ROL64rCL : RI<0xD3, MRM0r, (outs GR64:$dst), (ins GR64:$src),
816 "rol{q}\t{%cl, $dst|$dst, %CL}",
817 [(set GR64:$dst, (rotl GR64:$src, CL))]>;
818 def ROL64ri : RIi8<0xC1, MRM0r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
819 "rol{q}\t{$src2, $dst|$dst, $src2}",
820 [(set GR64:$dst, (rotl GR64:$src1, (i8 imm:$src2)))]>;
821 def ROL64r1 : RI<0xD1, MRM0r, (outs GR64:$dst), (ins GR64:$src1),
823 [(set GR64:$dst, (rotl GR64:$src1, (i8 1)))]>;
827 def ROL64mCL : I<0xD3, MRM0m, (outs), (ins i64mem:$dst),
828 "rol{q}\t{%cl, $dst|$dst, %CL}",
829 [(store (rotl (loadi64 addr:$dst), CL), addr:$dst)]>;
830 def ROL64mi : RIi8<0xC1, MRM0m, (outs), (ins i64mem:$dst, i8imm:$src),
831 "rol{q}\t{$src, $dst|$dst, $src}",
832 [(store (rotl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
833 def ROL64m1 : RI<0xD1, MRM0m, (outs), (ins i64mem:$dst),
835 [(store (rotl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
837 let isTwoAddress = 1 in {
839 def ROR64rCL : RI<0xD3, MRM1r, (outs GR64:$dst), (ins GR64:$src),
840 "ror{q}\t{%cl, $dst|$dst, %CL}",
841 [(set GR64:$dst, (rotr GR64:$src, CL))]>;
842 def ROR64ri : RIi8<0xC1, MRM1r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
843 "ror{q}\t{$src2, $dst|$dst, $src2}",
844 [(set GR64:$dst, (rotr GR64:$src1, (i8 imm:$src2)))]>;
845 def ROR64r1 : RI<0xD1, MRM1r, (outs GR64:$dst), (ins GR64:$src1),
847 [(set GR64:$dst, (rotr GR64:$src1, (i8 1)))]>;
851 def ROR64mCL : RI<0xD3, MRM1m, (outs), (ins i64mem:$dst),
852 "ror{q}\t{%cl, $dst|$dst, %CL}",
853 [(store (rotr (loadi64 addr:$dst), CL), addr:$dst)]>;
854 def ROR64mi : RIi8<0xC1, MRM1m, (outs), (ins i64mem:$dst, i8imm:$src),
855 "ror{q}\t{$src, $dst|$dst, $src}",
856 [(store (rotr (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
857 def ROR64m1 : RI<0xD1, MRM1m, (outs), (ins i64mem:$dst),
859 [(store (rotr (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
861 // Double shift instructions (generalizations of rotate)
862 let isTwoAddress = 1 in {
864 def SHLD64rrCL : RI<0xA5, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
865 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
866 [(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2, CL))]>, TB;
867 def SHRD64rrCL : RI<0xAD, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
868 "shrd{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
869 [(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2, CL))]>, TB;
872 let isCommutable = 1 in { // FIXME: Update X86InstrInfo::commuteInstruction
873 def SHLD64rri8 : RIi8<0xA4, MRMDestReg,
874 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2, i8imm:$src3),
875 "shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
876 [(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2,
879 def SHRD64rri8 : RIi8<0xAC, MRMDestReg,
880 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2, i8imm:$src3),
881 "shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
882 [(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2,
889 def SHLD64mrCL : RI<0xA5, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
890 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
891 [(store (X86shld (loadi64 addr:$dst), GR64:$src2, CL),
893 def SHRD64mrCL : RI<0xAD, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
894 "shrd{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
895 [(store (X86shrd (loadi64 addr:$dst), GR64:$src2, CL),
898 def SHLD64mri8 : RIi8<0xA4, MRMDestMem,
899 (outs), (ins i64mem:$dst, GR64:$src2, i8imm:$src3),
900 "shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
901 [(store (X86shld (loadi64 addr:$dst), GR64:$src2,
902 (i8 imm:$src3)), addr:$dst)]>,
904 def SHRD64mri8 : RIi8<0xAC, MRMDestMem,
905 (outs), (ins i64mem:$dst, GR64:$src2, i8imm:$src3),
906 "shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
907 [(store (X86shrd (loadi64 addr:$dst), GR64:$src2,
908 (i8 imm:$src3)), addr:$dst)]>,
912 //===----------------------------------------------------------------------===//
913 // Logical Instructions...
916 let isTwoAddress = 1 , AddedComplexity = 15 in
917 def NOT64r : RI<0xF7, MRM2r, (outs GR64:$dst), (ins GR64:$src), "not{q}\t$dst",
918 [(set GR64:$dst, (not GR64:$src))]>;
919 def NOT64m : RI<0xF7, MRM2m, (outs), (ins i64mem:$dst), "not{q}\t$dst",
920 [(store (not (loadi64 addr:$dst)), addr:$dst)]>;
922 let Defs = [EFLAGS] in {
923 def AND64i32 : RI<0x25, RawFrm, (outs), (ins i32imm:$src),
924 "and{q}\t{$src, %rax|%rax, $src}", []>;
926 let isTwoAddress = 1 in {
927 let isCommutable = 1 in
928 def AND64rr : RI<0x21, MRMDestReg,
929 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
930 "and{q}\t{$src2, $dst|$dst, $src2}",
931 [(set GR64:$dst, (and GR64:$src1, GR64:$src2)),
933 def AND64rm : RI<0x23, MRMSrcMem,
934 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
935 "and{q}\t{$src2, $dst|$dst, $src2}",
936 [(set GR64:$dst, (and GR64:$src1, (load addr:$src2))),
938 def AND64ri8 : RIi8<0x83, MRM4r,
939 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
940 "and{q}\t{$src2, $dst|$dst, $src2}",
941 [(set GR64:$dst, (and GR64:$src1, i64immSExt8:$src2)),
943 def AND64ri32 : RIi32<0x81, MRM4r,
944 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
945 "and{q}\t{$src2, $dst|$dst, $src2}",
946 [(set GR64:$dst, (and GR64:$src1, i64immSExt32:$src2)),
950 def AND64mr : RI<0x21, MRMDestMem,
951 (outs), (ins i64mem:$dst, GR64:$src),
952 "and{q}\t{$src, $dst|$dst, $src}",
953 [(store (and (load addr:$dst), GR64:$src), addr:$dst),
955 def AND64mi8 : RIi8<0x83, MRM4m,
956 (outs), (ins i64mem:$dst, i64i8imm :$src),
957 "and{q}\t{$src, $dst|$dst, $src}",
958 [(store (and (load addr:$dst), i64immSExt8:$src), addr:$dst),
960 def AND64mi32 : RIi32<0x81, MRM4m,
961 (outs), (ins i64mem:$dst, i64i32imm:$src),
962 "and{q}\t{$src, $dst|$dst, $src}",
963 [(store (and (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst),
966 let isTwoAddress = 1 in {
967 let isCommutable = 1 in
968 def OR64rr : RI<0x09, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
969 "or{q}\t{$src2, $dst|$dst, $src2}",
970 [(set GR64:$dst, (or GR64:$src1, GR64:$src2)),
972 def OR64rm : RI<0x0B, MRMSrcMem , (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
973 "or{q}\t{$src2, $dst|$dst, $src2}",
974 [(set GR64:$dst, (or GR64:$src1, (load addr:$src2))),
976 def OR64ri8 : RIi8<0x83, MRM1r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
977 "or{q}\t{$src2, $dst|$dst, $src2}",
978 [(set GR64:$dst, (or GR64:$src1, i64immSExt8:$src2)),
980 def OR64ri32 : RIi32<0x81, MRM1r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
981 "or{q}\t{$src2, $dst|$dst, $src2}",
982 [(set GR64:$dst, (or GR64:$src1, i64immSExt32:$src2)),
986 def OR64mr : RI<0x09, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
987 "or{q}\t{$src, $dst|$dst, $src}",
988 [(store (or (load addr:$dst), GR64:$src), addr:$dst),
990 def OR64mi8 : RIi8<0x83, MRM1m, (outs), (ins i64mem:$dst, i64i8imm:$src),
991 "or{q}\t{$src, $dst|$dst, $src}",
992 [(store (or (load addr:$dst), i64immSExt8:$src), addr:$dst),
994 def OR64mi32 : RIi32<0x81, MRM1m, (outs), (ins i64mem:$dst, i64i32imm:$src),
995 "or{q}\t{$src, $dst|$dst, $src}",
996 [(store (or (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst),
999 def OR64i32 : RIi32<0x0D, RawFrm, (outs), (ins i32imm:$src),
1000 "or{q}\t{$src, %rax|%rax, $src}", []>;
1002 let isTwoAddress = 1 in {
1003 let isCommutable = 1 in
1004 def XOR64rr : RI<0x31, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1005 "xor{q}\t{$src2, $dst|$dst, $src2}",
1006 [(set GR64:$dst, (xor GR64:$src1, GR64:$src2)),
1007 (implicit EFLAGS)]>;
1008 def XOR64rm : RI<0x33, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1009 "xor{q}\t{$src2, $dst|$dst, $src2}",
1010 [(set GR64:$dst, (xor GR64:$src1, (load addr:$src2))),
1011 (implicit EFLAGS)]>;
1012 def XOR64ri8 : RIi8<0x83, MRM6r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
1013 "xor{q}\t{$src2, $dst|$dst, $src2}",
1014 [(set GR64:$dst, (xor GR64:$src1, i64immSExt8:$src2)),
1015 (implicit EFLAGS)]>;
1016 def XOR64ri32 : RIi32<0x81, MRM6r,
1017 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
1018 "xor{q}\t{$src2, $dst|$dst, $src2}",
1019 [(set GR64:$dst, (xor GR64:$src1, i64immSExt32:$src2)),
1020 (implicit EFLAGS)]>;
1023 def XOR64mr : RI<0x31, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1024 "xor{q}\t{$src, $dst|$dst, $src}",
1025 [(store (xor (load addr:$dst), GR64:$src), addr:$dst),
1026 (implicit EFLAGS)]>;
1027 def XOR64mi8 : RIi8<0x83, MRM6m, (outs), (ins i64mem:$dst, i64i8imm :$src),
1028 "xor{q}\t{$src, $dst|$dst, $src}",
1029 [(store (xor (load addr:$dst), i64immSExt8:$src), addr:$dst),
1030 (implicit EFLAGS)]>;
1031 def XOR64mi32 : RIi32<0x81, MRM6m, (outs), (ins i64mem:$dst, i64i32imm:$src),
1032 "xor{q}\t{$src, $dst|$dst, $src}",
1033 [(store (xor (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst),
1034 (implicit EFLAGS)]>;
1036 def XOR64i32 : RIi32<0x35, RawFrm, (outs), (ins i32imm:$src),
1037 "xor{q}\t{$src, %rax|%rax, $src}", []>;
1039 } // Defs = [EFLAGS]
1041 //===----------------------------------------------------------------------===//
1042 // Comparison Instructions...
1045 // Integer comparison
1046 let Defs = [EFLAGS] in {
1047 def TEST64i32 : RI<0xa9, RawFrm, (outs), (ins i32imm:$src),
1048 "test{q}\t{$src, %rax|%rax, $src}", []>;
1049 let isCommutable = 1 in
1050 def TEST64rr : RI<0x85, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1051 "test{q}\t{$src2, $src1|$src1, $src2}",
1052 [(X86cmp (and GR64:$src1, GR64:$src2), 0),
1053 (implicit EFLAGS)]>;
1054 def TEST64rm : RI<0x85, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2),
1055 "test{q}\t{$src2, $src1|$src1, $src2}",
1056 [(X86cmp (and GR64:$src1, (loadi64 addr:$src2)), 0),
1057 (implicit EFLAGS)]>;
1058 def TEST64ri32 : RIi32<0xF7, MRM0r, (outs),
1059 (ins GR64:$src1, i64i32imm:$src2),
1060 "test{q}\t{$src2, $src1|$src1, $src2}",
1061 [(X86cmp (and GR64:$src1, i64immSExt32:$src2), 0),
1062 (implicit EFLAGS)]>;
1063 def TEST64mi32 : RIi32<0xF7, MRM0m, (outs),
1064 (ins i64mem:$src1, i64i32imm:$src2),
1065 "test{q}\t{$src2, $src1|$src1, $src2}",
1066 [(X86cmp (and (loadi64 addr:$src1), i64immSExt32:$src2), 0),
1067 (implicit EFLAGS)]>;
1070 def CMP64i32 : RI<0x3D, RawFrm, (outs), (ins i32imm:$src),
1071 "cmp{q}\t{$src, %rax|%rax, $src}", []>;
1072 def CMP64rr : RI<0x39, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1073 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1074 [(X86cmp GR64:$src1, GR64:$src2),
1075 (implicit EFLAGS)]>;
1076 def CMP64mr : RI<0x39, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1077 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1078 [(X86cmp (loadi64 addr:$src1), GR64:$src2),
1079 (implicit EFLAGS)]>;
1080 def CMP64rm : RI<0x3B, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2),
1081 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1082 [(X86cmp GR64:$src1, (loadi64 addr:$src2)),
1083 (implicit EFLAGS)]>;
1084 def CMP64ri8 : RIi8<0x83, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1085 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1086 [(X86cmp GR64:$src1, i64immSExt8:$src2),
1087 (implicit EFLAGS)]>;
1088 def CMP64ri32 : RIi32<0x81, MRM7r, (outs), (ins GR64:$src1, i64i32imm:$src2),
1089 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1090 [(X86cmp GR64:$src1, i64immSExt32:$src2),
1091 (implicit EFLAGS)]>;
1092 def CMP64mi8 : RIi8<0x83, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1093 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1094 [(X86cmp (loadi64 addr:$src1), i64immSExt8:$src2),
1095 (implicit EFLAGS)]>;
1096 def CMP64mi32 : RIi32<0x81, MRM7m, (outs),
1097 (ins i64mem:$src1, i64i32imm:$src2),
1098 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1099 [(X86cmp (loadi64 addr:$src1), i64immSExt32:$src2),
1100 (implicit EFLAGS)]>;
1101 } // Defs = [EFLAGS]
1104 // TODO: BTC, BTR, and BTS
1105 let Defs = [EFLAGS] in {
1106 def BT64rr : RI<0xA3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1107 "bt{q}\t{$src2, $src1|$src1, $src2}",
1108 [(X86bt GR64:$src1, GR64:$src2),
1109 (implicit EFLAGS)]>, TB;
1111 // Unlike with the register+register form, the memory+register form of the
1112 // bt instruction does not ignore the high bits of the index. From ISel's
1113 // perspective, this is pretty bizarre. Disable these instructions for now.
1114 //def BT64mr : RI<0xA3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1115 // "bt{q}\t{$src2, $src1|$src1, $src2}",
1116 // [(X86bt (loadi64 addr:$src1), GR64:$src2),
1117 // (implicit EFLAGS)]>, TB;
1119 def BT64ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1120 "bt{q}\t{$src2, $src1|$src1, $src2}",
1121 [(X86bt GR64:$src1, i64immSExt8:$src2),
1122 (implicit EFLAGS)]>, TB;
1123 // Note that these instructions don't need FastBTMem because that
1124 // only applies when the other operand is in a register. When it's
1125 // an immediate, bt is still fast.
1126 def BT64mi8 : Ii8<0xBA, MRM4m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1127 "bt{q}\t{$src2, $src1|$src1, $src2}",
1128 [(X86bt (loadi64 addr:$src1), i64immSExt8:$src2),
1129 (implicit EFLAGS)]>, TB;
1130 } // Defs = [EFLAGS]
1132 // Conditional moves
1133 let Uses = [EFLAGS], isTwoAddress = 1 in {
1134 let isCommutable = 1 in {
1135 def CMOVB64rr : RI<0x42, MRMSrcReg, // if <u, GR64 = GR64
1136 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1137 "cmovb\t{$src2, $dst|$dst, $src2}",
1138 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1139 X86_COND_B, EFLAGS))]>, TB;
1140 def CMOVAE64rr: RI<0x43, MRMSrcReg, // if >=u, GR64 = GR64
1141 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1142 "cmovae\t{$src2, $dst|$dst, $src2}",
1143 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1144 X86_COND_AE, EFLAGS))]>, TB;
1145 def CMOVE64rr : RI<0x44, MRMSrcReg, // if ==, GR64 = GR64
1146 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1147 "cmove\t{$src2, $dst|$dst, $src2}",
1148 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1149 X86_COND_E, EFLAGS))]>, TB;
1150 def CMOVNE64rr: RI<0x45, MRMSrcReg, // if !=, GR64 = GR64
1151 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1152 "cmovne\t{$src2, $dst|$dst, $src2}",
1153 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1154 X86_COND_NE, EFLAGS))]>, TB;
1155 def CMOVBE64rr: RI<0x46, MRMSrcReg, // if <=u, GR64 = GR64
1156 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1157 "cmovbe\t{$src2, $dst|$dst, $src2}",
1158 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1159 X86_COND_BE, EFLAGS))]>, TB;
1160 def CMOVA64rr : RI<0x47, MRMSrcReg, // if >u, GR64 = GR64
1161 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1162 "cmova\t{$src2, $dst|$dst, $src2}",
1163 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1164 X86_COND_A, EFLAGS))]>, TB;
1165 def CMOVL64rr : RI<0x4C, MRMSrcReg, // if <s, GR64 = GR64
1166 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1167 "cmovl\t{$src2, $dst|$dst, $src2}",
1168 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1169 X86_COND_L, EFLAGS))]>, TB;
1170 def CMOVGE64rr: RI<0x4D, MRMSrcReg, // if >=s, GR64 = GR64
1171 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1172 "cmovge\t{$src2, $dst|$dst, $src2}",
1173 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1174 X86_COND_GE, EFLAGS))]>, TB;
1175 def CMOVLE64rr: RI<0x4E, MRMSrcReg, // if <=s, GR64 = GR64
1176 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1177 "cmovle\t{$src2, $dst|$dst, $src2}",
1178 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1179 X86_COND_LE, EFLAGS))]>, TB;
1180 def CMOVG64rr : RI<0x4F, MRMSrcReg, // if >s, GR64 = GR64
1181 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1182 "cmovg\t{$src2, $dst|$dst, $src2}",
1183 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1184 X86_COND_G, EFLAGS))]>, TB;
1185 def CMOVS64rr : RI<0x48, MRMSrcReg, // if signed, GR64 = GR64
1186 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1187 "cmovs\t{$src2, $dst|$dst, $src2}",
1188 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1189 X86_COND_S, EFLAGS))]>, TB;
1190 def CMOVNS64rr: RI<0x49, MRMSrcReg, // if !signed, GR64 = GR64
1191 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1192 "cmovns\t{$src2, $dst|$dst, $src2}",
1193 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1194 X86_COND_NS, EFLAGS))]>, TB;
1195 def CMOVP64rr : RI<0x4A, MRMSrcReg, // if parity, GR64 = GR64
1196 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1197 "cmovp\t{$src2, $dst|$dst, $src2}",
1198 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1199 X86_COND_P, EFLAGS))]>, TB;
1200 def CMOVNP64rr : RI<0x4B, MRMSrcReg, // if !parity, GR64 = GR64
1201 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1202 "cmovnp\t{$src2, $dst|$dst, $src2}",
1203 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1204 X86_COND_NP, EFLAGS))]>, TB;
1205 def CMOVO64rr : RI<0x40, MRMSrcReg, // if overflow, GR64 = GR64
1206 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1207 "cmovo\t{$src2, $dst|$dst, $src2}",
1208 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1209 X86_COND_O, EFLAGS))]>, TB;
1210 def CMOVNO64rr : RI<0x41, MRMSrcReg, // if !overflow, GR64 = GR64
1211 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1212 "cmovno\t{$src2, $dst|$dst, $src2}",
1213 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1214 X86_COND_NO, EFLAGS))]>, TB;
1215 } // isCommutable = 1
1217 def CMOVB64rm : RI<0x42, MRMSrcMem, // if <u, GR64 = [mem64]
1218 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1219 "cmovb\t{$src2, $dst|$dst, $src2}",
1220 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1221 X86_COND_B, EFLAGS))]>, TB;
1222 def CMOVAE64rm: RI<0x43, MRMSrcMem, // if >=u, GR64 = [mem64]
1223 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1224 "cmovae\t{$src2, $dst|$dst, $src2}",
1225 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1226 X86_COND_AE, EFLAGS))]>, TB;
1227 def CMOVE64rm : RI<0x44, MRMSrcMem, // if ==, GR64 = [mem64]
1228 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1229 "cmove\t{$src2, $dst|$dst, $src2}",
1230 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1231 X86_COND_E, EFLAGS))]>, TB;
1232 def CMOVNE64rm: RI<0x45, MRMSrcMem, // if !=, GR64 = [mem64]
1233 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1234 "cmovne\t{$src2, $dst|$dst, $src2}",
1235 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1236 X86_COND_NE, EFLAGS))]>, TB;
1237 def CMOVBE64rm: RI<0x46, MRMSrcMem, // if <=u, GR64 = [mem64]
1238 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1239 "cmovbe\t{$src2, $dst|$dst, $src2}",
1240 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1241 X86_COND_BE, EFLAGS))]>, TB;
1242 def CMOVA64rm : RI<0x47, MRMSrcMem, // if >u, GR64 = [mem64]
1243 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1244 "cmova\t{$src2, $dst|$dst, $src2}",
1245 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1246 X86_COND_A, EFLAGS))]>, TB;
1247 def CMOVL64rm : RI<0x4C, MRMSrcMem, // if <s, GR64 = [mem64]
1248 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1249 "cmovl\t{$src2, $dst|$dst, $src2}",
1250 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1251 X86_COND_L, EFLAGS))]>, TB;
1252 def CMOVGE64rm: RI<0x4D, MRMSrcMem, // if >=s, GR64 = [mem64]
1253 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1254 "cmovge\t{$src2, $dst|$dst, $src2}",
1255 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1256 X86_COND_GE, EFLAGS))]>, TB;
1257 def CMOVLE64rm: RI<0x4E, MRMSrcMem, // if <=s, GR64 = [mem64]
1258 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1259 "cmovle\t{$src2, $dst|$dst, $src2}",
1260 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1261 X86_COND_LE, EFLAGS))]>, TB;
1262 def CMOVG64rm : RI<0x4F, MRMSrcMem, // if >s, GR64 = [mem64]
1263 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1264 "cmovg\t{$src2, $dst|$dst, $src2}",
1265 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1266 X86_COND_G, EFLAGS))]>, TB;
1267 def CMOVS64rm : RI<0x48, MRMSrcMem, // if signed, GR64 = [mem64]
1268 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1269 "cmovs\t{$src2, $dst|$dst, $src2}",
1270 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1271 X86_COND_S, EFLAGS))]>, TB;
1272 def CMOVNS64rm: RI<0x49, MRMSrcMem, // if !signed, GR64 = [mem64]
1273 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1274 "cmovns\t{$src2, $dst|$dst, $src2}",
1275 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1276 X86_COND_NS, EFLAGS))]>, TB;
1277 def CMOVP64rm : RI<0x4A, MRMSrcMem, // if parity, GR64 = [mem64]
1278 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1279 "cmovp\t{$src2, $dst|$dst, $src2}",
1280 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1281 X86_COND_P, EFLAGS))]>, TB;
1282 def CMOVNP64rm : RI<0x4B, MRMSrcMem, // if !parity, GR64 = [mem64]
1283 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1284 "cmovnp\t{$src2, $dst|$dst, $src2}",
1285 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1286 X86_COND_NP, EFLAGS))]>, TB;
1287 def CMOVO64rm : RI<0x40, MRMSrcMem, // if overflow, GR64 = [mem64]
1288 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1289 "cmovo\t{$src2, $dst|$dst, $src2}",
1290 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1291 X86_COND_O, EFLAGS))]>, TB;
1292 def CMOVNO64rm : RI<0x41, MRMSrcMem, // if !overflow, GR64 = [mem64]
1293 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1294 "cmovno\t{$src2, $dst|$dst, $src2}",
1295 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1296 X86_COND_NO, EFLAGS))]>, TB;
1299 //===----------------------------------------------------------------------===//
1300 // Conversion Instructions...
1303 // f64 -> signed i64
1304 def Int_CVTSD2SI64rr: RSDI<0x2D, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1305 "cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1307 (int_x86_sse2_cvtsd2si64 VR128:$src))]>;
1308 def Int_CVTSD2SI64rm: RSDI<0x2D, MRMSrcMem, (outs GR64:$dst), (ins f128mem:$src),
1309 "cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1310 [(set GR64:$dst, (int_x86_sse2_cvtsd2si64
1311 (load addr:$src)))]>;
1312 def CVTTSD2SI64rr: RSDI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins FR64:$src),
1313 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1314 [(set GR64:$dst, (fp_to_sint FR64:$src))]>;
1315 def CVTTSD2SI64rm: RSDI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f64mem:$src),
1316 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1317 [(set GR64:$dst, (fp_to_sint (loadf64 addr:$src)))]>;
1318 def Int_CVTTSD2SI64rr: RSDI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1319 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1321 (int_x86_sse2_cvttsd2si64 VR128:$src))]>;
1322 def Int_CVTTSD2SI64rm: RSDI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f128mem:$src),
1323 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1325 (int_x86_sse2_cvttsd2si64
1326 (load addr:$src)))]>;
1328 // Signed i64 -> f64
1329 def CVTSI2SD64rr: RSDI<0x2A, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
1330 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
1331 [(set FR64:$dst, (sint_to_fp GR64:$src))]>;
1332 def CVTSI2SD64rm: RSDI<0x2A, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
1333 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
1334 [(set FR64:$dst, (sint_to_fp (loadi64 addr:$src)))]>;
1336 let isTwoAddress = 1 in {
1337 def Int_CVTSI2SD64rr: RSDI<0x2A, MRMSrcReg,
1338 (outs VR128:$dst), (ins VR128:$src1, GR64:$src2),
1339 "cvtsi2sd{q}\t{$src2, $dst|$dst, $src2}",
1341 (int_x86_sse2_cvtsi642sd VR128:$src1,
1343 def Int_CVTSI2SD64rm: RSDI<0x2A, MRMSrcMem,
1344 (outs VR128:$dst), (ins VR128:$src1, i64mem:$src2),
1345 "cvtsi2sd{q}\t{$src2, $dst|$dst, $src2}",
1347 (int_x86_sse2_cvtsi642sd VR128:$src1,
1348 (loadi64 addr:$src2)))]>;
1351 // Signed i64 -> f32
1352 def CVTSI2SS64rr: RSSI<0x2A, MRMSrcReg, (outs FR32:$dst), (ins GR64:$src),
1353 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
1354 [(set FR32:$dst, (sint_to_fp GR64:$src))]>;
1355 def CVTSI2SS64rm: RSSI<0x2A, MRMSrcMem, (outs FR32:$dst), (ins i64mem:$src),
1356 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
1357 [(set FR32:$dst, (sint_to_fp (loadi64 addr:$src)))]>;
1359 let isTwoAddress = 1 in {
1360 def Int_CVTSI2SS64rr : RSSI<0x2A, MRMSrcReg,
1361 (outs VR128:$dst), (ins VR128:$src1, GR64:$src2),
1362 "cvtsi2ss{q}\t{$src2, $dst|$dst, $src2}",
1364 (int_x86_sse_cvtsi642ss VR128:$src1,
1366 def Int_CVTSI2SS64rm : RSSI<0x2A, MRMSrcMem,
1367 (outs VR128:$dst), (ins VR128:$src1, i64mem:$src2),
1368 "cvtsi2ss{q}\t{$src2, $dst|$dst, $src2}",
1370 (int_x86_sse_cvtsi642ss VR128:$src1,
1371 (loadi64 addr:$src2)))]>;
1374 // f32 -> signed i64
1375 def Int_CVTSS2SI64rr: RSSI<0x2D, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1376 "cvtss2si{q}\t{$src, $dst|$dst, $src}",
1378 (int_x86_sse_cvtss2si64 VR128:$src))]>;
1379 def Int_CVTSS2SI64rm: RSSI<0x2D, MRMSrcMem, (outs GR64:$dst), (ins f32mem:$src),
1380 "cvtss2si{q}\t{$src, $dst|$dst, $src}",
1381 [(set GR64:$dst, (int_x86_sse_cvtss2si64
1382 (load addr:$src)))]>;
1383 def CVTTSS2SI64rr: RSSI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins FR32:$src),
1384 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1385 [(set GR64:$dst, (fp_to_sint FR32:$src))]>;
1386 def CVTTSS2SI64rm: RSSI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f32mem:$src),
1387 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1388 [(set GR64:$dst, (fp_to_sint (loadf32 addr:$src)))]>;
1389 def Int_CVTTSS2SI64rr: RSSI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1390 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1392 (int_x86_sse_cvttss2si64 VR128:$src))]>;
1393 def Int_CVTTSS2SI64rm: RSSI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f32mem:$src),
1394 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1396 (int_x86_sse_cvttss2si64 (load addr:$src)))]>;
1398 //===----------------------------------------------------------------------===//
1399 // Alias Instructions
1400 //===----------------------------------------------------------------------===//
1402 // Alias instructions that map movr0 to xor. Use xorl instead of xorq; it's
1403 // equivalent due to implicit zero-extending, and it sometimes has a smaller
1405 // FIXME: AddedComplexity gives this a higher priority than MOV64ri32. Remove
1406 // when we have a better way to specify isel priority.
1407 let AddedComplexity = 1 in
1409 (SUBREG_TO_REG (i64 0), (MOV32r0), x86_subreg_32bit)>;
1412 // Materialize i64 constant where top 32-bits are zero.
1413 let AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1 in
1414 def MOV64ri64i32 : Ii32<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64i32imm:$src),
1415 "mov{l}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
1416 [(set GR64:$dst, i64immZExt32:$src)]>;
1418 //===----------------------------------------------------------------------===//
1419 // Thread Local Storage Instructions
1420 //===----------------------------------------------------------------------===//
1422 // All calls clobber the non-callee saved registers. RSP is marked as
1423 // a use to prevent stack-pointer assignments that appear immediately
1424 // before calls from potentially appearing dead.
1425 let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
1426 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
1427 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
1428 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
1429 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
1431 def TLS_addr64 : I<0, Pseudo, (outs), (ins lea64mem:$sym),
1433 "leaq\t$sym(%rip), %rdi; "
1436 "call\t__tls_get_addr@PLT",
1437 [(X86tlsaddr tls64addr:$sym)]>,
1438 Requires<[In64BitMode]>;
1440 let AddedComplexity = 5, isCodeGenOnly = 1 in
1441 def MOV64GSrm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1442 "movq\t%gs:$src, $dst",
1443 [(set GR64:$dst, (gsload addr:$src))]>, SegGS;
1445 let AddedComplexity = 5, isCodeGenOnly = 1 in
1446 def MOV64FSrm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1447 "movq\t%fs:$src, $dst",
1448 [(set GR64:$dst, (fsload addr:$src))]>, SegFS;
1450 //===----------------------------------------------------------------------===//
1451 // Atomic Instructions
1452 //===----------------------------------------------------------------------===//
1454 let Defs = [RAX, EFLAGS], Uses = [RAX] in {
1455 def LCMPXCHG64 : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$ptr, GR64:$swap),
1457 "cmpxchgq\t$swap,$ptr",
1458 [(X86cas addr:$ptr, GR64:$swap, 8)]>, TB, LOCK;
1461 let Constraints = "$val = $dst" in {
1462 let Defs = [EFLAGS] in
1463 def LXADD64 : RI<0xC1, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$ptr,GR64:$val),
1466 [(set GR64:$dst, (atomic_load_add_64 addr:$ptr, GR64:$val))]>,
1469 def XCHG64rm : RI<0x87, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$ptr,GR64:$val),
1471 [(set GR64:$dst, (atomic_swap_64 addr:$ptr, GR64:$val))]>;
1474 // Optimized codegen when the non-memory output is not used.
1475 // FIXME: Use normal add / sub instructions and add lock prefix dynamically.
1476 def LOCK_ADD64mr : RI<0x03, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
1478 "add{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1479 def LOCK_ADD64mi8 : RIi8<0x83, MRM0m, (outs),
1480 (ins i64mem:$dst, i64i8imm :$src2),
1482 "add{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1483 def LOCK_ADD64mi32 : RIi32<0x81, MRM0m, (outs),
1484 (ins i64mem:$dst, i64i32imm :$src2),
1486 "add{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1487 def LOCK_SUB64mr : RI<0x29, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
1489 "sub{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1490 def LOCK_SUB64mi8 : RIi8<0x83, MRM5m, (outs),
1491 (ins i64mem:$dst, i64i8imm :$src2),
1493 "sub{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1494 def LOCK_SUB64mi32 : RIi32<0x81, MRM5m, (outs),
1495 (ins i64mem:$dst, i64i32imm:$src2),
1497 "sub{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1498 def LOCK_INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst),
1500 "inc{q}\t$dst", []>, LOCK;
1501 def LOCK_DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst),
1503 "dec{q}\t$dst", []>, LOCK;
1505 // Atomic exchange, and, or, xor
1506 let Constraints = "$val = $dst", Defs = [EFLAGS],
1507 usesCustomDAGSchedInserter = 1 in {
1508 def ATOMAND64 : I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1509 "#ATOMAND64 PSEUDO!",
1510 [(set GR64:$dst, (atomic_load_and_64 addr:$ptr, GR64:$val))]>;
1511 def ATOMOR64 : I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1512 "#ATOMOR64 PSEUDO!",
1513 [(set GR64:$dst, (atomic_load_or_64 addr:$ptr, GR64:$val))]>;
1514 def ATOMXOR64 : I<0, Pseudo,(outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1515 "#ATOMXOR64 PSEUDO!",
1516 [(set GR64:$dst, (atomic_load_xor_64 addr:$ptr, GR64:$val))]>;
1517 def ATOMNAND64 : I<0, Pseudo,(outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1518 "#ATOMNAND64 PSEUDO!",
1519 [(set GR64:$dst, (atomic_load_nand_64 addr:$ptr, GR64:$val))]>;
1520 def ATOMMIN64: I<0, Pseudo, (outs GR64:$dst), (ins i64mem:$ptr, GR64:$val),
1521 "#ATOMMIN64 PSEUDO!",
1522 [(set GR64:$dst, (atomic_load_min_64 addr:$ptr, GR64:$val))]>;
1523 def ATOMMAX64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1524 "#ATOMMAX64 PSEUDO!",
1525 [(set GR64:$dst, (atomic_load_max_64 addr:$ptr, GR64:$val))]>;
1526 def ATOMUMIN64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1527 "#ATOMUMIN64 PSEUDO!",
1528 [(set GR64:$dst, (atomic_load_umin_64 addr:$ptr, GR64:$val))]>;
1529 def ATOMUMAX64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1530 "#ATOMUMAX64 PSEUDO!",
1531 [(set GR64:$dst, (atomic_load_umax_64 addr:$ptr, GR64:$val))]>;
1534 //===----------------------------------------------------------------------===//
1535 // Non-Instruction Patterns
1536 //===----------------------------------------------------------------------===//
1538 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable when not in small
1539 // code model mode, should use 'movabs'. FIXME: This is really a hack, the
1540 // 'movabs' predicate should handle this sort of thing.
1541 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
1542 (MOV64ri tconstpool :$dst)>, Requires<[FarData]>;
1543 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
1544 (MOV64ri tjumptable :$dst)>, Requires<[FarData]>;
1545 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
1546 (MOV64ri tglobaladdr :$dst)>, Requires<[FarData]>;
1547 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
1548 (MOV64ri texternalsym:$dst)>, Requires<[FarData]>;
1550 // In static codegen with small code model, we can get the address of a label
1551 // into a register with 'movl'. FIXME: This is a hack, the 'imm' predicate of
1552 // the MOV64ri64i32 should accept these.
1553 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
1554 (MOV64ri64i32 tconstpool :$dst)>, Requires<[SmallCode]>;
1555 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
1556 (MOV64ri64i32 tjumptable :$dst)>, Requires<[SmallCode]>;
1557 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
1558 (MOV64ri64i32 tglobaladdr :$dst)>, Requires<[SmallCode]>;
1559 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
1560 (MOV64ri64i32 texternalsym:$dst)>, Requires<[SmallCode]>;
1562 // In kernel code model, we can get the address of a label
1563 // into a register with 'movq'. FIXME: This is a hack, the 'imm' predicate of
1564 // the MOV64ri32 should accept these.
1565 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
1566 (MOV64ri32 tconstpool :$dst)>, Requires<[KernelCode]>;
1567 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
1568 (MOV64ri32 tjumptable :$dst)>, Requires<[KernelCode]>;
1569 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
1570 (MOV64ri32 tglobaladdr :$dst)>, Requires<[KernelCode]>;
1571 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
1572 (MOV64ri32 texternalsym:$dst)>, Requires<[KernelCode]>;
1574 // If we have small model and -static mode, it is safe to store global addresses
1575 // directly as immediates. FIXME: This is really a hack, the 'imm' predicate
1576 // for MOV64mi32 should handle this sort of thing.
1577 def : Pat<(store (i64 (X86Wrapper tconstpool:$src)), addr:$dst),
1578 (MOV64mi32 addr:$dst, tconstpool:$src)>,
1579 Requires<[NearData, IsStatic]>;
1580 def : Pat<(store (i64 (X86Wrapper tjumptable:$src)), addr:$dst),
1581 (MOV64mi32 addr:$dst, tjumptable:$src)>,
1582 Requires<[NearData, IsStatic]>;
1583 def : Pat<(store (i64 (X86Wrapper tglobaladdr:$src)), addr:$dst),
1584 (MOV64mi32 addr:$dst, tglobaladdr:$src)>,
1585 Requires<[NearData, IsStatic]>;
1586 def : Pat<(store (i64 (X86Wrapper texternalsym:$src)), addr:$dst),
1587 (MOV64mi32 addr:$dst, texternalsym:$src)>,
1588 Requires<[NearData, IsStatic]>;
1591 // Direct PC relative function call for small code model. 32-bit displacement
1592 // sign extended to 64-bit.
1593 def : Pat<(X86call (i64 tglobaladdr:$dst)),
1594 (CALL64pcrel32 tglobaladdr:$dst)>, Requires<[NotWin64]>;
1595 def : Pat<(X86call (i64 texternalsym:$dst)),
1596 (CALL64pcrel32 texternalsym:$dst)>, Requires<[NotWin64]>;
1598 def : Pat<(X86call (i64 tglobaladdr:$dst)),
1599 (WINCALL64pcrel32 tglobaladdr:$dst)>, Requires<[IsWin64]>;
1600 def : Pat<(X86call (i64 texternalsym:$dst)),
1601 (WINCALL64pcrel32 texternalsym:$dst)>, Requires<[IsWin64]>;
1604 def : Pat<(X86tcret GR64:$dst, imm:$off),
1605 (TCRETURNri64 GR64:$dst, imm:$off)>;
1607 def : Pat<(X86tcret (i64 tglobaladdr:$dst), imm:$off),
1608 (TCRETURNdi64 texternalsym:$dst, imm:$off)>;
1610 def : Pat<(X86tcret (i64 texternalsym:$dst), imm:$off),
1611 (TCRETURNdi64 texternalsym:$dst, imm:$off)>;
1615 // TEST R,R is smaller than CMP R,0
1616 def : Pat<(parallel (X86cmp GR64:$src1, 0), (implicit EFLAGS)),
1617 (TEST64rr GR64:$src1, GR64:$src1)>;
1619 // Conditional moves with folded loads with operands swapped and conditions
1621 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_B, EFLAGS),
1622 (CMOVAE64rm GR64:$src2, addr:$src1)>;
1623 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_AE, EFLAGS),
1624 (CMOVB64rm GR64:$src2, addr:$src1)>;
1625 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_E, EFLAGS),
1626 (CMOVNE64rm GR64:$src2, addr:$src1)>;
1627 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NE, EFLAGS),
1628 (CMOVE64rm GR64:$src2, addr:$src1)>;
1629 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_BE, EFLAGS),
1630 (CMOVA64rm GR64:$src2, addr:$src1)>;
1631 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_A, EFLAGS),
1632 (CMOVBE64rm GR64:$src2, addr:$src1)>;
1633 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_L, EFLAGS),
1634 (CMOVGE64rm GR64:$src2, addr:$src1)>;
1635 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_GE, EFLAGS),
1636 (CMOVL64rm GR64:$src2, addr:$src1)>;
1637 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_LE, EFLAGS),
1638 (CMOVG64rm GR64:$src2, addr:$src1)>;
1639 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_G, EFLAGS),
1640 (CMOVLE64rm GR64:$src2, addr:$src1)>;
1641 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_P, EFLAGS),
1642 (CMOVNP64rm GR64:$src2, addr:$src1)>;
1643 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NP, EFLAGS),
1644 (CMOVP64rm GR64:$src2, addr:$src1)>;
1645 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_S, EFLAGS),
1646 (CMOVNS64rm GR64:$src2, addr:$src1)>;
1647 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NS, EFLAGS),
1648 (CMOVS64rm GR64:$src2, addr:$src1)>;
1649 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_O, EFLAGS),
1650 (CMOVNO64rm GR64:$src2, addr:$src1)>;
1651 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NO, EFLAGS),
1652 (CMOVO64rm GR64:$src2, addr:$src1)>;
1654 // zextload bool -> zextload byte
1655 def : Pat<(zextloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>;
1658 // When extloading from 16-bit and smaller memory locations into 64-bit registers,
1659 // use zero-extending loads so that the entire 64-bit register is defined, avoiding
1660 // partial-register updates.
1661 def : Pat<(extloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>;
1662 def : Pat<(extloadi64i8 addr:$src), (MOVZX64rm8 addr:$src)>;
1663 def : Pat<(extloadi64i16 addr:$src), (MOVZX64rm16 addr:$src)>;
1664 // For other extloads, use subregs, since the high contents of the register are
1665 // defined after an extload.
1666 def : Pat<(extloadi64i32 addr:$src),
1667 (SUBREG_TO_REG (i64 0), (MOV32rm addr:$src),
1670 // anyext. Define these to do an explicit zero-extend to
1671 // avoid partial-register updates.
1672 def : Pat<(i64 (anyext GR8 :$src)), (MOVZX64rr8 GR8 :$src)>;
1673 def : Pat<(i64 (anyext GR16:$src)), (MOVZX64rr16 GR16 :$src)>;
1674 def : Pat<(i64 (anyext GR32:$src)),
1675 (SUBREG_TO_REG (i64 0), GR32:$src, x86_subreg_32bit)>;
1677 //===----------------------------------------------------------------------===//
1679 //===----------------------------------------------------------------------===//
1681 // Odd encoding trick: -128 fits into an 8-bit immediate field while
1682 // +128 doesn't, so in this special case use a sub instead of an add.
1683 def : Pat<(add GR64:$src1, 128),
1684 (SUB64ri8 GR64:$src1, -128)>;
1685 def : Pat<(store (add (loadi64 addr:$dst), 128), addr:$dst),
1686 (SUB64mi8 addr:$dst, -128)>;
1688 // The same trick applies for 32-bit immediate fields in 64-bit
1690 def : Pat<(add GR64:$src1, 0x0000000080000000),
1691 (SUB64ri32 GR64:$src1, 0xffffffff80000000)>;
1692 def : Pat<(store (add (loadi64 addr:$dst), 0x00000000800000000), addr:$dst),
1693 (SUB64mi32 addr:$dst, 0xffffffff80000000)>;
1695 // r & (2^32-1) ==> movz
1696 def : Pat<(and GR64:$src, 0x00000000FFFFFFFF),
1697 (MOVZX64rr32 (EXTRACT_SUBREG GR64:$src, x86_subreg_32bit))>;
1698 // r & (2^16-1) ==> movz
1699 def : Pat<(and GR64:$src, 0xffff),
1700 (MOVZX64rr16 (i16 (EXTRACT_SUBREG GR64:$src, x86_subreg_16bit)))>;
1701 // r & (2^8-1) ==> movz
1702 def : Pat<(and GR64:$src, 0xff),
1703 (MOVZX64rr8 (i8 (EXTRACT_SUBREG GR64:$src, x86_subreg_8bit)))>;
1704 // r & (2^8-1) ==> movz
1705 def : Pat<(and GR32:$src1, 0xff),
1706 (MOVZX32rr8 (EXTRACT_SUBREG GR32:$src1, x86_subreg_8bit))>,
1707 Requires<[In64BitMode]>;
1708 // r & (2^8-1) ==> movz
1709 def : Pat<(and GR16:$src1, 0xff),
1710 (MOVZX16rr8 (i8 (EXTRACT_SUBREG GR16:$src1, x86_subreg_8bit)))>,
1711 Requires<[In64BitMode]>;
1713 // sext_inreg patterns
1714 def : Pat<(sext_inreg GR64:$src, i32),
1715 (MOVSX64rr32 (EXTRACT_SUBREG GR64:$src, x86_subreg_32bit))>;
1716 def : Pat<(sext_inreg GR64:$src, i16),
1717 (MOVSX64rr16 (EXTRACT_SUBREG GR64:$src, x86_subreg_16bit))>;
1718 def : Pat<(sext_inreg GR64:$src, i8),
1719 (MOVSX64rr8 (EXTRACT_SUBREG GR64:$src, x86_subreg_8bit))>;
1720 def : Pat<(sext_inreg GR32:$src, i8),
1721 (MOVSX32rr8 (EXTRACT_SUBREG GR32:$src, x86_subreg_8bit))>,
1722 Requires<[In64BitMode]>;
1723 def : Pat<(sext_inreg GR16:$src, i8),
1724 (MOVSX16rr8 (i8 (EXTRACT_SUBREG GR16:$src, x86_subreg_8bit)))>,
1725 Requires<[In64BitMode]>;
1728 def : Pat<(i32 (trunc GR64:$src)),
1729 (EXTRACT_SUBREG GR64:$src, x86_subreg_32bit)>;
1730 def : Pat<(i16 (trunc GR64:$src)),
1731 (EXTRACT_SUBREG GR64:$src, x86_subreg_16bit)>;
1732 def : Pat<(i8 (trunc GR64:$src)),
1733 (EXTRACT_SUBREG GR64:$src, x86_subreg_8bit)>;
1734 def : Pat<(i8 (trunc GR32:$src)),
1735 (EXTRACT_SUBREG GR32:$src, x86_subreg_8bit)>,
1736 Requires<[In64BitMode]>;
1737 def : Pat<(i8 (trunc GR16:$src)),
1738 (EXTRACT_SUBREG GR16:$src, x86_subreg_8bit)>,
1739 Requires<[In64BitMode]>;
1741 // h-register tricks.
1742 // For now, be conservative on x86-64 and use an h-register extract only if the
1743 // value is immediately zero-extended or stored, which are somewhat common
1744 // cases. This uses a bunch of code to prevent a register requiring a REX prefix
1745 // from being allocated in the same instruction as the h register, as there's
1746 // currently no way to describe this requirement to the register allocator.
1748 // h-register extract and zero-extend.
1749 def : Pat<(and (srl_su GR64:$src, (i8 8)), (i64 255)),
1753 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR64:$src, GR64_ABCD),
1754 x86_subreg_8bit_hi)),
1756 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
1758 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_ABCD),
1759 x86_subreg_8bit_hi))>,
1760 Requires<[In64BitMode]>;
1761 def : Pat<(srl_su GR16:$src, (i8 8)),
1764 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
1765 x86_subreg_8bit_hi)),
1767 Requires<[In64BitMode]>;
1768 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
1770 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
1771 x86_subreg_8bit_hi))>,
1772 Requires<[In64BitMode]>;
1773 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
1775 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
1776 x86_subreg_8bit_hi))>,
1777 Requires<[In64BitMode]>;
1778 def : Pat<(i64 (zext (srl_su GR16:$src, (i8 8)))),
1782 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
1783 x86_subreg_8bit_hi)),
1785 def : Pat<(i64 (anyext (srl_su GR16:$src, (i8 8)))),
1789 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
1790 x86_subreg_8bit_hi)),
1793 // h-register extract and store.
1794 def : Pat<(store (i8 (trunc_su (srl_su GR64:$src, (i8 8)))), addr:$dst),
1797 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR64:$src, GR64_ABCD),
1798 x86_subreg_8bit_hi))>;
1799 def : Pat<(store (i8 (trunc_su (srl_su GR32:$src, (i8 8)))), addr:$dst),
1802 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_ABCD),
1803 x86_subreg_8bit_hi))>,
1804 Requires<[In64BitMode]>;
1805 def : Pat<(store (i8 (trunc_su (srl_su GR16:$src, (i8 8)))), addr:$dst),
1808 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
1809 x86_subreg_8bit_hi))>,
1810 Requires<[In64BitMode]>;
1812 // (shl x, 1) ==> (add x, x)
1813 def : Pat<(shl GR64:$src1, (i8 1)), (ADD64rr GR64:$src1, GR64:$src1)>;
1815 // (shl x (and y, 63)) ==> (shl x, y)
1816 def : Pat<(shl GR64:$src1, (and CL:$amt, 63)),
1817 (SHL64rCL GR64:$src1)>;
1818 def : Pat<(store (shl (loadi64 addr:$dst), (and CL:$amt, 63)), addr:$dst),
1819 (SHL64mCL addr:$dst)>;
1821 def : Pat<(srl GR64:$src1, (and CL:$amt, 63)),
1822 (SHR64rCL GR64:$src1)>;
1823 def : Pat<(store (srl (loadi64 addr:$dst), (and CL:$amt, 63)), addr:$dst),
1824 (SHR64mCL addr:$dst)>;
1826 def : Pat<(sra GR64:$src1, (and CL:$amt, 63)),
1827 (SAR64rCL GR64:$src1)>;
1828 def : Pat<(store (sra (loadi64 addr:$dst), (and CL:$amt, 63)), addr:$dst),
1829 (SAR64mCL addr:$dst)>;
1831 // (or (x >> c) | (y << (64 - c))) ==> (shrd64 x, y, c)
1832 def : Pat<(or (srl GR64:$src1, CL:$amt),
1833 (shl GR64:$src2, (sub 64, CL:$amt))),
1834 (SHRD64rrCL GR64:$src1, GR64:$src2)>;
1836 def : Pat<(store (or (srl (loadi64 addr:$dst), CL:$amt),
1837 (shl GR64:$src2, (sub 64, CL:$amt))), addr:$dst),
1838 (SHRD64mrCL addr:$dst, GR64:$src2)>;
1840 def : Pat<(or (srl GR64:$src1, (i8 (trunc RCX:$amt))),
1841 (shl GR64:$src2, (i8 (trunc (sub 64, RCX:$amt))))),
1842 (SHRD64rrCL GR64:$src1, GR64:$src2)>;
1844 def : Pat<(store (or (srl (loadi64 addr:$dst), (i8 (trunc RCX:$amt))),
1845 (shl GR64:$src2, (i8 (trunc (sub 64, RCX:$amt))))),
1847 (SHRD64mrCL addr:$dst, GR64:$src2)>;
1849 def : Pat<(shrd GR64:$src1, (i8 imm:$amt1), GR64:$src2, (i8 imm:$amt2)),
1850 (SHRD64rri8 GR64:$src1, GR64:$src2, (i8 imm:$amt1))>;
1852 def : Pat<(store (shrd (loadi64 addr:$dst), (i8 imm:$amt1),
1853 GR64:$src2, (i8 imm:$amt2)), addr:$dst),
1854 (SHRD64mri8 addr:$dst, GR64:$src2, (i8 imm:$amt1))>;
1856 // (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
1857 def : Pat<(or (shl GR64:$src1, CL:$amt),
1858 (srl GR64:$src2, (sub 64, CL:$amt))),
1859 (SHLD64rrCL GR64:$src1, GR64:$src2)>;
1861 def : Pat<(store (or (shl (loadi64 addr:$dst), CL:$amt),
1862 (srl GR64:$src2, (sub 64, CL:$amt))), addr:$dst),
1863 (SHLD64mrCL addr:$dst, GR64:$src2)>;
1865 def : Pat<(or (shl GR64:$src1, (i8 (trunc RCX:$amt))),
1866 (srl GR64:$src2, (i8 (trunc (sub 64, RCX:$amt))))),
1867 (SHLD64rrCL GR64:$src1, GR64:$src2)>;
1869 def : Pat<(store (or (shl (loadi64 addr:$dst), (i8 (trunc RCX:$amt))),
1870 (srl GR64:$src2, (i8 (trunc (sub 64, RCX:$amt))))),
1872 (SHLD64mrCL addr:$dst, GR64:$src2)>;
1874 def : Pat<(shld GR64:$src1, (i8 imm:$amt1), GR64:$src2, (i8 imm:$amt2)),
1875 (SHLD64rri8 GR64:$src1, GR64:$src2, (i8 imm:$amt1))>;
1877 def : Pat<(store (shld (loadi64 addr:$dst), (i8 imm:$amt1),
1878 GR64:$src2, (i8 imm:$amt2)), addr:$dst),
1879 (SHLD64mri8 addr:$dst, GR64:$src2, (i8 imm:$amt1))>;
1881 // X86 specific add which produces a flag.
1882 def : Pat<(addc GR64:$src1, GR64:$src2),
1883 (ADD64rr GR64:$src1, GR64:$src2)>;
1884 def : Pat<(addc GR64:$src1, (load addr:$src2)),
1885 (ADD64rm GR64:$src1, addr:$src2)>;
1886 def : Pat<(addc GR64:$src1, i64immSExt8:$src2),
1887 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
1888 def : Pat<(addc GR64:$src1, i64immSExt32:$src2),
1889 (ADD64ri32 GR64:$src1, imm:$src2)>;
1891 def : Pat<(subc GR64:$src1, GR64:$src2),
1892 (SUB64rr GR64:$src1, GR64:$src2)>;
1893 def : Pat<(subc GR64:$src1, (load addr:$src2)),
1894 (SUB64rm GR64:$src1, addr:$src2)>;
1895 def : Pat<(subc GR64:$src1, i64immSExt8:$src2),
1896 (SUB64ri8 GR64:$src1, i64immSExt8:$src2)>;
1897 def : Pat<(subc GR64:$src1, imm:$src2),
1898 (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>;
1900 //===----------------------------------------------------------------------===//
1901 // EFLAGS-defining Patterns
1902 //===----------------------------------------------------------------------===//
1904 // Register-Register Addition with EFLAGS result
1905 def : Pat<(parallel (X86add_flag GR64:$src1, GR64:$src2),
1907 (ADD64rr GR64:$src1, GR64:$src2)>;
1909 // Register-Integer Addition with EFLAGS result
1910 def : Pat<(parallel (X86add_flag GR64:$src1, i64immSExt8:$src2),
1912 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
1913 def : Pat<(parallel (X86add_flag GR64:$src1, i64immSExt32:$src2),
1915 (ADD64ri32 GR64:$src1, i64immSExt32:$src2)>;
1917 // Register-Memory Addition with EFLAGS result
1918 def : Pat<(parallel (X86add_flag GR64:$src1, (loadi64 addr:$src2)),
1920 (ADD64rm GR64:$src1, addr:$src2)>;
1922 // Memory-Register Addition with EFLAGS result
1923 def : Pat<(parallel (store (X86add_flag (loadi64 addr:$dst), GR64:$src2),
1926 (ADD64mr addr:$dst, GR64:$src2)>;
1927 def : Pat<(parallel (store (X86add_flag (loadi64 addr:$dst), i64immSExt8:$src2),
1930 (ADD64mi8 addr:$dst, i64immSExt8:$src2)>;
1931 def : Pat<(parallel (store (X86add_flag (loadi64 addr:$dst), i64immSExt32:$src2),
1934 (ADD64mi32 addr:$dst, i64immSExt32:$src2)>;
1936 // Register-Register Subtraction with EFLAGS result
1937 def : Pat<(parallel (X86sub_flag GR64:$src1, GR64:$src2),
1939 (SUB64rr GR64:$src1, GR64:$src2)>;
1941 // Register-Memory Subtraction with EFLAGS result
1942 def : Pat<(parallel (X86sub_flag GR64:$src1, (loadi64 addr:$src2)),
1944 (SUB64rm GR64:$src1, addr:$src2)>;
1946 // Register-Integer Subtraction with EFLAGS result
1947 def : Pat<(parallel (X86sub_flag GR64:$src1, i64immSExt8:$src2),
1949 (SUB64ri8 GR64:$src1, i64immSExt8:$src2)>;
1950 def : Pat<(parallel (X86sub_flag GR64:$src1, i64immSExt32:$src2),
1952 (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>;
1954 // Memory-Register Subtraction with EFLAGS result
1955 def : Pat<(parallel (store (X86sub_flag (loadi64 addr:$dst), GR64:$src2),
1958 (SUB64mr addr:$dst, GR64:$src2)>;
1960 // Memory-Integer Subtraction with EFLAGS result
1961 def : Pat<(parallel (store (X86sub_flag (loadi64 addr:$dst), i64immSExt8:$src2),
1964 (SUB64mi8 addr:$dst, i64immSExt8:$src2)>;
1965 def : Pat<(parallel (store (X86sub_flag (loadi64 addr:$dst), i64immSExt32:$src2),
1968 (SUB64mi32 addr:$dst, i64immSExt32:$src2)>;
1970 // Register-Register Signed Integer Multiplication with EFLAGS result
1971 def : Pat<(parallel (X86smul_flag GR64:$src1, GR64:$src2),
1973 (IMUL64rr GR64:$src1, GR64:$src2)>;
1975 // Register-Memory Signed Integer Multiplication with EFLAGS result
1976 def : Pat<(parallel (X86smul_flag GR64:$src1, (loadi64 addr:$src2)),
1978 (IMUL64rm GR64:$src1, addr:$src2)>;
1980 // Register-Integer Signed Integer Multiplication with EFLAGS result
1981 def : Pat<(parallel (X86smul_flag GR64:$src1, i64immSExt8:$src2),
1983 (IMUL64rri8 GR64:$src1, i64immSExt8:$src2)>;
1984 def : Pat<(parallel (X86smul_flag GR64:$src1, i64immSExt32:$src2),
1986 (IMUL64rri32 GR64:$src1, i64immSExt32:$src2)>;
1988 // Memory-Integer Signed Integer Multiplication with EFLAGS result
1989 def : Pat<(parallel (X86smul_flag (loadi64 addr:$src1), i64immSExt8:$src2),
1991 (IMUL64rmi8 addr:$src1, i64immSExt8:$src2)>;
1992 def : Pat<(parallel (X86smul_flag (loadi64 addr:$src1), i64immSExt32:$src2),
1994 (IMUL64rmi32 addr:$src1, i64immSExt32:$src2)>;
1996 // INC and DEC with EFLAGS result. Note that these do not set CF.
1997 def : Pat<(parallel (X86inc_flag GR16:$src), (implicit EFLAGS)),
1998 (INC64_16r GR16:$src)>, Requires<[In64BitMode]>;
1999 def : Pat<(parallel (store (i16 (X86inc_flag (loadi16 addr:$dst))), addr:$dst),
2001 (INC64_16m addr:$dst)>, Requires<[In64BitMode]>;
2002 def : Pat<(parallel (X86dec_flag GR16:$src), (implicit EFLAGS)),
2003 (DEC64_16r GR16:$src)>, Requires<[In64BitMode]>;
2004 def : Pat<(parallel (store (i16 (X86dec_flag (loadi16 addr:$dst))), addr:$dst),
2006 (DEC64_16m addr:$dst)>, Requires<[In64BitMode]>;
2008 def : Pat<(parallel (X86inc_flag GR32:$src), (implicit EFLAGS)),
2009 (INC64_32r GR32:$src)>, Requires<[In64BitMode]>;
2010 def : Pat<(parallel (store (i32 (X86inc_flag (loadi32 addr:$dst))), addr:$dst),
2012 (INC64_32m addr:$dst)>, Requires<[In64BitMode]>;
2013 def : Pat<(parallel (X86dec_flag GR32:$src), (implicit EFLAGS)),
2014 (DEC64_32r GR32:$src)>, Requires<[In64BitMode]>;
2015 def : Pat<(parallel (store (i32 (X86dec_flag (loadi32 addr:$dst))), addr:$dst),
2017 (DEC64_32m addr:$dst)>, Requires<[In64BitMode]>;
2019 def : Pat<(parallel (X86inc_flag GR64:$src), (implicit EFLAGS)),
2020 (INC64r GR64:$src)>;
2021 def : Pat<(parallel (store (i64 (X86inc_flag (loadi64 addr:$dst))), addr:$dst),
2023 (INC64m addr:$dst)>;
2024 def : Pat<(parallel (X86dec_flag GR64:$src), (implicit EFLAGS)),
2025 (DEC64r GR64:$src)>;
2026 def : Pat<(parallel (store (i64 (X86dec_flag (loadi64 addr:$dst))), addr:$dst),
2028 (DEC64m addr:$dst)>;
2030 //===----------------------------------------------------------------------===//
2031 // X86-64 SSE Instructions
2032 //===----------------------------------------------------------------------===//
2034 // Move instructions...
2036 def MOV64toPQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
2037 "mov{d|q}\t{$src, $dst|$dst, $src}",
2039 (v2i64 (scalar_to_vector GR64:$src)))]>;
2040 def MOVPQIto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
2041 "mov{d|q}\t{$src, $dst|$dst, $src}",
2042 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
2045 def MOV64toSDrr : RPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
2046 "mov{d|q}\t{$src, $dst|$dst, $src}",
2047 [(set FR64:$dst, (bitconvert GR64:$src))]>;
2048 def MOV64toSDrm : RPDI<0x6E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
2049 "movq\t{$src, $dst|$dst, $src}",
2050 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>;
2052 def MOVSDto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
2053 "mov{d|q}\t{$src, $dst|$dst, $src}",
2054 [(set GR64:$dst, (bitconvert FR64:$src))]>;
2055 def MOVSDto64mr : RPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
2056 "movq\t{$src, $dst|$dst, $src}",
2057 [(store (i64 (bitconvert FR64:$src)), addr:$dst)]>;
2059 //===----------------------------------------------------------------------===//
2060 // X86-64 SSE4.1 Instructions
2061 //===----------------------------------------------------------------------===//
2063 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
2064 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
2065 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
2066 (ins VR128:$src1, i32i8imm:$src2),
2067 !strconcat(OpcodeStr,
2068 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2070 (extractelt (v2i64 VR128:$src1), imm:$src2))]>, OpSize, REX_W;
2071 def mr : SS4AIi8<opc, MRMDestMem, (outs),
2072 (ins i64mem:$dst, VR128:$src1, i32i8imm:$src2),
2073 !strconcat(OpcodeStr,
2074 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2075 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
2076 addr:$dst)]>, OpSize, REX_W;
2079 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
2081 let isTwoAddress = 1 in {
2082 multiclass SS41I_insert64<bits<8> opc, string OpcodeStr> {
2083 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
2084 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
2085 !strconcat(OpcodeStr,
2086 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2088 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
2090 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
2091 (ins VR128:$src1, i64mem:$src2, i32i8imm:$src3),
2092 !strconcat(OpcodeStr,
2093 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2095 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
2096 imm:$src3)))]>, OpSize, REX_W;
2100 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">;
2102 // -disable-16bit support.
2103 def : Pat<(truncstorei16 (i64 imm:$src), addr:$dst),
2104 (MOV16mi addr:$dst, imm:$src)>;
2105 def : Pat<(truncstorei16 GR64:$src, addr:$dst),
2106 (MOV16mr addr:$dst, (EXTRACT_SUBREG GR64:$src, x86_subreg_16bit))>;
2107 def : Pat<(i64 (sextloadi16 addr:$dst)),
2108 (MOVSX64rm16 addr:$dst)>;
2109 def : Pat<(i64 (zextloadi16 addr:$dst)),
2110 (MOVZX64rm16 addr:$dst)>;
2111 def : Pat<(i64 (extloadi16 addr:$dst)),
2112 (MOVZX64rm16 addr:$dst)>;