1 //====- X86Instr64bit.td - Describe X86-64 Instructions ----*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86-64 instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // Operand Definitions.
20 // 64-bits but only 32 bits are significant.
21 def i64i32imm : Operand<i64>;
22 // 64-bits but only 8 bits are significant.
23 def i64i8imm : Operand<i64>;
25 def lea64mem : Operand<i64> {
26 let PrintMethod = "printi64mem";
27 let MIOperandInfo = (ops GR64, i8imm, GR64, i32imm);
30 def lea64_32mem : Operand<i32> {
31 let PrintMethod = "printlea64_32mem";
32 let MIOperandInfo = (ops GR32, i8imm, GR32, i32imm);
35 //===----------------------------------------------------------------------===//
36 // Complex Pattern Definitions.
38 def lea64addr : ComplexPattern<i64, 4, "SelectLEAAddr",
39 [add, mul, shl, or, frameindex, X86Wrapper],
42 //===----------------------------------------------------------------------===//
46 def i64immSExt8 : PatLeaf<(i64 imm), [{
47 // i64immSExt8 predicate - True if the 64-bit immediate fits in a 8-bit
48 // sign extended field.
49 return (int64_t)N->getZExtValue() == (int8_t)N->getZExtValue();
52 def i64immSExt32 : PatLeaf<(i64 imm), [{
53 // i64immSExt32 predicate - True if the 64-bit immediate fits in a 32-bit
54 // sign extended field.
55 return (int64_t)N->getZExtValue() == (int32_t)N->getZExtValue();
58 def i64immZExt32 : PatLeaf<(i64 imm), [{
59 // i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit
60 // unsignedsign extended field.
61 return (uint64_t)N->getZExtValue() == (uint32_t)N->getZExtValue();
64 def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>;
65 def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>;
66 def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>;
68 def zextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (zextloadi1 node:$ptr))>;
69 def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>;
70 def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>;
71 def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>;
73 def extloadi64i1 : PatFrag<(ops node:$ptr), (i64 (extloadi1 node:$ptr))>;
74 def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>;
75 def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>;
76 def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>;
78 //===----------------------------------------------------------------------===//
79 // Instruction list...
82 // ADJCALLSTACKDOWN/UP implicitly use/def RSP because they may be expanded into
83 // a stack adjustment and the codegen must know that they may modify the stack
84 // pointer before prolog-epilog rewriting occurs.
85 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
86 // sub / add which can clobber EFLAGS.
87 let Defs = [RSP, EFLAGS], Uses = [RSP] in {
88 def ADJCALLSTACKDOWN64 : I<0, Pseudo, (outs), (ins i32imm:$amt),
90 [(X86callseq_start timm:$amt)]>,
91 Requires<[In64BitMode]>;
92 def ADJCALLSTACKUP64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
94 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
95 Requires<[In64BitMode]>;
98 //===----------------------------------------------------------------------===//
99 // Call Instructions...
102 // All calls clobber the non-callee saved registers. RSP is marked as
103 // a use to prevent stack-pointer assignments that appear immediately
104 // before calls from potentially appearing dead. Uses for argument
105 // registers are added manually.
106 let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
107 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
108 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
109 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
110 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
112 def CALL64pcrel32 : I<0xE8, RawFrm,
113 (outs), (ins i64i32imm:$dst, variable_ops),
114 "call\t${dst:call}", [(X86call imm:$dst)]>,
115 Requires<[In64BitMode]>;
116 def CALL64r : I<0xFF, MRM2r, (outs), (ins GR64:$dst, variable_ops),
117 "call\t{*}$dst", [(X86call GR64:$dst)]>;
118 def CALL64m : I<0xFF, MRM2m, (outs), (ins i64mem:$dst, variable_ops),
119 "call\t{*}$dst", [(X86call (loadi64 addr:$dst))]>;
124 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
125 def TCRETURNdi64 : I<0, Pseudo, (outs), (ins i64imm:$dst, i32imm:$offset,
127 "#TC_RETURN $dst $offset",
130 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
131 def TCRETURNri64 : I<0, Pseudo, (outs), (ins GR64:$dst, i32imm:$offset,
133 "#TC_RETURN $dst $offset",
137 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
138 def TAILJMPr64 : I<0xFF, MRM4r, (outs), (ins GR64:$dst),
139 "jmp{q}\t{*}$dst # TAILCALL",
143 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
144 def JMP64r : I<0xFF, MRM4r, (outs), (ins GR64:$dst), "jmp{q}\t{*}$dst",
145 [(brind GR64:$dst)]>;
146 def JMP64m : I<0xFF, MRM4m, (outs), (ins i64mem:$dst), "jmp{q}\t{*}$dst",
147 [(brind (loadi64 addr:$dst))]>;
150 //===----------------------------------------------------------------------===//
151 // EH Pseudo Instructions
153 let isTerminator = 1, isReturn = 1, isBarrier = 1,
155 def EH_RETURN64 : I<0xC3, RawFrm, (outs), (ins GR64:$addr),
156 "ret\t#eh_return, addr: $addr",
157 [(X86ehret GR64:$addr)]>;
161 //===----------------------------------------------------------------------===//
162 // Miscellaneous Instructions...
164 let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, neverHasSideEffects = 1 in
165 def LEAVE64 : I<0xC9, RawFrm,
166 (outs), (ins), "leave", []>;
167 let Defs = [RSP], Uses = [RSP], neverHasSideEffects=1 in {
169 def POP64r : I<0x58, AddRegFrm,
170 (outs GR64:$reg), (ins), "pop{q}\t$reg", []>;
172 def PUSH64r : I<0x50, AddRegFrm,
173 (outs), (ins GR64:$reg), "push{q}\t$reg", []>;
176 let Defs = [RSP, EFLAGS], Uses = [RSP], mayLoad = 1 in
177 def POPFQ : I<0x9D, RawFrm, (outs), (ins), "popf", []>, REX_W;
178 let Defs = [RSP], Uses = [RSP, EFLAGS], mayStore = 1 in
179 def PUSHFQ : I<0x9C, RawFrm, (outs), (ins), "pushf", []>;
181 def LEA64_32r : I<0x8D, MRMSrcMem,
182 (outs GR32:$dst), (ins lea64_32mem:$src),
183 "lea{l}\t{$src|$dst}, {$dst|$src}",
184 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In64BitMode]>;
186 let isReMaterializable = 1 in
187 def LEA64r : RI<0x8D, MRMSrcMem, (outs GR64:$dst), (ins lea64mem:$src),
188 "lea{q}\t{$src|$dst}, {$dst|$src}",
189 [(set GR64:$dst, lea64addr:$src)]>;
191 let isTwoAddress = 1 in
192 def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src),
194 [(set GR64:$dst, (bswap GR64:$src))]>, TB;
196 // Bit scan instructions.
197 let Defs = [EFLAGS] in {
198 def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
199 "bsf{q}\t{$src, $dst|$dst, $src}",
200 [(set GR64:$dst, (X86bsf GR64:$src)), (implicit EFLAGS)]>, TB;
201 def BSF64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
202 "bsf{q}\t{$src, $dst|$dst, $src}",
203 [(set GR64:$dst, (X86bsf (loadi64 addr:$src))),
204 (implicit EFLAGS)]>, TB;
206 def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
207 "bsr{q}\t{$src, $dst|$dst, $src}",
208 [(set GR64:$dst, (X86bsr GR64:$src)), (implicit EFLAGS)]>, TB;
209 def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
210 "bsr{q}\t{$src, $dst|$dst, $src}",
211 [(set GR64:$dst, (X86bsr (loadi64 addr:$src))),
212 (implicit EFLAGS)]>, TB;
216 let Defs = [RCX,RDI,RSI], Uses = [RCX,RDI,RSI] in
217 def REP_MOVSQ : RI<0xA5, RawFrm, (outs), (ins), "{rep;movsq|rep movsq}",
218 [(X86rep_movs i64)]>, REP;
219 let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI] in
220 def REP_STOSQ : RI<0xAB, RawFrm, (outs), (ins), "{rep;stosq|rep stosq}",
221 [(X86rep_stos i64)]>, REP;
223 //===----------------------------------------------------------------------===//
224 // Move Instructions...
227 let neverHasSideEffects = 1 in
228 def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
229 "mov{q}\t{$src, $dst|$dst, $src}", []>;
231 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
232 def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src),
233 "movabs{q}\t{$src, $dst|$dst, $src}",
234 [(set GR64:$dst, imm:$src)]>;
235 def MOV64ri32 : RIi32<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src),
236 "mov{q}\t{$src, $dst|$dst, $src}",
237 [(set GR64:$dst, i64immSExt32:$src)]>;
240 let canFoldAsLoad = 1 in
241 def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
242 "mov{q}\t{$src, $dst|$dst, $src}",
243 [(set GR64:$dst, (load addr:$src))]>;
245 def MOV64mr : RI<0x89, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
246 "mov{q}\t{$src, $dst|$dst, $src}",
247 [(store GR64:$src, addr:$dst)]>;
248 def MOV64mi32 : RIi32<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src),
249 "mov{q}\t{$src, $dst|$dst, $src}",
250 [(store i64immSExt32:$src, addr:$dst)]>;
252 // Sign/Zero extenders
254 def MOVSX64rr8 : RI<0xBE, MRMSrcReg, (outs GR64:$dst), (ins GR8 :$src),
255 "movs{bq|x}\t{$src, $dst|$dst, $src}",
256 [(set GR64:$dst, (sext GR8:$src))]>, TB;
257 def MOVSX64rm8 : RI<0xBE, MRMSrcMem, (outs GR64:$dst), (ins i8mem :$src),
258 "movs{bq|x}\t{$src, $dst|$dst, $src}",
259 [(set GR64:$dst, (sextloadi64i8 addr:$src))]>, TB;
260 def MOVSX64rr16: RI<0xBF, MRMSrcReg, (outs GR64:$dst), (ins GR16:$src),
261 "movs{wq|x}\t{$src, $dst|$dst, $src}",
262 [(set GR64:$dst, (sext GR16:$src))]>, TB;
263 def MOVSX64rm16: RI<0xBF, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
264 "movs{wq|x}\t{$src, $dst|$dst, $src}",
265 [(set GR64:$dst, (sextloadi64i16 addr:$src))]>, TB;
266 def MOVSX64rr32: RI<0x63, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src),
267 "movs{lq|xd}\t{$src, $dst|$dst, $src}",
268 [(set GR64:$dst, (sext GR32:$src))]>;
269 def MOVSX64rm32: RI<0x63, MRMSrcMem, (outs GR64:$dst), (ins i32mem:$src),
270 "movs{lq|xd}\t{$src, $dst|$dst, $src}",
271 [(set GR64:$dst, (sextloadi64i32 addr:$src))]>;
273 // Use movzbl instead of movzbq when the destination is a register; it's
274 // equivalent due to implicit zero-extending, and it has a smaller encoding.
275 def MOVZX64rr8 : I<0xB6, MRMSrcReg, (outs GR64:$dst), (ins GR8 :$src),
276 "movz{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
277 [(set GR64:$dst, (zext GR8:$src))]>, TB;
278 def MOVZX64rm8 : I<0xB6, MRMSrcMem, (outs GR64:$dst), (ins i8mem :$src),
279 "movz{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
280 [(set GR64:$dst, (zextloadi64i8 addr:$src))]>, TB;
281 // Use movzwl instead of movzwq when the destination is a register; it's
282 // equivalent due to implicit zero-extending, and it has a smaller encoding.
283 def MOVZX64rr16: I<0xB7, MRMSrcReg, (outs GR64:$dst), (ins GR16:$src),
284 "movz{wl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
285 [(set GR64:$dst, (zext GR16:$src))]>, TB;
286 def MOVZX64rm16: I<0xB7, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
287 "movz{wl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
288 [(set GR64:$dst, (zextloadi64i16 addr:$src))]>, TB;
290 // There's no movzlq instruction, but movl can be used for this purpose, using
291 // implicit zero-extension. We need this because the seeming alternative for
292 // implementing zext from 32 to 64, an EXTRACT_SUBREG/SUBREG_TO_REG pair, isn't
293 // safe because both instructions could be optimized away in the
294 // register-to-register case, leaving nothing behind to do the zero extension.
295 def MOVZX64rr32 : I<0x89, MRMDestReg, (outs GR64:$dst), (ins GR32:$src),
296 "mov{l}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
297 [(set GR64:$dst, (zext GR32:$src))]>;
298 def MOVZX64rm32 : I<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i32mem:$src),
299 "mov{l}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
300 [(set GR64:$dst, (zextloadi64i32 addr:$src))]>;
302 let neverHasSideEffects = 1 in {
303 let Defs = [RAX], Uses = [EAX] in
304 def CDQE : RI<0x98, RawFrm, (outs), (ins),
305 "{cltq|cdqe}", []>; // RAX = signext(EAX)
307 let Defs = [RAX,RDX], Uses = [RAX] in
308 def CQO : RI<0x99, RawFrm, (outs), (ins),
309 "{cqto|cqo}", []>; // RDX:RAX = signext(RAX)
312 //===----------------------------------------------------------------------===//
313 // Arithmetic Instructions...
316 let Defs = [EFLAGS] in {
317 let isTwoAddress = 1 in {
318 let isConvertibleToThreeAddress = 1 in {
319 let isCommutable = 1 in
320 // Register-Register Addition
321 def ADD64rr : RI<0x01, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
322 "add{q}\t{$src2, $dst|$dst, $src2}",
323 [(set GR64:$dst, (add GR64:$src1, GR64:$src2)),
326 // Register-Integer Addition
327 def ADD64ri8 : RIi8<0x83, MRM0r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
328 "add{q}\t{$src2, $dst|$dst, $src2}",
329 [(set GR64:$dst, (add GR64:$src1, i64immSExt8:$src2)),
331 def ADD64ri32 : RIi32<0x81, MRM0r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
332 "add{q}\t{$src2, $dst|$dst, $src2}",
333 [(set GR64:$dst, (add GR64:$src1, i64immSExt32:$src2)),
335 } // isConvertibleToThreeAddress
337 // Register-Memory Addition
338 def ADD64rm : RI<0x03, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
339 "add{q}\t{$src2, $dst|$dst, $src2}",
340 [(set GR64:$dst, (add GR64:$src1, (load addr:$src2))),
344 // Memory-Register Addition
345 def ADD64mr : RI<0x01, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
346 "add{q}\t{$src2, $dst|$dst, $src2}",
347 [(store (add (load addr:$dst), GR64:$src2), addr:$dst),
349 def ADD64mi8 : RIi8<0x83, MRM0m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
350 "add{q}\t{$src2, $dst|$dst, $src2}",
351 [(store (add (load addr:$dst), i64immSExt8:$src2), addr:$dst),
353 def ADD64mi32 : RIi32<0x81, MRM0m, (outs), (ins i64mem:$dst, i64i32imm :$src2),
354 "add{q}\t{$src2, $dst|$dst, $src2}",
355 [(store (add (load addr:$dst), i64immSExt32:$src2), addr:$dst),
358 let Uses = [EFLAGS] in {
359 let isTwoAddress = 1 in {
360 let isCommutable = 1 in
361 def ADC64rr : RI<0x11, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
362 "adc{q}\t{$src2, $dst|$dst, $src2}",
363 [(set GR64:$dst, (adde GR64:$src1, GR64:$src2))]>;
365 def ADC64rm : RI<0x13, MRMSrcMem , (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
366 "adc{q}\t{$src2, $dst|$dst, $src2}",
367 [(set GR64:$dst, (adde GR64:$src1, (load addr:$src2)))]>;
369 def ADC64ri8 : RIi8<0x83, MRM2r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
370 "adc{q}\t{$src2, $dst|$dst, $src2}",
371 [(set GR64:$dst, (adde GR64:$src1, i64immSExt8:$src2))]>;
372 def ADC64ri32 : RIi32<0x81, MRM2r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
373 "adc{q}\t{$src2, $dst|$dst, $src2}",
374 [(set GR64:$dst, (adde GR64:$src1, i64immSExt32:$src2))]>;
377 def ADC64mr : RI<0x11, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
378 "adc{q}\t{$src2, $dst|$dst, $src2}",
379 [(store (adde (load addr:$dst), GR64:$src2), addr:$dst)]>;
380 def ADC64mi8 : RIi8<0x83, MRM2m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
381 "adc{q}\t{$src2, $dst|$dst, $src2}",
382 [(store (adde (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>;
383 def ADC64mi32 : RIi32<0x81, MRM2m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
384 "adc{q}\t{$src2, $dst|$dst, $src2}",
385 [(store (adde (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>;
388 let isTwoAddress = 1 in {
389 // Register-Register Subtraction
390 def SUB64rr : RI<0x29, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
391 "sub{q}\t{$src2, $dst|$dst, $src2}",
392 [(set GR64:$dst, (sub GR64:$src1, GR64:$src2)),
395 // Register-Memory Subtraction
396 def SUB64rm : RI<0x2B, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
397 "sub{q}\t{$src2, $dst|$dst, $src2}",
398 [(set GR64:$dst, (sub GR64:$src1, (load addr:$src2))),
401 // Register-Integer Subtraction
402 def SUB64ri8 : RIi8<0x83, MRM5r, (outs GR64:$dst),
403 (ins GR64:$src1, i64i8imm:$src2),
404 "sub{q}\t{$src2, $dst|$dst, $src2}",
405 [(set GR64:$dst, (sub GR64:$src1, i64immSExt8:$src2)),
407 def SUB64ri32 : RIi32<0x81, MRM5r, (outs GR64:$dst),
408 (ins GR64:$src1, i64i32imm:$src2),
409 "sub{q}\t{$src2, $dst|$dst, $src2}",
410 [(set GR64:$dst, (sub GR64:$src1, i64immSExt32:$src2)),
414 // Memory-Register Subtraction
415 def SUB64mr : RI<0x29, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
416 "sub{q}\t{$src2, $dst|$dst, $src2}",
417 [(store (sub (load addr:$dst), GR64:$src2), addr:$dst),
420 // Memory-Integer Subtraction
421 def SUB64mi8 : RIi8<0x83, MRM5m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
422 "sub{q}\t{$src2, $dst|$dst, $src2}",
423 [(store (sub (load addr:$dst), i64immSExt8:$src2),
426 def SUB64mi32 : RIi32<0x81, MRM5m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
427 "sub{q}\t{$src2, $dst|$dst, $src2}",
428 [(store (sub (load addr:$dst), i64immSExt32:$src2),
432 let Uses = [EFLAGS] in {
433 let isTwoAddress = 1 in {
434 def SBB64rr : RI<0x19, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
435 "sbb{q}\t{$src2, $dst|$dst, $src2}",
436 [(set GR64:$dst, (sube GR64:$src1, GR64:$src2))]>;
438 def SBB64rm : RI<0x1B, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
439 "sbb{q}\t{$src2, $dst|$dst, $src2}",
440 [(set GR64:$dst, (sube GR64:$src1, (load addr:$src2)))]>;
442 def SBB64ri8 : RIi8<0x83, MRM3r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
443 "sbb{q}\t{$src2, $dst|$dst, $src2}",
444 [(set GR64:$dst, (sube GR64:$src1, i64immSExt8:$src2))]>;
445 def SBB64ri32 : RIi32<0x81, MRM3r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
446 "sbb{q}\t{$src2, $dst|$dst, $src2}",
447 [(set GR64:$dst, (sube GR64:$src1, i64immSExt32:$src2))]>;
450 def SBB64mr : RI<0x19, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
451 "sbb{q}\t{$src2, $dst|$dst, $src2}",
452 [(store (sube (load addr:$dst), GR64:$src2), addr:$dst)]>;
453 def SBB64mi8 : RIi8<0x83, MRM3m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
454 "sbb{q}\t{$src2, $dst|$dst, $src2}",
455 [(store (sube (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>;
456 def SBB64mi32 : RIi32<0x81, MRM3m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
457 "sbb{q}\t{$src2, $dst|$dst, $src2}",
458 [(store (sube (load addr:$dst), i64immSExt32:$src2), addr:$dst)]>;
462 // Unsigned multiplication
463 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], neverHasSideEffects = 1 in {
464 def MUL64r : RI<0xF7, MRM4r, (outs), (ins GR64:$src),
465 "mul{q}\t$src", []>; // RAX,RDX = RAX*GR64
467 def MUL64m : RI<0xF7, MRM4m, (outs), (ins i64mem:$src),
468 "mul{q}\t$src", []>; // RAX,RDX = RAX*[mem64]
470 // Signed multiplication
471 def IMUL64r : RI<0xF7, MRM5r, (outs), (ins GR64:$src),
472 "imul{q}\t$src", []>; // RAX,RDX = RAX*GR64
474 def IMUL64m : RI<0xF7, MRM5m, (outs), (ins i64mem:$src),
475 "imul{q}\t$src", []>; // RAX,RDX = RAX*[mem64]
478 let Defs = [EFLAGS] in {
479 let isTwoAddress = 1 in {
480 let isCommutable = 1 in
481 // Register-Register Signed Integer Multiplication
482 def IMUL64rr : RI<0xAF, MRMSrcReg, (outs GR64:$dst),
483 (ins GR64:$src1, GR64:$src2),
484 "imul{q}\t{$src2, $dst|$dst, $src2}",
485 [(set GR64:$dst, (mul GR64:$src1, GR64:$src2)),
486 (implicit EFLAGS)]>, TB;
488 // Register-Memory Signed Integer Multiplication
489 def IMUL64rm : RI<0xAF, MRMSrcMem, (outs GR64:$dst),
490 (ins GR64:$src1, i64mem:$src2),
491 "imul{q}\t{$src2, $dst|$dst, $src2}",
492 [(set GR64:$dst, (mul GR64:$src1, (load addr:$src2))),
493 (implicit EFLAGS)]>, TB;
496 // Suprisingly enough, these are not two address instructions!
498 // Register-Integer Signed Integer Multiplication
499 def IMUL64rri8 : RIi8<0x6B, MRMSrcReg, // GR64 = GR64*I8
500 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
501 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
502 [(set GR64:$dst, (mul GR64:$src1, i64immSExt8:$src2)),
504 def IMUL64rri32 : RIi32<0x69, MRMSrcReg, // GR64 = GR64*I32
505 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
506 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
507 [(set GR64:$dst, (mul GR64:$src1, i64immSExt32:$src2)),
510 // Memory-Integer Signed Integer Multiplication
511 def IMUL64rmi8 : RIi8<0x6B, MRMSrcMem, // GR64 = [mem64]*I8
512 (outs GR64:$dst), (ins i64mem:$src1, i64i8imm: $src2),
513 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
514 [(set GR64:$dst, (mul (load addr:$src1),
517 def IMUL64rmi32 : RIi32<0x69, MRMSrcMem, // GR64 = [mem64]*I32
518 (outs GR64:$dst), (ins i64mem:$src1, i64i32imm:$src2),
519 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
520 [(set GR64:$dst, (mul (load addr:$src1),
521 i64immSExt32:$src2)),
525 // Unsigned division / remainder
526 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in {
527 def DIV64r : RI<0xF7, MRM6r, (outs), (ins GR64:$src), // RDX:RAX/r64 = RAX,RDX
529 // Signed division / remainder
530 def IDIV64r: RI<0xF7, MRM7r, (outs), (ins GR64:$src), // RDX:RAX/r64 = RAX,RDX
531 "idiv{q}\t$src", []>;
533 def DIV64m : RI<0xF7, MRM6m, (outs), (ins i64mem:$src), // RDX:RAX/[mem64] = RAX,RDX
535 def IDIV64m: RI<0xF7, MRM7m, (outs), (ins i64mem:$src), // RDX:RAX/[mem64] = RAX,RDX
536 "idiv{q}\t$src", []>;
540 // Unary instructions
541 let Defs = [EFLAGS], CodeSize = 2 in {
542 let isTwoAddress = 1 in
543 def NEG64r : RI<0xF7, MRM3r, (outs GR64:$dst), (ins GR64:$src), "neg{q}\t$dst",
544 [(set GR64:$dst, (ineg GR64:$src)),
546 def NEG64m : RI<0xF7, MRM3m, (outs), (ins i64mem:$dst), "neg{q}\t$dst",
547 [(store (ineg (loadi64 addr:$dst)), addr:$dst),
550 let isTwoAddress = 1, isConvertibleToThreeAddress = 1 in
551 def INC64r : RI<0xFF, MRM0r, (outs GR64:$dst), (ins GR64:$src), "inc{q}\t$dst",
552 [(set GR64:$dst, (add GR64:$src, 1)),
554 def INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst), "inc{q}\t$dst",
555 [(store (add (loadi64 addr:$dst), 1), addr:$dst),
558 let isTwoAddress = 1, isConvertibleToThreeAddress = 1 in
559 def DEC64r : RI<0xFF, MRM1r, (outs GR64:$dst), (ins GR64:$src), "dec{q}\t$dst",
560 [(set GR64:$dst, (add GR64:$src, -1)),
562 def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst",
563 [(store (add (loadi64 addr:$dst), -1), addr:$dst),
566 // In 64-bit mode, single byte INC and DEC cannot be encoded.
567 let isTwoAddress = 1, isConvertibleToThreeAddress = 1 in {
568 // Can transform into LEA.
569 def INC64_16r : I<0xFF, MRM0r, (outs GR16:$dst), (ins GR16:$src), "inc{w}\t$dst",
570 [(set GR16:$dst, (add GR16:$src, 1)),
572 OpSize, Requires<[In64BitMode]>;
573 def INC64_32r : I<0xFF, MRM0r, (outs GR32:$dst), (ins GR32:$src), "inc{l}\t$dst",
574 [(set GR32:$dst, (add GR32:$src, 1)),
576 Requires<[In64BitMode]>;
577 def DEC64_16r : I<0xFF, MRM1r, (outs GR16:$dst), (ins GR16:$src), "dec{w}\t$dst",
578 [(set GR16:$dst, (add GR16:$src, -1)),
580 OpSize, Requires<[In64BitMode]>;
581 def DEC64_32r : I<0xFF, MRM1r, (outs GR32:$dst), (ins GR32:$src), "dec{l}\t$dst",
582 [(set GR32:$dst, (add GR32:$src, -1)),
584 Requires<[In64BitMode]>;
585 } // isConvertibleToThreeAddress
587 // These are duplicates of their 32-bit counterparts. Only needed so X86 knows
588 // how to unfold them.
589 let isTwoAddress = 0, CodeSize = 2 in {
590 def INC64_16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
591 [(store (add (loadi16 addr:$dst), 1), addr:$dst),
593 OpSize, Requires<[In64BitMode]>;
594 def INC64_32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
595 [(store (add (loadi32 addr:$dst), 1), addr:$dst),
597 Requires<[In64BitMode]>;
598 def DEC64_16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
599 [(store (add (loadi16 addr:$dst), -1), addr:$dst),
601 OpSize, Requires<[In64BitMode]>;
602 def DEC64_32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
603 [(store (add (loadi32 addr:$dst), -1), addr:$dst),
605 Requires<[In64BitMode]>;
607 } // Defs = [EFLAGS], CodeSize
610 let Defs = [EFLAGS] in {
611 // Shift instructions
612 let isTwoAddress = 1 in {
614 def SHL64rCL : RI<0xD3, MRM4r, (outs GR64:$dst), (ins GR64:$src),
615 "shl{q}\t{%cl, $dst|$dst, %CL}",
616 [(set GR64:$dst, (shl GR64:$src, CL))]>;
617 let isConvertibleToThreeAddress = 1 in // Can transform into LEA.
618 def SHL64ri : RIi8<0xC1, MRM4r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
619 "shl{q}\t{$src2, $dst|$dst, $src2}",
620 [(set GR64:$dst, (shl GR64:$src1, (i8 imm:$src2)))]>;
621 // NOTE: We don't use shifts of a register by one, because 'add reg,reg' is
626 def SHL64mCL : RI<0xD3, MRM4m, (outs), (ins i64mem:$dst),
627 "shl{q}\t{%cl, $dst|$dst, %CL}",
628 [(store (shl (loadi64 addr:$dst), CL), addr:$dst)]>;
629 def SHL64mi : RIi8<0xC1, MRM4m, (outs), (ins i64mem:$dst, i8imm:$src),
630 "shl{q}\t{$src, $dst|$dst, $src}",
631 [(store (shl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
632 def SHL64m1 : RI<0xD1, MRM4m, (outs), (ins i64mem:$dst),
634 [(store (shl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
636 let isTwoAddress = 1 in {
638 def SHR64rCL : RI<0xD3, MRM5r, (outs GR64:$dst), (ins GR64:$src),
639 "shr{q}\t{%cl, $dst|$dst, %CL}",
640 [(set GR64:$dst, (srl GR64:$src, CL))]>;
641 def SHR64ri : RIi8<0xC1, MRM5r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
642 "shr{q}\t{$src2, $dst|$dst, $src2}",
643 [(set GR64:$dst, (srl GR64:$src1, (i8 imm:$src2)))]>;
644 def SHR64r1 : RI<0xD1, MRM5r, (outs GR64:$dst), (ins GR64:$src1),
646 [(set GR64:$dst, (srl GR64:$src1, (i8 1)))]>;
650 def SHR64mCL : RI<0xD3, MRM5m, (outs), (ins i64mem:$dst),
651 "shr{q}\t{%cl, $dst|$dst, %CL}",
652 [(store (srl (loadi64 addr:$dst), CL), addr:$dst)]>;
653 def SHR64mi : RIi8<0xC1, MRM5m, (outs), (ins i64mem:$dst, i8imm:$src),
654 "shr{q}\t{$src, $dst|$dst, $src}",
655 [(store (srl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
656 def SHR64m1 : RI<0xD1, MRM5m, (outs), (ins i64mem:$dst),
658 [(store (srl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
660 let isTwoAddress = 1 in {
662 def SAR64rCL : RI<0xD3, MRM7r, (outs GR64:$dst), (ins GR64:$src),
663 "sar{q}\t{%cl, $dst|$dst, %CL}",
664 [(set GR64:$dst, (sra GR64:$src, CL))]>;
665 def SAR64ri : RIi8<0xC1, MRM7r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
666 "sar{q}\t{$src2, $dst|$dst, $src2}",
667 [(set GR64:$dst, (sra GR64:$src1, (i8 imm:$src2)))]>;
668 def SAR64r1 : RI<0xD1, MRM7r, (outs GR64:$dst), (ins GR64:$src1),
670 [(set GR64:$dst, (sra GR64:$src1, (i8 1)))]>;
674 def SAR64mCL : RI<0xD3, MRM7m, (outs), (ins i64mem:$dst),
675 "sar{q}\t{%cl, $dst|$dst, %CL}",
676 [(store (sra (loadi64 addr:$dst), CL), addr:$dst)]>;
677 def SAR64mi : RIi8<0xC1, MRM7m, (outs), (ins i64mem:$dst, i8imm:$src),
678 "sar{q}\t{$src, $dst|$dst, $src}",
679 [(store (sra (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
680 def SAR64m1 : RI<0xD1, MRM7m, (outs), (ins i64mem:$dst),
682 [(store (sra (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
684 // Rotate instructions
685 let isTwoAddress = 1 in {
687 def ROL64rCL : RI<0xD3, MRM0r, (outs GR64:$dst), (ins GR64:$src),
688 "rol{q}\t{%cl, $dst|$dst, %CL}",
689 [(set GR64:$dst, (rotl GR64:$src, CL))]>;
690 def ROL64ri : RIi8<0xC1, MRM0r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
691 "rol{q}\t{$src2, $dst|$dst, $src2}",
692 [(set GR64:$dst, (rotl GR64:$src1, (i8 imm:$src2)))]>;
693 def ROL64r1 : RI<0xD1, MRM0r, (outs GR64:$dst), (ins GR64:$src1),
695 [(set GR64:$dst, (rotl GR64:$src1, (i8 1)))]>;
699 def ROL64mCL : I<0xD3, MRM0m, (outs), (ins i64mem:$dst),
700 "rol{q}\t{%cl, $dst|$dst, %CL}",
701 [(store (rotl (loadi64 addr:$dst), CL), addr:$dst)]>;
702 def ROL64mi : RIi8<0xC1, MRM0m, (outs), (ins i64mem:$dst, i8imm:$src),
703 "rol{q}\t{$src, $dst|$dst, $src}",
704 [(store (rotl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
705 def ROL64m1 : RI<0xD1, MRM0m, (outs), (ins i64mem:$dst),
707 [(store (rotl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
709 let isTwoAddress = 1 in {
711 def ROR64rCL : RI<0xD3, MRM1r, (outs GR64:$dst), (ins GR64:$src),
712 "ror{q}\t{%cl, $dst|$dst, %CL}",
713 [(set GR64:$dst, (rotr GR64:$src, CL))]>;
714 def ROR64ri : RIi8<0xC1, MRM1r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
715 "ror{q}\t{$src2, $dst|$dst, $src2}",
716 [(set GR64:$dst, (rotr GR64:$src1, (i8 imm:$src2)))]>;
717 def ROR64r1 : RI<0xD1, MRM1r, (outs GR64:$dst), (ins GR64:$src1),
719 [(set GR64:$dst, (rotr GR64:$src1, (i8 1)))]>;
723 def ROR64mCL : RI<0xD3, MRM1m, (outs), (ins i64mem:$dst),
724 "ror{q}\t{%cl, $dst|$dst, %CL}",
725 [(store (rotr (loadi64 addr:$dst), CL), addr:$dst)]>;
726 def ROR64mi : RIi8<0xC1, MRM1m, (outs), (ins i64mem:$dst, i8imm:$src),
727 "ror{q}\t{$src, $dst|$dst, $src}",
728 [(store (rotr (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
729 def ROR64m1 : RI<0xD1, MRM1m, (outs), (ins i64mem:$dst),
731 [(store (rotr (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
733 // Double shift instructions (generalizations of rotate)
734 let isTwoAddress = 1 in {
736 def SHLD64rrCL : RI<0xA5, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
737 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
738 [(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2, CL))]>, TB;
739 def SHRD64rrCL : RI<0xAD, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
740 "shrd{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
741 [(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2, CL))]>, TB;
744 let isCommutable = 1 in { // FIXME: Update X86InstrInfo::commuteInstruction
745 def SHLD64rri8 : RIi8<0xA4, MRMDestReg,
746 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2, i8imm:$src3),
747 "shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
748 [(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2,
751 def SHRD64rri8 : RIi8<0xAC, MRMDestReg,
752 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2, i8imm:$src3),
753 "shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
754 [(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2,
761 def SHLD64mrCL : RI<0xA5, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
762 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
763 [(store (X86shld (loadi64 addr:$dst), GR64:$src2, CL),
765 def SHRD64mrCL : RI<0xAD, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
766 "shrd{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
767 [(store (X86shrd (loadi64 addr:$dst), GR64:$src2, CL),
770 def SHLD64mri8 : RIi8<0xA4, MRMDestMem,
771 (outs), (ins i64mem:$dst, GR64:$src2, i8imm:$src3),
772 "shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
773 [(store (X86shld (loadi64 addr:$dst), GR64:$src2,
774 (i8 imm:$src3)), addr:$dst)]>,
776 def SHRD64mri8 : RIi8<0xAC, MRMDestMem,
777 (outs), (ins i64mem:$dst, GR64:$src2, i8imm:$src3),
778 "shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
779 [(store (X86shrd (loadi64 addr:$dst), GR64:$src2,
780 (i8 imm:$src3)), addr:$dst)]>,
784 //===----------------------------------------------------------------------===//
785 // Logical Instructions...
788 let isTwoAddress = 1 , AddedComplexity = 15 in
789 def NOT64r : RI<0xF7, MRM2r, (outs GR64:$dst), (ins GR64:$src), "not{q}\t$dst",
790 [(set GR64:$dst, (not GR64:$src))]>;
791 def NOT64m : RI<0xF7, MRM2m, (outs), (ins i64mem:$dst), "not{q}\t$dst",
792 [(store (not (loadi64 addr:$dst)), addr:$dst)]>;
794 let Defs = [EFLAGS] in {
795 let isTwoAddress = 1 in {
796 let isCommutable = 1 in
797 def AND64rr : RI<0x21, MRMDestReg,
798 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
799 "and{q}\t{$src2, $dst|$dst, $src2}",
800 [(set GR64:$dst, (and GR64:$src1, GR64:$src2)),
802 def AND64rm : RI<0x23, MRMSrcMem,
803 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
804 "and{q}\t{$src2, $dst|$dst, $src2}",
805 [(set GR64:$dst, (and GR64:$src1, (load addr:$src2))),
807 def AND64ri8 : RIi8<0x83, MRM4r,
808 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
809 "and{q}\t{$src2, $dst|$dst, $src2}",
810 [(set GR64:$dst, (and GR64:$src1, i64immSExt8:$src2)),
812 def AND64ri32 : RIi32<0x81, MRM4r,
813 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
814 "and{q}\t{$src2, $dst|$dst, $src2}",
815 [(set GR64:$dst, (and GR64:$src1, i64immSExt32:$src2)),
819 def AND64mr : RI<0x21, MRMDestMem,
820 (outs), (ins i64mem:$dst, GR64:$src),
821 "and{q}\t{$src, $dst|$dst, $src}",
822 [(store (and (load addr:$dst), GR64:$src), addr:$dst),
824 def AND64mi8 : RIi8<0x83, MRM4m,
825 (outs), (ins i64mem:$dst, i64i8imm :$src),
826 "and{q}\t{$src, $dst|$dst, $src}",
827 [(store (and (load addr:$dst), i64immSExt8:$src), addr:$dst),
829 def AND64mi32 : RIi32<0x81, MRM4m,
830 (outs), (ins i64mem:$dst, i64i32imm:$src),
831 "and{q}\t{$src, $dst|$dst, $src}",
832 [(store (and (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst),
835 let isTwoAddress = 1 in {
836 let isCommutable = 1 in
837 def OR64rr : RI<0x09, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
838 "or{q}\t{$src2, $dst|$dst, $src2}",
839 [(set GR64:$dst, (or GR64:$src1, GR64:$src2)),
841 def OR64rm : RI<0x0B, MRMSrcMem , (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
842 "or{q}\t{$src2, $dst|$dst, $src2}",
843 [(set GR64:$dst, (or GR64:$src1, (load addr:$src2))),
845 def OR64ri8 : RIi8<0x83, MRM1r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
846 "or{q}\t{$src2, $dst|$dst, $src2}",
847 [(set GR64:$dst, (or GR64:$src1, i64immSExt8:$src2)),
849 def OR64ri32 : RIi32<0x81, MRM1r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
850 "or{q}\t{$src2, $dst|$dst, $src2}",
851 [(set GR64:$dst, (or GR64:$src1, i64immSExt32:$src2)),
855 def OR64mr : RI<0x09, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
856 "or{q}\t{$src, $dst|$dst, $src}",
857 [(store (or (load addr:$dst), GR64:$src), addr:$dst),
859 def OR64mi8 : RIi8<0x83, MRM1m, (outs), (ins i64mem:$dst, i64i8imm:$src),
860 "or{q}\t{$src, $dst|$dst, $src}",
861 [(store (or (load addr:$dst), i64immSExt8:$src), addr:$dst),
863 def OR64mi32 : RIi32<0x81, MRM1m, (outs), (ins i64mem:$dst, i64i32imm:$src),
864 "or{q}\t{$src, $dst|$dst, $src}",
865 [(store (or (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst),
868 let isTwoAddress = 1 in {
869 let isCommutable = 1 in
870 def XOR64rr : RI<0x31, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
871 "xor{q}\t{$src2, $dst|$dst, $src2}",
872 [(set GR64:$dst, (xor GR64:$src1, GR64:$src2)),
874 def XOR64rm : RI<0x33, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
875 "xor{q}\t{$src2, $dst|$dst, $src2}",
876 [(set GR64:$dst, (xor GR64:$src1, (load addr:$src2))),
878 def XOR64ri8 : RIi8<0x83, MRM6r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
879 "xor{q}\t{$src2, $dst|$dst, $src2}",
880 [(set GR64:$dst, (xor GR64:$src1, i64immSExt8:$src2)),
882 def XOR64ri32 : RIi32<0x81, MRM6r,
883 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
884 "xor{q}\t{$src2, $dst|$dst, $src2}",
885 [(set GR64:$dst, (xor GR64:$src1, i64immSExt32:$src2)),
889 def XOR64mr : RI<0x31, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
890 "xor{q}\t{$src, $dst|$dst, $src}",
891 [(store (xor (load addr:$dst), GR64:$src), addr:$dst),
893 def XOR64mi8 : RIi8<0x83, MRM6m, (outs), (ins i64mem:$dst, i64i8imm :$src),
894 "xor{q}\t{$src, $dst|$dst, $src}",
895 [(store (xor (load addr:$dst), i64immSExt8:$src), addr:$dst),
897 def XOR64mi32 : RIi32<0x81, MRM6m, (outs), (ins i64mem:$dst, i64i32imm:$src),
898 "xor{q}\t{$src, $dst|$dst, $src}",
899 [(store (xor (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst),
903 //===----------------------------------------------------------------------===//
904 // Comparison Instructions...
907 // Integer comparison
908 let Defs = [EFLAGS] in {
909 let isCommutable = 1 in
910 def TEST64rr : RI<0x85, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
911 "test{q}\t{$src2, $src1|$src1, $src2}",
912 [(X86cmp (and GR64:$src1, GR64:$src2), 0),
914 def TEST64rm : RI<0x85, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2),
915 "test{q}\t{$src2, $src1|$src1, $src2}",
916 [(X86cmp (and GR64:$src1, (loadi64 addr:$src2)), 0),
918 def TEST64ri32 : RIi32<0xF7, MRM0r, (outs),
919 (ins GR64:$src1, i64i32imm:$src2),
920 "test{q}\t{$src2, $src1|$src1, $src2}",
921 [(X86cmp (and GR64:$src1, i64immSExt32:$src2), 0),
923 def TEST64mi32 : RIi32<0xF7, MRM0m, (outs),
924 (ins i64mem:$src1, i64i32imm:$src2),
925 "test{q}\t{$src2, $src1|$src1, $src2}",
926 [(X86cmp (and (loadi64 addr:$src1), i64immSExt32:$src2), 0),
929 def CMP64rr : RI<0x39, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
930 "cmp{q}\t{$src2, $src1|$src1, $src2}",
931 [(X86cmp GR64:$src1, GR64:$src2),
933 def CMP64mr : RI<0x39, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
934 "cmp{q}\t{$src2, $src1|$src1, $src2}",
935 [(X86cmp (loadi64 addr:$src1), GR64:$src2),
937 def CMP64rm : RI<0x3B, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2),
938 "cmp{q}\t{$src2, $src1|$src1, $src2}",
939 [(X86cmp GR64:$src1, (loadi64 addr:$src2)),
941 def CMP64ri8 : RIi8<0x83, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2),
942 "cmp{q}\t{$src2, $src1|$src1, $src2}",
943 [(X86cmp GR64:$src1, i64immSExt8:$src2),
945 def CMP64ri32 : RIi32<0x81, MRM7r, (outs), (ins GR64:$src1, i64i32imm:$src2),
946 "cmp{q}\t{$src2, $src1|$src1, $src2}",
947 [(X86cmp GR64:$src1, i64immSExt32:$src2),
949 def CMP64mi8 : RIi8<0x83, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
950 "cmp{q}\t{$src2, $src1|$src1, $src2}",
951 [(X86cmp (loadi64 addr:$src1), i64immSExt8:$src2),
953 def CMP64mi32 : RIi32<0x81, MRM7m, (outs),
954 (ins i64mem:$src1, i64i32imm:$src2),
955 "cmp{q}\t{$src2, $src1|$src1, $src2}",
956 [(X86cmp (loadi64 addr:$src1), i64immSExt32:$src2),
961 // TODO: BTC, BTR, and BTS
962 let Defs = [EFLAGS] in {
963 def BT64rr : RI<0xA3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
964 "bt{q}\t{$src2, $src1|$src1, $src2}",
965 [(X86bt GR64:$src1, GR64:$src2),
966 (implicit EFLAGS)]>, TB;
968 // Unlike with the register+register form, the memory+register form of the
969 // bt instruction does not ignore the high bits of the index. From ISel's
970 // perspective, this is pretty bizarre. Disable these instructions for now.
971 //def BT64mr : RI<0xA3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
972 // "bt{q}\t{$src2, $src1|$src1, $src2}",
973 // [(X86bt (loadi64 addr:$src1), GR64:$src2),
974 // (implicit EFLAGS)]>, TB;
976 def BT64ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR64:$src1, i64i8imm:$src2),
977 "bt{q}\t{$src2, $src1|$src1, $src2}",
978 [(X86bt GR64:$src1, i64immSExt8:$src2),
979 (implicit EFLAGS)]>, TB;
980 // Note that these instructions don't need FastBTMem because that
981 // only applies when the other operand is in a register. When it's
982 // an immediate, bt is still fast.
983 def BT64mi8 : Ii8<0xBA, MRM4m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
984 "bt{q}\t{$src2, $src1|$src1, $src2}",
985 [(X86bt (loadi64 addr:$src1), i64immSExt8:$src2),
986 (implicit EFLAGS)]>, TB;
990 let Uses = [EFLAGS], isTwoAddress = 1 in {
991 let isCommutable = 1 in {
992 def CMOVB64rr : RI<0x42, MRMSrcReg, // if <u, GR64 = GR64
993 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
994 "cmovb\t{$src2, $dst|$dst, $src2}",
995 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
996 X86_COND_B, EFLAGS))]>, TB;
997 def CMOVAE64rr: RI<0x43, MRMSrcReg, // if >=u, GR64 = GR64
998 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
999 "cmovae\t{$src2, $dst|$dst, $src2}",
1000 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1001 X86_COND_AE, EFLAGS))]>, TB;
1002 def CMOVE64rr : RI<0x44, MRMSrcReg, // if ==, GR64 = GR64
1003 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1004 "cmove\t{$src2, $dst|$dst, $src2}",
1005 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1006 X86_COND_E, EFLAGS))]>, TB;
1007 def CMOVNE64rr: RI<0x45, MRMSrcReg, // if !=, GR64 = GR64
1008 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1009 "cmovne\t{$src2, $dst|$dst, $src2}",
1010 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1011 X86_COND_NE, EFLAGS))]>, TB;
1012 def CMOVBE64rr: RI<0x46, MRMSrcReg, // if <=u, GR64 = GR64
1013 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1014 "cmovbe\t{$src2, $dst|$dst, $src2}",
1015 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1016 X86_COND_BE, EFLAGS))]>, TB;
1017 def CMOVA64rr : RI<0x47, MRMSrcReg, // if >u, GR64 = GR64
1018 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1019 "cmova\t{$src2, $dst|$dst, $src2}",
1020 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1021 X86_COND_A, EFLAGS))]>, TB;
1022 def CMOVL64rr : RI<0x4C, MRMSrcReg, // if <s, GR64 = GR64
1023 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1024 "cmovl\t{$src2, $dst|$dst, $src2}",
1025 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1026 X86_COND_L, EFLAGS))]>, TB;
1027 def CMOVGE64rr: RI<0x4D, MRMSrcReg, // if >=s, GR64 = GR64
1028 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1029 "cmovge\t{$src2, $dst|$dst, $src2}",
1030 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1031 X86_COND_GE, EFLAGS))]>, TB;
1032 def CMOVLE64rr: RI<0x4E, MRMSrcReg, // if <=s, GR64 = GR64
1033 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1034 "cmovle\t{$src2, $dst|$dst, $src2}",
1035 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1036 X86_COND_LE, EFLAGS))]>, TB;
1037 def CMOVG64rr : RI<0x4F, MRMSrcReg, // if >s, GR64 = GR64
1038 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1039 "cmovg\t{$src2, $dst|$dst, $src2}",
1040 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1041 X86_COND_G, EFLAGS))]>, TB;
1042 def CMOVS64rr : RI<0x48, MRMSrcReg, // if signed, GR64 = GR64
1043 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1044 "cmovs\t{$src2, $dst|$dst, $src2}",
1045 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1046 X86_COND_S, EFLAGS))]>, TB;
1047 def CMOVNS64rr: RI<0x49, MRMSrcReg, // if !signed, GR64 = GR64
1048 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1049 "cmovns\t{$src2, $dst|$dst, $src2}",
1050 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1051 X86_COND_NS, EFLAGS))]>, TB;
1052 def CMOVP64rr : RI<0x4A, MRMSrcReg, // if parity, GR64 = GR64
1053 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1054 "cmovp\t{$src2, $dst|$dst, $src2}",
1055 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1056 X86_COND_P, EFLAGS))]>, TB;
1057 def CMOVNP64rr : RI<0x4B, MRMSrcReg, // if !parity, GR64 = GR64
1058 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1059 "cmovnp\t{$src2, $dst|$dst, $src2}",
1060 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1061 X86_COND_NP, EFLAGS))]>, TB;
1062 def CMOVO64rr : RI<0x40, MRMSrcReg, // if overflow, GR64 = GR64
1063 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1064 "cmovo\t{$src2, $dst|$dst, $src2}",
1065 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1066 X86_COND_O, EFLAGS))]>, TB;
1067 def CMOVNO64rr : RI<0x41, MRMSrcReg, // if !overflow, GR64 = GR64
1068 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1069 "cmovno\t{$src2, $dst|$dst, $src2}",
1070 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1071 X86_COND_NO, EFLAGS))]>, TB;
1072 } // isCommutable = 1
1074 def CMOVB64rm : RI<0x42, MRMSrcMem, // if <u, GR64 = [mem64]
1075 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1076 "cmovb\t{$src2, $dst|$dst, $src2}",
1077 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1078 X86_COND_B, EFLAGS))]>, TB;
1079 def CMOVAE64rm: RI<0x43, MRMSrcMem, // if >=u, GR64 = [mem64]
1080 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1081 "cmovae\t{$src2, $dst|$dst, $src2}",
1082 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1083 X86_COND_AE, EFLAGS))]>, TB;
1084 def CMOVE64rm : RI<0x44, MRMSrcMem, // if ==, GR64 = [mem64]
1085 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1086 "cmove\t{$src2, $dst|$dst, $src2}",
1087 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1088 X86_COND_E, EFLAGS))]>, TB;
1089 def CMOVNE64rm: RI<0x45, MRMSrcMem, // if !=, GR64 = [mem64]
1090 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1091 "cmovne\t{$src2, $dst|$dst, $src2}",
1092 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1093 X86_COND_NE, EFLAGS))]>, TB;
1094 def CMOVBE64rm: RI<0x46, MRMSrcMem, // if <=u, GR64 = [mem64]
1095 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1096 "cmovbe\t{$src2, $dst|$dst, $src2}",
1097 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1098 X86_COND_BE, EFLAGS))]>, TB;
1099 def CMOVA64rm : RI<0x47, MRMSrcMem, // if >u, GR64 = [mem64]
1100 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1101 "cmova\t{$src2, $dst|$dst, $src2}",
1102 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1103 X86_COND_A, EFLAGS))]>, TB;
1104 def CMOVL64rm : RI<0x4C, MRMSrcMem, // if <s, GR64 = [mem64]
1105 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1106 "cmovl\t{$src2, $dst|$dst, $src2}",
1107 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1108 X86_COND_L, EFLAGS))]>, TB;
1109 def CMOVGE64rm: RI<0x4D, MRMSrcMem, // if >=s, GR64 = [mem64]
1110 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1111 "cmovge\t{$src2, $dst|$dst, $src2}",
1112 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1113 X86_COND_GE, EFLAGS))]>, TB;
1114 def CMOVLE64rm: RI<0x4E, MRMSrcMem, // if <=s, GR64 = [mem64]
1115 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1116 "cmovle\t{$src2, $dst|$dst, $src2}",
1117 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1118 X86_COND_LE, EFLAGS))]>, TB;
1119 def CMOVG64rm : RI<0x4F, MRMSrcMem, // if >s, GR64 = [mem64]
1120 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1121 "cmovg\t{$src2, $dst|$dst, $src2}",
1122 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1123 X86_COND_G, EFLAGS))]>, TB;
1124 def CMOVS64rm : RI<0x48, MRMSrcMem, // if signed, GR64 = [mem64]
1125 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1126 "cmovs\t{$src2, $dst|$dst, $src2}",
1127 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1128 X86_COND_S, EFLAGS))]>, TB;
1129 def CMOVNS64rm: RI<0x49, MRMSrcMem, // if !signed, GR64 = [mem64]
1130 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1131 "cmovns\t{$src2, $dst|$dst, $src2}",
1132 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1133 X86_COND_NS, EFLAGS))]>, TB;
1134 def CMOVP64rm : RI<0x4A, MRMSrcMem, // if parity, GR64 = [mem64]
1135 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1136 "cmovp\t{$src2, $dst|$dst, $src2}",
1137 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1138 X86_COND_P, EFLAGS))]>, TB;
1139 def CMOVNP64rm : RI<0x4B, MRMSrcMem, // if !parity, GR64 = [mem64]
1140 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1141 "cmovnp\t{$src2, $dst|$dst, $src2}",
1142 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1143 X86_COND_NP, EFLAGS))]>, TB;
1144 def CMOVO64rm : RI<0x40, MRMSrcMem, // if overflow, GR64 = [mem64]
1145 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1146 "cmovo\t{$src2, $dst|$dst, $src2}",
1147 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1148 X86_COND_O, EFLAGS))]>, TB;
1149 def CMOVNO64rm : RI<0x41, MRMSrcMem, // if !overflow, GR64 = [mem64]
1150 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1151 "cmovno\t{$src2, $dst|$dst, $src2}",
1152 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1153 X86_COND_NO, EFLAGS))]>, TB;
1156 //===----------------------------------------------------------------------===//
1157 // Conversion Instructions...
1160 // f64 -> signed i64
1161 def Int_CVTSD2SI64rr: RSDI<0x2D, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1162 "cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1164 (int_x86_sse2_cvtsd2si64 VR128:$src))]>;
1165 def Int_CVTSD2SI64rm: RSDI<0x2D, MRMSrcMem, (outs GR64:$dst), (ins f128mem:$src),
1166 "cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1167 [(set GR64:$dst, (int_x86_sse2_cvtsd2si64
1168 (load addr:$src)))]>;
1169 def CVTTSD2SI64rr: RSDI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins FR64:$src),
1170 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1171 [(set GR64:$dst, (fp_to_sint FR64:$src))]>;
1172 def CVTTSD2SI64rm: RSDI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f64mem:$src),
1173 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1174 [(set GR64:$dst, (fp_to_sint (loadf64 addr:$src)))]>;
1175 def Int_CVTTSD2SI64rr: RSDI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1176 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1178 (int_x86_sse2_cvttsd2si64 VR128:$src))]>;
1179 def Int_CVTTSD2SI64rm: RSDI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f128mem:$src),
1180 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1182 (int_x86_sse2_cvttsd2si64
1183 (load addr:$src)))]>;
1185 // Signed i64 -> f64
1186 def CVTSI2SD64rr: RSDI<0x2A, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
1187 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
1188 [(set FR64:$dst, (sint_to_fp GR64:$src))]>;
1189 def CVTSI2SD64rm: RSDI<0x2A, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
1190 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
1191 [(set FR64:$dst, (sint_to_fp (loadi64 addr:$src)))]>;
1193 let isTwoAddress = 1 in {
1194 def Int_CVTSI2SD64rr: RSDI<0x2A, MRMSrcReg,
1195 (outs VR128:$dst), (ins VR128:$src1, GR64:$src2),
1196 "cvtsi2sd{q}\t{$src2, $dst|$dst, $src2}",
1198 (int_x86_sse2_cvtsi642sd VR128:$src1,
1200 def Int_CVTSI2SD64rm: RSDI<0x2A, MRMSrcMem,
1201 (outs VR128:$dst), (ins VR128:$src1, i64mem:$src2),
1202 "cvtsi2sd{q}\t{$src2, $dst|$dst, $src2}",
1204 (int_x86_sse2_cvtsi642sd VR128:$src1,
1205 (loadi64 addr:$src2)))]>;
1208 // Signed i64 -> f32
1209 def CVTSI2SS64rr: RSSI<0x2A, MRMSrcReg, (outs FR32:$dst), (ins GR64:$src),
1210 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
1211 [(set FR32:$dst, (sint_to_fp GR64:$src))]>;
1212 def CVTSI2SS64rm: RSSI<0x2A, MRMSrcMem, (outs FR32:$dst), (ins i64mem:$src),
1213 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
1214 [(set FR32:$dst, (sint_to_fp (loadi64 addr:$src)))]>;
1216 let isTwoAddress = 1 in {
1217 def Int_CVTSI2SS64rr : RSSI<0x2A, MRMSrcReg,
1218 (outs VR128:$dst), (ins VR128:$src1, GR64:$src2),
1219 "cvtsi2ss{q}\t{$src2, $dst|$dst, $src2}",
1221 (int_x86_sse_cvtsi642ss VR128:$src1,
1223 def Int_CVTSI2SS64rm : RSSI<0x2A, MRMSrcMem,
1224 (outs VR128:$dst), (ins VR128:$src1, i64mem:$src2),
1225 "cvtsi2ss{q}\t{$src2, $dst|$dst, $src2}",
1227 (int_x86_sse_cvtsi642ss VR128:$src1,
1228 (loadi64 addr:$src2)))]>;
1231 // f32 -> signed i64
1232 def Int_CVTSS2SI64rr: RSSI<0x2D, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1233 "cvtss2si{q}\t{$src, $dst|$dst, $src}",
1235 (int_x86_sse_cvtss2si64 VR128:$src))]>;
1236 def Int_CVTSS2SI64rm: RSSI<0x2D, MRMSrcMem, (outs GR64:$dst), (ins f32mem:$src),
1237 "cvtss2si{q}\t{$src, $dst|$dst, $src}",
1238 [(set GR64:$dst, (int_x86_sse_cvtss2si64
1239 (load addr:$src)))]>;
1240 def CVTTSS2SI64rr: RSSI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins FR32:$src),
1241 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1242 [(set GR64:$dst, (fp_to_sint FR32:$src))]>;
1243 def CVTTSS2SI64rm: RSSI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f32mem:$src),
1244 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1245 [(set GR64:$dst, (fp_to_sint (loadf32 addr:$src)))]>;
1246 def Int_CVTTSS2SI64rr: RSSI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1247 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1249 (int_x86_sse_cvttss2si64 VR128:$src))]>;
1250 def Int_CVTTSS2SI64rm: RSSI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f32mem:$src),
1251 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1253 (int_x86_sse_cvttss2si64 (load addr:$src)))]>;
1255 //===----------------------------------------------------------------------===//
1256 // Alias Instructions
1257 //===----------------------------------------------------------------------===//
1259 // Alias instructions that map movr0 to xor. Use xorl instead of xorq; it's
1260 // equivalent due to implicit zero-extending, and it sometimes has a smaller
1262 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
1263 // FIXME: AddedComplexity gives MOV64r0 a higher priority than MOV64ri32. Remove
1264 // when we have a better way to specify isel priority.
1265 let Defs = [EFLAGS], AddedComplexity = 1,
1266 isReMaterializable = 1, isAsCheapAsAMove = 1 in
1267 def MOV64r0 : I<0x31, MRMInitReg, (outs GR64:$dst), (ins),
1268 "xor{l}\t${dst:subreg32}, ${dst:subreg32}",
1269 [(set GR64:$dst, 0)]>;
1271 // Materialize i64 constant where top 32-bits are zero.
1272 let AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1 in
1273 def MOV64ri64i32 : Ii32<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64i32imm:$src),
1274 "mov{l}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
1275 [(set GR64:$dst, i64immZExt32:$src)]>;
1277 //===----------------------------------------------------------------------===//
1278 // Thread Local Storage Instructions
1279 //===----------------------------------------------------------------------===//
1281 def TLS_addr64 : I<0, Pseudo, (outs GR64:$dst), (ins i64imm:$sym),
1282 ".byte\t0x66; leaq\t${sym:mem}(%rip), $dst; .word\t0x6666; rex64",
1283 [(set GR64:$dst, (X86tlsaddr tglobaltlsaddr:$sym))]>;
1285 let AddedComplexity = 5 in
1286 def MOV64GSrm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1287 "movq\t%gs:$src, $dst",
1288 [(set GR64:$dst, (gsload addr:$src))]>, SegGS;
1290 //===----------------------------------------------------------------------===//
1291 // Atomic Instructions
1292 //===----------------------------------------------------------------------===//
1294 let Defs = [RAX, EFLAGS], Uses = [RAX] in {
1295 def LCMPXCHG64 : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$ptr, GR64:$swap),
1296 "lock\n\tcmpxchgq\t$swap,$ptr",
1297 [(X86cas addr:$ptr, GR64:$swap, 8)]>, TB, LOCK;
1300 let Constraints = "$val = $dst" in {
1301 let Defs = [EFLAGS] in
1302 def LXADD64 : RI<0xC1, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$ptr,GR64:$val),
1303 "lock\n\txadd\t$val, $ptr",
1304 [(set GR64:$dst, (atomic_load_add_64 addr:$ptr, GR64:$val))]>,
1306 def XCHG64rm : RI<0x87, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$ptr,GR64:$val),
1308 [(set GR64:$dst, (atomic_swap_64 addr:$ptr, GR64:$val))]>;
1311 // Atomic exchange, and, or, xor
1312 let Constraints = "$val = $dst", Defs = [EFLAGS],
1313 usesCustomDAGSchedInserter = 1 in {
1314 def ATOMAND64 : I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1315 "#ATOMAND64 PSEUDO!",
1316 [(set GR64:$dst, (atomic_load_and_64 addr:$ptr, GR64:$val))]>;
1317 def ATOMOR64 : I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1318 "#ATOMOR64 PSEUDO!",
1319 [(set GR64:$dst, (atomic_load_or_64 addr:$ptr, GR64:$val))]>;
1320 def ATOMXOR64 : I<0, Pseudo,(outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1321 "#ATOMXOR64 PSEUDO!",
1322 [(set GR64:$dst, (atomic_load_xor_64 addr:$ptr, GR64:$val))]>;
1323 def ATOMNAND64 : I<0, Pseudo,(outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1324 "#ATOMNAND64 PSEUDO!",
1325 [(set GR64:$dst, (atomic_load_nand_64 addr:$ptr, GR64:$val))]>;
1326 def ATOMMIN64: I<0, Pseudo, (outs GR64:$dst), (ins i64mem:$ptr, GR64:$val),
1327 "#ATOMMIN64 PSEUDO!",
1328 [(set GR64:$dst, (atomic_load_min_64 addr:$ptr, GR64:$val))]>;
1329 def ATOMMAX64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1330 "#ATOMMAX64 PSEUDO!",
1331 [(set GR64:$dst, (atomic_load_max_64 addr:$ptr, GR64:$val))]>;
1332 def ATOMUMIN64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1333 "#ATOMUMIN64 PSEUDO!",
1334 [(set GR64:$dst, (atomic_load_umin_64 addr:$ptr, GR64:$val))]>;
1335 def ATOMUMAX64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1336 "#ATOMUMAX64 PSEUDO!",
1337 [(set GR64:$dst, (atomic_load_umax_64 addr:$ptr, GR64:$val))]>;
1340 //===----------------------------------------------------------------------===//
1341 // Non-Instruction Patterns
1342 //===----------------------------------------------------------------------===//
1344 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable
1345 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
1346 (MOV64ri tconstpool :$dst)>, Requires<[NotSmallCode]>;
1347 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
1348 (MOV64ri tjumptable :$dst)>, Requires<[NotSmallCode]>;
1349 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
1350 (MOV64ri tglobaladdr :$dst)>, Requires<[NotSmallCode]>;
1351 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
1352 (MOV64ri texternalsym:$dst)>, Requires<[NotSmallCode]>;
1354 def : Pat<(store (i64 (X86Wrapper tconstpool:$src)), addr:$dst),
1355 (MOV64mi32 addr:$dst, tconstpool:$src)>,
1356 Requires<[SmallCode, IsStatic]>;
1357 def : Pat<(store (i64 (X86Wrapper tjumptable:$src)), addr:$dst),
1358 (MOV64mi32 addr:$dst, tjumptable:$src)>,
1359 Requires<[SmallCode, IsStatic]>;
1360 def : Pat<(store (i64 (X86Wrapper tglobaladdr:$src)), addr:$dst),
1361 (MOV64mi32 addr:$dst, tglobaladdr:$src)>,
1362 Requires<[SmallCode, IsStatic]>;
1363 def : Pat<(store (i64 (X86Wrapper texternalsym:$src)), addr:$dst),
1364 (MOV64mi32 addr:$dst, texternalsym:$src)>,
1365 Requires<[SmallCode, IsStatic]>;
1368 // Direct PC relative function call for small code model. 32-bit displacement
1369 // sign extended to 64-bit.
1370 def : Pat<(X86call (i64 tglobaladdr:$dst)),
1371 (CALL64pcrel32 tglobaladdr:$dst)>;
1372 def : Pat<(X86call (i64 texternalsym:$dst)),
1373 (CALL64pcrel32 texternalsym:$dst)>;
1375 def : Pat<(X86tailcall (i64 tglobaladdr:$dst)),
1376 (CALL64pcrel32 tglobaladdr:$dst)>;
1377 def : Pat<(X86tailcall (i64 texternalsym:$dst)),
1378 (CALL64pcrel32 texternalsym:$dst)>;
1380 def : Pat<(X86tailcall GR64:$dst),
1381 (CALL64r GR64:$dst)>;
1385 def : Pat<(X86tailcall GR32:$dst),
1387 def : Pat<(X86tailcall (i64 tglobaladdr:$dst)),
1389 def : Pat<(X86tailcall (i64 texternalsym:$dst)),
1392 def : Pat<(X86tcret GR64:$dst, imm:$off),
1393 (TCRETURNri64 GR64:$dst, imm:$off)>;
1395 def : Pat<(X86tcret (i64 tglobaladdr:$dst), imm:$off),
1396 (TCRETURNdi64 texternalsym:$dst, imm:$off)>;
1398 def : Pat<(X86tcret (i64 texternalsym:$dst), imm:$off),
1399 (TCRETURNdi64 texternalsym:$dst, imm:$off)>;
1403 // TEST R,R is smaller than CMP R,0
1404 def : Pat<(parallel (X86cmp GR64:$src1, 0), (implicit EFLAGS)),
1405 (TEST64rr GR64:$src1, GR64:$src1)>;
1407 // Conditional moves with folded loads with operands swapped and conditions
1409 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_B, EFLAGS),
1410 (CMOVAE64rm GR64:$src2, addr:$src1)>;
1411 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_AE, EFLAGS),
1412 (CMOVB64rm GR64:$src2, addr:$src1)>;
1413 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_E, EFLAGS),
1414 (CMOVNE64rm GR64:$src2, addr:$src1)>;
1415 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NE, EFLAGS),
1416 (CMOVE64rm GR64:$src2, addr:$src1)>;
1417 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_BE, EFLAGS),
1418 (CMOVA64rm GR64:$src2, addr:$src1)>;
1419 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_A, EFLAGS),
1420 (CMOVBE64rm GR64:$src2, addr:$src1)>;
1421 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_L, EFLAGS),
1422 (CMOVGE64rm GR64:$src2, addr:$src1)>;
1423 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_GE, EFLAGS),
1424 (CMOVL64rm GR64:$src2, addr:$src1)>;
1425 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_LE, EFLAGS),
1426 (CMOVG64rm GR64:$src2, addr:$src1)>;
1427 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_G, EFLAGS),
1428 (CMOVLE64rm GR64:$src2, addr:$src1)>;
1429 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_P, EFLAGS),
1430 (CMOVNP64rm GR64:$src2, addr:$src1)>;
1431 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NP, EFLAGS),
1432 (CMOVP64rm GR64:$src2, addr:$src1)>;
1433 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_S, EFLAGS),
1434 (CMOVNS64rm GR64:$src2, addr:$src1)>;
1435 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NS, EFLAGS),
1436 (CMOVS64rm GR64:$src2, addr:$src1)>;
1437 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_O, EFLAGS),
1438 (CMOVNO64rm GR64:$src2, addr:$src1)>;
1439 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NO, EFLAGS),
1440 (CMOVO64rm GR64:$src2, addr:$src1)>;
1443 def : Pat<(i64 (zext GR32:$src)),
1444 (SUBREG_TO_REG (i64 0), GR32:$src, x86_subreg_32bit)>;
1446 // zextload bool -> zextload byte
1447 def : Pat<(zextloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>;
1450 // When extloading from 16-bit and smaller memory locations into 64-bit registers,
1451 // use zero-extending loads so that the entire 64-bit register is defined, avoiding
1452 // partial-register updates.
1453 def : Pat<(extloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>;
1454 def : Pat<(extloadi64i8 addr:$src), (MOVZX64rm8 addr:$src)>;
1455 def : Pat<(extloadi64i16 addr:$src), (MOVZX64rm16 addr:$src)>;
1456 // For other extloads, use subregs, since the high contents of the register are
1457 // defined after an extload.
1458 def : Pat<(extloadi64i32 addr:$src),
1459 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (MOV32rm addr:$src),
1461 def : Pat<(extloadi16i1 addr:$src),
1462 (INSERT_SUBREG (i16 (IMPLICIT_DEF)), (MOV8rm addr:$src),
1464 Requires<[In64BitMode]>;
1465 def : Pat<(extloadi16i8 addr:$src),
1466 (INSERT_SUBREG (i16 (IMPLICIT_DEF)), (MOV8rm addr:$src),
1468 Requires<[In64BitMode]>;
1471 def : Pat<(i64 (anyext GR8:$src)),
1472 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR8:$src, x86_subreg_8bit)>;
1473 def : Pat<(i64 (anyext GR16:$src)),
1474 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR16:$src, x86_subreg_16bit)>;
1475 def : Pat<(i64 (anyext GR32:$src)),
1476 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, x86_subreg_32bit)>;
1477 def : Pat<(i16 (anyext GR8:$src)),
1478 (INSERT_SUBREG (i16 (IMPLICIT_DEF)), GR8:$src, x86_subreg_8bit)>,
1479 Requires<[In64BitMode]>;
1480 def : Pat<(i32 (anyext GR8:$src)),
1481 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR8:$src, x86_subreg_8bit)>,
1482 Requires<[In64BitMode]>;
1484 //===----------------------------------------------------------------------===//
1486 //===----------------------------------------------------------------------===//
1488 // Odd encoding trick: -128 fits into an 8-bit immediate field while
1489 // +128 doesn't, so in this special case use a sub instead of an add.
1490 def : Pat<(add GR64:$src1, 128),
1491 (SUB64ri8 GR64:$src1, -128)>;
1492 def : Pat<(store (add (loadi64 addr:$dst), 128), addr:$dst),
1493 (SUB64mi8 addr:$dst, -128)>;
1495 // The same trick applies for 32-bit immediate fields in 64-bit
1497 def : Pat<(add GR64:$src1, 0x0000000080000000),
1498 (SUB64ri32 GR64:$src1, 0xffffffff80000000)>;
1499 def : Pat<(store (add (loadi64 addr:$dst), 0x00000000800000000), addr:$dst),
1500 (SUB64mi32 addr:$dst, 0xffffffff80000000)>;
1502 // r & (2^32-1) ==> movz
1503 def : Pat<(and GR64:$src, 0x00000000FFFFFFFF),
1504 (MOVZX64rr32 (i32 (EXTRACT_SUBREG GR64:$src, x86_subreg_32bit)))>;
1505 // r & (2^16-1) ==> movz
1506 def : Pat<(and GR64:$src, 0xffff),
1507 (MOVZX64rr16 (i16 (EXTRACT_SUBREG GR64:$src, x86_subreg_16bit)))>;
1508 // r & (2^8-1) ==> movz
1509 def : Pat<(and GR64:$src, 0xff),
1510 (MOVZX64rr8 (i8 (EXTRACT_SUBREG GR64:$src, x86_subreg_8bit)))>;
1511 // r & (2^8-1) ==> movz
1512 def : Pat<(and GR32:$src1, 0xff),
1513 (MOVZX32rr8 (i8 (EXTRACT_SUBREG GR32:$src1, x86_subreg_8bit)))>,
1514 Requires<[In64BitMode]>;
1515 // r & (2^8-1) ==> movz
1516 def : Pat<(and GR16:$src1, 0xff),
1517 (MOVZX16rr8 (i8 (EXTRACT_SUBREG GR16:$src1, x86_subreg_8bit)))>,
1518 Requires<[In64BitMode]>;
1520 // sext_inreg patterns
1521 def : Pat<(sext_inreg GR64:$src, i32),
1522 (MOVSX64rr32 (i32 (EXTRACT_SUBREG GR64:$src, x86_subreg_32bit)))>;
1523 def : Pat<(sext_inreg GR64:$src, i16),
1524 (MOVSX64rr16 (i16 (EXTRACT_SUBREG GR64:$src, x86_subreg_16bit)))>;
1525 def : Pat<(sext_inreg GR64:$src, i8),
1526 (MOVSX64rr8 (i8 (EXTRACT_SUBREG GR64:$src, x86_subreg_8bit)))>;
1527 def : Pat<(sext_inreg GR32:$src, i8),
1528 (MOVSX32rr8 (i8 (EXTRACT_SUBREG GR32:$src, x86_subreg_8bit)))>,
1529 Requires<[In64BitMode]>;
1530 def : Pat<(sext_inreg GR16:$src, i8),
1531 (MOVSX16rr8 (i8 (EXTRACT_SUBREG GR16:$src, x86_subreg_8bit)))>,
1532 Requires<[In64BitMode]>;
1535 def : Pat<(i32 (trunc GR64:$src)),
1536 (i32 (EXTRACT_SUBREG GR64:$src, x86_subreg_32bit))>;
1537 def : Pat<(i16 (trunc GR64:$src)),
1538 (i16 (EXTRACT_SUBREG GR64:$src, x86_subreg_16bit))>;
1539 def : Pat<(i8 (trunc GR64:$src)),
1540 (i8 (EXTRACT_SUBREG GR64:$src, x86_subreg_8bit))>;
1541 def : Pat<(i8 (trunc GR32:$src)),
1542 (i8 (EXTRACT_SUBREG GR32:$src, x86_subreg_8bit))>,
1543 Requires<[In64BitMode]>;
1544 def : Pat<(i8 (trunc GR16:$src)),
1545 (i8 (EXTRACT_SUBREG GR16:$src, x86_subreg_8bit))>,
1546 Requires<[In64BitMode]>;
1548 // (shl x, 1) ==> (add x, x)
1549 def : Pat<(shl GR64:$src1, (i8 1)), (ADD64rr GR64:$src1, GR64:$src1)>;
1551 // (shl x (and y, 63)) ==> (shl x, y)
1552 def : Pat<(shl GR64:$src1, (and CL:$amt, 63)),
1553 (SHL64rCL GR64:$src1)>;
1554 def : Pat<(store (shl (loadi64 addr:$dst), (and CL:$amt, 63)), addr:$dst),
1555 (SHL64mCL addr:$dst)>;
1557 def : Pat<(srl GR64:$src1, (and CL:$amt, 63)),
1558 (SHR64rCL GR64:$src1)>;
1559 def : Pat<(store (srl (loadi64 addr:$dst), (and CL:$amt, 63)), addr:$dst),
1560 (SHR64mCL addr:$dst)>;
1562 def : Pat<(sra GR64:$src1, (and CL:$amt, 63)),
1563 (SAR64rCL GR64:$src1)>;
1564 def : Pat<(store (sra (loadi64 addr:$dst), (and CL:$amt, 63)), addr:$dst),
1565 (SAR64mCL addr:$dst)>;
1567 // (or (x >> c) | (y << (64 - c))) ==> (shrd64 x, y, c)
1568 def : Pat<(or (srl GR64:$src1, CL:$amt),
1569 (shl GR64:$src2, (sub 64, CL:$amt))),
1570 (SHRD64rrCL GR64:$src1, GR64:$src2)>;
1572 def : Pat<(store (or (srl (loadi64 addr:$dst), CL:$amt),
1573 (shl GR64:$src2, (sub 64, CL:$amt))), addr:$dst),
1574 (SHRD64mrCL addr:$dst, GR64:$src2)>;
1576 def : Pat<(or (srl GR64:$src1, (i8 (trunc RCX:$amt))),
1577 (shl GR64:$src2, (i8 (trunc (sub 64, RCX:$amt))))),
1578 (SHRD64rrCL GR64:$src1, GR64:$src2)>;
1580 def : Pat<(store (or (srl (loadi64 addr:$dst), (i8 (trunc RCX:$amt))),
1581 (shl GR64:$src2, (i8 (trunc (sub 64, RCX:$amt))))),
1583 (SHRD64mrCL addr:$dst, GR64:$src2)>;
1585 def : Pat<(shrd GR64:$src1, (i8 imm:$amt1), GR64:$src2, (i8 imm:$amt2)),
1586 (SHRD64rri8 GR64:$src1, GR64:$src2, (i8 imm:$amt1))>;
1588 def : Pat<(store (shrd (loadi64 addr:$dst), (i8 imm:$amt1),
1589 GR64:$src2, (i8 imm:$amt2)), addr:$dst),
1590 (SHRD64mri8 addr:$dst, GR64:$src2, (i8 imm:$amt1))>;
1592 // (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
1593 def : Pat<(or (shl GR64:$src1, CL:$amt),
1594 (srl GR64:$src2, (sub 64, CL:$amt))),
1595 (SHLD64rrCL GR64:$src1, GR64:$src2)>;
1597 def : Pat<(store (or (shl (loadi64 addr:$dst), CL:$amt),
1598 (srl GR64:$src2, (sub 64, CL:$amt))), addr:$dst),
1599 (SHLD64mrCL addr:$dst, GR64:$src2)>;
1601 def : Pat<(or (shl GR64:$src1, (i8 (trunc RCX:$amt))),
1602 (srl GR64:$src2, (i8 (trunc (sub 64, RCX:$amt))))),
1603 (SHLD64rrCL GR64:$src1, GR64:$src2)>;
1605 def : Pat<(store (or (shl (loadi64 addr:$dst), (i8 (trunc RCX:$amt))),
1606 (srl GR64:$src2, (i8 (trunc (sub 64, RCX:$amt))))),
1608 (SHLD64mrCL addr:$dst, GR64:$src2)>;
1610 def : Pat<(shld GR64:$src1, (i8 imm:$amt1), GR64:$src2, (i8 imm:$amt2)),
1611 (SHLD64rri8 GR64:$src1, GR64:$src2, (i8 imm:$amt1))>;
1613 def : Pat<(store (shld (loadi64 addr:$dst), (i8 imm:$amt1),
1614 GR64:$src2, (i8 imm:$amt2)), addr:$dst),
1615 (SHLD64mri8 addr:$dst, GR64:$src2, (i8 imm:$amt1))>;
1617 // X86 specific add which produces a flag.
1618 def : Pat<(addc GR64:$src1, GR64:$src2),
1619 (ADD64rr GR64:$src1, GR64:$src2)>;
1620 def : Pat<(addc GR64:$src1, (load addr:$src2)),
1621 (ADD64rm GR64:$src1, addr:$src2)>;
1622 def : Pat<(addc GR64:$src1, i64immSExt8:$src2),
1623 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
1624 def : Pat<(addc GR64:$src1, i64immSExt32:$src2),
1625 (ADD64ri32 GR64:$src1, imm:$src2)>;
1627 def : Pat<(subc GR64:$src1, GR64:$src2),
1628 (SUB64rr GR64:$src1, GR64:$src2)>;
1629 def : Pat<(subc GR64:$src1, (load addr:$src2)),
1630 (SUB64rm GR64:$src1, addr:$src2)>;
1631 def : Pat<(subc GR64:$src1, i64immSExt8:$src2),
1632 (SUB64ri8 GR64:$src1, i64immSExt8:$src2)>;
1633 def : Pat<(subc GR64:$src1, imm:$src2),
1634 (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>;
1636 //===----------------------------------------------------------------------===//
1637 // EFLAGS-defining Patterns
1638 //===----------------------------------------------------------------------===//
1640 // Register-Register Addition with EFLAGS result
1641 def : Pat<(parallel (X86add_flag GR64:$src1, GR64:$src2),
1643 (ADD64rr GR64:$src1, GR64:$src2)>;
1645 // Register-Integer Addition with EFLAGS result
1646 def : Pat<(parallel (X86add_flag GR64:$src1, i64immSExt8:$src2),
1648 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
1649 def : Pat<(parallel (X86add_flag GR64:$src1, i64immSExt32:$src2),
1651 (ADD64ri32 GR64:$src1, i64immSExt32:$src2)>;
1653 // Register-Memory Addition with EFLAGS result
1654 def : Pat<(parallel (X86add_flag GR64:$src1, (loadi64 addr:$src2)),
1656 (ADD64rm GR64:$src1, addr:$src2)>;
1658 // Memory-Register Addition with EFLAGS result
1659 def : Pat<(parallel (store (X86add_flag (loadi64 addr:$dst), GR64:$src2),
1662 (ADD64mr addr:$dst, GR64:$src2)>;
1663 def : Pat<(parallel (store (X86add_flag (loadi64 addr:$dst), i64immSExt8:$src2),
1666 (ADD64mi8 addr:$dst, i64immSExt8:$src2)>;
1667 def : Pat<(parallel (store (X86add_flag (loadi64 addr:$dst), i64immSExt32:$src2),
1670 (ADD64mi32 addr:$dst, i64immSExt32:$src2)>;
1672 // Register-Register Subtraction with EFLAGS result
1673 def : Pat<(parallel (X86sub_flag GR64:$src1, GR64:$src2),
1675 (SUB64rr GR64:$src1, GR64:$src2)>;
1677 // Register-Memory Subtraction with EFLAGS result
1678 def : Pat<(parallel (X86sub_flag GR64:$src1, (loadi64 addr:$src2)),
1680 (SUB64rm GR64:$src1, addr:$src2)>;
1682 // Register-Integer Subtraction with EFLAGS result
1683 def : Pat<(parallel (X86sub_flag GR64:$src1, i64immSExt8:$src2),
1685 (SUB64ri8 GR64:$src1, i64immSExt8:$src2)>;
1686 def : Pat<(parallel (X86sub_flag GR64:$src1, i64immSExt32:$src2),
1688 (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>;
1690 // Memory-Register Subtraction with EFLAGS result
1691 def : Pat<(parallel (store (X86sub_flag (loadi64 addr:$dst), GR64:$src2),
1694 (SUB64mr addr:$dst, GR64:$src2)>;
1696 // Memory-Integer Subtraction with EFLAGS result
1697 def : Pat<(parallel (store (X86sub_flag (loadi64 addr:$dst), i64immSExt8:$src2),
1700 (SUB64mi8 addr:$dst, i64immSExt8:$src2)>;
1701 def : Pat<(parallel (store (X86sub_flag (loadi64 addr:$dst), i64immSExt32:$src2),
1704 (SUB64mi32 addr:$dst, i64immSExt32:$src2)>;
1706 // Register-Register Signed Integer Multiplication with EFLAGS result
1707 def : Pat<(parallel (X86smul_flag GR64:$src1, GR64:$src2),
1709 (IMUL64rr GR64:$src1, GR64:$src2)>;
1711 // Register-Memory Signed Integer Multiplication with EFLAGS result
1712 def : Pat<(parallel (X86smul_flag GR64:$src1, (loadi64 addr:$src2)),
1714 (IMUL64rm GR64:$src1, addr:$src2)>;
1716 // Register-Integer Signed Integer Multiplication with EFLAGS result
1717 def : Pat<(parallel (X86smul_flag GR64:$src1, i64immSExt8:$src2),
1719 (IMUL64rri8 GR64:$src1, i64immSExt8:$src2)>;
1720 def : Pat<(parallel (X86smul_flag GR64:$src1, i64immSExt32:$src2),
1722 (IMUL64rri32 GR64:$src1, i64immSExt32:$src2)>;
1724 // Memory-Integer Signed Integer Multiplication with EFLAGS result
1725 def : Pat<(parallel (X86smul_flag (loadi64 addr:$src1), i64immSExt8:$src2),
1727 (IMUL64rmi8 addr:$src1, i64immSExt8:$src2)>;
1728 def : Pat<(parallel (X86smul_flag (loadi64 addr:$src1), i64immSExt32:$src2),
1730 (IMUL64rmi32 addr:$src1, i64immSExt32:$src2)>;
1732 // INC and DEC with EFLAGS result. Note that these do not set CF.
1733 def : Pat<(parallel (X86inc_flag GR16:$src), (implicit EFLAGS)),
1734 (INC64_16r GR16:$src)>, Requires<[In64BitMode]>;
1735 def : Pat<(parallel (store (i16 (X86inc_flag (loadi16 addr:$dst))), addr:$dst),
1737 (INC64_16m addr:$dst)>, Requires<[In64BitMode]>;
1738 def : Pat<(parallel (X86dec_flag GR16:$src), (implicit EFLAGS)),
1739 (DEC64_16r GR16:$src)>, Requires<[In64BitMode]>;
1740 def : Pat<(parallel (store (i16 (X86dec_flag (loadi16 addr:$dst))), addr:$dst),
1742 (DEC64_16m addr:$dst)>, Requires<[In64BitMode]>;
1744 def : Pat<(parallel (X86inc_flag GR32:$src), (implicit EFLAGS)),
1745 (INC64_32r GR32:$src)>, Requires<[In64BitMode]>;
1746 def : Pat<(parallel (store (i32 (X86inc_flag (loadi32 addr:$dst))), addr:$dst),
1748 (INC64_32m addr:$dst)>, Requires<[In64BitMode]>;
1749 def : Pat<(parallel (X86dec_flag GR32:$src), (implicit EFLAGS)),
1750 (DEC64_32r GR32:$src)>, Requires<[In64BitMode]>;
1751 def : Pat<(parallel (store (i32 (X86dec_flag (loadi32 addr:$dst))), addr:$dst),
1753 (DEC64_32m addr:$dst)>, Requires<[In64BitMode]>;
1755 def : Pat<(parallel (X86inc_flag GR64:$src), (implicit EFLAGS)),
1756 (INC64r GR64:$src)>;
1757 def : Pat<(parallel (store (i64 (X86inc_flag (loadi64 addr:$dst))), addr:$dst),
1759 (INC64m addr:$dst)>;
1760 def : Pat<(parallel (X86dec_flag GR64:$src), (implicit EFLAGS)),
1761 (DEC64r GR64:$src)>;
1762 def : Pat<(parallel (store (i64 (X86dec_flag (loadi64 addr:$dst))), addr:$dst),
1764 (DEC64m addr:$dst)>;
1766 //===----------------------------------------------------------------------===//
1767 // X86-64 SSE Instructions
1768 //===----------------------------------------------------------------------===//
1770 // Move instructions...
1772 def MOV64toPQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
1773 "mov{d|q}\t{$src, $dst|$dst, $src}",
1775 (v2i64 (scalar_to_vector GR64:$src)))]>;
1776 def MOVPQIto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
1777 "mov{d|q}\t{$src, $dst|$dst, $src}",
1778 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
1781 def MOV64toSDrr : RPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
1782 "mov{d|q}\t{$src, $dst|$dst, $src}",
1783 [(set FR64:$dst, (bitconvert GR64:$src))]>;
1784 def MOV64toSDrm : RPDI<0x6E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
1785 "movq\t{$src, $dst|$dst, $src}",
1786 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>;
1788 def MOVSDto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
1789 "mov{d|q}\t{$src, $dst|$dst, $src}",
1790 [(set GR64:$dst, (bitconvert FR64:$src))]>;
1791 def MOVSDto64mr : RPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
1792 "movq\t{$src, $dst|$dst, $src}",
1793 [(store (i64 (bitconvert FR64:$src)), addr:$dst)]>;
1795 //===----------------------------------------------------------------------===//
1796 // X86-64 SSE4.1 Instructions
1797 //===----------------------------------------------------------------------===//
1799 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
1800 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
1801 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
1802 (ins VR128:$src1, i32i8imm:$src2),
1803 !strconcat(OpcodeStr,
1804 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1806 (extractelt (v2i64 VR128:$src1), imm:$src2))]>, OpSize, REX_W;
1807 def mr : SS4AIi8<opc, MRMDestMem, (outs),
1808 (ins i64mem:$dst, VR128:$src1, i32i8imm:$src2),
1809 !strconcat(OpcodeStr,
1810 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1811 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
1812 addr:$dst)]>, OpSize, REX_W;
1815 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
1817 let isTwoAddress = 1 in {
1818 multiclass SS41I_insert64<bits<8> opc, string OpcodeStr> {
1819 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
1820 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
1821 !strconcat(OpcodeStr,
1822 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
1824 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
1826 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
1827 (ins VR128:$src1, i64mem:$src2, i32i8imm:$src3),
1828 !strconcat(OpcodeStr,
1829 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
1831 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
1832 imm:$src3)))]>, OpSize, REX_W;
1836 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">;