1 //====- X86Instr64bit.td - Describe X86-64 Instructions ----*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86-64 instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // Operand Definitions.
20 // 64-bits but only 32 bits are significant.
21 def i64i32imm : Operand<i64> {
22 let ParserMatchClass = ImmSExti64i32AsmOperand;
25 // 64-bits but only 32 bits are significant, and those bits are treated as being
27 def i64i32imm_pcrel : Operand<i64> {
28 let PrintMethod = "print_pcrel_imm";
29 let ParserMatchClass = X86AbsMemAsmOperand;
33 // 64-bits but only 8 bits are significant.
34 def i64i8imm : Operand<i64> {
35 let ParserMatchClass = ImmSExti64i8AsmOperand;
38 def lea64_32mem : Operand<i32> {
39 let PrintMethod = "printi32mem";
40 let AsmOperandLowerMethod = "lower_lea64_32mem";
41 let MIOperandInfo = (ops GR32, i8imm, GR32_NOSP, i32imm, i8imm);
42 let ParserMatchClass = X86MemAsmOperand;
46 // Special i64mem for addresses of load folding tail calls. These are not
47 // allowed to use callee-saved registers since they must be scheduled
48 // after callee-saved register are popped.
49 def i64mem_TC : Operand<i64> {
50 let PrintMethod = "printi64mem";
51 let MIOperandInfo = (ops GR64_TC, i8imm, GR64_TC, i32imm, i8imm);
52 let ParserMatchClass = X86MemAsmOperand;
55 //===----------------------------------------------------------------------===//
56 // Complex Pattern Definitions.
58 def lea64addr : ComplexPattern<i64, 5, "SelectLEAAddr",
59 [add, sub, mul, X86mul_imm, shl, or, frameindex,
62 def tls64addr : ComplexPattern<i64, 5, "SelectTLSADDRAddr",
63 [tglobaltlsaddr], []>;
65 //===----------------------------------------------------------------------===//
69 def i64immSExt8 : PatLeaf<(i64 immSext8)>;
71 def GetLo32XForm : SDNodeXForm<imm, [{
72 // Transformation function: get the low 32 bits.
73 return getI32Imm((unsigned)N->getZExtValue());
76 def i64immSExt32 : PatLeaf<(i64 imm), [{
77 // i64immSExt32 predicate - True if the 64-bit immediate fits in a 32-bit
78 // sign extended field.
79 return (int64_t)N->getZExtValue() == (int32_t)N->getZExtValue();
83 def i64immZExt32 : PatLeaf<(i64 imm), [{
84 // i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit
85 // unsignedsign extended field.
86 return (uint64_t)N->getZExtValue() == (uint32_t)N->getZExtValue();
89 def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>;
90 def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>;
91 def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>;
93 def zextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (zextloadi1 node:$ptr))>;
94 def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>;
95 def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>;
96 def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>;
98 def extloadi64i1 : PatFrag<(ops node:$ptr), (i64 (extloadi1 node:$ptr))>;
99 def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>;
100 def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>;
101 def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>;
103 //===----------------------------------------------------------------------===//
104 // Instruction list...
107 // ADJCALLSTACKDOWN/UP implicitly use/def RSP because they may be expanded into
108 // a stack adjustment and the codegen must know that they may modify the stack
109 // pointer before prolog-epilog rewriting occurs.
110 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
111 // sub / add which can clobber EFLAGS.
112 let Defs = [RSP, EFLAGS], Uses = [RSP] in {
113 def ADJCALLSTACKDOWN64 : I<0, Pseudo, (outs), (ins i32imm:$amt),
115 [(X86callseq_start timm:$amt)]>,
116 Requires<[In64BitMode]>;
117 def ADJCALLSTACKUP64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
119 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
120 Requires<[In64BitMode]>;
123 // Interrupt Instructions
124 def IRET64 : RI<0xcf, RawFrm, (outs), (ins), "iret{q}", []>;
126 //===----------------------------------------------------------------------===//
127 // Call Instructions...
130 // All calls clobber the non-callee saved registers. RSP is marked as
131 // a use to prevent stack-pointer assignments that appear immediately
132 // before calls from potentially appearing dead. Uses for argument
133 // registers are added manually.
134 let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
135 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
136 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
137 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
138 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
141 // NOTE: this pattern doesn't match "X86call imm", because we do not know
142 // that the offset between an arbitrary immediate and the call will fit in
143 // the 32-bit pcrel field that we have.
144 def CALL64pcrel32 : Ii32PCRel<0xE8, RawFrm,
145 (outs), (ins i64i32imm_pcrel:$dst, variable_ops),
146 "call{q}\t$dst", []>,
147 Requires<[In64BitMode, NotWin64]>;
148 def CALL64r : I<0xFF, MRM2r, (outs), (ins GR64:$dst, variable_ops),
149 "call{q}\t{*}$dst", [(X86call GR64:$dst)]>,
150 Requires<[NotWin64]>;
151 def CALL64m : I<0xFF, MRM2m, (outs), (ins i64mem:$dst, variable_ops),
152 "call{q}\t{*}$dst", [(X86call (loadi64 addr:$dst))]>,
153 Requires<[NotWin64]>;
155 def FARCALL64 : RI<0xFF, MRM3m, (outs), (ins opaque80mem:$dst),
156 "lcall{q}\t{*}$dst", []>;
159 // FIXME: We need to teach codegen about single list of call-clobbered
162 // All calls clobber the non-callee saved registers. RSP is marked as
163 // a use to prevent stack-pointer assignments that appear immediately
164 // before calls from potentially appearing dead. Uses for argument
165 // registers are added manually.
166 let Defs = [RAX, RCX, RDX, R8, R9, R10, R11,
167 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
168 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
169 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, EFLAGS],
171 def WINCALL64pcrel32 : I<0xE8, RawFrm,
172 (outs), (ins i64i32imm_pcrel:$dst, variable_ops),
175 def WINCALL64r : I<0xFF, MRM2r, (outs), (ins GR64:$dst, variable_ops),
177 [(X86call GR64:$dst)]>, Requires<[IsWin64]>;
178 def WINCALL64m : I<0xFF, MRM2m, (outs),
179 (ins i64mem:$dst, variable_ops), "call\t{*}$dst",
180 [(X86call (loadi64 addr:$dst))]>,
185 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
186 let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
187 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
188 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
189 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
190 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
192 def TCRETURNdi64 : I<0, Pseudo, (outs),
193 (ins i64i32imm_pcrel:$dst, i32imm:$offset, variable_ops),
194 "#TC_RETURN $dst $offset", []>;
195 def TCRETURNri64 : I<0, Pseudo, (outs), (ins GR64_TC:$dst, i32imm:$offset,
197 "#TC_RETURN $dst $offset", []>;
199 def TCRETURNmi64 : I<0, Pseudo, (outs),
200 (ins i64mem_TC:$dst, i32imm:$offset, variable_ops),
201 "#TC_RETURN $dst $offset", []>;
203 def TAILJMPd64 : Ii32PCRel<0xE9, RawFrm, (outs),
204 (ins i64i32imm_pcrel:$dst, variable_ops),
205 "jmp\t$dst # TAILCALL", []>;
206 def TAILJMPr64 : I<0xFF, MRM4r, (outs), (ins GR64_TC:$dst, variable_ops),
207 "jmp{q}\t{*}$dst # TAILCALL", []>;
210 def TAILJMPm64 : I<0xFF, MRM4m, (outs), (ins i64mem_TC:$dst, variable_ops),
211 "jmp{q}\t{*}$dst # TAILCALL", []>;
215 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
216 def JMP64pcrel32 : I<0xE9, RawFrm, (outs), (ins brtarget:$dst),
218 def JMP64r : I<0xFF, MRM4r, (outs), (ins GR64:$dst), "jmp{q}\t{*}$dst",
219 [(brind GR64:$dst)]>;
220 def JMP64m : I<0xFF, MRM4m, (outs), (ins i64mem:$dst), "jmp{q}\t{*}$dst",
221 [(brind (loadi64 addr:$dst))]>;
222 def FARJMP64 : RI<0xFF, MRM5m, (outs), (ins opaque80mem:$dst),
223 "ljmp{q}\t{*}$dst", []>;
226 //===----------------------------------------------------------------------===//
227 // EH Pseudo Instructions
229 let isTerminator = 1, isReturn = 1, isBarrier = 1,
230 hasCtrlDep = 1, isCodeGenOnly = 1 in {
231 def EH_RETURN64 : I<0xC3, RawFrm, (outs), (ins GR64:$addr),
232 "ret\t#eh_return, addr: $addr",
233 [(X86ehret GR64:$addr)]>;
237 //===----------------------------------------------------------------------===//
238 // Miscellaneous Instructions...
241 def POPCNT64rr : RI<0xB8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
242 "popcnt{q}\t{$src, $dst|$dst, $src}", []>, XS;
244 def POPCNT64rm : RI<0xB8, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
245 "popcnt{q}\t{$src, $dst|$dst, $src}", []>, XS;
247 let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, neverHasSideEffects = 1 in
248 def LEAVE64 : I<0xC9, RawFrm,
249 (outs), (ins), "leave", []>;
250 let Defs = [RSP], Uses = [RSP], neverHasSideEffects=1 in {
252 def POP64r : I<0x58, AddRegFrm,
253 (outs GR64:$reg), (ins), "pop{q}\t$reg", []>;
254 def POP64rmr: I<0x8F, MRM0r, (outs GR64:$reg), (ins), "pop{q}\t$reg", []>;
255 def POP64rmm: I<0x8F, MRM0m, (outs i64mem:$dst), (ins), "pop{q}\t$dst", []>;
257 let mayStore = 1 in {
258 def PUSH64r : I<0x50, AddRegFrm,
259 (outs), (ins GR64:$reg), "push{q}\t$reg", []>;
260 def PUSH64rmr: I<0xFF, MRM6r, (outs), (ins GR64:$reg), "push{q}\t$reg", []>;
261 def PUSH64rmm: I<0xFF, MRM6m, (outs), (ins i64mem:$src), "push{q}\t$src", []>;
265 let Defs = [RSP], Uses = [RSP], neverHasSideEffects = 1, mayStore = 1 in {
266 def PUSH64i8 : Ii8<0x6a, RawFrm, (outs), (ins i8imm:$imm),
267 "push{q}\t$imm", []>;
268 def PUSH64i16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
269 "push{q}\t$imm", []>;
270 def PUSH64i32 : Ii32<0x68, RawFrm, (outs), (ins i64i32imm:$imm),
271 "push{q}\t$imm", []>;
274 let Defs = [RSP, EFLAGS], Uses = [RSP], mayLoad = 1, neverHasSideEffects=1 in
275 def POPF64 : I<0x9D, RawFrm, (outs), (ins), "popfq", []>,
276 Requires<[In64BitMode]>;
277 let Defs = [RSP], Uses = [RSP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in
278 def PUSHF64 : I<0x9C, RawFrm, (outs), (ins), "pushfq", []>,
279 Requires<[In64BitMode]>;
281 def LEA64_32r : I<0x8D, MRMSrcMem,
282 (outs GR32:$dst), (ins lea64_32mem:$src),
283 "lea{l}\t{$src|$dst}, {$dst|$src}",
284 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In64BitMode]>;
286 let isReMaterializable = 1 in
287 def LEA64r : RI<0x8D, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
288 "lea{q}\t{$src|$dst}, {$dst|$src}",
289 [(set GR64:$dst, lea64addr:$src)]>;
291 let Constraints = "$src = $dst" in
292 def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src),
294 [(set GR64:$dst, (bswap GR64:$src))]>, TB;
296 // Bit scan instructions.
297 let Defs = [EFLAGS] in {
298 def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
299 "bsf{q}\t{$src, $dst|$dst, $src}",
300 [(set GR64:$dst, EFLAGS, (X86bsf GR64:$src))]>, TB;
301 def BSF64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
302 "bsf{q}\t{$src, $dst|$dst, $src}",
303 [(set GR64:$dst, EFLAGS, (X86bsf (loadi64 addr:$src)))]>, TB;
305 def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
306 "bsr{q}\t{$src, $dst|$dst, $src}",
307 [(set GR64:$dst, EFLAGS, (X86bsr GR64:$src))]>, TB;
308 def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
309 "bsr{q}\t{$src, $dst|$dst, $src}",
310 [(set GR64:$dst, EFLAGS, (X86bsr (loadi64 addr:$src)))]>, TB;
314 let Defs = [RCX,RDI,RSI], Uses = [RCX,RDI,RSI], isCodeGenOnly = 1 in
315 def REP_MOVSQ : RI<0xA5, RawFrm, (outs), (ins), "{rep;movsq|rep movsq}",
316 [(X86rep_movs i64)]>, REP;
317 let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI], isCodeGenOnly = 1 in
318 def REP_STOSQ : RI<0xAB, RawFrm, (outs), (ins), "{rep;stosq|rep stosq}",
319 [(X86rep_stos i64)]>, REP;
321 let Defs = [EDI,ESI], Uses = [EDI,ESI,EFLAGS] in
322 def MOVSQ : RI<0xA5, RawFrm, (outs), (ins), "movsq", []>;
324 let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI,EFLAGS] in
325 def STOSQ : RI<0xAB, RawFrm, (outs), (ins), "stosq", []>;
327 def SCAS64 : RI<0xAF, RawFrm, (outs), (ins), "scasq", []>;
329 def CMPS64 : RI<0xA7, RawFrm, (outs), (ins), "cmpsq", []>;
331 // Fast system-call instructions
332 def SYSEXIT64 : RI<0x35, RawFrm,
333 (outs), (ins), "sysexit", []>, TB;
335 //===----------------------------------------------------------------------===//
336 // Move Instructions...
339 let neverHasSideEffects = 1 in
340 def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
341 "mov{q}\t{$src, $dst|$dst, $src}", []>;
343 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
344 def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src),
345 "movabs{q}\t{$src, $dst|$dst, $src}",
346 [(set GR64:$dst, imm:$src)]>;
347 def MOV64ri32 : RIi32<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src),
348 "mov{q}\t{$src, $dst|$dst, $src}",
349 [(set GR64:$dst, i64immSExt32:$src)]>;
352 // The assembler accepts movq of a 64-bit immediate as an alternate spelling of
354 let isAsmParserOnly = 1 in {
355 def MOV64ri_alt : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src),
356 "mov{q}\t{$src, $dst|$dst, $src}", []>;
359 let isCodeGenOnly = 1 in {
360 def MOV64rr_REV : RI<0x8B, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
361 "mov{q}\t{$src, $dst|$dst, $src}", []>;
364 let canFoldAsLoad = 1, isReMaterializable = 1 in
365 def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
366 "mov{q}\t{$src, $dst|$dst, $src}",
367 [(set GR64:$dst, (load addr:$src))]>;
369 def MOV64mr : RI<0x89, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
370 "mov{q}\t{$src, $dst|$dst, $src}",
371 [(store GR64:$src, addr:$dst)]>;
372 def MOV64mi32 : RIi32<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src),
373 "mov{q}\t{$src, $dst|$dst, $src}",
374 [(store i64immSExt32:$src, addr:$dst)]>;
376 /// Versions of MOV64rr, MOV64rm, and MOV64mr for i64mem_TC and GR64_TC.
377 let neverHasSideEffects = 1 in
378 def MOV64rr_TC : RI<0x89, MRMDestReg, (outs GR64_TC:$dst), (ins GR64_TC:$src),
379 "mov{q}\t{$src, $dst|$dst, $src}", []>;
382 canFoldAsLoad = 1, isReMaterializable = 1 in
383 def MOV64rm_TC : RI<0x8B, MRMSrcMem, (outs GR64_TC:$dst), (ins i64mem_TC:$src),
384 "mov{q}\t{$src, $dst|$dst, $src}",
388 def MOV64mr_TC : RI<0x89, MRMDestMem, (outs), (ins i64mem_TC:$dst, GR64_TC:$src),
389 "mov{q}\t{$src, $dst|$dst, $src}",
392 def MOV64o8a : RIi8<0xA0, RawFrm, (outs), (ins offset8:$src),
393 "mov{q}\t{$src, %rax|%rax, $src}", []>;
394 def MOV64o64a : RIi32<0xA1, RawFrm, (outs), (ins offset64:$src),
395 "mov{q}\t{$src, %rax|%rax, $src}", []>;
396 def MOV64ao8 : RIi8<0xA2, RawFrm, (outs offset8:$dst), (ins),
397 "mov{q}\t{%rax, $dst|$dst, %rax}", []>;
398 def MOV64ao64 : RIi32<0xA3, RawFrm, (outs offset64:$dst), (ins),
399 "mov{q}\t{%rax, $dst|$dst, %rax}", []>;
401 // Moves to and from segment registers
402 def MOV64rs : RI<0x8C, MRMDestReg, (outs GR64:$dst), (ins SEGMENT_REG:$src),
403 "mov{q}\t{$src, $dst|$dst, $src}", []>;
404 def MOV64ms : RI<0x8C, MRMDestMem, (outs i64mem:$dst), (ins SEGMENT_REG:$src),
405 "mov{q}\t{$src, $dst|$dst, $src}", []>;
406 def MOV64sr : RI<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR64:$src),
407 "mov{q}\t{$src, $dst|$dst, $src}", []>;
408 def MOV64sm : RI<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i64mem:$src),
409 "mov{q}\t{$src, $dst|$dst, $src}", []>;
411 // Moves to and from debug registers
412 def MOV64rd : I<0x21, MRMDestReg, (outs GR64:$dst), (ins DEBUG_REG:$src),
413 "mov{q}\t{$src, $dst|$dst, $src}", []>, TB;
414 def MOV64dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR64:$src),
415 "mov{q}\t{$src, $dst|$dst, $src}", []>, TB;
417 // Moves to and from control registers
418 def MOV64rc : I<0x20, MRMDestReg, (outs GR64:$dst), (ins CONTROL_REG:$src),
419 "mov{q}\t{$src, $dst|$dst, $src}", []>, TB;
420 def MOV64cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR64:$src),
421 "mov{q}\t{$src, $dst|$dst, $src}", []>, TB;
423 // Sign/Zero extenders
425 // MOVSX64rr8 always has a REX prefix and it has an 8-bit register
426 // operand, which makes it a rare instruction with an 8-bit register
427 // operand that can never access an h register. If support for h registers
428 // were generalized, this would require a special register class.
429 def MOVSX64rr8 : RI<0xBE, MRMSrcReg, (outs GR64:$dst), (ins GR8 :$src),
430 "movs{bq|x}\t{$src, $dst|$dst, $src}",
431 [(set GR64:$dst, (sext GR8:$src))]>, TB;
432 def MOVSX64rm8 : RI<0xBE, MRMSrcMem, (outs GR64:$dst), (ins i8mem :$src),
433 "movs{bq|x}\t{$src, $dst|$dst, $src}",
434 [(set GR64:$dst, (sextloadi64i8 addr:$src))]>, TB;
435 def MOVSX64rr16: RI<0xBF, MRMSrcReg, (outs GR64:$dst), (ins GR16:$src),
436 "movs{wq|x}\t{$src, $dst|$dst, $src}",
437 [(set GR64:$dst, (sext GR16:$src))]>, TB;
438 def MOVSX64rm16: RI<0xBF, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
439 "movs{wq|x}\t{$src, $dst|$dst, $src}",
440 [(set GR64:$dst, (sextloadi64i16 addr:$src))]>, TB;
441 def MOVSX64rr32: RI<0x63, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src),
442 "movs{lq|xd}\t{$src, $dst|$dst, $src}",
443 [(set GR64:$dst, (sext GR32:$src))]>;
444 def MOVSX64rm32: RI<0x63, MRMSrcMem, (outs GR64:$dst), (ins i32mem:$src),
445 "movs{lq|xd}\t{$src, $dst|$dst, $src}",
446 [(set GR64:$dst, (sextloadi64i32 addr:$src))]>;
448 // movzbq and movzwq encodings for the disassembler
449 def MOVZX64rr8_Q : RI<0xB6, MRMSrcReg, (outs GR64:$dst), (ins GR8:$src),
450 "movz{bq|x}\t{$src, $dst|$dst, $src}", []>, TB;
451 def MOVZX64rm8_Q : RI<0xB6, MRMSrcMem, (outs GR64:$dst), (ins i8mem:$src),
452 "movz{bq|x}\t{$src, $dst|$dst, $src}", []>, TB;
453 def MOVZX64rr16_Q : RI<0xB7, MRMSrcReg, (outs GR64:$dst), (ins GR16:$src),
454 "movz{wq|x}\t{$src, $dst|$dst, $src}", []>, TB;
455 def MOVZX64rm16_Q : RI<0xB7, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
456 "movz{wq|x}\t{$src, $dst|$dst, $src}", []>, TB;
458 // Use movzbl instead of movzbq when the destination is a register; it's
459 // equivalent due to implicit zero-extending, and it has a smaller encoding.
460 def MOVZX64rr8 : I<0xB6, MRMSrcReg, (outs GR64:$dst), (ins GR8 :$src),
461 "", [(set GR64:$dst, (zext GR8:$src))]>, TB;
462 def MOVZX64rm8 : I<0xB6, MRMSrcMem, (outs GR64:$dst), (ins i8mem :$src),
463 "", [(set GR64:$dst, (zextloadi64i8 addr:$src))]>, TB;
464 // Use movzwl instead of movzwq when the destination is a register; it's
465 // equivalent due to implicit zero-extending, and it has a smaller encoding.
466 def MOVZX64rr16: I<0xB7, MRMSrcReg, (outs GR64:$dst), (ins GR16:$src),
467 "", [(set GR64:$dst, (zext GR16:$src))]>, TB;
468 def MOVZX64rm16: I<0xB7, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
469 "", [(set GR64:$dst, (zextloadi64i16 addr:$src))]>, TB;
471 // There's no movzlq instruction, but movl can be used for this purpose, using
472 // implicit zero-extension. The preferred way to do 32-bit-to-64-bit zero
473 // extension on x86-64 is to use a SUBREG_TO_REG to utilize implicit
474 // zero-extension, however this isn't possible when the 32-bit value is
475 // defined by a truncate or is copied from something where the high bits aren't
476 // necessarily all zero. In such cases, we fall back to these explicit zext
478 def MOVZX64rr32 : I<0x89, MRMDestReg, (outs GR64:$dst), (ins GR32:$src),
479 "", [(set GR64:$dst, (zext GR32:$src))]>;
480 def MOVZX64rm32 : I<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i32mem:$src),
481 "", [(set GR64:$dst, (zextloadi64i32 addr:$src))]>;
483 // Any instruction that defines a 32-bit result leaves the high half of the
484 // register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may
485 // be copying from a truncate. And x86's cmov doesn't do anything if the
486 // condition is false. But any other 32-bit operation will zero-extend
488 def def32 : PatLeaf<(i32 GR32:$src), [{
489 return N->getOpcode() != ISD::TRUNCATE &&
490 N->getOpcode() != TargetOpcode::EXTRACT_SUBREG &&
491 N->getOpcode() != ISD::CopyFromReg &&
492 N->getOpcode() != X86ISD::CMOV;
495 // In the case of a 32-bit def that is known to implicitly zero-extend,
496 // we can use a SUBREG_TO_REG.
497 def : Pat<(i64 (zext def32:$src)),
498 (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>;
500 let neverHasSideEffects = 1 in {
501 let Defs = [RAX], Uses = [EAX] in
502 def CDQE : RI<0x98, RawFrm, (outs), (ins),
503 "{cltq|cdqe}", []>; // RAX = signext(EAX)
505 let Defs = [RAX,RDX], Uses = [RAX] in
506 def CQO : RI<0x99, RawFrm, (outs), (ins),
507 "{cqto|cqo}", []>; // RDX:RAX = signext(RAX)
510 //===----------------------------------------------------------------------===//
511 // Arithmetic Instructions...
514 let Defs = [EFLAGS] in {
516 def ADD64i32 : RIi32<0x05, RawFrm, (outs), (ins i64i32imm:$src),
517 "add{q}\t{$src, %rax|%rax, $src}", []>;
519 let Constraints = "$src1 = $dst" in {
520 let isConvertibleToThreeAddress = 1 in {
521 let isCommutable = 1 in
522 // Register-Register Addition
523 def ADD64rr : RI<0x01, MRMDestReg, (outs GR64:$dst),
524 (ins GR64:$src1, GR64:$src2),
525 "add{q}\t{$src2, $dst|$dst, $src2}",
526 [(set GR64:$dst, EFLAGS,
527 (X86add_flag GR64:$src1, GR64:$src2))]>;
529 // These are alternate spellings for use by the disassembler, we mark them as
530 // code gen only to ensure they aren't matched by the assembler.
531 let isCodeGenOnly = 1 in {
532 def ADD64rr_alt : RI<0x03, MRMSrcReg, (outs GR64:$dst),
533 (ins GR64:$src1, GR64:$src2),
534 "add{l}\t{$src2, $dst|$dst, $src2}", []>;
537 // Register-Integer Addition
538 def ADD64ri8 : RIi8<0x83, MRM0r, (outs GR64:$dst),
539 (ins GR64:$src1, i64i8imm:$src2),
540 "add{q}\t{$src2, $dst|$dst, $src2}",
541 [(set GR64:$dst, EFLAGS,
542 (X86add_flag GR64:$src1, i64immSExt8:$src2))]>;
543 def ADD64ri32 : RIi32<0x81, MRM0r, (outs GR64:$dst),
544 (ins GR64:$src1, i64i32imm:$src2),
545 "add{q}\t{$src2, $dst|$dst, $src2}",
546 [(set GR64:$dst, EFLAGS,
547 (X86add_flag GR64:$src1, i64immSExt32:$src2))]>;
548 } // isConvertibleToThreeAddress
550 // Register-Memory Addition
551 def ADD64rm : RI<0x03, MRMSrcMem, (outs GR64:$dst),
552 (ins GR64:$src1, i64mem:$src2),
553 "add{q}\t{$src2, $dst|$dst, $src2}",
554 [(set GR64:$dst, EFLAGS,
555 (X86add_flag GR64:$src1, (load addr:$src2)))]>;
557 } // Constraints = "$src1 = $dst"
559 // Memory-Register Addition
560 def ADD64mr : RI<0x01, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
561 "add{q}\t{$src2, $dst|$dst, $src2}",
562 [(store (add (load addr:$dst), GR64:$src2), addr:$dst),
564 def ADD64mi8 : RIi8<0x83, MRM0m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
565 "add{q}\t{$src2, $dst|$dst, $src2}",
566 [(store (add (load addr:$dst), i64immSExt8:$src2), addr:$dst),
568 def ADD64mi32 : RIi32<0x81, MRM0m, (outs), (ins i64mem:$dst, i64i32imm :$src2),
569 "add{q}\t{$src2, $dst|$dst, $src2}",
570 [(store (add (load addr:$dst), i64immSExt32:$src2), addr:$dst),
573 let Uses = [EFLAGS] in {
575 def ADC64i32 : RIi32<0x15, RawFrm, (outs), (ins i64i32imm:$src),
576 "adc{q}\t{$src, %rax|%rax, $src}", []>;
578 let Constraints = "$src1 = $dst" in {
579 let isCommutable = 1 in
580 def ADC64rr : RI<0x11, MRMDestReg, (outs GR64:$dst),
581 (ins GR64:$src1, GR64:$src2),
582 "adc{q}\t{$src2, $dst|$dst, $src2}",
583 [(set GR64:$dst, (adde GR64:$src1, GR64:$src2))]>;
585 let isCodeGenOnly = 1 in {
586 def ADC64rr_REV : RI<0x13, MRMSrcReg , (outs GR32:$dst),
587 (ins GR64:$src1, GR64:$src2),
588 "adc{q}\t{$src2, $dst|$dst, $src2}", []>;
591 def ADC64rm : RI<0x13, MRMSrcMem , (outs GR64:$dst),
592 (ins GR64:$src1, i64mem:$src2),
593 "adc{q}\t{$src2, $dst|$dst, $src2}",
594 [(set GR64:$dst, (adde GR64:$src1, (load addr:$src2)))]>;
596 def ADC64ri8 : RIi8<0x83, MRM2r, (outs GR64:$dst),
597 (ins GR64:$src1, i64i8imm:$src2),
598 "adc{q}\t{$src2, $dst|$dst, $src2}",
599 [(set GR64:$dst, (adde GR64:$src1, i64immSExt8:$src2))]>;
600 def ADC64ri32 : RIi32<0x81, MRM2r, (outs GR64:$dst),
601 (ins GR64:$src1, i64i32imm:$src2),
602 "adc{q}\t{$src2, $dst|$dst, $src2}",
603 [(set GR64:$dst, (adde GR64:$src1, i64immSExt32:$src2))]>;
604 } // Constraints = "$src1 = $dst"
606 def ADC64mr : RI<0x11, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
607 "adc{q}\t{$src2, $dst|$dst, $src2}",
608 [(store (adde (load addr:$dst), GR64:$src2), addr:$dst)]>;
609 def ADC64mi8 : RIi8<0x83, MRM2m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
610 "adc{q}\t{$src2, $dst|$dst, $src2}",
611 [(store (adde (load addr:$dst), i64immSExt8:$src2),
613 def ADC64mi32 : RIi32<0x81, MRM2m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
614 "adc{q}\t{$src2, $dst|$dst, $src2}",
615 [(store (adde (load addr:$dst), i64immSExt32:$src2),
619 let Constraints = "$src1 = $dst" in {
620 // Register-Register Subtraction
621 def SUB64rr : RI<0x29, MRMDestReg, (outs GR64:$dst),
622 (ins GR64:$src1, GR64:$src2),
623 "sub{q}\t{$src2, $dst|$dst, $src2}",
624 [(set GR64:$dst, EFLAGS,
625 (X86sub_flag GR64:$src1, GR64:$src2))]>;
627 let isCodeGenOnly = 1 in {
628 def SUB64rr_REV : RI<0x2B, MRMSrcReg, (outs GR64:$dst),
629 (ins GR64:$src1, GR64:$src2),
630 "sub{q}\t{$src2, $dst|$dst, $src2}", []>;
633 // Register-Memory Subtraction
634 def SUB64rm : RI<0x2B, MRMSrcMem, (outs GR64:$dst),
635 (ins GR64:$src1, i64mem:$src2),
636 "sub{q}\t{$src2, $dst|$dst, $src2}",
637 [(set GR64:$dst, EFLAGS,
638 (X86sub_flag GR64:$src1, (load addr:$src2)))]>;
640 // Register-Integer Subtraction
641 def SUB64ri8 : RIi8<0x83, MRM5r, (outs GR64:$dst),
642 (ins GR64:$src1, i64i8imm:$src2),
643 "sub{q}\t{$src2, $dst|$dst, $src2}",
644 [(set GR64:$dst, EFLAGS,
645 (X86sub_flag GR64:$src1, i64immSExt8:$src2))]>;
646 def SUB64ri32 : RIi32<0x81, MRM5r, (outs GR64:$dst),
647 (ins GR64:$src1, i64i32imm:$src2),
648 "sub{q}\t{$src2, $dst|$dst, $src2}",
649 [(set GR64:$dst, EFLAGS,
650 (X86sub_flag GR64:$src1, i64immSExt32:$src2))]>;
651 } // Constraints = "$src1 = $dst"
653 def SUB64i32 : RIi32<0x2D, RawFrm, (outs), (ins i64i32imm:$src),
654 "sub{q}\t{$src, %rax|%rax, $src}", []>;
656 // Memory-Register Subtraction
657 def SUB64mr : RI<0x29, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
658 "sub{q}\t{$src2, $dst|$dst, $src2}",
659 [(store (sub (load addr:$dst), GR64:$src2), addr:$dst),
662 // Memory-Integer Subtraction
663 def SUB64mi8 : RIi8<0x83, MRM5m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
664 "sub{q}\t{$src2, $dst|$dst, $src2}",
665 [(store (sub (load addr:$dst), i64immSExt8:$src2),
668 def SUB64mi32 : RIi32<0x81, MRM5m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
669 "sub{q}\t{$src2, $dst|$dst, $src2}",
670 [(store (sub (load addr:$dst), i64immSExt32:$src2),
674 let Uses = [EFLAGS] in {
675 let Constraints = "$src1 = $dst" in {
676 def SBB64rr : RI<0x19, MRMDestReg, (outs GR64:$dst),
677 (ins GR64:$src1, GR64:$src2),
678 "sbb{q}\t{$src2, $dst|$dst, $src2}",
679 [(set GR64:$dst, (sube GR64:$src1, GR64:$src2))]>;
681 let isCodeGenOnly = 1 in {
682 def SBB64rr_REV : RI<0x1B, MRMSrcReg, (outs GR64:$dst),
683 (ins GR64:$src1, GR64:$src2),
684 "sbb{q}\t{$src2, $dst|$dst, $src2}", []>;
687 def SBB64rm : RI<0x1B, MRMSrcMem, (outs GR64:$dst),
688 (ins GR64:$src1, i64mem:$src2),
689 "sbb{q}\t{$src2, $dst|$dst, $src2}",
690 [(set GR64:$dst, (sube GR64:$src1, (load addr:$src2)))]>;
692 def SBB64ri8 : RIi8<0x83, MRM3r, (outs GR64:$dst),
693 (ins GR64:$src1, i64i8imm:$src2),
694 "sbb{q}\t{$src2, $dst|$dst, $src2}",
695 [(set GR64:$dst, (sube GR64:$src1, i64immSExt8:$src2))]>;
696 def SBB64ri32 : RIi32<0x81, MRM3r, (outs GR64:$dst),
697 (ins GR64:$src1, i64i32imm:$src2),
698 "sbb{q}\t{$src2, $dst|$dst, $src2}",
699 [(set GR64:$dst, (sube GR64:$src1, i64immSExt32:$src2))]>;
700 } // Constraints = "$src1 = $dst"
702 def SBB64i32 : RIi32<0x1D, RawFrm, (outs), (ins i64i32imm:$src),
703 "sbb{q}\t{$src, %rax|%rax, $src}", []>;
705 def SBB64mr : RI<0x19, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
706 "sbb{q}\t{$src2, $dst|$dst, $src2}",
707 [(store (sube (load addr:$dst), GR64:$src2), addr:$dst)]>;
708 def SBB64mi8 : RIi8<0x83, MRM3m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
709 "sbb{q}\t{$src2, $dst|$dst, $src2}",
710 [(store (sube (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>;
711 def SBB64mi32 : RIi32<0x81, MRM3m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
712 "sbb{q}\t{$src2, $dst|$dst, $src2}",
713 [(store (sube (load addr:$dst), i64immSExt32:$src2), addr:$dst)]>;
717 // Unsigned multiplication
718 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], neverHasSideEffects = 1 in {
719 def MUL64r : RI<0xF7, MRM4r, (outs), (ins GR64:$src),
720 "mul{q}\t$src", []>; // RAX,RDX = RAX*GR64
722 def MUL64m : RI<0xF7, MRM4m, (outs), (ins i64mem:$src),
723 "mul{q}\t$src", []>; // RAX,RDX = RAX*[mem64]
725 // Signed multiplication
726 def IMUL64r : RI<0xF7, MRM5r, (outs), (ins GR64:$src),
727 "imul{q}\t$src", []>; // RAX,RDX = RAX*GR64
729 def IMUL64m : RI<0xF7, MRM5m, (outs), (ins i64mem:$src),
730 "imul{q}\t$src", []>; // RAX,RDX = RAX*[mem64]
733 let Defs = [EFLAGS] in {
734 let Constraints = "$src1 = $dst" in {
735 let isCommutable = 1 in
736 // Register-Register Signed Integer Multiplication
737 def IMUL64rr : RI<0xAF, MRMSrcReg, (outs GR64:$dst),
738 (ins GR64:$src1, GR64:$src2),
739 "imul{q}\t{$src2, $dst|$dst, $src2}",
740 [(set GR64:$dst, EFLAGS,
741 (X86smul_flag GR64:$src1, GR64:$src2))]>, TB;
743 // Register-Memory Signed Integer Multiplication
744 def IMUL64rm : RI<0xAF, MRMSrcMem, (outs GR64:$dst),
745 (ins GR64:$src1, i64mem:$src2),
746 "imul{q}\t{$src2, $dst|$dst, $src2}",
747 [(set GR64:$dst, EFLAGS,
748 (X86smul_flag GR64:$src1, (load addr:$src2)))]>, TB;
749 } // Constraints = "$src1 = $dst"
751 // Suprisingly enough, these are not two address instructions!
753 // Register-Integer Signed Integer Multiplication
754 def IMUL64rri8 : RIi8<0x6B, MRMSrcReg, // GR64 = GR64*I8
755 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
756 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
757 [(set GR64:$dst, EFLAGS,
758 (X86smul_flag GR64:$src1, i64immSExt8:$src2))]>;
759 def IMUL64rri32 : RIi32<0x69, MRMSrcReg, // GR64 = GR64*I32
760 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
761 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
762 [(set GR64:$dst, EFLAGS,
763 (X86smul_flag GR64:$src1, i64immSExt32:$src2))]>;
765 // Memory-Integer Signed Integer Multiplication
766 def IMUL64rmi8 : RIi8<0x6B, MRMSrcMem, // GR64 = [mem64]*I8
767 (outs GR64:$dst), (ins i64mem:$src1, i64i8imm: $src2),
768 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
769 [(set GR64:$dst, EFLAGS,
770 (X86smul_flag (load addr:$src1),
771 i64immSExt8:$src2))]>;
772 def IMUL64rmi32 : RIi32<0x69, MRMSrcMem, // GR64 = [mem64]*I32
773 (outs GR64:$dst), (ins i64mem:$src1, i64i32imm:$src2),
774 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
775 [(set GR64:$dst, EFLAGS,
776 (X86smul_flag (load addr:$src1),
777 i64immSExt32:$src2))]>;
780 // Unsigned division / remainder
781 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in {
782 // RDX:RAX/r64 = RAX,RDX
783 def DIV64r : RI<0xF7, MRM6r, (outs), (ins GR64:$src),
785 // Signed division / remainder
786 // RDX:RAX/r64 = RAX,RDX
787 def IDIV64r: RI<0xF7, MRM7r, (outs), (ins GR64:$src),
788 "idiv{q}\t$src", []>;
790 // RDX:RAX/[mem64] = RAX,RDX
791 def DIV64m : RI<0xF7, MRM6m, (outs), (ins i64mem:$src),
793 // RDX:RAX/[mem64] = RAX,RDX
794 def IDIV64m: RI<0xF7, MRM7m, (outs), (ins i64mem:$src),
795 "idiv{q}\t$src", []>;
799 // Unary instructions
800 let Defs = [EFLAGS], CodeSize = 2 in {
801 let Constraints = "$src = $dst" in
802 def NEG64r : RI<0xF7, MRM3r, (outs GR64:$dst), (ins GR64:$src), "neg{q}\t$dst",
803 [(set GR64:$dst, (ineg GR64:$src)),
805 def NEG64m : RI<0xF7, MRM3m, (outs), (ins i64mem:$dst), "neg{q}\t$dst",
806 [(store (ineg (loadi64 addr:$dst)), addr:$dst),
809 let Constraints = "$src = $dst", isConvertibleToThreeAddress = 1 in
810 def INC64r : RI<0xFF, MRM0r, (outs GR64:$dst), (ins GR64:$src), "inc{q}\t$dst",
811 [(set GR64:$dst, EFLAGS, (X86inc_flag GR64:$src))]>;
812 def INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst), "inc{q}\t$dst",
813 [(store (add (loadi64 addr:$dst), 1), addr:$dst),
816 let Constraints = "$src = $dst", isConvertibleToThreeAddress = 1 in
817 def DEC64r : RI<0xFF, MRM1r, (outs GR64:$dst), (ins GR64:$src), "dec{q}\t$dst",
818 [(set GR64:$dst, EFLAGS, (X86dec_flag GR64:$src))]>;
819 def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst",
820 [(store (add (loadi64 addr:$dst), -1), addr:$dst),
823 // In 64-bit mode, single byte INC and DEC cannot be encoded.
824 let Constraints = "$src = $dst", isConvertibleToThreeAddress = 1 in {
825 // Can transform into LEA.
826 def INC64_16r : I<0xFF, MRM0r, (outs GR16:$dst), (ins GR16:$src),
828 [(set GR16:$dst, EFLAGS, (X86inc_flag GR16:$src))]>,
829 OpSize, Requires<[In64BitMode]>;
830 def INC64_32r : I<0xFF, MRM0r, (outs GR32:$dst), (ins GR32:$src),
832 [(set GR32:$dst, EFLAGS, (X86inc_flag GR32:$src))]>,
833 Requires<[In64BitMode]>;
834 def DEC64_16r : I<0xFF, MRM1r, (outs GR16:$dst), (ins GR16:$src),
836 [(set GR16:$dst, EFLAGS, (X86dec_flag GR16:$src))]>,
837 OpSize, Requires<[In64BitMode]>;
838 def DEC64_32r : I<0xFF, MRM1r, (outs GR32:$dst), (ins GR32:$src),
840 [(set GR32:$dst, EFLAGS, (X86dec_flag GR32:$src))]>,
841 Requires<[In64BitMode]>;
842 } // Constraints = "$src = $dst", isConvertibleToThreeAddress
844 // These are duplicates of their 32-bit counterparts. Only needed so X86 knows
845 // how to unfold them.
846 def INC64_16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
847 [(store (add (loadi16 addr:$dst), 1), addr:$dst),
849 OpSize, Requires<[In64BitMode]>;
850 def INC64_32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
851 [(store (add (loadi32 addr:$dst), 1), addr:$dst),
853 Requires<[In64BitMode]>;
854 def DEC64_16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
855 [(store (add (loadi16 addr:$dst), -1), addr:$dst),
857 OpSize, Requires<[In64BitMode]>;
858 def DEC64_32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
859 [(store (add (loadi32 addr:$dst), -1), addr:$dst),
861 Requires<[In64BitMode]>;
862 } // Defs = [EFLAGS], CodeSize
865 let Defs = [EFLAGS] in {
866 // Shift instructions
867 let Constraints = "$src1 = $dst" in {
869 def SHL64rCL : RI<0xD3, MRM4r, (outs GR64:$dst), (ins GR64:$src1),
870 "shl{q}\t{%cl, $dst|$dst, %CL}",
871 [(set GR64:$dst, (shl GR64:$src1, CL))]>;
872 let isConvertibleToThreeAddress = 1 in // Can transform into LEA.
873 def SHL64ri : RIi8<0xC1, MRM4r, (outs GR64:$dst),
874 (ins GR64:$src1, i8imm:$src2),
875 "shl{q}\t{$src2, $dst|$dst, $src2}",
876 [(set GR64:$dst, (shl GR64:$src1, (i8 imm:$src2)))]>;
877 // NOTE: We don't include patterns for shifts of a register by one, because
878 // 'add reg,reg' is cheaper.
879 def SHL64r1 : RI<0xD1, MRM4r, (outs GR64:$dst), (ins GR64:$src1),
881 } // Constraints = "$src1 = $dst"
884 def SHL64mCL : RI<0xD3, MRM4m, (outs), (ins i64mem:$dst),
885 "shl{q}\t{%cl, $dst|$dst, %CL}",
886 [(store (shl (loadi64 addr:$dst), CL), addr:$dst)]>;
887 def SHL64mi : RIi8<0xC1, MRM4m, (outs), (ins i64mem:$dst, i8imm:$src),
888 "shl{q}\t{$src, $dst|$dst, $src}",
889 [(store (shl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
890 def SHL64m1 : RI<0xD1, MRM4m, (outs), (ins i64mem:$dst),
892 [(store (shl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
894 let Constraints = "$src1 = $dst" in {
896 def SHR64rCL : RI<0xD3, MRM5r, (outs GR64:$dst), (ins GR64:$src1),
897 "shr{q}\t{%cl, $dst|$dst, %CL}",
898 [(set GR64:$dst, (srl GR64:$src1, CL))]>;
899 def SHR64ri : RIi8<0xC1, MRM5r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
900 "shr{q}\t{$src2, $dst|$dst, $src2}",
901 [(set GR64:$dst, (srl GR64:$src1, (i8 imm:$src2)))]>;
902 def SHR64r1 : RI<0xD1, MRM5r, (outs GR64:$dst), (ins GR64:$src1),
904 [(set GR64:$dst, (srl GR64:$src1, (i8 1)))]>;
905 } // Constraints = "$src1 = $dst"
908 def SHR64mCL : RI<0xD3, MRM5m, (outs), (ins i64mem:$dst),
909 "shr{q}\t{%cl, $dst|$dst, %CL}",
910 [(store (srl (loadi64 addr:$dst), CL), addr:$dst)]>;
911 def SHR64mi : RIi8<0xC1, MRM5m, (outs), (ins i64mem:$dst, i8imm:$src),
912 "shr{q}\t{$src, $dst|$dst, $src}",
913 [(store (srl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
914 def SHR64m1 : RI<0xD1, MRM5m, (outs), (ins i64mem:$dst),
916 [(store (srl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
918 let Constraints = "$src1 = $dst" in {
920 def SAR64rCL : RI<0xD3, MRM7r, (outs GR64:$dst), (ins GR64:$src1),
921 "sar{q}\t{%cl, $dst|$dst, %CL}",
922 [(set GR64:$dst, (sra GR64:$src1, CL))]>;
923 def SAR64ri : RIi8<0xC1, MRM7r, (outs GR64:$dst),
924 (ins GR64:$src1, i8imm:$src2),
925 "sar{q}\t{$src2, $dst|$dst, $src2}",
926 [(set GR64:$dst, (sra GR64:$src1, (i8 imm:$src2)))]>;
927 def SAR64r1 : RI<0xD1, MRM7r, (outs GR64:$dst), (ins GR64:$src1),
929 [(set GR64:$dst, (sra GR64:$src1, (i8 1)))]>;
930 } // Constraints = "$src = $dst"
933 def SAR64mCL : RI<0xD3, MRM7m, (outs), (ins i64mem:$dst),
934 "sar{q}\t{%cl, $dst|$dst, %CL}",
935 [(store (sra (loadi64 addr:$dst), CL), addr:$dst)]>;
936 def SAR64mi : RIi8<0xC1, MRM7m, (outs), (ins i64mem:$dst, i8imm:$src),
937 "sar{q}\t{$src, $dst|$dst, $src}",
938 [(store (sra (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
939 def SAR64m1 : RI<0xD1, MRM7m, (outs), (ins i64mem:$dst),
941 [(store (sra (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
943 // Rotate instructions
945 let Constraints = "$src = $dst" in {
946 def RCL64r1 : RI<0xD1, MRM2r, (outs GR64:$dst), (ins GR64:$src),
947 "rcl{q}\t{1, $dst|$dst, 1}", []>;
948 def RCL64ri : RIi8<0xC1, MRM2r, (outs GR64:$dst), (ins GR64:$src, i8imm:$cnt),
949 "rcl{q}\t{$cnt, $dst|$dst, $cnt}", []>;
951 def RCR64r1 : RI<0xD1, MRM3r, (outs GR64:$dst), (ins GR64:$src),
952 "rcr{q}\t{1, $dst|$dst, 1}", []>;
953 def RCR64ri : RIi8<0xC1, MRM3r, (outs GR64:$dst), (ins GR64:$src, i8imm:$cnt),
954 "rcr{q}\t{$cnt, $dst|$dst, $cnt}", []>;
957 def RCL64rCL : RI<0xD3, MRM2r, (outs GR64:$dst), (ins GR64:$src),
958 "rcl{q}\t{%cl, $dst|$dst, CL}", []>;
959 def RCR64rCL : RI<0xD3, MRM3r, (outs GR64:$dst), (ins GR64:$src),
960 "rcr{q}\t{%cl, $dst|$dst, CL}", []>;
962 } // Constraints = "$src = $dst"
964 def RCL64m1 : RI<0xD1, MRM2m, (outs), (ins i64mem:$dst),
965 "rcl{q}\t{1, $dst|$dst, 1}", []>;
966 def RCL64mi : RIi8<0xC1, MRM2m, (outs), (ins i64mem:$dst, i8imm:$cnt),
967 "rcl{q}\t{$cnt, $dst|$dst, $cnt}", []>;
968 def RCR64m1 : RI<0xD1, MRM3m, (outs), (ins i64mem:$dst),
969 "rcr{q}\t{1, $dst|$dst, 1}", []>;
970 def RCR64mi : RIi8<0xC1, MRM3m, (outs), (ins i64mem:$dst, i8imm:$cnt),
971 "rcr{q}\t{$cnt, $dst|$dst, $cnt}", []>;
974 def RCL64mCL : RI<0xD3, MRM2m, (outs), (ins i64mem:$dst),
975 "rcl{q}\t{%cl, $dst|$dst, CL}", []>;
976 def RCR64mCL : RI<0xD3, MRM3m, (outs), (ins i64mem:$dst),
977 "rcr{q}\t{%cl, $dst|$dst, CL}", []>;
980 let Constraints = "$src1 = $dst" in {
982 def ROL64rCL : RI<0xD3, MRM0r, (outs GR64:$dst), (ins GR64:$src1),
983 "rol{q}\t{%cl, $dst|$dst, %CL}",
984 [(set GR64:$dst, (rotl GR64:$src1, CL))]>;
985 def ROL64ri : RIi8<0xC1, MRM0r, (outs GR64:$dst),
986 (ins GR64:$src1, i8imm:$src2),
987 "rol{q}\t{$src2, $dst|$dst, $src2}",
988 [(set GR64:$dst, (rotl GR64:$src1, (i8 imm:$src2)))]>;
989 def ROL64r1 : RI<0xD1, MRM0r, (outs GR64:$dst), (ins GR64:$src1),
991 [(set GR64:$dst, (rotl GR64:$src1, (i8 1)))]>;
992 } // Constraints = "$src1 = $dst"
995 def ROL64mCL : RI<0xD3, MRM0m, (outs), (ins i64mem:$dst),
996 "rol{q}\t{%cl, $dst|$dst, %CL}",
997 [(store (rotl (loadi64 addr:$dst), CL), addr:$dst)]>;
998 def ROL64mi : RIi8<0xC1, MRM0m, (outs), (ins i64mem:$dst, i8imm:$src),
999 "rol{q}\t{$src, $dst|$dst, $src}",
1000 [(store (rotl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1001 def ROL64m1 : RI<0xD1, MRM0m, (outs), (ins i64mem:$dst),
1003 [(store (rotl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
1005 let Constraints = "$src1 = $dst" in {
1007 def ROR64rCL : RI<0xD3, MRM1r, (outs GR64:$dst), (ins GR64:$src1),
1008 "ror{q}\t{%cl, $dst|$dst, %CL}",
1009 [(set GR64:$dst, (rotr GR64:$src1, CL))]>;
1010 def ROR64ri : RIi8<0xC1, MRM1r, (outs GR64:$dst),
1011 (ins GR64:$src1, i8imm:$src2),
1012 "ror{q}\t{$src2, $dst|$dst, $src2}",
1013 [(set GR64:$dst, (rotr GR64:$src1, (i8 imm:$src2)))]>;
1014 def ROR64r1 : RI<0xD1, MRM1r, (outs GR64:$dst), (ins GR64:$src1),
1016 [(set GR64:$dst, (rotr GR64:$src1, (i8 1)))]>;
1017 } // Constraints = "$src1 = $dst"
1020 def ROR64mCL : RI<0xD3, MRM1m, (outs), (ins i64mem:$dst),
1021 "ror{q}\t{%cl, $dst|$dst, %CL}",
1022 [(store (rotr (loadi64 addr:$dst), CL), addr:$dst)]>;
1023 def ROR64mi : RIi8<0xC1, MRM1m, (outs), (ins i64mem:$dst, i8imm:$src),
1024 "ror{q}\t{$src, $dst|$dst, $src}",
1025 [(store (rotr (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1026 def ROR64m1 : RI<0xD1, MRM1m, (outs), (ins i64mem:$dst),
1028 [(store (rotr (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
1030 // Double shift instructions (generalizations of rotate)
1031 let Constraints = "$src1 = $dst" in {
1032 let Uses = [CL] in {
1033 def SHLD64rrCL : RI<0xA5, MRMDestReg, (outs GR64:$dst),
1034 (ins GR64:$src1, GR64:$src2),
1035 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1036 [(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2, CL))]>,
1038 def SHRD64rrCL : RI<0xAD, MRMDestReg, (outs GR64:$dst),
1039 (ins GR64:$src1, GR64:$src2),
1040 "shrd{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1041 [(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2, CL))]>,
1045 let isCommutable = 1 in { // FIXME: Update X86InstrInfo::commuteInstruction
1046 def SHLD64rri8 : RIi8<0xA4, MRMDestReg,
1048 (ins GR64:$src1, GR64:$src2, i8imm:$src3),
1049 "shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1050 [(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2,
1053 def SHRD64rri8 : RIi8<0xAC, MRMDestReg,
1055 (ins GR64:$src1, GR64:$src2, i8imm:$src3),
1056 "shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1057 [(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2,
1061 } // Constraints = "$src1 = $dst"
1063 let Uses = [CL] in {
1064 def SHLD64mrCL : RI<0xA5, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
1065 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1066 [(store (X86shld (loadi64 addr:$dst), GR64:$src2, CL),
1068 def SHRD64mrCL : RI<0xAD, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
1069 "shrd{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1070 [(store (X86shrd (loadi64 addr:$dst), GR64:$src2, CL),
1073 def SHLD64mri8 : RIi8<0xA4, MRMDestMem,
1074 (outs), (ins i64mem:$dst, GR64:$src2, i8imm:$src3),
1075 "shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1076 [(store (X86shld (loadi64 addr:$dst), GR64:$src2,
1077 (i8 imm:$src3)), addr:$dst)]>,
1079 def SHRD64mri8 : RIi8<0xAC, MRMDestMem,
1080 (outs), (ins i64mem:$dst, GR64:$src2, i8imm:$src3),
1081 "shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1082 [(store (X86shrd (loadi64 addr:$dst), GR64:$src2,
1083 (i8 imm:$src3)), addr:$dst)]>,
1085 } // Defs = [EFLAGS]
1087 //===----------------------------------------------------------------------===//
1088 // Logical Instructions...
1091 let Constraints = "$src = $dst" , AddedComplexity = 15 in
1092 def NOT64r : RI<0xF7, MRM2r, (outs GR64:$dst), (ins GR64:$src), "not{q}\t$dst",
1093 [(set GR64:$dst, (not GR64:$src))]>;
1094 def NOT64m : RI<0xF7, MRM2m, (outs), (ins i64mem:$dst), "not{q}\t$dst",
1095 [(store (not (loadi64 addr:$dst)), addr:$dst)]>;
1097 let Defs = [EFLAGS] in {
1098 def AND64i32 : RIi32<0x25, RawFrm, (outs), (ins i64i32imm:$src),
1099 "and{q}\t{$src, %rax|%rax, $src}", []>;
1101 let Constraints = "$src1 = $dst" in {
1102 let isCommutable = 1 in
1103 def AND64rr : RI<0x21, MRMDestReg,
1104 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1105 "and{q}\t{$src2, $dst|$dst, $src2}",
1106 [(set GR64:$dst, EFLAGS,
1107 (X86and_flag GR64:$src1, GR64:$src2))]>;
1108 let isCodeGenOnly = 1 in {
1109 def AND64rr_REV : RI<0x23, MRMSrcReg, (outs GR64:$dst),
1110 (ins GR64:$src1, GR64:$src2),
1111 "and{q}\t{$src2, $dst|$dst, $src2}", []>;
1113 def AND64rm : RI<0x23, MRMSrcMem,
1114 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1115 "and{q}\t{$src2, $dst|$dst, $src2}",
1116 [(set GR64:$dst, EFLAGS,
1117 (X86and_flag GR64:$src1, (load addr:$src2)))]>;
1118 def AND64ri8 : RIi8<0x83, MRM4r,
1119 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
1120 "and{q}\t{$src2, $dst|$dst, $src2}",
1121 [(set GR64:$dst, EFLAGS,
1122 (X86and_flag GR64:$src1, i64immSExt8:$src2))]>;
1123 def AND64ri32 : RIi32<0x81, MRM4r,
1124 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
1125 "and{q}\t{$src2, $dst|$dst, $src2}",
1126 [(set GR64:$dst, EFLAGS,
1127 (X86and_flag GR64:$src1, i64immSExt32:$src2))]>;
1128 } // Constraints = "$src1 = $dst"
1130 def AND64mr : RI<0x21, MRMDestMem,
1131 (outs), (ins i64mem:$dst, GR64:$src),
1132 "and{q}\t{$src, $dst|$dst, $src}",
1133 [(store (and (load addr:$dst), GR64:$src), addr:$dst),
1134 (implicit EFLAGS)]>;
1135 def AND64mi8 : RIi8<0x83, MRM4m,
1136 (outs), (ins i64mem:$dst, i64i8imm :$src),
1137 "and{q}\t{$src, $dst|$dst, $src}",
1138 [(store (and (load addr:$dst), i64immSExt8:$src), addr:$dst),
1139 (implicit EFLAGS)]>;
1140 def AND64mi32 : RIi32<0x81, MRM4m,
1141 (outs), (ins i64mem:$dst, i64i32imm:$src),
1142 "and{q}\t{$src, $dst|$dst, $src}",
1143 [(store (and (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst),
1144 (implicit EFLAGS)]>;
1146 let Constraints = "$src1 = $dst" in {
1147 let isCommutable = 1 in
1148 def OR64rr : RI<0x09, MRMDestReg, (outs GR64:$dst),
1149 (ins GR64:$src1, GR64:$src2),
1150 "or{q}\t{$src2, $dst|$dst, $src2}",
1151 [(set GR64:$dst, EFLAGS,
1152 (X86or_flag GR64:$src1, GR64:$src2))]>;
1153 let isCodeGenOnly = 1 in {
1154 def OR64rr_REV : RI<0x0B, MRMSrcReg, (outs GR64:$dst),
1155 (ins GR64:$src1, GR64:$src2),
1156 "or{q}\t{$src2, $dst|$dst, $src2}", []>;
1158 def OR64rm : RI<0x0B, MRMSrcMem , (outs GR64:$dst),
1159 (ins GR64:$src1, i64mem:$src2),
1160 "or{q}\t{$src2, $dst|$dst, $src2}",
1161 [(set GR64:$dst, EFLAGS,
1162 (X86or_flag GR64:$src1, (load addr:$src2)))]>;
1163 def OR64ri8 : RIi8<0x83, MRM1r, (outs GR64:$dst),
1164 (ins GR64:$src1, i64i8imm:$src2),
1165 "or{q}\t{$src2, $dst|$dst, $src2}",
1166 [(set GR64:$dst, EFLAGS,
1167 (X86or_flag GR64:$src1, i64immSExt8:$src2))]>;
1168 def OR64ri32 : RIi32<0x81, MRM1r, (outs GR64:$dst),
1169 (ins GR64:$src1, i64i32imm:$src2),
1170 "or{q}\t{$src2, $dst|$dst, $src2}",
1171 [(set GR64:$dst, EFLAGS,
1172 (X86or_flag GR64:$src1, i64immSExt32:$src2))]>;
1173 } // Constraints = "$src1 = $dst"
1175 def OR64mr : RI<0x09, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1176 "or{q}\t{$src, $dst|$dst, $src}",
1177 [(store (or (load addr:$dst), GR64:$src), addr:$dst),
1178 (implicit EFLAGS)]>;
1179 def OR64mi8 : RIi8<0x83, MRM1m, (outs), (ins i64mem:$dst, i64i8imm:$src),
1180 "or{q}\t{$src, $dst|$dst, $src}",
1181 [(store (or (load addr:$dst), i64immSExt8:$src), addr:$dst),
1182 (implicit EFLAGS)]>;
1183 def OR64mi32 : RIi32<0x81, MRM1m, (outs), (ins i64mem:$dst, i64i32imm:$src),
1184 "or{q}\t{$src, $dst|$dst, $src}",
1185 [(store (or (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst),
1186 (implicit EFLAGS)]>;
1188 def OR64i32 : RIi32<0x0D, RawFrm, (outs), (ins i64i32imm:$src),
1189 "or{q}\t{$src, %rax|%rax, $src}", []>;
1191 let Constraints = "$src1 = $dst" in {
1192 let isCommutable = 1 in
1193 def XOR64rr : RI<0x31, MRMDestReg, (outs GR64:$dst),
1194 (ins GR64:$src1, GR64:$src2),
1195 "xor{q}\t{$src2, $dst|$dst, $src2}",
1196 [(set GR64:$dst, EFLAGS,
1197 (X86xor_flag GR64:$src1, GR64:$src2))]>;
1198 let isCodeGenOnly = 1 in {
1199 def XOR64rr_REV : RI<0x33, MRMSrcReg, (outs GR64:$dst),
1200 (ins GR64:$src1, GR64:$src2),
1201 "xor{q}\t{$src2, $dst|$dst, $src2}", []>;
1203 def XOR64rm : RI<0x33, MRMSrcMem, (outs GR64:$dst),
1204 (ins GR64:$src1, i64mem:$src2),
1205 "xor{q}\t{$src2, $dst|$dst, $src2}",
1206 [(set GR64:$dst, EFLAGS,
1207 (X86xor_flag GR64:$src1, (load addr:$src2)))]>;
1208 def XOR64ri8 : RIi8<0x83, MRM6r, (outs GR64:$dst),
1209 (ins GR64:$src1, i64i8imm:$src2),
1210 "xor{q}\t{$src2, $dst|$dst, $src2}",
1211 [(set GR64:$dst, EFLAGS,
1212 (X86xor_flag GR64:$src1, i64immSExt8:$src2))]>;
1213 def XOR64ri32 : RIi32<0x81, MRM6r,
1214 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
1215 "xor{q}\t{$src2, $dst|$dst, $src2}",
1216 [(set GR64:$dst, EFLAGS,
1217 (X86xor_flag GR64:$src1, i64immSExt32:$src2))]>;
1218 } // Constraints = "$src1 = $dst"
1220 def XOR64mr : RI<0x31, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1221 "xor{q}\t{$src, $dst|$dst, $src}",
1222 [(store (xor (load addr:$dst), GR64:$src), addr:$dst),
1223 (implicit EFLAGS)]>;
1224 def XOR64mi8 : RIi8<0x83, MRM6m, (outs), (ins i64mem:$dst, i64i8imm :$src),
1225 "xor{q}\t{$src, $dst|$dst, $src}",
1226 [(store (xor (load addr:$dst), i64immSExt8:$src), addr:$dst),
1227 (implicit EFLAGS)]>;
1228 def XOR64mi32 : RIi32<0x81, MRM6m, (outs), (ins i64mem:$dst, i64i32imm:$src),
1229 "xor{q}\t{$src, $dst|$dst, $src}",
1230 [(store (xor (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst),
1231 (implicit EFLAGS)]>;
1233 def XOR64i32 : RIi32<0x35, RawFrm, (outs), (ins i64i32imm:$src),
1234 "xor{q}\t{$src, %rax|%rax, $src}", []>;
1236 } // Defs = [EFLAGS]
1238 //===----------------------------------------------------------------------===//
1239 // Comparison Instructions...
1242 // Integer comparison
1243 let Defs = [EFLAGS] in {
1244 def TEST64i32 : RIi32<0xa9, RawFrm, (outs), (ins i64i32imm:$src),
1245 "test{q}\t{$src, %rax|%rax, $src}", []>;
1246 let isCommutable = 1 in
1247 def TEST64rr : RI<0x85, MRMSrcReg, (outs), (ins GR64:$src1, GR64:$src2),
1248 "test{q}\t{$src2, $src1|$src1, $src2}",
1249 [(set EFLAGS, (X86cmp (and GR64:$src1, GR64:$src2), 0))]>;
1250 def TEST64rm : RI<0x85, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2),
1251 "test{q}\t{$src2, $src1|$src1, $src2}",
1252 [(set EFLAGS, (X86cmp (and GR64:$src1, (loadi64 addr:$src2)),
1254 def TEST64ri32 : RIi32<0xF7, MRM0r, (outs),
1255 (ins GR64:$src1, i64i32imm:$src2),
1256 "test{q}\t{$src2, $src1|$src1, $src2}",
1257 [(set EFLAGS, (X86cmp (and GR64:$src1, i64immSExt32:$src2),
1259 def TEST64mi32 : RIi32<0xF7, MRM0m, (outs),
1260 (ins i64mem:$src1, i64i32imm:$src2),
1261 "test{q}\t{$src2, $src1|$src1, $src2}",
1262 [(set EFLAGS, (X86cmp (and (loadi64 addr:$src1),
1263 i64immSExt32:$src2), 0))]>;
1266 def CMP64i32 : RIi32<0x3D, RawFrm, (outs), (ins i64i32imm:$src),
1267 "cmp{q}\t{$src, %rax|%rax, $src}", []>;
1268 def CMP64rr : RI<0x39, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1269 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1270 [(set EFLAGS, (X86cmp GR64:$src1, GR64:$src2))]>;
1272 // These are alternate spellings for use by the disassembler, we mark them as
1273 // code gen only to ensure they aren't matched by the assembler.
1274 let isCodeGenOnly = 1 in {
1275 def CMP64mrmrr : RI<0x3B, MRMSrcReg, (outs), (ins GR64:$src1, GR64:$src2),
1276 "cmp{q}\t{$src2, $src1|$src1, $src2}", []>;
1279 def CMP64mr : RI<0x39, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1280 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1281 [(set EFLAGS, (X86cmp (loadi64 addr:$src1), GR64:$src2))]>;
1282 def CMP64rm : RI<0x3B, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2),
1283 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1284 [(set EFLAGS, (X86cmp GR64:$src1, (loadi64 addr:$src2)))]>;
1285 def CMP64ri8 : RIi8<0x83, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1286 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1287 [(set EFLAGS, (X86cmp GR64:$src1, i64immSExt8:$src2))]>;
1288 def CMP64ri32 : RIi32<0x81, MRM7r, (outs), (ins GR64:$src1, i64i32imm:$src2),
1289 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1290 [(set EFLAGS, (X86cmp GR64:$src1, i64immSExt32:$src2))]>;
1291 def CMP64mi8 : RIi8<0x83, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1292 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1293 [(set EFLAGS, (X86cmp (loadi64 addr:$src1),
1294 i64immSExt8:$src2))]>;
1295 def CMP64mi32 : RIi32<0x81, MRM7m, (outs),
1296 (ins i64mem:$src1, i64i32imm:$src2),
1297 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1298 [(set EFLAGS, (X86cmp (loadi64 addr:$src1),
1299 i64immSExt32:$src2))]>;
1300 } // Defs = [EFLAGS]
1303 // TODO: BTC, BTR, and BTS
1304 let Defs = [EFLAGS] in {
1305 def BT64rr : RI<0xA3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1306 "bt{q}\t{$src2, $src1|$src1, $src2}",
1307 [(set EFLAGS, (X86bt GR64:$src1, GR64:$src2))]>, TB;
1309 // Unlike with the register+register form, the memory+register form of the
1310 // bt instruction does not ignore the high bits of the index. From ISel's
1311 // perspective, this is pretty bizarre. Disable these instructions for now.
1312 def BT64mr : RI<0xA3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1313 "bt{q}\t{$src2, $src1|$src1, $src2}",
1314 // [(X86bt (loadi64 addr:$src1), GR64:$src2),
1315 // (implicit EFLAGS)]
1319 def BT64ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1320 "bt{q}\t{$src2, $src1|$src1, $src2}",
1321 [(set EFLAGS, (X86bt GR64:$src1, i64immSExt8:$src2))]>, TB,
1323 // Note that these instructions don't need FastBTMem because that
1324 // only applies when the other operand is in a register. When it's
1325 // an immediate, bt is still fast.
1326 def BT64mi8 : Ii8<0xBA, MRM4m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1327 "bt{q}\t{$src2, $src1|$src1, $src2}",
1328 [(set EFLAGS, (X86bt (loadi64 addr:$src1),
1329 i64immSExt8:$src2))]>, TB;
1331 def BTC64rr : RI<0xBB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1332 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1333 def BTC64mr : RI<0xBB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1334 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1335 def BTC64ri8 : RIi8<0xBA, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1336 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1337 def BTC64mi8 : RIi8<0xBA, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1338 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1340 def BTR64rr : RI<0xB3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1341 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1342 def BTR64mr : RI<0xB3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1343 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1344 def BTR64ri8 : RIi8<0xBA, MRM6r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1345 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1346 def BTR64mi8 : RIi8<0xBA, MRM6m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1347 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1349 def BTS64rr : RI<0xAB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1350 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1351 def BTS64mr : RI<0xAB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1352 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1353 def BTS64ri8 : RIi8<0xBA, MRM5r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1354 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1355 def BTS64mi8 : RIi8<0xBA, MRM5m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1356 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1357 } // Defs = [EFLAGS]
1359 // Conditional moves
1360 let Uses = [EFLAGS], Constraints = "$src1 = $dst" in {
1361 let isCommutable = 1 in {
1362 def CMOVB64rr : RI<0x42, MRMSrcReg, // if <u, GR64 = GR64
1363 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1364 "cmovb{q}\t{$src2, $dst|$dst, $src2}",
1365 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1366 X86_COND_B, EFLAGS))]>, TB;
1367 def CMOVAE64rr: RI<0x43, MRMSrcReg, // if >=u, GR64 = GR64
1368 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1369 "cmovae{q}\t{$src2, $dst|$dst, $src2}",
1370 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1371 X86_COND_AE, EFLAGS))]>, TB;
1372 def CMOVE64rr : RI<0x44, MRMSrcReg, // if ==, GR64 = GR64
1373 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1374 "cmove{q}\t{$src2, $dst|$dst, $src2}",
1375 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1376 X86_COND_E, EFLAGS))]>, TB;
1377 def CMOVNE64rr: RI<0x45, MRMSrcReg, // if !=, GR64 = GR64
1378 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1379 "cmovne{q}\t{$src2, $dst|$dst, $src2}",
1380 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1381 X86_COND_NE, EFLAGS))]>, TB;
1382 def CMOVBE64rr: RI<0x46, MRMSrcReg, // if <=u, GR64 = GR64
1383 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1384 "cmovbe{q}\t{$src2, $dst|$dst, $src2}",
1385 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1386 X86_COND_BE, EFLAGS))]>, TB;
1387 def CMOVA64rr : RI<0x47, MRMSrcReg, // if >u, GR64 = GR64
1388 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1389 "cmova{q}\t{$src2, $dst|$dst, $src2}",
1390 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1391 X86_COND_A, EFLAGS))]>, TB;
1392 def CMOVL64rr : RI<0x4C, MRMSrcReg, // if <s, GR64 = GR64
1393 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1394 "cmovl{q}\t{$src2, $dst|$dst, $src2}",
1395 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1396 X86_COND_L, EFLAGS))]>, TB;
1397 def CMOVGE64rr: RI<0x4D, MRMSrcReg, // if >=s, GR64 = GR64
1398 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1399 "cmovge{q}\t{$src2, $dst|$dst, $src2}",
1400 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1401 X86_COND_GE, EFLAGS))]>, TB;
1402 def CMOVLE64rr: RI<0x4E, MRMSrcReg, // if <=s, GR64 = GR64
1403 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1404 "cmovle{q}\t{$src2, $dst|$dst, $src2}",
1405 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1406 X86_COND_LE, EFLAGS))]>, TB;
1407 def CMOVG64rr : RI<0x4F, MRMSrcReg, // if >s, GR64 = GR64
1408 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1409 "cmovg{q}\t{$src2, $dst|$dst, $src2}",
1410 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1411 X86_COND_G, EFLAGS))]>, TB;
1412 def CMOVS64rr : RI<0x48, MRMSrcReg, // if signed, GR64 = GR64
1413 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1414 "cmovs{q}\t{$src2, $dst|$dst, $src2}",
1415 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1416 X86_COND_S, EFLAGS))]>, TB;
1417 def CMOVNS64rr: RI<0x49, MRMSrcReg, // if !signed, GR64 = GR64
1418 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1419 "cmovns{q}\t{$src2, $dst|$dst, $src2}",
1420 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1421 X86_COND_NS, EFLAGS))]>, TB;
1422 def CMOVP64rr : RI<0x4A, MRMSrcReg, // if parity, GR64 = GR64
1423 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1424 "cmovp{q}\t{$src2, $dst|$dst, $src2}",
1425 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1426 X86_COND_P, EFLAGS))]>, TB;
1427 def CMOVNP64rr : RI<0x4B, MRMSrcReg, // if !parity, GR64 = GR64
1428 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1429 "cmovnp{q}\t{$src2, $dst|$dst, $src2}",
1430 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1431 X86_COND_NP, EFLAGS))]>, TB;
1432 def CMOVO64rr : RI<0x40, MRMSrcReg, // if overflow, GR64 = GR64
1433 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1434 "cmovo{q}\t{$src2, $dst|$dst, $src2}",
1435 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1436 X86_COND_O, EFLAGS))]>, TB;
1437 def CMOVNO64rr : RI<0x41, MRMSrcReg, // if !overflow, GR64 = GR64
1438 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1439 "cmovno{q}\t{$src2, $dst|$dst, $src2}",
1440 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1441 X86_COND_NO, EFLAGS))]>, TB;
1442 } // isCommutable = 1
1444 def CMOVB64rm : RI<0x42, MRMSrcMem, // if <u, GR64 = [mem64]
1445 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1446 "cmovb{q}\t{$src2, $dst|$dst, $src2}",
1447 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1448 X86_COND_B, EFLAGS))]>, TB;
1449 def CMOVAE64rm: RI<0x43, MRMSrcMem, // if >=u, GR64 = [mem64]
1450 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1451 "cmovae{q}\t{$src2, $dst|$dst, $src2}",
1452 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1453 X86_COND_AE, EFLAGS))]>, TB;
1454 def CMOVE64rm : RI<0x44, MRMSrcMem, // if ==, GR64 = [mem64]
1455 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1456 "cmove{q}\t{$src2, $dst|$dst, $src2}",
1457 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1458 X86_COND_E, EFLAGS))]>, TB;
1459 def CMOVNE64rm: RI<0x45, MRMSrcMem, // if !=, GR64 = [mem64]
1460 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1461 "cmovne{q}\t{$src2, $dst|$dst, $src2}",
1462 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1463 X86_COND_NE, EFLAGS))]>, TB;
1464 def CMOVBE64rm: RI<0x46, MRMSrcMem, // if <=u, GR64 = [mem64]
1465 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1466 "cmovbe{q}\t{$src2, $dst|$dst, $src2}",
1467 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1468 X86_COND_BE, EFLAGS))]>, TB;
1469 def CMOVA64rm : RI<0x47, MRMSrcMem, // if >u, GR64 = [mem64]
1470 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1471 "cmova{q}\t{$src2, $dst|$dst, $src2}",
1472 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1473 X86_COND_A, EFLAGS))]>, TB;
1474 def CMOVL64rm : RI<0x4C, MRMSrcMem, // if <s, GR64 = [mem64]
1475 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1476 "cmovl{q}\t{$src2, $dst|$dst, $src2}",
1477 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1478 X86_COND_L, EFLAGS))]>, TB;
1479 def CMOVGE64rm: RI<0x4D, MRMSrcMem, // if >=s, GR64 = [mem64]
1480 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1481 "cmovge{q}\t{$src2, $dst|$dst, $src2}",
1482 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1483 X86_COND_GE, EFLAGS))]>, TB;
1484 def CMOVLE64rm: RI<0x4E, MRMSrcMem, // if <=s, GR64 = [mem64]
1485 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1486 "cmovle{q}\t{$src2, $dst|$dst, $src2}",
1487 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1488 X86_COND_LE, EFLAGS))]>, TB;
1489 def CMOVG64rm : RI<0x4F, MRMSrcMem, // if >s, GR64 = [mem64]
1490 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1491 "cmovg{q}\t{$src2, $dst|$dst, $src2}",
1492 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1493 X86_COND_G, EFLAGS))]>, TB;
1494 def CMOVS64rm : RI<0x48, MRMSrcMem, // if signed, GR64 = [mem64]
1495 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1496 "cmovs{q}\t{$src2, $dst|$dst, $src2}",
1497 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1498 X86_COND_S, EFLAGS))]>, TB;
1499 def CMOVNS64rm: RI<0x49, MRMSrcMem, // if !signed, GR64 = [mem64]
1500 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1501 "cmovns{q}\t{$src2, $dst|$dst, $src2}",
1502 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1503 X86_COND_NS, EFLAGS))]>, TB;
1504 def CMOVP64rm : RI<0x4A, MRMSrcMem, // if parity, GR64 = [mem64]
1505 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1506 "cmovp{q}\t{$src2, $dst|$dst, $src2}",
1507 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1508 X86_COND_P, EFLAGS))]>, TB;
1509 def CMOVNP64rm : RI<0x4B, MRMSrcMem, // if !parity, GR64 = [mem64]
1510 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1511 "cmovnp{q}\t{$src2, $dst|$dst, $src2}",
1512 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1513 X86_COND_NP, EFLAGS))]>, TB;
1514 def CMOVO64rm : RI<0x40, MRMSrcMem, // if overflow, GR64 = [mem64]
1515 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1516 "cmovo{q}\t{$src2, $dst|$dst, $src2}",
1517 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1518 X86_COND_O, EFLAGS))]>, TB;
1519 def CMOVNO64rm : RI<0x41, MRMSrcMem, // if !overflow, GR64 = [mem64]
1520 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1521 "cmovno{q}\t{$src2, $dst|$dst, $src2}",
1522 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1523 X86_COND_NO, EFLAGS))]>, TB;
1524 } // Constraints = "$src1 = $dst"
1526 // Use sbb to materialize carry flag into a GPR.
1527 // FIXME: This are pseudo ops that should be replaced with Pat<> patterns.
1528 // However, Pat<> can't replicate the destination reg into the inputs of the
1530 // FIXME: Change this to have encoding Pseudo when X86MCCodeEmitter replaces
1532 let Defs = [EFLAGS], Uses = [EFLAGS], isCodeGenOnly = 1 in
1533 def SETB_C64r : RI<0x19, MRMInitReg, (outs GR64:$dst), (ins), "",
1534 [(set GR64:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
1536 def : Pat<(i64 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
1539 //===----------------------------------------------------------------------===//
1540 // Conversion Instructions...
1543 // f64 -> signed i64
1544 def CVTSD2SI64rr: RSDI<0x2D, MRMSrcReg, (outs GR64:$dst), (ins FR64:$src),
1545 "cvtsd2si{q}\t{$src, $dst|$dst, $src}", []>;
1546 def CVTSD2SI64rm: RSDI<0x2D, MRMSrcMem, (outs GR64:$dst), (ins f64mem:$src),
1547 "cvtsd2si{q}\t{$src, $dst|$dst, $src}", []>;
1548 def Int_CVTSD2SI64rr: RSDI<0x2D, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1549 "cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1551 (int_x86_sse2_cvtsd2si64 VR128:$src))]>;
1552 def Int_CVTSD2SI64rm: RSDI<0x2D, MRMSrcMem, (outs GR64:$dst),
1554 "cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1555 [(set GR64:$dst, (int_x86_sse2_cvtsd2si64
1556 (load addr:$src)))]>;
1557 def CVTTSD2SI64rr: RSDI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins FR64:$src),
1558 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1559 [(set GR64:$dst, (fp_to_sint FR64:$src))]>;
1560 def CVTTSD2SI64rm: RSDI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f64mem:$src),
1561 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1562 [(set GR64:$dst, (fp_to_sint (loadf64 addr:$src)))]>;
1563 def Int_CVTTSD2SI64rr: RSDI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1564 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1566 (int_x86_sse2_cvttsd2si64 VR128:$src))]>;
1567 def Int_CVTTSD2SI64rm: RSDI<0x2C, MRMSrcMem, (outs GR64:$dst),
1569 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1571 (int_x86_sse2_cvttsd2si64
1572 (load addr:$src)))]>;
1574 // Signed i64 -> f64
1575 def CVTSI2SD64rr: RSDI<0x2A, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
1576 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
1577 [(set FR64:$dst, (sint_to_fp GR64:$src))]>;
1578 def CVTSI2SD64rm: RSDI<0x2A, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
1579 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
1580 [(set FR64:$dst, (sint_to_fp (loadi64 addr:$src)))]>;
1582 let Constraints = "$src1 = $dst" in {
1583 def Int_CVTSI2SD64rr: RSDI<0x2A, MRMSrcReg,
1584 (outs VR128:$dst), (ins VR128:$src1, GR64:$src2),
1585 "cvtsi2sd{q}\t{$src2, $dst|$dst, $src2}",
1587 (int_x86_sse2_cvtsi642sd VR128:$src1,
1589 def Int_CVTSI2SD64rm: RSDI<0x2A, MRMSrcMem,
1590 (outs VR128:$dst), (ins VR128:$src1, i64mem:$src2),
1591 "cvtsi2sd{q}\t{$src2, $dst|$dst, $src2}",
1593 (int_x86_sse2_cvtsi642sd VR128:$src1,
1594 (loadi64 addr:$src2)))]>;
1595 } // Constraints = "$src1 = $dst"
1597 // Signed i64 -> f32
1598 def CVTSI2SS64rr: RSSI<0x2A, MRMSrcReg, (outs FR32:$dst), (ins GR64:$src),
1599 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
1600 [(set FR32:$dst, (sint_to_fp GR64:$src))]>;
1601 def CVTSI2SS64rm: RSSI<0x2A, MRMSrcMem, (outs FR32:$dst), (ins i64mem:$src),
1602 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
1603 [(set FR32:$dst, (sint_to_fp (loadi64 addr:$src)))]>;
1605 let Constraints = "$src1 = $dst" in {
1606 def Int_CVTSI2SS64rr : RSSI<0x2A, MRMSrcReg,
1607 (outs VR128:$dst), (ins VR128:$src1, GR64:$src2),
1608 "cvtsi2ss{q}\t{$src2, $dst|$dst, $src2}",
1610 (int_x86_sse_cvtsi642ss VR128:$src1,
1612 def Int_CVTSI2SS64rm : RSSI<0x2A, MRMSrcMem,
1614 (ins VR128:$src1, i64mem:$src2),
1615 "cvtsi2ss{q}\t{$src2, $dst|$dst, $src2}",
1617 (int_x86_sse_cvtsi642ss VR128:$src1,
1618 (loadi64 addr:$src2)))]>;
1619 } // Constraints = "$src1 = $dst"
1621 // f32 -> signed i64
1622 def CVTSS2SI64rr: RSSI<0x2D, MRMSrcReg, (outs GR64:$dst), (ins FR32:$src),
1623 "cvtss2si{q}\t{$src, $dst|$dst, $src}", []>;
1624 def CVTSS2SI64rm: RSSI<0x2D, MRMSrcMem, (outs GR64:$dst), (ins f32mem:$src),
1625 "cvtss2si{q}\t{$src, $dst|$dst, $src}", []>;
1626 def Int_CVTSS2SI64rr: RSSI<0x2D, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1627 "cvtss2si{q}\t{$src, $dst|$dst, $src}",
1629 (int_x86_sse_cvtss2si64 VR128:$src))]>;
1630 def Int_CVTSS2SI64rm: RSSI<0x2D, MRMSrcMem, (outs GR64:$dst), (ins f32mem:$src),
1631 "cvtss2si{q}\t{$src, $dst|$dst, $src}",
1632 [(set GR64:$dst, (int_x86_sse_cvtss2si64
1633 (load addr:$src)))]>;
1634 def CVTTSS2SI64rr: RSSI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins FR32:$src),
1635 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1636 [(set GR64:$dst, (fp_to_sint FR32:$src))]>;
1637 def CVTTSS2SI64rm: RSSI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f32mem:$src),
1638 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1639 [(set GR64:$dst, (fp_to_sint (loadf32 addr:$src)))]>;
1640 def Int_CVTTSS2SI64rr: RSSI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1641 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1643 (int_x86_sse_cvttss2si64 VR128:$src))]>;
1644 def Int_CVTTSS2SI64rm: RSSI<0x2C, MRMSrcMem, (outs GR64:$dst),
1646 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1648 (int_x86_sse_cvttss2si64 (load addr:$src)))]>;
1650 // Descriptor-table support instructions
1652 // LLDT is not interpreted specially in 64-bit mode because there is no sign
1654 def SLDT64r : RI<0x00, MRM0r, (outs GR64:$dst), (ins),
1655 "sldt{q}\t$dst", []>, TB;
1656 def SLDT64m : RI<0x00, MRM0m, (outs i16mem:$dst), (ins),
1657 "sldt{q}\t$dst", []>, TB;
1659 //===----------------------------------------------------------------------===//
1660 // Alias Instructions
1661 //===----------------------------------------------------------------------===//
1663 // We want to rewrite MOV64r0 in terms of MOV32r0, because it's sometimes a
1664 // smaller encoding, but doing so at isel time interferes with rematerialization
1665 // in the current register allocator. For now, this is rewritten when the
1666 // instruction is lowered to an MCInst.
1667 // FIXME: AddedComplexity gives this a higher priority than MOV64ri32. Remove
1668 // when we have a better way to specify isel priority.
1669 let Defs = [EFLAGS],
1670 AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1 in
1671 def MOV64r0 : I<0x31, MRMInitReg, (outs GR64:$dst), (ins), "",
1672 [(set GR64:$dst, 0)]>;
1674 // Materialize i64 constant where top 32-bits are zero. This could theoretically
1675 // use MOV32ri with a SUBREG_TO_REG to represent the zero-extension, however
1676 // that would make it more difficult to rematerialize.
1677 let AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1 in
1678 def MOV64ri64i32 : Ii32<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64i32imm:$src),
1679 "", [(set GR64:$dst, i64immZExt32:$src)]>;
1681 //===----------------------------------------------------------------------===//
1682 // Thread Local Storage Instructions
1683 //===----------------------------------------------------------------------===//
1686 // All calls clobber the non-callee saved registers. RSP is marked as
1687 // a use to prevent stack-pointer assignments that appear immediately
1688 // before calls from potentially appearing dead.
1689 let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
1690 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
1691 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
1692 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
1693 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
1695 def TLS_addr64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
1697 "leaq\t$sym(%rip), %rdi; "
1700 "call\t__tls_get_addr@PLT",
1701 [(X86tlsaddr tls64addr:$sym)]>,
1702 Requires<[In64BitMode]>;
1704 // Darwin TLS Support
1705 // For x86_64, the address of the thunk is passed in %rdi, on return
1706 // the address of the variable is in %rax. All other registers are preserved.
1709 usesCustomInserter = 1 in
1710 def TLSCall_64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
1712 [(X86TLSCall addr:$sym)]>,
1713 Requires<[In64BitMode]>;
1715 let AddedComplexity = 5, isCodeGenOnly = 1 in
1716 def MOV64GSrm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1717 "movq\t%gs:$src, $dst",
1718 [(set GR64:$dst, (gsload addr:$src))]>, SegGS;
1720 let AddedComplexity = 5, isCodeGenOnly = 1 in
1721 def MOV64FSrm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1722 "movq\t%fs:$src, $dst",
1723 [(set GR64:$dst, (fsload addr:$src))]>, SegFS;
1725 //===----------------------------------------------------------------------===//
1726 // Atomic Instructions
1727 //===----------------------------------------------------------------------===//
1729 let Defs = [RAX, EFLAGS], Uses = [RAX] in {
1730 def LCMPXCHG64 : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$ptr, GR64:$swap),
1732 "cmpxchgq\t$swap,$ptr",
1733 [(X86cas addr:$ptr, GR64:$swap, 8)]>, TB, LOCK;
1736 let Constraints = "$val = $dst" in {
1737 let Defs = [EFLAGS] in
1738 def LXADD64 : RI<0xC1, MRMSrcMem, (outs GR64:$dst), (ins GR64:$val,i64mem:$ptr),
1741 [(set GR64:$dst, (atomic_load_add_64 addr:$ptr, GR64:$val))]>,
1744 def XCHG64rm : RI<0x87, MRMSrcMem, (outs GR64:$dst),
1745 (ins GR64:$val,i64mem:$ptr),
1746 "xchg{q}\t{$val, $ptr|$ptr, $val}",
1747 [(set GR64:$dst, (atomic_swap_64 addr:$ptr, GR64:$val))]>;
1749 def XCHG64rr : RI<0x87, MRMSrcReg, (outs GR64:$dst), (ins GR64:$val,GR64:$src),
1750 "xchg{q}\t{$val, $src|$src, $val}", []>;
1753 def XADD64rr : RI<0xC1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1754 "xadd{q}\t{$src, $dst|$dst, $src}", []>, TB;
1755 let mayLoad = 1, mayStore = 1 in
1756 def XADD64rm : RI<0xC1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1757 "xadd{q}\t{$src, $dst|$dst, $src}", []>, TB;
1759 def CMPXCHG64rr : RI<0xB1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1760 "cmpxchg{q}\t{$src, $dst|$dst, $src}", []>, TB;
1761 let mayLoad = 1, mayStore = 1 in
1762 def CMPXCHG64rm : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1763 "cmpxchg{q}\t{$src, $dst|$dst, $src}", []>, TB;
1765 let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX] in
1766 def CMPXCHG16B : RI<0xC7, MRM1m, (outs), (ins i128mem:$dst),
1767 "cmpxchg16b\t$dst", []>, TB;
1769 def XCHG64ar : RI<0x90, AddRegFrm, (outs), (ins GR64:$src),
1770 "xchg{q}\t{$src, %rax|%rax, $src}", []>;
1772 // Optimized codegen when the non-memory output is not used.
1773 let Defs = [EFLAGS], mayLoad = 1, mayStore = 1 in {
1774 // FIXME: Use normal add / sub instructions and add lock prefix dynamically.
1775 def LOCK_ADD64mr : RI<0x03, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
1777 "add{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1778 def LOCK_ADD64mi8 : RIi8<0x83, MRM0m, (outs),
1779 (ins i64mem:$dst, i64i8imm :$src2),
1781 "add{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1782 def LOCK_ADD64mi32 : RIi32<0x81, MRM0m, (outs),
1783 (ins i64mem:$dst, i64i32imm :$src2),
1785 "add{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1786 def LOCK_SUB64mr : RI<0x29, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
1788 "sub{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1789 def LOCK_SUB64mi8 : RIi8<0x83, MRM5m, (outs),
1790 (ins i64mem:$dst, i64i8imm :$src2),
1792 "sub{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1793 def LOCK_SUB64mi32 : RIi32<0x81, MRM5m, (outs),
1794 (ins i64mem:$dst, i64i32imm:$src2),
1796 "sub{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1797 def LOCK_INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst),
1799 "inc{q}\t$dst", []>, LOCK;
1800 def LOCK_DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst),
1802 "dec{q}\t$dst", []>, LOCK;
1804 // Atomic exchange, and, or, xor
1805 let Constraints = "$val = $dst", Defs = [EFLAGS],
1806 usesCustomInserter = 1 in {
1807 def ATOMAND64 : I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1808 "#ATOMAND64 PSEUDO!",
1809 [(set GR64:$dst, (atomic_load_and_64 addr:$ptr, GR64:$val))]>;
1810 def ATOMOR64 : I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1811 "#ATOMOR64 PSEUDO!",
1812 [(set GR64:$dst, (atomic_load_or_64 addr:$ptr, GR64:$val))]>;
1813 def ATOMXOR64 : I<0, Pseudo,(outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1814 "#ATOMXOR64 PSEUDO!",
1815 [(set GR64:$dst, (atomic_load_xor_64 addr:$ptr, GR64:$val))]>;
1816 def ATOMNAND64 : I<0, Pseudo,(outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1817 "#ATOMNAND64 PSEUDO!",
1818 [(set GR64:$dst, (atomic_load_nand_64 addr:$ptr, GR64:$val))]>;
1819 def ATOMMIN64: I<0, Pseudo, (outs GR64:$dst), (ins i64mem:$ptr, GR64:$val),
1820 "#ATOMMIN64 PSEUDO!",
1821 [(set GR64:$dst, (atomic_load_min_64 addr:$ptr, GR64:$val))]>;
1822 def ATOMMAX64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1823 "#ATOMMAX64 PSEUDO!",
1824 [(set GR64:$dst, (atomic_load_max_64 addr:$ptr, GR64:$val))]>;
1825 def ATOMUMIN64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1826 "#ATOMUMIN64 PSEUDO!",
1827 [(set GR64:$dst, (atomic_load_umin_64 addr:$ptr, GR64:$val))]>;
1828 def ATOMUMAX64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1829 "#ATOMUMAX64 PSEUDO!",
1830 [(set GR64:$dst, (atomic_load_umax_64 addr:$ptr, GR64:$val))]>;
1833 // Segmentation support instructions
1835 // i16mem operand in LAR64rm and GR32 operand in LAR32rr is not a typo.
1836 def LAR64rm : RI<0x02, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
1837 "lar{q}\t{$src, $dst|$dst, $src}", []>, TB;
1838 def LAR64rr : RI<0x02, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src),
1839 "lar{q}\t{$src, $dst|$dst, $src}", []>, TB;
1841 def LSL64rm : RI<0x03, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1842 "lsl{q}\t{$src, $dst|$dst, $src}", []>, TB;
1843 def LSL64rr : RI<0x03, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1844 "lsl{q}\t{$src, $dst|$dst, $src}", []>, TB;
1846 def SWAPGS : I<0x01, MRM_F8, (outs), (ins), "swapgs", []>, TB;
1848 def PUSHFS64 : I<0xa0, RawFrm, (outs), (ins),
1849 "push{q}\t%fs", []>, TB;
1850 def PUSHGS64 : I<0xa8, RawFrm, (outs), (ins),
1851 "push{q}\t%gs", []>, TB;
1853 def POPFS64 : I<0xa1, RawFrm, (outs), (ins),
1854 "pop{q}\t%fs", []>, TB;
1855 def POPGS64 : I<0xa9, RawFrm, (outs), (ins),
1856 "pop{q}\t%gs", []>, TB;
1858 def LSS64rm : RI<0xb2, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
1859 "lss{q}\t{$src, $dst|$dst, $src}", []>, TB;
1860 def LFS64rm : RI<0xb4, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
1861 "lfs{q}\t{$src, $dst|$dst, $src}", []>, TB;
1862 def LGS64rm : RI<0xb5, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
1863 "lgs{q}\t{$src, $dst|$dst, $src}", []>, TB;
1865 // Specialized register support
1867 // no m form encodable; use SMSW16m
1868 def SMSW64r : RI<0x01, MRM4r, (outs GR64:$dst), (ins),
1869 "smsw{q}\t$dst", []>, TB;
1871 // String manipulation instructions
1873 def LODSQ : RI<0xAD, RawFrm, (outs), (ins), "lodsq", []>;
1875 //===----------------------------------------------------------------------===//
1876 // Non-Instruction Patterns
1877 //===----------------------------------------------------------------------===//
1879 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable when not in small
1880 // code model mode, should use 'movabs'. FIXME: This is really a hack, the
1881 // 'movabs' predicate should handle this sort of thing.
1882 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
1883 (MOV64ri tconstpool :$dst)>, Requires<[FarData]>;
1884 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
1885 (MOV64ri tjumptable :$dst)>, Requires<[FarData]>;
1886 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
1887 (MOV64ri tglobaladdr :$dst)>, Requires<[FarData]>;
1888 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
1889 (MOV64ri texternalsym:$dst)>, Requires<[FarData]>;
1890 def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
1891 (MOV64ri tblockaddress:$dst)>, Requires<[FarData]>;
1893 // In static codegen with small code model, we can get the address of a label
1894 // into a register with 'movl'. FIXME: This is a hack, the 'imm' predicate of
1895 // the MOV64ri64i32 should accept these.
1896 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
1897 (MOV64ri64i32 tconstpool :$dst)>, Requires<[SmallCode]>;
1898 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
1899 (MOV64ri64i32 tjumptable :$dst)>, Requires<[SmallCode]>;
1900 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
1901 (MOV64ri64i32 tglobaladdr :$dst)>, Requires<[SmallCode]>;
1902 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
1903 (MOV64ri64i32 texternalsym:$dst)>, Requires<[SmallCode]>;
1904 def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
1905 (MOV64ri64i32 tblockaddress:$dst)>, Requires<[SmallCode]>;
1907 // In kernel code model, we can get the address of a label
1908 // into a register with 'movq'. FIXME: This is a hack, the 'imm' predicate of
1909 // the MOV64ri32 should accept these.
1910 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
1911 (MOV64ri32 tconstpool :$dst)>, Requires<[KernelCode]>;
1912 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
1913 (MOV64ri32 tjumptable :$dst)>, Requires<[KernelCode]>;
1914 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
1915 (MOV64ri32 tglobaladdr :$dst)>, Requires<[KernelCode]>;
1916 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
1917 (MOV64ri32 texternalsym:$dst)>, Requires<[KernelCode]>;
1918 def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
1919 (MOV64ri32 tblockaddress:$dst)>, Requires<[KernelCode]>;
1921 // If we have small model and -static mode, it is safe to store global addresses
1922 // directly as immediates. FIXME: This is really a hack, the 'imm' predicate
1923 // for MOV64mi32 should handle this sort of thing.
1924 def : Pat<(store (i64 (X86Wrapper tconstpool:$src)), addr:$dst),
1925 (MOV64mi32 addr:$dst, tconstpool:$src)>,
1926 Requires<[NearData, IsStatic]>;
1927 def : Pat<(store (i64 (X86Wrapper tjumptable:$src)), addr:$dst),
1928 (MOV64mi32 addr:$dst, tjumptable:$src)>,
1929 Requires<[NearData, IsStatic]>;
1930 def : Pat<(store (i64 (X86Wrapper tglobaladdr:$src)), addr:$dst),
1931 (MOV64mi32 addr:$dst, tglobaladdr:$src)>,
1932 Requires<[NearData, IsStatic]>;
1933 def : Pat<(store (i64 (X86Wrapper texternalsym:$src)), addr:$dst),
1934 (MOV64mi32 addr:$dst, texternalsym:$src)>,
1935 Requires<[NearData, IsStatic]>;
1936 def : Pat<(store (i64 (X86Wrapper tblockaddress:$src)), addr:$dst),
1937 (MOV64mi32 addr:$dst, tblockaddress:$src)>,
1938 Requires<[NearData, IsStatic]>;
1941 // Direct PC relative function call for small code model. 32-bit displacement
1942 // sign extended to 64-bit.
1943 def : Pat<(X86call (i64 tglobaladdr:$dst)),
1944 (CALL64pcrel32 tglobaladdr:$dst)>, Requires<[NotWin64]>;
1945 def : Pat<(X86call (i64 texternalsym:$dst)),
1946 (CALL64pcrel32 texternalsym:$dst)>, Requires<[NotWin64]>;
1948 def : Pat<(X86call (i64 tglobaladdr:$dst)),
1949 (WINCALL64pcrel32 tglobaladdr:$dst)>, Requires<[IsWin64]>;
1950 def : Pat<(X86call (i64 texternalsym:$dst)),
1951 (WINCALL64pcrel32 texternalsym:$dst)>, Requires<[IsWin64]>;
1954 def : Pat<(X86tcret GR64_TC:$dst, imm:$off),
1955 (TCRETURNri64 GR64_TC:$dst, imm:$off)>,
1956 Requires<[In64BitMode]>;
1958 def : Pat<(X86tcret (load addr:$dst), imm:$off),
1959 (TCRETURNmi64 addr:$dst, imm:$off)>,
1960 Requires<[In64BitMode]>;
1962 def : Pat<(X86tcret (i64 tglobaladdr:$dst), imm:$off),
1963 (TCRETURNdi64 tglobaladdr:$dst, imm:$off)>,
1964 Requires<[In64BitMode]>;
1966 def : Pat<(X86tcret (i64 texternalsym:$dst), imm:$off),
1967 (TCRETURNdi64 texternalsym:$dst, imm:$off)>,
1968 Requires<[In64BitMode]>;
1970 // tls has some funny stuff here...
1971 // This corresponds to movabs $foo@tpoff, %rax
1972 def : Pat<(i64 (X86Wrapper tglobaltlsaddr :$dst)),
1973 (MOV64ri tglobaltlsaddr :$dst)>;
1974 // This corresponds to add $foo@tpoff, %rax
1975 def : Pat<(add GR64:$src1, (X86Wrapper tglobaltlsaddr :$dst)),
1976 (ADD64ri32 GR64:$src1, tglobaltlsaddr :$dst)>;
1977 // This corresponds to mov foo@tpoff(%rbx), %eax
1978 def : Pat<(load (i64 (X86Wrapper tglobaltlsaddr :$dst))),
1979 (MOV64rm tglobaltlsaddr :$dst)>;
1983 // TEST R,R is smaller than CMP R,0
1984 def : Pat<(X86cmp GR64:$src1, 0),
1985 (TEST64rr GR64:$src1, GR64:$src1)>;
1987 // Conditional moves with folded loads with operands swapped and conditions
1989 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_B, EFLAGS),
1990 (CMOVAE64rm GR64:$src2, addr:$src1)>;
1991 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_AE, EFLAGS),
1992 (CMOVB64rm GR64:$src2, addr:$src1)>;
1993 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_E, EFLAGS),
1994 (CMOVNE64rm GR64:$src2, addr:$src1)>;
1995 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NE, EFLAGS),
1996 (CMOVE64rm GR64:$src2, addr:$src1)>;
1997 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_BE, EFLAGS),
1998 (CMOVA64rm GR64:$src2, addr:$src1)>;
1999 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_A, EFLAGS),
2000 (CMOVBE64rm GR64:$src2, addr:$src1)>;
2001 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_L, EFLAGS),
2002 (CMOVGE64rm GR64:$src2, addr:$src1)>;
2003 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_GE, EFLAGS),
2004 (CMOVL64rm GR64:$src2, addr:$src1)>;
2005 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_LE, EFLAGS),
2006 (CMOVG64rm GR64:$src2, addr:$src1)>;
2007 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_G, EFLAGS),
2008 (CMOVLE64rm GR64:$src2, addr:$src1)>;
2009 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_P, EFLAGS),
2010 (CMOVNP64rm GR64:$src2, addr:$src1)>;
2011 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NP, EFLAGS),
2012 (CMOVP64rm GR64:$src2, addr:$src1)>;
2013 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_S, EFLAGS),
2014 (CMOVNS64rm GR64:$src2, addr:$src1)>;
2015 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NS, EFLAGS),
2016 (CMOVS64rm GR64:$src2, addr:$src1)>;
2017 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_O, EFLAGS),
2018 (CMOVNO64rm GR64:$src2, addr:$src1)>;
2019 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NO, EFLAGS),
2020 (CMOVO64rm GR64:$src2, addr:$src1)>;
2022 // zextload bool -> zextload byte
2023 def : Pat<(zextloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>;
2026 // When extloading from 16-bit and smaller memory locations into 64-bit
2027 // registers, use zero-extending loads so that the entire 64-bit register is
2028 // defined, avoiding partial-register updates.
2029 def : Pat<(extloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>;
2030 def : Pat<(extloadi64i8 addr:$src), (MOVZX64rm8 addr:$src)>;
2031 def : Pat<(extloadi64i16 addr:$src), (MOVZX64rm16 addr:$src)>;
2032 // For other extloads, use subregs, since the high contents of the register are
2033 // defined after an extload.
2034 def : Pat<(extloadi64i32 addr:$src),
2035 (SUBREG_TO_REG (i64 0), (MOV32rm addr:$src),
2038 // anyext. Define these to do an explicit zero-extend to
2039 // avoid partial-register updates.
2040 def : Pat<(i64 (anyext GR8 :$src)), (MOVZX64rr8 GR8 :$src)>;
2041 def : Pat<(i64 (anyext GR16:$src)), (MOVZX64rr16 GR16 :$src)>;
2042 def : Pat<(i64 (anyext GR32:$src)),
2043 (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>;
2045 //===----------------------------------------------------------------------===//
2047 //===----------------------------------------------------------------------===//
2049 // Odd encoding trick: -128 fits into an 8-bit immediate field while
2050 // +128 doesn't, so in this special case use a sub instead of an add.
2051 def : Pat<(add GR64:$src1, 128),
2052 (SUB64ri8 GR64:$src1, -128)>;
2053 def : Pat<(store (add (loadi64 addr:$dst), 128), addr:$dst),
2054 (SUB64mi8 addr:$dst, -128)>;
2056 // The same trick applies for 32-bit immediate fields in 64-bit
2058 def : Pat<(add GR64:$src1, 0x0000000080000000),
2059 (SUB64ri32 GR64:$src1, 0xffffffff80000000)>;
2060 def : Pat<(store (add (loadi64 addr:$dst), 0x00000000800000000), addr:$dst),
2061 (SUB64mi32 addr:$dst, 0xffffffff80000000)>;
2063 // Use a 32-bit and with implicit zero-extension instead of a 64-bit and if it
2064 // has an immediate with at least 32 bits of leading zeros, to avoid needing to
2065 // materialize that immediate in a register first.
2066 def : Pat<(and GR64:$src, i64immZExt32:$imm),
2070 (EXTRACT_SUBREG GR64:$src, sub_32bit),
2071 (i32 (GetLo32XForm imm:$imm))),
2074 // r & (2^32-1) ==> movz
2075 def : Pat<(and GR64:$src, 0x00000000FFFFFFFF),
2076 (MOVZX64rr32 (EXTRACT_SUBREG GR64:$src, sub_32bit))>;
2077 // r & (2^16-1) ==> movz
2078 def : Pat<(and GR64:$src, 0xffff),
2079 (MOVZX64rr16 (i16 (EXTRACT_SUBREG GR64:$src, sub_16bit)))>;
2080 // r & (2^8-1) ==> movz
2081 def : Pat<(and GR64:$src, 0xff),
2082 (MOVZX64rr8 (i8 (EXTRACT_SUBREG GR64:$src, sub_8bit)))>;
2083 // r & (2^8-1) ==> movz
2084 def : Pat<(and GR32:$src1, 0xff),
2085 (MOVZX32rr8 (EXTRACT_SUBREG GR32:$src1, sub_8bit))>,
2086 Requires<[In64BitMode]>;
2087 // r & (2^8-1) ==> movz
2088 def : Pat<(and GR16:$src1, 0xff),
2089 (MOVZX16rr8 (i8 (EXTRACT_SUBREG GR16:$src1, sub_8bit)))>,
2090 Requires<[In64BitMode]>;
2092 // sext_inreg patterns
2093 def : Pat<(sext_inreg GR64:$src, i32),
2094 (MOVSX64rr32 (EXTRACT_SUBREG GR64:$src, sub_32bit))>;
2095 def : Pat<(sext_inreg GR64:$src, i16),
2096 (MOVSX64rr16 (EXTRACT_SUBREG GR64:$src, sub_16bit))>;
2097 def : Pat<(sext_inreg GR64:$src, i8),
2098 (MOVSX64rr8 (EXTRACT_SUBREG GR64:$src, sub_8bit))>;
2099 def : Pat<(sext_inreg GR32:$src, i8),
2100 (MOVSX32rr8 (EXTRACT_SUBREG GR32:$src, sub_8bit))>,
2101 Requires<[In64BitMode]>;
2102 def : Pat<(sext_inreg GR16:$src, i8),
2103 (MOVSX16rr8 (i8 (EXTRACT_SUBREG GR16:$src, sub_8bit)))>,
2104 Requires<[In64BitMode]>;
2107 def : Pat<(i32 (trunc GR64:$src)),
2108 (EXTRACT_SUBREG GR64:$src, sub_32bit)>;
2109 def : Pat<(i16 (trunc GR64:$src)),
2110 (EXTRACT_SUBREG GR64:$src, sub_16bit)>;
2111 def : Pat<(i8 (trunc GR64:$src)),
2112 (EXTRACT_SUBREG GR64:$src, sub_8bit)>;
2113 def : Pat<(i8 (trunc GR32:$src)),
2114 (EXTRACT_SUBREG GR32:$src, sub_8bit)>,
2115 Requires<[In64BitMode]>;
2116 def : Pat<(i8 (trunc GR16:$src)),
2117 (EXTRACT_SUBREG GR16:$src, sub_8bit)>,
2118 Requires<[In64BitMode]>;
2120 // h-register tricks.
2121 // For now, be conservative on x86-64 and use an h-register extract only if the
2122 // value is immediately zero-extended or stored, which are somewhat common
2123 // cases. This uses a bunch of code to prevent a register requiring a REX prefix
2124 // from being allocated in the same instruction as the h register, as there's
2125 // currently no way to describe this requirement to the register allocator.
2127 // h-register extract and zero-extend.
2128 def : Pat<(and (srl_su GR64:$src, (i8 8)), (i64 255)),
2132 (EXTRACT_SUBREG (i64 (COPY_TO_REGCLASS GR64:$src, GR64_ABCD)),
2135 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
2137 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
2139 Requires<[In64BitMode]>;
2140 def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)),
2141 (MOVZX32_NOREXrr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
2144 Requires<[In64BitMode]>;
2145 def : Pat<(srl GR16:$src, (i8 8)),
2148 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
2151 Requires<[In64BitMode]>;
2152 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
2154 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
2156 Requires<[In64BitMode]>;
2157 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
2159 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
2161 Requires<[In64BitMode]>;
2162 def : Pat<(i64 (zext (srl_su GR16:$src, (i8 8)))),
2166 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
2169 def : Pat<(i64 (anyext (srl_su GR16:$src, (i8 8)))),
2173 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
2177 // h-register extract and store.
2178 def : Pat<(store (i8 (trunc_su (srl_su GR64:$src, (i8 8)))), addr:$dst),
2181 (EXTRACT_SUBREG (i64 (COPY_TO_REGCLASS GR64:$src, GR64_ABCD)),
2183 def : Pat<(store (i8 (trunc_su (srl_su GR32:$src, (i8 8)))), addr:$dst),
2186 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
2188 Requires<[In64BitMode]>;
2189 def : Pat<(store (i8 (trunc_su (srl_su GR16:$src, (i8 8)))), addr:$dst),
2192 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
2194 Requires<[In64BitMode]>;
2196 // (shl x, 1) ==> (add x, x)
2197 def : Pat<(shl GR64:$src1, (i8 1)), (ADD64rr GR64:$src1, GR64:$src1)>;
2199 // (shl x (and y, 63)) ==> (shl x, y)
2200 def : Pat<(shl GR64:$src1, (and CL, 63)),
2201 (SHL64rCL GR64:$src1)>;
2202 def : Pat<(store (shl (loadi64 addr:$dst), (and CL, 63)), addr:$dst),
2203 (SHL64mCL addr:$dst)>;
2205 def : Pat<(srl GR64:$src1, (and CL, 63)),
2206 (SHR64rCL GR64:$src1)>;
2207 def : Pat<(store (srl (loadi64 addr:$dst), (and CL, 63)), addr:$dst),
2208 (SHR64mCL addr:$dst)>;
2210 def : Pat<(sra GR64:$src1, (and CL, 63)),
2211 (SAR64rCL GR64:$src1)>;
2212 def : Pat<(store (sra (loadi64 addr:$dst), (and CL, 63)), addr:$dst),
2213 (SAR64mCL addr:$dst)>;
2215 // (or x1, x2) -> (add x1, x2) if two operands are known not to share bits.
2216 let AddedComplexity = 5 in { // Try this before the selecting to OR
2217 def : Pat<(or_is_add GR64:$src1, i64immSExt8:$src2),
2218 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
2219 def : Pat<(or_is_add GR64:$src1, i64immSExt32:$src2),
2220 (ADD64ri32 GR64:$src1, i64immSExt32:$src2)>;
2221 def : Pat<(or_is_add GR64:$src1, GR64:$src2),
2222 (ADD64rr GR64:$src1, GR64:$src2)>;
2223 } // AddedComplexity
2225 // X86 specific add which produces a flag.
2226 def : Pat<(addc GR64:$src1, GR64:$src2),
2227 (ADD64rr GR64:$src1, GR64:$src2)>;
2228 def : Pat<(addc GR64:$src1, (load addr:$src2)),
2229 (ADD64rm GR64:$src1, addr:$src2)>;
2230 def : Pat<(addc GR64:$src1, i64immSExt8:$src2),
2231 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
2232 def : Pat<(addc GR64:$src1, i64immSExt32:$src2),
2233 (ADD64ri32 GR64:$src1, imm:$src2)>;
2235 def : Pat<(subc GR64:$src1, GR64:$src2),
2236 (SUB64rr GR64:$src1, GR64:$src2)>;
2237 def : Pat<(subc GR64:$src1, (load addr:$src2)),
2238 (SUB64rm GR64:$src1, addr:$src2)>;
2239 def : Pat<(subc GR64:$src1, i64immSExt8:$src2),
2240 (SUB64ri8 GR64:$src1, i64immSExt8:$src2)>;
2241 def : Pat<(subc GR64:$src1, imm:$src2),
2242 (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>;
2244 //===----------------------------------------------------------------------===//
2245 // EFLAGS-defining Patterns
2246 //===----------------------------------------------------------------------===//
2249 def : Pat<(add GR64:$src1, GR64:$src2),
2250 (ADD64rr GR64:$src1, GR64:$src2)>;
2251 def : Pat<(add GR64:$src1, i64immSExt8:$src2),
2252 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
2253 def : Pat<(add GR64:$src1, i64immSExt32:$src2),
2254 (ADD64ri32 GR64:$src1, i64immSExt32:$src2)>;
2255 def : Pat<(add GR64:$src1, (loadi64 addr:$src2)),
2256 (ADD64rm GR64:$src1, addr:$src2)>;
2259 def : Pat<(sub GR64:$src1, GR64:$src2),
2260 (SUB64rr GR64:$src1, GR64:$src2)>;
2261 def : Pat<(sub GR64:$src1, (loadi64 addr:$src2)),
2262 (SUB64rm GR64:$src1, addr:$src2)>;
2263 def : Pat<(sub GR64:$src1, i64immSExt8:$src2),
2264 (SUB64ri8 GR64:$src1, i64immSExt8:$src2)>;
2265 def : Pat<(sub GR64:$src1, i64immSExt32:$src2),
2266 (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>;
2269 def : Pat<(mul GR64:$src1, GR64:$src2),
2270 (IMUL64rr GR64:$src1, GR64:$src2)>;
2271 def : Pat<(mul GR64:$src1, (loadi64 addr:$src2)),
2272 (IMUL64rm GR64:$src1, addr:$src2)>;
2273 def : Pat<(mul GR64:$src1, i64immSExt8:$src2),
2274 (IMUL64rri8 GR64:$src1, i64immSExt8:$src2)>;
2275 def : Pat<(mul GR64:$src1, i64immSExt32:$src2),
2276 (IMUL64rri32 GR64:$src1, i64immSExt32:$src2)>;
2277 def : Pat<(mul (loadi64 addr:$src1), i64immSExt8:$src2),
2278 (IMUL64rmi8 addr:$src1, i64immSExt8:$src2)>;
2279 def : Pat<(mul (loadi64 addr:$src1), i64immSExt32:$src2),
2280 (IMUL64rmi32 addr:$src1, i64immSExt32:$src2)>;
2283 def : Pat<(add GR16:$src, 1), (INC64_16r GR16:$src)>, Requires<[In64BitMode]>;
2284 def : Pat<(add GR16:$src, -1), (DEC64_16r GR16:$src)>, Requires<[In64BitMode]>;
2285 def : Pat<(add GR32:$src, 1), (INC64_32r GR32:$src)>, Requires<[In64BitMode]>;
2286 def : Pat<(add GR32:$src, -1), (DEC64_32r GR32:$src)>, Requires<[In64BitMode]>;
2287 def : Pat<(add GR64:$src, 1), (INC64r GR64:$src)>;
2288 def : Pat<(add GR64:$src, -1), (DEC64r GR64:$src)>;
2291 def : Pat<(or GR64:$src1, GR64:$src2),
2292 (OR64rr GR64:$src1, GR64:$src2)>;
2293 def : Pat<(or GR64:$src1, i64immSExt8:$src2),
2294 (OR64ri8 GR64:$src1, i64immSExt8:$src2)>;
2295 def : Pat<(or GR64:$src1, i64immSExt32:$src2),
2296 (OR64ri32 GR64:$src1, i64immSExt32:$src2)>;
2297 def : Pat<(or GR64:$src1, (loadi64 addr:$src2)),
2298 (OR64rm GR64:$src1, addr:$src2)>;
2301 def : Pat<(xor GR64:$src1, GR64:$src2),
2302 (XOR64rr GR64:$src1, GR64:$src2)>;
2303 def : Pat<(xor GR64:$src1, i64immSExt8:$src2),
2304 (XOR64ri8 GR64:$src1, i64immSExt8:$src2)>;
2305 def : Pat<(xor GR64:$src1, i64immSExt32:$src2),
2306 (XOR64ri32 GR64:$src1, i64immSExt32:$src2)>;
2307 def : Pat<(xor GR64:$src1, (loadi64 addr:$src2)),
2308 (XOR64rm GR64:$src1, addr:$src2)>;
2311 def : Pat<(and GR64:$src1, GR64:$src2),
2312 (AND64rr GR64:$src1, GR64:$src2)>;
2313 def : Pat<(and GR64:$src1, i64immSExt8:$src2),
2314 (AND64ri8 GR64:$src1, i64immSExt8:$src2)>;
2315 def : Pat<(and GR64:$src1, i64immSExt32:$src2),
2316 (AND64ri32 GR64:$src1, i64immSExt32:$src2)>;
2317 def : Pat<(and GR64:$src1, (loadi64 addr:$src2)),
2318 (AND64rm GR64:$src1, addr:$src2)>;
2320 //===----------------------------------------------------------------------===//
2321 // X86-64 SSE Instructions
2322 //===----------------------------------------------------------------------===//
2324 // Move instructions...
2326 def MOV64toPQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
2327 "mov{d|q}\t{$src, $dst|$dst, $src}",
2329 (v2i64 (scalar_to_vector GR64:$src)))]>;
2330 def MOVPQIto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
2331 "mov{d|q}\t{$src, $dst|$dst, $src}",
2332 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
2335 def MOV64toSDrr : RPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
2336 "mov{d|q}\t{$src, $dst|$dst, $src}",
2337 [(set FR64:$dst, (bitconvert GR64:$src))]>;
2338 def MOV64toSDrm : S3SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
2339 "movq\t{$src, $dst|$dst, $src}",
2340 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>;
2342 def MOVSDto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
2343 "mov{d|q}\t{$src, $dst|$dst, $src}",
2344 [(set GR64:$dst, (bitconvert FR64:$src))]>;
2345 def MOVSDto64mr : RPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
2346 "movq\t{$src, $dst|$dst, $src}",
2347 [(store (i64 (bitconvert FR64:$src)), addr:$dst)]>;