1 //====- X86Instr64bit.td - Describe X86-64 Instructions ----*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86-64 instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // Operand Definitions.
20 // 64-bits but only 32 bits are significant.
21 def i64i32imm : Operand<i64> {
22 let ParserMatchClass = ImmSExti64i32AsmOperand;
25 // 64-bits but only 32 bits are significant, and those bits are treated as being
27 def i64i32imm_pcrel : Operand<i64> {
28 let PrintMethod = "print_pcrel_imm";
29 let ParserMatchClass = X86AbsMemAsmOperand;
33 // 64-bits but only 8 bits are significant.
34 def i64i8imm : Operand<i64> {
35 let ParserMatchClass = ImmSExti64i8AsmOperand;
38 def lea64_32mem : Operand<i32> {
39 let PrintMethod = "printi32mem";
40 let AsmOperandLowerMethod = "lower_lea64_32mem";
41 let MIOperandInfo = (ops GR32, i8imm, GR32_NOSP, i32imm, i8imm);
42 let ParserMatchClass = X86MemAsmOperand;
46 // Special i64mem for addresses of load folding tail calls. These are not
47 // allowed to use callee-saved registers since they must be scheduled
48 // after callee-saved register are popped.
49 def i64mem_TC : Operand<i64> {
50 let PrintMethod = "printi64mem";
51 let MIOperandInfo = (ops GR64_TC, i8imm, GR64_TC, i32imm, i8imm);
52 let ParserMatchClass = X86MemAsmOperand;
55 //===----------------------------------------------------------------------===//
56 // Complex Pattern Definitions.
58 def lea64addr : ComplexPattern<i64, 5, "SelectLEAAddr",
59 [add, sub, mul, X86mul_imm, shl, or, frameindex,
62 def tls64addr : ComplexPattern<i64, 5, "SelectTLSADDRAddr",
63 [tglobaltlsaddr], []>;
65 //===----------------------------------------------------------------------===//
69 def i64immSExt8 : PatLeaf<(i64 immSext8)>;
71 def GetLo32XForm : SDNodeXForm<imm, [{
72 // Transformation function: get the low 32 bits.
73 return getI32Imm((unsigned)N->getZExtValue());
76 def i64immSExt32 : PatLeaf<(i64 imm), [{
77 // i64immSExt32 predicate - True if the 64-bit immediate fits in a 32-bit
78 // sign extended field.
79 return (int64_t)N->getZExtValue() == (int32_t)N->getZExtValue();
83 def i64immZExt32 : PatLeaf<(i64 imm), [{
84 // i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit
85 // unsignedsign extended field.
86 return (uint64_t)N->getZExtValue() == (uint32_t)N->getZExtValue();
89 def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>;
90 def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>;
91 def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>;
93 def zextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (zextloadi1 node:$ptr))>;
94 def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>;
95 def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>;
96 def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>;
98 def extloadi64i1 : PatFrag<(ops node:$ptr), (i64 (extloadi1 node:$ptr))>;
99 def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>;
100 def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>;
101 def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>;
103 //===----------------------------------------------------------------------===//
104 // Instruction list...
107 // ADJCALLSTACKDOWN/UP implicitly use/def RSP because they may be expanded into
108 // a stack adjustment and the codegen must know that they may modify the stack
109 // pointer before prolog-epilog rewriting occurs.
110 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
111 // sub / add which can clobber EFLAGS.
112 let Defs = [RSP, EFLAGS], Uses = [RSP] in {
113 def ADJCALLSTACKDOWN64 : I<0, Pseudo, (outs), (ins i32imm:$amt),
115 [(X86callseq_start timm:$amt)]>,
116 Requires<[In64BitMode]>;
117 def ADJCALLSTACKUP64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
119 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
120 Requires<[In64BitMode]>;
123 // Interrupt Instructions
124 def IRET64 : RI<0xcf, RawFrm, (outs), (ins), "iret{q}", []>;
126 //===----------------------------------------------------------------------===//
127 // Call Instructions...
130 // All calls clobber the non-callee saved registers. RSP is marked as
131 // a use to prevent stack-pointer assignments that appear immediately
132 // before calls from potentially appearing dead. Uses for argument
133 // registers are added manually.
134 let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
135 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
136 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
137 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
138 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
141 // NOTE: this pattern doesn't match "X86call imm", because we do not know
142 // that the offset between an arbitrary immediate and the call will fit in
143 // the 32-bit pcrel field that we have.
144 def CALL64pcrel32 : Ii32PCRel<0xE8, RawFrm,
145 (outs), (ins i64i32imm_pcrel:$dst, variable_ops),
146 "call{q}\t$dst", []>,
147 Requires<[In64BitMode, NotWin64]>;
148 def CALL64r : I<0xFF, MRM2r, (outs), (ins GR64:$dst, variable_ops),
149 "call{q}\t{*}$dst", [(X86call GR64:$dst)]>,
150 Requires<[NotWin64]>;
151 def CALL64m : I<0xFF, MRM2m, (outs), (ins i64mem:$dst, variable_ops),
152 "call{q}\t{*}$dst", [(X86call (loadi64 addr:$dst))]>,
153 Requires<[NotWin64]>;
155 def FARCALL64 : RI<0xFF, MRM3m, (outs), (ins opaque80mem:$dst),
156 "lcall{q}\t{*}$dst", []>;
159 // FIXME: We need to teach codegen about single list of call-clobbered
161 let isCall = 1, isCodeGenOnly = 1 in
162 // All calls clobber the non-callee saved registers. RSP is marked as
163 // a use to prevent stack-pointer assignments that appear immediately
164 // before calls from potentially appearing dead. Uses for argument
165 // registers are added manually.
166 let Defs = [RAX, RCX, RDX, R8, R9, R10, R11,
167 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
168 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
169 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, EFLAGS],
171 def WINCALL64pcrel32 : Ii32PCRel<0xE8, RawFrm,
172 (outs), (ins i64i32imm_pcrel:$dst, variable_ops),
175 def WINCALL64r : I<0xFF, MRM2r, (outs), (ins GR64:$dst, variable_ops),
177 [(X86call GR64:$dst)]>, Requires<[IsWin64]>;
178 def WINCALL64m : I<0xFF, MRM2m, (outs),
179 (ins i64mem:$dst, variable_ops), "call\t{*}$dst",
180 [(X86call (loadi64 addr:$dst))]>,
185 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1,
187 let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
188 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
189 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
190 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
191 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
193 def TCRETURNdi64 : I<0, Pseudo, (outs),
194 (ins i64i32imm_pcrel:$dst, i32imm:$offset, variable_ops),
195 "#TC_RETURN $dst $offset", []>;
196 def TCRETURNri64 : I<0, Pseudo, (outs), (ins GR64_TC:$dst, i32imm:$offset,
198 "#TC_RETURN $dst $offset", []>;
200 def TCRETURNmi64 : I<0, Pseudo, (outs),
201 (ins i64mem_TC:$dst, i32imm:$offset, variable_ops),
202 "#TC_RETURN $dst $offset", []>;
204 def TAILJMPd64 : Ii32PCRel<0xE9, RawFrm, (outs),
205 (ins i64i32imm_pcrel:$dst, variable_ops),
206 "jmp\t$dst # TAILCALL", []>;
207 def TAILJMPr64 : I<0xFF, MRM4r, (outs), (ins GR64_TC:$dst, variable_ops),
208 "jmp{q}\t{*}$dst # TAILCALL", []>;
211 def TAILJMPm64 : I<0xFF, MRM4m, (outs), (ins i64mem_TC:$dst, variable_ops),
212 "jmp{q}\t{*}$dst # TAILCALL", []>;
216 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
217 def JMP64pcrel32 : I<0xE9, RawFrm, (outs), (ins brtarget:$dst),
219 def JMP64r : I<0xFF, MRM4r, (outs), (ins GR64:$dst), "jmp{q}\t{*}$dst",
220 [(brind GR64:$dst)]>, Requires<[In64BitMode]>;
221 def JMP64m : I<0xFF, MRM4m, (outs), (ins i64mem:$dst), "jmp{q}\t{*}$dst",
222 [(brind (loadi64 addr:$dst))]>, Requires<[In64BitMode]>;
223 def FARJMP64 : RI<0xFF, MRM5m, (outs), (ins opaque80mem:$dst),
224 "ljmp{q}\t{*}$dst", []>;
227 //===----------------------------------------------------------------------===//
228 // EH Pseudo Instructions
230 let isTerminator = 1, isReturn = 1, isBarrier = 1,
231 hasCtrlDep = 1, isCodeGenOnly = 1 in {
232 def EH_RETURN64 : I<0xC3, RawFrm, (outs), (ins GR64:$addr),
233 "ret\t#eh_return, addr: $addr",
234 [(X86ehret GR64:$addr)]>;
238 //===----------------------------------------------------------------------===//
239 // Miscellaneous Instructions...
242 def POPCNT64rr : RI<0xB8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
243 "popcnt{q}\t{$src, $dst|$dst, $src}", []>, XS;
245 def POPCNT64rm : RI<0xB8, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
246 "popcnt{q}\t{$src, $dst|$dst, $src}", []>, XS;
248 let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, neverHasSideEffects = 1 in
249 def LEAVE64 : I<0xC9, RawFrm,
250 (outs), (ins), "leave", []>, Requires<[In64BitMode]>;
251 let Defs = [RSP], Uses = [RSP], neverHasSideEffects=1 in {
253 def POP64r : I<0x58, AddRegFrm,
254 (outs GR64:$reg), (ins), "pop{q}\t$reg", []>;
255 def POP64rmr: I<0x8F, MRM0r, (outs GR64:$reg), (ins), "pop{q}\t$reg", []>;
256 def POP64rmm: I<0x8F, MRM0m, (outs i64mem:$dst), (ins), "pop{q}\t$dst", []>;
258 let mayStore = 1 in {
259 def PUSH64r : I<0x50, AddRegFrm,
260 (outs), (ins GR64:$reg), "push{q}\t$reg", []>;
261 def PUSH64rmr: I<0xFF, MRM6r, (outs), (ins GR64:$reg), "push{q}\t$reg", []>;
262 def PUSH64rmm: I<0xFF, MRM6m, (outs), (ins i64mem:$src), "push{q}\t$src", []>;
266 let Defs = [RSP], Uses = [RSP], neverHasSideEffects = 1, mayStore = 1 in {
267 def PUSH64i8 : Ii8<0x6a, RawFrm, (outs), (ins i8imm:$imm),
268 "push{q}\t$imm", []>;
269 def PUSH64i16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
270 "push{q}\t$imm", []>;
271 def PUSH64i32 : Ii32<0x68, RawFrm, (outs), (ins i64i32imm:$imm),
272 "push{q}\t$imm", []>;
275 let Defs = [RSP, EFLAGS], Uses = [RSP], mayLoad = 1, neverHasSideEffects=1 in
276 def POPF64 : I<0x9D, RawFrm, (outs), (ins), "popfq", []>,
277 Requires<[In64BitMode]>;
278 let Defs = [RSP], Uses = [RSP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in
279 def PUSHF64 : I<0x9C, RawFrm, (outs), (ins), "pushfq", []>,
280 Requires<[In64BitMode]>;
282 def LEA64_32r : I<0x8D, MRMSrcMem,
283 (outs GR32:$dst), (ins lea64_32mem:$src),
284 "lea{l}\t{$src|$dst}, {$dst|$src}",
285 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In64BitMode]>;
287 let isReMaterializable = 1 in
288 def LEA64r : RI<0x8D, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
289 "lea{q}\t{$src|$dst}, {$dst|$src}",
290 [(set GR64:$dst, lea64addr:$src)]>;
292 let Constraints = "$src = $dst" in
293 def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src),
295 [(set GR64:$dst, (bswap GR64:$src))]>, TB;
297 // Bit scan instructions.
298 let Defs = [EFLAGS] in {
299 def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
300 "bsf{q}\t{$src, $dst|$dst, $src}",
301 [(set GR64:$dst, EFLAGS, (X86bsf GR64:$src))]>, TB;
302 def BSF64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
303 "bsf{q}\t{$src, $dst|$dst, $src}",
304 [(set GR64:$dst, EFLAGS, (X86bsf (loadi64 addr:$src)))]>, TB;
306 def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
307 "bsr{q}\t{$src, $dst|$dst, $src}",
308 [(set GR64:$dst, EFLAGS, (X86bsr GR64:$src))]>, TB;
309 def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
310 "bsr{q}\t{$src, $dst|$dst, $src}",
311 [(set GR64:$dst, EFLAGS, (X86bsr (loadi64 addr:$src)))]>, TB;
315 let Defs = [RCX,RDI,RSI], Uses = [RCX,RDI,RSI], isCodeGenOnly = 1 in
316 def REP_MOVSQ : RI<0xA5, RawFrm, (outs), (ins), "{rep;movsq|rep movsq}",
317 [(X86rep_movs i64)]>, REP;
318 let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI], isCodeGenOnly = 1 in
319 def REP_STOSQ : RI<0xAB, RawFrm, (outs), (ins), "{rep;stosq|rep stosq}",
320 [(X86rep_stos i64)]>, REP;
322 let Defs = [EDI,ESI], Uses = [EDI,ESI,EFLAGS] in
323 def MOVSQ : RI<0xA5, RawFrm, (outs), (ins), "movsq", []>;
325 let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI,EFLAGS] in
326 def STOSQ : RI<0xAB, RawFrm, (outs), (ins), "stosq", []>;
328 def SCAS64 : RI<0xAF, RawFrm, (outs), (ins), "scasq", []>;
330 def CMPS64 : RI<0xA7, RawFrm, (outs), (ins), "cmpsq", []>;
332 // Fast system-call instructions
333 def SYSEXIT64 : RI<0x35, RawFrm,
334 (outs), (ins), "sysexit", []>, TB, Requires<[In64BitMode]>;
336 //===----------------------------------------------------------------------===//
337 // Move Instructions...
340 let neverHasSideEffects = 1 in
341 def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
342 "mov{q}\t{$src, $dst|$dst, $src}", []>;
344 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
345 def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src),
346 "movabs{q}\t{$src, $dst|$dst, $src}",
347 [(set GR64:$dst, imm:$src)]>;
348 def MOV64ri32 : RIi32<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src),
349 "mov{q}\t{$src, $dst|$dst, $src}",
350 [(set GR64:$dst, i64immSExt32:$src)]>;
353 // The assembler accepts movq of a 64-bit immediate as an alternate spelling of
355 let isAsmParserOnly = 1 in {
356 def MOV64ri_alt : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src),
357 "mov{q}\t{$src, $dst|$dst, $src}", []>;
360 let isCodeGenOnly = 1 in {
361 def MOV64rr_REV : RI<0x8B, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
362 "mov{q}\t{$src, $dst|$dst, $src}", []>;
365 let canFoldAsLoad = 1, isReMaterializable = 1 in
366 def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
367 "mov{q}\t{$src, $dst|$dst, $src}",
368 [(set GR64:$dst, (load addr:$src))]>;
370 def MOV64mr : RI<0x89, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
371 "mov{q}\t{$src, $dst|$dst, $src}",
372 [(store GR64:$src, addr:$dst)]>;
373 def MOV64mi32 : RIi32<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src),
374 "mov{q}\t{$src, $dst|$dst, $src}",
375 [(store i64immSExt32:$src, addr:$dst)]>;
377 /// Versions of MOV64rr, MOV64rm, and MOV64mr for i64mem_TC and GR64_TC.
378 let isCodeGenOnly = 1 in {
379 let neverHasSideEffects = 1 in
380 def MOV64rr_TC : RI<0x89, MRMDestReg, (outs GR64_TC:$dst), (ins GR64_TC:$src),
381 "mov{q}\t{$src, $dst|$dst, $src}", []>;
384 canFoldAsLoad = 1, isReMaterializable = 1 in
385 def MOV64rm_TC : RI<0x8B, MRMSrcMem, (outs GR64_TC:$dst), (ins i64mem_TC:$src),
386 "mov{q}\t{$src, $dst|$dst, $src}",
390 def MOV64mr_TC : RI<0x89, MRMDestMem, (outs), (ins i64mem_TC:$dst, GR64_TC:$src),
391 "mov{q}\t{$src, $dst|$dst, $src}",
395 // FIXME: These definitions are utterly broken
396 // Just leave them commented out for now because they're useless outside
397 // of the large code model, and most compilers won't generate the instructions
400 def MOV64o8a : RIi8<0xA0, RawFrm, (outs), (ins offset8:$src),
401 "mov{q}\t{$src, %rax|%rax, $src}", []>;
402 def MOV64o64a : RIi32<0xA1, RawFrm, (outs), (ins offset64:$src),
403 "mov{q}\t{$src, %rax|%rax, $src}", []>;
404 def MOV64ao8 : RIi8<0xA2, RawFrm, (outs offset8:$dst), (ins),
405 "mov{q}\t{%rax, $dst|$dst, %rax}", []>;
406 def MOV64ao64 : RIi32<0xA3, RawFrm, (outs offset64:$dst), (ins),
407 "mov{q}\t{%rax, $dst|$dst, %rax}", []>;
410 // Moves to and from segment registers
411 def MOV64rs : RI<0x8C, MRMDestReg, (outs GR64:$dst), (ins SEGMENT_REG:$src),
412 "mov{q}\t{$src, $dst|$dst, $src}", []>;
413 def MOV64ms : RI<0x8C, MRMDestMem, (outs i64mem:$dst), (ins SEGMENT_REG:$src),
414 "mov{q}\t{$src, $dst|$dst, $src}", []>;
415 def MOV64sr : RI<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR64:$src),
416 "mov{q}\t{$src, $dst|$dst, $src}", []>;
417 def MOV64sm : RI<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i64mem:$src),
418 "mov{q}\t{$src, $dst|$dst, $src}", []>;
420 // Moves to and from debug registers
421 def MOV64rd : I<0x21, MRMDestReg, (outs GR64:$dst), (ins DEBUG_REG:$src),
422 "mov{q}\t{$src, $dst|$dst, $src}", []>, TB;
423 def MOV64dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR64:$src),
424 "mov{q}\t{$src, $dst|$dst, $src}", []>, TB;
426 // Moves to and from control registers
427 def MOV64rc : I<0x20, MRMDestReg, (outs GR64:$dst), (ins CONTROL_REG:$src),
428 "mov{q}\t{$src, $dst|$dst, $src}", []>, TB;
429 def MOV64cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR64:$src),
430 "mov{q}\t{$src, $dst|$dst, $src}", []>, TB;
432 // Sign/Zero extenders
434 // MOVSX64rr8 always has a REX prefix and it has an 8-bit register
435 // operand, which makes it a rare instruction with an 8-bit register
436 // operand that can never access an h register. If support for h registers
437 // were generalized, this would require a special register class.
438 def MOVSX64rr8 : RI<0xBE, MRMSrcReg, (outs GR64:$dst), (ins GR8 :$src),
439 "movs{bq|x}\t{$src, $dst|$dst, $src}",
440 [(set GR64:$dst, (sext GR8:$src))]>, TB;
441 def MOVSX64rm8 : RI<0xBE, MRMSrcMem, (outs GR64:$dst), (ins i8mem :$src),
442 "movs{bq|x}\t{$src, $dst|$dst, $src}",
443 [(set GR64:$dst, (sextloadi64i8 addr:$src))]>, TB;
444 def MOVSX64rr16: RI<0xBF, MRMSrcReg, (outs GR64:$dst), (ins GR16:$src),
445 "movs{wq|x}\t{$src, $dst|$dst, $src}",
446 [(set GR64:$dst, (sext GR16:$src))]>, TB;
447 def MOVSX64rm16: RI<0xBF, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
448 "movs{wq|x}\t{$src, $dst|$dst, $src}",
449 [(set GR64:$dst, (sextloadi64i16 addr:$src))]>, TB;
450 def MOVSX64rr32: RI<0x63, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src),
451 "movs{lq|xd}\t{$src, $dst|$dst, $src}",
452 [(set GR64:$dst, (sext GR32:$src))]>;
453 def MOVSX64rm32: RI<0x63, MRMSrcMem, (outs GR64:$dst), (ins i32mem:$src),
454 "movs{lq|xd}\t{$src, $dst|$dst, $src}",
455 [(set GR64:$dst, (sextloadi64i32 addr:$src))]>;
457 // movzbq and movzwq encodings for the disassembler
458 def MOVZX64rr8_Q : RI<0xB6, MRMSrcReg, (outs GR64:$dst), (ins GR8:$src),
459 "movz{bq|x}\t{$src, $dst|$dst, $src}", []>, TB;
460 def MOVZX64rm8_Q : RI<0xB6, MRMSrcMem, (outs GR64:$dst), (ins i8mem:$src),
461 "movz{bq|x}\t{$src, $dst|$dst, $src}", []>, TB;
462 def MOVZX64rr16_Q : RI<0xB7, MRMSrcReg, (outs GR64:$dst), (ins GR16:$src),
463 "movz{wq|x}\t{$src, $dst|$dst, $src}", []>, TB;
464 def MOVZX64rm16_Q : RI<0xB7, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
465 "movz{wq|x}\t{$src, $dst|$dst, $src}", []>, TB;
467 // Use movzbl instead of movzbq when the destination is a register; it's
468 // equivalent due to implicit zero-extending, and it has a smaller encoding.
469 def MOVZX64rr8 : I<0xB6, MRMSrcReg, (outs GR64:$dst), (ins GR8 :$src),
470 "", [(set GR64:$dst, (zext GR8:$src))]>, TB;
471 def MOVZX64rm8 : I<0xB6, MRMSrcMem, (outs GR64:$dst), (ins i8mem :$src),
472 "", [(set GR64:$dst, (zextloadi64i8 addr:$src))]>, TB;
473 // Use movzwl instead of movzwq when the destination is a register; it's
474 // equivalent due to implicit zero-extending, and it has a smaller encoding.
475 def MOVZX64rr16: I<0xB7, MRMSrcReg, (outs GR64:$dst), (ins GR16:$src),
476 "", [(set GR64:$dst, (zext GR16:$src))]>, TB;
477 def MOVZX64rm16: I<0xB7, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
478 "", [(set GR64:$dst, (zextloadi64i16 addr:$src))]>, TB;
480 // There's no movzlq instruction, but movl can be used for this purpose, using
481 // implicit zero-extension. The preferred way to do 32-bit-to-64-bit zero
482 // extension on x86-64 is to use a SUBREG_TO_REG to utilize implicit
483 // zero-extension, however this isn't possible when the 32-bit value is
484 // defined by a truncate or is copied from something where the high bits aren't
485 // necessarily all zero. In such cases, we fall back to these explicit zext
487 def MOVZX64rr32 : I<0x89, MRMDestReg, (outs GR64:$dst), (ins GR32:$src),
488 "", [(set GR64:$dst, (zext GR32:$src))]>;
489 def MOVZX64rm32 : I<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i32mem:$src),
490 "", [(set GR64:$dst, (zextloadi64i32 addr:$src))]>;
492 // Any instruction that defines a 32-bit result leaves the high half of the
493 // register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may
494 // be copying from a truncate. And x86's cmov doesn't do anything if the
495 // condition is false. But any other 32-bit operation will zero-extend
497 def def32 : PatLeaf<(i32 GR32:$src), [{
498 return N->getOpcode() != ISD::TRUNCATE &&
499 N->getOpcode() != TargetOpcode::EXTRACT_SUBREG &&
500 N->getOpcode() != ISD::CopyFromReg &&
501 N->getOpcode() != X86ISD::CMOV;
504 // In the case of a 32-bit def that is known to implicitly zero-extend,
505 // we can use a SUBREG_TO_REG.
506 def : Pat<(i64 (zext def32:$src)),
507 (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>;
509 let neverHasSideEffects = 1 in {
510 let Defs = [RAX], Uses = [EAX] in
511 def CDQE : RI<0x98, RawFrm, (outs), (ins),
512 "{cltq|cdqe}", []>; // RAX = signext(EAX)
514 let Defs = [RAX,RDX], Uses = [RAX] in
515 def CQO : RI<0x99, RawFrm, (outs), (ins),
516 "{cqto|cqo}", []>; // RDX:RAX = signext(RAX)
519 //===----------------------------------------------------------------------===//
520 // Arithmetic Instructions...
523 let Defs = [EFLAGS] in {
525 def ADD64i32 : RIi32<0x05, RawFrm, (outs), (ins i64i32imm:$src),
526 "add{q}\t{$src, %rax|%rax, $src}", []>;
528 let Constraints = "$src1 = $dst" in {
529 let isConvertibleToThreeAddress = 1 in {
530 let isCommutable = 1 in
531 // Register-Register Addition
532 def ADD64rr : RI<0x01, MRMDestReg, (outs GR64:$dst),
533 (ins GR64:$src1, GR64:$src2),
534 "add{q}\t{$src2, $dst|$dst, $src2}",
535 [(set GR64:$dst, EFLAGS,
536 (X86add_flag GR64:$src1, GR64:$src2))]>;
538 // These are alternate spellings for use by the disassembler, we mark them as
539 // code gen only to ensure they aren't matched by the assembler.
540 let isCodeGenOnly = 1 in {
541 def ADD64rr_alt : RI<0x03, MRMSrcReg, (outs GR64:$dst),
542 (ins GR64:$src1, GR64:$src2),
543 "add{l}\t{$src2, $dst|$dst, $src2}", []>;
546 // Register-Integer Addition
547 def ADD64ri8 : RIi8<0x83, MRM0r, (outs GR64:$dst),
548 (ins GR64:$src1, i64i8imm:$src2),
549 "add{q}\t{$src2, $dst|$dst, $src2}",
550 [(set GR64:$dst, EFLAGS,
551 (X86add_flag GR64:$src1, i64immSExt8:$src2))]>;
552 def ADD64ri32 : RIi32<0x81, MRM0r, (outs GR64:$dst),
553 (ins GR64:$src1, i64i32imm:$src2),
554 "add{q}\t{$src2, $dst|$dst, $src2}",
555 [(set GR64:$dst, EFLAGS,
556 (X86add_flag GR64:$src1, i64immSExt32:$src2))]>;
557 } // isConvertibleToThreeAddress
559 // Register-Memory Addition
560 def ADD64rm : RI<0x03, MRMSrcMem, (outs GR64:$dst),
561 (ins GR64:$src1, i64mem:$src2),
562 "add{q}\t{$src2, $dst|$dst, $src2}",
563 [(set GR64:$dst, EFLAGS,
564 (X86add_flag GR64:$src1, (load addr:$src2)))]>;
566 } // Constraints = "$src1 = $dst"
568 // Memory-Register Addition
569 def ADD64mr : RI<0x01, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
570 "add{q}\t{$src2, $dst|$dst, $src2}",
571 [(store (add (load addr:$dst), GR64:$src2), addr:$dst),
573 def ADD64mi8 : RIi8<0x83, MRM0m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
574 "add{q}\t{$src2, $dst|$dst, $src2}",
575 [(store (add (load addr:$dst), i64immSExt8:$src2), addr:$dst),
577 def ADD64mi32 : RIi32<0x81, MRM0m, (outs), (ins i64mem:$dst, i64i32imm :$src2),
578 "add{q}\t{$src2, $dst|$dst, $src2}",
579 [(store (add (load addr:$dst), i64immSExt32:$src2), addr:$dst),
582 let Uses = [EFLAGS] in {
584 def ADC64i32 : RIi32<0x15, RawFrm, (outs), (ins i64i32imm:$src),
585 "adc{q}\t{$src, %rax|%rax, $src}", []>;
587 let Constraints = "$src1 = $dst" in {
588 let isCommutable = 1 in
589 def ADC64rr : RI<0x11, MRMDestReg, (outs GR64:$dst),
590 (ins GR64:$src1, GR64:$src2),
591 "adc{q}\t{$src2, $dst|$dst, $src2}",
592 [(set GR64:$dst, (adde GR64:$src1, GR64:$src2))]>;
594 let isCodeGenOnly = 1 in {
595 def ADC64rr_REV : RI<0x13, MRMSrcReg , (outs GR32:$dst),
596 (ins GR64:$src1, GR64:$src2),
597 "adc{q}\t{$src2, $dst|$dst, $src2}", []>;
600 def ADC64rm : RI<0x13, MRMSrcMem , (outs GR64:$dst),
601 (ins GR64:$src1, i64mem:$src2),
602 "adc{q}\t{$src2, $dst|$dst, $src2}",
603 [(set GR64:$dst, (adde GR64:$src1, (load addr:$src2)))]>;
605 def ADC64ri8 : RIi8<0x83, MRM2r, (outs GR64:$dst),
606 (ins GR64:$src1, i64i8imm:$src2),
607 "adc{q}\t{$src2, $dst|$dst, $src2}",
608 [(set GR64:$dst, (adde GR64:$src1, i64immSExt8:$src2))]>;
609 def ADC64ri32 : RIi32<0x81, MRM2r, (outs GR64:$dst),
610 (ins GR64:$src1, i64i32imm:$src2),
611 "adc{q}\t{$src2, $dst|$dst, $src2}",
612 [(set GR64:$dst, (adde GR64:$src1, i64immSExt32:$src2))]>;
613 } // Constraints = "$src1 = $dst"
615 def ADC64mr : RI<0x11, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
616 "adc{q}\t{$src2, $dst|$dst, $src2}",
617 [(store (adde (load addr:$dst), GR64:$src2), addr:$dst)]>;
618 def ADC64mi8 : RIi8<0x83, MRM2m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
619 "adc{q}\t{$src2, $dst|$dst, $src2}",
620 [(store (adde (load addr:$dst), i64immSExt8:$src2),
622 def ADC64mi32 : RIi32<0x81, MRM2m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
623 "adc{q}\t{$src2, $dst|$dst, $src2}",
624 [(store (adde (load addr:$dst), i64immSExt32:$src2),
628 let Constraints = "$src1 = $dst" in {
629 // Register-Register Subtraction
630 def SUB64rr : RI<0x29, MRMDestReg, (outs GR64:$dst),
631 (ins GR64:$src1, GR64:$src2),
632 "sub{q}\t{$src2, $dst|$dst, $src2}",
633 [(set GR64:$dst, EFLAGS,
634 (X86sub_flag GR64:$src1, GR64:$src2))]>;
636 let isCodeGenOnly = 1 in {
637 def SUB64rr_REV : RI<0x2B, MRMSrcReg, (outs GR64:$dst),
638 (ins GR64:$src1, GR64:$src2),
639 "sub{q}\t{$src2, $dst|$dst, $src2}", []>;
642 // Register-Memory Subtraction
643 def SUB64rm : RI<0x2B, MRMSrcMem, (outs GR64:$dst),
644 (ins GR64:$src1, i64mem:$src2),
645 "sub{q}\t{$src2, $dst|$dst, $src2}",
646 [(set GR64:$dst, EFLAGS,
647 (X86sub_flag GR64:$src1, (load addr:$src2)))]>;
649 // Register-Integer Subtraction
650 def SUB64ri8 : RIi8<0x83, MRM5r, (outs GR64:$dst),
651 (ins GR64:$src1, i64i8imm:$src2),
652 "sub{q}\t{$src2, $dst|$dst, $src2}",
653 [(set GR64:$dst, EFLAGS,
654 (X86sub_flag GR64:$src1, i64immSExt8:$src2))]>;
655 def SUB64ri32 : RIi32<0x81, MRM5r, (outs GR64:$dst),
656 (ins GR64:$src1, i64i32imm:$src2),
657 "sub{q}\t{$src2, $dst|$dst, $src2}",
658 [(set GR64:$dst, EFLAGS,
659 (X86sub_flag GR64:$src1, i64immSExt32:$src2))]>;
660 } // Constraints = "$src1 = $dst"
662 def SUB64i32 : RIi32<0x2D, RawFrm, (outs), (ins i64i32imm:$src),
663 "sub{q}\t{$src, %rax|%rax, $src}", []>;
665 // Memory-Register Subtraction
666 def SUB64mr : RI<0x29, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
667 "sub{q}\t{$src2, $dst|$dst, $src2}",
668 [(store (sub (load addr:$dst), GR64:$src2), addr:$dst),
671 // Memory-Integer Subtraction
672 def SUB64mi8 : RIi8<0x83, MRM5m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
673 "sub{q}\t{$src2, $dst|$dst, $src2}",
674 [(store (sub (load addr:$dst), i64immSExt8:$src2),
677 def SUB64mi32 : RIi32<0x81, MRM5m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
678 "sub{q}\t{$src2, $dst|$dst, $src2}",
679 [(store (sub (load addr:$dst), i64immSExt32:$src2),
683 let Uses = [EFLAGS] in {
684 let Constraints = "$src1 = $dst" in {
685 def SBB64rr : RI<0x19, MRMDestReg, (outs GR64:$dst),
686 (ins GR64:$src1, GR64:$src2),
687 "sbb{q}\t{$src2, $dst|$dst, $src2}",
688 [(set GR64:$dst, (sube GR64:$src1, GR64:$src2))]>;
690 let isCodeGenOnly = 1 in {
691 def SBB64rr_REV : RI<0x1B, MRMSrcReg, (outs GR64:$dst),
692 (ins GR64:$src1, GR64:$src2),
693 "sbb{q}\t{$src2, $dst|$dst, $src2}", []>;
696 def SBB64rm : RI<0x1B, MRMSrcMem, (outs GR64:$dst),
697 (ins GR64:$src1, i64mem:$src2),
698 "sbb{q}\t{$src2, $dst|$dst, $src2}",
699 [(set GR64:$dst, (sube GR64:$src1, (load addr:$src2)))]>;
701 def SBB64ri8 : RIi8<0x83, MRM3r, (outs GR64:$dst),
702 (ins GR64:$src1, i64i8imm:$src2),
703 "sbb{q}\t{$src2, $dst|$dst, $src2}",
704 [(set GR64:$dst, (sube GR64:$src1, i64immSExt8:$src2))]>;
705 def SBB64ri32 : RIi32<0x81, MRM3r, (outs GR64:$dst),
706 (ins GR64:$src1, i64i32imm:$src2),
707 "sbb{q}\t{$src2, $dst|$dst, $src2}",
708 [(set GR64:$dst, (sube GR64:$src1, i64immSExt32:$src2))]>;
709 } // Constraints = "$src1 = $dst"
711 def SBB64i32 : RIi32<0x1D, RawFrm, (outs), (ins i64i32imm:$src),
712 "sbb{q}\t{$src, %rax|%rax, $src}", []>;
714 def SBB64mr : RI<0x19, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
715 "sbb{q}\t{$src2, $dst|$dst, $src2}",
716 [(store (sube (load addr:$dst), GR64:$src2), addr:$dst)]>;
717 def SBB64mi8 : RIi8<0x83, MRM3m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
718 "sbb{q}\t{$src2, $dst|$dst, $src2}",
719 [(store (sube (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>;
720 def SBB64mi32 : RIi32<0x81, MRM3m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
721 "sbb{q}\t{$src2, $dst|$dst, $src2}",
722 [(store (sube (load addr:$dst), i64immSExt32:$src2), addr:$dst)]>;
726 // Unsigned multiplication
727 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], neverHasSideEffects = 1 in {
728 def MUL64r : RI<0xF7, MRM4r, (outs), (ins GR64:$src),
729 "mul{q}\t$src", []>; // RAX,RDX = RAX*GR64
731 def MUL64m : RI<0xF7, MRM4m, (outs), (ins i64mem:$src),
732 "mul{q}\t$src", []>; // RAX,RDX = RAX*[mem64]
734 // Signed multiplication
735 def IMUL64r : RI<0xF7, MRM5r, (outs), (ins GR64:$src),
736 "imul{q}\t$src", []>; // RAX,RDX = RAX*GR64
738 def IMUL64m : RI<0xF7, MRM5m, (outs), (ins i64mem:$src),
739 "imul{q}\t$src", []>; // RAX,RDX = RAX*[mem64]
742 let Defs = [EFLAGS] in {
743 let Constraints = "$src1 = $dst" in {
744 let isCommutable = 1 in
745 // Register-Register Signed Integer Multiplication
746 def IMUL64rr : RI<0xAF, MRMSrcReg, (outs GR64:$dst),
747 (ins GR64:$src1, GR64:$src2),
748 "imul{q}\t{$src2, $dst|$dst, $src2}",
749 [(set GR64:$dst, EFLAGS,
750 (X86smul_flag GR64:$src1, GR64:$src2))]>, TB;
752 // Register-Memory Signed Integer Multiplication
753 def IMUL64rm : RI<0xAF, MRMSrcMem, (outs GR64:$dst),
754 (ins GR64:$src1, i64mem:$src2),
755 "imul{q}\t{$src2, $dst|$dst, $src2}",
756 [(set GR64:$dst, EFLAGS,
757 (X86smul_flag GR64:$src1, (load addr:$src2)))]>, TB;
758 } // Constraints = "$src1 = $dst"
760 // Suprisingly enough, these are not two address instructions!
762 // Register-Integer Signed Integer Multiplication
763 def IMUL64rri8 : RIi8<0x6B, MRMSrcReg, // GR64 = GR64*I8
764 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
765 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
766 [(set GR64:$dst, EFLAGS,
767 (X86smul_flag GR64:$src1, i64immSExt8:$src2))]>;
768 def IMUL64rri32 : RIi32<0x69, MRMSrcReg, // GR64 = GR64*I32
769 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
770 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
771 [(set GR64:$dst, EFLAGS,
772 (X86smul_flag GR64:$src1, i64immSExt32:$src2))]>;
774 // Memory-Integer Signed Integer Multiplication
775 def IMUL64rmi8 : RIi8<0x6B, MRMSrcMem, // GR64 = [mem64]*I8
776 (outs GR64:$dst), (ins i64mem:$src1, i64i8imm: $src2),
777 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
778 [(set GR64:$dst, EFLAGS,
779 (X86smul_flag (load addr:$src1),
780 i64immSExt8:$src2))]>;
781 def IMUL64rmi32 : RIi32<0x69, MRMSrcMem, // GR64 = [mem64]*I32
782 (outs GR64:$dst), (ins i64mem:$src1, i64i32imm:$src2),
783 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
784 [(set GR64:$dst, EFLAGS,
785 (X86smul_flag (load addr:$src1),
786 i64immSExt32:$src2))]>;
789 // Unsigned division / remainder
790 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in {
791 // RDX:RAX/r64 = RAX,RDX
792 def DIV64r : RI<0xF7, MRM6r, (outs), (ins GR64:$src),
794 // Signed division / remainder
795 // RDX:RAX/r64 = RAX,RDX
796 def IDIV64r: RI<0xF7, MRM7r, (outs), (ins GR64:$src),
797 "idiv{q}\t$src", []>;
799 // RDX:RAX/[mem64] = RAX,RDX
800 def DIV64m : RI<0xF7, MRM6m, (outs), (ins i64mem:$src),
802 // RDX:RAX/[mem64] = RAX,RDX
803 def IDIV64m: RI<0xF7, MRM7m, (outs), (ins i64mem:$src),
804 "idiv{q}\t$src", []>;
808 // Unary instructions
809 let Defs = [EFLAGS], CodeSize = 2 in {
810 let Constraints = "$src = $dst" in
811 def NEG64r : RI<0xF7, MRM3r, (outs GR64:$dst), (ins GR64:$src), "neg{q}\t$dst",
812 [(set GR64:$dst, (ineg GR64:$src)),
814 def NEG64m : RI<0xF7, MRM3m, (outs), (ins i64mem:$dst), "neg{q}\t$dst",
815 [(store (ineg (loadi64 addr:$dst)), addr:$dst),
818 let Constraints = "$src = $dst", isConvertibleToThreeAddress = 1 in
819 def INC64r : RI<0xFF, MRM0r, (outs GR64:$dst), (ins GR64:$src), "inc{q}\t$dst",
820 [(set GR64:$dst, EFLAGS, (X86inc_flag GR64:$src))]>;
821 def INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst), "inc{q}\t$dst",
822 [(store (add (loadi64 addr:$dst), 1), addr:$dst),
825 let Constraints = "$src = $dst", isConvertibleToThreeAddress = 1 in
826 def DEC64r : RI<0xFF, MRM1r, (outs GR64:$dst), (ins GR64:$src), "dec{q}\t$dst",
827 [(set GR64:$dst, EFLAGS, (X86dec_flag GR64:$src))]>;
828 def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst",
829 [(store (add (loadi64 addr:$dst), -1), addr:$dst),
832 // In 64-bit mode, single byte INC and DEC cannot be encoded.
833 let Constraints = "$src = $dst", isConvertibleToThreeAddress = 1 in {
834 // Can transform into LEA.
835 def INC64_16r : I<0xFF, MRM0r, (outs GR16:$dst), (ins GR16:$src),
837 [(set GR16:$dst, EFLAGS, (X86inc_flag GR16:$src))]>,
838 OpSize, Requires<[In64BitMode]>;
839 def INC64_32r : I<0xFF, MRM0r, (outs GR32:$dst), (ins GR32:$src),
841 [(set GR32:$dst, EFLAGS, (X86inc_flag GR32:$src))]>,
842 Requires<[In64BitMode]>;
843 def DEC64_16r : I<0xFF, MRM1r, (outs GR16:$dst), (ins GR16:$src),
845 [(set GR16:$dst, EFLAGS, (X86dec_flag GR16:$src))]>,
846 OpSize, Requires<[In64BitMode]>;
847 def DEC64_32r : I<0xFF, MRM1r, (outs GR32:$dst), (ins GR32:$src),
849 [(set GR32:$dst, EFLAGS, (X86dec_flag GR32:$src))]>,
850 Requires<[In64BitMode]>;
851 } // Constraints = "$src = $dst", isConvertibleToThreeAddress
853 // These are duplicates of their 32-bit counterparts. Only needed so X86 knows
854 // how to unfold them.
855 def INC64_16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
856 [(store (add (loadi16 addr:$dst), 1), addr:$dst),
858 OpSize, Requires<[In64BitMode]>;
859 def INC64_32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
860 [(store (add (loadi32 addr:$dst), 1), addr:$dst),
862 Requires<[In64BitMode]>;
863 def DEC64_16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
864 [(store (add (loadi16 addr:$dst), -1), addr:$dst),
866 OpSize, Requires<[In64BitMode]>;
867 def DEC64_32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
868 [(store (add (loadi32 addr:$dst), -1), addr:$dst),
870 Requires<[In64BitMode]>;
871 } // Defs = [EFLAGS], CodeSize
874 let Defs = [EFLAGS] in {
875 // Shift instructions
876 let Constraints = "$src1 = $dst" in {
878 def SHL64rCL : RI<0xD3, MRM4r, (outs GR64:$dst), (ins GR64:$src1),
879 "shl{q}\t{%cl, $dst|$dst, %CL}",
880 [(set GR64:$dst, (shl GR64:$src1, CL))]>;
881 let isConvertibleToThreeAddress = 1 in // Can transform into LEA.
882 def SHL64ri : RIi8<0xC1, MRM4r, (outs GR64:$dst),
883 (ins GR64:$src1, i8imm:$src2),
884 "shl{q}\t{$src2, $dst|$dst, $src2}",
885 [(set GR64:$dst, (shl GR64:$src1, (i8 imm:$src2)))]>;
886 // NOTE: We don't include patterns for shifts of a register by one, because
887 // 'add reg,reg' is cheaper.
888 def SHL64r1 : RI<0xD1, MRM4r, (outs GR64:$dst), (ins GR64:$src1),
890 } // Constraints = "$src1 = $dst"
893 def SHL64mCL : RI<0xD3, MRM4m, (outs), (ins i64mem:$dst),
894 "shl{q}\t{%cl, $dst|$dst, %CL}",
895 [(store (shl (loadi64 addr:$dst), CL), addr:$dst)]>;
896 def SHL64mi : RIi8<0xC1, MRM4m, (outs), (ins i64mem:$dst, i8imm:$src),
897 "shl{q}\t{$src, $dst|$dst, $src}",
898 [(store (shl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
899 def SHL64m1 : RI<0xD1, MRM4m, (outs), (ins i64mem:$dst),
901 [(store (shl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
903 let Constraints = "$src1 = $dst" in {
905 def SHR64rCL : RI<0xD3, MRM5r, (outs GR64:$dst), (ins GR64:$src1),
906 "shr{q}\t{%cl, $dst|$dst, %CL}",
907 [(set GR64:$dst, (srl GR64:$src1, CL))]>;
908 def SHR64ri : RIi8<0xC1, MRM5r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
909 "shr{q}\t{$src2, $dst|$dst, $src2}",
910 [(set GR64:$dst, (srl GR64:$src1, (i8 imm:$src2)))]>;
911 def SHR64r1 : RI<0xD1, MRM5r, (outs GR64:$dst), (ins GR64:$src1),
913 [(set GR64:$dst, (srl GR64:$src1, (i8 1)))]>;
914 } // Constraints = "$src1 = $dst"
917 def SHR64mCL : RI<0xD3, MRM5m, (outs), (ins i64mem:$dst),
918 "shr{q}\t{%cl, $dst|$dst, %CL}",
919 [(store (srl (loadi64 addr:$dst), CL), addr:$dst)]>;
920 def SHR64mi : RIi8<0xC1, MRM5m, (outs), (ins i64mem:$dst, i8imm:$src),
921 "shr{q}\t{$src, $dst|$dst, $src}",
922 [(store (srl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
923 def SHR64m1 : RI<0xD1, MRM5m, (outs), (ins i64mem:$dst),
925 [(store (srl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
927 let Constraints = "$src1 = $dst" in {
929 def SAR64rCL : RI<0xD3, MRM7r, (outs GR64:$dst), (ins GR64:$src1),
930 "sar{q}\t{%cl, $dst|$dst, %CL}",
931 [(set GR64:$dst, (sra GR64:$src1, CL))]>;
932 def SAR64ri : RIi8<0xC1, MRM7r, (outs GR64:$dst),
933 (ins GR64:$src1, i8imm:$src2),
934 "sar{q}\t{$src2, $dst|$dst, $src2}",
935 [(set GR64:$dst, (sra GR64:$src1, (i8 imm:$src2)))]>;
936 def SAR64r1 : RI<0xD1, MRM7r, (outs GR64:$dst), (ins GR64:$src1),
938 [(set GR64:$dst, (sra GR64:$src1, (i8 1)))]>;
939 } // Constraints = "$src = $dst"
942 def SAR64mCL : RI<0xD3, MRM7m, (outs), (ins i64mem:$dst),
943 "sar{q}\t{%cl, $dst|$dst, %CL}",
944 [(store (sra (loadi64 addr:$dst), CL), addr:$dst)]>;
945 def SAR64mi : RIi8<0xC1, MRM7m, (outs), (ins i64mem:$dst, i8imm:$src),
946 "sar{q}\t{$src, $dst|$dst, $src}",
947 [(store (sra (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
948 def SAR64m1 : RI<0xD1, MRM7m, (outs), (ins i64mem:$dst),
950 [(store (sra (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
952 // Rotate instructions
954 let Constraints = "$src = $dst" in {
955 def RCL64r1 : RI<0xD1, MRM2r, (outs GR64:$dst), (ins GR64:$src),
956 "rcl{q}\t{1, $dst|$dst, 1}", []>;
957 def RCL64ri : RIi8<0xC1, MRM2r, (outs GR64:$dst), (ins GR64:$src, i8imm:$cnt),
958 "rcl{q}\t{$cnt, $dst|$dst, $cnt}", []>;
960 def RCR64r1 : RI<0xD1, MRM3r, (outs GR64:$dst), (ins GR64:$src),
961 "rcr{q}\t{1, $dst|$dst, 1}", []>;
962 def RCR64ri : RIi8<0xC1, MRM3r, (outs GR64:$dst), (ins GR64:$src, i8imm:$cnt),
963 "rcr{q}\t{$cnt, $dst|$dst, $cnt}", []>;
966 def RCL64rCL : RI<0xD3, MRM2r, (outs GR64:$dst), (ins GR64:$src),
967 "rcl{q}\t{%cl, $dst|$dst, CL}", []>;
968 def RCR64rCL : RI<0xD3, MRM3r, (outs GR64:$dst), (ins GR64:$src),
969 "rcr{q}\t{%cl, $dst|$dst, CL}", []>;
971 } // Constraints = "$src = $dst"
973 def RCL64m1 : RI<0xD1, MRM2m, (outs), (ins i64mem:$dst),
974 "rcl{q}\t{1, $dst|$dst, 1}", []>;
975 def RCL64mi : RIi8<0xC1, MRM2m, (outs), (ins i64mem:$dst, i8imm:$cnt),
976 "rcl{q}\t{$cnt, $dst|$dst, $cnt}", []>;
977 def RCR64m1 : RI<0xD1, MRM3m, (outs), (ins i64mem:$dst),
978 "rcr{q}\t{1, $dst|$dst, 1}", []>;
979 def RCR64mi : RIi8<0xC1, MRM3m, (outs), (ins i64mem:$dst, i8imm:$cnt),
980 "rcr{q}\t{$cnt, $dst|$dst, $cnt}", []>;
983 def RCL64mCL : RI<0xD3, MRM2m, (outs), (ins i64mem:$dst),
984 "rcl{q}\t{%cl, $dst|$dst, CL}", []>;
985 def RCR64mCL : RI<0xD3, MRM3m, (outs), (ins i64mem:$dst),
986 "rcr{q}\t{%cl, $dst|$dst, CL}", []>;
989 let Constraints = "$src1 = $dst" in {
991 def ROL64rCL : RI<0xD3, MRM0r, (outs GR64:$dst), (ins GR64:$src1),
992 "rol{q}\t{%cl, $dst|$dst, %CL}",
993 [(set GR64:$dst, (rotl GR64:$src1, CL))]>;
994 def ROL64ri : RIi8<0xC1, MRM0r, (outs GR64:$dst),
995 (ins GR64:$src1, i8imm:$src2),
996 "rol{q}\t{$src2, $dst|$dst, $src2}",
997 [(set GR64:$dst, (rotl GR64:$src1, (i8 imm:$src2)))]>;
998 def ROL64r1 : RI<0xD1, MRM0r, (outs GR64:$dst), (ins GR64:$src1),
1000 [(set GR64:$dst, (rotl GR64:$src1, (i8 1)))]>;
1001 } // Constraints = "$src1 = $dst"
1004 def ROL64mCL : RI<0xD3, MRM0m, (outs), (ins i64mem:$dst),
1005 "rol{q}\t{%cl, $dst|$dst, %CL}",
1006 [(store (rotl (loadi64 addr:$dst), CL), addr:$dst)]>;
1007 def ROL64mi : RIi8<0xC1, MRM0m, (outs), (ins i64mem:$dst, i8imm:$src),
1008 "rol{q}\t{$src, $dst|$dst, $src}",
1009 [(store (rotl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1010 def ROL64m1 : RI<0xD1, MRM0m, (outs), (ins i64mem:$dst),
1012 [(store (rotl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
1014 let Constraints = "$src1 = $dst" in {
1016 def ROR64rCL : RI<0xD3, MRM1r, (outs GR64:$dst), (ins GR64:$src1),
1017 "ror{q}\t{%cl, $dst|$dst, %CL}",
1018 [(set GR64:$dst, (rotr GR64:$src1, CL))]>;
1019 def ROR64ri : RIi8<0xC1, MRM1r, (outs GR64:$dst),
1020 (ins GR64:$src1, i8imm:$src2),
1021 "ror{q}\t{$src2, $dst|$dst, $src2}",
1022 [(set GR64:$dst, (rotr GR64:$src1, (i8 imm:$src2)))]>;
1023 def ROR64r1 : RI<0xD1, MRM1r, (outs GR64:$dst), (ins GR64:$src1),
1025 [(set GR64:$dst, (rotr GR64:$src1, (i8 1)))]>;
1026 } // Constraints = "$src1 = $dst"
1029 def ROR64mCL : RI<0xD3, MRM1m, (outs), (ins i64mem:$dst),
1030 "ror{q}\t{%cl, $dst|$dst, %CL}",
1031 [(store (rotr (loadi64 addr:$dst), CL), addr:$dst)]>;
1032 def ROR64mi : RIi8<0xC1, MRM1m, (outs), (ins i64mem:$dst, i8imm:$src),
1033 "ror{q}\t{$src, $dst|$dst, $src}",
1034 [(store (rotr (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1035 def ROR64m1 : RI<0xD1, MRM1m, (outs), (ins i64mem:$dst),
1037 [(store (rotr (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
1039 // Double shift instructions (generalizations of rotate)
1040 let Constraints = "$src1 = $dst" in {
1041 let Uses = [CL] in {
1042 def SHLD64rrCL : RI<0xA5, MRMDestReg, (outs GR64:$dst),
1043 (ins GR64:$src1, GR64:$src2),
1044 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1045 [(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2, CL))]>,
1047 def SHRD64rrCL : RI<0xAD, MRMDestReg, (outs GR64:$dst),
1048 (ins GR64:$src1, GR64:$src2),
1049 "shrd{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1050 [(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2, CL))]>,
1054 let isCommutable = 1 in { // FIXME: Update X86InstrInfo::commuteInstruction
1055 def SHLD64rri8 : RIi8<0xA4, MRMDestReg,
1057 (ins GR64:$src1, GR64:$src2, i8imm:$src3),
1058 "shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1059 [(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2,
1062 def SHRD64rri8 : RIi8<0xAC, MRMDestReg,
1064 (ins GR64:$src1, GR64:$src2, i8imm:$src3),
1065 "shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1066 [(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2,
1070 } // Constraints = "$src1 = $dst"
1072 let Uses = [CL] in {
1073 def SHLD64mrCL : RI<0xA5, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
1074 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1075 [(store (X86shld (loadi64 addr:$dst), GR64:$src2, CL),
1077 def SHRD64mrCL : RI<0xAD, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
1078 "shrd{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1079 [(store (X86shrd (loadi64 addr:$dst), GR64:$src2, CL),
1082 def SHLD64mri8 : RIi8<0xA4, MRMDestMem,
1083 (outs), (ins i64mem:$dst, GR64:$src2, i8imm:$src3),
1084 "shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1085 [(store (X86shld (loadi64 addr:$dst), GR64:$src2,
1086 (i8 imm:$src3)), addr:$dst)]>,
1088 def SHRD64mri8 : RIi8<0xAC, MRMDestMem,
1089 (outs), (ins i64mem:$dst, GR64:$src2, i8imm:$src3),
1090 "shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1091 [(store (X86shrd (loadi64 addr:$dst), GR64:$src2,
1092 (i8 imm:$src3)), addr:$dst)]>,
1094 } // Defs = [EFLAGS]
1096 //===----------------------------------------------------------------------===//
1097 // Logical Instructions...
1100 let Constraints = "$src = $dst" , AddedComplexity = 15 in
1101 def NOT64r : RI<0xF7, MRM2r, (outs GR64:$dst), (ins GR64:$src), "not{q}\t$dst",
1102 [(set GR64:$dst, (not GR64:$src))]>;
1103 def NOT64m : RI<0xF7, MRM2m, (outs), (ins i64mem:$dst), "not{q}\t$dst",
1104 [(store (not (loadi64 addr:$dst)), addr:$dst)]>;
1106 let Defs = [EFLAGS] in {
1107 def AND64i32 : RIi32<0x25, RawFrm, (outs), (ins i64i32imm:$src),
1108 "and{q}\t{$src, %rax|%rax, $src}", []>;
1110 let Constraints = "$src1 = $dst" in {
1111 let isCommutable = 1 in
1112 def AND64rr : RI<0x21, MRMDestReg,
1113 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1114 "and{q}\t{$src2, $dst|$dst, $src2}",
1115 [(set GR64:$dst, EFLAGS,
1116 (X86and_flag GR64:$src1, GR64:$src2))]>;
1117 let isCodeGenOnly = 1 in {
1118 def AND64rr_REV : RI<0x23, MRMSrcReg, (outs GR64:$dst),
1119 (ins GR64:$src1, GR64:$src2),
1120 "and{q}\t{$src2, $dst|$dst, $src2}", []>;
1122 def AND64rm : RI<0x23, MRMSrcMem,
1123 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1124 "and{q}\t{$src2, $dst|$dst, $src2}",
1125 [(set GR64:$dst, EFLAGS,
1126 (X86and_flag GR64:$src1, (load addr:$src2)))]>;
1127 def AND64ri8 : RIi8<0x83, MRM4r,
1128 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
1129 "and{q}\t{$src2, $dst|$dst, $src2}",
1130 [(set GR64:$dst, EFLAGS,
1131 (X86and_flag GR64:$src1, i64immSExt8:$src2))]>;
1132 def AND64ri32 : RIi32<0x81, MRM4r,
1133 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
1134 "and{q}\t{$src2, $dst|$dst, $src2}",
1135 [(set GR64:$dst, EFLAGS,
1136 (X86and_flag GR64:$src1, i64immSExt32:$src2))]>;
1137 } // Constraints = "$src1 = $dst"
1139 def AND64mr : RI<0x21, MRMDestMem,
1140 (outs), (ins i64mem:$dst, GR64:$src),
1141 "and{q}\t{$src, $dst|$dst, $src}",
1142 [(store (and (load addr:$dst), GR64:$src), addr:$dst),
1143 (implicit EFLAGS)]>;
1144 def AND64mi8 : RIi8<0x83, MRM4m,
1145 (outs), (ins i64mem:$dst, i64i8imm :$src),
1146 "and{q}\t{$src, $dst|$dst, $src}",
1147 [(store (and (load addr:$dst), i64immSExt8:$src), addr:$dst),
1148 (implicit EFLAGS)]>;
1149 def AND64mi32 : RIi32<0x81, MRM4m,
1150 (outs), (ins i64mem:$dst, i64i32imm:$src),
1151 "and{q}\t{$src, $dst|$dst, $src}",
1152 [(store (and (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst),
1153 (implicit EFLAGS)]>;
1155 let Constraints = "$src1 = $dst" in {
1156 let isCommutable = 1 in
1157 def OR64rr : RI<0x09, MRMDestReg, (outs GR64:$dst),
1158 (ins GR64:$src1, GR64:$src2),
1159 "or{q}\t{$src2, $dst|$dst, $src2}",
1160 [(set GR64:$dst, EFLAGS,
1161 (X86or_flag GR64:$src1, GR64:$src2))]>;
1162 let isCodeGenOnly = 1 in {
1163 def OR64rr_REV : RI<0x0B, MRMSrcReg, (outs GR64:$dst),
1164 (ins GR64:$src1, GR64:$src2),
1165 "or{q}\t{$src2, $dst|$dst, $src2}", []>;
1167 def OR64rm : RI<0x0B, MRMSrcMem , (outs GR64:$dst),
1168 (ins GR64:$src1, i64mem:$src2),
1169 "or{q}\t{$src2, $dst|$dst, $src2}",
1170 [(set GR64:$dst, EFLAGS,
1171 (X86or_flag GR64:$src1, (load addr:$src2)))]>;
1172 def OR64ri8 : RIi8<0x83, MRM1r, (outs GR64:$dst),
1173 (ins GR64:$src1, i64i8imm:$src2),
1174 "or{q}\t{$src2, $dst|$dst, $src2}",
1175 [(set GR64:$dst, EFLAGS,
1176 (X86or_flag GR64:$src1, i64immSExt8:$src2))]>;
1177 def OR64ri32 : RIi32<0x81, MRM1r, (outs GR64:$dst),
1178 (ins GR64:$src1, i64i32imm:$src2),
1179 "or{q}\t{$src2, $dst|$dst, $src2}",
1180 [(set GR64:$dst, EFLAGS,
1181 (X86or_flag GR64:$src1, i64immSExt32:$src2))]>;
1182 } // Constraints = "$src1 = $dst"
1184 def OR64mr : RI<0x09, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1185 "or{q}\t{$src, $dst|$dst, $src}",
1186 [(store (or (load addr:$dst), GR64:$src), addr:$dst),
1187 (implicit EFLAGS)]>;
1188 def OR64mi8 : RIi8<0x83, MRM1m, (outs), (ins i64mem:$dst, i64i8imm:$src),
1189 "or{q}\t{$src, $dst|$dst, $src}",
1190 [(store (or (load addr:$dst), i64immSExt8:$src), addr:$dst),
1191 (implicit EFLAGS)]>;
1192 def OR64mi32 : RIi32<0x81, MRM1m, (outs), (ins i64mem:$dst, i64i32imm:$src),
1193 "or{q}\t{$src, $dst|$dst, $src}",
1194 [(store (or (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst),
1195 (implicit EFLAGS)]>;
1197 def OR64i32 : RIi32<0x0D, RawFrm, (outs), (ins i64i32imm:$src),
1198 "or{q}\t{$src, %rax|%rax, $src}", []>;
1200 let Constraints = "$src1 = $dst" in {
1201 let isCommutable = 1 in
1202 def XOR64rr : RI<0x31, MRMDestReg, (outs GR64:$dst),
1203 (ins GR64:$src1, GR64:$src2),
1204 "xor{q}\t{$src2, $dst|$dst, $src2}",
1205 [(set GR64:$dst, EFLAGS,
1206 (X86xor_flag GR64:$src1, GR64:$src2))]>;
1207 let isCodeGenOnly = 1 in {
1208 def XOR64rr_REV : RI<0x33, MRMSrcReg, (outs GR64:$dst),
1209 (ins GR64:$src1, GR64:$src2),
1210 "xor{q}\t{$src2, $dst|$dst, $src2}", []>;
1212 def XOR64rm : RI<0x33, MRMSrcMem, (outs GR64:$dst),
1213 (ins GR64:$src1, i64mem:$src2),
1214 "xor{q}\t{$src2, $dst|$dst, $src2}",
1215 [(set GR64:$dst, EFLAGS,
1216 (X86xor_flag GR64:$src1, (load addr:$src2)))]>;
1217 def XOR64ri8 : RIi8<0x83, MRM6r, (outs GR64:$dst),
1218 (ins GR64:$src1, i64i8imm:$src2),
1219 "xor{q}\t{$src2, $dst|$dst, $src2}",
1220 [(set GR64:$dst, EFLAGS,
1221 (X86xor_flag GR64:$src1, i64immSExt8:$src2))]>;
1222 def XOR64ri32 : RIi32<0x81, MRM6r,
1223 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
1224 "xor{q}\t{$src2, $dst|$dst, $src2}",
1225 [(set GR64:$dst, EFLAGS,
1226 (X86xor_flag GR64:$src1, i64immSExt32:$src2))]>;
1227 } // Constraints = "$src1 = $dst"
1229 def XOR64mr : RI<0x31, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1230 "xor{q}\t{$src, $dst|$dst, $src}",
1231 [(store (xor (load addr:$dst), GR64:$src), addr:$dst),
1232 (implicit EFLAGS)]>;
1233 def XOR64mi8 : RIi8<0x83, MRM6m, (outs), (ins i64mem:$dst, i64i8imm :$src),
1234 "xor{q}\t{$src, $dst|$dst, $src}",
1235 [(store (xor (load addr:$dst), i64immSExt8:$src), addr:$dst),
1236 (implicit EFLAGS)]>;
1237 def XOR64mi32 : RIi32<0x81, MRM6m, (outs), (ins i64mem:$dst, i64i32imm:$src),
1238 "xor{q}\t{$src, $dst|$dst, $src}",
1239 [(store (xor (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst),
1240 (implicit EFLAGS)]>;
1242 def XOR64i32 : RIi32<0x35, RawFrm, (outs), (ins i64i32imm:$src),
1243 "xor{q}\t{$src, %rax|%rax, $src}", []>;
1245 } // Defs = [EFLAGS]
1247 //===----------------------------------------------------------------------===//
1248 // Comparison Instructions...
1251 // Integer comparison
1252 let Defs = [EFLAGS] in {
1253 def TEST64i32 : RIi32<0xa9, RawFrm, (outs), (ins i64i32imm:$src),
1254 "test{q}\t{$src, %rax|%rax, $src}", []>;
1255 let isCommutable = 1 in
1256 def TEST64rr : RI<0x85, MRMSrcReg, (outs), (ins GR64:$src1, GR64:$src2),
1257 "test{q}\t{$src2, $src1|$src1, $src2}",
1258 [(set EFLAGS, (X86cmp (and GR64:$src1, GR64:$src2), 0))]>;
1259 def TEST64rm : RI<0x85, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2),
1260 "test{q}\t{$src2, $src1|$src1, $src2}",
1261 [(set EFLAGS, (X86cmp (and GR64:$src1, (loadi64 addr:$src2)),
1263 def TEST64ri32 : RIi32<0xF7, MRM0r, (outs),
1264 (ins GR64:$src1, i64i32imm:$src2),
1265 "test{q}\t{$src2, $src1|$src1, $src2}",
1266 [(set EFLAGS, (X86cmp (and GR64:$src1, i64immSExt32:$src2),
1268 def TEST64mi32 : RIi32<0xF7, MRM0m, (outs),
1269 (ins i64mem:$src1, i64i32imm:$src2),
1270 "test{q}\t{$src2, $src1|$src1, $src2}",
1271 [(set EFLAGS, (X86cmp (and (loadi64 addr:$src1),
1272 i64immSExt32:$src2), 0))]>;
1275 def CMP64i32 : RIi32<0x3D, RawFrm, (outs), (ins i64i32imm:$src),
1276 "cmp{q}\t{$src, %rax|%rax, $src}", []>;
1277 def CMP64rr : RI<0x39, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1278 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1279 [(set EFLAGS, (X86cmp GR64:$src1, GR64:$src2))]>;
1281 // These are alternate spellings for use by the disassembler, we mark them as
1282 // code gen only to ensure they aren't matched by the assembler.
1283 let isCodeGenOnly = 1 in {
1284 def CMP64mrmrr : RI<0x3B, MRMSrcReg, (outs), (ins GR64:$src1, GR64:$src2),
1285 "cmp{q}\t{$src2, $src1|$src1, $src2}", []>;
1288 def CMP64mr : RI<0x39, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1289 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1290 [(set EFLAGS, (X86cmp (loadi64 addr:$src1), GR64:$src2))]>;
1291 def CMP64rm : RI<0x3B, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2),
1292 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1293 [(set EFLAGS, (X86cmp GR64:$src1, (loadi64 addr:$src2)))]>;
1294 def CMP64ri8 : RIi8<0x83, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1295 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1296 [(set EFLAGS, (X86cmp GR64:$src1, i64immSExt8:$src2))]>;
1297 def CMP64ri32 : RIi32<0x81, MRM7r, (outs), (ins GR64:$src1, i64i32imm:$src2),
1298 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1299 [(set EFLAGS, (X86cmp GR64:$src1, i64immSExt32:$src2))]>;
1300 def CMP64mi8 : RIi8<0x83, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1301 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1302 [(set EFLAGS, (X86cmp (loadi64 addr:$src1),
1303 i64immSExt8:$src2))]>;
1304 def CMP64mi32 : RIi32<0x81, MRM7m, (outs),
1305 (ins i64mem:$src1, i64i32imm:$src2),
1306 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1307 [(set EFLAGS, (X86cmp (loadi64 addr:$src1),
1308 i64immSExt32:$src2))]>;
1309 } // Defs = [EFLAGS]
1312 // TODO: BTC, BTR, and BTS
1313 let Defs = [EFLAGS] in {
1314 def BT64rr : RI<0xA3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1315 "bt{q}\t{$src2, $src1|$src1, $src2}",
1316 [(set EFLAGS, (X86bt GR64:$src1, GR64:$src2))]>, TB;
1318 // Unlike with the register+register form, the memory+register form of the
1319 // bt instruction does not ignore the high bits of the index. From ISel's
1320 // perspective, this is pretty bizarre. Disable these instructions for now.
1321 def BT64mr : RI<0xA3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1322 "bt{q}\t{$src2, $src1|$src1, $src2}",
1323 // [(X86bt (loadi64 addr:$src1), GR64:$src2),
1324 // (implicit EFLAGS)]
1328 def BT64ri8 : RIi8<0xBA, MRM4r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1329 "bt{q}\t{$src2, $src1|$src1, $src2}",
1330 [(set EFLAGS, (X86bt GR64:$src1, i64immSExt8:$src2))]>, TB;
1331 // Note that these instructions don't need FastBTMem because that
1332 // only applies when the other operand is in a register. When it's
1333 // an immediate, bt is still fast.
1334 def BT64mi8 : RIi8<0xBA, MRM4m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1335 "bt{q}\t{$src2, $src1|$src1, $src2}",
1336 [(set EFLAGS, (X86bt (loadi64 addr:$src1),
1337 i64immSExt8:$src2))]>, TB;
1339 def BTC64rr : RI<0xBB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1340 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1341 def BTC64mr : RI<0xBB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1342 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1343 def BTC64ri8 : RIi8<0xBA, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1344 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1345 def BTC64mi8 : RIi8<0xBA, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1346 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1348 def BTR64rr : RI<0xB3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1349 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1350 def BTR64mr : RI<0xB3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1351 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1352 def BTR64ri8 : RIi8<0xBA, MRM6r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1353 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1354 def BTR64mi8 : RIi8<0xBA, MRM6m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1355 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1357 def BTS64rr : RI<0xAB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1358 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1359 def BTS64mr : RI<0xAB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1360 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1361 def BTS64ri8 : RIi8<0xBA, MRM5r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1362 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1363 def BTS64mi8 : RIi8<0xBA, MRM5m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1364 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1365 } // Defs = [EFLAGS]
1367 // Conditional moves
1368 let Uses = [EFLAGS], Constraints = "$src1 = $dst" in {
1369 let isCommutable = 1 in {
1370 def CMOVB64rr : RI<0x42, MRMSrcReg, // if <u, GR64 = GR64
1371 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1372 "cmovb{q}\t{$src2, $dst|$dst, $src2}",
1373 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1374 X86_COND_B, EFLAGS))]>, TB;
1375 def CMOVAE64rr: RI<0x43, MRMSrcReg, // if >=u, GR64 = GR64
1376 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1377 "cmovae{q}\t{$src2, $dst|$dst, $src2}",
1378 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1379 X86_COND_AE, EFLAGS))]>, TB;
1380 def CMOVE64rr : RI<0x44, MRMSrcReg, // if ==, GR64 = GR64
1381 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1382 "cmove{q}\t{$src2, $dst|$dst, $src2}",
1383 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1384 X86_COND_E, EFLAGS))]>, TB;
1385 def CMOVNE64rr: RI<0x45, MRMSrcReg, // if !=, GR64 = GR64
1386 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1387 "cmovne{q}\t{$src2, $dst|$dst, $src2}",
1388 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1389 X86_COND_NE, EFLAGS))]>, TB;
1390 def CMOVBE64rr: RI<0x46, MRMSrcReg, // if <=u, GR64 = GR64
1391 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1392 "cmovbe{q}\t{$src2, $dst|$dst, $src2}",
1393 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1394 X86_COND_BE, EFLAGS))]>, TB;
1395 def CMOVA64rr : RI<0x47, MRMSrcReg, // if >u, GR64 = GR64
1396 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1397 "cmova{q}\t{$src2, $dst|$dst, $src2}",
1398 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1399 X86_COND_A, EFLAGS))]>, TB;
1400 def CMOVL64rr : RI<0x4C, MRMSrcReg, // if <s, GR64 = GR64
1401 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1402 "cmovl{q}\t{$src2, $dst|$dst, $src2}",
1403 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1404 X86_COND_L, EFLAGS))]>, TB;
1405 def CMOVGE64rr: RI<0x4D, MRMSrcReg, // if >=s, GR64 = GR64
1406 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1407 "cmovge{q}\t{$src2, $dst|$dst, $src2}",
1408 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1409 X86_COND_GE, EFLAGS))]>, TB;
1410 def CMOVLE64rr: RI<0x4E, MRMSrcReg, // if <=s, GR64 = GR64
1411 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1412 "cmovle{q}\t{$src2, $dst|$dst, $src2}",
1413 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1414 X86_COND_LE, EFLAGS))]>, TB;
1415 def CMOVG64rr : RI<0x4F, MRMSrcReg, // if >s, GR64 = GR64
1416 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1417 "cmovg{q}\t{$src2, $dst|$dst, $src2}",
1418 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1419 X86_COND_G, EFLAGS))]>, TB;
1420 def CMOVS64rr : RI<0x48, MRMSrcReg, // if signed, GR64 = GR64
1421 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1422 "cmovs{q}\t{$src2, $dst|$dst, $src2}",
1423 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1424 X86_COND_S, EFLAGS))]>, TB;
1425 def CMOVNS64rr: RI<0x49, MRMSrcReg, // if !signed, GR64 = GR64
1426 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1427 "cmovns{q}\t{$src2, $dst|$dst, $src2}",
1428 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1429 X86_COND_NS, EFLAGS))]>, TB;
1430 def CMOVP64rr : RI<0x4A, MRMSrcReg, // if parity, GR64 = GR64
1431 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1432 "cmovp{q}\t{$src2, $dst|$dst, $src2}",
1433 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1434 X86_COND_P, EFLAGS))]>, TB;
1435 def CMOVNP64rr : RI<0x4B, MRMSrcReg, // if !parity, GR64 = GR64
1436 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1437 "cmovnp{q}\t{$src2, $dst|$dst, $src2}",
1438 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1439 X86_COND_NP, EFLAGS))]>, TB;
1440 def CMOVO64rr : RI<0x40, MRMSrcReg, // if overflow, GR64 = GR64
1441 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1442 "cmovo{q}\t{$src2, $dst|$dst, $src2}",
1443 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1444 X86_COND_O, EFLAGS))]>, TB;
1445 def CMOVNO64rr : RI<0x41, MRMSrcReg, // if !overflow, GR64 = GR64
1446 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1447 "cmovno{q}\t{$src2, $dst|$dst, $src2}",
1448 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1449 X86_COND_NO, EFLAGS))]>, TB;
1450 } // isCommutable = 1
1452 def CMOVB64rm : RI<0x42, MRMSrcMem, // if <u, GR64 = [mem64]
1453 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1454 "cmovb{q}\t{$src2, $dst|$dst, $src2}",
1455 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1456 X86_COND_B, EFLAGS))]>, TB;
1457 def CMOVAE64rm: RI<0x43, MRMSrcMem, // if >=u, GR64 = [mem64]
1458 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1459 "cmovae{q}\t{$src2, $dst|$dst, $src2}",
1460 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1461 X86_COND_AE, EFLAGS))]>, TB;
1462 def CMOVE64rm : RI<0x44, MRMSrcMem, // if ==, GR64 = [mem64]
1463 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1464 "cmove{q}\t{$src2, $dst|$dst, $src2}",
1465 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1466 X86_COND_E, EFLAGS))]>, TB;
1467 def CMOVNE64rm: RI<0x45, MRMSrcMem, // if !=, GR64 = [mem64]
1468 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1469 "cmovne{q}\t{$src2, $dst|$dst, $src2}",
1470 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1471 X86_COND_NE, EFLAGS))]>, TB;
1472 def CMOVBE64rm: RI<0x46, MRMSrcMem, // if <=u, GR64 = [mem64]
1473 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1474 "cmovbe{q}\t{$src2, $dst|$dst, $src2}",
1475 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1476 X86_COND_BE, EFLAGS))]>, TB;
1477 def CMOVA64rm : RI<0x47, MRMSrcMem, // if >u, GR64 = [mem64]
1478 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1479 "cmova{q}\t{$src2, $dst|$dst, $src2}",
1480 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1481 X86_COND_A, EFLAGS))]>, TB;
1482 def CMOVL64rm : RI<0x4C, MRMSrcMem, // if <s, GR64 = [mem64]
1483 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1484 "cmovl{q}\t{$src2, $dst|$dst, $src2}",
1485 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1486 X86_COND_L, EFLAGS))]>, TB;
1487 def CMOVGE64rm: RI<0x4D, MRMSrcMem, // if >=s, GR64 = [mem64]
1488 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1489 "cmovge{q}\t{$src2, $dst|$dst, $src2}",
1490 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1491 X86_COND_GE, EFLAGS))]>, TB;
1492 def CMOVLE64rm: RI<0x4E, MRMSrcMem, // if <=s, GR64 = [mem64]
1493 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1494 "cmovle{q}\t{$src2, $dst|$dst, $src2}",
1495 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1496 X86_COND_LE, EFLAGS))]>, TB;
1497 def CMOVG64rm : RI<0x4F, MRMSrcMem, // if >s, GR64 = [mem64]
1498 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1499 "cmovg{q}\t{$src2, $dst|$dst, $src2}",
1500 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1501 X86_COND_G, EFLAGS))]>, TB;
1502 def CMOVS64rm : RI<0x48, MRMSrcMem, // if signed, GR64 = [mem64]
1503 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1504 "cmovs{q}\t{$src2, $dst|$dst, $src2}",
1505 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1506 X86_COND_S, EFLAGS))]>, TB;
1507 def CMOVNS64rm: RI<0x49, MRMSrcMem, // if !signed, GR64 = [mem64]
1508 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1509 "cmovns{q}\t{$src2, $dst|$dst, $src2}",
1510 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1511 X86_COND_NS, EFLAGS))]>, TB;
1512 def CMOVP64rm : RI<0x4A, MRMSrcMem, // if parity, GR64 = [mem64]
1513 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1514 "cmovp{q}\t{$src2, $dst|$dst, $src2}",
1515 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1516 X86_COND_P, EFLAGS))]>, TB;
1517 def CMOVNP64rm : RI<0x4B, MRMSrcMem, // if !parity, GR64 = [mem64]
1518 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1519 "cmovnp{q}\t{$src2, $dst|$dst, $src2}",
1520 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1521 X86_COND_NP, EFLAGS))]>, TB;
1522 def CMOVO64rm : RI<0x40, MRMSrcMem, // if overflow, GR64 = [mem64]
1523 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1524 "cmovo{q}\t{$src2, $dst|$dst, $src2}",
1525 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1526 X86_COND_O, EFLAGS))]>, TB;
1527 def CMOVNO64rm : RI<0x41, MRMSrcMem, // if !overflow, GR64 = [mem64]
1528 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1529 "cmovno{q}\t{$src2, $dst|$dst, $src2}",
1530 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1531 X86_COND_NO, EFLAGS))]>, TB;
1532 } // Constraints = "$src1 = $dst"
1534 // Use sbb to materialize carry flag into a GPR.
1535 // FIXME: This are pseudo ops that should be replaced with Pat<> patterns.
1536 // However, Pat<> can't replicate the destination reg into the inputs of the
1538 // FIXME: Change this to have encoding Pseudo when X86MCCodeEmitter replaces
1540 let Defs = [EFLAGS], Uses = [EFLAGS], isCodeGenOnly = 1 in
1541 def SETB_C64r : RI<0x19, MRMInitReg, (outs GR64:$dst), (ins), "",
1542 [(set GR64:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
1544 def : Pat<(i64 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
1547 //===----------------------------------------------------------------------===//
1548 // Descriptor-table support instructions
1550 // LLDT is not interpreted specially in 64-bit mode because there is no sign
1552 def SLDT64r : RI<0x00, MRM0r, (outs GR64:$dst), (ins),
1553 "sldt{q}\t$dst", []>, TB;
1554 def SLDT64m : RI<0x00, MRM0m, (outs i16mem:$dst), (ins),
1555 "sldt{q}\t$dst", []>, TB;
1557 //===----------------------------------------------------------------------===//
1558 // Alias Instructions
1559 //===----------------------------------------------------------------------===//
1561 // We want to rewrite MOV64r0 in terms of MOV32r0, because it's sometimes a
1562 // smaller encoding, but doing so at isel time interferes with rematerialization
1563 // in the current register allocator. For now, this is rewritten when the
1564 // instruction is lowered to an MCInst.
1565 // FIXME: AddedComplexity gives this a higher priority than MOV64ri32. Remove
1566 // when we have a better way to specify isel priority.
1567 let Defs = [EFLAGS],
1568 AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1 in
1569 def MOV64r0 : I<0x31, MRMInitReg, (outs GR64:$dst), (ins), "",
1570 [(set GR64:$dst, 0)]>;
1572 // Materialize i64 constant where top 32-bits are zero. This could theoretically
1573 // use MOV32ri with a SUBREG_TO_REG to represent the zero-extension, however
1574 // that would make it more difficult to rematerialize.
1575 let AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1 in
1576 def MOV64ri64i32 : Ii32<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64i32imm:$src),
1577 "", [(set GR64:$dst, i64immZExt32:$src)]>;
1579 //===----------------------------------------------------------------------===//
1580 // Thread Local Storage Instructions
1581 //===----------------------------------------------------------------------===//
1584 // All calls clobber the non-callee saved registers. RSP is marked as
1585 // a use to prevent stack-pointer assignments that appear immediately
1586 // before calls from potentially appearing dead.
1587 let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
1588 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
1589 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
1590 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
1591 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
1593 def TLS_addr64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
1595 "leaq\t$sym(%rip), %rdi; "
1598 "call\t__tls_get_addr@PLT",
1599 [(X86tlsaddr tls64addr:$sym)]>,
1600 Requires<[In64BitMode]>;
1602 // Darwin TLS Support
1603 // For x86_64, the address of the thunk is passed in %rdi, on return
1604 // the address of the variable is in %rax. All other registers are preserved.
1607 usesCustomInserter = 1 in
1608 def TLSCall_64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
1610 [(X86TLSCall addr:$sym)]>,
1611 Requires<[In64BitMode]>;
1613 let AddedComplexity = 5, isCodeGenOnly = 1 in
1614 def MOV64GSrm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1615 "movq\t%gs:$src, $dst",
1616 [(set GR64:$dst, (gsload addr:$src))]>, SegGS;
1618 let AddedComplexity = 5, isCodeGenOnly = 1 in
1619 def MOV64FSrm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1620 "movq\t%fs:$src, $dst",
1621 [(set GR64:$dst, (fsload addr:$src))]>, SegFS;
1623 //===----------------------------------------------------------------------===//
1624 // Atomic Instructions
1625 //===----------------------------------------------------------------------===//
1627 // TODO: Get this to fold the constant into the instruction.
1628 let hasSideEffects = 1, Defs = [ESP] in
1629 def Int_MemBarrierNoSSE64 : RI<0x09, MRM1r, (outs), (ins GR64:$zero),
1631 "or{q}\t{$zero, (%rsp)|(%rsp), $zero}",
1632 [(X86MemBarrierNoSSE GR64:$zero)]>,
1633 Requires<[In64BitMode]>, LOCK;
1635 let Defs = [RAX, EFLAGS], Uses = [RAX] in {
1636 def LCMPXCHG64 : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$ptr, GR64:$swap),
1638 "cmpxchgq\t$swap,$ptr",
1639 [(X86cas addr:$ptr, GR64:$swap, 8)]>, TB, LOCK;
1642 let Constraints = "$val = $dst" in {
1643 let Defs = [EFLAGS] in
1644 def LXADD64 : RI<0xC1, MRMSrcMem, (outs GR64:$dst), (ins GR64:$val,i64mem:$ptr),
1647 [(set GR64:$dst, (atomic_load_add_64 addr:$ptr, GR64:$val))]>,
1650 def XCHG64rm : RI<0x87, MRMSrcMem, (outs GR64:$dst),
1651 (ins GR64:$val,i64mem:$ptr),
1652 "xchg{q}\t{$val, $ptr|$ptr, $val}",
1653 [(set GR64:$dst, (atomic_swap_64 addr:$ptr, GR64:$val))]>;
1655 def XCHG64rr : RI<0x87, MRMSrcReg, (outs GR64:$dst), (ins GR64:$val,GR64:$src),
1656 "xchg{q}\t{$val, $src|$src, $val}", []>;
1659 def XADD64rr : RI<0xC1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1660 "xadd{q}\t{$src, $dst|$dst, $src}", []>, TB;
1661 let mayLoad = 1, mayStore = 1 in
1662 def XADD64rm : RI<0xC1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1663 "xadd{q}\t{$src, $dst|$dst, $src}", []>, TB;
1665 def CMPXCHG64rr : RI<0xB1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1666 "cmpxchg{q}\t{$src, $dst|$dst, $src}", []>, TB;
1667 let mayLoad = 1, mayStore = 1 in
1668 def CMPXCHG64rm : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1669 "cmpxchg{q}\t{$src, $dst|$dst, $src}", []>, TB;
1671 let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX] in
1672 def CMPXCHG16B : RI<0xC7, MRM1m, (outs), (ins i128mem:$dst),
1673 "cmpxchg16b\t$dst", []>, TB;
1675 def XCHG64ar : RI<0x90, AddRegFrm, (outs), (ins GR64:$src),
1676 "xchg{q}\t{$src, %rax|%rax, $src}", []>;
1678 // Optimized codegen when the non-memory output is not used.
1679 let Defs = [EFLAGS], mayLoad = 1, mayStore = 1 in {
1680 // FIXME: Use normal add / sub instructions and add lock prefix dynamically.
1681 def LOCK_ADD64mr : RI<0x01, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
1683 "add{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1684 def LOCK_ADD64mi8 : RIi8<0x83, MRM0m, (outs),
1685 (ins i64mem:$dst, i64i8imm :$src2),
1687 "add{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1688 def LOCK_ADD64mi32 : RIi32<0x81, MRM0m, (outs),
1689 (ins i64mem:$dst, i64i32imm :$src2),
1691 "add{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1692 def LOCK_SUB64mr : RI<0x29, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
1694 "sub{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1695 def LOCK_SUB64mi8 : RIi8<0x83, MRM5m, (outs),
1696 (ins i64mem:$dst, i64i8imm :$src2),
1698 "sub{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1699 def LOCK_SUB64mi32 : RIi32<0x81, MRM5m, (outs),
1700 (ins i64mem:$dst, i64i32imm:$src2),
1702 "sub{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1703 def LOCK_INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst),
1705 "inc{q}\t$dst", []>, LOCK;
1706 def LOCK_DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst),
1708 "dec{q}\t$dst", []>, LOCK;
1710 // Atomic exchange, and, or, xor
1711 let Constraints = "$val = $dst", Defs = [EFLAGS],
1712 usesCustomInserter = 1 in {
1713 def ATOMAND64 : I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1714 "#ATOMAND64 PSEUDO!",
1715 [(set GR64:$dst, (atomic_load_and_64 addr:$ptr, GR64:$val))]>;
1716 def ATOMOR64 : I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1717 "#ATOMOR64 PSEUDO!",
1718 [(set GR64:$dst, (atomic_load_or_64 addr:$ptr, GR64:$val))]>;
1719 def ATOMXOR64 : I<0, Pseudo,(outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1720 "#ATOMXOR64 PSEUDO!",
1721 [(set GR64:$dst, (atomic_load_xor_64 addr:$ptr, GR64:$val))]>;
1722 def ATOMNAND64 : I<0, Pseudo,(outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1723 "#ATOMNAND64 PSEUDO!",
1724 [(set GR64:$dst, (atomic_load_nand_64 addr:$ptr, GR64:$val))]>;
1725 def ATOMMIN64: I<0, Pseudo, (outs GR64:$dst), (ins i64mem:$ptr, GR64:$val),
1726 "#ATOMMIN64 PSEUDO!",
1727 [(set GR64:$dst, (atomic_load_min_64 addr:$ptr, GR64:$val))]>;
1728 def ATOMMAX64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1729 "#ATOMMAX64 PSEUDO!",
1730 [(set GR64:$dst, (atomic_load_max_64 addr:$ptr, GR64:$val))]>;
1731 def ATOMUMIN64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1732 "#ATOMUMIN64 PSEUDO!",
1733 [(set GR64:$dst, (atomic_load_umin_64 addr:$ptr, GR64:$val))]>;
1734 def ATOMUMAX64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1735 "#ATOMUMAX64 PSEUDO!",
1736 [(set GR64:$dst, (atomic_load_umax_64 addr:$ptr, GR64:$val))]>;
1739 // Segmentation support instructions
1741 // i16mem operand in LAR64rm and GR32 operand in LAR32rr is not a typo.
1742 def LAR64rm : RI<0x02, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
1743 "lar{q}\t{$src, $dst|$dst, $src}", []>, TB;
1744 def LAR64rr : RI<0x02, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src),
1745 "lar{q}\t{$src, $dst|$dst, $src}", []>, TB;
1747 def LSL64rm : RI<0x03, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1748 "lsl{q}\t{$src, $dst|$dst, $src}", []>, TB;
1749 def LSL64rr : RI<0x03, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1750 "lsl{q}\t{$src, $dst|$dst, $src}", []>, TB;
1752 def SWAPGS : I<0x01, MRM_F8, (outs), (ins), "swapgs", []>, TB;
1754 def PUSHFS64 : I<0xa0, RawFrm, (outs), (ins),
1755 "push{q}\t%fs", []>, TB;
1756 def PUSHGS64 : I<0xa8, RawFrm, (outs), (ins),
1757 "push{q}\t%gs", []>, TB;
1759 def POPFS64 : I<0xa1, RawFrm, (outs), (ins),
1760 "pop{q}\t%fs", []>, TB;
1761 def POPGS64 : I<0xa9, RawFrm, (outs), (ins),
1762 "pop{q}\t%gs", []>, TB;
1764 def LSS64rm : RI<0xb2, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
1765 "lss{q}\t{$src, $dst|$dst, $src}", []>, TB;
1766 def LFS64rm : RI<0xb4, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
1767 "lfs{q}\t{$src, $dst|$dst, $src}", []>, TB;
1768 def LGS64rm : RI<0xb5, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
1769 "lgs{q}\t{$src, $dst|$dst, $src}", []>, TB;
1771 // Specialized register support
1773 // no m form encodable; use SMSW16m
1774 def SMSW64r : RI<0x01, MRM4r, (outs GR64:$dst), (ins),
1775 "smsw{q}\t$dst", []>, TB;
1777 // String manipulation instructions
1779 def LODSQ : RI<0xAD, RawFrm, (outs), (ins), "lodsq", []>;
1781 //===----------------------------------------------------------------------===//
1782 // Non-Instruction Patterns
1783 //===----------------------------------------------------------------------===//
1785 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable when not in small
1786 // code model mode, should use 'movabs'. FIXME: This is really a hack, the
1787 // 'movabs' predicate should handle this sort of thing.
1788 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
1789 (MOV64ri tconstpool :$dst)>, Requires<[FarData]>;
1790 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
1791 (MOV64ri tjumptable :$dst)>, Requires<[FarData]>;
1792 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
1793 (MOV64ri tglobaladdr :$dst)>, Requires<[FarData]>;
1794 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
1795 (MOV64ri texternalsym:$dst)>, Requires<[FarData]>;
1796 def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
1797 (MOV64ri tblockaddress:$dst)>, Requires<[FarData]>;
1799 // In static codegen with small code model, we can get the address of a label
1800 // into a register with 'movl'. FIXME: This is a hack, the 'imm' predicate of
1801 // the MOV64ri64i32 should accept these.
1802 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
1803 (MOV64ri64i32 tconstpool :$dst)>, Requires<[SmallCode]>;
1804 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
1805 (MOV64ri64i32 tjumptable :$dst)>, Requires<[SmallCode]>;
1806 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
1807 (MOV64ri64i32 tglobaladdr :$dst)>, Requires<[SmallCode]>;
1808 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
1809 (MOV64ri64i32 texternalsym:$dst)>, Requires<[SmallCode]>;
1810 def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
1811 (MOV64ri64i32 tblockaddress:$dst)>, Requires<[SmallCode]>;
1813 // In kernel code model, we can get the address of a label
1814 // into a register with 'movq'. FIXME: This is a hack, the 'imm' predicate of
1815 // the MOV64ri32 should accept these.
1816 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
1817 (MOV64ri32 tconstpool :$dst)>, Requires<[KernelCode]>;
1818 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
1819 (MOV64ri32 tjumptable :$dst)>, Requires<[KernelCode]>;
1820 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
1821 (MOV64ri32 tglobaladdr :$dst)>, Requires<[KernelCode]>;
1822 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
1823 (MOV64ri32 texternalsym:$dst)>, Requires<[KernelCode]>;
1824 def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
1825 (MOV64ri32 tblockaddress:$dst)>, Requires<[KernelCode]>;
1827 // If we have small model and -static mode, it is safe to store global addresses
1828 // directly as immediates. FIXME: This is really a hack, the 'imm' predicate
1829 // for MOV64mi32 should handle this sort of thing.
1830 def : Pat<(store (i64 (X86Wrapper tconstpool:$src)), addr:$dst),
1831 (MOV64mi32 addr:$dst, tconstpool:$src)>,
1832 Requires<[NearData, IsStatic]>;
1833 def : Pat<(store (i64 (X86Wrapper tjumptable:$src)), addr:$dst),
1834 (MOV64mi32 addr:$dst, tjumptable:$src)>,
1835 Requires<[NearData, IsStatic]>;
1836 def : Pat<(store (i64 (X86Wrapper tglobaladdr:$src)), addr:$dst),
1837 (MOV64mi32 addr:$dst, tglobaladdr:$src)>,
1838 Requires<[NearData, IsStatic]>;
1839 def : Pat<(store (i64 (X86Wrapper texternalsym:$src)), addr:$dst),
1840 (MOV64mi32 addr:$dst, texternalsym:$src)>,
1841 Requires<[NearData, IsStatic]>;
1842 def : Pat<(store (i64 (X86Wrapper tblockaddress:$src)), addr:$dst),
1843 (MOV64mi32 addr:$dst, tblockaddress:$src)>,
1844 Requires<[NearData, IsStatic]>;
1847 // Direct PC relative function call for small code model. 32-bit displacement
1848 // sign extended to 64-bit.
1849 def : Pat<(X86call (i64 tglobaladdr:$dst)),
1850 (CALL64pcrel32 tglobaladdr:$dst)>, Requires<[NotWin64]>;
1851 def : Pat<(X86call (i64 texternalsym:$dst)),
1852 (CALL64pcrel32 texternalsym:$dst)>, Requires<[NotWin64]>;
1854 def : Pat<(X86call (i64 tglobaladdr:$dst)),
1855 (WINCALL64pcrel32 tglobaladdr:$dst)>, Requires<[IsWin64]>;
1856 def : Pat<(X86call (i64 texternalsym:$dst)),
1857 (WINCALL64pcrel32 texternalsym:$dst)>, Requires<[IsWin64]>;
1860 def : Pat<(X86tcret GR64_TC:$dst, imm:$off),
1861 (TCRETURNri64 GR64_TC:$dst, imm:$off)>,
1862 Requires<[In64BitMode]>;
1864 def : Pat<(X86tcret (load addr:$dst), imm:$off),
1865 (TCRETURNmi64 addr:$dst, imm:$off)>,
1866 Requires<[In64BitMode]>;
1868 def : Pat<(X86tcret (i64 tglobaladdr:$dst), imm:$off),
1869 (TCRETURNdi64 tglobaladdr:$dst, imm:$off)>,
1870 Requires<[In64BitMode]>;
1872 def : Pat<(X86tcret (i64 texternalsym:$dst), imm:$off),
1873 (TCRETURNdi64 texternalsym:$dst, imm:$off)>,
1874 Requires<[In64BitMode]>;
1876 // tls has some funny stuff here...
1877 // This corresponds to movabs $foo@tpoff, %rax
1878 def : Pat<(i64 (X86Wrapper tglobaltlsaddr :$dst)),
1879 (MOV64ri tglobaltlsaddr :$dst)>;
1880 // This corresponds to add $foo@tpoff, %rax
1881 def : Pat<(add GR64:$src1, (X86Wrapper tglobaltlsaddr :$dst)),
1882 (ADD64ri32 GR64:$src1, tglobaltlsaddr :$dst)>;
1883 // This corresponds to mov foo@tpoff(%rbx), %eax
1884 def : Pat<(load (i64 (X86Wrapper tglobaltlsaddr :$dst))),
1885 (MOV64rm tglobaltlsaddr :$dst)>;
1889 // TEST R,R is smaller than CMP R,0
1890 def : Pat<(X86cmp GR64:$src1, 0),
1891 (TEST64rr GR64:$src1, GR64:$src1)>;
1893 // Conditional moves with folded loads with operands swapped and conditions
1895 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_B, EFLAGS),
1896 (CMOVAE64rm GR64:$src2, addr:$src1)>;
1897 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_AE, EFLAGS),
1898 (CMOVB64rm GR64:$src2, addr:$src1)>;
1899 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_E, EFLAGS),
1900 (CMOVNE64rm GR64:$src2, addr:$src1)>;
1901 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NE, EFLAGS),
1902 (CMOVE64rm GR64:$src2, addr:$src1)>;
1903 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_BE, EFLAGS),
1904 (CMOVA64rm GR64:$src2, addr:$src1)>;
1905 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_A, EFLAGS),
1906 (CMOVBE64rm GR64:$src2, addr:$src1)>;
1907 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_L, EFLAGS),
1908 (CMOVGE64rm GR64:$src2, addr:$src1)>;
1909 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_GE, EFLAGS),
1910 (CMOVL64rm GR64:$src2, addr:$src1)>;
1911 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_LE, EFLAGS),
1912 (CMOVG64rm GR64:$src2, addr:$src1)>;
1913 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_G, EFLAGS),
1914 (CMOVLE64rm GR64:$src2, addr:$src1)>;
1915 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_P, EFLAGS),
1916 (CMOVNP64rm GR64:$src2, addr:$src1)>;
1917 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NP, EFLAGS),
1918 (CMOVP64rm GR64:$src2, addr:$src1)>;
1919 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_S, EFLAGS),
1920 (CMOVNS64rm GR64:$src2, addr:$src1)>;
1921 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NS, EFLAGS),
1922 (CMOVS64rm GR64:$src2, addr:$src1)>;
1923 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_O, EFLAGS),
1924 (CMOVNO64rm GR64:$src2, addr:$src1)>;
1925 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NO, EFLAGS),
1926 (CMOVO64rm GR64:$src2, addr:$src1)>;
1928 // zextload bool -> zextload byte
1929 def : Pat<(zextloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>;
1932 // When extloading from 16-bit and smaller memory locations into 64-bit
1933 // registers, use zero-extending loads so that the entire 64-bit register is
1934 // defined, avoiding partial-register updates.
1935 def : Pat<(extloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>;
1936 def : Pat<(extloadi64i8 addr:$src), (MOVZX64rm8 addr:$src)>;
1937 def : Pat<(extloadi64i16 addr:$src), (MOVZX64rm16 addr:$src)>;
1938 // For other extloads, use subregs, since the high contents of the register are
1939 // defined after an extload.
1940 def : Pat<(extloadi64i32 addr:$src),
1941 (SUBREG_TO_REG (i64 0), (MOV32rm addr:$src),
1944 // anyext. Define these to do an explicit zero-extend to
1945 // avoid partial-register updates.
1946 def : Pat<(i64 (anyext GR8 :$src)), (MOVZX64rr8 GR8 :$src)>;
1947 def : Pat<(i64 (anyext GR16:$src)), (MOVZX64rr16 GR16 :$src)>;
1948 def : Pat<(i64 (anyext GR32:$src)),
1949 (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>;
1951 //===----------------------------------------------------------------------===//
1953 //===----------------------------------------------------------------------===//
1955 // Odd encoding trick: -128 fits into an 8-bit immediate field while
1956 // +128 doesn't, so in this special case use a sub instead of an add.
1957 def : Pat<(add GR64:$src1, 128),
1958 (SUB64ri8 GR64:$src1, -128)>;
1959 def : Pat<(store (add (loadi64 addr:$dst), 128), addr:$dst),
1960 (SUB64mi8 addr:$dst, -128)>;
1962 // The same trick applies for 32-bit immediate fields in 64-bit
1964 def : Pat<(add GR64:$src1, 0x0000000080000000),
1965 (SUB64ri32 GR64:$src1, 0xffffffff80000000)>;
1966 def : Pat<(store (add (loadi64 addr:$dst), 0x00000000800000000), addr:$dst),
1967 (SUB64mi32 addr:$dst, 0xffffffff80000000)>;
1969 // Use a 32-bit and with implicit zero-extension instead of a 64-bit and if it
1970 // has an immediate with at least 32 bits of leading zeros, to avoid needing to
1971 // materialize that immediate in a register first.
1972 def : Pat<(and GR64:$src, i64immZExt32:$imm),
1976 (EXTRACT_SUBREG GR64:$src, sub_32bit),
1977 (i32 (GetLo32XForm imm:$imm))),
1980 // r & (2^32-1) ==> movz
1981 def : Pat<(and GR64:$src, 0x00000000FFFFFFFF),
1982 (MOVZX64rr32 (EXTRACT_SUBREG GR64:$src, sub_32bit))>;
1983 // r & (2^16-1) ==> movz
1984 def : Pat<(and GR64:$src, 0xffff),
1985 (MOVZX64rr16 (i16 (EXTRACT_SUBREG GR64:$src, sub_16bit)))>;
1986 // r & (2^8-1) ==> movz
1987 def : Pat<(and GR64:$src, 0xff),
1988 (MOVZX64rr8 (i8 (EXTRACT_SUBREG GR64:$src, sub_8bit)))>;
1989 // r & (2^8-1) ==> movz
1990 def : Pat<(and GR32:$src1, 0xff),
1991 (MOVZX32rr8 (EXTRACT_SUBREG GR32:$src1, sub_8bit))>,
1992 Requires<[In64BitMode]>;
1993 // r & (2^8-1) ==> movz
1994 def : Pat<(and GR16:$src1, 0xff),
1995 (MOVZX16rr8 (i8 (EXTRACT_SUBREG GR16:$src1, sub_8bit)))>,
1996 Requires<[In64BitMode]>;
1998 // sext_inreg patterns
1999 def : Pat<(sext_inreg GR64:$src, i32),
2000 (MOVSX64rr32 (EXTRACT_SUBREG GR64:$src, sub_32bit))>;
2001 def : Pat<(sext_inreg GR64:$src, i16),
2002 (MOVSX64rr16 (EXTRACT_SUBREG GR64:$src, sub_16bit))>;
2003 def : Pat<(sext_inreg GR64:$src, i8),
2004 (MOVSX64rr8 (EXTRACT_SUBREG GR64:$src, sub_8bit))>;
2005 def : Pat<(sext_inreg GR32:$src, i8),
2006 (MOVSX32rr8 (EXTRACT_SUBREG GR32:$src, sub_8bit))>,
2007 Requires<[In64BitMode]>;
2008 def : Pat<(sext_inreg GR16:$src, i8),
2009 (MOVSX16rr8 (i8 (EXTRACT_SUBREG GR16:$src, sub_8bit)))>,
2010 Requires<[In64BitMode]>;
2013 def : Pat<(i32 (trunc GR64:$src)),
2014 (EXTRACT_SUBREG GR64:$src, sub_32bit)>;
2015 def : Pat<(i16 (trunc GR64:$src)),
2016 (EXTRACT_SUBREG GR64:$src, sub_16bit)>;
2017 def : Pat<(i8 (trunc GR64:$src)),
2018 (EXTRACT_SUBREG GR64:$src, sub_8bit)>;
2019 def : Pat<(i8 (trunc GR32:$src)),
2020 (EXTRACT_SUBREG GR32:$src, sub_8bit)>,
2021 Requires<[In64BitMode]>;
2022 def : Pat<(i8 (trunc GR16:$src)),
2023 (EXTRACT_SUBREG GR16:$src, sub_8bit)>,
2024 Requires<[In64BitMode]>;
2026 // h-register tricks.
2027 // For now, be conservative on x86-64 and use an h-register extract only if the
2028 // value is immediately zero-extended or stored, which are somewhat common
2029 // cases. This uses a bunch of code to prevent a register requiring a REX prefix
2030 // from being allocated in the same instruction as the h register, as there's
2031 // currently no way to describe this requirement to the register allocator.
2033 // h-register extract and zero-extend.
2034 def : Pat<(and (srl_su GR64:$src, (i8 8)), (i64 255)),
2038 (EXTRACT_SUBREG (i64 (COPY_TO_REGCLASS GR64:$src, GR64_ABCD)),
2041 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
2043 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
2045 Requires<[In64BitMode]>;
2046 def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)),
2047 (MOVZX32_NOREXrr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
2050 Requires<[In64BitMode]>;
2051 def : Pat<(srl GR16:$src, (i8 8)),
2054 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
2057 Requires<[In64BitMode]>;
2058 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
2060 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
2062 Requires<[In64BitMode]>;
2063 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
2065 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
2067 Requires<[In64BitMode]>;
2068 def : Pat<(i64 (zext (srl_su GR16:$src, (i8 8)))),
2072 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
2075 def : Pat<(i64 (anyext (srl_su GR16:$src, (i8 8)))),
2079 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
2083 // h-register extract and store.
2084 def : Pat<(store (i8 (trunc_su (srl_su GR64:$src, (i8 8)))), addr:$dst),
2087 (EXTRACT_SUBREG (i64 (COPY_TO_REGCLASS GR64:$src, GR64_ABCD)),
2089 def : Pat<(store (i8 (trunc_su (srl_su GR32:$src, (i8 8)))), addr:$dst),
2092 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
2094 Requires<[In64BitMode]>;
2095 def : Pat<(store (i8 (trunc_su (srl_su GR16:$src, (i8 8)))), addr:$dst),
2098 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
2100 Requires<[In64BitMode]>;
2102 // (shl x, 1) ==> (add x, x)
2103 def : Pat<(shl GR64:$src1, (i8 1)), (ADD64rr GR64:$src1, GR64:$src1)>;
2105 // (shl x (and y, 63)) ==> (shl x, y)
2106 def : Pat<(shl GR64:$src1, (and CL, 63)),
2107 (SHL64rCL GR64:$src1)>;
2108 def : Pat<(store (shl (loadi64 addr:$dst), (and CL, 63)), addr:$dst),
2109 (SHL64mCL addr:$dst)>;
2111 def : Pat<(srl GR64:$src1, (and CL, 63)),
2112 (SHR64rCL GR64:$src1)>;
2113 def : Pat<(store (srl (loadi64 addr:$dst), (and CL, 63)), addr:$dst),
2114 (SHR64mCL addr:$dst)>;
2116 def : Pat<(sra GR64:$src1, (and CL, 63)),
2117 (SAR64rCL GR64:$src1)>;
2118 def : Pat<(store (sra (loadi64 addr:$dst), (and CL, 63)), addr:$dst),
2119 (SAR64mCL addr:$dst)>;
2121 // (or x1, x2) -> (add x1, x2) if two operands are known not to share bits.
2122 let AddedComplexity = 5 in { // Try this before the selecting to OR
2123 def : Pat<(or_is_add GR64:$src1, i64immSExt8:$src2),
2124 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
2125 def : Pat<(or_is_add GR64:$src1, i64immSExt32:$src2),
2126 (ADD64ri32 GR64:$src1, i64immSExt32:$src2)>;
2127 def : Pat<(or_is_add GR64:$src1, GR64:$src2),
2128 (ADD64rr GR64:$src1, GR64:$src2)>;
2129 } // AddedComplexity
2131 // X86 specific add which produces a flag.
2132 def : Pat<(addc GR64:$src1, GR64:$src2),
2133 (ADD64rr GR64:$src1, GR64:$src2)>;
2134 def : Pat<(addc GR64:$src1, (load addr:$src2)),
2135 (ADD64rm GR64:$src1, addr:$src2)>;
2136 def : Pat<(addc GR64:$src1, i64immSExt8:$src2),
2137 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
2138 def : Pat<(addc GR64:$src1, i64immSExt32:$src2),
2139 (ADD64ri32 GR64:$src1, imm:$src2)>;
2141 def : Pat<(subc GR64:$src1, GR64:$src2),
2142 (SUB64rr GR64:$src1, GR64:$src2)>;
2143 def : Pat<(subc GR64:$src1, (load addr:$src2)),
2144 (SUB64rm GR64:$src1, addr:$src2)>;
2145 def : Pat<(subc GR64:$src1, i64immSExt8:$src2),
2146 (SUB64ri8 GR64:$src1, i64immSExt8:$src2)>;
2147 def : Pat<(subc GR64:$src1, imm:$src2),
2148 (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>;
2150 //===----------------------------------------------------------------------===//
2151 // EFLAGS-defining Patterns
2152 //===----------------------------------------------------------------------===//
2155 def : Pat<(add GR64:$src1, GR64:$src2),
2156 (ADD64rr GR64:$src1, GR64:$src2)>;
2157 def : Pat<(add GR64:$src1, i64immSExt8:$src2),
2158 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
2159 def : Pat<(add GR64:$src1, i64immSExt32:$src2),
2160 (ADD64ri32 GR64:$src1, i64immSExt32:$src2)>;
2161 def : Pat<(add GR64:$src1, (loadi64 addr:$src2)),
2162 (ADD64rm GR64:$src1, addr:$src2)>;
2165 def : Pat<(sub GR64:$src1, GR64:$src2),
2166 (SUB64rr GR64:$src1, GR64:$src2)>;
2167 def : Pat<(sub GR64:$src1, (loadi64 addr:$src2)),
2168 (SUB64rm GR64:$src1, addr:$src2)>;
2169 def : Pat<(sub GR64:$src1, i64immSExt8:$src2),
2170 (SUB64ri8 GR64:$src1, i64immSExt8:$src2)>;
2171 def : Pat<(sub GR64:$src1, i64immSExt32:$src2),
2172 (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>;
2175 def : Pat<(mul GR64:$src1, GR64:$src2),
2176 (IMUL64rr GR64:$src1, GR64:$src2)>;
2177 def : Pat<(mul GR64:$src1, (loadi64 addr:$src2)),
2178 (IMUL64rm GR64:$src1, addr:$src2)>;
2179 def : Pat<(mul GR64:$src1, i64immSExt8:$src2),
2180 (IMUL64rri8 GR64:$src1, i64immSExt8:$src2)>;
2181 def : Pat<(mul GR64:$src1, i64immSExt32:$src2),
2182 (IMUL64rri32 GR64:$src1, i64immSExt32:$src2)>;
2183 def : Pat<(mul (loadi64 addr:$src1), i64immSExt8:$src2),
2184 (IMUL64rmi8 addr:$src1, i64immSExt8:$src2)>;
2185 def : Pat<(mul (loadi64 addr:$src1), i64immSExt32:$src2),
2186 (IMUL64rmi32 addr:$src1, i64immSExt32:$src2)>;
2189 def : Pat<(add GR16:$src, 1), (INC64_16r GR16:$src)>, Requires<[In64BitMode]>;
2190 def : Pat<(add GR16:$src, -1), (DEC64_16r GR16:$src)>, Requires<[In64BitMode]>;
2191 def : Pat<(add GR32:$src, 1), (INC64_32r GR32:$src)>, Requires<[In64BitMode]>;
2192 def : Pat<(add GR32:$src, -1), (DEC64_32r GR32:$src)>, Requires<[In64BitMode]>;
2193 def : Pat<(add GR64:$src, 1), (INC64r GR64:$src)>;
2194 def : Pat<(add GR64:$src, -1), (DEC64r GR64:$src)>;
2197 def : Pat<(or GR64:$src1, GR64:$src2),
2198 (OR64rr GR64:$src1, GR64:$src2)>;
2199 def : Pat<(or GR64:$src1, i64immSExt8:$src2),
2200 (OR64ri8 GR64:$src1, i64immSExt8:$src2)>;
2201 def : Pat<(or GR64:$src1, i64immSExt32:$src2),
2202 (OR64ri32 GR64:$src1, i64immSExt32:$src2)>;
2203 def : Pat<(or GR64:$src1, (loadi64 addr:$src2)),
2204 (OR64rm GR64:$src1, addr:$src2)>;
2207 def : Pat<(xor GR64:$src1, GR64:$src2),
2208 (XOR64rr GR64:$src1, GR64:$src2)>;
2209 def : Pat<(xor GR64:$src1, i64immSExt8:$src2),
2210 (XOR64ri8 GR64:$src1, i64immSExt8:$src2)>;
2211 def : Pat<(xor GR64:$src1, i64immSExt32:$src2),
2212 (XOR64ri32 GR64:$src1, i64immSExt32:$src2)>;
2213 def : Pat<(xor GR64:$src1, (loadi64 addr:$src2)),
2214 (XOR64rm GR64:$src1, addr:$src2)>;
2217 def : Pat<(and GR64:$src1, GR64:$src2),
2218 (AND64rr GR64:$src1, GR64:$src2)>;
2219 def : Pat<(and GR64:$src1, i64immSExt8:$src2),
2220 (AND64ri8 GR64:$src1, i64immSExt8:$src2)>;
2221 def : Pat<(and GR64:$src1, i64immSExt32:$src2),
2222 (AND64ri32 GR64:$src1, i64immSExt32:$src2)>;
2223 def : Pat<(and GR64:$src1, (loadi64 addr:$src2)),
2224 (AND64rm GR64:$src1, addr:$src2)>;
2226 //===----------------------------------------------------------------------===//
2227 // X86-64 SSE Instructions
2228 //===----------------------------------------------------------------------===//
2230 // Move instructions...
2232 def MOV64toPQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
2233 "mov{d|q}\t{$src, $dst|$dst, $src}",
2235 (v2i64 (scalar_to_vector GR64:$src)))]>;
2236 def MOVPQIto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
2237 "mov{d|q}\t{$src, $dst|$dst, $src}",
2238 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
2241 def MOV64toSDrr : RPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
2242 "mov{d|q}\t{$src, $dst|$dst, $src}",
2243 [(set FR64:$dst, (bitconvert GR64:$src))]>;
2244 def MOV64toSDrm : S3SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
2245 "movq\t{$src, $dst|$dst, $src}",
2246 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>;
2248 def MOVSDto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
2249 "mov{d|q}\t{$src, $dst|$dst, $src}",
2250 [(set GR64:$dst, (bitconvert FR64:$src))]>;
2251 def MOVSDto64mr : RPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
2252 "movq\t{$src, $dst|$dst, $src}",
2253 [(store (i64 (bitconvert FR64:$src)), addr:$dst)]>;