1 //====- X86Instr64bit.td - Describe X86-64 Instructions ----*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86-64 instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // Operand Definitions.
20 // 64-bits but only 32 bits are significant.
21 def i64i32imm : Operand<i64>;
23 // 64-bits but only 32 bits are significant, and those bits are treated as being
25 def i64i32imm_pcrel : Operand<i64> {
26 let PrintMethod = "print_pcrel_imm";
30 // 64-bits but only 8 bits are significant.
31 def i64i8imm : Operand<i64> {
32 let ParserMatchClass = ImmSExt8AsmOperand;
35 def lea64mem : Operand<i64> {
36 let PrintMethod = "printlea64mem";
37 let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm);
38 let ParserMatchClass = X86MemAsmOperand;
41 def lea64_32mem : Operand<i32> {
42 let PrintMethod = "printlea64_32mem";
43 let AsmOperandLowerMethod = "lower_lea64_32mem";
44 let MIOperandInfo = (ops GR32, i8imm, GR32_NOSP, i32imm);
45 let ParserMatchClass = X86MemAsmOperand;
48 //===----------------------------------------------------------------------===//
49 // Complex Pattern Definitions.
51 def lea64addr : ComplexPattern<i64, 4, "SelectLEAAddr",
52 [add, sub, mul, X86mul_imm, shl, or, frameindex,
55 def tls64addr : ComplexPattern<i64, 4, "SelectTLSADDRAddr",
56 [tglobaltlsaddr], []>;
58 //===----------------------------------------------------------------------===//
62 def i64immSExt8 : PatLeaf<(i64 imm), [{
63 // i64immSExt8 predicate - True if the 64-bit immediate fits in a 8-bit
64 // sign extended field.
65 return (int64_t)N->getZExtValue() == (int8_t)N->getZExtValue();
68 def i64immSExt32 : PatLeaf<(i64 imm), [{
69 // i64immSExt32 predicate - True if the 64-bit immediate fits in a 32-bit
70 // sign extended field.
71 return (int64_t)N->getZExtValue() == (int32_t)N->getZExtValue();
74 def i64immZExt32 : PatLeaf<(i64 imm), [{
75 // i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit
76 // unsignedsign extended field.
77 return (uint64_t)N->getZExtValue() == (uint32_t)N->getZExtValue();
80 def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>;
81 def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>;
82 def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>;
84 def zextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (zextloadi1 node:$ptr))>;
85 def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>;
86 def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>;
87 def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>;
89 def extloadi64i1 : PatFrag<(ops node:$ptr), (i64 (extloadi1 node:$ptr))>;
90 def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>;
91 def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>;
92 def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>;
94 //===----------------------------------------------------------------------===//
95 // Instruction list...
98 // ADJCALLSTACKDOWN/UP implicitly use/def RSP because they may be expanded into
99 // a stack adjustment and the codegen must know that they may modify the stack
100 // pointer before prolog-epilog rewriting occurs.
101 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
102 // sub / add which can clobber EFLAGS.
103 let Defs = [RSP, EFLAGS], Uses = [RSP] in {
104 def ADJCALLSTACKDOWN64 : I<0, Pseudo, (outs), (ins i32imm:$amt),
106 [(X86callseq_start timm:$amt)]>,
107 Requires<[In64BitMode]>;
108 def ADJCALLSTACKUP64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
110 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
111 Requires<[In64BitMode]>;
114 //===----------------------------------------------------------------------===//
115 // Call Instructions...
118 // All calls clobber the non-callee saved registers. RSP is marked as
119 // a use to prevent stack-pointer assignments that appear immediately
120 // before calls from potentially appearing dead. Uses for argument
121 // registers are added manually.
122 let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
123 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
124 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
125 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
126 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
129 // NOTE: this pattern doesn't match "X86call imm", because we do not know
130 // that the offset between an arbitrary immediate and the call will fit in
131 // the 32-bit pcrel field that we have.
132 def CALL64pcrel32 : Ii32<0xE8, RawFrm,
133 (outs), (ins i64i32imm_pcrel:$dst, variable_ops),
135 Requires<[In64BitMode, NotWin64]>;
136 def CALL64r : I<0xFF, MRM2r, (outs), (ins GR64:$dst, variable_ops),
137 "call\t{*}$dst", [(X86call GR64:$dst)]>,
138 Requires<[NotWin64]>;
139 def CALL64m : I<0xFF, MRM2m, (outs), (ins i64mem:$dst, variable_ops),
140 "call\t{*}$dst", [(X86call (loadi64 addr:$dst))]>,
141 Requires<[NotWin64]>;
143 def FARCALL64 : RI<0xFF, MRM3m, (outs), (ins opaque80mem:$dst),
144 "lcall{q}\t{*}$dst", []>;
147 // FIXME: We need to teach codegen about single list of call-clobbered registers.
149 // All calls clobber the non-callee saved registers. RSP is marked as
150 // a use to prevent stack-pointer assignments that appear immediately
151 // before calls from potentially appearing dead. Uses for argument
152 // registers are added manually.
153 let Defs = [RAX, RCX, RDX, R8, R9, R10, R11,
154 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
155 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
156 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, EFLAGS],
158 def WINCALL64pcrel32 : I<0xE8, RawFrm,
159 (outs), (ins i64i32imm_pcrel:$dst, variable_ops),
162 def WINCALL64r : I<0xFF, MRM2r, (outs), (ins GR64:$dst, variable_ops),
164 [(X86call GR64:$dst)]>, Requires<[IsWin64]>;
165 def WINCALL64m : I<0xFF, MRM2m, (outs), (ins i64mem:$dst, variable_ops),
167 [(X86call (loadi64 addr:$dst))]>, Requires<[IsWin64]>;
171 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
172 def TCRETURNdi64 : I<0, Pseudo, (outs), (ins i64imm:$dst, i32imm:$offset,
174 "#TC_RETURN $dst $offset",
177 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
178 def TCRETURNri64 : I<0, Pseudo, (outs), (ins GR64:$dst, i32imm:$offset,
180 "#TC_RETURN $dst $offset",
184 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
185 def TAILJMPr64 : I<0xFF, MRM4r, (outs), (ins GR64:$dst),
186 "jmp{q}\t{*}$dst # TAILCALL",
190 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
191 def JMP64r : I<0xFF, MRM4r, (outs), (ins GR64:$dst), "jmp{q}\t{*}$dst",
192 [(brind GR64:$dst)]>;
193 def JMP64m : I<0xFF, MRM4m, (outs), (ins i64mem:$dst), "jmp{q}\t{*}$dst",
194 [(brind (loadi64 addr:$dst))]>;
195 def FARJMP64 : RI<0xFF, MRM5m, (outs), (ins opaque80mem:$dst),
196 "ljmp{q}\t{*}$dst", []>;
199 //===----------------------------------------------------------------------===//
200 // EH Pseudo Instructions
202 let isTerminator = 1, isReturn = 1, isBarrier = 1,
204 def EH_RETURN64 : I<0xC3, RawFrm, (outs), (ins GR64:$addr),
205 "ret\t#eh_return, addr: $addr",
206 [(X86ehret GR64:$addr)]>;
210 //===----------------------------------------------------------------------===//
211 // Miscellaneous Instructions...
213 let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, neverHasSideEffects = 1 in
214 def LEAVE64 : I<0xC9, RawFrm,
215 (outs), (ins), "leave", []>;
216 let Defs = [RSP], Uses = [RSP], neverHasSideEffects=1 in {
218 def POP64r : I<0x58, AddRegFrm,
219 (outs GR64:$reg), (ins), "pop{q}\t$reg", []>;
220 def POP64rmr: I<0x8F, MRM0r, (outs GR64:$reg), (ins), "pop{q}\t$reg", []>;
221 def POP64rmm: I<0x8F, MRM0m, (outs i64mem:$dst), (ins), "pop{q}\t$dst", []>;
223 let mayStore = 1 in {
224 def PUSH64r : I<0x50, AddRegFrm,
225 (outs), (ins GR64:$reg), "push{q}\t$reg", []>;
226 def PUSH64rmr: I<0xFF, MRM6r, (outs), (ins GR64:$reg), "push{q}\t$reg", []>;
227 def PUSH64rmm: I<0xFF, MRM6m, (outs), (ins i64mem:$src), "push{q}\t$src", []>;
231 let Defs = [RSP], Uses = [RSP], neverHasSideEffects = 1, mayStore = 1 in {
232 def PUSH64i8 : Ii8<0x6a, RawFrm, (outs), (ins i8imm:$imm),
233 "push{q}\t$imm", []>;
234 def PUSH64i16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
235 "push{q}\t$imm", []>;
236 def PUSH64i32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
237 "push{q}\t$imm", []>;
240 let Defs = [RSP, EFLAGS], Uses = [RSP], mayLoad = 1 in
241 def POPFQ : I<0x9D, RawFrm, (outs), (ins), "popf", []>, REX_W;
242 let Defs = [RSP], Uses = [RSP, EFLAGS], mayStore = 1 in
243 def PUSHFQ : I<0x9C, RawFrm, (outs), (ins), "pushf", []>;
245 def LEA64_32r : I<0x8D, MRMSrcMem,
246 (outs GR32:$dst), (ins lea64_32mem:$src),
247 "lea{l}\t{$src|$dst}, {$dst|$src}",
248 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In64BitMode]>;
250 let isReMaterializable = 1 in
251 def LEA64r : RI<0x8D, MRMSrcMem, (outs GR64:$dst), (ins lea64mem:$src),
252 "lea{q}\t{$src|$dst}, {$dst|$src}",
253 [(set GR64:$dst, lea64addr:$src)]>;
255 let isTwoAddress = 1 in
256 def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src),
258 [(set GR64:$dst, (bswap GR64:$src))]>, TB;
260 // Bit scan instructions.
261 let Defs = [EFLAGS] in {
262 def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
263 "bsf{q}\t{$src, $dst|$dst, $src}",
264 [(set GR64:$dst, (X86bsf GR64:$src)), (implicit EFLAGS)]>, TB;
265 def BSF64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
266 "bsf{q}\t{$src, $dst|$dst, $src}",
267 [(set GR64:$dst, (X86bsf (loadi64 addr:$src))),
268 (implicit EFLAGS)]>, TB;
270 def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
271 "bsr{q}\t{$src, $dst|$dst, $src}",
272 [(set GR64:$dst, (X86bsr GR64:$src)), (implicit EFLAGS)]>, TB;
273 def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
274 "bsr{q}\t{$src, $dst|$dst, $src}",
275 [(set GR64:$dst, (X86bsr (loadi64 addr:$src))),
276 (implicit EFLAGS)]>, TB;
280 let Defs = [RCX,RDI,RSI], Uses = [RCX,RDI,RSI] in
281 def REP_MOVSQ : RI<0xA5, RawFrm, (outs), (ins), "{rep;movsq|rep movsq}",
282 [(X86rep_movs i64)]>, REP;
283 let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI] in
284 def REP_STOSQ : RI<0xAB, RawFrm, (outs), (ins), "{rep;stosq|rep stosq}",
285 [(X86rep_stos i64)]>, REP;
287 def SCAS64 : RI<0xAF, RawFrm, (outs), (ins), "scas{q}", []>;
289 def CMPS64 : RI<0xA7, RawFrm, (outs), (ins), "cmps{q}", []>;
291 // Fast system-call instructions
292 def SYSEXIT64 : RI<0x35, RawFrm,
293 (outs), (ins), "sysexit", []>, TB;
295 //===----------------------------------------------------------------------===//
296 // Move Instructions...
299 let neverHasSideEffects = 1 in
300 def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
301 "mov{q}\t{$src, $dst|$dst, $src}", []>;
303 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
304 def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src),
305 "movabs{q}\t{$src, $dst|$dst, $src}",
306 [(set GR64:$dst, imm:$src)]>;
307 def MOV64ri32 : RIi32<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src),
308 "mov{q}\t{$src, $dst|$dst, $src}",
309 [(set GR64:$dst, i64immSExt32:$src)]>;
312 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
313 def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
314 "mov{q}\t{$src, $dst|$dst, $src}",
315 [(set GR64:$dst, (load addr:$src))]>;
317 def MOV64mr : RI<0x89, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
318 "mov{q}\t{$src, $dst|$dst, $src}",
319 [(store GR64:$src, addr:$dst)]>;
320 def MOV64mi32 : RIi32<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src),
321 "mov{q}\t{$src, $dst|$dst, $src}",
322 [(store i64immSExt32:$src, addr:$dst)]>;
324 def MOV64o8a : RIi8<0xA0, RawFrm, (outs), (ins i8imm:$src),
325 "mov{q}\t{$src, %rax|%rax, $src}", []>;
326 def MOV64o32a : RIi32<0xA1, RawFrm, (outs), (ins i32imm:$src),
327 "mov{q}\t{$src, %rax|%rax, $src}", []>;
328 def MOV64ao8 : RIi8<0xA2, RawFrm, (outs i8imm:$dst), (ins),
329 "mov{q}\t{%rax, $dst|$dst, %rax}", []>;
330 def MOV64ao32 : RIi32<0xA3, RawFrm, (outs i32imm:$dst), (ins),
331 "mov{q}\t{%rax, $dst|$dst, %rax}", []>;
333 // Moves to and from segment registers
334 def MOV64rs : RI<0x8C, MRMDestReg, (outs GR64:$dst), (ins SEGMENT_REG:$src),
335 "mov{w}\t{$src, $dst|$dst, $src}", []>;
336 def MOV64ms : RI<0x8C, MRMDestMem, (outs i64mem:$dst), (ins SEGMENT_REG:$src),
337 "mov{w}\t{$src, $dst|$dst, $src}", []>;
338 def MOV64sr : RI<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR64:$src),
339 "mov{w}\t{$src, $dst|$dst, $src}", []>;
340 def MOV64sm : RI<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i64mem:$src),
341 "mov{w}\t{$src, $dst|$dst, $src}", []>;
343 // Sign/Zero extenders
345 // MOVSX64rr8 always has a REX prefix and it has an 8-bit register
346 // operand, which makes it a rare instruction with an 8-bit register
347 // operand that can never access an h register. If support for h registers
348 // were generalized, this would require a special register class.
349 def MOVSX64rr8 : RI<0xBE, MRMSrcReg, (outs GR64:$dst), (ins GR8 :$src),
350 "movs{bq|x}\t{$src, $dst|$dst, $src}",
351 [(set GR64:$dst, (sext GR8:$src))]>, TB;
352 def MOVSX64rm8 : RI<0xBE, MRMSrcMem, (outs GR64:$dst), (ins i8mem :$src),
353 "movs{bq|x}\t{$src, $dst|$dst, $src}",
354 [(set GR64:$dst, (sextloadi64i8 addr:$src))]>, TB;
355 def MOVSX64rr16: RI<0xBF, MRMSrcReg, (outs GR64:$dst), (ins GR16:$src),
356 "movs{wq|x}\t{$src, $dst|$dst, $src}",
357 [(set GR64:$dst, (sext GR16:$src))]>, TB;
358 def MOVSX64rm16: RI<0xBF, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
359 "movs{wq|x}\t{$src, $dst|$dst, $src}",
360 [(set GR64:$dst, (sextloadi64i16 addr:$src))]>, TB;
361 def MOVSX64rr32: RI<0x63, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src),
362 "movs{lq|xd}\t{$src, $dst|$dst, $src}",
363 [(set GR64:$dst, (sext GR32:$src))]>;
364 def MOVSX64rm32: RI<0x63, MRMSrcMem, (outs GR64:$dst), (ins i32mem:$src),
365 "movs{lq|xd}\t{$src, $dst|$dst, $src}",
366 [(set GR64:$dst, (sextloadi64i32 addr:$src))]>;
368 // Use movzbl instead of movzbq when the destination is a register; it's
369 // equivalent due to implicit zero-extending, and it has a smaller encoding.
370 def MOVZX64rr8 : I<0xB6, MRMSrcReg, (outs GR64:$dst), (ins GR8 :$src),
371 "", [(set GR64:$dst, (zext GR8:$src))]>, TB;
372 def MOVZX64rm8 : I<0xB6, MRMSrcMem, (outs GR64:$dst), (ins i8mem :$src),
373 "", [(set GR64:$dst, (zextloadi64i8 addr:$src))]>, TB;
374 // Use movzwl instead of movzwq when the destination is a register; it's
375 // equivalent due to implicit zero-extending, and it has a smaller encoding.
376 def MOVZX64rr16: I<0xB7, MRMSrcReg, (outs GR64:$dst), (ins GR16:$src),
377 "", [(set GR64:$dst, (zext GR16:$src))]>, TB;
378 def MOVZX64rm16: I<0xB7, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
379 "", [(set GR64:$dst, (zextloadi64i16 addr:$src))]>, TB;
381 // There's no movzlq instruction, but movl can be used for this purpose, using
382 // implicit zero-extension. The preferred way to do 32-bit-to-64-bit zero
383 // extension on x86-64 is to use a SUBREG_TO_REG to utilize implicit
384 // zero-extension, however this isn't possible when the 32-bit value is
385 // defined by a truncate or is copied from something where the high bits aren't
386 // necessarily all zero. In such cases, we fall back to these explicit zext
388 def MOVZX64rr32 : I<0x89, MRMDestReg, (outs GR64:$dst), (ins GR32:$src),
389 "", [(set GR64:$dst, (zext GR32:$src))]>;
390 def MOVZX64rm32 : I<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i32mem:$src),
391 "", [(set GR64:$dst, (zextloadi64i32 addr:$src))]>;
393 // Any instruction that defines a 32-bit result leaves the high half of the
394 // register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may
395 // be copying from a truncate. And x86's cmov doesn't do anything if the
396 // condition is false. But any other 32-bit operation will zero-extend
398 def def32 : PatLeaf<(i32 GR32:$src), [{
399 return N->getOpcode() != ISD::TRUNCATE &&
400 N->getOpcode() != TargetInstrInfo::EXTRACT_SUBREG &&
401 N->getOpcode() != ISD::CopyFromReg &&
402 N->getOpcode() != X86ISD::CMOV;
405 // In the case of a 32-bit def that is known to implicitly zero-extend,
406 // we can use a SUBREG_TO_REG.
407 def : Pat<(i64 (zext def32:$src)),
408 (SUBREG_TO_REG (i64 0), GR32:$src, x86_subreg_32bit)>;
410 let neverHasSideEffects = 1 in {
411 let Defs = [RAX], Uses = [EAX] in
412 def CDQE : RI<0x98, RawFrm, (outs), (ins),
413 "{cltq|cdqe}", []>; // RAX = signext(EAX)
415 let Defs = [RAX,RDX], Uses = [RAX] in
416 def CQO : RI<0x99, RawFrm, (outs), (ins),
417 "{cqto|cqo}", []>; // RDX:RAX = signext(RAX)
420 //===----------------------------------------------------------------------===//
421 // Arithmetic Instructions...
424 let Defs = [EFLAGS] in {
426 def ADD64i32 : RI<0x05, RawFrm, (outs), (ins i32imm:$src),
427 "add{q}\t{$src, %rax|%rax, $src}", []>;
429 let isTwoAddress = 1 in {
430 let isConvertibleToThreeAddress = 1 in {
431 let isCommutable = 1 in
432 // Register-Register Addition
433 def ADD64rr : RI<0x01, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
434 "add{q}\t{$src2, $dst|$dst, $src2}",
435 [(set GR64:$dst, (add GR64:$src1, GR64:$src2)),
438 // Register-Integer Addition
439 def ADD64ri8 : RIi8<0x83, MRM0r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
440 "add{q}\t{$src2, $dst|$dst, $src2}",
441 [(set GR64:$dst, (add GR64:$src1, i64immSExt8:$src2)),
443 def ADD64ri32 : RIi32<0x81, MRM0r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
444 "add{q}\t{$src2, $dst|$dst, $src2}",
445 [(set GR64:$dst, (add GR64:$src1, i64immSExt32:$src2)),
447 } // isConvertibleToThreeAddress
449 // Register-Memory Addition
450 def ADD64rm : RI<0x03, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
451 "add{q}\t{$src2, $dst|$dst, $src2}",
452 [(set GR64:$dst, (add GR64:$src1, (load addr:$src2))),
455 // Register-Register Addition - Equivalent to the normal rr form (ADD64rr), but
456 // differently encoded.
457 def ADD64mrmrr : RI<0x03, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
458 "add{l}\t{$src2, $dst|$dst, $src2}", []>;
462 // Memory-Register Addition
463 def ADD64mr : RI<0x01, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
464 "add{q}\t{$src2, $dst|$dst, $src2}",
465 [(store (add (load addr:$dst), GR64:$src2), addr:$dst),
467 def ADD64mi8 : RIi8<0x83, MRM0m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
468 "add{q}\t{$src2, $dst|$dst, $src2}",
469 [(store (add (load addr:$dst), i64immSExt8:$src2), addr:$dst),
471 def ADD64mi32 : RIi32<0x81, MRM0m, (outs), (ins i64mem:$dst, i64i32imm :$src2),
472 "add{q}\t{$src2, $dst|$dst, $src2}",
473 [(store (add (load addr:$dst), i64immSExt32:$src2), addr:$dst),
476 let Uses = [EFLAGS] in {
478 def ADC64i32 : RI<0x15, RawFrm, (outs), (ins i32imm:$src),
479 "adc{q}\t{$src, %rax|%rax, $src}", []>;
481 let isTwoAddress = 1 in {
482 let isCommutable = 1 in
483 def ADC64rr : RI<0x11, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
484 "adc{q}\t{$src2, $dst|$dst, $src2}",
485 [(set GR64:$dst, (adde GR64:$src1, GR64:$src2))]>;
487 def ADC64rm : RI<0x13, MRMSrcMem , (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
488 "adc{q}\t{$src2, $dst|$dst, $src2}",
489 [(set GR64:$dst, (adde GR64:$src1, (load addr:$src2)))]>;
491 def ADC64ri8 : RIi8<0x83, MRM2r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
492 "adc{q}\t{$src2, $dst|$dst, $src2}",
493 [(set GR64:$dst, (adde GR64:$src1, i64immSExt8:$src2))]>;
494 def ADC64ri32 : RIi32<0x81, MRM2r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
495 "adc{q}\t{$src2, $dst|$dst, $src2}",
496 [(set GR64:$dst, (adde GR64:$src1, i64immSExt32:$src2))]>;
499 def ADC64mr : RI<0x11, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
500 "adc{q}\t{$src2, $dst|$dst, $src2}",
501 [(store (adde (load addr:$dst), GR64:$src2), addr:$dst)]>;
502 def ADC64mi8 : RIi8<0x83, MRM2m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
503 "adc{q}\t{$src2, $dst|$dst, $src2}",
504 [(store (adde (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>;
505 def ADC64mi32 : RIi32<0x81, MRM2m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
506 "adc{q}\t{$src2, $dst|$dst, $src2}",
507 [(store (adde (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>;
510 let isTwoAddress = 1 in {
511 // Register-Register Subtraction
512 def SUB64rr : RI<0x29, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
513 "sub{q}\t{$src2, $dst|$dst, $src2}",
514 [(set GR64:$dst, (sub GR64:$src1, GR64:$src2)),
517 // Register-Memory Subtraction
518 def SUB64rm : RI<0x2B, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
519 "sub{q}\t{$src2, $dst|$dst, $src2}",
520 [(set GR64:$dst, (sub GR64:$src1, (load addr:$src2))),
523 // Register-Integer Subtraction
524 def SUB64ri8 : RIi8<0x83, MRM5r, (outs GR64:$dst),
525 (ins GR64:$src1, i64i8imm:$src2),
526 "sub{q}\t{$src2, $dst|$dst, $src2}",
527 [(set GR64:$dst, (sub GR64:$src1, i64immSExt8:$src2)),
529 def SUB64ri32 : RIi32<0x81, MRM5r, (outs GR64:$dst),
530 (ins GR64:$src1, i64i32imm:$src2),
531 "sub{q}\t{$src2, $dst|$dst, $src2}",
532 [(set GR64:$dst, (sub GR64:$src1, i64immSExt32:$src2)),
536 def SUB64i32 : RI<0x2D, RawFrm, (outs), (ins i32imm:$src),
537 "sub{q}\t{$src, %rax|%rax, $src}", []>;
539 // Memory-Register Subtraction
540 def SUB64mr : RI<0x29, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
541 "sub{q}\t{$src2, $dst|$dst, $src2}",
542 [(store (sub (load addr:$dst), GR64:$src2), addr:$dst),
545 // Memory-Integer Subtraction
546 def SUB64mi8 : RIi8<0x83, MRM5m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
547 "sub{q}\t{$src2, $dst|$dst, $src2}",
548 [(store (sub (load addr:$dst), i64immSExt8:$src2),
551 def SUB64mi32 : RIi32<0x81, MRM5m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
552 "sub{q}\t{$src2, $dst|$dst, $src2}",
553 [(store (sub (load addr:$dst), i64immSExt32:$src2),
557 let Uses = [EFLAGS] in {
558 let isTwoAddress = 1 in {
559 def SBB64rr : RI<0x19, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
560 "sbb{q}\t{$src2, $dst|$dst, $src2}",
561 [(set GR64:$dst, (sube GR64:$src1, GR64:$src2))]>;
563 def SBB64rm : RI<0x1B, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
564 "sbb{q}\t{$src2, $dst|$dst, $src2}",
565 [(set GR64:$dst, (sube GR64:$src1, (load addr:$src2)))]>;
567 def SBB64ri8 : RIi8<0x83, MRM3r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
568 "sbb{q}\t{$src2, $dst|$dst, $src2}",
569 [(set GR64:$dst, (sube GR64:$src1, i64immSExt8:$src2))]>;
570 def SBB64ri32 : RIi32<0x81, MRM3r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
571 "sbb{q}\t{$src2, $dst|$dst, $src2}",
572 [(set GR64:$dst, (sube GR64:$src1, i64immSExt32:$src2))]>;
575 def SBB64i32 : RI<0x1D, RawFrm, (outs), (ins i32imm:$src),
576 "sbb{q}\t{$src, %rax|%rax, $src}", []>;
578 def SBB64mr : RI<0x19, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
579 "sbb{q}\t{$src2, $dst|$dst, $src2}",
580 [(store (sube (load addr:$dst), GR64:$src2), addr:$dst)]>;
581 def SBB64mi8 : RIi8<0x83, MRM3m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
582 "sbb{q}\t{$src2, $dst|$dst, $src2}",
583 [(store (sube (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>;
584 def SBB64mi32 : RIi32<0x81, MRM3m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
585 "sbb{q}\t{$src2, $dst|$dst, $src2}",
586 [(store (sube (load addr:$dst), i64immSExt32:$src2), addr:$dst)]>;
590 // Unsigned multiplication
591 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], neverHasSideEffects = 1 in {
592 def MUL64r : RI<0xF7, MRM4r, (outs), (ins GR64:$src),
593 "mul{q}\t$src", []>; // RAX,RDX = RAX*GR64
595 def MUL64m : RI<0xF7, MRM4m, (outs), (ins i64mem:$src),
596 "mul{q}\t$src", []>; // RAX,RDX = RAX*[mem64]
598 // Signed multiplication
599 def IMUL64r : RI<0xF7, MRM5r, (outs), (ins GR64:$src),
600 "imul{q}\t$src", []>; // RAX,RDX = RAX*GR64
602 def IMUL64m : RI<0xF7, MRM5m, (outs), (ins i64mem:$src),
603 "imul{q}\t$src", []>; // RAX,RDX = RAX*[mem64]
606 let Defs = [EFLAGS] in {
607 let isTwoAddress = 1 in {
608 let isCommutable = 1 in
609 // Register-Register Signed Integer Multiplication
610 def IMUL64rr : RI<0xAF, MRMSrcReg, (outs GR64:$dst),
611 (ins GR64:$src1, GR64:$src2),
612 "imul{q}\t{$src2, $dst|$dst, $src2}",
613 [(set GR64:$dst, (mul GR64:$src1, GR64:$src2)),
614 (implicit EFLAGS)]>, TB;
616 // Register-Memory Signed Integer Multiplication
617 def IMUL64rm : RI<0xAF, MRMSrcMem, (outs GR64:$dst),
618 (ins GR64:$src1, i64mem:$src2),
619 "imul{q}\t{$src2, $dst|$dst, $src2}",
620 [(set GR64:$dst, (mul GR64:$src1, (load addr:$src2))),
621 (implicit EFLAGS)]>, TB;
624 // Suprisingly enough, these are not two address instructions!
626 // Register-Integer Signed Integer Multiplication
627 def IMUL64rri8 : RIi8<0x6B, MRMSrcReg, // GR64 = GR64*I8
628 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
629 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
630 [(set GR64:$dst, (mul GR64:$src1, i64immSExt8:$src2)),
632 def IMUL64rri32 : RIi32<0x69, MRMSrcReg, // GR64 = GR64*I32
633 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
634 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
635 [(set GR64:$dst, (mul GR64:$src1, i64immSExt32:$src2)),
638 // Memory-Integer Signed Integer Multiplication
639 def IMUL64rmi8 : RIi8<0x6B, MRMSrcMem, // GR64 = [mem64]*I8
640 (outs GR64:$dst), (ins i64mem:$src1, i64i8imm: $src2),
641 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
642 [(set GR64:$dst, (mul (load addr:$src1),
645 def IMUL64rmi32 : RIi32<0x69, MRMSrcMem, // GR64 = [mem64]*I32
646 (outs GR64:$dst), (ins i64mem:$src1, i64i32imm:$src2),
647 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
648 [(set GR64:$dst, (mul (load addr:$src1),
649 i64immSExt32:$src2)),
653 // Unsigned division / remainder
654 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in {
655 def DIV64r : RI<0xF7, MRM6r, (outs), (ins GR64:$src), // RDX:RAX/r64 = RAX,RDX
657 // Signed division / remainder
658 def IDIV64r: RI<0xF7, MRM7r, (outs), (ins GR64:$src), // RDX:RAX/r64 = RAX,RDX
659 "idiv{q}\t$src", []>;
661 def DIV64m : RI<0xF7, MRM6m, (outs), (ins i64mem:$src), // RDX:RAX/[mem64] = RAX,RDX
663 def IDIV64m: RI<0xF7, MRM7m, (outs), (ins i64mem:$src), // RDX:RAX/[mem64] = RAX,RDX
664 "idiv{q}\t$src", []>;
668 // Unary instructions
669 let Defs = [EFLAGS], CodeSize = 2 in {
670 let isTwoAddress = 1 in
671 def NEG64r : RI<0xF7, MRM3r, (outs GR64:$dst), (ins GR64:$src), "neg{q}\t$dst",
672 [(set GR64:$dst, (ineg GR64:$src)),
674 def NEG64m : RI<0xF7, MRM3m, (outs), (ins i64mem:$dst), "neg{q}\t$dst",
675 [(store (ineg (loadi64 addr:$dst)), addr:$dst),
678 let isTwoAddress = 1, isConvertibleToThreeAddress = 1 in
679 def INC64r : RI<0xFF, MRM0r, (outs GR64:$dst), (ins GR64:$src), "inc{q}\t$dst",
680 [(set GR64:$dst, (add GR64:$src, 1)),
682 def INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst), "inc{q}\t$dst",
683 [(store (add (loadi64 addr:$dst), 1), addr:$dst),
686 let isTwoAddress = 1, isConvertibleToThreeAddress = 1 in
687 def DEC64r : RI<0xFF, MRM1r, (outs GR64:$dst), (ins GR64:$src), "dec{q}\t$dst",
688 [(set GR64:$dst, (add GR64:$src, -1)),
690 def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst",
691 [(store (add (loadi64 addr:$dst), -1), addr:$dst),
694 // In 64-bit mode, single byte INC and DEC cannot be encoded.
695 let isTwoAddress = 1, isConvertibleToThreeAddress = 1 in {
696 // Can transform into LEA.
697 def INC64_16r : I<0xFF, MRM0r, (outs GR16:$dst), (ins GR16:$src), "inc{w}\t$dst",
698 [(set GR16:$dst, (add GR16:$src, 1)),
700 OpSize, Requires<[In64BitMode]>;
701 def INC64_32r : I<0xFF, MRM0r, (outs GR32:$dst), (ins GR32:$src), "inc{l}\t$dst",
702 [(set GR32:$dst, (add GR32:$src, 1)),
704 Requires<[In64BitMode]>;
705 def DEC64_16r : I<0xFF, MRM1r, (outs GR16:$dst), (ins GR16:$src), "dec{w}\t$dst",
706 [(set GR16:$dst, (add GR16:$src, -1)),
708 OpSize, Requires<[In64BitMode]>;
709 def DEC64_32r : I<0xFF, MRM1r, (outs GR32:$dst), (ins GR32:$src), "dec{l}\t$dst",
710 [(set GR32:$dst, (add GR32:$src, -1)),
712 Requires<[In64BitMode]>;
713 } // isConvertibleToThreeAddress
715 // These are duplicates of their 32-bit counterparts. Only needed so X86 knows
716 // how to unfold them.
717 let isTwoAddress = 0, CodeSize = 2 in {
718 def INC64_16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
719 [(store (add (loadi16 addr:$dst), 1), addr:$dst),
721 OpSize, Requires<[In64BitMode]>;
722 def INC64_32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
723 [(store (add (loadi32 addr:$dst), 1), addr:$dst),
725 Requires<[In64BitMode]>;
726 def DEC64_16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
727 [(store (add (loadi16 addr:$dst), -1), addr:$dst),
729 OpSize, Requires<[In64BitMode]>;
730 def DEC64_32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
731 [(store (add (loadi32 addr:$dst), -1), addr:$dst),
733 Requires<[In64BitMode]>;
735 } // Defs = [EFLAGS], CodeSize
738 let Defs = [EFLAGS] in {
739 // Shift instructions
740 let isTwoAddress = 1 in {
742 def SHL64rCL : RI<0xD3, MRM4r, (outs GR64:$dst), (ins GR64:$src),
743 "shl{q}\t{%cl, $dst|$dst, %CL}",
744 [(set GR64:$dst, (shl GR64:$src, CL))]>;
745 let isConvertibleToThreeAddress = 1 in // Can transform into LEA.
746 def SHL64ri : RIi8<0xC1, MRM4r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
747 "shl{q}\t{$src2, $dst|$dst, $src2}",
748 [(set GR64:$dst, (shl GR64:$src1, (i8 imm:$src2)))]>;
749 // NOTE: We don't include patterns for shifts of a register by one, because
750 // 'add reg,reg' is cheaper.
751 def SHL64r1 : RI<0xD1, MRM4r, (outs GR64:$dst), (ins GR64:$src1),
756 def SHL64mCL : RI<0xD3, MRM4m, (outs), (ins i64mem:$dst),
757 "shl{q}\t{%cl, $dst|$dst, %CL}",
758 [(store (shl (loadi64 addr:$dst), CL), addr:$dst)]>;
759 def SHL64mi : RIi8<0xC1, MRM4m, (outs), (ins i64mem:$dst, i8imm:$src),
760 "shl{q}\t{$src, $dst|$dst, $src}",
761 [(store (shl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
762 def SHL64m1 : RI<0xD1, MRM4m, (outs), (ins i64mem:$dst),
764 [(store (shl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
766 let isTwoAddress = 1 in {
768 def SHR64rCL : RI<0xD3, MRM5r, (outs GR64:$dst), (ins GR64:$src),
769 "shr{q}\t{%cl, $dst|$dst, %CL}",
770 [(set GR64:$dst, (srl GR64:$src, CL))]>;
771 def SHR64ri : RIi8<0xC1, MRM5r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
772 "shr{q}\t{$src2, $dst|$dst, $src2}",
773 [(set GR64:$dst, (srl GR64:$src1, (i8 imm:$src2)))]>;
774 def SHR64r1 : RI<0xD1, MRM5r, (outs GR64:$dst), (ins GR64:$src1),
776 [(set GR64:$dst, (srl GR64:$src1, (i8 1)))]>;
780 def SHR64mCL : RI<0xD3, MRM5m, (outs), (ins i64mem:$dst),
781 "shr{q}\t{%cl, $dst|$dst, %CL}",
782 [(store (srl (loadi64 addr:$dst), CL), addr:$dst)]>;
783 def SHR64mi : RIi8<0xC1, MRM5m, (outs), (ins i64mem:$dst, i8imm:$src),
784 "shr{q}\t{$src, $dst|$dst, $src}",
785 [(store (srl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
786 def SHR64m1 : RI<0xD1, MRM5m, (outs), (ins i64mem:$dst),
788 [(store (srl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
790 let isTwoAddress = 1 in {
792 def SAR64rCL : RI<0xD3, MRM7r, (outs GR64:$dst), (ins GR64:$src),
793 "sar{q}\t{%cl, $dst|$dst, %CL}",
794 [(set GR64:$dst, (sra GR64:$src, CL))]>;
795 def SAR64ri : RIi8<0xC1, MRM7r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
796 "sar{q}\t{$src2, $dst|$dst, $src2}",
797 [(set GR64:$dst, (sra GR64:$src1, (i8 imm:$src2)))]>;
798 def SAR64r1 : RI<0xD1, MRM7r, (outs GR64:$dst), (ins GR64:$src1),
800 [(set GR64:$dst, (sra GR64:$src1, (i8 1)))]>;
804 def SAR64mCL : RI<0xD3, MRM7m, (outs), (ins i64mem:$dst),
805 "sar{q}\t{%cl, $dst|$dst, %CL}",
806 [(store (sra (loadi64 addr:$dst), CL), addr:$dst)]>;
807 def SAR64mi : RIi8<0xC1, MRM7m, (outs), (ins i64mem:$dst, i8imm:$src),
808 "sar{q}\t{$src, $dst|$dst, $src}",
809 [(store (sra (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
810 def SAR64m1 : RI<0xD1, MRM7m, (outs), (ins i64mem:$dst),
812 [(store (sra (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
814 // Rotate instructions
816 let isTwoAddress = 1 in {
817 def RCL64r1 : RI<0xD1, MRM2r, (outs GR64:$dst), (ins GR64:$src),
818 "rcl{q}\t{1, $dst|$dst, 1}", []>;
819 def RCL64m1 : RI<0xD1, MRM2m, (outs i64mem:$dst), (ins i64mem:$src),
820 "rcl{q}\t{1, $dst|$dst, 1}", []>;
822 def RCL64rCL : RI<0xD3, MRM2r, (outs GR64:$dst), (ins GR64:$src),
823 "rcl{q}\t{%cl, $dst|$dst, CL}", []>;
824 def RCL64mCL : RI<0xD3, MRM2m, (outs i64mem:$dst), (ins i64mem:$src),
825 "rcl{q}\t{%cl, $dst|$dst, CL}", []>;
827 def RCL64ri : RIi8<0xC1, MRM2r, (outs GR64:$dst), (ins GR64:$src, i8imm:$cnt),
828 "rcl{q}\t{$cnt, $dst|$dst, $cnt}", []>;
829 def RCL64mi : RIi8<0xC1, MRM2m, (outs i64mem:$dst), (ins i64mem:$src, i8imm:$cnt),
830 "rcl{q}\t{$cnt, $dst|$dst, $cnt}", []>;
832 def RCR64r1 : RI<0xD1, MRM3r, (outs GR64:$dst), (ins GR64:$src),
833 "rcr{q}\t{1, $dst|$dst, 1}", []>;
834 def RCR64m1 : RI<0xD1, MRM3m, (outs i64mem:$dst), (ins i64mem:$src),
835 "rcr{q}\t{1, $dst|$dst, 1}", []>;
837 def RCR64rCL : RI<0xD3, MRM3r, (outs GR64:$dst), (ins GR64:$src),
838 "rcr{q}\t{%cl, $dst|$dst, CL}", []>;
839 def RCR64mCL : RI<0xD3, MRM3m, (outs i64mem:$dst), (ins i64mem:$src),
840 "rcr{q}\t{%cl, $dst|$dst, CL}", []>;
842 def RCR64ri : RIi8<0xC1, MRM3r, (outs GR64:$dst), (ins GR64:$src, i8imm:$cnt),
843 "rcr{q}\t{$cnt, $dst|$dst, $cnt}", []>;
844 def RCR64mi : RIi8<0xC1, MRM3m, (outs i64mem:$dst), (ins i64mem:$src, i8imm:$cnt),
845 "rcr{q}\t{$cnt, $dst|$dst, $cnt}", []>;
848 let isTwoAddress = 1 in {
850 def ROL64rCL : RI<0xD3, MRM0r, (outs GR64:$dst), (ins GR64:$src),
851 "rol{q}\t{%cl, $dst|$dst, %CL}",
852 [(set GR64:$dst, (rotl GR64:$src, CL))]>;
853 def ROL64ri : RIi8<0xC1, MRM0r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
854 "rol{q}\t{$src2, $dst|$dst, $src2}",
855 [(set GR64:$dst, (rotl GR64:$src1, (i8 imm:$src2)))]>;
856 def ROL64r1 : RI<0xD1, MRM0r, (outs GR64:$dst), (ins GR64:$src1),
858 [(set GR64:$dst, (rotl GR64:$src1, (i8 1)))]>;
862 def ROL64mCL : I<0xD3, MRM0m, (outs), (ins i64mem:$dst),
863 "rol{q}\t{%cl, $dst|$dst, %CL}",
864 [(store (rotl (loadi64 addr:$dst), CL), addr:$dst)]>;
865 def ROL64mi : RIi8<0xC1, MRM0m, (outs), (ins i64mem:$dst, i8imm:$src),
866 "rol{q}\t{$src, $dst|$dst, $src}",
867 [(store (rotl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
868 def ROL64m1 : RI<0xD1, MRM0m, (outs), (ins i64mem:$dst),
870 [(store (rotl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
872 let isTwoAddress = 1 in {
874 def ROR64rCL : RI<0xD3, MRM1r, (outs GR64:$dst), (ins GR64:$src),
875 "ror{q}\t{%cl, $dst|$dst, %CL}",
876 [(set GR64:$dst, (rotr GR64:$src, CL))]>;
877 def ROR64ri : RIi8<0xC1, MRM1r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
878 "ror{q}\t{$src2, $dst|$dst, $src2}",
879 [(set GR64:$dst, (rotr GR64:$src1, (i8 imm:$src2)))]>;
880 def ROR64r1 : RI<0xD1, MRM1r, (outs GR64:$dst), (ins GR64:$src1),
882 [(set GR64:$dst, (rotr GR64:$src1, (i8 1)))]>;
886 def ROR64mCL : RI<0xD3, MRM1m, (outs), (ins i64mem:$dst),
887 "ror{q}\t{%cl, $dst|$dst, %CL}",
888 [(store (rotr (loadi64 addr:$dst), CL), addr:$dst)]>;
889 def ROR64mi : RIi8<0xC1, MRM1m, (outs), (ins i64mem:$dst, i8imm:$src),
890 "ror{q}\t{$src, $dst|$dst, $src}",
891 [(store (rotr (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
892 def ROR64m1 : RI<0xD1, MRM1m, (outs), (ins i64mem:$dst),
894 [(store (rotr (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
896 // Double shift instructions (generalizations of rotate)
897 let isTwoAddress = 1 in {
899 def SHLD64rrCL : RI<0xA5, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
900 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
901 [(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2, CL))]>, TB;
902 def SHRD64rrCL : RI<0xAD, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
903 "shrd{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
904 [(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2, CL))]>, TB;
907 let isCommutable = 1 in { // FIXME: Update X86InstrInfo::commuteInstruction
908 def SHLD64rri8 : RIi8<0xA4, MRMDestReg,
909 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2, i8imm:$src3),
910 "shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
911 [(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2,
914 def SHRD64rri8 : RIi8<0xAC, MRMDestReg,
915 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2, i8imm:$src3),
916 "shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
917 [(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2,
924 def SHLD64mrCL : RI<0xA5, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
925 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
926 [(store (X86shld (loadi64 addr:$dst), GR64:$src2, CL),
928 def SHRD64mrCL : RI<0xAD, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
929 "shrd{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
930 [(store (X86shrd (loadi64 addr:$dst), GR64:$src2, CL),
933 def SHLD64mri8 : RIi8<0xA4, MRMDestMem,
934 (outs), (ins i64mem:$dst, GR64:$src2, i8imm:$src3),
935 "shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
936 [(store (X86shld (loadi64 addr:$dst), GR64:$src2,
937 (i8 imm:$src3)), addr:$dst)]>,
939 def SHRD64mri8 : RIi8<0xAC, MRMDestMem,
940 (outs), (ins i64mem:$dst, GR64:$src2, i8imm:$src3),
941 "shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
942 [(store (X86shrd (loadi64 addr:$dst), GR64:$src2,
943 (i8 imm:$src3)), addr:$dst)]>,
947 //===----------------------------------------------------------------------===//
948 // Logical Instructions...
951 let isTwoAddress = 1 , AddedComplexity = 15 in
952 def NOT64r : RI<0xF7, MRM2r, (outs GR64:$dst), (ins GR64:$src), "not{q}\t$dst",
953 [(set GR64:$dst, (not GR64:$src))]>;
954 def NOT64m : RI<0xF7, MRM2m, (outs), (ins i64mem:$dst), "not{q}\t$dst",
955 [(store (not (loadi64 addr:$dst)), addr:$dst)]>;
957 let Defs = [EFLAGS] in {
958 def AND64i32 : RI<0x25, RawFrm, (outs), (ins i32imm:$src),
959 "and{q}\t{$src, %rax|%rax, $src}", []>;
961 let isTwoAddress = 1 in {
962 let isCommutable = 1 in
963 def AND64rr : RI<0x21, MRMDestReg,
964 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
965 "and{q}\t{$src2, $dst|$dst, $src2}",
966 [(set GR64:$dst, (and GR64:$src1, GR64:$src2)),
968 def AND64rm : RI<0x23, MRMSrcMem,
969 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
970 "and{q}\t{$src2, $dst|$dst, $src2}",
971 [(set GR64:$dst, (and GR64:$src1, (load addr:$src2))),
973 def AND64ri8 : RIi8<0x83, MRM4r,
974 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
975 "and{q}\t{$src2, $dst|$dst, $src2}",
976 [(set GR64:$dst, (and GR64:$src1, i64immSExt8:$src2)),
978 def AND64ri32 : RIi32<0x81, MRM4r,
979 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
980 "and{q}\t{$src2, $dst|$dst, $src2}",
981 [(set GR64:$dst, (and GR64:$src1, i64immSExt32:$src2)),
985 def AND64mr : RI<0x21, MRMDestMem,
986 (outs), (ins i64mem:$dst, GR64:$src),
987 "and{q}\t{$src, $dst|$dst, $src}",
988 [(store (and (load addr:$dst), GR64:$src), addr:$dst),
990 def AND64mi8 : RIi8<0x83, MRM4m,
991 (outs), (ins i64mem:$dst, i64i8imm :$src),
992 "and{q}\t{$src, $dst|$dst, $src}",
993 [(store (and (load addr:$dst), i64immSExt8:$src), addr:$dst),
995 def AND64mi32 : RIi32<0x81, MRM4m,
996 (outs), (ins i64mem:$dst, i64i32imm:$src),
997 "and{q}\t{$src, $dst|$dst, $src}",
998 [(store (and (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst),
1001 let isTwoAddress = 1 in {
1002 let isCommutable = 1 in
1003 def OR64rr : RI<0x09, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1004 "or{q}\t{$src2, $dst|$dst, $src2}",
1005 [(set GR64:$dst, (or GR64:$src1, GR64:$src2)),
1006 (implicit EFLAGS)]>;
1007 def OR64rm : RI<0x0B, MRMSrcMem , (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1008 "or{q}\t{$src2, $dst|$dst, $src2}",
1009 [(set GR64:$dst, (or GR64:$src1, (load addr:$src2))),
1010 (implicit EFLAGS)]>;
1011 def OR64ri8 : RIi8<0x83, MRM1r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
1012 "or{q}\t{$src2, $dst|$dst, $src2}",
1013 [(set GR64:$dst, (or GR64:$src1, i64immSExt8:$src2)),
1014 (implicit EFLAGS)]>;
1015 def OR64ri32 : RIi32<0x81, MRM1r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
1016 "or{q}\t{$src2, $dst|$dst, $src2}",
1017 [(set GR64:$dst, (or GR64:$src1, i64immSExt32:$src2)),
1018 (implicit EFLAGS)]>;
1021 def OR64mr : RI<0x09, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1022 "or{q}\t{$src, $dst|$dst, $src}",
1023 [(store (or (load addr:$dst), GR64:$src), addr:$dst),
1024 (implicit EFLAGS)]>;
1025 def OR64mi8 : RIi8<0x83, MRM1m, (outs), (ins i64mem:$dst, i64i8imm:$src),
1026 "or{q}\t{$src, $dst|$dst, $src}",
1027 [(store (or (load addr:$dst), i64immSExt8:$src), addr:$dst),
1028 (implicit EFLAGS)]>;
1029 def OR64mi32 : RIi32<0x81, MRM1m, (outs), (ins i64mem:$dst, i64i32imm:$src),
1030 "or{q}\t{$src, $dst|$dst, $src}",
1031 [(store (or (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst),
1032 (implicit EFLAGS)]>;
1034 def OR64i32 : RIi32<0x0D, RawFrm, (outs), (ins i32imm:$src),
1035 "or{q}\t{$src, %rax|%rax, $src}", []>;
1037 let isTwoAddress = 1 in {
1038 let isCommutable = 1 in
1039 def XOR64rr : RI<0x31, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1040 "xor{q}\t{$src2, $dst|$dst, $src2}",
1041 [(set GR64:$dst, (xor GR64:$src1, GR64:$src2)),
1042 (implicit EFLAGS)]>;
1043 def XOR64rm : RI<0x33, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1044 "xor{q}\t{$src2, $dst|$dst, $src2}",
1045 [(set GR64:$dst, (xor GR64:$src1, (load addr:$src2))),
1046 (implicit EFLAGS)]>;
1047 def XOR64ri8 : RIi8<0x83, MRM6r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
1048 "xor{q}\t{$src2, $dst|$dst, $src2}",
1049 [(set GR64:$dst, (xor GR64:$src1, i64immSExt8:$src2)),
1050 (implicit EFLAGS)]>;
1051 def XOR64ri32 : RIi32<0x81, MRM6r,
1052 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
1053 "xor{q}\t{$src2, $dst|$dst, $src2}",
1054 [(set GR64:$dst, (xor GR64:$src1, i64immSExt32:$src2)),
1055 (implicit EFLAGS)]>;
1058 def XOR64mr : RI<0x31, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1059 "xor{q}\t{$src, $dst|$dst, $src}",
1060 [(store (xor (load addr:$dst), GR64:$src), addr:$dst),
1061 (implicit EFLAGS)]>;
1062 def XOR64mi8 : RIi8<0x83, MRM6m, (outs), (ins i64mem:$dst, i64i8imm :$src),
1063 "xor{q}\t{$src, $dst|$dst, $src}",
1064 [(store (xor (load addr:$dst), i64immSExt8:$src), addr:$dst),
1065 (implicit EFLAGS)]>;
1066 def XOR64mi32 : RIi32<0x81, MRM6m, (outs), (ins i64mem:$dst, i64i32imm:$src),
1067 "xor{q}\t{$src, $dst|$dst, $src}",
1068 [(store (xor (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst),
1069 (implicit EFLAGS)]>;
1071 def XOR64i32 : RIi32<0x35, RawFrm, (outs), (ins i32imm:$src),
1072 "xor{q}\t{$src, %rax|%rax, $src}", []>;
1074 } // Defs = [EFLAGS]
1076 //===----------------------------------------------------------------------===//
1077 // Comparison Instructions...
1080 // Integer comparison
1081 let Defs = [EFLAGS] in {
1082 def TEST64i32 : RI<0xa9, RawFrm, (outs), (ins i32imm:$src),
1083 "test{q}\t{$src, %rax|%rax, $src}", []>;
1084 let isCommutable = 1 in
1085 def TEST64rr : RI<0x85, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1086 "test{q}\t{$src2, $src1|$src1, $src2}",
1087 [(X86cmp (and GR64:$src1, GR64:$src2), 0),
1088 (implicit EFLAGS)]>;
1089 def TEST64rm : RI<0x85, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2),
1090 "test{q}\t{$src2, $src1|$src1, $src2}",
1091 [(X86cmp (and GR64:$src1, (loadi64 addr:$src2)), 0),
1092 (implicit EFLAGS)]>;
1093 def TEST64ri32 : RIi32<0xF7, MRM0r, (outs),
1094 (ins GR64:$src1, i64i32imm:$src2),
1095 "test{q}\t{$src2, $src1|$src1, $src2}",
1096 [(X86cmp (and GR64:$src1, i64immSExt32:$src2), 0),
1097 (implicit EFLAGS)]>;
1098 def TEST64mi32 : RIi32<0xF7, MRM0m, (outs),
1099 (ins i64mem:$src1, i64i32imm:$src2),
1100 "test{q}\t{$src2, $src1|$src1, $src2}",
1101 [(X86cmp (and (loadi64 addr:$src1), i64immSExt32:$src2), 0),
1102 (implicit EFLAGS)]>;
1105 def CMP64i32 : RI<0x3D, RawFrm, (outs), (ins i32imm:$src),
1106 "cmp{q}\t{$src, %rax|%rax, $src}", []>;
1107 def CMP64rr : RI<0x39, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1108 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1109 [(X86cmp GR64:$src1, GR64:$src2),
1110 (implicit EFLAGS)]>;
1111 def CMP64mrmrr : RI<0x3B, MRMSrcReg, (outs), (ins GR64:$src1, GR64:$src2),
1112 "cmp{q}\t{$src2, $src1|$src1, $src2}", []>;
1113 def CMP64mr : RI<0x39, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1114 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1115 [(X86cmp (loadi64 addr:$src1), GR64:$src2),
1116 (implicit EFLAGS)]>;
1117 def CMP64rm : RI<0x3B, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2),
1118 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1119 [(X86cmp GR64:$src1, (loadi64 addr:$src2)),
1120 (implicit EFLAGS)]>;
1121 def CMP64ri8 : RIi8<0x83, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1122 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1123 [(X86cmp GR64:$src1, i64immSExt8:$src2),
1124 (implicit EFLAGS)]>;
1125 def CMP64ri32 : RIi32<0x81, MRM7r, (outs), (ins GR64:$src1, i64i32imm:$src2),
1126 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1127 [(X86cmp GR64:$src1, i64immSExt32:$src2),
1128 (implicit EFLAGS)]>;
1129 def CMP64mi8 : RIi8<0x83, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1130 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1131 [(X86cmp (loadi64 addr:$src1), i64immSExt8:$src2),
1132 (implicit EFLAGS)]>;
1133 def CMP64mi32 : RIi32<0x81, MRM7m, (outs),
1134 (ins i64mem:$src1, i64i32imm:$src2),
1135 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1136 [(X86cmp (loadi64 addr:$src1), i64immSExt32:$src2),
1137 (implicit EFLAGS)]>;
1138 } // Defs = [EFLAGS]
1141 // TODO: BTC, BTR, and BTS
1142 let Defs = [EFLAGS] in {
1143 def BT64rr : RI<0xA3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1144 "bt{q}\t{$src2, $src1|$src1, $src2}",
1145 [(X86bt GR64:$src1, GR64:$src2),
1146 (implicit EFLAGS)]>, TB;
1148 // Unlike with the register+register form, the memory+register form of the
1149 // bt instruction does not ignore the high bits of the index. From ISel's
1150 // perspective, this is pretty bizarre. Disable these instructions for now.
1151 //def BT64mr : RI<0xA3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1152 // "bt{q}\t{$src2, $src1|$src1, $src2}",
1153 // [(X86bt (loadi64 addr:$src1), GR64:$src2),
1154 // (implicit EFLAGS)]>, TB;
1156 def BT64ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1157 "bt{q}\t{$src2, $src1|$src1, $src2}",
1158 [(X86bt GR64:$src1, i64immSExt8:$src2),
1159 (implicit EFLAGS)]>, TB;
1160 // Note that these instructions don't need FastBTMem because that
1161 // only applies when the other operand is in a register. When it's
1162 // an immediate, bt is still fast.
1163 def BT64mi8 : Ii8<0xBA, MRM4m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1164 "bt{q}\t{$src2, $src1|$src1, $src2}",
1165 [(X86bt (loadi64 addr:$src1), i64immSExt8:$src2),
1166 (implicit EFLAGS)]>, TB;
1167 } // Defs = [EFLAGS]
1169 // Conditional moves
1170 let Uses = [EFLAGS], isTwoAddress = 1 in {
1171 let isCommutable = 1 in {
1172 def CMOVB64rr : RI<0x42, MRMSrcReg, // if <u, GR64 = GR64
1173 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1174 "cmovb\t{$src2, $dst|$dst, $src2}",
1175 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1176 X86_COND_B, EFLAGS))]>, TB;
1177 def CMOVAE64rr: RI<0x43, MRMSrcReg, // if >=u, GR64 = GR64
1178 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1179 "cmovae\t{$src2, $dst|$dst, $src2}",
1180 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1181 X86_COND_AE, EFLAGS))]>, TB;
1182 def CMOVE64rr : RI<0x44, MRMSrcReg, // if ==, GR64 = GR64
1183 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1184 "cmove\t{$src2, $dst|$dst, $src2}",
1185 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1186 X86_COND_E, EFLAGS))]>, TB;
1187 def CMOVNE64rr: RI<0x45, MRMSrcReg, // if !=, GR64 = GR64
1188 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1189 "cmovne\t{$src2, $dst|$dst, $src2}",
1190 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1191 X86_COND_NE, EFLAGS))]>, TB;
1192 def CMOVBE64rr: RI<0x46, MRMSrcReg, // if <=u, GR64 = GR64
1193 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1194 "cmovbe\t{$src2, $dst|$dst, $src2}",
1195 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1196 X86_COND_BE, EFLAGS))]>, TB;
1197 def CMOVA64rr : RI<0x47, MRMSrcReg, // if >u, GR64 = GR64
1198 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1199 "cmova\t{$src2, $dst|$dst, $src2}",
1200 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1201 X86_COND_A, EFLAGS))]>, TB;
1202 def CMOVL64rr : RI<0x4C, MRMSrcReg, // if <s, GR64 = GR64
1203 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1204 "cmovl\t{$src2, $dst|$dst, $src2}",
1205 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1206 X86_COND_L, EFLAGS))]>, TB;
1207 def CMOVGE64rr: RI<0x4D, MRMSrcReg, // if >=s, GR64 = GR64
1208 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1209 "cmovge\t{$src2, $dst|$dst, $src2}",
1210 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1211 X86_COND_GE, EFLAGS))]>, TB;
1212 def CMOVLE64rr: RI<0x4E, MRMSrcReg, // if <=s, GR64 = GR64
1213 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1214 "cmovle\t{$src2, $dst|$dst, $src2}",
1215 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1216 X86_COND_LE, EFLAGS))]>, TB;
1217 def CMOVG64rr : RI<0x4F, MRMSrcReg, // if >s, GR64 = GR64
1218 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1219 "cmovg\t{$src2, $dst|$dst, $src2}",
1220 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1221 X86_COND_G, EFLAGS))]>, TB;
1222 def CMOVS64rr : RI<0x48, MRMSrcReg, // if signed, GR64 = GR64
1223 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1224 "cmovs\t{$src2, $dst|$dst, $src2}",
1225 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1226 X86_COND_S, EFLAGS))]>, TB;
1227 def CMOVNS64rr: RI<0x49, MRMSrcReg, // if !signed, GR64 = GR64
1228 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1229 "cmovns\t{$src2, $dst|$dst, $src2}",
1230 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1231 X86_COND_NS, EFLAGS))]>, TB;
1232 def CMOVP64rr : RI<0x4A, MRMSrcReg, // if parity, GR64 = GR64
1233 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1234 "cmovp\t{$src2, $dst|$dst, $src2}",
1235 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1236 X86_COND_P, EFLAGS))]>, TB;
1237 def CMOVNP64rr : RI<0x4B, MRMSrcReg, // if !parity, GR64 = GR64
1238 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1239 "cmovnp\t{$src2, $dst|$dst, $src2}",
1240 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1241 X86_COND_NP, EFLAGS))]>, TB;
1242 def CMOVO64rr : RI<0x40, MRMSrcReg, // if overflow, GR64 = GR64
1243 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1244 "cmovo\t{$src2, $dst|$dst, $src2}",
1245 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1246 X86_COND_O, EFLAGS))]>, TB;
1247 def CMOVNO64rr : RI<0x41, MRMSrcReg, // if !overflow, GR64 = GR64
1248 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1249 "cmovno\t{$src2, $dst|$dst, $src2}",
1250 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1251 X86_COND_NO, EFLAGS))]>, TB;
1252 } // isCommutable = 1
1254 def CMOVB64rm : RI<0x42, MRMSrcMem, // if <u, GR64 = [mem64]
1255 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1256 "cmovb\t{$src2, $dst|$dst, $src2}",
1257 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1258 X86_COND_B, EFLAGS))]>, TB;
1259 def CMOVAE64rm: RI<0x43, MRMSrcMem, // if >=u, GR64 = [mem64]
1260 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1261 "cmovae\t{$src2, $dst|$dst, $src2}",
1262 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1263 X86_COND_AE, EFLAGS))]>, TB;
1264 def CMOVE64rm : RI<0x44, MRMSrcMem, // if ==, GR64 = [mem64]
1265 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1266 "cmove\t{$src2, $dst|$dst, $src2}",
1267 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1268 X86_COND_E, EFLAGS))]>, TB;
1269 def CMOVNE64rm: RI<0x45, MRMSrcMem, // if !=, GR64 = [mem64]
1270 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1271 "cmovne\t{$src2, $dst|$dst, $src2}",
1272 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1273 X86_COND_NE, EFLAGS))]>, TB;
1274 def CMOVBE64rm: RI<0x46, MRMSrcMem, // if <=u, GR64 = [mem64]
1275 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1276 "cmovbe\t{$src2, $dst|$dst, $src2}",
1277 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1278 X86_COND_BE, EFLAGS))]>, TB;
1279 def CMOVA64rm : RI<0x47, MRMSrcMem, // if >u, GR64 = [mem64]
1280 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1281 "cmova\t{$src2, $dst|$dst, $src2}",
1282 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1283 X86_COND_A, EFLAGS))]>, TB;
1284 def CMOVL64rm : RI<0x4C, MRMSrcMem, // if <s, GR64 = [mem64]
1285 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1286 "cmovl\t{$src2, $dst|$dst, $src2}",
1287 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1288 X86_COND_L, EFLAGS))]>, TB;
1289 def CMOVGE64rm: RI<0x4D, MRMSrcMem, // if >=s, GR64 = [mem64]
1290 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1291 "cmovge\t{$src2, $dst|$dst, $src2}",
1292 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1293 X86_COND_GE, EFLAGS))]>, TB;
1294 def CMOVLE64rm: RI<0x4E, MRMSrcMem, // if <=s, GR64 = [mem64]
1295 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1296 "cmovle\t{$src2, $dst|$dst, $src2}",
1297 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1298 X86_COND_LE, EFLAGS))]>, TB;
1299 def CMOVG64rm : RI<0x4F, MRMSrcMem, // if >s, GR64 = [mem64]
1300 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1301 "cmovg\t{$src2, $dst|$dst, $src2}",
1302 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1303 X86_COND_G, EFLAGS))]>, TB;
1304 def CMOVS64rm : RI<0x48, MRMSrcMem, // if signed, GR64 = [mem64]
1305 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1306 "cmovs\t{$src2, $dst|$dst, $src2}",
1307 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1308 X86_COND_S, EFLAGS))]>, TB;
1309 def CMOVNS64rm: RI<0x49, MRMSrcMem, // if !signed, GR64 = [mem64]
1310 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1311 "cmovns\t{$src2, $dst|$dst, $src2}",
1312 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1313 X86_COND_NS, EFLAGS))]>, TB;
1314 def CMOVP64rm : RI<0x4A, MRMSrcMem, // if parity, GR64 = [mem64]
1315 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1316 "cmovp\t{$src2, $dst|$dst, $src2}",
1317 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1318 X86_COND_P, EFLAGS))]>, TB;
1319 def CMOVNP64rm : RI<0x4B, MRMSrcMem, // if !parity, GR64 = [mem64]
1320 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1321 "cmovnp\t{$src2, $dst|$dst, $src2}",
1322 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1323 X86_COND_NP, EFLAGS))]>, TB;
1324 def CMOVO64rm : RI<0x40, MRMSrcMem, // if overflow, GR64 = [mem64]
1325 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1326 "cmovo\t{$src2, $dst|$dst, $src2}",
1327 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1328 X86_COND_O, EFLAGS))]>, TB;
1329 def CMOVNO64rm : RI<0x41, MRMSrcMem, // if !overflow, GR64 = [mem64]
1330 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1331 "cmovno\t{$src2, $dst|$dst, $src2}",
1332 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1333 X86_COND_NO, EFLAGS))]>, TB;
1336 // Use sbb to materialize carry flag into a GPR.
1337 let Defs = [EFLAGS], Uses = [EFLAGS], isCodeGenOnly = 1 in
1338 def SETB_C64r : RI<0x19, MRMInitReg, (outs GR64:$dst), (ins),
1339 "sbb{q}\t$dst, $dst",
1340 [(set GR64:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
1342 def : Pat<(i64 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
1345 //===----------------------------------------------------------------------===//
1346 // Conversion Instructions...
1349 // f64 -> signed i64
1350 def Int_CVTSD2SI64rr: RSDI<0x2D, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1351 "cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1353 (int_x86_sse2_cvtsd2si64 VR128:$src))]>;
1354 def Int_CVTSD2SI64rm: RSDI<0x2D, MRMSrcMem, (outs GR64:$dst), (ins f128mem:$src),
1355 "cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1356 [(set GR64:$dst, (int_x86_sse2_cvtsd2si64
1357 (load addr:$src)))]>;
1358 def CVTTSD2SI64rr: RSDI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins FR64:$src),
1359 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1360 [(set GR64:$dst, (fp_to_sint FR64:$src))]>;
1361 def CVTTSD2SI64rm: RSDI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f64mem:$src),
1362 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1363 [(set GR64:$dst, (fp_to_sint (loadf64 addr:$src)))]>;
1364 def Int_CVTTSD2SI64rr: RSDI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1365 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1367 (int_x86_sse2_cvttsd2si64 VR128:$src))]>;
1368 def Int_CVTTSD2SI64rm: RSDI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f128mem:$src),
1369 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1371 (int_x86_sse2_cvttsd2si64
1372 (load addr:$src)))]>;
1374 // Signed i64 -> f64
1375 def CVTSI2SD64rr: RSDI<0x2A, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
1376 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
1377 [(set FR64:$dst, (sint_to_fp GR64:$src))]>;
1378 def CVTSI2SD64rm: RSDI<0x2A, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
1379 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
1380 [(set FR64:$dst, (sint_to_fp (loadi64 addr:$src)))]>;
1382 let isTwoAddress = 1 in {
1383 def Int_CVTSI2SD64rr: RSDI<0x2A, MRMSrcReg,
1384 (outs VR128:$dst), (ins VR128:$src1, GR64:$src2),
1385 "cvtsi2sd{q}\t{$src2, $dst|$dst, $src2}",
1387 (int_x86_sse2_cvtsi642sd VR128:$src1,
1389 def Int_CVTSI2SD64rm: RSDI<0x2A, MRMSrcMem,
1390 (outs VR128:$dst), (ins VR128:$src1, i64mem:$src2),
1391 "cvtsi2sd{q}\t{$src2, $dst|$dst, $src2}",
1393 (int_x86_sse2_cvtsi642sd VR128:$src1,
1394 (loadi64 addr:$src2)))]>;
1397 // Signed i64 -> f32
1398 def CVTSI2SS64rr: RSSI<0x2A, MRMSrcReg, (outs FR32:$dst), (ins GR64:$src),
1399 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
1400 [(set FR32:$dst, (sint_to_fp GR64:$src))]>;
1401 def CVTSI2SS64rm: RSSI<0x2A, MRMSrcMem, (outs FR32:$dst), (ins i64mem:$src),
1402 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
1403 [(set FR32:$dst, (sint_to_fp (loadi64 addr:$src)))]>;
1405 let isTwoAddress = 1 in {
1406 def Int_CVTSI2SS64rr : RSSI<0x2A, MRMSrcReg,
1407 (outs VR128:$dst), (ins VR128:$src1, GR64:$src2),
1408 "cvtsi2ss{q}\t{$src2, $dst|$dst, $src2}",
1410 (int_x86_sse_cvtsi642ss VR128:$src1,
1412 def Int_CVTSI2SS64rm : RSSI<0x2A, MRMSrcMem,
1413 (outs VR128:$dst), (ins VR128:$src1, i64mem:$src2),
1414 "cvtsi2ss{q}\t{$src2, $dst|$dst, $src2}",
1416 (int_x86_sse_cvtsi642ss VR128:$src1,
1417 (loadi64 addr:$src2)))]>;
1420 // f32 -> signed i64
1421 def Int_CVTSS2SI64rr: RSSI<0x2D, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1422 "cvtss2si{q}\t{$src, $dst|$dst, $src}",
1424 (int_x86_sse_cvtss2si64 VR128:$src))]>;
1425 def Int_CVTSS2SI64rm: RSSI<0x2D, MRMSrcMem, (outs GR64:$dst), (ins f32mem:$src),
1426 "cvtss2si{q}\t{$src, $dst|$dst, $src}",
1427 [(set GR64:$dst, (int_x86_sse_cvtss2si64
1428 (load addr:$src)))]>;
1429 def CVTTSS2SI64rr: RSSI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins FR32:$src),
1430 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1431 [(set GR64:$dst, (fp_to_sint FR32:$src))]>;
1432 def CVTTSS2SI64rm: RSSI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f32mem:$src),
1433 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1434 [(set GR64:$dst, (fp_to_sint (loadf32 addr:$src)))]>;
1435 def Int_CVTTSS2SI64rr: RSSI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1436 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1438 (int_x86_sse_cvttss2si64 VR128:$src))]>;
1439 def Int_CVTTSS2SI64rm: RSSI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f32mem:$src),
1440 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1442 (int_x86_sse_cvttss2si64 (load addr:$src)))]>;
1444 //===----------------------------------------------------------------------===//
1445 // Alias Instructions
1446 //===----------------------------------------------------------------------===//
1448 // Alias instructions that map movr0 to xor. Use xorl instead of xorq; it's
1449 // equivalent due to implicit zero-extending, and it sometimes has a smaller
1451 // FIXME: AddedComplexity gives this a higher priority than MOV64ri32. Remove
1452 // when we have a better way to specify isel priority.
1453 let AddedComplexity = 1 in
1455 (SUBREG_TO_REG (i64 0), (MOV32r0), x86_subreg_32bit)>;
1458 // Materialize i64 constant where top 32-bits are zero.
1459 let AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1 in
1460 def MOV64ri64i32 : Ii32<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64i32imm:$src),
1461 "", [(set GR64:$dst, i64immZExt32:$src)]>;
1463 //===----------------------------------------------------------------------===//
1464 // Thread Local Storage Instructions
1465 //===----------------------------------------------------------------------===//
1467 // All calls clobber the non-callee saved registers. RSP is marked as
1468 // a use to prevent stack-pointer assignments that appear immediately
1469 // before calls from potentially appearing dead.
1470 let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
1471 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
1472 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
1473 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
1474 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
1476 def TLS_addr64 : I<0, Pseudo, (outs), (ins lea64mem:$sym),
1478 "leaq\t$sym(%rip), %rdi; "
1481 "call\t__tls_get_addr@PLT",
1482 [(X86tlsaddr tls64addr:$sym)]>,
1483 Requires<[In64BitMode]>;
1485 let AddedComplexity = 5, isCodeGenOnly = 1 in
1486 def MOV64GSrm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1487 "movq\t%gs:$src, $dst",
1488 [(set GR64:$dst, (gsload addr:$src))]>, SegGS;
1490 let AddedComplexity = 5, isCodeGenOnly = 1 in
1491 def MOV64FSrm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1492 "movq\t%fs:$src, $dst",
1493 [(set GR64:$dst, (fsload addr:$src))]>, SegFS;
1495 //===----------------------------------------------------------------------===//
1496 // Atomic Instructions
1497 //===----------------------------------------------------------------------===//
1499 let Defs = [RAX, EFLAGS], Uses = [RAX] in {
1500 def LCMPXCHG64 : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$ptr, GR64:$swap),
1502 "cmpxchgq\t$swap,$ptr",
1503 [(X86cas addr:$ptr, GR64:$swap, 8)]>, TB, LOCK;
1506 let Constraints = "$val = $dst" in {
1507 let Defs = [EFLAGS] in
1508 def LXADD64 : RI<0xC1, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$ptr,GR64:$val),
1511 [(set GR64:$dst, (atomic_load_add_64 addr:$ptr, GR64:$val))]>,
1514 def XCHG64rm : RI<0x87, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$ptr,GR64:$val),
1516 [(set GR64:$dst, (atomic_swap_64 addr:$ptr, GR64:$val))]>;
1519 // Optimized codegen when the non-memory output is not used.
1520 let Defs = [EFLAGS] in {
1521 // FIXME: Use normal add / sub instructions and add lock prefix dynamically.
1522 def LOCK_ADD64mr : RI<0x03, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
1524 "add{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1525 def LOCK_ADD64mi8 : RIi8<0x83, MRM0m, (outs),
1526 (ins i64mem:$dst, i64i8imm :$src2),
1528 "add{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1529 def LOCK_ADD64mi32 : RIi32<0x81, MRM0m, (outs),
1530 (ins i64mem:$dst, i64i32imm :$src2),
1532 "add{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1533 def LOCK_SUB64mr : RI<0x29, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
1535 "sub{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1536 def LOCK_SUB64mi8 : RIi8<0x83, MRM5m, (outs),
1537 (ins i64mem:$dst, i64i8imm :$src2),
1539 "sub{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1540 def LOCK_SUB64mi32 : RIi32<0x81, MRM5m, (outs),
1541 (ins i64mem:$dst, i64i32imm:$src2),
1543 "sub{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1544 def LOCK_INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst),
1546 "inc{q}\t$dst", []>, LOCK;
1547 def LOCK_DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst),
1549 "dec{q}\t$dst", []>, LOCK;
1551 // Atomic exchange, and, or, xor
1552 let Constraints = "$val = $dst", Defs = [EFLAGS],
1553 usesCustomInserter = 1 in {
1554 def ATOMAND64 : I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1555 "#ATOMAND64 PSEUDO!",
1556 [(set GR64:$dst, (atomic_load_and_64 addr:$ptr, GR64:$val))]>;
1557 def ATOMOR64 : I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1558 "#ATOMOR64 PSEUDO!",
1559 [(set GR64:$dst, (atomic_load_or_64 addr:$ptr, GR64:$val))]>;
1560 def ATOMXOR64 : I<0, Pseudo,(outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1561 "#ATOMXOR64 PSEUDO!",
1562 [(set GR64:$dst, (atomic_load_xor_64 addr:$ptr, GR64:$val))]>;
1563 def ATOMNAND64 : I<0, Pseudo,(outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1564 "#ATOMNAND64 PSEUDO!",
1565 [(set GR64:$dst, (atomic_load_nand_64 addr:$ptr, GR64:$val))]>;
1566 def ATOMMIN64: I<0, Pseudo, (outs GR64:$dst), (ins i64mem:$ptr, GR64:$val),
1567 "#ATOMMIN64 PSEUDO!",
1568 [(set GR64:$dst, (atomic_load_min_64 addr:$ptr, GR64:$val))]>;
1569 def ATOMMAX64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1570 "#ATOMMAX64 PSEUDO!",
1571 [(set GR64:$dst, (atomic_load_max_64 addr:$ptr, GR64:$val))]>;
1572 def ATOMUMIN64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1573 "#ATOMUMIN64 PSEUDO!",
1574 [(set GR64:$dst, (atomic_load_umin_64 addr:$ptr, GR64:$val))]>;
1575 def ATOMUMAX64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1576 "#ATOMUMAX64 PSEUDO!",
1577 [(set GR64:$dst, (atomic_load_umax_64 addr:$ptr, GR64:$val))]>;
1580 // Segmentation support instructions
1582 // i16mem operand in LAR64rm and GR32 operand in LAR32rr is not a typo.
1583 def LAR64rm : RI<0x02, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
1584 "lar{q}\t{$src, $dst|$dst, $src}", []>, TB;
1585 def LAR64rr : RI<0x02, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src),
1586 "lar{q}\t{$src, $dst|$dst, $src}", []>, TB;
1588 // String manipulation instructions
1590 def LODSQ : RI<0xAD, RawFrm, (outs), (ins), "lodsq", []>;
1592 //===----------------------------------------------------------------------===//
1593 // Non-Instruction Patterns
1594 //===----------------------------------------------------------------------===//
1596 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable when not in small
1597 // code model mode, should use 'movabs'. FIXME: This is really a hack, the
1598 // 'movabs' predicate should handle this sort of thing.
1599 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
1600 (MOV64ri tconstpool :$dst)>, Requires<[FarData]>;
1601 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
1602 (MOV64ri tjumptable :$dst)>, Requires<[FarData]>;
1603 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
1604 (MOV64ri tglobaladdr :$dst)>, Requires<[FarData]>;
1605 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
1606 (MOV64ri texternalsym:$dst)>, Requires<[FarData]>;
1607 def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
1608 (MOV64ri tblockaddress:$dst)>, Requires<[FarData]>;
1610 // In static codegen with small code model, we can get the address of a label
1611 // into a register with 'movl'. FIXME: This is a hack, the 'imm' predicate of
1612 // the MOV64ri64i32 should accept these.
1613 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
1614 (MOV64ri64i32 tconstpool :$dst)>, Requires<[SmallCode]>;
1615 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
1616 (MOV64ri64i32 tjumptable :$dst)>, Requires<[SmallCode]>;
1617 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
1618 (MOV64ri64i32 tglobaladdr :$dst)>, Requires<[SmallCode]>;
1619 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
1620 (MOV64ri64i32 texternalsym:$dst)>, Requires<[SmallCode]>;
1621 def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
1622 (MOV64ri64i32 tblockaddress:$dst)>, Requires<[SmallCode]>;
1624 // In kernel code model, we can get the address of a label
1625 // into a register with 'movq'. FIXME: This is a hack, the 'imm' predicate of
1626 // the MOV64ri32 should accept these.
1627 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
1628 (MOV64ri32 tconstpool :$dst)>, Requires<[KernelCode]>;
1629 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
1630 (MOV64ri32 tjumptable :$dst)>, Requires<[KernelCode]>;
1631 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
1632 (MOV64ri32 tglobaladdr :$dst)>, Requires<[KernelCode]>;
1633 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
1634 (MOV64ri32 texternalsym:$dst)>, Requires<[KernelCode]>;
1635 def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
1636 (MOV64ri32 tblockaddress:$dst)>, Requires<[KernelCode]>;
1638 // If we have small model and -static mode, it is safe to store global addresses
1639 // directly as immediates. FIXME: This is really a hack, the 'imm' predicate
1640 // for MOV64mi32 should handle this sort of thing.
1641 def : Pat<(store (i64 (X86Wrapper tconstpool:$src)), addr:$dst),
1642 (MOV64mi32 addr:$dst, tconstpool:$src)>,
1643 Requires<[NearData, IsStatic]>;
1644 def : Pat<(store (i64 (X86Wrapper tjumptable:$src)), addr:$dst),
1645 (MOV64mi32 addr:$dst, tjumptable:$src)>,
1646 Requires<[NearData, IsStatic]>;
1647 def : Pat<(store (i64 (X86Wrapper tglobaladdr:$src)), addr:$dst),
1648 (MOV64mi32 addr:$dst, tglobaladdr:$src)>,
1649 Requires<[NearData, IsStatic]>;
1650 def : Pat<(store (i64 (X86Wrapper texternalsym:$src)), addr:$dst),
1651 (MOV64mi32 addr:$dst, texternalsym:$src)>,
1652 Requires<[NearData, IsStatic]>;
1653 def : Pat<(store (i64 (X86Wrapper tblockaddress:$src)), addr:$dst),
1654 (MOV64mi32 addr:$dst, tblockaddress:$src)>,
1655 Requires<[NearData, IsStatic]>;
1658 // Direct PC relative function call for small code model. 32-bit displacement
1659 // sign extended to 64-bit.
1660 def : Pat<(X86call (i64 tglobaladdr:$dst)),
1661 (CALL64pcrel32 tglobaladdr:$dst)>, Requires<[NotWin64]>;
1662 def : Pat<(X86call (i64 texternalsym:$dst)),
1663 (CALL64pcrel32 texternalsym:$dst)>, Requires<[NotWin64]>;
1665 def : Pat<(X86call (i64 tglobaladdr:$dst)),
1666 (WINCALL64pcrel32 tglobaladdr:$dst)>, Requires<[IsWin64]>;
1667 def : Pat<(X86call (i64 texternalsym:$dst)),
1668 (WINCALL64pcrel32 texternalsym:$dst)>, Requires<[IsWin64]>;
1671 def : Pat<(X86tcret GR64:$dst, imm:$off),
1672 (TCRETURNri64 GR64:$dst, imm:$off)>;
1674 def : Pat<(X86tcret (i64 tglobaladdr:$dst), imm:$off),
1675 (TCRETURNdi64 tglobaladdr:$dst, imm:$off)>;
1677 def : Pat<(X86tcret (i64 texternalsym:$dst), imm:$off),
1678 (TCRETURNdi64 texternalsym:$dst, imm:$off)>;
1682 // TEST R,R is smaller than CMP R,0
1683 def : Pat<(parallel (X86cmp GR64:$src1, 0), (implicit EFLAGS)),
1684 (TEST64rr GR64:$src1, GR64:$src1)>;
1686 // Conditional moves with folded loads with operands swapped and conditions
1688 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_B, EFLAGS),
1689 (CMOVAE64rm GR64:$src2, addr:$src1)>;
1690 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_AE, EFLAGS),
1691 (CMOVB64rm GR64:$src2, addr:$src1)>;
1692 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_E, EFLAGS),
1693 (CMOVNE64rm GR64:$src2, addr:$src1)>;
1694 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NE, EFLAGS),
1695 (CMOVE64rm GR64:$src2, addr:$src1)>;
1696 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_BE, EFLAGS),
1697 (CMOVA64rm GR64:$src2, addr:$src1)>;
1698 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_A, EFLAGS),
1699 (CMOVBE64rm GR64:$src2, addr:$src1)>;
1700 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_L, EFLAGS),
1701 (CMOVGE64rm GR64:$src2, addr:$src1)>;
1702 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_GE, EFLAGS),
1703 (CMOVL64rm GR64:$src2, addr:$src1)>;
1704 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_LE, EFLAGS),
1705 (CMOVG64rm GR64:$src2, addr:$src1)>;
1706 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_G, EFLAGS),
1707 (CMOVLE64rm GR64:$src2, addr:$src1)>;
1708 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_P, EFLAGS),
1709 (CMOVNP64rm GR64:$src2, addr:$src1)>;
1710 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NP, EFLAGS),
1711 (CMOVP64rm GR64:$src2, addr:$src1)>;
1712 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_S, EFLAGS),
1713 (CMOVNS64rm GR64:$src2, addr:$src1)>;
1714 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NS, EFLAGS),
1715 (CMOVS64rm GR64:$src2, addr:$src1)>;
1716 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_O, EFLAGS),
1717 (CMOVNO64rm GR64:$src2, addr:$src1)>;
1718 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NO, EFLAGS),
1719 (CMOVO64rm GR64:$src2, addr:$src1)>;
1721 // zextload bool -> zextload byte
1722 def : Pat<(zextloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>;
1725 // When extloading from 16-bit and smaller memory locations into 64-bit registers,
1726 // use zero-extending loads so that the entire 64-bit register is defined, avoiding
1727 // partial-register updates.
1728 def : Pat<(extloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>;
1729 def : Pat<(extloadi64i8 addr:$src), (MOVZX64rm8 addr:$src)>;
1730 def : Pat<(extloadi64i16 addr:$src), (MOVZX64rm16 addr:$src)>;
1731 // For other extloads, use subregs, since the high contents of the register are
1732 // defined after an extload.
1733 def : Pat<(extloadi64i32 addr:$src),
1734 (SUBREG_TO_REG (i64 0), (MOV32rm addr:$src),
1737 // anyext. Define these to do an explicit zero-extend to
1738 // avoid partial-register updates.
1739 def : Pat<(i64 (anyext GR8 :$src)), (MOVZX64rr8 GR8 :$src)>;
1740 def : Pat<(i64 (anyext GR16:$src)), (MOVZX64rr16 GR16 :$src)>;
1741 def : Pat<(i64 (anyext GR32:$src)),
1742 (SUBREG_TO_REG (i64 0), GR32:$src, x86_subreg_32bit)>;
1744 //===----------------------------------------------------------------------===//
1746 //===----------------------------------------------------------------------===//
1748 // Odd encoding trick: -128 fits into an 8-bit immediate field while
1749 // +128 doesn't, so in this special case use a sub instead of an add.
1750 def : Pat<(add GR64:$src1, 128),
1751 (SUB64ri8 GR64:$src1, -128)>;
1752 def : Pat<(store (add (loadi64 addr:$dst), 128), addr:$dst),
1753 (SUB64mi8 addr:$dst, -128)>;
1755 // The same trick applies for 32-bit immediate fields in 64-bit
1757 def : Pat<(add GR64:$src1, 0x0000000080000000),
1758 (SUB64ri32 GR64:$src1, 0xffffffff80000000)>;
1759 def : Pat<(store (add (loadi64 addr:$dst), 0x00000000800000000), addr:$dst),
1760 (SUB64mi32 addr:$dst, 0xffffffff80000000)>;
1762 // r & (2^32-1) ==> movz
1763 def : Pat<(and GR64:$src, 0x00000000FFFFFFFF),
1764 (MOVZX64rr32 (EXTRACT_SUBREG GR64:$src, x86_subreg_32bit))>;
1765 // r & (2^16-1) ==> movz
1766 def : Pat<(and GR64:$src, 0xffff),
1767 (MOVZX64rr16 (i16 (EXTRACT_SUBREG GR64:$src, x86_subreg_16bit)))>;
1768 // r & (2^8-1) ==> movz
1769 def : Pat<(and GR64:$src, 0xff),
1770 (MOVZX64rr8 (i8 (EXTRACT_SUBREG GR64:$src, x86_subreg_8bit)))>;
1771 // r & (2^8-1) ==> movz
1772 def : Pat<(and GR32:$src1, 0xff),
1773 (MOVZX32rr8 (EXTRACT_SUBREG GR32:$src1, x86_subreg_8bit))>,
1774 Requires<[In64BitMode]>;
1775 // r & (2^8-1) ==> movz
1776 def : Pat<(and GR16:$src1, 0xff),
1777 (MOVZX16rr8 (i8 (EXTRACT_SUBREG GR16:$src1, x86_subreg_8bit)))>,
1778 Requires<[In64BitMode]>;
1780 // sext_inreg patterns
1781 def : Pat<(sext_inreg GR64:$src, i32),
1782 (MOVSX64rr32 (EXTRACT_SUBREG GR64:$src, x86_subreg_32bit))>;
1783 def : Pat<(sext_inreg GR64:$src, i16),
1784 (MOVSX64rr16 (EXTRACT_SUBREG GR64:$src, x86_subreg_16bit))>;
1785 def : Pat<(sext_inreg GR64:$src, i8),
1786 (MOVSX64rr8 (EXTRACT_SUBREG GR64:$src, x86_subreg_8bit))>;
1787 def : Pat<(sext_inreg GR32:$src, i8),
1788 (MOVSX32rr8 (EXTRACT_SUBREG GR32:$src, x86_subreg_8bit))>,
1789 Requires<[In64BitMode]>;
1790 def : Pat<(sext_inreg GR16:$src, i8),
1791 (MOVSX16rr8 (i8 (EXTRACT_SUBREG GR16:$src, x86_subreg_8bit)))>,
1792 Requires<[In64BitMode]>;
1795 def : Pat<(i32 (trunc GR64:$src)),
1796 (EXTRACT_SUBREG GR64:$src, x86_subreg_32bit)>;
1797 def : Pat<(i16 (trunc GR64:$src)),
1798 (EXTRACT_SUBREG GR64:$src, x86_subreg_16bit)>;
1799 def : Pat<(i8 (trunc GR64:$src)),
1800 (EXTRACT_SUBREG GR64:$src, x86_subreg_8bit)>;
1801 def : Pat<(i8 (trunc GR32:$src)),
1802 (EXTRACT_SUBREG GR32:$src, x86_subreg_8bit)>,
1803 Requires<[In64BitMode]>;
1804 def : Pat<(i8 (trunc GR16:$src)),
1805 (EXTRACT_SUBREG GR16:$src, x86_subreg_8bit)>,
1806 Requires<[In64BitMode]>;
1808 // h-register tricks.
1809 // For now, be conservative on x86-64 and use an h-register extract only if the
1810 // value is immediately zero-extended or stored, which are somewhat common
1811 // cases. This uses a bunch of code to prevent a register requiring a REX prefix
1812 // from being allocated in the same instruction as the h register, as there's
1813 // currently no way to describe this requirement to the register allocator.
1815 // h-register extract and zero-extend.
1816 def : Pat<(and (srl_su GR64:$src, (i8 8)), (i64 255)),
1820 (EXTRACT_SUBREG (i64 (COPY_TO_REGCLASS GR64:$src, GR64_ABCD)),
1821 x86_subreg_8bit_hi)),
1823 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
1825 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1826 x86_subreg_8bit_hi))>,
1827 Requires<[In64BitMode]>;
1828 def : Pat<(srl_su GR16:$src, (i8 8)),
1831 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1832 x86_subreg_8bit_hi)),
1834 Requires<[In64BitMode]>;
1835 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
1837 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1838 x86_subreg_8bit_hi))>,
1839 Requires<[In64BitMode]>;
1840 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
1842 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1843 x86_subreg_8bit_hi))>,
1844 Requires<[In64BitMode]>;
1845 def : Pat<(i64 (zext (srl_su GR16:$src, (i8 8)))),
1849 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1850 x86_subreg_8bit_hi)),
1852 def : Pat<(i64 (anyext (srl_su GR16:$src, (i8 8)))),
1856 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1857 x86_subreg_8bit_hi)),
1860 // h-register extract and store.
1861 def : Pat<(store (i8 (trunc_su (srl_su GR64:$src, (i8 8)))), addr:$dst),
1864 (EXTRACT_SUBREG (i64 (COPY_TO_REGCLASS GR64:$src, GR64_ABCD)),
1865 x86_subreg_8bit_hi))>;
1866 def : Pat<(store (i8 (trunc_su (srl_su GR32:$src, (i8 8)))), addr:$dst),
1869 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1870 x86_subreg_8bit_hi))>,
1871 Requires<[In64BitMode]>;
1872 def : Pat<(store (i8 (trunc_su (srl_su GR16:$src, (i8 8)))), addr:$dst),
1875 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1876 x86_subreg_8bit_hi))>,
1877 Requires<[In64BitMode]>;
1879 // (shl x, 1) ==> (add x, x)
1880 def : Pat<(shl GR64:$src1, (i8 1)), (ADD64rr GR64:$src1, GR64:$src1)>;
1882 // (shl x (and y, 63)) ==> (shl x, y)
1883 def : Pat<(shl GR64:$src1, (and CL:$amt, 63)),
1884 (SHL64rCL GR64:$src1)>;
1885 def : Pat<(store (shl (loadi64 addr:$dst), (and CL:$amt, 63)), addr:$dst),
1886 (SHL64mCL addr:$dst)>;
1888 def : Pat<(srl GR64:$src1, (and CL:$amt, 63)),
1889 (SHR64rCL GR64:$src1)>;
1890 def : Pat<(store (srl (loadi64 addr:$dst), (and CL:$amt, 63)), addr:$dst),
1891 (SHR64mCL addr:$dst)>;
1893 def : Pat<(sra GR64:$src1, (and CL:$amt, 63)),
1894 (SAR64rCL GR64:$src1)>;
1895 def : Pat<(store (sra (loadi64 addr:$dst), (and CL:$amt, 63)), addr:$dst),
1896 (SAR64mCL addr:$dst)>;
1898 // (or (x >> c) | (y << (64 - c))) ==> (shrd64 x, y, c)
1899 def : Pat<(or (srl GR64:$src1, CL:$amt),
1900 (shl GR64:$src2, (sub 64, CL:$amt))),
1901 (SHRD64rrCL GR64:$src1, GR64:$src2)>;
1903 def : Pat<(store (or (srl (loadi64 addr:$dst), CL:$amt),
1904 (shl GR64:$src2, (sub 64, CL:$amt))), addr:$dst),
1905 (SHRD64mrCL addr:$dst, GR64:$src2)>;
1907 def : Pat<(or (srl GR64:$src1, (i8 (trunc RCX:$amt))),
1908 (shl GR64:$src2, (i8 (trunc (sub 64, RCX:$amt))))),
1909 (SHRD64rrCL GR64:$src1, GR64:$src2)>;
1911 def : Pat<(store (or (srl (loadi64 addr:$dst), (i8 (trunc RCX:$amt))),
1912 (shl GR64:$src2, (i8 (trunc (sub 64, RCX:$amt))))),
1914 (SHRD64mrCL addr:$dst, GR64:$src2)>;
1916 def : Pat<(shrd GR64:$src1, (i8 imm:$amt1), GR64:$src2, (i8 imm:$amt2)),
1917 (SHRD64rri8 GR64:$src1, GR64:$src2, (i8 imm:$amt1))>;
1919 def : Pat<(store (shrd (loadi64 addr:$dst), (i8 imm:$amt1),
1920 GR64:$src2, (i8 imm:$amt2)), addr:$dst),
1921 (SHRD64mri8 addr:$dst, GR64:$src2, (i8 imm:$amt1))>;
1923 // (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
1924 def : Pat<(or (shl GR64:$src1, CL:$amt),
1925 (srl GR64:$src2, (sub 64, CL:$amt))),
1926 (SHLD64rrCL GR64:$src1, GR64:$src2)>;
1928 def : Pat<(store (or (shl (loadi64 addr:$dst), CL:$amt),
1929 (srl GR64:$src2, (sub 64, CL:$amt))), addr:$dst),
1930 (SHLD64mrCL addr:$dst, GR64:$src2)>;
1932 def : Pat<(or (shl GR64:$src1, (i8 (trunc RCX:$amt))),
1933 (srl GR64:$src2, (i8 (trunc (sub 64, RCX:$amt))))),
1934 (SHLD64rrCL GR64:$src1, GR64:$src2)>;
1936 def : Pat<(store (or (shl (loadi64 addr:$dst), (i8 (trunc RCX:$amt))),
1937 (srl GR64:$src2, (i8 (trunc (sub 64, RCX:$amt))))),
1939 (SHLD64mrCL addr:$dst, GR64:$src2)>;
1941 def : Pat<(shld GR64:$src1, (i8 imm:$amt1), GR64:$src2, (i8 imm:$amt2)),
1942 (SHLD64rri8 GR64:$src1, GR64:$src2, (i8 imm:$amt1))>;
1944 def : Pat<(store (shld (loadi64 addr:$dst), (i8 imm:$amt1),
1945 GR64:$src2, (i8 imm:$amt2)), addr:$dst),
1946 (SHLD64mri8 addr:$dst, GR64:$src2, (i8 imm:$amt1))>;
1948 // X86 specific add which produces a flag.
1949 def : Pat<(addc GR64:$src1, GR64:$src2),
1950 (ADD64rr GR64:$src1, GR64:$src2)>;
1951 def : Pat<(addc GR64:$src1, (load addr:$src2)),
1952 (ADD64rm GR64:$src1, addr:$src2)>;
1953 def : Pat<(addc GR64:$src1, i64immSExt8:$src2),
1954 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
1955 def : Pat<(addc GR64:$src1, i64immSExt32:$src2),
1956 (ADD64ri32 GR64:$src1, imm:$src2)>;
1958 def : Pat<(subc GR64:$src1, GR64:$src2),
1959 (SUB64rr GR64:$src1, GR64:$src2)>;
1960 def : Pat<(subc GR64:$src1, (load addr:$src2)),
1961 (SUB64rm GR64:$src1, addr:$src2)>;
1962 def : Pat<(subc GR64:$src1, i64immSExt8:$src2),
1963 (SUB64ri8 GR64:$src1, i64immSExt8:$src2)>;
1964 def : Pat<(subc GR64:$src1, imm:$src2),
1965 (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>;
1967 //===----------------------------------------------------------------------===//
1968 // EFLAGS-defining Patterns
1969 //===----------------------------------------------------------------------===//
1971 // Register-Register Addition with EFLAGS result
1972 def : Pat<(parallel (X86add_flag GR64:$src1, GR64:$src2),
1974 (ADD64rr GR64:$src1, GR64:$src2)>;
1976 // Register-Integer Addition with EFLAGS result
1977 def : Pat<(parallel (X86add_flag GR64:$src1, i64immSExt8:$src2),
1979 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
1980 def : Pat<(parallel (X86add_flag GR64:$src1, i64immSExt32:$src2),
1982 (ADD64ri32 GR64:$src1, i64immSExt32:$src2)>;
1984 // Register-Memory Addition with EFLAGS result
1985 def : Pat<(parallel (X86add_flag GR64:$src1, (loadi64 addr:$src2)),
1987 (ADD64rm GR64:$src1, addr:$src2)>;
1989 // Memory-Register Addition with EFLAGS result
1990 def : Pat<(parallel (store (X86add_flag (loadi64 addr:$dst), GR64:$src2),
1993 (ADD64mr addr:$dst, GR64:$src2)>;
1994 def : Pat<(parallel (store (X86add_flag (loadi64 addr:$dst), i64immSExt8:$src2),
1997 (ADD64mi8 addr:$dst, i64immSExt8:$src2)>;
1998 def : Pat<(parallel (store (X86add_flag (loadi64 addr:$dst), i64immSExt32:$src2),
2001 (ADD64mi32 addr:$dst, i64immSExt32:$src2)>;
2003 // Register-Register Subtraction with EFLAGS result
2004 def : Pat<(parallel (X86sub_flag GR64:$src1, GR64:$src2),
2006 (SUB64rr GR64:$src1, GR64:$src2)>;
2008 // Register-Memory Subtraction with EFLAGS result
2009 def : Pat<(parallel (X86sub_flag GR64:$src1, (loadi64 addr:$src2)),
2011 (SUB64rm GR64:$src1, addr:$src2)>;
2013 // Register-Integer Subtraction with EFLAGS result
2014 def : Pat<(parallel (X86sub_flag GR64:$src1, i64immSExt8:$src2),
2016 (SUB64ri8 GR64:$src1, i64immSExt8:$src2)>;
2017 def : Pat<(parallel (X86sub_flag GR64:$src1, i64immSExt32:$src2),
2019 (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>;
2021 // Memory-Register Subtraction with EFLAGS result
2022 def : Pat<(parallel (store (X86sub_flag (loadi64 addr:$dst), GR64:$src2),
2025 (SUB64mr addr:$dst, GR64:$src2)>;
2027 // Memory-Integer Subtraction with EFLAGS result
2028 def : Pat<(parallel (store (X86sub_flag (loadi64 addr:$dst), i64immSExt8:$src2),
2031 (SUB64mi8 addr:$dst, i64immSExt8:$src2)>;
2032 def : Pat<(parallel (store (X86sub_flag (loadi64 addr:$dst), i64immSExt32:$src2),
2035 (SUB64mi32 addr:$dst, i64immSExt32:$src2)>;
2037 // Register-Register Signed Integer Multiplication with EFLAGS result
2038 def : Pat<(parallel (X86smul_flag GR64:$src1, GR64:$src2),
2040 (IMUL64rr GR64:$src1, GR64:$src2)>;
2042 // Register-Memory Signed Integer Multiplication with EFLAGS result
2043 def : Pat<(parallel (X86smul_flag GR64:$src1, (loadi64 addr:$src2)),
2045 (IMUL64rm GR64:$src1, addr:$src2)>;
2047 // Register-Integer Signed Integer Multiplication with EFLAGS result
2048 def : Pat<(parallel (X86smul_flag GR64:$src1, i64immSExt8:$src2),
2050 (IMUL64rri8 GR64:$src1, i64immSExt8:$src2)>;
2051 def : Pat<(parallel (X86smul_flag GR64:$src1, i64immSExt32:$src2),
2053 (IMUL64rri32 GR64:$src1, i64immSExt32:$src2)>;
2055 // Memory-Integer Signed Integer Multiplication with EFLAGS result
2056 def : Pat<(parallel (X86smul_flag (loadi64 addr:$src1), i64immSExt8:$src2),
2058 (IMUL64rmi8 addr:$src1, i64immSExt8:$src2)>;
2059 def : Pat<(parallel (X86smul_flag (loadi64 addr:$src1), i64immSExt32:$src2),
2061 (IMUL64rmi32 addr:$src1, i64immSExt32:$src2)>;
2063 // INC and DEC with EFLAGS result. Note that these do not set CF.
2064 def : Pat<(parallel (X86inc_flag GR16:$src), (implicit EFLAGS)),
2065 (INC64_16r GR16:$src)>, Requires<[In64BitMode]>;
2066 def : Pat<(parallel (store (i16 (X86inc_flag (loadi16 addr:$dst))), addr:$dst),
2068 (INC64_16m addr:$dst)>, Requires<[In64BitMode]>;
2069 def : Pat<(parallel (X86dec_flag GR16:$src), (implicit EFLAGS)),
2070 (DEC64_16r GR16:$src)>, Requires<[In64BitMode]>;
2071 def : Pat<(parallel (store (i16 (X86dec_flag (loadi16 addr:$dst))), addr:$dst),
2073 (DEC64_16m addr:$dst)>, Requires<[In64BitMode]>;
2075 def : Pat<(parallel (X86inc_flag GR32:$src), (implicit EFLAGS)),
2076 (INC64_32r GR32:$src)>, Requires<[In64BitMode]>;
2077 def : Pat<(parallel (store (i32 (X86inc_flag (loadi32 addr:$dst))), addr:$dst),
2079 (INC64_32m addr:$dst)>, Requires<[In64BitMode]>;
2080 def : Pat<(parallel (X86dec_flag GR32:$src), (implicit EFLAGS)),
2081 (DEC64_32r GR32:$src)>, Requires<[In64BitMode]>;
2082 def : Pat<(parallel (store (i32 (X86dec_flag (loadi32 addr:$dst))), addr:$dst),
2084 (DEC64_32m addr:$dst)>, Requires<[In64BitMode]>;
2086 def : Pat<(parallel (X86inc_flag GR64:$src), (implicit EFLAGS)),
2087 (INC64r GR64:$src)>;
2088 def : Pat<(parallel (store (i64 (X86inc_flag (loadi64 addr:$dst))), addr:$dst),
2090 (INC64m addr:$dst)>;
2091 def : Pat<(parallel (X86dec_flag GR64:$src), (implicit EFLAGS)),
2092 (DEC64r GR64:$src)>;
2093 def : Pat<(parallel (store (i64 (X86dec_flag (loadi64 addr:$dst))), addr:$dst),
2095 (DEC64m addr:$dst)>;
2097 // Register-Register Logical Or with EFLAGS result
2098 def : Pat<(parallel (X86or_flag GR64:$src1, GR64:$src2),
2100 (OR64rr GR64:$src1, GR64:$src2)>;
2102 // Register-Integer Logical Or with EFLAGS result
2103 def : Pat<(parallel (X86or_flag GR64:$src1, i64immSExt8:$src2),
2105 (OR64ri8 GR64:$src1, i64immSExt8:$src2)>;
2106 def : Pat<(parallel (X86or_flag GR64:$src1, i64immSExt32:$src2),
2108 (OR64ri32 GR64:$src1, i64immSExt32:$src2)>;
2110 // Register-Memory Logical Or with EFLAGS result
2111 def : Pat<(parallel (X86or_flag GR64:$src1, (loadi64 addr:$src2)),
2113 (OR64rm GR64:$src1, addr:$src2)>;
2115 // Memory-Register Logical Or with EFLAGS result
2116 def : Pat<(parallel (store (X86or_flag (loadi64 addr:$dst), GR64:$src2),
2119 (OR64mr addr:$dst, GR64:$src2)>;
2120 def : Pat<(parallel (store (X86or_flag (loadi64 addr:$dst), i64immSExt8:$src2),
2123 (OR64mi8 addr:$dst, i64immSExt8:$src2)>;
2124 def : Pat<(parallel (store (X86or_flag (loadi64 addr:$dst), i64immSExt32:$src2),
2127 (OR64mi32 addr:$dst, i64immSExt32:$src2)>;
2129 // Register-Register Logical XOr with EFLAGS result
2130 def : Pat<(parallel (X86xor_flag GR64:$src1, GR64:$src2),
2132 (XOR64rr GR64:$src1, GR64:$src2)>;
2134 // Register-Integer Logical XOr with EFLAGS result
2135 def : Pat<(parallel (X86xor_flag GR64:$src1, i64immSExt8:$src2),
2137 (XOR64ri8 GR64:$src1, i64immSExt8:$src2)>;
2138 def : Pat<(parallel (X86xor_flag GR64:$src1, i64immSExt32:$src2),
2140 (XOR64ri32 GR64:$src1, i64immSExt32:$src2)>;
2142 // Register-Memory Logical XOr with EFLAGS result
2143 def : Pat<(parallel (X86xor_flag GR64:$src1, (loadi64 addr:$src2)),
2145 (XOR64rm GR64:$src1, addr:$src2)>;
2147 // Memory-Register Logical XOr with EFLAGS result
2148 def : Pat<(parallel (store (X86xor_flag (loadi64 addr:$dst), GR64:$src2),
2151 (XOR64mr addr:$dst, GR64:$src2)>;
2152 def : Pat<(parallel (store (X86xor_flag (loadi64 addr:$dst), i64immSExt8:$src2),
2155 (XOR64mi8 addr:$dst, i64immSExt8:$src2)>;
2156 def : Pat<(parallel (store (X86xor_flag (loadi64 addr:$dst), i64immSExt32:$src2),
2159 (XOR64mi32 addr:$dst, i64immSExt32:$src2)>;
2161 // Register-Register Logical And with EFLAGS result
2162 def : Pat<(parallel (X86and_flag GR64:$src1, GR64:$src2),
2164 (AND64rr GR64:$src1, GR64:$src2)>;
2166 // Register-Integer Logical And with EFLAGS result
2167 def : Pat<(parallel (X86and_flag GR64:$src1, i64immSExt8:$src2),
2169 (AND64ri8 GR64:$src1, i64immSExt8:$src2)>;
2170 def : Pat<(parallel (X86and_flag GR64:$src1, i64immSExt32:$src2),
2172 (AND64ri32 GR64:$src1, i64immSExt32:$src2)>;
2174 // Register-Memory Logical And with EFLAGS result
2175 def : Pat<(parallel (X86and_flag GR64:$src1, (loadi64 addr:$src2)),
2177 (AND64rm GR64:$src1, addr:$src2)>;
2179 // Memory-Register Logical And with EFLAGS result
2180 def : Pat<(parallel (store (X86and_flag (loadi64 addr:$dst), GR64:$src2),
2183 (AND64mr addr:$dst, GR64:$src2)>;
2184 def : Pat<(parallel (store (X86and_flag (loadi64 addr:$dst), i64immSExt8:$src2),
2187 (AND64mi8 addr:$dst, i64immSExt8:$src2)>;
2188 def : Pat<(parallel (store (X86and_flag (loadi64 addr:$dst), i64immSExt32:$src2),
2191 (AND64mi32 addr:$dst, i64immSExt32:$src2)>;
2193 //===----------------------------------------------------------------------===//
2194 // X86-64 SSE Instructions
2195 //===----------------------------------------------------------------------===//
2197 // Move instructions...
2199 def MOV64toPQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
2200 "mov{d|q}\t{$src, $dst|$dst, $src}",
2202 (v2i64 (scalar_to_vector GR64:$src)))]>;
2203 def MOVPQIto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
2204 "mov{d|q}\t{$src, $dst|$dst, $src}",
2205 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
2208 def MOV64toSDrr : RPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
2209 "mov{d|q}\t{$src, $dst|$dst, $src}",
2210 [(set FR64:$dst, (bitconvert GR64:$src))]>;
2211 def MOV64toSDrm : RPDI<0x6E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
2212 "movq\t{$src, $dst|$dst, $src}",
2213 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>;
2215 def MOVSDto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
2216 "mov{d|q}\t{$src, $dst|$dst, $src}",
2217 [(set GR64:$dst, (bitconvert FR64:$src))]>;
2218 def MOVSDto64mr : RPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
2219 "movq\t{$src, $dst|$dst, $src}",
2220 [(store (i64 (bitconvert FR64:$src)), addr:$dst)]>;
2222 //===----------------------------------------------------------------------===//
2223 // X86-64 SSE4.1 Instructions
2224 //===----------------------------------------------------------------------===//
2226 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
2227 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
2228 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
2229 (ins VR128:$src1, i32i8imm:$src2),
2230 !strconcat(OpcodeStr,
2231 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2233 (extractelt (v2i64 VR128:$src1), imm:$src2))]>, OpSize, REX_W;
2234 def mr : SS4AIi8<opc, MRMDestMem, (outs),
2235 (ins i64mem:$dst, VR128:$src1, i32i8imm:$src2),
2236 !strconcat(OpcodeStr,
2237 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2238 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
2239 addr:$dst)]>, OpSize, REX_W;
2242 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
2244 let isTwoAddress = 1 in {
2245 multiclass SS41I_insert64<bits<8> opc, string OpcodeStr> {
2246 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
2247 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
2248 !strconcat(OpcodeStr,
2249 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2251 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
2253 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
2254 (ins VR128:$src1, i64mem:$src2, i32i8imm:$src3),
2255 !strconcat(OpcodeStr,
2256 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2258 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
2259 imm:$src3)))]>, OpSize, REX_W;
2263 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">;
2265 // -disable-16bit support.
2266 def : Pat<(truncstorei16 (i64 imm:$src), addr:$dst),
2267 (MOV16mi addr:$dst, imm:$src)>;
2268 def : Pat<(truncstorei16 GR64:$src, addr:$dst),
2269 (MOV16mr addr:$dst, (EXTRACT_SUBREG GR64:$src, x86_subreg_16bit))>;
2270 def : Pat<(i64 (sextloadi16 addr:$dst)),
2271 (MOVSX64rm16 addr:$dst)>;
2272 def : Pat<(i64 (zextloadi16 addr:$dst)),
2273 (MOVZX64rm16 addr:$dst)>;
2274 def : Pat<(i64 (extloadi16 addr:$dst)),
2275 (MOVZX64rm16 addr:$dst)>;