1 //===-- InstSelectSimple.cpp - A simple instruction selector for x86 ------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a simple peephole instruction selector for the x86 target
12 //===----------------------------------------------------------------------===//
15 #include "X86InstrBuilder.h"
16 #include "X86InstrInfo.h"
17 #include "llvm/Constants.h"
18 #include "llvm/DerivedTypes.h"
19 #include "llvm/Function.h"
20 #include "llvm/Instructions.h"
21 #include "llvm/IntrinsicLowering.h"
22 #include "llvm/Pass.h"
23 #include "llvm/CodeGen/MachineConstantPool.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/SSARegMap.h"
27 #include "llvm/Target/MRegisterInfo.h"
28 #include "llvm/Target/TargetMachine.h"
29 #include "llvm/Support/GetElementPtrTypeIterator.h"
30 #include "llvm/Support/InstVisitor.h"
31 #include "Support/Statistic.h"
36 NumFPKill("x86-codegen", "Number of FP_REG_KILL instructions added");
38 /// TypeClass - Used by the X86 backend to group LLVM types by their basic X86
42 cByte, cShort, cInt, cFP, cLong
46 /// getClass - Turn a primitive type into a "class" number which is based on the
47 /// size of the type, and whether or not it is floating point.
49 static inline TypeClass getClass(const Type *Ty) {
50 switch (Ty->getPrimitiveID()) {
52 case Type::UByteTyID: return cByte; // Byte operands are class #0
54 case Type::UShortTyID: return cShort; // Short operands are class #1
57 case Type::PointerTyID: return cInt; // Int's and pointers are class #2
60 case Type::DoubleTyID: return cFP; // Floating Point is #3
63 case Type::ULongTyID: return cLong; // Longs are class #4
65 assert(0 && "Invalid type to getClass!");
66 return cByte; // not reached
70 // getClassB - Just like getClass, but treat boolean values as bytes.
71 static inline TypeClass getClassB(const Type *Ty) {
72 if (Ty == Type::BoolTy) return cByte;
77 struct ISel : public FunctionPass, InstVisitor<ISel> {
79 MachineFunction *F; // The function we are compiling into
80 MachineBasicBlock *BB; // The current MBB we are compiling
81 int VarArgsFrameIndex; // FrameIndex for start of varargs area
82 int ReturnAddressIndex; // FrameIndex for the return address
84 std::map<Value*, unsigned> RegMap; // Mapping between Val's and SSA Regs
86 // MBBMap - Mapping between LLVM BB -> Machine BB
87 std::map<const BasicBlock*, MachineBasicBlock*> MBBMap;
89 ISel(TargetMachine &tm) : TM(tm), F(0), BB(0) {}
91 /// runOnFunction - Top level implementation of instruction selection for
92 /// the entire function.
94 bool runOnFunction(Function &Fn) {
95 // First pass over the function, lower any unknown intrinsic functions
96 // with the IntrinsicLowering class.
97 LowerUnknownIntrinsicFunctionCalls(Fn);
99 F = &MachineFunction::construct(&Fn, TM);
101 // Create all of the machine basic blocks for the function...
102 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
103 F->getBasicBlockList().push_back(MBBMap[I] = new MachineBasicBlock(I));
107 // Set up a frame object for the return address. This is used by the
108 // llvm.returnaddress & llvm.frameaddress intrinisics.
109 ReturnAddressIndex = F->getFrameInfo()->CreateFixedObject(4, -4);
111 // Copy incoming arguments off of the stack...
112 LoadArgumentsToVirtualRegs(Fn);
114 // Instruction select everything except PHI nodes
117 // Select the PHI nodes
120 // Insert the FP_REG_KILL instructions into blocks that need them.
126 // We always build a machine code representation for the function
130 virtual const char *getPassName() const {
131 return "X86 Simple Instruction Selection";
134 /// visitBasicBlock - This method is called when we are visiting a new basic
135 /// block. This simply creates a new MachineBasicBlock to emit code into
136 /// and adds it to the current MachineFunction. Subsequent visit* for
137 /// instructions will be invoked for all instructions in the basic block.
139 void visitBasicBlock(BasicBlock &LLVM_BB) {
140 BB = MBBMap[&LLVM_BB];
143 /// LowerUnknownIntrinsicFunctionCalls - This performs a prepass over the
144 /// function, lowering any calls to unknown intrinsic functions into the
145 /// equivalent LLVM code.
147 void LowerUnknownIntrinsicFunctionCalls(Function &F);
149 /// LoadArgumentsToVirtualRegs - Load all of the arguments to this function
150 /// from the stack into virtual registers.
152 void LoadArgumentsToVirtualRegs(Function &F);
154 /// SelectPHINodes - Insert machine code to generate phis. This is tricky
155 /// because we have to generate our sources into the source basic blocks,
156 /// not the current one.
158 void SelectPHINodes();
160 /// InsertFPRegKills - Insert FP_REG_KILL instructions into basic blocks
161 /// that need them. This only occurs due to the floating point stackifier
162 /// not being aggressive enough to handle arbitrary global stackification.
164 void InsertFPRegKills();
166 // Visitation methods for various instructions. These methods simply emit
167 // fixed X86 code for each instruction.
170 // Control flow operators
171 void visitReturnInst(ReturnInst &RI);
172 void visitBranchInst(BranchInst &BI);
178 ValueRecord(unsigned R, const Type *T) : Val(0), Reg(R), Ty(T) {}
179 ValueRecord(Value *V) : Val(V), Reg(0), Ty(V->getType()) {}
181 void doCall(const ValueRecord &Ret, MachineInstr *CallMI,
182 const std::vector<ValueRecord> &Args);
183 void visitCallInst(CallInst &I);
184 void visitIntrinsicCall(Intrinsic::ID ID, CallInst &I);
186 // Arithmetic operators
187 void visitSimpleBinary(BinaryOperator &B, unsigned OpcodeClass);
188 void visitAdd(BinaryOperator &B) { visitSimpleBinary(B, 0); }
189 void visitSub(BinaryOperator &B) { visitSimpleBinary(B, 1); }
190 void visitMul(BinaryOperator &B);
192 void visitDiv(BinaryOperator &B) { visitDivRem(B); }
193 void visitRem(BinaryOperator &B) { visitDivRem(B); }
194 void visitDivRem(BinaryOperator &B);
197 void visitAnd(BinaryOperator &B) { visitSimpleBinary(B, 2); }
198 void visitOr (BinaryOperator &B) { visitSimpleBinary(B, 3); }
199 void visitXor(BinaryOperator &B) { visitSimpleBinary(B, 4); }
201 // Comparison operators...
202 void visitSetCondInst(SetCondInst &I);
203 unsigned EmitComparison(unsigned OpNum, Value *Op0, Value *Op1,
204 MachineBasicBlock *MBB,
205 MachineBasicBlock::iterator MBBI);
206 void visitSelectInst(SelectInst &SI);
209 // Memory Instructions
210 void visitLoadInst(LoadInst &I);
211 void visitStoreInst(StoreInst &I);
212 void visitGetElementPtrInst(GetElementPtrInst &I);
213 void visitAllocaInst(AllocaInst &I);
214 void visitMallocInst(MallocInst &I);
215 void visitFreeInst(FreeInst &I);
218 void visitShiftInst(ShiftInst &I);
219 void visitPHINode(PHINode &I) {} // PHI nodes handled by second pass
220 void visitCastInst(CastInst &I);
221 void visitVANextInst(VANextInst &I);
222 void visitVAArgInst(VAArgInst &I);
224 void visitInstruction(Instruction &I) {
225 std::cerr << "Cannot instruction select: " << I;
229 /// promote32 - Make a value 32-bits wide, and put it somewhere.
231 void promote32(unsigned targetReg, const ValueRecord &VR);
233 /// getAddressingMode - Get the addressing mode to use to address the
234 /// specified value. The returned value should be used with addFullAddress.
235 void getAddressingMode(Value *Addr, unsigned &BaseReg, unsigned &Scale,
236 unsigned &IndexReg, unsigned &Disp);
239 /// getGEPIndex - This is used to fold GEP instructions into X86 addressing
241 void getGEPIndex(MachineBasicBlock *MBB, MachineBasicBlock::iterator IP,
242 std::vector<Value*> &GEPOps,
243 std::vector<const Type*> &GEPTypes, unsigned &BaseReg,
244 unsigned &Scale, unsigned &IndexReg, unsigned &Disp);
246 /// isGEPFoldable - Return true if the specified GEP can be completely
247 /// folded into the addressing mode of a load/store or lea instruction.
248 bool isGEPFoldable(MachineBasicBlock *MBB,
249 Value *Src, User::op_iterator IdxBegin,
250 User::op_iterator IdxEnd, unsigned &BaseReg,
251 unsigned &Scale, unsigned &IndexReg, unsigned &Disp);
253 /// emitGEPOperation - Common code shared between visitGetElementPtrInst and
254 /// constant expression GEP support.
256 void emitGEPOperation(MachineBasicBlock *BB, MachineBasicBlock::iterator IP,
257 Value *Src, User::op_iterator IdxBegin,
258 User::op_iterator IdxEnd, unsigned TargetReg);
260 /// emitCastOperation - Common code shared between visitCastInst and
261 /// constant expression cast support.
263 void emitCastOperation(MachineBasicBlock *BB,MachineBasicBlock::iterator IP,
264 Value *Src, const Type *DestTy, unsigned TargetReg);
266 /// emitSimpleBinaryOperation - Common code shared between visitSimpleBinary
267 /// and constant expression support.
269 void emitSimpleBinaryOperation(MachineBasicBlock *BB,
270 MachineBasicBlock::iterator IP,
271 Value *Op0, Value *Op1,
272 unsigned OperatorClass, unsigned TargetReg);
274 /// emitBinaryFPOperation - This method handles emission of floating point
275 /// Add (0), Sub (1), Mul (2), and Div (3) operations.
276 void emitBinaryFPOperation(MachineBasicBlock *BB,
277 MachineBasicBlock::iterator IP,
278 Value *Op0, Value *Op1,
279 unsigned OperatorClass, unsigned TargetReg);
281 void emitMultiply(MachineBasicBlock *BB, MachineBasicBlock::iterator IP,
282 Value *Op0, Value *Op1, unsigned TargetReg);
284 void doMultiply(MachineBasicBlock *MBB, MachineBasicBlock::iterator MBBI,
285 unsigned DestReg, const Type *DestTy,
286 unsigned Op0Reg, unsigned Op1Reg);
287 void doMultiplyConst(MachineBasicBlock *MBB,
288 MachineBasicBlock::iterator MBBI,
289 unsigned DestReg, const Type *DestTy,
290 unsigned Op0Reg, unsigned Op1Val);
292 void emitDivRemOperation(MachineBasicBlock *BB,
293 MachineBasicBlock::iterator IP,
294 Value *Op0, Value *Op1, bool isDiv,
297 /// emitSetCCOperation - Common code shared between visitSetCondInst and
298 /// constant expression support.
300 void emitSetCCOperation(MachineBasicBlock *BB,
301 MachineBasicBlock::iterator IP,
302 Value *Op0, Value *Op1, unsigned Opcode,
305 /// emitShiftOperation - Common code shared between visitShiftInst and
306 /// constant expression support.
308 void emitShiftOperation(MachineBasicBlock *MBB,
309 MachineBasicBlock::iterator IP,
310 Value *Op, Value *ShiftAmount, bool isLeftShift,
311 const Type *ResultTy, unsigned DestReg);
313 /// emitSelectOperation - Common code shared between visitSelectInst and the
314 /// constant expression support.
315 void emitSelectOperation(MachineBasicBlock *MBB,
316 MachineBasicBlock::iterator IP,
317 Value *Cond, Value *TrueVal, Value *FalseVal,
320 /// copyConstantToRegister - Output the instructions required to put the
321 /// specified constant into the specified register.
323 void copyConstantToRegister(MachineBasicBlock *MBB,
324 MachineBasicBlock::iterator MBBI,
325 Constant *C, unsigned Reg);
327 /// makeAnotherReg - This method returns the next register number we haven't
330 /// Long values are handled somewhat specially. They are always allocated
331 /// as pairs of 32 bit integer values. The register number returned is the
332 /// lower 32 bits of the long value, and the regNum+1 is the upper 32 bits
333 /// of the long value.
335 unsigned makeAnotherReg(const Type *Ty) {
336 assert(dynamic_cast<const X86RegisterInfo*>(TM.getRegisterInfo()) &&
337 "Current target doesn't have X86 reg info??");
338 const X86RegisterInfo *MRI =
339 static_cast<const X86RegisterInfo*>(TM.getRegisterInfo());
340 if (Ty == Type::LongTy || Ty == Type::ULongTy) {
341 const TargetRegisterClass *RC = MRI->getRegClassForType(Type::IntTy);
342 // Create the lower part
343 F->getSSARegMap()->createVirtualRegister(RC);
344 // Create the upper part.
345 return F->getSSARegMap()->createVirtualRegister(RC)-1;
348 // Add the mapping of regnumber => reg class to MachineFunction
349 const TargetRegisterClass *RC = MRI->getRegClassForType(Ty);
350 return F->getSSARegMap()->createVirtualRegister(RC);
353 /// getReg - This method turns an LLVM value into a register number. This
354 /// is guaranteed to produce the same register number for a particular value
355 /// every time it is queried.
357 unsigned getReg(Value &V) { return getReg(&V); } // Allow references
358 unsigned getReg(Value *V) {
359 // Just append to the end of the current bb.
360 MachineBasicBlock::iterator It = BB->end();
361 return getReg(V, BB, It);
363 unsigned getReg(Value *V, MachineBasicBlock *MBB,
364 MachineBasicBlock::iterator IPt) {
365 // If this operand is a constant, emit the code to copy the constant into
366 // the register here...
368 if (Constant *C = dyn_cast<Constant>(V)) {
369 unsigned Reg = makeAnotherReg(V->getType());
370 copyConstantToRegister(MBB, IPt, C, Reg);
372 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
373 unsigned Reg = makeAnotherReg(V->getType());
374 // Move the address of the global into the register
375 BuildMI(*MBB, IPt, X86::MOV32ri, 1, Reg).addGlobalAddress(GV);
377 } else if (CastInst *CI = dyn_cast<CastInst>(V)) {
378 // Do not emit noop casts at all.
379 if (getClassB(CI->getType()) == getClassB(CI->getOperand(0)->getType()))
380 return getReg(CI->getOperand(0), MBB, IPt);
383 unsigned &Reg = RegMap[V];
385 Reg = makeAnotherReg(V->getType());
394 /// copyConstantToRegister - Output the instructions required to put the
395 /// specified constant into the specified register.
397 void ISel::copyConstantToRegister(MachineBasicBlock *MBB,
398 MachineBasicBlock::iterator IP,
399 Constant *C, unsigned R) {
400 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
402 switch (CE->getOpcode()) {
403 case Instruction::GetElementPtr:
404 emitGEPOperation(MBB, IP, CE->getOperand(0),
405 CE->op_begin()+1, CE->op_end(), R);
407 case Instruction::Cast:
408 emitCastOperation(MBB, IP, CE->getOperand(0), CE->getType(), R);
411 case Instruction::Xor: ++Class; // FALL THROUGH
412 case Instruction::Or: ++Class; // FALL THROUGH
413 case Instruction::And: ++Class; // FALL THROUGH
414 case Instruction::Sub: ++Class; // FALL THROUGH
415 case Instruction::Add:
416 emitSimpleBinaryOperation(MBB, IP, CE->getOperand(0), CE->getOperand(1),
420 case Instruction::Mul:
421 emitMultiply(MBB, IP, CE->getOperand(0), CE->getOperand(1), R);
424 case Instruction::Div:
425 case Instruction::Rem:
426 emitDivRemOperation(MBB, IP, CE->getOperand(0), CE->getOperand(1),
427 CE->getOpcode() == Instruction::Div, R);
430 case Instruction::SetNE:
431 case Instruction::SetEQ:
432 case Instruction::SetLT:
433 case Instruction::SetGT:
434 case Instruction::SetLE:
435 case Instruction::SetGE:
436 emitSetCCOperation(MBB, IP, CE->getOperand(0), CE->getOperand(1),
440 case Instruction::Shl:
441 case Instruction::Shr:
442 emitShiftOperation(MBB, IP, CE->getOperand(0), CE->getOperand(1),
443 CE->getOpcode() == Instruction::Shl, CE->getType(), R);
446 case Instruction::Select:
447 emitSelectOperation(MBB, IP, CE->getOperand(0), CE->getOperand(1),
448 CE->getOperand(2), R);
452 std::cerr << "Offending expr: " << C << "\n";
453 assert(0 && "Constant expression not yet handled!\n");
457 if (C->getType()->isIntegral()) {
458 unsigned Class = getClassB(C->getType());
460 if (Class == cLong) {
461 // Copy the value into the register pair.
462 uint64_t Val = cast<ConstantInt>(C)->getRawValue();
463 BuildMI(*MBB, IP, X86::MOV32ri, 1, R).addImm(Val & 0xFFFFFFFF);
464 BuildMI(*MBB, IP, X86::MOV32ri, 1, R+1).addImm(Val >> 32);
468 assert(Class <= cInt && "Type not handled yet!");
470 static const unsigned IntegralOpcodeTab[] = {
471 X86::MOV8ri, X86::MOV16ri, X86::MOV32ri
474 if (C->getType() == Type::BoolTy) {
475 BuildMI(*MBB, IP, X86::MOV8ri, 1, R).addImm(C == ConstantBool::True);
477 ConstantInt *CI = cast<ConstantInt>(C);
478 BuildMI(*MBB, IP, IntegralOpcodeTab[Class],1,R).addImm(CI->getRawValue());
480 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
481 if (CFP->isExactlyValue(+0.0))
482 BuildMI(*MBB, IP, X86::FLD0, 0, R);
483 else if (CFP->isExactlyValue(+1.0))
484 BuildMI(*MBB, IP, X86::FLD1, 0, R);
486 // Otherwise we need to spill the constant to memory...
487 MachineConstantPool *CP = F->getConstantPool();
488 unsigned CPI = CP->getConstantPoolIndex(CFP);
489 const Type *Ty = CFP->getType();
491 assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!");
492 unsigned LoadOpcode = Ty == Type::FloatTy ? X86::FLD32m : X86::FLD64m;
493 addConstantPoolReference(BuildMI(*MBB, IP, LoadOpcode, 4, R), CPI);
496 } else if (isa<ConstantPointerNull>(C)) {
497 // Copy zero (null pointer) to the register.
498 BuildMI(*MBB, IP, X86::MOV32ri, 1, R).addImm(0);
499 } else if (ConstantPointerRef *CPR = dyn_cast<ConstantPointerRef>(C)) {
500 BuildMI(*MBB, IP, X86::MOV32ri, 1, R).addGlobalAddress(CPR->getValue());
502 std::cerr << "Offending constant: " << C << "\n";
503 assert(0 && "Type not handled yet!");
507 /// LoadArgumentsToVirtualRegs - Load all of the arguments to this function from
508 /// the stack into virtual registers.
510 void ISel::LoadArgumentsToVirtualRegs(Function &Fn) {
511 // Emit instructions to load the arguments... On entry to a function on the
512 // X86, the stack frame looks like this:
514 // [ESP] -- return address
515 // [ESP + 4] -- first argument (leftmost lexically)
516 // [ESP + 8] -- second argument, if first argument is four bytes in size
519 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
520 MachineFrameInfo *MFI = F->getFrameInfo();
522 for (Function::aiterator I = Fn.abegin(), E = Fn.aend(); I != E; ++I) {
523 bool ArgLive = !I->use_empty();
524 unsigned Reg = ArgLive ? getReg(*I) : 0;
525 int FI; // Frame object index
527 switch (getClassB(I->getType())) {
530 FI = MFI->CreateFixedObject(1, ArgOffset);
531 addFrameReference(BuildMI(BB, X86::MOV8rm, 4, Reg), FI);
536 FI = MFI->CreateFixedObject(2, ArgOffset);
537 addFrameReference(BuildMI(BB, X86::MOV16rm, 4, Reg), FI);
542 FI = MFI->CreateFixedObject(4, ArgOffset);
543 addFrameReference(BuildMI(BB, X86::MOV32rm, 4, Reg), FI);
548 FI = MFI->CreateFixedObject(8, ArgOffset);
549 addFrameReference(BuildMI(BB, X86::MOV32rm, 4, Reg), FI);
550 addFrameReference(BuildMI(BB, X86::MOV32rm, 4, Reg+1), FI, 4);
552 ArgOffset += 4; // longs require 4 additional bytes
557 if (I->getType() == Type::FloatTy) {
558 Opcode = X86::FLD32m;
559 FI = MFI->CreateFixedObject(4, ArgOffset);
561 Opcode = X86::FLD64m;
562 FI = MFI->CreateFixedObject(8, ArgOffset);
564 addFrameReference(BuildMI(BB, Opcode, 4, Reg), FI);
566 if (I->getType() == Type::DoubleTy)
567 ArgOffset += 4; // doubles require 4 additional bytes
570 assert(0 && "Unhandled argument type!");
572 ArgOffset += 4; // Each argument takes at least 4 bytes on the stack...
575 // If the function takes variable number of arguments, add a frame offset for
576 // the start of the first vararg value... this is used to expand
578 if (Fn.getFunctionType()->isVarArg())
579 VarArgsFrameIndex = MFI->CreateFixedObject(1, ArgOffset);
583 /// SelectPHINodes - Insert machine code to generate phis. This is tricky
584 /// because we have to generate our sources into the source basic blocks, not
587 void ISel::SelectPHINodes() {
588 const TargetInstrInfo &TII = TM.getInstrInfo();
589 const Function &LF = *F->getFunction(); // The LLVM function...
590 for (Function::const_iterator I = LF.begin(), E = LF.end(); I != E; ++I) {
591 const BasicBlock *BB = I;
592 MachineBasicBlock &MBB = *MBBMap[I];
594 // Loop over all of the PHI nodes in the LLVM basic block...
595 MachineBasicBlock::iterator PHIInsertPoint = MBB.begin();
596 for (BasicBlock::const_iterator I = BB->begin();
597 PHINode *PN = const_cast<PHINode*>(dyn_cast<PHINode>(I)); ++I) {
599 // Create a new machine instr PHI node, and insert it.
600 unsigned PHIReg = getReg(*PN);
601 MachineInstr *PhiMI = BuildMI(MBB, PHIInsertPoint,
602 X86::PHI, PN->getNumOperands(), PHIReg);
604 MachineInstr *LongPhiMI = 0;
605 if (PN->getType() == Type::LongTy || PN->getType() == Type::ULongTy)
606 LongPhiMI = BuildMI(MBB, PHIInsertPoint,
607 X86::PHI, PN->getNumOperands(), PHIReg+1);
609 // PHIValues - Map of blocks to incoming virtual registers. We use this
610 // so that we only initialize one incoming value for a particular block,
611 // even if the block has multiple entries in the PHI node.
613 std::map<MachineBasicBlock*, unsigned> PHIValues;
615 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
616 MachineBasicBlock *PredMBB = MBBMap[PN->getIncomingBlock(i)];
618 std::map<MachineBasicBlock*, unsigned>::iterator EntryIt =
619 PHIValues.lower_bound(PredMBB);
621 if (EntryIt != PHIValues.end() && EntryIt->first == PredMBB) {
622 // We already inserted an initialization of the register for this
623 // predecessor. Recycle it.
624 ValReg = EntryIt->second;
627 // Get the incoming value into a virtual register.
629 Value *Val = PN->getIncomingValue(i);
631 // If this is a constant or GlobalValue, we may have to insert code
632 // into the basic block to compute it into a virtual register.
633 if (isa<Constant>(Val) || isa<GlobalValue>(Val)) {
634 if (isa<ConstantExpr>(Val)) {
635 // Because we don't want to clobber any values which might be in
636 // physical registers with the computation of this constant (which
637 // might be arbitrarily complex if it is a constant expression),
638 // just insert the computation at the top of the basic block.
639 MachineBasicBlock::iterator PI = PredMBB->begin();
641 // Skip over any PHI nodes though!
642 while (PI != PredMBB->end() && PI->getOpcode() == X86::PHI)
645 ValReg = getReg(Val, PredMBB, PI);
647 // Simple constants get emitted at the end of the basic block,
648 // before any terminator instructions. We "know" that the code to
649 // move a constant into a register will never clobber any flags.
650 ValReg = getReg(Val, PredMBB, PredMBB->getFirstTerminator());
653 ValReg = getReg(Val);
656 // Remember that we inserted a value for this PHI for this predecessor
657 PHIValues.insert(EntryIt, std::make_pair(PredMBB, ValReg));
660 PhiMI->addRegOperand(ValReg);
661 PhiMI->addMachineBasicBlockOperand(PredMBB);
663 LongPhiMI->addRegOperand(ValReg+1);
664 LongPhiMI->addMachineBasicBlockOperand(PredMBB);
668 // Now that we emitted all of the incoming values for the PHI node, make
669 // sure to reposition the InsertPoint after the PHI that we just added.
670 // This is needed because we might have inserted a constant into this
671 // block, right after the PHI's which is before the old insert point!
672 PHIInsertPoint = LongPhiMI ? LongPhiMI : PhiMI;
678 /// RequiresFPRegKill - The floating point stackifier pass cannot insert
679 /// compensation code on critical edges. As such, it requires that we kill all
680 /// FP registers on the exit from any blocks that either ARE critical edges, or
681 /// branch to a block that has incoming critical edges.
683 /// Note that this kill instruction will eventually be eliminated when
684 /// restrictions in the stackifier are relaxed.
686 static bool RequiresFPRegKill(const MachineBasicBlock *MBB) {
688 const BasicBlock *BB = MBB->getBasicBlock ();
689 for (succ_const_iterator SI = succ_begin(BB), E = succ_end(BB); SI!=E; ++SI) {
690 const BasicBlock *Succ = *SI;
691 pred_const_iterator PI = pred_begin(Succ), PE = pred_end(Succ);
692 ++PI; // Block have at least one predecessory
693 if (PI != PE) { // If it has exactly one, this isn't crit edge
694 // If this block has more than one predecessor, check all of the
695 // predecessors to see if they have multiple successors. If so, then the
696 // block we are analyzing needs an FPRegKill.
697 for (PI = pred_begin(Succ); PI != PE; ++PI) {
698 const BasicBlock *Pred = *PI;
699 succ_const_iterator SI2 = succ_begin(Pred);
700 ++SI2; // There must be at least one successor of this block.
701 if (SI2 != succ_end(Pred))
702 return true; // Yes, we must insert the kill on this edge.
706 // If we got this far, there is no need to insert the kill instruction.
713 // InsertFPRegKills - Insert FP_REG_KILL instructions into basic blocks that
714 // need them. This only occurs due to the floating point stackifier not being
715 // aggressive enough to handle arbitrary global stackification.
717 // Currently we insert an FP_REG_KILL instruction into each block that uses or
718 // defines a floating point virtual register.
720 // When the global register allocators (like linear scan) finally update live
721 // variable analysis, we can keep floating point values in registers across
722 // portions of the CFG that do not involve critical edges. This will be a big
723 // win, but we are waiting on the global allocators before we can do this.
725 // With a bit of work, the floating point stackifier pass can be enhanced to
726 // break critical edges as needed (to make a place to put compensation code),
727 // but this will require some infrastructure improvements as well.
729 void ISel::InsertFPRegKills() {
730 SSARegMap &RegMap = *F->getSSARegMap();
732 for (MachineFunction::iterator BB = F->begin(), E = F->end(); BB != E; ++BB) {
733 for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I!=E; ++I)
734 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
735 MachineOperand& MO = I->getOperand(i);
736 if (MO.isRegister() && MO.getReg()) {
737 unsigned Reg = MO.getReg();
738 if (MRegisterInfo::isVirtualRegister(Reg))
739 if (RegMap.getRegClass(Reg)->getSize() == 10)
743 // If we haven't found an FP register use or def in this basic block, check
744 // to see if any of our successors has an FP PHI node, which will cause a
745 // copy to be inserted into this block.
746 for (MachineBasicBlock::const_succ_iterator SI = BB->succ_begin(),
747 SE = BB->succ_end(); SI != SE; ++SI) {
748 MachineBasicBlock *SBB = *SI;
749 for (MachineBasicBlock::iterator I = SBB->begin();
750 I != SBB->end() && I->getOpcode() == X86::PHI; ++I) {
751 if (RegMap.getRegClass(I->getOperand(0).getReg())->getSize() == 10)
757 // Okay, this block uses an FP register. If the block has successors (ie,
758 // it's not an unwind/return), insert the FP_REG_KILL instruction.
759 if (BB->succ_size () && RequiresFPRegKill(BB)) {
760 BuildMI(*BB, BB->getFirstTerminator(), X86::FP_REG_KILL, 0);
767 // canFoldSetCCIntoBranchOrSelect - Return the setcc instruction if we can fold
768 // it into the conditional branch or select instruction which is the only user
769 // of the cc instruction. This is the case if the conditional branch is the
770 // only user of the setcc, and if the setcc is in the same basic block as the
771 // conditional branch. We also don't handle long arguments below, so we reject
772 // them here as well.
774 static SetCondInst *canFoldSetCCIntoBranchOrSelect(Value *V) {
775 if (SetCondInst *SCI = dyn_cast<SetCondInst>(V))
776 if (SCI->hasOneUse()) {
777 Instruction *User = cast<Instruction>(SCI->use_back());
778 if ((isa<BranchInst>(User) || isa<SelectInst>(User)) &&
779 SCI->getParent() == User->getParent() &&
780 (getClassB(SCI->getOperand(0)->getType()) != cLong ||
781 SCI->getOpcode() == Instruction::SetEQ ||
782 SCI->getOpcode() == Instruction::SetNE))
788 // Return a fixed numbering for setcc instructions which does not depend on the
789 // order of the opcodes.
791 static unsigned getSetCCNumber(unsigned Opcode) {
793 default: assert(0 && "Unknown setcc instruction!");
794 case Instruction::SetEQ: return 0;
795 case Instruction::SetNE: return 1;
796 case Instruction::SetLT: return 2;
797 case Instruction::SetGE: return 3;
798 case Instruction::SetGT: return 4;
799 case Instruction::SetLE: return 5;
803 // LLVM -> X86 signed X86 unsigned
804 // ----- ---------- ------------
805 // seteq -> sete sete
806 // setne -> setne setne
807 // setlt -> setl setb
808 // setge -> setge setae
809 // setgt -> setg seta
810 // setle -> setle setbe
812 // sets // Used by comparison with 0 optimization
814 static const unsigned SetCCOpcodeTab[2][8] = {
815 { X86::SETEr, X86::SETNEr, X86::SETBr, X86::SETAEr, X86::SETAr, X86::SETBEr,
817 { X86::SETEr, X86::SETNEr, X86::SETLr, X86::SETGEr, X86::SETGr, X86::SETLEr,
818 X86::SETSr, X86::SETNSr },
821 // EmitComparison - This function emits a comparison of the two operands,
822 // returning the extended setcc code to use.
823 unsigned ISel::EmitComparison(unsigned OpNum, Value *Op0, Value *Op1,
824 MachineBasicBlock *MBB,
825 MachineBasicBlock::iterator IP) {
826 // The arguments are already supposed to be of the same type.
827 const Type *CompTy = Op0->getType();
828 unsigned Class = getClassB(CompTy);
829 unsigned Op0r = getReg(Op0, MBB, IP);
831 // Special case handling of: cmp R, i
832 if (ConstantInt *CI = dyn_cast<ConstantInt>(Op1)) {
833 if (Class == cByte || Class == cShort || Class == cInt) {
834 unsigned Op1v = CI->getRawValue();
836 // Mask off any upper bits of the constant, if there are any...
837 Op1v &= (1ULL << (8 << Class)) - 1;
839 // If this is a comparison against zero, emit more efficient code. We
840 // can't handle unsigned comparisons against zero unless they are == or
841 // !=. These should have been strength reduced already anyway.
842 if (Op1v == 0 && (CompTy->isSigned() || OpNum < 2)) {
843 static const unsigned TESTTab[] = {
844 X86::TEST8rr, X86::TEST16rr, X86::TEST32rr
846 BuildMI(*MBB, IP, TESTTab[Class], 2).addReg(Op0r).addReg(Op0r);
848 if (OpNum == 2) return 6; // Map jl -> js
849 if (OpNum == 3) return 7; // Map jg -> jns
853 static const unsigned CMPTab[] = {
854 X86::CMP8ri, X86::CMP16ri, X86::CMP32ri
857 BuildMI(*MBB, IP, CMPTab[Class], 2).addReg(Op0r).addImm(Op1v);
860 assert(Class == cLong && "Unknown integer class!");
861 unsigned LowCst = CI->getRawValue();
862 unsigned HiCst = CI->getRawValue() >> 32;
863 if (OpNum < 2) { // seteq, setne
864 unsigned LoTmp = Op0r;
866 LoTmp = makeAnotherReg(Type::IntTy);
867 BuildMI(*MBB, IP, X86::XOR32ri, 2, LoTmp).addReg(Op0r).addImm(LowCst);
869 unsigned HiTmp = Op0r+1;
871 HiTmp = makeAnotherReg(Type::IntTy);
872 BuildMI(*MBB, IP, X86::XOR32ri, 2,HiTmp).addReg(Op0r+1).addImm(HiCst);
874 unsigned FinalTmp = makeAnotherReg(Type::IntTy);
875 BuildMI(*MBB, IP, X86::OR32rr, 2, FinalTmp).addReg(LoTmp).addReg(HiTmp);
878 // Emit a sequence of code which compares the high and low parts once
879 // each, then uses a conditional move to handle the overflow case. For
880 // example, a setlt for long would generate code like this:
882 // AL = lo(op1) < lo(op2) // Signedness depends on operands
883 // BL = hi(op1) < hi(op2) // Always unsigned comparison
884 // dest = hi(op1) == hi(op2) ? AL : BL;
887 // FIXME: This would be much better if we had hierarchical register
888 // classes! Until then, hardcode registers so that we can deal with
889 // their aliases (because we don't have conditional byte moves).
891 BuildMI(*MBB, IP, X86::CMP32ri, 2).addReg(Op0r).addImm(LowCst);
892 BuildMI(*MBB, IP, SetCCOpcodeTab[0][OpNum], 0, X86::AL);
893 BuildMI(*MBB, IP, X86::CMP32ri, 2).addReg(Op0r+1).addImm(HiCst);
894 BuildMI(*MBB, IP, SetCCOpcodeTab[CompTy->isSigned()][OpNum], 0,X86::BL);
895 BuildMI(*MBB, IP, X86::IMPLICIT_DEF, 0, X86::BH);
896 BuildMI(*MBB, IP, X86::IMPLICIT_DEF, 0, X86::AH);
897 BuildMI(*MBB, IP, X86::CMOVE16rr, 2, X86::BX).addReg(X86::BX)
899 // NOTE: visitSetCondInst knows that the value is dumped into the BL
900 // register at this point for long values...
906 // Special case handling of comparison against +/- 0.0
907 if (ConstantFP *CFP = dyn_cast<ConstantFP>(Op1))
908 if (CFP->isExactlyValue(+0.0) || CFP->isExactlyValue(-0.0)) {
909 BuildMI(*MBB, IP, X86::FTST, 1).addReg(Op0r);
910 BuildMI(*MBB, IP, X86::FNSTSW8r, 0);
911 BuildMI(*MBB, IP, X86::SAHF, 1);
915 unsigned Op1r = getReg(Op1, MBB, IP);
917 default: assert(0 && "Unknown type class!");
918 // Emit: cmp <var1>, <var2> (do the comparison). We can
919 // compare 8-bit with 8-bit, 16-bit with 16-bit, 32-bit with
922 BuildMI(*MBB, IP, X86::CMP8rr, 2).addReg(Op0r).addReg(Op1r);
925 BuildMI(*MBB, IP, X86::CMP16rr, 2).addReg(Op0r).addReg(Op1r);
928 BuildMI(*MBB, IP, X86::CMP32rr, 2).addReg(Op0r).addReg(Op1r);
931 if (0) { // for processors prior to the P6
932 BuildMI(*MBB, IP, X86::FpUCOM, 2).addReg(Op0r).addReg(Op1r);
933 BuildMI(*MBB, IP, X86::FNSTSW8r, 0);
934 BuildMI(*MBB, IP, X86::SAHF, 1);
936 BuildMI(*MBB, IP, X86::FpUCOMI, 2).addReg(Op0r).addReg(Op1r);
941 if (OpNum < 2) { // seteq, setne
942 unsigned LoTmp = makeAnotherReg(Type::IntTy);
943 unsigned HiTmp = makeAnotherReg(Type::IntTy);
944 unsigned FinalTmp = makeAnotherReg(Type::IntTy);
945 BuildMI(*MBB, IP, X86::XOR32rr, 2, LoTmp).addReg(Op0r).addReg(Op1r);
946 BuildMI(*MBB, IP, X86::XOR32rr, 2, HiTmp).addReg(Op0r+1).addReg(Op1r+1);
947 BuildMI(*MBB, IP, X86::OR32rr, 2, FinalTmp).addReg(LoTmp).addReg(HiTmp);
948 break; // Allow the sete or setne to be generated from flags set by OR
950 // Emit a sequence of code which compares the high and low parts once
951 // each, then uses a conditional move to handle the overflow case. For
952 // example, a setlt for long would generate code like this:
954 // AL = lo(op1) < lo(op2) // Signedness depends on operands
955 // BL = hi(op1) < hi(op2) // Always unsigned comparison
956 // dest = hi(op1) == hi(op2) ? AL : BL;
959 // FIXME: This would be much better if we had hierarchical register
960 // classes! Until then, hardcode registers so that we can deal with their
961 // aliases (because we don't have conditional byte moves).
963 BuildMI(*MBB, IP, X86::CMP32rr, 2).addReg(Op0r).addReg(Op1r);
964 BuildMI(*MBB, IP, SetCCOpcodeTab[0][OpNum], 0, X86::AL);
965 BuildMI(*MBB, IP, X86::CMP32rr, 2).addReg(Op0r+1).addReg(Op1r+1);
966 BuildMI(*MBB, IP, SetCCOpcodeTab[CompTy->isSigned()][OpNum], 0, X86::BL);
967 BuildMI(*MBB, IP, X86::IMPLICIT_DEF, 0, X86::BH);
968 BuildMI(*MBB, IP, X86::IMPLICIT_DEF, 0, X86::AH);
969 BuildMI(*MBB, IP, X86::CMOVE16rr, 2, X86::BX).addReg(X86::BX)
971 // NOTE: visitSetCondInst knows that the value is dumped into the BL
972 // register at this point for long values...
979 /// SetCC instructions - Here we just emit boilerplate code to set a byte-sized
980 /// register, then move it to wherever the result should be.
982 void ISel::visitSetCondInst(SetCondInst &I) {
983 if (canFoldSetCCIntoBranchOrSelect(&I))
984 return; // Fold this into a branch or select.
986 unsigned DestReg = getReg(I);
987 MachineBasicBlock::iterator MII = BB->end();
988 emitSetCCOperation(BB, MII, I.getOperand(0), I.getOperand(1), I.getOpcode(),
992 /// emitSetCCOperation - Common code shared between visitSetCondInst and
993 /// constant expression support.
995 void ISel::emitSetCCOperation(MachineBasicBlock *MBB,
996 MachineBasicBlock::iterator IP,
997 Value *Op0, Value *Op1, unsigned Opcode,
998 unsigned TargetReg) {
999 unsigned OpNum = getSetCCNumber(Opcode);
1000 OpNum = EmitComparison(OpNum, Op0, Op1, MBB, IP);
1002 const Type *CompTy = Op0->getType();
1003 unsigned CompClass = getClassB(CompTy);
1004 bool isSigned = CompTy->isSigned() && CompClass != cFP;
1006 if (CompClass != cLong || OpNum < 2) {
1007 // Handle normal comparisons with a setcc instruction...
1008 BuildMI(*MBB, IP, SetCCOpcodeTab[isSigned][OpNum], 0, TargetReg);
1010 // Handle long comparisons by copying the value which is already in BL into
1011 // the register we want...
1012 BuildMI(*MBB, IP, X86::MOV8rr, 1, TargetReg).addReg(X86::BL);
1016 void ISel::visitSelectInst(SelectInst &SI) {
1017 unsigned DestReg = getReg(SI);
1018 MachineBasicBlock::iterator MII = BB->end();
1019 emitSelectOperation(BB, MII, SI.getCondition(), SI.getTrueValue(),
1020 SI.getFalseValue(), DestReg);
1023 /// emitSelect - Common code shared between visitSelectInst and the constant
1024 /// expression support.
1025 void ISel::emitSelectOperation(MachineBasicBlock *MBB,
1026 MachineBasicBlock::iterator IP,
1027 Value *Cond, Value *TrueVal, Value *FalseVal,
1029 unsigned SelectClass = getClassB(TrueVal->getType());
1031 // We don't support 8-bit conditional moves. If we have incoming constants,
1032 // transform them into 16-bit constants to avoid having a run-time conversion.
1033 if (SelectClass == cByte) {
1034 if (Constant *T = dyn_cast<Constant>(TrueVal))
1035 TrueVal = ConstantExpr::getCast(T, Type::ShortTy);
1036 if (Constant *F = dyn_cast<Constant>(FalseVal))
1037 FalseVal = ConstantExpr::getCast(F, Type::ShortTy);
1040 unsigned TrueReg = getReg(TrueVal, MBB, IP);
1041 unsigned FalseReg = getReg(FalseVal, MBB, IP);
1042 if (TrueReg == FalseReg) {
1043 static const unsigned Opcode[] = {
1044 X86::MOV8rr, X86::MOV16rr, X86::MOV32rr, X86::FpMOV, X86::MOV32rr
1046 BuildMI(*MBB, IP, Opcode[SelectClass], 1, DestReg).addReg(TrueReg);
1047 if (SelectClass == cLong)
1048 BuildMI(*MBB, IP, X86::MOV32rr, 1, DestReg+1).addReg(TrueReg+1);
1053 if (SetCondInst *SCI = canFoldSetCCIntoBranchOrSelect(Cond)) {
1054 // We successfully folded the setcc into the select instruction.
1056 unsigned OpNum = getSetCCNumber(SCI->getOpcode());
1057 OpNum = EmitComparison(OpNum, SCI->getOperand(0), SCI->getOperand(1), MBB,
1060 const Type *CompTy = SCI->getOperand(0)->getType();
1061 bool isSigned = CompTy->isSigned() && getClassB(CompTy) != cFP;
1063 // LLVM -> X86 signed X86 unsigned
1064 // ----- ---------- ------------
1065 // seteq -> cmovNE cmovNE
1066 // setne -> cmovE cmovE
1067 // setlt -> cmovGE cmovAE
1068 // setge -> cmovL cmovB
1069 // setgt -> cmovLE cmovBE
1070 // setle -> cmovG cmovA
1072 // cmovNS // Used by comparison with 0 optimization
1075 switch (SelectClass) {
1076 default: assert(0 && "Unknown value class!");
1078 // Annoyingly, we don't have a full set of floating point conditional
1080 static const unsigned OpcodeTab[2][8] = {
1081 { X86::FCMOVNE, X86::FCMOVE, X86::FCMOVAE, X86::FCMOVB,
1082 X86::FCMOVBE, X86::FCMOVA, 0, 0 },
1083 { X86::FCMOVNE, X86::FCMOVE, 0, 0, 0, 0, 0, 0 },
1085 Opcode = OpcodeTab[isSigned][OpNum];
1087 // If opcode == 0, we hit a case that we don't support. Output a setcc
1088 // and compare the result against zero.
1090 unsigned CompClass = getClassB(CompTy);
1092 if (CompClass != cLong || OpNum < 2) {
1093 CondReg = makeAnotherReg(Type::BoolTy);
1094 // Handle normal comparisons with a setcc instruction...
1095 BuildMI(*MBB, IP, SetCCOpcodeTab[isSigned][OpNum], 0, CondReg);
1097 // Long comparisons end up in the BL register.
1101 BuildMI(*MBB, IP, X86::TEST8rr, 2).addReg(CondReg).addReg(CondReg);
1102 Opcode = X86::FCMOVE;
1108 static const unsigned OpcodeTab[2][8] = {
1109 { X86::CMOVNE16rr, X86::CMOVE16rr, X86::CMOVAE16rr, X86::CMOVB16rr,
1110 X86::CMOVBE16rr, X86::CMOVA16rr, 0, 0 },
1111 { X86::CMOVNE16rr, X86::CMOVE16rr, X86::CMOVGE16rr, X86::CMOVL16rr,
1112 X86::CMOVLE16rr, X86::CMOVG16rr, X86::CMOVNS16rr, X86::CMOVS16rr },
1114 Opcode = OpcodeTab[isSigned][OpNum];
1119 static const unsigned OpcodeTab[2][8] = {
1120 { X86::CMOVNE32rr, X86::CMOVE32rr, X86::CMOVAE32rr, X86::CMOVB32rr,
1121 X86::CMOVBE32rr, X86::CMOVA32rr, 0, 0 },
1122 { X86::CMOVNE32rr, X86::CMOVE32rr, X86::CMOVGE32rr, X86::CMOVL32rr,
1123 X86::CMOVLE32rr, X86::CMOVG32rr, X86::CMOVNS32rr, X86::CMOVS32rr },
1125 Opcode = OpcodeTab[isSigned][OpNum];
1130 // Get the value being branched on, and use it to set the condition codes.
1131 unsigned CondReg = getReg(Cond, MBB, IP);
1132 BuildMI(*MBB, IP, X86::TEST8rr, 2).addReg(CondReg).addReg(CondReg);
1133 switch (SelectClass) {
1134 default: assert(0 && "Unknown value class!");
1135 case cFP: Opcode = X86::FCMOVE; break;
1137 case cShort: Opcode = X86::CMOVE16rr; break;
1139 case cLong: Opcode = X86::CMOVE32rr; break;
1143 unsigned RealDestReg = DestReg;
1146 // Annoyingly enough, X86 doesn't HAVE 8-bit conditional moves. Because of
1147 // this, we have to promote the incoming values to 16 bits, perform a 16-bit
1148 // cmove, then truncate the result.
1149 if (SelectClass == cByte) {
1150 DestReg = makeAnotherReg(Type::ShortTy);
1151 if (getClassB(TrueVal->getType()) == cByte) {
1152 // Promote the true value, by storing it into AL, and reading from AX.
1153 BuildMI(*MBB, IP, X86::MOV8rr, 1, X86::AL).addReg(TrueReg);
1154 BuildMI(*MBB, IP, X86::MOV8ri, 1, X86::AH).addImm(0);
1155 TrueReg = makeAnotherReg(Type::ShortTy);
1156 BuildMI(*MBB, IP, X86::MOV16rr, 1, TrueReg).addReg(X86::AX);
1158 if (getClassB(FalseVal->getType()) == cByte) {
1159 // Promote the true value, by storing it into CL, and reading from CX.
1160 BuildMI(*MBB, IP, X86::MOV8rr, 1, X86::CL).addReg(FalseReg);
1161 BuildMI(*MBB, IP, X86::MOV8ri, 1, X86::CH).addImm(0);
1162 FalseReg = makeAnotherReg(Type::ShortTy);
1163 BuildMI(*MBB, IP, X86::MOV16rr, 1, FalseReg).addReg(X86::CX);
1167 BuildMI(*MBB, IP, Opcode, 2, DestReg).addReg(TrueReg).addReg(FalseReg);
1169 switch (SelectClass) {
1171 // We did the computation with 16-bit registers. Truncate back to our
1172 // result by copying into AX then copying out AL.
1173 BuildMI(*MBB, IP, X86::MOV16rr, 1, X86::AX).addReg(DestReg);
1174 BuildMI(*MBB, IP, X86::MOV8rr, 1, RealDestReg).addReg(X86::AL);
1177 // Move the upper half of the value as well.
1178 BuildMI(*MBB, IP, Opcode, 2,DestReg+1).addReg(TrueReg+1).addReg(FalseReg+1);
1185 /// promote32 - Emit instructions to turn a narrow operand into a 32-bit-wide
1186 /// operand, in the specified target register.
1188 void ISel::promote32(unsigned targetReg, const ValueRecord &VR) {
1189 bool isUnsigned = VR.Ty->isUnsigned();
1191 Value *Val = VR.Val;
1192 const Type *Ty = VR.Ty;
1194 if (Constant *C = dyn_cast<Constant>(Val)) {
1195 Val = ConstantExpr::getCast(C, Type::IntTy);
1199 // If this is a simple constant, just emit a MOVri directly to avoid the
1201 if (ConstantInt *CI = dyn_cast<ConstantInt>(Val)) {
1202 int TheVal = CI->getRawValue() & 0xFFFFFFFF;
1203 BuildMI(BB, X86::MOV32ri, 1, targetReg).addImm(TheVal);
1208 // Make sure we have the register number for this value...
1209 unsigned Reg = Val ? getReg(Val) : VR.Reg;
1211 switch (getClassB(Ty)) {
1213 // Extend value into target register (8->32)
1215 BuildMI(BB, X86::MOVZX32rr8, 1, targetReg).addReg(Reg);
1217 BuildMI(BB, X86::MOVSX32rr8, 1, targetReg).addReg(Reg);
1220 // Extend value into target register (16->32)
1222 BuildMI(BB, X86::MOVZX32rr16, 1, targetReg).addReg(Reg);
1224 BuildMI(BB, X86::MOVSX32rr16, 1, targetReg).addReg(Reg);
1227 // Move value into target register (32->32)
1228 BuildMI(BB, X86::MOV32rr, 1, targetReg).addReg(Reg);
1231 assert(0 && "Unpromotable operand class in promote32");
1235 /// 'ret' instruction - Here we are interested in meeting the x86 ABI. As such,
1236 /// we have the following possibilities:
1238 /// ret void: No return value, simply emit a 'ret' instruction
1239 /// ret sbyte, ubyte : Extend value into EAX and return
1240 /// ret short, ushort: Extend value into EAX and return
1241 /// ret int, uint : Move value into EAX and return
1242 /// ret pointer : Move value into EAX and return
1243 /// ret long, ulong : Move value into EAX/EDX and return
1244 /// ret float/double : Top of FP stack
1246 void ISel::visitReturnInst(ReturnInst &I) {
1247 if (I.getNumOperands() == 0) {
1248 BuildMI(BB, X86::RET, 0); // Just emit a 'ret' instruction
1252 Value *RetVal = I.getOperand(0);
1253 switch (getClassB(RetVal->getType())) {
1254 case cByte: // integral return values: extend or move into EAX and return
1257 promote32(X86::EAX, ValueRecord(RetVal));
1258 // Declare that EAX is live on exit
1259 BuildMI(BB, X86::IMPLICIT_USE, 2).addReg(X86::EAX).addReg(X86::ESP);
1261 case cFP: { // Floats & Doubles: Return in ST(0)
1262 unsigned RetReg = getReg(RetVal);
1263 BuildMI(BB, X86::FpSETRESULT, 1).addReg(RetReg);
1264 // Declare that top-of-stack is live on exit
1265 BuildMI(BB, X86::IMPLICIT_USE, 2).addReg(X86::ST0).addReg(X86::ESP);
1269 unsigned RetReg = getReg(RetVal);
1270 BuildMI(BB, X86::MOV32rr, 1, X86::EAX).addReg(RetReg);
1271 BuildMI(BB, X86::MOV32rr, 1, X86::EDX).addReg(RetReg+1);
1272 // Declare that EAX & EDX are live on exit
1273 BuildMI(BB, X86::IMPLICIT_USE, 3).addReg(X86::EAX).addReg(X86::EDX)
1278 visitInstruction(I);
1280 // Emit a 'ret' instruction
1281 BuildMI(BB, X86::RET, 0);
1284 // getBlockAfter - Return the basic block which occurs lexically after the
1286 static inline BasicBlock *getBlockAfter(BasicBlock *BB) {
1287 Function::iterator I = BB; ++I; // Get iterator to next block
1288 return I != BB->getParent()->end() ? &*I : 0;
1291 /// visitBranchInst - Handle conditional and unconditional branches here. Note
1292 /// that since code layout is frozen at this point, that if we are trying to
1293 /// jump to a block that is the immediate successor of the current block, we can
1294 /// just make a fall-through (but we don't currently).
1296 void ISel::visitBranchInst(BranchInst &BI) {
1297 // Update machine-CFG edges
1298 BB->addSuccessor (MBBMap[BI.getSuccessor(0)]);
1299 if (BI.isConditional())
1300 BB->addSuccessor (MBBMap[BI.getSuccessor(1)]);
1302 BasicBlock *NextBB = getBlockAfter(BI.getParent()); // BB after current one
1304 if (!BI.isConditional()) { // Unconditional branch?
1305 if (BI.getSuccessor(0) != NextBB)
1306 BuildMI(BB, X86::JMP, 1).addPCDisp(BI.getSuccessor(0));
1310 // See if we can fold the setcc into the branch itself...
1311 SetCondInst *SCI = canFoldSetCCIntoBranchOrSelect(BI.getCondition());
1313 // Nope, cannot fold setcc into this branch. Emit a branch on a condition
1314 // computed some other way...
1315 unsigned condReg = getReg(BI.getCondition());
1316 BuildMI(BB, X86::TEST8rr, 2).addReg(condReg).addReg(condReg);
1317 if (BI.getSuccessor(1) == NextBB) {
1318 if (BI.getSuccessor(0) != NextBB)
1319 BuildMI(BB, X86::JNE, 1).addPCDisp(BI.getSuccessor(0));
1321 BuildMI(BB, X86::JE, 1).addPCDisp(BI.getSuccessor(1));
1323 if (BI.getSuccessor(0) != NextBB)
1324 BuildMI(BB, X86::JMP, 1).addPCDisp(BI.getSuccessor(0));
1329 unsigned OpNum = getSetCCNumber(SCI->getOpcode());
1330 MachineBasicBlock::iterator MII = BB->end();
1331 OpNum = EmitComparison(OpNum, SCI->getOperand(0), SCI->getOperand(1), BB,MII);
1333 const Type *CompTy = SCI->getOperand(0)->getType();
1334 bool isSigned = CompTy->isSigned() && getClassB(CompTy) != cFP;
1337 // LLVM -> X86 signed X86 unsigned
1338 // ----- ---------- ------------
1346 // js // Used by comparison with 0 optimization
1349 static const unsigned OpcodeTab[2][8] = {
1350 { X86::JE, X86::JNE, X86::JB, X86::JAE, X86::JA, X86::JBE, 0, 0 },
1351 { X86::JE, X86::JNE, X86::JL, X86::JGE, X86::JG, X86::JLE,
1352 X86::JS, X86::JNS },
1355 if (BI.getSuccessor(0) != NextBB) {
1356 BuildMI(BB, OpcodeTab[isSigned][OpNum], 1).addPCDisp(BI.getSuccessor(0));
1357 if (BI.getSuccessor(1) != NextBB)
1358 BuildMI(BB, X86::JMP, 1).addPCDisp(BI.getSuccessor(1));
1360 // Change to the inverse condition...
1361 if (BI.getSuccessor(1) != NextBB) {
1363 BuildMI(BB, OpcodeTab[isSigned][OpNum], 1).addPCDisp(BI.getSuccessor(1));
1369 /// doCall - This emits an abstract call instruction, setting up the arguments
1370 /// and the return value as appropriate. For the actual function call itself,
1371 /// it inserts the specified CallMI instruction into the stream.
1373 void ISel::doCall(const ValueRecord &Ret, MachineInstr *CallMI,
1374 const std::vector<ValueRecord> &Args) {
1376 // Count how many bytes are to be pushed on the stack...
1377 unsigned NumBytes = 0;
1379 if (!Args.empty()) {
1380 for (unsigned i = 0, e = Args.size(); i != e; ++i)
1381 switch (getClassB(Args[i].Ty)) {
1382 case cByte: case cShort: case cInt:
1383 NumBytes += 4; break;
1385 NumBytes += 8; break;
1387 NumBytes += Args[i].Ty == Type::FloatTy ? 4 : 8;
1389 default: assert(0 && "Unknown class!");
1392 // Adjust the stack pointer for the new arguments...
1393 BuildMI(BB, X86::ADJCALLSTACKDOWN, 1).addImm(NumBytes);
1395 // Arguments go on the stack in reverse order, as specified by the ABI.
1396 unsigned ArgOffset = 0;
1397 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
1399 switch (getClassB(Args[i].Ty)) {
1402 if (Args[i].Val && isa<ConstantInt>(Args[i].Val)) {
1403 // Zero/Sign extend constant, then stuff into memory.
1404 ConstantInt *Val = cast<ConstantInt>(Args[i].Val);
1405 Val = cast<ConstantInt>(ConstantExpr::getCast(Val, Type::IntTy));
1406 addRegOffset(BuildMI(BB, X86::MOV32mi, 5), X86::ESP, ArgOffset)
1407 .addImm(Val->getRawValue() & 0xFFFFFFFF);
1409 // Promote arg to 32 bits wide into a temporary register...
1410 ArgReg = makeAnotherReg(Type::UIntTy);
1411 promote32(ArgReg, Args[i]);
1412 addRegOffset(BuildMI(BB, X86::MOV32mr, 5),
1413 X86::ESP, ArgOffset).addReg(ArgReg);
1417 if (Args[i].Val && isa<ConstantInt>(Args[i].Val)) {
1418 unsigned Val = cast<ConstantInt>(Args[i].Val)->getRawValue();
1419 addRegOffset(BuildMI(BB, X86::MOV32mi, 5),
1420 X86::ESP, ArgOffset).addImm(Val);
1422 ArgReg = Args[i].Val ? getReg(Args[i].Val) : Args[i].Reg;
1423 addRegOffset(BuildMI(BB, X86::MOV32mr, 5),
1424 X86::ESP, ArgOffset).addReg(ArgReg);
1428 if (Args[i].Val && isa<ConstantInt>(Args[i].Val)) {
1429 uint64_t Val = cast<ConstantInt>(Args[i].Val)->getRawValue();
1430 addRegOffset(BuildMI(BB, X86::MOV32mi, 5),
1431 X86::ESP, ArgOffset).addImm(Val & ~0U);
1432 addRegOffset(BuildMI(BB, X86::MOV32mi, 5),
1433 X86::ESP, ArgOffset+4).addImm(Val >> 32ULL);
1435 ArgReg = Args[i].Val ? getReg(Args[i].Val) : Args[i].Reg;
1436 addRegOffset(BuildMI(BB, X86::MOV32mr, 5),
1437 X86::ESP, ArgOffset).addReg(ArgReg);
1438 addRegOffset(BuildMI(BB, X86::MOV32mr, 5),
1439 X86::ESP, ArgOffset+4).addReg(ArgReg+1);
1441 ArgOffset += 4; // 8 byte entry, not 4.
1445 ArgReg = Args[i].Val ? getReg(Args[i].Val) : Args[i].Reg;
1446 if (Args[i].Ty == Type::FloatTy) {
1447 addRegOffset(BuildMI(BB, X86::FST32m, 5),
1448 X86::ESP, ArgOffset).addReg(ArgReg);
1450 assert(Args[i].Ty == Type::DoubleTy && "Unknown FP type!");
1451 addRegOffset(BuildMI(BB, X86::FST64m, 5),
1452 X86::ESP, ArgOffset).addReg(ArgReg);
1453 ArgOffset += 4; // 8 byte entry, not 4.
1457 default: assert(0 && "Unknown class!");
1462 BuildMI(BB, X86::ADJCALLSTACKDOWN, 1).addImm(0);
1465 BB->push_back(CallMI);
1467 BuildMI(BB, X86::ADJCALLSTACKUP, 1).addImm(NumBytes);
1469 // If there is a return value, scavenge the result from the location the call
1472 if (Ret.Ty != Type::VoidTy) {
1473 unsigned DestClass = getClassB(Ret.Ty);
1474 switch (DestClass) {
1478 // Integral results are in %eax, or the appropriate portion
1480 static const unsigned regRegMove[] = {
1481 X86::MOV8rr, X86::MOV16rr, X86::MOV32rr
1483 static const unsigned AReg[] = { X86::AL, X86::AX, X86::EAX };
1484 BuildMI(BB, regRegMove[DestClass], 1, Ret.Reg).addReg(AReg[DestClass]);
1487 case cFP: // Floating-point return values live in %ST(0)
1488 BuildMI(BB, X86::FpGETRESULT, 1, Ret.Reg);
1490 case cLong: // Long values are left in EDX:EAX
1491 BuildMI(BB, X86::MOV32rr, 1, Ret.Reg).addReg(X86::EAX);
1492 BuildMI(BB, X86::MOV32rr, 1, Ret.Reg+1).addReg(X86::EDX);
1494 default: assert(0 && "Unknown class!");
1500 /// visitCallInst - Push args on stack and do a procedure call instruction.
1501 void ISel::visitCallInst(CallInst &CI) {
1502 MachineInstr *TheCall;
1503 if (Function *F = CI.getCalledFunction()) {
1504 // Is it an intrinsic function call?
1505 if (Intrinsic::ID ID = (Intrinsic::ID)F->getIntrinsicID()) {
1506 visitIntrinsicCall(ID, CI); // Special intrinsics are not handled here
1510 // Emit a CALL instruction with PC-relative displacement.
1511 TheCall = BuildMI(X86::CALLpcrel32, 1).addGlobalAddress(F, true);
1512 } else { // Emit an indirect call...
1513 unsigned Reg = getReg(CI.getCalledValue());
1514 TheCall = BuildMI(X86::CALL32r, 1).addReg(Reg);
1517 std::vector<ValueRecord> Args;
1518 for (unsigned i = 1, e = CI.getNumOperands(); i != e; ++i)
1519 Args.push_back(ValueRecord(CI.getOperand(i)));
1521 unsigned DestReg = CI.getType() != Type::VoidTy ? getReg(CI) : 0;
1522 doCall(ValueRecord(DestReg, CI.getType()), TheCall, Args);
1526 /// LowerUnknownIntrinsicFunctionCalls - This performs a prepass over the
1527 /// function, lowering any calls to unknown intrinsic functions into the
1528 /// equivalent LLVM code.
1530 void ISel::LowerUnknownIntrinsicFunctionCalls(Function &F) {
1531 for (Function::iterator BB = F.begin(), E = F.end(); BB != E; ++BB)
1532 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; )
1533 if (CallInst *CI = dyn_cast<CallInst>(I++))
1534 if (Function *F = CI->getCalledFunction())
1535 switch (F->getIntrinsicID()) {
1536 case Intrinsic::not_intrinsic:
1537 case Intrinsic::vastart:
1538 case Intrinsic::vacopy:
1539 case Intrinsic::vaend:
1540 case Intrinsic::returnaddress:
1541 case Intrinsic::frameaddress:
1542 case Intrinsic::memcpy:
1543 case Intrinsic::memset:
1544 case Intrinsic::readport:
1545 case Intrinsic::writeport:
1546 // We directly implement these intrinsics
1548 case Intrinsic::readio: {
1549 // On X86, memory operations are in-order. Lower this intrinsic
1550 // into a volatile load.
1551 Instruction *Before = CI->getPrev();
1552 LoadInst * LI = new LoadInst (CI->getOperand(1), "", true, CI);
1553 CI->replaceAllUsesWith (LI);
1554 BB->getInstList().erase (CI);
1557 case Intrinsic::writeio: {
1558 // On X86, memory operations are in-order. Lower this intrinsic
1559 // into a volatile store.
1560 Instruction *Before = CI->getPrev();
1561 StoreInst * LI = new StoreInst (CI->getOperand(1),
1562 CI->getOperand(2), true, CI);
1563 CI->replaceAllUsesWith (LI);
1564 BB->getInstList().erase (CI);
1568 // All other intrinsic calls we must lower.
1569 Instruction *Before = CI->getPrev();
1570 TM.getIntrinsicLowering().LowerIntrinsicCall(CI);
1571 if (Before) { // Move iterator to instruction after call
1580 void ISel::visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI) {
1581 unsigned TmpReg1, TmpReg2;
1583 case Intrinsic::vastart:
1584 // Get the address of the first vararg value...
1585 TmpReg1 = getReg(CI);
1586 addFrameReference(BuildMI(BB, X86::LEA32r, 5, TmpReg1), VarArgsFrameIndex);
1589 case Intrinsic::vacopy:
1590 TmpReg1 = getReg(CI);
1591 TmpReg2 = getReg(CI.getOperand(1));
1592 BuildMI(BB, X86::MOV32rr, 1, TmpReg1).addReg(TmpReg2);
1594 case Intrinsic::vaend: return; // Noop on X86
1596 case Intrinsic::returnaddress:
1597 case Intrinsic::frameaddress:
1598 TmpReg1 = getReg(CI);
1599 if (cast<Constant>(CI.getOperand(1))->isNullValue()) {
1600 if (ID == Intrinsic::returnaddress) {
1601 // Just load the return address
1602 addFrameReference(BuildMI(BB, X86::MOV32rm, 4, TmpReg1),
1603 ReturnAddressIndex);
1605 addFrameReference(BuildMI(BB, X86::LEA32r, 4, TmpReg1),
1606 ReturnAddressIndex, -4);
1609 // Values other than zero are not implemented yet.
1610 BuildMI(BB, X86::MOV32ri, 1, TmpReg1).addImm(0);
1614 case Intrinsic::memcpy: {
1615 assert(CI.getNumOperands() == 5 && "Illegal llvm.memcpy call!");
1617 if (ConstantInt *AlignC = dyn_cast<ConstantInt>(CI.getOperand(4))) {
1618 Align = AlignC->getRawValue();
1619 if (Align == 0) Align = 1;
1622 // Turn the byte code into # iterations
1625 switch (Align & 3) {
1626 case 2: // WORD aligned
1627 if (ConstantInt *I = dyn_cast<ConstantInt>(CI.getOperand(3))) {
1628 CountReg = getReg(ConstantUInt::get(Type::UIntTy, I->getRawValue()/2));
1630 CountReg = makeAnotherReg(Type::IntTy);
1631 unsigned ByteReg = getReg(CI.getOperand(3));
1632 BuildMI(BB, X86::SHR32ri, 2, CountReg).addReg(ByteReg).addImm(1);
1634 Opcode = X86::REP_MOVSW;
1636 case 0: // DWORD aligned
1637 if (ConstantInt *I = dyn_cast<ConstantInt>(CI.getOperand(3))) {
1638 CountReg = getReg(ConstantUInt::get(Type::UIntTy, I->getRawValue()/4));
1640 CountReg = makeAnotherReg(Type::IntTy);
1641 unsigned ByteReg = getReg(CI.getOperand(3));
1642 BuildMI(BB, X86::SHR32ri, 2, CountReg).addReg(ByteReg).addImm(2);
1644 Opcode = X86::REP_MOVSD;
1646 default: // BYTE aligned
1647 CountReg = getReg(CI.getOperand(3));
1648 Opcode = X86::REP_MOVSB;
1652 // No matter what the alignment is, we put the source in ESI, the
1653 // destination in EDI, and the count in ECX.
1654 TmpReg1 = getReg(CI.getOperand(1));
1655 TmpReg2 = getReg(CI.getOperand(2));
1656 BuildMI(BB, X86::MOV32rr, 1, X86::ECX).addReg(CountReg);
1657 BuildMI(BB, X86::MOV32rr, 1, X86::EDI).addReg(TmpReg1);
1658 BuildMI(BB, X86::MOV32rr, 1, X86::ESI).addReg(TmpReg2);
1659 BuildMI(BB, Opcode, 0);
1662 case Intrinsic::memset: {
1663 assert(CI.getNumOperands() == 5 && "Illegal llvm.memset call!");
1665 if (ConstantInt *AlignC = dyn_cast<ConstantInt>(CI.getOperand(4))) {
1666 Align = AlignC->getRawValue();
1667 if (Align == 0) Align = 1;
1670 // Turn the byte code into # iterations
1673 if (ConstantInt *ValC = dyn_cast<ConstantInt>(CI.getOperand(2))) {
1674 unsigned Val = ValC->getRawValue() & 255;
1676 // If the value is a constant, then we can potentially use larger copies.
1677 switch (Align & 3) {
1678 case 2: // WORD aligned
1679 if (ConstantInt *I = dyn_cast<ConstantInt>(CI.getOperand(3))) {
1680 CountReg =getReg(ConstantUInt::get(Type::UIntTy, I->getRawValue()/2));
1682 CountReg = makeAnotherReg(Type::IntTy);
1683 unsigned ByteReg = getReg(CI.getOperand(3));
1684 BuildMI(BB, X86::SHR32ri, 2, CountReg).addReg(ByteReg).addImm(1);
1686 BuildMI(BB, X86::MOV16ri, 1, X86::AX).addImm((Val << 8) | Val);
1687 Opcode = X86::REP_STOSW;
1689 case 0: // DWORD aligned
1690 if (ConstantInt *I = dyn_cast<ConstantInt>(CI.getOperand(3))) {
1691 CountReg =getReg(ConstantUInt::get(Type::UIntTy, I->getRawValue()/4));
1693 CountReg = makeAnotherReg(Type::IntTy);
1694 unsigned ByteReg = getReg(CI.getOperand(3));
1695 BuildMI(BB, X86::SHR32ri, 2, CountReg).addReg(ByteReg).addImm(2);
1697 Val = (Val << 8) | Val;
1698 BuildMI(BB, X86::MOV32ri, 1, X86::EAX).addImm((Val << 16) | Val);
1699 Opcode = X86::REP_STOSD;
1701 default: // BYTE aligned
1702 CountReg = getReg(CI.getOperand(3));
1703 BuildMI(BB, X86::MOV8ri, 1, X86::AL).addImm(Val);
1704 Opcode = X86::REP_STOSB;
1708 // If it's not a constant value we are storing, just fall back. We could
1709 // try to be clever to form 16 bit and 32 bit values, but we don't yet.
1710 unsigned ValReg = getReg(CI.getOperand(2));
1711 BuildMI(BB, X86::MOV8rr, 1, X86::AL).addReg(ValReg);
1712 CountReg = getReg(CI.getOperand(3));
1713 Opcode = X86::REP_STOSB;
1716 // No matter what the alignment is, we put the source in ESI, the
1717 // destination in EDI, and the count in ECX.
1718 TmpReg1 = getReg(CI.getOperand(1));
1719 //TmpReg2 = getReg(CI.getOperand(2));
1720 BuildMI(BB, X86::MOV32rr, 1, X86::ECX).addReg(CountReg);
1721 BuildMI(BB, X86::MOV32rr, 1, X86::EDI).addReg(TmpReg1);
1722 BuildMI(BB, Opcode, 0);
1726 case Intrinsic::readport: {
1727 // First, determine that the size of the operand falls within the acceptable
1728 // range for this architecture.
1730 if (getClassB(CI.getOperand(1)->getType()) != cShort) {
1731 std::cerr << "llvm.readport: Address size is not 16 bits\n";
1735 // Now, move the I/O port address into the DX register and use the IN
1736 // instruction to get the input data.
1738 unsigned Class = getClass(CI.getCalledFunction()->getReturnType());
1739 unsigned DestReg = getReg(CI);
1741 // If the port is a single-byte constant, use the immediate form.
1742 if (ConstantInt *C = dyn_cast<ConstantInt>(CI.getOperand(1)))
1743 if ((C->getRawValue() & 255) == C->getRawValue()) {
1746 BuildMI(BB, X86::IN8ri, 1).addImm((unsigned char)C->getRawValue());
1747 BuildMI(BB, X86::MOV8rr, 1, DestReg).addReg(X86::AL);
1750 BuildMI(BB, X86::IN16ri, 1).addImm((unsigned char)C->getRawValue());
1751 BuildMI(BB, X86::MOV8rr, 1, DestReg).addReg(X86::AX);
1754 BuildMI(BB, X86::IN32ri, 1).addImm((unsigned char)C->getRawValue());
1755 BuildMI(BB, X86::MOV8rr, 1, DestReg).addReg(X86::EAX);
1760 unsigned Reg = getReg(CI.getOperand(1));
1761 BuildMI(BB, X86::MOV16rr, 1, X86::DX).addReg(Reg);
1764 BuildMI(BB, X86::IN8rr, 0);
1765 BuildMI(BB, X86::MOV8rr, 1, DestReg).addReg(X86::AL);
1768 BuildMI(BB, X86::IN16rr, 0);
1769 BuildMI(BB, X86::MOV8rr, 1, DestReg).addReg(X86::AX);
1772 BuildMI(BB, X86::IN32rr, 0);
1773 BuildMI(BB, X86::MOV8rr, 1, DestReg).addReg(X86::EAX);
1776 std::cerr << "Cannot do input on this data type";
1782 case Intrinsic::writeport: {
1783 // First, determine that the size of the operand falls within the
1784 // acceptable range for this architecture.
1785 if (getClass(CI.getOperand(2)->getType()) != cShort) {
1786 std::cerr << "llvm.writeport: Address size is not 16 bits\n";
1790 unsigned Class = getClassB(CI.getOperand(1)->getType());
1791 unsigned ValReg = getReg(CI.getOperand(1));
1794 BuildMI(BB, X86::MOV8rr, 1, X86::AL).addReg(ValReg);
1797 BuildMI(BB, X86::MOV16rr, 1, X86::AX).addReg(ValReg);
1800 BuildMI(BB, X86::MOV32rr, 1, X86::EAX).addReg(ValReg);
1803 std::cerr << "llvm.writeport: invalid data type for X86 target";
1808 // If the port is a single-byte constant, use the immediate form.
1809 if (ConstantInt *C = dyn_cast<ConstantInt>(CI.getOperand(2)))
1810 if ((C->getRawValue() & 255) == C->getRawValue()) {
1811 static const unsigned O[] = { X86::OUT8ir, X86::OUT16ir, X86::OUT32ir };
1812 BuildMI(BB, O[Class], 1).addImm((unsigned char)C->getRawValue());
1816 // Otherwise, move the I/O port address into the DX register and the value
1817 // to write into the AL/AX/EAX register.
1818 static const unsigned Opc[] = { X86::OUT8rr, X86::OUT16rr, X86::OUT32rr };
1819 unsigned Reg = getReg(CI.getOperand(2));
1820 BuildMI(BB, X86::MOV16rr, 1, X86::DX).addReg(Reg);
1821 BuildMI(BB, Opc[Class], 0);
1825 default: assert(0 && "Error: unknown intrinsics should have been lowered!");
1829 static bool isSafeToFoldLoadIntoInstruction(LoadInst &LI, Instruction &User) {
1830 if (LI.getParent() != User.getParent())
1832 BasicBlock::iterator It = &LI;
1833 // Check all of the instructions between the load and the user. We should
1834 // really use alias analysis here, but for now we just do something simple.
1835 for (++It; It != BasicBlock::iterator(&User); ++It) {
1836 switch (It->getOpcode()) {
1837 case Instruction::Free:
1838 case Instruction::Store:
1839 case Instruction::Call:
1840 case Instruction::Invoke:
1842 case Instruction::Load:
1843 if (cast<LoadInst>(It)->isVolatile() && LI.isVolatile())
1851 /// visitSimpleBinary - Implement simple binary operators for integral types...
1852 /// OperatorClass is one of: 0 for Add, 1 for Sub, 2 for And, 3 for Or, 4 for
1855 void ISel::visitSimpleBinary(BinaryOperator &B, unsigned OperatorClass) {
1856 unsigned DestReg = getReg(B);
1857 MachineBasicBlock::iterator MI = BB->end();
1858 Value *Op0 = B.getOperand(0), *Op1 = B.getOperand(1);
1860 // Special case: op Reg, load [mem]
1861 if (isa<LoadInst>(Op0) && !isa<LoadInst>(Op1))
1862 if (!B.swapOperands())
1863 std::swap(Op0, Op1); // Make sure any loads are in the RHS.
1865 unsigned Class = getClassB(B.getType());
1866 if (isa<LoadInst>(Op1) && Class != cLong &&
1867 isSafeToFoldLoadIntoInstruction(*cast<LoadInst>(Op1), B)) {
1871 static const unsigned OpcodeTab[][3] = {
1872 // Arithmetic operators
1873 { X86::ADD8rm, X86::ADD16rm, X86::ADD32rm }, // ADD
1874 { X86::SUB8rm, X86::SUB16rm, X86::SUB32rm }, // SUB
1876 // Bitwise operators
1877 { X86::AND8rm, X86::AND16rm, X86::AND32rm }, // AND
1878 { X86:: OR8rm, X86:: OR16rm, X86:: OR32rm }, // OR
1879 { X86::XOR8rm, X86::XOR16rm, X86::XOR32rm }, // XOR
1881 Opcode = OpcodeTab[OperatorClass][Class];
1883 static const unsigned OpcodeTab[][2] = {
1884 { X86::FADD32m, X86::FADD64m }, // ADD
1885 { X86::FSUB32m, X86::FSUB64m }, // SUB
1887 const Type *Ty = Op0->getType();
1888 assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!");
1889 Opcode = OpcodeTab[OperatorClass][Ty == Type::DoubleTy];
1892 unsigned BaseReg, Scale, IndexReg, Disp;
1893 getAddressingMode(cast<LoadInst>(Op1)->getOperand(0), BaseReg,
1894 Scale, IndexReg, Disp);
1896 unsigned Op0r = getReg(Op0);
1897 addFullAddress(BuildMI(BB, Opcode, 2, DestReg).addReg(Op0r),
1898 BaseReg, Scale, IndexReg, Disp);
1902 // If this is a floating point subtract, check to see if we can fold the first
1904 if (Class == cFP && OperatorClass == 1 &&
1905 isa<LoadInst>(Op0) &&
1906 isSafeToFoldLoadIntoInstruction(*cast<LoadInst>(Op0), B)) {
1907 const Type *Ty = Op0->getType();
1908 assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!");
1909 unsigned Opcode = Ty == Type::FloatTy ? X86::FSUBR32m : X86::FSUBR64m;
1911 unsigned BaseReg, Scale, IndexReg, Disp;
1912 getAddressingMode(cast<LoadInst>(Op0)->getOperand(0), BaseReg,
1913 Scale, IndexReg, Disp);
1915 unsigned Op1r = getReg(Op1);
1916 addFullAddress(BuildMI(BB, Opcode, 2, DestReg).addReg(Op1r),
1917 BaseReg, Scale, IndexReg, Disp);
1921 emitSimpleBinaryOperation(BB, MI, Op0, Op1, OperatorClass, DestReg);
1925 /// emitBinaryFPOperation - This method handles emission of floating point
1926 /// Add (0), Sub (1), Mul (2), and Div (3) operations.
1927 void ISel::emitBinaryFPOperation(MachineBasicBlock *BB,
1928 MachineBasicBlock::iterator IP,
1929 Value *Op0, Value *Op1,
1930 unsigned OperatorClass, unsigned DestReg) {
1932 // Special case: op Reg, <const fp>
1933 if (ConstantFP *Op1C = dyn_cast<ConstantFP>(Op1))
1934 if (!Op1C->isExactlyValue(+0.0) && !Op1C->isExactlyValue(+1.0)) {
1935 // Create a constant pool entry for this constant.
1936 MachineConstantPool *CP = F->getConstantPool();
1937 unsigned CPI = CP->getConstantPoolIndex(Op1C);
1938 const Type *Ty = Op1->getType();
1940 static const unsigned OpcodeTab[][4] = {
1941 { X86::FADD32m, X86::FSUB32m, X86::FMUL32m, X86::FDIV32m }, // Float
1942 { X86::FADD64m, X86::FSUB64m, X86::FMUL64m, X86::FDIV64m }, // Double
1945 assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!");
1946 unsigned Opcode = OpcodeTab[Ty != Type::FloatTy][OperatorClass];
1947 unsigned Op0r = getReg(Op0, BB, IP);
1948 addConstantPoolReference(BuildMI(*BB, IP, Opcode, 5,
1949 DestReg).addReg(Op0r), CPI);
1953 // Special case: R1 = op <const fp>, R2
1954 if (ConstantFP *CFP = dyn_cast<ConstantFP>(Op0))
1955 if (CFP->isExactlyValue(-0.0) && OperatorClass == 1) {
1957 unsigned op1Reg = getReg(Op1, BB, IP);
1958 BuildMI(*BB, IP, X86::FCHS, 1, DestReg).addReg(op1Reg);
1960 } else if (!CFP->isExactlyValue(+0.0) && !CFP->isExactlyValue(+1.0)) {
1961 // R1 = op CST, R2 --> R1 = opr R2, CST
1963 // Create a constant pool entry for this constant.
1964 MachineConstantPool *CP = F->getConstantPool();
1965 unsigned CPI = CP->getConstantPoolIndex(CFP);
1966 const Type *Ty = CFP->getType();
1968 static const unsigned OpcodeTab[][4] = {
1969 { X86::FADD32m, X86::FSUBR32m, X86::FMUL32m, X86::FDIVR32m }, // Float
1970 { X86::FADD64m, X86::FSUBR64m, X86::FMUL64m, X86::FDIVR64m }, // Double
1973 assert(Ty == Type::FloatTy||Ty == Type::DoubleTy && "Unknown FP type!");
1974 unsigned Opcode = OpcodeTab[Ty != Type::FloatTy][OperatorClass];
1975 unsigned Op1r = getReg(Op1, BB, IP);
1976 addConstantPoolReference(BuildMI(*BB, IP, Opcode, 5,
1977 DestReg).addReg(Op1r), CPI);
1982 static const unsigned OpcodeTab[4] = {
1983 X86::FpADD, X86::FpSUB, X86::FpMUL, X86::FpDIV
1986 unsigned Opcode = OpcodeTab[OperatorClass];
1987 unsigned Op0r = getReg(Op0, BB, IP);
1988 unsigned Op1r = getReg(Op1, BB, IP);
1989 BuildMI(*BB, IP, Opcode, 2, DestReg).addReg(Op0r).addReg(Op1r);
1992 /// emitSimpleBinaryOperation - Implement simple binary operators for integral
1993 /// types... OperatorClass is one of: 0 for Add, 1 for Sub, 2 for And, 3 for
1996 /// emitSimpleBinaryOperation - Common code shared between visitSimpleBinary
1997 /// and constant expression support.
1999 void ISel::emitSimpleBinaryOperation(MachineBasicBlock *MBB,
2000 MachineBasicBlock::iterator IP,
2001 Value *Op0, Value *Op1,
2002 unsigned OperatorClass, unsigned DestReg) {
2003 unsigned Class = getClassB(Op0->getType());
2006 assert(OperatorClass < 2 && "No logical ops for FP!");
2007 emitBinaryFPOperation(MBB, IP, Op0, Op1, OperatorClass, DestReg);
2011 // sub 0, X -> neg X
2012 if (ConstantInt *CI = dyn_cast<ConstantInt>(Op0))
2013 if (OperatorClass == 1 && CI->isNullValue()) {
2014 unsigned op1Reg = getReg(Op1, MBB, IP);
2015 static unsigned const NEGTab[] = {
2016 X86::NEG8r, X86::NEG16r, X86::NEG32r, 0, X86::NEG32r
2018 BuildMI(*MBB, IP, NEGTab[Class], 1, DestReg).addReg(op1Reg);
2020 if (Class == cLong) {
2021 // We just emitted: Dl = neg Sl
2022 // Now emit : T = addc Sh, 0
2024 unsigned T = makeAnotherReg(Type::IntTy);
2025 BuildMI(*MBB, IP, X86::ADC32ri, 2, T).addReg(op1Reg+1).addImm(0);
2026 BuildMI(*MBB, IP, X86::NEG32r, 1, DestReg+1).addReg(T);
2031 // Special case: op Reg, <const int>
2032 if (ConstantInt *Op1C = dyn_cast<ConstantInt>(Op1)) {
2033 unsigned Op0r = getReg(Op0, MBB, IP);
2035 // xor X, -1 -> not X
2036 if (OperatorClass == 4 && Op1C->isAllOnesValue()) {
2037 static unsigned const NOTTab[] = {
2038 X86::NOT8r, X86::NOT16r, X86::NOT32r, 0, X86::NOT32r
2040 BuildMI(*MBB, IP, NOTTab[Class], 1, DestReg).addReg(Op0r);
2041 if (Class == cLong) // Invert the top part too
2042 BuildMI(*MBB, IP, X86::NOT32r, 1, DestReg+1).addReg(Op0r+1);
2046 // add X, -1 -> dec X
2047 if (OperatorClass == 0 && Op1C->isAllOnesValue() && Class != cLong) {
2048 // Note that we can't use dec for 64-bit decrements, because it does not
2049 // set the carry flag!
2050 static unsigned const DECTab[] = { X86::DEC8r, X86::DEC16r, X86::DEC32r };
2051 BuildMI(*MBB, IP, DECTab[Class], 1, DestReg).addReg(Op0r);
2055 // add X, 1 -> inc X
2056 if (OperatorClass == 0 && Op1C->equalsInt(1) && Class != cLong) {
2057 // Note that we can't use inc for 64-bit increments, because it does not
2058 // set the carry flag!
2059 static unsigned const INCTab[] = { X86::INC8r, X86::INC16r, X86::INC32r };
2060 BuildMI(*MBB, IP, INCTab[Class], 1, DestReg).addReg(Op0r);
2064 static const unsigned OpcodeTab[][5] = {
2065 // Arithmetic operators
2066 { X86::ADD8ri, X86::ADD16ri, X86::ADD32ri, 0, X86::ADD32ri }, // ADD
2067 { X86::SUB8ri, X86::SUB16ri, X86::SUB32ri, 0, X86::SUB32ri }, // SUB
2069 // Bitwise operators
2070 { X86::AND8ri, X86::AND16ri, X86::AND32ri, 0, X86::AND32ri }, // AND
2071 { X86:: OR8ri, X86:: OR16ri, X86:: OR32ri, 0, X86::OR32ri }, // OR
2072 { X86::XOR8ri, X86::XOR16ri, X86::XOR32ri, 0, X86::XOR32ri }, // XOR
2075 unsigned Opcode = OpcodeTab[OperatorClass][Class];
2076 unsigned Op1l = cast<ConstantInt>(Op1C)->getRawValue();
2078 if (Class != cLong) {
2079 BuildMI(*MBB, IP, Opcode, 2, DestReg).addReg(Op0r).addImm(Op1l);
2083 // If this is a long value and the high or low bits have a special
2084 // property, emit some special cases.
2085 unsigned Op1h = cast<ConstantInt>(Op1C)->getRawValue() >> 32LL;
2087 // If the constant is zero in the low 32-bits, just copy the low part
2088 // across and apply the normal 32-bit operation to the high parts. There
2089 // will be no carry or borrow into the top.
2091 if (OperatorClass != 2) // All but and...
2092 BuildMI(*MBB, IP, X86::MOV32rr, 1, DestReg).addReg(Op0r);
2094 BuildMI(*MBB, IP, X86::MOV32ri, 1, DestReg).addImm(0);
2095 BuildMI(*MBB, IP, OpcodeTab[OperatorClass][cLong], 2, DestReg+1)
2096 .addReg(Op0r+1).addImm(Op1h);
2100 // If this is a logical operation and the top 32-bits are zero, just
2101 // operate on the lower 32.
2102 if (Op1h == 0 && OperatorClass > 1) {
2103 BuildMI(*MBB, IP, OpcodeTab[OperatorClass][cLong], 2, DestReg)
2104 .addReg(Op0r).addImm(Op1l);
2105 if (OperatorClass != 2) // All but and
2106 BuildMI(*MBB, IP, X86::MOV32rr, 1, DestReg+1).addReg(Op0r+1);
2108 BuildMI(*MBB, IP, X86::MOV32ri, 1, DestReg+1).addImm(0);
2112 // TODO: We could handle lots of other special cases here, such as AND'ing
2113 // with 0xFFFFFFFF00000000 -> noop, etc.
2115 // Otherwise, code generate the full operation with a constant.
2116 static const unsigned TopTab[] = {
2117 X86::ADC32ri, X86::SBB32ri, X86::AND32ri, X86::OR32ri, X86::XOR32ri
2120 BuildMI(*MBB, IP, Opcode, 2, DestReg).addReg(Op0r).addImm(Op1l);
2121 BuildMI(*MBB, IP, TopTab[OperatorClass], 2, DestReg+1)
2122 .addReg(Op0r+1).addImm(Op1h);
2126 // Finally, handle the general case now.
2127 static const unsigned OpcodeTab[][5] = {
2128 // Arithmetic operators
2129 { X86::ADD8rr, X86::ADD16rr, X86::ADD32rr, 0, X86::ADD32rr }, // ADD
2130 { X86::SUB8rr, X86::SUB16rr, X86::SUB32rr, 0, X86::SUB32rr }, // SUB
2132 // Bitwise operators
2133 { X86::AND8rr, X86::AND16rr, X86::AND32rr, 0, X86::AND32rr }, // AND
2134 { X86:: OR8rr, X86:: OR16rr, X86:: OR32rr, 0, X86:: OR32rr }, // OR
2135 { X86::XOR8rr, X86::XOR16rr, X86::XOR32rr, 0, X86::XOR32rr }, // XOR
2138 unsigned Opcode = OpcodeTab[OperatorClass][Class];
2139 unsigned Op0r = getReg(Op0, MBB, IP);
2140 unsigned Op1r = getReg(Op1, MBB, IP);
2141 BuildMI(*MBB, IP, Opcode, 2, DestReg).addReg(Op0r).addReg(Op1r);
2143 if (Class == cLong) { // Handle the upper 32 bits of long values...
2144 static const unsigned TopTab[] = {
2145 X86::ADC32rr, X86::SBB32rr, X86::AND32rr, X86::OR32rr, X86::XOR32rr
2147 BuildMI(*MBB, IP, TopTab[OperatorClass], 2,
2148 DestReg+1).addReg(Op0r+1).addReg(Op1r+1);
2152 /// doMultiply - Emit appropriate instructions to multiply together the
2153 /// registers op0Reg and op1Reg, and put the result in DestReg. The type of the
2154 /// result should be given as DestTy.
2156 void ISel::doMultiply(MachineBasicBlock *MBB, MachineBasicBlock::iterator MBBI,
2157 unsigned DestReg, const Type *DestTy,
2158 unsigned op0Reg, unsigned op1Reg) {
2159 unsigned Class = getClass(DestTy);
2163 BuildMI(*MBB, MBBI, Class == cInt ? X86::IMUL32rr:X86::IMUL16rr, 2, DestReg)
2164 .addReg(op0Reg).addReg(op1Reg);
2167 // Must use the MUL instruction, which forces use of AL...
2168 BuildMI(*MBB, MBBI, X86::MOV8rr, 1, X86::AL).addReg(op0Reg);
2169 BuildMI(*MBB, MBBI, X86::MUL8r, 1).addReg(op1Reg);
2170 BuildMI(*MBB, MBBI, X86::MOV8rr, 1, DestReg).addReg(X86::AL);
2173 case cLong: assert(0 && "doMultiply cannot operate on LONG values!");
2177 // ExactLog2 - This function solves for (Val == 1 << (N-1)) and returns N. It
2178 // returns zero when the input is not exactly a power of two.
2179 static unsigned ExactLog2(unsigned Val) {
2180 if (Val == 0) return 0;
2183 if (Val & 1) return 0;
2191 /// doMultiplyConst - This function is specialized to efficiently codegen an 8,
2192 /// 16, or 32-bit integer multiply by a constant.
2193 void ISel::doMultiplyConst(MachineBasicBlock *MBB,
2194 MachineBasicBlock::iterator IP,
2195 unsigned DestReg, const Type *DestTy,
2196 unsigned op0Reg, unsigned ConstRHS) {
2197 static const unsigned MOVrrTab[] = {X86::MOV8rr, X86::MOV16rr, X86::MOV32rr};
2198 static const unsigned MOVriTab[] = {X86::MOV8ri, X86::MOV16ri, X86::MOV32ri};
2200 unsigned Class = getClass(DestTy);
2202 if (ConstRHS == 0) {
2203 BuildMI(*MBB, IP, MOVriTab[Class], 1, DestReg).addImm(0);
2205 } else if (ConstRHS == 1) {
2206 BuildMI(*MBB, IP, MOVrrTab[Class], 1, DestReg).addReg(op0Reg);
2210 // If the element size is exactly a power of 2, use a shift to get it.
2211 if (unsigned Shift = ExactLog2(ConstRHS)) {
2213 default: assert(0 && "Unknown class for this function!");
2215 BuildMI(*MBB, IP, X86::SHL32ri,2, DestReg).addReg(op0Reg).addImm(Shift-1);
2218 BuildMI(*MBB, IP, X86::SHL32ri,2, DestReg).addReg(op0Reg).addImm(Shift-1);
2221 BuildMI(*MBB, IP, X86::SHL32ri,2, DestReg).addReg(op0Reg).addImm(Shift-1);
2226 if (Class == cShort) {
2227 BuildMI(*MBB, IP, X86::IMUL16rri,2,DestReg).addReg(op0Reg).addImm(ConstRHS);
2229 } else if (Class == cInt) {
2230 BuildMI(*MBB, IP, X86::IMUL32rri,2,DestReg).addReg(op0Reg).addImm(ConstRHS);
2234 // Most general case, emit a normal multiply...
2235 unsigned TmpReg = makeAnotherReg(DestTy);
2236 BuildMI(*MBB, IP, MOVriTab[Class], 1, TmpReg).addImm(ConstRHS);
2238 // Emit a MUL to multiply the register holding the index by
2239 // elementSize, putting the result in OffsetReg.
2240 doMultiply(MBB, IP, DestReg, DestTy, op0Reg, TmpReg);
2243 /// visitMul - Multiplies are not simple binary operators because they must deal
2244 /// with the EAX register explicitly.
2246 void ISel::visitMul(BinaryOperator &I) {
2247 unsigned ResultReg = getReg(I);
2249 Value *Op0 = I.getOperand(0);
2250 Value *Op1 = I.getOperand(1);
2252 // Fold loads into floating point multiplies.
2253 if (getClass(Op0->getType()) == cFP) {
2254 if (isa<LoadInst>(Op0) && !isa<LoadInst>(Op1))
2255 if (!I.swapOperands())
2256 std::swap(Op0, Op1); // Make sure any loads are in the RHS.
2257 if (LoadInst *LI = dyn_cast<LoadInst>(Op1))
2258 if (isSafeToFoldLoadIntoInstruction(*LI, I)) {
2259 const Type *Ty = Op0->getType();
2260 assert(Ty == Type::FloatTy||Ty == Type::DoubleTy && "Unknown FP type!");
2261 unsigned Opcode = Ty == Type::FloatTy ? X86::FMUL32m : X86::FMUL64m;
2263 unsigned BaseReg, Scale, IndexReg, Disp;
2264 getAddressingMode(LI->getOperand(0), BaseReg,
2265 Scale, IndexReg, Disp);
2267 unsigned Op0r = getReg(Op0);
2268 addFullAddress(BuildMI(BB, Opcode, 2, ResultReg).addReg(Op0r),
2269 BaseReg, Scale, IndexReg, Disp);
2274 MachineBasicBlock::iterator IP = BB->end();
2275 emitMultiply(BB, IP, Op0, Op1, ResultReg);
2278 void ISel::emitMultiply(MachineBasicBlock *MBB, MachineBasicBlock::iterator IP,
2279 Value *Op0, Value *Op1, unsigned DestReg) {
2280 MachineBasicBlock &BB = *MBB;
2281 TypeClass Class = getClass(Op0->getType());
2283 // Simple scalar multiply?
2284 unsigned Op0Reg = getReg(Op0, &BB, IP);
2289 if (ConstantInt *CI = dyn_cast<ConstantInt>(Op1)) {
2290 unsigned Val = (unsigned)CI->getRawValue(); // Isn't a 64-bit constant
2291 doMultiplyConst(&BB, IP, DestReg, Op0->getType(), Op0Reg, Val);
2293 unsigned Op1Reg = getReg(Op1, &BB, IP);
2294 doMultiply(&BB, IP, DestReg, Op1->getType(), Op0Reg, Op1Reg);
2298 emitBinaryFPOperation(MBB, IP, Op0, Op1, 2, DestReg);
2304 // Long value. We have to do things the hard way...
2305 if (ConstantInt *CI = dyn_cast<ConstantInt>(Op1)) {
2306 unsigned CLow = CI->getRawValue();
2307 unsigned CHi = CI->getRawValue() >> 32;
2310 // If the low part of the constant is all zeros, things are simple.
2311 BuildMI(BB, IP, X86::MOV32ri, 1, DestReg).addImm(0);
2312 doMultiplyConst(&BB, IP, DestReg+1, Type::UIntTy, Op0Reg, CHi);
2316 // Multiply the two low parts... capturing carry into EDX
2317 unsigned OverflowReg = 0;
2319 BuildMI(BB, IP, X86::MOV32rr, 1, DestReg).addReg(Op0Reg);
2321 unsigned Op1RegL = makeAnotherReg(Type::UIntTy);
2322 OverflowReg = makeAnotherReg(Type::UIntTy);
2323 BuildMI(BB, IP, X86::MOV32ri, 1, Op1RegL).addImm(CLow);
2324 BuildMI(BB, IP, X86::MOV32rr, 1, X86::EAX).addReg(Op0Reg);
2325 BuildMI(BB, IP, X86::MUL32r, 1).addReg(Op1RegL); // AL*BL
2327 BuildMI(BB, IP, X86::MOV32rr, 1, DestReg).addReg(X86::EAX); // AL*BL
2328 BuildMI(BB, IP, X86::MOV32rr, 1,
2329 OverflowReg).addReg(X86::EDX); // AL*BL >> 32
2332 unsigned AHBLReg = makeAnotherReg(Type::UIntTy); // AH*BL
2333 doMultiplyConst(&BB, IP, AHBLReg, Type::UIntTy, Op0Reg+1, CLow);
2335 unsigned AHBLplusOverflowReg;
2337 AHBLplusOverflowReg = makeAnotherReg(Type::UIntTy);
2338 BuildMI(BB, IP, X86::ADD32rr, 2, // AH*BL+(AL*BL >> 32)
2339 AHBLplusOverflowReg).addReg(AHBLReg).addReg(OverflowReg);
2341 AHBLplusOverflowReg = AHBLReg;
2345 BuildMI(BB, IP, X86::MOV32rr, 1, DestReg+1).addReg(AHBLplusOverflowReg);
2347 unsigned ALBHReg = makeAnotherReg(Type::UIntTy); // AL*BH
2348 doMultiplyConst(&BB, IP, ALBHReg, Type::UIntTy, Op0Reg, CHi);
2350 BuildMI(BB, IP, X86::ADD32rr, 2, // AL*BH + AH*BL + (AL*BL >> 32)
2351 DestReg+1).addReg(AHBLplusOverflowReg).addReg(ALBHReg);
2356 // General 64x64 multiply
2358 unsigned Op1Reg = getReg(Op1, &BB, IP);
2359 // Multiply the two low parts... capturing carry into EDX
2360 BuildMI(BB, IP, X86::MOV32rr, 1, X86::EAX).addReg(Op0Reg);
2361 BuildMI(BB, IP, X86::MUL32r, 1).addReg(Op1Reg); // AL*BL
2363 unsigned OverflowReg = makeAnotherReg(Type::UIntTy);
2364 BuildMI(BB, IP, X86::MOV32rr, 1, DestReg).addReg(X86::EAX); // AL*BL
2365 BuildMI(BB, IP, X86::MOV32rr, 1,
2366 OverflowReg).addReg(X86::EDX); // AL*BL >> 32
2368 unsigned AHBLReg = makeAnotherReg(Type::UIntTy); // AH*BL
2369 BuildMI(BB, IP, X86::IMUL32rr, 2,
2370 AHBLReg).addReg(Op0Reg+1).addReg(Op1Reg);
2372 unsigned AHBLplusOverflowReg = makeAnotherReg(Type::UIntTy);
2373 BuildMI(BB, IP, X86::ADD32rr, 2, // AH*BL+(AL*BL >> 32)
2374 AHBLplusOverflowReg).addReg(AHBLReg).addReg(OverflowReg);
2376 unsigned ALBHReg = makeAnotherReg(Type::UIntTy); // AL*BH
2377 BuildMI(BB, IP, X86::IMUL32rr, 2,
2378 ALBHReg).addReg(Op0Reg).addReg(Op1Reg+1);
2380 BuildMI(BB, IP, X86::ADD32rr, 2, // AL*BH + AH*BL + (AL*BL >> 32)
2381 DestReg+1).addReg(AHBLplusOverflowReg).addReg(ALBHReg);
2385 /// visitDivRem - Handle division and remainder instructions... these
2386 /// instruction both require the same instructions to be generated, they just
2387 /// select the result from a different register. Note that both of these
2388 /// instructions work differently for signed and unsigned operands.
2390 void ISel::visitDivRem(BinaryOperator &I) {
2391 unsigned ResultReg = getReg(I);
2392 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1);
2394 // Fold loads into floating point divides.
2395 if (getClass(Op0->getType()) == cFP) {
2396 if (LoadInst *LI = dyn_cast<LoadInst>(Op1))
2397 if (isSafeToFoldLoadIntoInstruction(*LI, I)) {
2398 const Type *Ty = Op0->getType();
2399 assert(Ty == Type::FloatTy||Ty == Type::DoubleTy && "Unknown FP type!");
2400 unsigned Opcode = Ty == Type::FloatTy ? X86::FDIV32m : X86::FDIV64m;
2402 unsigned BaseReg, Scale, IndexReg, Disp;
2403 getAddressingMode(LI->getOperand(0), BaseReg,
2404 Scale, IndexReg, Disp);
2406 unsigned Op0r = getReg(Op0);
2407 addFullAddress(BuildMI(BB, Opcode, 2, ResultReg).addReg(Op0r),
2408 BaseReg, Scale, IndexReg, Disp);
2412 if (LoadInst *LI = dyn_cast<LoadInst>(Op0))
2413 if (isSafeToFoldLoadIntoInstruction(*LI, I)) {
2414 const Type *Ty = Op0->getType();
2415 assert(Ty == Type::FloatTy||Ty == Type::DoubleTy && "Unknown FP type!");
2416 unsigned Opcode = Ty == Type::FloatTy ? X86::FDIVR32m : X86::FDIVR64m;
2418 unsigned BaseReg, Scale, IndexReg, Disp;
2419 getAddressingMode(LI->getOperand(0), BaseReg,
2420 Scale, IndexReg, Disp);
2422 unsigned Op1r = getReg(Op1);
2423 addFullAddress(BuildMI(BB, Opcode, 2, ResultReg).addReg(Op1r),
2424 BaseReg, Scale, IndexReg, Disp);
2430 MachineBasicBlock::iterator IP = BB->end();
2431 emitDivRemOperation(BB, IP, Op0, Op1,
2432 I.getOpcode() == Instruction::Div, ResultReg);
2435 void ISel::emitDivRemOperation(MachineBasicBlock *BB,
2436 MachineBasicBlock::iterator IP,
2437 Value *Op0, Value *Op1, bool isDiv,
2438 unsigned ResultReg) {
2439 const Type *Ty = Op0->getType();
2440 unsigned Class = getClass(Ty);
2442 case cFP: // Floating point divide
2444 emitBinaryFPOperation(BB, IP, Op0, Op1, 3, ResultReg);
2446 } else { // Floating point remainder...
2447 unsigned Op0Reg = getReg(Op0, BB, IP);
2448 unsigned Op1Reg = getReg(Op1, BB, IP);
2449 MachineInstr *TheCall =
2450 BuildMI(X86::CALLpcrel32, 1).addExternalSymbol("fmod", true);
2451 std::vector<ValueRecord> Args;
2452 Args.push_back(ValueRecord(Op0Reg, Type::DoubleTy));
2453 Args.push_back(ValueRecord(Op1Reg, Type::DoubleTy));
2454 doCall(ValueRecord(ResultReg, Type::DoubleTy), TheCall, Args);
2458 static const char *FnName[] =
2459 { "__moddi3", "__divdi3", "__umoddi3", "__udivdi3" };
2460 unsigned Op0Reg = getReg(Op0, BB, IP);
2461 unsigned Op1Reg = getReg(Op1, BB, IP);
2462 unsigned NameIdx = Ty->isUnsigned()*2 + isDiv;
2463 MachineInstr *TheCall =
2464 BuildMI(X86::CALLpcrel32, 1).addExternalSymbol(FnName[NameIdx], true);
2466 std::vector<ValueRecord> Args;
2467 Args.push_back(ValueRecord(Op0Reg, Type::LongTy));
2468 Args.push_back(ValueRecord(Op1Reg, Type::LongTy));
2469 doCall(ValueRecord(ResultReg, Type::LongTy), TheCall, Args);
2472 case cByte: case cShort: case cInt:
2473 break; // Small integrals, handled below...
2474 default: assert(0 && "Unknown class!");
2477 static const unsigned Regs[] ={ X86::AL , X86::AX , X86::EAX };
2478 static const unsigned MovOpcode[]={ X86::MOV8rr, X86::MOV16rr, X86::MOV32rr };
2479 static const unsigned SarOpcode[]={ X86::SAR8ri, X86::SAR16ri, X86::SAR32ri };
2480 static const unsigned ClrOpcode[]={ X86::MOV8ri, X86::MOV16ri, X86::MOV32ri };
2481 static const unsigned ExtRegs[] ={ X86::AH , X86::DX , X86::EDX };
2483 static const unsigned DivOpcode[][4] = {
2484 { X86::DIV8r , X86::DIV16r , X86::DIV32r , 0 }, // Unsigned division
2485 { X86::IDIV8r, X86::IDIV16r, X86::IDIV32r, 0 }, // Signed division
2488 bool isSigned = Ty->isSigned();
2489 unsigned Reg = Regs[Class];
2490 unsigned ExtReg = ExtRegs[Class];
2492 // Put the first operand into one of the A registers...
2493 unsigned Op0Reg = getReg(Op0, BB, IP);
2494 unsigned Op1Reg = getReg(Op1, BB, IP);
2495 BuildMI(*BB, IP, MovOpcode[Class], 1, Reg).addReg(Op0Reg);
2498 // Emit a sign extension instruction...
2499 unsigned ShiftResult = makeAnotherReg(Op0->getType());
2500 BuildMI(*BB, IP, SarOpcode[Class], 2,ShiftResult).addReg(Op0Reg).addImm(31);
2501 BuildMI(*BB, IP, MovOpcode[Class], 1, ExtReg).addReg(ShiftResult);
2503 // If unsigned, emit a zeroing instruction... (reg = 0)
2504 BuildMI(*BB, IP, ClrOpcode[Class], 2, ExtReg).addImm(0);
2507 // Emit the appropriate divide or remainder instruction...
2508 BuildMI(*BB, IP, DivOpcode[isSigned][Class], 1).addReg(Op1Reg);
2510 // Figure out which register we want to pick the result out of...
2511 unsigned DestReg = isDiv ? Reg : ExtReg;
2513 // Put the result into the destination register...
2514 BuildMI(*BB, IP, MovOpcode[Class], 1, ResultReg).addReg(DestReg);
2518 /// Shift instructions: 'shl', 'sar', 'shr' - Some special cases here
2519 /// for constant immediate shift values, and for constant immediate
2520 /// shift values equal to 1. Even the general case is sort of special,
2521 /// because the shift amount has to be in CL, not just any old register.
2523 void ISel::visitShiftInst(ShiftInst &I) {
2524 MachineBasicBlock::iterator IP = BB->end ();
2525 emitShiftOperation (BB, IP, I.getOperand (0), I.getOperand (1),
2526 I.getOpcode () == Instruction::Shl, I.getType (),
2530 /// emitShiftOperation - Common code shared between visitShiftInst and
2531 /// constant expression support.
2532 void ISel::emitShiftOperation(MachineBasicBlock *MBB,
2533 MachineBasicBlock::iterator IP,
2534 Value *Op, Value *ShiftAmount, bool isLeftShift,
2535 const Type *ResultTy, unsigned DestReg) {
2536 unsigned SrcReg = getReg (Op, MBB, IP);
2537 bool isSigned = ResultTy->isSigned ();
2538 unsigned Class = getClass (ResultTy);
2540 static const unsigned ConstantOperand[][4] = {
2541 { X86::SHR8ri, X86::SHR16ri, X86::SHR32ri, X86::SHRD32rri8 }, // SHR
2542 { X86::SAR8ri, X86::SAR16ri, X86::SAR32ri, X86::SHRD32rri8 }, // SAR
2543 { X86::SHL8ri, X86::SHL16ri, X86::SHL32ri, X86::SHLD32rri8 }, // SHL
2544 { X86::SHL8ri, X86::SHL16ri, X86::SHL32ri, X86::SHLD32rri8 }, // SAL = SHL
2547 static const unsigned NonConstantOperand[][4] = {
2548 { X86::SHR8rCL, X86::SHR16rCL, X86::SHR32rCL }, // SHR
2549 { X86::SAR8rCL, X86::SAR16rCL, X86::SAR32rCL }, // SAR
2550 { X86::SHL8rCL, X86::SHL16rCL, X86::SHL32rCL }, // SHL
2551 { X86::SHL8rCL, X86::SHL16rCL, X86::SHL32rCL }, // SAL = SHL
2554 // Longs, as usual, are handled specially...
2555 if (Class == cLong) {
2556 // If we have a constant shift, we can generate much more efficient code
2557 // than otherwise...
2559 if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(ShiftAmount)) {
2560 unsigned Amount = CUI->getValue();
2562 const unsigned *Opc = ConstantOperand[isLeftShift*2+isSigned];
2564 BuildMI(*MBB, IP, Opc[3], 3,
2565 DestReg+1).addReg(SrcReg+1).addReg(SrcReg).addImm(Amount);
2566 BuildMI(*MBB, IP, Opc[2], 2, DestReg).addReg(SrcReg).addImm(Amount);
2568 BuildMI(*MBB, IP, Opc[3], 3,
2569 DestReg).addReg(SrcReg ).addReg(SrcReg+1).addImm(Amount);
2570 BuildMI(*MBB, IP, Opc[2],2,DestReg+1).addReg(SrcReg+1).addImm(Amount);
2572 } else { // Shifting more than 32 bits
2576 BuildMI(*MBB, IP, X86::SHL32ri, 2,
2577 DestReg + 1).addReg(SrcReg).addImm(Amount);
2579 BuildMI(*MBB, IP, X86::MOV32rr, 1, DestReg+1).addReg(SrcReg);
2581 BuildMI(*MBB, IP, X86::MOV32ri, 1, DestReg).addImm(0);
2584 BuildMI(*MBB, IP, isSigned ? X86::SAR32ri : X86::SHR32ri, 2,
2585 DestReg).addReg(SrcReg+1).addImm(Amount);
2587 BuildMI(*MBB, IP, X86::MOV32rr, 1, DestReg).addReg(SrcReg+1);
2589 BuildMI(*MBB, IP, X86::MOV32ri, 1, DestReg+1).addImm(0);
2593 unsigned TmpReg = makeAnotherReg(Type::IntTy);
2595 if (!isLeftShift && isSigned) {
2596 // If this is a SHR of a Long, then we need to do funny sign extension
2597 // stuff. TmpReg gets the value to use as the high-part if we are
2598 // shifting more than 32 bits.
2599 BuildMI(*MBB, IP, X86::SAR32ri, 2, TmpReg).addReg(SrcReg).addImm(31);
2601 // Other shifts use a fixed zero value if the shift is more than 32
2603 BuildMI(*MBB, IP, X86::MOV32ri, 1, TmpReg).addImm(0);
2606 // Initialize CL with the shift amount...
2607 unsigned ShiftAmountReg = getReg(ShiftAmount, MBB, IP);
2608 BuildMI(*MBB, IP, X86::MOV8rr, 1, X86::CL).addReg(ShiftAmountReg);
2610 unsigned TmpReg2 = makeAnotherReg(Type::IntTy);
2611 unsigned TmpReg3 = makeAnotherReg(Type::IntTy);
2613 // TmpReg2 = shld inHi, inLo
2614 BuildMI(*MBB, IP, X86::SHLD32rrCL,2,TmpReg2).addReg(SrcReg+1)
2616 // TmpReg3 = shl inLo, CL
2617 BuildMI(*MBB, IP, X86::SHL32rCL, 1, TmpReg3).addReg(SrcReg);
2619 // Set the flags to indicate whether the shift was by more than 32 bits.
2620 BuildMI(*MBB, IP, X86::TEST8ri, 2).addReg(X86::CL).addImm(32);
2622 // DestHi = (>32) ? TmpReg3 : TmpReg2;
2623 BuildMI(*MBB, IP, X86::CMOVNE32rr, 2,
2624 DestReg+1).addReg(TmpReg2).addReg(TmpReg3);
2625 // DestLo = (>32) ? TmpReg : TmpReg3;
2626 BuildMI(*MBB, IP, X86::CMOVNE32rr, 2,
2627 DestReg).addReg(TmpReg3).addReg(TmpReg);
2629 // TmpReg2 = shrd inLo, inHi
2630 BuildMI(*MBB, IP, X86::SHRD32rrCL,2,TmpReg2).addReg(SrcReg)
2632 // TmpReg3 = s[ah]r inHi, CL
2633 BuildMI(*MBB, IP, isSigned ? X86::SAR32rCL : X86::SHR32rCL, 1, TmpReg3)
2636 // Set the flags to indicate whether the shift was by more than 32 bits.
2637 BuildMI(*MBB, IP, X86::TEST8ri, 2).addReg(X86::CL).addImm(32);
2639 // DestLo = (>32) ? TmpReg3 : TmpReg2;
2640 BuildMI(*MBB, IP, X86::CMOVNE32rr, 2,
2641 DestReg).addReg(TmpReg2).addReg(TmpReg3);
2643 // DestHi = (>32) ? TmpReg : TmpReg3;
2644 BuildMI(*MBB, IP, X86::CMOVNE32rr, 2,
2645 DestReg+1).addReg(TmpReg3).addReg(TmpReg);
2651 if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(ShiftAmount)) {
2652 // The shift amount is constant, guaranteed to be a ubyte. Get its value.
2653 assert(CUI->getType() == Type::UByteTy && "Shift amount not a ubyte?");
2655 const unsigned *Opc = ConstantOperand[isLeftShift*2+isSigned];
2656 BuildMI(*MBB, IP, Opc[Class], 2,
2657 DestReg).addReg(SrcReg).addImm(CUI->getValue());
2658 } else { // The shift amount is non-constant.
2659 unsigned ShiftAmountReg = getReg (ShiftAmount, MBB, IP);
2660 BuildMI(*MBB, IP, X86::MOV8rr, 1, X86::CL).addReg(ShiftAmountReg);
2662 const unsigned *Opc = NonConstantOperand[isLeftShift*2+isSigned];
2663 BuildMI(*MBB, IP, Opc[Class], 1, DestReg).addReg(SrcReg);
2668 void ISel::getAddressingMode(Value *Addr, unsigned &BaseReg, unsigned &Scale,
2669 unsigned &IndexReg, unsigned &Disp) {
2670 BaseReg = 0; Scale = 1; IndexReg = 0; Disp = 0;
2671 if (GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(Addr)) {
2672 if (isGEPFoldable(BB, GEP->getOperand(0), GEP->op_begin()+1, GEP->op_end(),
2673 BaseReg, Scale, IndexReg, Disp))
2675 } else if (ConstantExpr *CE = dyn_cast<ConstantExpr>(Addr)) {
2676 if (CE->getOpcode() == Instruction::GetElementPtr)
2677 if (isGEPFoldable(BB, CE->getOperand(0), CE->op_begin()+1, CE->op_end(),
2678 BaseReg, Scale, IndexReg, Disp))
2682 // If it's not foldable, reset addr mode.
2683 BaseReg = getReg(Addr);
2684 Scale = 1; IndexReg = 0; Disp = 0;
2688 /// visitLoadInst - Implement LLVM load instructions in terms of the x86 'mov'
2689 /// instruction. The load and store instructions are the only place where we
2690 /// need to worry about the memory layout of the target machine.
2692 void ISel::visitLoadInst(LoadInst &I) {
2693 // Check to see if this load instruction is going to be folded into a binary
2694 // instruction, like add. If so, we don't want to emit it. Wouldn't a real
2695 // pattern matching instruction selector be nice?
2696 unsigned Class = getClassB(I.getType());
2697 if (I.hasOneUse()) {
2698 Instruction *User = cast<Instruction>(I.use_back());
2699 switch (User->getOpcode()) {
2700 case Instruction::Cast:
2701 // If this is a cast from a signed-integer type to a floating point type,
2702 // fold the cast here.
2703 if (getClass(User->getType()) == cFP &&
2704 (I.getType() == Type::ShortTy || I.getType() == Type::IntTy ||
2705 I.getType() == Type::LongTy)) {
2706 unsigned DestReg = getReg(User);
2707 static const unsigned Opcode[] = {
2708 0/*BYTE*/, X86::FILD16m, X86::FILD32m, 0/*FP*/, X86::FILD64m
2710 unsigned BaseReg = 0, Scale = 1, IndexReg = 0, Disp = 0;
2711 getAddressingMode(I.getOperand(0), BaseReg, Scale, IndexReg, Disp);
2712 addFullAddress(BuildMI(BB, Opcode[Class], 5, DestReg),
2713 BaseReg, Scale, IndexReg, Disp);
2720 case Instruction::Add:
2721 case Instruction::Sub:
2722 case Instruction::And:
2723 case Instruction::Or:
2724 case Instruction::Xor:
2725 if (Class == cLong) User = 0;
2727 case Instruction::Mul:
2728 case Instruction::Div:
2729 if (Class != cFP) User = 0;
2730 break; // Folding only implemented for floating point.
2731 default: User = 0; break;
2735 // Okay, we found a user. If the load is the first operand and there is
2736 // no second operand load, reverse the operand ordering. Note that this
2737 // can fail for a subtract (ie, no change will be made).
2738 if (!isa<LoadInst>(User->getOperand(1)))
2739 cast<BinaryOperator>(User)->swapOperands();
2741 // Okay, now that everything is set up, if this load is used by the second
2742 // operand, and if there are no instructions that invalidate the load
2743 // before the binary operator, eliminate the load.
2744 if (User->getOperand(1) == &I &&
2745 isSafeToFoldLoadIntoInstruction(I, *User))
2746 return; // Eliminate the load!
2748 // If this is a floating point sub or div, we won't be able to swap the
2749 // operands, but we will still be able to eliminate the load.
2750 if (Class == cFP && User->getOperand(0) == &I &&
2751 !isa<LoadInst>(User->getOperand(1)) &&
2752 (User->getOpcode() == Instruction::Sub ||
2753 User->getOpcode() == Instruction::Div) &&
2754 isSafeToFoldLoadIntoInstruction(I, *User))
2755 return; // Eliminate the load!
2759 unsigned DestReg = getReg(I);
2760 unsigned BaseReg = 0, Scale = 1, IndexReg = 0, Disp = 0;
2761 getAddressingMode(I.getOperand(0), BaseReg, Scale, IndexReg, Disp);
2763 if (Class == cLong) {
2764 addFullAddress(BuildMI(BB, X86::MOV32rm, 4, DestReg),
2765 BaseReg, Scale, IndexReg, Disp);
2766 addFullAddress(BuildMI(BB, X86::MOV32rm, 4, DestReg+1),
2767 BaseReg, Scale, IndexReg, Disp+4);
2771 static const unsigned Opcodes[] = {
2772 X86::MOV8rm, X86::MOV16rm, X86::MOV32rm, X86::FLD32m
2774 unsigned Opcode = Opcodes[Class];
2775 if (I.getType() == Type::DoubleTy) Opcode = X86::FLD64m;
2776 addFullAddress(BuildMI(BB, Opcode, 4, DestReg),
2777 BaseReg, Scale, IndexReg, Disp);
2780 /// visitStoreInst - Implement LLVM store instructions in terms of the x86 'mov'
2783 void ISel::visitStoreInst(StoreInst &I) {
2784 unsigned BaseReg, Scale, IndexReg, Disp;
2785 getAddressingMode(I.getOperand(1), BaseReg, Scale, IndexReg, Disp);
2787 const Type *ValTy = I.getOperand(0)->getType();
2788 unsigned Class = getClassB(ValTy);
2790 if (ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(0))) {
2791 uint64_t Val = CI->getRawValue();
2792 if (Class == cLong) {
2793 addFullAddress(BuildMI(BB, X86::MOV32mi, 5),
2794 BaseReg, Scale, IndexReg, Disp).addImm(Val & ~0U);
2795 addFullAddress(BuildMI(BB, X86::MOV32mi, 5),
2796 BaseReg, Scale, IndexReg, Disp+4).addImm(Val>>32);
2798 static const unsigned Opcodes[] = {
2799 X86::MOV8mi, X86::MOV16mi, X86::MOV32mi
2801 unsigned Opcode = Opcodes[Class];
2802 addFullAddress(BuildMI(BB, Opcode, 5),
2803 BaseReg, Scale, IndexReg, Disp).addImm(Val);
2805 } else if (ConstantBool *CB = dyn_cast<ConstantBool>(I.getOperand(0))) {
2806 addFullAddress(BuildMI(BB, X86::MOV8mi, 5),
2807 BaseReg, Scale, IndexReg, Disp).addImm(CB->getValue());
2809 if (Class == cLong) {
2810 unsigned ValReg = getReg(I.getOperand(0));
2811 addFullAddress(BuildMI(BB, X86::MOV32mr, 5),
2812 BaseReg, Scale, IndexReg, Disp).addReg(ValReg);
2813 addFullAddress(BuildMI(BB, X86::MOV32mr, 5),
2814 BaseReg, Scale, IndexReg, Disp+4).addReg(ValReg+1);
2816 unsigned ValReg = getReg(I.getOperand(0));
2817 static const unsigned Opcodes[] = {
2818 X86::MOV8mr, X86::MOV16mr, X86::MOV32mr, X86::FST32m
2820 unsigned Opcode = Opcodes[Class];
2821 if (ValTy == Type::DoubleTy) Opcode = X86::FST64m;
2822 addFullAddress(BuildMI(BB, Opcode, 1+4),
2823 BaseReg, Scale, IndexReg, Disp).addReg(ValReg);
2829 /// visitCastInst - Here we have various kinds of copying with or without sign
2830 /// extension going on.
2832 void ISel::visitCastInst(CastInst &CI) {
2833 Value *Op = CI.getOperand(0);
2835 unsigned SrcClass = getClassB(Op->getType());
2836 unsigned DestClass = getClassB(CI.getType());
2837 // Noop casts are not emitted: getReg will return the source operand as the
2838 // register to use for any uses of the noop cast.
2839 if (DestClass == SrcClass)
2842 // If this is a cast from a 32-bit integer to a Long type, and the only uses
2843 // of the case are GEP instructions, then the cast does not need to be
2844 // generated explicitly, it will be folded into the GEP.
2845 if (DestClass == cLong && SrcClass == cInt) {
2846 bool AllUsesAreGEPs = true;
2847 for (Value::use_iterator I = CI.use_begin(), E = CI.use_end(); I != E; ++I)
2848 if (!isa<GetElementPtrInst>(*I)) {
2849 AllUsesAreGEPs = false;
2853 // No need to codegen this cast if all users are getelementptr instrs...
2854 if (AllUsesAreGEPs) return;
2857 // If this cast converts a load from a short,int, or long integer to a FP
2858 // value, we will have folded this cast away.
2859 if (DestClass == cFP && isa<LoadInst>(Op) && Op->hasOneUse() &&
2860 (Op->getType() == Type::ShortTy || Op->getType() == Type::IntTy ||
2861 Op->getType() == Type::LongTy))
2865 unsigned DestReg = getReg(CI);
2866 MachineBasicBlock::iterator MI = BB->end();
2867 emitCastOperation(BB, MI, Op, CI.getType(), DestReg);
2870 /// emitCastOperation - Common code shared between visitCastInst and constant
2871 /// expression cast support.
2873 void ISel::emitCastOperation(MachineBasicBlock *BB,
2874 MachineBasicBlock::iterator IP,
2875 Value *Src, const Type *DestTy,
2877 const Type *SrcTy = Src->getType();
2878 unsigned SrcClass = getClassB(SrcTy);
2879 unsigned DestClass = getClassB(DestTy);
2880 unsigned SrcReg = getReg(Src, BB, IP);
2882 // Implement casts to bool by using compare on the operand followed by set if
2883 // not zero on the result.
2884 if (DestTy == Type::BoolTy) {
2887 BuildMI(*BB, IP, X86::TEST8rr, 2).addReg(SrcReg).addReg(SrcReg);
2890 BuildMI(*BB, IP, X86::TEST16rr, 2).addReg(SrcReg).addReg(SrcReg);
2893 BuildMI(*BB, IP, X86::TEST32rr, 2).addReg(SrcReg).addReg(SrcReg);
2896 unsigned TmpReg = makeAnotherReg(Type::IntTy);
2897 BuildMI(*BB, IP, X86::OR32rr, 2, TmpReg).addReg(SrcReg).addReg(SrcReg+1);
2901 BuildMI(*BB, IP, X86::FTST, 1).addReg(SrcReg);
2902 BuildMI(*BB, IP, X86::FNSTSW8r, 0);
2903 BuildMI(*BB, IP, X86::SAHF, 1);
2907 // If the zero flag is not set, then the value is true, set the byte to
2909 BuildMI(*BB, IP, X86::SETNEr, 1, DestReg);
2913 static const unsigned RegRegMove[] = {
2914 X86::MOV8rr, X86::MOV16rr, X86::MOV32rr, X86::FpMOV, X86::MOV32rr
2917 // Implement casts between values of the same type class (as determined by
2918 // getClass) by using a register-to-register move.
2919 if (SrcClass == DestClass) {
2920 if (SrcClass <= cInt || (SrcClass == cFP && SrcTy == DestTy)) {
2921 BuildMI(*BB, IP, RegRegMove[SrcClass], 1, DestReg).addReg(SrcReg);
2922 } else if (SrcClass == cFP) {
2923 if (SrcTy == Type::FloatTy) { // double -> float
2924 assert(DestTy == Type::DoubleTy && "Unknown cFP member!");
2925 BuildMI(*BB, IP, X86::FpMOV, 1, DestReg).addReg(SrcReg);
2926 } else { // float -> double
2927 assert(SrcTy == Type::DoubleTy && DestTy == Type::FloatTy &&
2928 "Unknown cFP member!");
2929 // Truncate from double to float by storing to memory as short, then
2931 unsigned FltAlign = TM.getTargetData().getFloatAlignment();
2932 int FrameIdx = F->getFrameInfo()->CreateStackObject(4, FltAlign);
2933 addFrameReference(BuildMI(*BB, IP, X86::FST32m, 5), FrameIdx).addReg(SrcReg);
2934 addFrameReference(BuildMI(*BB, IP, X86::FLD32m, 5, DestReg), FrameIdx);
2936 } else if (SrcClass == cLong) {
2937 BuildMI(*BB, IP, X86::MOV32rr, 1, DestReg).addReg(SrcReg);
2938 BuildMI(*BB, IP, X86::MOV32rr, 1, DestReg+1).addReg(SrcReg+1);
2940 assert(0 && "Cannot handle this type of cast instruction!");
2946 // Handle cast of SMALLER int to LARGER int using a move with sign extension
2947 // or zero extension, depending on whether the source type was signed.
2948 if (SrcClass <= cInt && (DestClass <= cInt || DestClass == cLong) &&
2949 SrcClass < DestClass) {
2950 bool isLong = DestClass == cLong;
2951 if (isLong) DestClass = cInt;
2953 static const unsigned Opc[][4] = {
2954 { X86::MOVSX16rr8, X86::MOVSX32rr8, X86::MOVSX32rr16, X86::MOV32rr }, // s
2955 { X86::MOVZX16rr8, X86::MOVZX32rr8, X86::MOVZX32rr16, X86::MOV32rr } // u
2958 bool isUnsigned = SrcTy->isUnsigned();
2959 BuildMI(*BB, IP, Opc[isUnsigned][SrcClass + DestClass - 1], 1,
2960 DestReg).addReg(SrcReg);
2962 if (isLong) { // Handle upper 32 bits as appropriate...
2963 if (isUnsigned) // Zero out top bits...
2964 BuildMI(*BB, IP, X86::MOV32ri, 1, DestReg+1).addImm(0);
2965 else // Sign extend bottom half...
2966 BuildMI(*BB, IP, X86::SAR32ri, 2, DestReg+1).addReg(DestReg).addImm(31);
2971 // Special case long -> int ...
2972 if (SrcClass == cLong && DestClass == cInt) {
2973 BuildMI(*BB, IP, X86::MOV32rr, 1, DestReg).addReg(SrcReg);
2977 // Handle cast of LARGER int to SMALLER int using a move to EAX followed by a
2978 // move out of AX or AL.
2979 if ((SrcClass <= cInt || SrcClass == cLong) && DestClass <= cInt
2980 && SrcClass > DestClass) {
2981 static const unsigned AReg[] = { X86::AL, X86::AX, X86::EAX, 0, X86::EAX };
2982 BuildMI(*BB, IP, RegRegMove[SrcClass], 1, AReg[SrcClass]).addReg(SrcReg);
2983 BuildMI(*BB, IP, RegRegMove[DestClass], 1, DestReg).addReg(AReg[DestClass]);
2987 // Handle casts from integer to floating point now...
2988 if (DestClass == cFP) {
2989 // Promote the integer to a type supported by FLD. We do this because there
2990 // are no unsigned FLD instructions, so we must promote an unsigned value to
2991 // a larger signed value, then use FLD on the larger value.
2993 const Type *PromoteType = 0;
2994 unsigned PromoteOpcode = 0;
2995 unsigned RealDestReg = DestReg;
2996 switch (SrcTy->getPrimitiveID()) {
2997 case Type::BoolTyID:
2998 case Type::SByteTyID:
2999 // We don't have the facilities for directly loading byte sized data from
3000 // memory (even signed). Promote it to 16 bits.
3001 PromoteType = Type::ShortTy;
3002 PromoteOpcode = X86::MOVSX16rr8;
3004 case Type::UByteTyID:
3005 PromoteType = Type::ShortTy;
3006 PromoteOpcode = X86::MOVZX16rr8;
3008 case Type::UShortTyID:
3009 PromoteType = Type::IntTy;
3010 PromoteOpcode = X86::MOVZX32rr16;
3012 case Type::UIntTyID: {
3013 // Make a 64 bit temporary... and zero out the top of it...
3014 unsigned TmpReg = makeAnotherReg(Type::LongTy);
3015 BuildMI(*BB, IP, X86::MOV32rr, 1, TmpReg).addReg(SrcReg);
3016 BuildMI(*BB, IP, X86::MOV32ri, 1, TmpReg+1).addImm(0);
3017 SrcTy = Type::LongTy;
3022 case Type::ULongTyID:
3023 // Don't fild into the read destination.
3024 DestReg = makeAnotherReg(Type::DoubleTy);
3026 default: // No promotion needed...
3031 unsigned TmpReg = makeAnotherReg(PromoteType);
3032 BuildMI(*BB, IP, PromoteOpcode, 1, TmpReg).addReg(SrcReg);
3033 SrcTy = PromoteType;
3034 SrcClass = getClass(PromoteType);
3038 // Spill the integer to memory and reload it from there...
3040 F->getFrameInfo()->CreateStackObject(SrcTy, TM.getTargetData());
3042 if (SrcClass == cLong) {
3043 addFrameReference(BuildMI(*BB, IP, X86::MOV32mr, 5),
3044 FrameIdx).addReg(SrcReg);
3045 addFrameReference(BuildMI(*BB, IP, X86::MOV32mr, 5),
3046 FrameIdx, 4).addReg(SrcReg+1);
3048 static const unsigned Op1[] = { X86::MOV8mr, X86::MOV16mr, X86::MOV32mr };
3049 addFrameReference(BuildMI(*BB, IP, Op1[SrcClass], 5),
3050 FrameIdx).addReg(SrcReg);
3053 static const unsigned Op2[] =
3054 { 0/*byte*/, X86::FILD16m, X86::FILD32m, 0/*FP*/, X86::FILD64m };
3055 addFrameReference(BuildMI(*BB, IP, Op2[SrcClass], 5, DestReg), FrameIdx);
3057 // We need special handling for unsigned 64-bit integer sources. If the
3058 // input number has the "sign bit" set, then we loaded it incorrectly as a
3059 // negative 64-bit number. In this case, add an offset value.
3060 if (SrcTy == Type::ULongTy) {
3061 // Emit a test instruction to see if the dynamic input value was signed.
3062 BuildMI(*BB, IP, X86::TEST32rr, 2).addReg(SrcReg+1).addReg(SrcReg+1);
3064 // If the sign bit is set, get a pointer to an offset, otherwise get a
3065 // pointer to a zero.
3066 MachineConstantPool *CP = F->getConstantPool();
3067 unsigned Zero = makeAnotherReg(Type::IntTy);
3068 Constant *Null = Constant::getNullValue(Type::UIntTy);
3069 addConstantPoolReference(BuildMI(*BB, IP, X86::LEA32r, 5, Zero),
3070 CP->getConstantPoolIndex(Null));
3071 unsigned Offset = makeAnotherReg(Type::IntTy);
3072 Constant *OffsetCst = ConstantUInt::get(Type::UIntTy, 0x5f800000);
3074 addConstantPoolReference(BuildMI(*BB, IP, X86::LEA32r, 5, Offset),
3075 CP->getConstantPoolIndex(OffsetCst));
3076 unsigned Addr = makeAnotherReg(Type::IntTy);
3077 BuildMI(*BB, IP, X86::CMOVS32rr, 2, Addr).addReg(Zero).addReg(Offset);
3079 // Load the constant for an add. FIXME: this could make an 'fadd' that
3080 // reads directly from memory, but we don't support these yet.
3081 unsigned ConstReg = makeAnotherReg(Type::DoubleTy);
3082 addDirectMem(BuildMI(*BB, IP, X86::FLD32m, 4, ConstReg), Addr);
3084 BuildMI(*BB, IP, X86::FpADD, 2, RealDestReg)
3085 .addReg(ConstReg).addReg(DestReg);
3091 // Handle casts from floating point to integer now...
3092 if (SrcClass == cFP) {
3093 // Change the floating point control register to use "round towards zero"
3094 // mode when truncating to an integer value.
3096 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2);
3097 addFrameReference(BuildMI(*BB, IP, X86::FNSTCW16m, 4), CWFrameIdx);
3099 // Load the old value of the high byte of the control word...
3100 unsigned HighPartOfCW = makeAnotherReg(Type::UByteTy);
3101 addFrameReference(BuildMI(*BB, IP, X86::MOV8rm, 4, HighPartOfCW),
3104 // Set the high part to be round to zero...
3105 addFrameReference(BuildMI(*BB, IP, X86::MOV8mi, 5),
3106 CWFrameIdx, 1).addImm(12);
3108 // Reload the modified control word now...
3109 addFrameReference(BuildMI(*BB, IP, X86::FLDCW16m, 4), CWFrameIdx);
3111 // Restore the memory image of control word to original value
3112 addFrameReference(BuildMI(*BB, IP, X86::MOV8mr, 5),
3113 CWFrameIdx, 1).addReg(HighPartOfCW);
3115 // We don't have the facilities for directly storing byte sized data to
3116 // memory. Promote it to 16 bits. We also must promote unsigned values to
3117 // larger classes because we only have signed FP stores.
3118 unsigned StoreClass = DestClass;
3119 const Type *StoreTy = DestTy;
3120 if (StoreClass == cByte || DestTy->isUnsigned())
3121 switch (StoreClass) {
3122 case cByte: StoreTy = Type::ShortTy; StoreClass = cShort; break;
3123 case cShort: StoreTy = Type::IntTy; StoreClass = cInt; break;
3124 case cInt: StoreTy = Type::LongTy; StoreClass = cLong; break;
3125 // The following treatment of cLong may not be perfectly right,
3126 // but it survives chains of casts of the form
3127 // double->ulong->double.
3128 case cLong: StoreTy = Type::LongTy; StoreClass = cLong; break;
3129 default: assert(0 && "Unknown store class!");
3132 // Spill the integer to memory and reload it from there...
3134 F->getFrameInfo()->CreateStackObject(StoreTy, TM.getTargetData());
3136 static const unsigned Op1[] =
3137 { 0, X86::FIST16m, X86::FIST32m, 0, X86::FISTP64m };
3138 addFrameReference(BuildMI(*BB, IP, Op1[StoreClass], 5),
3139 FrameIdx).addReg(SrcReg);
3141 if (DestClass == cLong) {
3142 addFrameReference(BuildMI(*BB, IP, X86::MOV32rm, 4, DestReg), FrameIdx);
3143 addFrameReference(BuildMI(*BB, IP, X86::MOV32rm, 4, DestReg+1),
3146 static const unsigned Op2[] = { X86::MOV8rm, X86::MOV16rm, X86::MOV32rm };
3147 addFrameReference(BuildMI(*BB, IP, Op2[DestClass], 4, DestReg), FrameIdx);
3150 // Reload the original control word now...
3151 addFrameReference(BuildMI(*BB, IP, X86::FLDCW16m, 4), CWFrameIdx);
3155 // Anything we haven't handled already, we can't (yet) handle at all.
3156 assert(0 && "Unhandled cast instruction!");
3160 /// visitVANextInst - Implement the va_next instruction...
3162 void ISel::visitVANextInst(VANextInst &I) {
3163 unsigned VAList = getReg(I.getOperand(0));
3164 unsigned DestReg = getReg(I);
3167 switch (I.getArgType()->getPrimitiveID()) {
3170 assert(0 && "Error: bad type for va_next instruction!");
3172 case Type::PointerTyID:
3173 case Type::UIntTyID:
3177 case Type::ULongTyID:
3178 case Type::LongTyID:
3179 case Type::DoubleTyID:
3184 // Increment the VAList pointer...
3185 BuildMI(BB, X86::ADD32ri, 2, DestReg).addReg(VAList).addImm(Size);
3188 void ISel::visitVAArgInst(VAArgInst &I) {
3189 unsigned VAList = getReg(I.getOperand(0));
3190 unsigned DestReg = getReg(I);
3192 switch (I.getType()->getPrimitiveID()) {
3195 assert(0 && "Error: bad type for va_next instruction!");
3197 case Type::PointerTyID:
3198 case Type::UIntTyID:
3200 addDirectMem(BuildMI(BB, X86::MOV32rm, 4, DestReg), VAList);
3202 case Type::ULongTyID:
3203 case Type::LongTyID:
3204 addDirectMem(BuildMI(BB, X86::MOV32rm, 4, DestReg), VAList);
3205 addRegOffset(BuildMI(BB, X86::MOV32rm, 4, DestReg+1), VAList, 4);
3207 case Type::DoubleTyID:
3208 addDirectMem(BuildMI(BB, X86::FLD64m, 4, DestReg), VAList);
3213 /// visitGetElementPtrInst - instruction-select GEP instructions
3215 void ISel::visitGetElementPtrInst(GetElementPtrInst &I) {
3216 // If this GEP instruction will be folded into all of its users, we don't need
3217 // to explicitly calculate it!
3218 unsigned A, B, C, D;
3219 if (isGEPFoldable(0, I.getOperand(0), I.op_begin()+1, I.op_end(), A,B,C,D)) {
3220 // Check all of the users of the instruction to see if they are loads and
3222 bool AllWillFold = true;
3223 for (Value::use_iterator UI = I.use_begin(), E = I.use_end(); UI != E; ++UI)
3224 if (cast<Instruction>(*UI)->getOpcode() != Instruction::Load)
3225 if (cast<Instruction>(*UI)->getOpcode() != Instruction::Store ||
3226 cast<Instruction>(*UI)->getOperand(0) == &I) {
3227 AllWillFold = false;
3231 // If the instruction is foldable, and will be folded into all users, don't
3233 if (AllWillFold) return;
3236 unsigned outputReg = getReg(I);
3237 emitGEPOperation(BB, BB->end(), I.getOperand(0),
3238 I.op_begin()+1, I.op_end(), outputReg);
3241 /// getGEPIndex - Inspect the getelementptr operands specified with GEPOps and
3242 /// GEPTypes (the derived types being stepped through at each level). On return
3243 /// from this function, if some indexes of the instruction are representable as
3244 /// an X86 lea instruction, the machine operands are put into the Ops
3245 /// instruction and the consumed indexes are poped from the GEPOps/GEPTypes
3246 /// lists. Otherwise, GEPOps.size() is returned. If this returns a an
3247 /// addressing mode that only partially consumes the input, the BaseReg input of
3248 /// the addressing mode must be left free.
3250 /// Note that there is one fewer entry in GEPTypes than there is in GEPOps.
3252 void ISel::getGEPIndex(MachineBasicBlock *MBB, MachineBasicBlock::iterator IP,
3253 std::vector<Value*> &GEPOps,
3254 std::vector<const Type*> &GEPTypes, unsigned &BaseReg,
3255 unsigned &Scale, unsigned &IndexReg, unsigned &Disp) {
3256 const TargetData &TD = TM.getTargetData();
3258 // Clear out the state we are working with...
3259 BaseReg = 0; // No base register
3260 Scale = 1; // Unit scale
3261 IndexReg = 0; // No index register
3262 Disp = 0; // No displacement
3264 // While there are GEP indexes that can be folded into the current address,
3265 // keep processing them.
3266 while (!GEPTypes.empty()) {
3267 if (const StructType *StTy = dyn_cast<StructType>(GEPTypes.back())) {
3268 // It's a struct access. CUI is the index into the structure,
3269 // which names the field. This index must have unsigned type.
3270 const ConstantUInt *CUI = cast<ConstantUInt>(GEPOps.back());
3272 // Use the TargetData structure to pick out what the layout of the
3273 // structure is in memory. Since the structure index must be constant, we
3274 // can get its value and use it to find the right byte offset from the
3275 // StructLayout class's list of structure member offsets.
3276 Disp += TD.getStructLayout(StTy)->MemberOffsets[CUI->getValue()];
3277 GEPOps.pop_back(); // Consume a GEP operand
3278 GEPTypes.pop_back();
3280 // It's an array or pointer access: [ArraySize x ElementType].
3281 const SequentialType *SqTy = cast<SequentialType>(GEPTypes.back());
3282 Value *idx = GEPOps.back();
3284 // idx is the index into the array. Unlike with structure
3285 // indices, we may not know its actual value at code-generation
3288 // If idx is a constant, fold it into the offset.
3289 unsigned TypeSize = TD.getTypeSize(SqTy->getElementType());
3290 if (ConstantSInt *CSI = dyn_cast<ConstantSInt>(idx)) {
3291 Disp += TypeSize*CSI->getValue();
3292 } else if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(idx)) {
3293 Disp += TypeSize*CUI->getValue();
3295 // If the index reg is already taken, we can't handle this index.
3296 if (IndexReg) return;
3298 // If this is a size that we can handle, then add the index as
3300 case 1: case 2: case 4: case 8:
3301 // These are all acceptable scales on X86.
3305 // Otherwise, we can't handle this scale
3309 if (CastInst *CI = dyn_cast<CastInst>(idx))
3310 if (CI->getOperand(0)->getType() == Type::IntTy ||
3311 CI->getOperand(0)->getType() == Type::UIntTy)
3312 idx = CI->getOperand(0);
3314 IndexReg = MBB ? getReg(idx, MBB, IP) : 1;
3317 GEPOps.pop_back(); // Consume a GEP operand
3318 GEPTypes.pop_back();
3322 // GEPTypes is empty, which means we have a single operand left. See if we
3323 // can set it as the base register.
3325 // FIXME: When addressing modes are more powerful/correct, we could load
3326 // global addresses directly as 32-bit immediates.
3327 assert(BaseReg == 0);
3328 BaseReg = MBB ? getReg(GEPOps[0], MBB, IP) : 1;
3329 GEPOps.pop_back(); // Consume the last GEP operand
3333 /// isGEPFoldable - Return true if the specified GEP can be completely
3334 /// folded into the addressing mode of a load/store or lea instruction.
3335 bool ISel::isGEPFoldable(MachineBasicBlock *MBB,
3336 Value *Src, User::op_iterator IdxBegin,
3337 User::op_iterator IdxEnd, unsigned &BaseReg,
3338 unsigned &Scale, unsigned &IndexReg, unsigned &Disp) {
3339 if (ConstantPointerRef *CPR = dyn_cast<ConstantPointerRef>(Src))
3340 Src = CPR->getValue();
3342 std::vector<Value*> GEPOps;
3343 GEPOps.resize(IdxEnd-IdxBegin+1);
3345 std::copy(IdxBegin, IdxEnd, GEPOps.begin()+1);
3347 std::vector<const Type*> GEPTypes;
3348 GEPTypes.assign(gep_type_begin(Src->getType(), IdxBegin, IdxEnd),
3349 gep_type_end(Src->getType(), IdxBegin, IdxEnd));
3351 MachineBasicBlock::iterator IP;
3352 if (MBB) IP = MBB->end();
3353 getGEPIndex(MBB, IP, GEPOps, GEPTypes, BaseReg, Scale, IndexReg, Disp);
3355 // We can fold it away iff the getGEPIndex call eliminated all operands.
3356 return GEPOps.empty();
3359 void ISel::emitGEPOperation(MachineBasicBlock *MBB,
3360 MachineBasicBlock::iterator IP,
3361 Value *Src, User::op_iterator IdxBegin,
3362 User::op_iterator IdxEnd, unsigned TargetReg) {
3363 const TargetData &TD = TM.getTargetData();
3364 if (ConstantPointerRef *CPR = dyn_cast<ConstantPointerRef>(Src))
3365 Src = CPR->getValue();
3367 std::vector<Value*> GEPOps;
3368 GEPOps.resize(IdxEnd-IdxBegin+1);
3370 std::copy(IdxBegin, IdxEnd, GEPOps.begin()+1);
3372 std::vector<const Type*> GEPTypes;
3373 GEPTypes.assign(gep_type_begin(Src->getType(), IdxBegin, IdxEnd),
3374 gep_type_end(Src->getType(), IdxBegin, IdxEnd));
3376 // Keep emitting instructions until we consume the entire GEP instruction.
3377 while (!GEPOps.empty()) {
3378 unsigned OldSize = GEPOps.size();
3379 unsigned BaseReg, Scale, IndexReg, Disp;
3380 getGEPIndex(MBB, IP, GEPOps, GEPTypes, BaseReg, Scale, IndexReg, Disp);
3382 if (GEPOps.size() != OldSize) {
3383 // getGEPIndex consumed some of the input. Build an LEA instruction here.
3384 unsigned NextTarget = 0;
3385 if (!GEPOps.empty()) {
3386 assert(BaseReg == 0 &&
3387 "getGEPIndex should have left the base register open for chaining!");
3388 NextTarget = BaseReg = makeAnotherReg(Type::UIntTy);
3391 if (IndexReg == 0 && Disp == 0)
3392 BuildMI(*MBB, IP, X86::MOV32rr, 1, TargetReg).addReg(BaseReg);
3394 addFullAddress(BuildMI(*MBB, IP, X86::LEA32r, 5, TargetReg),
3395 BaseReg, Scale, IndexReg, Disp);
3397 TargetReg = NextTarget;
3398 } else if (GEPTypes.empty()) {
3399 // The getGEPIndex operation didn't want to build an LEA. Check to see if
3400 // all operands are consumed but the base pointer. If so, just load it
3401 // into the register.
3402 if (GlobalValue *GV = dyn_cast<GlobalValue>(GEPOps[0])) {
3403 BuildMI(*MBB, IP, X86::MOV32ri, 1, TargetReg).addGlobalAddress(GV);
3405 unsigned BaseReg = getReg(GEPOps[0], MBB, IP);
3406 BuildMI(*MBB, IP, X86::MOV32rr, 1, TargetReg).addReg(BaseReg);
3408 break; // we are now done
3411 // It's an array or pointer access: [ArraySize x ElementType].
3412 const SequentialType *SqTy = cast<SequentialType>(GEPTypes.back());
3413 Value *idx = GEPOps.back();
3414 GEPOps.pop_back(); // Consume a GEP operand
3415 GEPTypes.pop_back();
3417 // Many GEP instructions use a [cast (int/uint) to LongTy] as their
3418 // operand on X86. Handle this case directly now...
3419 if (CastInst *CI = dyn_cast<CastInst>(idx))
3420 if (CI->getOperand(0)->getType() == Type::IntTy ||
3421 CI->getOperand(0)->getType() == Type::UIntTy)
3422 idx = CI->getOperand(0);
3424 // We want to add BaseReg to(idxReg * sizeof ElementType). First, we
3425 // must find the size of the pointed-to type (Not coincidentally, the next
3426 // type is the type of the elements in the array).
3427 const Type *ElTy = SqTy->getElementType();
3428 unsigned elementSize = TD.getTypeSize(ElTy);
3430 // If idxReg is a constant, we don't need to perform the multiply!
3431 if (ConstantInt *CSI = dyn_cast<ConstantInt>(idx)) {
3432 if (!CSI->isNullValue()) {
3433 unsigned Offset = elementSize*CSI->getRawValue();
3434 unsigned Reg = makeAnotherReg(Type::UIntTy);
3435 BuildMI(*MBB, IP, X86::ADD32ri, 2, TargetReg)
3436 .addReg(Reg).addImm(Offset);
3437 --IP; // Insert the next instruction before this one.
3438 TargetReg = Reg; // Codegen the rest of the GEP into this
3440 } else if (elementSize == 1) {
3441 // If the element size is 1, we don't have to multiply, just add
3442 unsigned idxReg = getReg(idx, MBB, IP);
3443 unsigned Reg = makeAnotherReg(Type::UIntTy);
3444 BuildMI(*MBB, IP, X86::ADD32rr, 2,TargetReg).addReg(Reg).addReg(idxReg);
3445 --IP; // Insert the next instruction before this one.
3446 TargetReg = Reg; // Codegen the rest of the GEP into this
3448 unsigned idxReg = getReg(idx, MBB, IP);
3449 unsigned OffsetReg = makeAnotherReg(Type::UIntTy);
3451 // Make sure we can back the iterator up to point to the first
3452 // instruction emitted.
3453 MachineBasicBlock::iterator BeforeIt = IP;
3454 if (IP == MBB->begin())
3455 BeforeIt = MBB->end();
3458 doMultiplyConst(MBB, IP, OffsetReg, Type::IntTy, idxReg, elementSize);
3460 // Emit an ADD to add OffsetReg to the basePtr.
3461 unsigned Reg = makeAnotherReg(Type::UIntTy);
3462 BuildMI(*MBB, IP, X86::ADD32rr, 2, TargetReg)
3463 .addReg(Reg).addReg(OffsetReg);
3465 // Step to the first instruction of the multiply.
3466 if (BeforeIt == MBB->end())
3471 TargetReg = Reg; // Codegen the rest of the GEP into this
3478 /// visitAllocaInst - If this is a fixed size alloca, allocate space from the
3479 /// frame manager, otherwise do it the hard way.
3481 void ISel::visitAllocaInst(AllocaInst &I) {
3482 // Find the data size of the alloca inst's getAllocatedType.
3483 const Type *Ty = I.getAllocatedType();
3484 unsigned TySize = TM.getTargetData().getTypeSize(Ty);
3486 // If this is a fixed size alloca in the entry block for the function,
3487 // statically stack allocate the space.
3489 if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(I.getArraySize())) {
3490 if (I.getParent() == I.getParent()->getParent()->begin()) {
3491 TySize *= CUI->getValue(); // Get total allocated size...
3492 unsigned Alignment = TM.getTargetData().getTypeAlignment(Ty);
3494 // Create a new stack object using the frame manager...
3495 int FrameIdx = F->getFrameInfo()->CreateStackObject(TySize, Alignment);
3496 addFrameReference(BuildMI(BB, X86::LEA32r, 5, getReg(I)), FrameIdx);
3501 // Create a register to hold the temporary result of multiplying the type size
3502 // constant by the variable amount.
3503 unsigned TotalSizeReg = makeAnotherReg(Type::UIntTy);
3504 unsigned SrcReg1 = getReg(I.getArraySize());
3506 // TotalSizeReg = mul <numelements>, <TypeSize>
3507 MachineBasicBlock::iterator MBBI = BB->end();
3508 doMultiplyConst(BB, MBBI, TotalSizeReg, Type::UIntTy, SrcReg1, TySize);
3510 // AddedSize = add <TotalSizeReg>, 15
3511 unsigned AddedSizeReg = makeAnotherReg(Type::UIntTy);
3512 BuildMI(BB, X86::ADD32ri, 2, AddedSizeReg).addReg(TotalSizeReg).addImm(15);
3514 // AlignedSize = and <AddedSize>, ~15
3515 unsigned AlignedSize = makeAnotherReg(Type::UIntTy);
3516 BuildMI(BB, X86::AND32ri, 2, AlignedSize).addReg(AddedSizeReg).addImm(~15);
3518 // Subtract size from stack pointer, thereby allocating some space.
3519 BuildMI(BB, X86::SUB32rr, 2, X86::ESP).addReg(X86::ESP).addReg(AlignedSize);
3521 // Put a pointer to the space into the result register, by copying
3522 // the stack pointer.
3523 BuildMI(BB, X86::MOV32rr, 1, getReg(I)).addReg(X86::ESP);
3525 // Inform the Frame Information that we have just allocated a variable-sized
3527 F->getFrameInfo()->CreateVariableSizedObject();
3530 /// visitMallocInst - Malloc instructions are code generated into direct calls
3531 /// to the library malloc.
3533 void ISel::visitMallocInst(MallocInst &I) {
3534 unsigned AllocSize = TM.getTargetData().getTypeSize(I.getAllocatedType());
3537 if (ConstantUInt *C = dyn_cast<ConstantUInt>(I.getOperand(0))) {
3538 Arg = getReg(ConstantUInt::get(Type::UIntTy, C->getValue() * AllocSize));
3540 Arg = makeAnotherReg(Type::UIntTy);
3541 unsigned Op0Reg = getReg(I.getOperand(0));
3542 MachineBasicBlock::iterator MBBI = BB->end();
3543 doMultiplyConst(BB, MBBI, Arg, Type::UIntTy, Op0Reg, AllocSize);
3546 std::vector<ValueRecord> Args;
3547 Args.push_back(ValueRecord(Arg, Type::UIntTy));
3548 MachineInstr *TheCall = BuildMI(X86::CALLpcrel32,
3549 1).addExternalSymbol("malloc", true);
3550 doCall(ValueRecord(getReg(I), I.getType()), TheCall, Args);
3554 /// visitFreeInst - Free instructions are code gen'd to call the free libc
3557 void ISel::visitFreeInst(FreeInst &I) {
3558 std::vector<ValueRecord> Args;
3559 Args.push_back(ValueRecord(I.getOperand(0)));
3560 MachineInstr *TheCall = BuildMI(X86::CALLpcrel32,
3561 1).addExternalSymbol("free", true);
3562 doCall(ValueRecord(0, Type::VoidTy), TheCall, Args);
3565 /// createX86SimpleInstructionSelector - This pass converts an LLVM function
3566 /// into a machine code representation is a very simple peep-hole fashion. The
3567 /// generated code sucks but the implementation is nice and simple.
3569 FunctionPass *llvm::createX86SimpleInstructionSelector(TargetMachine &TM) {
3570 return new ISel(TM);