1 //===-- InstSelectSimple.cpp - A simple instruction selector for x86 ------===//
3 // This file defines a simple peephole instruction selector for the x86 platform
5 //===----------------------------------------------------------------------===//
8 #include "X86InstrInfo.h"
9 #include "X86InstrBuilder.h"
10 #include "llvm/Function.h"
11 #include "llvm/iTerminators.h"
12 #include "llvm/iOperators.h"
13 #include "llvm/iOther.h"
14 #include "llvm/iPHINode.h"
15 #include "llvm/iMemory.h"
16 #include "llvm/Type.h"
17 #include "llvm/Constants.h"
18 #include "llvm/Pass.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/Support/InstVisitor.h"
22 using namespace MOTy; // Get Use, Def, UseAndDef
25 struct ISel : public FunctionPass, InstVisitor<ISel> {
27 MachineFunction *F; // The function we are compiling into
28 MachineBasicBlock *BB; // The current MBB we are compiling
31 std::map<Value*, unsigned> RegMap; // Mapping between Val's and SSA Regs
33 ISel(TargetMachine &tm)
34 : TM(tm), F(0), BB(0), CurReg(MRegisterInfo::FirstVirtualRegister) {}
36 /// runOnFunction - Top level implementation of instruction selection for
37 /// the entire function.
39 bool runOnFunction(Function &Fn) {
40 F = &MachineFunction::construct(&Fn, TM);
44 return false; // We never modify the LLVM itself.
47 /// visitBasicBlock - This method is called when we are visiting a new basic
48 /// block. This simply creates a new MachineBasicBlock to emit code into
49 /// and adds it to the current MachineFunction. Subsequent visit* for
50 /// instructions will be invoked for all instructions in the basic block.
52 void visitBasicBlock(BasicBlock &LLVM_BB) {
53 BB = new MachineBasicBlock(&LLVM_BB);
54 // FIXME: Use the auto-insert form when it's available
55 F->getBasicBlockList().push_back(BB);
58 // Visitation methods for various instructions. These methods simply emit
59 // fixed X86 code for each instruction.
61 void visitReturnInst(ReturnInst &RI);
62 void visitBranchInst(BranchInst &BI);
64 // Arithmetic operators
65 void visitSimpleBinary(BinaryOperator &B, unsigned OpcodeClass);
66 void visitAdd(BinaryOperator &B) { visitSimpleBinary(B, 0); }
67 void visitSub(BinaryOperator &B) { visitSimpleBinary(B, 1); }
68 void visitMul(BinaryOperator &B);
70 void visitDiv(BinaryOperator &B) { visitDivRem(B); }
71 void visitRem(BinaryOperator &B) { visitDivRem(B); }
72 void visitDivRem(BinaryOperator &B);
75 void visitAnd(BinaryOperator &B) { visitSimpleBinary(B, 2); }
76 void visitOr (BinaryOperator &B) { visitSimpleBinary(B, 3); }
77 void visitXor(BinaryOperator &B) { visitSimpleBinary(B, 4); }
79 // Binary comparison operators
80 void visitSetCondInst(SetCondInst &I);
82 // Memory Instructions
83 void visitLoadInst(LoadInst &I);
84 void visitStoreInst(StoreInst &I);
87 void visitShiftInst(ShiftInst &I);
88 void visitPHINode(PHINode &I);
90 void visitInstruction(Instruction &I) {
91 std::cerr << "Cannot instruction select: " << I;
96 /// copyConstantToRegister - Output the instructions required to put the
97 /// specified constant into the specified register.
99 void copyConstantToRegister(Constant *C, unsigned Reg);
101 /// getReg - This method turns an LLVM value into a register number. This
102 /// is guaranteed to produce the same register number for a particular value
103 /// every time it is queried.
105 unsigned getReg(Value &V) { return getReg(&V); } // Allow references
106 unsigned getReg(Value *V) {
107 unsigned &Reg = RegMap[V];
111 // If this operand is a constant, emit the code to copy the constant into
112 // the register here...
114 if (Constant *C = dyn_cast<Constant>(V))
115 copyConstantToRegister(C, Reg);
122 /// TypeClass - Used by the X86 backend to group LLVM types by their basic X86
126 cByte, cShort, cInt, cLong, cFloat, cDouble
129 /// getClass - Turn a primitive type into a "class" number which is based on the
130 /// size of the type, and whether or not it is floating point.
132 static inline TypeClass getClass(const Type *Ty) {
133 switch (Ty->getPrimitiveID()) {
134 case Type::SByteTyID:
135 case Type::UByteTyID: return cByte; // Byte operands are class #0
136 case Type::ShortTyID:
137 case Type::UShortTyID: return cShort; // Short operands are class #1
140 case Type::PointerTyID: return cInt; // Int's and pointers are class #2
143 case Type::ULongTyID: return cLong; // Longs are class #3
144 case Type::FloatTyID: return cFloat; // Float is class #4
145 case Type::DoubleTyID: return cDouble; // Doubles are class #5
147 assert(0 && "Invalid type to getClass!");
148 return cByte; // not reached
153 /// copyConstantToRegister - Output the instructions required to put the
154 /// specified constant into the specified register.
156 void ISel::copyConstantToRegister(Constant *C, unsigned R) {
157 assert (!isa<ConstantExpr>(C) && "Constant expressions not yet handled!\n");
159 if (C->getType()->isIntegral()) {
160 unsigned Class = getClass(C->getType());
161 assert(Class != 3 && "Type not handled yet!");
163 static const unsigned IntegralOpcodeTab[] = {
164 X86::MOVir8, X86::MOVir16, X86::MOVir32
167 if (C->getType()->isSigned()) {
168 ConstantSInt *CSI = cast<ConstantSInt>(C);
169 BuildMI(BB, IntegralOpcodeTab[Class], 1, R).addSImm(CSI->getValue());
171 ConstantUInt *CUI = cast<ConstantUInt>(C);
172 BuildMI(BB, IntegralOpcodeTab[Class], 1, R).addZImm(CUI->getValue());
175 assert(0 && "Type not handled yet!");
180 /// SetCC instructions - Here we just emit boilerplate code to set a byte-sized
181 /// register, then move it to wherever the result should be.
182 /// We handle FP setcc instructions by pushing them, doing a
183 /// compare-and-pop-twice, and then copying the concodes to the main
184 /// processor's concodes (I didn't make this up, it's in the Intel manual)
187 ISel::visitSetCondInst (SetCondInst & I)
189 // The arguments are already supposed to be of the same type.
190 Value *var1 = I.getOperand (0);
191 Value *var2 = I.getOperand (1);
192 unsigned reg1 = getReg (var1);
193 unsigned reg2 = getReg (var2);
194 unsigned resultReg = getReg (I);
195 unsigned comparisonWidth = var1->getType ()->getPrimitiveSize ();
196 unsigned unsignedComparison = var1->getType ()->isUnsigned ();
197 unsigned resultWidth = I.getType ()->getPrimitiveSize ();
198 bool fpComparison = var1->getType ()->isFloatingPoint ();
201 // Push the variables on the stack with fldl opcodes.
202 // FIXME: assuming var1, var2 are in memory, if not, spill to
204 switch (comparisonWidth)
207 BuildMI (BB, X86::FLDr4, 1, X86::NoReg).addReg (reg1);
210 BuildMI (BB, X86::FLDr8, 1, X86::NoReg).addReg (reg1);
213 visitInstruction (I);
216 switch (comparisonWidth)
219 BuildMI (BB, X86::FLDr4, 1, X86::NoReg).addReg (reg2);
222 BuildMI (BB, X86::FLDr8, 1, X86::NoReg).addReg (reg2);
225 visitInstruction (I);
228 // (Non-trapping) compare and pop twice.
229 BuildMI (BB, X86::FUCOMPP, 0);
230 // Move fp status word (concodes) to ax.
231 BuildMI (BB, X86::FNSTSWr8, 1, X86::AX);
232 // Load real concodes from ax.
233 BuildMI (BB, X86::SAHF, 1, X86::EFLAGS).addReg(X86::AH);
236 { // integer comparison
237 // Emit: cmp <var1>, <var2> (do the comparison). We can
238 // compare 8-bit with 8-bit, 16-bit with 16-bit, 32-bit with
240 switch (comparisonWidth)
243 BuildMI (BB, X86::CMPrr8, 2,
244 X86::EFLAGS).addReg (reg1).addReg (reg2);
247 BuildMI (BB, X86::CMPrr16, 2,
248 X86::EFLAGS).addReg (reg1).addReg (reg2);
251 BuildMI (BB, X86::CMPrr32, 2,
252 X86::EFLAGS).addReg (reg1).addReg (reg2);
256 visitInstruction (I);
260 // Emit setOp instruction (extract concode; clobbers ax),
261 // using the following mapping:
262 // LLVM -> X86 signed X86 unsigned
264 // seteq -> sete sete
265 // setne -> setne setne
266 // setlt -> setl setb
267 // setgt -> setg seta
268 // setle -> setle setbe
269 // setge -> setge setae
270 switch (I.getOpcode ())
272 case Instruction::SetEQ:
273 BuildMI (BB, X86::SETE, 0, X86::AL);
275 case Instruction::SetGE:
276 if (unsignedComparison)
277 BuildMI (BB, X86::SETAE, 0, X86::AL);
279 BuildMI (BB, X86::SETGE, 0, X86::AL);
281 case Instruction::SetGT:
282 if (unsignedComparison)
283 BuildMI (BB, X86::SETA, 0, X86::AL);
285 BuildMI (BB, X86::SETG, 0, X86::AL);
287 case Instruction::SetLE:
288 if (unsignedComparison)
289 BuildMI (BB, X86::SETBE, 0, X86::AL);
291 BuildMI (BB, X86::SETLE, 0, X86::AL);
293 case Instruction::SetLT:
294 if (unsignedComparison)
295 BuildMI (BB, X86::SETB, 0, X86::AL);
297 BuildMI (BB, X86::SETL, 0, X86::AL);
299 case Instruction::SetNE:
300 BuildMI (BB, X86::SETNE, 0, X86::AL);
303 visitInstruction (I);
306 // Put it in the result using a move.
310 BuildMI (BB, X86::MOVrr8, 1, resultReg).addReg (X86::AL);
313 BuildMI (BB, X86::MOVZXr16r8, 1, resultReg).addReg (X86::AL);
316 BuildMI (BB, X86::MOVZXr32r8, 1, resultReg).addReg (X86::AL);
320 visitInstruction (I);
326 /// 'ret' instruction - Here we are interested in meeting the x86 ABI. As such,
327 /// we have the following possibilities:
329 /// ret void: No return value, simply emit a 'ret' instruction
330 /// ret sbyte, ubyte : Extend value into EAX and return
331 /// ret short, ushort: Extend value into EAX and return
332 /// ret int, uint : Move value into EAX and return
333 /// ret pointer : Move value into EAX and return
334 /// ret long, ulong : Move value into EAX/EDX and return
335 /// ret float/double : Top of FP stack
337 void ISel::visitReturnInst (ReturnInst &I) {
338 if (I.getNumOperands() == 0) {
339 // Emit a 'ret' instruction
340 BuildMI(BB, X86::RET, 0);
344 unsigned val = getReg(I.getOperand(0));
345 unsigned Class = getClass(I.getOperand(0)->getType());
346 bool isUnsigned = I.getOperand(0)->getType()->isUnsigned();
349 // ret sbyte, ubyte: Extend value into EAX and return
351 BuildMI (BB, X86::MOVZXr32r8, 1, X86::EAX).addReg (val);
353 BuildMI (BB, X86::MOVSXr32r8, 1, X86::EAX).addReg (val);
356 // ret short, ushort: Extend value into EAX and return
358 BuildMI (BB, X86::MOVZXr32r16, 1, X86::EAX).addReg (val);
360 BuildMI (BB, X86::MOVSXr32r16, 1, X86::EAX).addReg (val);
363 // ret int, uint, ptr: Move value into EAX and return
365 BuildMI(BB, X86::MOVrr32, 1, X86::EAX).addReg(val);
368 // ret float/double: top of FP stack
370 case cFloat: // Floats
371 BuildMI(BB, X86::FLDr4, 1).addReg(val);
373 case cDouble: // Doubles
374 BuildMI(BB, X86::FLDr8, 1).addReg(val);
377 // ret long: use EAX(least significant 32 bits)/EDX (most
378 // significant 32)...uh, I think so Brain, but how do i call
379 // up the two parts of the value from inside this mouse
385 // Emit a 'ret' instruction
386 BuildMI(BB, X86::RET, 0);
390 /// visitBranchInst - Handle conditional and unconditional branches here. Note
391 /// that since code layout is frozen at this point, that if we are trying to
392 /// jump to a block that is the immediate successor of the current block, we can
393 /// just make a fall-through. (but we don't currently).
395 void ISel::visitBranchInst(BranchInst &BI) {
396 if (BI.isConditional()) // Only handles unconditional branches so far...
397 visitInstruction(BI);
399 BuildMI(BB, X86::JMP, 1).addPCDisp(BI.getSuccessor(0));
403 /// visitSimpleBinary - Implement simple binary operators for integral types...
404 /// OperatorClass is one of: 0 for Add, 1 for Sub, 2 for And, 3 for Or,
407 void ISel::visitSimpleBinary(BinaryOperator &B, unsigned OperatorClass) {
408 if (B.getType() == Type::BoolTy) // FIXME: Handle bools for logicals
411 unsigned Class = getClass(B.getType());
412 if (Class > 2) // FIXME: Handle longs
415 static const unsigned OpcodeTab[][4] = {
416 // Arithmetic operators
417 { X86::ADDrr8, X86::ADDrr16, X86::ADDrr32, 0 }, // ADD
418 { X86::SUBrr8, X86::SUBrr16, X86::SUBrr32, 0 }, // SUB
421 { X86::ANDrr8, X86::ANDrr16, X86::ANDrr32, 0 }, // AND
422 { X86:: ORrr8, X86:: ORrr16, X86:: ORrr32, 0 }, // OR
423 { X86::XORrr8, X86::XORrr16, X86::XORrr32, 0 }, // XOR
426 unsigned Opcode = OpcodeTab[OperatorClass][Class];
427 unsigned Op0r = getReg(B.getOperand(0));
428 unsigned Op1r = getReg(B.getOperand(1));
429 BuildMI(BB, Opcode, 2, getReg(B)).addReg(Op0r).addReg(Op1r);
432 /// visitMul - Multiplies are not simple binary operators because they must deal
433 /// with the EAX register explicitly.
435 void ISel::visitMul(BinaryOperator &I) {
436 unsigned Class = getClass(I.getType());
437 if (Class > 2) // FIXME: Handle longs
440 static const unsigned Regs[] ={ X86::AL , X86::AX , X86::EAX };
441 static const unsigned Clobbers[] ={ X86::AH , X86::DX , X86::EDX };
442 static const unsigned MulOpcode[]={ X86::MULrr8, X86::MULrr16, X86::MULrr32 };
443 static const unsigned MovOpcode[]={ X86::MOVrr8, X86::MOVrr16, X86::MOVrr32 };
445 unsigned Reg = Regs[Class];
446 unsigned Clobber = Clobbers[Class];
447 unsigned Op0Reg = getReg(I.getOperand(0));
448 unsigned Op1Reg = getReg(I.getOperand(1));
450 // Put the first operand into one of the A registers...
451 BuildMI(BB, MovOpcode[Class], 1, Reg).addReg(Op0Reg);
453 // Emit the appropriate multiply instruction...
454 BuildMI(BB, MulOpcode[Class], 4)
455 .addReg(Reg, UseAndDef).addReg(Op1Reg).addClobber(Clobber);
457 // Put the result into the destination register...
458 BuildMI(BB, MovOpcode[Class], 1, getReg(I)).addReg(Reg);
462 /// visitDivRem - Handle division and remainder instructions... these
463 /// instruction both require the same instructions to be generated, they just
464 /// select the result from a different register. Note that both of these
465 /// instructions work differently for signed and unsigned operands.
467 void ISel::visitDivRem(BinaryOperator &I) {
468 unsigned Class = getClass(I.getType());
469 if (Class > 2) // FIXME: Handle longs
472 static const unsigned Regs[] ={ X86::AL , X86::AX , X86::EAX };
473 static const unsigned MovOpcode[]={ X86::MOVrr8, X86::MOVrr16, X86::MOVrr32 };
474 static const unsigned ExtOpcode[]={ X86::CBW , X86::CWD , X86::CDQ };
475 static const unsigned ClrOpcode[]={ X86::XORrr8, X86::XORrr16, X86::XORrr32 };
476 static const unsigned ExtRegs[] ={ X86::AH , X86::DX , X86::EDX };
478 static const unsigned DivOpcode[][4] = {
479 { X86::DIVrr8 , X86::DIVrr16 , X86::DIVrr32 , 0 }, // Unsigned division
480 { X86::IDIVrr8, X86::IDIVrr16, X86::IDIVrr32, 0 }, // Signed division
483 bool isSigned = I.getType()->isSigned();
484 unsigned Reg = Regs[Class];
485 unsigned ExtReg = ExtRegs[Class];
486 unsigned Op0Reg = getReg(I.getOperand(0));
487 unsigned Op1Reg = getReg(I.getOperand(1));
489 // Put the first operand into one of the A registers...
490 BuildMI(BB, MovOpcode[Class], 1, Reg).addReg(Op0Reg);
493 // Emit a sign extension instruction...
494 BuildMI(BB, ExtOpcode[Class], 1, ExtReg).addReg(Reg);
496 // If unsigned, emit a zeroing instruction... (reg = xor reg, reg)
497 BuildMI(BB, ClrOpcode[Class], 2, ExtReg).addReg(ExtReg).addReg(ExtReg);
500 // Emit the appropriate divide or remainder instruction...
501 BuildMI(BB, DivOpcode[isSigned][Class], 2)
502 .addReg(Reg, UseAndDef).addReg(ExtReg, UseAndDef).addReg(Op1Reg);
504 // Figure out which register we want to pick the result out of...
505 unsigned DestReg = (I.getOpcode() == Instruction::Div) ? Reg : ExtReg;
507 // Put the result into the destination register...
508 BuildMI(BB, MovOpcode[Class], 1, getReg(I)).addReg(DestReg);
512 /// Shift instructions: 'shl', 'sar', 'shr' - Some special cases here
513 /// for constant immediate shift values, and for constant immediate
514 /// shift values equal to 1. Even the general case is sort of special,
515 /// because the shift amount has to be in CL, not just any old register.
517 void ISel::visitShiftInst (ShiftInst &I) {
518 unsigned Op0r = getReg (I.getOperand(0));
519 unsigned DestReg = getReg(I);
520 bool isLeftShift = I.getOpcode() == Instruction::Shl;
521 bool isOperandSigned = I.getType()->isUnsigned();
522 unsigned OperandClass = getClass(I.getType());
524 if (OperandClass > 2)
525 visitInstruction(I); // Can't handle longs yet!
527 if (ConstantUInt *CUI = dyn_cast <ConstantUInt> (I.getOperand (1)))
529 // The shift amount is constant, guaranteed to be a ubyte. Get its value.
530 assert(CUI->getType() == Type::UByteTy && "Shift amount not a ubyte?");
531 unsigned char shAmt = CUI->getValue();
533 static const unsigned ConstantOperand[][4] = {
534 { X86::SHRir8, X86::SHRir16, X86::SHRir32, 0 }, // SHR
535 { X86::SARir8, X86::SARir16, X86::SARir32, 0 }, // SAR
536 { X86::SHLir8, X86::SHLir16, X86::SHLir32, 0 }, // SHL
537 { X86::SHLir8, X86::SHLir16, X86::SHLir32, 0 }, // SAL = SHL
540 const unsigned *OpTab = // Figure out the operand table to use
541 ConstantOperand[isLeftShift*2+isOperandSigned];
543 // Emit: <insn> reg, shamt (shift-by-immediate opcode "ir" form.)
544 BuildMI(BB, OpTab[OperandClass], 2, DestReg).addReg(Op0r).addZImm(shAmt);
548 // The shift amount is non-constant.
550 // In fact, you can only shift with a variable shift amount if
551 // that amount is already in the CL register, so we have to put it
555 // Emit: move cl, shiftAmount (put the shift amount in CL.)
556 BuildMI(BB, X86::MOVrr8, 1, X86::CL).addReg(getReg(I.getOperand(1)));
558 // This is a shift right (SHR).
559 static const unsigned NonConstantOperand[][4] = {
560 { X86::SHRrr8, X86::SHRrr16, X86::SHRrr32, 0 }, // SHR
561 { X86::SARrr8, X86::SARrr16, X86::SARrr32, 0 }, // SAR
562 { X86::SHLrr8, X86::SHLrr16, X86::SHLrr32, 0 }, // SHL
563 { X86::SHLrr8, X86::SHLrr16, X86::SHLrr32, 0 }, // SAL = SHL
566 const unsigned *OpTab = // Figure out the operand table to use
567 NonConstantOperand[isLeftShift*2+isOperandSigned];
569 BuildMI(BB, OpTab[OperandClass], 2, DestReg).addReg(Op0r).addReg(X86::CL);
574 /// visitLoadInst - Implement LLVM load instructions in terms of the x86 'mov'
577 void ISel::visitLoadInst(LoadInst &I) {
578 unsigned Class = getClass(I.getType());
579 if (Class > 2) // FIXME: Handle longs and others...
582 static const unsigned Opcode[] = { X86::MOVmr8, X86::MOVmr16, X86::MOVmr32 };
584 unsigned AddressReg = getReg(I.getOperand(0));
585 addDirectMem(BuildMI(BB, Opcode[Class], 4, getReg(I)), AddressReg);
589 /// visitStoreInst - Implement LLVM store instructions in terms of the x86 'mov'
592 void ISel::visitStoreInst(StoreInst &I) {
593 unsigned Class = getClass(I.getOperand(0)->getType());
594 if (Class > 2) // FIXME: Handle longs and others...
597 static const unsigned Opcode[] = { X86::MOVrm8, X86::MOVrm16, X86::MOVrm32 };
599 unsigned ValReg = getReg(I.getOperand(0));
600 unsigned AddressReg = getReg(I.getOperand(1));
601 addDirectMem(BuildMI(BB, Opcode[Class], 1+4), AddressReg).addReg(ValReg);
605 /// visitPHINode - Turn an LLVM PHI node into an X86 PHI node...
607 void ISel::visitPHINode(PHINode &PN) {
608 MachineInstr *MI = BuildMI(BB, X86::PHI, PN.getNumOperands(), getReg(PN));
610 for (unsigned i = 0, e = PN.getNumIncomingValues(); i != e; ++i) {
611 // FIXME: This will put constants after the PHI nodes in the block, which
612 // is invalid. They should be put inline into the PHI node eventually.
614 MI->addRegOperand(getReg(PN.getIncomingValue(i)));
615 MI->addPCDispOperand(PN.getIncomingBlock(i));
620 /// createSimpleX86InstructionSelector - This pass converts an LLVM function
621 /// into a machine code representation is a very simple peep-hole fashion. The
622 /// generated code sucks but the implementation is nice and simple.
624 Pass *createSimpleX86InstructionSelector(TargetMachine &TM) {