1 //===-- InstSelectSimple.cpp - A simple instruction selector for x86 ------===//
3 // This file defines a simple peephole instruction selector for the x86 platform
5 //===----------------------------------------------------------------------===//
8 #include "X86InstrInfo.h"
9 #include "llvm/Function.h"
10 #include "llvm/iTerminators.h"
11 #include "llvm/iOperators.h"
12 #include "llvm/iOther.h"
13 #include "llvm/iPHINode.h"
14 #include "llvm/Type.h"
15 #include "llvm/Constants.h"
16 #include "llvm/Pass.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/Support/InstVisitor.h"
22 struct ISel : public FunctionPass, InstVisitor<ISel> {
24 MachineFunction *F; // The function we are compiling into
25 MachineBasicBlock *BB; // The current MBB we are compiling
28 std::map<Value*, unsigned> RegMap; // Mapping between Val's and SSA Regs
30 ISel(TargetMachine &tm)
31 : TM(tm), F(0), BB(0), CurReg(MRegisterInfo::FirstVirtualRegister) {}
33 /// runOnFunction - Top level implementation of instruction selection for
34 /// the entire function.
36 bool runOnFunction(Function &Fn) {
37 F = &MachineFunction::construct(&Fn, TM);
41 return false; // We never modify the LLVM itself.
44 /// visitBasicBlock - This method is called when we are visiting a new basic
45 /// block. This simply creates a new MachineBasicBlock to emit code into
46 /// and adds it to the current MachineFunction. Subsequent visit* for
47 /// instructions will be invoked for all instructions in the basic block.
49 void visitBasicBlock(BasicBlock &LLVM_BB) {
50 BB = new MachineBasicBlock(&LLVM_BB);
51 // FIXME: Use the auto-insert form when it's available
52 F->getBasicBlockList().push_back(BB);
55 // Visitation methods for various instructions. These methods simply emit
56 // fixed X86 code for each instruction.
58 void visitReturnInst(ReturnInst &RI);
59 void visitBranchInst(BranchInst &BI);
61 // Arithmetic operators
62 void visitSimpleBinary(BinaryOperator &B, unsigned OpcodeClass);
63 void visitAdd(BinaryOperator &B) { visitSimpleBinary(B, 0); }
64 void visitSub(BinaryOperator &B) { visitSimpleBinary(B, 1); }
65 void visitMul(BinaryOperator &B);
67 void visitDiv(BinaryOperator &B) { visitDivRem(B); }
68 void visitRem(BinaryOperator &B) { visitDivRem(B); }
69 void visitDivRem(BinaryOperator &B);
72 void visitAnd(BinaryOperator &B) { visitSimpleBinary(B, 2); }
73 void visitOr (BinaryOperator &B) { visitSimpleBinary(B, 3); }
74 void visitXor(BinaryOperator &B) { visitSimpleBinary(B, 4); }
76 // Binary comparison operators
79 void visitShiftInst(ShiftInst &I);
80 void visitSetCondInst(SetCondInst &I);
81 void visitPHINode(PHINode &I);
83 void visitInstruction(Instruction &I) {
84 std::cerr << "Cannot instruction select: " << I;
89 /// copyConstantToRegister - Output the instructions required to put the
90 /// specified constant into the specified register.
92 void copyConstantToRegister(Constant *C, unsigned Reg);
94 /// getReg - This method turns an LLVM value into a register number. This
95 /// is guaranteed to produce the same register number for a particular value
96 /// every time it is queried.
98 unsigned getReg(Value &V) { return getReg(&V); } // Allow references
99 unsigned getReg(Value *V) {
100 unsigned &Reg = RegMap[V];
104 // If this operand is a constant, emit the code to copy the constant into
105 // the register here...
107 if (Constant *C = dyn_cast<Constant>(V))
108 copyConstantToRegister(C, Reg);
115 /// TypeClass - Used by the X86 backend to group LLVM types by their basic X86
119 cByte, cShort, cInt, cLong, cFloat, cDouble
122 /// getClass - Turn a primitive type into a "class" number which is based on the
123 /// size of the type, and whether or not it is floating point.
125 static inline TypeClass getClass(const Type *Ty) {
126 switch (Ty->getPrimitiveID()) {
127 case Type::SByteTyID:
128 case Type::UByteTyID: return cByte; // Byte operands are class #0
129 case Type::ShortTyID:
130 case Type::UShortTyID: return cShort; // Short operands are class #1
133 case Type::PointerTyID: return cInt; // Int's and pointers are class #2
136 case Type::ULongTyID: return cLong; // Longs are class #3
137 case Type::FloatTyID: return cFloat; // Float is class #4
138 case Type::DoubleTyID: return cDouble; // Doubles are class #5
140 assert(0 && "Invalid type to getClass!");
141 return cByte; // not reached
145 /// copyConstantToRegister - Output the instructions required to put the
146 /// specified constant into the specified register.
148 void ISel::copyConstantToRegister(Constant *C, unsigned R) {
149 assert (!isa<ConstantExpr>(C) && "Constant expressions not yet handled!\n");
151 if (C->getType()->isIntegral()) {
152 unsigned Class = getClass(C->getType());
153 assert(Class != 3 && "Type not handled yet!");
155 static const unsigned IntegralOpcodeTab[] = {
156 X86::MOVir8, X86::MOVir16, X86::MOVir32
159 if (C->getType()->isSigned()) {
160 ConstantSInt *CSI = cast<ConstantSInt>(C);
161 BuildMI(BB, IntegralOpcodeTab[Class], 1, R).addSImm(CSI->getValue());
163 ConstantUInt *CUI = cast<ConstantUInt>(C);
164 BuildMI(BB, IntegralOpcodeTab[Class], 1, R).addZImm(CUI->getValue());
167 assert(0 && "Type not handled yet!");
171 /// SetCC instructions - Here we just emit boilerplate code to set a byte-sized
172 /// register, then move it to wherever the result should be.
173 /// We handle FP setcc instructions by pushing them, doing a
174 /// compare-and-pop-twice, and then copying the concodes to the main
175 /// processor's concodes (I didn't make this up, it's in the Intel manual)
178 ISel::visitSetCondInst (SetCondInst & I)
180 // The arguments are already supposed to be of the same type.
181 Value *var1 = I.getOperand (0);
182 Value *var2 = I.getOperand (1);
183 unsigned reg1 = getReg (var1);
184 unsigned reg2 = getReg (var2);
185 unsigned resultReg = getReg (I);
186 unsigned comparisonWidth = var1->getType ()->getPrimitiveSize ();
187 unsigned unsignedComparison = var1->getType ()->isUnsigned ();
188 unsigned resultWidth = I.getType ()->getPrimitiveSize ();
189 bool fpComparison = var1->getType ()->isFloatingPoint ();
192 // Push the variables on the stack with fldl opcodes.
193 // FIXME: assuming var1, var2 are in memory, if not, spill to
195 switch (comparisonWidth)
198 BuildMI (BB, X86::FLDr4, 1, X86::NoReg).addReg (reg1);
201 BuildMI (BB, X86::FLDr8, 1, X86::NoReg).addReg (reg1);
204 visitInstruction (I);
207 switch (comparisonWidth)
210 BuildMI (BB, X86::FLDr4, 1, X86::NoReg).addReg (reg2);
213 BuildMI (BB, X86::FLDr8, 1, X86::NoReg).addReg (reg2);
216 visitInstruction (I);
219 // (Non-trapping) compare and pop twice.
220 BuildMI (BB, X86::FUCOMPP, 0);
221 // Move fp status word (concodes) to ax.
222 BuildMI (BB, X86::FNSTSWr8, 1, X86::AX);
223 // Load real concodes from ax.
224 BuildMI (BB, X86::SAHF, 1, X86::EFLAGS).addReg(X86::AH);
227 { // integer comparison
228 // Emit: cmp <var1>, <var2> (do the comparison). We can
229 // compare 8-bit with 8-bit, 16-bit with 16-bit, 32-bit with
231 switch (comparisonWidth)
234 BuildMI (BB, X86::CMPrr8, 2,
235 X86::EFLAGS).addReg (reg1).addReg (reg2);
238 BuildMI (BB, X86::CMPrr16, 2,
239 X86::EFLAGS).addReg (reg1).addReg (reg2);
242 BuildMI (BB, X86::CMPrr32, 2,
243 X86::EFLAGS).addReg (reg1).addReg (reg2);
247 visitInstruction (I);
251 // Emit setOp instruction (extract concode; clobbers ax),
252 // using the following mapping:
253 // LLVM -> X86 signed X86 unsigned
255 // seteq -> sete sete
256 // setne -> setne setne
257 // setlt -> setl setb
258 // setgt -> setg seta
259 // setle -> setle setbe
260 // setge -> setge setae
261 switch (I.getOpcode ())
263 case Instruction::SetEQ:
264 BuildMI (BB, X86::SETE, 0, X86::AL);
266 case Instruction::SetGE:
267 if (unsignedComparison)
268 BuildMI (BB, X86::SETAE, 0, X86::AL);
270 BuildMI (BB, X86::SETGE, 0, X86::AL);
272 case Instruction::SetGT:
273 if (unsignedComparison)
274 BuildMI (BB, X86::SETA, 0, X86::AL);
276 BuildMI (BB, X86::SETG, 0, X86::AL);
278 case Instruction::SetLE:
279 if (unsignedComparison)
280 BuildMI (BB, X86::SETBE, 0, X86::AL);
282 BuildMI (BB, X86::SETLE, 0, X86::AL);
284 case Instruction::SetLT:
285 if (unsignedComparison)
286 BuildMI (BB, X86::SETB, 0, X86::AL);
288 BuildMI (BB, X86::SETL, 0, X86::AL);
290 case Instruction::SetNE:
291 BuildMI (BB, X86::SETNE, 0, X86::AL);
294 visitInstruction (I);
297 // Put it in the result using a move.
301 BuildMI (BB, X86::MOVrr8, 1, resultReg).addReg (X86::AL);
304 BuildMI (BB, X86::MOVZXr16r8, 1, resultReg).addReg (X86::AL);
307 BuildMI (BB, X86::MOVZXr32r8, 1, resultReg).addReg (X86::AL);
311 visitInstruction (I);
317 /// 'ret' instruction - Here we are interested in meeting the x86 ABI. As such,
318 /// we have the following possibilities:
320 /// ret void: No return value, simply emit a 'ret' instruction
321 /// ret sbyte, ubyte : Extend value into EAX and return
322 /// ret short, ushort: Extend value into EAX and return
323 /// ret int, uint : Move value into EAX and return
324 /// ret pointer : Move value into EAX and return
325 /// ret long, ulong : Move value into EAX/EDX (?) and return
326 /// ret float/double : ? Top of FP stack? XMM0?
328 void ISel::visitReturnInst (ReturnInst & I) {
329 if (I.getNumOperands() == 0) {
330 // Emit a 'ret' instruction
331 BuildMI(BB, X86::RET, 0);
335 unsigned val = getReg(I.getOperand(0));
336 unsigned Class = getClass(I.getType());
337 bool isUnsigned = I.getOperand(0)->getType()->isUnsigned();
340 // ret sbyte, ubyte: Extend value into EAX and return
342 BuildMI (BB, X86::MOVZXr32r8, 1, X86::EAX).addReg (val);
344 BuildMI (BB, X86::MOVSXr32r8, 1, X86::EAX).addReg (val);
348 // ret short, ushort: Extend value into EAX and return
349 if (unsignedReturnValue) {
350 BuildMI (BB, X86::MOVZXr32r16, 1, X86::EAX).addReg (val);
352 BuildMI (BB, X86::MOVSXr32r16, 1, X86::EAX).addReg (val);
356 // ret int, uint, ptr: Move value into EAX and return
358 BuildMI(BB, X86::MOVrr32, 1, X86::EAX).addReg(val);
361 // ret float/double: top of FP stack
363 case cFloat: // Floats
364 BuildMI(BB, X86::FLDr4, 1).addReg(val);
366 case cDouble: // Doubles
367 BuildMI(BB, X86::FLDr8, 1).addReg(val);
370 // ret long: use EAX(least significant 32 bits)/EDX (most
371 // significant 32)...uh, I think so Brain, but how do i call
372 // up the two parts of the value from inside this mouse
378 // Emit a 'ret' instruction
379 BuildMI(BB, X86::RET, 0);
382 /// visitBranchInst - Handle conditional and unconditional branches here. Note
383 /// that since code layout is frozen at this point, that if we are trying to
384 /// jump to a block that is the immediate successor of the current block, we can
385 /// just make a fall-through. (but we don't currently).
387 void ISel::visitBranchInst(BranchInst &BI) {
388 if (BI.isConditional()) // Only handles unconditional branches so far...
389 visitInstruction(BI);
391 BuildMI(BB, X86::JMP, 1).addPCDisp(BI.getSuccessor(0));
395 /// visitSimpleBinary - Implement simple binary operators for integral types...
396 /// OperatorClass is one of: 0 for Add, 1 for Sub, 2 for And, 3 for Or,
399 void ISel::visitSimpleBinary(BinaryOperator &B, unsigned OperatorClass) {
400 if (B.getType() == Type::BoolTy) // FIXME: Handle bools for logicals
403 unsigned Class = getClass(B.getType());
404 if (Class > 2) // FIXME: Handle longs
407 static const unsigned OpcodeTab[][4] = {
408 // Arithmetic operators
409 { X86::ADDrr8, X86::ADDrr16, X86::ADDrr32, 0 }, // ADD
410 { X86::SUBrr8, X86::SUBrr16, X86::SUBrr32, 0 }, // SUB
413 { X86::ANDrr8, X86::ANDrr16, X86::ANDrr32, 0 }, // AND
414 { X86:: ORrr8, X86:: ORrr16, X86:: ORrr32, 0 }, // OR
415 { X86::XORrr8, X86::XORrr16, X86::XORrr32, 0 }, // XOR
418 unsigned Opcode = OpcodeTab[OperatorClass][Class];
419 unsigned Op0r = getReg(B.getOperand(0));
420 unsigned Op1r = getReg(B.getOperand(1));
421 BuildMI(BB, Opcode, 2, getReg(B)).addReg(Op0r).addReg(Op1r);
424 /// visitMul - Multiplies are not simple binary operators because they must deal
425 /// with the EAX register explicitly.
427 void ISel::visitMul(BinaryOperator &I) {
428 unsigned Class = getClass(I.getType());
429 if (Class > 2) // FIXME: Handle longs
432 static const unsigned Regs[] ={ X86::AL , X86::AX , X86::EAX };
433 static const unsigned MulOpcode[]={ X86::MULrr8, X86::MULrr16, X86::MULrr32 };
434 static const unsigned MovOpcode[]={ X86::MOVrr8, X86::MOVrr16, X86::MOVrr32 };
436 unsigned Reg = Regs[Class];
437 unsigned Op0Reg = getReg(I.getOperand(1));
438 unsigned Op1Reg = getReg(I.getOperand(1));
440 // Put the first operand into one of the A registers...
441 BuildMI(BB, MovOpcode[Class], 1, Reg).addReg(Op0Reg);
443 // Emit the appropriate multiple instruction...
444 // FIXME: We need to mark that this modified AH, DX, or EDX also!!
445 BuildMI(BB, MulOpcode[Class], 2, Reg).addReg(Reg).addReg(Op1Reg);
447 // Put the result into the destination register...
448 BuildMI(BB, MovOpcode[Class], 1, getReg(I)).addReg(Reg);
451 /// visitDivRem - Handle division and remainder instructions... these
452 /// instruction both require the same instructions to be generated, they just
453 /// select the result from a different register. Note that both of these
454 /// instructions work differently for signed and unsigned operands.
456 void ISel::visitDivRem(BinaryOperator &I) {
457 unsigned Class = getClass(I.getType());
458 if (Class > 2) // FIXME: Handle longs
461 static const unsigned Regs[] ={ X86::AL , X86::AX , X86::EAX };
462 static const unsigned MovOpcode[]={ X86::MOVrr8, X86::MOVrr16, X86::MOVrr32 };
463 static const unsigned ExtOpcode[]={ X86::CBW , X86::CWD , X86::CDQ };
464 static const unsigned ClrOpcode[]={ X86::XORrr8, X86::XORrr16, X86::XORrr32 };
465 static const unsigned ExtRegs[] ={ X86::AH , X86::DX , X86::EDX };
467 static const unsigned DivOpcode[][4] = {
468 { X86::DIVrr8 , X86::DIVrr16 , X86::DIVrr32 , 0 }, // Unsigned division
469 { X86::IDIVrr8, X86::IDIVrr16, X86::IDIVrr32, 0 }, // Signed division
472 bool isSigned = I.getType()->isSigned();
473 unsigned Reg = Regs[Class];
474 unsigned ExtReg = ExtRegs[Class];
475 unsigned Op0Reg = getReg(I.getOperand(1));
476 unsigned Op1Reg = getReg(I.getOperand(1));
478 // Put the first operand into one of the A registers...
479 BuildMI(BB, MovOpcode[Class], 1, Reg).addReg(Op0Reg);
482 // Emit a sign extension instruction...
483 BuildMI(BB, ExtOpcode[Class], 1, ExtReg).addReg(Reg);
485 // If unsigned, emit a zeroing instruction... (reg = xor reg, reg)
486 BuildMI(BB, ClrOpcode[Class], 2, ExtReg).addReg(ExtReg).addReg(ExtReg);
489 // Figure out which register we want to pick the result out of...
490 unsigned DestReg = (I.getOpcode() == Instruction::Div) ? Reg : ExtReg;
492 // Emit the appropriate divide or remainder instruction...
493 // FIXME: We need to mark that this modified AH, DX, or EDX also!!
494 BuildMI(BB,DivOpcode[isSigned][Class], 2, DestReg).addReg(Reg).addReg(Op1Reg);
496 // Put the result into the destination register...
497 BuildMI(BB, MovOpcode[Class], 1, getReg(I)).addReg(DestReg);
500 /// Shift instructions: 'shl', 'sar', 'shr' - Some special cases here
501 /// for constant immediate shift values, and for constant immediate
502 /// shift values equal to 1. Even the general case is sort of special,
503 /// because the shift amount has to be in CL, not just any old register.
505 void ISel::visitShiftInst (ShiftInst &I) {
506 unsigned Op0r = getReg (I.getOperand(0));
507 unsigned DestReg = getReg(I);
508 bool isLeftShift = I.getOpcode() == Instruction::Shl;
509 bool isOperandSigned = I.getType()->isUnsigned();
510 unsigned OperandClass = getClass(I.getType());
512 if (OperandClass > 2)
513 visitInstruction(I); // Can't handle longs yet!
515 if (ConstantUInt *CUI = dyn_cast <ConstantUInt> (I.getOperand (1)))
517 // The shift amount is constant, guaranteed to be a ubyte. Get its value.
518 assert(CUI->getType() == Type::UByteTy && "Shift amount not a ubyte?");
519 unsigned char shAmt = CUI->getValue();
521 static const unsigned ConstantOperand[][4] = {
522 { X86::SHRir8, X86::SHRir16, X86::SHRir32, 0 }, // SHR
523 { X86::SARir8, X86::SARir16, X86::SARir32, 0 }, // SAR
524 { X86::SHLir8, X86::SHLir16, X86::SHLir32, 0 }, // SHL
525 { X86::SHLir8, X86::SHLir16, X86::SHLir32, 0 }, // SAL = SHL
528 const unsigned *OpTab = // Figure out the operand table to use
529 ConstantOperand[isLeftShift*2+isOperandSigned];
531 // Emit: <insn> reg, shamt (shift-by-immediate opcode "ir" form.)
532 BuildMI(BB, OpTab[OperandClass], 2, DestReg).addReg(Op0r).addZImm(shAmt);
536 // The shift amount is non-constant.
538 // In fact, you can only shift with a variable shift amount if
539 // that amount is already in the CL register, so we have to put it
543 // Emit: move cl, shiftAmount (put the shift amount in CL.)
544 BuildMI(BB, X86::MOVrr8, 1, X86::CL).addReg(getReg(I.getOperand(1)));
546 // This is a shift right (SHR).
547 static const unsigned NonConstantOperand[][4] = {
548 { X86::SHRrr8, X86::SHRrr16, X86::SHRrr32, 0 }, // SHR
549 { X86::SARrr8, X86::SARrr16, X86::SARrr32, 0 }, // SAR
550 { X86::SHLrr8, X86::SHLrr16, X86::SHLrr32, 0 }, // SHL
551 { X86::SHLrr8, X86::SHLrr16, X86::SHLrr32, 0 }, // SAL = SHL
554 const unsigned *OpTab = // Figure out the operand table to use
555 NonConstantOperand[isLeftShift*2+isOperandSigned];
557 BuildMI(BB, OpTab[OperandClass], 2, DestReg).addReg(Op0r).addReg(X86::CL);
561 /// visitPHINode - Turn an LLVM PHI node into an X86 PHI node...
563 void ISel::visitPHINode(PHINode &PN) {
564 MachineInstr *MI = BuildMI(BB, X86::PHI, PN.getNumOperands(), getReg(PN));
566 for (unsigned i = 0, e = PN.getNumIncomingValues(); i != e; ++i) {
567 // FIXME: This will put constants after the PHI nodes in the block, which
568 // is invalid. They should be put inline into the PHI node eventually.
570 MI->addRegOperand(getReg(PN.getIncomingValue(i)));
571 MI->addPCDispOperand(PN.getIncomingBlock(i));
576 /// createSimpleX86InstructionSelector - This pass converts an LLVM function
577 /// into a machine code representation is a very simple peep-hole fashion. The
578 /// generated code sucks but the implementation is nice and simple.
580 Pass *createSimpleX86InstructionSelector(TargetMachine &TM) {