1 //===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_X86_X86ISELLOWERING_H
16 #define LLVM_LIB_TARGET_X86_X86ISELLOWERING_H
18 #include "llvm/CodeGen/CallingConvLower.h"
19 #include "llvm/CodeGen/SelectionDAG.h"
20 #include "llvm/Target/TargetLowering.h"
21 #include "llvm/Target/TargetOptions.h"
25 class X86TargetMachine;
28 // X86 Specific DAG Nodes
30 // Start the numbering where the builtin ops leave off.
31 FIRST_NUMBER = ISD::BUILTIN_OP_END,
38 /// Double shift instructions. These correspond to
39 /// X86::SHLDxx and X86::SHRDxx instructions.
43 /// Bitwise logical AND of floating point values. This corresponds
44 /// to X86::ANDPS or X86::ANDPD.
47 /// Bitwise logical OR of floating point values. This corresponds
48 /// to X86::ORPS or X86::ORPD.
51 /// Bitwise logical XOR of floating point values. This corresponds
52 /// to X86::XORPS or X86::XORPD.
55 /// Bitwise logical ANDNOT of floating point values. This
56 /// corresponds to X86::ANDNPS or X86::ANDNPD.
59 /// Bitwise logical right shift of floating point values. This
60 /// corresponds to X86::PSRLDQ.
63 /// These operations represent an abstract X86 call
64 /// instruction, which includes a bunch of information. In particular the
65 /// operands of these node are:
67 /// #0 - The incoming token chain
69 /// #2 - The number of arg bytes the caller pushes on the stack.
70 /// #3 - The number of arg bytes the callee pops off the stack.
71 /// #4 - The value to pass in AL/AX/EAX (optional)
72 /// #5 - The value to pass in DL/DX/EDX (optional)
74 /// The result values of these nodes are:
76 /// #0 - The outgoing token chain
77 /// #1 - The first register result value (optional)
78 /// #2 - The second register result value (optional)
82 /// This operation implements the lowering for readcyclecounter
85 /// X86 Read Time-Stamp Counter and Processor ID.
88 /// X86 Read Performance Monitoring Counters.
91 /// X86 compare and logical compare instructions.
94 /// X86 bit-test instructions.
97 /// X86 SetCC. Operand 0 is condition code, and operand 1 is the EFLAGS
98 /// operand, usually produced by a CMP instruction.
104 // Same as SETCC except it's materialized with a sbb and the value is all
105 // one's or all zero's.
106 SETCC_CARRY, // R = carry_bit ? ~0 : 0
108 /// X86 FP SETCC, implemented with CMP{cc}SS/CMP{cc}SD.
109 /// Operands are two FP values to compare; result is a mask of
110 /// 0s or 1s. Generally DTRT for C/C++ with NaNs.
113 /// X86 MOVMSK{pd|ps}, extracts sign bits of two or four FP values,
114 /// result in an integer GPR. Needs masking for scalar result.
117 /// X86 conditional moves. Operand 0 and operand 1 are the two values
118 /// to select from. Operand 2 is the condition code, and operand 3 is the
119 /// flag operand produced by a CMP or TEST instruction. It also writes a
123 /// X86 conditional branches. Operand 0 is the chain operand, operand 1
124 /// is the block to branch if condition is true, operand 2 is the
125 /// condition code, and operand 3 is the flag operand produced by a CMP
126 /// or TEST instruction.
129 /// Return with a flag operand. Operand 0 is the chain operand, operand
130 /// 1 is the number of bytes of stack to pop.
133 /// Repeat fill, corresponds to X86::REP_STOSx.
136 /// Repeat move, corresponds to X86::REP_MOVSx.
139 /// On Darwin, this node represents the result of the popl
140 /// at function entry, used for PIC code.
143 /// A wrapper node for TargetConstantPool,
144 /// TargetExternalSymbol, and TargetGlobalAddress.
147 /// Special wrapper used under X86-64 PIC mode for RIP
148 /// relative displacements.
151 /// Copies a 64-bit value from the low word of an XMM vector
152 /// to an MMX vector. If you think this is too close to the previous
153 /// mnemonic, so do I; blame Intel.
156 /// Copies a 32-bit value from the low word of a MMX
160 /// Copies a GPR into the low 32-bit word of a MMX vector
161 /// and zero out the high word.
164 /// Extract an 8-bit value from a vector and zero extend it to
165 /// i32, corresponds to X86::PEXTRB.
168 /// Extract a 16-bit value from a vector and zero extend it to
169 /// i32, corresponds to X86::PEXTRW.
172 /// Insert any element of a 4 x float vector into any element
173 /// of a destination 4 x floatvector.
176 /// Insert the lower 8-bits of a 32-bit value to a vector,
177 /// corresponds to X86::PINSRB.
180 /// Insert the lower 16-bits of a 32-bit value to a vector,
181 /// corresponds to X86::PINSRW.
184 /// Shuffle 16 8-bit values within a vector.
187 /// Bitwise Logical AND NOT of Packed FP values.
190 /// Copy integer sign.
193 /// Blend where the selector is an immediate.
196 /// Blend where the condition has been shrunk.
197 /// This is used to emphasize that the condition mask is
198 /// no more valid for generic VSELECT optimizations.
201 /// Combined add and sub on an FP vector.
203 // FP vector ops with rounding mode.
209 // Integer add/sub with unsigned saturation.
212 // Integer add/sub with signed saturation.
216 /// Integer horizontal add.
219 /// Integer horizontal sub.
222 /// Floating point horizontal add.
225 /// Floating point horizontal sub.
228 /// Unsigned integer max and min.
231 /// Signed integer max and min.
234 /// Floating point max and min.
237 /// Commutative FMIN and FMAX.
240 /// Floating point reciprocal-sqrt and reciprocal approximation.
241 /// Note that these typically require refinement
242 /// in order to obtain suitable precision.
245 // Thread Local Storage.
248 // Thread Local Storage. A call to get the start address
249 // of the TLS block for the current module.
252 // Thread Local Storage. When calling to an OS provided
253 // thunk at the address from an earlier relocation.
256 // Exception Handling helpers.
259 // SjLj exception handling setjmp.
262 // SjLj exception handling longjmp.
265 /// Tail call return. See X86TargetLowering::LowerCall for
266 /// the list of operands.
269 // Vector move to low scalar and zero higher vector elements.
272 // Vector integer zero-extend.
275 // Vector integer signed-extend.
278 // Vector integer truncate.
281 // Vector integer truncate with mask.
290 // 128-bit vector logical left / right shift
293 // Vector shift elements
296 // Vector shift elements by immediate
299 // Vector packed double/float comparison.
302 // Vector integer comparisons.
304 // Vector integer comparisons, the result is in a mask vector.
307 /// Vector comparison generating mask bits for fp and
308 /// integer signed and unsigned data types.
311 // Vector comparison with rounding mode for FP values
314 // Arithmetic operations with FLAGS results.
315 ADD, SUB, ADC, SBB, SMUL,
316 INC, DEC, OR, XOR, AND,
318 BEXTR, // Bit field extract
320 UMUL, // LOW, HI, FLAGS = umul LHS, RHS
322 // 8-bit SMUL/UMUL - AX, FLAGS = smul8/umul8 AL, RHS
325 // 8-bit divrem that zero-extend the high result (AH).
329 // X86-specific multiply by immediate.
332 // Vector bitwise comparisons.
335 // Vector packed fp sign bitwise comparisons.
338 // Vector "test" in AVX-512, the result is in a mask vector.
342 // OR/AND test for masks
345 // Several flavors of instructions with vector shuffle behaviors.
350 // AVX512 inter-lane alignr
376 // Insert/Extract vector element
380 // Vector multiply packed unsigned doubleword integers
382 // Vector multiply packed signed doubleword integers
392 // FMA with rounding mode
401 // Compress and expand
405 // Save xmm argument registers to the stack, according to %al. An operator
406 // is needed so that this can be expanded with control flow.
407 VASTART_SAVE_XMM_REGS,
409 // Windows's _chkstk call to do stack probing.
412 // For allocating variable amounts of stack space when using
413 // segmented stacks. Check if the current stacklet has enough space, and
414 // falls back to heap allocation if not.
417 // Windows's _ftol2 runtime routine to do fptoui.
426 // Store FP status word into i16 register.
429 // Store contents of %ah into %eflags.
432 // Get a random integer and indicate whether it is valid in CF.
435 // Get a NIST SP800-90B & C compliant random integer and
436 // indicate whether it is valid in CF.
442 // Test if in transactional execution.
446 RSQRT28, RCP28, EXP2,
449 LCMPXCHG_DAG = ISD::FIRST_TARGET_MEMORY_OPCODE,
453 // Load, scalar_to_vector, and zero extend.
456 // Store FP control world into i16 memory.
459 /// This instruction implements FP_TO_SINT with the
460 /// integer destination in memory and a FP reg source. This corresponds
461 /// to the X86::FIST*m instructions and the rounding mode change stuff. It
462 /// has two inputs (token chain and address) and two outputs (int value
463 /// and token chain).
468 /// This instruction implements SINT_TO_FP with the
469 /// integer source in memory and FP reg result. This corresponds to the
470 /// X86::FILD*m instructions. It has three inputs (token chain, address,
471 /// and source type) and two outputs (FP value and token chain). FILD_FLAG
472 /// also produces a flag).
476 /// This instruction implements an extending load to FP stack slots.
477 /// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain
478 /// operand, ptr to load from, and a ValueType node indicating the type
482 /// This instruction implements a truncating store to FP stack
483 /// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a
484 /// chain operand, value to store, address, and a ValueType to store it
488 /// This instruction grabs the address of the next argument
489 /// from a va_list. (reads and modifies the va_list in memory)
492 // WARNING: Do not add anything in the end unless you want the node to
493 // have memop! In fact, starting from ATOMADD64_DAG all opcodes will be
494 // thought as target memory ops!
498 /// Define some predicates that are used for node matching.
500 /// Return true if the specified
501 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
502 /// suitable for input to VEXTRACTF128, VEXTRACTI128 instructions.
503 bool isVEXTRACT128Index(SDNode *N);
505 /// Return true if the specified
506 /// INSERT_SUBVECTOR operand specifies a subvector insert that is
507 /// suitable for input to VINSERTF128, VINSERTI128 instructions.
508 bool isVINSERT128Index(SDNode *N);
510 /// Return true if the specified
511 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
512 /// suitable for input to VEXTRACTF64X4, VEXTRACTI64X4 instructions.
513 bool isVEXTRACT256Index(SDNode *N);
515 /// Return true if the specified
516 /// INSERT_SUBVECTOR operand specifies a subvector insert that is
517 /// suitable for input to VINSERTF64X4, VINSERTI64X4 instructions.
518 bool isVINSERT256Index(SDNode *N);
520 /// Return the appropriate
521 /// immediate to extract the specified EXTRACT_SUBVECTOR index
522 /// with VEXTRACTF128, VEXTRACTI128 instructions.
523 unsigned getExtractVEXTRACT128Immediate(SDNode *N);
525 /// Return the appropriate
526 /// immediate to insert at the specified INSERT_SUBVECTOR index
527 /// with VINSERTF128, VINSERT128 instructions.
528 unsigned getInsertVINSERT128Immediate(SDNode *N);
530 /// Return the appropriate
531 /// immediate to extract the specified EXTRACT_SUBVECTOR index
532 /// with VEXTRACTF64X4, VEXTRACTI64x4 instructions.
533 unsigned getExtractVEXTRACT256Immediate(SDNode *N);
535 /// Return the appropriate
536 /// immediate to insert at the specified INSERT_SUBVECTOR index
537 /// with VINSERTF64x4, VINSERTI64x4 instructions.
538 unsigned getInsertVINSERT256Immediate(SDNode *N);
540 /// Returns true if Elt is a constant zero or floating point constant +0.0.
541 bool isZeroNode(SDValue Elt);
543 /// Returns true of the given offset can be
544 /// fit into displacement field of the instruction.
545 bool isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
546 bool hasSymbolicDisplacement = true);
549 /// Determines whether the callee is required to pop its
550 /// own arguments. Callee pop is necessary to support tail calls.
551 bool isCalleePop(CallingConv::ID CallingConv,
552 bool is64Bit, bool IsVarArg, bool TailCallOpt);
554 /// AVX512 static rounding constants. These need to match the values in
556 enum STATIC_ROUNDING {
565 //===--------------------------------------------------------------------===//
566 // X86 Implementation of the TargetLowering interface
567 class X86TargetLowering final : public TargetLowering {
569 explicit X86TargetLowering(const X86TargetMachine &TM,
570 const X86Subtarget &STI);
572 unsigned getJumpTableEncoding() const override;
574 MVT getScalarShiftAmountTy(EVT LHSTy) const override { return MVT::i8; }
577 LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
578 const MachineBasicBlock *MBB, unsigned uid,
579 MCContext &Ctx) const override;
581 /// Returns relocation base for the given PIC jumptable.
582 SDValue getPICJumpTableRelocBase(SDValue Table,
583 SelectionDAG &DAG) const override;
585 getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
586 unsigned JTI, MCContext &Ctx) const override;
588 /// Return the desired alignment for ByVal aggregate
589 /// function arguments in the caller parameter area. For X86, aggregates
590 /// that contains are placed at 16-byte boundaries while the rest are at
591 /// 4-byte boundaries.
592 unsigned getByValTypeAlignment(Type *Ty) const override;
594 /// Returns the target specific optimal type for load
595 /// and store operations as a result of memset, memcpy, and memmove
596 /// lowering. If DstAlign is zero that means it's safe to destination
597 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
598 /// means there isn't a need to check it against alignment requirement,
599 /// probably because the source does not need to be loaded. If 'IsMemset' is
600 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
601 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
602 /// source is constant so it does not need to be loaded.
603 /// It returns EVT::Other if the type should be determined using generic
604 /// target-independent logic.
605 EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
606 bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc,
607 MachineFunction &MF) const override;
609 /// Returns true if it's safe to use load / store of the
610 /// specified type to expand memcpy / memset inline. This is mostly true
611 /// for all types except for some special cases. For example, on X86
612 /// targets without SSE2 f64 load / store are done with fldl / fstpl which
613 /// also does type conversion. Note the specified type doesn't have to be
614 /// legal as the hook is used before type legalization.
615 bool isSafeMemOpType(MVT VT) const override;
617 /// Returns true if the target allows
618 /// unaligned memory accesses. of the specified type. Returns whether it
619 /// is "fast" by reference in the second argument.
620 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, unsigned Align,
621 bool *Fast) const override;
623 /// Provide custom lowering hooks for some operations.
625 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
627 /// Replace the results of node with an illegal result
628 /// type with new values built out of custom code.
630 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
631 SelectionDAG &DAG) const override;
634 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
636 /// Return true if the target has native support for
637 /// the specified value type and it is 'desirable' to use the type for the
638 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
639 /// instruction encodings are longer and some i16 instructions are slow.
640 bool isTypeDesirableForOp(unsigned Opc, EVT VT) const override;
642 /// Return true if the target has native support for the
643 /// specified value type and it is 'desirable' to use the type. e.g. On x86
644 /// i16 is legal, but undesirable since i16 instruction encodings are longer
645 /// and some i16 instructions are slow.
646 bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const override;
649 EmitInstrWithCustomInserter(MachineInstr *MI,
650 MachineBasicBlock *MBB) const override;
653 /// This method returns the name of a target specific DAG node.
654 const char *getTargetNodeName(unsigned Opcode) const override;
656 bool isCheapToSpeculateCttz() const override;
658 bool isCheapToSpeculateCtlz() const override;
660 /// Return the value type to use for ISD::SETCC.
661 EVT getSetCCResultType(LLVMContext &Context, EVT VT) const override;
663 /// Determine which of the bits specified in Mask are known to be either
664 /// zero or one and return them in the KnownZero/KnownOne bitsets.
665 void computeKnownBitsForTargetNode(const SDValue Op,
668 const SelectionDAG &DAG,
669 unsigned Depth = 0) const override;
671 /// Determine the number of bits in the operation that are sign bits.
672 unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
673 const SelectionDAG &DAG,
674 unsigned Depth) const override;
676 bool isGAPlusOffset(SDNode *N, const GlobalValue* &GA,
677 int64_t &Offset) const override;
679 SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
681 bool ExpandInlineAsm(CallInst *CI) const override;
684 getConstraintType(const std::string &Constraint) const override;
686 /// Examine constraint string and operand type and determine a weight value.
687 /// The operand object must already have been set up with the operand type.
689 getSingleConstraintMatchWeight(AsmOperandInfo &info,
690 const char *constraint) const override;
692 const char *LowerXConstraint(EVT ConstraintVT) const override;
694 /// Lower the specified operand into the Ops vector. If it is invalid, don't
695 /// add anything to Ops. If hasMemory is true it means one of the asm
696 /// constraint of the inline asm instruction being processed is 'm'.
697 void LowerAsmOperandForConstraint(SDValue Op,
698 std::string &Constraint,
699 std::vector<SDValue> &Ops,
700 SelectionDAG &DAG) const override;
702 unsigned getInlineAsmMemConstraint(
703 const std::string &ConstraintCode) const override {
704 // FIXME: Map different constraints differently.
705 return InlineAsm::Constraint_m;
708 /// Given a physical register constraint
709 /// (e.g. {edx}), return the register number and the register class for the
710 /// register. This should only be used for C_Register constraints. On
711 /// error, this returns a register number of 0.
712 std::pair<unsigned, const TargetRegisterClass *>
713 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
714 const std::string &Constraint,
715 MVT VT) const override;
717 /// Return true if the addressing mode represented
718 /// by AM is legal for this target, for a load/store of the specified type.
719 bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const override;
721 /// Return true if the specified immediate is legal
722 /// icmp immediate, that is the target has icmp instructions which can
723 /// compare a register against the immediate without having to materialize
724 /// the immediate into a register.
725 bool isLegalICmpImmediate(int64_t Imm) const override;
727 /// Return true if the specified immediate is legal
728 /// add immediate, that is the target has add instructions which can
729 /// add a register and the immediate without having to materialize
730 /// the immediate into a register.
731 bool isLegalAddImmediate(int64_t Imm) const override;
733 /// \brief Return the cost of the scaling factor used in the addressing
734 /// mode represented by AM for this target, for a load/store
735 /// of the specified type.
736 /// If the AM is supported, the return value must be >= 0.
737 /// If the AM is not supported, it returns a negative value.
738 int getScalingFactorCost(const AddrMode &AM, Type *Ty) const override;
740 bool isVectorShiftByScalarCheap(Type *Ty) const override;
742 /// Return true if it's free to truncate a value of
743 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
744 /// register EAX to i16 by referencing its sub-register AX.
745 bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
746 bool isTruncateFree(EVT VT1, EVT VT2) const override;
748 bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override;
750 /// Return true if any actual instruction that defines a
751 /// value of type Ty1 implicit zero-extends the value to Ty2 in the result
752 /// register. This does not necessarily include registers defined in
753 /// unknown ways, such as incoming arguments, or copies from unknown
754 /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this
755 /// does not necessarily apply to truncate instructions. e.g. on x86-64,
756 /// all instructions that define 32-bit values implicit zero-extend the
757 /// result out to 64 bits.
758 bool isZExtFree(Type *Ty1, Type *Ty2) const override;
759 bool isZExtFree(EVT VT1, EVT VT2) const override;
760 bool isZExtFree(SDValue Val, EVT VT2) const override;
762 /// Return true if folding a vector load into ExtVal (a sign, zero, or any
763 /// extend node) is profitable.
764 bool isVectorLoadExtDesirable(SDValue) const override;
766 /// Return true if an FMA operation is faster than a pair of fmul and fadd
767 /// instructions. fmuladd intrinsics will be expanded to FMAs when this
768 /// method returns true, otherwise fmuladd is expanded to fmul + fadd.
769 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
771 /// Return true if it's profitable to narrow
772 /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow
773 /// from i32 to i8 but not from i32 to i16.
774 bool isNarrowingProfitable(EVT VT1, EVT VT2) const override;
776 /// Returns true if the target can instruction select the
777 /// specified FP immediate natively. If false, the legalizer will
778 /// materialize the FP immediate as a load from a constant pool.
779 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
781 /// Targets can use this to indicate that they only support *some*
782 /// VECTOR_SHUFFLE operations, those with specific masks. By default, if a
783 /// target supports the VECTOR_SHUFFLE node, all mask values are assumed to
785 bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask,
786 EVT VT) const override;
788 /// Similar to isShuffleMaskLegal. This is used by Targets can use this to
789 /// indicate if there is a suitable VECTOR_SHUFFLE that can be used to
790 /// replace a VAND with a constant pool entry.
791 bool isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
792 EVT VT) const override;
794 /// If true, then instruction selection should
795 /// seek to shrink the FP constant of the specified type to a smaller type
796 /// in order to save space and / or reduce runtime.
797 bool ShouldShrinkFPConstant(EVT VT) const override {
798 // Don't shrink FP constpool if SSE2 is available since cvtss2sd is more
799 // expensive than a straight movsd. On the other hand, it's important to
800 // shrink long double fp constant since fldt is very slow.
801 return !X86ScalarSSEf64 || VT == MVT::f80;
804 /// Return true if we believe it is correct and profitable to reduce the
805 /// load node to a smaller type.
806 bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy,
807 EVT NewVT) const override;
809 /// Return true if the specified scalar FP type is computed in an SSE
810 /// register, not on the X87 floating point stack.
811 bool isScalarFPTypeInSSEReg(EVT VT) const {
812 return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2
813 (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1
816 /// Return true if the target uses the MSVC _ftol2 routine for fptoui.
817 bool isTargetFTOL() const;
819 /// Return true if the MSVC _ftol2 routine should be used for fptoui to the
821 bool isIntegerTypeFTOL(EVT VT) const {
822 return isTargetFTOL() && VT == MVT::i64;
825 /// \brief Returns true if it is beneficial to convert a load of a constant
826 /// to just the constant itself.
827 bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
828 Type *Ty) const override;
830 /// Return true if EXTRACT_SUBVECTOR is cheap for this result type
832 bool isExtractSubvectorCheap(EVT ResVT, unsigned Index) const override;
834 /// Intel processors have a unified instruction and data cache
835 const char * getClearCacheBuiltinName() const override {
836 return nullptr; // nothing to do, move along.
839 unsigned getRegisterByName(const char* RegName, EVT VT) const override;
841 /// This method returns a target specific FastISel object,
842 /// or null if the target does not support "fast" ISel.
843 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
844 const TargetLibraryInfo *libInfo) const override;
846 /// Return true if the target stores stack protector cookies at a fixed
847 /// offset in some non-standard address space, and populates the address
848 /// space and offset as appropriate.
849 bool getStackCookieLocation(unsigned &AddressSpace,
850 unsigned &Offset) const override;
852 SDValue BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, SDValue StackSlot,
853 SelectionDAG &DAG) const;
855 bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override;
857 bool useLoadStackGuardNode() const override;
858 /// \brief Customize the preferred legalization strategy for certain types.
859 LegalizeTypeAction getPreferredVectorAction(EVT VT) const override;
862 std::pair<const TargetRegisterClass *, uint8_t>
863 findRepresentativeClass(const TargetRegisterInfo *TRI,
864 MVT VT) const override;
867 /// Keep a pointer to the X86Subtarget around so that we can
868 /// make the right decision when generating code for different targets.
869 const X86Subtarget *Subtarget;
870 const DataLayout *TD;
872 /// Select between SSE or x87 floating point ops.
873 /// When SSE is available, use it for f32 operations.
874 /// When SSE2 is available, use it for f64 operations.
875 bool X86ScalarSSEf32;
876 bool X86ScalarSSEf64;
878 /// A list of legal FP immediates.
879 std::vector<APFloat> LegalFPImmediates;
881 /// Indicate that this x86 target can instruction
882 /// select the specified FP immediate natively.
883 void addLegalFPImmediate(const APFloat& Imm) {
884 LegalFPImmediates.push_back(Imm);
887 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
888 CallingConv::ID CallConv, bool isVarArg,
889 const SmallVectorImpl<ISD::InputArg> &Ins,
890 SDLoc dl, SelectionDAG &DAG,
891 SmallVectorImpl<SDValue> &InVals) const;
892 SDValue LowerMemArgument(SDValue Chain,
893 CallingConv::ID CallConv,
894 const SmallVectorImpl<ISD::InputArg> &ArgInfo,
895 SDLoc dl, SelectionDAG &DAG,
896 const CCValAssign &VA, MachineFrameInfo *MFI,
898 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
899 SDLoc dl, SelectionDAG &DAG,
900 const CCValAssign &VA,
901 ISD::ArgFlagsTy Flags) const;
903 // Call lowering helpers.
905 /// Check whether the call is eligible for tail call optimization. Targets
906 /// that want to do tail call optimization should implement this function.
907 bool IsEligibleForTailCallOptimization(SDValue Callee,
908 CallingConv::ID CalleeCC,
910 bool isCalleeStructRet,
911 bool isCallerStructRet,
913 const SmallVectorImpl<ISD::OutputArg> &Outs,
914 const SmallVectorImpl<SDValue> &OutVals,
915 const SmallVectorImpl<ISD::InputArg> &Ins,
916 SelectionDAG& DAG) const;
917 bool IsCalleePop(bool isVarArg, CallingConv::ID CallConv) const;
918 SDValue EmitTailCallLoadRetAddr(SelectionDAG &DAG, SDValue &OutRetAddr,
919 SDValue Chain, bool IsTailCall, bool Is64Bit,
920 int FPDiff, SDLoc dl) const;
922 unsigned GetAlignedArgumentStackSize(unsigned StackSize,
923 SelectionDAG &DAG) const;
925 std::pair<SDValue,SDValue> FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
927 bool isReplace) const;
929 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
930 SDValue LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const;
931 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
932 SDValue LowerVSELECT(SDValue Op, SelectionDAG &DAG) const;
933 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
934 SDValue ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const;
935 SDValue InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const;
937 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
938 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
939 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
940 SDValue LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
941 int64_t Offset, SelectionDAG &DAG) const;
942 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
943 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
944 SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const;
945 SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
946 SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
947 SDValue LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) const;
948 SDValue LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) const;
949 SDValue lowerUINT_TO_FP_vec(SDValue Op, SelectionDAG &DAG) const;
950 SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const;
951 SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
952 SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const;
953 SDValue LowerToBT(SDValue And, ISD::CondCode CC,
954 SDLoc dl, SelectionDAG &DAG) const;
955 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
956 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
957 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
958 SDValue LowerMEMSET(SDValue Op, SelectionDAG &DAG) const;
959 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
960 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
961 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
962 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
963 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
964 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
965 SDValue LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG) const;
966 SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
967 SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
968 SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
969 SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
970 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
971 SDValue LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const;
974 LowerFormalArguments(SDValue Chain,
975 CallingConv::ID CallConv, bool isVarArg,
976 const SmallVectorImpl<ISD::InputArg> &Ins,
977 SDLoc dl, SelectionDAG &DAG,
978 SmallVectorImpl<SDValue> &InVals) const override;
979 SDValue LowerCall(CallLoweringInfo &CLI,
980 SmallVectorImpl<SDValue> &InVals) const override;
982 SDValue LowerReturn(SDValue Chain,
983 CallingConv::ID CallConv, bool isVarArg,
984 const SmallVectorImpl<ISD::OutputArg> &Outs,
985 const SmallVectorImpl<SDValue> &OutVals,
986 SDLoc dl, SelectionDAG &DAG) const override;
988 bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
990 bool mayBeEmittedAsTailCall(CallInst *CI) const override;
992 EVT getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
993 ISD::NodeType ExtendKind) const override;
995 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
997 const SmallVectorImpl<ISD::OutputArg> &Outs,
998 LLVMContext &Context) const override;
1000 const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override;
1002 bool shouldExpandAtomicLoadInIR(LoadInst *SI) const override;
1003 bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
1004 TargetLoweringBase::AtomicRMWExpansionKind
1005 shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
1008 lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const override;
1010 bool needsCmpXchgNb(const Type *MemType) const;
1012 /// Utility function to emit atomic-load-arith operations (and, or, xor,
1013 /// nand, max, min, umax, umin). It takes the corresponding instruction to
1014 /// expand, the associated machine basic block, and the associated X86
1015 /// opcodes for reg/reg.
1016 MachineBasicBlock *EmitAtomicLoadArith(MachineInstr *MI,
1017 MachineBasicBlock *MBB) const;
1019 /// Utility function to emit atomic-load-arith operations (and, or, xor,
1020 /// nand, add, sub, swap) for 64-bit operands on 32-bit target.
1021 MachineBasicBlock *EmitAtomicLoadArith6432(MachineInstr *MI,
1022 MachineBasicBlock *MBB) const;
1024 // Utility function to emit the low-level va_arg code for X86-64.
1025 MachineBasicBlock *EmitVAARG64WithCustomInserter(
1027 MachineBasicBlock *MBB) const;
1029 /// Utility function to emit the xmm reg save portion of va_start.
1030 MachineBasicBlock *EmitVAStartSaveXMMRegsWithCustomInserter(
1031 MachineInstr *BInstr,
1032 MachineBasicBlock *BB) const;
1034 MachineBasicBlock *EmitLoweredSelect(MachineInstr *I,
1035 MachineBasicBlock *BB) const;
1037 MachineBasicBlock *EmitLoweredWinAlloca(MachineInstr *MI,
1038 MachineBasicBlock *BB) const;
1040 MachineBasicBlock *EmitLoweredSegAlloca(MachineInstr *MI,
1041 MachineBasicBlock *BB) const;
1043 MachineBasicBlock *EmitLoweredTLSCall(MachineInstr *MI,
1044 MachineBasicBlock *BB) const;
1046 MachineBasicBlock *emitLoweredTLSAddr(MachineInstr *MI,
1047 MachineBasicBlock *BB) const;
1049 MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr *MI,
1050 MachineBasicBlock *MBB) const;
1052 MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr *MI,
1053 MachineBasicBlock *MBB) const;
1055 MachineBasicBlock *emitFMA3Instr(MachineInstr *MI,
1056 MachineBasicBlock *MBB) const;
1058 /// Emit nodes that will be selected as "test Op0,Op0", or something
1059 /// equivalent, for use with the given x86 condition code.
1060 SDValue EmitTest(SDValue Op0, unsigned X86CC, SDLoc dl,
1061 SelectionDAG &DAG) const;
1063 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
1064 /// equivalent, for use with the given x86 condition code.
1065 SDValue EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC, SDLoc dl,
1066 SelectionDAG &DAG) const;
1068 /// Convert a comparison if required by the subtarget.
1069 SDValue ConvertCmpIfNecessary(SDValue Cmp, SelectionDAG &DAG) const;
1071 /// Use rsqrt* to speed up sqrt calculations.
1072 SDValue getRsqrtEstimate(SDValue Operand, DAGCombinerInfo &DCI,
1073 unsigned &RefinementSteps,
1074 bool &UseOneConstNR) const override;
1076 /// Use rcp* to speed up fdiv calculations.
1077 SDValue getRecipEstimate(SDValue Operand, DAGCombinerInfo &DCI,
1078 unsigned &RefinementSteps) const override;
1080 /// Reassociate floating point divisions into multiply by reciprocal.
1081 bool combineRepeatedFPDivisors(unsigned NumUsers) const override;
1085 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
1086 const TargetLibraryInfo *libInfo);
1090 #endif // X86ISELLOWERING_H