1 //===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef X86ISELLOWERING_H
16 #define X86ISELLOWERING_H
18 #include "X86Subtarget.h"
19 #include "X86RegisterInfo.h"
20 #include "llvm/Target/TargetLowering.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
22 #include "llvm/CodeGen/CallingConvLower.h"
26 // X86 Specific DAG Nodes
28 // Start the numbering where the builtin ops leave off.
29 FIRST_NUMBER = ISD::BUILTIN_OP_END+X86::INSTRUCTION_LIST_END,
31 /// SHLD, SHRD - Double shift instructions. These correspond to
32 /// X86::SHLDxx and X86::SHRDxx instructions.
36 /// FAND - Bitwise logical AND of floating point values. This corresponds
37 /// to X86::ANDPS or X86::ANDPD.
40 /// FOR - Bitwise logical OR of floating point values. This corresponds
41 /// to X86::ORPS or X86::ORPD.
44 /// FXOR - Bitwise logical XOR of floating point values. This corresponds
45 /// to X86::XORPS or X86::XORPD.
48 /// FSRL - Bitwise logical right shift of floating point values. These
49 /// corresponds to X86::PSRLDQ.
52 /// FILD, FILD_FLAG - This instruction implements SINT_TO_FP with the
53 /// integer source in memory and FP reg result. This corresponds to the
54 /// X86::FILD*m instructions. It has three inputs (token chain, address,
55 /// and source type) and two outputs (FP value and token chain). FILD_FLAG
56 /// also produces a flag).
60 /// FP_TO_INT*_IN_MEM - This instruction implements FP_TO_SINT with the
61 /// integer destination in memory and a FP reg source. This corresponds
62 /// to the X86::FIST*m instructions and the rounding mode change stuff. It
63 /// has two inputs (token chain and address) and two outputs (int value
69 /// FLD - This instruction implements an extending load to FP stack slots.
70 /// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain
71 /// operand, ptr to load from, and a ValueType node indicating the type
75 /// FST - This instruction implements a truncating store to FP stack
76 /// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a
77 /// chain operand, value to store, address, and a ValueType to store it
81 /// FP_GET_RESULT - This corresponds to FpGETRESULT pseudo instruction
82 /// which copies from ST(0) to the destination. It takes a chain and
83 /// writes a RFP result and a chain.
86 /// FP_SET_RESULT - This corresponds to FpSETRESULT pseudo instruction
87 /// which copies the source operand to ST(0). It takes a chain+value and
88 /// returns a chain and a flag.
91 /// CALL/TAILCALL - These operations represent an abstract X86 call
92 /// instruction, which includes a bunch of information. In particular the
93 /// operands of these node are:
95 /// #0 - The incoming token chain
97 /// #2 - The number of arg bytes the caller pushes on the stack.
98 /// #3 - The number of arg bytes the callee pops off the stack.
99 /// #4 - The value to pass in AL/AX/EAX (optional)
100 /// #5 - The value to pass in DL/DX/EDX (optional)
102 /// The result values of these nodes are:
104 /// #0 - The outgoing token chain
105 /// #1 - The first register result value (optional)
106 /// #2 - The second register result value (optional)
108 /// The CALL vs TAILCALL distinction boils down to whether the callee is
109 /// known not to modify the caller's stack frame, as is standard with
114 /// RDTSC_DAG - This operation implements the lowering for
118 /// X86 compare and logical compare instructions.
121 /// X86 SetCC. Operand 1 is condition code, and operand 2 is the flag
122 /// operand produced by a CMP instruction.
125 /// X86 conditional moves. Operand 1 and operand 2 are the two values
126 /// to select from (operand 1 is a R/W operand). Operand 3 is the
127 /// condition code, and operand 4 is the flag operand produced by a CMP
128 /// or TEST instruction. It also writes a flag result.
131 /// X86 conditional branches. Operand 1 is the chain operand, operand 2
132 /// is the block to branch if condition is true, operand 3 is the
133 /// condition code, and operand 4 is the flag operand produced by a CMP
134 /// or TEST instruction.
137 /// Return with a flag operand. Operand 1 is the chain operand, operand
138 /// 2 is the number of bytes of stack to pop.
141 /// REP_STOS - Repeat fill, corresponds to X86::REP_STOSx.
144 /// REP_MOVS - Repeat move, corresponds to X86::REP_MOVSx.
147 /// GlobalBaseReg - On Darwin, this node represents the result of the popl
148 /// at function entry, used for PIC code.
151 /// Wrapper - A wrapper node for TargetConstantPool,
152 /// TargetExternalSymbol, and TargetGlobalAddress.
155 /// WrapperRIP - Special wrapper used under X86-64 PIC mode for RIP
156 /// relative displacements.
159 /// S2VEC - X86 version of SCALAR_TO_VECTOR. The destination base does not
160 /// have to match the operand type.
163 /// PEXTRW - Extract a 16-bit value from a vector and zero extend it to
164 /// i32, corresponds to X86::PEXTRW.
167 /// PINSRW - Insert the lower 16-bits of a 32-bit value to a vector,
168 /// corresponds to X86::PINSRW.
171 /// FMAX, FMIN - Floating point max and min.
175 /// FRSQRT, FRCP - Floating point reciprocal-sqrt and reciprocal
176 /// approximation. Note that these typically require refinement
177 /// in order to obtain suitable precision.
180 /// DIV, IDIV - Unsigned and signed integer division and remainder.
184 // Thread Local Storage
185 TLSADDR, THREAD_POINTER,
187 // Exception Handling helpers
192 /// Define some predicates that are used for node matching.
194 /// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand
195 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
196 bool isPSHUFDMask(SDNode *N);
198 /// isPSHUFHWMask - Return true if the specified VECTOR_SHUFFLE operand
199 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
200 bool isPSHUFHWMask(SDNode *N);
202 /// isPSHUFLWMask - Return true if the specified VECTOR_SHUFFLE operand
203 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
204 bool isPSHUFLWMask(SDNode *N);
206 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
207 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
208 bool isSHUFPMask(SDNode *N);
210 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
211 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
212 bool isMOVHLPSMask(SDNode *N);
214 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
215 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
217 bool isMOVHLPS_v_undef_Mask(SDNode *N);
219 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
220 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
221 bool isMOVLPMask(SDNode *N);
223 /// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand
224 /// specifies a shuffle of elements that is suitable for input to MOVHP{S|D}
225 /// as well as MOVLHPS.
226 bool isMOVHPMask(SDNode *N);
228 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
229 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
230 bool isUNPCKLMask(SDNode *N, bool V2IsSplat = false);
232 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
233 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
234 bool isUNPCKHMask(SDNode *N, bool V2IsSplat = false);
236 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
237 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
239 bool isUNPCKL_v_undef_Mask(SDNode *N);
241 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
242 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
244 bool isUNPCKH_v_undef_Mask(SDNode *N);
246 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
247 /// specifies a shuffle of elements that is suitable for input to MOVSS,
248 /// MOVSD, and MOVD, i.e. setting the lowest element.
249 bool isMOVLMask(SDNode *N);
251 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
252 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
253 bool isMOVSHDUPMask(SDNode *N);
255 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
256 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
257 bool isMOVSLDUPMask(SDNode *N);
259 /// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand
260 /// specifies a splat of a single element.
261 bool isSplatMask(SDNode *N);
263 /// isSplatLoMask - Return true if the specified VECTOR_SHUFFLE operand
264 /// specifies a splat of zero element.
265 bool isSplatLoMask(SDNode *N);
267 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
268 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP*
270 unsigned getShuffleSHUFImmediate(SDNode *N);
272 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
273 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFHW
275 unsigned getShufflePSHUFHWImmediate(SDNode *N);
277 /// getShufflePSHUFKWImmediate - Return the appropriate immediate to shuffle
278 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFLW
280 unsigned getShufflePSHUFLWImmediate(SDNode *N);
283 //===--------------------------------------------------------------------===//
284 // X86TargetLowering - X86 Implementation of the TargetLowering interface
285 class X86TargetLowering : public TargetLowering {
286 int VarArgsFrameIndex; // FrameIndex for start of varargs area.
287 int RegSaveFrameIndex; // X86-64 vararg func register save area.
288 unsigned VarArgsGPOffset; // X86-64 vararg func int reg offset.
289 unsigned VarArgsFPOffset; // X86-64 vararg func fp reg offset.
290 int BytesToPopOnReturn; // Number of arg bytes ret should pop.
291 int BytesCallerReserves; // Number of arg bytes caller makes.
293 explicit X86TargetLowering(TargetMachine &TM);
295 // Return the number of bytes that a function should pop when it returns (in
296 // addition to the space used by the return address).
298 unsigned getBytesToPopOnReturn() const { return BytesToPopOnReturn; }
300 // Return the number of bytes that the caller reserves for arguments passed
302 unsigned getBytesCallerReserves() const { return BytesCallerReserves; }
304 /// getStackPtrReg - Return the stack pointer register we are using: either
306 unsigned getStackPtrReg() const { return X86StackPtr; }
308 /// LowerOperation - Provide custom lowering hooks for some operations.
310 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
312 virtual SDOperand PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
314 virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI,
315 MachineBasicBlock *MBB);
317 /// getTargetNodeName - This method returns the name of a target specific
319 virtual const char *getTargetNodeName(unsigned Opcode) const;
321 /// computeMaskedBitsForTargetNode - Determine which of the bits specified
322 /// in Mask are known to be either zero or one and return them in the
323 /// KnownZero/KnownOne bitsets.
324 virtual void computeMaskedBitsForTargetNode(const SDOperand Op,
328 const SelectionDAG &DAG,
329 unsigned Depth = 0) const;
331 SDOperand getReturnAddressFrameIndex(SelectionDAG &DAG);
333 ConstraintType getConstraintType(const std::string &Constraint) const;
335 std::vector<unsigned>
336 getRegClassForInlineAsmConstraint(const std::string &Constraint,
337 MVT::ValueType VT) const;
339 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
340 /// vector. If it is invalid, don't add anything to Ops.
341 virtual void LowerAsmOperandForConstraint(SDOperand Op,
342 char ConstraintLetter,
343 std::vector<SDOperand> &Ops,
346 /// getRegForInlineAsmConstraint - Given a physical register constraint
347 /// (e.g. {edx}), return the register number and the register class for the
348 /// register. This should only be used for C_Register constraints. On
349 /// error, this returns a register number of 0.
350 std::pair<unsigned, const TargetRegisterClass*>
351 getRegForInlineAsmConstraint(const std::string &Constraint,
352 MVT::ValueType VT) const;
354 /// isLegalAddressingMode - Return true if the addressing mode represented
355 /// by AM is legal for this target, for a load/store of the specified type.
356 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty)const;
358 /// isShuffleMaskLegal - Targets can use this to indicate that they only
359 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
360 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask
361 /// values are assumed to be legal.
362 virtual bool isShuffleMaskLegal(SDOperand Mask, MVT::ValueType VT) const;
364 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is
365 /// used by Targets can use this to indicate if there is a suitable
366 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
368 virtual bool isVectorClearMaskLegal(std::vector<SDOperand> &BVOps,
370 SelectionDAG &DAG) const;
372 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
373 /// make the right decision when generating code for different targets.
374 const X86Subtarget *Subtarget;
375 const MRegisterInfo *RegInfo;
377 /// X86StackPtr - X86 physical register used as stack ptr.
378 unsigned X86StackPtr;
380 /// X86ScalarSSEf32, X86ScalarSSEf64 - Select between SSE or x87
381 /// floating point ops.
382 /// When SSE is available, use it for f32 operations.
383 /// When SSE2 is available, use it for f64 operations.
384 bool X86ScalarSSEf32;
385 bool X86ScalarSSEf64;
387 SDNode *LowerCallResult(SDOperand Chain, SDOperand InFlag, SDNode*TheCall,
388 unsigned CallingConv, SelectionDAG &DAG);
391 SDOperand LowerMemArgument(SDOperand Op, SelectionDAG &DAG,
392 const CCValAssign &VA, MachineFrameInfo *MFI,
393 SDOperand Root, unsigned i);
395 SDOperand LowerMemOpCallTo(SDOperand Op, SelectionDAG &DAG,
396 const SDOperand &StackPtr,
397 const CCValAssign &VA, SDOperand Chain,
400 // C and StdCall Calling Convention implementation.
401 SDOperand LowerCCCArguments(SDOperand Op, SelectionDAG &DAG,
402 bool isStdCall = false);
403 SDOperand LowerCCCCallTo(SDOperand Op, SelectionDAG &DAG, unsigned CC);
405 // X86-64 C Calling Convention implementation.
406 SDOperand LowerX86_64CCCArguments(SDOperand Op, SelectionDAG &DAG);
407 SDOperand LowerX86_64CCCCallTo(SDOperand Op, SelectionDAG &DAG,unsigned CC);
409 // Fast and FastCall Calling Convention implementation.
410 SDOperand LowerFastCCArguments(SDOperand Op, SelectionDAG &DAG);
411 SDOperand LowerFastCCCallTo(SDOperand Op, SelectionDAG &DAG, unsigned CC);
413 SDOperand LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG);
414 SDOperand LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG);
415 SDOperand LowerEXTRACT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG);
416 SDOperand LowerINSERT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG);
417 SDOperand LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG);
418 SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG);
419 SDOperand LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG);
420 SDOperand LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG);
421 SDOperand LowerExternalSymbol(SDOperand Op, SelectionDAG &DAG);
422 SDOperand LowerShift(SDOperand Op, SelectionDAG &DAG);
423 SDOperand LowerIntegerDivOrRem(SDOperand Op, SelectionDAG &DAG);
424 SDOperand LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG);
425 SDOperand LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG);
426 SDOperand LowerFABS(SDOperand Op, SelectionDAG &DAG);
427 SDOperand LowerFNEG(SDOperand Op, SelectionDAG &DAG);
428 SDOperand LowerFCOPYSIGN(SDOperand Op, SelectionDAG &DAG);
429 SDOperand LowerSETCC(SDOperand Op, SelectionDAG &DAG);
430 SDOperand LowerSELECT(SDOperand Op, SelectionDAG &DAG);
431 SDOperand LowerBRCOND(SDOperand Op, SelectionDAG &DAG);
432 SDOperand LowerMEMSET(SDOperand Op, SelectionDAG &DAG);
433 SDOperand LowerMEMCPYInline(SDOperand Dest, SDOperand Source,
434 SDOperand Chain, unsigned Size, unsigned Align,
436 SDOperand LowerMEMCPYCall(SDOperand ChainOp, SDOperand DestOp,
437 SDOperand SourceOp, SDOperand CountOp,
439 SDOperand LowerMEMCPY(SDOperand Op, SelectionDAG &DAG);
440 SDOperand LowerJumpTable(SDOperand Op, SelectionDAG &DAG);
441 SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG);
442 SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG);
443 SDOperand LowerDYNAMIC_STACKALLOC(SDOperand Op, SelectionDAG &DAG);
444 SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG);
445 SDOperand LowerREADCYCLCECOUNTER(SDOperand Op, SelectionDAG &DAG);
446 SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG);
447 SDOperand LowerVACOPY(SDOperand Op, SelectionDAG &DAG);
448 SDOperand LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG);
449 SDOperand LowerRETURNADDR(SDOperand Op, SelectionDAG &DAG);
450 SDOperand LowerFRAMEADDR(SDOperand Op, SelectionDAG &DAG);
451 SDOperand LowerFRAME_TO_ARGS_OFFSET(SDOperand Op, SelectionDAG &DAG);
452 SDOperand LowerEH_RETURN(SDOperand Op, SelectionDAG &DAG);
453 SDOperand LowerTRAMPOLINE(SDOperand Op, SelectionDAG &DAG);
457 #endif // X86ISELLOWERING_H