1 //===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_X86_X86ISELLOWERING_H
16 #define LLVM_LIB_TARGET_X86_X86ISELLOWERING_H
18 #include "llvm/CodeGen/CallingConvLower.h"
19 #include "llvm/CodeGen/SelectionDAG.h"
20 #include "llvm/Target/TargetLowering.h"
21 #include "llvm/Target/TargetOptions.h"
25 class X86TargetMachine;
28 // X86 Specific DAG Nodes
30 // Start the numbering where the builtin ops leave off.
31 FIRST_NUMBER = ISD::BUILTIN_OP_END,
33 /// BSF - Bit scan forward.
34 /// BSR - Bit scan reverse.
38 /// SHLD, SHRD - Double shift instructions. These correspond to
39 /// X86::SHLDxx and X86::SHRDxx instructions.
43 /// FAND - Bitwise logical AND of floating point values. This corresponds
44 /// to X86::ANDPS or X86::ANDPD.
47 /// FOR - Bitwise logical OR of floating point values. This corresponds
48 /// to X86::ORPS or X86::ORPD.
51 /// FXOR - Bitwise logical XOR of floating point values. This corresponds
52 /// to X86::XORPS or X86::XORPD.
55 /// FANDN - Bitwise logical ANDNOT of floating point values. This
56 /// corresponds to X86::ANDNPS or X86::ANDNPD.
59 /// FSRL - Bitwise logical right shift of floating point values. These
60 /// corresponds to X86::PSRLDQ.
63 /// CALL - These operations represent an abstract X86 call
64 /// instruction, which includes a bunch of information. In particular the
65 /// operands of these node are:
67 /// #0 - The incoming token chain
69 /// #2 - The number of arg bytes the caller pushes on the stack.
70 /// #3 - The number of arg bytes the callee pops off the stack.
71 /// #4 - The value to pass in AL/AX/EAX (optional)
72 /// #5 - The value to pass in DL/DX/EDX (optional)
74 /// The result values of these nodes are:
76 /// #0 - The outgoing token chain
77 /// #1 - The first register result value (optional)
78 /// #2 - The second register result value (optional)
82 /// RDTSC_DAG - This operation implements the lowering for
86 /// X86 Read Time-Stamp Counter and Processor ID.
89 /// X86 Read Performance Monitoring Counters.
92 /// X86 compare and logical compare instructions.
95 /// X86 bit-test instructions.
98 /// X86 SetCC. Operand 0 is condition code, and operand 1 is the EFLAGS
99 /// operand, usually produced by a CMP instruction.
105 // Same as SETCC except it's materialized with a sbb and the value is all
106 // one's or all zero's.
107 SETCC_CARRY, // R = carry_bit ? ~0 : 0
109 /// X86 FP SETCC, implemented with CMP{cc}SS/CMP{cc}SD.
110 /// Operands are two FP values to compare; result is a mask of
111 /// 0s or 1s. Generally DTRT for C/C++ with NaNs.
114 /// X86 MOVMSK{pd|ps}, extracts sign bits of two or four FP values,
115 /// result in an integer GPR. Needs masking for scalar result.
118 /// X86 conditional moves. Operand 0 and operand 1 are the two values
119 /// to select from. Operand 2 is the condition code, and operand 3 is the
120 /// flag operand produced by a CMP or TEST instruction. It also writes a
124 /// X86 conditional branches. Operand 0 is the chain operand, operand 1
125 /// is the block to branch if condition is true, operand 2 is the
126 /// condition code, and operand 3 is the flag operand produced by a CMP
127 /// or TEST instruction.
130 /// Return with a flag operand. Operand 0 is the chain operand, operand
131 /// 1 is the number of bytes of stack to pop.
134 /// REP_STOS - Repeat fill, corresponds to X86::REP_STOSx.
137 /// REP_MOVS - Repeat move, corresponds to X86::REP_MOVSx.
140 /// GlobalBaseReg - On Darwin, this node represents the result of the popl
141 /// at function entry, used for PIC code.
144 /// Wrapper - A wrapper node for TargetConstantPool,
145 /// TargetExternalSymbol, and TargetGlobalAddress.
148 /// WrapperRIP - Special wrapper used under X86-64 PIC mode for RIP
149 /// relative displacements.
152 /// MOVDQ2Q - Copies a 64-bit value from the low word of an XMM vector
153 /// to an MMX vector. If you think this is too close to the previous
154 /// mnemonic, so do I; blame Intel.
157 /// MMX_MOVD2W - Copies a 32-bit value from the low word of a MMX
161 /// PEXTRB - Extract an 8-bit value from a vector and zero extend it to
162 /// i32, corresponds to X86::PEXTRB.
165 /// PEXTRW - Extract a 16-bit value from a vector and zero extend it to
166 /// i32, corresponds to X86::PEXTRW.
169 /// INSERTPS - Insert any element of a 4 x float vector into any element
170 /// of a destination 4 x floatvector.
173 /// PINSRB - Insert the lower 8-bits of a 32-bit value to a vector,
174 /// corresponds to X86::PINSRB.
177 /// PINSRW - Insert the lower 16-bits of a 32-bit value to a vector,
178 /// corresponds to X86::PINSRW.
181 /// PSHUFB - Shuffle 16 8-bit values within a vector.
184 /// ANDNP - Bitwise Logical AND NOT of Packed FP values.
187 /// PSIGN - Copy integer sign.
190 /// BLENDI - Blend where the selector is an immediate.
193 /// SHRUNKBLEND - Blend where the condition has been shrunk.
194 /// This is used to emphasize that the condition mask is
195 /// no more valid for generic VSELECT optimizations.
198 /// ADDSUB - Combined add and sub on an FP vector.
201 // SUBUS - Integer sub with unsigned saturation.
204 /// HADD - Integer horizontal add.
207 /// HSUB - Integer horizontal sub.
210 /// FHADD - Floating point horizontal add.
213 /// FHSUB - Floating point horizontal sub.
216 /// UMAX, UMIN - Unsigned integer max and min.
219 /// SMAX, SMIN - Signed integer max and min.
222 /// FMAX, FMIN - Floating point max and min.
226 /// FMAXC, FMINC - Commutative FMIN and FMAX.
229 /// FRSQRT, FRCP - Floating point reciprocal-sqrt and reciprocal
230 /// approximation. Note that these typically require refinement
231 /// in order to obtain suitable precision.
234 // TLSADDR - Thread Local Storage.
237 // TLSBASEADDR - Thread Local Storage. A call to get the start address
238 // of the TLS block for the current module.
241 // TLSCALL - Thread Local Storage. When calling to an OS provided
242 // thunk at the address from an earlier relocation.
245 // EH_RETURN - Exception Handling helpers.
248 // EH_SJLJ_SETJMP - SjLj exception handling setjmp.
251 // EH_SJLJ_LONGJMP - SjLj exception handling longjmp.
254 /// TC_RETURN - Tail call return. See X86TargetLowering::LowerCall for
255 /// the list of operands.
258 // VZEXT_MOVL - Vector move to low scalar and zero higher vector elements.
261 // VZEXT - Vector integer zero-extend.
264 // VSEXT - Vector integer signed-extend.
267 // VTRUNC - Vector integer truncate.
270 // VTRUNC - Vector integer truncate with mask.
273 // VFPEXT - Vector FP extend.
276 // VFPROUND - Vector FP round.
279 // VSHL, VSRL - 128-bit vector logical left / right shift
282 // VSHL, VSRL, VSRA - Vector shift elements
285 // VSHLI, VSRLI, VSRAI - Vector shift elements by immediate
288 // CMPP - Vector packed double/float comparison.
291 // PCMP* - Vector integer comparisons.
293 // PCMP*M - Vector integer comparisons, the result is in a mask vector.
296 /// CMPM, CMPMU - Vector comparison generating mask bits for fp and
297 /// integer signed and unsigned data types.
301 // ADD, SUB, SMUL, etc. - Arithmetic operations with FLAGS results.
302 ADD, SUB, ADC, SBB, SMUL,
303 INC, DEC, OR, XOR, AND,
305 BEXTR, // BEXTR - Bit field extract
307 UMUL, // LOW, HI, FLAGS = umul LHS, RHS
309 // 8-bit SMUL/UMUL - AX, FLAGS = smul8/umul8 AL, RHS
312 // 8-bit divrem that zero-extend the high result (AH).
316 // MUL_IMM - X86 specific multiply by immediate.
319 // PTEST - Vector bitwise comparisons.
322 // TESTP - Vector packed fp sign bitwise comparisons.
325 // TESTM, TESTNM - Vector "test" in AVX-512, the result is in a mask vector.
329 // OR/AND test for masks
332 // Several flavors of instructions with vector shuffle behaviors.
337 // AVX512 inter-lane alignr
365 // Insert/Extract vector element
369 // Vector multiply packed unsigned doubleword integers
371 // Vector multiply packed signed doubleword integers
382 // Save xmm argument registers to the stack, according to %al. An operator
383 // is needed so that this can be expanded with control flow.
384 VASTART_SAVE_XMM_REGS,
386 // Windows's _chkstk call to do stack probing.
389 // For allocating variable amounts of stack space when using
390 // segmented stacks. Check if the current stacklet has enough space, and
391 // falls back to heap allocation if not.
394 // Windows's _ftol2 runtime routine to do fptoui.
403 // Store FP status word into i16 register.
406 // Store contents of %ah into %eflags.
409 // Get a random integer and indicate whether it is valid in CF.
412 // Get a NIST SP800-90B & C compliant random integer and
413 // indicate whether it is valid in CF.
419 // Test if in transactional execution.
423 RSQRT28, RCP28, EXP2,
426 LCMPXCHG_DAG = ISD::FIRST_TARGET_MEMORY_OPCODE,
430 // Load, scalar_to_vector, and zero extend.
433 // Store FP control world into i16 memory.
436 /// This instruction implements FP_TO_SINT with the
437 /// integer destination in memory and a FP reg source. This corresponds
438 /// to the X86::FIST*m instructions and the rounding mode change stuff. It
439 /// has two inputs (token chain and address) and two outputs (int value
440 /// and token chain).
445 /// This instruction implements SINT_TO_FP with the
446 /// integer source in memory and FP reg result. This corresponds to the
447 /// X86::FILD*m instructions. It has three inputs (token chain, address,
448 /// and source type) and two outputs (FP value and token chain). FILD_FLAG
449 /// also produces a flag).
453 /// This instruction implements an extending load to FP stack slots.
454 /// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain
455 /// operand, ptr to load from, and a ValueType node indicating the type
459 /// This instruction implements a truncating store to FP stack
460 /// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a
461 /// chain operand, value to store, address, and a ValueType to store it
465 /// This instruction grabs the address of the next argument
466 /// from a va_list. (reads and modifies the va_list in memory)
469 // WARNING: Do not add anything in the end unless you want the node to
470 // have memop! In fact, starting from ATOMADD64_DAG all opcodes will be
471 // thought as target memory ops!
475 /// Define some predicates that are used for node matching.
477 /// Return true if the specified
478 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
479 /// suitable for input to VEXTRACTF128, VEXTRACTI128 instructions.
480 bool isVEXTRACT128Index(SDNode *N);
482 /// Return true if the specified
483 /// INSERT_SUBVECTOR operand specifies a subvector insert that is
484 /// suitable for input to VINSERTF128, VINSERTI128 instructions.
485 bool isVINSERT128Index(SDNode *N);
487 /// Return true if the specified
488 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
489 /// suitable for input to VEXTRACTF64X4, VEXTRACTI64X4 instructions.
490 bool isVEXTRACT256Index(SDNode *N);
492 /// Return true if the specified
493 /// INSERT_SUBVECTOR operand specifies a subvector insert that is
494 /// suitable for input to VINSERTF64X4, VINSERTI64X4 instructions.
495 bool isVINSERT256Index(SDNode *N);
497 /// Return the appropriate
498 /// immediate to extract the specified EXTRACT_SUBVECTOR index
499 /// with VEXTRACTF128, VEXTRACTI128 instructions.
500 unsigned getExtractVEXTRACT128Immediate(SDNode *N);
502 /// Return the appropriate
503 /// immediate to insert at the specified INSERT_SUBVECTOR index
504 /// with VINSERTF128, VINSERT128 instructions.
505 unsigned getInsertVINSERT128Immediate(SDNode *N);
507 /// Return the appropriate
508 /// immediate to extract the specified EXTRACT_SUBVECTOR index
509 /// with VEXTRACTF64X4, VEXTRACTI64x4 instructions.
510 unsigned getExtractVEXTRACT256Immediate(SDNode *N);
512 /// Return the appropriate
513 /// immediate to insert at the specified INSERT_SUBVECTOR index
514 /// with VINSERTF64x4, VINSERTI64x4 instructions.
515 unsigned getInsertVINSERT256Immediate(SDNode *N);
517 /// Returns true if Elt is a constant zero or floating point constant +0.0.
518 bool isZeroNode(SDValue Elt);
520 /// Returns true of the given offset can be
521 /// fit into displacement field of the instruction.
522 bool isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
523 bool hasSymbolicDisplacement = true);
526 /// Determines whether the callee is required to pop its
527 /// own arguments. Callee pop is necessary to support tail calls.
528 bool isCalleePop(CallingConv::ID CallingConv,
529 bool is64Bit, bool IsVarArg, bool TailCallOpt);
531 /// AVX512 static rounding constants. These need to match the values in
533 enum STATIC_ROUNDING {
542 //===--------------------------------------------------------------------===//
543 // X86 Implementation of the TargetLowering interface
544 class X86TargetLowering final : public TargetLowering {
546 explicit X86TargetLowering(const X86TargetMachine &TM);
548 unsigned getJumpTableEncoding() const override;
550 MVT getScalarShiftAmountTy(EVT LHSTy) const override { return MVT::i8; }
553 LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
554 const MachineBasicBlock *MBB, unsigned uid,
555 MCContext &Ctx) const override;
557 /// Returns relocation base for the given PIC jumptable.
558 SDValue getPICJumpTableRelocBase(SDValue Table,
559 SelectionDAG &DAG) const override;
561 getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
562 unsigned JTI, MCContext &Ctx) const override;
564 /// Return the desired alignment for ByVal aggregate
565 /// function arguments in the caller parameter area. For X86, aggregates
566 /// that contains are placed at 16-byte boundaries while the rest are at
567 /// 4-byte boundaries.
568 unsigned getByValTypeAlignment(Type *Ty) const override;
570 /// Returns the target specific optimal type for load
571 /// and store operations as a result of memset, memcpy, and memmove
572 /// lowering. If DstAlign is zero that means it's safe to destination
573 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
574 /// means there isn't a need to check it against alignment requirement,
575 /// probably because the source does not need to be loaded. If 'IsMemset' is
576 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
577 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
578 /// source is constant so it does not need to be loaded.
579 /// It returns EVT::Other if the type should be determined using generic
580 /// target-independent logic.
581 EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
582 bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc,
583 MachineFunction &MF) const override;
585 /// Returns true if it's safe to use load / store of the
586 /// specified type to expand memcpy / memset inline. This is mostly true
587 /// for all types except for some special cases. For example, on X86
588 /// targets without SSE2 f64 load / store are done with fldl / fstpl which
589 /// also does type conversion. Note the specified type doesn't have to be
590 /// legal as the hook is used before type legalization.
591 bool isSafeMemOpType(MVT VT) const override;
593 /// Returns true if the target allows
594 /// unaligned memory accesses. of the specified type. Returns whether it
595 /// is "fast" by reference in the second argument.
596 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, unsigned Align,
597 bool *Fast) const override;
599 /// Provide custom lowering hooks for some operations.
601 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
603 /// Replace the results of node with an illegal result
604 /// type with new values built out of custom code.
606 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
607 SelectionDAG &DAG) const override;
610 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
612 /// Return true if the target has native support for
613 /// the specified value type and it is 'desirable' to use the type for the
614 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
615 /// instruction encodings are longer and some i16 instructions are slow.
616 bool isTypeDesirableForOp(unsigned Opc, EVT VT) const override;
618 /// Return true if the target has native support for the
619 /// specified value type and it is 'desirable' to use the type. e.g. On x86
620 /// i16 is legal, but undesirable since i16 instruction encodings are longer
621 /// and some i16 instructions are slow.
622 bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const override;
625 EmitInstrWithCustomInserter(MachineInstr *MI,
626 MachineBasicBlock *MBB) const override;
629 /// This method returns the name of a target specific DAG node.
630 const char *getTargetNodeName(unsigned Opcode) const override;
632 /// Return the value type to use for ISD::SETCC.
633 EVT getSetCCResultType(LLVMContext &Context, EVT VT) const override;
635 /// Determine which of the bits specified in Mask are known to be either
636 /// zero or one and return them in the KnownZero/KnownOne bitsets.
637 void computeKnownBitsForTargetNode(const SDValue Op,
640 const SelectionDAG &DAG,
641 unsigned Depth = 0) const override;
643 /// Determine the number of bits in the operation that are sign bits.
644 unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
645 const SelectionDAG &DAG,
646 unsigned Depth) const override;
648 bool isGAPlusOffset(SDNode *N, const GlobalValue* &GA,
649 int64_t &Offset) const override;
651 SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
653 bool ExpandInlineAsm(CallInst *CI) const override;
656 getConstraintType(const std::string &Constraint) const override;
658 /// Examine constraint string and operand type and determine a weight value.
659 /// The operand object must already have been set up with the operand type.
661 getSingleConstraintMatchWeight(AsmOperandInfo &info,
662 const char *constraint) const override;
664 const char *LowerXConstraint(EVT ConstraintVT) const override;
666 /// Lower the specified operand into the Ops vector. If it is invalid, don't
667 /// add anything to Ops. If hasMemory is true it means one of the asm
668 /// constraint of the inline asm instruction being processed is 'm'.
669 void LowerAsmOperandForConstraint(SDValue Op,
670 std::string &Constraint,
671 std::vector<SDValue> &Ops,
672 SelectionDAG &DAG) const override;
674 /// Given a physical register constraint
675 /// (e.g. {edx}), return the register number and the register class for the
676 /// register. This should only be used for C_Register constraints. On
677 /// error, this returns a register number of 0.
678 std::pair<unsigned, const TargetRegisterClass*>
679 getRegForInlineAsmConstraint(const std::string &Constraint,
680 MVT VT) const override;
682 /// Return true if the addressing mode represented
683 /// by AM is legal for this target, for a load/store of the specified type.
684 bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const override;
686 /// Return true if the specified immediate is legal
687 /// icmp immediate, that is the target has icmp instructions which can
688 /// compare a register against the immediate without having to materialize
689 /// the immediate into a register.
690 bool isLegalICmpImmediate(int64_t Imm) const override;
692 /// Return true if the specified immediate is legal
693 /// add immediate, that is the target has add instructions which can
694 /// add a register and the immediate without having to materialize
695 /// the immediate into a register.
696 bool isLegalAddImmediate(int64_t Imm) const override;
698 /// \brief Return the cost of the scaling factor used in the addressing
699 /// mode represented by AM for this target, for a load/store
700 /// of the specified type.
701 /// If the AM is supported, the return value must be >= 0.
702 /// If the AM is not supported, it returns a negative value.
703 int getScalingFactorCost(const AddrMode &AM, Type *Ty) const override;
705 bool isVectorShiftByScalarCheap(Type *Ty) const override;
707 /// Return true if it's free to truncate a value of
708 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
709 /// register EAX to i16 by referencing its sub-register AX.
710 bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
711 bool isTruncateFree(EVT VT1, EVT VT2) const override;
713 bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override;
715 /// Return true if any actual instruction that defines a
716 /// value of type Ty1 implicit zero-extends the value to Ty2 in the result
717 /// register. This does not necessarily include registers defined in
718 /// unknown ways, such as incoming arguments, or copies from unknown
719 /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this
720 /// does not necessarily apply to truncate instructions. e.g. on x86-64,
721 /// all instructions that define 32-bit values implicit zero-extend the
722 /// result out to 64 bits.
723 bool isZExtFree(Type *Ty1, Type *Ty2) const override;
724 bool isZExtFree(EVT VT1, EVT VT2) const override;
725 bool isZExtFree(SDValue Val, EVT VT2) const override;
727 /// Return true if an FMA operation is faster than a pair of fmul and fadd
728 /// instructions. fmuladd intrinsics will be expanded to FMAs when this
729 /// method returns true, otherwise fmuladd is expanded to fmul + fadd.
730 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
732 /// Return true if it's profitable to narrow
733 /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow
734 /// from i32 to i8 but not from i32 to i16.
735 bool isNarrowingProfitable(EVT VT1, EVT VT2) const override;
737 /// Returns true if the target can instruction select the
738 /// specified FP immediate natively. If false, the legalizer will
739 /// materialize the FP immediate as a load from a constant pool.
740 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
742 /// Targets can use this to indicate that they only support *some*
743 /// VECTOR_SHUFFLE operations, those with specific masks. By default, if a
744 /// target supports the VECTOR_SHUFFLE node, all mask values are assumed to
746 bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask,
747 EVT VT) const override;
749 /// Similar to isShuffleMaskLegal. This is used by Targets can use this to
750 /// indicate if there is a suitable VECTOR_SHUFFLE that can be used to
751 /// replace a VAND with a constant pool entry.
752 bool isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
753 EVT VT) const override;
755 /// If true, then instruction selection should
756 /// seek to shrink the FP constant of the specified type to a smaller type
757 /// in order to save space and / or reduce runtime.
758 bool ShouldShrinkFPConstant(EVT VT) const override {
759 // Don't shrink FP constpool if SSE2 is available since cvtss2sd is more
760 // expensive than a straight movsd. On the other hand, it's important to
761 // shrink long double fp constant since fldt is very slow.
762 return !X86ScalarSSEf64 || VT == MVT::f80;
765 const X86Subtarget* getSubtarget() const {
769 /// Return true if the specified scalar FP type is computed in an SSE
770 /// register, not on the X87 floating point stack.
771 bool isScalarFPTypeInSSEReg(EVT VT) const {
772 return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2
773 (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1
776 /// Return true if the target uses the MSVC _ftol2 routine for fptoui.
777 bool isTargetFTOL() const;
779 /// Return true if the MSVC _ftol2 routine should be used for fptoui to the
781 bool isIntegerTypeFTOL(EVT VT) const {
782 return isTargetFTOL() && VT == MVT::i64;
785 /// \brief Returns true if it is beneficial to convert a load of a constant
786 /// to just the constant itself.
787 bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
788 Type *Ty) const override;
790 /// Intel processors have a unified instruction and data cache
791 const char * getClearCacheBuiltinName() const override {
792 return nullptr; // nothing to do, move along.
795 unsigned getRegisterByName(const char* RegName, EVT VT) const override;
797 /// This method returns a target specific FastISel object,
798 /// or null if the target does not support "fast" ISel.
799 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
800 const TargetLibraryInfo *libInfo) const override;
802 /// Return true if the target stores stack protector cookies at a fixed
803 /// offset in some non-standard address space, and populates the address
804 /// space and offset as appropriate.
805 bool getStackCookieLocation(unsigned &AddressSpace,
806 unsigned &Offset) const override;
808 SDValue BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, SDValue StackSlot,
809 SelectionDAG &DAG) const;
811 bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override;
813 /// \brief Reset the operation actions based on target options.
814 void resetOperationActions() override;
816 bool useLoadStackGuardNode() const override;
817 /// \brief Customize the preferred legalization strategy for certain types.
818 LegalizeTypeAction getPreferredVectorAction(EVT VT) const override;
821 std::pair<const TargetRegisterClass*, uint8_t>
822 findRepresentativeClass(MVT VT) const override;
825 /// Keep a pointer to the X86Subtarget around so that we can
826 /// make the right decision when generating code for different targets.
827 const X86Subtarget *Subtarget;
828 const DataLayout *TD;
830 /// Used to store the TargetOptions so that we don't waste time resetting
831 /// the operation actions unless we have to.
834 /// Select between SSE or x87 floating point ops.
835 /// When SSE is available, use it for f32 operations.
836 /// When SSE2 is available, use it for f64 operations.
837 bool X86ScalarSSEf32;
838 bool X86ScalarSSEf64;
840 /// A list of legal FP immediates.
841 std::vector<APFloat> LegalFPImmediates;
843 /// Indicate that this x86 target can instruction
844 /// select the specified FP immediate natively.
845 void addLegalFPImmediate(const APFloat& Imm) {
846 LegalFPImmediates.push_back(Imm);
849 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
850 CallingConv::ID CallConv, bool isVarArg,
851 const SmallVectorImpl<ISD::InputArg> &Ins,
852 SDLoc dl, SelectionDAG &DAG,
853 SmallVectorImpl<SDValue> &InVals) const;
854 SDValue LowerMemArgument(SDValue Chain,
855 CallingConv::ID CallConv,
856 const SmallVectorImpl<ISD::InputArg> &ArgInfo,
857 SDLoc dl, SelectionDAG &DAG,
858 const CCValAssign &VA, MachineFrameInfo *MFI,
860 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
861 SDLoc dl, SelectionDAG &DAG,
862 const CCValAssign &VA,
863 ISD::ArgFlagsTy Flags) const;
865 // Call lowering helpers.
867 /// Check whether the call is eligible for tail call optimization. Targets
868 /// that want to do tail call optimization should implement this function.
869 bool IsEligibleForTailCallOptimization(SDValue Callee,
870 CallingConv::ID CalleeCC,
872 bool isCalleeStructRet,
873 bool isCallerStructRet,
875 const SmallVectorImpl<ISD::OutputArg> &Outs,
876 const SmallVectorImpl<SDValue> &OutVals,
877 const SmallVectorImpl<ISD::InputArg> &Ins,
878 SelectionDAG& DAG) const;
879 bool IsCalleePop(bool isVarArg, CallingConv::ID CallConv) const;
880 SDValue EmitTailCallLoadRetAddr(SelectionDAG &DAG, SDValue &OutRetAddr,
881 SDValue Chain, bool IsTailCall, bool Is64Bit,
882 int FPDiff, SDLoc dl) const;
884 unsigned GetAlignedArgumentStackSize(unsigned StackSize,
885 SelectionDAG &DAG) const;
887 std::pair<SDValue,SDValue> FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
889 bool isReplace) const;
891 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
892 SDValue LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const;
893 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
894 SDValue LowerVSELECT(SDValue Op, SelectionDAG &DAG) const;
895 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
896 SDValue ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const;
897 SDValue InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const;
899 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
900 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
901 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
902 SDValue LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
903 int64_t Offset, SelectionDAG &DAG) const;
904 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
905 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
906 SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const;
907 SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
908 SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
909 SDValue LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) const;
910 SDValue LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) const;
911 SDValue lowerUINT_TO_FP_vec(SDValue Op, SelectionDAG &DAG) const;
912 SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const;
913 SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
914 SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const;
915 SDValue LowerToBT(SDValue And, ISD::CondCode CC,
916 SDLoc dl, SelectionDAG &DAG) const;
917 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
918 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
919 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
920 SDValue LowerMEMSET(SDValue Op, SelectionDAG &DAG) const;
921 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
922 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
923 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
924 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
925 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
926 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
927 SDValue LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG) const;
928 SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
929 SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
930 SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
931 SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
932 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
933 SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
934 SDValue LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const;
937 LowerFormalArguments(SDValue Chain,
938 CallingConv::ID CallConv, bool isVarArg,
939 const SmallVectorImpl<ISD::InputArg> &Ins,
940 SDLoc dl, SelectionDAG &DAG,
941 SmallVectorImpl<SDValue> &InVals) const override;
942 SDValue LowerCall(CallLoweringInfo &CLI,
943 SmallVectorImpl<SDValue> &InVals) const override;
945 SDValue LowerReturn(SDValue Chain,
946 CallingConv::ID CallConv, bool isVarArg,
947 const SmallVectorImpl<ISD::OutputArg> &Outs,
948 const SmallVectorImpl<SDValue> &OutVals,
949 SDLoc dl, SelectionDAG &DAG) const override;
951 bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
953 bool mayBeEmittedAsTailCall(CallInst *CI) const override;
955 EVT getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
956 ISD::NodeType ExtendKind) const override;
958 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
960 const SmallVectorImpl<ISD::OutputArg> &Outs,
961 LLVMContext &Context) const override;
963 const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override;
965 bool shouldExpandAtomicLoadInIR(LoadInst *SI) const override;
966 bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
967 bool shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
970 lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const override;
972 bool needsCmpXchgNb(const Type *MemType) const;
974 /// Utility function to emit atomic-load-arith operations (and, or, xor,
975 /// nand, max, min, umax, umin). It takes the corresponding instruction to
976 /// expand, the associated machine basic block, and the associated X86
977 /// opcodes for reg/reg.
978 MachineBasicBlock *EmitAtomicLoadArith(MachineInstr *MI,
979 MachineBasicBlock *MBB) const;
981 /// Utility function to emit atomic-load-arith operations (and, or, xor,
982 /// nand, add, sub, swap) for 64-bit operands on 32-bit target.
983 MachineBasicBlock *EmitAtomicLoadArith6432(MachineInstr *MI,
984 MachineBasicBlock *MBB) const;
986 // Utility function to emit the low-level va_arg code for X86-64.
987 MachineBasicBlock *EmitVAARG64WithCustomInserter(
989 MachineBasicBlock *MBB) const;
991 /// Utility function to emit the xmm reg save portion of va_start.
992 MachineBasicBlock *EmitVAStartSaveXMMRegsWithCustomInserter(
993 MachineInstr *BInstr,
994 MachineBasicBlock *BB) const;
996 MachineBasicBlock *EmitLoweredSelect(MachineInstr *I,
997 MachineBasicBlock *BB) const;
999 MachineBasicBlock *EmitLoweredWinAlloca(MachineInstr *MI,
1000 MachineBasicBlock *BB) const;
1002 MachineBasicBlock *EmitLoweredSegAlloca(MachineInstr *MI,
1003 MachineBasicBlock *BB) const;
1005 MachineBasicBlock *EmitLoweredTLSCall(MachineInstr *MI,
1006 MachineBasicBlock *BB) const;
1008 MachineBasicBlock *emitLoweredTLSAddr(MachineInstr *MI,
1009 MachineBasicBlock *BB) const;
1011 MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr *MI,
1012 MachineBasicBlock *MBB) const;
1014 MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr *MI,
1015 MachineBasicBlock *MBB) const;
1017 MachineBasicBlock *emitFMA3Instr(MachineInstr *MI,
1018 MachineBasicBlock *MBB) const;
1020 /// Emit nodes that will be selected as "test Op0,Op0", or something
1021 /// equivalent, for use with the given x86 condition code.
1022 SDValue EmitTest(SDValue Op0, unsigned X86CC, SDLoc dl,
1023 SelectionDAG &DAG) const;
1025 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
1026 /// equivalent, for use with the given x86 condition code.
1027 SDValue EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC, SDLoc dl,
1028 SelectionDAG &DAG) const;
1030 /// Convert a comparison if required by the subtarget.
1031 SDValue ConvertCmpIfNecessary(SDValue Cmp, SelectionDAG &DAG) const;
1033 /// Use rsqrt* to speed up sqrt calculations.
1034 SDValue getRsqrtEstimate(SDValue Operand, DAGCombinerInfo &DCI,
1035 unsigned &RefinementSteps,
1036 bool &UseOneConstNR) const override;
1038 /// Use rcp* to speed up fdiv calculations.
1039 SDValue getRecipEstimate(SDValue Operand, DAGCombinerInfo &DCI,
1040 unsigned &RefinementSteps) const override;
1044 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
1045 const TargetLibraryInfo *libInfo);
1049 #endif // X86ISELLOWERING_H