1 //===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef X86ISELLOWERING_H
16 #define X86ISELLOWERING_H
18 #include "X86Subtarget.h"
19 #include "X86RegisterInfo.h"
20 #include "X86MachineFunctionInfo.h"
21 #include "llvm/Target/TargetLowering.h"
22 #include "llvm/Target/TargetOptions.h"
23 #include "llvm/CodeGen/FastISel.h"
24 #include "llvm/CodeGen/SelectionDAG.h"
25 #include "llvm/CodeGen/CallingConvLower.h"
29 // X86 Specific DAG Nodes
31 // Start the numbering where the builtin ops leave off.
32 FIRST_NUMBER = ISD::BUILTIN_OP_END,
34 /// BSF - Bit scan forward.
35 /// BSR - Bit scan reverse.
39 /// SHLD, SHRD - Double shift instructions. These correspond to
40 /// X86::SHLDxx and X86::SHRDxx instructions.
44 /// FAND - Bitwise logical AND of floating point values. This corresponds
45 /// to X86::ANDPS or X86::ANDPD.
48 /// FOR - Bitwise logical OR of floating point values. This corresponds
49 /// to X86::ORPS or X86::ORPD.
52 /// FXOR - Bitwise logical XOR of floating point values. This corresponds
53 /// to X86::XORPS or X86::XORPD.
56 /// FSRL - Bitwise logical right shift of floating point values. These
57 /// corresponds to X86::PSRLDQ.
60 /// CALL - These operations represent an abstract X86 call
61 /// instruction, which includes a bunch of information. In particular the
62 /// operands of these node are:
64 /// #0 - The incoming token chain
66 /// #2 - The number of arg bytes the caller pushes on the stack.
67 /// #3 - The number of arg bytes the callee pops off the stack.
68 /// #4 - The value to pass in AL/AX/EAX (optional)
69 /// #5 - The value to pass in DL/DX/EDX (optional)
71 /// The result values of these nodes are:
73 /// #0 - The outgoing token chain
74 /// #1 - The first register result value (optional)
75 /// #2 - The second register result value (optional)
79 /// RDTSC_DAG - This operation implements the lowering for
83 /// X86 compare and logical compare instructions.
86 /// X86 bit-test instructions.
89 /// X86 SetCC. Operand 0 is condition code, and operand 1 is the flag
90 /// operand produced by a CMP instruction.
93 // Same as SETCC except it's materialized with a sbb and the value is all
94 // one's or all zero's.
97 /// X86 conditional moves. Operand 0 and operand 1 are the two values
98 /// to select from. Operand 2 is the condition code, and operand 3 is the
99 /// flag operand produced by a CMP or TEST instruction. It also writes a
103 /// X86 conditional branches. Operand 0 is the chain operand, operand 1
104 /// is the block to branch if condition is true, operand 2 is the
105 /// condition code, and operand 3 is the flag operand produced by a CMP
106 /// or TEST instruction.
109 /// Return with a flag operand. Operand 0 is the chain operand, operand
110 /// 1 is the number of bytes of stack to pop.
113 /// REP_STOS - Repeat fill, corresponds to X86::REP_STOSx.
116 /// REP_MOVS - Repeat move, corresponds to X86::REP_MOVSx.
119 /// GlobalBaseReg - On Darwin, this node represents the result of the popl
120 /// at function entry, used for PIC code.
123 /// Wrapper - A wrapper node for TargetConstantPool,
124 /// TargetExternalSymbol, and TargetGlobalAddress.
127 /// WrapperRIP - Special wrapper used under X86-64 PIC mode for RIP
128 /// relative displacements.
131 /// MOVQ2DQ - Copies a 64-bit value from an MMX vector to the low word
132 /// of an XMM vector, with the high word zero filled.
135 /// MOVDQ2Q - Copies a 64-bit value from the low word of an XMM vector
136 /// to an MMX vector. If you think this is too close to the previous
137 /// mnemonic, so do I; blame Intel.
140 /// PEXTRB - Extract an 8-bit value from a vector and zero extend it to
141 /// i32, corresponds to X86::PEXTRB.
144 /// PEXTRW - Extract a 16-bit value from a vector and zero extend it to
145 /// i32, corresponds to X86::PEXTRW.
148 /// INSERTPS - Insert any element of a 4 x float vector into any element
149 /// of a destination 4 x floatvector.
152 /// PINSRB - Insert the lower 8-bits of a 32-bit value to a vector,
153 /// corresponds to X86::PINSRB.
156 /// PINSRW - Insert the lower 16-bits of a 32-bit value to a vector,
157 /// corresponds to X86::PINSRW.
160 /// PSHUFB - Shuffle 16 8-bit values within a vector.
163 /// PANDN - and with not'd value.
166 /// PSIGNB/W/D - Copy integer sign.
167 PSIGNB, PSIGNW, PSIGND,
169 /// FMAX, FMIN - Floating point max and min.
173 /// FRSQRT, FRCP - Floating point reciprocal-sqrt and reciprocal
174 /// approximation. Note that these typically require refinement
175 /// in order to obtain suitable precision.
178 // TLSADDR - Thread Local Storage.
181 // TLSCALL - Thread Local Storage. When calling to an OS provided
182 // thunk at the address from an earlier relocation.
185 // EH_RETURN - Exception Handling helpers.
188 /// TC_RETURN - Tail call return.
190 /// operand #1 callee (register or absolute)
191 /// operand #2 stack adjustment
192 /// operand #3 optional in flag
195 // VZEXT_MOVL - Vector move low and zero extend.
198 // VSHL, VSRL - Vector logical left / right shift.
201 // CMPPD, CMPPS - Vector double/float comparison.
202 // CMPPD, CMPPS - Vector double/float comparison.
205 // PCMP* - Vector integer comparisons.
206 PCMPEQB, PCMPEQW, PCMPEQD, PCMPEQQ,
207 PCMPGTB, PCMPGTW, PCMPGTD, PCMPGTQ,
209 // ADD, SUB, SMUL, etc. - Arithmetic operations with FLAGS results.
211 INC, DEC, OR, XOR, AND,
213 UMUL, // LOW, HI, FLAGS = umul LHS, RHS
215 // MUL_IMM - X86 specific multiply by immediate.
218 // PTEST - Vector bitwise comparisons
221 // TESTP - Vector packed fp sign bitwise comparisons
224 // Several flavors of instructions with vector shuffle behaviors.
259 // VASTART_SAVE_XMM_REGS - Save xmm argument registers to the stack,
260 // according to %al. An operator is needed so that this can be expanded
261 // with control flow.
262 VASTART_SAVE_XMM_REGS,
264 // WIN_ALLOCA - Windows's _chkstk call to do stack probing.
273 // ATOMADD64_DAG, ATOMSUB64_DAG, ATOMOR64_DAG, ATOMAND64_DAG,
274 // ATOMXOR64_DAG, ATOMNAND64_DAG, ATOMSWAP64_DAG -
275 // Atomic 64-bit binary operations.
276 ATOMADD64_DAG = ISD::FIRST_TARGET_MEMORY_OPCODE,
284 // LCMPXCHG_DAG, LCMPXCHG8_DAG - Compare and swap.
288 // VZEXT_LOAD - Load, scalar_to_vector, and zero extend.
291 // FNSTCW16m - Store FP control world into i16 memory.
294 /// FP_TO_INT*_IN_MEM - This instruction implements FP_TO_SINT with the
295 /// integer destination in memory and a FP reg source. This corresponds
296 /// to the X86::FIST*m instructions and the rounding mode change stuff. It
297 /// has two inputs (token chain and address) and two outputs (int value
298 /// and token chain).
303 /// FILD, FILD_FLAG - This instruction implements SINT_TO_FP with the
304 /// integer source in memory and FP reg result. This corresponds to the
305 /// X86::FILD*m instructions. It has three inputs (token chain, address,
306 /// and source type) and two outputs (FP value and token chain). FILD_FLAG
307 /// also produces a flag).
311 /// FLD - This instruction implements an extending load to FP stack slots.
312 /// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain
313 /// operand, ptr to load from, and a ValueType node indicating the type
317 /// FST - This instruction implements a truncating store to FP stack
318 /// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a
319 /// chain operand, value to store, address, and a ValueType to store it
323 /// VAARG_64 - This instruction grabs the address of the next argument
324 /// from a va_list. (reads and modifies the va_list in memory)
327 // WARNING: Do not add anything in the end unless you want the node to
328 // have memop! In fact, starting from ATOMADD64_DAG all opcodes will be
329 // thought as target memory ops!
333 /// Define some predicates that are used for node matching.
335 /// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand
336 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
337 bool isPSHUFDMask(ShuffleVectorSDNode *N);
339 /// isPSHUFHWMask - Return true if the specified VECTOR_SHUFFLE operand
340 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
341 bool isPSHUFHWMask(ShuffleVectorSDNode *N);
343 /// isPSHUFLWMask - Return true if the specified VECTOR_SHUFFLE operand
344 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
345 bool isPSHUFLWMask(ShuffleVectorSDNode *N);
347 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
348 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
349 bool isSHUFPMask(ShuffleVectorSDNode *N);
351 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
352 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
353 bool isMOVHLPSMask(ShuffleVectorSDNode *N);
355 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
356 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
358 bool isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N);
360 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
361 /// specifies a shuffle of elements that is suitable for MOVLP{S|D}.
362 bool isMOVLPMask(ShuffleVectorSDNode *N);
364 /// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand
365 /// specifies a shuffle of elements that is suitable for MOVHP{S|D}.
366 /// as well as MOVLHPS.
367 bool isMOVLHPSMask(ShuffleVectorSDNode *N);
369 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
370 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
371 bool isUNPCKLMask(ShuffleVectorSDNode *N, bool V2IsSplat = false);
373 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
374 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
375 bool isUNPCKHMask(ShuffleVectorSDNode *N, bool V2IsSplat = false);
377 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
378 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
380 bool isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N);
382 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
383 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
385 bool isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N);
387 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
388 /// specifies a shuffle of elements that is suitable for input to MOVSS,
389 /// MOVSD, and MOVD, i.e. setting the lowest element.
390 bool isMOVLMask(ShuffleVectorSDNode *N);
392 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
393 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
394 bool isMOVSHDUPMask(ShuffleVectorSDNode *N);
396 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
397 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
398 bool isMOVSLDUPMask(ShuffleVectorSDNode *N);
400 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
401 /// specifies a shuffle of elements that is suitable for input to MOVDDUP.
402 bool isMOVDDUPMask(ShuffleVectorSDNode *N);
404 /// isPALIGNRMask - Return true if the specified VECTOR_SHUFFLE operand
405 /// specifies a shuffle of elements that is suitable for input to PALIGNR.
406 bool isPALIGNRMask(ShuffleVectorSDNode *N);
408 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
409 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP*
411 unsigned getShuffleSHUFImmediate(SDNode *N);
413 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
414 /// the specified VECTOR_SHUFFLE mask with PSHUFHW instruction.
415 unsigned getShufflePSHUFHWImmediate(SDNode *N);
417 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
418 /// the specified VECTOR_SHUFFLE mask with PSHUFLW instruction.
419 unsigned getShufflePSHUFLWImmediate(SDNode *N);
421 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
422 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
423 unsigned getShufflePALIGNRImmediate(SDNode *N);
425 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
427 bool isZeroNode(SDValue Elt);
429 /// isOffsetSuitableForCodeModel - Returns true of the given offset can be
430 /// fit into displacement field of the instruction.
431 bool isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
432 bool hasSymbolicDisplacement = true);
435 //===--------------------------------------------------------------------===//
436 // X86TargetLowering - X86 Implementation of the TargetLowering interface
437 class X86TargetLowering : public TargetLowering {
439 explicit X86TargetLowering(X86TargetMachine &TM);
441 virtual unsigned getJumpTableEncoding() const;
443 virtual const MCExpr *
444 LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
445 const MachineBasicBlock *MBB, unsigned uid,
446 MCContext &Ctx) const;
448 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
450 virtual SDValue getPICJumpTableRelocBase(SDValue Table,
451 SelectionDAG &DAG) const;
452 virtual const MCExpr *
453 getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
454 unsigned JTI, MCContext &Ctx) const;
456 /// getStackPtrReg - Return the stack pointer register we are using: either
458 unsigned getStackPtrReg() const { return X86StackPtr; }
460 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
461 /// function arguments in the caller parameter area. For X86, aggregates
462 /// that contains are placed at 16-byte boundaries while the rest are at
463 /// 4-byte boundaries.
464 virtual unsigned getByValTypeAlignment(const Type *Ty) const;
466 /// getOptimalMemOpType - Returns the target specific optimal type for load
467 /// and store operations as a result of memset, memcpy, and memmove
468 /// lowering. If DstAlign is zero that means it's safe to destination
469 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
470 /// means there isn't a need to check it against alignment requirement,
471 /// probably because the source does not need to be loaded. If
472 /// 'NonScalarIntSafe' is true, that means it's safe to return a
473 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
474 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
475 /// constant so it does not need to be loaded.
476 /// It returns EVT::Other if the type should be determined using generic
477 /// target-independent logic.
479 getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
480 bool NonScalarIntSafe, bool MemcpyStrSrc,
481 MachineFunction &MF) const;
483 /// allowsUnalignedMemoryAccesses - Returns true if the target allows
484 /// unaligned memory accesses. of the specified type.
485 virtual bool allowsUnalignedMemoryAccesses(EVT VT) const {
489 /// LowerOperation - Provide custom lowering hooks for some operations.
491 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
493 /// ReplaceNodeResults - Replace the results of node with an illegal result
494 /// type with new values built out of custom code.
496 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
497 SelectionDAG &DAG) const;
500 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
502 /// isTypeDesirableForOp - Return true if the target has native support for
503 /// the specified value type and it is 'desirable' to use the type for the
504 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
505 /// instruction encodings are longer and some i16 instructions are slow.
506 virtual bool isTypeDesirableForOp(unsigned Opc, EVT VT) const;
508 /// isTypeDesirable - Return true if the target has native support for the
509 /// specified value type and it is 'desirable' to use the type. e.g. On x86
510 /// i16 is legal, but undesirable since i16 instruction encodings are longer
511 /// and some i16 instructions are slow.
512 virtual bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const;
514 virtual MachineBasicBlock *
515 EmitInstrWithCustomInserter(MachineInstr *MI,
516 MachineBasicBlock *MBB) const;
519 /// getTargetNodeName - This method returns the name of a target specific
521 virtual const char *getTargetNodeName(unsigned Opcode) const;
523 /// getSetCCResultType - Return the ISD::SETCC ValueType
524 virtual MVT::SimpleValueType getSetCCResultType(EVT VT) const;
526 /// computeMaskedBitsForTargetNode - Determine which of the bits specified
527 /// in Mask are known to be either zero or one and return them in the
528 /// KnownZero/KnownOne bitsets.
529 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
533 const SelectionDAG &DAG,
534 unsigned Depth = 0) const;
536 // ComputeNumSignBitsForTargetNode - Determine the number of bits in the
537 // operation that are sign bits.
538 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
539 unsigned Depth) const;
542 isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const;
544 SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
546 virtual bool ExpandInlineAsm(CallInst *CI) const;
548 ConstraintType getConstraintType(const std::string &Constraint) const;
550 /// Examine constraint string and operand type and determine a weight value.
551 /// The operand object must already have been set up with the operand type.
552 virtual ConstraintWeight getSingleConstraintMatchWeight(
553 AsmOperandInfo &info, const char *constraint) const;
555 std::vector<unsigned>
556 getRegClassForInlineAsmConstraint(const std::string &Constraint,
559 virtual const char *LowerXConstraint(EVT ConstraintVT) const;
561 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
562 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
563 /// true it means one of the asm constraint of the inline asm instruction
564 /// being processed is 'm'.
565 virtual void LowerAsmOperandForConstraint(SDValue Op,
566 char ConstraintLetter,
567 std::vector<SDValue> &Ops,
568 SelectionDAG &DAG) const;
570 /// getRegForInlineAsmConstraint - Given a physical register constraint
571 /// (e.g. {edx}), return the register number and the register class for the
572 /// register. This should only be used for C_Register constraints. On
573 /// error, this returns a register number of 0.
574 std::pair<unsigned, const TargetRegisterClass*>
575 getRegForInlineAsmConstraint(const std::string &Constraint,
578 /// isLegalAddressingMode - Return true if the addressing mode represented
579 /// by AM is legal for this target, for a load/store of the specified type.
580 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty)const;
582 /// isTruncateFree - Return true if it's free to truncate a value of
583 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
584 /// register EAX to i16 by referencing its sub-register AX.
585 virtual bool isTruncateFree(const Type *Ty1, const Type *Ty2) const;
586 virtual bool isTruncateFree(EVT VT1, EVT VT2) const;
588 /// isZExtFree - Return true if any actual instruction that defines a
589 /// value of type Ty1 implicit zero-extends the value to Ty2 in the result
590 /// register. This does not necessarily include registers defined in
591 /// unknown ways, such as incoming arguments, or copies from unknown
592 /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this
593 /// does not necessarily apply to truncate instructions. e.g. on x86-64,
594 /// all instructions that define 32-bit values implicit zero-extend the
595 /// result out to 64 bits.
596 virtual bool isZExtFree(const Type *Ty1, const Type *Ty2) const;
597 virtual bool isZExtFree(EVT VT1, EVT VT2) const;
599 /// isNarrowingProfitable - Return true if it's profitable to narrow
600 /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow
601 /// from i32 to i8 but not from i32 to i16.
602 virtual bool isNarrowingProfitable(EVT VT1, EVT VT2) const;
604 /// isFPImmLegal - Returns true if the target can instruction select the
605 /// specified FP immediate natively. If false, the legalizer will
606 /// materialize the FP immediate as a load from a constant pool.
607 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
609 /// isShuffleMaskLegal - Targets can use this to indicate that they only
610 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
611 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask
612 /// values are assumed to be legal.
613 virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask,
616 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is
617 /// used by Targets can use this to indicate if there is a suitable
618 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
620 virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
623 /// ShouldShrinkFPConstant - If true, then instruction selection should
624 /// seek to shrink the FP constant of the specified type to a smaller type
625 /// in order to save space and / or reduce runtime.
626 virtual bool ShouldShrinkFPConstant(EVT VT) const {
627 // Don't shrink FP constpool if SSE2 is available since cvtss2sd is more
628 // expensive than a straight movsd. On the other hand, it's important to
629 // shrink long double fp constant since fldt is very slow.
630 return !X86ScalarSSEf64 || VT == MVT::f80;
633 const X86Subtarget* getSubtarget() const {
637 /// isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is
638 /// computed in an SSE register, not on the X87 floating point stack.
639 bool isScalarFPTypeInSSEReg(EVT VT) const {
640 return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2
641 (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1
644 /// createFastISel - This method returns a target specific FastISel object,
645 /// or null if the target does not support "fast" ISel.
646 virtual FastISel *createFastISel(FunctionLoweringInfo &funcInfo) const;
648 /// getFunctionAlignment - Return the Log2 alignment of this function.
649 virtual unsigned getFunctionAlignment(const Function *F) const;
651 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
652 MachineFunction &MF) const;
654 /// getStackCookieLocation - Return true if the target stores stack
655 /// protector cookies at a fixed offset in some non-standard address
656 /// space, and populates the address space and offset as
658 virtual bool getStackCookieLocation(unsigned &AddressSpace, unsigned &Offset) const;
661 std::pair<const TargetRegisterClass*, uint8_t>
662 findRepresentativeClass(EVT VT) const;
665 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
666 /// make the right decision when generating code for different targets.
667 const X86Subtarget *Subtarget;
668 const X86RegisterInfo *RegInfo;
669 const TargetData *TD;
671 /// X86StackPtr - X86 physical register used as stack ptr.
672 unsigned X86StackPtr;
674 /// X86ScalarSSEf32, X86ScalarSSEf64 - Select between SSE or x87
675 /// floating point ops.
676 /// When SSE is available, use it for f32 operations.
677 /// When SSE2 is available, use it for f64 operations.
678 bool X86ScalarSSEf32;
679 bool X86ScalarSSEf64;
681 /// LegalFPImmediates - A list of legal fp immediates.
682 std::vector<APFloat> LegalFPImmediates;
684 /// addLegalFPImmediate - Indicate that this x86 target can instruction
685 /// select the specified FP immediate natively.
686 void addLegalFPImmediate(const APFloat& Imm) {
687 LegalFPImmediates.push_back(Imm);
690 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
691 CallingConv::ID CallConv, bool isVarArg,
692 const SmallVectorImpl<ISD::InputArg> &Ins,
693 DebugLoc dl, SelectionDAG &DAG,
694 SmallVectorImpl<SDValue> &InVals) const;
695 SDValue LowerMemArgument(SDValue Chain,
696 CallingConv::ID CallConv,
697 const SmallVectorImpl<ISD::InputArg> &ArgInfo,
698 DebugLoc dl, SelectionDAG &DAG,
699 const CCValAssign &VA, MachineFrameInfo *MFI,
701 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
702 DebugLoc dl, SelectionDAG &DAG,
703 const CCValAssign &VA,
704 ISD::ArgFlagsTy Flags) const;
706 // Call lowering helpers.
708 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
709 /// for tail call optimization. Targets which want to do tail call
710 /// optimization should implement this function.
711 bool IsEligibleForTailCallOptimization(SDValue Callee,
712 CallingConv::ID CalleeCC,
714 bool isCalleeStructRet,
715 bool isCallerStructRet,
716 const SmallVectorImpl<ISD::OutputArg> &Outs,
717 const SmallVectorImpl<SDValue> &OutVals,
718 const SmallVectorImpl<ISD::InputArg> &Ins,
719 SelectionDAG& DAG) const;
720 bool IsCalleePop(bool isVarArg, CallingConv::ID CallConv) const;
721 SDValue EmitTailCallLoadRetAddr(SelectionDAG &DAG, SDValue &OutRetAddr,
722 SDValue Chain, bool IsTailCall, bool Is64Bit,
723 int FPDiff, DebugLoc dl) const;
725 unsigned GetAlignedArgumentStackSize(unsigned StackSize,
726 SelectionDAG &DAG) const;
728 std::pair<SDValue,SDValue> FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
729 bool isSigned) const;
731 SDValue LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
732 SelectionDAG &DAG) const;
733 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
734 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
735 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
736 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
737 SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) const;
738 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
739 SDValue LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) const;
740 SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
741 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
742 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
743 SDValue LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
744 int64_t Offset, SelectionDAG &DAG) const;
745 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
746 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
747 SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const;
748 SDValue LowerShift(SDValue Op, SelectionDAG &DAG) const;
749 SDValue BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, SDValue StackSlot,
750 SelectionDAG &DAG) const;
751 SDValue LowerBITCAST(SDValue op, SelectionDAG &DAG) const;
752 SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
753 SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
754 SDValue LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) const;
755 SDValue LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) const;
756 SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
757 SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const;
758 SDValue LowerFABS(SDValue Op, SelectionDAG &DAG) const;
759 SDValue LowerFNEG(SDValue Op, SelectionDAG &DAG) const;
760 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
761 SDValue LowerToBT(SDValue And, ISD::CondCode CC,
762 DebugLoc dl, SelectionDAG &DAG) const;
763 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
764 SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) const;
765 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
766 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
767 SDValue LowerMEMSET(SDValue Op, SelectionDAG &DAG) const;
768 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
769 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
770 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
771 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
772 SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
773 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
774 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
775 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
776 SDValue LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG) const;
777 SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
778 SDValue LowerTRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
779 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
780 SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) const;
781 SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) const;
782 SDValue LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG) const;
783 SDValue LowerSHL(SDValue Op, SelectionDAG &DAG) const;
784 SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) const;
786 SDValue LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const;
787 SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const;
788 SDValue LowerREADCYCLECOUNTER(SDValue Op, SelectionDAG &DAG) const;
789 SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const;
791 // Utility functions to help LowerVECTOR_SHUFFLE
792 SDValue LowerVECTOR_SHUFFLEv8i16(SDValue Op, SelectionDAG &DAG) const;
795 LowerFormalArguments(SDValue Chain,
796 CallingConv::ID CallConv, bool isVarArg,
797 const SmallVectorImpl<ISD::InputArg> &Ins,
798 DebugLoc dl, SelectionDAG &DAG,
799 SmallVectorImpl<SDValue> &InVals) const;
801 LowerCall(SDValue Chain, SDValue Callee,
802 CallingConv::ID CallConv, bool isVarArg, bool &isTailCall,
803 const SmallVectorImpl<ISD::OutputArg> &Outs,
804 const SmallVectorImpl<SDValue> &OutVals,
805 const SmallVectorImpl<ISD::InputArg> &Ins,
806 DebugLoc dl, SelectionDAG &DAG,
807 SmallVectorImpl<SDValue> &InVals) const;
810 LowerReturn(SDValue Chain,
811 CallingConv::ID CallConv, bool isVarArg,
812 const SmallVectorImpl<ISD::OutputArg> &Outs,
813 const SmallVectorImpl<SDValue> &OutVals,
814 DebugLoc dl, SelectionDAG &DAG) const;
816 virtual bool isUsedByReturnOnly(SDNode *N) const;
819 CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
820 const SmallVectorImpl<ISD::OutputArg> &Outs,
821 LLVMContext &Context) const;
823 void ReplaceATOMIC_BINARY_64(SDNode *N, SmallVectorImpl<SDValue> &Results,
824 SelectionDAG &DAG, unsigned NewOp) const;
826 /// Utility function to emit string processing sse4.2 instructions
827 /// that return in xmm0.
828 /// This takes the instruction to expand, the associated machine basic
829 /// block, the number of args, and whether or not the second arg is
830 /// in memory or not.
831 MachineBasicBlock *EmitPCMP(MachineInstr *BInstr, MachineBasicBlock *BB,
832 unsigned argNum, bool inMem) const;
834 /// Utility functions to emit monitor and mwait instructions. These
835 /// need to make sure that the arguments to the intrinsic are in the
836 /// correct registers.
837 MachineBasicBlock *EmitMonitor(MachineInstr *MI,
838 MachineBasicBlock *BB) const;
839 MachineBasicBlock *EmitMwait(MachineInstr *MI, MachineBasicBlock *BB) const;
841 /// Utility function to emit atomic bitwise operations (and, or, xor).
842 /// It takes the bitwise instruction to expand, the associated machine basic
843 /// block, and the associated X86 opcodes for reg/reg and reg/imm.
844 MachineBasicBlock *EmitAtomicBitwiseWithCustomInserter(
845 MachineInstr *BInstr,
846 MachineBasicBlock *BB,
853 TargetRegisterClass *RC,
854 bool invSrc = false) const;
856 MachineBasicBlock *EmitAtomicBit6432WithCustomInserter(
857 MachineInstr *BInstr,
858 MachineBasicBlock *BB,
863 bool invSrc = false) const;
865 /// Utility function to emit atomic min and max. It takes the min/max
866 /// instruction to expand, the associated basic block, and the associated
867 /// cmov opcode for moving the min or max value.
868 MachineBasicBlock *EmitAtomicMinMaxWithCustomInserter(MachineInstr *BInstr,
869 MachineBasicBlock *BB,
870 unsigned cmovOpc) const;
872 // Utility function to emit the low-level va_arg code for X86-64.
873 MachineBasicBlock *EmitVAARG64WithCustomInserter(
875 MachineBasicBlock *MBB) const;
877 /// Utility function to emit the xmm reg save portion of va_start.
878 MachineBasicBlock *EmitVAStartSaveXMMRegsWithCustomInserter(
879 MachineInstr *BInstr,
880 MachineBasicBlock *BB) const;
882 MachineBasicBlock *EmitLoweredSelect(MachineInstr *I,
883 MachineBasicBlock *BB) const;
885 MachineBasicBlock *EmitLoweredWinAlloca(MachineInstr *MI,
886 MachineBasicBlock *BB) const;
888 MachineBasicBlock *EmitLoweredTLSCall(MachineInstr *MI,
889 MachineBasicBlock *BB) const;
891 MachineBasicBlock *emitLoweredTLSAddr(MachineInstr *MI,
892 MachineBasicBlock *BB) const;
894 /// Emit nodes that will be selected as "test Op0,Op0", or something
895 /// equivalent, for use with the given x86 condition code.
896 SDValue EmitTest(SDValue Op0, unsigned X86CC, SelectionDAG &DAG) const;
898 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
899 /// equivalent, for use with the given x86 condition code.
900 SDValue EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
901 SelectionDAG &DAG) const;
905 FastISel *createFastISel(FunctionLoweringInfo &funcInfo);
909 #endif // X86ISELLOWERING_H