1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
16 #include "X86ISelLowering.h"
17 #include "Utils/X86ShuffleDecode.h"
19 #include "X86InstrBuilder.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/ADT/SmallSet.h"
23 #include "llvm/ADT/Statistic.h"
24 #include "llvm/ADT/StringExtras.h"
25 #include "llvm/ADT/VariadicFunction.h"
26 #include "llvm/CodeGen/IntrinsicLowering.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineJumpTableInfo.h"
31 #include "llvm/CodeGen/MachineModuleInfo.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/IR/CallingConv.h"
34 #include "llvm/IR/Constants.h"
35 #include "llvm/IR/DerivedTypes.h"
36 #include "llvm/IR/Function.h"
37 #include "llvm/IR/GlobalAlias.h"
38 #include "llvm/IR/GlobalVariable.h"
39 #include "llvm/IR/Instructions.h"
40 #include "llvm/IR/Intrinsics.h"
41 #include "llvm/IR/LLVMContext.h"
42 #include "llvm/MC/MCAsmInfo.h"
43 #include "llvm/MC/MCContext.h"
44 #include "llvm/MC/MCExpr.h"
45 #include "llvm/MC/MCSymbol.h"
46 #include "llvm/Support/CallSite.h"
47 #include "llvm/Support/Debug.h"
48 #include "llvm/Support/ErrorHandling.h"
49 #include "llvm/Support/MathExtras.h"
50 #include "llvm/Target/TargetOptions.h"
55 STATISTIC(NumTailCalls, "Number of tail calls");
57 // Forward declarations.
58 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
61 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
62 SelectionDAG &DAG, SDLoc dl,
63 unsigned vectorWidth) {
64 assert((vectorWidth == 128 || vectorWidth == 256) &&
65 "Unsupported vector width");
66 EVT VT = Vec.getValueType();
67 EVT ElVT = VT.getVectorElementType();
68 unsigned Factor = VT.getSizeInBits()/vectorWidth;
69 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
70 VT.getVectorNumElements()/Factor);
72 // Extract from UNDEF is UNDEF.
73 if (Vec.getOpcode() == ISD::UNDEF)
74 return DAG.getUNDEF(ResultVT);
76 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
77 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
79 // This is the index of the first element of the vectorWidth-bit chunk
81 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
84 // If the input is a buildvector just emit a smaller one.
85 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
86 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
87 Vec->op_begin()+NormalizedIdxVal, ElemsPerChunk);
89 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
90 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
96 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
97 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
98 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
99 /// instructions or a simple subregister reference. Idx is an index in the
100 /// 128 bits we want. It need not be aligned to a 128-bit bounday. That makes
101 /// lowering EXTRACT_VECTOR_ELT operations easier.
102 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
103 SelectionDAG &DAG, SDLoc dl) {
104 assert((Vec.getValueType().is256BitVector() ||
105 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
106 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
109 /// Generate a DAG to grab 256-bits from a 512-bit vector.
110 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
111 SelectionDAG &DAG, SDLoc dl) {
112 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
113 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
116 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
117 unsigned IdxVal, SelectionDAG &DAG,
118 SDLoc dl, unsigned vectorWidth) {
119 assert((vectorWidth == 128 || vectorWidth == 256) &&
120 "Unsupported vector width");
121 // Inserting UNDEF is Result
122 if (Vec.getOpcode() == ISD::UNDEF)
124 EVT VT = Vec.getValueType();
125 EVT ElVT = VT.getVectorElementType();
126 EVT ResultVT = Result.getValueType();
128 // Insert the relevant vectorWidth bits.
129 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
131 // This is the index of the first element of the vectorWidth-bit chunk
133 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
136 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
137 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
140 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
141 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
142 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
143 /// simple superregister reference. Idx is an index in the 128 bits
144 /// we want. It need not be aligned to a 128-bit bounday. That makes
145 /// lowering INSERT_VECTOR_ELT operations easier.
146 static SDValue Insert128BitVector(SDValue Result, SDValue Vec,
147 unsigned IdxVal, SelectionDAG &DAG,
149 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
150 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
153 static SDValue Insert256BitVector(SDValue Result, SDValue Vec,
154 unsigned IdxVal, SelectionDAG &DAG,
156 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
157 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
160 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
161 /// instructions. This is used because creating CONCAT_VECTOR nodes of
162 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
163 /// large BUILD_VECTORS.
164 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
165 unsigned NumElems, SelectionDAG &DAG,
167 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
168 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
171 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
172 unsigned NumElems, SelectionDAG &DAG,
174 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
175 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
178 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
179 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
180 bool is64Bit = Subtarget->is64Bit();
182 if (Subtarget->isTargetEnvMacho()) {
184 return new X86_64MachoTargetObjectFile();
185 return new TargetLoweringObjectFileMachO();
188 if (Subtarget->isTargetLinux())
189 return new X86LinuxTargetObjectFile();
190 if (Subtarget->isTargetELF())
191 return new TargetLoweringObjectFileELF();
192 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
193 return new TargetLoweringObjectFileCOFF();
194 llvm_unreachable("unknown subtarget type");
197 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
198 : TargetLowering(TM, createTLOF(TM)) {
199 Subtarget = &TM.getSubtarget<X86Subtarget>();
200 X86ScalarSSEf64 = Subtarget->hasSSE2();
201 X86ScalarSSEf32 = Subtarget->hasSSE1();
202 TD = getDataLayout();
204 resetOperationActions();
207 void X86TargetLowering::resetOperationActions() {
208 const TargetMachine &TM = getTargetMachine();
209 static bool FirstTimeThrough = true;
211 // If none of the target options have changed, then we don't need to reset the
212 // operation actions.
213 if (!FirstTimeThrough && TO == TM.Options) return;
215 if (!FirstTimeThrough) {
216 // Reinitialize the actions.
218 FirstTimeThrough = false;
223 // Set up the TargetLowering object.
224 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
226 // X86 is weird, it always uses i8 for shift amounts and setcc results.
227 setBooleanContents(ZeroOrOneBooleanContent);
228 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
229 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
231 // For 64-bit since we have so many registers use the ILP scheduler, for
232 // 32-bit code use the register pressure specific scheduling.
233 // For Atom, always use ILP scheduling.
234 if (Subtarget->isAtom())
235 setSchedulingPreference(Sched::ILP);
236 else if (Subtarget->is64Bit())
237 setSchedulingPreference(Sched::ILP);
239 setSchedulingPreference(Sched::RegPressure);
240 const X86RegisterInfo *RegInfo =
241 static_cast<const X86RegisterInfo*>(TM.getRegisterInfo());
242 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
244 // Bypass expensive divides on Atom when compiling with O2
245 if (Subtarget->hasSlowDivide() && TM.getOptLevel() >= CodeGenOpt::Default) {
246 addBypassSlowDiv(32, 8);
247 if (Subtarget->is64Bit())
248 addBypassSlowDiv(64, 16);
251 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) {
252 // Setup Windows compiler runtime calls.
253 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
254 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
255 setLibcallName(RTLIB::SREM_I64, "_allrem");
256 setLibcallName(RTLIB::UREM_I64, "_aullrem");
257 setLibcallName(RTLIB::MUL_I64, "_allmul");
258 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
259 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
260 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
261 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
262 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
264 // The _ftol2 runtime function has an unusual calling conv, which
265 // is modeled by a special pseudo-instruction.
266 setLibcallName(RTLIB::FPTOUINT_F64_I64, 0);
267 setLibcallName(RTLIB::FPTOUINT_F32_I64, 0);
268 setLibcallName(RTLIB::FPTOUINT_F64_I32, 0);
269 setLibcallName(RTLIB::FPTOUINT_F32_I32, 0);
272 if (Subtarget->isTargetDarwin()) {
273 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
274 setUseUnderscoreSetJmp(false);
275 setUseUnderscoreLongJmp(false);
276 } else if (Subtarget->isTargetMingw()) {
277 // MS runtime is weird: it exports _setjmp, but longjmp!
278 setUseUnderscoreSetJmp(true);
279 setUseUnderscoreLongJmp(false);
281 setUseUnderscoreSetJmp(true);
282 setUseUnderscoreLongJmp(true);
285 // Set up the register classes.
286 addRegisterClass(MVT::i8, &X86::GR8RegClass);
287 addRegisterClass(MVT::i16, &X86::GR16RegClass);
288 addRegisterClass(MVT::i32, &X86::GR32RegClass);
289 if (Subtarget->is64Bit())
290 addRegisterClass(MVT::i64, &X86::GR64RegClass);
292 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
294 // We don't accept any truncstore of integer registers.
295 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
296 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
297 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
298 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
299 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
300 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
302 // SETOEQ and SETUNE require checking two conditions.
303 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
304 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
305 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
306 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
307 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
308 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
310 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
312 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
313 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
314 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
316 if (Subtarget->is64Bit()) {
317 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
318 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
319 } else if (!TM.Options.UseSoftFloat) {
320 // We have an algorithm for SSE2->double, and we turn this into a
321 // 64-bit FILD followed by conditional FADD for other targets.
322 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
323 // We have an algorithm for SSE2, and we turn this into a 64-bit
324 // FILD for other targets.
325 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
328 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
330 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
331 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
333 if (!TM.Options.UseSoftFloat) {
334 // SSE has no i16 to fp conversion, only i32
335 if (X86ScalarSSEf32) {
336 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
337 // f32 and f64 cases are Legal, f80 case is not
338 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
340 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
341 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
344 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
345 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
348 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
349 // are Legal, f80 is custom lowered.
350 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
351 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
353 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
355 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
356 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
358 if (X86ScalarSSEf32) {
359 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
360 // f32 and f64 cases are Legal, f80 case is not
361 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
363 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
364 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
367 // Handle FP_TO_UINT by promoting the destination to a larger signed
369 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
370 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
371 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
373 if (Subtarget->is64Bit()) {
374 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
375 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
376 } else if (!TM.Options.UseSoftFloat) {
377 // Since AVX is a superset of SSE3, only check for SSE here.
378 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
379 // Expand FP_TO_UINT into a select.
380 // FIXME: We would like to use a Custom expander here eventually to do
381 // the optimal thing for SSE vs. the default expansion in the legalizer.
382 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
384 // With SSE3 we can use fisttpll to convert to a signed i64; without
385 // SSE, we're stuck with a fistpll.
386 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
389 if (isTargetFTOL()) {
390 // Use the _ftol2 runtime function, which has a pseudo-instruction
391 // to handle its weird calling convention.
392 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
395 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
396 if (!X86ScalarSSEf64) {
397 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
398 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
399 if (Subtarget->is64Bit()) {
400 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
401 // Without SSE, i64->f64 goes through memory.
402 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
406 // Scalar integer divide and remainder are lowered to use operations that
407 // produce two results, to match the available instructions. This exposes
408 // the two-result form to trivial CSE, which is able to combine x/y and x%y
409 // into a single instruction.
411 // Scalar integer multiply-high is also lowered to use two-result
412 // operations, to match the available instructions. However, plain multiply
413 // (low) operations are left as Legal, as there are single-result
414 // instructions for this in x86. Using the two-result multiply instructions
415 // when both high and low results are needed must be arranged by dagcombine.
416 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
418 setOperationAction(ISD::MULHS, VT, Expand);
419 setOperationAction(ISD::MULHU, VT, Expand);
420 setOperationAction(ISD::SDIV, VT, Expand);
421 setOperationAction(ISD::UDIV, VT, Expand);
422 setOperationAction(ISD::SREM, VT, Expand);
423 setOperationAction(ISD::UREM, VT, Expand);
425 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
426 setOperationAction(ISD::ADDC, VT, Custom);
427 setOperationAction(ISD::ADDE, VT, Custom);
428 setOperationAction(ISD::SUBC, VT, Custom);
429 setOperationAction(ISD::SUBE, VT, Custom);
432 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
433 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
434 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
435 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
436 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
437 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
438 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
439 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
440 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
441 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
442 if (Subtarget->is64Bit())
443 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
444 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
445 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
446 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
447 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
448 setOperationAction(ISD::FREM , MVT::f32 , Expand);
449 setOperationAction(ISD::FREM , MVT::f64 , Expand);
450 setOperationAction(ISD::FREM , MVT::f80 , Expand);
451 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
453 // Promote the i8 variants and force them on up to i32 which has a shorter
455 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
456 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
457 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
458 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
459 if (Subtarget->hasBMI()) {
460 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
461 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
462 if (Subtarget->is64Bit())
463 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
465 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
466 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
467 if (Subtarget->is64Bit())
468 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
471 if (Subtarget->hasLZCNT()) {
472 // When promoting the i8 variants, force them to i32 for a shorter
474 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
475 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
476 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
477 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
478 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
479 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
480 if (Subtarget->is64Bit())
481 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
483 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
484 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
485 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
486 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
487 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
488 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
489 if (Subtarget->is64Bit()) {
490 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
491 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
495 if (Subtarget->hasPOPCNT()) {
496 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
498 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
499 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
500 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
501 if (Subtarget->is64Bit())
502 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
505 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
506 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
508 // These should be promoted to a larger select which is supported.
509 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
510 // X86 wants to expand cmov itself.
511 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
512 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
513 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
514 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
515 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
516 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
517 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
518 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
519 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
520 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
521 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
522 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
523 if (Subtarget->is64Bit()) {
524 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
525 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
527 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
528 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
529 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
530 // support continuation, user-level threading, and etc.. As a result, no
531 // other SjLj exception interfaces are implemented and please don't build
532 // your own exception handling based on them.
533 // LLVM/Clang supports zero-cost DWARF exception handling.
534 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
535 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
538 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
539 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
540 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
541 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
542 if (Subtarget->is64Bit())
543 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
544 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
545 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
546 if (Subtarget->is64Bit()) {
547 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
548 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
549 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
550 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
551 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
553 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
554 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
555 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
556 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
557 if (Subtarget->is64Bit()) {
558 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
559 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
560 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
563 if (Subtarget->hasSSE1())
564 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
566 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
568 // Expand certain atomics
569 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
571 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom);
572 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
573 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
576 if (!Subtarget->is64Bit()) {
577 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
578 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
579 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
580 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
581 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
582 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
583 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
584 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
585 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i64, Custom);
586 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i64, Custom);
587 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i64, Custom);
588 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i64, Custom);
591 if (Subtarget->hasCmpxchg16b()) {
592 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom);
595 // FIXME - use subtarget debug flags
596 if (!Subtarget->isTargetDarwin() &&
597 !Subtarget->isTargetELF() &&
598 !Subtarget->isTargetCygMing()) {
599 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
602 if (Subtarget->is64Bit()) {
603 setExceptionPointerRegister(X86::RAX);
604 setExceptionSelectorRegister(X86::RDX);
606 setExceptionPointerRegister(X86::EAX);
607 setExceptionSelectorRegister(X86::EDX);
609 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
610 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
612 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
613 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
615 setOperationAction(ISD::TRAP, MVT::Other, Legal);
616 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
618 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
619 setOperationAction(ISD::VASTART , MVT::Other, Custom);
620 setOperationAction(ISD::VAEND , MVT::Other, Expand);
621 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
622 // TargetInfo::X86_64ABIBuiltinVaList
623 setOperationAction(ISD::VAARG , MVT::Other, Custom);
624 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
626 // TargetInfo::CharPtrBuiltinVaList
627 setOperationAction(ISD::VAARG , MVT::Other, Expand);
628 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
631 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
632 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
634 if (Subtarget->isOSWindows() && !Subtarget->isTargetEnvMacho())
635 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
636 MVT::i64 : MVT::i32, Custom);
637 else if (TM.Options.EnableSegmentedStacks)
638 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
639 MVT::i64 : MVT::i32, Custom);
641 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
642 MVT::i64 : MVT::i32, Expand);
644 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
645 // f32 and f64 use SSE.
646 // Set up the FP register classes.
647 addRegisterClass(MVT::f32, &X86::FR32RegClass);
648 addRegisterClass(MVT::f64, &X86::FR64RegClass);
650 // Use ANDPD to simulate FABS.
651 setOperationAction(ISD::FABS , MVT::f64, Custom);
652 setOperationAction(ISD::FABS , MVT::f32, Custom);
654 // Use XORP to simulate FNEG.
655 setOperationAction(ISD::FNEG , MVT::f64, Custom);
656 setOperationAction(ISD::FNEG , MVT::f32, Custom);
658 // Use ANDPD and ORPD to simulate FCOPYSIGN.
659 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
660 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
662 // Lower this to FGETSIGNx86 plus an AND.
663 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
664 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
666 // We don't support sin/cos/fmod
667 setOperationAction(ISD::FSIN , MVT::f64, Expand);
668 setOperationAction(ISD::FCOS , MVT::f64, Expand);
669 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
670 setOperationAction(ISD::FSIN , MVT::f32, Expand);
671 setOperationAction(ISD::FCOS , MVT::f32, Expand);
672 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
674 // Expand FP immediates into loads from the stack, except for the special
676 addLegalFPImmediate(APFloat(+0.0)); // xorpd
677 addLegalFPImmediate(APFloat(+0.0f)); // xorps
678 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
679 // Use SSE for f32, x87 for f64.
680 // Set up the FP register classes.
681 addRegisterClass(MVT::f32, &X86::FR32RegClass);
682 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
684 // Use ANDPS to simulate FABS.
685 setOperationAction(ISD::FABS , MVT::f32, Custom);
687 // Use XORP to simulate FNEG.
688 setOperationAction(ISD::FNEG , MVT::f32, Custom);
690 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
692 // Use ANDPS and ORPS to simulate FCOPYSIGN.
693 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
694 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
696 // We don't support sin/cos/fmod
697 setOperationAction(ISD::FSIN , MVT::f32, Expand);
698 setOperationAction(ISD::FCOS , MVT::f32, Expand);
699 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
701 // Special cases we handle for FP constants.
702 addLegalFPImmediate(APFloat(+0.0f)); // xorps
703 addLegalFPImmediate(APFloat(+0.0)); // FLD0
704 addLegalFPImmediate(APFloat(+1.0)); // FLD1
705 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
706 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
708 if (!TM.Options.UnsafeFPMath) {
709 setOperationAction(ISD::FSIN , MVT::f64, Expand);
710 setOperationAction(ISD::FCOS , MVT::f64, Expand);
711 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
713 } else if (!TM.Options.UseSoftFloat) {
714 // f32 and f64 in x87.
715 // Set up the FP register classes.
716 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
717 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
719 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
720 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
721 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
722 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
724 if (!TM.Options.UnsafeFPMath) {
725 setOperationAction(ISD::FSIN , MVT::f64, Expand);
726 setOperationAction(ISD::FSIN , MVT::f32, Expand);
727 setOperationAction(ISD::FCOS , MVT::f64, Expand);
728 setOperationAction(ISD::FCOS , MVT::f32, Expand);
729 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
730 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
732 addLegalFPImmediate(APFloat(+0.0)); // FLD0
733 addLegalFPImmediate(APFloat(+1.0)); // FLD1
734 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
735 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
736 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
737 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
738 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
739 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
742 // We don't support FMA.
743 setOperationAction(ISD::FMA, MVT::f64, Expand);
744 setOperationAction(ISD::FMA, MVT::f32, Expand);
746 // Long double always uses X87.
747 if (!TM.Options.UseSoftFloat) {
748 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
749 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
750 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
752 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
753 addLegalFPImmediate(TmpFlt); // FLD0
755 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
758 APFloat TmpFlt2(+1.0);
759 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
761 addLegalFPImmediate(TmpFlt2); // FLD1
762 TmpFlt2.changeSign();
763 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
766 if (!TM.Options.UnsafeFPMath) {
767 setOperationAction(ISD::FSIN , MVT::f80, Expand);
768 setOperationAction(ISD::FCOS , MVT::f80, Expand);
769 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
772 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
773 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
774 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
775 setOperationAction(ISD::FRINT, MVT::f80, Expand);
776 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
777 setOperationAction(ISD::FMA, MVT::f80, Expand);
780 // Always use a library call for pow.
781 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
782 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
783 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
785 setOperationAction(ISD::FLOG, MVT::f80, Expand);
786 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
787 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
788 setOperationAction(ISD::FEXP, MVT::f80, Expand);
789 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
791 // First set operation action for all vector types to either promote
792 // (for widening) or expand (for scalarization). Then we will selectively
793 // turn on ones that can be effectively codegen'd.
794 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
795 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
796 MVT VT = (MVT::SimpleValueType)i;
797 setOperationAction(ISD::ADD , VT, Expand);
798 setOperationAction(ISD::SUB , VT, Expand);
799 setOperationAction(ISD::FADD, VT, Expand);
800 setOperationAction(ISD::FNEG, VT, Expand);
801 setOperationAction(ISD::FSUB, VT, Expand);
802 setOperationAction(ISD::MUL , VT, Expand);
803 setOperationAction(ISD::FMUL, VT, Expand);
804 setOperationAction(ISD::SDIV, VT, Expand);
805 setOperationAction(ISD::UDIV, VT, Expand);
806 setOperationAction(ISD::FDIV, VT, Expand);
807 setOperationAction(ISD::SREM, VT, Expand);
808 setOperationAction(ISD::UREM, VT, Expand);
809 setOperationAction(ISD::LOAD, VT, Expand);
810 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
811 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
812 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
813 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
814 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
815 setOperationAction(ISD::FABS, VT, Expand);
816 setOperationAction(ISD::FSIN, VT, Expand);
817 setOperationAction(ISD::FSINCOS, VT, Expand);
818 setOperationAction(ISD::FCOS, VT, Expand);
819 setOperationAction(ISD::FSINCOS, VT, Expand);
820 setOperationAction(ISD::FREM, VT, Expand);
821 setOperationAction(ISD::FMA, VT, Expand);
822 setOperationAction(ISD::FPOWI, VT, Expand);
823 setOperationAction(ISD::FSQRT, VT, Expand);
824 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
825 setOperationAction(ISD::FFLOOR, VT, Expand);
826 setOperationAction(ISD::FCEIL, VT, Expand);
827 setOperationAction(ISD::FTRUNC, VT, Expand);
828 setOperationAction(ISD::FRINT, VT, Expand);
829 setOperationAction(ISD::FNEARBYINT, VT, Expand);
830 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
831 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
832 setOperationAction(ISD::SDIVREM, VT, Expand);
833 setOperationAction(ISD::UDIVREM, VT, Expand);
834 setOperationAction(ISD::FPOW, VT, Expand);
835 setOperationAction(ISD::CTPOP, VT, Expand);
836 setOperationAction(ISD::CTTZ, VT, Expand);
837 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
838 setOperationAction(ISD::CTLZ, VT, Expand);
839 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
840 setOperationAction(ISD::SHL, VT, Expand);
841 setOperationAction(ISD::SRA, VT, Expand);
842 setOperationAction(ISD::SRL, VT, Expand);
843 setOperationAction(ISD::ROTL, VT, Expand);
844 setOperationAction(ISD::ROTR, VT, Expand);
845 setOperationAction(ISD::BSWAP, VT, Expand);
846 setOperationAction(ISD::SETCC, VT, Expand);
847 setOperationAction(ISD::FLOG, VT, Expand);
848 setOperationAction(ISD::FLOG2, VT, Expand);
849 setOperationAction(ISD::FLOG10, VT, Expand);
850 setOperationAction(ISD::FEXP, VT, Expand);
851 setOperationAction(ISD::FEXP2, VT, Expand);
852 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
853 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
854 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
855 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
856 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
857 setOperationAction(ISD::TRUNCATE, VT, Expand);
858 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
859 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
860 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
861 setOperationAction(ISD::VSELECT, VT, Expand);
862 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
863 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
864 setTruncStoreAction(VT,
865 (MVT::SimpleValueType)InnerVT, Expand);
866 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
867 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
868 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
871 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
872 // with -msoft-float, disable use of MMX as well.
873 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
874 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
875 // No operations on x86mmx supported, everything uses intrinsics.
878 // MMX-sized vectors (other than x86mmx) are expected to be expanded
879 // into smaller operations.
880 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
881 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
882 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
883 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
884 setOperationAction(ISD::AND, MVT::v8i8, Expand);
885 setOperationAction(ISD::AND, MVT::v4i16, Expand);
886 setOperationAction(ISD::AND, MVT::v2i32, Expand);
887 setOperationAction(ISD::AND, MVT::v1i64, Expand);
888 setOperationAction(ISD::OR, MVT::v8i8, Expand);
889 setOperationAction(ISD::OR, MVT::v4i16, Expand);
890 setOperationAction(ISD::OR, MVT::v2i32, Expand);
891 setOperationAction(ISD::OR, MVT::v1i64, Expand);
892 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
893 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
894 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
895 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
896 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
897 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
898 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
899 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
900 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
901 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
902 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
903 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
904 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
905 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
906 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
907 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
908 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
910 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
911 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
913 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
914 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
915 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
916 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
917 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
918 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
919 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
920 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
921 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
922 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
923 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
924 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
927 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
928 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
930 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
931 // registers cannot be used even for integer operations.
932 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
933 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
934 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
935 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
937 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
938 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
939 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
940 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
941 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
942 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
943 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
944 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
945 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
946 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
947 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
948 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
949 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
950 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
951 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
952 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
953 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
954 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
956 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
957 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
958 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
959 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
961 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
962 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
963 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
964 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
965 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
967 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
968 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
969 MVT VT = (MVT::SimpleValueType)i;
970 // Do not attempt to custom lower non-power-of-2 vectors
971 if (!isPowerOf2_32(VT.getVectorNumElements()))
973 // Do not attempt to custom lower non-128-bit vectors
974 if (!VT.is128BitVector())
976 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
977 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
978 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
981 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
982 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
983 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
984 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
985 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
986 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
988 if (Subtarget->is64Bit()) {
989 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
990 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
993 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
994 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
995 MVT VT = (MVT::SimpleValueType)i;
997 // Do not attempt to promote non-128-bit vectors
998 if (!VT.is128BitVector())
1001 setOperationAction(ISD::AND, VT, Promote);
1002 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
1003 setOperationAction(ISD::OR, VT, Promote);
1004 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
1005 setOperationAction(ISD::XOR, VT, Promote);
1006 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
1007 setOperationAction(ISD::LOAD, VT, Promote);
1008 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
1009 setOperationAction(ISD::SELECT, VT, Promote);
1010 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
1013 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
1015 // Custom lower v2i64 and v2f64 selects.
1016 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1017 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
1018 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
1019 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1021 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1022 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1024 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1025 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1026 // As there is no 64-bit GPR available, we need build a special custom
1027 // sequence to convert from v2i32 to v2f32.
1028 if (!Subtarget->is64Bit())
1029 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
1031 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1032 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1034 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal);
1037 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
1038 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1039 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1040 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1041 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1042 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1043 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1044 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1045 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1046 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1047 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1049 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1050 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1051 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1052 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1053 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1054 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1055 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1056 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1057 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1058 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1060 // FIXME: Do we need to handle scalar-to-vector here?
1061 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1063 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
1064 setOperationAction(ISD::VSELECT, MVT::v2i64, Legal);
1065 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1066 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
1067 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
1069 // i8 and i16 vectors are custom , because the source register and source
1070 // source memory operand types are not the same width. f32 vectors are
1071 // custom since the immediate controlling the insert encodes additional
1073 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1074 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1075 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1076 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1078 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1079 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1080 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1081 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1083 // FIXME: these should be Legal but thats only for the case where
1084 // the index is constant. For now custom expand to deal with that.
1085 if (Subtarget->is64Bit()) {
1086 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1087 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1091 if (Subtarget->hasSSE2()) {
1092 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1093 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1095 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1096 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1098 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1099 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1101 // In the customized shift lowering, the legal cases in AVX2 will be
1103 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1104 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1106 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1107 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1109 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1111 setOperationAction(ISD::SDIV, MVT::v8i16, Custom);
1112 setOperationAction(ISD::SDIV, MVT::v4i32, Custom);
1115 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1116 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1117 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1118 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1119 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1120 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1121 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1123 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1124 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1125 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1127 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1128 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1129 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1130 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1131 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1132 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1133 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1134 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1135 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1136 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1137 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1138 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1140 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1141 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1142 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1143 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1144 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1145 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1146 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1147 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1148 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1149 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1150 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1151 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1153 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Custom);
1155 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1156 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1157 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1158 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1160 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1161 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1163 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal);
1165 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1166 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1168 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1169 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1171 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1172 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1174 setOperationAction(ISD::SDIV, MVT::v16i16, Custom);
1176 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1177 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1178 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1179 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1181 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1182 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1183 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1185 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal);
1186 setOperationAction(ISD::VSELECT, MVT::v4i64, Legal);
1187 setOperationAction(ISD::VSELECT, MVT::v8i32, Legal);
1188 setOperationAction(ISD::VSELECT, MVT::v8f32, Legal);
1190 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1191 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1192 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1193 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1194 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1195 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1196 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1197 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1198 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1199 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1200 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1201 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1203 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1204 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1205 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1206 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1207 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1208 setOperationAction(ISD::FMA, MVT::f32, Legal);
1209 setOperationAction(ISD::FMA, MVT::f64, Legal);
1212 if (Subtarget->hasInt256()) {
1213 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1214 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1215 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1216 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1218 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1219 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1220 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1221 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1223 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1224 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1225 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1226 // Don't lower v32i8 because there is no 128-bit byte mul
1228 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1230 setOperationAction(ISD::SDIV, MVT::v8i32, Custom);
1232 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1233 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1234 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1235 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1237 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1238 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1239 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1240 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1242 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1243 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1244 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1245 // Don't lower v32i8 because there is no 128-bit byte mul
1248 // In the customized shift lowering, the legal cases in AVX2 will be
1250 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1251 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1253 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1254 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1256 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1258 // Custom lower several nodes for 256-bit types.
1259 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1260 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1261 MVT VT = (MVT::SimpleValueType)i;
1263 // Extract subvector is special because the value type
1264 // (result) is 128-bit but the source is 256-bit wide.
1265 if (VT.is128BitVector())
1266 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1268 // Do not attempt to custom lower other non-256-bit vectors
1269 if (!VT.is256BitVector())
1272 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1273 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1274 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1275 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1276 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1277 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1278 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1281 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1282 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1283 MVT VT = (MVT::SimpleValueType)i;
1285 // Do not attempt to promote non-256-bit vectors
1286 if (!VT.is256BitVector())
1289 setOperationAction(ISD::AND, VT, Promote);
1290 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1291 setOperationAction(ISD::OR, VT, Promote);
1292 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1293 setOperationAction(ISD::XOR, VT, Promote);
1294 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1295 setOperationAction(ISD::LOAD, VT, Promote);
1296 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1297 setOperationAction(ISD::SELECT, VT, Promote);
1298 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1302 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) {
1303 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1304 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1305 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1306 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1308 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1309 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1311 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, Legal);
1312 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1313 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1314 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1315 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1316 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1318 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1319 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1320 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1321 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1322 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1323 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1325 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1326 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1327 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1328 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1329 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1330 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1331 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1332 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1333 setOperationAction(ISD::SDIV, MVT::v16i32, Custom);
1335 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1336 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1337 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1338 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1339 if (Subtarget->is64Bit()) {
1340 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1341 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1342 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1343 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1345 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1346 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1347 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1348 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1349 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1350 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1351 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1352 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1354 setOperationAction(ISD::TRUNCATE, MVT::i1, Legal);
1355 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1356 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1357 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1358 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1359 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1360 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1361 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1362 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1363 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1364 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1365 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1367 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1368 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1369 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1370 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1371 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1373 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1374 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1376 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1378 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1379 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1380 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1381 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1382 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1384 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1385 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1387 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1388 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1390 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1392 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1393 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1395 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1396 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1398 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1399 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1401 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1402 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1403 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1404 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1405 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1406 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1408 // Custom lower several nodes.
1409 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1410 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1411 MVT VT = (MVT::SimpleValueType)i;
1413 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1414 // Extract subvector is special because the value type
1415 // (result) is 256/128-bit but the source is 512-bit wide.
1416 if (VT.is128BitVector() || VT.is256BitVector())
1417 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1419 if (VT.getVectorElementType() == MVT::i1)
1420 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1422 // Do not attempt to custom lower other non-512-bit vectors
1423 if (!VT.is512BitVector())
1426 if ( EltSize >= 32) {
1427 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1428 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1429 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1430 setOperationAction(ISD::VSELECT, VT, Legal);
1431 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1432 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1433 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1436 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1437 MVT VT = (MVT::SimpleValueType)i;
1439 // Do not attempt to promote non-256-bit vectors
1440 if (!VT.is512BitVector())
1443 setOperationAction(ISD::SELECT, VT, Promote);
1444 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1448 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1449 // of this type with custom code.
1450 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1451 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1452 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1456 // We want to custom lower some of our intrinsics.
1457 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1458 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1459 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1461 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1462 // handle type legalization for these operations here.
1464 // FIXME: We really should do custom legalization for addition and
1465 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1466 // than generic legalization for 64-bit multiplication-with-overflow, though.
1467 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1468 // Add/Sub/Mul with overflow operations are custom lowered.
1470 setOperationAction(ISD::SADDO, VT, Custom);
1471 setOperationAction(ISD::UADDO, VT, Custom);
1472 setOperationAction(ISD::SSUBO, VT, Custom);
1473 setOperationAction(ISD::USUBO, VT, Custom);
1474 setOperationAction(ISD::SMULO, VT, Custom);
1475 setOperationAction(ISD::UMULO, VT, Custom);
1478 // There are no 8-bit 3-address imul/mul instructions
1479 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1480 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1482 if (!Subtarget->is64Bit()) {
1483 // These libcalls are not available in 32-bit.
1484 setLibcallName(RTLIB::SHL_I128, 0);
1485 setLibcallName(RTLIB::SRL_I128, 0);
1486 setLibcallName(RTLIB::SRA_I128, 0);
1489 // Combine sin / cos into one node or libcall if possible.
1490 if (Subtarget->hasSinCos()) {
1491 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1492 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1493 if (Subtarget->isTargetDarwin()) {
1494 // For MacOSX, we don't want to the normal expansion of a libcall to
1495 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
1497 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1498 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1502 // We have target-specific dag combine patterns for the following nodes:
1503 setTargetDAGCombine(ISD::CONCAT_VECTORS);
1504 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1505 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1506 setTargetDAGCombine(ISD::VSELECT);
1507 setTargetDAGCombine(ISD::SELECT);
1508 setTargetDAGCombine(ISD::SHL);
1509 setTargetDAGCombine(ISD::SRA);
1510 setTargetDAGCombine(ISD::SRL);
1511 setTargetDAGCombine(ISD::OR);
1512 setTargetDAGCombine(ISD::AND);
1513 setTargetDAGCombine(ISD::ADD);
1514 setTargetDAGCombine(ISD::FADD);
1515 setTargetDAGCombine(ISD::FSUB);
1516 setTargetDAGCombine(ISD::FMA);
1517 setTargetDAGCombine(ISD::SUB);
1518 setTargetDAGCombine(ISD::LOAD);
1519 setTargetDAGCombine(ISD::STORE);
1520 setTargetDAGCombine(ISD::ZERO_EXTEND);
1521 setTargetDAGCombine(ISD::ANY_EXTEND);
1522 setTargetDAGCombine(ISD::SIGN_EXTEND);
1523 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1524 setTargetDAGCombine(ISD::TRUNCATE);
1525 setTargetDAGCombine(ISD::SINT_TO_FP);
1526 setTargetDAGCombine(ISD::SETCC);
1527 if (Subtarget->is64Bit())
1528 setTargetDAGCombine(ISD::MUL);
1529 setTargetDAGCombine(ISD::XOR);
1531 computeRegisterProperties();
1533 // On Darwin, -Os means optimize for size without hurting performance,
1534 // do not reduce the limit.
1535 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1536 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1537 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1538 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1539 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1540 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1541 setPrefLoopAlignment(4); // 2^4 bytes.
1543 // Predictable cmov don't hurt on atom because it's in-order.
1544 PredictableSelectIsExpensive = !Subtarget->isAtom();
1546 setPrefFunctionAlignment(4); // 2^4 bytes.
1549 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1550 if (!VT.isVector()) return MVT::i8;
1551 return VT.changeVectorElementTypeToInteger();
1554 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1555 /// the desired ByVal argument alignment.
1556 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1559 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1560 if (VTy->getBitWidth() == 128)
1562 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1563 unsigned EltAlign = 0;
1564 getMaxByValAlign(ATy->getElementType(), EltAlign);
1565 if (EltAlign > MaxAlign)
1566 MaxAlign = EltAlign;
1567 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1568 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1569 unsigned EltAlign = 0;
1570 getMaxByValAlign(STy->getElementType(i), EltAlign);
1571 if (EltAlign > MaxAlign)
1572 MaxAlign = EltAlign;
1579 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1580 /// function arguments in the caller parameter area. For X86, aggregates
1581 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1582 /// are at 4-byte boundaries.
1583 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1584 if (Subtarget->is64Bit()) {
1585 // Max of 8 and alignment of type.
1586 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1593 if (Subtarget->hasSSE1())
1594 getMaxByValAlign(Ty, Align);
1598 /// getOptimalMemOpType - Returns the target specific optimal type for load
1599 /// and store operations as a result of memset, memcpy, and memmove
1600 /// lowering. If DstAlign is zero that means it's safe to destination
1601 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1602 /// means there isn't a need to check it against alignment requirement,
1603 /// probably because the source does not need to be loaded. If 'IsMemset' is
1604 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1605 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1606 /// source is constant so it does not need to be loaded.
1607 /// It returns EVT::Other if the type should be determined using generic
1608 /// target-independent logic.
1610 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1611 unsigned DstAlign, unsigned SrcAlign,
1612 bool IsMemset, bool ZeroMemset,
1614 MachineFunction &MF) const {
1615 const Function *F = MF.getFunction();
1616 if ((!IsMemset || ZeroMemset) &&
1617 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1618 Attribute::NoImplicitFloat)) {
1620 (Subtarget->isUnalignedMemAccessFast() ||
1621 ((DstAlign == 0 || DstAlign >= 16) &&
1622 (SrcAlign == 0 || SrcAlign >= 16)))) {
1624 if (Subtarget->hasInt256())
1626 if (Subtarget->hasFp256())
1629 if (Subtarget->hasSSE2())
1631 if (Subtarget->hasSSE1())
1633 } else if (!MemcpyStrSrc && Size >= 8 &&
1634 !Subtarget->is64Bit() &&
1635 Subtarget->hasSSE2()) {
1636 // Do not use f64 to lower memcpy if source is string constant. It's
1637 // better to use i32 to avoid the loads.
1641 if (Subtarget->is64Bit() && Size >= 8)
1646 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1648 return X86ScalarSSEf32;
1649 else if (VT == MVT::f64)
1650 return X86ScalarSSEf64;
1655 X86TargetLowering::allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const {
1657 *Fast = Subtarget->isUnalignedMemAccessFast();
1661 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1662 /// current function. The returned value is a member of the
1663 /// MachineJumpTableInfo::JTEntryKind enum.
1664 unsigned X86TargetLowering::getJumpTableEncoding() const {
1665 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1667 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1668 Subtarget->isPICStyleGOT())
1669 return MachineJumpTableInfo::EK_Custom32;
1671 // Otherwise, use the normal jump table encoding heuristics.
1672 return TargetLowering::getJumpTableEncoding();
1676 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1677 const MachineBasicBlock *MBB,
1678 unsigned uid,MCContext &Ctx) const{
1679 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1680 Subtarget->isPICStyleGOT());
1681 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1683 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1684 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1687 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1689 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1690 SelectionDAG &DAG) const {
1691 if (!Subtarget->is64Bit())
1692 // This doesn't have SDLoc associated with it, but is not really the
1693 // same as a Register.
1694 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1698 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1699 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1701 const MCExpr *X86TargetLowering::
1702 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1703 MCContext &Ctx) const {
1704 // X86-64 uses RIP relative addressing based on the jump table label.
1705 if (Subtarget->isPICStyleRIPRel())
1706 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1708 // Otherwise, the reference is relative to the PIC base.
1709 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1712 // FIXME: Why this routine is here? Move to RegInfo!
1713 std::pair<const TargetRegisterClass*, uint8_t>
1714 X86TargetLowering::findRepresentativeClass(MVT VT) const{
1715 const TargetRegisterClass *RRC = 0;
1717 switch (VT.SimpleTy) {
1719 return TargetLowering::findRepresentativeClass(VT);
1720 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1721 RRC = Subtarget->is64Bit() ?
1722 (const TargetRegisterClass*)&X86::GR64RegClass :
1723 (const TargetRegisterClass*)&X86::GR32RegClass;
1726 RRC = &X86::VR64RegClass;
1728 case MVT::f32: case MVT::f64:
1729 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1730 case MVT::v4f32: case MVT::v2f64:
1731 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1733 RRC = &X86::VR128RegClass;
1736 return std::make_pair(RRC, Cost);
1739 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1740 unsigned &Offset) const {
1741 if (!Subtarget->isTargetLinux())
1744 if (Subtarget->is64Bit()) {
1745 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1747 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1759 //===----------------------------------------------------------------------===//
1760 // Return Value Calling Convention Implementation
1761 //===----------------------------------------------------------------------===//
1763 #include "X86GenCallingConv.inc"
1766 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1767 MachineFunction &MF, bool isVarArg,
1768 const SmallVectorImpl<ISD::OutputArg> &Outs,
1769 LLVMContext &Context) const {
1770 SmallVector<CCValAssign, 16> RVLocs;
1771 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1773 return CCInfo.CheckReturn(Outs, RetCC_X86);
1777 X86TargetLowering::LowerReturn(SDValue Chain,
1778 CallingConv::ID CallConv, bool isVarArg,
1779 const SmallVectorImpl<ISD::OutputArg> &Outs,
1780 const SmallVectorImpl<SDValue> &OutVals,
1781 SDLoc dl, SelectionDAG &DAG) const {
1782 MachineFunction &MF = DAG.getMachineFunction();
1783 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1785 SmallVector<CCValAssign, 16> RVLocs;
1786 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1787 RVLocs, *DAG.getContext());
1788 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1791 SmallVector<SDValue, 6> RetOps;
1792 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1793 // Operand #1 = Bytes To Pop
1794 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1797 // Copy the result values into the output registers.
1798 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1799 CCValAssign &VA = RVLocs[i];
1800 assert(VA.isRegLoc() && "Can only return in registers!");
1801 SDValue ValToCopy = OutVals[i];
1802 EVT ValVT = ValToCopy.getValueType();
1804 // Promote values to the appropriate types
1805 if (VA.getLocInfo() == CCValAssign::SExt)
1806 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
1807 else if (VA.getLocInfo() == CCValAssign::ZExt)
1808 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
1809 else if (VA.getLocInfo() == CCValAssign::AExt)
1810 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
1811 else if (VA.getLocInfo() == CCValAssign::BCvt)
1812 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
1814 // If this is x86-64, and we disabled SSE, we can't return FP values,
1815 // or SSE or MMX vectors.
1816 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1817 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1818 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
1819 report_fatal_error("SSE register return with SSE disabled");
1821 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1822 // llvm-gcc has never done it right and no one has noticed, so this
1823 // should be OK for now.
1824 if (ValVT == MVT::f64 &&
1825 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
1826 report_fatal_error("SSE2 register return with SSE2 disabled");
1828 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1829 // the RET instruction and handled by the FP Stackifier.
1830 if (VA.getLocReg() == X86::ST0 ||
1831 VA.getLocReg() == X86::ST1) {
1832 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1833 // change the value to the FP stack register class.
1834 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1835 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1836 RetOps.push_back(ValToCopy);
1837 // Don't emit a copytoreg.
1841 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1842 // which is returned in RAX / RDX.
1843 if (Subtarget->is64Bit()) {
1844 if (ValVT == MVT::x86mmx) {
1845 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1846 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1847 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1849 // If we don't have SSE2 available, convert to v4f32 so the generated
1850 // register is legal.
1851 if (!Subtarget->hasSSE2())
1852 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1857 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1858 Flag = Chain.getValue(1);
1859 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
1862 // The x86-64 ABIs require that for returning structs by value we copy
1863 // the sret argument into %rax/%eax (depending on ABI) for the return.
1864 // Win32 requires us to put the sret argument to %eax as well.
1865 // We saved the argument into a virtual register in the entry block,
1866 // so now we copy the value out and into %rax/%eax.
1867 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr() &&
1868 (Subtarget->is64Bit() || Subtarget->isTargetWindows())) {
1869 MachineFunction &MF = DAG.getMachineFunction();
1870 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1871 unsigned Reg = FuncInfo->getSRetReturnReg();
1873 "SRetReturnReg should have been set in LowerFormalArguments().");
1874 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1877 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
1878 X86::RAX : X86::EAX;
1879 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
1880 Flag = Chain.getValue(1);
1882 // RAX/EAX now acts like a return value.
1883 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
1886 RetOps[0] = Chain; // Update chain.
1888 // Add the flag if we have it.
1890 RetOps.push_back(Flag);
1892 return DAG.getNode(X86ISD::RET_FLAG, dl,
1893 MVT::Other, &RetOps[0], RetOps.size());
1896 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
1897 if (N->getNumValues() != 1)
1899 if (!N->hasNUsesOfValue(1, 0))
1902 SDValue TCChain = Chain;
1903 SDNode *Copy = *N->use_begin();
1904 if (Copy->getOpcode() == ISD::CopyToReg) {
1905 // If the copy has a glue operand, we conservatively assume it isn't safe to
1906 // perform a tail call.
1907 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
1909 TCChain = Copy->getOperand(0);
1910 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
1913 bool HasRet = false;
1914 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1916 if (UI->getOpcode() != X86ISD::RET_FLAG)
1929 X86TargetLowering::getTypeForExtArgOrReturn(MVT VT,
1930 ISD::NodeType ExtendKind) const {
1932 // TODO: Is this also valid on 32-bit?
1933 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
1934 ReturnMVT = MVT::i8;
1936 ReturnMVT = MVT::i32;
1938 MVT MinVT = getRegisterType(ReturnMVT);
1939 return VT.bitsLT(MinVT) ? MinVT : VT;
1942 /// LowerCallResult - Lower the result values of a call into the
1943 /// appropriate copies out of appropriate physical registers.
1946 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1947 CallingConv::ID CallConv, bool isVarArg,
1948 const SmallVectorImpl<ISD::InputArg> &Ins,
1949 SDLoc dl, SelectionDAG &DAG,
1950 SmallVectorImpl<SDValue> &InVals) const {
1952 // Assign locations to each value returned by this call.
1953 SmallVector<CCValAssign, 16> RVLocs;
1954 bool Is64Bit = Subtarget->is64Bit();
1955 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1956 getTargetMachine(), RVLocs, *DAG.getContext());
1957 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1959 // Copy all of the result registers out of their specified physreg.
1960 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
1961 CCValAssign &VA = RVLocs[i];
1962 EVT CopyVT = VA.getValVT();
1964 // If this is x86-64, and we disabled SSE, we can't return FP values
1965 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1966 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
1967 report_fatal_error("SSE register return with SSE disabled");
1972 // If this is a call to a function that returns an fp value on the floating
1973 // point stack, we must guarantee the value is popped from the stack, so
1974 // a CopyFromReg is not good enough - the copy instruction may be eliminated
1975 // if the return value is not used. We use the FpPOP_RETVAL instruction
1977 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {
1978 // If we prefer to use the value in xmm registers, copy it out as f80 and
1979 // use a truncate to move it from fp stack reg to xmm reg.
1980 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
1981 SDValue Ops[] = { Chain, InFlag };
1982 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT,
1983 MVT::Other, MVT::Glue, Ops), 1);
1984 Val = Chain.getValue(0);
1986 // Round the f80 to the right size, which also moves it to the appropriate
1988 if (CopyVT != VA.getValVT())
1989 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1990 // This truncation won't change the value.
1991 DAG.getIntPtrConstant(1));
1993 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1994 CopyVT, InFlag).getValue(1);
1995 Val = Chain.getValue(0);
1997 InFlag = Chain.getValue(2);
1998 InVals.push_back(Val);
2004 //===----------------------------------------------------------------------===//
2005 // C & StdCall & Fast Calling Convention implementation
2006 //===----------------------------------------------------------------------===//
2007 // StdCall calling convention seems to be standard for many Windows' API
2008 // routines and around. It differs from C calling convention just a little:
2009 // callee should clean up the stack, not caller. Symbols should be also
2010 // decorated in some fancy way :) It doesn't support any vector arguments.
2011 // For info on fast calling convention see Fast Calling Convention (tail call)
2012 // implementation LowerX86_32FastCCCallTo.
2014 /// CallIsStructReturn - Determines whether a call uses struct return
2016 enum StructReturnType {
2021 static StructReturnType
2022 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2024 return NotStructReturn;
2026 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2027 if (!Flags.isSRet())
2028 return NotStructReturn;
2029 if (Flags.isInReg())
2030 return RegStructReturn;
2031 return StackStructReturn;
2034 /// ArgsAreStructReturn - Determines whether a function uses struct
2035 /// return semantics.
2036 static StructReturnType
2037 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2039 return NotStructReturn;
2041 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2042 if (!Flags.isSRet())
2043 return NotStructReturn;
2044 if (Flags.isInReg())
2045 return RegStructReturn;
2046 return StackStructReturn;
2049 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2050 /// by "Src" to address "Dst" with size and alignment information specified by
2051 /// the specific parameter attribute. The copy will be passed as a byval
2052 /// function parameter.
2054 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2055 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2057 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2059 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2060 /*isVolatile*/false, /*AlwaysInline=*/true,
2061 MachinePointerInfo(), MachinePointerInfo());
2064 /// IsTailCallConvention - Return true if the calling convention is one that
2065 /// supports tail call optimization.
2066 static bool IsTailCallConvention(CallingConv::ID CC) {
2067 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2068 CC == CallingConv::HiPE);
2071 /// \brief Return true if the calling convention is a C calling convention.
2072 static bool IsCCallConvention(CallingConv::ID CC) {
2073 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2074 CC == CallingConv::X86_64_SysV);
2077 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2078 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2082 CallingConv::ID CalleeCC = CS.getCallingConv();
2083 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2089 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
2090 /// a tailcall target by changing its ABI.
2091 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2092 bool GuaranteedTailCallOpt) {
2093 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2097 X86TargetLowering::LowerMemArgument(SDValue Chain,
2098 CallingConv::ID CallConv,
2099 const SmallVectorImpl<ISD::InputArg> &Ins,
2100 SDLoc dl, SelectionDAG &DAG,
2101 const CCValAssign &VA,
2102 MachineFrameInfo *MFI,
2104 // Create the nodes corresponding to a load from this parameter slot.
2105 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2106 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv,
2107 getTargetMachine().Options.GuaranteedTailCallOpt);
2108 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2111 // If value is passed by pointer we have address passed instead of the value
2113 if (VA.getLocInfo() == CCValAssign::Indirect)
2114 ValVT = VA.getLocVT();
2116 ValVT = VA.getValVT();
2118 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2119 // changed with more analysis.
2120 // In case of tail call optimization mark all arguments mutable. Since they
2121 // could be overwritten by lowering of arguments in case of a tail call.
2122 if (Flags.isByVal()) {
2123 unsigned Bytes = Flags.getByValSize();
2124 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2125 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2126 return DAG.getFrameIndex(FI, getPointerTy());
2128 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2129 VA.getLocMemOffset(), isImmutable);
2130 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2131 return DAG.getLoad(ValVT, dl, Chain, FIN,
2132 MachinePointerInfo::getFixedStack(FI),
2133 false, false, false, 0);
2138 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2139 CallingConv::ID CallConv,
2141 const SmallVectorImpl<ISD::InputArg> &Ins,
2144 SmallVectorImpl<SDValue> &InVals)
2146 MachineFunction &MF = DAG.getMachineFunction();
2147 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2149 const Function* Fn = MF.getFunction();
2150 if (Fn->hasExternalLinkage() &&
2151 Subtarget->isTargetCygMing() &&
2152 Fn->getName() == "main")
2153 FuncInfo->setForceFramePointer(true);
2155 MachineFrameInfo *MFI = MF.getFrameInfo();
2156 bool Is64Bit = Subtarget->is64Bit();
2157 bool IsWindows = Subtarget->isTargetWindows();
2158 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2160 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2161 "Var args not supported with calling convention fastcc, ghc or hipe");
2163 // Assign locations to all of the incoming arguments.
2164 SmallVector<CCValAssign, 16> ArgLocs;
2165 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
2166 ArgLocs, *DAG.getContext());
2168 // Allocate shadow area for Win64
2170 CCInfo.AllocateStack(32, 8);
2172 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2174 unsigned LastVal = ~0U;
2176 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2177 CCValAssign &VA = ArgLocs[i];
2178 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2180 assert(VA.getValNo() != LastVal &&
2181 "Don't support value assigned to multiple locs yet");
2183 LastVal = VA.getValNo();
2185 if (VA.isRegLoc()) {
2186 EVT RegVT = VA.getLocVT();
2187 const TargetRegisterClass *RC;
2188 if (RegVT == MVT::i32)
2189 RC = &X86::GR32RegClass;
2190 else if (Is64Bit && RegVT == MVT::i64)
2191 RC = &X86::GR64RegClass;
2192 else if (RegVT == MVT::f32)
2193 RC = &X86::FR32RegClass;
2194 else if (RegVT == MVT::f64)
2195 RC = &X86::FR64RegClass;
2196 else if (RegVT.is512BitVector())
2197 RC = &X86::VR512RegClass;
2198 else if (RegVT.is256BitVector())
2199 RC = &X86::VR256RegClass;
2200 else if (RegVT.is128BitVector())
2201 RC = &X86::VR128RegClass;
2202 else if (RegVT == MVT::x86mmx)
2203 RC = &X86::VR64RegClass;
2204 else if (RegVT == MVT::v8i1)
2205 RC = &X86::VK8RegClass;
2206 else if (RegVT == MVT::v16i1)
2207 RC = &X86::VK16RegClass;
2209 llvm_unreachable("Unknown argument type!");
2211 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2212 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2214 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2215 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2217 if (VA.getLocInfo() == CCValAssign::SExt)
2218 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2219 DAG.getValueType(VA.getValVT()));
2220 else if (VA.getLocInfo() == CCValAssign::ZExt)
2221 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2222 DAG.getValueType(VA.getValVT()));
2223 else if (VA.getLocInfo() == CCValAssign::BCvt)
2224 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2226 if (VA.isExtInLoc()) {
2227 // Handle MMX values passed in XMM regs.
2228 if (RegVT.isVector())
2229 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2231 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2234 assert(VA.isMemLoc());
2235 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2238 // If value is passed via pointer - do a load.
2239 if (VA.getLocInfo() == CCValAssign::Indirect)
2240 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2241 MachinePointerInfo(), false, false, false, 0);
2243 InVals.push_back(ArgValue);
2246 // The x86-64 ABIs require that for returning structs by value we copy
2247 // the sret argument into %rax/%eax (depending on ABI) for the return.
2248 // Win32 requires us to put the sret argument to %eax as well.
2249 // Save the argument into a virtual register so that we can access it
2250 // from the return points.
2251 if (MF.getFunction()->hasStructRetAttr() &&
2252 (Subtarget->is64Bit() || Subtarget->isTargetWindows())) {
2253 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2254 unsigned Reg = FuncInfo->getSRetReturnReg();
2256 MVT PtrTy = getPointerTy();
2257 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2258 FuncInfo->setSRetReturnReg(Reg);
2260 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
2261 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2264 unsigned StackSize = CCInfo.getNextStackOffset();
2265 // Align stack specially for tail calls.
2266 if (FuncIsMadeTailCallSafe(CallConv,
2267 MF.getTarget().Options.GuaranteedTailCallOpt))
2268 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2270 // If the function takes variable number of arguments, make a frame index for
2271 // the start of the first vararg value... for expansion of llvm.va_start.
2273 if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2274 CallConv != CallingConv::X86_ThisCall)) {
2275 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
2278 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
2280 // FIXME: We should really autogenerate these arrays
2281 static const uint16_t GPR64ArgRegsWin64[] = {
2282 X86::RCX, X86::RDX, X86::R8, X86::R9
2284 static const uint16_t GPR64ArgRegs64Bit[] = {
2285 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2287 static const uint16_t XMMArgRegs64Bit[] = {
2288 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2289 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2291 const uint16_t *GPR64ArgRegs;
2292 unsigned NumXMMRegs = 0;
2295 // The XMM registers which might contain var arg parameters are shadowed
2296 // in their paired GPR. So we only need to save the GPR to their home
2298 TotalNumIntRegs = 4;
2299 GPR64ArgRegs = GPR64ArgRegsWin64;
2301 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
2302 GPR64ArgRegs = GPR64ArgRegs64Bit;
2304 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit,
2307 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
2310 bool NoImplicitFloatOps = Fn->getAttributes().
2311 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2312 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2313 "SSE register cannot be used when SSE is disabled!");
2314 assert(!(NumXMMRegs && MF.getTarget().Options.UseSoftFloat &&
2315 NoImplicitFloatOps) &&
2316 "SSE register cannot be used when SSE is disabled!");
2317 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2318 !Subtarget->hasSSE1())
2319 // Kernel mode asks for SSE to be disabled, so don't push them
2321 TotalNumXMMRegs = 0;
2324 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering();
2325 // Get to the caller-allocated home save location. Add 8 to account
2326 // for the return address.
2327 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2328 FuncInfo->setRegSaveFrameIndex(
2329 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2330 // Fixup to set vararg frame on shadow area (4 x i64).
2332 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2334 // For X86-64, if there are vararg parameters that are passed via
2335 // registers, then we must store them to their spots on the stack so
2336 // they may be loaded by deferencing the result of va_next.
2337 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2338 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
2339 FuncInfo->setRegSaveFrameIndex(
2340 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
2344 // Store the integer parameter registers.
2345 SmallVector<SDValue, 8> MemOps;
2346 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2348 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2349 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
2350 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2351 DAG.getIntPtrConstant(Offset));
2352 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
2353 &X86::GR64RegClass);
2354 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2356 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2357 MachinePointerInfo::getFixedStack(
2358 FuncInfo->getRegSaveFrameIndex(), Offset),
2360 MemOps.push_back(Store);
2364 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
2365 // Now store the XMM (fp + vector) parameter registers.
2366 SmallVector<SDValue, 11> SaveXMMOps;
2367 SaveXMMOps.push_back(Chain);
2369 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2370 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
2371 SaveXMMOps.push_back(ALVal);
2373 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2374 FuncInfo->getRegSaveFrameIndex()));
2375 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2376 FuncInfo->getVarArgsFPOffset()));
2378 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
2379 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs],
2380 &X86::VR128RegClass);
2381 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
2382 SaveXMMOps.push_back(Val);
2384 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2386 &SaveXMMOps[0], SaveXMMOps.size()));
2389 if (!MemOps.empty())
2390 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2391 &MemOps[0], MemOps.size());
2395 // Some CCs need callee pop.
2396 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2397 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2398 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2400 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2401 // If this is an sret function, the return should pop the hidden pointer.
2402 if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows &&
2403 argsAreStructReturn(Ins) == StackStructReturn)
2404 FuncInfo->setBytesToPopOnReturn(4);
2408 // RegSaveFrameIndex is X86-64 only.
2409 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2410 if (CallConv == CallingConv::X86_FastCall ||
2411 CallConv == CallingConv::X86_ThisCall)
2412 // fastcc functions can't have varargs.
2413 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2416 FuncInfo->setArgumentStackSize(StackSize);
2422 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2423 SDValue StackPtr, SDValue Arg,
2424 SDLoc dl, SelectionDAG &DAG,
2425 const CCValAssign &VA,
2426 ISD::ArgFlagsTy Flags) const {
2427 unsigned LocMemOffset = VA.getLocMemOffset();
2428 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2429 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2430 if (Flags.isByVal())
2431 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2433 return DAG.getStore(Chain, dl, Arg, PtrOff,
2434 MachinePointerInfo::getStack(LocMemOffset),
2438 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2439 /// optimization is performed and it is required.
2441 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2442 SDValue &OutRetAddr, SDValue Chain,
2443 bool IsTailCall, bool Is64Bit,
2444 int FPDiff, SDLoc dl) const {
2445 // Adjust the Return address stack slot.
2446 EVT VT = getPointerTy();
2447 OutRetAddr = getReturnAddressFrameIndex(DAG);
2449 // Load the "old" Return address.
2450 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2451 false, false, false, 0);
2452 return SDValue(OutRetAddr.getNode(), 1);
2455 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2456 /// optimization is performed and it is required (FPDiff!=0).
2458 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
2459 SDValue Chain, SDValue RetAddrFrIdx, EVT PtrVT,
2460 unsigned SlotSize, int FPDiff, SDLoc dl) {
2461 // Store the return address to the appropriate stack slot.
2462 if (!FPDiff) return Chain;
2463 // Calculate the new stack slot for the return address.
2464 int NewReturnAddrFI =
2465 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2467 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2468 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2469 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2475 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2476 SmallVectorImpl<SDValue> &InVals) const {
2477 SelectionDAG &DAG = CLI.DAG;
2479 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2480 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2481 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2482 SDValue Chain = CLI.Chain;
2483 SDValue Callee = CLI.Callee;
2484 CallingConv::ID CallConv = CLI.CallConv;
2485 bool &isTailCall = CLI.IsTailCall;
2486 bool isVarArg = CLI.IsVarArg;
2488 MachineFunction &MF = DAG.getMachineFunction();
2489 bool Is64Bit = Subtarget->is64Bit();
2490 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2491 bool IsWindows = Subtarget->isTargetWindows();
2492 StructReturnType SR = callIsStructReturn(Outs);
2493 bool IsSibcall = false;
2495 if (MF.getTarget().Options.DisableTailCalls)
2499 // Check if it's really possible to do a tail call.
2500 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2501 isVarArg, SR != NotStructReturn,
2502 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2503 Outs, OutVals, Ins, DAG);
2505 // Sibcalls are automatically detected tailcalls which do not require
2507 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2514 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2515 "Var args not supported with calling convention fastcc, ghc or hipe");
2517 // Analyze operands of the call, assigning locations to each operand.
2518 SmallVector<CCValAssign, 16> ArgLocs;
2519 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
2520 ArgLocs, *DAG.getContext());
2522 // Allocate shadow area for Win64
2524 CCInfo.AllocateStack(32, 8);
2526 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2528 // Get a count of how many bytes are to be pushed on the stack.
2529 unsigned NumBytes = CCInfo.getNextStackOffset();
2531 // This is a sibcall. The memory operands are available in caller's
2532 // own caller's stack.
2534 else if (getTargetMachine().Options.GuaranteedTailCallOpt &&
2535 IsTailCallConvention(CallConv))
2536 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2539 if (isTailCall && !IsSibcall) {
2540 // Lower arguments at fp - stackoffset + fpdiff.
2541 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2542 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2544 FPDiff = NumBytesCallerPushed - NumBytes;
2546 // Set the delta of movement of the returnaddr stackslot.
2547 // But only set if delta is greater than previous delta.
2548 if (FPDiff < X86Info->getTCReturnAddrDelta())
2549 X86Info->setTCReturnAddrDelta(FPDiff);
2553 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
2556 SDValue RetAddrFrIdx;
2557 // Load return address for tail calls.
2558 if (isTailCall && FPDiff)
2559 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2560 Is64Bit, FPDiff, dl);
2562 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2563 SmallVector<SDValue, 8> MemOpChains;
2566 // Walk the register/memloc assignments, inserting copies/loads. In the case
2567 // of tail call optimization arguments are handle later.
2568 const X86RegisterInfo *RegInfo =
2569 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
2570 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2571 CCValAssign &VA = ArgLocs[i];
2572 EVT RegVT = VA.getLocVT();
2573 SDValue Arg = OutVals[i];
2574 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2575 bool isByVal = Flags.isByVal();
2577 // Promote the value if needed.
2578 switch (VA.getLocInfo()) {
2579 default: llvm_unreachable("Unknown loc info!");
2580 case CCValAssign::Full: break;
2581 case CCValAssign::SExt:
2582 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2584 case CCValAssign::ZExt:
2585 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2587 case CCValAssign::AExt:
2588 if (RegVT.is128BitVector()) {
2589 // Special case: passing MMX values in XMM registers.
2590 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2591 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2592 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2594 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2596 case CCValAssign::BCvt:
2597 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2599 case CCValAssign::Indirect: {
2600 // Store the argument.
2601 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2602 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2603 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2604 MachinePointerInfo::getFixedStack(FI),
2611 if (VA.isRegLoc()) {
2612 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2613 if (isVarArg && IsWin64) {
2614 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2615 // shadow reg if callee is a varargs function.
2616 unsigned ShadowReg = 0;
2617 switch (VA.getLocReg()) {
2618 case X86::XMM0: ShadowReg = X86::RCX; break;
2619 case X86::XMM1: ShadowReg = X86::RDX; break;
2620 case X86::XMM2: ShadowReg = X86::R8; break;
2621 case X86::XMM3: ShadowReg = X86::R9; break;
2624 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2626 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2627 assert(VA.isMemLoc());
2628 if (StackPtr.getNode() == 0)
2629 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2631 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2632 dl, DAG, VA, Flags));
2636 if (!MemOpChains.empty())
2637 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2638 &MemOpChains[0], MemOpChains.size());
2640 if (Subtarget->isPICStyleGOT()) {
2641 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2644 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2645 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2647 // If we are tail calling and generating PIC/GOT style code load the
2648 // address of the callee into ECX. The value in ecx is used as target of
2649 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2650 // for tail calls on PIC/GOT architectures. Normally we would just put the
2651 // address of GOT into ebx and then call target@PLT. But for tail calls
2652 // ebx would be restored (since ebx is callee saved) before jumping to the
2655 // Note: The actual moving to ECX is done further down.
2656 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2657 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2658 !G->getGlobal()->hasProtectedVisibility())
2659 Callee = LowerGlobalAddress(Callee, DAG);
2660 else if (isa<ExternalSymbolSDNode>(Callee))
2661 Callee = LowerExternalSymbol(Callee, DAG);
2665 if (Is64Bit && isVarArg && !IsWin64) {
2666 // From AMD64 ABI document:
2667 // For calls that may call functions that use varargs or stdargs
2668 // (prototype-less calls or calls to functions containing ellipsis (...) in
2669 // the declaration) %al is used as hidden argument to specify the number
2670 // of SSE registers used. The contents of %al do not need to match exactly
2671 // the number of registers, but must be an ubound on the number of SSE
2672 // registers used and is in the range 0 - 8 inclusive.
2674 // Count the number of XMM registers allocated.
2675 static const uint16_t XMMArgRegs[] = {
2676 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2677 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2679 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2680 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2681 && "SSE registers cannot be used when SSE is disabled");
2683 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2684 DAG.getConstant(NumXMMRegs, MVT::i8)));
2687 // For tail calls lower the arguments to the 'real' stack slot.
2689 // Force all the incoming stack arguments to be loaded from the stack
2690 // before any new outgoing arguments are stored to the stack, because the
2691 // outgoing stack slots may alias the incoming argument stack slots, and
2692 // the alias isn't otherwise explicit. This is slightly more conservative
2693 // than necessary, because it means that each store effectively depends
2694 // on every argument instead of just those arguments it would clobber.
2695 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2697 SmallVector<SDValue, 8> MemOpChains2;
2700 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2701 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2702 CCValAssign &VA = ArgLocs[i];
2705 assert(VA.isMemLoc());
2706 SDValue Arg = OutVals[i];
2707 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2708 // Create frame index.
2709 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2710 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2711 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2712 FIN = DAG.getFrameIndex(FI, getPointerTy());
2714 if (Flags.isByVal()) {
2715 // Copy relative to framepointer.
2716 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2717 if (StackPtr.getNode() == 0)
2718 StackPtr = DAG.getCopyFromReg(Chain, dl,
2719 RegInfo->getStackRegister(),
2721 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2723 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2727 // Store relative to framepointer.
2728 MemOpChains2.push_back(
2729 DAG.getStore(ArgChain, dl, Arg, FIN,
2730 MachinePointerInfo::getFixedStack(FI),
2736 if (!MemOpChains2.empty())
2737 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2738 &MemOpChains2[0], MemOpChains2.size());
2740 // Store the return address to the appropriate stack slot.
2741 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
2742 getPointerTy(), RegInfo->getSlotSize(),
2746 // Build a sequence of copy-to-reg nodes chained together with token chain
2747 // and flag operands which copy the outgoing args into registers.
2749 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2750 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2751 RegsToPass[i].second, InFlag);
2752 InFlag = Chain.getValue(1);
2755 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2756 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2757 // In the 64-bit large code model, we have to make all calls
2758 // through a register, since the call instruction's 32-bit
2759 // pc-relative offset may not be large enough to hold the whole
2761 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2762 // If the callee is a GlobalAddress node (quite common, every direct call
2763 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2766 // We should use extra load for direct calls to dllimported functions in
2768 const GlobalValue *GV = G->getGlobal();
2769 if (!GV->hasDLLImportLinkage()) {
2770 unsigned char OpFlags = 0;
2771 bool ExtraLoad = false;
2772 unsigned WrapperKind = ISD::DELETED_NODE;
2774 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2775 // external symbols most go through the PLT in PIC mode. If the symbol
2776 // has hidden or protected visibility, or if it is static or local, then
2777 // we don't need to use the PLT - we can directly call it.
2778 if (Subtarget->isTargetELF() &&
2779 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2780 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2781 OpFlags = X86II::MO_PLT;
2782 } else if (Subtarget->isPICStyleStubAny() &&
2783 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2784 (!Subtarget->getTargetTriple().isMacOSX() ||
2785 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2786 // PC-relative references to external symbols should go through $stub,
2787 // unless we're building with the leopard linker or later, which
2788 // automatically synthesizes these stubs.
2789 OpFlags = X86II::MO_DARWIN_STUB;
2790 } else if (Subtarget->isPICStyleRIPRel() &&
2791 isa<Function>(GV) &&
2792 cast<Function>(GV)->getAttributes().
2793 hasAttribute(AttributeSet::FunctionIndex,
2794 Attribute::NonLazyBind)) {
2795 // If the function is marked as non-lazy, generate an indirect call
2796 // which loads from the GOT directly. This avoids runtime overhead
2797 // at the cost of eager binding (and one extra byte of encoding).
2798 OpFlags = X86II::MO_GOTPCREL;
2799 WrapperKind = X86ISD::WrapperRIP;
2803 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2804 G->getOffset(), OpFlags);
2806 // Add a wrapper if needed.
2807 if (WrapperKind != ISD::DELETED_NODE)
2808 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
2809 // Add extra indirection if needed.
2811 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
2812 MachinePointerInfo::getGOT(),
2813 false, false, false, 0);
2815 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2816 unsigned char OpFlags = 0;
2818 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
2819 // external symbols should go through the PLT.
2820 if (Subtarget->isTargetELF() &&
2821 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2822 OpFlags = X86II::MO_PLT;
2823 } else if (Subtarget->isPICStyleStubAny() &&
2824 (!Subtarget->getTargetTriple().isMacOSX() ||
2825 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2826 // PC-relative references to external symbols should go through $stub,
2827 // unless we're building with the leopard linker or later, which
2828 // automatically synthesizes these stubs.
2829 OpFlags = X86II::MO_DARWIN_STUB;
2832 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2836 // Returns a chain & a flag for retval copy to use.
2837 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2838 SmallVector<SDValue, 8> Ops;
2840 if (!IsSibcall && isTailCall) {
2841 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2842 DAG.getIntPtrConstant(0, true), InFlag, dl);
2843 InFlag = Chain.getValue(1);
2846 Ops.push_back(Chain);
2847 Ops.push_back(Callee);
2850 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2852 // Add argument registers to the end of the list so that they are known live
2854 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2855 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2856 RegsToPass[i].second.getValueType()));
2858 // Add a register mask operand representing the call-preserved registers.
2859 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2860 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
2861 assert(Mask && "Missing call preserved mask for calling convention");
2862 Ops.push_back(DAG.getRegisterMask(Mask));
2864 if (InFlag.getNode())
2865 Ops.push_back(InFlag);
2869 //// If this is the first return lowered for this function, add the regs
2870 //// to the liveout set for the function.
2871 // This isn't right, although it's probably harmless on x86; liveouts
2872 // should be computed from returns not tail calls. Consider a void
2873 // function making a tail call to a function returning int.
2874 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size());
2877 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2878 InFlag = Chain.getValue(1);
2880 // Create the CALLSEQ_END node.
2881 unsigned NumBytesForCalleeToPush;
2882 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2883 getTargetMachine().Options.GuaranteedTailCallOpt))
2884 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2885 else if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows &&
2886 SR == StackStructReturn)
2887 // If this is a call to a struct-return function, the callee
2888 // pops the hidden struct pointer, so we have to push it back.
2889 // This is common for Darwin/X86, Linux & Mingw32 targets.
2890 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
2891 NumBytesForCalleeToPush = 4;
2893 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2895 // Returns a flag for retval copy to use.
2897 Chain = DAG.getCALLSEQ_END(Chain,
2898 DAG.getIntPtrConstant(NumBytes, true),
2899 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2902 InFlag = Chain.getValue(1);
2905 // Handle result values, copying them out of physregs into vregs that we
2907 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2908 Ins, dl, DAG, InVals);
2911 //===----------------------------------------------------------------------===//
2912 // Fast Calling Convention (tail call) implementation
2913 //===----------------------------------------------------------------------===//
2915 // Like std call, callee cleans arguments, convention except that ECX is
2916 // reserved for storing the tail called function address. Only 2 registers are
2917 // free for argument passing (inreg). Tail call optimization is performed
2919 // * tailcallopt is enabled
2920 // * caller/callee are fastcc
2921 // On X86_64 architecture with GOT-style position independent code only local
2922 // (within module) calls are supported at the moment.
2923 // To keep the stack aligned according to platform abi the function
2924 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2925 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2926 // If a tail called function callee has more arguments than the caller the
2927 // caller needs to make sure that there is room to move the RETADDR to. This is
2928 // achieved by reserving an area the size of the argument delta right after the
2929 // original REtADDR, but before the saved framepointer or the spilled registers
2930 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2942 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2943 /// for a 16 byte align requirement.
2945 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2946 SelectionDAG& DAG) const {
2947 MachineFunction &MF = DAG.getMachineFunction();
2948 const TargetMachine &TM = MF.getTarget();
2949 const X86RegisterInfo *RegInfo =
2950 static_cast<const X86RegisterInfo*>(TM.getRegisterInfo());
2951 const TargetFrameLowering &TFI = *TM.getFrameLowering();
2952 unsigned StackAlignment = TFI.getStackAlignment();
2953 uint64_t AlignMask = StackAlignment - 1;
2954 int64_t Offset = StackSize;
2955 unsigned SlotSize = RegInfo->getSlotSize();
2956 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2957 // Number smaller than 12 so just add the difference.
2958 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2960 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2961 Offset = ((~AlignMask) & Offset) + StackAlignment +
2962 (StackAlignment-SlotSize);
2967 /// MatchingStackOffset - Return true if the given stack call argument is
2968 /// already available in the same position (relatively) of the caller's
2969 /// incoming argument stack.
2971 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2972 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
2973 const X86InstrInfo *TII) {
2974 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
2976 if (Arg.getOpcode() == ISD::CopyFromReg) {
2977 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2978 if (!TargetRegisterInfo::isVirtualRegister(VR))
2980 MachineInstr *Def = MRI->getVRegDef(VR);
2983 if (!Flags.isByVal()) {
2984 if (!TII->isLoadFromStackSlot(Def, FI))
2987 unsigned Opcode = Def->getOpcode();
2988 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
2989 Def->getOperand(1).isFI()) {
2990 FI = Def->getOperand(1).getIndex();
2991 Bytes = Flags.getByValSize();
2995 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2996 if (Flags.isByVal())
2997 // ByVal argument is passed in as a pointer but it's now being
2998 // dereferenced. e.g.
2999 // define @foo(%struct.X* %A) {
3000 // tail call @bar(%struct.X* byval %A)
3003 SDValue Ptr = Ld->getBasePtr();
3004 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3007 FI = FINode->getIndex();
3008 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3009 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3010 FI = FINode->getIndex();
3011 Bytes = Flags.getByValSize();
3015 assert(FI != INT_MAX);
3016 if (!MFI->isFixedObjectIndex(FI))
3018 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3021 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3022 /// for tail call optimization. Targets which want to do tail call
3023 /// optimization should implement this function.
3025 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3026 CallingConv::ID CalleeCC,
3028 bool isCalleeStructRet,
3029 bool isCallerStructRet,
3031 const SmallVectorImpl<ISD::OutputArg> &Outs,
3032 const SmallVectorImpl<SDValue> &OutVals,
3033 const SmallVectorImpl<ISD::InputArg> &Ins,
3034 SelectionDAG &DAG) const {
3035 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3038 // If -tailcallopt is specified, make fastcc functions tail-callable.
3039 const MachineFunction &MF = DAG.getMachineFunction();
3040 const Function *CallerF = MF.getFunction();
3042 // If the function return type is x86_fp80 and the callee return type is not,
3043 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3044 // perform a tailcall optimization here.
3045 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3048 CallingConv::ID CallerCC = CallerF->getCallingConv();
3049 bool CCMatch = CallerCC == CalleeCC;
3050 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3051 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3053 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
3054 if (IsTailCallConvention(CalleeCC) && CCMatch)
3059 // Look for obvious safe cases to perform tail call optimization that do not
3060 // require ABI changes. This is what gcc calls sibcall.
3062 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3063 // emit a special epilogue.
3064 const X86RegisterInfo *RegInfo =
3065 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
3066 if (RegInfo->needsStackRealignment(MF))
3069 // Also avoid sibcall optimization if either caller or callee uses struct
3070 // return semantics.
3071 if (isCalleeStructRet || isCallerStructRet)
3074 // An stdcall caller is expected to clean up its arguments; the callee
3075 // isn't going to do that.
3076 if (!CCMatch && CallerCC == CallingConv::X86_StdCall)
3079 // Do not sibcall optimize vararg calls unless all arguments are passed via
3081 if (isVarArg && !Outs.empty()) {
3083 // Optimizing for varargs on Win64 is unlikely to be safe without
3084 // additional testing.
3085 if (IsCalleeWin64 || IsCallerWin64)
3088 SmallVector<CCValAssign, 16> ArgLocs;
3089 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
3090 getTargetMachine(), ArgLocs, *DAG.getContext());
3092 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3093 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3094 if (!ArgLocs[i].isRegLoc())
3098 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3099 // stack. Therefore, if it's not used by the call it is not safe to optimize
3100 // this into a sibcall.
3101 bool Unused = false;
3102 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3109 SmallVector<CCValAssign, 16> RVLocs;
3110 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(),
3111 getTargetMachine(), RVLocs, *DAG.getContext());
3112 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3113 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3114 CCValAssign &VA = RVLocs[i];
3115 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
3120 // If the calling conventions do not match, then we'd better make sure the
3121 // results are returned in the same way as what the caller expects.
3123 SmallVector<CCValAssign, 16> RVLocs1;
3124 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
3125 getTargetMachine(), RVLocs1, *DAG.getContext());
3126 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3128 SmallVector<CCValAssign, 16> RVLocs2;
3129 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
3130 getTargetMachine(), RVLocs2, *DAG.getContext());
3131 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3133 if (RVLocs1.size() != RVLocs2.size())
3135 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3136 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3138 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3140 if (RVLocs1[i].isRegLoc()) {
3141 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3144 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3150 // If the callee takes no arguments then go on to check the results of the
3152 if (!Outs.empty()) {
3153 // Check if stack adjustment is needed. For now, do not do this if any
3154 // argument is passed on the stack.
3155 SmallVector<CCValAssign, 16> ArgLocs;
3156 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
3157 getTargetMachine(), ArgLocs, *DAG.getContext());
3159 // Allocate shadow area for Win64
3161 CCInfo.AllocateStack(32, 8);
3163 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3164 if (CCInfo.getNextStackOffset()) {
3165 MachineFunction &MF = DAG.getMachineFunction();
3166 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3169 // Check if the arguments are already laid out in the right way as
3170 // the caller's fixed stack objects.
3171 MachineFrameInfo *MFI = MF.getFrameInfo();
3172 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3173 const X86InstrInfo *TII =
3174 ((const X86TargetMachine&)getTargetMachine()).getInstrInfo();
3175 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3176 CCValAssign &VA = ArgLocs[i];
3177 SDValue Arg = OutVals[i];
3178 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3179 if (VA.getLocInfo() == CCValAssign::Indirect)
3181 if (!VA.isRegLoc()) {
3182 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3189 // If the tailcall address may be in a register, then make sure it's
3190 // possible to register allocate for it. In 32-bit, the call address can
3191 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3192 // callee-saved registers are restored. These happen to be the same
3193 // registers used to pass 'inreg' arguments so watch out for those.
3194 if (!Subtarget->is64Bit() &&
3195 ((!isa<GlobalAddressSDNode>(Callee) &&
3196 !isa<ExternalSymbolSDNode>(Callee)) ||
3197 getTargetMachine().getRelocationModel() == Reloc::PIC_)) {
3198 unsigned NumInRegs = 0;
3199 // In PIC we need an extra register to formulate the address computation
3201 unsigned MaxInRegs =
3202 (getTargetMachine().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3204 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3205 CCValAssign &VA = ArgLocs[i];
3208 unsigned Reg = VA.getLocReg();
3211 case X86::EAX: case X86::EDX: case X86::ECX:
3212 if (++NumInRegs == MaxInRegs)
3224 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3225 const TargetLibraryInfo *libInfo) const {
3226 return X86::createFastISel(funcInfo, libInfo);
3229 //===----------------------------------------------------------------------===//
3230 // Other Lowering Hooks
3231 //===----------------------------------------------------------------------===//
3233 static bool MayFoldLoad(SDValue Op) {
3234 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3237 static bool MayFoldIntoStore(SDValue Op) {
3238 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3241 static bool isTargetShuffle(unsigned Opcode) {
3243 default: return false;
3244 case X86ISD::PSHUFD:
3245 case X86ISD::PSHUFHW:
3246 case X86ISD::PSHUFLW:
3248 case X86ISD::PALIGNR:
3249 case X86ISD::MOVLHPS:
3250 case X86ISD::MOVLHPD:
3251 case X86ISD::MOVHLPS:
3252 case X86ISD::MOVLPS:
3253 case X86ISD::MOVLPD:
3254 case X86ISD::MOVSHDUP:
3255 case X86ISD::MOVSLDUP:
3256 case X86ISD::MOVDDUP:
3259 case X86ISD::UNPCKL:
3260 case X86ISD::UNPCKH:
3261 case X86ISD::VPERMILP:
3262 case X86ISD::VPERM2X128:
3263 case X86ISD::VPERMI:
3268 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3269 SDValue V1, SelectionDAG &DAG) {
3271 default: llvm_unreachable("Unknown x86 shuffle node");
3272 case X86ISD::MOVSHDUP:
3273 case X86ISD::MOVSLDUP:
3274 case X86ISD::MOVDDUP:
3275 return DAG.getNode(Opc, dl, VT, V1);
3279 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3280 SDValue V1, unsigned TargetMask,
3281 SelectionDAG &DAG) {
3283 default: llvm_unreachable("Unknown x86 shuffle node");
3284 case X86ISD::PSHUFD:
3285 case X86ISD::PSHUFHW:
3286 case X86ISD::PSHUFLW:
3287 case X86ISD::VPERMILP:
3288 case X86ISD::VPERMI:
3289 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3293 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3294 SDValue V1, SDValue V2, unsigned TargetMask,
3295 SelectionDAG &DAG) {
3297 default: llvm_unreachable("Unknown x86 shuffle node");
3298 case X86ISD::PALIGNR:
3300 case X86ISD::VPERM2X128:
3301 return DAG.getNode(Opc, dl, VT, V1, V2,
3302 DAG.getConstant(TargetMask, MVT::i8));
3306 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3307 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3309 default: llvm_unreachable("Unknown x86 shuffle node");
3310 case X86ISD::MOVLHPS:
3311 case X86ISD::MOVLHPD:
3312 case X86ISD::MOVHLPS:
3313 case X86ISD::MOVLPS:
3314 case X86ISD::MOVLPD:
3317 case X86ISD::UNPCKL:
3318 case X86ISD::UNPCKH:
3319 return DAG.getNode(Opc, dl, VT, V1, V2);
3323 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3324 MachineFunction &MF = DAG.getMachineFunction();
3325 const X86RegisterInfo *RegInfo =
3326 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
3327 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3328 int ReturnAddrIndex = FuncInfo->getRAIndex();
3330 if (ReturnAddrIndex == 0) {
3331 // Set up a frame object for the return address.
3332 unsigned SlotSize = RegInfo->getSlotSize();
3333 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3336 FuncInfo->setRAIndex(ReturnAddrIndex);
3339 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3342 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3343 bool hasSymbolicDisplacement) {
3344 // Offset should fit into 32 bit immediate field.
3345 if (!isInt<32>(Offset))
3348 // If we don't have a symbolic displacement - we don't have any extra
3350 if (!hasSymbolicDisplacement)
3353 // FIXME: Some tweaks might be needed for medium code model.
3354 if (M != CodeModel::Small && M != CodeModel::Kernel)
3357 // For small code model we assume that latest object is 16MB before end of 31
3358 // bits boundary. We may also accept pretty large negative constants knowing
3359 // that all objects are in the positive half of address space.
3360 if (M == CodeModel::Small && Offset < 16*1024*1024)
3363 // For kernel code model we know that all object resist in the negative half
3364 // of 32bits address space. We may not accept negative offsets, since they may
3365 // be just off and we may accept pretty large positive ones.
3366 if (M == CodeModel::Kernel && Offset > 0)
3372 /// isCalleePop - Determines whether the callee is required to pop its
3373 /// own arguments. Callee pop is necessary to support tail calls.
3374 bool X86::isCalleePop(CallingConv::ID CallingConv,
3375 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3379 switch (CallingConv) {
3382 case CallingConv::X86_StdCall:
3384 case CallingConv::X86_FastCall:
3386 case CallingConv::X86_ThisCall:
3388 case CallingConv::Fast:
3390 case CallingConv::GHC:
3392 case CallingConv::HiPE:
3397 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3398 /// specific condition code, returning the condition code and the LHS/RHS of the
3399 /// comparison to make.
3400 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3401 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3403 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3404 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3405 // X > -1 -> X == 0, jump !sign.
3406 RHS = DAG.getConstant(0, RHS.getValueType());
3407 return X86::COND_NS;
3409 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3410 // X < 0 -> X == 0, jump on sign.
3413 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3415 RHS = DAG.getConstant(0, RHS.getValueType());
3416 return X86::COND_LE;
3420 switch (SetCCOpcode) {
3421 default: llvm_unreachable("Invalid integer condition!");
3422 case ISD::SETEQ: return X86::COND_E;
3423 case ISD::SETGT: return X86::COND_G;
3424 case ISD::SETGE: return X86::COND_GE;
3425 case ISD::SETLT: return X86::COND_L;
3426 case ISD::SETLE: return X86::COND_LE;
3427 case ISD::SETNE: return X86::COND_NE;
3428 case ISD::SETULT: return X86::COND_B;
3429 case ISD::SETUGT: return X86::COND_A;
3430 case ISD::SETULE: return X86::COND_BE;
3431 case ISD::SETUGE: return X86::COND_AE;
3435 // First determine if it is required or is profitable to flip the operands.
3437 // If LHS is a foldable load, but RHS is not, flip the condition.
3438 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3439 !ISD::isNON_EXTLoad(RHS.getNode())) {
3440 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3441 std::swap(LHS, RHS);
3444 switch (SetCCOpcode) {
3450 std::swap(LHS, RHS);
3454 // On a floating point condition, the flags are set as follows:
3456 // 0 | 0 | 0 | X > Y
3457 // 0 | 0 | 1 | X < Y
3458 // 1 | 0 | 0 | X == Y
3459 // 1 | 1 | 1 | unordered
3460 switch (SetCCOpcode) {
3461 default: llvm_unreachable("Condcode should be pre-legalized away");
3463 case ISD::SETEQ: return X86::COND_E;
3464 case ISD::SETOLT: // flipped
3466 case ISD::SETGT: return X86::COND_A;
3467 case ISD::SETOLE: // flipped
3469 case ISD::SETGE: return X86::COND_AE;
3470 case ISD::SETUGT: // flipped
3472 case ISD::SETLT: return X86::COND_B;
3473 case ISD::SETUGE: // flipped
3475 case ISD::SETLE: return X86::COND_BE;
3477 case ISD::SETNE: return X86::COND_NE;
3478 case ISD::SETUO: return X86::COND_P;
3479 case ISD::SETO: return X86::COND_NP;
3481 case ISD::SETUNE: return X86::COND_INVALID;
3485 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3486 /// code. Current x86 isa includes the following FP cmov instructions:
3487 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3488 static bool hasFPCMov(unsigned X86CC) {
3504 /// isFPImmLegal - Returns true if the target can instruction select the
3505 /// specified FP immediate natively. If false, the legalizer will
3506 /// materialize the FP immediate as a load from a constant pool.
3507 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3508 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3509 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3515 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3516 /// the specified range (L, H].
3517 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3518 return (Val < 0) || (Val >= Low && Val < Hi);
3521 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3522 /// specified value.
3523 static bool isUndefOrEqual(int Val, int CmpVal) {
3524 return (Val < 0 || Val == CmpVal);
3527 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3528 /// from position Pos and ending in Pos+Size, falls within the specified
3529 /// sequential range (L, L+Pos]. or is undef.
3530 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3531 unsigned Pos, unsigned Size, int Low) {
3532 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3533 if (!isUndefOrEqual(Mask[i], Low))
3538 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3539 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3540 /// the second operand.
3541 static bool isPSHUFDMask(ArrayRef<int> Mask, MVT VT) {
3542 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3543 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3544 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3545 return (Mask[0] < 2 && Mask[1] < 2);
3549 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3550 /// is suitable for input to PSHUFHW.
3551 static bool isPSHUFHWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3552 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3555 // Lower quadword copied in order or undef.
3556 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3559 // Upper quadword shuffled.
3560 for (unsigned i = 4; i != 8; ++i)
3561 if (!isUndefOrInRange(Mask[i], 4, 8))
3564 if (VT == MVT::v16i16) {
3565 // Lower quadword copied in order or undef.
3566 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3569 // Upper quadword shuffled.
3570 for (unsigned i = 12; i != 16; ++i)
3571 if (!isUndefOrInRange(Mask[i], 12, 16))
3578 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3579 /// is suitable for input to PSHUFLW.
3580 static bool isPSHUFLWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3581 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3584 // Upper quadword copied in order.
3585 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3588 // Lower quadword shuffled.
3589 for (unsigned i = 0; i != 4; ++i)
3590 if (!isUndefOrInRange(Mask[i], 0, 4))
3593 if (VT == MVT::v16i16) {
3594 // Upper quadword copied in order.
3595 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3598 // Lower quadword shuffled.
3599 for (unsigned i = 8; i != 12; ++i)
3600 if (!isUndefOrInRange(Mask[i], 8, 12))
3607 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
3608 /// is suitable for input to PALIGNR.
3609 static bool isPALIGNRMask(ArrayRef<int> Mask, MVT VT,
3610 const X86Subtarget *Subtarget) {
3611 if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
3612 (VT.is256BitVector() && !Subtarget->hasInt256()))
3615 unsigned NumElts = VT.getVectorNumElements();
3616 unsigned NumLanes = VT.is512BitVector() ? 1: VT.getSizeInBits()/128;
3617 unsigned NumLaneElts = NumElts/NumLanes;
3619 // Do not handle 64-bit element shuffles with palignr.
3620 if (NumLaneElts == 2)
3623 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3625 for (i = 0; i != NumLaneElts; ++i) {
3630 // Lane is all undef, go to next lane
3631 if (i == NumLaneElts)
3634 int Start = Mask[i+l];
3636 // Make sure its in this lane in one of the sources
3637 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3638 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3641 // If not lane 0, then we must match lane 0
3642 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3645 // Correct second source to be contiguous with first source
3646 if (Start >= (int)NumElts)
3647 Start -= NumElts - NumLaneElts;
3649 // Make sure we're shifting in the right direction.
3650 if (Start <= (int)(i+l))
3655 // Check the rest of the elements to see if they are consecutive.
3656 for (++i; i != NumLaneElts; ++i) {
3657 int Idx = Mask[i+l];
3659 // Make sure its in this lane
3660 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3661 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3664 // If not lane 0, then we must match lane 0
3665 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3668 if (Idx >= (int)NumElts)
3669 Idx -= NumElts - NumLaneElts;
3671 if (!isUndefOrEqual(Idx, Start+i))
3680 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3681 /// the two vector operands have swapped position.
3682 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
3683 unsigned NumElems) {
3684 for (unsigned i = 0; i != NumElems; ++i) {
3688 else if (idx < (int)NumElems)
3689 Mask[i] = idx + NumElems;
3691 Mask[i] = idx - NumElems;
3695 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
3696 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
3697 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
3698 /// reverse of what x86 shuffles want.
3699 static bool isSHUFPMask(ArrayRef<int> Mask, MVT VT, bool Commuted = false) {
3701 unsigned NumElems = VT.getVectorNumElements();
3702 unsigned NumLanes = VT.getSizeInBits()/128;
3703 unsigned NumLaneElems = NumElems/NumLanes;
3705 if (NumLaneElems != 2 && NumLaneElems != 4)
3708 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3709 bool symetricMaskRequired =
3710 (VT.getSizeInBits() >= 256) && (EltSize == 32);
3712 // VSHUFPSY divides the resulting vector into 4 chunks.
3713 // The sources are also splitted into 4 chunks, and each destination
3714 // chunk must come from a different source chunk.
3716 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
3717 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
3719 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
3720 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
3722 // VSHUFPDY divides the resulting vector into 4 chunks.
3723 // The sources are also splitted into 4 chunks, and each destination
3724 // chunk must come from a different source chunk.
3726 // SRC1 => X3 X2 X1 X0
3727 // SRC2 => Y3 Y2 Y1 Y0
3729 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
3731 SmallVector<int, 4> MaskVal(NumLaneElems, -1);
3732 unsigned HalfLaneElems = NumLaneElems/2;
3733 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
3734 for (unsigned i = 0; i != NumLaneElems; ++i) {
3735 int Idx = Mask[i+l];
3736 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
3737 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
3739 // For VSHUFPSY, the mask of the second half must be the same as the
3740 // first but with the appropriate offsets. This works in the same way as
3741 // VPERMILPS works with masks.
3742 if (!symetricMaskRequired || Idx < 0)
3744 if (MaskVal[i] < 0) {
3745 MaskVal[i] = Idx - l;
3748 if ((signed)(Idx - l) != MaskVal[i])
3756 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
3757 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
3758 static bool isMOVHLPSMask(ArrayRef<int> Mask, MVT VT) {
3759 if (!VT.is128BitVector())
3762 unsigned NumElems = VT.getVectorNumElements();
3767 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
3768 return isUndefOrEqual(Mask[0], 6) &&
3769 isUndefOrEqual(Mask[1], 7) &&
3770 isUndefOrEqual(Mask[2], 2) &&
3771 isUndefOrEqual(Mask[3], 3);
3774 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
3775 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
3777 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, MVT VT) {
3778 if (!VT.is128BitVector())
3781 unsigned NumElems = VT.getVectorNumElements();
3786 return isUndefOrEqual(Mask[0], 2) &&
3787 isUndefOrEqual(Mask[1], 3) &&
3788 isUndefOrEqual(Mask[2], 2) &&
3789 isUndefOrEqual(Mask[3], 3);
3792 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
3793 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
3794 static bool isMOVLPMask(ArrayRef<int> Mask, MVT VT) {
3795 if (!VT.is128BitVector())
3798 unsigned NumElems = VT.getVectorNumElements();
3800 if (NumElems != 2 && NumElems != 4)
3803 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3804 if (!isUndefOrEqual(Mask[i], i + NumElems))
3807 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
3808 if (!isUndefOrEqual(Mask[i], i))
3814 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
3815 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
3816 static bool isMOVLHPSMask(ArrayRef<int> Mask, MVT VT) {
3817 if (!VT.is128BitVector())
3820 unsigned NumElems = VT.getVectorNumElements();
3822 if (NumElems != 2 && NumElems != 4)
3825 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3826 if (!isUndefOrEqual(Mask[i], i))
3829 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3830 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
3837 // Some special combinations that can be optimized.
3840 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
3841 SelectionDAG &DAG) {
3842 MVT VT = SVOp->getSimpleValueType(0);
3845 if (VT != MVT::v8i32 && VT != MVT::v8f32)
3848 ArrayRef<int> Mask = SVOp->getMask();
3850 // These are the special masks that may be optimized.
3851 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
3852 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
3853 bool MatchEvenMask = true;
3854 bool MatchOddMask = true;
3855 for (int i=0; i<8; ++i) {
3856 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
3857 MatchEvenMask = false;
3858 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
3859 MatchOddMask = false;
3862 if (!MatchEvenMask && !MatchOddMask)
3865 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
3867 SDValue Op0 = SVOp->getOperand(0);
3868 SDValue Op1 = SVOp->getOperand(1);
3870 if (MatchEvenMask) {
3871 // Shift the second operand right to 32 bits.
3872 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 };
3873 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
3875 // Shift the first operand left to 32 bits.
3876 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 };
3877 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
3879 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15};
3880 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
3883 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
3884 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
3885 static bool isUNPCKLMask(ArrayRef<int> Mask, MVT VT,
3886 bool HasInt256, bool V2IsSplat = false) {
3888 assert(VT.getSizeInBits() >= 128 &&
3889 "Unsupported vector type for unpckl");
3891 // AVX defines UNPCK* to operate independently on 128-bit lanes.
3893 unsigned NumOf256BitLanes;
3894 unsigned NumElts = VT.getVectorNumElements();
3895 if (VT.is256BitVector()) {
3896 if (NumElts != 4 && NumElts != 8 &&
3897 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
3900 NumOf256BitLanes = 1;
3901 } else if (VT.is512BitVector()) {
3902 assert(VT.getScalarType().getSizeInBits() >= 32 &&
3903 "Unsupported vector type for unpckh");
3905 NumOf256BitLanes = 2;
3908 NumOf256BitLanes = 1;
3911 unsigned NumEltsInStride = NumElts/NumOf256BitLanes;
3912 unsigned NumLaneElts = NumEltsInStride/NumLanes;
3914 for (unsigned l256 = 0; l256 < NumOf256BitLanes; l256 += 1) {
3915 for (unsigned l = 0; l != NumEltsInStride; l += NumLaneElts) {
3916 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
3917 int BitI = Mask[l256*NumEltsInStride+l+i];
3918 int BitI1 = Mask[l256*NumEltsInStride+l+i+1];
3919 if (!isUndefOrEqual(BitI, j+l256*NumElts))
3921 if (V2IsSplat && !isUndefOrEqual(BitI1, NumElts))
3923 if (!isUndefOrEqual(BitI1, j+l256*NumElts+NumEltsInStride))
3931 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
3932 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
3933 static bool isUNPCKHMask(ArrayRef<int> Mask, MVT VT,
3934 bool HasInt256, bool V2IsSplat = false) {
3935 assert(VT.getSizeInBits() >= 128 &&
3936 "Unsupported vector type for unpckh");
3938 // AVX defines UNPCK* to operate independently on 128-bit lanes.
3940 unsigned NumOf256BitLanes;
3941 unsigned NumElts = VT.getVectorNumElements();
3942 if (VT.is256BitVector()) {
3943 if (NumElts != 4 && NumElts != 8 &&
3944 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
3947 NumOf256BitLanes = 1;
3948 } else if (VT.is512BitVector()) {
3949 assert(VT.getScalarType().getSizeInBits() >= 32 &&
3950 "Unsupported vector type for unpckh");
3952 NumOf256BitLanes = 2;
3955 NumOf256BitLanes = 1;
3958 unsigned NumEltsInStride = NumElts/NumOf256BitLanes;
3959 unsigned NumLaneElts = NumEltsInStride/NumLanes;
3961 for (unsigned l256 = 0; l256 < NumOf256BitLanes; l256 += 1) {
3962 for (unsigned l = 0; l != NumEltsInStride; l += NumLaneElts) {
3963 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
3964 int BitI = Mask[l256*NumEltsInStride+l+i];
3965 int BitI1 = Mask[l256*NumEltsInStride+l+i+1];
3966 if (!isUndefOrEqual(BitI, j+l256*NumElts))
3968 if (V2IsSplat && !isUndefOrEqual(BitI1, NumElts))
3970 if (!isUndefOrEqual(BitI1, j+l256*NumElts+NumEltsInStride))
3978 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
3979 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
3981 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3982 unsigned NumElts = VT.getVectorNumElements();
3983 bool Is256BitVec = VT.is256BitVector();
3985 if (VT.is512BitVector())
3987 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3988 "Unsupported vector type for unpckh");
3990 if (Is256BitVec && NumElts != 4 && NumElts != 8 &&
3991 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
3994 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
3995 // FIXME: Need a better way to get rid of this, there's no latency difference
3996 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
3997 // the former later. We should also remove the "_undef" special mask.
3998 if (NumElts == 4 && Is256BitVec)
4001 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4002 // independently on 128-bit lanes.
4003 unsigned NumLanes = VT.getSizeInBits()/128;
4004 unsigned NumLaneElts = NumElts/NumLanes;
4006 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4007 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4008 int BitI = Mask[l+i];
4009 int BitI1 = Mask[l+i+1];
4011 if (!isUndefOrEqual(BitI, j))
4013 if (!isUndefOrEqual(BitI1, j))
4021 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
4022 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
4024 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4025 unsigned NumElts = VT.getVectorNumElements();
4027 if (VT.is512BitVector())
4030 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4031 "Unsupported vector type for unpckh");
4033 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4034 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4037 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4038 // independently on 128-bit lanes.
4039 unsigned NumLanes = VT.getSizeInBits()/128;
4040 unsigned NumLaneElts = NumElts/NumLanes;
4042 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4043 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4044 int BitI = Mask[l+i];
4045 int BitI1 = Mask[l+i+1];
4046 if (!isUndefOrEqual(BitI, j))
4048 if (!isUndefOrEqual(BitI1, j))
4055 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
4056 /// specifies a shuffle of elements that is suitable for input to MOVSS,
4057 /// MOVSD, and MOVD, i.e. setting the lowest element.
4058 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
4059 if (VT.getVectorElementType().getSizeInBits() < 32)
4061 if (!VT.is128BitVector())
4064 unsigned NumElts = VT.getVectorNumElements();
4066 if (!isUndefOrEqual(Mask[0], NumElts))
4069 for (unsigned i = 1; i != NumElts; ++i)
4070 if (!isUndefOrEqual(Mask[i], i))
4076 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
4077 /// as permutations between 128-bit chunks or halves. As an example: this
4079 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
4080 /// The first half comes from the second half of V1 and the second half from the
4081 /// the second half of V2.
4082 static bool isVPERM2X128Mask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4083 if (!HasFp256 || !VT.is256BitVector())
4086 // The shuffle result is divided into half A and half B. In total the two
4087 // sources have 4 halves, namely: C, D, E, F. The final values of A and
4088 // B must come from C, D, E or F.
4089 unsigned HalfSize = VT.getVectorNumElements()/2;
4090 bool MatchA = false, MatchB = false;
4092 // Check if A comes from one of C, D, E, F.
4093 for (unsigned Half = 0; Half != 4; ++Half) {
4094 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
4100 // Check if B comes from one of C, D, E, F.
4101 for (unsigned Half = 0; Half != 4; ++Half) {
4102 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
4108 return MatchA && MatchB;
4111 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
4112 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
4113 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
4114 MVT VT = SVOp->getSimpleValueType(0);
4116 unsigned HalfSize = VT.getVectorNumElements()/2;
4118 unsigned FstHalf = 0, SndHalf = 0;
4119 for (unsigned i = 0; i < HalfSize; ++i) {
4120 if (SVOp->getMaskElt(i) > 0) {
4121 FstHalf = SVOp->getMaskElt(i)/HalfSize;
4125 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
4126 if (SVOp->getMaskElt(i) > 0) {
4127 SndHalf = SVOp->getMaskElt(i)/HalfSize;
4132 return (FstHalf | (SndHalf << 4));
4135 // Symetric in-lane mask. Each lane has 4 elements (for imm8)
4136 static bool isPermImmMask(ArrayRef<int> Mask, MVT VT, unsigned& Imm8) {
4137 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4141 unsigned NumElts = VT.getVectorNumElements();
4143 if (VT.is128BitVector() || (VT.is256BitVector() && EltSize == 64)) {
4144 for (unsigned i = 0; i != NumElts; ++i) {
4147 Imm8 |= Mask[i] << (i*2);
4152 unsigned LaneSize = 4;
4153 SmallVector<int, 4> MaskVal(LaneSize, -1);
4155 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4156 for (unsigned i = 0; i != LaneSize; ++i) {
4157 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4161 if (MaskVal[i] < 0) {
4162 MaskVal[i] = Mask[i+l] - l;
4163 Imm8 |= MaskVal[i] << (i*2);
4166 if (Mask[i+l] != (signed)(MaskVal[i]+l))
4173 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
4174 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
4175 /// Note that VPERMIL mask matching is different depending whether theunderlying
4176 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
4177 /// to the same elements of the low, but to the higher half of the source.
4178 /// In VPERMILPD the two lanes could be shuffled independently of each other
4179 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
4180 static bool isVPERMILPMask(ArrayRef<int> Mask, MVT VT) {
4181 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4182 if (VT.getSizeInBits() < 256 || EltSize < 32)
4184 bool symetricMaskRequired = (EltSize == 32);
4185 unsigned NumElts = VT.getVectorNumElements();
4187 unsigned NumLanes = VT.getSizeInBits()/128;
4188 unsigned LaneSize = NumElts/NumLanes;
4189 // 2 or 4 elements in one lane
4191 SmallVector<int, 4> ExpectedMaskVal(LaneSize, -1);
4192 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4193 for (unsigned i = 0; i != LaneSize; ++i) {
4194 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4196 if (symetricMaskRequired) {
4197 if (ExpectedMaskVal[i] < 0 && Mask[i+l] >= 0) {
4198 ExpectedMaskVal[i] = Mask[i+l] - l;
4201 if (!isUndefOrEqual(Mask[i+l], ExpectedMaskVal[i]+l))
4209 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
4210 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
4211 /// element of vector 2 and the other elements to come from vector 1 in order.
4212 static bool isCommutedMOVLMask(ArrayRef<int> Mask, MVT VT,
4213 bool V2IsSplat = false, bool V2IsUndef = false) {
4214 if (!VT.is128BitVector())
4217 unsigned NumOps = VT.getVectorNumElements();
4218 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
4221 if (!isUndefOrEqual(Mask[0], 0))
4224 for (unsigned i = 1; i != NumOps; ++i)
4225 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
4226 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
4227 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
4233 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4234 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
4235 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
4236 static bool isMOVSHDUPMask(ArrayRef<int> Mask, MVT VT,
4237 const X86Subtarget *Subtarget) {
4238 if (!Subtarget->hasSSE3())
4241 unsigned NumElems = VT.getVectorNumElements();
4243 if ((VT.is128BitVector() && NumElems != 4) ||
4244 (VT.is256BitVector() && NumElems != 8) ||
4245 (VT.is512BitVector() && NumElems != 16))
4248 // "i+1" is the value the indexed mask element must have
4249 for (unsigned i = 0; i != NumElems; i += 2)
4250 if (!isUndefOrEqual(Mask[i], i+1) ||
4251 !isUndefOrEqual(Mask[i+1], i+1))
4257 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4258 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
4259 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
4260 static bool isMOVSLDUPMask(ArrayRef<int> Mask, MVT VT,
4261 const X86Subtarget *Subtarget) {
4262 if (!Subtarget->hasSSE3())
4265 unsigned NumElems = VT.getVectorNumElements();
4267 if ((VT.is128BitVector() && NumElems != 4) ||
4268 (VT.is256BitVector() && NumElems != 8) ||
4269 (VT.is512BitVector() && NumElems != 16))
4272 // "i" is the value the indexed mask element must have
4273 for (unsigned i = 0; i != NumElems; i += 2)
4274 if (!isUndefOrEqual(Mask[i], i) ||
4275 !isUndefOrEqual(Mask[i+1], i))
4281 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
4282 /// specifies a shuffle of elements that is suitable for input to 256-bit
4283 /// version of MOVDDUP.
4284 static bool isMOVDDUPYMask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4285 if (!HasFp256 || !VT.is256BitVector())
4288 unsigned NumElts = VT.getVectorNumElements();
4292 for (unsigned i = 0; i != NumElts/2; ++i)
4293 if (!isUndefOrEqual(Mask[i], 0))
4295 for (unsigned i = NumElts/2; i != NumElts; ++i)
4296 if (!isUndefOrEqual(Mask[i], NumElts/2))
4301 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4302 /// specifies a shuffle of elements that is suitable for input to 128-bit
4303 /// version of MOVDDUP.
4304 static bool isMOVDDUPMask(ArrayRef<int> Mask, MVT VT) {
4305 if (!VT.is128BitVector())
4308 unsigned e = VT.getVectorNumElements() / 2;
4309 for (unsigned i = 0; i != e; ++i)
4310 if (!isUndefOrEqual(Mask[i], i))
4312 for (unsigned i = 0; i != e; ++i)
4313 if (!isUndefOrEqual(Mask[e+i], i))
4318 /// isVEXTRACTIndex - Return true if the specified
4319 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
4320 /// suitable for instruction that extract 128 or 256 bit vectors
4321 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4322 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4323 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4326 // The index should be aligned on a vecWidth-bit boundary.
4328 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4330 MVT VT = N->getSimpleValueType(0);
4331 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4332 bool Result = (Index * ElSize) % vecWidth == 0;
4337 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
4338 /// operand specifies a subvector insert that is suitable for input to
4339 /// insertion of 128 or 256-bit subvectors
4340 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4341 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4342 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4344 // The index should be aligned on a vecWidth-bit boundary.
4346 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4348 MVT VT = N->getSimpleValueType(0);
4349 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4350 bool Result = (Index * ElSize) % vecWidth == 0;
4355 bool X86::isVINSERT128Index(SDNode *N) {
4356 return isVINSERTIndex(N, 128);
4359 bool X86::isVINSERT256Index(SDNode *N) {
4360 return isVINSERTIndex(N, 256);
4363 bool X86::isVEXTRACT128Index(SDNode *N) {
4364 return isVEXTRACTIndex(N, 128);
4367 bool X86::isVEXTRACT256Index(SDNode *N) {
4368 return isVEXTRACTIndex(N, 256);
4371 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4372 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4373 /// Handles 128-bit and 256-bit.
4374 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
4375 MVT VT = N->getSimpleValueType(0);
4377 assert((VT.getSizeInBits() >= 128) &&
4378 "Unsupported vector type for PSHUF/SHUFP");
4380 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
4381 // independently on 128-bit lanes.
4382 unsigned NumElts = VT.getVectorNumElements();
4383 unsigned NumLanes = VT.getSizeInBits()/128;
4384 unsigned NumLaneElts = NumElts/NumLanes;
4386 assert((NumLaneElts == 2 || NumLaneElts == 4 || NumLaneElts == 8) &&
4387 "Only supports 2, 4 or 8 elements per lane");
4389 unsigned Shift = (NumLaneElts >= 4) ? 1 : 0;
4391 for (unsigned i = 0; i != NumElts; ++i) {
4392 int Elt = N->getMaskElt(i);
4393 if (Elt < 0) continue;
4394 Elt &= NumLaneElts - 1;
4395 unsigned ShAmt = (i << Shift) % 8;
4396 Mask |= Elt << ShAmt;
4402 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4403 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4404 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4405 MVT VT = N->getSimpleValueType(0);
4407 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4408 "Unsupported vector type for PSHUFHW");
4410 unsigned NumElts = VT.getVectorNumElements();
4413 for (unsigned l = 0; l != NumElts; l += 8) {
4414 // 8 nodes per lane, but we only care about the last 4.
4415 for (unsigned i = 0; i < 4; ++i) {
4416 int Elt = N->getMaskElt(l+i+4);
4417 if (Elt < 0) continue;
4418 Elt &= 0x3; // only 2-bits.
4419 Mask |= Elt << (i * 2);
4426 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4427 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4428 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4429 MVT VT = N->getSimpleValueType(0);
4431 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4432 "Unsupported vector type for PSHUFHW");
4434 unsigned NumElts = VT.getVectorNumElements();
4437 for (unsigned l = 0; l != NumElts; l += 8) {
4438 // 8 nodes per lane, but we only care about the first 4.
4439 for (unsigned i = 0; i < 4; ++i) {
4440 int Elt = N->getMaskElt(l+i);
4441 if (Elt < 0) continue;
4442 Elt &= 0x3; // only 2-bits
4443 Mask |= Elt << (i * 2);
4450 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
4451 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
4452 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4453 MVT VT = SVOp->getSimpleValueType(0);
4454 unsigned EltSize = VT.is512BitVector() ? 1 :
4455 VT.getVectorElementType().getSizeInBits() >> 3;
4457 unsigned NumElts = VT.getVectorNumElements();
4458 unsigned NumLanes = VT.is512BitVector() ? 1 : VT.getSizeInBits()/128;
4459 unsigned NumLaneElts = NumElts/NumLanes;
4463 for (i = 0; i != NumElts; ++i) {
4464 Val = SVOp->getMaskElt(i);
4468 if (Val >= (int)NumElts)
4469 Val -= NumElts - NumLaneElts;
4471 assert(Val - i > 0 && "PALIGNR imm should be positive");
4472 return (Val - i) * EltSize;
4475 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4476 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4477 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4478 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4481 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4483 MVT VecVT = N->getOperand(0).getSimpleValueType();
4484 MVT ElVT = VecVT.getVectorElementType();
4486 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4487 return Index / NumElemsPerChunk;
4490 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4491 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4492 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4493 llvm_unreachable("Illegal insert subvector for VINSERT");
4496 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4498 MVT VecVT = N->getSimpleValueType(0);
4499 MVT ElVT = VecVT.getVectorElementType();
4501 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4502 return Index / NumElemsPerChunk;
4505 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
4506 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4507 /// and VINSERTI128 instructions.
4508 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4509 return getExtractVEXTRACTImmediate(N, 128);
4512 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
4513 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4514 /// and VINSERTI64x4 instructions.
4515 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4516 return getExtractVEXTRACTImmediate(N, 256);
4519 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4520 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4521 /// and VINSERTI128 instructions.
4522 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4523 return getInsertVINSERTImmediate(N, 128);
4526 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4527 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4528 /// and VINSERTI64x4 instructions.
4529 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4530 return getInsertVINSERTImmediate(N, 256);
4533 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4535 bool X86::isZeroNode(SDValue Elt) {
4536 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Elt))
4537 return CN->isNullValue();
4538 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4539 return CFP->getValueAPF().isPosZero();
4543 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
4544 /// their permute mask.
4545 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
4546 SelectionDAG &DAG) {
4547 MVT VT = SVOp->getSimpleValueType(0);
4548 unsigned NumElems = VT.getVectorNumElements();
4549 SmallVector<int, 8> MaskVec;
4551 for (unsigned i = 0; i != NumElems; ++i) {
4552 int Idx = SVOp->getMaskElt(i);
4554 if (Idx < (int)NumElems)
4559 MaskVec.push_back(Idx);
4561 return DAG.getVectorShuffle(VT, SDLoc(SVOp), SVOp->getOperand(1),
4562 SVOp->getOperand(0), &MaskVec[0]);
4565 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4566 /// match movhlps. The lower half elements should come from upper half of
4567 /// V1 (and in order), and the upper half elements should come from the upper
4568 /// half of V2 (and in order).
4569 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, MVT VT) {
4570 if (!VT.is128BitVector())
4572 if (VT.getVectorNumElements() != 4)
4574 for (unsigned i = 0, e = 2; i != e; ++i)
4575 if (!isUndefOrEqual(Mask[i], i+2))
4577 for (unsigned i = 2; i != 4; ++i)
4578 if (!isUndefOrEqual(Mask[i], i+4))
4583 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4584 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4586 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
4587 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4589 N = N->getOperand(0).getNode();
4590 if (!ISD::isNON_EXTLoad(N))
4593 *LD = cast<LoadSDNode>(N);
4597 // Test whether the given value is a vector value which will be legalized
4599 static bool WillBeConstantPoolLoad(SDNode *N) {
4600 if (N->getOpcode() != ISD::BUILD_VECTOR)
4603 // Check for any non-constant elements.
4604 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4605 switch (N->getOperand(i).getNode()->getOpcode()) {
4607 case ISD::ConstantFP:
4614 // Vectors of all-zeros and all-ones are materialized with special
4615 // instructions rather than being loaded.
4616 return !ISD::isBuildVectorAllZeros(N) &&
4617 !ISD::isBuildVectorAllOnes(N);
4620 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
4621 /// match movlp{s|d}. The lower half elements should come from lower half of
4622 /// V1 (and in order), and the upper half elements should come from the upper
4623 /// half of V2 (and in order). And since V1 will become the source of the
4624 /// MOVLP, it must be either a vector load or a scalar load to vector.
4625 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
4626 ArrayRef<int> Mask, MVT VT) {
4627 if (!VT.is128BitVector())
4630 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
4632 // Is V2 is a vector load, don't do this transformation. We will try to use
4633 // load folding shufps op.
4634 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
4637 unsigned NumElems = VT.getVectorNumElements();
4639 if (NumElems != 2 && NumElems != 4)
4641 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4642 if (!isUndefOrEqual(Mask[i], i))
4644 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4645 if (!isUndefOrEqual(Mask[i], i+NumElems))
4650 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
4652 static bool isSplatVector(SDNode *N) {
4653 if (N->getOpcode() != ISD::BUILD_VECTOR)
4656 SDValue SplatValue = N->getOperand(0);
4657 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
4658 if (N->getOperand(i) != SplatValue)
4663 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
4664 /// to an zero vector.
4665 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
4666 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
4667 SDValue V1 = N->getOperand(0);
4668 SDValue V2 = N->getOperand(1);
4669 unsigned NumElems = N->getValueType(0).getVectorNumElements();
4670 for (unsigned i = 0; i != NumElems; ++i) {
4671 int Idx = N->getMaskElt(i);
4672 if (Idx >= (int)NumElems) {
4673 unsigned Opc = V2.getOpcode();
4674 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
4676 if (Opc != ISD::BUILD_VECTOR ||
4677 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
4679 } else if (Idx >= 0) {
4680 unsigned Opc = V1.getOpcode();
4681 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
4683 if (Opc != ISD::BUILD_VECTOR ||
4684 !X86::isZeroNode(V1.getOperand(Idx)))
4691 /// getZeroVector - Returns a vector of specified type with all zero elements.
4693 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4694 SelectionDAG &DAG, SDLoc dl) {
4695 assert(VT.isVector() && "Expected a vector type");
4697 // Always build SSE zero vectors as <4 x i32> bitcasted
4698 // to their dest type. This ensures they get CSE'd.
4700 if (VT.is128BitVector()) { // SSE
4701 if (Subtarget->hasSSE2()) { // SSE2
4702 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4703 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4705 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4706 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4708 } else if (VT.is256BitVector()) { // AVX
4709 if (Subtarget->hasInt256()) { // AVX2
4710 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4711 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4712 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops,
4713 array_lengthof(Ops));
4715 // 256-bit logic and arithmetic instructions in AVX are all
4716 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4717 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4718 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4719 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops,
4720 array_lengthof(Ops));
4722 } else if (VT.is512BitVector()) { // AVX-512
4723 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4724 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4725 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4726 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops, 16);
4728 llvm_unreachable("Unexpected vector type");
4730 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4733 /// getOnesVector - Returns a vector of specified type with all bits set.
4734 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4735 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4736 /// Then bitcast to their original type, ensuring they get CSE'd.
4737 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
4739 assert(VT.isVector() && "Expected a vector type");
4741 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
4743 if (VT.is256BitVector()) {
4744 if (HasInt256) { // AVX2
4745 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4746 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops,
4747 array_lengthof(Ops));
4749 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4750 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4752 } else if (VT.is128BitVector()) {
4753 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4755 llvm_unreachable("Unexpected vector type");
4757 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4760 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
4761 /// that point to V2 points to its first element.
4762 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
4763 for (unsigned i = 0; i != NumElems; ++i) {
4764 if (Mask[i] > (int)NumElems) {
4770 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4771 /// operation of specified width.
4772 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
4774 unsigned NumElems = VT.getVectorNumElements();
4775 SmallVector<int, 8> Mask;
4776 Mask.push_back(NumElems);
4777 for (unsigned i = 1; i != NumElems; ++i)
4779 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4782 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4783 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4785 unsigned NumElems = VT.getVectorNumElements();
4786 SmallVector<int, 8> Mask;
4787 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4789 Mask.push_back(i + NumElems);
4791 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4794 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4795 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4797 unsigned NumElems = VT.getVectorNumElements();
4798 SmallVector<int, 8> Mask;
4799 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
4800 Mask.push_back(i + Half);
4801 Mask.push_back(i + NumElems + Half);
4803 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4806 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
4807 // a generic shuffle instruction because the target has no such instructions.
4808 // Generate shuffles which repeat i16 and i8 several times until they can be
4809 // represented by v4f32 and then be manipulated by target suported shuffles.
4810 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
4811 MVT VT = V.getSimpleValueType();
4812 int NumElems = VT.getVectorNumElements();
4815 while (NumElems > 4) {
4816 if (EltNo < NumElems/2) {
4817 V = getUnpackl(DAG, dl, VT, V, V);
4819 V = getUnpackh(DAG, dl, VT, V, V);
4820 EltNo -= NumElems/2;
4827 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
4828 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
4829 MVT VT = V.getSimpleValueType();
4832 if (VT.is128BitVector()) {
4833 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
4834 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
4835 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
4837 } else if (VT.is256BitVector()) {
4838 // To use VPERMILPS to splat scalars, the second half of indicies must
4839 // refer to the higher part, which is a duplication of the lower one,
4840 // because VPERMILPS can only handle in-lane permutations.
4841 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
4842 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
4844 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
4845 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
4848 llvm_unreachable("Vector size not supported");
4850 return DAG.getNode(ISD::BITCAST, dl, VT, V);
4853 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
4854 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
4855 MVT SrcVT = SV->getSimpleValueType(0);
4856 SDValue V1 = SV->getOperand(0);
4859 int EltNo = SV->getSplatIndex();
4860 int NumElems = SrcVT.getVectorNumElements();
4861 bool Is256BitVec = SrcVT.is256BitVector();
4863 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) &&
4864 "Unknown how to promote splat for type");
4866 // Extract the 128-bit part containing the splat element and update
4867 // the splat element index when it refers to the higher register.
4869 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
4870 if (EltNo >= NumElems/2)
4871 EltNo -= NumElems/2;
4874 // All i16 and i8 vector types can't be used directly by a generic shuffle
4875 // instruction because the target has no such instruction. Generate shuffles
4876 // which repeat i16 and i8 several times until they fit in i32, and then can
4877 // be manipulated by target suported shuffles.
4878 MVT EltVT = SrcVT.getVectorElementType();
4879 if (EltVT == MVT::i8 || EltVT == MVT::i16)
4880 V1 = PromoteSplati8i16(V1, DAG, EltNo);
4882 // Recreate the 256-bit vector and place the same 128-bit vector
4883 // into the low and high part. This is necessary because we want
4884 // to use VPERM* to shuffle the vectors
4886 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
4889 return getLegalSplat(DAG, V1, EltNo);
4892 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
4893 /// vector of zero or undef vector. This produces a shuffle where the low
4894 /// element of V2 is swizzled into the zero/undef vector, landing at element
4895 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4896 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4898 const X86Subtarget *Subtarget,
4899 SelectionDAG &DAG) {
4900 MVT VT = V2.getSimpleValueType();
4902 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
4903 unsigned NumElems = VT.getVectorNumElements();
4904 SmallVector<int, 16> MaskVec;
4905 for (unsigned i = 0; i != NumElems; ++i)
4906 // If this is the insertion idx, put the low elt of V2 here.
4907 MaskVec.push_back(i == Idx ? NumElems : i);
4908 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
4911 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
4912 /// target specific opcode. Returns true if the Mask could be calculated.
4913 /// Sets IsUnary to true if only uses one source.
4914 static bool getTargetShuffleMask(SDNode *N, MVT VT,
4915 SmallVectorImpl<int> &Mask, bool &IsUnary) {
4916 unsigned NumElems = VT.getVectorNumElements();
4920 switch(N->getOpcode()) {
4922 ImmN = N->getOperand(N->getNumOperands()-1);
4923 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4925 case X86ISD::UNPCKH:
4926 DecodeUNPCKHMask(VT, Mask);
4928 case X86ISD::UNPCKL:
4929 DecodeUNPCKLMask(VT, Mask);
4931 case X86ISD::MOVHLPS:
4932 DecodeMOVHLPSMask(NumElems, Mask);
4934 case X86ISD::MOVLHPS:
4935 DecodeMOVLHPSMask(NumElems, Mask);
4937 case X86ISD::PALIGNR:
4938 ImmN = N->getOperand(N->getNumOperands()-1);
4939 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4941 case X86ISD::PSHUFD:
4942 case X86ISD::VPERMILP:
4943 ImmN = N->getOperand(N->getNumOperands()-1);
4944 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4947 case X86ISD::PSHUFHW:
4948 ImmN = N->getOperand(N->getNumOperands()-1);
4949 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4952 case X86ISD::PSHUFLW:
4953 ImmN = N->getOperand(N->getNumOperands()-1);
4954 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4957 case X86ISD::VPERMI:
4958 ImmN = N->getOperand(N->getNumOperands()-1);
4959 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4963 case X86ISD::MOVSD: {
4964 // The index 0 always comes from the first element of the second source,
4965 // this is why MOVSS and MOVSD are used in the first place. The other
4966 // elements come from the other positions of the first source vector
4967 Mask.push_back(NumElems);
4968 for (unsigned i = 1; i != NumElems; ++i) {
4973 case X86ISD::VPERM2X128:
4974 ImmN = N->getOperand(N->getNumOperands()-1);
4975 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4976 if (Mask.empty()) return false;
4978 case X86ISD::MOVDDUP:
4979 case X86ISD::MOVLHPD:
4980 case X86ISD::MOVLPD:
4981 case X86ISD::MOVLPS:
4982 case X86ISD::MOVSHDUP:
4983 case X86ISD::MOVSLDUP:
4984 // Not yet implemented
4986 default: llvm_unreachable("unknown target shuffle node");
4992 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
4993 /// element of the result of the vector shuffle.
4994 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
4997 return SDValue(); // Limit search depth.
4999 SDValue V = SDValue(N, 0);
5000 EVT VT = V.getValueType();
5001 unsigned Opcode = V.getOpcode();
5003 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
5004 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
5005 int Elt = SV->getMaskElt(Index);
5008 return DAG.getUNDEF(VT.getVectorElementType());
5010 unsigned NumElems = VT.getVectorNumElements();
5011 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
5012 : SV->getOperand(1);
5013 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
5016 // Recurse into target specific vector shuffles to find scalars.
5017 if (isTargetShuffle(Opcode)) {
5018 MVT ShufVT = V.getSimpleValueType();
5019 unsigned NumElems = ShufVT.getVectorNumElements();
5020 SmallVector<int, 16> ShuffleMask;
5023 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
5026 int Elt = ShuffleMask[Index];
5028 return DAG.getUNDEF(ShufVT.getVectorElementType());
5030 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
5032 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
5036 // Actual nodes that may contain scalar elements
5037 if (Opcode == ISD::BITCAST) {
5038 V = V.getOperand(0);
5039 EVT SrcVT = V.getValueType();
5040 unsigned NumElems = VT.getVectorNumElements();
5042 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5046 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5047 return (Index == 0) ? V.getOperand(0)
5048 : DAG.getUNDEF(VT.getVectorElementType());
5050 if (V.getOpcode() == ISD::BUILD_VECTOR)
5051 return V.getOperand(Index);
5056 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
5057 /// shuffle operation which come from a consecutively from a zero. The
5058 /// search can start in two different directions, from left or right.
5059 /// We count undefs as zeros until PreferredNum is reached.
5060 static unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp,
5061 unsigned NumElems, bool ZerosFromLeft,
5063 unsigned PreferredNum = -1U) {
5064 unsigned NumZeros = 0;
5065 for (unsigned i = 0; i != NumElems; ++i) {
5066 unsigned Index = ZerosFromLeft ? i : NumElems - i - 1;
5067 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
5071 if (X86::isZeroNode(Elt))
5073 else if (Elt.getOpcode() == ISD::UNDEF) // Undef as zero up to PreferredNum.
5074 NumZeros = std::min(NumZeros + 1, PreferredNum);
5082 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
5083 /// correspond consecutively to elements from one of the vector operands,
5084 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
5086 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
5087 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
5088 unsigned NumElems, unsigned &OpNum) {
5089 bool SeenV1 = false;
5090 bool SeenV2 = false;
5092 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
5093 int Idx = SVOp->getMaskElt(i);
5094 // Ignore undef indicies
5098 if (Idx < (int)NumElems)
5103 // Only accept consecutive elements from the same vector
5104 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
5108 OpNum = SeenV1 ? 0 : 1;
5112 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
5113 /// logical left shift of a vector.
5114 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5115 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5117 SVOp->getSimpleValueType(0).getVectorNumElements();
5118 unsigned NumZeros = getNumOfConsecutiveZeros(
5119 SVOp, NumElems, false /* check zeros from right */, DAG,
5120 SVOp->getMaskElt(0));
5126 // Considering the elements in the mask that are not consecutive zeros,
5127 // check if they consecutively come from only one of the source vectors.
5129 // V1 = {X, A, B, C} 0
5131 // vector_shuffle V1, V2 <1, 2, 3, X>
5133 if (!isShuffleMaskConsecutive(SVOp,
5134 0, // Mask Start Index
5135 NumElems-NumZeros, // Mask End Index(exclusive)
5136 NumZeros, // Where to start looking in the src vector
5137 NumElems, // Number of elements in vector
5138 OpSrc)) // Which source operand ?
5143 ShVal = SVOp->getOperand(OpSrc);
5147 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
5148 /// logical left shift of a vector.
5149 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5150 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5152 SVOp->getSimpleValueType(0).getVectorNumElements();
5153 unsigned NumZeros = getNumOfConsecutiveZeros(
5154 SVOp, NumElems, true /* check zeros from left */, DAG,
5155 NumElems - SVOp->getMaskElt(NumElems - 1) - 1);
5161 // Considering the elements in the mask that are not consecutive zeros,
5162 // check if they consecutively come from only one of the source vectors.
5164 // 0 { A, B, X, X } = V2
5166 // vector_shuffle V1, V2 <X, X, 4, 5>
5168 if (!isShuffleMaskConsecutive(SVOp,
5169 NumZeros, // Mask Start Index
5170 NumElems, // Mask End Index(exclusive)
5171 0, // Where to start looking in the src vector
5172 NumElems, // Number of elements in vector
5173 OpSrc)) // Which source operand ?
5178 ShVal = SVOp->getOperand(OpSrc);
5182 /// isVectorShift - Returns true if the shuffle can be implemented as a
5183 /// logical left or right shift of a vector.
5184 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5185 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5186 // Although the logic below support any bitwidth size, there are no
5187 // shift instructions which handle more than 128-bit vectors.
5188 if (!SVOp->getSimpleValueType(0).is128BitVector())
5191 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
5192 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
5198 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
5200 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5201 unsigned NumNonZero, unsigned NumZero,
5203 const X86Subtarget* Subtarget,
5204 const TargetLowering &TLI) {
5211 for (unsigned i = 0; i < 16; ++i) {
5212 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5213 if (ThisIsNonZero && First) {
5215 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5217 V = DAG.getUNDEF(MVT::v8i16);
5222 SDValue ThisElt(0, 0), LastElt(0, 0);
5223 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5224 if (LastIsNonZero) {
5225 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5226 MVT::i16, Op.getOperand(i-1));
5228 if (ThisIsNonZero) {
5229 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5230 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5231 ThisElt, DAG.getConstant(8, MVT::i8));
5233 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5237 if (ThisElt.getNode())
5238 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5239 DAG.getIntPtrConstant(i/2));
5243 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
5246 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
5248 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5249 unsigned NumNonZero, unsigned NumZero,
5251 const X86Subtarget* Subtarget,
5252 const TargetLowering &TLI) {
5259 for (unsigned i = 0; i < 8; ++i) {
5260 bool isNonZero = (NonZeros & (1 << i)) != 0;
5264 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5266 V = DAG.getUNDEF(MVT::v8i16);
5269 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5270 MVT::v8i16, V, Op.getOperand(i),
5271 DAG.getIntPtrConstant(i));
5278 /// getVShift - Return a vector logical shift node.
5280 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5281 unsigned NumBits, SelectionDAG &DAG,
5282 const TargetLowering &TLI, SDLoc dl) {
5283 assert(VT.is128BitVector() && "Unknown type for VShift");
5284 EVT ShVT = MVT::v2i64;
5285 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5286 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
5287 return DAG.getNode(ISD::BITCAST, dl, VT,
5288 DAG.getNode(Opc, dl, ShVT, SrcOp,
5289 DAG.getConstant(NumBits,
5290 TLI.getScalarShiftAmountTy(SrcOp.getValueType()))));
5294 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5296 // Check if the scalar load can be widened into a vector load. And if
5297 // the address is "base + cst" see if the cst can be "absorbed" into
5298 // the shuffle mask.
5299 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5300 SDValue Ptr = LD->getBasePtr();
5301 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5303 EVT PVT = LD->getValueType(0);
5304 if (PVT != MVT::i32 && PVT != MVT::f32)
5309 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5310 FI = FINode->getIndex();
5312 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5313 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5314 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5315 Offset = Ptr.getConstantOperandVal(1);
5316 Ptr = Ptr.getOperand(0);
5321 // FIXME: 256-bit vector instructions don't require a strict alignment,
5322 // improve this code to support it better.
5323 unsigned RequiredAlign = VT.getSizeInBits()/8;
5324 SDValue Chain = LD->getChain();
5325 // Make sure the stack object alignment is at least 16 or 32.
5326 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5327 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5328 if (MFI->isFixedObjectIndex(FI)) {
5329 // Can't change the alignment. FIXME: It's possible to compute
5330 // the exact stack offset and reference FI + adjust offset instead.
5331 // If someone *really* cares about this. That's the way to implement it.
5334 MFI->setObjectAlignment(FI, RequiredAlign);
5338 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5339 // Ptr + (Offset & ~15).
5342 if ((Offset % RequiredAlign) & 3)
5344 int64_t StartOffset = Offset & ~(RequiredAlign-1);
5346 Ptr = DAG.getNode(ISD::ADD, SDLoc(Ptr), Ptr.getValueType(),
5347 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
5349 int EltNo = (Offset - StartOffset) >> 2;
5350 unsigned NumElems = VT.getVectorNumElements();
5352 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5353 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5354 LD->getPointerInfo().getWithOffset(StartOffset),
5355 false, false, false, 0);
5357 SmallVector<int, 8> Mask;
5358 for (unsigned i = 0; i != NumElems; ++i)
5359 Mask.push_back(EltNo);
5361 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5367 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
5368 /// vector of type 'VT', see if the elements can be replaced by a single large
5369 /// load which has the same value as a build_vector whose operands are 'elts'.
5371 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5373 /// FIXME: we'd also like to handle the case where the last elements are zero
5374 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5375 /// There's even a handy isZeroNode for that purpose.
5376 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
5377 SDLoc &DL, SelectionDAG &DAG) {
5378 EVT EltVT = VT.getVectorElementType();
5379 unsigned NumElems = Elts.size();
5381 LoadSDNode *LDBase = NULL;
5382 unsigned LastLoadedElt = -1U;
5384 // For each element in the initializer, see if we've found a load or an undef.
5385 // If we don't find an initial load element, or later load elements are
5386 // non-consecutive, bail out.
5387 for (unsigned i = 0; i < NumElems; ++i) {
5388 SDValue Elt = Elts[i];
5390 if (!Elt.getNode() ||
5391 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5394 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5396 LDBase = cast<LoadSDNode>(Elt.getNode());
5400 if (Elt.getOpcode() == ISD::UNDEF)
5403 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5404 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
5409 // If we have found an entire vector of loads and undefs, then return a large
5410 // load of the entire vector width starting at the base pointer. If we found
5411 // consecutive loads for the low half, generate a vzext_load node.
5412 if (LastLoadedElt == NumElems - 1) {
5413 SDValue NewLd = SDValue();
5414 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
5415 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5416 LDBase->getPointerInfo(),
5417 LDBase->isVolatile(), LDBase->isNonTemporal(),
5418 LDBase->isInvariant(), 0);
5419 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5420 LDBase->getPointerInfo(),
5421 LDBase->isVolatile(), LDBase->isNonTemporal(),
5422 LDBase->isInvariant(), LDBase->getAlignment());
5424 if (LDBase->hasAnyUseOfValue(1)) {
5425 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5427 SDValue(NewLd.getNode(), 1));
5428 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5429 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5430 SDValue(NewLd.getNode(), 1));
5435 if (NumElems == 4 && LastLoadedElt == 1 &&
5436 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5437 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5438 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5440 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops,
5441 array_lengthof(Ops), MVT::i64,
5442 LDBase->getPointerInfo(),
5443 LDBase->getAlignment(),
5444 false/*isVolatile*/, true/*ReadMem*/,
5447 // Make sure the newly-created LOAD is in the same position as LDBase in
5448 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5449 // update uses of LDBase's output chain to use the TokenFactor.
5450 if (LDBase->hasAnyUseOfValue(1)) {
5451 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5452 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5453 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5454 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5455 SDValue(ResNode.getNode(), 1));
5458 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
5463 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
5464 /// to generate a splat value for the following cases:
5465 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
5466 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
5467 /// a scalar load, or a constant.
5468 /// The VBROADCAST node is returned when a pattern is found,
5469 /// or SDValue() otherwise.
5470 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
5471 SelectionDAG &DAG) {
5472 if (!Subtarget->hasFp256())
5475 MVT VT = Op.getSimpleValueType();
5478 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
5479 "Unsupported vector type for broadcast.");
5484 switch (Op.getOpcode()) {
5486 // Unknown pattern found.
5489 case ISD::BUILD_VECTOR: {
5490 // The BUILD_VECTOR node must be a splat.
5491 if (!isSplatVector(Op.getNode()))
5494 Ld = Op.getOperand(0);
5495 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5496 Ld.getOpcode() == ISD::ConstantFP);
5498 // The suspected load node has several users. Make sure that all
5499 // of its users are from the BUILD_VECTOR node.
5500 // Constants may have multiple users.
5501 if (!ConstSplatVal && !Ld->hasNUsesOfValue(VT.getVectorNumElements(), 0))
5506 case ISD::VECTOR_SHUFFLE: {
5507 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5509 // Shuffles must have a splat mask where the first element is
5511 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
5514 SDValue Sc = Op.getOperand(0);
5515 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
5516 Sc.getOpcode() != ISD::BUILD_VECTOR) {
5518 if (!Subtarget->hasInt256())
5521 // Use the register form of the broadcast instruction available on AVX2.
5522 if (VT.getSizeInBits() >= 256)
5523 Sc = Extract128BitVector(Sc, 0, DAG, dl);
5524 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
5527 Ld = Sc.getOperand(0);
5528 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5529 Ld.getOpcode() == ISD::ConstantFP);
5531 // The scalar_to_vector node and the suspected
5532 // load node must have exactly one user.
5533 // Constants may have multiple users.
5535 // AVX-512 has register version of the broadcast
5536 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
5537 Ld.getValueType().getSizeInBits() >= 32;
5538 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
5545 bool IsGE256 = (VT.getSizeInBits() >= 256);
5547 // Handle the broadcasting a single constant scalar from the constant pool
5548 // into a vector. On Sandybridge it is still better to load a constant vector
5549 // from the constant pool and not to broadcast it from a scalar.
5550 if (ConstSplatVal && Subtarget->hasInt256()) {
5551 EVT CVT = Ld.getValueType();
5552 assert(!CVT.isVector() && "Must not broadcast a vector type");
5553 unsigned ScalarSize = CVT.getSizeInBits();
5555 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)) {
5556 const Constant *C = 0;
5557 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
5558 C = CI->getConstantIntValue();
5559 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
5560 C = CF->getConstantFPValue();
5562 assert(C && "Invalid constant type");
5564 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5565 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
5566 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
5567 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
5568 MachinePointerInfo::getConstantPool(),
5569 false, false, false, Alignment);
5571 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5575 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
5576 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5578 // Handle AVX2 in-register broadcasts.
5579 if (!IsLoad && Subtarget->hasInt256() &&
5580 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
5581 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5583 // The scalar source must be a normal load.
5587 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64))
5588 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5590 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5591 // double since there is no vbroadcastsd xmm
5592 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
5593 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
5594 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5597 // Unsupported broadcast.
5601 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
5602 MVT VT = Op.getSimpleValueType();
5604 // Skip if insert_vec_elt is not supported.
5605 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5606 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
5610 unsigned NumElems = Op.getNumOperands();
5614 SmallVector<unsigned, 4> InsertIndices;
5615 SmallVector<int, 8> Mask(NumElems, -1);
5617 for (unsigned i = 0; i != NumElems; ++i) {
5618 unsigned Opc = Op.getOperand(i).getOpcode();
5620 if (Opc == ISD::UNDEF)
5623 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
5624 // Quit if more than 1 elements need inserting.
5625 if (InsertIndices.size() > 1)
5628 InsertIndices.push_back(i);
5632 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
5633 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
5635 // Quit if extracted from vector of different type.
5636 if (ExtractedFromVec.getValueType() != VT)
5639 // Quit if non-constant index.
5640 if (!isa<ConstantSDNode>(ExtIdx))
5643 if (VecIn1.getNode() == 0)
5644 VecIn1 = ExtractedFromVec;
5645 else if (VecIn1 != ExtractedFromVec) {
5646 if (VecIn2.getNode() == 0)
5647 VecIn2 = ExtractedFromVec;
5648 else if (VecIn2 != ExtractedFromVec)
5649 // Quit if more than 2 vectors to shuffle
5653 unsigned Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
5655 if (ExtractedFromVec == VecIn1)
5657 else if (ExtractedFromVec == VecIn2)
5658 Mask[i] = Idx + NumElems;
5661 if (VecIn1.getNode() == 0)
5664 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
5665 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
5666 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
5667 unsigned Idx = InsertIndices[i];
5668 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
5669 DAG.getIntPtrConstant(Idx));
5675 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
5677 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
5679 MVT VT = Op.getSimpleValueType();
5680 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
5681 "Unexpected type in LowerBUILD_VECTORvXi1!");
5684 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5685 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
5686 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
5687 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5688 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
5689 Ops, VT.getVectorNumElements());
5692 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5693 SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
5694 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
5695 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5696 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
5697 Ops, VT.getVectorNumElements());
5700 bool AllContants = true;
5701 uint64_t Immediate = 0;
5702 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5703 SDValue In = Op.getOperand(idx);
5704 if (In.getOpcode() == ISD::UNDEF)
5706 if (!isa<ConstantSDNode>(In)) {
5707 AllContants = false;
5710 if (cast<ConstantSDNode>(In)->getZExtValue())
5711 Immediate |= (1ULL << idx);
5715 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
5716 DAG.getConstant(Immediate, MVT::i16));
5717 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
5718 DAG.getIntPtrConstant(0));
5721 // Splat vector (with undefs)
5722 SDValue In = Op.getOperand(0);
5723 for (unsigned i = 1, e = Op.getNumOperands(); i != e; ++i) {
5724 if (Op.getOperand(i) != In && Op.getOperand(i).getOpcode() != ISD::UNDEF)
5725 llvm_unreachable("Unsupported predicate operation");
5728 SDValue EFLAGS, X86CC;
5729 if (In.getOpcode() == ISD::SETCC) {
5730 SDValue Op0 = In.getOperand(0);
5731 SDValue Op1 = In.getOperand(1);
5732 ISD::CondCode CC = cast<CondCodeSDNode>(In.getOperand(2))->get();
5733 bool isFP = Op1.getValueType().isFloatingPoint();
5734 unsigned X86CCVal = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
5736 assert(X86CCVal != X86::COND_INVALID && "Unsupported predicate operation");
5738 X86CC = DAG.getConstant(X86CCVal, MVT::i8);
5739 EFLAGS = EmitCmp(Op0, Op1, X86CCVal, DAG);
5740 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
5741 } else if (In.getOpcode() == X86ISD::SETCC) {
5742 X86CC = In.getOperand(0);
5743 EFLAGS = In.getOperand(1);
5752 // res = allOnes ### CMOVNE -1, %res
5755 MVT InVT = In.getSimpleValueType();
5756 SDValue Bit1 = DAG.getNode(ISD::AND, dl, InVT, In, DAG.getConstant(1, InVT));
5757 EFLAGS = EmitTest(Bit1, X86::COND_NE, DAG);
5758 X86CC = DAG.getConstant(X86::COND_NE, MVT::i8);
5761 if (VT == MVT::v16i1) {
5762 SDValue Cst1 = DAG.getConstant(-1, MVT::i16);
5763 SDValue Cst0 = DAG.getConstant(0, MVT::i16);
5764 SDValue CmovOp = DAG.getNode(X86ISD::CMOV, dl, MVT::i16,
5765 Cst0, Cst1, X86CC, EFLAGS);
5766 return DAG.getNode(ISD::BITCAST, dl, VT, CmovOp);
5769 if (VT == MVT::v8i1) {
5770 SDValue Cst1 = DAG.getConstant(-1, MVT::i32);
5771 SDValue Cst0 = DAG.getConstant(0, MVT::i32);
5772 SDValue CmovOp = DAG.getNode(X86ISD::CMOV, dl, MVT::i32,
5773 Cst0, Cst1, X86CC, EFLAGS);
5774 CmovOp = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, CmovOp);
5775 return DAG.getNode(ISD::BITCAST, dl, VT, CmovOp);
5777 llvm_unreachable("Unsupported predicate operation");
5781 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
5784 MVT VT = Op.getSimpleValueType();
5785 MVT ExtVT = VT.getVectorElementType();
5786 unsigned NumElems = Op.getNumOperands();
5788 // Generate vectors for predicate vectors.
5789 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
5790 return LowerBUILD_VECTORvXi1(Op, DAG);
5792 // Vectors containing all zeros can be matched by pxor and xorps later
5793 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5794 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
5795 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
5796 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
5799 return getZeroVector(VT, Subtarget, DAG, dl);
5802 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
5803 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
5804 // vpcmpeqd on 256-bit vectors.
5805 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
5806 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
5809 if (!VT.is512BitVector())
5810 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
5813 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
5814 if (Broadcast.getNode())
5817 unsigned EVTBits = ExtVT.getSizeInBits();
5819 unsigned NumZero = 0;
5820 unsigned NumNonZero = 0;
5821 unsigned NonZeros = 0;
5822 bool IsAllConstants = true;
5823 SmallSet<SDValue, 8> Values;
5824 for (unsigned i = 0; i < NumElems; ++i) {
5825 SDValue Elt = Op.getOperand(i);
5826 if (Elt.getOpcode() == ISD::UNDEF)
5829 if (Elt.getOpcode() != ISD::Constant &&
5830 Elt.getOpcode() != ISD::ConstantFP)
5831 IsAllConstants = false;
5832 if (X86::isZeroNode(Elt))
5835 NonZeros |= (1 << i);
5840 // All undef vector. Return an UNDEF. All zero vectors were handled above.
5841 if (NumNonZero == 0)
5842 return DAG.getUNDEF(VT);
5844 // Special case for single non-zero, non-undef, element.
5845 if (NumNonZero == 1) {
5846 unsigned Idx = countTrailingZeros(NonZeros);
5847 SDValue Item = Op.getOperand(Idx);
5849 // If this is an insertion of an i64 value on x86-32, and if the top bits of
5850 // the value are obviously zero, truncate the value to i32 and do the
5851 // insertion that way. Only do this if the value is non-constant or if the
5852 // value is a constant being inserted into element 0. It is cheaper to do
5853 // a constant pool load than it is to do a movd + shuffle.
5854 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
5855 (!IsAllConstants || Idx == 0)) {
5856 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
5858 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
5859 EVT VecVT = MVT::v4i32;
5860 unsigned VecElts = 4;
5862 // Truncate the value (which may itself be a constant) to i32, and
5863 // convert it to a vector with movd (S2V+shuffle to zero extend).
5864 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
5865 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
5866 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5868 // Now we have our 32-bit value zero extended in the low element of
5869 // a vector. If Idx != 0, swizzle it into place.
5871 SmallVector<int, 4> Mask;
5872 Mask.push_back(Idx);
5873 for (unsigned i = 1; i != VecElts; ++i)
5875 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
5878 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5882 // If we have a constant or non-constant insertion into the low element of
5883 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
5884 // the rest of the elements. This will be matched as movd/movq/movss/movsd
5885 // depending on what the source datatype is.
5888 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5890 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
5891 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
5892 if (VT.is256BitVector() || VT.is512BitVector()) {
5893 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
5894 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
5895 Item, DAG.getIntPtrConstant(0));
5897 assert(VT.is128BitVector() && "Expected an SSE value type!");
5898 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5899 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
5900 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5903 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
5904 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
5905 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5906 if (VT.is256BitVector()) {
5907 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
5908 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
5910 assert(VT.is128BitVector() && "Expected an SSE value type!");
5911 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5913 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5917 // Is it a vector logical left shift?
5918 if (NumElems == 2 && Idx == 1 &&
5919 X86::isZeroNode(Op.getOperand(0)) &&
5920 !X86::isZeroNode(Op.getOperand(1))) {
5921 unsigned NumBits = VT.getSizeInBits();
5922 return getVShift(true, VT,
5923 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5924 VT, Op.getOperand(1)),
5925 NumBits/2, DAG, *this, dl);
5928 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
5931 // Otherwise, if this is a vector with i32 or f32 elements, and the element
5932 // is a non-constant being inserted into an element other than the low one,
5933 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
5934 // movd/movss) to move this into the low element, then shuffle it into
5936 if (EVTBits == 32) {
5937 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5939 // Turn it into a shuffle of zero and zero-extended scalar to vector.
5940 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
5941 SmallVector<int, 8> MaskVec;
5942 for (unsigned i = 0; i != NumElems; ++i)
5943 MaskVec.push_back(i == Idx ? 0 : 1);
5944 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
5948 // Splat is obviously ok. Let legalizer expand it to a shuffle.
5949 if (Values.size() == 1) {
5950 if (EVTBits == 32) {
5951 // Instead of a shuffle like this:
5952 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
5953 // Check if it's possible to issue this instead.
5954 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
5955 unsigned Idx = countTrailingZeros(NonZeros);
5956 SDValue Item = Op.getOperand(Idx);
5957 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
5958 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
5963 // A vector full of immediates; various special cases are already
5964 // handled, so this is best done with a single constant-pool load.
5968 // For AVX-length vectors, build the individual 128-bit pieces and use
5969 // shuffles to put them in place.
5970 if (VT.is256BitVector()) {
5971 SmallVector<SDValue, 32> V;
5972 for (unsigned i = 0; i != NumElems; ++i)
5973 V.push_back(Op.getOperand(i));
5975 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
5977 // Build both the lower and upper subvector.
5978 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2);
5979 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2],
5982 // Recreate the wider vector with the lower and upper part.
5983 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
5986 // Let legalizer expand 2-wide build_vectors.
5987 if (EVTBits == 64) {
5988 if (NumNonZero == 1) {
5989 // One half is zero or undef.
5990 unsigned Idx = countTrailingZeros(NonZeros);
5991 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
5992 Op.getOperand(Idx));
5993 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
5998 // If element VT is < 32 bits, convert it to inserts into a zero vector.
5999 if (EVTBits == 8 && NumElems == 16) {
6000 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
6002 if (V.getNode()) return V;
6005 if (EVTBits == 16 && NumElems == 8) {
6006 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
6008 if (V.getNode()) return V;
6011 // If element VT is == 32 bits, turn it into a number of shuffles.
6012 SmallVector<SDValue, 8> V(NumElems);
6013 if (NumElems == 4 && NumZero > 0) {
6014 for (unsigned i = 0; i < 4; ++i) {
6015 bool isZero = !(NonZeros & (1 << i));
6017 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
6019 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6022 for (unsigned i = 0; i < 2; ++i) {
6023 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
6026 V[i] = V[i*2]; // Must be a zero vector.
6029 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
6032 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
6035 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
6040 bool Reverse1 = (NonZeros & 0x3) == 2;
6041 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
6045 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
6046 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
6048 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
6051 if (Values.size() > 1 && VT.is128BitVector()) {
6052 // Check for a build vector of consecutive loads.
6053 for (unsigned i = 0; i < NumElems; ++i)
6054 V[i] = Op.getOperand(i);
6056 // Check for elements which are consecutive loads.
6057 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG);
6061 // Check for a build vector from mostly shuffle plus few inserting.
6062 SDValue Sh = buildFromShuffleMostly(Op, DAG);
6066 // For SSE 4.1, use insertps to put the high elements into the low element.
6067 if (getSubtarget()->hasSSE41()) {
6069 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
6070 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
6072 Result = DAG.getUNDEF(VT);
6074 for (unsigned i = 1; i < NumElems; ++i) {
6075 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
6076 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
6077 Op.getOperand(i), DAG.getIntPtrConstant(i));
6082 // Otherwise, expand into a number of unpckl*, start by extending each of
6083 // our (non-undef) elements to the full vector width with the element in the
6084 // bottom slot of the vector (which generates no code for SSE).
6085 for (unsigned i = 0; i < NumElems; ++i) {
6086 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
6087 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6089 V[i] = DAG.getUNDEF(VT);
6092 // Next, we iteratively mix elements, e.g. for v4f32:
6093 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
6094 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
6095 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
6096 unsigned EltStride = NumElems >> 1;
6097 while (EltStride != 0) {
6098 for (unsigned i = 0; i < EltStride; ++i) {
6099 // If V[i+EltStride] is undef and this is the first round of mixing,
6100 // then it is safe to just drop this shuffle: V[i] is already in the
6101 // right place, the one element (since it's the first round) being
6102 // inserted as undef can be dropped. This isn't safe for successive
6103 // rounds because they will permute elements within both vectors.
6104 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
6105 EltStride == NumElems/2)
6108 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
6117 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
6118 // to create 256-bit vectors from two other 128-bit ones.
6119 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6121 MVT ResVT = Op.getSimpleValueType();
6123 assert((ResVT.is256BitVector() ||
6124 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
6126 SDValue V1 = Op.getOperand(0);
6127 SDValue V2 = Op.getOperand(1);
6128 unsigned NumElems = ResVT.getVectorNumElements();
6129 if(ResVT.is256BitVector())
6130 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6132 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6135 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6136 assert(Op.getNumOperands() == 2);
6138 // AVX/AVX-512 can use the vinsertf128 instruction to create 256-bit vectors
6139 // from two other 128-bit ones.
6140 return LowerAVXCONCAT_VECTORS(Op, DAG);
6143 // Try to lower a shuffle node into a simple blend instruction.
6145 LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
6146 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
6147 SDValue V1 = SVOp->getOperand(0);
6148 SDValue V2 = SVOp->getOperand(1);
6150 MVT VT = SVOp->getSimpleValueType(0);
6151 MVT EltVT = VT.getVectorElementType();
6152 unsigned NumElems = VT.getVectorNumElements();
6154 // There is no blend with immediate in AVX-512.
6155 if (VT.is512BitVector())
6158 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
6160 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
6163 // Check the mask for BLEND and build the value.
6164 unsigned MaskValue = 0;
6165 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
6166 unsigned NumLanes = (NumElems-1)/8 + 1;
6167 unsigned NumElemsInLane = NumElems / NumLanes;
6169 // Blend for v16i16 should be symetric for the both lanes.
6170 for (unsigned i = 0; i < NumElemsInLane; ++i) {
6172 int SndLaneEltIdx = (NumLanes == 2) ?
6173 SVOp->getMaskElt(i + NumElemsInLane) : -1;
6174 int EltIdx = SVOp->getMaskElt(i);
6176 if ((EltIdx < 0 || EltIdx == (int)i) &&
6177 (SndLaneEltIdx < 0 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
6180 if (((unsigned)EltIdx == (i + NumElems)) &&
6181 (SndLaneEltIdx < 0 ||
6182 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
6183 MaskValue |= (1<<i);
6188 // Convert i32 vectors to floating point if it is not AVX2.
6189 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
6191 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
6192 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
6194 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
6195 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
6198 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
6199 DAG.getConstant(MaskValue, MVT::i32));
6200 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
6203 // v8i16 shuffles - Prefer shuffles in the following order:
6204 // 1. [all] pshuflw, pshufhw, optional move
6205 // 2. [ssse3] 1 x pshufb
6206 // 3. [ssse3] 2 x pshufb + 1 x por
6207 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
6209 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
6210 SelectionDAG &DAG) {
6211 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6212 SDValue V1 = SVOp->getOperand(0);
6213 SDValue V2 = SVOp->getOperand(1);
6215 SmallVector<int, 8> MaskVals;
6217 // Determine if more than 1 of the words in each of the low and high quadwords
6218 // of the result come from the same quadword of one of the two inputs. Undef
6219 // mask values count as coming from any quadword, for better codegen.
6220 unsigned LoQuad[] = { 0, 0, 0, 0 };
6221 unsigned HiQuad[] = { 0, 0, 0, 0 };
6222 std::bitset<4> InputQuads;
6223 for (unsigned i = 0; i < 8; ++i) {
6224 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
6225 int EltIdx = SVOp->getMaskElt(i);
6226 MaskVals.push_back(EltIdx);
6235 InputQuads.set(EltIdx / 4);
6238 int BestLoQuad = -1;
6239 unsigned MaxQuad = 1;
6240 for (unsigned i = 0; i < 4; ++i) {
6241 if (LoQuad[i] > MaxQuad) {
6243 MaxQuad = LoQuad[i];
6247 int BestHiQuad = -1;
6249 for (unsigned i = 0; i < 4; ++i) {
6250 if (HiQuad[i] > MaxQuad) {
6252 MaxQuad = HiQuad[i];
6256 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
6257 // of the two input vectors, shuffle them into one input vector so only a
6258 // single pshufb instruction is necessary. If There are more than 2 input
6259 // quads, disable the next transformation since it does not help SSSE3.
6260 bool V1Used = InputQuads[0] || InputQuads[1];
6261 bool V2Used = InputQuads[2] || InputQuads[3];
6262 if (Subtarget->hasSSSE3()) {
6263 if (InputQuads.count() == 2 && V1Used && V2Used) {
6264 BestLoQuad = InputQuads[0] ? 0 : 1;
6265 BestHiQuad = InputQuads[2] ? 2 : 3;
6267 if (InputQuads.count() > 2) {
6273 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
6274 // the shuffle mask. If a quad is scored as -1, that means that it contains
6275 // words from all 4 input quadwords.
6277 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
6279 BestLoQuad < 0 ? 0 : BestLoQuad,
6280 BestHiQuad < 0 ? 1 : BestHiQuad
6282 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
6283 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
6284 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
6285 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
6287 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
6288 // source words for the shuffle, to aid later transformations.
6289 bool AllWordsInNewV = true;
6290 bool InOrder[2] = { true, true };
6291 for (unsigned i = 0; i != 8; ++i) {
6292 int idx = MaskVals[i];
6294 InOrder[i/4] = false;
6295 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
6297 AllWordsInNewV = false;
6301 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
6302 if (AllWordsInNewV) {
6303 for (int i = 0; i != 8; ++i) {
6304 int idx = MaskVals[i];
6307 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
6308 if ((idx != i) && idx < 4)
6310 if ((idx != i) && idx > 3)
6319 // If we've eliminated the use of V2, and the new mask is a pshuflw or
6320 // pshufhw, that's as cheap as it gets. Return the new shuffle.
6321 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
6322 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
6323 unsigned TargetMask = 0;
6324 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
6325 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
6326 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
6327 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
6328 getShufflePSHUFLWImmediate(SVOp);
6329 V1 = NewV.getOperand(0);
6330 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
6334 // Promote splats to a larger type which usually leads to more efficient code.
6335 // FIXME: Is this true if pshufb is available?
6336 if (SVOp->isSplat())
6337 return PromoteSplat(SVOp, DAG);
6339 // If we have SSSE3, and all words of the result are from 1 input vector,
6340 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
6341 // is present, fall back to case 4.
6342 if (Subtarget->hasSSSE3()) {
6343 SmallVector<SDValue,16> pshufbMask;
6345 // If we have elements from both input vectors, set the high bit of the
6346 // shuffle mask element to zero out elements that come from V2 in the V1
6347 // mask, and elements that come from V1 in the V2 mask, so that the two
6348 // results can be OR'd together.
6349 bool TwoInputs = V1Used && V2Used;
6350 for (unsigned i = 0; i != 8; ++i) {
6351 int EltIdx = MaskVals[i] * 2;
6352 int Idx0 = (TwoInputs && (EltIdx >= 16)) ? 0x80 : EltIdx;
6353 int Idx1 = (TwoInputs && (EltIdx >= 16)) ? 0x80 : EltIdx+1;
6354 pshufbMask.push_back(DAG.getConstant(Idx0, MVT::i8));
6355 pshufbMask.push_back(DAG.getConstant(Idx1, MVT::i8));
6357 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1);
6358 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
6359 DAG.getNode(ISD::BUILD_VECTOR, dl,
6360 MVT::v16i8, &pshufbMask[0], 16));
6362 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
6364 // Calculate the shuffle mask for the second input, shuffle it, and
6365 // OR it with the first shuffled input.
6367 for (unsigned i = 0; i != 8; ++i) {
6368 int EltIdx = MaskVals[i] * 2;
6369 int Idx0 = (EltIdx < 16) ? 0x80 : EltIdx - 16;
6370 int Idx1 = (EltIdx < 16) ? 0x80 : EltIdx - 15;
6371 pshufbMask.push_back(DAG.getConstant(Idx0, MVT::i8));
6372 pshufbMask.push_back(DAG.getConstant(Idx1, MVT::i8));
6374 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2);
6375 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
6376 DAG.getNode(ISD::BUILD_VECTOR, dl,
6377 MVT::v16i8, &pshufbMask[0], 16));
6378 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
6379 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
6382 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
6383 // and update MaskVals with new element order.
6384 std::bitset<8> InOrder;
6385 if (BestLoQuad >= 0) {
6386 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
6387 for (int i = 0; i != 4; ++i) {
6388 int idx = MaskVals[i];
6391 } else if ((idx / 4) == BestLoQuad) {
6396 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
6399 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
6400 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
6401 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
6403 getShufflePSHUFLWImmediate(SVOp), DAG);
6407 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
6408 // and update MaskVals with the new element order.
6409 if (BestHiQuad >= 0) {
6410 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
6411 for (unsigned i = 4; i != 8; ++i) {
6412 int idx = MaskVals[i];
6415 } else if ((idx / 4) == BestHiQuad) {
6416 MaskV[i] = (idx & 3) + 4;
6420 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
6423 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
6424 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
6425 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
6427 getShufflePSHUFHWImmediate(SVOp), DAG);
6431 // In case BestHi & BestLo were both -1, which means each quadword has a word
6432 // from each of the four input quadwords, calculate the InOrder bitvector now
6433 // before falling through to the insert/extract cleanup.
6434 if (BestLoQuad == -1 && BestHiQuad == -1) {
6436 for (int i = 0; i != 8; ++i)
6437 if (MaskVals[i] < 0 || MaskVals[i] == i)
6441 // The other elements are put in the right place using pextrw and pinsrw.
6442 for (unsigned i = 0; i != 8; ++i) {
6445 int EltIdx = MaskVals[i];
6448 SDValue ExtOp = (EltIdx < 8) ?
6449 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
6450 DAG.getIntPtrConstant(EltIdx)) :
6451 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
6452 DAG.getIntPtrConstant(EltIdx - 8));
6453 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
6454 DAG.getIntPtrConstant(i));
6459 // v16i8 shuffles - Prefer shuffles in the following order:
6460 // 1. [ssse3] 1 x pshufb
6461 // 2. [ssse3] 2 x pshufb + 1 x por
6462 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
6463 static SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
6464 const X86Subtarget* Subtarget,
6465 SelectionDAG &DAG) {
6466 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6467 SDValue V1 = SVOp->getOperand(0);
6468 SDValue V2 = SVOp->getOperand(1);
6470 ArrayRef<int> MaskVals = SVOp->getMask();
6472 // Promote splats to a larger type which usually leads to more efficient code.
6473 // FIXME: Is this true if pshufb is available?
6474 if (SVOp->isSplat())
6475 return PromoteSplat(SVOp, DAG);
6477 // If we have SSSE3, case 1 is generated when all result bytes come from
6478 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
6479 // present, fall back to case 3.
6481 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
6482 if (Subtarget->hasSSSE3()) {
6483 SmallVector<SDValue,16> pshufbMask;
6485 // If all result elements are from one input vector, then only translate
6486 // undef mask values to 0x80 (zero out result) in the pshufb mask.
6488 // Otherwise, we have elements from both input vectors, and must zero out
6489 // elements that come from V2 in the first mask, and V1 in the second mask
6490 // so that we can OR them together.
6491 for (unsigned i = 0; i != 16; ++i) {
6492 int EltIdx = MaskVals[i];
6493 if (EltIdx < 0 || EltIdx >= 16)
6495 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
6497 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
6498 DAG.getNode(ISD::BUILD_VECTOR, dl,
6499 MVT::v16i8, &pshufbMask[0], 16));
6501 // As PSHUFB will zero elements with negative indices, it's safe to ignore
6502 // the 2nd operand if it's undefined or zero.
6503 if (V2.getOpcode() == ISD::UNDEF ||
6504 ISD::isBuildVectorAllZeros(V2.getNode()))
6507 // Calculate the shuffle mask for the second input, shuffle it, and
6508 // OR it with the first shuffled input.
6510 for (unsigned i = 0; i != 16; ++i) {
6511 int EltIdx = MaskVals[i];
6512 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
6513 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
6515 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
6516 DAG.getNode(ISD::BUILD_VECTOR, dl,
6517 MVT::v16i8, &pshufbMask[0], 16));
6518 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
6521 // No SSSE3 - Calculate in place words and then fix all out of place words
6522 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
6523 // the 16 different words that comprise the two doublequadword input vectors.
6524 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
6525 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
6527 for (int i = 0; i != 8; ++i) {
6528 int Elt0 = MaskVals[i*2];
6529 int Elt1 = MaskVals[i*2+1];
6531 // This word of the result is all undef, skip it.
6532 if (Elt0 < 0 && Elt1 < 0)
6535 // This word of the result is already in the correct place, skip it.
6536 if ((Elt0 == i*2) && (Elt1 == i*2+1))
6539 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
6540 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
6543 // If Elt0 and Elt1 are defined, are consecutive, and can be load
6544 // using a single extract together, load it and store it.
6545 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
6546 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
6547 DAG.getIntPtrConstant(Elt1 / 2));
6548 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
6549 DAG.getIntPtrConstant(i));
6553 // If Elt1 is defined, extract it from the appropriate source. If the
6554 // source byte is not also odd, shift the extracted word left 8 bits
6555 // otherwise clear the bottom 8 bits if we need to do an or.
6557 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
6558 DAG.getIntPtrConstant(Elt1 / 2));
6559 if ((Elt1 & 1) == 0)
6560 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
6562 TLI.getShiftAmountTy(InsElt.getValueType())));
6564 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
6565 DAG.getConstant(0xFF00, MVT::i16));
6567 // If Elt0 is defined, extract it from the appropriate source. If the
6568 // source byte is not also even, shift the extracted word right 8 bits. If
6569 // Elt1 was also defined, OR the extracted values together before
6570 // inserting them in the result.
6572 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
6573 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
6574 if ((Elt0 & 1) != 0)
6575 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
6577 TLI.getShiftAmountTy(InsElt0.getValueType())));
6579 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
6580 DAG.getConstant(0x00FF, MVT::i16));
6581 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
6584 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
6585 DAG.getIntPtrConstant(i));
6587 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
6590 // v32i8 shuffles - Translate to VPSHUFB if possible.
6592 SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
6593 const X86Subtarget *Subtarget,
6594 SelectionDAG &DAG) {
6595 MVT VT = SVOp->getSimpleValueType(0);
6596 SDValue V1 = SVOp->getOperand(0);
6597 SDValue V2 = SVOp->getOperand(1);
6599 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
6601 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
6602 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
6603 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
6605 // VPSHUFB may be generated if
6606 // (1) one of input vector is undefined or zeroinitializer.
6607 // The mask value 0x80 puts 0 in the corresponding slot of the vector.
6608 // And (2) the mask indexes don't cross the 128-bit lane.
6609 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
6610 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
6613 if (V1IsAllZero && !V2IsAllZero) {
6614 CommuteVectorShuffleMask(MaskVals, 32);
6617 SmallVector<SDValue, 32> pshufbMask;
6618 for (unsigned i = 0; i != 32; i++) {
6619 int EltIdx = MaskVals[i];
6620 if (EltIdx < 0 || EltIdx >= 32)
6623 if ((EltIdx >= 16 && i < 16) || (EltIdx < 16 && i >= 16))
6624 // Cross lane is not allowed.
6628 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
6630 return DAG.getNode(X86ISD::PSHUFB, dl, MVT::v32i8, V1,
6631 DAG.getNode(ISD::BUILD_VECTOR, dl,
6632 MVT::v32i8, &pshufbMask[0], 32));
6635 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
6636 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
6637 /// done when every pair / quad of shuffle mask elements point to elements in
6638 /// the right sequence. e.g.
6639 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
6641 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
6642 SelectionDAG &DAG) {
6643 MVT VT = SVOp->getSimpleValueType(0);
6645 unsigned NumElems = VT.getVectorNumElements();
6648 switch (VT.SimpleTy) {
6649 default: llvm_unreachable("Unexpected!");
6650 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
6651 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
6652 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
6653 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
6654 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
6655 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
6658 SmallVector<int, 8> MaskVec;
6659 for (unsigned i = 0; i != NumElems; i += Scale) {
6661 for (unsigned j = 0; j != Scale; ++j) {
6662 int EltIdx = SVOp->getMaskElt(i+j);
6666 StartIdx = (EltIdx / Scale);
6667 if (EltIdx != (int)(StartIdx*Scale + j))
6670 MaskVec.push_back(StartIdx);
6673 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
6674 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
6675 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
6678 /// getVZextMovL - Return a zero-extending vector move low node.
6680 static SDValue getVZextMovL(MVT VT, MVT OpVT,
6681 SDValue SrcOp, SelectionDAG &DAG,
6682 const X86Subtarget *Subtarget, SDLoc dl) {
6683 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
6684 LoadSDNode *LD = NULL;
6685 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
6686 LD = dyn_cast<LoadSDNode>(SrcOp);
6688 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
6690 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
6691 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
6692 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
6693 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
6694 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
6696 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
6697 return DAG.getNode(ISD::BITCAST, dl, VT,
6698 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
6699 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6707 return DAG.getNode(ISD::BITCAST, dl, VT,
6708 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
6709 DAG.getNode(ISD::BITCAST, dl,
6713 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
6714 /// which could not be matched by any known target speficic shuffle
6716 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
6718 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
6719 if (NewOp.getNode())
6722 MVT VT = SVOp->getSimpleValueType(0);
6724 unsigned NumElems = VT.getVectorNumElements();
6725 unsigned NumLaneElems = NumElems / 2;
6728 MVT EltVT = VT.getVectorElementType();
6729 MVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
6732 SmallVector<int, 16> Mask;
6733 for (unsigned l = 0; l < 2; ++l) {
6734 // Build a shuffle mask for the output, discovering on the fly which
6735 // input vectors to use as shuffle operands (recorded in InputUsed).
6736 // If building a suitable shuffle vector proves too hard, then bail
6737 // out with UseBuildVector set.
6738 bool UseBuildVector = false;
6739 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
6740 unsigned LaneStart = l * NumLaneElems;
6741 for (unsigned i = 0; i != NumLaneElems; ++i) {
6742 // The mask element. This indexes into the input.
6743 int Idx = SVOp->getMaskElt(i+LaneStart);
6745 // the mask element does not index into any input vector.
6750 // The input vector this mask element indexes into.
6751 int Input = Idx / NumLaneElems;
6753 // Turn the index into an offset from the start of the input vector.
6754 Idx -= Input * NumLaneElems;
6756 // Find or create a shuffle vector operand to hold this input.
6758 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
6759 if (InputUsed[OpNo] == Input)
6760 // This input vector is already an operand.
6762 if (InputUsed[OpNo] < 0) {
6763 // Create a new operand for this input vector.
6764 InputUsed[OpNo] = Input;
6769 if (OpNo >= array_lengthof(InputUsed)) {
6770 // More than two input vectors used! Give up on trying to create a
6771 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
6772 UseBuildVector = true;
6776 // Add the mask index for the new shuffle vector.
6777 Mask.push_back(Idx + OpNo * NumLaneElems);
6780 if (UseBuildVector) {
6781 SmallVector<SDValue, 16> SVOps;
6782 for (unsigned i = 0; i != NumLaneElems; ++i) {
6783 // The mask element. This indexes into the input.
6784 int Idx = SVOp->getMaskElt(i+LaneStart);
6786 SVOps.push_back(DAG.getUNDEF(EltVT));
6790 // The input vector this mask element indexes into.
6791 int Input = Idx / NumElems;
6793 // Turn the index into an offset from the start of the input vector.
6794 Idx -= Input * NumElems;
6796 // Extract the vector element by hand.
6797 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
6798 SVOp->getOperand(Input),
6799 DAG.getIntPtrConstant(Idx)));
6802 // Construct the output using a BUILD_VECTOR.
6803 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, &SVOps[0],
6805 } else if (InputUsed[0] < 0) {
6806 // No input vectors were used! The result is undefined.
6807 Output[l] = DAG.getUNDEF(NVT);
6809 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
6810 (InputUsed[0] % 2) * NumLaneElems,
6812 // If only one input was used, use an undefined vector for the other.
6813 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
6814 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
6815 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
6816 // At least one input vector was used. Create a new shuffle vector.
6817 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
6823 // Concatenate the result back
6824 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
6827 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
6828 /// 4 elements, and match them with several different shuffle types.
6830 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
6831 SDValue V1 = SVOp->getOperand(0);
6832 SDValue V2 = SVOp->getOperand(1);
6834 MVT VT = SVOp->getSimpleValueType(0);
6836 assert(VT.is128BitVector() && "Unsupported vector size");
6838 std::pair<int, int> Locs[4];
6839 int Mask1[] = { -1, -1, -1, -1 };
6840 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
6844 for (unsigned i = 0; i != 4; ++i) {
6845 int Idx = PermMask[i];
6847 Locs[i] = std::make_pair(-1, -1);
6849 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
6851 Locs[i] = std::make_pair(0, NumLo);
6855 Locs[i] = std::make_pair(1, NumHi);
6857 Mask1[2+NumHi] = Idx;
6863 if (NumLo <= 2 && NumHi <= 2) {
6864 // If no more than two elements come from either vector. This can be
6865 // implemented with two shuffles. First shuffle gather the elements.
6866 // The second shuffle, which takes the first shuffle as both of its
6867 // vector operands, put the elements into the right order.
6868 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6870 int Mask2[] = { -1, -1, -1, -1 };
6872 for (unsigned i = 0; i != 4; ++i)
6873 if (Locs[i].first != -1) {
6874 unsigned Idx = (i < 2) ? 0 : 4;
6875 Idx += Locs[i].first * 2 + Locs[i].second;
6879 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
6882 if (NumLo == 3 || NumHi == 3) {
6883 // Otherwise, we must have three elements from one vector, call it X, and
6884 // one element from the other, call it Y. First, use a shufps to build an
6885 // intermediate vector with the one element from Y and the element from X
6886 // that will be in the same half in the final destination (the indexes don't
6887 // matter). Then, use a shufps to build the final vector, taking the half
6888 // containing the element from Y from the intermediate, and the other half
6891 // Normalize it so the 3 elements come from V1.
6892 CommuteVectorShuffleMask(PermMask, 4);
6896 // Find the element from V2.
6898 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
6899 int Val = PermMask[HiIndex];
6906 Mask1[0] = PermMask[HiIndex];
6908 Mask1[2] = PermMask[HiIndex^1];
6910 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6913 Mask1[0] = PermMask[0];
6914 Mask1[1] = PermMask[1];
6915 Mask1[2] = HiIndex & 1 ? 6 : 4;
6916 Mask1[3] = HiIndex & 1 ? 4 : 6;
6917 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6920 Mask1[0] = HiIndex & 1 ? 2 : 0;
6921 Mask1[1] = HiIndex & 1 ? 0 : 2;
6922 Mask1[2] = PermMask[2];
6923 Mask1[3] = PermMask[3];
6928 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
6931 // Break it into (shuffle shuffle_hi, shuffle_lo).
6932 int LoMask[] = { -1, -1, -1, -1 };
6933 int HiMask[] = { -1, -1, -1, -1 };
6935 int *MaskPtr = LoMask;
6936 unsigned MaskIdx = 0;
6939 for (unsigned i = 0; i != 4; ++i) {
6946 int Idx = PermMask[i];
6948 Locs[i] = std::make_pair(-1, -1);
6949 } else if (Idx < 4) {
6950 Locs[i] = std::make_pair(MaskIdx, LoIdx);
6951 MaskPtr[LoIdx] = Idx;
6954 Locs[i] = std::make_pair(MaskIdx, HiIdx);
6955 MaskPtr[HiIdx] = Idx;
6960 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
6961 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
6962 int MaskOps[] = { -1, -1, -1, -1 };
6963 for (unsigned i = 0; i != 4; ++i)
6964 if (Locs[i].first != -1)
6965 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
6966 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
6969 static bool MayFoldVectorLoad(SDValue V) {
6970 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6971 V = V.getOperand(0);
6973 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6974 V = V.getOperand(0);
6975 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
6976 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
6977 // BUILD_VECTOR (load), undef
6978 V = V.getOperand(0);
6980 return MayFoldLoad(V);
6984 SDValue getMOVDDup(SDValue &Op, SDLoc &dl, SDValue V1, SelectionDAG &DAG) {
6985 MVT VT = Op.getSimpleValueType();
6987 // Canonizalize to v2f64.
6988 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
6989 return DAG.getNode(ISD::BITCAST, dl, VT,
6990 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
6995 SDValue getMOVLowToHigh(SDValue &Op, SDLoc &dl, SelectionDAG &DAG,
6997 SDValue V1 = Op.getOperand(0);
6998 SDValue V2 = Op.getOperand(1);
6999 MVT VT = Op.getSimpleValueType();
7001 assert(VT != MVT::v2i64 && "unsupported shuffle type");
7003 if (HasSSE2 && VT == MVT::v2f64)
7004 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
7006 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
7007 return DAG.getNode(ISD::BITCAST, dl, VT,
7008 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
7009 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
7010 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
7014 SDValue getMOVHighToLow(SDValue &Op, SDLoc &dl, SelectionDAG &DAG) {
7015 SDValue V1 = Op.getOperand(0);
7016 SDValue V2 = Op.getOperand(1);
7017 MVT VT = Op.getSimpleValueType();
7019 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
7020 "unsupported shuffle type");
7022 if (V2.getOpcode() == ISD::UNDEF)
7026 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
7030 SDValue getMOVLP(SDValue &Op, SDLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
7031 SDValue V1 = Op.getOperand(0);
7032 SDValue V2 = Op.getOperand(1);
7033 MVT VT = Op.getSimpleValueType();
7034 unsigned NumElems = VT.getVectorNumElements();
7036 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
7037 // operand of these instructions is only memory, so check if there's a
7038 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
7040 bool CanFoldLoad = false;
7042 // Trivial case, when V2 comes from a load.
7043 if (MayFoldVectorLoad(V2))
7046 // When V1 is a load, it can be folded later into a store in isel, example:
7047 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
7049 // (MOVLPSmr addr:$src1, VR128:$src2)
7050 // So, recognize this potential and also use MOVLPS or MOVLPD
7051 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
7054 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7056 if (HasSSE2 && NumElems == 2)
7057 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
7060 // If we don't care about the second element, proceed to use movss.
7061 if (SVOp->getMaskElt(1) != -1)
7062 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
7065 // movl and movlp will both match v2i64, but v2i64 is never matched by
7066 // movl earlier because we make it strict to avoid messing with the movlp load
7067 // folding logic (see the code above getMOVLP call). Match it here then,
7068 // this is horrible, but will stay like this until we move all shuffle
7069 // matching to x86 specific nodes. Note that for the 1st condition all
7070 // types are matched with movsd.
7072 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
7073 // as to remove this logic from here, as much as possible
7074 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
7075 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
7076 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
7079 assert(VT != MVT::v4i32 && "unsupported shuffle type");
7081 // Invert the operand order and use SHUFPS to match it.
7082 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
7083 getShuffleSHUFImmediate(SVOp), DAG);
7086 // Reduce a vector shuffle to zext.
7087 static SDValue LowerVectorIntExtend(SDValue Op, const X86Subtarget *Subtarget,
7088 SelectionDAG &DAG) {
7089 // PMOVZX is only available from SSE41.
7090 if (!Subtarget->hasSSE41())
7093 MVT VT = Op.getSimpleValueType();
7095 // Only AVX2 support 256-bit vector integer extending.
7096 if (!Subtarget->hasInt256() && VT.is256BitVector())
7099 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7101 SDValue V1 = Op.getOperand(0);
7102 SDValue V2 = Op.getOperand(1);
7103 unsigned NumElems = VT.getVectorNumElements();
7105 // Extending is an unary operation and the element type of the source vector
7106 // won't be equal to or larger than i64.
7107 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
7108 VT.getVectorElementType() == MVT::i64)
7111 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
7112 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
7113 while ((1U << Shift) < NumElems) {
7114 if (SVOp->getMaskElt(1U << Shift) == 1)
7117 // The maximal ratio is 8, i.e. from i8 to i64.
7122 // Check the shuffle mask.
7123 unsigned Mask = (1U << Shift) - 1;
7124 for (unsigned i = 0; i != NumElems; ++i) {
7125 int EltIdx = SVOp->getMaskElt(i);
7126 if ((i & Mask) != 0 && EltIdx != -1)
7128 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift))
7132 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
7133 MVT NeVT = MVT::getIntegerVT(NBits);
7134 MVT NVT = MVT::getVectorVT(NeVT, NumElems >> Shift);
7136 if (!DAG.getTargetLoweringInfo().isTypeLegal(NVT))
7139 // Simplify the operand as it's prepared to be fed into shuffle.
7140 unsigned SignificantBits = NVT.getSizeInBits() >> Shift;
7141 if (V1.getOpcode() == ISD::BITCAST &&
7142 V1.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
7143 V1.getOperand(0).getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
7144 V1.getOperand(0).getOperand(0)
7145 .getSimpleValueType().getSizeInBits() == SignificantBits) {
7146 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
7147 SDValue V = V1.getOperand(0).getOperand(0).getOperand(0);
7148 ConstantSDNode *CIdx =
7149 dyn_cast<ConstantSDNode>(V1.getOperand(0).getOperand(0).getOperand(1));
7150 // If it's foldable, i.e. normal load with single use, we will let code
7151 // selection to fold it. Otherwise, we will short the conversion sequence.
7152 if (CIdx && CIdx->getZExtValue() == 0 &&
7153 (!ISD::isNormalLoad(V.getNode()) || !V.hasOneUse())) {
7154 MVT FullVT = V.getSimpleValueType();
7155 MVT V1VT = V1.getSimpleValueType();
7156 if (FullVT.getSizeInBits() > V1VT.getSizeInBits()) {
7157 // The "ext_vec_elt" node is wider than the result node.
7158 // In this case we should extract subvector from V.
7159 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast (extract_subvector x)).
7160 unsigned Ratio = FullVT.getSizeInBits() / V1VT.getSizeInBits();
7161 MVT SubVecVT = MVT::getVectorVT(FullVT.getVectorElementType(),
7162 FullVT.getVectorNumElements()/Ratio);
7163 V = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVecVT, V,
7164 DAG.getIntPtrConstant(0));
7166 V1 = DAG.getNode(ISD::BITCAST, DL, V1VT, V);
7170 return DAG.getNode(ISD::BITCAST, DL, VT,
7171 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
7175 NormalizeVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
7176 SelectionDAG &DAG) {
7177 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7178 MVT VT = Op.getSimpleValueType();
7180 SDValue V1 = Op.getOperand(0);
7181 SDValue V2 = Op.getOperand(1);
7183 if (isZeroShuffle(SVOp))
7184 return getZeroVector(VT, Subtarget, DAG, dl);
7186 // Handle splat operations
7187 if (SVOp->isSplat()) {
7188 // Use vbroadcast whenever the splat comes from a foldable load
7189 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
7190 if (Broadcast.getNode())
7194 // Check integer expanding shuffles.
7195 SDValue NewOp = LowerVectorIntExtend(Op, Subtarget, DAG);
7196 if (NewOp.getNode())
7199 // If the shuffle can be profitably rewritten as a narrower shuffle, then
7201 if (VT == MVT::v8i16 || VT == MVT::v16i8 ||
7202 VT == MVT::v16i16 || VT == MVT::v32i8) {
7203 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
7204 if (NewOp.getNode())
7205 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
7206 } else if ((VT == MVT::v4i32 ||
7207 (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
7208 // FIXME: Figure out a cleaner way to do this.
7209 // Try to make use of movq to zero out the top part.
7210 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
7211 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
7212 if (NewOp.getNode()) {
7213 MVT NewVT = NewOp.getSimpleValueType();
7214 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
7215 NewVT, true, false))
7216 return getVZextMovL(VT, NewVT, NewOp.getOperand(0),
7217 DAG, Subtarget, dl);
7219 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
7220 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
7221 if (NewOp.getNode()) {
7222 MVT NewVT = NewOp.getSimpleValueType();
7223 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
7224 return getVZextMovL(VT, NewVT, NewOp.getOperand(1),
7225 DAG, Subtarget, dl);
7233 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
7234 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7235 SDValue V1 = Op.getOperand(0);
7236 SDValue V2 = Op.getOperand(1);
7237 MVT VT = Op.getSimpleValueType();
7239 unsigned NumElems = VT.getVectorNumElements();
7240 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
7241 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
7242 bool V1IsSplat = false;
7243 bool V2IsSplat = false;
7244 bool HasSSE2 = Subtarget->hasSSE2();
7245 bool HasFp256 = Subtarget->hasFp256();
7246 bool HasInt256 = Subtarget->hasInt256();
7247 MachineFunction &MF = DAG.getMachineFunction();
7248 bool OptForSize = MF.getFunction()->getAttributes().
7249 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
7251 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
7253 if (V1IsUndef && V2IsUndef)
7254 return DAG.getUNDEF(VT);
7256 assert(!V1IsUndef && "Op 1 of shuffle should not be undef");
7258 // Vector shuffle lowering takes 3 steps:
7260 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
7261 // narrowing and commutation of operands should be handled.
7262 // 2) Matching of shuffles with known shuffle masks to x86 target specific
7264 // 3) Rewriting of unmatched masks into new generic shuffle operations,
7265 // so the shuffle can be broken into other shuffles and the legalizer can
7266 // try the lowering again.
7268 // The general idea is that no vector_shuffle operation should be left to
7269 // be matched during isel, all of them must be converted to a target specific
7272 // Normalize the input vectors. Here splats, zeroed vectors, profitable
7273 // narrowing and commutation of operands should be handled. The actual code
7274 // doesn't include all of those, work in progress...
7275 SDValue NewOp = NormalizeVectorShuffle(Op, Subtarget, DAG);
7276 if (NewOp.getNode())
7279 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
7281 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
7282 // unpckh_undef). Only use pshufd if speed is more important than size.
7283 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
7284 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
7285 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
7286 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
7288 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
7289 V2IsUndef && MayFoldVectorLoad(V1))
7290 return getMOVDDup(Op, dl, V1, DAG);
7292 if (isMOVHLPS_v_undef_Mask(M, VT))
7293 return getMOVHighToLow(Op, dl, DAG);
7295 // Use to match splats
7296 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
7297 (VT == MVT::v2f64 || VT == MVT::v2i64))
7298 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
7300 if (isPSHUFDMask(M, VT)) {
7301 // The actual implementation will match the mask in the if above and then
7302 // during isel it can match several different instructions, not only pshufd
7303 // as its name says, sad but true, emulate the behavior for now...
7304 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
7305 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
7307 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
7309 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
7310 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
7312 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
7313 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, TargetMask,
7316 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
7320 if (isPALIGNRMask(M, VT, Subtarget))
7321 return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
7322 getShufflePALIGNRImmediate(SVOp),
7325 // Check if this can be converted into a logical shift.
7326 bool isLeft = false;
7329 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
7330 if (isShift && ShVal.hasOneUse()) {
7331 // If the shifted value has multiple uses, it may be cheaper to use
7332 // v_set0 + movlhps or movhlps, etc.
7333 MVT EltVT = VT.getVectorElementType();
7334 ShAmt *= EltVT.getSizeInBits();
7335 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
7338 if (isMOVLMask(M, VT)) {
7339 if (ISD::isBuildVectorAllZeros(V1.getNode()))
7340 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
7341 if (!isMOVLPMask(M, VT)) {
7342 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
7343 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
7345 if (VT == MVT::v4i32 || VT == MVT::v4f32)
7346 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
7350 // FIXME: fold these into legal mask.
7351 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
7352 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
7354 if (isMOVHLPSMask(M, VT))
7355 return getMOVHighToLow(Op, dl, DAG);
7357 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
7358 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
7360 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
7361 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
7363 if (isMOVLPMask(M, VT))
7364 return getMOVLP(Op, dl, DAG, HasSSE2);
7366 if (ShouldXformToMOVHLPS(M, VT) ||
7367 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
7368 return CommuteVectorShuffle(SVOp, DAG);
7371 // No better options. Use a vshldq / vsrldq.
7372 MVT EltVT = VT.getVectorElementType();
7373 ShAmt *= EltVT.getSizeInBits();
7374 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
7377 bool Commuted = false;
7378 // FIXME: This should also accept a bitcast of a splat? Be careful, not
7379 // 1,1,1,1 -> v8i16 though.
7380 V1IsSplat = isSplatVector(V1.getNode());
7381 V2IsSplat = isSplatVector(V2.getNode());
7383 // Canonicalize the splat or undef, if present, to be on the RHS.
7384 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
7385 CommuteVectorShuffleMask(M, NumElems);
7387 std::swap(V1IsSplat, V2IsSplat);
7391 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
7392 // Shuffling low element of v1 into undef, just return v1.
7395 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
7396 // the instruction selector will not match, so get a canonical MOVL with
7397 // swapped operands to undo the commute.
7398 return getMOVL(DAG, dl, VT, V2, V1);
7401 if (isUNPCKLMask(M, VT, HasInt256))
7402 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
7404 if (isUNPCKHMask(M, VT, HasInt256))
7405 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
7408 // Normalize mask so all entries that point to V2 points to its first
7409 // element then try to match unpck{h|l} again. If match, return a
7410 // new vector_shuffle with the corrected mask.p
7411 SmallVector<int, 8> NewMask(M.begin(), M.end());
7412 NormalizeMask(NewMask, NumElems);
7413 if (isUNPCKLMask(NewMask, VT, HasInt256, true))
7414 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
7415 if (isUNPCKHMask(NewMask, VT, HasInt256, true))
7416 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
7420 // Commute is back and try unpck* again.
7421 // FIXME: this seems wrong.
7422 CommuteVectorShuffleMask(M, NumElems);
7424 std::swap(V1IsSplat, V2IsSplat);
7427 if (isUNPCKLMask(M, VT, HasInt256))
7428 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
7430 if (isUNPCKHMask(M, VT, HasInt256))
7431 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
7434 // Normalize the node to match x86 shuffle ops if needed
7435 if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true)))
7436 return CommuteVectorShuffle(SVOp, DAG);
7438 // The checks below are all present in isShuffleMaskLegal, but they are
7439 // inlined here right now to enable us to directly emit target specific
7440 // nodes, and remove one by one until they don't return Op anymore.
7442 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
7443 SVOp->getSplatIndex() == 0 && V2IsUndef) {
7444 if (VT == MVT::v2f64 || VT == MVT::v2i64)
7445 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
7448 if (isPSHUFHWMask(M, VT, HasInt256))
7449 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
7450 getShufflePSHUFHWImmediate(SVOp),
7453 if (isPSHUFLWMask(M, VT, HasInt256))
7454 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
7455 getShufflePSHUFLWImmediate(SVOp),
7458 if (isSHUFPMask(M, VT))
7459 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
7460 getShuffleSHUFImmediate(SVOp), DAG);
7462 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
7463 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
7464 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
7465 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
7467 //===--------------------------------------------------------------------===//
7468 // Generate target specific nodes for 128 or 256-bit shuffles only
7469 // supported in the AVX instruction set.
7472 // Handle VMOVDDUPY permutations
7473 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
7474 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
7476 // Handle VPERMILPS/D* permutations
7477 if (isVPERMILPMask(M, VT)) {
7478 if ((HasInt256 && VT == MVT::v8i32) || VT == MVT::v16i32)
7479 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
7480 getShuffleSHUFImmediate(SVOp), DAG);
7481 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1,
7482 getShuffleSHUFImmediate(SVOp), DAG);
7485 // Handle VPERM2F128/VPERM2I128 permutations
7486 if (isVPERM2X128Mask(M, VT, HasFp256))
7487 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
7488 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
7490 SDValue BlendOp = LowerVECTOR_SHUFFLEtoBlend(SVOp, Subtarget, DAG);
7491 if (BlendOp.getNode())
7495 if (V2IsUndef && HasInt256 && isPermImmMask(M, VT, Imm8))
7496 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, Imm8, DAG);
7498 if ((V2IsUndef && HasInt256 && VT.is256BitVector() && NumElems == 8) ||
7499 VT.is512BitVector()) {
7500 MVT MaskEltVT = MVT::getIntegerVT(VT.getVectorElementType().getSizeInBits());
7501 MVT MaskVectorVT = MVT::getVectorVT(MaskEltVT, NumElems);
7502 SmallVector<SDValue, 16> permclMask;
7503 for (unsigned i = 0; i != NumElems; ++i) {
7504 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MaskEltVT));
7507 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVectorVT,
7508 &permclMask[0], NumElems);
7510 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
7511 return DAG.getNode(X86ISD::VPERMV, dl, VT,
7512 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
7513 return DAG.getNode(X86ISD::VPERMV3, dl, VT,
7514 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1, V2);
7517 //===--------------------------------------------------------------------===//
7518 // Since no target specific shuffle was selected for this generic one,
7519 // lower it into other known shuffles. FIXME: this isn't true yet, but
7520 // this is the plan.
7523 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
7524 if (VT == MVT::v8i16) {
7525 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
7526 if (NewOp.getNode())
7530 if (VT == MVT::v16i8) {
7531 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, Subtarget, DAG);
7532 if (NewOp.getNode())
7536 if (VT == MVT::v32i8) {
7537 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
7538 if (NewOp.getNode())
7542 // Handle all 128-bit wide vectors with 4 elements, and match them with
7543 // several different shuffle types.
7544 if (NumElems == 4 && VT.is128BitVector())
7545 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
7547 // Handle general 256-bit shuffles
7548 if (VT.is256BitVector())
7549 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
7554 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
7555 MVT VT = Op.getSimpleValueType();
7558 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
7561 if (VT.getSizeInBits() == 8) {
7562 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
7563 Op.getOperand(0), Op.getOperand(1));
7564 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
7565 DAG.getValueType(VT));
7566 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
7569 if (VT.getSizeInBits() == 16) {
7570 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7571 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
7573 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
7574 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
7575 DAG.getNode(ISD::BITCAST, dl,
7579 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
7580 Op.getOperand(0), Op.getOperand(1));
7581 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
7582 DAG.getValueType(VT));
7583 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
7586 if (VT == MVT::f32) {
7587 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
7588 // the result back to FR32 register. It's only worth matching if the
7589 // result has a single use which is a store or a bitcast to i32. And in
7590 // the case of a store, it's not worth it if the index is a constant 0,
7591 // because a MOVSSmr can be used instead, which is smaller and faster.
7592 if (!Op.hasOneUse())
7594 SDNode *User = *Op.getNode()->use_begin();
7595 if ((User->getOpcode() != ISD::STORE ||
7596 (isa<ConstantSDNode>(Op.getOperand(1)) &&
7597 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
7598 (User->getOpcode() != ISD::BITCAST ||
7599 User->getValueType(0) != MVT::i32))
7601 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
7602 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
7605 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
7608 if (VT == MVT::i32 || VT == MVT::i64) {
7609 // ExtractPS/pextrq works with constant index.
7610 if (isa<ConstantSDNode>(Op.getOperand(1)))
7617 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
7618 SelectionDAG &DAG) const {
7620 SDValue Vec = Op.getOperand(0);
7621 MVT VecVT = Vec.getSimpleValueType();
7622 SDValue Idx = Op.getOperand(1);
7623 if (!isa<ConstantSDNode>(Idx)) {
7624 if (VecVT.is512BitVector() ||
7625 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
7626 VecVT.getVectorElementType().getSizeInBits() == 32)) {
7629 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
7630 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
7631 MaskEltVT.getSizeInBits());
7633 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
7634 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
7635 getZeroVector(MaskVT, Subtarget, DAG, dl),
7636 Idx, DAG.getConstant(0, getPointerTy()));
7637 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
7638 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
7639 Perm, DAG.getConstant(0, getPointerTy()));
7644 // If this is a 256-bit vector result, first extract the 128-bit vector and
7645 // then extract the element from the 128-bit vector.
7646 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
7648 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7649 // Get the 128-bit vector.
7650 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
7651 MVT EltVT = VecVT.getVectorElementType();
7653 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
7655 //if (IdxVal >= NumElems/2)
7656 // IdxVal -= NumElems/2;
7657 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
7658 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
7659 DAG.getConstant(IdxVal, MVT::i32));
7662 assert(VecVT.is128BitVector() && "Unexpected vector length");
7664 if (Subtarget->hasSSE41()) {
7665 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
7670 MVT VT = Op.getSimpleValueType();
7671 // TODO: handle v16i8.
7672 if (VT.getSizeInBits() == 16) {
7673 SDValue Vec = Op.getOperand(0);
7674 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7676 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
7677 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
7678 DAG.getNode(ISD::BITCAST, dl,
7681 // Transform it so it match pextrw which produces a 32-bit result.
7682 MVT EltVT = MVT::i32;
7683 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
7684 Op.getOperand(0), Op.getOperand(1));
7685 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
7686 DAG.getValueType(VT));
7687 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
7690 if (VT.getSizeInBits() == 32) {
7691 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7695 // SHUFPS the element to the lowest double word, then movss.
7696 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
7697 MVT VVT = Op.getOperand(0).getSimpleValueType();
7698 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
7699 DAG.getUNDEF(VVT), Mask);
7700 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
7701 DAG.getIntPtrConstant(0));
7704 if (VT.getSizeInBits() == 64) {
7705 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
7706 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
7707 // to match extract_elt for f64.
7708 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7712 // UNPCKHPD the element to the lowest double word, then movsd.
7713 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
7714 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
7715 int Mask[2] = { 1, -1 };
7716 MVT VVT = Op.getOperand(0).getSimpleValueType();
7717 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
7718 DAG.getUNDEF(VVT), Mask);
7719 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
7720 DAG.getIntPtrConstant(0));
7726 static SDValue LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
7727 MVT VT = Op.getSimpleValueType();
7728 MVT EltVT = VT.getVectorElementType();
7731 SDValue N0 = Op.getOperand(0);
7732 SDValue N1 = Op.getOperand(1);
7733 SDValue N2 = Op.getOperand(2);
7735 if (!VT.is128BitVector())
7738 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
7739 isa<ConstantSDNode>(N2)) {
7741 if (VT == MVT::v8i16)
7742 Opc = X86ISD::PINSRW;
7743 else if (VT == MVT::v16i8)
7744 Opc = X86ISD::PINSRB;
7746 Opc = X86ISD::PINSRB;
7748 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
7750 if (N1.getValueType() != MVT::i32)
7751 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
7752 if (N2.getValueType() != MVT::i32)
7753 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
7754 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
7757 if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
7758 // Bits [7:6] of the constant are the source select. This will always be
7759 // zero here. The DAG Combiner may combine an extract_elt index into these
7760 // bits. For example (insert (extract, 3), 2) could be matched by putting
7761 // the '3' into bits [7:6] of X86ISD::INSERTPS.
7762 // Bits [5:4] of the constant are the destination select. This is the
7763 // value of the incoming immediate.
7764 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
7765 // combine either bitwise AND or insert of float 0.0 to set these bits.
7766 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
7767 // Create this as a scalar to vector..
7768 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
7769 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
7772 if ((EltVT == MVT::i32 || EltVT == MVT::i64) && isa<ConstantSDNode>(N2)) {
7773 // PINSR* works with constant index.
7780 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
7781 MVT VT = Op.getSimpleValueType();
7782 MVT EltVT = VT.getVectorElementType();
7785 SDValue N0 = Op.getOperand(0);
7786 SDValue N1 = Op.getOperand(1);
7787 SDValue N2 = Op.getOperand(2);
7789 // If this is a 256-bit vector result, first extract the 128-bit vector,
7790 // insert the element into the extracted half and then place it back.
7791 if (VT.is256BitVector() || VT.is512BitVector()) {
7792 if (!isa<ConstantSDNode>(N2))
7795 // Get the desired 128-bit vector half.
7796 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue();
7797 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
7799 // Insert the element into the desired half.
7800 unsigned NumEltsIn128 = 128/EltVT.getSizeInBits();
7801 unsigned IdxIn128 = IdxVal - (IdxVal/NumEltsIn128) * NumEltsIn128;
7803 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
7804 DAG.getConstant(IdxIn128, MVT::i32));
7806 // Insert the changed part back to the 256-bit vector
7807 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
7810 if (Subtarget->hasSSE41())
7811 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
7813 if (EltVT == MVT::i8)
7816 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
7817 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
7818 // as its second argument.
7819 if (N1.getValueType() != MVT::i32)
7820 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
7821 if (N2.getValueType() != MVT::i32)
7822 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
7823 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
7828 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
7830 MVT OpVT = Op.getSimpleValueType();
7832 // If this is a 256-bit vector result, first insert into a 128-bit
7833 // vector and then insert into the 256-bit vector.
7834 if (!OpVT.is128BitVector()) {
7835 // Insert into a 128-bit vector.
7836 unsigned SizeFactor = OpVT.getSizeInBits()/128;
7837 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
7838 OpVT.getVectorNumElements() / SizeFactor);
7840 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
7842 // Insert the 128-bit vector.
7843 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
7846 if (OpVT == MVT::v1i64 &&
7847 Op.getOperand(0).getValueType() == MVT::i64)
7848 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
7850 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
7851 assert(OpVT.is128BitVector() && "Expected an SSE type!");
7852 return DAG.getNode(ISD::BITCAST, dl, OpVT,
7853 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
7856 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
7857 // a simple subregister reference or explicit instructions to grab
7858 // upper bits of a vector.
7859 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
7860 SelectionDAG &DAG) {
7862 SDValue In = Op.getOperand(0);
7863 SDValue Idx = Op.getOperand(1);
7864 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7865 MVT ResVT = Op.getSimpleValueType();
7866 MVT InVT = In.getSimpleValueType();
7868 if (Subtarget->hasFp256()) {
7869 if (ResVT.is128BitVector() &&
7870 (InVT.is256BitVector() || InVT.is512BitVector()) &&
7871 isa<ConstantSDNode>(Idx)) {
7872 return Extract128BitVector(In, IdxVal, DAG, dl);
7874 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
7875 isa<ConstantSDNode>(Idx)) {
7876 return Extract256BitVector(In, IdxVal, DAG, dl);
7882 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
7883 // simple superregister reference or explicit instructions to insert
7884 // the upper bits of a vector.
7885 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
7886 SelectionDAG &DAG) {
7887 if (Subtarget->hasFp256()) {
7888 SDLoc dl(Op.getNode());
7889 SDValue Vec = Op.getNode()->getOperand(0);
7890 SDValue SubVec = Op.getNode()->getOperand(1);
7891 SDValue Idx = Op.getNode()->getOperand(2);
7893 if ((Op.getNode()->getSimpleValueType(0).is256BitVector() ||
7894 Op.getNode()->getSimpleValueType(0).is512BitVector()) &&
7895 SubVec.getNode()->getSimpleValueType(0).is128BitVector() &&
7896 isa<ConstantSDNode>(Idx)) {
7897 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7898 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
7901 if (Op.getNode()->getSimpleValueType(0).is512BitVector() &&
7902 SubVec.getNode()->getSimpleValueType(0).is256BitVector() &&
7903 isa<ConstantSDNode>(Idx)) {
7904 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7905 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
7911 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
7912 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
7913 // one of the above mentioned nodes. It has to be wrapped because otherwise
7914 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
7915 // be used to form addressing mode. These wrapped nodes will be selected
7918 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
7919 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
7921 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7923 unsigned char OpFlag = 0;
7924 unsigned WrapperKind = X86ISD::Wrapper;
7925 CodeModel::Model M = getTargetMachine().getCodeModel();
7927 if (Subtarget->isPICStyleRIPRel() &&
7928 (M == CodeModel::Small || M == CodeModel::Kernel))
7929 WrapperKind = X86ISD::WrapperRIP;
7930 else if (Subtarget->isPICStyleGOT())
7931 OpFlag = X86II::MO_GOTOFF;
7932 else if (Subtarget->isPICStyleStubPIC())
7933 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7935 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
7937 CP->getOffset(), OpFlag);
7939 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7940 // With PIC, the address is actually $g + Offset.
7942 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7943 DAG.getNode(X86ISD::GlobalBaseReg,
7944 SDLoc(), getPointerTy()),
7951 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
7952 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
7954 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7956 unsigned char OpFlag = 0;
7957 unsigned WrapperKind = X86ISD::Wrapper;
7958 CodeModel::Model M = getTargetMachine().getCodeModel();
7960 if (Subtarget->isPICStyleRIPRel() &&
7961 (M == CodeModel::Small || M == CodeModel::Kernel))
7962 WrapperKind = X86ISD::WrapperRIP;
7963 else if (Subtarget->isPICStyleGOT())
7964 OpFlag = X86II::MO_GOTOFF;
7965 else if (Subtarget->isPICStyleStubPIC())
7966 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7968 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
7971 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7973 // With PIC, the address is actually $g + Offset.
7975 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7976 DAG.getNode(X86ISD::GlobalBaseReg,
7977 SDLoc(), getPointerTy()),
7984 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
7985 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
7987 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7989 unsigned char OpFlag = 0;
7990 unsigned WrapperKind = X86ISD::Wrapper;
7991 CodeModel::Model M = getTargetMachine().getCodeModel();
7993 if (Subtarget->isPICStyleRIPRel() &&
7994 (M == CodeModel::Small || M == CodeModel::Kernel)) {
7995 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
7996 OpFlag = X86II::MO_GOTPCREL;
7997 WrapperKind = X86ISD::WrapperRIP;
7998 } else if (Subtarget->isPICStyleGOT()) {
7999 OpFlag = X86II::MO_GOT;
8000 } else if (Subtarget->isPICStyleStubPIC()) {
8001 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
8002 } else if (Subtarget->isPICStyleStubNoDynamic()) {
8003 OpFlag = X86II::MO_DARWIN_NONLAZY;
8006 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
8009 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
8011 // With PIC, the address is actually $g + Offset.
8012 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
8013 !Subtarget->is64Bit()) {
8014 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8015 DAG.getNode(X86ISD::GlobalBaseReg,
8016 SDLoc(), getPointerTy()),
8020 // For symbols that require a load from a stub to get the address, emit the
8022 if (isGlobalStubReference(OpFlag))
8023 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
8024 MachinePointerInfo::getGOT(), false, false, false, 0);
8030 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
8031 // Create the TargetBlockAddressAddress node.
8032 unsigned char OpFlags =
8033 Subtarget->ClassifyBlockAddressReference();
8034 CodeModel::Model M = getTargetMachine().getCodeModel();
8035 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
8036 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
8038 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
8041 if (Subtarget->isPICStyleRIPRel() &&
8042 (M == CodeModel::Small || M == CodeModel::Kernel))
8043 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
8045 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
8047 // With PIC, the address is actually $g + Offset.
8048 if (isGlobalRelativeToPICBase(OpFlags)) {
8049 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
8050 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
8058 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
8059 int64_t Offset, SelectionDAG &DAG) const {
8060 // Create the TargetGlobalAddress node, folding in the constant
8061 // offset if it is legal.
8062 unsigned char OpFlags =
8063 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
8064 CodeModel::Model M = getTargetMachine().getCodeModel();
8066 if (OpFlags == X86II::MO_NO_FLAG &&
8067 X86::isOffsetSuitableForCodeModel(Offset, M)) {
8068 // A direct static reference to a global.
8069 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
8072 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
8075 if (Subtarget->isPICStyleRIPRel() &&
8076 (M == CodeModel::Small || M == CodeModel::Kernel))
8077 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
8079 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
8081 // With PIC, the address is actually $g + Offset.
8082 if (isGlobalRelativeToPICBase(OpFlags)) {
8083 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
8084 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
8088 // For globals that require a load from a stub to get the address, emit the
8090 if (isGlobalStubReference(OpFlags))
8091 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
8092 MachinePointerInfo::getGOT(), false, false, false, 0);
8094 // If there was a non-zero offset that we didn't fold, create an explicit
8097 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
8098 DAG.getConstant(Offset, getPointerTy()));
8104 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
8105 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
8106 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
8107 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
8111 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
8112 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
8113 unsigned char OperandFlags, bool LocalDynamic = false) {
8114 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
8115 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
8117 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
8118 GA->getValueType(0),
8122 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
8126 SDValue Ops[] = { Chain, TGA, *InFlag };
8127 Chain = DAG.getNode(CallType, dl, NodeTys, Ops, array_lengthof(Ops));
8129 SDValue Ops[] = { Chain, TGA };
8130 Chain = DAG.getNode(CallType, dl, NodeTys, Ops, array_lengthof(Ops));
8133 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
8134 MFI->setAdjustsStack(true);
8136 SDValue Flag = Chain.getValue(1);
8137 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
8140 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
8142 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
8145 SDLoc dl(GA); // ? function entry point might be better
8146 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
8147 DAG.getNode(X86ISD::GlobalBaseReg,
8148 SDLoc(), PtrVT), InFlag);
8149 InFlag = Chain.getValue(1);
8151 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
8154 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
8156 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
8158 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
8159 X86::RAX, X86II::MO_TLSGD);
8162 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
8168 // Get the start address of the TLS block for this module.
8169 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
8170 .getInfo<X86MachineFunctionInfo>();
8171 MFI->incNumLocalDynamicTLSAccesses();
8175 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT, X86::RAX,
8176 X86II::MO_TLSLD, /*LocalDynamic=*/true);
8179 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
8180 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
8181 InFlag = Chain.getValue(1);
8182 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
8183 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
8186 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
8190 unsigned char OperandFlags = X86II::MO_DTPOFF;
8191 unsigned WrapperKind = X86ISD::Wrapper;
8192 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
8193 GA->getValueType(0),
8194 GA->getOffset(), OperandFlags);
8195 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
8197 // Add x@dtpoff with the base.
8198 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
8201 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
8202 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
8203 const EVT PtrVT, TLSModel::Model model,
8204 bool is64Bit, bool isPIC) {
8207 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
8208 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
8209 is64Bit ? 257 : 256));
8211 SDValue ThreadPointer =
8212 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0),
8213 MachinePointerInfo(Ptr), false, false, false, 0);
8215 unsigned char OperandFlags = 0;
8216 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
8218 unsigned WrapperKind = X86ISD::Wrapper;
8219 if (model == TLSModel::LocalExec) {
8220 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
8221 } else if (model == TLSModel::InitialExec) {
8223 OperandFlags = X86II::MO_GOTTPOFF;
8224 WrapperKind = X86ISD::WrapperRIP;
8226 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
8229 llvm_unreachable("Unexpected model");
8232 // emit "addl x@ntpoff,%eax" (local exec)
8233 // or "addl x@indntpoff,%eax" (initial exec)
8234 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
8236 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
8237 GA->getOffset(), OperandFlags);
8238 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
8240 if (model == TLSModel::InitialExec) {
8241 if (isPIC && !is64Bit) {
8242 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
8243 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
8247 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
8248 MachinePointerInfo::getGOT(), false, false, false, 0);
8251 // The address of the thread local variable is the add of the thread
8252 // pointer with the offset of the variable.
8253 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
8257 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
8259 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
8260 const GlobalValue *GV = GA->getGlobal();
8262 if (Subtarget->isTargetELF()) {
8263 TLSModel::Model model = getTargetMachine().getTLSModel(GV);
8266 case TLSModel::GeneralDynamic:
8267 if (Subtarget->is64Bit())
8268 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
8269 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
8270 case TLSModel::LocalDynamic:
8271 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
8272 Subtarget->is64Bit());
8273 case TLSModel::InitialExec:
8274 case TLSModel::LocalExec:
8275 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
8276 Subtarget->is64Bit(),
8277 getTargetMachine().getRelocationModel() == Reloc::PIC_);
8279 llvm_unreachable("Unknown TLS model.");
8282 if (Subtarget->isTargetDarwin()) {
8283 // Darwin only has one model of TLS. Lower to that.
8284 unsigned char OpFlag = 0;
8285 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
8286 X86ISD::WrapperRIP : X86ISD::Wrapper;
8288 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
8290 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) &&
8291 !Subtarget->is64Bit();
8293 OpFlag = X86II::MO_TLVP_PIC_BASE;
8295 OpFlag = X86II::MO_TLVP;
8297 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
8298 GA->getValueType(0),
8299 GA->getOffset(), OpFlag);
8300 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
8302 // With PIC32, the address is actually $g + Offset.
8304 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8305 DAG.getNode(X86ISD::GlobalBaseReg,
8306 SDLoc(), getPointerTy()),
8309 // Lowering the machine isd will make sure everything is in the right
8311 SDValue Chain = DAG.getEntryNode();
8312 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
8313 SDValue Args[] = { Chain, Offset };
8314 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2);
8316 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
8317 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
8318 MFI->setAdjustsStack(true);
8320 // And our return value (tls address) is in the standard call return value
8322 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
8323 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
8327 if (Subtarget->isTargetWindows() || Subtarget->isTargetMingw()) {
8328 // Just use the implicit TLS architecture
8329 // Need to generate someting similar to:
8330 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
8332 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
8333 // mov rcx, qword [rdx+rcx*8]
8334 // mov eax, .tls$:tlsvar
8335 // [rax+rcx] contains the address
8336 // Windows 64bit: gs:0x58
8337 // Windows 32bit: fs:__tls_array
8339 // If GV is an alias then use the aliasee for determining
8340 // thread-localness.
8341 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
8342 GV = GA->resolveAliasedGlobal(false);
8344 SDValue Chain = DAG.getEntryNode();
8346 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
8347 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
8348 // use its literal value of 0x2C.
8349 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
8350 ? Type::getInt8PtrTy(*DAG.getContext(),
8352 : Type::getInt32PtrTy(*DAG.getContext(),
8355 SDValue TlsArray = Subtarget->is64Bit() ? DAG.getIntPtrConstant(0x58) :
8356 (Subtarget->isTargetMingw() ? DAG.getIntPtrConstant(0x2C) :
8357 DAG.getExternalSymbol("_tls_array", getPointerTy()));
8359 SDValue ThreadPointer = DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
8360 MachinePointerInfo(Ptr),
8361 false, false, false, 0);
8363 // Load the _tls_index variable
8364 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
8365 if (Subtarget->is64Bit())
8366 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
8367 IDX, MachinePointerInfo(), MVT::i32,
8370 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
8371 false, false, false, 0);
8373 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
8375 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
8377 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
8378 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
8379 false, false, false, 0);
8381 // Get the offset of start of .tls section
8382 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
8383 GA->getValueType(0),
8384 GA->getOffset(), X86II::MO_SECREL);
8385 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
8387 // The address of the thread local variable is the add of the thread
8388 // pointer with the offset of the variable.
8389 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
8392 llvm_unreachable("TLS not implemented for this target.");
8395 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
8396 /// and take a 2 x i32 value to shift plus a shift amount.
8397 SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const{
8398 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
8399 EVT VT = Op.getValueType();
8400 unsigned VTBits = VT.getSizeInBits();
8402 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
8403 SDValue ShOpLo = Op.getOperand(0);
8404 SDValue ShOpHi = Op.getOperand(1);
8405 SDValue ShAmt = Op.getOperand(2);
8406 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
8407 DAG.getConstant(VTBits - 1, MVT::i8))
8408 : DAG.getConstant(0, VT);
8411 if (Op.getOpcode() == ISD::SHL_PARTS) {
8412 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
8413 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
8415 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
8416 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
8419 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
8420 DAG.getConstant(VTBits, MVT::i8));
8421 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
8422 AndNode, DAG.getConstant(0, MVT::i8));
8425 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8426 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
8427 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
8429 if (Op.getOpcode() == ISD::SHL_PARTS) {
8430 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
8431 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
8433 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
8434 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
8437 SDValue Ops[2] = { Lo, Hi };
8438 return DAG.getMergeValues(Ops, array_lengthof(Ops), dl);
8441 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
8442 SelectionDAG &DAG) const {
8443 EVT SrcVT = Op.getOperand(0).getValueType();
8445 if (SrcVT.isVector())
8448 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
8449 "Unknown SINT_TO_FP to lower!");
8451 // These are really Legal; return the operand so the caller accepts it as
8453 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
8455 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
8456 Subtarget->is64Bit()) {
8461 unsigned Size = SrcVT.getSizeInBits()/8;
8462 MachineFunction &MF = DAG.getMachineFunction();
8463 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
8464 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8465 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
8467 MachinePointerInfo::getFixedStack(SSFI),
8469 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
8472 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
8474 SelectionDAG &DAG) const {
8478 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
8480 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
8482 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
8484 unsigned ByteSize = SrcVT.getSizeInBits()/8;
8486 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
8487 MachineMemOperand *MMO;
8489 int SSFI = FI->getIndex();
8491 DAG.getMachineFunction()
8492 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8493 MachineMemOperand::MOLoad, ByteSize, ByteSize);
8495 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
8496 StackSlot = StackSlot.getOperand(1);
8498 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
8499 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
8501 Tys, Ops, array_lengthof(Ops),
8505 Chain = Result.getValue(1);
8506 SDValue InFlag = Result.getValue(2);
8508 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
8509 // shouldn't be necessary except that RFP cannot be live across
8510 // multiple blocks. When stackifier is fixed, they can be uncoupled.
8511 MachineFunction &MF = DAG.getMachineFunction();
8512 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
8513 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
8514 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8515 Tys = DAG.getVTList(MVT::Other);
8517 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
8519 MachineMemOperand *MMO =
8520 DAG.getMachineFunction()
8521 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8522 MachineMemOperand::MOStore, SSFISize, SSFISize);
8524 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
8525 Ops, array_lengthof(Ops),
8526 Op.getValueType(), MMO);
8527 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
8528 MachinePointerInfo::getFixedStack(SSFI),
8529 false, false, false, 0);
8535 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
8536 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
8537 SelectionDAG &DAG) const {
8538 // This algorithm is not obvious. Here it is what we're trying to output:
8541 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
8542 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
8546 pshufd $0x4e, %xmm0, %xmm1
8552 LLVMContext *Context = DAG.getContext();
8554 // Build some magic constants.
8555 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
8556 Constant *C0 = ConstantDataVector::get(*Context, CV0);
8557 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
8559 SmallVector<Constant*,2> CV1;
8561 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
8562 APInt(64, 0x4330000000000000ULL))));
8564 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
8565 APInt(64, 0x4530000000000000ULL))));
8566 Constant *C1 = ConstantVector::get(CV1);
8567 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
8569 // Load the 64-bit value into an XMM register.
8570 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
8572 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
8573 MachinePointerInfo::getConstantPool(),
8574 false, false, false, 16);
8575 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
8576 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
8579 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
8580 MachinePointerInfo::getConstantPool(),
8581 false, false, false, 16);
8582 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
8583 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
8586 if (Subtarget->hasSSE3()) {
8587 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
8588 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
8590 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
8591 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
8593 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
8594 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
8598 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
8599 DAG.getIntPtrConstant(0));
8602 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
8603 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
8604 SelectionDAG &DAG) const {
8606 // FP constant to bias correct the final result.
8607 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
8610 // Load the 32-bit value into an XMM register.
8611 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
8614 // Zero out the upper parts of the register.
8615 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
8617 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
8618 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
8619 DAG.getIntPtrConstant(0));
8621 // Or the load with the bias.
8622 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
8623 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
8624 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
8626 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
8627 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
8628 MVT::v2f64, Bias)));
8629 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
8630 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
8631 DAG.getIntPtrConstant(0));
8633 // Subtract the bias.
8634 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
8636 // Handle final rounding.
8637 EVT DestVT = Op.getValueType();
8639 if (DestVT.bitsLT(MVT::f64))
8640 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
8641 DAG.getIntPtrConstant(0));
8642 if (DestVT.bitsGT(MVT::f64))
8643 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
8645 // Handle final rounding.
8649 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
8650 SelectionDAG &DAG) const {
8651 SDValue N0 = Op.getOperand(0);
8652 EVT SVT = N0.getValueType();
8655 assert((SVT == MVT::v4i8 || SVT == MVT::v4i16 ||
8656 SVT == MVT::v8i8 || SVT == MVT::v8i16) &&
8657 "Custom UINT_TO_FP is not supported!");
8659 EVT NVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
8660 SVT.getVectorNumElements());
8661 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
8662 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
8665 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
8666 SelectionDAG &DAG) const {
8667 SDValue N0 = Op.getOperand(0);
8670 if (Op.getValueType().isVector())
8671 return lowerUINT_TO_FP_vec(Op, DAG);
8673 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
8674 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
8675 // the optimization here.
8676 if (DAG.SignBitIsZero(N0))
8677 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
8679 EVT SrcVT = N0.getValueType();
8680 EVT DstVT = Op.getValueType();
8681 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
8682 return LowerUINT_TO_FP_i64(Op, DAG);
8683 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
8684 return LowerUINT_TO_FP_i32(Op, DAG);
8685 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
8688 // Make a 64-bit buffer, and use it to build an FILD.
8689 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
8690 if (SrcVT == MVT::i32) {
8691 SDValue WordOff = DAG.getConstant(4, getPointerTy());
8692 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
8693 getPointerTy(), StackSlot, WordOff);
8694 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
8695 StackSlot, MachinePointerInfo(),
8697 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
8698 OffsetSlot, MachinePointerInfo(),
8700 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
8704 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
8705 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
8706 StackSlot, MachinePointerInfo(),
8708 // For i64 source, we need to add the appropriate power of 2 if the input
8709 // was negative. This is the same as the optimization in
8710 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
8711 // we must be careful to do the computation in x87 extended precision, not
8712 // in SSE. (The generic code can't know it's OK to do this, or how to.)
8713 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
8714 MachineMemOperand *MMO =
8715 DAG.getMachineFunction()
8716 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8717 MachineMemOperand::MOLoad, 8, 8);
8719 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
8720 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
8721 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
8722 array_lengthof(Ops), MVT::i64, MMO);
8724 APInt FF(32, 0x5F800000ULL);
8726 // Check whether the sign bit is set.
8727 SDValue SignSet = DAG.getSetCC(dl,
8728 getSetCCResultType(*DAG.getContext(), MVT::i64),
8729 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
8732 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
8733 SDValue FudgePtr = DAG.getConstantPool(
8734 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
8737 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
8738 SDValue Zero = DAG.getIntPtrConstant(0);
8739 SDValue Four = DAG.getIntPtrConstant(4);
8740 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
8742 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
8744 // Load the value out, extending it from f32 to f80.
8745 // FIXME: Avoid the extend by constructing the right constant pool?
8746 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
8747 FudgePtr, MachinePointerInfo::getConstantPool(),
8748 MVT::f32, false, false, 4);
8749 // Extend everything to 80 bits to force it to be done on x87.
8750 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
8751 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
8754 std::pair<SDValue,SDValue>
8755 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
8756 bool IsSigned, bool IsReplace) const {
8759 EVT DstTy = Op.getValueType();
8761 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
8762 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
8766 assert(DstTy.getSimpleVT() <= MVT::i64 &&
8767 DstTy.getSimpleVT() >= MVT::i16 &&
8768 "Unknown FP_TO_INT to lower!");
8770 // These are really Legal.
8771 if (DstTy == MVT::i32 &&
8772 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
8773 return std::make_pair(SDValue(), SDValue());
8774 if (Subtarget->is64Bit() &&
8775 DstTy == MVT::i64 &&
8776 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
8777 return std::make_pair(SDValue(), SDValue());
8779 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
8780 // stack slot, or into the FTOL runtime function.
8781 MachineFunction &MF = DAG.getMachineFunction();
8782 unsigned MemSize = DstTy.getSizeInBits()/8;
8783 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
8784 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8787 if (!IsSigned && isIntegerTypeFTOL(DstTy))
8788 Opc = X86ISD::WIN_FTOL;
8790 switch (DstTy.getSimpleVT().SimpleTy) {
8791 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
8792 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
8793 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
8794 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
8797 SDValue Chain = DAG.getEntryNode();
8798 SDValue Value = Op.getOperand(0);
8799 EVT TheVT = Op.getOperand(0).getValueType();
8800 // FIXME This causes a redundant load/store if the SSE-class value is already
8801 // in memory, such as if it is on the callstack.
8802 if (isScalarFPTypeInSSEReg(TheVT)) {
8803 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
8804 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
8805 MachinePointerInfo::getFixedStack(SSFI),
8807 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
8809 Chain, StackSlot, DAG.getValueType(TheVT)
8812 MachineMemOperand *MMO =
8813 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8814 MachineMemOperand::MOLoad, MemSize, MemSize);
8815 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops,
8816 array_lengthof(Ops), DstTy, MMO);
8817 Chain = Value.getValue(1);
8818 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
8819 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8822 MachineMemOperand *MMO =
8823 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8824 MachineMemOperand::MOStore, MemSize, MemSize);
8826 if (Opc != X86ISD::WIN_FTOL) {
8827 // Build the FP_TO_INT*_IN_MEM
8828 SDValue Ops[] = { Chain, Value, StackSlot };
8829 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
8830 Ops, array_lengthof(Ops), DstTy,
8832 return std::make_pair(FIST, StackSlot);
8834 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
8835 DAG.getVTList(MVT::Other, MVT::Glue),
8837 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
8838 MVT::i32, ftol.getValue(1));
8839 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
8840 MVT::i32, eax.getValue(2));
8841 SDValue Ops[] = { eax, edx };
8842 SDValue pair = IsReplace
8843 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops, array_lengthof(Ops))
8844 : DAG.getMergeValues(Ops, array_lengthof(Ops), DL);
8845 return std::make_pair(pair, SDValue());
8849 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
8850 const X86Subtarget *Subtarget) {
8851 MVT VT = Op->getSimpleValueType(0);
8852 SDValue In = Op->getOperand(0);
8853 MVT InVT = In.getSimpleValueType();
8856 // Optimize vectors in AVX mode:
8859 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
8860 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
8861 // Concat upper and lower parts.
8864 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
8865 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
8866 // Concat upper and lower parts.
8869 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
8870 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
8871 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
8874 if (Subtarget->hasInt256())
8875 return DAG.getNode(X86ISD::VZEXT_MOVL, dl, VT, In);
8877 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
8878 SDValue Undef = DAG.getUNDEF(InVT);
8879 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
8880 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
8881 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
8883 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
8884 VT.getVectorNumElements()/2);
8886 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
8887 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
8889 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
8892 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
8893 SelectionDAG &DAG) {
8894 MVT VT = Op->getValueType(0).getSimpleVT();
8895 SDValue In = Op->getOperand(0);
8896 MVT InVT = In.getValueType().getSimpleVT();
8898 unsigned int NumElts = VT.getVectorNumElements();
8899 if (NumElts != 8 && NumElts != 16)
8902 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
8903 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
8905 EVT ExtVT = (NumElts == 8)? MVT::v8i64 : MVT::v16i32;
8906 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8907 // Now we have only mask extension
8908 assert(InVT.getVectorElementType() == MVT::i1);
8909 SDValue Cst = DAG.getTargetConstant(1, ExtVT.getScalarType());
8910 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
8911 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
8912 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
8913 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
8914 MachinePointerInfo::getConstantPool(),
8915 false, false, false, Alignment);
8917 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, DL, ExtVT, In, Ld);
8918 if (VT.is512BitVector())
8920 return DAG.getNode(X86ISD::VTRUNC, DL, VT, Brcst);
8923 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
8924 SelectionDAG &DAG) {
8925 if (Subtarget->hasFp256()) {
8926 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
8934 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
8935 SelectionDAG &DAG) {
8937 MVT VT = Op.getSimpleValueType();
8938 SDValue In = Op.getOperand(0);
8939 MVT SVT = In.getSimpleValueType();
8941 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
8942 return LowerZERO_EXTEND_AVX512(Op, DAG);
8944 if (Subtarget->hasFp256()) {
8945 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
8950 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
8951 VT.getVectorNumElements() != SVT.getVectorNumElements());
8955 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
8957 MVT VT = Op.getSimpleValueType();
8958 SDValue In = Op.getOperand(0);
8959 MVT InVT = In.getSimpleValueType();
8960 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
8961 "Invalid TRUNCATE operation");
8963 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
8964 if (VT.getVectorElementType().getSizeInBits() >=8)
8965 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
8967 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
8968 unsigned NumElts = InVT.getVectorNumElements();
8969 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
8970 if (InVT.getSizeInBits() < 512) {
8971 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
8972 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
8975 SDValue Cst = DAG.getTargetConstant(1, InVT.getVectorElementType());
8976 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
8977 SDValue CP = DAG.getConstantPool(C, getPointerTy());
8978 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
8979 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
8980 MachinePointerInfo::getConstantPool(),
8981 false, false, false, Alignment);
8982 SDValue OneV = DAG.getNode(X86ISD::VBROADCAST, DL, InVT, Ld);
8983 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
8984 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
8987 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
8988 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
8989 if (Subtarget->hasInt256()) {
8990 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
8991 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
8992 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
8994 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
8995 DAG.getIntPtrConstant(0));
8998 // On AVX, v4i64 -> v4i32 becomes a sequence that uses PSHUFD and MOVLHPS.
8999 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
9000 DAG.getIntPtrConstant(0));
9001 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
9002 DAG.getIntPtrConstant(2));
9004 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
9005 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
9008 static const int ShufMask1[] = {0, 2, 0, 0};
9009 SDValue Undef = DAG.getUNDEF(VT);
9010 OpLo = DAG.getVectorShuffle(VT, DL, OpLo, Undef, ShufMask1);
9011 OpHi = DAG.getVectorShuffle(VT, DL, OpHi, Undef, ShufMask1);
9013 // The MOVLHPS mask:
9014 static const int ShufMask2[] = {0, 1, 4, 5};
9015 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask2);
9018 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
9019 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
9020 if (Subtarget->hasInt256()) {
9021 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
9023 SmallVector<SDValue,32> pshufbMask;
9024 for (unsigned i = 0; i < 2; ++i) {
9025 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
9026 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
9027 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
9028 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
9029 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
9030 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
9031 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
9032 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
9033 for (unsigned j = 0; j < 8; ++j)
9034 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
9036 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8,
9037 &pshufbMask[0], 32);
9038 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
9039 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
9041 static const int ShufMask[] = {0, 2, -1, -1};
9042 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
9044 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
9045 DAG.getIntPtrConstant(0));
9046 return DAG.getNode(ISD::BITCAST, DL, VT, In);
9049 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
9050 DAG.getIntPtrConstant(0));
9052 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
9053 DAG.getIntPtrConstant(4));
9055 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
9056 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
9059 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
9060 -1, -1, -1, -1, -1, -1, -1, -1};
9062 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
9063 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
9064 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
9066 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
9067 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
9069 // The MOVLHPS Mask:
9070 static const int ShufMask2[] = {0, 1, 4, 5};
9071 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
9072 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
9075 // Handle truncation of V256 to V128 using shuffles.
9076 if (!VT.is128BitVector() || !InVT.is256BitVector())
9079 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
9081 unsigned NumElems = VT.getVectorNumElements();
9082 EVT NVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
9085 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
9086 // Prepare truncation shuffle mask
9087 for (unsigned i = 0; i != NumElems; ++i)
9089 SDValue V = DAG.getVectorShuffle(NVT, DL,
9090 DAG.getNode(ISD::BITCAST, DL, NVT, In),
9091 DAG.getUNDEF(NVT), &MaskVec[0]);
9092 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
9093 DAG.getIntPtrConstant(0));
9096 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
9097 SelectionDAG &DAG) const {
9098 MVT VT = Op.getSimpleValueType();
9099 if (VT.isVector()) {
9100 if (VT == MVT::v8i16)
9101 return DAG.getNode(ISD::TRUNCATE, SDLoc(Op), VT,
9102 DAG.getNode(ISD::FP_TO_SINT, SDLoc(Op),
9103 MVT::v8i32, Op.getOperand(0)));
9107 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
9108 /*IsSigned=*/ true, /*IsReplace=*/ false);
9109 SDValue FIST = Vals.first, StackSlot = Vals.second;
9110 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
9111 if (FIST.getNode() == 0) return Op;
9113 if (StackSlot.getNode())
9115 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
9116 FIST, StackSlot, MachinePointerInfo(),
9117 false, false, false, 0);
9119 // The node is the result.
9123 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
9124 SelectionDAG &DAG) const {
9125 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
9126 /*IsSigned=*/ false, /*IsReplace=*/ false);
9127 SDValue FIST = Vals.first, StackSlot = Vals.second;
9128 assert(FIST.getNode() && "Unexpected failure");
9130 if (StackSlot.getNode())
9132 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
9133 FIST, StackSlot, MachinePointerInfo(),
9134 false, false, false, 0);
9136 // The node is the result.
9140 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
9142 MVT VT = Op.getSimpleValueType();
9143 SDValue In = Op.getOperand(0);
9144 MVT SVT = In.getSimpleValueType();
9146 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
9148 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
9149 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
9150 In, DAG.getUNDEF(SVT)));
9153 SDValue X86TargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) const {
9154 LLVMContext *Context = DAG.getContext();
9156 MVT VT = Op.getSimpleValueType();
9158 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
9159 if (VT.isVector()) {
9160 EltVT = VT.getVectorElementType();
9161 NumElts = VT.getVectorNumElements();
9164 if (EltVT == MVT::f64)
9165 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
9166 APInt(64, ~(1ULL << 63))));
9168 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEsingle,
9169 APInt(32, ~(1U << 31))));
9170 C = ConstantVector::getSplat(NumElts, C);
9171 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy());
9172 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
9173 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9174 MachinePointerInfo::getConstantPool(),
9175 false, false, false, Alignment);
9176 if (VT.isVector()) {
9177 MVT ANDVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
9178 return DAG.getNode(ISD::BITCAST, dl, VT,
9179 DAG.getNode(ISD::AND, dl, ANDVT,
9180 DAG.getNode(ISD::BITCAST, dl, ANDVT,
9182 DAG.getNode(ISD::BITCAST, dl, ANDVT, Mask)));
9184 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
9187 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const {
9188 LLVMContext *Context = DAG.getContext();
9190 MVT VT = Op.getSimpleValueType();
9192 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
9193 if (VT.isVector()) {
9194 EltVT = VT.getVectorElementType();
9195 NumElts = VT.getVectorNumElements();
9198 if (EltVT == MVT::f64)
9199 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
9200 APInt(64, 1ULL << 63)));
9202 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEsingle,
9203 APInt(32, 1U << 31)));
9204 C = ConstantVector::getSplat(NumElts, C);
9205 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy());
9206 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
9207 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9208 MachinePointerInfo::getConstantPool(),
9209 false, false, false, Alignment);
9210 if (VT.isVector()) {
9211 MVT XORVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits()/64);
9212 return DAG.getNode(ISD::BITCAST, dl, VT,
9213 DAG.getNode(ISD::XOR, dl, XORVT,
9214 DAG.getNode(ISD::BITCAST, dl, XORVT,
9216 DAG.getNode(ISD::BITCAST, dl, XORVT, Mask)));
9219 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
9222 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
9223 LLVMContext *Context = DAG.getContext();
9224 SDValue Op0 = Op.getOperand(0);
9225 SDValue Op1 = Op.getOperand(1);
9227 MVT VT = Op.getSimpleValueType();
9228 MVT SrcVT = Op1.getSimpleValueType();
9230 // If second operand is smaller, extend it first.
9231 if (SrcVT.bitsLT(VT)) {
9232 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
9235 // And if it is bigger, shrink it first.
9236 if (SrcVT.bitsGT(VT)) {
9237 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
9241 // At this point the operands and the result should have the same
9242 // type, and that won't be f80 since that is not custom lowered.
9244 // First get the sign bit of second operand.
9245 SmallVector<Constant*,4> CV;
9246 if (SrcVT == MVT::f64) {
9247 const fltSemantics &Sem = APFloat::IEEEdouble;
9248 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 1ULL << 63))));
9249 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
9251 const fltSemantics &Sem = APFloat::IEEEsingle;
9252 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 1U << 31))));
9253 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9254 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9255 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9257 Constant *C = ConstantVector::get(CV);
9258 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
9259 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
9260 MachinePointerInfo::getConstantPool(),
9261 false, false, false, 16);
9262 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
9264 // Shift sign bit right or left if the two operands have different types.
9265 if (SrcVT.bitsGT(VT)) {
9266 // Op0 is MVT::f32, Op1 is MVT::f64.
9267 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
9268 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
9269 DAG.getConstant(32, MVT::i32));
9270 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
9271 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
9272 DAG.getIntPtrConstant(0));
9275 // Clear first operand sign bit.
9277 if (VT == MVT::f64) {
9278 const fltSemantics &Sem = APFloat::IEEEdouble;
9279 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
9280 APInt(64, ~(1ULL << 63)))));
9281 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
9283 const fltSemantics &Sem = APFloat::IEEEsingle;
9284 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
9285 APInt(32, ~(1U << 31)))));
9286 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9287 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9288 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9290 C = ConstantVector::get(CV);
9291 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
9292 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9293 MachinePointerInfo::getConstantPool(),
9294 false, false, false, 16);
9295 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
9297 // Or the value with the sign bit.
9298 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
9301 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
9302 SDValue N0 = Op.getOperand(0);
9304 MVT VT = Op.getSimpleValueType();
9306 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
9307 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
9308 DAG.getConstant(1, VT));
9309 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
9312 // LowerVectorAllZeroTest - Check whether an OR'd tree is PTEST-able.
9314 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
9315 SelectionDAG &DAG) {
9316 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
9318 if (!Subtarget->hasSSE41())
9321 if (!Op->hasOneUse())
9324 SDNode *N = Op.getNode();
9327 SmallVector<SDValue, 8> Opnds;
9328 DenseMap<SDValue, unsigned> VecInMap;
9329 EVT VT = MVT::Other;
9331 // Recognize a special case where a vector is casted into wide integer to
9333 Opnds.push_back(N->getOperand(0));
9334 Opnds.push_back(N->getOperand(1));
9336 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
9337 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
9338 // BFS traverse all OR'd operands.
9339 if (I->getOpcode() == ISD::OR) {
9340 Opnds.push_back(I->getOperand(0));
9341 Opnds.push_back(I->getOperand(1));
9342 // Re-evaluate the number of nodes to be traversed.
9343 e += 2; // 2 more nodes (LHS and RHS) are pushed.
9347 // Quit if a non-EXTRACT_VECTOR_ELT
9348 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
9351 // Quit if without a constant index.
9352 SDValue Idx = I->getOperand(1);
9353 if (!isa<ConstantSDNode>(Idx))
9356 SDValue ExtractedFromVec = I->getOperand(0);
9357 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
9358 if (M == VecInMap.end()) {
9359 VT = ExtractedFromVec.getValueType();
9360 // Quit if not 128/256-bit vector.
9361 if (!VT.is128BitVector() && !VT.is256BitVector())
9363 // Quit if not the same type.
9364 if (VecInMap.begin() != VecInMap.end() &&
9365 VT != VecInMap.begin()->first.getValueType())
9367 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
9369 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
9372 assert((VT.is128BitVector() || VT.is256BitVector()) &&
9373 "Not extracted from 128-/256-bit vector.");
9375 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
9376 SmallVector<SDValue, 8> VecIns;
9378 for (DenseMap<SDValue, unsigned>::const_iterator
9379 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
9380 // Quit if not all elements are used.
9381 if (I->second != FullMask)
9383 VecIns.push_back(I->first);
9386 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
9388 // Cast all vectors into TestVT for PTEST.
9389 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
9390 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
9392 // If more than one full vectors are evaluated, OR them first before PTEST.
9393 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
9394 // Each iteration will OR 2 nodes and append the result until there is only
9395 // 1 node left, i.e. the final OR'd value of all vectors.
9396 SDValue LHS = VecIns[Slot];
9397 SDValue RHS = VecIns[Slot + 1];
9398 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
9401 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
9402 VecIns.back(), VecIns.back());
9405 /// Emit nodes that will be selected as "test Op0,Op0", or something
9407 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
9408 SelectionDAG &DAG) const {
9411 // CF and OF aren't always set the way we want. Determine which
9412 // of these we need.
9413 bool NeedCF = false;
9414 bool NeedOF = false;
9417 case X86::COND_A: case X86::COND_AE:
9418 case X86::COND_B: case X86::COND_BE:
9421 case X86::COND_G: case X86::COND_GE:
9422 case X86::COND_L: case X86::COND_LE:
9423 case X86::COND_O: case X86::COND_NO:
9428 // See if we can use the EFLAGS value from the operand instead of
9429 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
9430 // we prove that the arithmetic won't overflow, we can't use OF or CF.
9431 if (Op.getResNo() != 0 || NeedOF || NeedCF)
9432 // Emit a CMP with 0, which is the TEST pattern.
9433 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
9434 DAG.getConstant(0, Op.getValueType()));
9436 unsigned Opcode = 0;
9437 unsigned NumOperands = 0;
9439 // Truncate operations may prevent the merge of the SETCC instruction
9440 // and the arithmetic instruction before it. Attempt to truncate the operands
9441 // of the arithmetic instruction and use a reduced bit-width instruction.
9442 bool NeedTruncation = false;
9443 SDValue ArithOp = Op;
9444 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
9445 SDValue Arith = Op->getOperand(0);
9446 // Both the trunc and the arithmetic op need to have one user each.
9447 if (Arith->hasOneUse())
9448 switch (Arith.getOpcode()) {
9455 NeedTruncation = true;
9461 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
9462 // which may be the result of a CAST. We use the variable 'Op', which is the
9463 // non-casted variable when we check for possible users.
9464 switch (ArithOp.getOpcode()) {
9466 // Due to an isel shortcoming, be conservative if this add is likely to be
9467 // selected as part of a load-modify-store instruction. When the root node
9468 // in a match is a store, isel doesn't know how to remap non-chain non-flag
9469 // uses of other nodes in the match, such as the ADD in this case. This
9470 // leads to the ADD being left around and reselected, with the result being
9471 // two adds in the output. Alas, even if none our users are stores, that
9472 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
9473 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
9474 // climbing the DAG back to the root, and it doesn't seem to be worth the
9476 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
9477 UE = Op.getNode()->use_end(); UI != UE; ++UI)
9478 if (UI->getOpcode() != ISD::CopyToReg &&
9479 UI->getOpcode() != ISD::SETCC &&
9480 UI->getOpcode() != ISD::STORE)
9483 if (ConstantSDNode *C =
9484 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
9485 // An add of one will be selected as an INC.
9486 if (C->getAPIntValue() == 1) {
9487 Opcode = X86ISD::INC;
9492 // An add of negative one (subtract of one) will be selected as a DEC.
9493 if (C->getAPIntValue().isAllOnesValue()) {
9494 Opcode = X86ISD::DEC;
9500 // Otherwise use a regular EFLAGS-setting add.
9501 Opcode = X86ISD::ADD;
9505 // If the primary and result isn't used, don't bother using X86ISD::AND,
9506 // because a TEST instruction will be better.
9507 bool NonFlagUse = false;
9508 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
9509 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
9511 unsigned UOpNo = UI.getOperandNo();
9512 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
9513 // Look pass truncate.
9514 UOpNo = User->use_begin().getOperandNo();
9515 User = *User->use_begin();
9518 if (User->getOpcode() != ISD::BRCOND &&
9519 User->getOpcode() != ISD::SETCC &&
9520 !(User->getOpcode() == ISD::SELECT && UOpNo == 0)) {
9533 // Due to the ISEL shortcoming noted above, be conservative if this op is
9534 // likely to be selected as part of a load-modify-store instruction.
9535 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
9536 UE = Op.getNode()->use_end(); UI != UE; ++UI)
9537 if (UI->getOpcode() == ISD::STORE)
9540 // Otherwise use a regular EFLAGS-setting instruction.
9541 switch (ArithOp.getOpcode()) {
9542 default: llvm_unreachable("unexpected operator!");
9543 case ISD::SUB: Opcode = X86ISD::SUB; break;
9544 case ISD::XOR: Opcode = X86ISD::XOR; break;
9545 case ISD::AND: Opcode = X86ISD::AND; break;
9547 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
9548 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
9549 if (EFLAGS.getNode())
9552 Opcode = X86ISD::OR;
9566 return SDValue(Op.getNode(), 1);
9572 // If we found that truncation is beneficial, perform the truncation and
9574 if (NeedTruncation) {
9575 EVT VT = Op.getValueType();
9576 SDValue WideVal = Op->getOperand(0);
9577 EVT WideVT = WideVal.getValueType();
9578 unsigned ConvertedOp = 0;
9579 // Use a target machine opcode to prevent further DAGCombine
9580 // optimizations that may separate the arithmetic operations
9581 // from the setcc node.
9582 switch (WideVal.getOpcode()) {
9584 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
9585 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
9586 case ISD::AND: ConvertedOp = X86ISD::AND; break;
9587 case ISD::OR: ConvertedOp = X86ISD::OR; break;
9588 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
9592 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9593 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
9594 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
9595 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
9596 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
9602 // Emit a CMP with 0, which is the TEST pattern.
9603 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
9604 DAG.getConstant(0, Op.getValueType()));
9606 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
9607 SmallVector<SDValue, 4> Ops;
9608 for (unsigned i = 0; i != NumOperands; ++i)
9609 Ops.push_back(Op.getOperand(i));
9611 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
9612 DAG.ReplaceAllUsesWith(Op, New);
9613 return SDValue(New.getNode(), 1);
9616 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
9618 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
9619 SelectionDAG &DAG) const {
9620 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
9621 if (C->getAPIntValue() == 0)
9622 return EmitTest(Op0, X86CC, DAG);
9625 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
9626 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
9627 // Use SUB instead of CMP to enable CSE between SUB and CMP.
9628 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
9629 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
9631 return SDValue(Sub.getNode(), 1);
9633 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
9636 /// Convert a comparison if required by the subtarget.
9637 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
9638 SelectionDAG &DAG) const {
9639 // If the subtarget does not support the FUCOMI instruction, floating-point
9640 // comparisons have to be converted.
9641 if (Subtarget->hasCMov() ||
9642 Cmp.getOpcode() != X86ISD::CMP ||
9643 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
9644 !Cmp.getOperand(1).getValueType().isFloatingPoint())
9647 // The instruction selector will select an FUCOM instruction instead of
9648 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
9649 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
9650 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
9652 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
9653 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
9654 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
9655 DAG.getConstant(8, MVT::i8));
9656 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
9657 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
9660 static bool isAllOnes(SDValue V) {
9661 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
9662 return C && C->isAllOnesValue();
9665 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
9666 /// if it's possible.
9667 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
9668 SDLoc dl, SelectionDAG &DAG) const {
9669 SDValue Op0 = And.getOperand(0);
9670 SDValue Op1 = And.getOperand(1);
9671 if (Op0.getOpcode() == ISD::TRUNCATE)
9672 Op0 = Op0.getOperand(0);
9673 if (Op1.getOpcode() == ISD::TRUNCATE)
9674 Op1 = Op1.getOperand(0);
9677 if (Op1.getOpcode() == ISD::SHL)
9678 std::swap(Op0, Op1);
9679 if (Op0.getOpcode() == ISD::SHL) {
9680 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
9681 if (And00C->getZExtValue() == 1) {
9682 // If we looked past a truncate, check that it's only truncating away
9684 unsigned BitWidth = Op0.getValueSizeInBits();
9685 unsigned AndBitWidth = And.getValueSizeInBits();
9686 if (BitWidth > AndBitWidth) {
9688 DAG.ComputeMaskedBits(Op0, Zeros, Ones);
9689 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
9693 RHS = Op0.getOperand(1);
9695 } else if (Op1.getOpcode() == ISD::Constant) {
9696 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
9697 uint64_t AndRHSVal = AndRHS->getZExtValue();
9698 SDValue AndLHS = Op0;
9700 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
9701 LHS = AndLHS.getOperand(0);
9702 RHS = AndLHS.getOperand(1);
9705 // Use BT if the immediate can't be encoded in a TEST instruction.
9706 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
9708 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
9712 if (LHS.getNode()) {
9713 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
9714 // instruction. Since the shift amount is in-range-or-undefined, we know
9715 // that doing a bittest on the i32 value is ok. We extend to i32 because
9716 // the encoding for the i16 version is larger than the i32 version.
9717 // Also promote i16 to i32 for performance / code size reason.
9718 if (LHS.getValueType() == MVT::i8 ||
9719 LHS.getValueType() == MVT::i16)
9720 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
9722 // If the operand types disagree, extend the shift amount to match. Since
9723 // BT ignores high bits (like shifts) we can use anyextend.
9724 if (LHS.getValueType() != RHS.getValueType())
9725 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
9727 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
9728 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
9729 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9730 DAG.getConstant(Cond, MVT::i8), BT);
9736 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
9738 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
9743 // SSE Condition code mapping:
9752 switch (SetCCOpcode) {
9753 default: llvm_unreachable("Unexpected SETCC condition");
9755 case ISD::SETEQ: SSECC = 0; break;
9757 case ISD::SETGT: Swap = true; // Fallthrough
9759 case ISD::SETOLT: SSECC = 1; break;
9761 case ISD::SETGE: Swap = true; // Fallthrough
9763 case ISD::SETOLE: SSECC = 2; break;
9764 case ISD::SETUO: SSECC = 3; break;
9766 case ISD::SETNE: SSECC = 4; break;
9767 case ISD::SETULE: Swap = true; // Fallthrough
9768 case ISD::SETUGE: SSECC = 5; break;
9769 case ISD::SETULT: Swap = true; // Fallthrough
9770 case ISD::SETUGT: SSECC = 6; break;
9771 case ISD::SETO: SSECC = 7; break;
9773 case ISD::SETONE: SSECC = 8; break;
9776 std::swap(Op0, Op1);
9781 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
9782 // ones, and then concatenate the result back.
9783 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
9784 MVT VT = Op.getSimpleValueType();
9786 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
9787 "Unsupported value type for operation");
9789 unsigned NumElems = VT.getVectorNumElements();
9791 SDValue CC = Op.getOperand(2);
9793 // Extract the LHS vectors
9794 SDValue LHS = Op.getOperand(0);
9795 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
9796 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
9798 // Extract the RHS vectors
9799 SDValue RHS = Op.getOperand(1);
9800 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
9801 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
9803 // Issue the operation on the smaller types and concatenate the result back
9804 MVT EltVT = VT.getVectorElementType();
9805 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
9806 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
9807 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
9808 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
9811 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG) {
9812 SDValue Op0 = Op.getOperand(0);
9813 SDValue Op1 = Op.getOperand(1);
9814 SDValue CC = Op.getOperand(2);
9815 MVT VT = Op.getSimpleValueType();
9817 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 32 &&
9818 Op.getValueType().getScalarType() == MVT::i1 &&
9819 "Cannot set masked compare for this operation");
9821 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
9824 bool Unsigned = false;
9826 switch (SetCCOpcode) {
9827 default: llvm_unreachable("Unexpected SETCC condition");
9828 case ISD::SETNE: SSECC = 4; break;
9829 case ISD::SETEQ: SSECC = 0; break;
9830 case ISD::SETUGT: Unsigned = true;
9831 case ISD::SETGT: SSECC = 6; break; // NLE
9832 case ISD::SETULT: Unsigned = true;
9833 case ISD::SETLT: SSECC = 1; break;
9834 case ISD::SETUGE: Unsigned = true;
9835 case ISD::SETGE: SSECC = 5; break; // NLT
9836 case ISD::SETULE: Unsigned = true;
9837 case ISD::SETLE: SSECC = 2; break;
9839 unsigned Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
9840 return DAG.getNode(Opc, dl, VT, Op0, Op1,
9841 DAG.getConstant(SSECC, MVT::i8));
9845 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
9846 SelectionDAG &DAG) {
9847 SDValue Op0 = Op.getOperand(0);
9848 SDValue Op1 = Op.getOperand(1);
9849 SDValue CC = Op.getOperand(2);
9850 MVT VT = Op.getSimpleValueType();
9851 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
9852 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
9857 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
9858 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
9861 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
9862 unsigned Opc = X86ISD::CMPP;
9863 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
9864 assert(VT.getVectorNumElements() <= 16);
9867 // In the two special cases we can't handle, emit two comparisons.
9870 unsigned CombineOpc;
9871 if (SetCCOpcode == ISD::SETUEQ) {
9872 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
9874 assert(SetCCOpcode == ISD::SETONE);
9875 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
9878 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
9879 DAG.getConstant(CC0, MVT::i8));
9880 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
9881 DAG.getConstant(CC1, MVT::i8));
9882 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
9884 // Handle all other FP comparisons here.
9885 return DAG.getNode(Opc, dl, VT, Op0, Op1,
9886 DAG.getConstant(SSECC, MVT::i8));
9889 // Break 256-bit integer vector compare into smaller ones.
9890 if (VT.is256BitVector() && !Subtarget->hasInt256())
9891 return Lower256IntVSETCC(Op, DAG);
9893 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
9894 EVT OpVT = Op1.getValueType();
9895 if (Subtarget->hasAVX512()) {
9896 if (Op1.getValueType().is512BitVector() ||
9897 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
9898 return LowerIntVSETCC_AVX512(Op, DAG);
9900 // In AVX-512 architecture setcc returns mask with i1 elements,
9901 // But there is no compare instruction for i8 and i16 elements.
9902 // We are not talking about 512-bit operands in this case, these
9903 // types are illegal.
9905 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
9906 OpVT.getVectorElementType().getSizeInBits() >= 8))
9907 return DAG.getNode(ISD::TRUNCATE, dl, VT,
9908 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
9911 // We are handling one of the integer comparisons here. Since SSE only has
9912 // GT and EQ comparisons for integer, swapping operands and multiple
9913 // operations may be required for some comparisons.
9915 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
9917 switch (SetCCOpcode) {
9918 default: llvm_unreachable("Unexpected SETCC condition");
9919 case ISD::SETNE: Invert = true;
9920 case ISD::SETEQ: Opc = MaskResult? X86ISD::PCMPEQM: X86ISD::PCMPEQ; break;
9921 case ISD::SETLT: Swap = true;
9922 case ISD::SETGT: Opc = MaskResult? X86ISD::PCMPGTM: X86ISD::PCMPGT; break;
9923 case ISD::SETGE: Swap = true;
9924 case ISD::SETLE: Opc = MaskResult? X86ISD::PCMPGTM: X86ISD::PCMPGT;
9925 Invert = true; break;
9926 case ISD::SETULT: Swap = true;
9927 case ISD::SETUGT: Opc = MaskResult? X86ISD::PCMPGTM: X86ISD::PCMPGT;
9928 FlipSigns = true; break;
9929 case ISD::SETUGE: Swap = true;
9930 case ISD::SETULE: Opc = MaskResult? X86ISD::PCMPGTM: X86ISD::PCMPGT;
9931 FlipSigns = true; Invert = true; break;
9934 // Special case: Use min/max operations for SETULE/SETUGE
9935 MVT VET = VT.getVectorElementType();
9937 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
9938 || (Subtarget->hasSSE2() && (VET == MVT::i8));
9941 switch (SetCCOpcode) {
9943 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
9944 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
9947 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
9951 std::swap(Op0, Op1);
9953 // Check that the operation in question is available (most are plain SSE2,
9954 // but PCMPGTQ and PCMPEQQ have different requirements).
9955 if (VT == MVT::v2i64) {
9956 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
9957 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
9959 // First cast everything to the right type.
9960 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
9961 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
9963 // Since SSE has no unsigned integer comparisons, we need to flip the sign
9964 // bits of the inputs before performing those operations. The lower
9965 // compare is always unsigned.
9968 SB = DAG.getConstant(0x80000000U, MVT::v4i32);
9970 SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
9971 SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
9972 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
9973 Sign, Zero, Sign, Zero);
9975 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
9976 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
9978 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
9979 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
9980 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
9982 // Create masks for only the low parts/high parts of the 64 bit integers.
9983 static const int MaskHi[] = { 1, 1, 3, 3 };
9984 static const int MaskLo[] = { 0, 0, 2, 2 };
9985 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
9986 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
9987 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
9989 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
9990 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
9993 Result = DAG.getNOT(dl, Result, MVT::v4i32);
9995 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
9998 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
9999 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
10000 // pcmpeqd + pshufd + pand.
10001 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
10003 // First cast everything to the right type.
10004 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
10005 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
10008 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
10010 // Make sure the lower and upper halves are both all-ones.
10011 static const int Mask[] = { 1, 0, 3, 2 };
10012 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
10013 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
10016 Result = DAG.getNOT(dl, Result, MVT::v4i32);
10018 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
10022 // Since SSE has no unsigned integer comparisons, we need to flip the sign
10023 // bits of the inputs before performing those operations.
10025 EVT EltVT = VT.getVectorElementType();
10026 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
10027 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
10028 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
10031 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
10033 // If the logical-not of the result is required, perform that now.
10035 Result = DAG.getNOT(dl, Result, VT);
10038 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
10043 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
10045 MVT VT = Op.getSimpleValueType();
10047 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
10049 assert(VT == MVT::i8 && "SetCC type must be 8-bit integer");
10050 SDValue Op0 = Op.getOperand(0);
10051 SDValue Op1 = Op.getOperand(1);
10053 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
10055 // Optimize to BT if possible.
10056 // Lower (X & (1 << N)) == 0 to BT(X, N).
10057 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
10058 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
10059 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
10060 Op1.getOpcode() == ISD::Constant &&
10061 cast<ConstantSDNode>(Op1)->isNullValue() &&
10062 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
10063 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
10064 if (NewSetCC.getNode())
10068 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
10070 if (Op1.getOpcode() == ISD::Constant &&
10071 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
10072 cast<ConstantSDNode>(Op1)->isNullValue()) &&
10073 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
10075 // If the input is a setcc, then reuse the input setcc or use a new one with
10076 // the inverted condition.
10077 if (Op0.getOpcode() == X86ISD::SETCC) {
10078 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
10079 bool Invert = (CC == ISD::SETNE) ^
10080 cast<ConstantSDNode>(Op1)->isNullValue();
10081 if (!Invert) return Op0;
10083 CCode = X86::GetOppositeBranchCondition(CCode);
10084 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
10085 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1));
10089 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
10090 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
10091 if (X86CC == X86::COND_INVALID)
10094 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG);
10095 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
10096 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
10097 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
10100 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
10101 static bool isX86LogicalCmp(SDValue Op) {
10102 unsigned Opc = Op.getNode()->getOpcode();
10103 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
10104 Opc == X86ISD::SAHF)
10106 if (Op.getResNo() == 1 &&
10107 (Opc == X86ISD::ADD ||
10108 Opc == X86ISD::SUB ||
10109 Opc == X86ISD::ADC ||
10110 Opc == X86ISD::SBB ||
10111 Opc == X86ISD::SMUL ||
10112 Opc == X86ISD::UMUL ||
10113 Opc == X86ISD::INC ||
10114 Opc == X86ISD::DEC ||
10115 Opc == X86ISD::OR ||
10116 Opc == X86ISD::XOR ||
10117 Opc == X86ISD::AND))
10120 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
10126 static bool isZero(SDValue V) {
10127 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
10128 return C && C->isNullValue();
10131 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
10132 if (V.getOpcode() != ISD::TRUNCATE)
10135 SDValue VOp0 = V.getOperand(0);
10136 unsigned InBits = VOp0.getValueSizeInBits();
10137 unsigned Bits = V.getValueSizeInBits();
10138 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
10141 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
10142 bool addTest = true;
10143 SDValue Cond = Op.getOperand(0);
10144 SDValue Op1 = Op.getOperand(1);
10145 SDValue Op2 = Op.getOperand(2);
10147 EVT VT = Op1.getValueType();
10150 // Lower fp selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
10151 // are available. Otherwise fp cmovs get lowered into a less efficient branch
10152 // sequence later on.
10153 if (Cond.getOpcode() == ISD::SETCC &&
10154 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
10155 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
10156 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
10157 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
10158 int SSECC = translateX86FSETCC(
10159 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
10162 unsigned Opcode = VT == MVT::f32 ? X86ISD::FSETCCss : X86ISD::FSETCCsd;
10163 SDValue Cmp = DAG.getNode(Opcode, DL, VT, CondOp0, CondOp1,
10164 DAG.getConstant(SSECC, MVT::i8));
10165 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
10166 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
10167 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
10171 if (Cond.getOpcode() == ISD::SETCC) {
10172 SDValue NewCond = LowerSETCC(Cond, DAG);
10173 if (NewCond.getNode())
10177 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
10178 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
10179 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
10180 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
10181 if (Cond.getOpcode() == X86ISD::SETCC &&
10182 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
10183 isZero(Cond.getOperand(1).getOperand(1))) {
10184 SDValue Cmp = Cond.getOperand(1);
10186 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
10188 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
10189 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
10190 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
10192 SDValue CmpOp0 = Cmp.getOperand(0);
10193 // Apply further optimizations for special cases
10194 // (select (x != 0), -1, 0) -> neg & sbb
10195 // (select (x == 0), 0, -1) -> neg & sbb
10196 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
10197 if (YC->isNullValue() &&
10198 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
10199 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
10200 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
10201 DAG.getConstant(0, CmpOp0.getValueType()),
10203 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
10204 DAG.getConstant(X86::COND_B, MVT::i8),
10205 SDValue(Neg.getNode(), 1));
10209 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
10210 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
10211 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
10213 SDValue Res = // Res = 0 or -1.
10214 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
10215 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
10217 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
10218 Res = DAG.getNOT(DL, Res, Res.getValueType());
10220 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
10221 if (N2C == 0 || !N2C->isNullValue())
10222 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
10227 // Look past (and (setcc_carry (cmp ...)), 1).
10228 if (Cond.getOpcode() == ISD::AND &&
10229 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
10230 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
10231 if (C && C->getAPIntValue() == 1)
10232 Cond = Cond.getOperand(0);
10235 // If condition flag is set by a X86ISD::CMP, then use it as the condition
10236 // setting operand in place of the X86ISD::SETCC.
10237 unsigned CondOpcode = Cond.getOpcode();
10238 if (CondOpcode == X86ISD::SETCC ||
10239 CondOpcode == X86ISD::SETCC_CARRY) {
10240 CC = Cond.getOperand(0);
10242 SDValue Cmp = Cond.getOperand(1);
10243 unsigned Opc = Cmp.getOpcode();
10244 MVT VT = Op.getSimpleValueType();
10246 bool IllegalFPCMov = false;
10247 if (VT.isFloatingPoint() && !VT.isVector() &&
10248 !isScalarFPTypeInSSEReg(VT)) // FPStack?
10249 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
10251 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
10252 Opc == X86ISD::BT) { // FIXME
10256 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
10257 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
10258 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
10259 Cond.getOperand(0).getValueType() != MVT::i8)) {
10260 SDValue LHS = Cond.getOperand(0);
10261 SDValue RHS = Cond.getOperand(1);
10262 unsigned X86Opcode;
10265 switch (CondOpcode) {
10266 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
10267 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
10268 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
10269 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
10270 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
10271 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
10272 default: llvm_unreachable("unexpected overflowing operator");
10274 if (CondOpcode == ISD::UMULO)
10275 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
10278 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
10280 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
10282 if (CondOpcode == ISD::UMULO)
10283 Cond = X86Op.getValue(2);
10285 Cond = X86Op.getValue(1);
10287 CC = DAG.getConstant(X86Cond, MVT::i8);
10292 // Look pass the truncate if the high bits are known zero.
10293 if (isTruncWithZeroHighBitsInput(Cond, DAG))
10294 Cond = Cond.getOperand(0);
10296 // We know the result of AND is compared against zero. Try to match
10298 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
10299 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
10300 if (NewSetCC.getNode()) {
10301 CC = NewSetCC.getOperand(0);
10302 Cond = NewSetCC.getOperand(1);
10309 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
10310 Cond = EmitTest(Cond, X86::COND_NE, DAG);
10313 // a < b ? -1 : 0 -> RES = ~setcc_carry
10314 // a < b ? 0 : -1 -> RES = setcc_carry
10315 // a >= b ? -1 : 0 -> RES = setcc_carry
10316 // a >= b ? 0 : -1 -> RES = ~setcc_carry
10317 if (Cond.getOpcode() == X86ISD::SUB) {
10318 Cond = ConvertCmpIfNecessary(Cond, DAG);
10319 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
10321 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
10322 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
10323 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
10324 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
10325 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
10326 return DAG.getNOT(DL, Res, Res.getValueType());
10331 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
10332 // widen the cmov and push the truncate through. This avoids introducing a new
10333 // branch during isel and doesn't add any extensions.
10334 if (Op.getValueType() == MVT::i8 &&
10335 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
10336 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
10337 if (T1.getValueType() == T2.getValueType() &&
10338 // Blacklist CopyFromReg to avoid partial register stalls.
10339 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
10340 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
10341 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
10342 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
10346 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
10347 // condition is true.
10348 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
10349 SDValue Ops[] = { Op2, Op1, CC, Cond };
10350 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops));
10353 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, SelectionDAG &DAG) {
10354 MVT VT = Op->getSimpleValueType(0);
10355 SDValue In = Op->getOperand(0);
10356 MVT InVT = In.getSimpleValueType();
10359 unsigned int NumElts = VT.getVectorNumElements();
10360 if (NumElts != 8 && NumElts != 16)
10363 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
10364 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
10366 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
10367 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
10369 MVT ExtVT = (NumElts == 8) ? MVT::v8i64 : MVT::v16i32;
10370 Constant *C = ConstantInt::get(*DAG.getContext(),
10371 APInt::getAllOnesValue(ExtVT.getScalarType().getSizeInBits()));
10373 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
10374 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
10375 SDValue Ld = DAG.getLoad(ExtVT.getScalarType(), dl, DAG.getEntryNode(), CP,
10376 MachinePointerInfo::getConstantPool(),
10377 false, false, false, Alignment);
10378 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, dl, ExtVT, In, Ld);
10379 if (VT.is512BitVector())
10381 return DAG.getNode(X86ISD::VTRUNC, dl, VT, Brcst);
10384 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
10385 SelectionDAG &DAG) {
10386 MVT VT = Op->getSimpleValueType(0);
10387 SDValue In = Op->getOperand(0);
10388 MVT InVT = In.getSimpleValueType();
10391 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
10392 return LowerSIGN_EXTEND_AVX512(Op, DAG);
10394 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
10395 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
10396 (VT != MVT::v16i16 || InVT != MVT::v16i8))
10399 if (Subtarget->hasInt256())
10400 return DAG.getNode(X86ISD::VSEXT_MOVL, dl, VT, In);
10402 // Optimize vectors in AVX mode
10403 // Sign extend v8i16 to v8i32 and
10406 // Divide input vector into two parts
10407 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
10408 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
10409 // concat the vectors to original VT
10411 unsigned NumElems = InVT.getVectorNumElements();
10412 SDValue Undef = DAG.getUNDEF(InVT);
10414 SmallVector<int,8> ShufMask1(NumElems, -1);
10415 for (unsigned i = 0; i != NumElems/2; ++i)
10418 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
10420 SmallVector<int,8> ShufMask2(NumElems, -1);
10421 for (unsigned i = 0; i != NumElems/2; ++i)
10422 ShufMask2[i] = i + NumElems/2;
10424 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
10426 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
10427 VT.getVectorNumElements()/2);
10429 OpLo = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpLo);
10430 OpHi = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpHi);
10432 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
10435 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
10436 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
10437 // from the AND / OR.
10438 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
10439 Opc = Op.getOpcode();
10440 if (Opc != ISD::OR && Opc != ISD::AND)
10442 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
10443 Op.getOperand(0).hasOneUse() &&
10444 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
10445 Op.getOperand(1).hasOneUse());
10448 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
10449 // 1 and that the SETCC node has a single use.
10450 static bool isXor1OfSetCC(SDValue Op) {
10451 if (Op.getOpcode() != ISD::XOR)
10453 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
10454 if (N1C && N1C->getAPIntValue() == 1) {
10455 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
10456 Op.getOperand(0).hasOneUse();
10461 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
10462 bool addTest = true;
10463 SDValue Chain = Op.getOperand(0);
10464 SDValue Cond = Op.getOperand(1);
10465 SDValue Dest = Op.getOperand(2);
10468 bool Inverted = false;
10470 if (Cond.getOpcode() == ISD::SETCC) {
10471 // Check for setcc([su]{add,sub,mul}o == 0).
10472 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
10473 isa<ConstantSDNode>(Cond.getOperand(1)) &&
10474 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
10475 Cond.getOperand(0).getResNo() == 1 &&
10476 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
10477 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
10478 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
10479 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
10480 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
10481 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
10483 Cond = Cond.getOperand(0);
10485 SDValue NewCond = LowerSETCC(Cond, DAG);
10486 if (NewCond.getNode())
10491 // FIXME: LowerXALUO doesn't handle these!!
10492 else if (Cond.getOpcode() == X86ISD::ADD ||
10493 Cond.getOpcode() == X86ISD::SUB ||
10494 Cond.getOpcode() == X86ISD::SMUL ||
10495 Cond.getOpcode() == X86ISD::UMUL)
10496 Cond = LowerXALUO(Cond, DAG);
10499 // Look pass (and (setcc_carry (cmp ...)), 1).
10500 if (Cond.getOpcode() == ISD::AND &&
10501 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
10502 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
10503 if (C && C->getAPIntValue() == 1)
10504 Cond = Cond.getOperand(0);
10507 // If condition flag is set by a X86ISD::CMP, then use it as the condition
10508 // setting operand in place of the X86ISD::SETCC.
10509 unsigned CondOpcode = Cond.getOpcode();
10510 if (CondOpcode == X86ISD::SETCC ||
10511 CondOpcode == X86ISD::SETCC_CARRY) {
10512 CC = Cond.getOperand(0);
10514 SDValue Cmp = Cond.getOperand(1);
10515 unsigned Opc = Cmp.getOpcode();
10516 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
10517 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
10521 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
10525 // These can only come from an arithmetic instruction with overflow,
10526 // e.g. SADDO, UADDO.
10527 Cond = Cond.getNode()->getOperand(1);
10533 CondOpcode = Cond.getOpcode();
10534 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
10535 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
10536 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
10537 Cond.getOperand(0).getValueType() != MVT::i8)) {
10538 SDValue LHS = Cond.getOperand(0);
10539 SDValue RHS = Cond.getOperand(1);
10540 unsigned X86Opcode;
10543 switch (CondOpcode) {
10544 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
10545 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
10546 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
10547 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
10548 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
10549 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
10550 default: llvm_unreachable("unexpected overflowing operator");
10553 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
10554 if (CondOpcode == ISD::UMULO)
10555 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
10558 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
10560 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
10562 if (CondOpcode == ISD::UMULO)
10563 Cond = X86Op.getValue(2);
10565 Cond = X86Op.getValue(1);
10567 CC = DAG.getConstant(X86Cond, MVT::i8);
10571 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
10572 SDValue Cmp = Cond.getOperand(0).getOperand(1);
10573 if (CondOpc == ISD::OR) {
10574 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
10575 // two branches instead of an explicit OR instruction with a
10577 if (Cmp == Cond.getOperand(1).getOperand(1) &&
10578 isX86LogicalCmp(Cmp)) {
10579 CC = Cond.getOperand(0).getOperand(0);
10580 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10581 Chain, Dest, CC, Cmp);
10582 CC = Cond.getOperand(1).getOperand(0);
10586 } else { // ISD::AND
10587 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
10588 // two branches instead of an explicit AND instruction with a
10589 // separate test. However, we only do this if this block doesn't
10590 // have a fall-through edge, because this requires an explicit
10591 // jmp when the condition is false.
10592 if (Cmp == Cond.getOperand(1).getOperand(1) &&
10593 isX86LogicalCmp(Cmp) &&
10594 Op.getNode()->hasOneUse()) {
10595 X86::CondCode CCode =
10596 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
10597 CCode = X86::GetOppositeBranchCondition(CCode);
10598 CC = DAG.getConstant(CCode, MVT::i8);
10599 SDNode *User = *Op.getNode()->use_begin();
10600 // Look for an unconditional branch following this conditional branch.
10601 // We need this because we need to reverse the successors in order
10602 // to implement FCMP_OEQ.
10603 if (User->getOpcode() == ISD::BR) {
10604 SDValue FalseBB = User->getOperand(1);
10606 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
10607 assert(NewBR == User);
10611 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10612 Chain, Dest, CC, Cmp);
10613 X86::CondCode CCode =
10614 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
10615 CCode = X86::GetOppositeBranchCondition(CCode);
10616 CC = DAG.getConstant(CCode, MVT::i8);
10622 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
10623 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
10624 // It should be transformed during dag combiner except when the condition
10625 // is set by a arithmetics with overflow node.
10626 X86::CondCode CCode =
10627 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
10628 CCode = X86::GetOppositeBranchCondition(CCode);
10629 CC = DAG.getConstant(CCode, MVT::i8);
10630 Cond = Cond.getOperand(0).getOperand(1);
10632 } else if (Cond.getOpcode() == ISD::SETCC &&
10633 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
10634 // For FCMP_OEQ, we can emit
10635 // two branches instead of an explicit AND instruction with a
10636 // separate test. However, we only do this if this block doesn't
10637 // have a fall-through edge, because this requires an explicit
10638 // jmp when the condition is false.
10639 if (Op.getNode()->hasOneUse()) {
10640 SDNode *User = *Op.getNode()->use_begin();
10641 // Look for an unconditional branch following this conditional branch.
10642 // We need this because we need to reverse the successors in order
10643 // to implement FCMP_OEQ.
10644 if (User->getOpcode() == ISD::BR) {
10645 SDValue FalseBB = User->getOperand(1);
10647 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
10648 assert(NewBR == User);
10652 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
10653 Cond.getOperand(0), Cond.getOperand(1));
10654 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
10655 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
10656 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10657 Chain, Dest, CC, Cmp);
10658 CC = DAG.getConstant(X86::COND_P, MVT::i8);
10663 } else if (Cond.getOpcode() == ISD::SETCC &&
10664 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
10665 // For FCMP_UNE, we can emit
10666 // two branches instead of an explicit AND instruction with a
10667 // separate test. However, we only do this if this block doesn't
10668 // have a fall-through edge, because this requires an explicit
10669 // jmp when the condition is false.
10670 if (Op.getNode()->hasOneUse()) {
10671 SDNode *User = *Op.getNode()->use_begin();
10672 // Look for an unconditional branch following this conditional branch.
10673 // We need this because we need to reverse the successors in order
10674 // to implement FCMP_UNE.
10675 if (User->getOpcode() == ISD::BR) {
10676 SDValue FalseBB = User->getOperand(1);
10678 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
10679 assert(NewBR == User);
10682 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
10683 Cond.getOperand(0), Cond.getOperand(1));
10684 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
10685 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
10686 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10687 Chain, Dest, CC, Cmp);
10688 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
10698 // Look pass the truncate if the high bits are known zero.
10699 if (isTruncWithZeroHighBitsInput(Cond, DAG))
10700 Cond = Cond.getOperand(0);
10702 // We know the result of AND is compared against zero. Try to match
10704 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
10705 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
10706 if (NewSetCC.getNode()) {
10707 CC = NewSetCC.getOperand(0);
10708 Cond = NewSetCC.getOperand(1);
10715 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
10716 Cond = EmitTest(Cond, X86::COND_NE, DAG);
10718 Cond = ConvertCmpIfNecessary(Cond, DAG);
10719 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10720 Chain, Dest, CC, Cond);
10723 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
10724 // Calls to _alloca is needed to probe the stack when allocating more than 4k
10725 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
10726 // that the guard pages used by the OS virtual memory manager are allocated in
10727 // correct sequence.
10729 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
10730 SelectionDAG &DAG) const {
10731 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows() ||
10732 getTargetMachine().Options.EnableSegmentedStacks) &&
10733 "This should be used only on Windows targets or when segmented stacks "
10735 assert(!Subtarget->isTargetEnvMacho() && "Not implemented");
10739 SDValue Chain = Op.getOperand(0);
10740 SDValue Size = Op.getOperand(1);
10741 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
10742 EVT VT = Op.getNode()->getValueType(0);
10744 bool Is64Bit = Subtarget->is64Bit();
10745 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32;
10747 if (getTargetMachine().Options.EnableSegmentedStacks) {
10748 MachineFunction &MF = DAG.getMachineFunction();
10749 MachineRegisterInfo &MRI = MF.getRegInfo();
10752 // The 64 bit implementation of segmented stacks needs to clobber both r10
10753 // r11. This makes it impossible to use it along with nested parameters.
10754 const Function *F = MF.getFunction();
10756 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
10758 if (I->hasNestAttr())
10759 report_fatal_error("Cannot use segmented stacks with functions that "
10760 "have nested arguments.");
10763 const TargetRegisterClass *AddrRegClass =
10764 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32);
10765 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
10766 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
10767 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
10768 DAG.getRegister(Vreg, SPTy));
10769 SDValue Ops1[2] = { Value, Chain };
10770 return DAG.getMergeValues(Ops1, 2, dl);
10773 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
10775 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
10776 Flag = Chain.getValue(1);
10777 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
10779 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
10781 const X86RegisterInfo *RegInfo =
10782 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
10783 unsigned SPReg = RegInfo->getStackRegister();
10784 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
10785 Chain = SP.getValue(1);
10788 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
10789 DAG.getConstant(-(uint64_t)Align, VT));
10790 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
10793 SDValue Ops1[2] = { SP, Chain };
10794 return DAG.getMergeValues(Ops1, 2, dl);
10798 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
10799 MachineFunction &MF = DAG.getMachineFunction();
10800 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
10802 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
10805 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
10806 // vastart just stores the address of the VarArgsFrameIndex slot into the
10807 // memory location argument.
10808 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
10810 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
10811 MachinePointerInfo(SV), false, false, 0);
10815 // gp_offset (0 - 6 * 8)
10816 // fp_offset (48 - 48 + 8 * 16)
10817 // overflow_arg_area (point to parameters coming in memory).
10819 SmallVector<SDValue, 8> MemOps;
10820 SDValue FIN = Op.getOperand(1);
10822 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
10823 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
10825 FIN, MachinePointerInfo(SV), false, false, 0);
10826 MemOps.push_back(Store);
10829 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10830 FIN, DAG.getIntPtrConstant(4));
10831 Store = DAG.getStore(Op.getOperand(0), DL,
10832 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
10834 FIN, MachinePointerInfo(SV, 4), false, false, 0);
10835 MemOps.push_back(Store);
10837 // Store ptr to overflow_arg_area
10838 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10839 FIN, DAG.getIntPtrConstant(4));
10840 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
10842 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
10843 MachinePointerInfo(SV, 8),
10845 MemOps.push_back(Store);
10847 // Store ptr to reg_save_area.
10848 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10849 FIN, DAG.getIntPtrConstant(8));
10850 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
10852 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
10853 MachinePointerInfo(SV, 16), false, false, 0);
10854 MemOps.push_back(Store);
10855 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
10856 &MemOps[0], MemOps.size());
10859 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
10860 assert(Subtarget->is64Bit() &&
10861 "LowerVAARG only handles 64-bit va_arg!");
10862 assert((Subtarget->isTargetLinux() ||
10863 Subtarget->isTargetDarwin()) &&
10864 "Unhandled target in LowerVAARG");
10865 assert(Op.getNode()->getNumOperands() == 4);
10866 SDValue Chain = Op.getOperand(0);
10867 SDValue SrcPtr = Op.getOperand(1);
10868 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
10869 unsigned Align = Op.getConstantOperandVal(3);
10872 EVT ArgVT = Op.getNode()->getValueType(0);
10873 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
10874 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
10877 // Decide which area this value should be read from.
10878 // TODO: Implement the AMD64 ABI in its entirety. This simple
10879 // selection mechanism works only for the basic types.
10880 if (ArgVT == MVT::f80) {
10881 llvm_unreachable("va_arg for f80 not yet implemented");
10882 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
10883 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
10884 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
10885 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
10887 llvm_unreachable("Unhandled argument type in LowerVAARG");
10890 if (ArgMode == 2) {
10891 // Sanity Check: Make sure using fp_offset makes sense.
10892 assert(!getTargetMachine().Options.UseSoftFloat &&
10893 !(DAG.getMachineFunction()
10894 .getFunction()->getAttributes()
10895 .hasAttribute(AttributeSet::FunctionIndex,
10896 Attribute::NoImplicitFloat)) &&
10897 Subtarget->hasSSE1());
10900 // Insert VAARG_64 node into the DAG
10901 // VAARG_64 returns two values: Variable Argument Address, Chain
10902 SmallVector<SDValue, 11> InstOps;
10903 InstOps.push_back(Chain);
10904 InstOps.push_back(SrcPtr);
10905 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
10906 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
10907 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
10908 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
10909 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
10910 VTs, &InstOps[0], InstOps.size(),
10912 MachinePointerInfo(SV),
10914 /*Volatile=*/false,
10916 /*WriteMem=*/true);
10917 Chain = VAARG.getValue(1);
10919 // Load the next argument and return it
10920 return DAG.getLoad(ArgVT, dl,
10923 MachinePointerInfo(),
10924 false, false, false, 0);
10927 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
10928 SelectionDAG &DAG) {
10929 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
10930 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
10931 SDValue Chain = Op.getOperand(0);
10932 SDValue DstPtr = Op.getOperand(1);
10933 SDValue SrcPtr = Op.getOperand(2);
10934 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
10935 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
10938 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
10939 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
10941 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
10944 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
10945 // amount is a constant. Takes immediate version of shift as input.
10946 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, EVT VT,
10947 SDValue SrcOp, uint64_t ShiftAmt,
10948 SelectionDAG &DAG) {
10950 // Check for ShiftAmt >= element width
10951 if (ShiftAmt >= VT.getVectorElementType().getSizeInBits()) {
10952 if (Opc == X86ISD::VSRAI)
10953 ShiftAmt = VT.getVectorElementType().getSizeInBits() - 1;
10955 return DAG.getConstant(0, VT);
10958 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
10959 && "Unknown target vector shift-by-constant node");
10961 return DAG.getNode(Opc, dl, VT, SrcOp, DAG.getConstant(ShiftAmt, MVT::i8));
10964 // getTargetVShiftNode - Handle vector element shifts where the shift amount
10965 // may or may not be a constant. Takes immediate version of shift as input.
10966 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, EVT VT,
10967 SDValue SrcOp, SDValue ShAmt,
10968 SelectionDAG &DAG) {
10969 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
10971 // Catch shift-by-constant.
10972 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
10973 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
10974 CShAmt->getZExtValue(), DAG);
10976 // Change opcode to non-immediate version
10978 default: llvm_unreachable("Unknown target vector shift node");
10979 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
10980 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
10981 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
10984 // Need to build a vector containing shift amount
10985 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
10988 ShOps[1] = DAG.getConstant(0, MVT::i32);
10989 ShOps[2] = ShOps[3] = DAG.getUNDEF(MVT::i32);
10990 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, &ShOps[0], 4);
10992 // The return type has to be a 128-bit type with the same element
10993 // type as the input type.
10994 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10995 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
10997 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
10998 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
11001 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
11003 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
11005 default: return SDValue(); // Don't custom lower most intrinsics.
11006 // Comparison intrinsics.
11007 case Intrinsic::x86_sse_comieq_ss:
11008 case Intrinsic::x86_sse_comilt_ss:
11009 case Intrinsic::x86_sse_comile_ss:
11010 case Intrinsic::x86_sse_comigt_ss:
11011 case Intrinsic::x86_sse_comige_ss:
11012 case Intrinsic::x86_sse_comineq_ss:
11013 case Intrinsic::x86_sse_ucomieq_ss:
11014 case Intrinsic::x86_sse_ucomilt_ss:
11015 case Intrinsic::x86_sse_ucomile_ss:
11016 case Intrinsic::x86_sse_ucomigt_ss:
11017 case Intrinsic::x86_sse_ucomige_ss:
11018 case Intrinsic::x86_sse_ucomineq_ss:
11019 case Intrinsic::x86_sse2_comieq_sd:
11020 case Intrinsic::x86_sse2_comilt_sd:
11021 case Intrinsic::x86_sse2_comile_sd:
11022 case Intrinsic::x86_sse2_comigt_sd:
11023 case Intrinsic::x86_sse2_comige_sd:
11024 case Intrinsic::x86_sse2_comineq_sd:
11025 case Intrinsic::x86_sse2_ucomieq_sd:
11026 case Intrinsic::x86_sse2_ucomilt_sd:
11027 case Intrinsic::x86_sse2_ucomile_sd:
11028 case Intrinsic::x86_sse2_ucomigt_sd:
11029 case Intrinsic::x86_sse2_ucomige_sd:
11030 case Intrinsic::x86_sse2_ucomineq_sd: {
11034 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11035 case Intrinsic::x86_sse_comieq_ss:
11036 case Intrinsic::x86_sse2_comieq_sd:
11037 Opc = X86ISD::COMI;
11040 case Intrinsic::x86_sse_comilt_ss:
11041 case Intrinsic::x86_sse2_comilt_sd:
11042 Opc = X86ISD::COMI;
11045 case Intrinsic::x86_sse_comile_ss:
11046 case Intrinsic::x86_sse2_comile_sd:
11047 Opc = X86ISD::COMI;
11050 case Intrinsic::x86_sse_comigt_ss:
11051 case Intrinsic::x86_sse2_comigt_sd:
11052 Opc = X86ISD::COMI;
11055 case Intrinsic::x86_sse_comige_ss:
11056 case Intrinsic::x86_sse2_comige_sd:
11057 Opc = X86ISD::COMI;
11060 case Intrinsic::x86_sse_comineq_ss:
11061 case Intrinsic::x86_sse2_comineq_sd:
11062 Opc = X86ISD::COMI;
11065 case Intrinsic::x86_sse_ucomieq_ss:
11066 case Intrinsic::x86_sse2_ucomieq_sd:
11067 Opc = X86ISD::UCOMI;
11070 case Intrinsic::x86_sse_ucomilt_ss:
11071 case Intrinsic::x86_sse2_ucomilt_sd:
11072 Opc = X86ISD::UCOMI;
11075 case Intrinsic::x86_sse_ucomile_ss:
11076 case Intrinsic::x86_sse2_ucomile_sd:
11077 Opc = X86ISD::UCOMI;
11080 case Intrinsic::x86_sse_ucomigt_ss:
11081 case Intrinsic::x86_sse2_ucomigt_sd:
11082 Opc = X86ISD::UCOMI;
11085 case Intrinsic::x86_sse_ucomige_ss:
11086 case Intrinsic::x86_sse2_ucomige_sd:
11087 Opc = X86ISD::UCOMI;
11090 case Intrinsic::x86_sse_ucomineq_ss:
11091 case Intrinsic::x86_sse2_ucomineq_sd:
11092 Opc = X86ISD::UCOMI;
11097 SDValue LHS = Op.getOperand(1);
11098 SDValue RHS = Op.getOperand(2);
11099 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
11100 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
11101 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
11102 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
11103 DAG.getConstant(X86CC, MVT::i8), Cond);
11104 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
11107 // Arithmetic intrinsics.
11108 case Intrinsic::x86_sse2_pmulu_dq:
11109 case Intrinsic::x86_avx2_pmulu_dq:
11110 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
11111 Op.getOperand(1), Op.getOperand(2));
11113 // SSE2/AVX2 sub with unsigned saturation intrinsics
11114 case Intrinsic::x86_sse2_psubus_b:
11115 case Intrinsic::x86_sse2_psubus_w:
11116 case Intrinsic::x86_avx2_psubus_b:
11117 case Intrinsic::x86_avx2_psubus_w:
11118 return DAG.getNode(X86ISD::SUBUS, dl, Op.getValueType(),
11119 Op.getOperand(1), Op.getOperand(2));
11121 // SSE3/AVX horizontal add/sub intrinsics
11122 case Intrinsic::x86_sse3_hadd_ps:
11123 case Intrinsic::x86_sse3_hadd_pd:
11124 case Intrinsic::x86_avx_hadd_ps_256:
11125 case Intrinsic::x86_avx_hadd_pd_256:
11126 case Intrinsic::x86_sse3_hsub_ps:
11127 case Intrinsic::x86_sse3_hsub_pd:
11128 case Intrinsic::x86_avx_hsub_ps_256:
11129 case Intrinsic::x86_avx_hsub_pd_256:
11130 case Intrinsic::x86_ssse3_phadd_w_128:
11131 case Intrinsic::x86_ssse3_phadd_d_128:
11132 case Intrinsic::x86_avx2_phadd_w:
11133 case Intrinsic::x86_avx2_phadd_d:
11134 case Intrinsic::x86_ssse3_phsub_w_128:
11135 case Intrinsic::x86_ssse3_phsub_d_128:
11136 case Intrinsic::x86_avx2_phsub_w:
11137 case Intrinsic::x86_avx2_phsub_d: {
11140 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11141 case Intrinsic::x86_sse3_hadd_ps:
11142 case Intrinsic::x86_sse3_hadd_pd:
11143 case Intrinsic::x86_avx_hadd_ps_256:
11144 case Intrinsic::x86_avx_hadd_pd_256:
11145 Opcode = X86ISD::FHADD;
11147 case Intrinsic::x86_sse3_hsub_ps:
11148 case Intrinsic::x86_sse3_hsub_pd:
11149 case Intrinsic::x86_avx_hsub_ps_256:
11150 case Intrinsic::x86_avx_hsub_pd_256:
11151 Opcode = X86ISD::FHSUB;
11153 case Intrinsic::x86_ssse3_phadd_w_128:
11154 case Intrinsic::x86_ssse3_phadd_d_128:
11155 case Intrinsic::x86_avx2_phadd_w:
11156 case Intrinsic::x86_avx2_phadd_d:
11157 Opcode = X86ISD::HADD;
11159 case Intrinsic::x86_ssse3_phsub_w_128:
11160 case Intrinsic::x86_ssse3_phsub_d_128:
11161 case Intrinsic::x86_avx2_phsub_w:
11162 case Intrinsic::x86_avx2_phsub_d:
11163 Opcode = X86ISD::HSUB;
11166 return DAG.getNode(Opcode, dl, Op.getValueType(),
11167 Op.getOperand(1), Op.getOperand(2));
11170 // SSE2/SSE41/AVX2 integer max/min intrinsics.
11171 case Intrinsic::x86_sse2_pmaxu_b:
11172 case Intrinsic::x86_sse41_pmaxuw:
11173 case Intrinsic::x86_sse41_pmaxud:
11174 case Intrinsic::x86_avx2_pmaxu_b:
11175 case Intrinsic::x86_avx2_pmaxu_w:
11176 case Intrinsic::x86_avx2_pmaxu_d:
11177 case Intrinsic::x86_sse2_pminu_b:
11178 case Intrinsic::x86_sse41_pminuw:
11179 case Intrinsic::x86_sse41_pminud:
11180 case Intrinsic::x86_avx2_pminu_b:
11181 case Intrinsic::x86_avx2_pminu_w:
11182 case Intrinsic::x86_avx2_pminu_d:
11183 case Intrinsic::x86_sse41_pmaxsb:
11184 case Intrinsic::x86_sse2_pmaxs_w:
11185 case Intrinsic::x86_sse41_pmaxsd:
11186 case Intrinsic::x86_avx2_pmaxs_b:
11187 case Intrinsic::x86_avx2_pmaxs_w:
11188 case Intrinsic::x86_avx2_pmaxs_d:
11189 case Intrinsic::x86_sse41_pminsb:
11190 case Intrinsic::x86_sse2_pmins_w:
11191 case Intrinsic::x86_sse41_pminsd:
11192 case Intrinsic::x86_avx2_pmins_b:
11193 case Intrinsic::x86_avx2_pmins_w:
11194 case Intrinsic::x86_avx2_pmins_d: {
11197 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11198 case Intrinsic::x86_sse2_pmaxu_b:
11199 case Intrinsic::x86_sse41_pmaxuw:
11200 case Intrinsic::x86_sse41_pmaxud:
11201 case Intrinsic::x86_avx2_pmaxu_b:
11202 case Intrinsic::x86_avx2_pmaxu_w:
11203 case Intrinsic::x86_avx2_pmaxu_d:
11204 Opcode = X86ISD::UMAX;
11206 case Intrinsic::x86_sse2_pminu_b:
11207 case Intrinsic::x86_sse41_pminuw:
11208 case Intrinsic::x86_sse41_pminud:
11209 case Intrinsic::x86_avx2_pminu_b:
11210 case Intrinsic::x86_avx2_pminu_w:
11211 case Intrinsic::x86_avx2_pminu_d:
11212 Opcode = X86ISD::UMIN;
11214 case Intrinsic::x86_sse41_pmaxsb:
11215 case Intrinsic::x86_sse2_pmaxs_w:
11216 case Intrinsic::x86_sse41_pmaxsd:
11217 case Intrinsic::x86_avx2_pmaxs_b:
11218 case Intrinsic::x86_avx2_pmaxs_w:
11219 case Intrinsic::x86_avx2_pmaxs_d:
11220 Opcode = X86ISD::SMAX;
11222 case Intrinsic::x86_sse41_pminsb:
11223 case Intrinsic::x86_sse2_pmins_w:
11224 case Intrinsic::x86_sse41_pminsd:
11225 case Intrinsic::x86_avx2_pmins_b:
11226 case Intrinsic::x86_avx2_pmins_w:
11227 case Intrinsic::x86_avx2_pmins_d:
11228 Opcode = X86ISD::SMIN;
11231 return DAG.getNode(Opcode, dl, Op.getValueType(),
11232 Op.getOperand(1), Op.getOperand(2));
11235 // SSE/SSE2/AVX floating point max/min intrinsics.
11236 case Intrinsic::x86_sse_max_ps:
11237 case Intrinsic::x86_sse2_max_pd:
11238 case Intrinsic::x86_avx_max_ps_256:
11239 case Intrinsic::x86_avx_max_pd_256:
11240 case Intrinsic::x86_avx512_max_ps_512:
11241 case Intrinsic::x86_avx512_max_pd_512:
11242 case Intrinsic::x86_sse_min_ps:
11243 case Intrinsic::x86_sse2_min_pd:
11244 case Intrinsic::x86_avx_min_ps_256:
11245 case Intrinsic::x86_avx_min_pd_256:
11246 case Intrinsic::x86_avx512_min_ps_512:
11247 case Intrinsic::x86_avx512_min_pd_512: {
11250 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11251 case Intrinsic::x86_sse_max_ps:
11252 case Intrinsic::x86_sse2_max_pd:
11253 case Intrinsic::x86_avx_max_ps_256:
11254 case Intrinsic::x86_avx_max_pd_256:
11255 case Intrinsic::x86_avx512_max_ps_512:
11256 case Intrinsic::x86_avx512_max_pd_512:
11257 Opcode = X86ISD::FMAX;
11259 case Intrinsic::x86_sse_min_ps:
11260 case Intrinsic::x86_sse2_min_pd:
11261 case Intrinsic::x86_avx_min_ps_256:
11262 case Intrinsic::x86_avx_min_pd_256:
11263 case Intrinsic::x86_avx512_min_ps_512:
11264 case Intrinsic::x86_avx512_min_pd_512:
11265 Opcode = X86ISD::FMIN;
11268 return DAG.getNode(Opcode, dl, Op.getValueType(),
11269 Op.getOperand(1), Op.getOperand(2));
11272 // AVX2 variable shift intrinsics
11273 case Intrinsic::x86_avx2_psllv_d:
11274 case Intrinsic::x86_avx2_psllv_q:
11275 case Intrinsic::x86_avx2_psllv_d_256:
11276 case Intrinsic::x86_avx2_psllv_q_256:
11277 case Intrinsic::x86_avx2_psrlv_d:
11278 case Intrinsic::x86_avx2_psrlv_q:
11279 case Intrinsic::x86_avx2_psrlv_d_256:
11280 case Intrinsic::x86_avx2_psrlv_q_256:
11281 case Intrinsic::x86_avx2_psrav_d:
11282 case Intrinsic::x86_avx2_psrav_d_256: {
11285 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11286 case Intrinsic::x86_avx2_psllv_d:
11287 case Intrinsic::x86_avx2_psllv_q:
11288 case Intrinsic::x86_avx2_psllv_d_256:
11289 case Intrinsic::x86_avx2_psllv_q_256:
11292 case Intrinsic::x86_avx2_psrlv_d:
11293 case Intrinsic::x86_avx2_psrlv_q:
11294 case Intrinsic::x86_avx2_psrlv_d_256:
11295 case Intrinsic::x86_avx2_psrlv_q_256:
11298 case Intrinsic::x86_avx2_psrav_d:
11299 case Intrinsic::x86_avx2_psrav_d_256:
11303 return DAG.getNode(Opcode, dl, Op.getValueType(),
11304 Op.getOperand(1), Op.getOperand(2));
11307 case Intrinsic::x86_ssse3_pshuf_b_128:
11308 case Intrinsic::x86_avx2_pshuf_b:
11309 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
11310 Op.getOperand(1), Op.getOperand(2));
11312 case Intrinsic::x86_ssse3_psign_b_128:
11313 case Intrinsic::x86_ssse3_psign_w_128:
11314 case Intrinsic::x86_ssse3_psign_d_128:
11315 case Intrinsic::x86_avx2_psign_b:
11316 case Intrinsic::x86_avx2_psign_w:
11317 case Intrinsic::x86_avx2_psign_d:
11318 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
11319 Op.getOperand(1), Op.getOperand(2));
11321 case Intrinsic::x86_sse41_insertps:
11322 return DAG.getNode(X86ISD::INSERTPS, dl, Op.getValueType(),
11323 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
11325 case Intrinsic::x86_avx_vperm2f128_ps_256:
11326 case Intrinsic::x86_avx_vperm2f128_pd_256:
11327 case Intrinsic::x86_avx_vperm2f128_si_256:
11328 case Intrinsic::x86_avx2_vperm2i128:
11329 return DAG.getNode(X86ISD::VPERM2X128, dl, Op.getValueType(),
11330 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
11332 case Intrinsic::x86_avx2_permd:
11333 case Intrinsic::x86_avx2_permps:
11334 // Operands intentionally swapped. Mask is last operand to intrinsic,
11335 // but second operand for node/instruction.
11336 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
11337 Op.getOperand(2), Op.getOperand(1));
11339 case Intrinsic::x86_sse_sqrt_ps:
11340 case Intrinsic::x86_sse2_sqrt_pd:
11341 case Intrinsic::x86_avx_sqrt_ps_256:
11342 case Intrinsic::x86_avx_sqrt_pd_256:
11343 return DAG.getNode(ISD::FSQRT, dl, Op.getValueType(), Op.getOperand(1));
11345 // ptest and testp intrinsics. The intrinsic these come from are designed to
11346 // return an integer value, not just an instruction so lower it to the ptest
11347 // or testp pattern and a setcc for the result.
11348 case Intrinsic::x86_sse41_ptestz:
11349 case Intrinsic::x86_sse41_ptestc:
11350 case Intrinsic::x86_sse41_ptestnzc:
11351 case Intrinsic::x86_avx_ptestz_256:
11352 case Intrinsic::x86_avx_ptestc_256:
11353 case Intrinsic::x86_avx_ptestnzc_256:
11354 case Intrinsic::x86_avx_vtestz_ps:
11355 case Intrinsic::x86_avx_vtestc_ps:
11356 case Intrinsic::x86_avx_vtestnzc_ps:
11357 case Intrinsic::x86_avx_vtestz_pd:
11358 case Intrinsic::x86_avx_vtestc_pd:
11359 case Intrinsic::x86_avx_vtestnzc_pd:
11360 case Intrinsic::x86_avx_vtestz_ps_256:
11361 case Intrinsic::x86_avx_vtestc_ps_256:
11362 case Intrinsic::x86_avx_vtestnzc_ps_256:
11363 case Intrinsic::x86_avx_vtestz_pd_256:
11364 case Intrinsic::x86_avx_vtestc_pd_256:
11365 case Intrinsic::x86_avx_vtestnzc_pd_256: {
11366 bool IsTestPacked = false;
11369 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
11370 case Intrinsic::x86_avx_vtestz_ps:
11371 case Intrinsic::x86_avx_vtestz_pd:
11372 case Intrinsic::x86_avx_vtestz_ps_256:
11373 case Intrinsic::x86_avx_vtestz_pd_256:
11374 IsTestPacked = true; // Fallthrough
11375 case Intrinsic::x86_sse41_ptestz:
11376 case Intrinsic::x86_avx_ptestz_256:
11378 X86CC = X86::COND_E;
11380 case Intrinsic::x86_avx_vtestc_ps:
11381 case Intrinsic::x86_avx_vtestc_pd:
11382 case Intrinsic::x86_avx_vtestc_ps_256:
11383 case Intrinsic::x86_avx_vtestc_pd_256:
11384 IsTestPacked = true; // Fallthrough
11385 case Intrinsic::x86_sse41_ptestc:
11386 case Intrinsic::x86_avx_ptestc_256:
11388 X86CC = X86::COND_B;
11390 case Intrinsic::x86_avx_vtestnzc_ps:
11391 case Intrinsic::x86_avx_vtestnzc_pd:
11392 case Intrinsic::x86_avx_vtestnzc_ps_256:
11393 case Intrinsic::x86_avx_vtestnzc_pd_256:
11394 IsTestPacked = true; // Fallthrough
11395 case Intrinsic::x86_sse41_ptestnzc:
11396 case Intrinsic::x86_avx_ptestnzc_256:
11398 X86CC = X86::COND_A;
11402 SDValue LHS = Op.getOperand(1);
11403 SDValue RHS = Op.getOperand(2);
11404 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
11405 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
11406 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
11407 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
11408 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
11410 case Intrinsic::x86_avx512_kortestz:
11411 case Intrinsic::x86_avx512_kortestc: {
11412 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz)? X86::COND_E: X86::COND_B;
11413 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
11414 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
11415 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
11416 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
11417 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
11418 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
11421 // SSE/AVX shift intrinsics
11422 case Intrinsic::x86_sse2_psll_w:
11423 case Intrinsic::x86_sse2_psll_d:
11424 case Intrinsic::x86_sse2_psll_q:
11425 case Intrinsic::x86_avx2_psll_w:
11426 case Intrinsic::x86_avx2_psll_d:
11427 case Intrinsic::x86_avx2_psll_q:
11428 case Intrinsic::x86_sse2_psrl_w:
11429 case Intrinsic::x86_sse2_psrl_d:
11430 case Intrinsic::x86_sse2_psrl_q:
11431 case Intrinsic::x86_avx2_psrl_w:
11432 case Intrinsic::x86_avx2_psrl_d:
11433 case Intrinsic::x86_avx2_psrl_q:
11434 case Intrinsic::x86_sse2_psra_w:
11435 case Intrinsic::x86_sse2_psra_d:
11436 case Intrinsic::x86_avx2_psra_w:
11437 case Intrinsic::x86_avx2_psra_d: {
11440 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11441 case Intrinsic::x86_sse2_psll_w:
11442 case Intrinsic::x86_sse2_psll_d:
11443 case Intrinsic::x86_sse2_psll_q:
11444 case Intrinsic::x86_avx2_psll_w:
11445 case Intrinsic::x86_avx2_psll_d:
11446 case Intrinsic::x86_avx2_psll_q:
11447 Opcode = X86ISD::VSHL;
11449 case Intrinsic::x86_sse2_psrl_w:
11450 case Intrinsic::x86_sse2_psrl_d:
11451 case Intrinsic::x86_sse2_psrl_q:
11452 case Intrinsic::x86_avx2_psrl_w:
11453 case Intrinsic::x86_avx2_psrl_d:
11454 case Intrinsic::x86_avx2_psrl_q:
11455 Opcode = X86ISD::VSRL;
11457 case Intrinsic::x86_sse2_psra_w:
11458 case Intrinsic::x86_sse2_psra_d:
11459 case Intrinsic::x86_avx2_psra_w:
11460 case Intrinsic::x86_avx2_psra_d:
11461 Opcode = X86ISD::VSRA;
11464 return DAG.getNode(Opcode, dl, Op.getValueType(),
11465 Op.getOperand(1), Op.getOperand(2));
11468 // SSE/AVX immediate shift intrinsics
11469 case Intrinsic::x86_sse2_pslli_w:
11470 case Intrinsic::x86_sse2_pslli_d:
11471 case Intrinsic::x86_sse2_pslli_q:
11472 case Intrinsic::x86_avx2_pslli_w:
11473 case Intrinsic::x86_avx2_pslli_d:
11474 case Intrinsic::x86_avx2_pslli_q:
11475 case Intrinsic::x86_sse2_psrli_w:
11476 case Intrinsic::x86_sse2_psrli_d:
11477 case Intrinsic::x86_sse2_psrli_q:
11478 case Intrinsic::x86_avx2_psrli_w:
11479 case Intrinsic::x86_avx2_psrli_d:
11480 case Intrinsic::x86_avx2_psrli_q:
11481 case Intrinsic::x86_sse2_psrai_w:
11482 case Intrinsic::x86_sse2_psrai_d:
11483 case Intrinsic::x86_avx2_psrai_w:
11484 case Intrinsic::x86_avx2_psrai_d: {
11487 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11488 case Intrinsic::x86_sse2_pslli_w:
11489 case Intrinsic::x86_sse2_pslli_d:
11490 case Intrinsic::x86_sse2_pslli_q:
11491 case Intrinsic::x86_avx2_pslli_w:
11492 case Intrinsic::x86_avx2_pslli_d:
11493 case Intrinsic::x86_avx2_pslli_q:
11494 Opcode = X86ISD::VSHLI;
11496 case Intrinsic::x86_sse2_psrli_w:
11497 case Intrinsic::x86_sse2_psrli_d:
11498 case Intrinsic::x86_sse2_psrli_q:
11499 case Intrinsic::x86_avx2_psrli_w:
11500 case Intrinsic::x86_avx2_psrli_d:
11501 case Intrinsic::x86_avx2_psrli_q:
11502 Opcode = X86ISD::VSRLI;
11504 case Intrinsic::x86_sse2_psrai_w:
11505 case Intrinsic::x86_sse2_psrai_d:
11506 case Intrinsic::x86_avx2_psrai_w:
11507 case Intrinsic::x86_avx2_psrai_d:
11508 Opcode = X86ISD::VSRAI;
11511 return getTargetVShiftNode(Opcode, dl, Op.getValueType(),
11512 Op.getOperand(1), Op.getOperand(2), DAG);
11515 case Intrinsic::x86_sse42_pcmpistria128:
11516 case Intrinsic::x86_sse42_pcmpestria128:
11517 case Intrinsic::x86_sse42_pcmpistric128:
11518 case Intrinsic::x86_sse42_pcmpestric128:
11519 case Intrinsic::x86_sse42_pcmpistrio128:
11520 case Intrinsic::x86_sse42_pcmpestrio128:
11521 case Intrinsic::x86_sse42_pcmpistris128:
11522 case Intrinsic::x86_sse42_pcmpestris128:
11523 case Intrinsic::x86_sse42_pcmpistriz128:
11524 case Intrinsic::x86_sse42_pcmpestriz128: {
11528 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11529 case Intrinsic::x86_sse42_pcmpistria128:
11530 Opcode = X86ISD::PCMPISTRI;
11531 X86CC = X86::COND_A;
11533 case Intrinsic::x86_sse42_pcmpestria128:
11534 Opcode = X86ISD::PCMPESTRI;
11535 X86CC = X86::COND_A;
11537 case Intrinsic::x86_sse42_pcmpistric128:
11538 Opcode = X86ISD::PCMPISTRI;
11539 X86CC = X86::COND_B;
11541 case Intrinsic::x86_sse42_pcmpestric128:
11542 Opcode = X86ISD::PCMPESTRI;
11543 X86CC = X86::COND_B;
11545 case Intrinsic::x86_sse42_pcmpistrio128:
11546 Opcode = X86ISD::PCMPISTRI;
11547 X86CC = X86::COND_O;
11549 case Intrinsic::x86_sse42_pcmpestrio128:
11550 Opcode = X86ISD::PCMPESTRI;
11551 X86CC = X86::COND_O;
11553 case Intrinsic::x86_sse42_pcmpistris128:
11554 Opcode = X86ISD::PCMPISTRI;
11555 X86CC = X86::COND_S;
11557 case Intrinsic::x86_sse42_pcmpestris128:
11558 Opcode = X86ISD::PCMPESTRI;
11559 X86CC = X86::COND_S;
11561 case Intrinsic::x86_sse42_pcmpistriz128:
11562 Opcode = X86ISD::PCMPISTRI;
11563 X86CC = X86::COND_E;
11565 case Intrinsic::x86_sse42_pcmpestriz128:
11566 Opcode = X86ISD::PCMPESTRI;
11567 X86CC = X86::COND_E;
11570 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
11571 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
11572 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps.data(), NewOps.size());
11573 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
11574 DAG.getConstant(X86CC, MVT::i8),
11575 SDValue(PCMP.getNode(), 1));
11576 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
11579 case Intrinsic::x86_sse42_pcmpistri128:
11580 case Intrinsic::x86_sse42_pcmpestri128: {
11582 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
11583 Opcode = X86ISD::PCMPISTRI;
11585 Opcode = X86ISD::PCMPESTRI;
11587 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
11588 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
11589 return DAG.getNode(Opcode, dl, VTs, NewOps.data(), NewOps.size());
11591 case Intrinsic::x86_fma_vfmadd_ps:
11592 case Intrinsic::x86_fma_vfmadd_pd:
11593 case Intrinsic::x86_fma_vfmsub_ps:
11594 case Intrinsic::x86_fma_vfmsub_pd:
11595 case Intrinsic::x86_fma_vfnmadd_ps:
11596 case Intrinsic::x86_fma_vfnmadd_pd:
11597 case Intrinsic::x86_fma_vfnmsub_ps:
11598 case Intrinsic::x86_fma_vfnmsub_pd:
11599 case Intrinsic::x86_fma_vfmaddsub_ps:
11600 case Intrinsic::x86_fma_vfmaddsub_pd:
11601 case Intrinsic::x86_fma_vfmsubadd_ps:
11602 case Intrinsic::x86_fma_vfmsubadd_pd:
11603 case Intrinsic::x86_fma_vfmadd_ps_256:
11604 case Intrinsic::x86_fma_vfmadd_pd_256:
11605 case Intrinsic::x86_fma_vfmsub_ps_256:
11606 case Intrinsic::x86_fma_vfmsub_pd_256:
11607 case Intrinsic::x86_fma_vfnmadd_ps_256:
11608 case Intrinsic::x86_fma_vfnmadd_pd_256:
11609 case Intrinsic::x86_fma_vfnmsub_ps_256:
11610 case Intrinsic::x86_fma_vfnmsub_pd_256:
11611 case Intrinsic::x86_fma_vfmaddsub_ps_256:
11612 case Intrinsic::x86_fma_vfmaddsub_pd_256:
11613 case Intrinsic::x86_fma_vfmsubadd_ps_256:
11614 case Intrinsic::x86_fma_vfmsubadd_pd_256: {
11617 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11618 case Intrinsic::x86_fma_vfmadd_ps:
11619 case Intrinsic::x86_fma_vfmadd_pd:
11620 case Intrinsic::x86_fma_vfmadd_ps_256:
11621 case Intrinsic::x86_fma_vfmadd_pd_256:
11622 Opc = X86ISD::FMADD;
11624 case Intrinsic::x86_fma_vfmsub_ps:
11625 case Intrinsic::x86_fma_vfmsub_pd:
11626 case Intrinsic::x86_fma_vfmsub_ps_256:
11627 case Intrinsic::x86_fma_vfmsub_pd_256:
11628 Opc = X86ISD::FMSUB;
11630 case Intrinsic::x86_fma_vfnmadd_ps:
11631 case Intrinsic::x86_fma_vfnmadd_pd:
11632 case Intrinsic::x86_fma_vfnmadd_ps_256:
11633 case Intrinsic::x86_fma_vfnmadd_pd_256:
11634 Opc = X86ISD::FNMADD;
11636 case Intrinsic::x86_fma_vfnmsub_ps:
11637 case Intrinsic::x86_fma_vfnmsub_pd:
11638 case Intrinsic::x86_fma_vfnmsub_ps_256:
11639 case Intrinsic::x86_fma_vfnmsub_pd_256:
11640 Opc = X86ISD::FNMSUB;
11642 case Intrinsic::x86_fma_vfmaddsub_ps:
11643 case Intrinsic::x86_fma_vfmaddsub_pd:
11644 case Intrinsic::x86_fma_vfmaddsub_ps_256:
11645 case Intrinsic::x86_fma_vfmaddsub_pd_256:
11646 Opc = X86ISD::FMADDSUB;
11648 case Intrinsic::x86_fma_vfmsubadd_ps:
11649 case Intrinsic::x86_fma_vfmsubadd_pd:
11650 case Intrinsic::x86_fma_vfmsubadd_ps_256:
11651 case Intrinsic::x86_fma_vfmsubadd_pd_256:
11652 Opc = X86ISD::FMSUBADD;
11656 return DAG.getNode(Opc, dl, Op.getValueType(), Op.getOperand(1),
11657 Op.getOperand(2), Op.getOperand(3));
11662 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
11663 SDValue Base, SDValue Index,
11664 SDValue ScaleOp, SDValue Chain,
11665 const X86Subtarget * Subtarget) {
11667 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
11668 assert(C && "Invalid scale type");
11669 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
11670 SDValue Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
11671 EVT MaskVT = MVT::getVectorVT(MVT::i1,
11672 Index.getValueType().getVectorNumElements());
11673 SDValue MaskInReg = DAG.getConstant(~0, MaskVT);
11674 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
11675 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
11676 SDValue Segment = DAG.getRegister(0, MVT::i32);
11677 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
11678 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
11679 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
11680 return DAG.getMergeValues(RetOps, array_lengthof(RetOps), dl);
11683 static SDValue getMGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
11684 SDValue Src, SDValue Mask, SDValue Base,
11685 SDValue Index, SDValue ScaleOp, SDValue Chain,
11686 const X86Subtarget * Subtarget) {
11688 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
11689 assert(C && "Invalid scale type");
11690 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
11691 EVT MaskVT = MVT::getVectorVT(MVT::i1,
11692 Index.getValueType().getVectorNumElements());
11693 SDValue MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
11694 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
11695 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
11696 SDValue Segment = DAG.getRegister(0, MVT::i32);
11697 if (Src.getOpcode() == ISD::UNDEF)
11698 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
11699 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
11700 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
11701 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
11702 return DAG.getMergeValues(RetOps, array_lengthof(RetOps), dl);
11705 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
11706 SDValue Src, SDValue Base, SDValue Index,
11707 SDValue ScaleOp, SDValue Chain) {
11709 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
11710 assert(C && "Invalid scale type");
11711 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
11712 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
11713 SDValue Segment = DAG.getRegister(0, MVT::i32);
11714 EVT MaskVT = MVT::getVectorVT(MVT::i1,
11715 Index.getValueType().getVectorNumElements());
11716 SDValue MaskInReg = DAG.getConstant(~0, MaskVT);
11717 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
11718 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
11719 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
11720 return SDValue(Res, 1);
11723 static SDValue getMScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
11724 SDValue Src, SDValue Mask, SDValue Base,
11725 SDValue Index, SDValue ScaleOp, SDValue Chain) {
11727 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
11728 assert(C && "Invalid scale type");
11729 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
11730 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
11731 SDValue Segment = DAG.getRegister(0, MVT::i32);
11732 EVT MaskVT = MVT::getVectorVT(MVT::i1,
11733 Index.getValueType().getVectorNumElements());
11734 SDValue MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
11735 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
11736 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
11737 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
11738 return SDValue(Res, 1);
11741 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
11742 SelectionDAG &DAG) {
11744 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11746 default: return SDValue(); // Don't custom lower most intrinsics.
11748 // RDRAND/RDSEED intrinsics.
11749 case Intrinsic::x86_rdrand_16:
11750 case Intrinsic::x86_rdrand_32:
11751 case Intrinsic::x86_rdrand_64:
11752 case Intrinsic::x86_rdseed_16:
11753 case Intrinsic::x86_rdseed_32:
11754 case Intrinsic::x86_rdseed_64: {
11755 unsigned Opcode = (IntNo == Intrinsic::x86_rdseed_16 ||
11756 IntNo == Intrinsic::x86_rdseed_32 ||
11757 IntNo == Intrinsic::x86_rdseed_64) ? X86ISD::RDSEED :
11759 // Emit the node with the right value type.
11760 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
11761 SDValue Result = DAG.getNode(Opcode, dl, VTs, Op.getOperand(0));
11763 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
11764 // Otherwise return the value from Rand, which is always 0, casted to i32.
11765 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
11766 DAG.getConstant(1, Op->getValueType(1)),
11767 DAG.getConstant(X86::COND_B, MVT::i32),
11768 SDValue(Result.getNode(), 1) };
11769 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
11770 DAG.getVTList(Op->getValueType(1), MVT::Glue),
11771 Ops, array_lengthof(Ops));
11773 // Return { result, isValid, chain }.
11774 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
11775 SDValue(Result.getNode(), 2));
11777 //int_gather(index, base, scale);
11778 case Intrinsic::x86_avx512_gather_qpd_512:
11779 case Intrinsic::x86_avx512_gather_qps_512:
11780 case Intrinsic::x86_avx512_gather_dpd_512:
11781 case Intrinsic::x86_avx512_gather_qpi_512:
11782 case Intrinsic::x86_avx512_gather_qpq_512:
11783 case Intrinsic::x86_avx512_gather_dpq_512:
11784 case Intrinsic::x86_avx512_gather_dps_512:
11785 case Intrinsic::x86_avx512_gather_dpi_512: {
11788 default: llvm_unreachable("Unexpected intrinsic!");
11789 case Intrinsic::x86_avx512_gather_qps_512: Opc = X86::VGATHERQPSZrm; break;
11790 case Intrinsic::x86_avx512_gather_qpd_512: Opc = X86::VGATHERQPDZrm; break;
11791 case Intrinsic::x86_avx512_gather_dpd_512: Opc = X86::VGATHERDPDZrm; break;
11792 case Intrinsic::x86_avx512_gather_dps_512: Opc = X86::VGATHERDPSZrm; break;
11793 case Intrinsic::x86_avx512_gather_qpi_512: Opc = X86::VPGATHERQDZrm; break;
11794 case Intrinsic::x86_avx512_gather_qpq_512: Opc = X86::VPGATHERQQZrm; break;
11795 case Intrinsic::x86_avx512_gather_dpi_512: Opc = X86::VPGATHERDDZrm; break;
11796 case Intrinsic::x86_avx512_gather_dpq_512: Opc = X86::VPGATHERDQZrm; break;
11798 SDValue Chain = Op.getOperand(0);
11799 SDValue Index = Op.getOperand(2);
11800 SDValue Base = Op.getOperand(3);
11801 SDValue Scale = Op.getOperand(4);
11802 return getGatherNode(Opc, Op, DAG, Base, Index, Scale, Chain, Subtarget);
11804 //int_gather_mask(v1, mask, index, base, scale);
11805 case Intrinsic::x86_avx512_gather_qps_mask_512:
11806 case Intrinsic::x86_avx512_gather_qpd_mask_512:
11807 case Intrinsic::x86_avx512_gather_dpd_mask_512:
11808 case Intrinsic::x86_avx512_gather_dps_mask_512:
11809 case Intrinsic::x86_avx512_gather_qpi_mask_512:
11810 case Intrinsic::x86_avx512_gather_qpq_mask_512:
11811 case Intrinsic::x86_avx512_gather_dpi_mask_512:
11812 case Intrinsic::x86_avx512_gather_dpq_mask_512: {
11815 default: llvm_unreachable("Unexpected intrinsic!");
11816 case Intrinsic::x86_avx512_gather_qps_mask_512:
11817 Opc = X86::VGATHERQPSZrm; break;
11818 case Intrinsic::x86_avx512_gather_qpd_mask_512:
11819 Opc = X86::VGATHERQPDZrm; break;
11820 case Intrinsic::x86_avx512_gather_dpd_mask_512:
11821 Opc = X86::VGATHERDPDZrm; break;
11822 case Intrinsic::x86_avx512_gather_dps_mask_512:
11823 Opc = X86::VGATHERDPSZrm; break;
11824 case Intrinsic::x86_avx512_gather_qpi_mask_512:
11825 Opc = X86::VPGATHERQDZrm; break;
11826 case Intrinsic::x86_avx512_gather_qpq_mask_512:
11827 Opc = X86::VPGATHERQQZrm; break;
11828 case Intrinsic::x86_avx512_gather_dpi_mask_512:
11829 Opc = X86::VPGATHERDDZrm; break;
11830 case Intrinsic::x86_avx512_gather_dpq_mask_512:
11831 Opc = X86::VPGATHERDQZrm; break;
11833 SDValue Chain = Op.getOperand(0);
11834 SDValue Src = Op.getOperand(2);
11835 SDValue Mask = Op.getOperand(3);
11836 SDValue Index = Op.getOperand(4);
11837 SDValue Base = Op.getOperand(5);
11838 SDValue Scale = Op.getOperand(6);
11839 return getMGatherNode(Opc, Op, DAG, Src, Mask, Base, Index, Scale, Chain,
11842 //int_scatter(base, index, v1, scale);
11843 case Intrinsic::x86_avx512_scatter_qpd_512:
11844 case Intrinsic::x86_avx512_scatter_qps_512:
11845 case Intrinsic::x86_avx512_scatter_dpd_512:
11846 case Intrinsic::x86_avx512_scatter_qpi_512:
11847 case Intrinsic::x86_avx512_scatter_qpq_512:
11848 case Intrinsic::x86_avx512_scatter_dpq_512:
11849 case Intrinsic::x86_avx512_scatter_dps_512:
11850 case Intrinsic::x86_avx512_scatter_dpi_512: {
11853 default: llvm_unreachable("Unexpected intrinsic!");
11854 case Intrinsic::x86_avx512_scatter_qpd_512:
11855 Opc = X86::VSCATTERQPDZmr; break;
11856 case Intrinsic::x86_avx512_scatter_qps_512:
11857 Opc = X86::VSCATTERQPSZmr; break;
11858 case Intrinsic::x86_avx512_scatter_dpd_512:
11859 Opc = X86::VSCATTERDPDZmr; break;
11860 case Intrinsic::x86_avx512_scatter_dps_512:
11861 Opc = X86::VSCATTERDPSZmr; break;
11862 case Intrinsic::x86_avx512_scatter_qpi_512:
11863 Opc = X86::VPSCATTERQDZmr; break;
11864 case Intrinsic::x86_avx512_scatter_qpq_512:
11865 Opc = X86::VPSCATTERQQZmr; break;
11866 case Intrinsic::x86_avx512_scatter_dpq_512:
11867 Opc = X86::VPSCATTERDQZmr; break;
11868 case Intrinsic::x86_avx512_scatter_dpi_512:
11869 Opc = X86::VPSCATTERDDZmr; break;
11871 SDValue Chain = Op.getOperand(0);
11872 SDValue Base = Op.getOperand(2);
11873 SDValue Index = Op.getOperand(3);
11874 SDValue Src = Op.getOperand(4);
11875 SDValue Scale = Op.getOperand(5);
11876 return getScatterNode(Opc, Op, DAG, Src, Base, Index, Scale, Chain);
11878 //int_scatter_mask(base, mask, index, v1, scale);
11879 case Intrinsic::x86_avx512_scatter_qps_mask_512:
11880 case Intrinsic::x86_avx512_scatter_qpd_mask_512:
11881 case Intrinsic::x86_avx512_scatter_dpd_mask_512:
11882 case Intrinsic::x86_avx512_scatter_dps_mask_512:
11883 case Intrinsic::x86_avx512_scatter_qpi_mask_512:
11884 case Intrinsic::x86_avx512_scatter_qpq_mask_512:
11885 case Intrinsic::x86_avx512_scatter_dpi_mask_512:
11886 case Intrinsic::x86_avx512_scatter_dpq_mask_512: {
11889 default: llvm_unreachable("Unexpected intrinsic!");
11890 case Intrinsic::x86_avx512_scatter_qpd_mask_512:
11891 Opc = X86::VSCATTERQPDZmr; break;
11892 case Intrinsic::x86_avx512_scatter_qps_mask_512:
11893 Opc = X86::VSCATTERQPSZmr; break;
11894 case Intrinsic::x86_avx512_scatter_dpd_mask_512:
11895 Opc = X86::VSCATTERDPDZmr; break;
11896 case Intrinsic::x86_avx512_scatter_dps_mask_512:
11897 Opc = X86::VSCATTERDPSZmr; break;
11898 case Intrinsic::x86_avx512_scatter_qpi_mask_512:
11899 Opc = X86::VPSCATTERQDZmr; break;
11900 case Intrinsic::x86_avx512_scatter_qpq_mask_512:
11901 Opc = X86::VPSCATTERQQZmr; break;
11902 case Intrinsic::x86_avx512_scatter_dpq_mask_512:
11903 Opc = X86::VPSCATTERDQZmr; break;
11904 case Intrinsic::x86_avx512_scatter_dpi_mask_512:
11905 Opc = X86::VPSCATTERDDZmr; break;
11907 SDValue Chain = Op.getOperand(0);
11908 SDValue Base = Op.getOperand(2);
11909 SDValue Mask = Op.getOperand(3);
11910 SDValue Index = Op.getOperand(4);
11911 SDValue Src = Op.getOperand(5);
11912 SDValue Scale = Op.getOperand(6);
11913 return getMScatterNode(Opc, Op, DAG, Src, Mask, Base, Index, Scale, Chain);
11915 // XTEST intrinsics.
11916 case Intrinsic::x86_xtest: {
11917 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
11918 SDValue InTrans = DAG.getNode(X86ISD::XTEST, dl, VTs, Op.getOperand(0));
11919 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
11920 DAG.getConstant(X86::COND_NE, MVT::i8),
11922 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
11923 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
11924 Ret, SDValue(InTrans.getNode(), 1));
11929 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
11930 SelectionDAG &DAG) const {
11931 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
11932 MFI->setReturnAddressIsTaken(true);
11934 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
11936 EVT PtrVT = getPointerTy();
11939 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
11940 const X86RegisterInfo *RegInfo =
11941 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
11942 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
11943 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
11944 DAG.getNode(ISD::ADD, dl, PtrVT,
11945 FrameAddr, Offset),
11946 MachinePointerInfo(), false, false, false, 0);
11949 // Just load the return address.
11950 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
11951 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
11952 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
11955 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
11956 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
11957 MFI->setFrameAddressIsTaken(true);
11959 EVT VT = Op.getValueType();
11960 SDLoc dl(Op); // FIXME probably not meaningful
11961 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
11962 const X86RegisterInfo *RegInfo =
11963 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
11964 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
11965 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
11966 (FrameReg == X86::EBP && VT == MVT::i32)) &&
11967 "Invalid Frame Register!");
11968 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
11970 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
11971 MachinePointerInfo(),
11972 false, false, false, 0);
11976 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
11977 SelectionDAG &DAG) const {
11978 const X86RegisterInfo *RegInfo =
11979 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
11980 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
11983 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
11984 SDValue Chain = Op.getOperand(0);
11985 SDValue Offset = Op.getOperand(1);
11986 SDValue Handler = Op.getOperand(2);
11989 EVT PtrVT = getPointerTy();
11990 const X86RegisterInfo *RegInfo =
11991 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
11992 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
11993 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
11994 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
11995 "Invalid Frame Register!");
11996 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
11997 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
11999 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
12000 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
12001 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
12002 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
12004 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
12006 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
12007 DAG.getRegister(StoreAddrReg, PtrVT));
12010 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
12011 SelectionDAG &DAG) const {
12013 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
12014 DAG.getVTList(MVT::i32, MVT::Other),
12015 Op.getOperand(0), Op.getOperand(1));
12018 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
12019 SelectionDAG &DAG) const {
12021 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
12022 Op.getOperand(0), Op.getOperand(1));
12025 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
12026 return Op.getOperand(0);
12029 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
12030 SelectionDAG &DAG) const {
12031 SDValue Root = Op.getOperand(0);
12032 SDValue Trmp = Op.getOperand(1); // trampoline
12033 SDValue FPtr = Op.getOperand(2); // nested function
12034 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
12037 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
12038 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
12040 if (Subtarget->is64Bit()) {
12041 SDValue OutChains[6];
12043 // Large code-model.
12044 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
12045 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
12047 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
12048 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
12050 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
12052 // Load the pointer to the nested function into R11.
12053 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
12054 SDValue Addr = Trmp;
12055 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
12056 Addr, MachinePointerInfo(TrmpAddr),
12059 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
12060 DAG.getConstant(2, MVT::i64));
12061 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
12062 MachinePointerInfo(TrmpAddr, 2),
12065 // Load the 'nest' parameter value into R10.
12066 // R10 is specified in X86CallingConv.td
12067 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
12068 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
12069 DAG.getConstant(10, MVT::i64));
12070 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
12071 Addr, MachinePointerInfo(TrmpAddr, 10),
12074 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
12075 DAG.getConstant(12, MVT::i64));
12076 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
12077 MachinePointerInfo(TrmpAddr, 12),
12080 // Jump to the nested function.
12081 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
12082 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
12083 DAG.getConstant(20, MVT::i64));
12084 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
12085 Addr, MachinePointerInfo(TrmpAddr, 20),
12088 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
12089 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
12090 DAG.getConstant(22, MVT::i64));
12091 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
12092 MachinePointerInfo(TrmpAddr, 22),
12095 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6);
12097 const Function *Func =
12098 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
12099 CallingConv::ID CC = Func->getCallingConv();
12104 llvm_unreachable("Unsupported calling convention");
12105 case CallingConv::C:
12106 case CallingConv::X86_StdCall: {
12107 // Pass 'nest' parameter in ECX.
12108 // Must be kept in sync with X86CallingConv.td
12109 NestReg = X86::ECX;
12111 // Check that ECX wasn't needed by an 'inreg' parameter.
12112 FunctionType *FTy = Func->getFunctionType();
12113 const AttributeSet &Attrs = Func->getAttributes();
12115 if (!Attrs.isEmpty() && !Func->isVarArg()) {
12116 unsigned InRegCount = 0;
12119 for (FunctionType::param_iterator I = FTy->param_begin(),
12120 E = FTy->param_end(); I != E; ++I, ++Idx)
12121 if (Attrs.hasAttribute(Idx, Attribute::InReg))
12122 // FIXME: should only count parameters that are lowered to integers.
12123 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
12125 if (InRegCount > 2) {
12126 report_fatal_error("Nest register in use - reduce number of inreg"
12132 case CallingConv::X86_FastCall:
12133 case CallingConv::X86_ThisCall:
12134 case CallingConv::Fast:
12135 // Pass 'nest' parameter in EAX.
12136 // Must be kept in sync with X86CallingConv.td
12137 NestReg = X86::EAX;
12141 SDValue OutChains[4];
12142 SDValue Addr, Disp;
12144 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
12145 DAG.getConstant(10, MVT::i32));
12146 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
12148 // This is storing the opcode for MOV32ri.
12149 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
12150 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
12151 OutChains[0] = DAG.getStore(Root, dl,
12152 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
12153 Trmp, MachinePointerInfo(TrmpAddr),
12156 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
12157 DAG.getConstant(1, MVT::i32));
12158 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
12159 MachinePointerInfo(TrmpAddr, 1),
12162 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
12163 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
12164 DAG.getConstant(5, MVT::i32));
12165 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
12166 MachinePointerInfo(TrmpAddr, 5),
12169 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
12170 DAG.getConstant(6, MVT::i32));
12171 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
12172 MachinePointerInfo(TrmpAddr, 6),
12175 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4);
12179 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
12180 SelectionDAG &DAG) const {
12182 The rounding mode is in bits 11:10 of FPSR, and has the following
12184 00 Round to nearest
12189 FLT_ROUNDS, on the other hand, expects the following:
12196 To perform the conversion, we do:
12197 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
12200 MachineFunction &MF = DAG.getMachineFunction();
12201 const TargetMachine &TM = MF.getTarget();
12202 const TargetFrameLowering &TFI = *TM.getFrameLowering();
12203 unsigned StackAlignment = TFI.getStackAlignment();
12204 EVT VT = Op.getValueType();
12207 // Save FP Control Word to stack slot
12208 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
12209 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
12211 MachineMemOperand *MMO =
12212 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12213 MachineMemOperand::MOStore, 2, 2);
12215 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
12216 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
12217 DAG.getVTList(MVT::Other),
12218 Ops, array_lengthof(Ops), MVT::i16,
12221 // Load FP Control Word from stack slot
12222 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
12223 MachinePointerInfo(), false, false, false, 0);
12225 // Transform as necessary
12227 DAG.getNode(ISD::SRL, DL, MVT::i16,
12228 DAG.getNode(ISD::AND, DL, MVT::i16,
12229 CWD, DAG.getConstant(0x800, MVT::i16)),
12230 DAG.getConstant(11, MVT::i8));
12232 DAG.getNode(ISD::SRL, DL, MVT::i16,
12233 DAG.getNode(ISD::AND, DL, MVT::i16,
12234 CWD, DAG.getConstant(0x400, MVT::i16)),
12235 DAG.getConstant(9, MVT::i8));
12238 DAG.getNode(ISD::AND, DL, MVT::i16,
12239 DAG.getNode(ISD::ADD, DL, MVT::i16,
12240 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
12241 DAG.getConstant(1, MVT::i16)),
12242 DAG.getConstant(3, MVT::i16));
12244 return DAG.getNode((VT.getSizeInBits() < 16 ?
12245 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
12248 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
12249 EVT VT = Op.getValueType();
12251 unsigned NumBits = VT.getSizeInBits();
12254 Op = Op.getOperand(0);
12255 if (VT == MVT::i8) {
12256 // Zero extend to i32 since there is not an i8 bsr.
12258 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
12261 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
12262 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
12263 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
12265 // If src is zero (i.e. bsr sets ZF), returns NumBits.
12268 DAG.getConstant(NumBits+NumBits-1, OpVT),
12269 DAG.getConstant(X86::COND_E, MVT::i8),
12272 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
12274 // Finally xor with NumBits-1.
12275 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
12278 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
12282 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
12283 EVT VT = Op.getValueType();
12285 unsigned NumBits = VT.getSizeInBits();
12288 Op = Op.getOperand(0);
12289 if (VT == MVT::i8) {
12290 // Zero extend to i32 since there is not an i8 bsr.
12292 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
12295 // Issue a bsr (scan bits in reverse).
12296 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
12297 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
12299 // And xor with NumBits-1.
12300 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
12303 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
12307 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
12308 EVT VT = Op.getValueType();
12309 unsigned NumBits = VT.getSizeInBits();
12311 Op = Op.getOperand(0);
12313 // Issue a bsf (scan bits forward) which also sets EFLAGS.
12314 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
12315 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
12317 // If src is zero (i.e. bsf sets ZF), returns NumBits.
12320 DAG.getConstant(NumBits, VT),
12321 DAG.getConstant(X86::COND_E, MVT::i8),
12324 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops, array_lengthof(Ops));
12327 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
12328 // ones, and then concatenate the result back.
12329 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
12330 EVT VT = Op.getValueType();
12332 assert(VT.is256BitVector() && VT.isInteger() &&
12333 "Unsupported value type for operation");
12335 unsigned NumElems = VT.getVectorNumElements();
12338 // Extract the LHS vectors
12339 SDValue LHS = Op.getOperand(0);
12340 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
12341 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
12343 // Extract the RHS vectors
12344 SDValue RHS = Op.getOperand(1);
12345 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
12346 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
12348 MVT EltVT = VT.getVectorElementType().getSimpleVT();
12349 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
12351 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
12352 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
12353 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
12356 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
12357 assert(Op.getValueType().is256BitVector() &&
12358 Op.getValueType().isInteger() &&
12359 "Only handle AVX 256-bit vector integer operation");
12360 return Lower256IntArith(Op, DAG);
12363 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
12364 assert(Op.getValueType().is256BitVector() &&
12365 Op.getValueType().isInteger() &&
12366 "Only handle AVX 256-bit vector integer operation");
12367 return Lower256IntArith(Op, DAG);
12370 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
12371 SelectionDAG &DAG) {
12373 EVT VT = Op.getValueType();
12375 // Decompose 256-bit ops into smaller 128-bit ops.
12376 if (VT.is256BitVector() && !Subtarget->hasInt256())
12377 return Lower256IntArith(Op, DAG);
12379 SDValue A = Op.getOperand(0);
12380 SDValue B = Op.getOperand(1);
12382 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
12383 if (VT == MVT::v4i32) {
12384 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
12385 "Should not custom lower when pmuldq is available!");
12387 // Extract the odd parts.
12388 static const int UnpackMask[] = { 1, -1, 3, -1 };
12389 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
12390 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
12392 // Multiply the even parts.
12393 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
12394 // Now multiply odd parts.
12395 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
12397 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
12398 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
12400 // Merge the two vectors back together with a shuffle. This expands into 2
12402 static const int ShufMask[] = { 0, 4, 2, 6 };
12403 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
12406 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
12407 "Only know how to lower V2I64/V4I64/V8I64 multiply");
12409 // Ahi = psrlqi(a, 32);
12410 // Bhi = psrlqi(b, 32);
12412 // AloBlo = pmuludq(a, b);
12413 // AloBhi = pmuludq(a, Bhi);
12414 // AhiBlo = pmuludq(Ahi, b);
12416 // AloBhi = psllqi(AloBhi, 32);
12417 // AhiBlo = psllqi(AhiBlo, 32);
12418 // return AloBlo + AloBhi + AhiBlo;
12420 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
12421 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
12423 // Bit cast to 32-bit vectors for MULUDQ
12424 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
12425 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
12426 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
12427 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
12428 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
12429 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
12431 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
12432 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
12433 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
12435 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
12436 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
12438 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
12439 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
12442 static SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG) {
12443 EVT VT = Op.getValueType();
12444 EVT EltTy = VT.getVectorElementType();
12445 unsigned NumElts = VT.getVectorNumElements();
12446 SDValue N0 = Op.getOperand(0);
12449 // Lower sdiv X, pow2-const.
12450 BuildVectorSDNode *C = dyn_cast<BuildVectorSDNode>(Op.getOperand(1));
12454 APInt SplatValue, SplatUndef;
12455 unsigned SplatBitSize;
12457 if (!C->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
12459 EltTy.getSizeInBits() < SplatBitSize)
12462 if ((SplatValue != 0) &&
12463 (SplatValue.isPowerOf2() || (-SplatValue).isPowerOf2())) {
12464 unsigned Lg2 = SplatValue.countTrailingZeros();
12465 // Splat the sign bit.
12466 SmallVector<SDValue, 16> Sz(NumElts,
12467 DAG.getConstant(EltTy.getSizeInBits() - 1,
12469 SDValue SGN = DAG.getNode(ISD::SRA, dl, VT, N0,
12470 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Sz[0],
12472 // Add (N0 < 0) ? abs2 - 1 : 0;
12473 SmallVector<SDValue, 16> Amt(NumElts,
12474 DAG.getConstant(EltTy.getSizeInBits() - Lg2,
12476 SDValue SRL = DAG.getNode(ISD::SRL, dl, VT, SGN,
12477 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Amt[0],
12479 SDValue ADD = DAG.getNode(ISD::ADD, dl, VT, N0, SRL);
12480 SmallVector<SDValue, 16> Lg2Amt(NumElts, DAG.getConstant(Lg2, EltTy));
12481 SDValue SRA = DAG.getNode(ISD::SRA, dl, VT, ADD,
12482 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Lg2Amt[0],
12485 // If we're dividing by a positive value, we're done. Otherwise, we must
12486 // negate the result.
12487 if (SplatValue.isNonNegative())
12490 SmallVector<SDValue, 16> V(NumElts, DAG.getConstant(0, EltTy));
12491 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], NumElts);
12492 return DAG.getNode(ISD::SUB, dl, VT, Zero, SRA);
12497 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
12498 const X86Subtarget *Subtarget) {
12499 EVT VT = Op.getValueType();
12501 SDValue R = Op.getOperand(0);
12502 SDValue Amt = Op.getOperand(1);
12504 // Optimize shl/srl/sra with constant shift amount.
12505 if (isSplatVector(Amt.getNode())) {
12506 SDValue SclrAmt = Amt->getOperand(0);
12507 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
12508 uint64_t ShiftAmt = C->getZExtValue();
12510 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
12511 (Subtarget->hasInt256() &&
12512 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16)) ||
12513 (Subtarget->hasAVX512() &&
12514 (VT == MVT::v8i64 || VT == MVT::v16i32))) {
12515 if (Op.getOpcode() == ISD::SHL)
12516 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
12518 if (Op.getOpcode() == ISD::SRL)
12519 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
12521 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
12522 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
12526 if (VT == MVT::v16i8) {
12527 if (Op.getOpcode() == ISD::SHL) {
12528 // Make a large shift.
12529 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
12530 MVT::v8i16, R, ShiftAmt,
12532 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
12533 // Zero out the rightmost bits.
12534 SmallVector<SDValue, 16> V(16,
12535 DAG.getConstant(uint8_t(-1U << ShiftAmt),
12537 return DAG.getNode(ISD::AND, dl, VT, SHL,
12538 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
12540 if (Op.getOpcode() == ISD::SRL) {
12541 // Make a large shift.
12542 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
12543 MVT::v8i16, R, ShiftAmt,
12545 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
12546 // Zero out the leftmost bits.
12547 SmallVector<SDValue, 16> V(16,
12548 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
12550 return DAG.getNode(ISD::AND, dl, VT, SRL,
12551 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
12553 if (Op.getOpcode() == ISD::SRA) {
12554 if (ShiftAmt == 7) {
12555 // R s>> 7 === R s< 0
12556 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
12557 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
12560 // R s>> a === ((R u>> a) ^ m) - m
12561 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
12562 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
12564 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16);
12565 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
12566 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
12569 llvm_unreachable("Unknown shift opcode.");
12572 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
12573 if (Op.getOpcode() == ISD::SHL) {
12574 // Make a large shift.
12575 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
12576 MVT::v16i16, R, ShiftAmt,
12578 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
12579 // Zero out the rightmost bits.
12580 SmallVector<SDValue, 32> V(32,
12581 DAG.getConstant(uint8_t(-1U << ShiftAmt),
12583 return DAG.getNode(ISD::AND, dl, VT, SHL,
12584 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
12586 if (Op.getOpcode() == ISD::SRL) {
12587 // Make a large shift.
12588 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
12589 MVT::v16i16, R, ShiftAmt,
12591 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
12592 // Zero out the leftmost bits.
12593 SmallVector<SDValue, 32> V(32,
12594 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
12596 return DAG.getNode(ISD::AND, dl, VT, SRL,
12597 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
12599 if (Op.getOpcode() == ISD::SRA) {
12600 if (ShiftAmt == 7) {
12601 // R s>> 7 === R s< 0
12602 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
12603 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
12606 // R s>> a === ((R u>> a) ^ m) - m
12607 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
12608 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
12610 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32);
12611 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
12612 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
12615 llvm_unreachable("Unknown shift opcode.");
12620 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
12621 if (!Subtarget->is64Bit() &&
12622 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
12623 Amt.getOpcode() == ISD::BITCAST &&
12624 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
12625 Amt = Amt.getOperand(0);
12626 unsigned Ratio = Amt.getValueType().getVectorNumElements() /
12627 VT.getVectorNumElements();
12628 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
12629 uint64_t ShiftAmt = 0;
12630 for (unsigned i = 0; i != Ratio; ++i) {
12631 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
12635 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
12637 // Check remaining shift amounts.
12638 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
12639 uint64_t ShAmt = 0;
12640 for (unsigned j = 0; j != Ratio; ++j) {
12641 ConstantSDNode *C =
12642 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
12646 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
12648 if (ShAmt != ShiftAmt)
12651 switch (Op.getOpcode()) {
12653 llvm_unreachable("Unknown shift opcode!");
12655 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
12658 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
12661 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
12669 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
12670 const X86Subtarget* Subtarget) {
12671 EVT VT = Op.getValueType();
12673 SDValue R = Op.getOperand(0);
12674 SDValue Amt = Op.getOperand(1);
12676 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
12677 VT == MVT::v4i32 || VT == MVT::v8i16 ||
12678 (Subtarget->hasInt256() &&
12679 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
12680 VT == MVT::v8i32 || VT == MVT::v16i16)) ||
12681 (Subtarget->hasAVX512() && (VT == MVT::v8i64 || VT == MVT::v16i32))) {
12683 EVT EltVT = VT.getVectorElementType();
12685 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
12686 unsigned NumElts = VT.getVectorNumElements();
12688 for (i = 0; i != NumElts; ++i) {
12689 if (Amt.getOperand(i).getOpcode() == ISD::UNDEF)
12693 for (j = i; j != NumElts; ++j) {
12694 SDValue Arg = Amt.getOperand(j);
12695 if (Arg.getOpcode() == ISD::UNDEF) continue;
12696 if (Arg != Amt.getOperand(i))
12699 if (i != NumElts && j == NumElts)
12700 BaseShAmt = Amt.getOperand(i);
12702 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
12703 Amt = Amt.getOperand(0);
12704 if (Amt.getOpcode() == ISD::VECTOR_SHUFFLE &&
12705 cast<ShuffleVectorSDNode>(Amt)->isSplat()) {
12706 SDValue InVec = Amt.getOperand(0);
12707 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
12708 unsigned NumElts = InVec.getValueType().getVectorNumElements();
12710 for (; i != NumElts; ++i) {
12711 SDValue Arg = InVec.getOperand(i);
12712 if (Arg.getOpcode() == ISD::UNDEF) continue;
12716 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
12717 if (ConstantSDNode *C =
12718 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
12719 unsigned SplatIdx =
12720 cast<ShuffleVectorSDNode>(Amt)->getSplatIndex();
12721 if (C->getZExtValue() == SplatIdx)
12722 BaseShAmt = InVec.getOperand(1);
12725 if (BaseShAmt.getNode() == 0)
12726 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Amt,
12727 DAG.getIntPtrConstant(0));
12731 if (BaseShAmt.getNode()) {
12732 if (EltVT.bitsGT(MVT::i32))
12733 BaseShAmt = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BaseShAmt);
12734 else if (EltVT.bitsLT(MVT::i32))
12735 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
12737 switch (Op.getOpcode()) {
12739 llvm_unreachable("Unknown shift opcode!");
12741 switch (VT.getSimpleVT().SimpleTy) {
12742 default: return SDValue();
12751 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
12754 switch (VT.getSimpleVT().SimpleTy) {
12755 default: return SDValue();
12762 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
12765 switch (VT.getSimpleVT().SimpleTy) {
12766 default: return SDValue();
12775 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);
12781 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
12782 if (!Subtarget->is64Bit() &&
12783 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64) ||
12784 (Subtarget->hasAVX512() && VT == MVT::v8i64)) &&
12785 Amt.getOpcode() == ISD::BITCAST &&
12786 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
12787 Amt = Amt.getOperand(0);
12788 unsigned Ratio = Amt.getValueType().getVectorNumElements() /
12789 VT.getVectorNumElements();
12790 std::vector<SDValue> Vals(Ratio);
12791 for (unsigned i = 0; i != Ratio; ++i)
12792 Vals[i] = Amt.getOperand(i);
12793 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
12794 for (unsigned j = 0; j != Ratio; ++j)
12795 if (Vals[j] != Amt.getOperand(i + j))
12798 switch (Op.getOpcode()) {
12800 llvm_unreachable("Unknown shift opcode!");
12802 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1));
12804 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1));
12806 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1));
12813 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
12814 SelectionDAG &DAG) {
12816 EVT VT = Op.getValueType();
12818 SDValue R = Op.getOperand(0);
12819 SDValue Amt = Op.getOperand(1);
12822 if (!Subtarget->hasSSE2())
12825 V = LowerScalarImmediateShift(Op, DAG, Subtarget);
12829 V = LowerScalarVariableShift(Op, DAG, Subtarget);
12833 if (Subtarget->hasAVX512() && (VT == MVT::v16i32 || VT == MVT::v8i64))
12835 // AVX2 has VPSLLV/VPSRAV/VPSRLV.
12836 if (Subtarget->hasInt256()) {
12837 if (Op.getOpcode() == ISD::SRL &&
12838 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
12839 VT == MVT::v4i64 || VT == MVT::v8i32))
12841 if (Op.getOpcode() == ISD::SHL &&
12842 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
12843 VT == MVT::v4i64 || VT == MVT::v8i32))
12845 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
12849 // Lower SHL with variable shift amount.
12850 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
12851 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
12853 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
12854 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
12855 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
12856 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
12858 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
12859 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
12862 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
12863 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
12865 // Turn 'a' into a mask suitable for VSELECT
12866 SDValue VSelM = DAG.getConstant(0x80, VT);
12867 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
12868 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
12870 SDValue CM1 = DAG.getConstant(0x0f, VT);
12871 SDValue CM2 = DAG.getConstant(0x3f, VT);
12873 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
12874 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
12875 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 4, DAG);
12876 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
12877 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
12880 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
12881 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
12882 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
12884 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
12885 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
12886 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 2, DAG);
12887 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
12888 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
12891 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
12892 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
12893 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
12895 // return VSELECT(r, r+r, a);
12896 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
12897 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
12901 // Decompose 256-bit shifts into smaller 128-bit shifts.
12902 if (VT.is256BitVector()) {
12903 unsigned NumElems = VT.getVectorNumElements();
12904 MVT EltVT = VT.getVectorElementType().getSimpleVT();
12905 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
12907 // Extract the two vectors
12908 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
12909 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
12911 // Recreate the shift amount vectors
12912 SDValue Amt1, Amt2;
12913 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
12914 // Constant shift amount
12915 SmallVector<SDValue, 4> Amt1Csts;
12916 SmallVector<SDValue, 4> Amt2Csts;
12917 for (unsigned i = 0; i != NumElems/2; ++i)
12918 Amt1Csts.push_back(Amt->getOperand(i));
12919 for (unsigned i = NumElems/2; i != NumElems; ++i)
12920 Amt2Csts.push_back(Amt->getOperand(i));
12922 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
12923 &Amt1Csts[0], NumElems/2);
12924 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
12925 &Amt2Csts[0], NumElems/2);
12927 // Variable shift amount
12928 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
12929 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
12932 // Issue new vector shifts for the smaller types
12933 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
12934 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
12936 // Concatenate the result back
12937 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
12943 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
12944 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
12945 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
12946 // looks for this combo and may remove the "setcc" instruction if the "setcc"
12947 // has only one use.
12948 SDNode *N = Op.getNode();
12949 SDValue LHS = N->getOperand(0);
12950 SDValue RHS = N->getOperand(1);
12951 unsigned BaseOp = 0;
12954 switch (Op.getOpcode()) {
12955 default: llvm_unreachable("Unknown ovf instruction!");
12957 // A subtract of one will be selected as a INC. Note that INC doesn't
12958 // set CF, so we can't do this for UADDO.
12959 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
12961 BaseOp = X86ISD::INC;
12962 Cond = X86::COND_O;
12965 BaseOp = X86ISD::ADD;
12966 Cond = X86::COND_O;
12969 BaseOp = X86ISD::ADD;
12970 Cond = X86::COND_B;
12973 // A subtract of one will be selected as a DEC. Note that DEC doesn't
12974 // set CF, so we can't do this for USUBO.
12975 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
12977 BaseOp = X86ISD::DEC;
12978 Cond = X86::COND_O;
12981 BaseOp = X86ISD::SUB;
12982 Cond = X86::COND_O;
12985 BaseOp = X86ISD::SUB;
12986 Cond = X86::COND_B;
12989 BaseOp = X86ISD::SMUL;
12990 Cond = X86::COND_O;
12992 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
12993 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
12995 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
12998 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
12999 DAG.getConstant(X86::COND_O, MVT::i32),
13000 SDValue(Sum.getNode(), 2));
13002 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
13006 // Also sets EFLAGS.
13007 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
13008 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
13011 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
13012 DAG.getConstant(Cond, MVT::i32),
13013 SDValue(Sum.getNode(), 1));
13015 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
13018 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
13019 SelectionDAG &DAG) const {
13021 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
13022 EVT VT = Op.getValueType();
13024 if (!Subtarget->hasSSE2() || !VT.isVector())
13027 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
13028 ExtraVT.getScalarType().getSizeInBits();
13030 switch (VT.getSimpleVT().SimpleTy) {
13031 default: return SDValue();
13034 if (!Subtarget->hasFp256())
13036 if (!Subtarget->hasInt256()) {
13037 // needs to be split
13038 unsigned NumElems = VT.getVectorNumElements();
13040 // Extract the LHS vectors
13041 SDValue LHS = Op.getOperand(0);
13042 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
13043 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
13045 MVT EltVT = VT.getVectorElementType().getSimpleVT();
13046 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
13048 EVT ExtraEltVT = ExtraVT.getVectorElementType();
13049 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
13050 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
13052 SDValue Extra = DAG.getValueType(ExtraVT);
13054 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
13055 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
13057 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
13062 // (sext (vzext x)) -> (vsext x)
13063 SDValue Op0 = Op.getOperand(0);
13064 SDValue Op00 = Op0.getOperand(0);
13066 // Hopefully, this VECTOR_SHUFFLE is just a VZEXT.
13067 if (Op0.getOpcode() == ISD::BITCAST &&
13068 Op00.getOpcode() == ISD::VECTOR_SHUFFLE)
13069 Tmp1 = LowerVectorIntExtend(Op00, Subtarget, DAG);
13070 if (Tmp1.getNode()) {
13071 SDValue Tmp1Op0 = Tmp1.getOperand(0);
13072 assert(Tmp1Op0.getOpcode() == X86ISD::VZEXT &&
13073 "This optimization is invalid without a VZEXT.");
13074 return DAG.getNode(X86ISD::VSEXT, dl, VT, Tmp1Op0.getOperand(0));
13077 // If the above didn't work, then just use Shift-Left + Shift-Right.
13078 Tmp1 = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, Op0, BitsDiff,
13080 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, Tmp1, BitsDiff,
13086 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
13087 SelectionDAG &DAG) {
13089 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
13090 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
13091 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
13092 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
13094 // The only fence that needs an instruction is a sequentially-consistent
13095 // cross-thread fence.
13096 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
13097 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
13098 // no-sse2). There isn't any reason to disable it if the target processor
13100 if (Subtarget->hasSSE2() || Subtarget->is64Bit())
13101 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
13103 SDValue Chain = Op.getOperand(0);
13104 SDValue Zero = DAG.getConstant(0, MVT::i32);
13106 DAG.getRegister(X86::ESP, MVT::i32), // Base
13107 DAG.getTargetConstant(1, MVT::i8), // Scale
13108 DAG.getRegister(0, MVT::i32), // Index
13109 DAG.getTargetConstant(0, MVT::i32), // Disp
13110 DAG.getRegister(0, MVT::i32), // Segment.
13114 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
13115 return SDValue(Res, 0);
13118 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
13119 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
13122 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
13123 SelectionDAG &DAG) {
13124 EVT T = Op.getValueType();
13128 switch(T.getSimpleVT().SimpleTy) {
13129 default: llvm_unreachable("Invalid value type!");
13130 case MVT::i8: Reg = X86::AL; size = 1; break;
13131 case MVT::i16: Reg = X86::AX; size = 2; break;
13132 case MVT::i32: Reg = X86::EAX; size = 4; break;
13134 assert(Subtarget->is64Bit() && "Node not type legal!");
13135 Reg = X86::RAX; size = 8;
13138 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
13139 Op.getOperand(2), SDValue());
13140 SDValue Ops[] = { cpIn.getValue(0),
13143 DAG.getTargetConstant(size, MVT::i8),
13144 cpIn.getValue(1) };
13145 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
13146 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
13147 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
13148 Ops, array_lengthof(Ops), T, MMO);
13150 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
13154 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
13155 SelectionDAG &DAG) {
13156 assert(Subtarget->is64Bit() && "Result not type legalized?");
13157 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
13158 SDValue TheChain = Op.getOperand(0);
13160 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
13161 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
13162 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
13164 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
13165 DAG.getConstant(32, MVT::i8));
13167 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
13170 return DAG.getMergeValues(Ops, array_lengthof(Ops), dl);
13173 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
13174 SelectionDAG &DAG) {
13175 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
13176 MVT DstVT = Op.getSimpleValueType();
13177 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
13178 Subtarget->hasMMX() && "Unexpected custom BITCAST");
13179 assert((DstVT == MVT::i64 ||
13180 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
13181 "Unexpected custom BITCAST");
13182 // i64 <=> MMX conversions are Legal.
13183 if (SrcVT==MVT::i64 && DstVT.isVector())
13185 if (DstVT==MVT::i64 && SrcVT.isVector())
13187 // MMX <=> MMX conversions are Legal.
13188 if (SrcVT.isVector() && DstVT.isVector())
13190 // All other conversions need to be expanded.
13194 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
13195 SDNode *Node = Op.getNode();
13197 EVT T = Node->getValueType(0);
13198 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
13199 DAG.getConstant(0, T), Node->getOperand(2));
13200 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
13201 cast<AtomicSDNode>(Node)->getMemoryVT(),
13202 Node->getOperand(0),
13203 Node->getOperand(1), negOp,
13204 cast<AtomicSDNode>(Node)->getSrcValue(),
13205 cast<AtomicSDNode>(Node)->getAlignment(),
13206 cast<AtomicSDNode>(Node)->getOrdering(),
13207 cast<AtomicSDNode>(Node)->getSynchScope());
13210 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
13211 SDNode *Node = Op.getNode();
13213 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
13215 // Convert seq_cst store -> xchg
13216 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
13217 // FIXME: On 32-bit, store -> fist or movq would be more efficient
13218 // (The only way to get a 16-byte store is cmpxchg16b)
13219 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
13220 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
13221 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
13222 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
13223 cast<AtomicSDNode>(Node)->getMemoryVT(),
13224 Node->getOperand(0),
13225 Node->getOperand(1), Node->getOperand(2),
13226 cast<AtomicSDNode>(Node)->getMemOperand(),
13227 cast<AtomicSDNode>(Node)->getOrdering(),
13228 cast<AtomicSDNode>(Node)->getSynchScope());
13229 return Swap.getValue(1);
13231 // Other atomic stores have a simple pattern.
13235 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
13236 EVT VT = Op.getNode()->getValueType(0);
13238 // Let legalize expand this if it isn't a legal type yet.
13239 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
13242 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
13245 bool ExtraOp = false;
13246 switch (Op.getOpcode()) {
13247 default: llvm_unreachable("Invalid code");
13248 case ISD::ADDC: Opc = X86ISD::ADD; break;
13249 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
13250 case ISD::SUBC: Opc = X86ISD::SUB; break;
13251 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
13255 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
13257 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
13258 Op.getOperand(1), Op.getOperand(2));
13261 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
13262 SelectionDAG &DAG) {
13263 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
13265 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
13266 // which returns the values as { float, float } (in XMM0) or
13267 // { double, double } (which is returned in XMM0, XMM1).
13269 SDValue Arg = Op.getOperand(0);
13270 EVT ArgVT = Arg.getValueType();
13271 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
13273 TargetLowering::ArgListTy Args;
13274 TargetLowering::ArgListEntry Entry;
13278 Entry.isSExt = false;
13279 Entry.isZExt = false;
13280 Args.push_back(Entry);
13282 bool isF64 = ArgVT == MVT::f64;
13283 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
13284 // the small struct {f32, f32} is returned in (eax, edx). For f64,
13285 // the results are returned via SRet in memory.
13286 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
13287 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13288 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
13290 Type *RetTy = isF64
13291 ? (Type*)StructType::get(ArgTy, ArgTy, NULL)
13292 : (Type*)VectorType::get(ArgTy, 4);
13294 CallLoweringInfo CLI(DAG.getEntryNode(), RetTy,
13295 false, false, false, false, 0,
13296 CallingConv::C, /*isTaillCall=*/false,
13297 /*doesNotRet=*/false, /*isReturnValueUsed*/true,
13298 Callee, Args, DAG, dl);
13299 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
13302 // Returned in xmm0 and xmm1.
13303 return CallResult.first;
13305 // Returned in bits 0:31 and 32:64 xmm0.
13306 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
13307 CallResult.first, DAG.getIntPtrConstant(0));
13308 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
13309 CallResult.first, DAG.getIntPtrConstant(1));
13310 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
13311 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
13314 /// LowerOperation - Provide custom lowering hooks for some operations.
13316 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
13317 switch (Op.getOpcode()) {
13318 default: llvm_unreachable("Should not custom lower this!");
13319 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
13320 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
13321 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op, Subtarget, DAG);
13322 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
13323 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
13324 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
13325 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
13326 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
13327 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
13328 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
13329 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
13330 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
13331 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
13332 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
13333 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
13334 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
13335 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
13336 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
13337 case ISD::SHL_PARTS:
13338 case ISD::SRA_PARTS:
13339 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
13340 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
13341 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
13342 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
13343 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
13344 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
13345 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
13346 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
13347 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
13348 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
13349 case ISD::FABS: return LowerFABS(Op, DAG);
13350 case ISD::FNEG: return LowerFNEG(Op, DAG);
13351 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
13352 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
13353 case ISD::SETCC: return LowerSETCC(Op, DAG);
13354 case ISD::SELECT: return LowerSELECT(Op, DAG);
13355 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
13356 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
13357 case ISD::VASTART: return LowerVASTART(Op, DAG);
13358 case ISD::VAARG: return LowerVAARG(Op, DAG);
13359 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
13360 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
13361 case ISD::INTRINSIC_VOID:
13362 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
13363 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
13364 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
13365 case ISD::FRAME_TO_ARGS_OFFSET:
13366 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
13367 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
13368 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
13369 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
13370 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
13371 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
13372 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
13373 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
13374 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
13375 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
13376 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
13377 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
13380 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
13386 case ISD::UMULO: return LowerXALUO(Op, DAG);
13387 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
13388 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
13392 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
13393 case ISD::ADD: return LowerADD(Op, DAG);
13394 case ISD::SUB: return LowerSUB(Op, DAG);
13395 case ISD::SDIV: return LowerSDIV(Op, DAG);
13396 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
13400 static void ReplaceATOMIC_LOAD(SDNode *Node,
13401 SmallVectorImpl<SDValue> &Results,
13402 SelectionDAG &DAG) {
13404 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
13406 // Convert wide load -> cmpxchg8b/cmpxchg16b
13407 // FIXME: On 32-bit, load -> fild or movq would be more efficient
13408 // (The only way to get a 16-byte load is cmpxchg16b)
13409 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment.
13410 SDValue Zero = DAG.getConstant(0, VT);
13411 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT,
13412 Node->getOperand(0),
13413 Node->getOperand(1), Zero, Zero,
13414 cast<AtomicSDNode>(Node)->getMemOperand(),
13415 cast<AtomicSDNode>(Node)->getOrdering(),
13416 cast<AtomicSDNode>(Node)->getSynchScope());
13417 Results.push_back(Swap.getValue(0));
13418 Results.push_back(Swap.getValue(1));
13422 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
13423 SelectionDAG &DAG, unsigned NewOp) {
13425 assert (Node->getValueType(0) == MVT::i64 &&
13426 "Only know how to expand i64 atomics");
13428 SDValue Chain = Node->getOperand(0);
13429 SDValue In1 = Node->getOperand(1);
13430 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
13431 Node->getOperand(2), DAG.getIntPtrConstant(0));
13432 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
13433 Node->getOperand(2), DAG.getIntPtrConstant(1));
13434 SDValue Ops[] = { Chain, In1, In2L, In2H };
13435 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
13437 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, array_lengthof(Ops), MVT::i64,
13438 cast<MemSDNode>(Node)->getMemOperand());
13439 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
13440 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
13441 Results.push_back(Result.getValue(2));
13444 /// ReplaceNodeResults - Replace a node with an illegal result type
13445 /// with a new node built out of custom code.
13446 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
13447 SmallVectorImpl<SDValue>&Results,
13448 SelectionDAG &DAG) const {
13450 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13451 switch (N->getOpcode()) {
13453 llvm_unreachable("Do not know how to custom type legalize this operation!");
13454 case ISD::SIGN_EXTEND_INREG:
13459 // We don't want to expand or promote these.
13461 case ISD::FP_TO_SINT:
13462 case ISD::FP_TO_UINT: {
13463 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
13465 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
13468 std::pair<SDValue,SDValue> Vals =
13469 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
13470 SDValue FIST = Vals.first, StackSlot = Vals.second;
13471 if (FIST.getNode() != 0) {
13472 EVT VT = N->getValueType(0);
13473 // Return a load from the stack slot.
13474 if (StackSlot.getNode() != 0)
13475 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
13476 MachinePointerInfo(),
13477 false, false, false, 0));
13479 Results.push_back(FIST);
13483 case ISD::UINT_TO_FP: {
13484 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
13485 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
13486 N->getValueType(0) != MVT::v2f32)
13488 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
13490 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
13492 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
13493 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
13494 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
13495 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
13496 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
13497 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
13500 case ISD::FP_ROUND: {
13501 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
13503 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
13504 Results.push_back(V);
13507 case ISD::READCYCLECOUNTER: {
13508 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
13509 SDValue TheChain = N->getOperand(0);
13510 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
13511 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
13513 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
13515 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
13516 SDValue Ops[] = { eax, edx };
13517 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops,
13518 array_lengthof(Ops)));
13519 Results.push_back(edx.getValue(1));
13522 case ISD::ATOMIC_CMP_SWAP: {
13523 EVT T = N->getValueType(0);
13524 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
13525 bool Regs64bit = T == MVT::i128;
13526 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
13527 SDValue cpInL, cpInH;
13528 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
13529 DAG.getConstant(0, HalfT));
13530 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
13531 DAG.getConstant(1, HalfT));
13532 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
13533 Regs64bit ? X86::RAX : X86::EAX,
13535 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
13536 Regs64bit ? X86::RDX : X86::EDX,
13537 cpInH, cpInL.getValue(1));
13538 SDValue swapInL, swapInH;
13539 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
13540 DAG.getConstant(0, HalfT));
13541 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
13542 DAG.getConstant(1, HalfT));
13543 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
13544 Regs64bit ? X86::RBX : X86::EBX,
13545 swapInL, cpInH.getValue(1));
13546 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
13547 Regs64bit ? X86::RCX : X86::ECX,
13548 swapInH, swapInL.getValue(1));
13549 SDValue Ops[] = { swapInH.getValue(0),
13551 swapInH.getValue(1) };
13552 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
13553 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
13554 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
13555 X86ISD::LCMPXCHG8_DAG;
13556 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys,
13557 Ops, array_lengthof(Ops), T, MMO);
13558 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
13559 Regs64bit ? X86::RAX : X86::EAX,
13560 HalfT, Result.getValue(1));
13561 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
13562 Regs64bit ? X86::RDX : X86::EDX,
13563 HalfT, cpOutL.getValue(2));
13564 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
13565 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF, 2));
13566 Results.push_back(cpOutH.getValue(1));
13569 case ISD::ATOMIC_LOAD_ADD:
13570 case ISD::ATOMIC_LOAD_AND:
13571 case ISD::ATOMIC_LOAD_NAND:
13572 case ISD::ATOMIC_LOAD_OR:
13573 case ISD::ATOMIC_LOAD_SUB:
13574 case ISD::ATOMIC_LOAD_XOR:
13575 case ISD::ATOMIC_LOAD_MAX:
13576 case ISD::ATOMIC_LOAD_MIN:
13577 case ISD::ATOMIC_LOAD_UMAX:
13578 case ISD::ATOMIC_LOAD_UMIN:
13579 case ISD::ATOMIC_SWAP: {
13581 switch (N->getOpcode()) {
13582 default: llvm_unreachable("Unexpected opcode");
13583 case ISD::ATOMIC_LOAD_ADD:
13584 Opc = X86ISD::ATOMADD64_DAG;
13586 case ISD::ATOMIC_LOAD_AND:
13587 Opc = X86ISD::ATOMAND64_DAG;
13589 case ISD::ATOMIC_LOAD_NAND:
13590 Opc = X86ISD::ATOMNAND64_DAG;
13592 case ISD::ATOMIC_LOAD_OR:
13593 Opc = X86ISD::ATOMOR64_DAG;
13595 case ISD::ATOMIC_LOAD_SUB:
13596 Opc = X86ISD::ATOMSUB64_DAG;
13598 case ISD::ATOMIC_LOAD_XOR:
13599 Opc = X86ISD::ATOMXOR64_DAG;
13601 case ISD::ATOMIC_LOAD_MAX:
13602 Opc = X86ISD::ATOMMAX64_DAG;
13604 case ISD::ATOMIC_LOAD_MIN:
13605 Opc = X86ISD::ATOMMIN64_DAG;
13607 case ISD::ATOMIC_LOAD_UMAX:
13608 Opc = X86ISD::ATOMUMAX64_DAG;
13610 case ISD::ATOMIC_LOAD_UMIN:
13611 Opc = X86ISD::ATOMUMIN64_DAG;
13613 case ISD::ATOMIC_SWAP:
13614 Opc = X86ISD::ATOMSWAP64_DAG;
13617 ReplaceATOMIC_BINARY_64(N, Results, DAG, Opc);
13620 case ISD::ATOMIC_LOAD:
13621 ReplaceATOMIC_LOAD(N, Results, DAG);
13625 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
13627 default: return NULL;
13628 case X86ISD::BSF: return "X86ISD::BSF";
13629 case X86ISD::BSR: return "X86ISD::BSR";
13630 case X86ISD::SHLD: return "X86ISD::SHLD";
13631 case X86ISD::SHRD: return "X86ISD::SHRD";
13632 case X86ISD::FAND: return "X86ISD::FAND";
13633 case X86ISD::FANDN: return "X86ISD::FANDN";
13634 case X86ISD::FOR: return "X86ISD::FOR";
13635 case X86ISD::FXOR: return "X86ISD::FXOR";
13636 case X86ISD::FSRL: return "X86ISD::FSRL";
13637 case X86ISD::FILD: return "X86ISD::FILD";
13638 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
13639 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
13640 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
13641 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
13642 case X86ISD::FLD: return "X86ISD::FLD";
13643 case X86ISD::FST: return "X86ISD::FST";
13644 case X86ISD::CALL: return "X86ISD::CALL";
13645 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
13646 case X86ISD::BT: return "X86ISD::BT";
13647 case X86ISD::CMP: return "X86ISD::CMP";
13648 case X86ISD::COMI: return "X86ISD::COMI";
13649 case X86ISD::UCOMI: return "X86ISD::UCOMI";
13650 case X86ISD::CMPM: return "X86ISD::CMPM";
13651 case X86ISD::CMPMU: return "X86ISD::CMPMU";
13652 case X86ISD::SETCC: return "X86ISD::SETCC";
13653 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
13654 case X86ISD::FSETCCsd: return "X86ISD::FSETCCsd";
13655 case X86ISD::FSETCCss: return "X86ISD::FSETCCss";
13656 case X86ISD::CMOV: return "X86ISD::CMOV";
13657 case X86ISD::BRCOND: return "X86ISD::BRCOND";
13658 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
13659 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
13660 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
13661 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
13662 case X86ISD::Wrapper: return "X86ISD::Wrapper";
13663 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
13664 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
13665 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
13666 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
13667 case X86ISD::PINSRB: return "X86ISD::PINSRB";
13668 case X86ISD::PINSRW: return "X86ISD::PINSRW";
13669 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
13670 case X86ISD::ANDNP: return "X86ISD::ANDNP";
13671 case X86ISD::PSIGN: return "X86ISD::PSIGN";
13672 case X86ISD::BLENDV: return "X86ISD::BLENDV";
13673 case X86ISD::BLENDI: return "X86ISD::BLENDI";
13674 case X86ISD::SUBUS: return "X86ISD::SUBUS";
13675 case X86ISD::HADD: return "X86ISD::HADD";
13676 case X86ISD::HSUB: return "X86ISD::HSUB";
13677 case X86ISD::FHADD: return "X86ISD::FHADD";
13678 case X86ISD::FHSUB: return "X86ISD::FHSUB";
13679 case X86ISD::UMAX: return "X86ISD::UMAX";
13680 case X86ISD::UMIN: return "X86ISD::UMIN";
13681 case X86ISD::SMAX: return "X86ISD::SMAX";
13682 case X86ISD::SMIN: return "X86ISD::SMIN";
13683 case X86ISD::FMAX: return "X86ISD::FMAX";
13684 case X86ISD::FMIN: return "X86ISD::FMIN";
13685 case X86ISD::FMAXC: return "X86ISD::FMAXC";
13686 case X86ISD::FMINC: return "X86ISD::FMINC";
13687 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
13688 case X86ISD::FRCP: return "X86ISD::FRCP";
13689 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
13690 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
13691 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
13692 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
13693 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
13694 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
13695 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
13696 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
13697 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
13698 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
13699 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
13700 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
13701 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
13702 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
13703 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
13704 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
13705 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
13706 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
13707 case X86ISD::VSEXT_MOVL: return "X86ISD::VSEXT_MOVL";
13708 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
13709 case X86ISD::VZEXT: return "X86ISD::VZEXT";
13710 case X86ISD::VSEXT: return "X86ISD::VSEXT";
13711 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
13712 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
13713 case X86ISD::VINSERT: return "X86ISD::VINSERT";
13714 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
13715 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
13716 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
13717 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
13718 case X86ISD::VSHL: return "X86ISD::VSHL";
13719 case X86ISD::VSRL: return "X86ISD::VSRL";
13720 case X86ISD::VSRA: return "X86ISD::VSRA";
13721 case X86ISD::VSHLI: return "X86ISD::VSHLI";
13722 case X86ISD::VSRLI: return "X86ISD::VSRLI";
13723 case X86ISD::VSRAI: return "X86ISD::VSRAI";
13724 case X86ISD::CMPP: return "X86ISD::CMPP";
13725 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
13726 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
13727 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
13728 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
13729 case X86ISD::ADD: return "X86ISD::ADD";
13730 case X86ISD::SUB: return "X86ISD::SUB";
13731 case X86ISD::ADC: return "X86ISD::ADC";
13732 case X86ISD::SBB: return "X86ISD::SBB";
13733 case X86ISD::SMUL: return "X86ISD::SMUL";
13734 case X86ISD::UMUL: return "X86ISD::UMUL";
13735 case X86ISD::INC: return "X86ISD::INC";
13736 case X86ISD::DEC: return "X86ISD::DEC";
13737 case X86ISD::OR: return "X86ISD::OR";
13738 case X86ISD::XOR: return "X86ISD::XOR";
13739 case X86ISD::AND: return "X86ISD::AND";
13740 case X86ISD::BLSI: return "X86ISD::BLSI";
13741 case X86ISD::BLSMSK: return "X86ISD::BLSMSK";
13742 case X86ISD::BLSR: return "X86ISD::BLSR";
13743 case X86ISD::BZHI: return "X86ISD::BZHI";
13744 case X86ISD::BEXTR: return "X86ISD::BEXTR";
13745 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
13746 case X86ISD::PTEST: return "X86ISD::PTEST";
13747 case X86ISD::TESTP: return "X86ISD::TESTP";
13748 case X86ISD::TESTM: return "X86ISD::TESTM";
13749 case X86ISD::KORTEST: return "X86ISD::KORTEST";
13750 case X86ISD::KTEST: return "X86ISD::KTEST";
13751 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
13752 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
13753 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
13754 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
13755 case X86ISD::SHUFP: return "X86ISD::SHUFP";
13756 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
13757 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
13758 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
13759 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
13760 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
13761 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
13762 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
13763 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
13764 case X86ISD::MOVSD: return "X86ISD::MOVSD";
13765 case X86ISD::MOVSS: return "X86ISD::MOVSS";
13766 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
13767 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
13768 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
13769 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
13770 case X86ISD::VPERMILP: return "X86ISD::VPERMILP";
13771 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
13772 case X86ISD::VPERMV: return "X86ISD::VPERMV";
13773 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
13774 case X86ISD::VPERMI: return "X86ISD::VPERMI";
13775 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
13776 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
13777 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
13778 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
13779 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
13780 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
13781 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
13782 case X86ISD::SAHF: return "X86ISD::SAHF";
13783 case X86ISD::RDRAND: return "X86ISD::RDRAND";
13784 case X86ISD::RDSEED: return "X86ISD::RDSEED";
13785 case X86ISD::FMADD: return "X86ISD::FMADD";
13786 case X86ISD::FMSUB: return "X86ISD::FMSUB";
13787 case X86ISD::FNMADD: return "X86ISD::FNMADD";
13788 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
13789 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
13790 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
13791 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
13792 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
13793 case X86ISD::XTEST: return "X86ISD::XTEST";
13797 // isLegalAddressingMode - Return true if the addressing mode represented
13798 // by AM is legal for this target, for a load/store of the specified type.
13799 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
13801 // X86 supports extremely general addressing modes.
13802 CodeModel::Model M = getTargetMachine().getCodeModel();
13803 Reloc::Model R = getTargetMachine().getRelocationModel();
13805 // X86 allows a sign-extended 32-bit immediate field as a displacement.
13806 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
13811 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
13813 // If a reference to this global requires an extra load, we can't fold it.
13814 if (isGlobalStubReference(GVFlags))
13817 // If BaseGV requires a register for the PIC base, we cannot also have a
13818 // BaseReg specified.
13819 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
13822 // If lower 4G is not available, then we must use rip-relative addressing.
13823 if ((M != CodeModel::Small || R != Reloc::Static) &&
13824 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
13828 switch (AM.Scale) {
13834 // These scales always work.
13839 // These scales are formed with basereg+scalereg. Only accept if there is
13844 default: // Other stuff never works.
13851 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
13852 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
13854 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
13855 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
13856 return NumBits1 > NumBits2;
13859 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
13860 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
13863 if (!isTypeLegal(EVT::getEVT(Ty1)))
13866 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
13868 // Assuming the caller doesn't have a zeroext or signext return parameter,
13869 // truncation all the way down to i1 is valid.
13873 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
13874 return isInt<32>(Imm);
13877 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
13878 // Can also use sub to handle negated immediates.
13879 return isInt<32>(Imm);
13882 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
13883 if (!VT1.isInteger() || !VT2.isInteger())
13885 unsigned NumBits1 = VT1.getSizeInBits();
13886 unsigned NumBits2 = VT2.getSizeInBits();
13887 return NumBits1 > NumBits2;
13890 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
13891 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
13892 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
13895 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
13896 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
13897 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
13900 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
13901 EVT VT1 = Val.getValueType();
13902 if (isZExtFree(VT1, VT2))
13905 if (Val.getOpcode() != ISD::LOAD)
13908 if (!VT1.isSimple() || !VT1.isInteger() ||
13909 !VT2.isSimple() || !VT2.isInteger())
13912 switch (VT1.getSimpleVT().SimpleTy) {
13917 // X86 has 8, 16, and 32-bit zero-extending loads.
13925 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
13926 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
13929 VT = VT.getScalarType();
13931 if (!VT.isSimple())
13934 switch (VT.getSimpleVT().SimpleTy) {
13945 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
13946 // i16 instructions are longer (0x66 prefix) and potentially slower.
13947 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
13950 /// isShuffleMaskLegal - Targets can use this to indicate that they only
13951 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
13952 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
13953 /// are assumed to be legal.
13955 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
13957 if (!VT.isSimple())
13960 MVT SVT = VT.getSimpleVT();
13962 // Very little shuffling can be done for 64-bit vectors right now.
13963 if (VT.getSizeInBits() == 64)
13966 // FIXME: pshufb, blends, shifts.
13967 return (SVT.getVectorNumElements() == 2 ||
13968 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
13969 isMOVLMask(M, SVT) ||
13970 isSHUFPMask(M, SVT) ||
13971 isPSHUFDMask(M, SVT) ||
13972 isPSHUFHWMask(M, SVT, Subtarget->hasInt256()) ||
13973 isPSHUFLWMask(M, SVT, Subtarget->hasInt256()) ||
13974 isPALIGNRMask(M, SVT, Subtarget) ||
13975 isUNPCKLMask(M, SVT, Subtarget->hasInt256()) ||
13976 isUNPCKHMask(M, SVT, Subtarget->hasInt256()) ||
13977 isUNPCKL_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
13978 isUNPCKH_v_undef_Mask(M, SVT, Subtarget->hasInt256()));
13982 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
13984 if (!VT.isSimple())
13987 MVT SVT = VT.getSimpleVT();
13988 unsigned NumElts = SVT.getVectorNumElements();
13989 // FIXME: This collection of masks seems suspect.
13992 if (NumElts == 4 && SVT.is128BitVector()) {
13993 return (isMOVLMask(Mask, SVT) ||
13994 isCommutedMOVLMask(Mask, SVT, true) ||
13995 isSHUFPMask(Mask, SVT) ||
13996 isSHUFPMask(Mask, SVT, /* Commuted */ true));
14001 //===----------------------------------------------------------------------===//
14002 // X86 Scheduler Hooks
14003 //===----------------------------------------------------------------------===//
14005 /// Utility function to emit xbegin specifying the start of an RTM region.
14006 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
14007 const TargetInstrInfo *TII) {
14008 DebugLoc DL = MI->getDebugLoc();
14010 const BasicBlock *BB = MBB->getBasicBlock();
14011 MachineFunction::iterator I = MBB;
14014 // For the v = xbegin(), we generate
14025 MachineBasicBlock *thisMBB = MBB;
14026 MachineFunction *MF = MBB->getParent();
14027 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
14028 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
14029 MF->insert(I, mainMBB);
14030 MF->insert(I, sinkMBB);
14032 // Transfer the remainder of BB and its successor edges to sinkMBB.
14033 sinkMBB->splice(sinkMBB->begin(), MBB,
14034 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
14035 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
14039 // # fallthrough to mainMBB
14040 // # abortion to sinkMBB
14041 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
14042 thisMBB->addSuccessor(mainMBB);
14043 thisMBB->addSuccessor(sinkMBB);
14047 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
14048 mainMBB->addSuccessor(sinkMBB);
14051 // EAX is live into the sinkMBB
14052 sinkMBB->addLiveIn(X86::EAX);
14053 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
14054 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
14057 MI->eraseFromParent();
14061 // Get CMPXCHG opcode for the specified data type.
14062 static unsigned getCmpXChgOpcode(EVT VT) {
14063 switch (VT.getSimpleVT().SimpleTy) {
14064 case MVT::i8: return X86::LCMPXCHG8;
14065 case MVT::i16: return X86::LCMPXCHG16;
14066 case MVT::i32: return X86::LCMPXCHG32;
14067 case MVT::i64: return X86::LCMPXCHG64;
14071 llvm_unreachable("Invalid operand size!");
14074 // Get LOAD opcode for the specified data type.
14075 static unsigned getLoadOpcode(EVT VT) {
14076 switch (VT.getSimpleVT().SimpleTy) {
14077 case MVT::i8: return X86::MOV8rm;
14078 case MVT::i16: return X86::MOV16rm;
14079 case MVT::i32: return X86::MOV32rm;
14080 case MVT::i64: return X86::MOV64rm;
14084 llvm_unreachable("Invalid operand size!");
14087 // Get opcode of the non-atomic one from the specified atomic instruction.
14088 static unsigned getNonAtomicOpcode(unsigned Opc) {
14090 case X86::ATOMAND8: return X86::AND8rr;
14091 case X86::ATOMAND16: return X86::AND16rr;
14092 case X86::ATOMAND32: return X86::AND32rr;
14093 case X86::ATOMAND64: return X86::AND64rr;
14094 case X86::ATOMOR8: return X86::OR8rr;
14095 case X86::ATOMOR16: return X86::OR16rr;
14096 case X86::ATOMOR32: return X86::OR32rr;
14097 case X86::ATOMOR64: return X86::OR64rr;
14098 case X86::ATOMXOR8: return X86::XOR8rr;
14099 case X86::ATOMXOR16: return X86::XOR16rr;
14100 case X86::ATOMXOR32: return X86::XOR32rr;
14101 case X86::ATOMXOR64: return X86::XOR64rr;
14103 llvm_unreachable("Unhandled atomic-load-op opcode!");
14106 // Get opcode of the non-atomic one from the specified atomic instruction with
14108 static unsigned getNonAtomicOpcodeWithExtraOpc(unsigned Opc,
14109 unsigned &ExtraOpc) {
14111 case X86::ATOMNAND8: ExtraOpc = X86::NOT8r; return X86::AND8rr;
14112 case X86::ATOMNAND16: ExtraOpc = X86::NOT16r; return X86::AND16rr;
14113 case X86::ATOMNAND32: ExtraOpc = X86::NOT32r; return X86::AND32rr;
14114 case X86::ATOMNAND64: ExtraOpc = X86::NOT64r; return X86::AND64rr;
14115 case X86::ATOMMAX8: ExtraOpc = X86::CMP8rr; return X86::CMOVL32rr;
14116 case X86::ATOMMAX16: ExtraOpc = X86::CMP16rr; return X86::CMOVL16rr;
14117 case X86::ATOMMAX32: ExtraOpc = X86::CMP32rr; return X86::CMOVL32rr;
14118 case X86::ATOMMAX64: ExtraOpc = X86::CMP64rr; return X86::CMOVL64rr;
14119 case X86::ATOMMIN8: ExtraOpc = X86::CMP8rr; return X86::CMOVG32rr;
14120 case X86::ATOMMIN16: ExtraOpc = X86::CMP16rr; return X86::CMOVG16rr;
14121 case X86::ATOMMIN32: ExtraOpc = X86::CMP32rr; return X86::CMOVG32rr;
14122 case X86::ATOMMIN64: ExtraOpc = X86::CMP64rr; return X86::CMOVG64rr;
14123 case X86::ATOMUMAX8: ExtraOpc = X86::CMP8rr; return X86::CMOVB32rr;
14124 case X86::ATOMUMAX16: ExtraOpc = X86::CMP16rr; return X86::CMOVB16rr;
14125 case X86::ATOMUMAX32: ExtraOpc = X86::CMP32rr; return X86::CMOVB32rr;
14126 case X86::ATOMUMAX64: ExtraOpc = X86::CMP64rr; return X86::CMOVB64rr;
14127 case X86::ATOMUMIN8: ExtraOpc = X86::CMP8rr; return X86::CMOVA32rr;
14128 case X86::ATOMUMIN16: ExtraOpc = X86::CMP16rr; return X86::CMOVA16rr;
14129 case X86::ATOMUMIN32: ExtraOpc = X86::CMP32rr; return X86::CMOVA32rr;
14130 case X86::ATOMUMIN64: ExtraOpc = X86::CMP64rr; return X86::CMOVA64rr;
14132 llvm_unreachable("Unhandled atomic-load-op opcode!");
14135 // Get opcode of the non-atomic one from the specified atomic instruction for
14136 // 64-bit data type on 32-bit target.
14137 static unsigned getNonAtomic6432Opcode(unsigned Opc, unsigned &HiOpc) {
14139 case X86::ATOMAND6432: HiOpc = X86::AND32rr; return X86::AND32rr;
14140 case X86::ATOMOR6432: HiOpc = X86::OR32rr; return X86::OR32rr;
14141 case X86::ATOMXOR6432: HiOpc = X86::XOR32rr; return X86::XOR32rr;
14142 case X86::ATOMADD6432: HiOpc = X86::ADC32rr; return X86::ADD32rr;
14143 case X86::ATOMSUB6432: HiOpc = X86::SBB32rr; return X86::SUB32rr;
14144 case X86::ATOMSWAP6432: HiOpc = X86::MOV32rr; return X86::MOV32rr;
14145 case X86::ATOMMAX6432: HiOpc = X86::SETLr; return X86::SETLr;
14146 case X86::ATOMMIN6432: HiOpc = X86::SETGr; return X86::SETGr;
14147 case X86::ATOMUMAX6432: HiOpc = X86::SETBr; return X86::SETBr;
14148 case X86::ATOMUMIN6432: HiOpc = X86::SETAr; return X86::SETAr;
14150 llvm_unreachable("Unhandled atomic-load-op opcode!");
14153 // Get opcode of the non-atomic one from the specified atomic instruction for
14154 // 64-bit data type on 32-bit target with extra opcode.
14155 static unsigned getNonAtomic6432OpcodeWithExtraOpc(unsigned Opc,
14157 unsigned &ExtraOpc) {
14159 case X86::ATOMNAND6432:
14160 ExtraOpc = X86::NOT32r;
14161 HiOpc = X86::AND32rr;
14162 return X86::AND32rr;
14164 llvm_unreachable("Unhandled atomic-load-op opcode!");
14167 // Get pseudo CMOV opcode from the specified data type.
14168 static unsigned getPseudoCMOVOpc(EVT VT) {
14169 switch (VT.getSimpleVT().SimpleTy) {
14170 case MVT::i8: return X86::CMOV_GR8;
14171 case MVT::i16: return X86::CMOV_GR16;
14172 case MVT::i32: return X86::CMOV_GR32;
14176 llvm_unreachable("Unknown CMOV opcode!");
14179 // EmitAtomicLoadArith - emit the code sequence for pseudo atomic instructions.
14180 // They will be translated into a spin-loop or compare-exchange loop from
14183 // dst = atomic-fetch-op MI.addr, MI.val
14189 // t1 = LOAD MI.addr
14191 // t4 = phi(t1, t3 / loop)
14192 // t2 = OP MI.val, t4
14194 // LCMPXCHG [MI.addr], t2, [EAX is implicitly used & defined]
14200 MachineBasicBlock *
14201 X86TargetLowering::EmitAtomicLoadArith(MachineInstr *MI,
14202 MachineBasicBlock *MBB) const {
14203 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
14204 DebugLoc DL = MI->getDebugLoc();
14206 MachineFunction *MF = MBB->getParent();
14207 MachineRegisterInfo &MRI = MF->getRegInfo();
14209 const BasicBlock *BB = MBB->getBasicBlock();
14210 MachineFunction::iterator I = MBB;
14213 assert(MI->getNumOperands() <= X86::AddrNumOperands + 4 &&
14214 "Unexpected number of operands");
14216 assert(MI->hasOneMemOperand() &&
14217 "Expected atomic-load-op to have one memoperand");
14219 // Memory Reference
14220 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
14221 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
14223 unsigned DstReg, SrcReg;
14224 unsigned MemOpndSlot;
14226 unsigned CurOp = 0;
14228 DstReg = MI->getOperand(CurOp++).getReg();
14229 MemOpndSlot = CurOp;
14230 CurOp += X86::AddrNumOperands;
14231 SrcReg = MI->getOperand(CurOp++).getReg();
14233 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
14234 MVT::SimpleValueType VT = *RC->vt_begin();
14235 unsigned t1 = MRI.createVirtualRegister(RC);
14236 unsigned t2 = MRI.createVirtualRegister(RC);
14237 unsigned t3 = MRI.createVirtualRegister(RC);
14238 unsigned t4 = MRI.createVirtualRegister(RC);
14239 unsigned PhyReg = getX86SubSuperRegister(X86::EAX, VT);
14241 unsigned LCMPXCHGOpc = getCmpXChgOpcode(VT);
14242 unsigned LOADOpc = getLoadOpcode(VT);
14244 // For the atomic load-arith operator, we generate
14247 // t1 = LOAD [MI.addr]
14249 // t4 = phi(t1 / thisMBB, t3 / mainMBB)
14250 // t1 = OP MI.val, EAX
14252 // LCMPXCHG [MI.addr], t1, [EAX is implicitly used & defined]
14258 MachineBasicBlock *thisMBB = MBB;
14259 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
14260 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
14261 MF->insert(I, mainMBB);
14262 MF->insert(I, sinkMBB);
14264 MachineInstrBuilder MIB;
14266 // Transfer the remainder of BB and its successor edges to sinkMBB.
14267 sinkMBB->splice(sinkMBB->begin(), MBB,
14268 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
14269 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
14272 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), t1);
14273 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14274 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
14276 NewMO.setIsKill(false);
14277 MIB.addOperand(NewMO);
14279 for (MachineInstr::mmo_iterator MMOI = MMOBegin; MMOI != MMOEnd; ++MMOI) {
14280 unsigned flags = (*MMOI)->getFlags();
14281 flags = (flags & ~MachineMemOperand::MOStore) | MachineMemOperand::MOLoad;
14282 MachineMemOperand *MMO =
14283 MF->getMachineMemOperand((*MMOI)->getPointerInfo(), flags,
14284 (*MMOI)->getSize(),
14285 (*MMOI)->getBaseAlignment(),
14286 (*MMOI)->getTBAAInfo(),
14287 (*MMOI)->getRanges());
14288 MIB.addMemOperand(MMO);
14291 thisMBB->addSuccessor(mainMBB);
14294 MachineBasicBlock *origMainMBB = mainMBB;
14297 MachineInstr *Phi = BuildMI(mainMBB, DL, TII->get(X86::PHI), t4)
14298 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(mainMBB);
14300 unsigned Opc = MI->getOpcode();
14303 llvm_unreachable("Unhandled atomic-load-op opcode!");
14304 case X86::ATOMAND8:
14305 case X86::ATOMAND16:
14306 case X86::ATOMAND32:
14307 case X86::ATOMAND64:
14309 case X86::ATOMOR16:
14310 case X86::ATOMOR32:
14311 case X86::ATOMOR64:
14312 case X86::ATOMXOR8:
14313 case X86::ATOMXOR16:
14314 case X86::ATOMXOR32:
14315 case X86::ATOMXOR64: {
14316 unsigned ARITHOpc = getNonAtomicOpcode(Opc);
14317 BuildMI(mainMBB, DL, TII->get(ARITHOpc), t2).addReg(SrcReg)
14321 case X86::ATOMNAND8:
14322 case X86::ATOMNAND16:
14323 case X86::ATOMNAND32:
14324 case X86::ATOMNAND64: {
14325 unsigned Tmp = MRI.createVirtualRegister(RC);
14327 unsigned ANDOpc = getNonAtomicOpcodeWithExtraOpc(Opc, NOTOpc);
14328 BuildMI(mainMBB, DL, TII->get(ANDOpc), Tmp).addReg(SrcReg)
14330 BuildMI(mainMBB, DL, TII->get(NOTOpc), t2).addReg(Tmp);
14333 case X86::ATOMMAX8:
14334 case X86::ATOMMAX16:
14335 case X86::ATOMMAX32:
14336 case X86::ATOMMAX64:
14337 case X86::ATOMMIN8:
14338 case X86::ATOMMIN16:
14339 case X86::ATOMMIN32:
14340 case X86::ATOMMIN64:
14341 case X86::ATOMUMAX8:
14342 case X86::ATOMUMAX16:
14343 case X86::ATOMUMAX32:
14344 case X86::ATOMUMAX64:
14345 case X86::ATOMUMIN8:
14346 case X86::ATOMUMIN16:
14347 case X86::ATOMUMIN32:
14348 case X86::ATOMUMIN64: {
14350 unsigned CMOVOpc = getNonAtomicOpcodeWithExtraOpc(Opc, CMPOpc);
14352 BuildMI(mainMBB, DL, TII->get(CMPOpc))
14356 if (Subtarget->hasCMov()) {
14357 if (VT != MVT::i8) {
14359 BuildMI(mainMBB, DL, TII->get(CMOVOpc), t2)
14363 // Promote i8 to i32 to use CMOV32
14364 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
14365 const TargetRegisterClass *RC32 =
14366 TRI->getSubClassWithSubReg(getRegClassFor(MVT::i32), X86::sub_8bit);
14367 unsigned SrcReg32 = MRI.createVirtualRegister(RC32);
14368 unsigned AccReg32 = MRI.createVirtualRegister(RC32);
14369 unsigned Tmp = MRI.createVirtualRegister(RC32);
14371 unsigned Undef = MRI.createVirtualRegister(RC32);
14372 BuildMI(mainMBB, DL, TII->get(TargetOpcode::IMPLICIT_DEF), Undef);
14374 BuildMI(mainMBB, DL, TII->get(TargetOpcode::INSERT_SUBREG), SrcReg32)
14377 .addImm(X86::sub_8bit);
14378 BuildMI(mainMBB, DL, TII->get(TargetOpcode::INSERT_SUBREG), AccReg32)
14381 .addImm(X86::sub_8bit);
14383 BuildMI(mainMBB, DL, TII->get(CMOVOpc), Tmp)
14387 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t2)
14388 .addReg(Tmp, 0, X86::sub_8bit);
14391 // Use pseudo select and lower them.
14392 assert((VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32) &&
14393 "Invalid atomic-load-op transformation!");
14394 unsigned SelOpc = getPseudoCMOVOpc(VT);
14395 X86::CondCode CC = X86::getCondFromCMovOpc(CMOVOpc);
14396 assert(CC != X86::COND_INVALID && "Invalid atomic-load-op transformation!");
14397 MIB = BuildMI(mainMBB, DL, TII->get(SelOpc), t2)
14398 .addReg(SrcReg).addReg(t4)
14400 mainMBB = EmitLoweredSelect(MIB, mainMBB);
14401 // Replace the original PHI node as mainMBB is changed after CMOV
14403 BuildMI(*origMainMBB, Phi, DL, TII->get(X86::PHI), t4)
14404 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(mainMBB);
14405 Phi->eraseFromParent();
14411 // Copy PhyReg back from virtual register.
14412 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), PhyReg)
14415 MIB = BuildMI(mainMBB, DL, TII->get(LCMPXCHGOpc));
14416 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14417 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
14419 NewMO.setIsKill(false);
14420 MIB.addOperand(NewMO);
14423 MIB.setMemRefs(MMOBegin, MMOEnd);
14425 // Copy PhyReg back to virtual register.
14426 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t3)
14429 BuildMI(mainMBB, DL, TII->get(X86::JNE_4)).addMBB(origMainMBB);
14431 mainMBB->addSuccessor(origMainMBB);
14432 mainMBB->addSuccessor(sinkMBB);
14435 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
14436 TII->get(TargetOpcode::COPY), DstReg)
14439 MI->eraseFromParent();
14443 // EmitAtomicLoadArith6432 - emit the code sequence for pseudo atomic
14444 // instructions. They will be translated into a spin-loop or compare-exchange
14448 // dst = atomic-fetch-op MI.addr, MI.val
14454 // t1L = LOAD [MI.addr + 0]
14455 // t1H = LOAD [MI.addr + 4]
14457 // t4L = phi(t1L, t3L / loop)
14458 // t4H = phi(t1H, t3H / loop)
14459 // t2L = OP MI.val.lo, t4L
14460 // t2H = OP MI.val.hi, t4H
14465 // LCMPXCHG8B [MI.addr], [ECX:EBX & EDX:EAX are implicitly used and EDX:EAX is implicitly defined]
14473 MachineBasicBlock *
14474 X86TargetLowering::EmitAtomicLoadArith6432(MachineInstr *MI,
14475 MachineBasicBlock *MBB) const {
14476 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
14477 DebugLoc DL = MI->getDebugLoc();
14479 MachineFunction *MF = MBB->getParent();
14480 MachineRegisterInfo &MRI = MF->getRegInfo();
14482 const BasicBlock *BB = MBB->getBasicBlock();
14483 MachineFunction::iterator I = MBB;
14486 assert(MI->getNumOperands() <= X86::AddrNumOperands + 7 &&
14487 "Unexpected number of operands");
14489 assert(MI->hasOneMemOperand() &&
14490 "Expected atomic-load-op32 to have one memoperand");
14492 // Memory Reference
14493 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
14494 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
14496 unsigned DstLoReg, DstHiReg;
14497 unsigned SrcLoReg, SrcHiReg;
14498 unsigned MemOpndSlot;
14500 unsigned CurOp = 0;
14502 DstLoReg = MI->getOperand(CurOp++).getReg();
14503 DstHiReg = MI->getOperand(CurOp++).getReg();
14504 MemOpndSlot = CurOp;
14505 CurOp += X86::AddrNumOperands;
14506 SrcLoReg = MI->getOperand(CurOp++).getReg();
14507 SrcHiReg = MI->getOperand(CurOp++).getReg();
14509 const TargetRegisterClass *RC = &X86::GR32RegClass;
14510 const TargetRegisterClass *RC8 = &X86::GR8RegClass;
14512 unsigned t1L = MRI.createVirtualRegister(RC);
14513 unsigned t1H = MRI.createVirtualRegister(RC);
14514 unsigned t2L = MRI.createVirtualRegister(RC);
14515 unsigned t2H = MRI.createVirtualRegister(RC);
14516 unsigned t3L = MRI.createVirtualRegister(RC);
14517 unsigned t3H = MRI.createVirtualRegister(RC);
14518 unsigned t4L = MRI.createVirtualRegister(RC);
14519 unsigned t4H = MRI.createVirtualRegister(RC);
14521 unsigned LCMPXCHGOpc = X86::LCMPXCHG8B;
14522 unsigned LOADOpc = X86::MOV32rm;
14524 // For the atomic load-arith operator, we generate
14527 // t1L = LOAD [MI.addr + 0]
14528 // t1H = LOAD [MI.addr + 4]
14530 // t4L = phi(t1L / thisMBB, t3L / mainMBB)
14531 // t4H = phi(t1H / thisMBB, t3H / mainMBB)
14532 // t2L = OP MI.val.lo, t4L
14533 // t2H = OP MI.val.hi, t4H
14536 // LCMPXCHG8B [MI.addr], [ECX:EBX & EDX:EAX are implicitly used and EDX:EAX is implicitly defined]
14544 MachineBasicBlock *thisMBB = MBB;
14545 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
14546 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
14547 MF->insert(I, mainMBB);
14548 MF->insert(I, sinkMBB);
14550 MachineInstrBuilder MIB;
14552 // Transfer the remainder of BB and its successor edges to sinkMBB.
14553 sinkMBB->splice(sinkMBB->begin(), MBB,
14554 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
14555 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
14559 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), t1L);
14560 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14561 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
14563 NewMO.setIsKill(false);
14564 MIB.addOperand(NewMO);
14566 for (MachineInstr::mmo_iterator MMOI = MMOBegin; MMOI != MMOEnd; ++MMOI) {
14567 unsigned flags = (*MMOI)->getFlags();
14568 flags = (flags & ~MachineMemOperand::MOStore) | MachineMemOperand::MOLoad;
14569 MachineMemOperand *MMO =
14570 MF->getMachineMemOperand((*MMOI)->getPointerInfo(), flags,
14571 (*MMOI)->getSize(),
14572 (*MMOI)->getBaseAlignment(),
14573 (*MMOI)->getTBAAInfo(),
14574 (*MMOI)->getRanges());
14575 MIB.addMemOperand(MMO);
14577 MachineInstr *LowMI = MIB;
14580 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), t1H);
14581 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14582 if (i == X86::AddrDisp) {
14583 MIB.addDisp(MI->getOperand(MemOpndSlot + i), 4); // 4 == sizeof(i32)
14585 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
14587 NewMO.setIsKill(false);
14588 MIB.addOperand(NewMO);
14591 MIB.setMemRefs(LowMI->memoperands_begin(), LowMI->memoperands_end());
14593 thisMBB->addSuccessor(mainMBB);
14596 MachineBasicBlock *origMainMBB = mainMBB;
14599 MachineInstr *PhiL = BuildMI(mainMBB, DL, TII->get(X86::PHI), t4L)
14600 .addReg(t1L).addMBB(thisMBB).addReg(t3L).addMBB(mainMBB);
14601 MachineInstr *PhiH = BuildMI(mainMBB, DL, TII->get(X86::PHI), t4H)
14602 .addReg(t1H).addMBB(thisMBB).addReg(t3H).addMBB(mainMBB);
14604 unsigned Opc = MI->getOpcode();
14607 llvm_unreachable("Unhandled atomic-load-op6432 opcode!");
14608 case X86::ATOMAND6432:
14609 case X86::ATOMOR6432:
14610 case X86::ATOMXOR6432:
14611 case X86::ATOMADD6432:
14612 case X86::ATOMSUB6432: {
14614 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc);
14615 BuildMI(mainMBB, DL, TII->get(LoOpc), t2L).addReg(t4L)
14617 BuildMI(mainMBB, DL, TII->get(HiOpc), t2H).addReg(t4H)
14621 case X86::ATOMNAND6432: {
14622 unsigned HiOpc, NOTOpc;
14623 unsigned LoOpc = getNonAtomic6432OpcodeWithExtraOpc(Opc, HiOpc, NOTOpc);
14624 unsigned TmpL = MRI.createVirtualRegister(RC);
14625 unsigned TmpH = MRI.createVirtualRegister(RC);
14626 BuildMI(mainMBB, DL, TII->get(LoOpc), TmpL).addReg(SrcLoReg)
14628 BuildMI(mainMBB, DL, TII->get(HiOpc), TmpH).addReg(SrcHiReg)
14630 BuildMI(mainMBB, DL, TII->get(NOTOpc), t2L).addReg(TmpL);
14631 BuildMI(mainMBB, DL, TII->get(NOTOpc), t2H).addReg(TmpH);
14634 case X86::ATOMMAX6432:
14635 case X86::ATOMMIN6432:
14636 case X86::ATOMUMAX6432:
14637 case X86::ATOMUMIN6432: {
14639 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc);
14640 unsigned cL = MRI.createVirtualRegister(RC8);
14641 unsigned cH = MRI.createVirtualRegister(RC8);
14642 unsigned cL32 = MRI.createVirtualRegister(RC);
14643 unsigned cH32 = MRI.createVirtualRegister(RC);
14644 unsigned cc = MRI.createVirtualRegister(RC);
14645 // cl := cmp src_lo, lo
14646 BuildMI(mainMBB, DL, TII->get(X86::CMP32rr))
14647 .addReg(SrcLoReg).addReg(t4L);
14648 BuildMI(mainMBB, DL, TII->get(LoOpc), cL);
14649 BuildMI(mainMBB, DL, TII->get(X86::MOVZX32rr8), cL32).addReg(cL);
14650 // ch := cmp src_hi, hi
14651 BuildMI(mainMBB, DL, TII->get(X86::CMP32rr))
14652 .addReg(SrcHiReg).addReg(t4H);
14653 BuildMI(mainMBB, DL, TII->get(HiOpc), cH);
14654 BuildMI(mainMBB, DL, TII->get(X86::MOVZX32rr8), cH32).addReg(cH);
14655 // cc := if (src_hi == hi) ? cl : ch;
14656 if (Subtarget->hasCMov()) {
14657 BuildMI(mainMBB, DL, TII->get(X86::CMOVE32rr), cc)
14658 .addReg(cH32).addReg(cL32);
14660 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), cc)
14661 .addReg(cH32).addReg(cL32)
14662 .addImm(X86::COND_E);
14663 mainMBB = EmitLoweredSelect(MIB, mainMBB);
14665 BuildMI(mainMBB, DL, TII->get(X86::TEST32rr)).addReg(cc).addReg(cc);
14666 if (Subtarget->hasCMov()) {
14667 BuildMI(mainMBB, DL, TII->get(X86::CMOVNE32rr), t2L)
14668 .addReg(SrcLoReg).addReg(t4L);
14669 BuildMI(mainMBB, DL, TII->get(X86::CMOVNE32rr), t2H)
14670 .addReg(SrcHiReg).addReg(t4H);
14672 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), t2L)
14673 .addReg(SrcLoReg).addReg(t4L)
14674 .addImm(X86::COND_NE);
14675 mainMBB = EmitLoweredSelect(MIB, mainMBB);
14676 // As the lowered CMOV won't clobber EFLAGS, we could reuse it for the
14677 // 2nd CMOV lowering.
14678 mainMBB->addLiveIn(X86::EFLAGS);
14679 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), t2H)
14680 .addReg(SrcHiReg).addReg(t4H)
14681 .addImm(X86::COND_NE);
14682 mainMBB = EmitLoweredSelect(MIB, mainMBB);
14683 // Replace the original PHI node as mainMBB is changed after CMOV
14685 BuildMI(*origMainMBB, PhiL, DL, TII->get(X86::PHI), t4L)
14686 .addReg(t1L).addMBB(thisMBB).addReg(t3L).addMBB(mainMBB);
14687 BuildMI(*origMainMBB, PhiH, DL, TII->get(X86::PHI), t4H)
14688 .addReg(t1H).addMBB(thisMBB).addReg(t3H).addMBB(mainMBB);
14689 PhiL->eraseFromParent();
14690 PhiH->eraseFromParent();
14694 case X86::ATOMSWAP6432: {
14696 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc);
14697 BuildMI(mainMBB, DL, TII->get(LoOpc), t2L).addReg(SrcLoReg);
14698 BuildMI(mainMBB, DL, TII->get(HiOpc), t2H).addReg(SrcHiReg);
14703 // Copy EDX:EAX back from HiReg:LoReg
14704 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EAX).addReg(t4L);
14705 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EDX).addReg(t4H);
14706 // Copy ECX:EBX from t1H:t1L
14707 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EBX).addReg(t2L);
14708 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::ECX).addReg(t2H);
14710 MIB = BuildMI(mainMBB, DL, TII->get(LCMPXCHGOpc));
14711 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14712 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
14714 NewMO.setIsKill(false);
14715 MIB.addOperand(NewMO);
14717 MIB.setMemRefs(MMOBegin, MMOEnd);
14719 // Copy EDX:EAX back to t3H:t3L
14720 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t3L).addReg(X86::EAX);
14721 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t3H).addReg(X86::EDX);
14723 BuildMI(mainMBB, DL, TII->get(X86::JNE_4)).addMBB(origMainMBB);
14725 mainMBB->addSuccessor(origMainMBB);
14726 mainMBB->addSuccessor(sinkMBB);
14729 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
14730 TII->get(TargetOpcode::COPY), DstLoReg)
14732 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
14733 TII->get(TargetOpcode::COPY), DstHiReg)
14736 MI->eraseFromParent();
14740 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
14741 // or XMM0_V32I8 in AVX all of this code can be replaced with that
14742 // in the .td file.
14743 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
14744 const TargetInstrInfo *TII) {
14746 switch (MI->getOpcode()) {
14747 default: llvm_unreachable("illegal opcode!");
14748 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
14749 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
14750 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
14751 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
14752 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
14753 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
14754 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
14755 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
14758 DebugLoc dl = MI->getDebugLoc();
14759 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
14761 unsigned NumArgs = MI->getNumOperands();
14762 for (unsigned i = 1; i < NumArgs; ++i) {
14763 MachineOperand &Op = MI->getOperand(i);
14764 if (!(Op.isReg() && Op.isImplicit()))
14765 MIB.addOperand(Op);
14767 if (MI->hasOneMemOperand())
14768 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
14770 BuildMI(*BB, MI, dl,
14771 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
14772 .addReg(X86::XMM0);
14774 MI->eraseFromParent();
14778 // FIXME: Custom handling because TableGen doesn't support multiple implicit
14779 // defs in an instruction pattern
14780 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
14781 const TargetInstrInfo *TII) {
14783 switch (MI->getOpcode()) {
14784 default: llvm_unreachable("illegal opcode!");
14785 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
14786 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
14787 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
14788 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
14789 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
14790 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
14791 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
14792 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
14795 DebugLoc dl = MI->getDebugLoc();
14796 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
14798 unsigned NumArgs = MI->getNumOperands(); // remove the results
14799 for (unsigned i = 1; i < NumArgs; ++i) {
14800 MachineOperand &Op = MI->getOperand(i);
14801 if (!(Op.isReg() && Op.isImplicit()))
14802 MIB.addOperand(Op);
14804 if (MI->hasOneMemOperand())
14805 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
14807 BuildMI(*BB, MI, dl,
14808 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
14811 MI->eraseFromParent();
14815 static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
14816 const TargetInstrInfo *TII,
14817 const X86Subtarget* Subtarget) {
14818 DebugLoc dl = MI->getDebugLoc();
14820 // Address into RAX/EAX, other two args into ECX, EDX.
14821 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
14822 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
14823 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
14824 for (int i = 0; i < X86::AddrNumOperands; ++i)
14825 MIB.addOperand(MI->getOperand(i));
14827 unsigned ValOps = X86::AddrNumOperands;
14828 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
14829 .addReg(MI->getOperand(ValOps).getReg());
14830 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
14831 .addReg(MI->getOperand(ValOps+1).getReg());
14833 // The instruction doesn't actually take any operands though.
14834 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
14836 MI->eraseFromParent(); // The pseudo is gone now.
14840 MachineBasicBlock *
14841 X86TargetLowering::EmitVAARG64WithCustomInserter(
14843 MachineBasicBlock *MBB) const {
14844 // Emit va_arg instruction on X86-64.
14846 // Operands to this pseudo-instruction:
14847 // 0 ) Output : destination address (reg)
14848 // 1-5) Input : va_list address (addr, i64mem)
14849 // 6 ) ArgSize : Size (in bytes) of vararg type
14850 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
14851 // 8 ) Align : Alignment of type
14852 // 9 ) EFLAGS (implicit-def)
14854 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
14855 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
14857 unsigned DestReg = MI->getOperand(0).getReg();
14858 MachineOperand &Base = MI->getOperand(1);
14859 MachineOperand &Scale = MI->getOperand(2);
14860 MachineOperand &Index = MI->getOperand(3);
14861 MachineOperand &Disp = MI->getOperand(4);
14862 MachineOperand &Segment = MI->getOperand(5);
14863 unsigned ArgSize = MI->getOperand(6).getImm();
14864 unsigned ArgMode = MI->getOperand(7).getImm();
14865 unsigned Align = MI->getOperand(8).getImm();
14867 // Memory Reference
14868 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
14869 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
14870 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
14872 // Machine Information
14873 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
14874 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
14875 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
14876 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
14877 DebugLoc DL = MI->getDebugLoc();
14879 // struct va_list {
14882 // i64 overflow_area (address)
14883 // i64 reg_save_area (address)
14885 // sizeof(va_list) = 24
14886 // alignment(va_list) = 8
14888 unsigned TotalNumIntRegs = 6;
14889 unsigned TotalNumXMMRegs = 8;
14890 bool UseGPOffset = (ArgMode == 1);
14891 bool UseFPOffset = (ArgMode == 2);
14892 unsigned MaxOffset = TotalNumIntRegs * 8 +
14893 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
14895 /* Align ArgSize to a multiple of 8 */
14896 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
14897 bool NeedsAlign = (Align > 8);
14899 MachineBasicBlock *thisMBB = MBB;
14900 MachineBasicBlock *overflowMBB;
14901 MachineBasicBlock *offsetMBB;
14902 MachineBasicBlock *endMBB;
14904 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
14905 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
14906 unsigned OffsetReg = 0;
14908 if (!UseGPOffset && !UseFPOffset) {
14909 // If we only pull from the overflow region, we don't create a branch.
14910 // We don't need to alter control flow.
14911 OffsetDestReg = 0; // unused
14912 OverflowDestReg = DestReg;
14915 overflowMBB = thisMBB;
14918 // First emit code to check if gp_offset (or fp_offset) is below the bound.
14919 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
14920 // If not, pull from overflow_area. (branch to overflowMBB)
14925 // offsetMBB overflowMBB
14930 // Registers for the PHI in endMBB
14931 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
14932 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
14934 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
14935 MachineFunction *MF = MBB->getParent();
14936 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
14937 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
14938 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
14940 MachineFunction::iterator MBBIter = MBB;
14943 // Insert the new basic blocks
14944 MF->insert(MBBIter, offsetMBB);
14945 MF->insert(MBBIter, overflowMBB);
14946 MF->insert(MBBIter, endMBB);
14948 // Transfer the remainder of MBB and its successor edges to endMBB.
14949 endMBB->splice(endMBB->begin(), thisMBB,
14950 llvm::next(MachineBasicBlock::iterator(MI)),
14952 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
14954 // Make offsetMBB and overflowMBB successors of thisMBB
14955 thisMBB->addSuccessor(offsetMBB);
14956 thisMBB->addSuccessor(overflowMBB);
14958 // endMBB is a successor of both offsetMBB and overflowMBB
14959 offsetMBB->addSuccessor(endMBB);
14960 overflowMBB->addSuccessor(endMBB);
14962 // Load the offset value into a register
14963 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
14964 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
14968 .addDisp(Disp, UseFPOffset ? 4 : 0)
14969 .addOperand(Segment)
14970 .setMemRefs(MMOBegin, MMOEnd);
14972 // Check if there is enough room left to pull this argument.
14973 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
14975 .addImm(MaxOffset + 8 - ArgSizeA8);
14977 // Branch to "overflowMBB" if offset >= max
14978 // Fall through to "offsetMBB" otherwise
14979 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
14980 .addMBB(overflowMBB);
14983 // In offsetMBB, emit code to use the reg_save_area.
14985 assert(OffsetReg != 0);
14987 // Read the reg_save_area address.
14988 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
14989 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
14994 .addOperand(Segment)
14995 .setMemRefs(MMOBegin, MMOEnd);
14997 // Zero-extend the offset
14998 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
14999 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
15002 .addImm(X86::sub_32bit);
15004 // Add the offset to the reg_save_area to get the final address.
15005 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
15006 .addReg(OffsetReg64)
15007 .addReg(RegSaveReg);
15009 // Compute the offset for the next argument
15010 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
15011 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
15013 .addImm(UseFPOffset ? 16 : 8);
15015 // Store it back into the va_list.
15016 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
15020 .addDisp(Disp, UseFPOffset ? 4 : 0)
15021 .addOperand(Segment)
15022 .addReg(NextOffsetReg)
15023 .setMemRefs(MMOBegin, MMOEnd);
15026 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
15031 // Emit code to use overflow area
15034 // Load the overflow_area address into a register.
15035 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
15036 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
15041 .addOperand(Segment)
15042 .setMemRefs(MMOBegin, MMOEnd);
15044 // If we need to align it, do so. Otherwise, just copy the address
15045 // to OverflowDestReg.
15047 // Align the overflow address
15048 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
15049 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
15051 // aligned_addr = (addr + (align-1)) & ~(align-1)
15052 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
15053 .addReg(OverflowAddrReg)
15056 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
15058 .addImm(~(uint64_t)(Align-1));
15060 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
15061 .addReg(OverflowAddrReg);
15064 // Compute the next overflow address after this argument.
15065 // (the overflow address should be kept 8-byte aligned)
15066 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
15067 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
15068 .addReg(OverflowDestReg)
15069 .addImm(ArgSizeA8);
15071 // Store the new overflow address.
15072 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
15077 .addOperand(Segment)
15078 .addReg(NextAddrReg)
15079 .setMemRefs(MMOBegin, MMOEnd);
15081 // If we branched, emit the PHI to the front of endMBB.
15083 BuildMI(*endMBB, endMBB->begin(), DL,
15084 TII->get(X86::PHI), DestReg)
15085 .addReg(OffsetDestReg).addMBB(offsetMBB)
15086 .addReg(OverflowDestReg).addMBB(overflowMBB);
15089 // Erase the pseudo instruction
15090 MI->eraseFromParent();
15095 MachineBasicBlock *
15096 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
15098 MachineBasicBlock *MBB) const {
15099 // Emit code to save XMM registers to the stack. The ABI says that the
15100 // number of registers to save is given in %al, so it's theoretically
15101 // possible to do an indirect jump trick to avoid saving all of them,
15102 // however this code takes a simpler approach and just executes all
15103 // of the stores if %al is non-zero. It's less code, and it's probably
15104 // easier on the hardware branch predictor, and stores aren't all that
15105 // expensive anyway.
15107 // Create the new basic blocks. One block contains all the XMM stores,
15108 // and one block is the final destination regardless of whether any
15109 // stores were performed.
15110 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
15111 MachineFunction *F = MBB->getParent();
15112 MachineFunction::iterator MBBIter = MBB;
15114 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
15115 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
15116 F->insert(MBBIter, XMMSaveMBB);
15117 F->insert(MBBIter, EndMBB);
15119 // Transfer the remainder of MBB and its successor edges to EndMBB.
15120 EndMBB->splice(EndMBB->begin(), MBB,
15121 llvm::next(MachineBasicBlock::iterator(MI)),
15123 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
15125 // The original block will now fall through to the XMM save block.
15126 MBB->addSuccessor(XMMSaveMBB);
15127 // The XMMSaveMBB will fall through to the end block.
15128 XMMSaveMBB->addSuccessor(EndMBB);
15130 // Now add the instructions.
15131 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15132 DebugLoc DL = MI->getDebugLoc();
15134 unsigned CountReg = MI->getOperand(0).getReg();
15135 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
15136 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
15138 if (!Subtarget->isTargetWin64()) {
15139 // If %al is 0, branch around the XMM save block.
15140 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
15141 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
15142 MBB->addSuccessor(EndMBB);
15145 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
15146 // In the XMM save block, save all the XMM argument registers.
15147 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
15148 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
15149 MachineMemOperand *MMO =
15150 F->getMachineMemOperand(
15151 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
15152 MachineMemOperand::MOStore,
15153 /*Size=*/16, /*Align=*/16);
15154 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
15155 .addFrameIndex(RegSaveFrameIndex)
15156 .addImm(/*Scale=*/1)
15157 .addReg(/*IndexReg=*/0)
15158 .addImm(/*Disp=*/Offset)
15159 .addReg(/*Segment=*/0)
15160 .addReg(MI->getOperand(i).getReg())
15161 .addMemOperand(MMO);
15164 MI->eraseFromParent(); // The pseudo instruction is gone now.
15169 // The EFLAGS operand of SelectItr might be missing a kill marker
15170 // because there were multiple uses of EFLAGS, and ISel didn't know
15171 // which to mark. Figure out whether SelectItr should have had a
15172 // kill marker, and set it if it should. Returns the correct kill
15174 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
15175 MachineBasicBlock* BB,
15176 const TargetRegisterInfo* TRI) {
15177 // Scan forward through BB for a use/def of EFLAGS.
15178 MachineBasicBlock::iterator miI(llvm::next(SelectItr));
15179 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
15180 const MachineInstr& mi = *miI;
15181 if (mi.readsRegister(X86::EFLAGS))
15183 if (mi.definesRegister(X86::EFLAGS))
15184 break; // Should have kill-flag - update below.
15187 // If we hit the end of the block, check whether EFLAGS is live into a
15189 if (miI == BB->end()) {
15190 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
15191 sEnd = BB->succ_end();
15192 sItr != sEnd; ++sItr) {
15193 MachineBasicBlock* succ = *sItr;
15194 if (succ->isLiveIn(X86::EFLAGS))
15199 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
15200 // out. SelectMI should have a kill flag on EFLAGS.
15201 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
15205 MachineBasicBlock *
15206 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
15207 MachineBasicBlock *BB) const {
15208 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15209 DebugLoc DL = MI->getDebugLoc();
15211 // To "insert" a SELECT_CC instruction, we actually have to insert the
15212 // diamond control-flow pattern. The incoming instruction knows the
15213 // destination vreg to set, the condition code register to branch on, the
15214 // true/false values to select between, and a branch opcode to use.
15215 const BasicBlock *LLVM_BB = BB->getBasicBlock();
15216 MachineFunction::iterator It = BB;
15222 // cmpTY ccX, r1, r2
15224 // fallthrough --> copy0MBB
15225 MachineBasicBlock *thisMBB = BB;
15226 MachineFunction *F = BB->getParent();
15227 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
15228 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
15229 F->insert(It, copy0MBB);
15230 F->insert(It, sinkMBB);
15232 // If the EFLAGS register isn't dead in the terminator, then claim that it's
15233 // live into the sink and copy blocks.
15234 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
15235 if (!MI->killsRegister(X86::EFLAGS) &&
15236 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
15237 copy0MBB->addLiveIn(X86::EFLAGS);
15238 sinkMBB->addLiveIn(X86::EFLAGS);
15241 // Transfer the remainder of BB and its successor edges to sinkMBB.
15242 sinkMBB->splice(sinkMBB->begin(), BB,
15243 llvm::next(MachineBasicBlock::iterator(MI)),
15245 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
15247 // Add the true and fallthrough blocks as its successors.
15248 BB->addSuccessor(copy0MBB);
15249 BB->addSuccessor(sinkMBB);
15251 // Create the conditional branch instruction.
15253 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
15254 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
15257 // %FalseValue = ...
15258 // # fallthrough to sinkMBB
15259 copy0MBB->addSuccessor(sinkMBB);
15262 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
15264 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
15265 TII->get(X86::PHI), MI->getOperand(0).getReg())
15266 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
15267 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
15269 MI->eraseFromParent(); // The pseudo instruction is gone now.
15273 MachineBasicBlock *
15274 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB,
15275 bool Is64Bit) const {
15276 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15277 DebugLoc DL = MI->getDebugLoc();
15278 MachineFunction *MF = BB->getParent();
15279 const BasicBlock *LLVM_BB = BB->getBasicBlock();
15281 assert(getTargetMachine().Options.EnableSegmentedStacks);
15283 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
15284 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30;
15287 // ... [Till the alloca]
15288 // If stacklet is not large enough, jump to mallocMBB
15291 // Allocate by subtracting from RSP
15292 // Jump to continueMBB
15295 // Allocate by call to runtime
15299 // [rest of original BB]
15302 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
15303 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
15304 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
15306 MachineRegisterInfo &MRI = MF->getRegInfo();
15307 const TargetRegisterClass *AddrRegClass =
15308 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32);
15310 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
15311 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
15312 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
15313 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
15314 sizeVReg = MI->getOperand(1).getReg(),
15315 physSPReg = Is64Bit ? X86::RSP : X86::ESP;
15317 MachineFunction::iterator MBBIter = BB;
15320 MF->insert(MBBIter, bumpMBB);
15321 MF->insert(MBBIter, mallocMBB);
15322 MF->insert(MBBIter, continueMBB);
15324 continueMBB->splice(continueMBB->begin(), BB, llvm::next
15325 (MachineBasicBlock::iterator(MI)), BB->end());
15326 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
15328 // Add code to the main basic block to check if the stack limit has been hit,
15329 // and if so, jump to mallocMBB otherwise to bumpMBB.
15330 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
15331 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
15332 .addReg(tmpSPVReg).addReg(sizeVReg);
15333 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr))
15334 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
15335 .addReg(SPLimitVReg);
15336 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
15338 // bumpMBB simply decreases the stack pointer, since we know the current
15339 // stacklet has enough space.
15340 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
15341 .addReg(SPLimitVReg);
15342 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
15343 .addReg(SPLimitVReg);
15344 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
15346 // Calls into a routine in libgcc to allocate more space from the heap.
15347 const uint32_t *RegMask =
15348 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
15350 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
15352 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
15353 .addExternalSymbol("__morestack_allocate_stack_space")
15354 .addRegMask(RegMask)
15355 .addReg(X86::RDI, RegState::Implicit)
15356 .addReg(X86::RAX, RegState::ImplicitDefine);
15358 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
15360 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
15361 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
15362 .addExternalSymbol("__morestack_allocate_stack_space")
15363 .addRegMask(RegMask)
15364 .addReg(X86::EAX, RegState::ImplicitDefine);
15368 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
15371 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
15372 .addReg(Is64Bit ? X86::RAX : X86::EAX);
15373 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
15375 // Set up the CFG correctly.
15376 BB->addSuccessor(bumpMBB);
15377 BB->addSuccessor(mallocMBB);
15378 mallocMBB->addSuccessor(continueMBB);
15379 bumpMBB->addSuccessor(continueMBB);
15381 // Take care of the PHI nodes.
15382 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
15383 MI->getOperand(0).getReg())
15384 .addReg(mallocPtrVReg).addMBB(mallocMBB)
15385 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
15387 // Delete the original pseudo instruction.
15388 MI->eraseFromParent();
15391 return continueMBB;
15394 MachineBasicBlock *
15395 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
15396 MachineBasicBlock *BB) const {
15397 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15398 DebugLoc DL = MI->getDebugLoc();
15400 assert(!Subtarget->isTargetEnvMacho());
15402 // The lowering is pretty easy: we're just emitting the call to _alloca. The
15403 // non-trivial part is impdef of ESP.
15405 if (Subtarget->isTargetWin64()) {
15406 if (Subtarget->isTargetCygMing()) {
15407 // ___chkstk(Mingw64):
15408 // Clobbers R10, R11, RAX and EFLAGS.
15410 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
15411 .addExternalSymbol("___chkstk")
15412 .addReg(X86::RAX, RegState::Implicit)
15413 .addReg(X86::RSP, RegState::Implicit)
15414 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
15415 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
15416 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
15418 // __chkstk(MSVCRT): does not update stack pointer.
15419 // Clobbers R10, R11 and EFLAGS.
15420 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
15421 .addExternalSymbol("__chkstk")
15422 .addReg(X86::RAX, RegState::Implicit)
15423 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
15424 // RAX has the offset to be subtracted from RSP.
15425 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
15430 const char *StackProbeSymbol =
15431 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca";
15433 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
15434 .addExternalSymbol(StackProbeSymbol)
15435 .addReg(X86::EAX, RegState::Implicit)
15436 .addReg(X86::ESP, RegState::Implicit)
15437 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
15438 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
15439 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
15442 MI->eraseFromParent(); // The pseudo instruction is gone now.
15446 MachineBasicBlock *
15447 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
15448 MachineBasicBlock *BB) const {
15449 // This is pretty easy. We're taking the value that we received from
15450 // our load from the relocation, sticking it in either RDI (x86-64)
15451 // or EAX and doing an indirect call. The return value will then
15452 // be in the normal return register.
15453 const X86InstrInfo *TII
15454 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo());
15455 DebugLoc DL = MI->getDebugLoc();
15456 MachineFunction *F = BB->getParent();
15458 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
15459 assert(MI->getOperand(3).isGlobal() && "This should be a global");
15461 // Get a register mask for the lowered call.
15462 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
15463 // proper register mask.
15464 const uint32_t *RegMask =
15465 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
15466 if (Subtarget->is64Bit()) {
15467 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
15468 TII->get(X86::MOV64rm), X86::RDI)
15470 .addImm(0).addReg(0)
15471 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
15472 MI->getOperand(3).getTargetFlags())
15474 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
15475 addDirectMem(MIB, X86::RDI);
15476 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
15477 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
15478 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
15479 TII->get(X86::MOV32rm), X86::EAX)
15481 .addImm(0).addReg(0)
15482 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
15483 MI->getOperand(3).getTargetFlags())
15485 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
15486 addDirectMem(MIB, X86::EAX);
15487 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
15489 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
15490 TII->get(X86::MOV32rm), X86::EAX)
15491 .addReg(TII->getGlobalBaseReg(F))
15492 .addImm(0).addReg(0)
15493 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
15494 MI->getOperand(3).getTargetFlags())
15496 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
15497 addDirectMem(MIB, X86::EAX);
15498 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
15501 MI->eraseFromParent(); // The pseudo instruction is gone now.
15505 MachineBasicBlock *
15506 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
15507 MachineBasicBlock *MBB) const {
15508 DebugLoc DL = MI->getDebugLoc();
15509 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15511 MachineFunction *MF = MBB->getParent();
15512 MachineRegisterInfo &MRI = MF->getRegInfo();
15514 const BasicBlock *BB = MBB->getBasicBlock();
15515 MachineFunction::iterator I = MBB;
15518 // Memory Reference
15519 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
15520 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
15523 unsigned MemOpndSlot = 0;
15525 unsigned CurOp = 0;
15527 DstReg = MI->getOperand(CurOp++).getReg();
15528 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
15529 assert(RC->hasType(MVT::i32) && "Invalid destination!");
15530 unsigned mainDstReg = MRI.createVirtualRegister(RC);
15531 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
15533 MemOpndSlot = CurOp;
15535 MVT PVT = getPointerTy();
15536 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
15537 "Invalid Pointer Size!");
15539 // For v = setjmp(buf), we generate
15542 // buf[LabelOffset] = restoreMBB
15543 // SjLjSetup restoreMBB
15549 // v = phi(main, restore)
15554 MachineBasicBlock *thisMBB = MBB;
15555 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
15556 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
15557 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
15558 MF->insert(I, mainMBB);
15559 MF->insert(I, sinkMBB);
15560 MF->push_back(restoreMBB);
15562 MachineInstrBuilder MIB;
15564 // Transfer the remainder of BB and its successor edges to sinkMBB.
15565 sinkMBB->splice(sinkMBB->begin(), MBB,
15566 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
15567 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
15570 unsigned PtrStoreOpc = 0;
15571 unsigned LabelReg = 0;
15572 const int64_t LabelOffset = 1 * PVT.getStoreSize();
15573 Reloc::Model RM = getTargetMachine().getRelocationModel();
15574 bool UseImmLabel = (getTargetMachine().getCodeModel() == CodeModel::Small) &&
15575 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
15577 // Prepare IP either in reg or imm.
15578 if (!UseImmLabel) {
15579 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
15580 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
15581 LabelReg = MRI.createVirtualRegister(PtrRC);
15582 if (Subtarget->is64Bit()) {
15583 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
15587 .addMBB(restoreMBB)
15590 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
15591 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
15592 .addReg(XII->getGlobalBaseReg(MF))
15595 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
15599 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
15601 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
15602 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
15603 if (i == X86::AddrDisp)
15604 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
15606 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
15609 MIB.addReg(LabelReg);
15611 MIB.addMBB(restoreMBB);
15612 MIB.setMemRefs(MMOBegin, MMOEnd);
15614 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
15615 .addMBB(restoreMBB);
15617 const X86RegisterInfo *RegInfo =
15618 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
15619 MIB.addRegMask(RegInfo->getNoPreservedMask());
15620 thisMBB->addSuccessor(mainMBB);
15621 thisMBB->addSuccessor(restoreMBB);
15625 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
15626 mainMBB->addSuccessor(sinkMBB);
15629 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
15630 TII->get(X86::PHI), DstReg)
15631 .addReg(mainDstReg).addMBB(mainMBB)
15632 .addReg(restoreDstReg).addMBB(restoreMBB);
15635 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
15636 BuildMI(restoreMBB, DL, TII->get(X86::JMP_4)).addMBB(sinkMBB);
15637 restoreMBB->addSuccessor(sinkMBB);
15639 MI->eraseFromParent();
15643 MachineBasicBlock *
15644 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
15645 MachineBasicBlock *MBB) const {
15646 DebugLoc DL = MI->getDebugLoc();
15647 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15649 MachineFunction *MF = MBB->getParent();
15650 MachineRegisterInfo &MRI = MF->getRegInfo();
15652 // Memory Reference
15653 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
15654 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
15656 MVT PVT = getPointerTy();
15657 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
15658 "Invalid Pointer Size!");
15660 const TargetRegisterClass *RC =
15661 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
15662 unsigned Tmp = MRI.createVirtualRegister(RC);
15663 // Since FP is only updated here but NOT referenced, it's treated as GPR.
15664 const X86RegisterInfo *RegInfo =
15665 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
15666 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
15667 unsigned SP = RegInfo->getStackRegister();
15669 MachineInstrBuilder MIB;
15671 const int64_t LabelOffset = 1 * PVT.getStoreSize();
15672 const int64_t SPOffset = 2 * PVT.getStoreSize();
15674 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
15675 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
15678 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
15679 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
15680 MIB.addOperand(MI->getOperand(i));
15681 MIB.setMemRefs(MMOBegin, MMOEnd);
15683 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
15684 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
15685 if (i == X86::AddrDisp)
15686 MIB.addDisp(MI->getOperand(i), LabelOffset);
15688 MIB.addOperand(MI->getOperand(i));
15690 MIB.setMemRefs(MMOBegin, MMOEnd);
15692 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
15693 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
15694 if (i == X86::AddrDisp)
15695 MIB.addDisp(MI->getOperand(i), SPOffset);
15697 MIB.addOperand(MI->getOperand(i));
15699 MIB.setMemRefs(MMOBegin, MMOEnd);
15701 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
15703 MI->eraseFromParent();
15707 MachineBasicBlock *
15708 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
15709 MachineBasicBlock *BB) const {
15710 switch (MI->getOpcode()) {
15711 default: llvm_unreachable("Unexpected instr type to insert");
15712 case X86::TAILJMPd64:
15713 case X86::TAILJMPr64:
15714 case X86::TAILJMPm64:
15715 llvm_unreachable("TAILJMP64 would not be touched here.");
15716 case X86::TCRETURNdi64:
15717 case X86::TCRETURNri64:
15718 case X86::TCRETURNmi64:
15720 case X86::WIN_ALLOCA:
15721 return EmitLoweredWinAlloca(MI, BB);
15722 case X86::SEG_ALLOCA_32:
15723 return EmitLoweredSegAlloca(MI, BB, false);
15724 case X86::SEG_ALLOCA_64:
15725 return EmitLoweredSegAlloca(MI, BB, true);
15726 case X86::TLSCall_32:
15727 case X86::TLSCall_64:
15728 return EmitLoweredTLSCall(MI, BB);
15729 case X86::CMOV_GR8:
15730 case X86::CMOV_FR32:
15731 case X86::CMOV_FR64:
15732 case X86::CMOV_V4F32:
15733 case X86::CMOV_V2F64:
15734 case X86::CMOV_V2I64:
15735 case X86::CMOV_V8F32:
15736 case X86::CMOV_V4F64:
15737 case X86::CMOV_V4I64:
15738 case X86::CMOV_GR16:
15739 case X86::CMOV_GR32:
15740 case X86::CMOV_RFP32:
15741 case X86::CMOV_RFP64:
15742 case X86::CMOV_RFP80:
15743 return EmitLoweredSelect(MI, BB);
15745 case X86::FP32_TO_INT16_IN_MEM:
15746 case X86::FP32_TO_INT32_IN_MEM:
15747 case X86::FP32_TO_INT64_IN_MEM:
15748 case X86::FP64_TO_INT16_IN_MEM:
15749 case X86::FP64_TO_INT32_IN_MEM:
15750 case X86::FP64_TO_INT64_IN_MEM:
15751 case X86::FP80_TO_INT16_IN_MEM:
15752 case X86::FP80_TO_INT32_IN_MEM:
15753 case X86::FP80_TO_INT64_IN_MEM: {
15754 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15755 DebugLoc DL = MI->getDebugLoc();
15757 // Change the floating point control register to use "round towards zero"
15758 // mode when truncating to an integer value.
15759 MachineFunction *F = BB->getParent();
15760 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
15761 addFrameReference(BuildMI(*BB, MI, DL,
15762 TII->get(X86::FNSTCW16m)), CWFrameIdx);
15764 // Load the old value of the high byte of the control word...
15766 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
15767 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
15770 // Set the high part to be round to zero...
15771 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
15774 // Reload the modified control word now...
15775 addFrameReference(BuildMI(*BB, MI, DL,
15776 TII->get(X86::FLDCW16m)), CWFrameIdx);
15778 // Restore the memory image of control word to original value
15779 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
15782 // Get the X86 opcode to use.
15784 switch (MI->getOpcode()) {
15785 default: llvm_unreachable("illegal opcode!");
15786 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
15787 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
15788 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
15789 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
15790 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
15791 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
15792 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
15793 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
15794 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
15798 MachineOperand &Op = MI->getOperand(0);
15800 AM.BaseType = X86AddressMode::RegBase;
15801 AM.Base.Reg = Op.getReg();
15803 AM.BaseType = X86AddressMode::FrameIndexBase;
15804 AM.Base.FrameIndex = Op.getIndex();
15806 Op = MI->getOperand(1);
15808 AM.Scale = Op.getImm();
15809 Op = MI->getOperand(2);
15811 AM.IndexReg = Op.getImm();
15812 Op = MI->getOperand(3);
15813 if (Op.isGlobal()) {
15814 AM.GV = Op.getGlobal();
15816 AM.Disp = Op.getImm();
15818 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
15819 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
15821 // Reload the original control word now.
15822 addFrameReference(BuildMI(*BB, MI, DL,
15823 TII->get(X86::FLDCW16m)), CWFrameIdx);
15825 MI->eraseFromParent(); // The pseudo instruction is gone now.
15828 // String/text processing lowering.
15829 case X86::PCMPISTRM128REG:
15830 case X86::VPCMPISTRM128REG:
15831 case X86::PCMPISTRM128MEM:
15832 case X86::VPCMPISTRM128MEM:
15833 case X86::PCMPESTRM128REG:
15834 case X86::VPCMPESTRM128REG:
15835 case X86::PCMPESTRM128MEM:
15836 case X86::VPCMPESTRM128MEM:
15837 assert(Subtarget->hasSSE42() &&
15838 "Target must have SSE4.2 or AVX features enabled");
15839 return EmitPCMPSTRM(MI, BB, getTargetMachine().getInstrInfo());
15841 // String/text processing lowering.
15842 case X86::PCMPISTRIREG:
15843 case X86::VPCMPISTRIREG:
15844 case X86::PCMPISTRIMEM:
15845 case X86::VPCMPISTRIMEM:
15846 case X86::PCMPESTRIREG:
15847 case X86::VPCMPESTRIREG:
15848 case X86::PCMPESTRIMEM:
15849 case X86::VPCMPESTRIMEM:
15850 assert(Subtarget->hasSSE42() &&
15851 "Target must have SSE4.2 or AVX features enabled");
15852 return EmitPCMPSTRI(MI, BB, getTargetMachine().getInstrInfo());
15854 // Thread synchronization.
15856 return EmitMonitor(MI, BB, getTargetMachine().getInstrInfo(), Subtarget);
15860 return EmitXBegin(MI, BB, getTargetMachine().getInstrInfo());
15862 // Atomic Lowering.
15863 case X86::ATOMAND8:
15864 case X86::ATOMAND16:
15865 case X86::ATOMAND32:
15866 case X86::ATOMAND64:
15869 case X86::ATOMOR16:
15870 case X86::ATOMOR32:
15871 case X86::ATOMOR64:
15873 case X86::ATOMXOR16:
15874 case X86::ATOMXOR8:
15875 case X86::ATOMXOR32:
15876 case X86::ATOMXOR64:
15878 case X86::ATOMNAND8:
15879 case X86::ATOMNAND16:
15880 case X86::ATOMNAND32:
15881 case X86::ATOMNAND64:
15883 case X86::ATOMMAX8:
15884 case X86::ATOMMAX16:
15885 case X86::ATOMMAX32:
15886 case X86::ATOMMAX64:
15888 case X86::ATOMMIN8:
15889 case X86::ATOMMIN16:
15890 case X86::ATOMMIN32:
15891 case X86::ATOMMIN64:
15893 case X86::ATOMUMAX8:
15894 case X86::ATOMUMAX16:
15895 case X86::ATOMUMAX32:
15896 case X86::ATOMUMAX64:
15898 case X86::ATOMUMIN8:
15899 case X86::ATOMUMIN16:
15900 case X86::ATOMUMIN32:
15901 case X86::ATOMUMIN64:
15902 return EmitAtomicLoadArith(MI, BB);
15904 // This group does 64-bit operations on a 32-bit host.
15905 case X86::ATOMAND6432:
15906 case X86::ATOMOR6432:
15907 case X86::ATOMXOR6432:
15908 case X86::ATOMNAND6432:
15909 case X86::ATOMADD6432:
15910 case X86::ATOMSUB6432:
15911 case X86::ATOMMAX6432:
15912 case X86::ATOMMIN6432:
15913 case X86::ATOMUMAX6432:
15914 case X86::ATOMUMIN6432:
15915 case X86::ATOMSWAP6432:
15916 return EmitAtomicLoadArith6432(MI, BB);
15918 case X86::VASTART_SAVE_XMM_REGS:
15919 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
15921 case X86::VAARG_64:
15922 return EmitVAARG64WithCustomInserter(MI, BB);
15924 case X86::EH_SjLj_SetJmp32:
15925 case X86::EH_SjLj_SetJmp64:
15926 return emitEHSjLjSetJmp(MI, BB);
15928 case X86::EH_SjLj_LongJmp32:
15929 case X86::EH_SjLj_LongJmp64:
15930 return emitEHSjLjLongJmp(MI, BB);
15934 //===----------------------------------------------------------------------===//
15935 // X86 Optimization Hooks
15936 //===----------------------------------------------------------------------===//
15938 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
15941 const SelectionDAG &DAG,
15942 unsigned Depth) const {
15943 unsigned BitWidth = KnownZero.getBitWidth();
15944 unsigned Opc = Op.getOpcode();
15945 assert((Opc >= ISD::BUILTIN_OP_END ||
15946 Opc == ISD::INTRINSIC_WO_CHAIN ||
15947 Opc == ISD::INTRINSIC_W_CHAIN ||
15948 Opc == ISD::INTRINSIC_VOID) &&
15949 "Should use MaskedValueIsZero if you don't know whether Op"
15950 " is a target node!");
15952 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
15966 // These nodes' second result is a boolean.
15967 if (Op.getResNo() == 0)
15970 case X86ISD::SETCC:
15971 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
15973 case ISD::INTRINSIC_WO_CHAIN: {
15974 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15975 unsigned NumLoBits = 0;
15978 case Intrinsic::x86_sse_movmsk_ps:
15979 case Intrinsic::x86_avx_movmsk_ps_256:
15980 case Intrinsic::x86_sse2_movmsk_pd:
15981 case Intrinsic::x86_avx_movmsk_pd_256:
15982 case Intrinsic::x86_mmx_pmovmskb:
15983 case Intrinsic::x86_sse2_pmovmskb_128:
15984 case Intrinsic::x86_avx2_pmovmskb: {
15985 // High bits of movmskp{s|d}, pmovmskb are known zero.
15987 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
15988 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
15989 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
15990 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
15991 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
15992 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
15993 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
15994 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
15996 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
16005 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
16006 unsigned Depth) const {
16007 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
16008 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
16009 return Op.getValueType().getScalarType().getSizeInBits();
16015 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
16016 /// node is a GlobalAddress + offset.
16017 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
16018 const GlobalValue* &GA,
16019 int64_t &Offset) const {
16020 if (N->getOpcode() == X86ISD::Wrapper) {
16021 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
16022 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
16023 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
16027 return TargetLowering::isGAPlusOffset(N, GA, Offset);
16030 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
16031 /// same as extracting the high 128-bit part of 256-bit vector and then
16032 /// inserting the result into the low part of a new 256-bit vector
16033 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
16034 EVT VT = SVOp->getValueType(0);
16035 unsigned NumElems = VT.getVectorNumElements();
16037 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
16038 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
16039 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
16040 SVOp->getMaskElt(j) >= 0)
16046 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
16047 /// same as extracting the low 128-bit part of 256-bit vector and then
16048 /// inserting the result into the high part of a new 256-bit vector
16049 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
16050 EVT VT = SVOp->getValueType(0);
16051 unsigned NumElems = VT.getVectorNumElements();
16053 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
16054 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
16055 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
16056 SVOp->getMaskElt(j) >= 0)
16062 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
16063 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
16064 TargetLowering::DAGCombinerInfo &DCI,
16065 const X86Subtarget* Subtarget) {
16067 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
16068 SDValue V1 = SVOp->getOperand(0);
16069 SDValue V2 = SVOp->getOperand(1);
16070 EVT VT = SVOp->getValueType(0);
16071 unsigned NumElems = VT.getVectorNumElements();
16073 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
16074 V2.getOpcode() == ISD::CONCAT_VECTORS) {
16078 // V UNDEF BUILD_VECTOR UNDEF
16080 // CONCAT_VECTOR CONCAT_VECTOR
16083 // RESULT: V + zero extended
16085 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
16086 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
16087 V1.getOperand(1).getOpcode() != ISD::UNDEF)
16090 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
16093 // To match the shuffle mask, the first half of the mask should
16094 // be exactly the first vector, and all the rest a splat with the
16095 // first element of the second one.
16096 for (unsigned i = 0; i != NumElems/2; ++i)
16097 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
16098 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
16101 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
16102 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
16103 if (Ld->hasNUsesOfValue(1, 0)) {
16104 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
16105 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
16107 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
16108 array_lengthof(Ops),
16110 Ld->getPointerInfo(),
16111 Ld->getAlignment(),
16112 false/*isVolatile*/, true/*ReadMem*/,
16113 false/*WriteMem*/);
16115 // Make sure the newly-created LOAD is in the same position as Ld in
16116 // terms of dependency. We create a TokenFactor for Ld and ResNode,
16117 // and update uses of Ld's output chain to use the TokenFactor.
16118 if (Ld->hasAnyUseOfValue(1)) {
16119 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
16120 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
16121 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
16122 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
16123 SDValue(ResNode.getNode(), 1));
16126 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
16130 // Emit a zeroed vector and insert the desired subvector on its
16132 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
16133 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
16134 return DCI.CombineTo(N, InsV);
16137 //===--------------------------------------------------------------------===//
16138 // Combine some shuffles into subvector extracts and inserts:
16141 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
16142 if (isShuffleHigh128VectorInsertLow(SVOp)) {
16143 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
16144 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
16145 return DCI.CombineTo(N, InsV);
16148 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
16149 if (isShuffleLow128VectorInsertHigh(SVOp)) {
16150 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
16151 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
16152 return DCI.CombineTo(N, InsV);
16158 static SDValue PerformConcatCombine(SDNode *N, SelectionDAG &DAG,
16159 TargetLowering::DAGCombinerInfo &DCI,
16160 const X86Subtarget *Subtarget) {
16161 // Creating a v8i16 from a v4i16 argument and an undef runs into trouble in
16162 // type legalization and ends up spilling to the stack. Avoid that by
16163 // creating a vector first and bitcasting the result rather than
16164 // bitcasting the source then creating the vector. Similar problems with
16167 // No point in doing this after legalize, so early exit for that.
16168 if (!DCI.isBeforeLegalize())
16171 EVT VT = N->getValueType(0);
16172 SDValue Op0 = N->getOperand(0);
16173 SDValue Op1 = N->getOperand(1);
16174 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16175 if (VT.getSizeInBits() == 128 && N->getNumOperands() == 2 &&
16176 Op1->getOpcode() == ISD::UNDEF &&
16177 Op0->getOpcode() == ISD::BITCAST &&
16178 !TLI.isTypeLegal(Op0->getValueType(0)) &&
16179 TLI.isTypeLegal(Op0->getOperand(0)->getValueType(0))) {
16180 if (Op0->getOperand(0)->getValueType(0).isVector())
16182 SDValue Scalar = Op0->getOperand(0);
16183 // Any legal type here will be a simple value type.
16184 MVT SVT = Scalar->getValueType(0).getSimpleVT();
16185 // As a special case, bail out on MMX values.
16186 if (SVT == MVT::x86mmx)
16188 EVT NVT = MVT::getVectorVT(SVT, 2);
16189 // If the result vector type isn't legal, this transform won't really
16190 // help, so bail on that, too.
16191 if (!TLI.isTypeLegal(NVT))
16193 SDLoc dl = SDLoc(N);
16194 SDValue Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NVT, Scalar);
16195 Res = DAG.getNode(ISD::BITCAST, dl, VT, Res);
16202 /// PerformShuffleCombine - Performs several different shuffle combines.
16203 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
16204 TargetLowering::DAGCombinerInfo &DCI,
16205 const X86Subtarget *Subtarget) {
16207 EVT VT = N->getValueType(0);
16209 // Don't create instructions with illegal types after legalize types has run.
16210 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16211 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
16214 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
16215 if (Subtarget->hasFp256() && VT.is256BitVector() &&
16216 N->getOpcode() == ISD::VECTOR_SHUFFLE)
16217 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
16219 // Only handle 128 wide vector from here on.
16220 if (!VT.is128BitVector())
16223 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
16224 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
16225 // consecutive, non-overlapping, and in the right order.
16226 SmallVector<SDValue, 16> Elts;
16227 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
16228 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
16230 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG);
16233 /// PerformTruncateCombine - Converts truncate operation to
16234 /// a sequence of vector shuffle operations.
16235 /// It is possible when we truncate 256-bit vector to 128-bit vector
16236 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
16237 TargetLowering::DAGCombinerInfo &DCI,
16238 const X86Subtarget *Subtarget) {
16242 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
16243 /// specific shuffle of a load can be folded into a single element load.
16244 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
16245 /// shuffles have been customed lowered so we need to handle those here.
16246 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
16247 TargetLowering::DAGCombinerInfo &DCI) {
16248 if (DCI.isBeforeLegalizeOps())
16251 SDValue InVec = N->getOperand(0);
16252 SDValue EltNo = N->getOperand(1);
16254 if (!isa<ConstantSDNode>(EltNo))
16257 EVT VT = InVec.getValueType();
16259 bool HasShuffleIntoBitcast = false;
16260 if (InVec.getOpcode() == ISD::BITCAST) {
16261 // Don't duplicate a load with other uses.
16262 if (!InVec.hasOneUse())
16264 EVT BCVT = InVec.getOperand(0).getValueType();
16265 if (BCVT.getVectorNumElements() != VT.getVectorNumElements())
16267 InVec = InVec.getOperand(0);
16268 HasShuffleIntoBitcast = true;
16271 if (!isTargetShuffle(InVec.getOpcode()))
16274 // Don't duplicate a load with other uses.
16275 if (!InVec.hasOneUse())
16278 SmallVector<int, 16> ShuffleMask;
16280 if (!getTargetShuffleMask(InVec.getNode(), VT.getSimpleVT(), ShuffleMask,
16284 // Select the input vector, guarding against out of range extract vector.
16285 unsigned NumElems = VT.getVectorNumElements();
16286 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
16287 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
16288 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
16289 : InVec.getOperand(1);
16291 // If inputs to shuffle are the same for both ops, then allow 2 uses
16292 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
16294 if (LdNode.getOpcode() == ISD::BITCAST) {
16295 // Don't duplicate a load with other uses.
16296 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
16299 AllowedUses = 1; // only allow 1 load use if we have a bitcast
16300 LdNode = LdNode.getOperand(0);
16303 if (!ISD::isNormalLoad(LdNode.getNode()))
16306 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
16308 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
16311 if (HasShuffleIntoBitcast) {
16312 // If there's a bitcast before the shuffle, check if the load type and
16313 // alignment is valid.
16314 unsigned Align = LN0->getAlignment();
16315 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16316 unsigned NewAlign = TLI.getDataLayout()->
16317 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
16319 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
16323 // All checks match so transform back to vector_shuffle so that DAG combiner
16324 // can finish the job
16327 // Create shuffle node taking into account the case that its a unary shuffle
16328 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1);
16329 Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl,
16330 InVec.getOperand(0), Shuffle,
16332 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
16333 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
16337 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
16338 /// generation and convert it from being a bunch of shuffles and extracts
16339 /// to a simple store and scalar loads to extract the elements.
16340 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
16341 TargetLowering::DAGCombinerInfo &DCI) {
16342 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
16343 if (NewOp.getNode())
16346 SDValue InputVector = N->getOperand(0);
16347 // Detect whether we are trying to convert from mmx to i32 and the bitcast
16348 // from mmx to v2i32 has a single usage.
16349 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
16350 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
16351 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
16352 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
16353 N->getValueType(0),
16354 InputVector.getNode()->getOperand(0));
16356 // Only operate on vectors of 4 elements, where the alternative shuffling
16357 // gets to be more expensive.
16358 if (InputVector.getValueType() != MVT::v4i32)
16361 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
16362 // single use which is a sign-extend or zero-extend, and all elements are
16364 SmallVector<SDNode *, 4> Uses;
16365 unsigned ExtractedElements = 0;
16366 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
16367 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
16368 if (UI.getUse().getResNo() != InputVector.getResNo())
16371 SDNode *Extract = *UI;
16372 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
16375 if (Extract->getValueType(0) != MVT::i32)
16377 if (!Extract->hasOneUse())
16379 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
16380 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
16382 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
16385 // Record which element was extracted.
16386 ExtractedElements |=
16387 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
16389 Uses.push_back(Extract);
16392 // If not all the elements were used, this may not be worthwhile.
16393 if (ExtractedElements != 15)
16396 // Ok, we've now decided to do the transformation.
16397 SDLoc dl(InputVector);
16399 // Store the value to a temporary stack slot.
16400 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
16401 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
16402 MachinePointerInfo(), false, false, 0);
16404 // Replace each use (extract) with a load of the appropriate element.
16405 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
16406 UE = Uses.end(); UI != UE; ++UI) {
16407 SDNode *Extract = *UI;
16409 // cOMpute the element's address.
16410 SDValue Idx = Extract->getOperand(1);
16412 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
16413 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
16414 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16415 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
16417 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
16418 StackPtr, OffsetVal);
16420 // Load the scalar.
16421 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
16422 ScalarAddr, MachinePointerInfo(),
16423 false, false, false, 0);
16425 // Replace the exact with the load.
16426 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
16429 // The replacement was made in place; don't return anything.
16433 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
16434 static std::pair<unsigned, bool>
16435 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
16436 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
16437 if (!VT.isVector())
16438 return std::make_pair(0, false);
16440 bool NeedSplit = false;
16441 switch (VT.getSimpleVT().SimpleTy) {
16442 default: return std::make_pair(0, false);
16446 if (!Subtarget->hasAVX2())
16448 if (!Subtarget->hasAVX())
16449 return std::make_pair(0, false);
16454 if (!Subtarget->hasSSE2())
16455 return std::make_pair(0, false);
16458 // SSE2 has only a small subset of the operations.
16459 bool hasUnsigned = Subtarget->hasSSE41() ||
16460 (Subtarget->hasSSE2() && VT == MVT::v16i8);
16461 bool hasSigned = Subtarget->hasSSE41() ||
16462 (Subtarget->hasSSE2() && VT == MVT::v8i16);
16464 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
16467 // Check for x CC y ? x : y.
16468 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
16469 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
16474 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
16477 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
16480 Opc = hasSigned ? X86ISD::SMIN : 0; break;
16483 Opc = hasSigned ? X86ISD::SMAX : 0; break;
16485 // Check for x CC y ? y : x -- a min/max with reversed arms.
16486 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
16487 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
16492 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
16495 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
16498 Opc = hasSigned ? X86ISD::SMAX : 0; break;
16501 Opc = hasSigned ? X86ISD::SMIN : 0; break;
16505 return std::make_pair(Opc, NeedSplit);
16508 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
16510 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
16511 TargetLowering::DAGCombinerInfo &DCI,
16512 const X86Subtarget *Subtarget) {
16514 SDValue Cond = N->getOperand(0);
16515 // Get the LHS/RHS of the select.
16516 SDValue LHS = N->getOperand(1);
16517 SDValue RHS = N->getOperand(2);
16518 EVT VT = LHS.getValueType();
16519 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16521 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
16522 // instructions match the semantics of the common C idiom x<y?x:y but not
16523 // x<=y?x:y, because of how they handle negative zero (which can be
16524 // ignored in unsafe-math mode).
16525 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
16526 VT != MVT::f80 && TLI.isTypeLegal(VT) &&
16527 (Subtarget->hasSSE2() ||
16528 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
16529 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
16531 unsigned Opcode = 0;
16532 // Check for x CC y ? x : y.
16533 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
16534 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
16538 // Converting this to a min would handle NaNs incorrectly, and swapping
16539 // the operands would cause it to handle comparisons between positive
16540 // and negative zero incorrectly.
16541 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
16542 if (!DAG.getTarget().Options.UnsafeFPMath &&
16543 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
16545 std::swap(LHS, RHS);
16547 Opcode = X86ISD::FMIN;
16550 // Converting this to a min would handle comparisons between positive
16551 // and negative zero incorrectly.
16552 if (!DAG.getTarget().Options.UnsafeFPMath &&
16553 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
16555 Opcode = X86ISD::FMIN;
16558 // Converting this to a min would handle both negative zeros and NaNs
16559 // incorrectly, but we can swap the operands to fix both.
16560 std::swap(LHS, RHS);
16564 Opcode = X86ISD::FMIN;
16568 // Converting this to a max would handle comparisons between positive
16569 // and negative zero incorrectly.
16570 if (!DAG.getTarget().Options.UnsafeFPMath &&
16571 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
16573 Opcode = X86ISD::FMAX;
16576 // Converting this to a max would handle NaNs incorrectly, and swapping
16577 // the operands would cause it to handle comparisons between positive
16578 // and negative zero incorrectly.
16579 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
16580 if (!DAG.getTarget().Options.UnsafeFPMath &&
16581 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
16583 std::swap(LHS, RHS);
16585 Opcode = X86ISD::FMAX;
16588 // Converting this to a max would handle both negative zeros and NaNs
16589 // incorrectly, but we can swap the operands to fix both.
16590 std::swap(LHS, RHS);
16594 Opcode = X86ISD::FMAX;
16597 // Check for x CC y ? y : x -- a min/max with reversed arms.
16598 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
16599 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
16603 // Converting this to a min would handle comparisons between positive
16604 // and negative zero incorrectly, and swapping the operands would
16605 // cause it to handle NaNs incorrectly.
16606 if (!DAG.getTarget().Options.UnsafeFPMath &&
16607 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
16608 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
16610 std::swap(LHS, RHS);
16612 Opcode = X86ISD::FMIN;
16615 // Converting this to a min would handle NaNs incorrectly.
16616 if (!DAG.getTarget().Options.UnsafeFPMath &&
16617 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
16619 Opcode = X86ISD::FMIN;
16622 // Converting this to a min would handle both negative zeros and NaNs
16623 // incorrectly, but we can swap the operands to fix both.
16624 std::swap(LHS, RHS);
16628 Opcode = X86ISD::FMIN;
16632 // Converting this to a max would handle NaNs incorrectly.
16633 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
16635 Opcode = X86ISD::FMAX;
16638 // Converting this to a max would handle comparisons between positive
16639 // and negative zero incorrectly, and swapping the operands would
16640 // cause it to handle NaNs incorrectly.
16641 if (!DAG.getTarget().Options.UnsafeFPMath &&
16642 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
16643 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
16645 std::swap(LHS, RHS);
16647 Opcode = X86ISD::FMAX;
16650 // Converting this to a max would handle both negative zeros and NaNs
16651 // incorrectly, but we can swap the operands to fix both.
16652 std::swap(LHS, RHS);
16656 Opcode = X86ISD::FMAX;
16662 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
16665 if (Subtarget->hasAVX512() && VT.isVector() &&
16666 Cond.getValueType().getVectorElementType() == MVT::i1) {
16667 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
16668 // lowering on AVX-512. In this case we convert it to
16669 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
16670 // The same situation for all 128 and 256-bit vectors of i8 and i16
16671 EVT OpVT = LHS.getValueType();
16672 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
16673 (OpVT.getVectorElementType() == MVT::i8 ||
16674 OpVT.getVectorElementType() == MVT::i16)) {
16675 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
16676 DCI.AddToWorklist(Cond.getNode());
16677 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
16680 // If this is a select between two integer constants, try to do some
16682 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
16683 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
16684 // Don't do this for crazy integer types.
16685 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
16686 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
16687 // so that TrueC (the true value) is larger than FalseC.
16688 bool NeedsCondInvert = false;
16690 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
16691 // Efficiently invertible.
16692 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
16693 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
16694 isa<ConstantSDNode>(Cond.getOperand(1))))) {
16695 NeedsCondInvert = true;
16696 std::swap(TrueC, FalseC);
16699 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
16700 if (FalseC->getAPIntValue() == 0 &&
16701 TrueC->getAPIntValue().isPowerOf2()) {
16702 if (NeedsCondInvert) // Invert the condition if needed.
16703 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
16704 DAG.getConstant(1, Cond.getValueType()));
16706 // Zero extend the condition if needed.
16707 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
16709 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
16710 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
16711 DAG.getConstant(ShAmt, MVT::i8));
16714 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
16715 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
16716 if (NeedsCondInvert) // Invert the condition if needed.
16717 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
16718 DAG.getConstant(1, Cond.getValueType()));
16720 // Zero extend the condition if needed.
16721 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
16722 FalseC->getValueType(0), Cond);
16723 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
16724 SDValue(FalseC, 0));
16727 // Optimize cases that will turn into an LEA instruction. This requires
16728 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
16729 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
16730 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
16731 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
16733 bool isFastMultiplier = false;
16735 switch ((unsigned char)Diff) {
16737 case 1: // result = add base, cond
16738 case 2: // result = lea base( , cond*2)
16739 case 3: // result = lea base(cond, cond*2)
16740 case 4: // result = lea base( , cond*4)
16741 case 5: // result = lea base(cond, cond*4)
16742 case 8: // result = lea base( , cond*8)
16743 case 9: // result = lea base(cond, cond*8)
16744 isFastMultiplier = true;
16749 if (isFastMultiplier) {
16750 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
16751 if (NeedsCondInvert) // Invert the condition if needed.
16752 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
16753 DAG.getConstant(1, Cond.getValueType()));
16755 // Zero extend the condition if needed.
16756 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
16758 // Scale the condition by the difference.
16760 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
16761 DAG.getConstant(Diff, Cond.getValueType()));
16763 // Add the base if non-zero.
16764 if (FalseC->getAPIntValue() != 0)
16765 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
16766 SDValue(FalseC, 0));
16773 // Canonicalize max and min:
16774 // (x > y) ? x : y -> (x >= y) ? x : y
16775 // (x < y) ? x : y -> (x <= y) ? x : y
16776 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
16777 // the need for an extra compare
16778 // against zero. e.g.
16779 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
16781 // testl %edi, %edi
16783 // cmovgl %edi, %eax
16787 // cmovsl %eax, %edi
16788 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
16789 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
16790 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
16791 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
16796 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
16797 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
16798 Cond.getOperand(0), Cond.getOperand(1), NewCC);
16799 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
16804 // Early exit check
16805 if (!TLI.isTypeLegal(VT))
16808 // Match VSELECTs into subs with unsigned saturation.
16809 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
16810 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
16811 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
16812 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
16813 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
16815 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
16816 // left side invert the predicate to simplify logic below.
16818 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
16820 CC = ISD::getSetCCInverse(CC, true);
16821 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
16825 if (Other.getNode() && Other->getNumOperands() == 2 &&
16826 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
16827 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
16828 SDValue CondRHS = Cond->getOperand(1);
16830 // Look for a general sub with unsigned saturation first.
16831 // x >= y ? x-y : 0 --> subus x, y
16832 // x > y ? x-y : 0 --> subus x, y
16833 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
16834 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
16835 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
16837 // If the RHS is a constant we have to reverse the const canonicalization.
16838 // x > C-1 ? x+-C : 0 --> subus x, C
16839 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
16840 isSplatVector(CondRHS.getNode()) && isSplatVector(OpRHS.getNode())) {
16841 APInt A = cast<ConstantSDNode>(OpRHS.getOperand(0))->getAPIntValue();
16842 if (CondRHS.getConstantOperandVal(0) == -A-1)
16843 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS,
16844 DAG.getConstant(-A, VT));
16847 // Another special case: If C was a sign bit, the sub has been
16848 // canonicalized into a xor.
16849 // FIXME: Would it be better to use ComputeMaskedBits to determine whether
16850 // it's safe to decanonicalize the xor?
16851 // x s< 0 ? x^C : 0 --> subus x, C
16852 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
16853 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
16854 isSplatVector(OpRHS.getNode())) {
16855 APInt A = cast<ConstantSDNode>(OpRHS.getOperand(0))->getAPIntValue();
16857 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
16862 // Try to match a min/max vector operation.
16863 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
16864 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
16865 unsigned Opc = ret.first;
16866 bool NeedSplit = ret.second;
16868 if (Opc && NeedSplit) {
16869 unsigned NumElems = VT.getVectorNumElements();
16870 // Extract the LHS vectors
16871 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
16872 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
16874 // Extract the RHS vectors
16875 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
16876 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
16878 // Create min/max for each subvector
16879 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
16880 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
16882 // Merge the result
16883 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
16885 return DAG.getNode(Opc, DL, VT, LHS, RHS);
16888 // Simplify vector selection if the selector will be produced by CMPP*/PCMP*.
16889 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
16890 // Check if SETCC has already been promoted
16891 TLI.getSetCCResultType(*DAG.getContext(), VT) == Cond.getValueType()) {
16893 assert(Cond.getValueType().isVector() &&
16894 "vector select expects a vector selector!");
16896 EVT IntVT = Cond.getValueType();
16897 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
16898 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
16900 if (!TValIsAllOnes && !FValIsAllZeros) {
16901 // Try invert the condition if true value is not all 1s and false value
16903 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
16904 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
16906 if (TValIsAllZeros || FValIsAllOnes) {
16907 SDValue CC = Cond.getOperand(2);
16908 ISD::CondCode NewCC =
16909 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
16910 Cond.getOperand(0).getValueType().isInteger());
16911 Cond = DAG.getSetCC(DL, IntVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
16912 std::swap(LHS, RHS);
16913 TValIsAllOnes = FValIsAllOnes;
16914 FValIsAllZeros = TValIsAllZeros;
16918 if (TValIsAllOnes || FValIsAllZeros) {
16921 if (TValIsAllOnes && FValIsAllZeros)
16923 else if (TValIsAllOnes)
16924 Ret = DAG.getNode(ISD::OR, DL, IntVT, Cond,
16925 DAG.getNode(ISD::BITCAST, DL, IntVT, RHS));
16926 else if (FValIsAllZeros)
16927 Ret = DAG.getNode(ISD::AND, DL, IntVT, Cond,
16928 DAG.getNode(ISD::BITCAST, DL, IntVT, LHS));
16930 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
16934 // If we know that this node is legal then we know that it is going to be
16935 // matched by one of the SSE/AVX BLEND instructions. These instructions only
16936 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
16937 // to simplify previous instructions.
16938 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
16939 !DCI.isBeforeLegalize() && TLI.isOperationLegal(ISD::VSELECT, VT)) {
16940 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
16942 // Don't optimize vector selects that map to mask-registers.
16946 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
16947 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
16949 APInt KnownZero, KnownOne;
16950 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
16951 DCI.isBeforeLegalizeOps());
16952 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
16953 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO))
16954 DCI.CommitTargetLoweringOpt(TLO);
16960 // Check whether a boolean test is testing a boolean value generated by
16961 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
16964 // Simplify the following patterns:
16965 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
16966 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
16967 // to (Op EFLAGS Cond)
16969 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
16970 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
16971 // to (Op EFLAGS !Cond)
16973 // where Op could be BRCOND or CMOV.
16975 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
16976 // Quit if not CMP and SUB with its value result used.
16977 if (Cmp.getOpcode() != X86ISD::CMP &&
16978 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
16981 // Quit if not used as a boolean value.
16982 if (CC != X86::COND_E && CC != X86::COND_NE)
16985 // Check CMP operands. One of them should be 0 or 1 and the other should be
16986 // an SetCC or extended from it.
16987 SDValue Op1 = Cmp.getOperand(0);
16988 SDValue Op2 = Cmp.getOperand(1);
16991 const ConstantSDNode* C = 0;
16992 bool needOppositeCond = (CC == X86::COND_E);
16993 bool checkAgainstTrue = false; // Is it a comparison against 1?
16995 if ((C = dyn_cast<ConstantSDNode>(Op1)))
16997 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
16999 else // Quit if all operands are not constants.
17002 if (C->getZExtValue() == 1) {
17003 needOppositeCond = !needOppositeCond;
17004 checkAgainstTrue = true;
17005 } else if (C->getZExtValue() != 0)
17006 // Quit if the constant is neither 0 or 1.
17009 bool truncatedToBoolWithAnd = false;
17010 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
17011 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
17012 SetCC.getOpcode() == ISD::TRUNCATE ||
17013 SetCC.getOpcode() == ISD::AND) {
17014 if (SetCC.getOpcode() == ISD::AND) {
17016 ConstantSDNode *CS;
17017 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
17018 CS->getZExtValue() == 1)
17020 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
17021 CS->getZExtValue() == 1)
17025 SetCC = SetCC.getOperand(OpIdx);
17026 truncatedToBoolWithAnd = true;
17028 SetCC = SetCC.getOperand(0);
17031 switch (SetCC.getOpcode()) {
17032 case X86ISD::SETCC_CARRY:
17033 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
17034 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
17035 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
17036 // truncated to i1 using 'and'.
17037 if (checkAgainstTrue && !truncatedToBoolWithAnd)
17039 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
17040 "Invalid use of SETCC_CARRY!");
17042 case X86ISD::SETCC:
17043 // Set the condition code or opposite one if necessary.
17044 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
17045 if (needOppositeCond)
17046 CC = X86::GetOppositeBranchCondition(CC);
17047 return SetCC.getOperand(1);
17048 case X86ISD::CMOV: {
17049 // Check whether false/true value has canonical one, i.e. 0 or 1.
17050 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
17051 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
17052 // Quit if true value is not a constant.
17055 // Quit if false value is not a constant.
17057 SDValue Op = SetCC.getOperand(0);
17058 // Skip 'zext' or 'trunc' node.
17059 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
17060 Op.getOpcode() == ISD::TRUNCATE)
17061 Op = Op.getOperand(0);
17062 // A special case for rdrand/rdseed, where 0 is set if false cond is
17064 if ((Op.getOpcode() != X86ISD::RDRAND &&
17065 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
17068 // Quit if false value is not the constant 0 or 1.
17069 bool FValIsFalse = true;
17070 if (FVal && FVal->getZExtValue() != 0) {
17071 if (FVal->getZExtValue() != 1)
17073 // If FVal is 1, opposite cond is needed.
17074 needOppositeCond = !needOppositeCond;
17075 FValIsFalse = false;
17077 // Quit if TVal is not the constant opposite of FVal.
17078 if (FValIsFalse && TVal->getZExtValue() != 1)
17080 if (!FValIsFalse && TVal->getZExtValue() != 0)
17082 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
17083 if (needOppositeCond)
17084 CC = X86::GetOppositeBranchCondition(CC);
17085 return SetCC.getOperand(3);
17092 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
17093 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
17094 TargetLowering::DAGCombinerInfo &DCI,
17095 const X86Subtarget *Subtarget) {
17098 // If the flag operand isn't dead, don't touch this CMOV.
17099 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
17102 SDValue FalseOp = N->getOperand(0);
17103 SDValue TrueOp = N->getOperand(1);
17104 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
17105 SDValue Cond = N->getOperand(3);
17107 if (CC == X86::COND_E || CC == X86::COND_NE) {
17108 switch (Cond.getOpcode()) {
17112 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
17113 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
17114 return (CC == X86::COND_E) ? FalseOp : TrueOp;
17120 Flags = checkBoolTestSetCCCombine(Cond, CC);
17121 if (Flags.getNode() &&
17122 // Extra check as FCMOV only supports a subset of X86 cond.
17123 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
17124 SDValue Ops[] = { FalseOp, TrueOp,
17125 DAG.getConstant(CC, MVT::i8), Flags };
17126 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(),
17127 Ops, array_lengthof(Ops));
17130 // If this is a select between two integer constants, try to do some
17131 // optimizations. Note that the operands are ordered the opposite of SELECT
17133 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
17134 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
17135 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
17136 // larger than FalseC (the false value).
17137 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
17138 CC = X86::GetOppositeBranchCondition(CC);
17139 std::swap(TrueC, FalseC);
17140 std::swap(TrueOp, FalseOp);
17143 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
17144 // This is efficient for any integer data type (including i8/i16) and
17146 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
17147 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
17148 DAG.getConstant(CC, MVT::i8), Cond);
17150 // Zero extend the condition if needed.
17151 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
17153 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
17154 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
17155 DAG.getConstant(ShAmt, MVT::i8));
17156 if (N->getNumValues() == 2) // Dead flag value?
17157 return DCI.CombineTo(N, Cond, SDValue());
17161 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
17162 // for any integer data type, including i8/i16.
17163 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
17164 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
17165 DAG.getConstant(CC, MVT::i8), Cond);
17167 // Zero extend the condition if needed.
17168 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
17169 FalseC->getValueType(0), Cond);
17170 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
17171 SDValue(FalseC, 0));
17173 if (N->getNumValues() == 2) // Dead flag value?
17174 return DCI.CombineTo(N, Cond, SDValue());
17178 // Optimize cases that will turn into an LEA instruction. This requires
17179 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
17180 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
17181 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
17182 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
17184 bool isFastMultiplier = false;
17186 switch ((unsigned char)Diff) {
17188 case 1: // result = add base, cond
17189 case 2: // result = lea base( , cond*2)
17190 case 3: // result = lea base(cond, cond*2)
17191 case 4: // result = lea base( , cond*4)
17192 case 5: // result = lea base(cond, cond*4)
17193 case 8: // result = lea base( , cond*8)
17194 case 9: // result = lea base(cond, cond*8)
17195 isFastMultiplier = true;
17200 if (isFastMultiplier) {
17201 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
17202 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
17203 DAG.getConstant(CC, MVT::i8), Cond);
17204 // Zero extend the condition if needed.
17205 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
17207 // Scale the condition by the difference.
17209 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
17210 DAG.getConstant(Diff, Cond.getValueType()));
17212 // Add the base if non-zero.
17213 if (FalseC->getAPIntValue() != 0)
17214 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
17215 SDValue(FalseC, 0));
17216 if (N->getNumValues() == 2) // Dead flag value?
17217 return DCI.CombineTo(N, Cond, SDValue());
17224 // Handle these cases:
17225 // (select (x != c), e, c) -> select (x != c), e, x),
17226 // (select (x == c), c, e) -> select (x == c), x, e)
17227 // where the c is an integer constant, and the "select" is the combination
17228 // of CMOV and CMP.
17230 // The rationale for this change is that the conditional-move from a constant
17231 // needs two instructions, however, conditional-move from a register needs
17232 // only one instruction.
17234 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
17235 // some instruction-combining opportunities. This opt needs to be
17236 // postponed as late as possible.
17238 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
17239 // the DCI.xxxx conditions are provided to postpone the optimization as
17240 // late as possible.
17242 ConstantSDNode *CmpAgainst = 0;
17243 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
17244 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
17245 !isa<ConstantSDNode>(Cond.getOperand(0))) {
17247 if (CC == X86::COND_NE &&
17248 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
17249 CC = X86::GetOppositeBranchCondition(CC);
17250 std::swap(TrueOp, FalseOp);
17253 if (CC == X86::COND_E &&
17254 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
17255 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
17256 DAG.getConstant(CC, MVT::i8), Cond };
17257 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops,
17258 array_lengthof(Ops));
17266 /// PerformMulCombine - Optimize a single multiply with constant into two
17267 /// in order to implement it with two cheaper instructions, e.g.
17268 /// LEA + SHL, LEA + LEA.
17269 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
17270 TargetLowering::DAGCombinerInfo &DCI) {
17271 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
17274 EVT VT = N->getValueType(0);
17275 if (VT != MVT::i64)
17278 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
17281 uint64_t MulAmt = C->getZExtValue();
17282 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
17285 uint64_t MulAmt1 = 0;
17286 uint64_t MulAmt2 = 0;
17287 if ((MulAmt % 9) == 0) {
17289 MulAmt2 = MulAmt / 9;
17290 } else if ((MulAmt % 5) == 0) {
17292 MulAmt2 = MulAmt / 5;
17293 } else if ((MulAmt % 3) == 0) {
17295 MulAmt2 = MulAmt / 3;
17298 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
17301 if (isPowerOf2_64(MulAmt2) &&
17302 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
17303 // If second multiplifer is pow2, issue it first. We want the multiply by
17304 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
17306 std::swap(MulAmt1, MulAmt2);
17309 if (isPowerOf2_64(MulAmt1))
17310 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
17311 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
17313 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
17314 DAG.getConstant(MulAmt1, VT));
17316 if (isPowerOf2_64(MulAmt2))
17317 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
17318 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
17320 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
17321 DAG.getConstant(MulAmt2, VT));
17323 // Do not add new nodes to DAG combiner worklist.
17324 DCI.CombineTo(N, NewMul, false);
17329 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
17330 SDValue N0 = N->getOperand(0);
17331 SDValue N1 = N->getOperand(1);
17332 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
17333 EVT VT = N0.getValueType();
17335 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
17336 // since the result of setcc_c is all zero's or all ones.
17337 if (VT.isInteger() && !VT.isVector() &&
17338 N1C && N0.getOpcode() == ISD::AND &&
17339 N0.getOperand(1).getOpcode() == ISD::Constant) {
17340 SDValue N00 = N0.getOperand(0);
17341 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
17342 ((N00.getOpcode() == ISD::ANY_EXTEND ||
17343 N00.getOpcode() == ISD::ZERO_EXTEND) &&
17344 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
17345 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
17346 APInt ShAmt = N1C->getAPIntValue();
17347 Mask = Mask.shl(ShAmt);
17349 return DAG.getNode(ISD::AND, SDLoc(N), VT,
17350 N00, DAG.getConstant(Mask, VT));
17354 // Hardware support for vector shifts is sparse which makes us scalarize the
17355 // vector operations in many cases. Also, on sandybridge ADD is faster than
17357 // (shl V, 1) -> add V,V
17358 if (isSplatVector(N1.getNode())) {
17359 assert(N0.getValueType().isVector() && "Invalid vector shift type");
17360 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1->getOperand(0));
17361 // We shift all of the values by one. In many cases we do not have
17362 // hardware support for this operation. This is better expressed as an ADD
17364 if (N1C && (1 == N1C->getZExtValue())) {
17365 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
17372 /// \brief Returns a vector of 0s if the node in input is a vector logical
17373 /// shift by a constant amount which is known to be bigger than or equal
17374 /// to the vector element size in bits.
17375 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
17376 const X86Subtarget *Subtarget) {
17377 EVT VT = N->getValueType(0);
17379 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
17380 (!Subtarget->hasInt256() ||
17381 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
17384 SDValue Amt = N->getOperand(1);
17386 if (isSplatVector(Amt.getNode())) {
17387 SDValue SclrAmt = Amt->getOperand(0);
17388 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
17389 APInt ShiftAmt = C->getAPIntValue();
17390 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
17392 // SSE2/AVX2 logical shifts always return a vector of 0s
17393 // if the shift amount is bigger than or equal to
17394 // the element size. The constant shift amount will be
17395 // encoded as a 8-bit immediate.
17396 if (ShiftAmt.trunc(8).uge(MaxAmount))
17397 return getZeroVector(VT, Subtarget, DAG, DL);
17404 /// PerformShiftCombine - Combine shifts.
17405 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
17406 TargetLowering::DAGCombinerInfo &DCI,
17407 const X86Subtarget *Subtarget) {
17408 if (N->getOpcode() == ISD::SHL) {
17409 SDValue V = PerformSHLCombine(N, DAG);
17410 if (V.getNode()) return V;
17413 if (N->getOpcode() != ISD::SRA) {
17414 // Try to fold this logical shift into a zero vector.
17415 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
17416 if (V.getNode()) return V;
17422 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
17423 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
17424 // and friends. Likewise for OR -> CMPNEQSS.
17425 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
17426 TargetLowering::DAGCombinerInfo &DCI,
17427 const X86Subtarget *Subtarget) {
17430 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
17431 // we're requiring SSE2 for both.
17432 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
17433 SDValue N0 = N->getOperand(0);
17434 SDValue N1 = N->getOperand(1);
17435 SDValue CMP0 = N0->getOperand(1);
17436 SDValue CMP1 = N1->getOperand(1);
17439 // The SETCCs should both refer to the same CMP.
17440 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
17443 SDValue CMP00 = CMP0->getOperand(0);
17444 SDValue CMP01 = CMP0->getOperand(1);
17445 EVT VT = CMP00.getValueType();
17447 if (VT == MVT::f32 || VT == MVT::f64) {
17448 bool ExpectingFlags = false;
17449 // Check for any users that want flags:
17450 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
17451 !ExpectingFlags && UI != UE; ++UI)
17452 switch (UI->getOpcode()) {
17457 ExpectingFlags = true;
17459 case ISD::CopyToReg:
17460 case ISD::SIGN_EXTEND:
17461 case ISD::ZERO_EXTEND:
17462 case ISD::ANY_EXTEND:
17466 if (!ExpectingFlags) {
17467 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
17468 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
17470 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
17471 X86::CondCode tmp = cc0;
17476 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
17477 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
17478 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
17479 X86ISD::NodeType NTOperator = is64BitFP ?
17480 X86ISD::FSETCCsd : X86ISD::FSETCCss;
17481 // FIXME: need symbolic constants for these magic numbers.
17482 // See X86ATTInstPrinter.cpp:printSSECC().
17483 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
17484 SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, MVT::f32, CMP00, CMP01,
17485 DAG.getConstant(x86cc, MVT::i8));
17486 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32,
17488 SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI,
17489 DAG.getConstant(1, MVT::i32));
17490 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
17491 return OneBitOfTruth;
17499 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
17500 /// so it can be folded inside ANDNP.
17501 static bool CanFoldXORWithAllOnes(const SDNode *N) {
17502 EVT VT = N->getValueType(0);
17504 // Match direct AllOnes for 128 and 256-bit vectors
17505 if (ISD::isBuildVectorAllOnes(N))
17508 // Look through a bit convert.
17509 if (N->getOpcode() == ISD::BITCAST)
17510 N = N->getOperand(0).getNode();
17512 // Sometimes the operand may come from a insert_subvector building a 256-bit
17514 if (VT.is256BitVector() &&
17515 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
17516 SDValue V1 = N->getOperand(0);
17517 SDValue V2 = N->getOperand(1);
17519 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
17520 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
17521 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
17522 ISD::isBuildVectorAllOnes(V2.getNode()))
17529 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
17530 // register. In most cases we actually compare or select YMM-sized registers
17531 // and mixing the two types creates horrible code. This method optimizes
17532 // some of the transition sequences.
17533 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
17534 TargetLowering::DAGCombinerInfo &DCI,
17535 const X86Subtarget *Subtarget) {
17536 EVT VT = N->getValueType(0);
17537 if (!VT.is256BitVector())
17540 assert((N->getOpcode() == ISD::ANY_EXTEND ||
17541 N->getOpcode() == ISD::ZERO_EXTEND ||
17542 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
17544 SDValue Narrow = N->getOperand(0);
17545 EVT NarrowVT = Narrow->getValueType(0);
17546 if (!NarrowVT.is128BitVector())
17549 if (Narrow->getOpcode() != ISD::XOR &&
17550 Narrow->getOpcode() != ISD::AND &&
17551 Narrow->getOpcode() != ISD::OR)
17554 SDValue N0 = Narrow->getOperand(0);
17555 SDValue N1 = Narrow->getOperand(1);
17558 // The Left side has to be a trunc.
17559 if (N0.getOpcode() != ISD::TRUNCATE)
17562 // The type of the truncated inputs.
17563 EVT WideVT = N0->getOperand(0)->getValueType(0);
17567 // The right side has to be a 'trunc' or a constant vector.
17568 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
17569 bool RHSConst = (isSplatVector(N1.getNode()) &&
17570 isa<ConstantSDNode>(N1->getOperand(0)));
17571 if (!RHSTrunc && !RHSConst)
17574 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17576 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
17579 // Set N0 and N1 to hold the inputs to the new wide operation.
17580 N0 = N0->getOperand(0);
17582 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
17583 N1->getOperand(0));
17584 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
17585 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, &C[0], C.size());
17586 } else if (RHSTrunc) {
17587 N1 = N1->getOperand(0);
17590 // Generate the wide operation.
17591 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
17592 unsigned Opcode = N->getOpcode();
17594 case ISD::ANY_EXTEND:
17596 case ISD::ZERO_EXTEND: {
17597 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
17598 APInt Mask = APInt::getAllOnesValue(InBits);
17599 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
17600 return DAG.getNode(ISD::AND, DL, VT,
17601 Op, DAG.getConstant(Mask, VT));
17603 case ISD::SIGN_EXTEND:
17604 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
17605 Op, DAG.getValueType(NarrowVT));
17607 llvm_unreachable("Unexpected opcode");
17611 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
17612 TargetLowering::DAGCombinerInfo &DCI,
17613 const X86Subtarget *Subtarget) {
17614 EVT VT = N->getValueType(0);
17615 if (DCI.isBeforeLegalizeOps())
17618 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
17622 // Create BLSI, BLSR, and BZHI instructions
17623 // BLSI is X & (-X)
17624 // BLSR is X & (X-1)
17625 // BZHI is X & ((1 << Y) - 1)
17626 // BEXTR is ((X >> imm) & (2**size-1))
17627 if (VT == MVT::i32 || VT == MVT::i64) {
17628 SDValue N0 = N->getOperand(0);
17629 SDValue N1 = N->getOperand(1);
17632 if (Subtarget->hasBMI()) {
17633 // Check LHS for neg
17634 if (N0.getOpcode() == ISD::SUB && N0.getOperand(1) == N1 &&
17635 isZero(N0.getOperand(0)))
17636 return DAG.getNode(X86ISD::BLSI, DL, VT, N1);
17638 // Check RHS for neg
17639 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1) == N0 &&
17640 isZero(N1.getOperand(0)))
17641 return DAG.getNode(X86ISD::BLSI, DL, VT, N0);
17643 // Check LHS for X-1
17644 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
17645 isAllOnes(N0.getOperand(1)))
17646 return DAG.getNode(X86ISD::BLSR, DL, VT, N1);
17648 // Check RHS for X-1
17649 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
17650 isAllOnes(N1.getOperand(1)))
17651 return DAG.getNode(X86ISD::BLSR, DL, VT, N0);
17654 if (Subtarget->hasBMI2()) {
17655 // Check for (and (add (shl 1, Y), -1), X)
17656 if (N0.getOpcode() == ISD::ADD && isAllOnes(N0.getOperand(1))) {
17657 SDValue N00 = N0.getOperand(0);
17658 if (N00.getOpcode() == ISD::SHL) {
17659 SDValue N001 = N00.getOperand(1);
17660 assert(N001.getValueType() == MVT::i8 && "unexpected type");
17661 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N00.getOperand(0));
17662 if (C && C->getZExtValue() == 1)
17663 return DAG.getNode(X86ISD::BZHI, DL, VT, N1, N001);
17667 // Check for (and X, (add (shl 1, Y), -1))
17668 if (N1.getOpcode() == ISD::ADD && isAllOnes(N1.getOperand(1))) {
17669 SDValue N10 = N1.getOperand(0);
17670 if (N10.getOpcode() == ISD::SHL) {
17671 SDValue N101 = N10.getOperand(1);
17672 assert(N101.getValueType() == MVT::i8 && "unexpected type");
17673 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N10.getOperand(0));
17674 if (C && C->getZExtValue() == 1)
17675 return DAG.getNode(X86ISD::BZHI, DL, VT, N0, N101);
17680 // Check for BEXTR.
17681 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
17682 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
17683 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
17684 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
17685 if (MaskNode && ShiftNode) {
17686 uint64_t Mask = MaskNode->getZExtValue();
17687 uint64_t Shift = ShiftNode->getZExtValue();
17688 if (isMask_64(Mask)) {
17689 uint64_t MaskSize = CountPopulation_64(Mask);
17690 if (Shift + MaskSize <= VT.getSizeInBits())
17691 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
17692 DAG.getConstant(Shift | (MaskSize << 8), VT));
17700 // Want to form ANDNP nodes:
17701 // 1) In the hopes of then easily combining them with OR and AND nodes
17702 // to form PBLEND/PSIGN.
17703 // 2) To match ANDN packed intrinsics
17704 if (VT != MVT::v2i64 && VT != MVT::v4i64)
17707 SDValue N0 = N->getOperand(0);
17708 SDValue N1 = N->getOperand(1);
17711 // Check LHS for vnot
17712 if (N0.getOpcode() == ISD::XOR &&
17713 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
17714 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
17715 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
17717 // Check RHS for vnot
17718 if (N1.getOpcode() == ISD::XOR &&
17719 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
17720 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
17721 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
17726 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
17727 TargetLowering::DAGCombinerInfo &DCI,
17728 const X86Subtarget *Subtarget) {
17729 EVT VT = N->getValueType(0);
17730 if (DCI.isBeforeLegalizeOps())
17733 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
17737 SDValue N0 = N->getOperand(0);
17738 SDValue N1 = N->getOperand(1);
17740 // look for psign/blend
17741 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
17742 if (!Subtarget->hasSSSE3() ||
17743 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
17746 // Canonicalize pandn to RHS
17747 if (N0.getOpcode() == X86ISD::ANDNP)
17749 // or (and (m, y), (pandn m, x))
17750 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
17751 SDValue Mask = N1.getOperand(0);
17752 SDValue X = N1.getOperand(1);
17754 if (N0.getOperand(0) == Mask)
17755 Y = N0.getOperand(1);
17756 if (N0.getOperand(1) == Mask)
17757 Y = N0.getOperand(0);
17759 // Check to see if the mask appeared in both the AND and ANDNP and
17763 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
17764 // Look through mask bitcast.
17765 if (Mask.getOpcode() == ISD::BITCAST)
17766 Mask = Mask.getOperand(0);
17767 if (X.getOpcode() == ISD::BITCAST)
17768 X = X.getOperand(0);
17769 if (Y.getOpcode() == ISD::BITCAST)
17770 Y = Y.getOperand(0);
17772 EVT MaskVT = Mask.getValueType();
17774 // Validate that the Mask operand is a vector sra node.
17775 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
17776 // there is no psrai.b
17777 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
17778 unsigned SraAmt = ~0;
17779 if (Mask.getOpcode() == ISD::SRA) {
17780 SDValue Amt = Mask.getOperand(1);
17781 if (isSplatVector(Amt.getNode())) {
17782 SDValue SclrAmt = Amt->getOperand(0);
17783 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt))
17784 SraAmt = C->getZExtValue();
17786 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
17787 SDValue SraC = Mask.getOperand(1);
17788 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
17790 if ((SraAmt + 1) != EltBits)
17795 // Now we know we at least have a plendvb with the mask val. See if
17796 // we can form a psignb/w/d.
17797 // psign = x.type == y.type == mask.type && y = sub(0, x);
17798 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
17799 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
17800 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
17801 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
17802 "Unsupported VT for PSIGN");
17803 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
17804 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
17806 // PBLENDVB only available on SSE 4.1
17807 if (!Subtarget->hasSSE41())
17810 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
17812 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
17813 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
17814 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
17815 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
17816 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
17820 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
17823 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
17824 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
17826 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
17828 if (!N0.hasOneUse() || !N1.hasOneUse())
17831 SDValue ShAmt0 = N0.getOperand(1);
17832 if (ShAmt0.getValueType() != MVT::i8)
17834 SDValue ShAmt1 = N1.getOperand(1);
17835 if (ShAmt1.getValueType() != MVT::i8)
17837 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
17838 ShAmt0 = ShAmt0.getOperand(0);
17839 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
17840 ShAmt1 = ShAmt1.getOperand(0);
17843 unsigned Opc = X86ISD::SHLD;
17844 SDValue Op0 = N0.getOperand(0);
17845 SDValue Op1 = N1.getOperand(0);
17846 if (ShAmt0.getOpcode() == ISD::SUB) {
17847 Opc = X86ISD::SHRD;
17848 std::swap(Op0, Op1);
17849 std::swap(ShAmt0, ShAmt1);
17852 unsigned Bits = VT.getSizeInBits();
17853 if (ShAmt1.getOpcode() == ISD::SUB) {
17854 SDValue Sum = ShAmt1.getOperand(0);
17855 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
17856 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
17857 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
17858 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
17859 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
17860 return DAG.getNode(Opc, DL, VT,
17862 DAG.getNode(ISD::TRUNCATE, DL,
17865 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
17866 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
17868 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
17869 return DAG.getNode(Opc, DL, VT,
17870 N0.getOperand(0), N1.getOperand(0),
17871 DAG.getNode(ISD::TRUNCATE, DL,
17878 // Generate NEG and CMOV for integer abs.
17879 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
17880 EVT VT = N->getValueType(0);
17882 // Since X86 does not have CMOV for 8-bit integer, we don't convert
17883 // 8-bit integer abs to NEG and CMOV.
17884 if (VT.isInteger() && VT.getSizeInBits() == 8)
17887 SDValue N0 = N->getOperand(0);
17888 SDValue N1 = N->getOperand(1);
17891 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
17892 // and change it to SUB and CMOV.
17893 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
17894 N0.getOpcode() == ISD::ADD &&
17895 N0.getOperand(1) == N1 &&
17896 N1.getOpcode() == ISD::SRA &&
17897 N1.getOperand(0) == N0.getOperand(0))
17898 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
17899 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
17900 // Generate SUB & CMOV.
17901 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
17902 DAG.getConstant(0, VT), N0.getOperand(0));
17904 SDValue Ops[] = { N0.getOperand(0), Neg,
17905 DAG.getConstant(X86::COND_GE, MVT::i8),
17906 SDValue(Neg.getNode(), 1) };
17907 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue),
17908 Ops, array_lengthof(Ops));
17913 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
17914 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
17915 TargetLowering::DAGCombinerInfo &DCI,
17916 const X86Subtarget *Subtarget) {
17917 EVT VT = N->getValueType(0);
17918 if (DCI.isBeforeLegalizeOps())
17921 if (Subtarget->hasCMov()) {
17922 SDValue RV = performIntegerAbsCombine(N, DAG);
17927 // Try forming BMI if it is available.
17928 if (!Subtarget->hasBMI())
17931 if (VT != MVT::i32 && VT != MVT::i64)
17934 assert(Subtarget->hasBMI() && "Creating BLSMSK requires BMI instructions");
17936 // Create BLSMSK instructions by finding X ^ (X-1)
17937 SDValue N0 = N->getOperand(0);
17938 SDValue N1 = N->getOperand(1);
17941 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
17942 isAllOnes(N0.getOperand(1)))
17943 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N1);
17945 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
17946 isAllOnes(N1.getOperand(1)))
17947 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N0);
17952 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
17953 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
17954 TargetLowering::DAGCombinerInfo &DCI,
17955 const X86Subtarget *Subtarget) {
17956 LoadSDNode *Ld = cast<LoadSDNode>(N);
17957 EVT RegVT = Ld->getValueType(0);
17958 EVT MemVT = Ld->getMemoryVT();
17960 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17961 unsigned RegSz = RegVT.getSizeInBits();
17963 // On Sandybridge unaligned 256bit loads are inefficient.
17964 ISD::LoadExtType Ext = Ld->getExtensionType();
17965 unsigned Alignment = Ld->getAlignment();
17966 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
17967 if (RegVT.is256BitVector() && !Subtarget->hasInt256() &&
17968 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
17969 unsigned NumElems = RegVT.getVectorNumElements();
17973 SDValue Ptr = Ld->getBasePtr();
17974 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
17976 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
17978 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
17979 Ld->getPointerInfo(), Ld->isVolatile(),
17980 Ld->isNonTemporal(), Ld->isInvariant(),
17982 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
17983 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
17984 Ld->getPointerInfo(), Ld->isVolatile(),
17985 Ld->isNonTemporal(), Ld->isInvariant(),
17986 std::min(16U, Alignment));
17987 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
17989 Load2.getValue(1));
17991 SDValue NewVec = DAG.getUNDEF(RegVT);
17992 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
17993 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
17994 return DCI.CombineTo(N, NewVec, TF, true);
17997 // If this is a vector EXT Load then attempt to optimize it using a
17998 // shuffle. If SSSE3 is not available we may emit an illegal shuffle but the
17999 // expansion is still better than scalar code.
18000 // We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise we'll
18001 // emit a shuffle and a arithmetic shift.
18002 // TODO: It is possible to support ZExt by zeroing the undef values
18003 // during the shuffle phase or after the shuffle.
18004 if (RegVT.isVector() && RegVT.isInteger() && Subtarget->hasSSE2() &&
18005 (Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)) {
18006 assert(MemVT != RegVT && "Cannot extend to the same type");
18007 assert(MemVT.isVector() && "Must load a vector from memory");
18009 unsigned NumElems = RegVT.getVectorNumElements();
18010 unsigned MemSz = MemVT.getSizeInBits();
18011 assert(RegSz > MemSz && "Register size must be greater than the mem size");
18013 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256())
18016 // All sizes must be a power of two.
18017 if (!isPowerOf2_32(RegSz * MemSz * NumElems))
18020 // Attempt to load the original value using scalar loads.
18021 // Find the largest scalar type that divides the total loaded size.
18022 MVT SclrLoadTy = MVT::i8;
18023 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
18024 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
18025 MVT Tp = (MVT::SimpleValueType)tp;
18026 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
18031 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
18032 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
18034 SclrLoadTy = MVT::f64;
18036 // Calculate the number of scalar loads that we need to perform
18037 // in order to load our vector from memory.
18038 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
18039 if (Ext == ISD::SEXTLOAD && NumLoads > 1)
18042 unsigned loadRegZize = RegSz;
18043 if (Ext == ISD::SEXTLOAD && RegSz == 256)
18046 // Represent our vector as a sequence of elements which are the
18047 // largest scalar that we can load.
18048 EVT LoadUnitVecVT = EVT::getVectorVT(*DAG.getContext(), SclrLoadTy,
18049 loadRegZize/SclrLoadTy.getSizeInBits());
18051 // Represent the data using the same element type that is stored in
18052 // memory. In practice, we ''widen'' MemVT.
18054 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
18055 loadRegZize/MemVT.getScalarType().getSizeInBits());
18057 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
18058 "Invalid vector type");
18060 // We can't shuffle using an illegal type.
18061 if (!TLI.isTypeLegal(WideVecVT))
18064 SmallVector<SDValue, 8> Chains;
18065 SDValue Ptr = Ld->getBasePtr();
18066 SDValue Increment = DAG.getConstant(SclrLoadTy.getSizeInBits()/8,
18067 TLI.getPointerTy());
18068 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
18070 for (unsigned i = 0; i < NumLoads; ++i) {
18071 // Perform a single load.
18072 SDValue ScalarLoad = DAG.getLoad(SclrLoadTy, dl, Ld->getChain(),
18073 Ptr, Ld->getPointerInfo(),
18074 Ld->isVolatile(), Ld->isNonTemporal(),
18075 Ld->isInvariant(), Ld->getAlignment());
18076 Chains.push_back(ScalarLoad.getValue(1));
18077 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
18078 // another round of DAGCombining.
18080 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
18082 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
18083 ScalarLoad, DAG.getIntPtrConstant(i));
18085 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
18088 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
18091 // Bitcast the loaded value to a vector of the original element type, in
18092 // the size of the target vector type.
18093 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
18094 unsigned SizeRatio = RegSz/MemSz;
18096 if (Ext == ISD::SEXTLOAD) {
18097 // If we have SSE4.1 we can directly emit a VSEXT node.
18098 if (Subtarget->hasSSE41()) {
18099 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
18100 return DCI.CombineTo(N, Sext, TF, true);
18103 // Otherwise we'll shuffle the small elements in the high bits of the
18104 // larger type and perform an arithmetic shift. If the shift is not legal
18105 // it's better to scalarize.
18106 if (!TLI.isOperationLegalOrCustom(ISD::SRA, RegVT))
18109 // Redistribute the loaded elements into the different locations.
18110 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
18111 for (unsigned i = 0; i != NumElems; ++i)
18112 ShuffleVec[i*SizeRatio + SizeRatio-1] = i;
18114 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
18115 DAG.getUNDEF(WideVecVT),
18118 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
18120 // Build the arithmetic shift.
18121 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
18122 MemVT.getVectorElementType().getSizeInBits();
18123 Shuff = DAG.getNode(ISD::SRA, dl, RegVT, Shuff,
18124 DAG.getConstant(Amt, RegVT));
18126 return DCI.CombineTo(N, Shuff, TF, true);
18129 // Redistribute the loaded elements into the different locations.
18130 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
18131 for (unsigned i = 0; i != NumElems; ++i)
18132 ShuffleVec[i*SizeRatio] = i;
18134 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
18135 DAG.getUNDEF(WideVecVT),
18138 // Bitcast to the requested type.
18139 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
18140 // Replace the original load with the new sequence
18141 // and return the new chain.
18142 return DCI.CombineTo(N, Shuff, TF, true);
18148 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
18149 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
18150 const X86Subtarget *Subtarget) {
18151 StoreSDNode *St = cast<StoreSDNode>(N);
18152 EVT VT = St->getValue().getValueType();
18153 EVT StVT = St->getMemoryVT();
18155 SDValue StoredVal = St->getOperand(1);
18156 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18158 // If we are saving a concatenation of two XMM registers, perform two stores.
18159 // On Sandy Bridge, 256-bit memory operations are executed by two
18160 // 128-bit ports. However, on Haswell it is better to issue a single 256-bit
18161 // memory operation.
18162 unsigned Alignment = St->getAlignment();
18163 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
18164 if (VT.is256BitVector() && !Subtarget->hasInt256() &&
18165 StVT == VT && !IsAligned) {
18166 unsigned NumElems = VT.getVectorNumElements();
18170 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
18171 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
18173 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
18174 SDValue Ptr0 = St->getBasePtr();
18175 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
18177 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
18178 St->getPointerInfo(), St->isVolatile(),
18179 St->isNonTemporal(), Alignment);
18180 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
18181 St->getPointerInfo(), St->isVolatile(),
18182 St->isNonTemporal(),
18183 std::min(16U, Alignment));
18184 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
18187 // Optimize trunc store (of multiple scalars) to shuffle and store.
18188 // First, pack all of the elements in one place. Next, store to memory
18189 // in fewer chunks.
18190 if (St->isTruncatingStore() && VT.isVector()) {
18191 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18192 unsigned NumElems = VT.getVectorNumElements();
18193 assert(StVT != VT && "Cannot truncate to the same type");
18194 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
18195 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
18197 // From, To sizes and ElemCount must be pow of two
18198 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
18199 // We are going to use the original vector elt for storing.
18200 // Accumulated smaller vector elements must be a multiple of the store size.
18201 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
18203 unsigned SizeRatio = FromSz / ToSz;
18205 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
18207 // Create a type on which we perform the shuffle
18208 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
18209 StVT.getScalarType(), NumElems*SizeRatio);
18211 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
18213 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
18214 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
18215 for (unsigned i = 0; i != NumElems; ++i)
18216 ShuffleVec[i] = i * SizeRatio;
18218 // Can't shuffle using an illegal type.
18219 if (!TLI.isTypeLegal(WideVecVT))
18222 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
18223 DAG.getUNDEF(WideVecVT),
18225 // At this point all of the data is stored at the bottom of the
18226 // register. We now need to save it to mem.
18228 // Find the largest store unit
18229 MVT StoreType = MVT::i8;
18230 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
18231 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
18232 MVT Tp = (MVT::SimpleValueType)tp;
18233 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
18237 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
18238 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
18239 (64 <= NumElems * ToSz))
18240 StoreType = MVT::f64;
18242 // Bitcast the original vector into a vector of store-size units
18243 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
18244 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
18245 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
18246 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
18247 SmallVector<SDValue, 8> Chains;
18248 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
18249 TLI.getPointerTy());
18250 SDValue Ptr = St->getBasePtr();
18252 // Perform one or more big stores into memory.
18253 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
18254 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
18255 StoreType, ShuffWide,
18256 DAG.getIntPtrConstant(i));
18257 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
18258 St->getPointerInfo(), St->isVolatile(),
18259 St->isNonTemporal(), St->getAlignment());
18260 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
18261 Chains.push_back(Ch);
18264 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
18268 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
18269 // the FP state in cases where an emms may be missing.
18270 // A preferable solution to the general problem is to figure out the right
18271 // places to insert EMMS. This qualifies as a quick hack.
18273 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
18274 if (VT.getSizeInBits() != 64)
18277 const Function *F = DAG.getMachineFunction().getFunction();
18278 bool NoImplicitFloatOps = F->getAttributes().
18279 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
18280 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
18281 && Subtarget->hasSSE2();
18282 if ((VT.isVector() ||
18283 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
18284 isa<LoadSDNode>(St->getValue()) &&
18285 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
18286 St->getChain().hasOneUse() && !St->isVolatile()) {
18287 SDNode* LdVal = St->getValue().getNode();
18288 LoadSDNode *Ld = 0;
18289 int TokenFactorIndex = -1;
18290 SmallVector<SDValue, 8> Ops;
18291 SDNode* ChainVal = St->getChain().getNode();
18292 // Must be a store of a load. We currently handle two cases: the load
18293 // is a direct child, and it's under an intervening TokenFactor. It is
18294 // possible to dig deeper under nested TokenFactors.
18295 if (ChainVal == LdVal)
18296 Ld = cast<LoadSDNode>(St->getChain());
18297 else if (St->getValue().hasOneUse() &&
18298 ChainVal->getOpcode() == ISD::TokenFactor) {
18299 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
18300 if (ChainVal->getOperand(i).getNode() == LdVal) {
18301 TokenFactorIndex = i;
18302 Ld = cast<LoadSDNode>(St->getValue());
18304 Ops.push_back(ChainVal->getOperand(i));
18308 if (!Ld || !ISD::isNormalLoad(Ld))
18311 // If this is not the MMX case, i.e. we are just turning i64 load/store
18312 // into f64 load/store, avoid the transformation if there are multiple
18313 // uses of the loaded value.
18314 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
18319 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
18320 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
18322 if (Subtarget->is64Bit() || F64IsLegal) {
18323 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
18324 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
18325 Ld->getPointerInfo(), Ld->isVolatile(),
18326 Ld->isNonTemporal(), Ld->isInvariant(),
18327 Ld->getAlignment());
18328 SDValue NewChain = NewLd.getValue(1);
18329 if (TokenFactorIndex != -1) {
18330 Ops.push_back(NewChain);
18331 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
18334 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
18335 St->getPointerInfo(),
18336 St->isVolatile(), St->isNonTemporal(),
18337 St->getAlignment());
18340 // Otherwise, lower to two pairs of 32-bit loads / stores.
18341 SDValue LoAddr = Ld->getBasePtr();
18342 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
18343 DAG.getConstant(4, MVT::i32));
18345 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
18346 Ld->getPointerInfo(),
18347 Ld->isVolatile(), Ld->isNonTemporal(),
18348 Ld->isInvariant(), Ld->getAlignment());
18349 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
18350 Ld->getPointerInfo().getWithOffset(4),
18351 Ld->isVolatile(), Ld->isNonTemporal(),
18353 MinAlign(Ld->getAlignment(), 4));
18355 SDValue NewChain = LoLd.getValue(1);
18356 if (TokenFactorIndex != -1) {
18357 Ops.push_back(LoLd);
18358 Ops.push_back(HiLd);
18359 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
18363 LoAddr = St->getBasePtr();
18364 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
18365 DAG.getConstant(4, MVT::i32));
18367 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
18368 St->getPointerInfo(),
18369 St->isVolatile(), St->isNonTemporal(),
18370 St->getAlignment());
18371 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
18372 St->getPointerInfo().getWithOffset(4),
18374 St->isNonTemporal(),
18375 MinAlign(St->getAlignment(), 4));
18376 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
18381 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
18382 /// and return the operands for the horizontal operation in LHS and RHS. A
18383 /// horizontal operation performs the binary operation on successive elements
18384 /// of its first operand, then on successive elements of its second operand,
18385 /// returning the resulting values in a vector. For example, if
18386 /// A = < float a0, float a1, float a2, float a3 >
18388 /// B = < float b0, float b1, float b2, float b3 >
18389 /// then the result of doing a horizontal operation on A and B is
18390 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
18391 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
18392 /// A horizontal-op B, for some already available A and B, and if so then LHS is
18393 /// set to A, RHS to B, and the routine returns 'true'.
18394 /// Note that the binary operation should have the property that if one of the
18395 /// operands is UNDEF then the result is UNDEF.
18396 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
18397 // Look for the following pattern: if
18398 // A = < float a0, float a1, float a2, float a3 >
18399 // B = < float b0, float b1, float b2, float b3 >
18401 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
18402 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
18403 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
18404 // which is A horizontal-op B.
18406 // At least one of the operands should be a vector shuffle.
18407 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
18408 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
18411 MVT VT = LHS.getSimpleValueType();
18413 assert((VT.is128BitVector() || VT.is256BitVector()) &&
18414 "Unsupported vector type for horizontal add/sub");
18416 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
18417 // operate independently on 128-bit lanes.
18418 unsigned NumElts = VT.getVectorNumElements();
18419 unsigned NumLanes = VT.getSizeInBits()/128;
18420 unsigned NumLaneElts = NumElts / NumLanes;
18421 assert((NumLaneElts % 2 == 0) &&
18422 "Vector type should have an even number of elements in each lane");
18423 unsigned HalfLaneElts = NumLaneElts/2;
18425 // View LHS in the form
18426 // LHS = VECTOR_SHUFFLE A, B, LMask
18427 // If LHS is not a shuffle then pretend it is the shuffle
18428 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
18429 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
18432 SmallVector<int, 16> LMask(NumElts);
18433 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
18434 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
18435 A = LHS.getOperand(0);
18436 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
18437 B = LHS.getOperand(1);
18438 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
18439 std::copy(Mask.begin(), Mask.end(), LMask.begin());
18441 if (LHS.getOpcode() != ISD::UNDEF)
18443 for (unsigned i = 0; i != NumElts; ++i)
18447 // Likewise, view RHS in the form
18448 // RHS = VECTOR_SHUFFLE C, D, RMask
18450 SmallVector<int, 16> RMask(NumElts);
18451 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
18452 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
18453 C = RHS.getOperand(0);
18454 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
18455 D = RHS.getOperand(1);
18456 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
18457 std::copy(Mask.begin(), Mask.end(), RMask.begin());
18459 if (RHS.getOpcode() != ISD::UNDEF)
18461 for (unsigned i = 0; i != NumElts; ++i)
18465 // Check that the shuffles are both shuffling the same vectors.
18466 if (!(A == C && B == D) && !(A == D && B == C))
18469 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
18470 if (!A.getNode() && !B.getNode())
18473 // If A and B occur in reverse order in RHS, then "swap" them (which means
18474 // rewriting the mask).
18476 CommuteVectorShuffleMask(RMask, NumElts);
18478 // At this point LHS and RHS are equivalent to
18479 // LHS = VECTOR_SHUFFLE A, B, LMask
18480 // RHS = VECTOR_SHUFFLE A, B, RMask
18481 // Check that the masks correspond to performing a horizontal operation.
18482 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
18483 for (unsigned i = 0; i != NumLaneElts; ++i) {
18484 int LIdx = LMask[i+l], RIdx = RMask[i+l];
18486 // Ignore any UNDEF components.
18487 if (LIdx < 0 || RIdx < 0 ||
18488 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
18489 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
18492 // Check that successive elements are being operated on. If not, this is
18493 // not a horizontal operation.
18494 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
18495 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
18496 if (!(LIdx == Index && RIdx == Index + 1) &&
18497 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
18502 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
18503 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
18507 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
18508 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
18509 const X86Subtarget *Subtarget) {
18510 EVT VT = N->getValueType(0);
18511 SDValue LHS = N->getOperand(0);
18512 SDValue RHS = N->getOperand(1);
18514 // Try to synthesize horizontal adds from adds of shuffles.
18515 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
18516 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
18517 isHorizontalBinOp(LHS, RHS, true))
18518 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
18522 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
18523 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
18524 const X86Subtarget *Subtarget) {
18525 EVT VT = N->getValueType(0);
18526 SDValue LHS = N->getOperand(0);
18527 SDValue RHS = N->getOperand(1);
18529 // Try to synthesize horizontal subs from subs of shuffles.
18530 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
18531 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
18532 isHorizontalBinOp(LHS, RHS, false))
18533 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
18537 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
18538 /// X86ISD::FXOR nodes.
18539 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
18540 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
18541 // F[X]OR(0.0, x) -> x
18542 // F[X]OR(x, 0.0) -> x
18543 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
18544 if (C->getValueAPF().isPosZero())
18545 return N->getOperand(1);
18546 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
18547 if (C->getValueAPF().isPosZero())
18548 return N->getOperand(0);
18552 /// PerformFMinFMaxCombine - Do target-specific dag combines on X86ISD::FMIN and
18553 /// X86ISD::FMAX nodes.
18554 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
18555 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
18557 // Only perform optimizations if UnsafeMath is used.
18558 if (!DAG.getTarget().Options.UnsafeFPMath)
18561 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
18562 // into FMINC and FMAXC, which are Commutative operations.
18563 unsigned NewOp = 0;
18564 switch (N->getOpcode()) {
18565 default: llvm_unreachable("unknown opcode");
18566 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
18567 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
18570 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
18571 N->getOperand(0), N->getOperand(1));
18574 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
18575 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
18576 // FAND(0.0, x) -> 0.0
18577 // FAND(x, 0.0) -> 0.0
18578 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
18579 if (C->getValueAPF().isPosZero())
18580 return N->getOperand(0);
18581 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
18582 if (C->getValueAPF().isPosZero())
18583 return N->getOperand(1);
18587 /// PerformFANDNCombine - Do target-specific dag combines on X86ISD::FANDN nodes
18588 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
18589 // FANDN(x, 0.0) -> 0.0
18590 // FANDN(0.0, x) -> x
18591 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
18592 if (C->getValueAPF().isPosZero())
18593 return N->getOperand(1);
18594 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
18595 if (C->getValueAPF().isPosZero())
18596 return N->getOperand(1);
18600 static SDValue PerformBTCombine(SDNode *N,
18602 TargetLowering::DAGCombinerInfo &DCI) {
18603 // BT ignores high bits in the bit index operand.
18604 SDValue Op1 = N->getOperand(1);
18605 if (Op1.hasOneUse()) {
18606 unsigned BitWidth = Op1.getValueSizeInBits();
18607 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
18608 APInt KnownZero, KnownOne;
18609 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
18610 !DCI.isBeforeLegalizeOps());
18611 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18612 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
18613 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
18614 DCI.CommitTargetLoweringOpt(TLO);
18619 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
18620 SDValue Op = N->getOperand(0);
18621 if (Op.getOpcode() == ISD::BITCAST)
18622 Op = Op.getOperand(0);
18623 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
18624 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
18625 VT.getVectorElementType().getSizeInBits() ==
18626 OpVT.getVectorElementType().getSizeInBits()) {
18627 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
18632 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
18633 const X86Subtarget *Subtarget) {
18634 EVT VT = N->getValueType(0);
18635 if (!VT.isVector())
18638 SDValue N0 = N->getOperand(0);
18639 SDValue N1 = N->getOperand(1);
18640 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
18643 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
18644 // both SSE and AVX2 since there is no sign-extended shift right
18645 // operation on a vector with 64-bit elements.
18646 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
18647 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
18648 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
18649 N0.getOpcode() == ISD::SIGN_EXTEND)) {
18650 SDValue N00 = N0.getOperand(0);
18652 // EXTLOAD has a better solution on AVX2,
18653 // it may be replaced with X86ISD::VSEXT node.
18654 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
18655 if (!ISD::isNormalLoad(N00.getNode()))
18658 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
18659 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
18661 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
18667 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
18668 TargetLowering::DAGCombinerInfo &DCI,
18669 const X86Subtarget *Subtarget) {
18670 if (!DCI.isBeforeLegalizeOps())
18673 if (!Subtarget->hasFp256())
18676 EVT VT = N->getValueType(0);
18677 if (VT.isVector() && VT.getSizeInBits() == 256) {
18678 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
18686 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
18687 const X86Subtarget* Subtarget) {
18689 EVT VT = N->getValueType(0);
18691 // Let legalize expand this if it isn't a legal type yet.
18692 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
18695 EVT ScalarVT = VT.getScalarType();
18696 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
18697 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
18700 SDValue A = N->getOperand(0);
18701 SDValue B = N->getOperand(1);
18702 SDValue C = N->getOperand(2);
18704 bool NegA = (A.getOpcode() == ISD::FNEG);
18705 bool NegB = (B.getOpcode() == ISD::FNEG);
18706 bool NegC = (C.getOpcode() == ISD::FNEG);
18708 // Negative multiplication when NegA xor NegB
18709 bool NegMul = (NegA != NegB);
18711 A = A.getOperand(0);
18713 B = B.getOperand(0);
18715 C = C.getOperand(0);
18719 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
18721 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
18723 return DAG.getNode(Opcode, dl, VT, A, B, C);
18726 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
18727 TargetLowering::DAGCombinerInfo &DCI,
18728 const X86Subtarget *Subtarget) {
18729 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
18730 // (and (i32 x86isd::setcc_carry), 1)
18731 // This eliminates the zext. This transformation is necessary because
18732 // ISD::SETCC is always legalized to i8.
18734 SDValue N0 = N->getOperand(0);
18735 EVT VT = N->getValueType(0);
18737 if (N0.getOpcode() == ISD::AND &&
18739 N0.getOperand(0).hasOneUse()) {
18740 SDValue N00 = N0.getOperand(0);
18741 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
18742 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
18743 if (!C || C->getZExtValue() != 1)
18745 return DAG.getNode(ISD::AND, dl, VT,
18746 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
18747 N00.getOperand(0), N00.getOperand(1)),
18748 DAG.getConstant(1, VT));
18752 if (VT.is256BitVector()) {
18753 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
18761 // Optimize x == -y --> x+y == 0
18762 // x != -y --> x+y != 0
18763 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG) {
18764 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
18765 SDValue LHS = N->getOperand(0);
18766 SDValue RHS = N->getOperand(1);
18768 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
18769 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
18770 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
18771 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
18772 LHS.getValueType(), RHS, LHS.getOperand(1));
18773 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
18774 addV, DAG.getConstant(0, addV.getValueType()), CC);
18776 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
18777 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
18778 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
18779 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
18780 RHS.getValueType(), LHS, RHS.getOperand(1));
18781 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
18782 addV, DAG.getConstant(0, addV.getValueType()), CC);
18787 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
18788 // as "sbb reg,reg", since it can be extended without zext and produces
18789 // an all-ones bit which is more useful than 0/1 in some cases.
18790 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG) {
18791 return DAG.getNode(ISD::AND, DL, MVT::i8,
18792 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
18793 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
18794 DAG.getConstant(1, MVT::i8));
18797 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
18798 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
18799 TargetLowering::DAGCombinerInfo &DCI,
18800 const X86Subtarget *Subtarget) {
18802 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
18803 SDValue EFLAGS = N->getOperand(1);
18805 if (CC == X86::COND_A) {
18806 // Try to convert COND_A into COND_B in an attempt to facilitate
18807 // materializing "setb reg".
18809 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
18810 // cannot take an immediate as its first operand.
18812 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
18813 EFLAGS.getValueType().isInteger() &&
18814 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
18815 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
18816 EFLAGS.getNode()->getVTList(),
18817 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
18818 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
18819 return MaterializeSETB(DL, NewEFLAGS, DAG);
18823 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
18824 // a zext and produces an all-ones bit which is more useful than 0/1 in some
18826 if (CC == X86::COND_B)
18827 return MaterializeSETB(DL, EFLAGS, DAG);
18831 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
18832 if (Flags.getNode()) {
18833 SDValue Cond = DAG.getConstant(CC, MVT::i8);
18834 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
18840 // Optimize branch condition evaluation.
18842 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
18843 TargetLowering::DAGCombinerInfo &DCI,
18844 const X86Subtarget *Subtarget) {
18846 SDValue Chain = N->getOperand(0);
18847 SDValue Dest = N->getOperand(1);
18848 SDValue EFLAGS = N->getOperand(3);
18849 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
18853 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
18854 if (Flags.getNode()) {
18855 SDValue Cond = DAG.getConstant(CC, MVT::i8);
18856 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
18863 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
18864 const X86TargetLowering *XTLI) {
18865 SDValue Op0 = N->getOperand(0);
18866 EVT InVT = Op0->getValueType(0);
18868 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
18869 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
18871 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
18872 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
18873 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
18876 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
18877 // a 32-bit target where SSE doesn't support i64->FP operations.
18878 if (Op0.getOpcode() == ISD::LOAD) {
18879 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
18880 EVT VT = Ld->getValueType(0);
18881 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
18882 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
18883 !XTLI->getSubtarget()->is64Bit() &&
18885 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
18886 Ld->getChain(), Op0, DAG);
18887 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
18894 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
18895 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
18896 X86TargetLowering::DAGCombinerInfo &DCI) {
18897 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
18898 // the result is either zero or one (depending on the input carry bit).
18899 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
18900 if (X86::isZeroNode(N->getOperand(0)) &&
18901 X86::isZeroNode(N->getOperand(1)) &&
18902 // We don't have a good way to replace an EFLAGS use, so only do this when
18904 SDValue(N, 1).use_empty()) {
18906 EVT VT = N->getValueType(0);
18907 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
18908 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
18909 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
18910 DAG.getConstant(X86::COND_B,MVT::i8),
18912 DAG.getConstant(1, VT));
18913 return DCI.CombineTo(N, Res1, CarryOut);
18919 // fold (add Y, (sete X, 0)) -> adc 0, Y
18920 // (add Y, (setne X, 0)) -> sbb -1, Y
18921 // (sub (sete X, 0), Y) -> sbb 0, Y
18922 // (sub (setne X, 0), Y) -> adc -1, Y
18923 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
18926 // Look through ZExts.
18927 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
18928 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
18931 SDValue SetCC = Ext.getOperand(0);
18932 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
18935 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
18936 if (CC != X86::COND_E && CC != X86::COND_NE)
18939 SDValue Cmp = SetCC.getOperand(1);
18940 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
18941 !X86::isZeroNode(Cmp.getOperand(1)) ||
18942 !Cmp.getOperand(0).getValueType().isInteger())
18945 SDValue CmpOp0 = Cmp.getOperand(0);
18946 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
18947 DAG.getConstant(1, CmpOp0.getValueType()));
18949 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
18950 if (CC == X86::COND_NE)
18951 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
18952 DL, OtherVal.getValueType(), OtherVal,
18953 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
18954 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
18955 DL, OtherVal.getValueType(), OtherVal,
18956 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
18959 /// PerformADDCombine - Do target-specific dag combines on integer adds.
18960 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
18961 const X86Subtarget *Subtarget) {
18962 EVT VT = N->getValueType(0);
18963 SDValue Op0 = N->getOperand(0);
18964 SDValue Op1 = N->getOperand(1);
18966 // Try to synthesize horizontal adds from adds of shuffles.
18967 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
18968 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
18969 isHorizontalBinOp(Op0, Op1, true))
18970 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
18972 return OptimizeConditionalInDecrement(N, DAG);
18975 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
18976 const X86Subtarget *Subtarget) {
18977 SDValue Op0 = N->getOperand(0);
18978 SDValue Op1 = N->getOperand(1);
18980 // X86 can't encode an immediate LHS of a sub. See if we can push the
18981 // negation into a preceding instruction.
18982 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
18983 // If the RHS of the sub is a XOR with one use and a constant, invert the
18984 // immediate. Then add one to the LHS of the sub so we can turn
18985 // X-Y -> X+~Y+1, saving one register.
18986 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
18987 isa<ConstantSDNode>(Op1.getOperand(1))) {
18988 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
18989 EVT VT = Op0.getValueType();
18990 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
18992 DAG.getConstant(~XorC, VT));
18993 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
18994 DAG.getConstant(C->getAPIntValue()+1, VT));
18998 // Try to synthesize horizontal adds from adds of shuffles.
18999 EVT VT = N->getValueType(0);
19000 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
19001 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
19002 isHorizontalBinOp(Op0, Op1, true))
19003 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
19005 return OptimizeConditionalInDecrement(N, DAG);
19008 /// performVZEXTCombine - Performs build vector combines
19009 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
19010 TargetLowering::DAGCombinerInfo &DCI,
19011 const X86Subtarget *Subtarget) {
19012 // (vzext (bitcast (vzext (x)) -> (vzext x)
19013 SDValue In = N->getOperand(0);
19014 while (In.getOpcode() == ISD::BITCAST)
19015 In = In.getOperand(0);
19017 if (In.getOpcode() != X86ISD::VZEXT)
19020 return DAG.getNode(X86ISD::VZEXT, SDLoc(N), N->getValueType(0),
19024 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
19025 DAGCombinerInfo &DCI) const {
19026 SelectionDAG &DAG = DCI.DAG;
19027 switch (N->getOpcode()) {
19029 case ISD::EXTRACT_VECTOR_ELT:
19030 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
19032 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget);
19033 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
19034 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
19035 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
19036 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
19037 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
19040 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
19041 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
19042 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
19043 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
19044 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
19045 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
19046 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
19047 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
19048 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
19050 case X86ISD::FOR: return PerformFORCombine(N, DAG);
19052 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
19053 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
19054 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
19055 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
19056 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
19057 case ISD::ANY_EXTEND:
19058 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
19059 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
19060 case ISD::SIGN_EXTEND_INREG: return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
19061 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
19062 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG);
19063 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
19064 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
19065 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
19066 case X86ISD::SHUFP: // Handle all target specific shuffles
19067 case X86ISD::PALIGNR:
19068 case X86ISD::UNPCKH:
19069 case X86ISD::UNPCKL:
19070 case X86ISD::MOVHLPS:
19071 case X86ISD::MOVLHPS:
19072 case X86ISD::PSHUFD:
19073 case X86ISD::PSHUFHW:
19074 case X86ISD::PSHUFLW:
19075 case X86ISD::MOVSS:
19076 case X86ISD::MOVSD:
19077 case X86ISD::VPERMILP:
19078 case X86ISD::VPERM2X128:
19079 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
19080 case ISD::CONCAT_VECTORS: return PerformConcatCombine(N, DAG, DCI, Subtarget);
19081 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
19087 /// isTypeDesirableForOp - Return true if the target has native support for
19088 /// the specified value type and it is 'desirable' to use the type for the
19089 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
19090 /// instruction encodings are longer and some i16 instructions are slow.
19091 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
19092 if (!isTypeLegal(VT))
19094 if (VT != MVT::i16)
19101 case ISD::SIGN_EXTEND:
19102 case ISD::ZERO_EXTEND:
19103 case ISD::ANY_EXTEND:
19116 /// IsDesirableToPromoteOp - This method query the target whether it is
19117 /// beneficial for dag combiner to promote the specified node. If true, it
19118 /// should return the desired promotion type by reference.
19119 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
19120 EVT VT = Op.getValueType();
19121 if (VT != MVT::i16)
19124 bool Promote = false;
19125 bool Commute = false;
19126 switch (Op.getOpcode()) {
19129 LoadSDNode *LD = cast<LoadSDNode>(Op);
19130 // If the non-extending load has a single use and it's not live out, then it
19131 // might be folded.
19132 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
19133 Op.hasOneUse()*/) {
19134 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
19135 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
19136 // The only case where we'd want to promote LOAD (rather then it being
19137 // promoted as an operand is when it's only use is liveout.
19138 if (UI->getOpcode() != ISD::CopyToReg)
19145 case ISD::SIGN_EXTEND:
19146 case ISD::ZERO_EXTEND:
19147 case ISD::ANY_EXTEND:
19152 SDValue N0 = Op.getOperand(0);
19153 // Look out for (store (shl (load), x)).
19154 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
19167 SDValue N0 = Op.getOperand(0);
19168 SDValue N1 = Op.getOperand(1);
19169 if (!Commute && MayFoldLoad(N1))
19171 // Avoid disabling potential load folding opportunities.
19172 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
19174 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
19184 //===----------------------------------------------------------------------===//
19185 // X86 Inline Assembly Support
19186 //===----------------------------------------------------------------------===//
19189 // Helper to match a string separated by whitespace.
19190 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
19191 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
19193 for (unsigned i = 0, e = args.size(); i != e; ++i) {
19194 StringRef piece(*args[i]);
19195 if (!s.startswith(piece)) // Check if the piece matches.
19198 s = s.substr(piece.size());
19199 StringRef::size_type pos = s.find_first_not_of(" \t");
19200 if (pos == 0) // We matched a prefix.
19208 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
19211 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
19212 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
19214 std::string AsmStr = IA->getAsmString();
19216 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
19217 if (!Ty || Ty->getBitWidth() % 16 != 0)
19220 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
19221 SmallVector<StringRef, 4> AsmPieces;
19222 SplitString(AsmStr, AsmPieces, ";\n");
19224 switch (AsmPieces.size()) {
19225 default: return false;
19227 // FIXME: this should verify that we are targeting a 486 or better. If not,
19228 // we will turn this bswap into something that will be lowered to logical
19229 // ops instead of emitting the bswap asm. For now, we don't support 486 or
19230 // lower so don't worry about this.
19232 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
19233 matchAsm(AsmPieces[0], "bswapl", "$0") ||
19234 matchAsm(AsmPieces[0], "bswapq", "$0") ||
19235 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
19236 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
19237 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
19238 // No need to check constraints, nothing other than the equivalent of
19239 // "=r,0" would be valid here.
19240 return IntrinsicLowering::LowerToByteSwap(CI);
19243 // rorw $$8, ${0:w} --> llvm.bswap.i16
19244 if (CI->getType()->isIntegerTy(16) &&
19245 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
19246 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
19247 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
19249 const std::string &ConstraintsStr = IA->getConstraintString();
19250 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
19251 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
19252 if (AsmPieces.size() == 4 &&
19253 AsmPieces[0] == "~{cc}" &&
19254 AsmPieces[1] == "~{dirflag}" &&
19255 AsmPieces[2] == "~{flags}" &&
19256 AsmPieces[3] == "~{fpsr}")
19257 return IntrinsicLowering::LowerToByteSwap(CI);
19261 if (CI->getType()->isIntegerTy(32) &&
19262 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
19263 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
19264 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
19265 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
19267 const std::string &ConstraintsStr = IA->getConstraintString();
19268 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
19269 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
19270 if (AsmPieces.size() == 4 &&
19271 AsmPieces[0] == "~{cc}" &&
19272 AsmPieces[1] == "~{dirflag}" &&
19273 AsmPieces[2] == "~{flags}" &&
19274 AsmPieces[3] == "~{fpsr}")
19275 return IntrinsicLowering::LowerToByteSwap(CI);
19278 if (CI->getType()->isIntegerTy(64)) {
19279 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
19280 if (Constraints.size() >= 2 &&
19281 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
19282 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
19283 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
19284 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
19285 matchAsm(AsmPieces[1], "bswap", "%edx") &&
19286 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
19287 return IntrinsicLowering::LowerToByteSwap(CI);
19295 /// getConstraintType - Given a constraint letter, return the type of
19296 /// constraint it is for this target.
19297 X86TargetLowering::ConstraintType
19298 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
19299 if (Constraint.size() == 1) {
19300 switch (Constraint[0]) {
19311 return C_RegisterClass;
19335 return TargetLowering::getConstraintType(Constraint);
19338 /// Examine constraint type and operand type and determine a weight value.
19339 /// This object must already have been set up with the operand type
19340 /// and the current alternative constraint selected.
19341 TargetLowering::ConstraintWeight
19342 X86TargetLowering::getSingleConstraintMatchWeight(
19343 AsmOperandInfo &info, const char *constraint) const {
19344 ConstraintWeight weight = CW_Invalid;
19345 Value *CallOperandVal = info.CallOperandVal;
19346 // If we don't have a value, we can't do a match,
19347 // but allow it at the lowest weight.
19348 if (CallOperandVal == NULL)
19350 Type *type = CallOperandVal->getType();
19351 // Look at the constraint type.
19352 switch (*constraint) {
19354 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
19365 if (CallOperandVal->getType()->isIntegerTy())
19366 weight = CW_SpecificReg;
19371 if (type->isFloatingPointTy())
19372 weight = CW_SpecificReg;
19375 if (type->isX86_MMXTy() && Subtarget->hasMMX())
19376 weight = CW_SpecificReg;
19380 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
19381 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
19382 weight = CW_Register;
19385 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
19386 if (C->getZExtValue() <= 31)
19387 weight = CW_Constant;
19391 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19392 if (C->getZExtValue() <= 63)
19393 weight = CW_Constant;
19397 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19398 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
19399 weight = CW_Constant;
19403 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19404 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
19405 weight = CW_Constant;
19409 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19410 if (C->getZExtValue() <= 3)
19411 weight = CW_Constant;
19415 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19416 if (C->getZExtValue() <= 0xff)
19417 weight = CW_Constant;
19422 if (dyn_cast<ConstantFP>(CallOperandVal)) {
19423 weight = CW_Constant;
19427 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19428 if ((C->getSExtValue() >= -0x80000000LL) &&
19429 (C->getSExtValue() <= 0x7fffffffLL))
19430 weight = CW_Constant;
19434 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19435 if (C->getZExtValue() <= 0xffffffff)
19436 weight = CW_Constant;
19443 /// LowerXConstraint - try to replace an X constraint, which matches anything,
19444 /// with another that has more specific requirements based on the type of the
19445 /// corresponding operand.
19446 const char *X86TargetLowering::
19447 LowerXConstraint(EVT ConstraintVT) const {
19448 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
19449 // 'f' like normal targets.
19450 if (ConstraintVT.isFloatingPoint()) {
19451 if (Subtarget->hasSSE2())
19453 if (Subtarget->hasSSE1())
19457 return TargetLowering::LowerXConstraint(ConstraintVT);
19460 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
19461 /// vector. If it is invalid, don't add anything to Ops.
19462 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
19463 std::string &Constraint,
19464 std::vector<SDValue>&Ops,
19465 SelectionDAG &DAG) const {
19466 SDValue Result(0, 0);
19468 // Only support length 1 constraints for now.
19469 if (Constraint.length() > 1) return;
19471 char ConstraintLetter = Constraint[0];
19472 switch (ConstraintLetter) {
19475 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
19476 if (C->getZExtValue() <= 31) {
19477 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
19483 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
19484 if (C->getZExtValue() <= 63) {
19485 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
19491 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
19492 if (isInt<8>(C->getSExtValue())) {
19493 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
19499 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
19500 if (C->getZExtValue() <= 255) {
19501 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
19507 // 32-bit signed value
19508 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
19509 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
19510 C->getSExtValue())) {
19511 // Widen to 64 bits here to get it sign extended.
19512 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
19515 // FIXME gcc accepts some relocatable values here too, but only in certain
19516 // memory models; it's complicated.
19521 // 32-bit unsigned value
19522 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
19523 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
19524 C->getZExtValue())) {
19525 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
19529 // FIXME gcc accepts some relocatable values here too, but only in certain
19530 // memory models; it's complicated.
19534 // Literal immediates are always ok.
19535 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
19536 // Widen to 64 bits here to get it sign extended.
19537 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
19541 // In any sort of PIC mode addresses need to be computed at runtime by
19542 // adding in a register or some sort of table lookup. These can't
19543 // be used as immediates.
19544 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
19547 // If we are in non-pic codegen mode, we allow the address of a global (with
19548 // an optional displacement) to be used with 'i'.
19549 GlobalAddressSDNode *GA = 0;
19550 int64_t Offset = 0;
19552 // Match either (GA), (GA+C), (GA+C1+C2), etc.
19554 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
19555 Offset += GA->getOffset();
19557 } else if (Op.getOpcode() == ISD::ADD) {
19558 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
19559 Offset += C->getZExtValue();
19560 Op = Op.getOperand(0);
19563 } else if (Op.getOpcode() == ISD::SUB) {
19564 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
19565 Offset += -C->getZExtValue();
19566 Op = Op.getOperand(0);
19571 // Otherwise, this isn't something we can handle, reject it.
19575 const GlobalValue *GV = GA->getGlobal();
19576 // If we require an extra load to get this address, as in PIC mode, we
19577 // can't accept it.
19578 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
19579 getTargetMachine())))
19582 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
19583 GA->getValueType(0), Offset);
19588 if (Result.getNode()) {
19589 Ops.push_back(Result);
19592 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
19595 std::pair<unsigned, const TargetRegisterClass*>
19596 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
19598 // First, see if this is a constraint that directly corresponds to an LLVM
19600 if (Constraint.size() == 1) {
19601 // GCC Constraint Letters
19602 switch (Constraint[0]) {
19604 // TODO: Slight differences here in allocation order and leaving
19605 // RIP in the class. Do they matter any more here than they do
19606 // in the normal allocation?
19607 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
19608 if (Subtarget->is64Bit()) {
19609 if (VT == MVT::i32 || VT == MVT::f32)
19610 return std::make_pair(0U, &X86::GR32RegClass);
19611 if (VT == MVT::i16)
19612 return std::make_pair(0U, &X86::GR16RegClass);
19613 if (VT == MVT::i8 || VT == MVT::i1)
19614 return std::make_pair(0U, &X86::GR8RegClass);
19615 if (VT == MVT::i64 || VT == MVT::f64)
19616 return std::make_pair(0U, &X86::GR64RegClass);
19619 // 32-bit fallthrough
19620 case 'Q': // Q_REGS
19621 if (VT == MVT::i32 || VT == MVT::f32)
19622 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
19623 if (VT == MVT::i16)
19624 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
19625 if (VT == MVT::i8 || VT == MVT::i1)
19626 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
19627 if (VT == MVT::i64)
19628 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
19630 case 'r': // GENERAL_REGS
19631 case 'l': // INDEX_REGS
19632 if (VT == MVT::i8 || VT == MVT::i1)
19633 return std::make_pair(0U, &X86::GR8RegClass);
19634 if (VT == MVT::i16)
19635 return std::make_pair(0U, &X86::GR16RegClass);
19636 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
19637 return std::make_pair(0U, &X86::GR32RegClass);
19638 return std::make_pair(0U, &X86::GR64RegClass);
19639 case 'R': // LEGACY_REGS
19640 if (VT == MVT::i8 || VT == MVT::i1)
19641 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
19642 if (VT == MVT::i16)
19643 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
19644 if (VT == MVT::i32 || !Subtarget->is64Bit())
19645 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
19646 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
19647 case 'f': // FP Stack registers.
19648 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
19649 // value to the correct fpstack register class.
19650 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
19651 return std::make_pair(0U, &X86::RFP32RegClass);
19652 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
19653 return std::make_pair(0U, &X86::RFP64RegClass);
19654 return std::make_pair(0U, &X86::RFP80RegClass);
19655 case 'y': // MMX_REGS if MMX allowed.
19656 if (!Subtarget->hasMMX()) break;
19657 return std::make_pair(0U, &X86::VR64RegClass);
19658 case 'Y': // SSE_REGS if SSE2 allowed
19659 if (!Subtarget->hasSSE2()) break;
19661 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
19662 if (!Subtarget->hasSSE1()) break;
19664 switch (VT.SimpleTy) {
19666 // Scalar SSE types.
19669 return std::make_pair(0U, &X86::FR32RegClass);
19672 return std::make_pair(0U, &X86::FR64RegClass);
19680 return std::make_pair(0U, &X86::VR128RegClass);
19688 return std::make_pair(0U, &X86::VR256RegClass);
19693 return std::make_pair(0U, &X86::VR512RegClass);
19699 // Use the default implementation in TargetLowering to convert the register
19700 // constraint into a member of a register class.
19701 std::pair<unsigned, const TargetRegisterClass*> Res;
19702 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
19704 // Not found as a standard register?
19705 if (Res.second == 0) {
19706 // Map st(0) -> st(7) -> ST0
19707 if (Constraint.size() == 7 && Constraint[0] == '{' &&
19708 tolower(Constraint[1]) == 's' &&
19709 tolower(Constraint[2]) == 't' &&
19710 Constraint[3] == '(' &&
19711 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
19712 Constraint[5] == ')' &&
19713 Constraint[6] == '}') {
19715 Res.first = X86::ST0+Constraint[4]-'0';
19716 Res.second = &X86::RFP80RegClass;
19720 // GCC allows "st(0)" to be called just plain "st".
19721 if (StringRef("{st}").equals_lower(Constraint)) {
19722 Res.first = X86::ST0;
19723 Res.second = &X86::RFP80RegClass;
19728 if (StringRef("{flags}").equals_lower(Constraint)) {
19729 Res.first = X86::EFLAGS;
19730 Res.second = &X86::CCRRegClass;
19734 // 'A' means EAX + EDX.
19735 if (Constraint == "A") {
19736 Res.first = X86::EAX;
19737 Res.second = &X86::GR32_ADRegClass;
19743 // Otherwise, check to see if this is a register class of the wrong value
19744 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
19745 // turn into {ax},{dx}.
19746 if (Res.second->hasType(VT))
19747 return Res; // Correct type already, nothing to do.
19749 // All of the single-register GCC register classes map their values onto
19750 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
19751 // really want an 8-bit or 32-bit register, map to the appropriate register
19752 // class and return the appropriate register.
19753 if (Res.second == &X86::GR16RegClass) {
19754 if (VT == MVT::i8 || VT == MVT::i1) {
19755 unsigned DestReg = 0;
19756 switch (Res.first) {
19758 case X86::AX: DestReg = X86::AL; break;
19759 case X86::DX: DestReg = X86::DL; break;
19760 case X86::CX: DestReg = X86::CL; break;
19761 case X86::BX: DestReg = X86::BL; break;
19764 Res.first = DestReg;
19765 Res.second = &X86::GR8RegClass;
19767 } else if (VT == MVT::i32 || VT == MVT::f32) {
19768 unsigned DestReg = 0;
19769 switch (Res.first) {
19771 case X86::AX: DestReg = X86::EAX; break;
19772 case X86::DX: DestReg = X86::EDX; break;
19773 case X86::CX: DestReg = X86::ECX; break;
19774 case X86::BX: DestReg = X86::EBX; break;
19775 case X86::SI: DestReg = X86::ESI; break;
19776 case X86::DI: DestReg = X86::EDI; break;
19777 case X86::BP: DestReg = X86::EBP; break;
19778 case X86::SP: DestReg = X86::ESP; break;
19781 Res.first = DestReg;
19782 Res.second = &X86::GR32RegClass;
19784 } else if (VT == MVT::i64 || VT == MVT::f64) {
19785 unsigned DestReg = 0;
19786 switch (Res.first) {
19788 case X86::AX: DestReg = X86::RAX; break;
19789 case X86::DX: DestReg = X86::RDX; break;
19790 case X86::CX: DestReg = X86::RCX; break;
19791 case X86::BX: DestReg = X86::RBX; break;
19792 case X86::SI: DestReg = X86::RSI; break;
19793 case X86::DI: DestReg = X86::RDI; break;
19794 case X86::BP: DestReg = X86::RBP; break;
19795 case X86::SP: DestReg = X86::RSP; break;
19798 Res.first = DestReg;
19799 Res.second = &X86::GR64RegClass;
19802 } else if (Res.second == &X86::FR32RegClass ||
19803 Res.second == &X86::FR64RegClass ||
19804 Res.second == &X86::VR128RegClass ||
19805 Res.second == &X86::VR256RegClass ||
19806 Res.second == &X86::FR32XRegClass ||
19807 Res.second == &X86::FR64XRegClass ||
19808 Res.second == &X86::VR128XRegClass ||
19809 Res.second == &X86::VR256XRegClass ||
19810 Res.second == &X86::VR512RegClass) {
19811 // Handle references to XMM physical registers that got mapped into the
19812 // wrong class. This can happen with constraints like {xmm0} where the
19813 // target independent register mapper will just pick the first match it can
19814 // find, ignoring the required type.
19816 if (VT == MVT::f32 || VT == MVT::i32)
19817 Res.second = &X86::FR32RegClass;
19818 else if (VT == MVT::f64 || VT == MVT::i64)
19819 Res.second = &X86::FR64RegClass;
19820 else if (X86::VR128RegClass.hasType(VT))
19821 Res.second = &X86::VR128RegClass;
19822 else if (X86::VR256RegClass.hasType(VT))
19823 Res.second = &X86::VR256RegClass;
19824 else if (X86::VR512RegClass.hasType(VT))
19825 Res.second = &X86::VR512RegClass;