1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
16 #include "X86InstrBuilder.h"
17 #include "X86ISelLowering.h"
18 #include "X86TargetMachine.h"
19 #include "X86TargetObjectFile.h"
20 #include "llvm/CallingConv.h"
21 #include "llvm/Constants.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/GlobalAlias.h"
24 #include "llvm/GlobalVariable.h"
25 #include "llvm/Function.h"
26 #include "llvm/Instructions.h"
27 #include "llvm/Intrinsics.h"
28 #include "llvm/LLVMContext.h"
29 #include "llvm/ADT/BitVector.h"
30 #include "llvm/ADT/VectorExtras.h"
31 #include "llvm/CodeGen/MachineFrameInfo.h"
32 #include "llvm/CodeGen/MachineFunction.h"
33 #include "llvm/CodeGen/MachineInstrBuilder.h"
34 #include "llvm/CodeGen/MachineModuleInfo.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/PseudoSourceValue.h"
37 #include "llvm/Support/MathExtras.h"
38 #include "llvm/Support/Debug.h"
39 #include "llvm/Support/ErrorHandling.h"
40 #include "llvm/Target/TargetOptions.h"
41 #include "llvm/ADT/SmallSet.h"
42 #include "llvm/ADT/StringExtras.h"
43 #include "llvm/Support/CommandLine.h"
44 #include "llvm/Support/raw_ostream.h"
48 DisableMMX("disable-mmx", cl::Hidden, cl::desc("Disable use of MMX"));
50 // Disable16Bit - 16-bit operations typically have a larger encoding than
51 // corresponding 32-bit instructions, and 16-bit code is slow on some
52 // processors. This is an experimental flag to disable 16-bit operations
53 // (which forces them to be Legalized to 32-bit operations).
55 Disable16Bit("disable-16bit", cl::Hidden,
56 cl::desc("Disable use of 16-bit instructions"));
58 // Forward declarations.
59 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
62 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
63 switch (TM.getSubtarget<X86Subtarget>().TargetType) {
64 default: llvm_unreachable("unknown subtarget type");
65 case X86Subtarget::isDarwin:
66 if (TM.getSubtarget<X86Subtarget>().is64Bit())
67 return new X8664_MachoTargetObjectFile();
68 return new X8632_MachoTargetObjectFile();
69 case X86Subtarget::isELF:
70 return new TargetLoweringObjectFileELF();
71 case X86Subtarget::isMingw:
72 case X86Subtarget::isCygwin:
73 case X86Subtarget::isWindows:
74 return new TargetLoweringObjectFileCOFF();
79 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
80 : TargetLowering(TM, createTLOF(TM)) {
81 Subtarget = &TM.getSubtarget<X86Subtarget>();
82 X86ScalarSSEf64 = Subtarget->hasSSE2();
83 X86ScalarSSEf32 = Subtarget->hasSSE1();
84 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
86 RegInfo = TM.getRegisterInfo();
89 // Set up the TargetLowering object.
91 // X86 is weird, it always uses i8 for shift amounts and setcc results.
92 setShiftAmountType(MVT::i8);
93 setBooleanContents(ZeroOrOneBooleanContent);
94 setSchedulingPreference(SchedulingForRegPressure);
95 setStackPointerRegisterToSaveRestore(X86StackPtr);
97 if (Subtarget->isTargetDarwin()) {
98 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
99 setUseUnderscoreSetJmp(false);
100 setUseUnderscoreLongJmp(false);
101 } else if (Subtarget->isTargetMingw()) {
102 // MS runtime is weird: it exports _setjmp, but longjmp!
103 setUseUnderscoreSetJmp(true);
104 setUseUnderscoreLongJmp(false);
106 setUseUnderscoreSetJmp(true);
107 setUseUnderscoreLongJmp(true);
110 // Set up the register classes.
111 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
113 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
114 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
115 if (Subtarget->is64Bit())
116 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
118 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
120 // We don't accept any truncstore of integer registers.
121 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
123 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
124 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
126 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
127 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
128 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
130 // SETOEQ and SETUNE require checking two conditions.
131 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
132 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
133 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
134 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
135 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
136 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
138 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
140 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
141 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
142 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
144 if (Subtarget->is64Bit()) {
145 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
146 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand);
147 } else if (!UseSoftFloat) {
148 if (X86ScalarSSEf64) {
149 // We have an impenetrably clever algorithm for ui64->double only.
150 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
152 // We have an algorithm for SSE2, and we turn this into a 64-bit
153 // FILD for other targets.
154 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
157 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
159 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
160 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
163 // SSE has no i16 to fp conversion, only i32
164 if (X86ScalarSSEf32) {
165 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
166 // f32 and f64 cases are Legal, f80 case is not
167 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
169 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
170 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
173 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
174 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
177 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
178 // are Legal, f80 is custom lowered.
179 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
180 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
182 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
184 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
185 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
187 if (X86ScalarSSEf32) {
188 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
189 // f32 and f64 cases are Legal, f80 case is not
190 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
192 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
193 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
196 // Handle FP_TO_UINT by promoting the destination to a larger signed
198 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
199 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
200 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
202 if (Subtarget->is64Bit()) {
203 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
204 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
205 } else if (!UseSoftFloat) {
206 if (X86ScalarSSEf32 && !Subtarget->hasSSE3())
207 // Expand FP_TO_UINT into a select.
208 // FIXME: We would like to use a Custom expander here eventually to do
209 // the optimal thing for SSE vs. the default expansion in the legalizer.
210 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
212 // With SSE3 we can use fisttpll to convert to a signed i64; without
213 // SSE, we're stuck with a fistpll.
214 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
217 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
218 if (!X86ScalarSSEf64) {
219 setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand);
220 setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand);
223 // Scalar integer divide and remainder are lowered to use operations that
224 // produce two results, to match the available instructions. This exposes
225 // the two-result form to trivial CSE, which is able to combine x/y and x%y
226 // into a single instruction.
228 // Scalar integer multiply-high is also lowered to use two-result
229 // operations, to match the available instructions. However, plain multiply
230 // (low) operations are left as Legal, as there are single-result
231 // instructions for this in x86. Using the two-result multiply instructions
232 // when both high and low results are needed must be arranged by dagcombine.
233 setOperationAction(ISD::MULHS , MVT::i8 , Expand);
234 setOperationAction(ISD::MULHU , MVT::i8 , Expand);
235 setOperationAction(ISD::SDIV , MVT::i8 , Expand);
236 setOperationAction(ISD::UDIV , MVT::i8 , Expand);
237 setOperationAction(ISD::SREM , MVT::i8 , Expand);
238 setOperationAction(ISD::UREM , MVT::i8 , Expand);
239 setOperationAction(ISD::MULHS , MVT::i16 , Expand);
240 setOperationAction(ISD::MULHU , MVT::i16 , Expand);
241 setOperationAction(ISD::SDIV , MVT::i16 , Expand);
242 setOperationAction(ISD::UDIV , MVT::i16 , Expand);
243 setOperationAction(ISD::SREM , MVT::i16 , Expand);
244 setOperationAction(ISD::UREM , MVT::i16 , Expand);
245 setOperationAction(ISD::MULHS , MVT::i32 , Expand);
246 setOperationAction(ISD::MULHU , MVT::i32 , Expand);
247 setOperationAction(ISD::SDIV , MVT::i32 , Expand);
248 setOperationAction(ISD::UDIV , MVT::i32 , Expand);
249 setOperationAction(ISD::SREM , MVT::i32 , Expand);
250 setOperationAction(ISD::UREM , MVT::i32 , Expand);
251 setOperationAction(ISD::MULHS , MVT::i64 , Expand);
252 setOperationAction(ISD::MULHU , MVT::i64 , Expand);
253 setOperationAction(ISD::SDIV , MVT::i64 , Expand);
254 setOperationAction(ISD::UDIV , MVT::i64 , Expand);
255 setOperationAction(ISD::SREM , MVT::i64 , Expand);
256 setOperationAction(ISD::UREM , MVT::i64 , Expand);
258 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
259 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
260 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
261 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
262 if (Subtarget->is64Bit())
263 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
264 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
265 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
266 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
267 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
268 setOperationAction(ISD::FREM , MVT::f32 , Expand);
269 setOperationAction(ISD::FREM , MVT::f64 , Expand);
270 setOperationAction(ISD::FREM , MVT::f80 , Expand);
271 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
273 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
274 setOperationAction(ISD::CTTZ , MVT::i8 , Custom);
275 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
276 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
278 setOperationAction(ISD::CTTZ , MVT::i16 , Expand);
279 setOperationAction(ISD::CTLZ , MVT::i16 , Expand);
281 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
282 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
284 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
285 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
286 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
287 if (Subtarget->is64Bit()) {
288 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
289 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
290 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
293 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
294 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
296 // These should be promoted to a larger select which is supported.
297 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
298 // X86 wants to expand cmov itself.
299 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
301 setOperationAction(ISD::SELECT , MVT::i16 , Expand);
303 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
304 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
305 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
306 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
307 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
308 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
310 setOperationAction(ISD::SETCC , MVT::i16 , Expand);
312 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
313 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
314 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
315 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
316 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
317 if (Subtarget->is64Bit()) {
318 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
319 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
321 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
324 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
325 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
326 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
327 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
328 if (Subtarget->is64Bit())
329 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
330 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
331 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
332 if (Subtarget->is64Bit()) {
333 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
334 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
335 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
336 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
337 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
339 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
340 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
341 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
342 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
343 if (Subtarget->is64Bit()) {
344 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
345 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
346 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
349 if (Subtarget->hasSSE1())
350 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
352 if (!Subtarget->hasSSE2())
353 setOperationAction(ISD::MEMBARRIER , MVT::Other, Expand);
355 // Expand certain atomics
356 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i8, Custom);
357 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i16, Custom);
358 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom);
359 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom);
361 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i8, Custom);
362 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i16, Custom);
363 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Custom);
364 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
366 if (!Subtarget->is64Bit()) {
367 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
368 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
369 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
370 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
371 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
372 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
373 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
376 // Use the default ISD::DBG_STOPPOINT.
377 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
378 // FIXME - use subtarget debug flags
379 if (!Subtarget->isTargetDarwin() &&
380 !Subtarget->isTargetELF() &&
381 !Subtarget->isTargetCygMing()) {
382 setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
383 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
386 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
387 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
388 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
389 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
390 if (Subtarget->is64Bit()) {
391 setExceptionPointerRegister(X86::RAX);
392 setExceptionSelectorRegister(X86::RDX);
394 setExceptionPointerRegister(X86::EAX);
395 setExceptionSelectorRegister(X86::EDX);
397 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
398 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
400 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom);
402 setOperationAction(ISD::TRAP, MVT::Other, Legal);
404 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
405 setOperationAction(ISD::VASTART , MVT::Other, Custom);
406 setOperationAction(ISD::VAEND , MVT::Other, Expand);
407 if (Subtarget->is64Bit()) {
408 setOperationAction(ISD::VAARG , MVT::Other, Custom);
409 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
411 setOperationAction(ISD::VAARG , MVT::Other, Expand);
412 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
415 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
416 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
417 if (Subtarget->is64Bit())
418 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
419 if (Subtarget->isTargetCygMing())
420 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
422 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
424 if (!UseSoftFloat && X86ScalarSSEf64) {
425 // f32 and f64 use SSE.
426 // Set up the FP register classes.
427 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
428 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
430 // Use ANDPD to simulate FABS.
431 setOperationAction(ISD::FABS , MVT::f64, Custom);
432 setOperationAction(ISD::FABS , MVT::f32, Custom);
434 // Use XORP to simulate FNEG.
435 setOperationAction(ISD::FNEG , MVT::f64, Custom);
436 setOperationAction(ISD::FNEG , MVT::f32, Custom);
438 // Use ANDPD and ORPD to simulate FCOPYSIGN.
439 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
440 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
442 // We don't support sin/cos/fmod
443 setOperationAction(ISD::FSIN , MVT::f64, Expand);
444 setOperationAction(ISD::FCOS , MVT::f64, Expand);
445 setOperationAction(ISD::FSIN , MVT::f32, Expand);
446 setOperationAction(ISD::FCOS , MVT::f32, Expand);
448 // Expand FP immediates into loads from the stack, except for the special
450 addLegalFPImmediate(APFloat(+0.0)); // xorpd
451 addLegalFPImmediate(APFloat(+0.0f)); // xorps
452 } else if (!UseSoftFloat && X86ScalarSSEf32) {
453 // Use SSE for f32, x87 for f64.
454 // Set up the FP register classes.
455 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
456 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
458 // Use ANDPS to simulate FABS.
459 setOperationAction(ISD::FABS , MVT::f32, Custom);
461 // Use XORP to simulate FNEG.
462 setOperationAction(ISD::FNEG , MVT::f32, Custom);
464 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
466 // Use ANDPS and ORPS to simulate FCOPYSIGN.
467 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
468 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
470 // We don't support sin/cos/fmod
471 setOperationAction(ISD::FSIN , MVT::f32, Expand);
472 setOperationAction(ISD::FCOS , MVT::f32, Expand);
474 // Special cases we handle for FP constants.
475 addLegalFPImmediate(APFloat(+0.0f)); // xorps
476 addLegalFPImmediate(APFloat(+0.0)); // FLD0
477 addLegalFPImmediate(APFloat(+1.0)); // FLD1
478 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
479 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
482 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
483 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
485 } else if (!UseSoftFloat) {
486 // f32 and f64 in x87.
487 // Set up the FP register classes.
488 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
489 addRegisterClass(MVT::f32, X86::RFP32RegisterClass);
491 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
492 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
493 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
494 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
497 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
498 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
500 addLegalFPImmediate(APFloat(+0.0)); // FLD0
501 addLegalFPImmediate(APFloat(+1.0)); // FLD1
502 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
503 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
504 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
505 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
506 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
507 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
510 // Long double always uses X87.
512 addRegisterClass(MVT::f80, X86::RFP80RegisterClass);
513 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
514 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
517 APFloat TmpFlt(+0.0);
518 TmpFlt.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
520 addLegalFPImmediate(TmpFlt); // FLD0
522 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
523 APFloat TmpFlt2(+1.0);
524 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
526 addLegalFPImmediate(TmpFlt2); // FLD1
527 TmpFlt2.changeSign();
528 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
532 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
533 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
537 // Always use a library call for pow.
538 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
539 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
540 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
542 setOperationAction(ISD::FLOG, MVT::f80, Expand);
543 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
544 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
545 setOperationAction(ISD::FEXP, MVT::f80, Expand);
546 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
548 // First set operation action for all vector types to either promote
549 // (for widening) or expand (for scalarization). Then we will selectively
550 // turn on ones that can be effectively codegen'd.
551 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
552 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
553 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
554 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
555 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
556 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
557 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
558 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
559 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
560 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
561 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
562 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
563 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
564 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
565 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
566 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
567 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
568 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
569 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
570 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
571 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
572 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
573 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
574 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
575 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
576 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
577 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
578 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
579 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
580 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
581 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
582 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
583 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
584 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
585 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
586 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
587 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
588 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
589 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
590 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
591 setOperationAction(ISD::VSETCC, (MVT::SimpleValueType)VT, Expand);
592 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
593 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
594 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
595 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand);
596 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand);
597 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand);
598 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand);
599 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
600 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
603 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
604 // with -msoft-float, disable use of MMX as well.
605 if (!UseSoftFloat && !DisableMMX && Subtarget->hasMMX()) {
606 addRegisterClass(MVT::v8i8, X86::VR64RegisterClass);
607 addRegisterClass(MVT::v4i16, X86::VR64RegisterClass);
608 addRegisterClass(MVT::v2i32, X86::VR64RegisterClass);
609 addRegisterClass(MVT::v2f32, X86::VR64RegisterClass);
610 addRegisterClass(MVT::v1i64, X86::VR64RegisterClass);
612 setOperationAction(ISD::ADD, MVT::v8i8, Legal);
613 setOperationAction(ISD::ADD, MVT::v4i16, Legal);
614 setOperationAction(ISD::ADD, MVT::v2i32, Legal);
615 setOperationAction(ISD::ADD, MVT::v1i64, Legal);
617 setOperationAction(ISD::SUB, MVT::v8i8, Legal);
618 setOperationAction(ISD::SUB, MVT::v4i16, Legal);
619 setOperationAction(ISD::SUB, MVT::v2i32, Legal);
620 setOperationAction(ISD::SUB, MVT::v1i64, Legal);
622 setOperationAction(ISD::MULHS, MVT::v4i16, Legal);
623 setOperationAction(ISD::MUL, MVT::v4i16, Legal);
625 setOperationAction(ISD::AND, MVT::v8i8, Promote);
626 AddPromotedToType (ISD::AND, MVT::v8i8, MVT::v1i64);
627 setOperationAction(ISD::AND, MVT::v4i16, Promote);
628 AddPromotedToType (ISD::AND, MVT::v4i16, MVT::v1i64);
629 setOperationAction(ISD::AND, MVT::v2i32, Promote);
630 AddPromotedToType (ISD::AND, MVT::v2i32, MVT::v1i64);
631 setOperationAction(ISD::AND, MVT::v1i64, Legal);
633 setOperationAction(ISD::OR, MVT::v8i8, Promote);
634 AddPromotedToType (ISD::OR, MVT::v8i8, MVT::v1i64);
635 setOperationAction(ISD::OR, MVT::v4i16, Promote);
636 AddPromotedToType (ISD::OR, MVT::v4i16, MVT::v1i64);
637 setOperationAction(ISD::OR, MVT::v2i32, Promote);
638 AddPromotedToType (ISD::OR, MVT::v2i32, MVT::v1i64);
639 setOperationAction(ISD::OR, MVT::v1i64, Legal);
641 setOperationAction(ISD::XOR, MVT::v8i8, Promote);
642 AddPromotedToType (ISD::XOR, MVT::v8i8, MVT::v1i64);
643 setOperationAction(ISD::XOR, MVT::v4i16, Promote);
644 AddPromotedToType (ISD::XOR, MVT::v4i16, MVT::v1i64);
645 setOperationAction(ISD::XOR, MVT::v2i32, Promote);
646 AddPromotedToType (ISD::XOR, MVT::v2i32, MVT::v1i64);
647 setOperationAction(ISD::XOR, MVT::v1i64, Legal);
649 setOperationAction(ISD::LOAD, MVT::v8i8, Promote);
650 AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v1i64);
651 setOperationAction(ISD::LOAD, MVT::v4i16, Promote);
652 AddPromotedToType (ISD::LOAD, MVT::v4i16, MVT::v1i64);
653 setOperationAction(ISD::LOAD, MVT::v2i32, Promote);
654 AddPromotedToType (ISD::LOAD, MVT::v2i32, MVT::v1i64);
655 setOperationAction(ISD::LOAD, MVT::v2f32, Promote);
656 AddPromotedToType (ISD::LOAD, MVT::v2f32, MVT::v1i64);
657 setOperationAction(ISD::LOAD, MVT::v1i64, Legal);
659 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Custom);
660 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom);
661 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Custom);
662 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f32, Custom);
663 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i64, Custom);
665 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom);
666 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
667 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i32, Custom);
668 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v1i64, Custom);
670 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f32, Custom);
671 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Custom);
672 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Custom);
673 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Custom);
675 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i16, Custom);
677 setTruncStoreAction(MVT::v8i16, MVT::v8i8, Expand);
678 setOperationAction(ISD::TRUNCATE, MVT::v8i8, Expand);
679 setOperationAction(ISD::SELECT, MVT::v8i8, Promote);
680 setOperationAction(ISD::SELECT, MVT::v4i16, Promote);
681 setOperationAction(ISD::SELECT, MVT::v2i32, Promote);
682 setOperationAction(ISD::SELECT, MVT::v1i64, Custom);
683 setOperationAction(ISD::VSETCC, MVT::v8i8, Custom);
684 setOperationAction(ISD::VSETCC, MVT::v4i16, Custom);
685 setOperationAction(ISD::VSETCC, MVT::v2i32, Custom);
688 if (!UseSoftFloat && Subtarget->hasSSE1()) {
689 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
691 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
692 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
693 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
694 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
695 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
696 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
697 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
698 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
699 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
700 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
701 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
702 setOperationAction(ISD::VSETCC, MVT::v4f32, Custom);
705 if (!UseSoftFloat && Subtarget->hasSSE2()) {
706 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
708 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
709 // registers cannot be used even for integer operations.
710 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
711 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
712 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
713 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
715 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
716 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
717 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
718 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
719 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
720 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
721 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
722 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
723 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
724 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
725 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
726 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
727 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
728 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
729 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
730 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
732 setOperationAction(ISD::VSETCC, MVT::v2f64, Custom);
733 setOperationAction(ISD::VSETCC, MVT::v16i8, Custom);
734 setOperationAction(ISD::VSETCC, MVT::v8i16, Custom);
735 setOperationAction(ISD::VSETCC, MVT::v4i32, Custom);
737 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
738 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
739 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
740 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
741 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
743 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
744 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) {
745 EVT VT = (MVT::SimpleValueType)i;
746 // Do not attempt to custom lower non-power-of-2 vectors
747 if (!isPowerOf2_32(VT.getVectorNumElements()))
749 // Do not attempt to custom lower non-128-bit vectors
750 if (!VT.is128BitVector())
752 setOperationAction(ISD::BUILD_VECTOR,
753 VT.getSimpleVT().SimpleTy, Custom);
754 setOperationAction(ISD::VECTOR_SHUFFLE,
755 VT.getSimpleVT().SimpleTy, Custom);
756 setOperationAction(ISD::EXTRACT_VECTOR_ELT,
757 VT.getSimpleVT().SimpleTy, Custom);
760 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
761 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
762 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
763 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
764 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
765 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
767 if (Subtarget->is64Bit()) {
768 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
769 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
772 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
773 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) {
774 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
777 // Do not attempt to promote non-128-bit vectors
778 if (!VT.is128BitVector()) {
781 setOperationAction(ISD::AND, SVT, Promote);
782 AddPromotedToType (ISD::AND, SVT, MVT::v2i64);
783 setOperationAction(ISD::OR, SVT, Promote);
784 AddPromotedToType (ISD::OR, SVT, MVT::v2i64);
785 setOperationAction(ISD::XOR, SVT, Promote);
786 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64);
787 setOperationAction(ISD::LOAD, SVT, Promote);
788 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64);
789 setOperationAction(ISD::SELECT, SVT, Promote);
790 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64);
793 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
795 // Custom lower v2i64 and v2f64 selects.
796 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
797 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
798 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
799 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
801 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
802 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
803 if (!DisableMMX && Subtarget->hasMMX()) {
804 setOperationAction(ISD::FP_TO_SINT, MVT::v2i32, Custom);
805 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
809 if (Subtarget->hasSSE41()) {
810 // FIXME: Do we need to handle scalar-to-vector here?
811 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
813 // i8 and i16 vectors are custom , because the source register and source
814 // source memory operand types are not the same width. f32 vectors are
815 // custom since the immediate controlling the insert encodes additional
817 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
818 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
819 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
820 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
822 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
823 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
824 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
825 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
827 if (Subtarget->is64Bit()) {
828 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal);
829 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal);
833 if (Subtarget->hasSSE42()) {
834 setOperationAction(ISD::VSETCC, MVT::v2i64, Custom);
837 if (!UseSoftFloat && Subtarget->hasAVX()) {
838 addRegisterClass(MVT::v8f32, X86::VR256RegisterClass);
839 addRegisterClass(MVT::v4f64, X86::VR256RegisterClass);
840 addRegisterClass(MVT::v8i32, X86::VR256RegisterClass);
841 addRegisterClass(MVT::v4i64, X86::VR256RegisterClass);
843 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
844 setOperationAction(ISD::LOAD, MVT::v8i32, Legal);
845 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
846 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
847 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
848 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
849 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
850 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
851 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
852 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
853 //setOperationAction(ISD::BUILD_VECTOR, MVT::v8f32, Custom);
854 //setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Custom);
855 //setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8f32, Custom);
856 //setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
857 //setOperationAction(ISD::VSETCC, MVT::v8f32, Custom);
859 // Operations to consider commented out -v16i16 v32i8
860 //setOperationAction(ISD::ADD, MVT::v16i16, Legal);
861 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
862 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
863 //setOperationAction(ISD::SUB, MVT::v32i8, Legal);
864 //setOperationAction(ISD::SUB, MVT::v16i16, Legal);
865 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
866 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
867 //setOperationAction(ISD::MUL, MVT::v16i16, Legal);
868 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
869 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
870 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
871 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
872 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
873 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
875 setOperationAction(ISD::VSETCC, MVT::v4f64, Custom);
876 // setOperationAction(ISD::VSETCC, MVT::v32i8, Custom);
877 // setOperationAction(ISD::VSETCC, MVT::v16i16, Custom);
878 setOperationAction(ISD::VSETCC, MVT::v8i32, Custom);
880 // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v32i8, Custom);
881 // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i16, Custom);
882 // setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i16, Custom);
883 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i32, Custom);
884 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8f32, Custom);
886 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f64, Custom);
887 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i64, Custom);
888 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f64, Custom);
889 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i64, Custom);
890 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f64, Custom);
891 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f64, Custom);
894 // Not sure we want to do this since there are no 256-bit integer
897 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
898 // This includes 256-bit vectors
899 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; ++i) {
900 EVT VT = (MVT::SimpleValueType)i;
902 // Do not attempt to custom lower non-power-of-2 vectors
903 if (!isPowerOf2_32(VT.getVectorNumElements()))
906 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
907 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
908 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
911 if (Subtarget->is64Bit()) {
912 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i64, Custom);
913 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i64, Custom);
918 // Not sure we want to do this since there are no 256-bit integer
921 // Promote v32i8, v16i16, v8i32 load, select, and, or, xor to v4i64.
922 // Including 256-bit vectors
923 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; i++) {
924 EVT VT = (MVT::SimpleValueType)i;
926 if (!VT.is256BitVector()) {
929 setOperationAction(ISD::AND, VT, Promote);
930 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
931 setOperationAction(ISD::OR, VT, Promote);
932 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
933 setOperationAction(ISD::XOR, VT, Promote);
934 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
935 setOperationAction(ISD::LOAD, VT, Promote);
936 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
937 setOperationAction(ISD::SELECT, VT, Promote);
938 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
941 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
945 // We want to custom lower some of our intrinsics.
946 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
948 // Add/Sub/Mul with overflow operations are custom lowered.
949 setOperationAction(ISD::SADDO, MVT::i32, Custom);
950 setOperationAction(ISD::SADDO, MVT::i64, Custom);
951 setOperationAction(ISD::UADDO, MVT::i32, Custom);
952 setOperationAction(ISD::UADDO, MVT::i64, Custom);
953 setOperationAction(ISD::SSUBO, MVT::i32, Custom);
954 setOperationAction(ISD::SSUBO, MVT::i64, Custom);
955 setOperationAction(ISD::USUBO, MVT::i32, Custom);
956 setOperationAction(ISD::USUBO, MVT::i64, Custom);
957 setOperationAction(ISD::SMULO, MVT::i32, Custom);
958 setOperationAction(ISD::SMULO, MVT::i64, Custom);
960 if (!Subtarget->is64Bit()) {
961 // These libcalls are not available in 32-bit.
962 setLibcallName(RTLIB::SHL_I128, 0);
963 setLibcallName(RTLIB::SRL_I128, 0);
964 setLibcallName(RTLIB::SRA_I128, 0);
967 // We have target-specific dag combine patterns for the following nodes:
968 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
969 setTargetDAGCombine(ISD::BUILD_VECTOR);
970 setTargetDAGCombine(ISD::SELECT);
971 setTargetDAGCombine(ISD::SHL);
972 setTargetDAGCombine(ISD::SRA);
973 setTargetDAGCombine(ISD::SRL);
974 setTargetDAGCombine(ISD::STORE);
975 setTargetDAGCombine(ISD::MEMBARRIER);
976 if (Subtarget->is64Bit())
977 setTargetDAGCombine(ISD::MUL);
979 computeRegisterProperties();
981 // FIXME: These should be based on subtarget info. Plus, the values should
982 // be smaller when we are in optimizing for size mode.
983 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
984 maxStoresPerMemcpy = 16; // For @llvm.memcpy -> sequence of stores
985 maxStoresPerMemmove = 3; // For @llvm.memmove -> sequence of stores
986 setPrefLoopAlignment(16);
987 benefitFromCodePlacementOpt = true;
991 MVT::SimpleValueType X86TargetLowering::getSetCCResultType(EVT VT) const {
996 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
997 /// the desired ByVal argument alignment.
998 static void getMaxByValAlign(const Type *Ty, unsigned &MaxAlign) {
1001 if (const VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1002 if (VTy->getBitWidth() == 128)
1004 } else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1005 unsigned EltAlign = 0;
1006 getMaxByValAlign(ATy->getElementType(), EltAlign);
1007 if (EltAlign > MaxAlign)
1008 MaxAlign = EltAlign;
1009 } else if (const StructType *STy = dyn_cast<StructType>(Ty)) {
1010 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1011 unsigned EltAlign = 0;
1012 getMaxByValAlign(STy->getElementType(i), EltAlign);
1013 if (EltAlign > MaxAlign)
1014 MaxAlign = EltAlign;
1022 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1023 /// function arguments in the caller parameter area. For X86, aggregates
1024 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1025 /// are at 4-byte boundaries.
1026 unsigned X86TargetLowering::getByValTypeAlignment(const Type *Ty) const {
1027 if (Subtarget->is64Bit()) {
1028 // Max of 8 and alignment of type.
1029 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1036 if (Subtarget->hasSSE1())
1037 getMaxByValAlign(Ty, Align);
1041 /// getOptimalMemOpType - Returns the target specific optimal type for load
1042 /// and store operations as a result of memset, memcpy, and memmove
1043 /// lowering. It returns MVT::iAny if SelectionDAG should be responsible for
1046 X86TargetLowering::getOptimalMemOpType(uint64_t Size, unsigned Align,
1047 bool isSrcConst, bool isSrcStr,
1048 SelectionDAG &DAG) const {
1049 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like
1050 // linux. This is because the stack realignment code can't handle certain
1051 // cases like PR2962. This should be removed when PR2962 is fixed.
1052 const Function *F = DAG.getMachineFunction().getFunction();
1053 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
1054 if (!NoImplicitFloatOps && Subtarget->getStackAlignment() >= 16) {
1055 if ((isSrcConst || isSrcStr) && Subtarget->hasSSE2() && Size >= 16)
1057 if ((isSrcConst || isSrcStr) && Subtarget->hasSSE1() && Size >= 16)
1060 if (Subtarget->is64Bit() && Size >= 8)
1065 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1067 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1068 SelectionDAG &DAG) const {
1069 if (usesGlobalOffsetTable())
1070 return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy());
1071 if (!Subtarget->is64Bit())
1072 // This doesn't have DebugLoc associated with it, but is not really the
1073 // same as a Register.
1074 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc::getUnknownLoc(),
1079 /// getFunctionAlignment - Return the Log2 alignment of this function.
1080 unsigned X86TargetLowering::getFunctionAlignment(const Function *F) const {
1081 return F->hasFnAttr(Attribute::OptimizeForSize) ? 0 : 4;
1084 //===----------------------------------------------------------------------===//
1085 // Return Value Calling Convention Implementation
1086 //===----------------------------------------------------------------------===//
1088 #include "X86GenCallingConv.inc"
1091 X86TargetLowering::LowerReturn(SDValue Chain,
1092 CallingConv::ID CallConv, bool isVarArg,
1093 const SmallVectorImpl<ISD::OutputArg> &Outs,
1094 DebugLoc dl, SelectionDAG &DAG) {
1096 SmallVector<CCValAssign, 16> RVLocs;
1097 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1098 RVLocs, *DAG.getContext());
1099 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1101 // If this is the first return lowered for this function, add the regs to the
1102 // liveout set for the function.
1103 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1104 for (unsigned i = 0; i != RVLocs.size(); ++i)
1105 if (RVLocs[i].isRegLoc())
1106 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1111 SmallVector<SDValue, 6> RetOps;
1112 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1113 // Operand #1 = Bytes To Pop
1114 RetOps.push_back(DAG.getTargetConstant(getBytesToPopOnReturn(), MVT::i16));
1116 // Copy the result values into the output registers.
1117 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1118 CCValAssign &VA = RVLocs[i];
1119 assert(VA.isRegLoc() && "Can only return in registers!");
1120 SDValue ValToCopy = Outs[i].Val;
1122 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1123 // the RET instruction and handled by the FP Stackifier.
1124 if (VA.getLocReg() == X86::ST0 ||
1125 VA.getLocReg() == X86::ST1) {
1126 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1127 // change the value to the FP stack register class.
1128 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1129 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1130 RetOps.push_back(ValToCopy);
1131 // Don't emit a copytoreg.
1135 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1136 // which is returned in RAX / RDX.
1137 if (Subtarget->is64Bit()) {
1138 EVT ValVT = ValToCopy.getValueType();
1139 if (ValVT.isVector() && ValVT.getSizeInBits() == 64) {
1140 ValToCopy = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, ValToCopy);
1141 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1)
1142 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, ValToCopy);
1146 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1147 Flag = Chain.getValue(1);
1150 // The x86-64 ABI for returning structs by value requires that we copy
1151 // the sret argument into %rax for the return. We saved the argument into
1152 // a virtual register in the entry block, so now we copy the value out
1154 if (Subtarget->is64Bit() &&
1155 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1156 MachineFunction &MF = DAG.getMachineFunction();
1157 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1158 unsigned Reg = FuncInfo->getSRetReturnReg();
1160 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1161 FuncInfo->setSRetReturnReg(Reg);
1163 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1165 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag);
1166 Flag = Chain.getValue(1);
1168 // RAX now acts like a return value.
1169 MF.getRegInfo().addLiveOut(X86::RAX);
1172 RetOps[0] = Chain; // Update chain.
1174 // Add the flag if we have it.
1176 RetOps.push_back(Flag);
1178 return DAG.getNode(X86ISD::RET_FLAG, dl,
1179 MVT::Other, &RetOps[0], RetOps.size());
1182 /// LowerCallResult - Lower the result values of a call into the
1183 /// appropriate copies out of appropriate physical registers.
1186 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1187 CallingConv::ID CallConv, bool isVarArg,
1188 const SmallVectorImpl<ISD::InputArg> &Ins,
1189 DebugLoc dl, SelectionDAG &DAG,
1190 SmallVectorImpl<SDValue> &InVals) {
1192 // Assign locations to each value returned by this call.
1193 SmallVector<CCValAssign, 16> RVLocs;
1194 bool Is64Bit = Subtarget->is64Bit();
1195 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1196 RVLocs, *DAG.getContext());
1197 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1199 // Copy all of the result registers out of their specified physreg.
1200 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1201 CCValAssign &VA = RVLocs[i];
1202 EVT CopyVT = VA.getValVT();
1204 // If this is x86-64, and we disabled SSE, we can't return FP values
1205 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1206 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
1207 llvm_report_error("SSE register return with SSE disabled");
1210 // If this is a call to a function that returns an fp value on the floating
1211 // point stack, but where we prefer to use the value in xmm registers, copy
1212 // it out as F80 and use a truncate to move it from fp stack reg to xmm reg.
1213 if ((VA.getLocReg() == X86::ST0 ||
1214 VA.getLocReg() == X86::ST1) &&
1215 isScalarFPTypeInSSEReg(VA.getValVT())) {
1220 if (Is64Bit && CopyVT.isVector() && CopyVT.getSizeInBits() == 64) {
1221 // For x86-64, MMX values are returned in XMM0 / XMM1 except for v1i64.
1222 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1223 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1224 MVT::v2i64, InFlag).getValue(1);
1225 Val = Chain.getValue(0);
1226 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64,
1227 Val, DAG.getConstant(0, MVT::i64));
1229 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1230 MVT::i64, InFlag).getValue(1);
1231 Val = Chain.getValue(0);
1233 Val = DAG.getNode(ISD::BIT_CONVERT, dl, CopyVT, Val);
1235 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1236 CopyVT, InFlag).getValue(1);
1237 Val = Chain.getValue(0);
1239 InFlag = Chain.getValue(2);
1241 if (CopyVT != VA.getValVT()) {
1242 // Round the F80 the right size, which also moves to the appropriate xmm
1244 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1245 // This truncation won't change the value.
1246 DAG.getIntPtrConstant(1));
1249 InVals.push_back(Val);
1256 //===----------------------------------------------------------------------===//
1257 // C & StdCall & Fast Calling Convention implementation
1258 //===----------------------------------------------------------------------===//
1259 // StdCall calling convention seems to be standard for many Windows' API
1260 // routines and around. It differs from C calling convention just a little:
1261 // callee should clean up the stack, not caller. Symbols should be also
1262 // decorated in some fancy way :) It doesn't support any vector arguments.
1263 // For info on fast calling convention see Fast Calling Convention (tail call)
1264 // implementation LowerX86_32FastCCCallTo.
1266 /// CallIsStructReturn - Determines whether a call uses struct return
1268 static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
1272 return Outs[0].Flags.isSRet();
1275 /// ArgsAreStructReturn - Determines whether a function uses struct
1276 /// return semantics.
1278 ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
1282 return Ins[0].Flags.isSRet();
1285 /// IsCalleePop - Determines whether the callee is required to pop its
1286 /// own arguments. Callee pop is necessary to support tail calls.
1287 bool X86TargetLowering::IsCalleePop(bool IsVarArg, CallingConv::ID CallingConv){
1291 switch (CallingConv) {
1294 case CallingConv::X86_StdCall:
1295 return !Subtarget->is64Bit();
1296 case CallingConv::X86_FastCall:
1297 return !Subtarget->is64Bit();
1298 case CallingConv::Fast:
1299 return PerformTailCallOpt;
1303 /// CCAssignFnForNode - Selects the correct CCAssignFn for a the
1304 /// given CallingConvention value.
1305 CCAssignFn *X86TargetLowering::CCAssignFnForNode(CallingConv::ID CC) const {
1306 if (Subtarget->is64Bit()) {
1307 if (Subtarget->isTargetWin64())
1308 return CC_X86_Win64_C;
1313 if (CC == CallingConv::X86_FastCall)
1314 return CC_X86_32_FastCall;
1315 else if (CC == CallingConv::Fast)
1316 return CC_X86_32_FastCC;
1321 /// NameDecorationForCallConv - Selects the appropriate decoration to
1322 /// apply to a MachineFunction containing a given calling convention.
1324 X86TargetLowering::NameDecorationForCallConv(CallingConv::ID CallConv) {
1325 if (CallConv == CallingConv::X86_FastCall)
1327 else if (CallConv == CallingConv::X86_StdCall)
1333 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1334 /// by "Src" to address "Dst" with size and alignment information specified by
1335 /// the specific parameter attribute. The copy will be passed as a byval
1336 /// function parameter.
1338 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1339 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1341 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1342 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1343 /*AlwaysInline=*/true, NULL, 0, NULL, 0);
1347 X86TargetLowering::LowerMemArgument(SDValue Chain,
1348 CallingConv::ID CallConv,
1349 const SmallVectorImpl<ISD::InputArg> &Ins,
1350 DebugLoc dl, SelectionDAG &DAG,
1351 const CCValAssign &VA,
1352 MachineFrameInfo *MFI,
1355 // Create the nodes corresponding to a load from this parameter slot.
1356 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1357 bool AlwaysUseMutable = (CallConv==CallingConv::Fast) && PerformTailCallOpt;
1358 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1361 // If value is passed by pointer we have address passed instead of the value
1363 if (VA.getLocInfo() == CCValAssign::Indirect)
1364 ValVT = VA.getLocVT();
1366 ValVT = VA.getValVT();
1368 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1369 // changed with more analysis.
1370 // In case of tail call optimization mark all arguments mutable. Since they
1371 // could be overwritten by lowering of arguments in case of a tail call.
1372 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
1373 VA.getLocMemOffset(), isImmutable);
1374 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1375 if (Flags.isByVal())
1377 return DAG.getLoad(ValVT, dl, Chain, FIN,
1378 PseudoSourceValue::getFixedStack(FI), 0);
1382 X86TargetLowering::LowerFormalArguments(SDValue Chain,
1383 CallingConv::ID CallConv,
1385 const SmallVectorImpl<ISD::InputArg> &Ins,
1388 SmallVectorImpl<SDValue> &InVals) {
1390 MachineFunction &MF = DAG.getMachineFunction();
1391 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1393 const Function* Fn = MF.getFunction();
1394 if (Fn->hasExternalLinkage() &&
1395 Subtarget->isTargetCygMing() &&
1396 Fn->getName() == "main")
1397 FuncInfo->setForceFramePointer(true);
1399 // Decorate the function name.
1400 FuncInfo->setDecorationStyle(NameDecorationForCallConv(CallConv));
1402 MachineFrameInfo *MFI = MF.getFrameInfo();
1403 bool Is64Bit = Subtarget->is64Bit();
1404 bool IsWin64 = Subtarget->isTargetWin64();
1406 assert(!(isVarArg && CallConv == CallingConv::Fast) &&
1407 "Var args not supported with calling convention fastcc");
1409 // Assign locations to all of the incoming arguments.
1410 SmallVector<CCValAssign, 16> ArgLocs;
1411 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1412 ArgLocs, *DAG.getContext());
1413 CCInfo.AnalyzeFormalArguments(Ins, CCAssignFnForNode(CallConv));
1415 unsigned LastVal = ~0U;
1417 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1418 CCValAssign &VA = ArgLocs[i];
1419 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1421 assert(VA.getValNo() != LastVal &&
1422 "Don't support value assigned to multiple locs yet");
1423 LastVal = VA.getValNo();
1425 if (VA.isRegLoc()) {
1426 EVT RegVT = VA.getLocVT();
1427 TargetRegisterClass *RC = NULL;
1428 if (RegVT == MVT::i32)
1429 RC = X86::GR32RegisterClass;
1430 else if (Is64Bit && RegVT == MVT::i64)
1431 RC = X86::GR64RegisterClass;
1432 else if (RegVT == MVT::f32)
1433 RC = X86::FR32RegisterClass;
1434 else if (RegVT == MVT::f64)
1435 RC = X86::FR64RegisterClass;
1436 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128)
1437 RC = X86::VR128RegisterClass;
1438 else if (RegVT.isVector() && RegVT.getSizeInBits() == 64)
1439 RC = X86::VR64RegisterClass;
1441 llvm_unreachable("Unknown argument type!");
1443 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1444 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1446 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1447 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1449 if (VA.getLocInfo() == CCValAssign::SExt)
1450 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1451 DAG.getValueType(VA.getValVT()));
1452 else if (VA.getLocInfo() == CCValAssign::ZExt)
1453 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1454 DAG.getValueType(VA.getValVT()));
1455 else if (VA.getLocInfo() == CCValAssign::BCvt)
1456 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue);
1458 if (VA.isExtInLoc()) {
1459 // Handle MMX values passed in XMM regs.
1460 if (RegVT.isVector()) {
1461 ArgValue = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64,
1462 ArgValue, DAG.getConstant(0, MVT::i64));
1463 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue);
1465 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1468 assert(VA.isMemLoc());
1469 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
1472 // If value is passed via pointer - do a load.
1473 if (VA.getLocInfo() == CCValAssign::Indirect)
1474 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue, NULL, 0);
1476 InVals.push_back(ArgValue);
1479 // The x86-64 ABI for returning structs by value requires that we copy
1480 // the sret argument into %rax for the return. Save the argument into
1481 // a virtual register so that we can access it from the return points.
1482 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) {
1483 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1484 unsigned Reg = FuncInfo->getSRetReturnReg();
1486 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1487 FuncInfo->setSRetReturnReg(Reg);
1489 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
1490 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
1493 unsigned StackSize = CCInfo.getNextStackOffset();
1494 // align stack specially for tail calls
1495 if (PerformTailCallOpt && CallConv == CallingConv::Fast)
1496 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1498 // If the function takes variable number of arguments, make a frame index for
1499 // the start of the first vararg value... for expansion of llvm.va_start.
1501 if (Is64Bit || CallConv != CallingConv::X86_FastCall) {
1502 VarArgsFrameIndex = MFI->CreateFixedObject(1, StackSize);
1505 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
1507 // FIXME: We should really autogenerate these arrays
1508 static const unsigned GPR64ArgRegsWin64[] = {
1509 X86::RCX, X86::RDX, X86::R8, X86::R9
1511 static const unsigned XMMArgRegsWin64[] = {
1512 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
1514 static const unsigned GPR64ArgRegs64Bit[] = {
1515 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1517 static const unsigned XMMArgRegs64Bit[] = {
1518 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1519 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1521 const unsigned *GPR64ArgRegs, *XMMArgRegs;
1524 TotalNumIntRegs = 4; TotalNumXMMRegs = 4;
1525 GPR64ArgRegs = GPR64ArgRegsWin64;
1526 XMMArgRegs = XMMArgRegsWin64;
1528 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
1529 GPR64ArgRegs = GPR64ArgRegs64Bit;
1530 XMMArgRegs = XMMArgRegs64Bit;
1532 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
1534 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs,
1537 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat);
1538 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
1539 "SSE register cannot be used when SSE is disabled!");
1540 assert(!(NumXMMRegs && UseSoftFloat && NoImplicitFloatOps) &&
1541 "SSE register cannot be used when SSE is disabled!");
1542 if (UseSoftFloat || NoImplicitFloatOps || !Subtarget->hasSSE1())
1543 // Kernel mode asks for SSE to be disabled, so don't push them
1545 TotalNumXMMRegs = 0;
1547 // For X86-64, if there are vararg parameters that are passed via
1548 // registers, then we must store them to their spots on the stack so they
1549 // may be loaded by deferencing the result of va_next.
1550 VarArgsGPOffset = NumIntRegs * 8;
1551 VarArgsFPOffset = TotalNumIntRegs * 8 + NumXMMRegs * 16;
1552 RegSaveFrameIndex = MFI->CreateStackObject(TotalNumIntRegs * 8 +
1553 TotalNumXMMRegs * 16, 16);
1555 // Store the integer parameter registers.
1556 SmallVector<SDValue, 8> MemOps;
1557 SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
1558 unsigned Offset = VarArgsGPOffset;
1559 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
1560 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
1561 DAG.getIntPtrConstant(Offset));
1562 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
1563 X86::GR64RegisterClass);
1564 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
1566 DAG.getStore(Val.getValue(1), dl, Val, FIN,
1567 PseudoSourceValue::getFixedStack(RegSaveFrameIndex),
1569 MemOps.push_back(Store);
1573 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
1574 // Now store the XMM (fp + vector) parameter registers.
1575 SmallVector<SDValue, 11> SaveXMMOps;
1576 SaveXMMOps.push_back(Chain);
1578 unsigned AL = MF.addLiveIn(X86::AL, X86::GR8RegisterClass);
1579 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
1580 SaveXMMOps.push_back(ALVal);
1582 SaveXMMOps.push_back(DAG.getIntPtrConstant(RegSaveFrameIndex));
1583 SaveXMMOps.push_back(DAG.getIntPtrConstant(VarArgsFPOffset));
1585 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
1586 unsigned VReg = MF.addLiveIn(XMMArgRegs[NumXMMRegs],
1587 X86::VR128RegisterClass);
1588 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
1589 SaveXMMOps.push_back(Val);
1591 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
1593 &SaveXMMOps[0], SaveXMMOps.size()));
1596 if (!MemOps.empty())
1597 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1598 &MemOps[0], MemOps.size());
1602 // Some CCs need callee pop.
1603 if (IsCalleePop(isVarArg, CallConv)) {
1604 BytesToPopOnReturn = StackSize; // Callee pops everything.
1605 BytesCallerReserves = 0;
1607 BytesToPopOnReturn = 0; // Callee pops nothing.
1608 // If this is an sret function, the return should pop the hidden pointer.
1609 if (!Is64Bit && CallConv != CallingConv::Fast && ArgsAreStructReturn(Ins))
1610 BytesToPopOnReturn = 4;
1611 BytesCallerReserves = StackSize;
1615 RegSaveFrameIndex = 0xAAAAAAA; // RegSaveFrameIndex is X86-64 only.
1616 if (CallConv == CallingConv::X86_FastCall)
1617 VarArgsFrameIndex = 0xAAAAAAA; // fastcc functions can't have varargs.
1620 FuncInfo->setBytesToPopOnReturn(BytesToPopOnReturn);
1626 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
1627 SDValue StackPtr, SDValue Arg,
1628 DebugLoc dl, SelectionDAG &DAG,
1629 const CCValAssign &VA,
1630 ISD::ArgFlagsTy Flags) {
1631 const unsigned FirstStackArgOffset = (Subtarget->isTargetWin64() ? 32 : 0);
1632 unsigned LocMemOffset = FirstStackArgOffset + VA.getLocMemOffset();
1633 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1634 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1635 if (Flags.isByVal()) {
1636 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
1638 return DAG.getStore(Chain, dl, Arg, PtrOff,
1639 PseudoSourceValue::getStack(), LocMemOffset);
1642 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
1643 /// optimization is performed and it is required.
1645 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
1646 SDValue &OutRetAddr,
1652 if (!IsTailCall || FPDiff==0) return Chain;
1654 // Adjust the Return address stack slot.
1655 EVT VT = getPointerTy();
1656 OutRetAddr = getReturnAddressFrameIndex(DAG);
1658 // Load the "old" Return address.
1659 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, NULL, 0);
1660 return SDValue(OutRetAddr.getNode(), 1);
1663 /// EmitTailCallStoreRetAddr - Emit a store of the return adress if tail call
1664 /// optimization is performed and it is required (FPDiff!=0).
1666 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
1667 SDValue Chain, SDValue RetAddrFrIdx,
1668 bool Is64Bit, int FPDiff, DebugLoc dl) {
1669 // Store the return address to the appropriate stack slot.
1670 if (!FPDiff) return Chain;
1671 // Calculate the new stack slot for the return address.
1672 int SlotSize = Is64Bit ? 8 : 4;
1673 int NewReturnAddrFI =
1674 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize);
1675 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
1676 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
1677 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
1678 PseudoSourceValue::getFixedStack(NewReturnAddrFI), 0);
1683 X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
1684 CallingConv::ID CallConv, bool isVarArg,
1686 const SmallVectorImpl<ISD::OutputArg> &Outs,
1687 const SmallVectorImpl<ISD::InputArg> &Ins,
1688 DebugLoc dl, SelectionDAG &DAG,
1689 SmallVectorImpl<SDValue> &InVals) {
1691 MachineFunction &MF = DAG.getMachineFunction();
1692 bool Is64Bit = Subtarget->is64Bit();
1693 bool IsStructRet = CallIsStructReturn(Outs);
1695 assert((!isTailCall ||
1696 (CallConv == CallingConv::Fast && PerformTailCallOpt)) &&
1697 "IsEligibleForTailCallOptimization missed a case!");
1698 assert(!(isVarArg && CallConv == CallingConv::Fast) &&
1699 "Var args not supported with calling convention fastcc");
1701 // Analyze operands of the call, assigning locations to each operand.
1702 SmallVector<CCValAssign, 16> ArgLocs;
1703 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1704 ArgLocs, *DAG.getContext());
1705 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForNode(CallConv));
1707 // Get a count of how many bytes are to be pushed on the stack.
1708 unsigned NumBytes = CCInfo.getNextStackOffset();
1709 if (PerformTailCallOpt && CallConv == CallingConv::Fast)
1710 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
1714 // Lower arguments at fp - stackoffset + fpdiff.
1715 unsigned NumBytesCallerPushed =
1716 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
1717 FPDiff = NumBytesCallerPushed - NumBytes;
1719 // Set the delta of movement of the returnaddr stackslot.
1720 // But only set if delta is greater than previous delta.
1721 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
1722 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
1725 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
1727 SDValue RetAddrFrIdx;
1728 // Load return adress for tail calls.
1729 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall, Is64Bit,
1732 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
1733 SmallVector<SDValue, 8> MemOpChains;
1736 // Walk the register/memloc assignments, inserting copies/loads. In the case
1737 // of tail call optimization arguments are handle later.
1738 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1739 CCValAssign &VA = ArgLocs[i];
1740 EVT RegVT = VA.getLocVT();
1741 SDValue Arg = Outs[i].Val;
1742 ISD::ArgFlagsTy Flags = Outs[i].Flags;
1743 bool isByVal = Flags.isByVal();
1745 // Promote the value if needed.
1746 switch (VA.getLocInfo()) {
1747 default: llvm_unreachable("Unknown loc info!");
1748 case CCValAssign::Full: break;
1749 case CCValAssign::SExt:
1750 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
1752 case CCValAssign::ZExt:
1753 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
1755 case CCValAssign::AExt:
1756 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) {
1757 // Special case: passing MMX values in XMM registers.
1758 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, Arg);
1759 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
1760 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
1762 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
1764 case CCValAssign::BCvt:
1765 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, RegVT, Arg);
1767 case CCValAssign::Indirect: {
1768 // Store the argument.
1769 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
1770 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
1771 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
1772 PseudoSourceValue::getFixedStack(FI), 0);
1778 if (VA.isRegLoc()) {
1779 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1781 if (!isTailCall || (isTailCall && isByVal)) {
1782 assert(VA.isMemLoc());
1783 if (StackPtr.getNode() == 0)
1784 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy());
1786 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
1787 dl, DAG, VA, Flags));
1792 if (!MemOpChains.empty())
1793 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1794 &MemOpChains[0], MemOpChains.size());
1796 // Build a sequence of copy-to-reg nodes chained together with token chain
1797 // and flag operands which copy the outgoing args into registers.
1799 // Tail call byval lowering might overwrite argument registers so in case of
1800 // tail call optimization the copies to registers are lowered later.
1802 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1803 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1804 RegsToPass[i].second, InFlag);
1805 InFlag = Chain.getValue(1);
1809 if (Subtarget->isPICStyleGOT()) {
1810 // ELF / PIC requires GOT in the EBX register before function calls via PLT
1813 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX,
1814 DAG.getNode(X86ISD::GlobalBaseReg,
1815 DebugLoc::getUnknownLoc(),
1818 InFlag = Chain.getValue(1);
1820 // If we are tail calling and generating PIC/GOT style code load the
1821 // address of the callee into ECX. The value in ecx is used as target of
1822 // the tail jump. This is done to circumvent the ebx/callee-saved problem
1823 // for tail calls on PIC/GOT architectures. Normally we would just put the
1824 // address of GOT into ebx and then call target@PLT. But for tail calls
1825 // ebx would be restored (since ebx is callee saved) before jumping to the
1828 // Note: The actual moving to ECX is done further down.
1829 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
1830 if (G && !G->getGlobal()->hasHiddenVisibility() &&
1831 !G->getGlobal()->hasProtectedVisibility())
1832 Callee = LowerGlobalAddress(Callee, DAG);
1833 else if (isa<ExternalSymbolSDNode>(Callee))
1834 Callee = LowerExternalSymbol(Callee, DAG);
1838 if (Is64Bit && isVarArg) {
1839 // From AMD64 ABI document:
1840 // For calls that may call functions that use varargs or stdargs
1841 // (prototype-less calls or calls to functions containing ellipsis (...) in
1842 // the declaration) %al is used as hidden argument to specify the number
1843 // of SSE registers used. The contents of %al do not need to match exactly
1844 // the number of registers, but must be an ubound on the number of SSE
1845 // registers used and is in the range 0 - 8 inclusive.
1847 // FIXME: Verify this on Win64
1848 // Count the number of XMM registers allocated.
1849 static const unsigned XMMArgRegs[] = {
1850 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1851 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1853 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
1854 assert((Subtarget->hasSSE1() || !NumXMMRegs)
1855 && "SSE registers cannot be used when SSE is disabled");
1857 Chain = DAG.getCopyToReg(Chain, dl, X86::AL,
1858 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
1859 InFlag = Chain.getValue(1);
1863 // For tail calls lower the arguments to the 'real' stack slot.
1865 // Force all the incoming stack arguments to be loaded from the stack
1866 // before any new outgoing arguments are stored to the stack, because the
1867 // outgoing stack slots may alias the incoming argument stack slots, and
1868 // the alias isn't otherwise explicit. This is slightly more conservative
1869 // than necessary, because it means that each store effectively depends
1870 // on every argument instead of just those arguments it would clobber.
1871 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
1873 SmallVector<SDValue, 8> MemOpChains2;
1876 // Do not flag preceeding copytoreg stuff together with the following stuff.
1878 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1879 CCValAssign &VA = ArgLocs[i];
1880 if (!VA.isRegLoc()) {
1881 assert(VA.isMemLoc());
1882 SDValue Arg = Outs[i].Val;
1883 ISD::ArgFlagsTy Flags = Outs[i].Flags;
1884 // Create frame index.
1885 int32_t Offset = VA.getLocMemOffset()+FPDiff;
1886 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
1887 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset);
1888 FIN = DAG.getFrameIndex(FI, getPointerTy());
1890 if (Flags.isByVal()) {
1891 // Copy relative to framepointer.
1892 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
1893 if (StackPtr.getNode() == 0)
1894 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr,
1896 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
1898 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
1902 // Store relative to framepointer.
1903 MemOpChains2.push_back(
1904 DAG.getStore(ArgChain, dl, Arg, FIN,
1905 PseudoSourceValue::getFixedStack(FI), 0));
1910 if (!MemOpChains2.empty())
1911 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1912 &MemOpChains2[0], MemOpChains2.size());
1914 // Copy arguments to their registers.
1915 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1916 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1917 RegsToPass[i].second, InFlag);
1918 InFlag = Chain.getValue(1);
1922 // Store the return address to the appropriate stack slot.
1923 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
1927 // If the callee is a GlobalAddress node (quite common, every direct call is)
1928 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
1929 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1930 // We should use extra load for direct calls to dllimported functions in
1932 GlobalValue *GV = G->getGlobal();
1933 if (!GV->hasDLLImportLinkage()) {
1934 unsigned char OpFlags = 0;
1936 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
1937 // external symbols most go through the PLT in PIC mode. If the symbol
1938 // has hidden or protected visibility, or if it is static or local, then
1939 // we don't need to use the PLT - we can directly call it.
1940 if (Subtarget->isTargetELF() &&
1941 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1942 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
1943 OpFlags = X86II::MO_PLT;
1944 } else if (Subtarget->isPICStyleStubAny() &&
1945 (GV->isDeclaration() || GV->isWeakForLinker()) &&
1946 Subtarget->getDarwinVers() < 9) {
1947 // PC-relative references to external symbols should go through $stub,
1948 // unless we're building with the leopard linker or later, which
1949 // automatically synthesizes these stubs.
1950 OpFlags = X86II::MO_DARWIN_STUB;
1953 Callee = DAG.getTargetGlobalAddress(GV, getPointerTy(),
1954 G->getOffset(), OpFlags);
1956 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1957 unsigned char OpFlags = 0;
1959 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to external
1960 // symbols should go through the PLT.
1961 if (Subtarget->isTargetELF() &&
1962 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
1963 OpFlags = X86II::MO_PLT;
1964 } else if (Subtarget->isPICStyleStubAny() &&
1965 Subtarget->getDarwinVers() < 9) {
1966 // PC-relative references to external symbols should go through $stub,
1967 // unless we're building with the leopard linker or later, which
1968 // automatically synthesizes these stubs.
1969 OpFlags = X86II::MO_DARWIN_STUB;
1972 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
1974 } else if (isTailCall) {
1975 unsigned Opc = Is64Bit ? X86::R11 : X86::EAX;
1977 Chain = DAG.getCopyToReg(Chain, dl,
1978 DAG.getRegister(Opc, getPointerTy()),
1980 Callee = DAG.getRegister(Opc, getPointerTy());
1981 // Add register as live out.
1982 MF.getRegInfo().addLiveOut(Opc);
1985 // Returns a chain & a flag for retval copy to use.
1986 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1987 SmallVector<SDValue, 8> Ops;
1990 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
1991 DAG.getIntPtrConstant(0, true), InFlag);
1992 InFlag = Chain.getValue(1);
1995 Ops.push_back(Chain);
1996 Ops.push_back(Callee);
1999 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2001 // Add argument registers to the end of the list so that they are known live
2003 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2004 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2005 RegsToPass[i].second.getValueType()));
2007 // Add an implicit use GOT pointer in EBX.
2008 if (!isTailCall && Subtarget->isPICStyleGOT())
2009 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
2011 // Add an implicit use of AL for x86 vararg functions.
2012 if (Is64Bit && isVarArg)
2013 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
2015 if (InFlag.getNode())
2016 Ops.push_back(InFlag);
2019 // If this is the first return lowered for this function, add the regs
2020 // to the liveout set for the function.
2021 if (MF.getRegInfo().liveout_empty()) {
2022 SmallVector<CCValAssign, 16> RVLocs;
2023 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs,
2025 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2026 for (unsigned i = 0; i != RVLocs.size(); ++i)
2027 if (RVLocs[i].isRegLoc())
2028 MF.getRegInfo().addLiveOut(RVLocs[i].getLocReg());
2031 assert(((Callee.getOpcode() == ISD::Register &&
2032 (cast<RegisterSDNode>(Callee)->getReg() == X86::EAX ||
2033 cast<RegisterSDNode>(Callee)->getReg() == X86::R9)) ||
2034 Callee.getOpcode() == ISD::TargetExternalSymbol ||
2035 Callee.getOpcode() == ISD::TargetGlobalAddress) &&
2036 "Expecting an global address, external symbol, or register");
2038 return DAG.getNode(X86ISD::TC_RETURN, dl,
2039 NodeTys, &Ops[0], Ops.size());
2042 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2043 InFlag = Chain.getValue(1);
2045 // Create the CALLSEQ_END node.
2046 unsigned NumBytesForCalleeToPush;
2047 if (IsCalleePop(isVarArg, CallConv))
2048 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2049 else if (!Is64Bit && CallConv != CallingConv::Fast && IsStructRet)
2050 // If this is is a call to a struct-return function, the callee
2051 // pops the hidden struct pointer, so we have to push it back.
2052 // This is common for Darwin/X86, Linux & Mingw32 targets.
2053 NumBytesForCalleeToPush = 4;
2055 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2057 // Returns a flag for retval copy to use.
2058 Chain = DAG.getCALLSEQ_END(Chain,
2059 DAG.getIntPtrConstant(NumBytes, true),
2060 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2063 InFlag = Chain.getValue(1);
2065 // Handle result values, copying them out of physregs into vregs that we
2067 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2068 Ins, dl, DAG, InVals);
2072 //===----------------------------------------------------------------------===//
2073 // Fast Calling Convention (tail call) implementation
2074 //===----------------------------------------------------------------------===//
2076 // Like std call, callee cleans arguments, convention except that ECX is
2077 // reserved for storing the tail called function address. Only 2 registers are
2078 // free for argument passing (inreg). Tail call optimization is performed
2080 // * tailcallopt is enabled
2081 // * caller/callee are fastcc
2082 // On X86_64 architecture with GOT-style position independent code only local
2083 // (within module) calls are supported at the moment.
2084 // To keep the stack aligned according to platform abi the function
2085 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2086 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2087 // If a tail called function callee has more arguments than the caller the
2088 // caller needs to make sure that there is room to move the RETADDR to. This is
2089 // achieved by reserving an area the size of the argument delta right after the
2090 // original REtADDR, but before the saved framepointer or the spilled registers
2091 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2103 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2104 /// for a 16 byte align requirement.
2105 unsigned X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2106 SelectionDAG& DAG) {
2107 MachineFunction &MF = DAG.getMachineFunction();
2108 const TargetMachine &TM = MF.getTarget();
2109 const TargetFrameInfo &TFI = *TM.getFrameInfo();
2110 unsigned StackAlignment = TFI.getStackAlignment();
2111 uint64_t AlignMask = StackAlignment - 1;
2112 int64_t Offset = StackSize;
2113 uint64_t SlotSize = TD->getPointerSize();
2114 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2115 // Number smaller than 12 so just add the difference.
2116 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2118 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2119 Offset = ((~AlignMask) & Offset) + StackAlignment +
2120 (StackAlignment-SlotSize);
2125 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2126 /// for tail call optimization. Targets which want to do tail call
2127 /// optimization should implement this function.
2129 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2130 CallingConv::ID CalleeCC,
2132 const SmallVectorImpl<ISD::InputArg> &Ins,
2133 SelectionDAG& DAG) const {
2134 MachineFunction &MF = DAG.getMachineFunction();
2135 CallingConv::ID CallerCC = MF.getFunction()->getCallingConv();
2136 return CalleeCC == CallingConv::Fast && CallerCC == CalleeCC;
2140 X86TargetLowering::createFastISel(MachineFunction &mf,
2141 MachineModuleInfo *mmo,
2143 DenseMap<const Value *, unsigned> &vm,
2144 DenseMap<const BasicBlock *,
2145 MachineBasicBlock *> &bm,
2146 DenseMap<const AllocaInst *, int> &am
2148 , SmallSet<Instruction*, 8> &cil
2151 return X86::createFastISel(mf, mmo, dw, vm, bm, am
2159 //===----------------------------------------------------------------------===//
2160 // Other Lowering Hooks
2161 //===----------------------------------------------------------------------===//
2164 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) {
2165 MachineFunction &MF = DAG.getMachineFunction();
2166 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2167 int ReturnAddrIndex = FuncInfo->getRAIndex();
2169 if (ReturnAddrIndex == 0) {
2170 // Set up a frame object for the return address.
2171 uint64_t SlotSize = TD->getPointerSize();
2172 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize);
2173 FuncInfo->setRAIndex(ReturnAddrIndex);
2176 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
2180 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
2181 bool hasSymbolicDisplacement) {
2182 // Offset should fit into 32 bit immediate field.
2183 if (!isInt32(Offset))
2186 // If we don't have a symbolic displacement - we don't have any extra
2188 if (!hasSymbolicDisplacement)
2191 // FIXME: Some tweaks might be needed for medium code model.
2192 if (M != CodeModel::Small && M != CodeModel::Kernel)
2195 // For small code model we assume that latest object is 16MB before end of 31
2196 // bits boundary. We may also accept pretty large negative constants knowing
2197 // that all objects are in the positive half of address space.
2198 if (M == CodeModel::Small && Offset < 16*1024*1024)
2201 // For kernel code model we know that all object resist in the negative half
2202 // of 32bits address space. We may not accept negative offsets, since they may
2203 // be just off and we may accept pretty large positive ones.
2204 if (M == CodeModel::Kernel && Offset > 0)
2210 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
2211 /// specific condition code, returning the condition code and the LHS/RHS of the
2212 /// comparison to make.
2213 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
2214 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
2216 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
2217 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
2218 // X > -1 -> X == 0, jump !sign.
2219 RHS = DAG.getConstant(0, RHS.getValueType());
2220 return X86::COND_NS;
2221 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
2222 // X < 0 -> X == 0, jump on sign.
2224 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
2226 RHS = DAG.getConstant(0, RHS.getValueType());
2227 return X86::COND_LE;
2231 switch (SetCCOpcode) {
2232 default: llvm_unreachable("Invalid integer condition!");
2233 case ISD::SETEQ: return X86::COND_E;
2234 case ISD::SETGT: return X86::COND_G;
2235 case ISD::SETGE: return X86::COND_GE;
2236 case ISD::SETLT: return X86::COND_L;
2237 case ISD::SETLE: return X86::COND_LE;
2238 case ISD::SETNE: return X86::COND_NE;
2239 case ISD::SETULT: return X86::COND_B;
2240 case ISD::SETUGT: return X86::COND_A;
2241 case ISD::SETULE: return X86::COND_BE;
2242 case ISD::SETUGE: return X86::COND_AE;
2246 // First determine if it is required or is profitable to flip the operands.
2248 // If LHS is a foldable load, but RHS is not, flip the condition.
2249 if ((ISD::isNON_EXTLoad(LHS.getNode()) && LHS.hasOneUse()) &&
2250 !(ISD::isNON_EXTLoad(RHS.getNode()) && RHS.hasOneUse())) {
2251 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
2252 std::swap(LHS, RHS);
2255 switch (SetCCOpcode) {
2261 std::swap(LHS, RHS);
2265 // On a floating point condition, the flags are set as follows:
2267 // 0 | 0 | 0 | X > Y
2268 // 0 | 0 | 1 | X < Y
2269 // 1 | 0 | 0 | X == Y
2270 // 1 | 1 | 1 | unordered
2271 switch (SetCCOpcode) {
2272 default: llvm_unreachable("Condcode should be pre-legalized away");
2274 case ISD::SETEQ: return X86::COND_E;
2275 case ISD::SETOLT: // flipped
2277 case ISD::SETGT: return X86::COND_A;
2278 case ISD::SETOLE: // flipped
2280 case ISD::SETGE: return X86::COND_AE;
2281 case ISD::SETUGT: // flipped
2283 case ISD::SETLT: return X86::COND_B;
2284 case ISD::SETUGE: // flipped
2286 case ISD::SETLE: return X86::COND_BE;
2288 case ISD::SETNE: return X86::COND_NE;
2289 case ISD::SETUO: return X86::COND_P;
2290 case ISD::SETO: return X86::COND_NP;
2292 case ISD::SETUNE: return X86::COND_INVALID;
2296 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
2297 /// code. Current x86 isa includes the following FP cmov instructions:
2298 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
2299 static bool hasFPCMov(unsigned X86CC) {
2315 /// isFPImmLegal - Returns true if the target can instruction select the
2316 /// specified FP immediate natively. If false, the legalizer will
2317 /// materialize the FP immediate as a load from a constant pool.
2318 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
2319 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
2320 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
2326 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
2327 /// the specified range (L, H].
2328 static bool isUndefOrInRange(int Val, int Low, int Hi) {
2329 return (Val < 0) || (Val >= Low && Val < Hi);
2332 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
2333 /// specified value.
2334 static bool isUndefOrEqual(int Val, int CmpVal) {
2335 if (Val < 0 || Val == CmpVal)
2340 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
2341 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
2342 /// the second operand.
2343 static bool isPSHUFDMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2344 if (VT == MVT::v4f32 || VT == MVT::v4i32 || VT == MVT::v4i16)
2345 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
2346 if (VT == MVT::v2f64 || VT == MVT::v2i64)
2347 return (Mask[0] < 2 && Mask[1] < 2);
2351 bool X86::isPSHUFDMask(ShuffleVectorSDNode *N) {
2352 SmallVector<int, 8> M;
2354 return ::isPSHUFDMask(M, N->getValueType(0));
2357 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
2358 /// is suitable for input to PSHUFHW.
2359 static bool isPSHUFHWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2360 if (VT != MVT::v8i16)
2363 // Lower quadword copied in order or undef.
2364 for (int i = 0; i != 4; ++i)
2365 if (Mask[i] >= 0 && Mask[i] != i)
2368 // Upper quadword shuffled.
2369 for (int i = 4; i != 8; ++i)
2370 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7))
2376 bool X86::isPSHUFHWMask(ShuffleVectorSDNode *N) {
2377 SmallVector<int, 8> M;
2379 return ::isPSHUFHWMask(M, N->getValueType(0));
2382 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
2383 /// is suitable for input to PSHUFLW.
2384 static bool isPSHUFLWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2385 if (VT != MVT::v8i16)
2388 // Upper quadword copied in order.
2389 for (int i = 4; i != 8; ++i)
2390 if (Mask[i] >= 0 && Mask[i] != i)
2393 // Lower quadword shuffled.
2394 for (int i = 0; i != 4; ++i)
2401 bool X86::isPSHUFLWMask(ShuffleVectorSDNode *N) {
2402 SmallVector<int, 8> M;
2404 return ::isPSHUFLWMask(M, N->getValueType(0));
2407 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
2408 /// is suitable for input to PALIGNR.
2409 static bool isPALIGNRMask(const SmallVectorImpl<int> &Mask, EVT VT,
2411 int i, e = VT.getVectorNumElements();
2413 // Do not handle v2i64 / v2f64 shuffles with palignr.
2414 if (e < 4 || !hasSSSE3)
2417 for (i = 0; i != e; ++i)
2421 // All undef, not a palignr.
2425 // Determine if it's ok to perform a palignr with only the LHS, since we
2426 // don't have access to the actual shuffle elements to see if RHS is undef.
2427 bool Unary = Mask[i] < (int)e;
2428 bool NeedsUnary = false;
2430 int s = Mask[i] - i;
2432 // Check the rest of the elements to see if they are consecutive.
2433 for (++i; i != e; ++i) {
2438 Unary = Unary && (m < (int)e);
2439 NeedsUnary = NeedsUnary || (m < s);
2441 if (NeedsUnary && !Unary)
2443 if (Unary && m != ((s+i) & (e-1)))
2445 if (!Unary && m != (s+i))
2451 bool X86::isPALIGNRMask(ShuffleVectorSDNode *N) {
2452 SmallVector<int, 8> M;
2454 return ::isPALIGNRMask(M, N->getValueType(0), true);
2457 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
2458 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
2459 static bool isSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2460 int NumElems = VT.getVectorNumElements();
2461 if (NumElems != 2 && NumElems != 4)
2464 int Half = NumElems / 2;
2465 for (int i = 0; i < Half; ++i)
2466 if (!isUndefOrInRange(Mask[i], 0, NumElems))
2468 for (int i = Half; i < NumElems; ++i)
2469 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
2475 bool X86::isSHUFPMask(ShuffleVectorSDNode *N) {
2476 SmallVector<int, 8> M;
2478 return ::isSHUFPMask(M, N->getValueType(0));
2481 /// isCommutedSHUFP - Returns true if the shuffle mask is exactly
2482 /// the reverse of what x86 shuffles want. x86 shuffles requires the lower
2483 /// half elements to come from vector 1 (which would equal the dest.) and
2484 /// the upper half to come from vector 2.
2485 static bool isCommutedSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2486 int NumElems = VT.getVectorNumElements();
2488 if (NumElems != 2 && NumElems != 4)
2491 int Half = NumElems / 2;
2492 for (int i = 0; i < Half; ++i)
2493 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
2495 for (int i = Half; i < NumElems; ++i)
2496 if (!isUndefOrInRange(Mask[i], 0, NumElems))
2501 static bool isCommutedSHUFP(ShuffleVectorSDNode *N) {
2502 SmallVector<int, 8> M;
2504 return isCommutedSHUFPMask(M, N->getValueType(0));
2507 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
2508 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
2509 bool X86::isMOVHLPSMask(ShuffleVectorSDNode *N) {
2510 if (N->getValueType(0).getVectorNumElements() != 4)
2513 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
2514 return isUndefOrEqual(N->getMaskElt(0), 6) &&
2515 isUndefOrEqual(N->getMaskElt(1), 7) &&
2516 isUndefOrEqual(N->getMaskElt(2), 2) &&
2517 isUndefOrEqual(N->getMaskElt(3), 3);
2520 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
2521 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
2522 bool X86::isMOVLPMask(ShuffleVectorSDNode *N) {
2523 unsigned NumElems = N->getValueType(0).getVectorNumElements();
2525 if (NumElems != 2 && NumElems != 4)
2528 for (unsigned i = 0; i < NumElems/2; ++i)
2529 if (!isUndefOrEqual(N->getMaskElt(i), i + NumElems))
2532 for (unsigned i = NumElems/2; i < NumElems; ++i)
2533 if (!isUndefOrEqual(N->getMaskElt(i), i))
2539 /// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand
2540 /// specifies a shuffle of elements that is suitable for input to MOVHP{S|D}
2542 bool X86::isMOVHPMask(ShuffleVectorSDNode *N) {
2543 unsigned NumElems = N->getValueType(0).getVectorNumElements();
2545 if (NumElems != 2 && NumElems != 4)
2548 for (unsigned i = 0; i < NumElems/2; ++i)
2549 if (!isUndefOrEqual(N->getMaskElt(i), i))
2552 for (unsigned i = 0; i < NumElems/2; ++i)
2553 if (!isUndefOrEqual(N->getMaskElt(i + NumElems/2), i + NumElems))
2559 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
2560 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
2562 bool X86::isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N) {
2563 unsigned NumElems = N->getValueType(0).getVectorNumElements();
2568 return isUndefOrEqual(N->getMaskElt(0), 2) &&
2569 isUndefOrEqual(N->getMaskElt(1), 3) &&
2570 isUndefOrEqual(N->getMaskElt(2), 2) &&
2571 isUndefOrEqual(N->getMaskElt(3), 3);
2574 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
2575 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
2576 static bool isUNPCKLMask(const SmallVectorImpl<int> &Mask, EVT VT,
2577 bool V2IsSplat = false) {
2578 int NumElts = VT.getVectorNumElements();
2579 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
2582 for (int i = 0, j = 0; i != NumElts; i += 2, ++j) {
2584 int BitI1 = Mask[i+1];
2585 if (!isUndefOrEqual(BitI, j))
2588 if (!isUndefOrEqual(BitI1, NumElts))
2591 if (!isUndefOrEqual(BitI1, j + NumElts))
2598 bool X86::isUNPCKLMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
2599 SmallVector<int, 8> M;
2601 return ::isUNPCKLMask(M, N->getValueType(0), V2IsSplat);
2604 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
2605 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
2606 static bool isUNPCKHMask(const SmallVectorImpl<int> &Mask, EVT VT,
2607 bool V2IsSplat = false) {
2608 int NumElts = VT.getVectorNumElements();
2609 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
2612 for (int i = 0, j = 0; i != NumElts; i += 2, ++j) {
2614 int BitI1 = Mask[i+1];
2615 if (!isUndefOrEqual(BitI, j + NumElts/2))
2618 if (isUndefOrEqual(BitI1, NumElts))
2621 if (!isUndefOrEqual(BitI1, j + NumElts/2 + NumElts))
2628 bool X86::isUNPCKHMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
2629 SmallVector<int, 8> M;
2631 return ::isUNPCKHMask(M, N->getValueType(0), V2IsSplat);
2634 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
2635 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
2637 static bool isUNPCKL_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) {
2638 int NumElems = VT.getVectorNumElements();
2639 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
2642 for (int i = 0, j = 0; i != NumElems; i += 2, ++j) {
2644 int BitI1 = Mask[i+1];
2645 if (!isUndefOrEqual(BitI, j))
2647 if (!isUndefOrEqual(BitI1, j))
2653 bool X86::isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N) {
2654 SmallVector<int, 8> M;
2656 return ::isUNPCKL_v_undef_Mask(M, N->getValueType(0));
2659 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
2660 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
2662 static bool isUNPCKH_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) {
2663 int NumElems = VT.getVectorNumElements();
2664 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
2667 for (int i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) {
2669 int BitI1 = Mask[i+1];
2670 if (!isUndefOrEqual(BitI, j))
2672 if (!isUndefOrEqual(BitI1, j))
2678 bool X86::isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N) {
2679 SmallVector<int, 8> M;
2681 return ::isUNPCKH_v_undef_Mask(M, N->getValueType(0));
2684 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
2685 /// specifies a shuffle of elements that is suitable for input to MOVSS,
2686 /// MOVSD, and MOVD, i.e. setting the lowest element.
2687 static bool isMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2688 if (VT.getVectorElementType().getSizeInBits() < 32)
2691 int NumElts = VT.getVectorNumElements();
2693 if (!isUndefOrEqual(Mask[0], NumElts))
2696 for (int i = 1; i < NumElts; ++i)
2697 if (!isUndefOrEqual(Mask[i], i))
2703 bool X86::isMOVLMask(ShuffleVectorSDNode *N) {
2704 SmallVector<int, 8> M;
2706 return ::isMOVLMask(M, N->getValueType(0));
2709 /// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
2710 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
2711 /// element of vector 2 and the other elements to come from vector 1 in order.
2712 static bool isCommutedMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT,
2713 bool V2IsSplat = false, bool V2IsUndef = false) {
2714 int NumOps = VT.getVectorNumElements();
2715 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
2718 if (!isUndefOrEqual(Mask[0], 0))
2721 for (int i = 1; i < NumOps; ++i)
2722 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
2723 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
2724 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
2730 static bool isCommutedMOVL(ShuffleVectorSDNode *N, bool V2IsSplat = false,
2731 bool V2IsUndef = false) {
2732 SmallVector<int, 8> M;
2734 return isCommutedMOVLMask(M, N->getValueType(0), V2IsSplat, V2IsUndef);
2737 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2738 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
2739 bool X86::isMOVSHDUPMask(ShuffleVectorSDNode *N) {
2740 if (N->getValueType(0).getVectorNumElements() != 4)
2743 // Expect 1, 1, 3, 3
2744 for (unsigned i = 0; i < 2; ++i) {
2745 int Elt = N->getMaskElt(i);
2746 if (Elt >= 0 && Elt != 1)
2751 for (unsigned i = 2; i < 4; ++i) {
2752 int Elt = N->getMaskElt(i);
2753 if (Elt >= 0 && Elt != 3)
2758 // Don't use movshdup if it can be done with a shufps.
2759 // FIXME: verify that matching u, u, 3, 3 is what we want.
2763 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2764 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
2765 bool X86::isMOVSLDUPMask(ShuffleVectorSDNode *N) {
2766 if (N->getValueType(0).getVectorNumElements() != 4)
2769 // Expect 0, 0, 2, 2
2770 for (unsigned i = 0; i < 2; ++i)
2771 if (N->getMaskElt(i) > 0)
2775 for (unsigned i = 2; i < 4; ++i) {
2776 int Elt = N->getMaskElt(i);
2777 if (Elt >= 0 && Elt != 2)
2782 // Don't use movsldup if it can be done with a shufps.
2786 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2787 /// specifies a shuffle of elements that is suitable for input to MOVDDUP.
2788 bool X86::isMOVDDUPMask(ShuffleVectorSDNode *N) {
2789 int e = N->getValueType(0).getVectorNumElements() / 2;
2791 for (int i = 0; i < e; ++i)
2792 if (!isUndefOrEqual(N->getMaskElt(i), i))
2794 for (int i = 0; i < e; ++i)
2795 if (!isUndefOrEqual(N->getMaskElt(e+i), i))
2800 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
2801 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
2802 unsigned X86::getShuffleSHUFImmediate(SDNode *N) {
2803 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
2804 int NumOperands = SVOp->getValueType(0).getVectorNumElements();
2806 unsigned Shift = (NumOperands == 4) ? 2 : 1;
2808 for (int i = 0; i < NumOperands; ++i) {
2809 int Val = SVOp->getMaskElt(NumOperands-i-1);
2810 if (Val < 0) Val = 0;
2811 if (Val >= NumOperands) Val -= NumOperands;
2813 if (i != NumOperands - 1)
2819 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
2820 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
2821 unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
2822 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
2824 // 8 nodes, but we only care about the last 4.
2825 for (unsigned i = 7; i >= 4; --i) {
2826 int Val = SVOp->getMaskElt(i);
2835 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
2836 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
2837 unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
2838 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
2840 // 8 nodes, but we only care about the first 4.
2841 for (int i = 3; i >= 0; --i) {
2842 int Val = SVOp->getMaskElt(i);
2851 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
2852 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
2853 unsigned X86::getShufflePALIGNRImmediate(SDNode *N) {
2854 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
2855 EVT VVT = N->getValueType(0);
2856 unsigned EltSize = VVT.getVectorElementType().getSizeInBits() >> 3;
2860 for (i = 0, e = VVT.getVectorNumElements(); i != e; ++i) {
2861 Val = SVOp->getMaskElt(i);
2865 return (Val - i) * EltSize;
2868 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
2870 bool X86::isZeroNode(SDValue Elt) {
2871 return ((isa<ConstantSDNode>(Elt) &&
2872 cast<ConstantSDNode>(Elt)->getZExtValue() == 0) ||
2873 (isa<ConstantFPSDNode>(Elt) &&
2874 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
2877 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
2878 /// their permute mask.
2879 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
2880 SelectionDAG &DAG) {
2881 EVT VT = SVOp->getValueType(0);
2882 unsigned NumElems = VT.getVectorNumElements();
2883 SmallVector<int, 8> MaskVec;
2885 for (unsigned i = 0; i != NumElems; ++i) {
2886 int idx = SVOp->getMaskElt(i);
2888 MaskVec.push_back(idx);
2889 else if (idx < (int)NumElems)
2890 MaskVec.push_back(idx + NumElems);
2892 MaskVec.push_back(idx - NumElems);
2894 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1),
2895 SVOp->getOperand(0), &MaskVec[0]);
2898 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
2899 /// the two vector operands have swapped position.
2900 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, EVT VT) {
2901 unsigned NumElems = VT.getVectorNumElements();
2902 for (unsigned i = 0; i != NumElems; ++i) {
2906 else if (idx < (int)NumElems)
2907 Mask[i] = idx + NumElems;
2909 Mask[i] = idx - NumElems;
2913 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
2914 /// match movhlps. The lower half elements should come from upper half of
2915 /// V1 (and in order), and the upper half elements should come from the upper
2916 /// half of V2 (and in order).
2917 static bool ShouldXformToMOVHLPS(ShuffleVectorSDNode *Op) {
2918 if (Op->getValueType(0).getVectorNumElements() != 4)
2920 for (unsigned i = 0, e = 2; i != e; ++i)
2921 if (!isUndefOrEqual(Op->getMaskElt(i), i+2))
2923 for (unsigned i = 2; i != 4; ++i)
2924 if (!isUndefOrEqual(Op->getMaskElt(i), i+4))
2929 /// isScalarLoadToVector - Returns true if the node is a scalar load that
2930 /// is promoted to a vector. It also returns the LoadSDNode by reference if
2932 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
2933 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
2935 N = N->getOperand(0).getNode();
2936 if (!ISD::isNON_EXTLoad(N))
2939 *LD = cast<LoadSDNode>(N);
2943 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
2944 /// match movlp{s|d}. The lower half elements should come from lower half of
2945 /// V1 (and in order), and the upper half elements should come from the upper
2946 /// half of V2 (and in order). And since V1 will become the source of the
2947 /// MOVLP, it must be either a vector load or a scalar load to vector.
2948 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
2949 ShuffleVectorSDNode *Op) {
2950 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
2952 // Is V2 is a vector load, don't do this transformation. We will try to use
2953 // load folding shufps op.
2954 if (ISD::isNON_EXTLoad(V2))
2957 unsigned NumElems = Op->getValueType(0).getVectorNumElements();
2959 if (NumElems != 2 && NumElems != 4)
2961 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
2962 if (!isUndefOrEqual(Op->getMaskElt(i), i))
2964 for (unsigned i = NumElems/2; i != NumElems; ++i)
2965 if (!isUndefOrEqual(Op->getMaskElt(i), i+NumElems))
2970 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
2972 static bool isSplatVector(SDNode *N) {
2973 if (N->getOpcode() != ISD::BUILD_VECTOR)
2976 SDValue SplatValue = N->getOperand(0);
2977 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
2978 if (N->getOperand(i) != SplatValue)
2983 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
2984 /// to an zero vector.
2985 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
2986 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
2987 SDValue V1 = N->getOperand(0);
2988 SDValue V2 = N->getOperand(1);
2989 unsigned NumElems = N->getValueType(0).getVectorNumElements();
2990 for (unsigned i = 0; i != NumElems; ++i) {
2991 int Idx = N->getMaskElt(i);
2992 if (Idx >= (int)NumElems) {
2993 unsigned Opc = V2.getOpcode();
2994 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
2996 if (Opc != ISD::BUILD_VECTOR ||
2997 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
2999 } else if (Idx >= 0) {
3000 unsigned Opc = V1.getOpcode();
3001 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
3003 if (Opc != ISD::BUILD_VECTOR ||
3004 !X86::isZeroNode(V1.getOperand(Idx)))
3011 /// getZeroVector - Returns a vector of specified type with all zero elements.
3013 static SDValue getZeroVector(EVT VT, bool HasSSE2, SelectionDAG &DAG,
3015 assert(VT.isVector() && "Expected a vector type");
3017 // Always build zero vectors as <4 x i32> or <2 x i32> bitcasted to their dest
3018 // type. This ensures they get CSE'd.
3020 if (VT.getSizeInBits() == 64) { // MMX
3021 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
3022 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
3023 } else if (HasSSE2) { // SSE2
3024 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
3025 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
3027 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
3028 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
3030 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
3033 /// getOnesVector - Returns a vector of specified type with all bits set.
3035 static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
3036 assert(VT.isVector() && "Expected a vector type");
3038 // Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest
3039 // type. This ensures they get CSE'd.
3040 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
3042 if (VT.getSizeInBits() == 64) // MMX
3043 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
3045 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
3046 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
3050 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
3051 /// that point to V2 points to its first element.
3052 static SDValue NormalizeMask(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
3053 EVT VT = SVOp->getValueType(0);
3054 unsigned NumElems = VT.getVectorNumElements();
3056 bool Changed = false;
3057 SmallVector<int, 8> MaskVec;
3058 SVOp->getMask(MaskVec);
3060 for (unsigned i = 0; i != NumElems; ++i) {
3061 if (MaskVec[i] > (int)NumElems) {
3062 MaskVec[i] = NumElems;
3067 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(0),
3068 SVOp->getOperand(1), &MaskVec[0]);
3069 return SDValue(SVOp, 0);
3072 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
3073 /// operation of specified width.
3074 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3076 unsigned NumElems = VT.getVectorNumElements();
3077 SmallVector<int, 8> Mask;
3078 Mask.push_back(NumElems);
3079 for (unsigned i = 1; i != NumElems; ++i)
3081 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3084 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
3085 static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3087 unsigned NumElems = VT.getVectorNumElements();
3088 SmallVector<int, 8> Mask;
3089 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
3091 Mask.push_back(i + NumElems);
3093 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3096 /// getUnpackhMask - Returns a vector_shuffle node for an unpackh operation.
3097 static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3099 unsigned NumElems = VT.getVectorNumElements();
3100 unsigned Half = NumElems/2;
3101 SmallVector<int, 8> Mask;
3102 for (unsigned i = 0; i != Half; ++i) {
3103 Mask.push_back(i + Half);
3104 Mask.push_back(i + NumElems + Half);
3106 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3109 /// PromoteSplat - Promote a splat of v4f32, v8i16 or v16i8 to v4i32.
3110 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG,
3112 if (SV->getValueType(0).getVectorNumElements() <= 4)
3113 return SDValue(SV, 0);
3115 EVT PVT = MVT::v4f32;
3116 EVT VT = SV->getValueType(0);
3117 DebugLoc dl = SV->getDebugLoc();
3118 SDValue V1 = SV->getOperand(0);
3119 int NumElems = VT.getVectorNumElements();
3120 int EltNo = SV->getSplatIndex();
3122 // unpack elements to the correct location
3123 while (NumElems > 4) {
3124 if (EltNo < NumElems/2) {
3125 V1 = getUnpackl(DAG, dl, VT, V1, V1);
3127 V1 = getUnpackh(DAG, dl, VT, V1, V1);
3128 EltNo -= NumElems/2;
3133 // Perform the splat.
3134 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
3135 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, PVT, V1);
3136 V1 = DAG.getVectorShuffle(PVT, dl, V1, DAG.getUNDEF(PVT), &SplatMask[0]);
3137 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, V1);
3140 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
3141 /// vector of zero or undef vector. This produces a shuffle where the low
3142 /// element of V2 is swizzled into the zero/undef vector, landing at element
3143 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
3144 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
3145 bool isZero, bool HasSSE2,
3146 SelectionDAG &DAG) {
3147 EVT VT = V2.getValueType();
3149 ? getZeroVector(VT, HasSSE2, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT);
3150 unsigned NumElems = VT.getVectorNumElements();
3151 SmallVector<int, 16> MaskVec;
3152 for (unsigned i = 0; i != NumElems; ++i)
3153 // If this is the insertion idx, put the low elt of V2 here.
3154 MaskVec.push_back(i == Idx ? NumElems : i);
3155 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]);
3158 /// getNumOfConsecutiveZeros - Return the number of elements in a result of
3159 /// a shuffle that is zero.
3161 unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp, int NumElems,
3162 bool Low, SelectionDAG &DAG) {
3163 unsigned NumZeros = 0;
3164 for (int i = 0; i < NumElems; ++i) {
3165 unsigned Index = Low ? i : NumElems-i-1;
3166 int Idx = SVOp->getMaskElt(Index);
3171 SDValue Elt = DAG.getShuffleScalarElt(SVOp, Index);
3172 if (Elt.getNode() && X86::isZeroNode(Elt))
3180 /// isVectorShift - Returns true if the shuffle can be implemented as a
3181 /// logical left or right shift of a vector.
3182 /// FIXME: split into pslldqi, psrldqi, palignr variants.
3183 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
3184 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
3185 int NumElems = SVOp->getValueType(0).getVectorNumElements();
3188 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, true, DAG);
3191 NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, false, DAG);
3195 bool SeenV1 = false;
3196 bool SeenV2 = false;
3197 for (int i = NumZeros; i < NumElems; ++i) {
3198 int Val = isLeft ? (i - NumZeros) : i;
3199 int Idx = SVOp->getMaskElt(isLeft ? i : (i - NumZeros));
3211 if (SeenV1 && SeenV2)
3214 ShVal = SeenV1 ? SVOp->getOperand(0) : SVOp->getOperand(1);
3220 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
3222 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
3223 unsigned NumNonZero, unsigned NumZero,
3224 SelectionDAG &DAG, TargetLowering &TLI) {
3228 DebugLoc dl = Op.getDebugLoc();
3231 for (unsigned i = 0; i < 16; ++i) {
3232 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
3233 if (ThisIsNonZero && First) {
3235 V = getZeroVector(MVT::v8i16, true, DAG, dl);
3237 V = DAG.getUNDEF(MVT::v8i16);
3242 SDValue ThisElt(0, 0), LastElt(0, 0);
3243 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
3244 if (LastIsNonZero) {
3245 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
3246 MVT::i16, Op.getOperand(i-1));
3248 if (ThisIsNonZero) {
3249 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
3250 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
3251 ThisElt, DAG.getConstant(8, MVT::i8));
3253 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
3257 if (ThisElt.getNode())
3258 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
3259 DAG.getIntPtrConstant(i/2));
3263 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V);
3266 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
3268 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
3269 unsigned NumNonZero, unsigned NumZero,
3270 SelectionDAG &DAG, TargetLowering &TLI) {
3274 DebugLoc dl = Op.getDebugLoc();
3277 for (unsigned i = 0; i < 8; ++i) {
3278 bool isNonZero = (NonZeros & (1 << i)) != 0;
3282 V = getZeroVector(MVT::v8i16, true, DAG, dl);
3284 V = DAG.getUNDEF(MVT::v8i16);
3287 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
3288 MVT::v8i16, V, Op.getOperand(i),
3289 DAG.getIntPtrConstant(i));
3296 /// getVShift - Return a vector logical shift node.
3298 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
3299 unsigned NumBits, SelectionDAG &DAG,
3300 const TargetLowering &TLI, DebugLoc dl) {
3301 bool isMMX = VT.getSizeInBits() == 64;
3302 EVT ShVT = isMMX ? MVT::v1i64 : MVT::v2i64;
3303 unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL;
3304 SrcOp = DAG.getNode(ISD::BIT_CONVERT, dl, ShVT, SrcOp);
3305 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
3306 DAG.getNode(Opc, dl, ShVT, SrcOp,
3307 DAG.getConstant(NumBits, TLI.getShiftAmountTy())));
3311 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
3312 DebugLoc dl = Op.getDebugLoc();
3313 // All zero's are handled with pxor, all one's are handled with pcmpeqd.
3314 if (ISD::isBuildVectorAllZeros(Op.getNode())
3315 || ISD::isBuildVectorAllOnes(Op.getNode())) {
3316 // Canonicalize this to either <4 x i32> or <2 x i32> (SSE vs MMX) to
3317 // 1) ensure the zero vectors are CSE'd, and 2) ensure that i64 scalars are
3318 // eliminated on x86-32 hosts.
3319 if (Op.getValueType() == MVT::v4i32 || Op.getValueType() == MVT::v2i32)
3322 if (ISD::isBuildVectorAllOnes(Op.getNode()))
3323 return getOnesVector(Op.getValueType(), DAG, dl);
3324 return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(), DAG, dl);
3327 EVT VT = Op.getValueType();
3328 EVT ExtVT = VT.getVectorElementType();
3329 unsigned EVTBits = ExtVT.getSizeInBits();
3331 unsigned NumElems = Op.getNumOperands();
3332 unsigned NumZero = 0;
3333 unsigned NumNonZero = 0;
3334 unsigned NonZeros = 0;
3335 bool IsAllConstants = true;
3336 SmallSet<SDValue, 8> Values;
3337 for (unsigned i = 0; i < NumElems; ++i) {
3338 SDValue Elt = Op.getOperand(i);
3339 if (Elt.getOpcode() == ISD::UNDEF)
3342 if (Elt.getOpcode() != ISD::Constant &&
3343 Elt.getOpcode() != ISD::ConstantFP)
3344 IsAllConstants = false;
3345 if (X86::isZeroNode(Elt))
3348 NonZeros |= (1 << i);
3353 if (NumNonZero == 0) {
3354 // All undef vector. Return an UNDEF. All zero vectors were handled above.
3355 return DAG.getUNDEF(VT);
3358 // Special case for single non-zero, non-undef, element.
3359 if (NumNonZero == 1) {
3360 unsigned Idx = CountTrailingZeros_32(NonZeros);
3361 SDValue Item = Op.getOperand(Idx);
3363 // If this is an insertion of an i64 value on x86-32, and if the top bits of
3364 // the value are obviously zero, truncate the value to i32 and do the
3365 // insertion that way. Only do this if the value is non-constant or if the
3366 // value is a constant being inserted into element 0. It is cheaper to do
3367 // a constant pool load than it is to do a movd + shuffle.
3368 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
3369 (!IsAllConstants || Idx == 0)) {
3370 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
3371 // Handle MMX and SSE both.
3372 EVT VecVT = VT == MVT::v2i64 ? MVT::v4i32 : MVT::v2i32;
3373 unsigned VecElts = VT == MVT::v2i64 ? 4 : 2;
3375 // Truncate the value (which may itself be a constant) to i32, and
3376 // convert it to a vector with movd (S2V+shuffle to zero extend).
3377 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
3378 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
3379 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
3380 Subtarget->hasSSE2(), DAG);
3382 // Now we have our 32-bit value zero extended in the low element of
3383 // a vector. If Idx != 0, swizzle it into place.
3385 SmallVector<int, 4> Mask;
3386 Mask.push_back(Idx);
3387 for (unsigned i = 1; i != VecElts; ++i)
3389 Item = DAG.getVectorShuffle(VecVT, dl, Item,
3390 DAG.getUNDEF(Item.getValueType()),
3393 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Item);
3397 // If we have a constant or non-constant insertion into the low element of
3398 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
3399 // the rest of the elements. This will be matched as movd/movq/movss/movsd
3400 // depending on what the source datatype is.
3403 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
3404 } else if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
3405 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
3406 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
3407 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
3408 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget->hasSSE2(),
3410 } else if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
3411 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
3412 EVT MiddleVT = VT.getSizeInBits() == 64 ? MVT::v2i32 : MVT::v4i32;
3413 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MiddleVT, Item);
3414 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
3415 Subtarget->hasSSE2(), DAG);
3416 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Item);
3420 // Is it a vector logical left shift?
3421 if (NumElems == 2 && Idx == 1 &&
3422 X86::isZeroNode(Op.getOperand(0)) &&
3423 !X86::isZeroNode(Op.getOperand(1))) {
3424 unsigned NumBits = VT.getSizeInBits();
3425 return getVShift(true, VT,
3426 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
3427 VT, Op.getOperand(1)),
3428 NumBits/2, DAG, *this, dl);
3431 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
3434 // Otherwise, if this is a vector with i32 or f32 elements, and the element
3435 // is a non-constant being inserted into an element other than the low one,
3436 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
3437 // movd/movss) to move this into the low element, then shuffle it into
3439 if (EVTBits == 32) {
3440 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
3442 // Turn it into a shuffle of zero and zero-extended scalar to vector.
3443 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0,
3444 Subtarget->hasSSE2(), DAG);
3445 SmallVector<int, 8> MaskVec;
3446 for (unsigned i = 0; i < NumElems; i++)
3447 MaskVec.push_back(i == Idx ? 0 : 1);
3448 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
3452 // Splat is obviously ok. Let legalizer expand it to a shuffle.
3453 if (Values.size() == 1)
3456 // A vector full of immediates; various special cases are already
3457 // handled, so this is best done with a single constant-pool load.
3461 // Let legalizer expand 2-wide build_vectors.
3462 if (EVTBits == 64) {
3463 if (NumNonZero == 1) {
3464 // One half is zero or undef.
3465 unsigned Idx = CountTrailingZeros_32(NonZeros);
3466 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
3467 Op.getOperand(Idx));
3468 return getShuffleVectorZeroOrUndef(V2, Idx, true,
3469 Subtarget->hasSSE2(), DAG);
3474 // If element VT is < 32 bits, convert it to inserts into a zero vector.
3475 if (EVTBits == 8 && NumElems == 16) {
3476 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
3478 if (V.getNode()) return V;
3481 if (EVTBits == 16 && NumElems == 8) {
3482 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
3484 if (V.getNode()) return V;
3487 // If element VT is == 32 bits, turn it into a number of shuffles.
3488 SmallVector<SDValue, 8> V;
3490 if (NumElems == 4 && NumZero > 0) {
3491 for (unsigned i = 0; i < 4; ++i) {
3492 bool isZero = !(NonZeros & (1 << i));
3494 V[i] = getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
3496 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
3499 for (unsigned i = 0; i < 2; ++i) {
3500 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
3503 V[i] = V[i*2]; // Must be a zero vector.
3506 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
3509 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
3512 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
3517 SmallVector<int, 8> MaskVec;
3518 bool Reverse = (NonZeros & 0x3) == 2;
3519 for (unsigned i = 0; i < 2; ++i)
3520 MaskVec.push_back(Reverse ? 1-i : i);
3521 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2;
3522 for (unsigned i = 0; i < 2; ++i)
3523 MaskVec.push_back(Reverse ? 1-i+NumElems : i+NumElems);
3524 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
3527 if (Values.size() > 2) {
3528 // If we have SSE 4.1, Expand into a number of inserts unless the number of
3529 // values to be inserted is equal to the number of elements, in which case
3530 // use the unpack code below in the hopes of matching the consecutive elts
3531 // load merge pattern for shuffles.
3532 // FIXME: We could probably just check that here directly.
3533 if (Values.size() < NumElems && VT.getSizeInBits() == 128 &&
3534 getSubtarget()->hasSSE41()) {
3535 V[0] = DAG.getUNDEF(VT);
3536 for (unsigned i = 0; i < NumElems; ++i)
3537 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
3538 V[0] = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, V[0],
3539 Op.getOperand(i), DAG.getIntPtrConstant(i));
3542 // Expand into a number of unpckl*.
3544 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
3545 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
3546 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
3547 for (unsigned i = 0; i < NumElems; ++i)
3548 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
3550 while (NumElems != 0) {
3551 for (unsigned i = 0; i < NumElems; ++i)
3552 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + NumElems]);
3561 // v8i16 shuffles - Prefer shuffles in the following order:
3562 // 1. [all] pshuflw, pshufhw, optional move
3563 // 2. [ssse3] 1 x pshufb
3564 // 3. [ssse3] 2 x pshufb + 1 x por
3565 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
3567 SDValue LowerVECTOR_SHUFFLEv8i16(ShuffleVectorSDNode *SVOp,
3568 SelectionDAG &DAG, X86TargetLowering &TLI) {
3569 SDValue V1 = SVOp->getOperand(0);
3570 SDValue V2 = SVOp->getOperand(1);
3571 DebugLoc dl = SVOp->getDebugLoc();
3572 SmallVector<int, 8> MaskVals;
3574 // Determine if more than 1 of the words in each of the low and high quadwords
3575 // of the result come from the same quadword of one of the two inputs. Undef
3576 // mask values count as coming from any quadword, for better codegen.
3577 SmallVector<unsigned, 4> LoQuad(4);
3578 SmallVector<unsigned, 4> HiQuad(4);
3579 BitVector InputQuads(4);
3580 for (unsigned i = 0; i < 8; ++i) {
3581 SmallVectorImpl<unsigned> &Quad = i < 4 ? LoQuad : HiQuad;
3582 int EltIdx = SVOp->getMaskElt(i);
3583 MaskVals.push_back(EltIdx);
3592 InputQuads.set(EltIdx / 4);
3595 int BestLoQuad = -1;
3596 unsigned MaxQuad = 1;
3597 for (unsigned i = 0; i < 4; ++i) {
3598 if (LoQuad[i] > MaxQuad) {
3600 MaxQuad = LoQuad[i];
3604 int BestHiQuad = -1;
3606 for (unsigned i = 0; i < 4; ++i) {
3607 if (HiQuad[i] > MaxQuad) {
3609 MaxQuad = HiQuad[i];
3613 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
3614 // of the two input vectors, shuffle them into one input vector so only a
3615 // single pshufb instruction is necessary. If There are more than 2 input
3616 // quads, disable the next transformation since it does not help SSSE3.
3617 bool V1Used = InputQuads[0] || InputQuads[1];
3618 bool V2Used = InputQuads[2] || InputQuads[3];
3619 if (TLI.getSubtarget()->hasSSSE3()) {
3620 if (InputQuads.count() == 2 && V1Used && V2Used) {
3621 BestLoQuad = InputQuads.find_first();
3622 BestHiQuad = InputQuads.find_next(BestLoQuad);
3624 if (InputQuads.count() > 2) {
3630 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
3631 // the shuffle mask. If a quad is scored as -1, that means that it contains
3632 // words from all 4 input quadwords.
3634 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
3635 SmallVector<int, 8> MaskV;
3636 MaskV.push_back(BestLoQuad < 0 ? 0 : BestLoQuad);
3637 MaskV.push_back(BestHiQuad < 0 ? 1 : BestHiQuad);
3638 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
3639 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V1),
3640 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V2), &MaskV[0]);
3641 NewV = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, NewV);
3643 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
3644 // source words for the shuffle, to aid later transformations.
3645 bool AllWordsInNewV = true;
3646 bool InOrder[2] = { true, true };
3647 for (unsigned i = 0; i != 8; ++i) {
3648 int idx = MaskVals[i];
3650 InOrder[i/4] = false;
3651 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
3653 AllWordsInNewV = false;
3657 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
3658 if (AllWordsInNewV) {
3659 for (int i = 0; i != 8; ++i) {
3660 int idx = MaskVals[i];
3663 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
3664 if ((idx != i) && idx < 4)
3666 if ((idx != i) && idx > 3)
3675 // If we've eliminated the use of V2, and the new mask is a pshuflw or
3676 // pshufhw, that's as cheap as it gets. Return the new shuffle.
3677 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
3678 return DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
3679 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
3683 // If we have SSSE3, and all words of the result are from 1 input vector,
3684 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
3685 // is present, fall back to case 4.
3686 if (TLI.getSubtarget()->hasSSSE3()) {
3687 SmallVector<SDValue,16> pshufbMask;
3689 // If we have elements from both input vectors, set the high bit of the
3690 // shuffle mask element to zero out elements that come from V2 in the V1
3691 // mask, and elements that come from V1 in the V2 mask, so that the two
3692 // results can be OR'd together.
3693 bool TwoInputs = V1Used && V2Used;
3694 for (unsigned i = 0; i != 8; ++i) {
3695 int EltIdx = MaskVals[i] * 2;
3696 if (TwoInputs && (EltIdx >= 16)) {
3697 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
3698 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
3701 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
3702 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8));
3704 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V1);
3705 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
3706 DAG.getNode(ISD::BUILD_VECTOR, dl,
3707 MVT::v16i8, &pshufbMask[0], 16));
3709 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
3711 // Calculate the shuffle mask for the second input, shuffle it, and
3712 // OR it with the first shuffled input.
3714 for (unsigned i = 0; i != 8; ++i) {
3715 int EltIdx = MaskVals[i] * 2;
3717 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
3718 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
3721 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
3722 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8));
3724 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V2);
3725 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
3726 DAG.getNode(ISD::BUILD_VECTOR, dl,
3727 MVT::v16i8, &pshufbMask[0], 16));
3728 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
3729 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
3732 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
3733 // and update MaskVals with new element order.
3734 BitVector InOrder(8);
3735 if (BestLoQuad >= 0) {
3736 SmallVector<int, 8> MaskV;
3737 for (int i = 0; i != 4; ++i) {
3738 int idx = MaskVals[i];
3740 MaskV.push_back(-1);
3742 } else if ((idx / 4) == BestLoQuad) {
3743 MaskV.push_back(idx & 3);
3746 MaskV.push_back(-1);
3749 for (unsigned i = 4; i != 8; ++i)
3751 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
3755 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
3756 // and update MaskVals with the new element order.
3757 if (BestHiQuad >= 0) {
3758 SmallVector<int, 8> MaskV;
3759 for (unsigned i = 0; i != 4; ++i)
3761 for (unsigned i = 4; i != 8; ++i) {
3762 int idx = MaskVals[i];
3764 MaskV.push_back(-1);
3766 } else if ((idx / 4) == BestHiQuad) {
3767 MaskV.push_back((idx & 3) + 4);
3770 MaskV.push_back(-1);
3773 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
3777 // In case BestHi & BestLo were both -1, which means each quadword has a word
3778 // from each of the four input quadwords, calculate the InOrder bitvector now
3779 // before falling through to the insert/extract cleanup.
3780 if (BestLoQuad == -1 && BestHiQuad == -1) {
3782 for (int i = 0; i != 8; ++i)
3783 if (MaskVals[i] < 0 || MaskVals[i] == i)
3787 // The other elements are put in the right place using pextrw and pinsrw.
3788 for (unsigned i = 0; i != 8; ++i) {
3791 int EltIdx = MaskVals[i];
3794 SDValue ExtOp = (EltIdx < 8)
3795 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
3796 DAG.getIntPtrConstant(EltIdx))
3797 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
3798 DAG.getIntPtrConstant(EltIdx - 8));
3799 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
3800 DAG.getIntPtrConstant(i));
3805 // v16i8 shuffles - Prefer shuffles in the following order:
3806 // 1. [ssse3] 1 x pshufb
3807 // 2. [ssse3] 2 x pshufb + 1 x por
3808 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
3810 SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
3811 SelectionDAG &DAG, X86TargetLowering &TLI) {
3812 SDValue V1 = SVOp->getOperand(0);
3813 SDValue V2 = SVOp->getOperand(1);
3814 DebugLoc dl = SVOp->getDebugLoc();
3815 SmallVector<int, 16> MaskVals;
3816 SVOp->getMask(MaskVals);
3818 // If we have SSSE3, case 1 is generated when all result bytes come from
3819 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
3820 // present, fall back to case 3.
3821 // FIXME: kill V2Only once shuffles are canonizalized by getNode.
3824 for (unsigned i = 0; i < 16; ++i) {
3825 int EltIdx = MaskVals[i];
3834 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
3835 if (TLI.getSubtarget()->hasSSSE3()) {
3836 SmallVector<SDValue,16> pshufbMask;
3838 // If all result elements are from one input vector, then only translate
3839 // undef mask values to 0x80 (zero out result) in the pshufb mask.
3841 // Otherwise, we have elements from both input vectors, and must zero out
3842 // elements that come from V2 in the first mask, and V1 in the second mask
3843 // so that we can OR them together.
3844 bool TwoInputs = !(V1Only || V2Only);
3845 for (unsigned i = 0; i != 16; ++i) {
3846 int EltIdx = MaskVals[i];
3847 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) {
3848 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
3851 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
3853 // If all the elements are from V2, assign it to V1 and return after
3854 // building the first pshufb.
3857 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
3858 DAG.getNode(ISD::BUILD_VECTOR, dl,
3859 MVT::v16i8, &pshufbMask[0], 16));
3863 // Calculate the shuffle mask for the second input, shuffle it, and
3864 // OR it with the first shuffled input.
3866 for (unsigned i = 0; i != 16; ++i) {
3867 int EltIdx = MaskVals[i];
3869 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
3872 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
3874 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
3875 DAG.getNode(ISD::BUILD_VECTOR, dl,
3876 MVT::v16i8, &pshufbMask[0], 16));
3877 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
3880 // No SSSE3 - Calculate in place words and then fix all out of place words
3881 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
3882 // the 16 different words that comprise the two doublequadword input vectors.
3883 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
3884 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V2);
3885 SDValue NewV = V2Only ? V2 : V1;
3886 for (int i = 0; i != 8; ++i) {
3887 int Elt0 = MaskVals[i*2];
3888 int Elt1 = MaskVals[i*2+1];
3890 // This word of the result is all undef, skip it.
3891 if (Elt0 < 0 && Elt1 < 0)
3894 // This word of the result is already in the correct place, skip it.
3895 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1))
3897 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17))
3900 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
3901 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
3904 // If Elt0 and Elt1 are defined, are consecutive, and can be load
3905 // using a single extract together, load it and store it.
3906 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
3907 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
3908 DAG.getIntPtrConstant(Elt1 / 2));
3909 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
3910 DAG.getIntPtrConstant(i));
3914 // If Elt1 is defined, extract it from the appropriate source. If the
3915 // source byte is not also odd, shift the extracted word left 8 bits
3916 // otherwise clear the bottom 8 bits if we need to do an or.
3918 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
3919 DAG.getIntPtrConstant(Elt1 / 2));
3920 if ((Elt1 & 1) == 0)
3921 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
3922 DAG.getConstant(8, TLI.getShiftAmountTy()));
3924 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
3925 DAG.getConstant(0xFF00, MVT::i16));
3927 // If Elt0 is defined, extract it from the appropriate source. If the
3928 // source byte is not also even, shift the extracted word right 8 bits. If
3929 // Elt1 was also defined, OR the extracted values together before
3930 // inserting them in the result.
3932 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
3933 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
3934 if ((Elt0 & 1) != 0)
3935 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
3936 DAG.getConstant(8, TLI.getShiftAmountTy()));
3938 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
3939 DAG.getConstant(0x00FF, MVT::i16));
3940 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
3943 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
3944 DAG.getIntPtrConstant(i));
3946 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, NewV);
3949 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
3950 /// ones, or rewriting v4i32 / v2f32 as 2 wide ones if possible. This can be
3951 /// done when every pair / quad of shuffle mask elements point to elements in
3952 /// the right sequence. e.g.
3953 /// vector_shuffle <>, <>, < 3, 4, | 10, 11, | 0, 1, | 14, 15>
3955 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
3957 TargetLowering &TLI, DebugLoc dl) {
3958 EVT VT = SVOp->getValueType(0);
3959 SDValue V1 = SVOp->getOperand(0);
3960 SDValue V2 = SVOp->getOperand(1);
3961 unsigned NumElems = VT.getVectorNumElements();
3962 unsigned NewWidth = (NumElems == 4) ? 2 : 4;
3963 EVT MaskVT = MVT::getIntVectorWithNumElements(NewWidth);
3964 EVT MaskEltVT = MaskVT.getVectorElementType();
3966 switch (VT.getSimpleVT().SimpleTy) {
3967 default: assert(false && "Unexpected!");
3968 case MVT::v4f32: NewVT = MVT::v2f64; break;
3969 case MVT::v4i32: NewVT = MVT::v2i64; break;
3970 case MVT::v8i16: NewVT = MVT::v4i32; break;
3971 case MVT::v16i8: NewVT = MVT::v4i32; break;
3974 if (NewWidth == 2) {
3980 int Scale = NumElems / NewWidth;
3981 SmallVector<int, 8> MaskVec;
3982 for (unsigned i = 0; i < NumElems; i += Scale) {
3984 for (int j = 0; j < Scale; ++j) {
3985 int EltIdx = SVOp->getMaskElt(i+j);
3989 StartIdx = EltIdx - (EltIdx % Scale);
3990 if (EltIdx != StartIdx + j)
3994 MaskVec.push_back(-1);
3996 MaskVec.push_back(StartIdx / Scale);
3999 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V1);
4000 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V2);
4001 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
4004 /// getVZextMovL - Return a zero-extending vector move low node.
4006 static SDValue getVZextMovL(EVT VT, EVT OpVT,
4007 SDValue SrcOp, SelectionDAG &DAG,
4008 const X86Subtarget *Subtarget, DebugLoc dl) {
4009 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
4010 LoadSDNode *LD = NULL;
4011 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
4012 LD = dyn_cast<LoadSDNode>(SrcOp);
4014 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
4016 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
4017 if ((ExtVT.SimpleTy != MVT::i64 || Subtarget->is64Bit()) &&
4018 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
4019 SrcOp.getOperand(0).getOpcode() == ISD::BIT_CONVERT &&
4020 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
4022 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
4023 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
4024 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
4025 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
4033 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
4034 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
4035 DAG.getNode(ISD::BIT_CONVERT, dl,
4039 /// LowerVECTOR_SHUFFLE_4wide - Handle all 4 wide cases with a number of
4042 LowerVECTOR_SHUFFLE_4wide(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
4043 SDValue V1 = SVOp->getOperand(0);
4044 SDValue V2 = SVOp->getOperand(1);
4045 DebugLoc dl = SVOp->getDebugLoc();
4046 EVT VT = SVOp->getValueType(0);
4048 SmallVector<std::pair<int, int>, 8> Locs;
4050 SmallVector<int, 8> Mask1(4U, -1);
4051 SmallVector<int, 8> PermMask;
4052 SVOp->getMask(PermMask);
4056 for (unsigned i = 0; i != 4; ++i) {
4057 int Idx = PermMask[i];
4059 Locs[i] = std::make_pair(-1, -1);
4061 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
4063 Locs[i] = std::make_pair(0, NumLo);
4067 Locs[i] = std::make_pair(1, NumHi);
4069 Mask1[2+NumHi] = Idx;
4075 if (NumLo <= 2 && NumHi <= 2) {
4076 // If no more than two elements come from either vector. This can be
4077 // implemented with two shuffles. First shuffle gather the elements.
4078 // The second shuffle, which takes the first shuffle as both of its
4079 // vector operands, put the elements into the right order.
4080 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
4082 SmallVector<int, 8> Mask2(4U, -1);
4084 for (unsigned i = 0; i != 4; ++i) {
4085 if (Locs[i].first == -1)
4088 unsigned Idx = (i < 2) ? 0 : 4;
4089 Idx += Locs[i].first * 2 + Locs[i].second;
4094 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
4095 } else if (NumLo == 3 || NumHi == 3) {
4096 // Otherwise, we must have three elements from one vector, call it X, and
4097 // one element from the other, call it Y. First, use a shufps to build an
4098 // intermediate vector with the one element from Y and the element from X
4099 // that will be in the same half in the final destination (the indexes don't
4100 // matter). Then, use a shufps to build the final vector, taking the half
4101 // containing the element from Y from the intermediate, and the other half
4104 // Normalize it so the 3 elements come from V1.
4105 CommuteVectorShuffleMask(PermMask, VT);
4109 // Find the element from V2.
4111 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
4112 int Val = PermMask[HiIndex];
4119 Mask1[0] = PermMask[HiIndex];
4121 Mask1[2] = PermMask[HiIndex^1];
4123 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
4126 Mask1[0] = PermMask[0];
4127 Mask1[1] = PermMask[1];
4128 Mask1[2] = HiIndex & 1 ? 6 : 4;
4129 Mask1[3] = HiIndex & 1 ? 4 : 6;
4130 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
4132 Mask1[0] = HiIndex & 1 ? 2 : 0;
4133 Mask1[1] = HiIndex & 1 ? 0 : 2;
4134 Mask1[2] = PermMask[2];
4135 Mask1[3] = PermMask[3];
4140 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
4144 // Break it into (shuffle shuffle_hi, shuffle_lo).
4146 SmallVector<int,8> LoMask(4U, -1);
4147 SmallVector<int,8> HiMask(4U, -1);
4149 SmallVector<int,8> *MaskPtr = &LoMask;
4150 unsigned MaskIdx = 0;
4153 for (unsigned i = 0; i != 4; ++i) {
4160 int Idx = PermMask[i];
4162 Locs[i] = std::make_pair(-1, -1);
4163 } else if (Idx < 4) {
4164 Locs[i] = std::make_pair(MaskIdx, LoIdx);
4165 (*MaskPtr)[LoIdx] = Idx;
4168 Locs[i] = std::make_pair(MaskIdx, HiIdx);
4169 (*MaskPtr)[HiIdx] = Idx;
4174 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
4175 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
4176 SmallVector<int, 8> MaskOps;
4177 for (unsigned i = 0; i != 4; ++i) {
4178 if (Locs[i].first == -1) {
4179 MaskOps.push_back(-1);
4181 unsigned Idx = Locs[i].first * 4 + Locs[i].second;
4182 MaskOps.push_back(Idx);
4185 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
4189 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
4190 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
4191 SDValue V1 = Op.getOperand(0);
4192 SDValue V2 = Op.getOperand(1);
4193 EVT VT = Op.getValueType();
4194 DebugLoc dl = Op.getDebugLoc();
4195 unsigned NumElems = VT.getVectorNumElements();
4196 bool isMMX = VT.getSizeInBits() == 64;
4197 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
4198 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
4199 bool V1IsSplat = false;
4200 bool V2IsSplat = false;
4202 if (isZeroShuffle(SVOp))
4203 return getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
4205 // Promote splats to v4f32.
4206 if (SVOp->isSplat()) {
4207 if (isMMX || NumElems < 4)
4209 return PromoteSplat(SVOp, DAG, Subtarget->hasSSE2());
4212 // If the shuffle can be profitably rewritten as a narrower shuffle, then
4214 if (VT == MVT::v8i16 || VT == MVT::v16i8) {
4215 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl);
4216 if (NewOp.getNode())
4217 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
4218 LowerVECTOR_SHUFFLE(NewOp, DAG));
4219 } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
4220 // FIXME: Figure out a cleaner way to do this.
4221 // Try to make use of movq to zero out the top part.
4222 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
4223 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl);
4224 if (NewOp.getNode()) {
4225 if (isCommutedMOVL(cast<ShuffleVectorSDNode>(NewOp), true, false))
4226 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(0),
4227 DAG, Subtarget, dl);
4229 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
4230 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl);
4231 if (NewOp.getNode() && X86::isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)))
4232 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1),
4233 DAG, Subtarget, dl);
4237 if (X86::isPSHUFDMask(SVOp))
4240 // Check if this can be converted into a logical shift.
4241 bool isLeft = false;
4244 bool isShift = getSubtarget()->hasSSE2() &&
4245 isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
4246 if (isShift && ShVal.hasOneUse()) {
4247 // If the shifted value has multiple uses, it may be cheaper to use
4248 // v_set0 + movlhps or movhlps, etc.
4249 EVT EltVT = VT.getVectorElementType();
4250 ShAmt *= EltVT.getSizeInBits();
4251 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
4254 if (X86::isMOVLMask(SVOp)) {
4257 if (ISD::isBuildVectorAllZeros(V1.getNode()))
4258 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
4263 // FIXME: fold these into legal mask.
4264 if (!isMMX && (X86::isMOVSHDUPMask(SVOp) ||
4265 X86::isMOVSLDUPMask(SVOp) ||
4266 X86::isMOVHLPSMask(SVOp) ||
4267 X86::isMOVHPMask(SVOp) ||
4268 X86::isMOVLPMask(SVOp)))
4271 if (ShouldXformToMOVHLPS(SVOp) ||
4272 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), SVOp))
4273 return CommuteVectorShuffle(SVOp, DAG);
4276 // No better options. Use a vshl / vsrl.
4277 EVT EltVT = VT.getVectorElementType();
4278 ShAmt *= EltVT.getSizeInBits();
4279 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
4282 bool Commuted = false;
4283 // FIXME: This should also accept a bitcast of a splat? Be careful, not
4284 // 1,1,1,1 -> v8i16 though.
4285 V1IsSplat = isSplatVector(V1.getNode());
4286 V2IsSplat = isSplatVector(V2.getNode());
4288 // Canonicalize the splat or undef, if present, to be on the RHS.
4289 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) {
4290 Op = CommuteVectorShuffle(SVOp, DAG);
4291 SVOp = cast<ShuffleVectorSDNode>(Op);
4292 V1 = SVOp->getOperand(0);
4293 V2 = SVOp->getOperand(1);
4294 std::swap(V1IsSplat, V2IsSplat);
4295 std::swap(V1IsUndef, V2IsUndef);
4299 if (isCommutedMOVL(SVOp, V2IsSplat, V2IsUndef)) {
4300 // Shuffling low element of v1 into undef, just return v1.
4303 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
4304 // the instruction selector will not match, so get a canonical MOVL with
4305 // swapped operands to undo the commute.
4306 return getMOVL(DAG, dl, VT, V2, V1);
4309 if (X86::isUNPCKL_v_undef_Mask(SVOp) ||
4310 X86::isUNPCKH_v_undef_Mask(SVOp) ||
4311 X86::isUNPCKLMask(SVOp) ||
4312 X86::isUNPCKHMask(SVOp))
4316 // Normalize mask so all entries that point to V2 points to its first
4317 // element then try to match unpck{h|l} again. If match, return a
4318 // new vector_shuffle with the corrected mask.
4319 SDValue NewMask = NormalizeMask(SVOp, DAG);
4320 ShuffleVectorSDNode *NSVOp = cast<ShuffleVectorSDNode>(NewMask);
4321 if (NSVOp != SVOp) {
4322 if (X86::isUNPCKLMask(NSVOp, true)) {
4324 } else if (X86::isUNPCKHMask(NSVOp, true)) {
4331 // Commute is back and try unpck* again.
4332 // FIXME: this seems wrong.
4333 SDValue NewOp = CommuteVectorShuffle(SVOp, DAG);
4334 ShuffleVectorSDNode *NewSVOp = cast<ShuffleVectorSDNode>(NewOp);
4335 if (X86::isUNPCKL_v_undef_Mask(NewSVOp) ||
4336 X86::isUNPCKH_v_undef_Mask(NewSVOp) ||
4337 X86::isUNPCKLMask(NewSVOp) ||
4338 X86::isUNPCKHMask(NewSVOp))
4342 // FIXME: for mmx, bitcast v2i32 to v4i16 for shuffle.
4344 // Normalize the node to match x86 shuffle ops if needed
4345 if (!isMMX && V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(SVOp))
4346 return CommuteVectorShuffle(SVOp, DAG);
4348 // Check for legal shuffle and return?
4349 SmallVector<int, 16> PermMask;
4350 SVOp->getMask(PermMask);
4351 if (isShuffleMaskLegal(PermMask, VT))
4354 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
4355 if (VT == MVT::v8i16) {
4356 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(SVOp, DAG, *this);
4357 if (NewOp.getNode())
4361 if (VT == MVT::v16i8) {
4362 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this);
4363 if (NewOp.getNode())
4367 // Handle all 4 wide cases with a number of shuffles except for MMX.
4368 if (NumElems == 4 && !isMMX)
4369 return LowerVECTOR_SHUFFLE_4wide(SVOp, DAG);
4375 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
4376 SelectionDAG &DAG) {
4377 EVT VT = Op.getValueType();
4378 DebugLoc dl = Op.getDebugLoc();
4379 if (VT.getSizeInBits() == 8) {
4380 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
4381 Op.getOperand(0), Op.getOperand(1));
4382 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
4383 DAG.getValueType(VT));
4384 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
4385 } else if (VT.getSizeInBits() == 16) {
4386 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4387 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
4389 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
4390 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
4391 DAG.getNode(ISD::BIT_CONVERT, dl,
4395 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
4396 Op.getOperand(0), Op.getOperand(1));
4397 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
4398 DAG.getValueType(VT));
4399 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
4400 } else if (VT == MVT::f32) {
4401 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
4402 // the result back to FR32 register. It's only worth matching if the
4403 // result has a single use which is a store or a bitcast to i32. And in
4404 // the case of a store, it's not worth it if the index is a constant 0,
4405 // because a MOVSSmr can be used instead, which is smaller and faster.
4406 if (!Op.hasOneUse())
4408 SDNode *User = *Op.getNode()->use_begin();
4409 if ((User->getOpcode() != ISD::STORE ||
4410 (isa<ConstantSDNode>(Op.getOperand(1)) &&
4411 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
4412 (User->getOpcode() != ISD::BIT_CONVERT ||
4413 User->getValueType(0) != MVT::i32))
4415 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
4416 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32,
4419 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Extract);
4420 } else if (VT == MVT::i32) {
4421 // ExtractPS works with constant index.
4422 if (isa<ConstantSDNode>(Op.getOperand(1)))
4430 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
4431 if (!isa<ConstantSDNode>(Op.getOperand(1)))
4434 if (Subtarget->hasSSE41()) {
4435 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
4440 EVT VT = Op.getValueType();
4441 DebugLoc dl = Op.getDebugLoc();
4442 // TODO: handle v16i8.
4443 if (VT.getSizeInBits() == 16) {
4444 SDValue Vec = Op.getOperand(0);
4445 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4447 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
4448 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
4449 DAG.getNode(ISD::BIT_CONVERT, dl,
4452 // Transform it so it match pextrw which produces a 32-bit result.
4453 EVT EltVT = (MVT::SimpleValueType)(VT.getSimpleVT().SimpleTy+1);
4454 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
4455 Op.getOperand(0), Op.getOperand(1));
4456 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
4457 DAG.getValueType(VT));
4458 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
4459 } else if (VT.getSizeInBits() == 32) {
4460 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4464 // SHUFPS the element to the lowest double word, then movss.
4465 int Mask[4] = { Idx, -1, -1, -1 };
4466 EVT VVT = Op.getOperand(0).getValueType();
4467 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
4468 DAG.getUNDEF(VVT), Mask);
4469 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
4470 DAG.getIntPtrConstant(0));
4471 } else if (VT.getSizeInBits() == 64) {
4472 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
4473 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
4474 // to match extract_elt for f64.
4475 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4479 // UNPCKHPD the element to the lowest double word, then movsd.
4480 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
4481 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
4482 int Mask[2] = { 1, -1 };
4483 EVT VVT = Op.getOperand(0).getValueType();
4484 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
4485 DAG.getUNDEF(VVT), Mask);
4486 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
4487 DAG.getIntPtrConstant(0));
4494 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG){
4495 EVT VT = Op.getValueType();
4496 EVT EltVT = VT.getVectorElementType();
4497 DebugLoc dl = Op.getDebugLoc();
4499 SDValue N0 = Op.getOperand(0);
4500 SDValue N1 = Op.getOperand(1);
4501 SDValue N2 = Op.getOperand(2);
4503 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
4504 isa<ConstantSDNode>(N2)) {
4505 unsigned Opc = (EltVT.getSizeInBits() == 8) ? X86ISD::PINSRB
4507 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
4509 if (N1.getValueType() != MVT::i32)
4510 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
4511 if (N2.getValueType() != MVT::i32)
4512 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
4513 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
4514 } else if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
4515 // Bits [7:6] of the constant are the source select. This will always be
4516 // zero here. The DAG Combiner may combine an extract_elt index into these
4517 // bits. For example (insert (extract, 3), 2) could be matched by putting
4518 // the '3' into bits [7:6] of X86ISD::INSERTPS.
4519 // Bits [5:4] of the constant are the destination select. This is the
4520 // value of the incoming immediate.
4521 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
4522 // combine either bitwise AND or insert of float 0.0 to set these bits.
4523 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
4524 // Create this as a scalar to vector..
4525 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
4526 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
4527 } else if (EltVT == MVT::i32 && isa<ConstantSDNode>(N2)) {
4528 // PINSR* works with constant index.
4535 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
4536 EVT VT = Op.getValueType();
4537 EVT EltVT = VT.getVectorElementType();
4539 if (Subtarget->hasSSE41())
4540 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
4542 if (EltVT == MVT::i8)
4545 DebugLoc dl = Op.getDebugLoc();
4546 SDValue N0 = Op.getOperand(0);
4547 SDValue N1 = Op.getOperand(1);
4548 SDValue N2 = Op.getOperand(2);
4550 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
4551 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
4552 // as its second argument.
4553 if (N1.getValueType() != MVT::i32)
4554 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
4555 if (N2.getValueType() != MVT::i32)
4556 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
4557 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
4563 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
4564 DebugLoc dl = Op.getDebugLoc();
4565 if (Op.getValueType() == MVT::v2f32)
4566 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f32,
4567 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i32,
4568 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32,
4569 Op.getOperand(0))));
4571 if (Op.getValueType() == MVT::v1i64 && Op.getOperand(0).getValueType() == MVT::i64)
4572 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
4574 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
4575 EVT VT = MVT::v2i32;
4576 switch (Op.getValueType().getSimpleVT().SimpleTy) {
4583 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(),
4584 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, AnyExt));
4587 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
4588 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
4589 // one of the above mentioned nodes. It has to be wrapped because otherwise
4590 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
4591 // be used to form addressing mode. These wrapped nodes will be selected
4594 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
4595 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
4597 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
4599 unsigned char OpFlag = 0;
4600 unsigned WrapperKind = X86ISD::Wrapper;
4601 CodeModel::Model M = getTargetMachine().getCodeModel();
4603 if (Subtarget->isPICStyleRIPRel() &&
4604 (M == CodeModel::Small || M == CodeModel::Kernel))
4605 WrapperKind = X86ISD::WrapperRIP;
4606 else if (Subtarget->isPICStyleGOT())
4607 OpFlag = X86II::MO_GOTOFF;
4608 else if (Subtarget->isPICStyleStubPIC())
4609 OpFlag = X86II::MO_PIC_BASE_OFFSET;
4611 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
4613 CP->getOffset(), OpFlag);
4614 DebugLoc DL = CP->getDebugLoc();
4615 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
4616 // With PIC, the address is actually $g + Offset.
4618 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
4619 DAG.getNode(X86ISD::GlobalBaseReg,
4620 DebugLoc::getUnknownLoc(), getPointerTy()),
4627 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) {
4628 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
4630 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
4632 unsigned char OpFlag = 0;
4633 unsigned WrapperKind = X86ISD::Wrapper;
4634 CodeModel::Model M = getTargetMachine().getCodeModel();
4636 if (Subtarget->isPICStyleRIPRel() &&
4637 (M == CodeModel::Small || M == CodeModel::Kernel))
4638 WrapperKind = X86ISD::WrapperRIP;
4639 else if (Subtarget->isPICStyleGOT())
4640 OpFlag = X86II::MO_GOTOFF;
4641 else if (Subtarget->isPICStyleStubPIC())
4642 OpFlag = X86II::MO_PIC_BASE_OFFSET;
4644 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
4646 DebugLoc DL = JT->getDebugLoc();
4647 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
4649 // With PIC, the address is actually $g + Offset.
4651 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
4652 DAG.getNode(X86ISD::GlobalBaseReg,
4653 DebugLoc::getUnknownLoc(), getPointerTy()),
4661 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) {
4662 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
4664 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
4666 unsigned char OpFlag = 0;
4667 unsigned WrapperKind = X86ISD::Wrapper;
4668 CodeModel::Model M = getTargetMachine().getCodeModel();
4670 if (Subtarget->isPICStyleRIPRel() &&
4671 (M == CodeModel::Small || M == CodeModel::Kernel))
4672 WrapperKind = X86ISD::WrapperRIP;
4673 else if (Subtarget->isPICStyleGOT())
4674 OpFlag = X86II::MO_GOTOFF;
4675 else if (Subtarget->isPICStyleStubPIC())
4676 OpFlag = X86II::MO_PIC_BASE_OFFSET;
4678 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
4680 DebugLoc DL = Op.getDebugLoc();
4681 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
4684 // With PIC, the address is actually $g + Offset.
4685 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
4686 !Subtarget->is64Bit()) {
4687 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
4688 DAG.getNode(X86ISD::GlobalBaseReg,
4689 DebugLoc::getUnknownLoc(),
4698 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) {
4699 unsigned WrapperKind = X86ISD::Wrapper;
4700 CodeModel::Model M = getTargetMachine().getCodeModel();
4701 if (Subtarget->isPICStyleRIPRel() &&
4702 (M == CodeModel::Small || M == CodeModel::Kernel))
4703 WrapperKind = X86ISD::WrapperRIP;
4705 DebugLoc DL = Op.getDebugLoc();
4707 BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
4708 SDValue Result = DAG.getBlockAddress(BA, DL, /*isTarget=*/true);
4710 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
4716 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
4718 SelectionDAG &DAG) const {
4719 // Create the TargetGlobalAddress node, folding in the constant
4720 // offset if it is legal.
4721 unsigned char OpFlags =
4722 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
4723 CodeModel::Model M = getTargetMachine().getCodeModel();
4725 if (OpFlags == X86II::MO_NO_FLAG &&
4726 X86::isOffsetSuitableForCodeModel(Offset, M)) {
4727 // A direct static reference to a global.
4728 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), Offset);
4731 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), 0, OpFlags);
4734 if (Subtarget->isPICStyleRIPRel() &&
4735 (M == CodeModel::Small || M == CodeModel::Kernel))
4736 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
4738 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
4740 // With PIC, the address is actually $g + Offset.
4741 if (isGlobalRelativeToPICBase(OpFlags)) {
4742 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
4743 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
4747 // For globals that require a load from a stub to get the address, emit the
4749 if (isGlobalStubReference(OpFlags))
4750 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
4751 PseudoSourceValue::getGOT(), 0);
4753 // If there was a non-zero offset that we didn't fold, create an explicit
4756 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
4757 DAG.getConstant(Offset, getPointerTy()));
4763 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) {
4764 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
4765 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
4766 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
4770 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
4771 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
4772 unsigned char OperandFlags) {
4773 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
4774 DebugLoc dl = GA->getDebugLoc();
4775 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
4776 GA->getValueType(0),
4780 SDValue Ops[] = { Chain, TGA, *InFlag };
4781 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3);
4783 SDValue Ops[] = { Chain, TGA };
4784 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2);
4786 SDValue Flag = Chain.getValue(1);
4787 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
4790 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
4792 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
4795 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
4796 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
4797 DAG.getNode(X86ISD::GlobalBaseReg,
4798 DebugLoc::getUnknownLoc(),
4800 InFlag = Chain.getValue(1);
4802 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
4805 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
4807 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
4809 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
4810 X86::RAX, X86II::MO_TLSGD);
4813 // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
4814 // "local exec" model.
4815 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
4816 const EVT PtrVT, TLSModel::Model model,
4818 DebugLoc dl = GA->getDebugLoc();
4819 // Get the Thread Pointer
4820 SDValue Base = DAG.getNode(X86ISD::SegmentBaseAddress,
4821 DebugLoc::getUnknownLoc(), PtrVT,
4822 DAG.getRegister(is64Bit? X86::FS : X86::GS,
4825 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Base,
4828 unsigned char OperandFlags = 0;
4829 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
4831 unsigned WrapperKind = X86ISD::Wrapper;
4832 if (model == TLSModel::LocalExec) {
4833 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
4834 } else if (is64Bit) {
4835 assert(model == TLSModel::InitialExec);
4836 OperandFlags = X86II::MO_GOTTPOFF;
4837 WrapperKind = X86ISD::WrapperRIP;
4839 assert(model == TLSModel::InitialExec);
4840 OperandFlags = X86II::MO_INDNTPOFF;
4843 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
4845 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), GA->getValueType(0),
4846 GA->getOffset(), OperandFlags);
4847 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
4849 if (model == TLSModel::InitialExec)
4850 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
4851 PseudoSourceValue::getGOT(), 0);
4853 // The address of the thread local variable is the add of the thread
4854 // pointer with the offset of the variable.
4855 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
4859 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) {
4860 // TODO: implement the "local dynamic" model
4861 // TODO: implement the "initial exec"model for pic executables
4862 assert(Subtarget->isTargetELF() &&
4863 "TLS not implemented for non-ELF targets");
4864 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
4865 const GlobalValue *GV = GA->getGlobal();
4867 // If GV is an alias then use the aliasee for determining
4868 // thread-localness.
4869 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
4870 GV = GA->resolveAliasedGlobal(false);
4872 TLSModel::Model model = getTLSModel(GV,
4873 getTargetMachine().getRelocationModel());
4876 case TLSModel::GeneralDynamic:
4877 case TLSModel::LocalDynamic: // not implemented
4878 if (Subtarget->is64Bit())
4879 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
4880 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
4882 case TLSModel::InitialExec:
4883 case TLSModel::LocalExec:
4884 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
4885 Subtarget->is64Bit());
4888 llvm_unreachable("Unreachable");
4893 /// LowerShift - Lower SRA_PARTS and friends, which return two i32 values and
4894 /// take a 2 x i32 value to shift plus a shift amount.
4895 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) {
4896 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
4897 EVT VT = Op.getValueType();
4898 unsigned VTBits = VT.getSizeInBits();
4899 DebugLoc dl = Op.getDebugLoc();
4900 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
4901 SDValue ShOpLo = Op.getOperand(0);
4902 SDValue ShOpHi = Op.getOperand(1);
4903 SDValue ShAmt = Op.getOperand(2);
4904 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
4905 DAG.getConstant(VTBits - 1, MVT::i8))
4906 : DAG.getConstant(0, VT);
4909 if (Op.getOpcode() == ISD::SHL_PARTS) {
4910 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
4911 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
4913 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
4914 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
4917 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
4918 DAG.getConstant(VTBits, MVT::i8));
4919 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, VT,
4920 AndNode, DAG.getConstant(0, MVT::i8));
4923 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
4924 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
4925 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
4927 if (Op.getOpcode() == ISD::SHL_PARTS) {
4928 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
4929 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
4931 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
4932 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
4935 SDValue Ops[2] = { Lo, Hi };
4936 return DAG.getMergeValues(Ops, 2, dl);
4939 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
4940 EVT SrcVT = Op.getOperand(0).getValueType();
4942 if (SrcVT.isVector()) {
4943 if (SrcVT == MVT::v2i32 && Op.getValueType() == MVT::v2f64) {
4949 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
4950 "Unknown SINT_TO_FP to lower!");
4952 // These are really Legal; return the operand so the caller accepts it as
4954 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
4956 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
4957 Subtarget->is64Bit()) {
4961 DebugLoc dl = Op.getDebugLoc();
4962 unsigned Size = SrcVT.getSizeInBits()/8;
4963 MachineFunction &MF = DAG.getMachineFunction();
4964 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
4965 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
4966 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
4968 PseudoSourceValue::getFixedStack(SSFI), 0);
4969 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
4972 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
4974 SelectionDAG &DAG) {
4976 DebugLoc dl = Op.getDebugLoc();
4978 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
4980 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag);
4982 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
4983 SmallVector<SDValue, 8> Ops;
4984 Ops.push_back(Chain);
4985 Ops.push_back(StackSlot);
4986 Ops.push_back(DAG.getValueType(SrcVT));
4987 SDValue Result = DAG.getNode(useSSE ? X86ISD::FILD_FLAG : X86ISD::FILD, dl,
4988 Tys, &Ops[0], Ops.size());
4991 Chain = Result.getValue(1);
4992 SDValue InFlag = Result.getValue(2);
4994 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
4995 // shouldn't be necessary except that RFP cannot be live across
4996 // multiple blocks. When stackifier is fixed, they can be uncoupled.
4997 MachineFunction &MF = DAG.getMachineFunction();
4998 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
4999 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5000 Tys = DAG.getVTList(MVT::Other);
5001 SmallVector<SDValue, 8> Ops;
5002 Ops.push_back(Chain);
5003 Ops.push_back(Result);
5004 Ops.push_back(StackSlot);
5005 Ops.push_back(DAG.getValueType(Op.getValueType()));
5006 Ops.push_back(InFlag);
5007 Chain = DAG.getNode(X86ISD::FST, dl, Tys, &Ops[0], Ops.size());
5008 Result = DAG.getLoad(Op.getValueType(), dl, Chain, StackSlot,
5009 PseudoSourceValue::getFixedStack(SSFI), 0);
5015 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
5016 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) {
5017 // This algorithm is not obvious. Here it is in C code, more or less:
5019 double uint64_to_double( uint32_t hi, uint32_t lo ) {
5020 static const __m128i exp = { 0x4330000045300000ULL, 0 };
5021 static const __m128d bias = { 0x1.0p84, 0x1.0p52 };
5023 // Copy ints to xmm registers.
5024 __m128i xh = _mm_cvtsi32_si128( hi );
5025 __m128i xl = _mm_cvtsi32_si128( lo );
5027 // Combine into low half of a single xmm register.
5028 __m128i x = _mm_unpacklo_epi32( xh, xl );
5032 // Merge in appropriate exponents to give the integer bits the right
5034 x = _mm_unpacklo_epi32( x, exp );
5036 // Subtract away the biases to deal with the IEEE-754 double precision
5038 d = _mm_sub_pd( (__m128d) x, bias );
5040 // All conversions up to here are exact. The correctly rounded result is
5041 // calculated using the current rounding mode using the following
5043 d = _mm_add_sd( d, _mm_unpackhi_pd( d, d ) );
5044 _mm_store_sd( &sd, d ); // Because we are returning doubles in XMM, this
5045 // store doesn't really need to be here (except
5046 // maybe to zero the other double)
5051 DebugLoc dl = Op.getDebugLoc();
5052 LLVMContext *Context = DAG.getContext();
5054 // Build some magic constants.
5055 std::vector<Constant*> CV0;
5056 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x45300000)));
5057 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x43300000)));
5058 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
5059 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
5060 Constant *C0 = ConstantVector::get(CV0);
5061 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
5063 std::vector<Constant*> CV1;
5065 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL))));
5067 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL))));
5068 Constant *C1 = ConstantVector::get(CV1);
5069 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
5071 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
5072 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
5074 DAG.getIntPtrConstant(1)));
5075 SDValue XR2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
5076 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
5078 DAG.getIntPtrConstant(0)));
5079 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, XR1, XR2);
5080 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
5081 PseudoSourceValue::getConstantPool(), 0,
5083 SDValue Unpck2 = getUnpackl(DAG, dl, MVT::v4i32, Unpck1, CLod0);
5084 SDValue XR2F = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Unpck2);
5085 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
5086 PseudoSourceValue::getConstantPool(), 0,
5088 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
5090 // Add the halves; easiest way is to swap them into another reg first.
5091 int ShufMask[2] = { 1, -1 };
5092 SDValue Shuf = DAG.getVectorShuffle(MVT::v2f64, dl, Sub,
5093 DAG.getUNDEF(MVT::v2f64), ShufMask);
5094 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::v2f64, Shuf, Sub);
5095 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Add,
5096 DAG.getIntPtrConstant(0));
5099 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
5100 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) {
5101 DebugLoc dl = Op.getDebugLoc();
5102 // FP constant to bias correct the final result.
5103 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
5106 // Load the 32-bit value into an XMM register.
5107 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
5108 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
5110 DAG.getIntPtrConstant(0)));
5112 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
5113 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Load),
5114 DAG.getIntPtrConstant(0));
5116 // Or the load with the bias.
5117 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
5118 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
5119 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5121 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
5122 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5123 MVT::v2f64, Bias)));
5124 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
5125 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Or),
5126 DAG.getIntPtrConstant(0));
5128 // Subtract the bias.
5129 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
5131 // Handle final rounding.
5132 EVT DestVT = Op.getValueType();
5134 if (DestVT.bitsLT(MVT::f64)) {
5135 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
5136 DAG.getIntPtrConstant(0));
5137 } else if (DestVT.bitsGT(MVT::f64)) {
5138 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
5141 // Handle final rounding.
5145 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
5146 SDValue N0 = Op.getOperand(0);
5147 DebugLoc dl = Op.getDebugLoc();
5149 // Now not UINT_TO_FP is legal (it's marked custom), dag combiner won't
5150 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
5151 // the optimization here.
5152 if (DAG.SignBitIsZero(N0))
5153 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
5155 EVT SrcVT = N0.getValueType();
5156 if (SrcVT == MVT::i64) {
5157 // We only handle SSE2 f64 target here; caller can expand the rest.
5158 if (Op.getValueType() != MVT::f64 || !X86ScalarSSEf64)
5161 return LowerUINT_TO_FP_i64(Op, DAG);
5162 } else if (SrcVT == MVT::i32 && X86ScalarSSEf64) {
5163 return LowerUINT_TO_FP_i32(Op, DAG);
5166 assert(SrcVT == MVT::i32 && "Unknown UINT_TO_FP to lower!");
5168 // Make a 64-bit buffer, and use it to build an FILD.
5169 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
5170 SDValue WordOff = DAG.getConstant(4, getPointerTy());
5171 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
5172 getPointerTy(), StackSlot, WordOff);
5173 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
5174 StackSlot, NULL, 0);
5175 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
5176 OffsetSlot, NULL, 0);
5177 return BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
5180 std::pair<SDValue,SDValue> X86TargetLowering::
5181 FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) {
5182 DebugLoc dl = Op.getDebugLoc();
5184 EVT DstTy = Op.getValueType();
5187 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
5191 assert(DstTy.getSimpleVT() <= MVT::i64 &&
5192 DstTy.getSimpleVT() >= MVT::i16 &&
5193 "Unknown FP_TO_SINT to lower!");
5195 // These are really Legal.
5196 if (DstTy == MVT::i32 &&
5197 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
5198 return std::make_pair(SDValue(), SDValue());
5199 if (Subtarget->is64Bit() &&
5200 DstTy == MVT::i64 &&
5201 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
5202 return std::make_pair(SDValue(), SDValue());
5204 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
5206 MachineFunction &MF = DAG.getMachineFunction();
5207 unsigned MemSize = DstTy.getSizeInBits()/8;
5208 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
5209 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5212 switch (DstTy.getSimpleVT().SimpleTy) {
5213 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
5214 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
5215 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
5216 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
5219 SDValue Chain = DAG.getEntryNode();
5220 SDValue Value = Op.getOperand(0);
5221 if (isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) {
5222 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
5223 Chain = DAG.getStore(Chain, dl, Value, StackSlot,
5224 PseudoSourceValue::getFixedStack(SSFI), 0);
5225 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
5227 Chain, StackSlot, DAG.getValueType(Op.getOperand(0).getValueType())
5229 Value = DAG.getNode(X86ISD::FLD, dl, Tys, Ops, 3);
5230 Chain = Value.getValue(1);
5231 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
5232 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5235 // Build the FP_TO_INT*_IN_MEM
5236 SDValue Ops[] = { Chain, Value, StackSlot };
5237 SDValue FIST = DAG.getNode(Opc, dl, MVT::Other, Ops, 3);
5239 return std::make_pair(FIST, StackSlot);
5242 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) {
5243 if (Op.getValueType().isVector()) {
5244 if (Op.getValueType() == MVT::v2i32 &&
5245 Op.getOperand(0).getValueType() == MVT::v2f64) {
5251 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, true);
5252 SDValue FIST = Vals.first, StackSlot = Vals.second;
5253 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
5254 if (FIST.getNode() == 0) return Op;
5257 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
5258 FIST, StackSlot, NULL, 0);
5261 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) {
5262 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, false);
5263 SDValue FIST = Vals.first, StackSlot = Vals.second;
5264 assert(FIST.getNode() && "Unexpected failure");
5267 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
5268 FIST, StackSlot, NULL, 0);
5271 SDValue X86TargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) {
5272 LLVMContext *Context = DAG.getContext();
5273 DebugLoc dl = Op.getDebugLoc();
5274 EVT VT = Op.getValueType();
5277 EltVT = VT.getVectorElementType();
5278 std::vector<Constant*> CV;
5279 if (EltVT == MVT::f64) {
5280 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))));
5284 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))));
5290 Constant *C = ConstantVector::get(CV);
5291 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5292 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
5293 PseudoSourceValue::getConstantPool(), 0,
5295 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
5298 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) {
5299 LLVMContext *Context = DAG.getContext();
5300 DebugLoc dl = Op.getDebugLoc();
5301 EVT VT = Op.getValueType();
5304 EltVT = VT.getVectorElementType();
5305 std::vector<Constant*> CV;
5306 if (EltVT == MVT::f64) {
5307 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)));
5311 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)));
5317 Constant *C = ConstantVector::get(CV);
5318 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5319 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
5320 PseudoSourceValue::getConstantPool(), 0,
5322 if (VT.isVector()) {
5323 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
5324 DAG.getNode(ISD::XOR, dl, MVT::v2i64,
5325 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
5327 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, Mask)));
5329 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
5333 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
5334 LLVMContext *Context = DAG.getContext();
5335 SDValue Op0 = Op.getOperand(0);
5336 SDValue Op1 = Op.getOperand(1);
5337 DebugLoc dl = Op.getDebugLoc();
5338 EVT VT = Op.getValueType();
5339 EVT SrcVT = Op1.getValueType();
5341 // If second operand is smaller, extend it first.
5342 if (SrcVT.bitsLT(VT)) {
5343 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
5346 // And if it is bigger, shrink it first.
5347 if (SrcVT.bitsGT(VT)) {
5348 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
5352 // At this point the operands and the result should have the same
5353 // type, and that won't be f80 since that is not custom lowered.
5355 // First get the sign bit of second operand.
5356 std::vector<Constant*> CV;
5357 if (SrcVT == MVT::f64) {
5358 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))));
5359 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
5361 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))));
5362 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5363 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5364 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5366 Constant *C = ConstantVector::get(CV);
5367 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5368 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
5369 PseudoSourceValue::getConstantPool(), 0,
5371 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
5373 // Shift sign bit right or left if the two operands have different types.
5374 if (SrcVT.bitsGT(VT)) {
5375 // Op0 is MVT::f32, Op1 is MVT::f64.
5376 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
5377 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
5378 DAG.getConstant(32, MVT::i32));
5379 SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4f32, SignBit);
5380 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
5381 DAG.getIntPtrConstant(0));
5384 // Clear first operand sign bit.
5386 if (VT == MVT::f64) {
5387 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
5388 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
5390 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
5391 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5392 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5393 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5395 C = ConstantVector::get(CV);
5396 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5397 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
5398 PseudoSourceValue::getConstantPool(), 0,
5400 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
5402 // Or the value with the sign bit.
5403 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
5406 /// Emit nodes that will be selected as "test Op0,Op0", or something
5408 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
5409 SelectionDAG &DAG) {
5410 DebugLoc dl = Op.getDebugLoc();
5412 // CF and OF aren't always set the way we want. Determine which
5413 // of these we need.
5414 bool NeedCF = false;
5415 bool NeedOF = false;
5417 case X86::COND_A: case X86::COND_AE:
5418 case X86::COND_B: case X86::COND_BE:
5421 case X86::COND_G: case X86::COND_GE:
5422 case X86::COND_L: case X86::COND_LE:
5423 case X86::COND_O: case X86::COND_NO:
5429 // See if we can use the EFLAGS value from the operand instead of
5430 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
5431 // we prove that the arithmetic won't overflow, we can't use OF or CF.
5432 if (Op.getResNo() == 0 && !NeedOF && !NeedCF) {
5433 unsigned Opcode = 0;
5434 unsigned NumOperands = 0;
5435 switch (Op.getNode()->getOpcode()) {
5437 // Due to an isel shortcoming, be conservative if this add is likely to
5438 // be selected as part of a load-modify-store instruction. When the root
5439 // node in a match is a store, isel doesn't know how to remap non-chain
5440 // non-flag uses of other nodes in the match, such as the ADD in this
5441 // case. This leads to the ADD being left around and reselected, with
5442 // the result being two adds in the output.
5443 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
5444 UE = Op.getNode()->use_end(); UI != UE; ++UI)
5445 if (UI->getOpcode() == ISD::STORE)
5447 if (ConstantSDNode *C =
5448 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) {
5449 // An add of one will be selected as an INC.
5450 if (C->getAPIntValue() == 1) {
5451 Opcode = X86ISD::INC;
5455 // An add of negative one (subtract of one) will be selected as a DEC.
5456 if (C->getAPIntValue().isAllOnesValue()) {
5457 Opcode = X86ISD::DEC;
5462 // Otherwise use a regular EFLAGS-setting add.
5463 Opcode = X86ISD::ADD;
5467 // If the primary and result isn't used, don't bother using X86ISD::AND,
5468 // because a TEST instruction will be better.
5469 bool NonFlagUse = false;
5470 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
5471 UE = Op.getNode()->use_end(); UI != UE; ++UI)
5472 if (UI->getOpcode() != ISD::BRCOND &&
5473 UI->getOpcode() != ISD::SELECT &&
5474 UI->getOpcode() != ISD::SETCC) {
5485 // Due to the ISEL shortcoming noted above, be conservative if this op is
5486 // likely to be selected as part of a load-modify-store instruction.
5487 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
5488 UE = Op.getNode()->use_end(); UI != UE; ++UI)
5489 if (UI->getOpcode() == ISD::STORE)
5491 // Otherwise use a regular EFLAGS-setting instruction.
5492 switch (Op.getNode()->getOpcode()) {
5493 case ISD::SUB: Opcode = X86ISD::SUB; break;
5494 case ISD::OR: Opcode = X86ISD::OR; break;
5495 case ISD::XOR: Opcode = X86ISD::XOR; break;
5496 case ISD::AND: Opcode = X86ISD::AND; break;
5497 default: llvm_unreachable("unexpected operator!");
5508 return SDValue(Op.getNode(), 1);
5514 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
5515 SmallVector<SDValue, 4> Ops;
5516 for (unsigned i = 0; i != NumOperands; ++i)
5517 Ops.push_back(Op.getOperand(i));
5518 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
5519 DAG.ReplaceAllUsesWith(Op, New);
5520 return SDValue(New.getNode(), 1);
5524 // Otherwise just emit a CMP with 0, which is the TEST pattern.
5525 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
5526 DAG.getConstant(0, Op.getValueType()));
5529 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
5531 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
5532 SelectionDAG &DAG) {
5533 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
5534 if (C->getAPIntValue() == 0)
5535 return EmitTest(Op0, X86CC, DAG);
5537 DebugLoc dl = Op0.getDebugLoc();
5538 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
5541 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) {
5542 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
5543 SDValue Op0 = Op.getOperand(0);
5544 SDValue Op1 = Op.getOperand(1);
5545 DebugLoc dl = Op.getDebugLoc();
5546 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
5548 // Lower (X & (1 << N)) == 0 to BT(X, N).
5549 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
5550 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
5551 if (Op0.getOpcode() == ISD::AND &&
5553 Op1.getOpcode() == ISD::Constant &&
5554 cast<ConstantSDNode>(Op1)->getZExtValue() == 0 &&
5555 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
5557 if (Op0.getOperand(1).getOpcode() == ISD::SHL) {
5558 if (ConstantSDNode *Op010C =
5559 dyn_cast<ConstantSDNode>(Op0.getOperand(1).getOperand(0)))
5560 if (Op010C->getZExtValue() == 1) {
5561 LHS = Op0.getOperand(0);
5562 RHS = Op0.getOperand(1).getOperand(1);
5564 } else if (Op0.getOperand(0).getOpcode() == ISD::SHL) {
5565 if (ConstantSDNode *Op000C =
5566 dyn_cast<ConstantSDNode>(Op0.getOperand(0).getOperand(0)))
5567 if (Op000C->getZExtValue() == 1) {
5568 LHS = Op0.getOperand(1);
5569 RHS = Op0.getOperand(0).getOperand(1);
5571 } else if (Op0.getOperand(1).getOpcode() == ISD::Constant) {
5572 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op0.getOperand(1));
5573 SDValue AndLHS = Op0.getOperand(0);
5574 if (AndRHS->getZExtValue() == 1 && AndLHS.getOpcode() == ISD::SRL) {
5575 LHS = AndLHS.getOperand(0);
5576 RHS = AndLHS.getOperand(1);
5580 if (LHS.getNode()) {
5581 // If LHS is i8, promote it to i16 with any_extend. There is no i8 BT
5582 // instruction. Since the shift amount is in-range-or-undefined, we know
5583 // that doing a bittest on the i16 value is ok. We extend to i32 because
5584 // the encoding for the i16 version is larger than the i32 version.
5585 if (LHS.getValueType() == MVT::i8)
5586 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
5588 // If the operand types disagree, extend the shift amount to match. Since
5589 // BT ignores high bits (like shifts) we can use anyextend.
5590 if (LHS.getValueType() != RHS.getValueType())
5591 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
5593 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
5594 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
5595 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
5596 DAG.getConstant(Cond, MVT::i8), BT);
5600 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
5601 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
5602 if (X86CC == X86::COND_INVALID)
5605 SDValue Cond = EmitCmp(Op0, Op1, X86CC, DAG);
5606 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
5607 DAG.getConstant(X86CC, MVT::i8), Cond);
5610 SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
5612 SDValue Op0 = Op.getOperand(0);
5613 SDValue Op1 = Op.getOperand(1);
5614 SDValue CC = Op.getOperand(2);
5615 EVT VT = Op.getValueType();
5616 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
5617 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
5618 DebugLoc dl = Op.getDebugLoc();
5622 EVT VT0 = Op0.getValueType();
5623 assert(VT0 == MVT::v4f32 || VT0 == MVT::v2f64);
5624 unsigned Opc = VT0 == MVT::v4f32 ? X86ISD::CMPPS : X86ISD::CMPPD;
5627 switch (SetCCOpcode) {
5630 case ISD::SETEQ: SSECC = 0; break;
5632 case ISD::SETGT: Swap = true; // Fallthrough
5634 case ISD::SETOLT: SSECC = 1; break;
5636 case ISD::SETGE: Swap = true; // Fallthrough
5638 case ISD::SETOLE: SSECC = 2; break;
5639 case ISD::SETUO: SSECC = 3; break;
5641 case ISD::SETNE: SSECC = 4; break;
5642 case ISD::SETULE: Swap = true;
5643 case ISD::SETUGE: SSECC = 5; break;
5644 case ISD::SETULT: Swap = true;
5645 case ISD::SETUGT: SSECC = 6; break;
5646 case ISD::SETO: SSECC = 7; break;
5649 std::swap(Op0, Op1);
5651 // In the two special cases we can't handle, emit two comparisons.
5653 if (SetCCOpcode == ISD::SETUEQ) {
5655 UNORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(3, MVT::i8));
5656 EQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(0, MVT::i8));
5657 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ);
5659 else if (SetCCOpcode == ISD::SETONE) {
5661 ORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(7, MVT::i8));
5662 NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, MVT::i8));
5663 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ);
5665 llvm_unreachable("Illegal FP comparison");
5667 // Handle all other FP comparisons here.
5668 return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8));
5671 // We are handling one of the integer comparisons here. Since SSE only has
5672 // GT and EQ comparisons for integer, swapping operands and multiple
5673 // operations may be required for some comparisons.
5674 unsigned Opc = 0, EQOpc = 0, GTOpc = 0;
5675 bool Swap = false, Invert = false, FlipSigns = false;
5677 switch (VT.getSimpleVT().SimpleTy) {
5680 case MVT::v16i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break;
5682 case MVT::v8i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break;
5684 case MVT::v4i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break;
5685 case MVT::v2i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break;
5688 switch (SetCCOpcode) {
5690 case ISD::SETNE: Invert = true;
5691 case ISD::SETEQ: Opc = EQOpc; break;
5692 case ISD::SETLT: Swap = true;
5693 case ISD::SETGT: Opc = GTOpc; break;
5694 case ISD::SETGE: Swap = true;
5695 case ISD::SETLE: Opc = GTOpc; Invert = true; break;
5696 case ISD::SETULT: Swap = true;
5697 case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break;
5698 case ISD::SETUGE: Swap = true;
5699 case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break;
5702 std::swap(Op0, Op1);
5704 // Since SSE has no unsigned integer comparisons, we need to flip the sign
5705 // bits of the inputs before performing those operations.
5707 EVT EltVT = VT.getVectorElementType();
5708 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
5710 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
5711 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
5713 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
5714 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
5717 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
5719 // If the logical-not of the result is required, perform that now.
5721 Result = DAG.getNOT(dl, Result, VT);
5726 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
5727 static bool isX86LogicalCmp(SDValue Op) {
5728 unsigned Opc = Op.getNode()->getOpcode();
5729 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI)
5731 if (Op.getResNo() == 1 &&
5732 (Opc == X86ISD::ADD ||
5733 Opc == X86ISD::SUB ||
5734 Opc == X86ISD::SMUL ||
5735 Opc == X86ISD::UMUL ||
5736 Opc == X86ISD::INC ||
5737 Opc == X86ISD::DEC ||
5738 Opc == X86ISD::OR ||
5739 Opc == X86ISD::XOR ||
5740 Opc == X86ISD::AND))
5746 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) {
5747 bool addTest = true;
5748 SDValue Cond = Op.getOperand(0);
5749 DebugLoc dl = Op.getDebugLoc();
5752 if (Cond.getOpcode() == ISD::SETCC) {
5753 SDValue NewCond = LowerSETCC(Cond, DAG);
5754 if (NewCond.getNode())
5758 // If condition flag is set by a X86ISD::CMP, then use it as the condition
5759 // setting operand in place of the X86ISD::SETCC.
5760 if (Cond.getOpcode() == X86ISD::SETCC) {
5761 CC = Cond.getOperand(0);
5763 SDValue Cmp = Cond.getOperand(1);
5764 unsigned Opc = Cmp.getOpcode();
5765 EVT VT = Op.getValueType();
5767 bool IllegalFPCMov = false;
5768 if (VT.isFloatingPoint() && !VT.isVector() &&
5769 !isScalarFPTypeInSSEReg(VT)) // FPStack?
5770 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
5772 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
5773 Opc == X86ISD::BT) { // FIXME
5780 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
5781 Cond = EmitTest(Cond, X86::COND_NE, DAG);
5784 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag);
5785 SmallVector<SDValue, 4> Ops;
5786 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
5787 // condition is true.
5788 Ops.push_back(Op.getOperand(2));
5789 Ops.push_back(Op.getOperand(1));
5791 Ops.push_back(Cond);
5792 return DAG.getNode(X86ISD::CMOV, dl, VTs, &Ops[0], Ops.size());
5795 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
5796 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
5797 // from the AND / OR.
5798 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
5799 Opc = Op.getOpcode();
5800 if (Opc != ISD::OR && Opc != ISD::AND)
5802 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
5803 Op.getOperand(0).hasOneUse() &&
5804 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
5805 Op.getOperand(1).hasOneUse());
5808 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
5809 // 1 and that the SETCC node has a single use.
5810 static bool isXor1OfSetCC(SDValue Op) {
5811 if (Op.getOpcode() != ISD::XOR)
5813 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
5814 if (N1C && N1C->getAPIntValue() == 1) {
5815 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
5816 Op.getOperand(0).hasOneUse();
5821 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) {
5822 bool addTest = true;
5823 SDValue Chain = Op.getOperand(0);
5824 SDValue Cond = Op.getOperand(1);
5825 SDValue Dest = Op.getOperand(2);
5826 DebugLoc dl = Op.getDebugLoc();
5829 if (Cond.getOpcode() == ISD::SETCC) {
5830 SDValue NewCond = LowerSETCC(Cond, DAG);
5831 if (NewCond.getNode())
5835 // FIXME: LowerXALUO doesn't handle these!!
5836 else if (Cond.getOpcode() == X86ISD::ADD ||
5837 Cond.getOpcode() == X86ISD::SUB ||
5838 Cond.getOpcode() == X86ISD::SMUL ||
5839 Cond.getOpcode() == X86ISD::UMUL)
5840 Cond = LowerXALUO(Cond, DAG);
5843 // If condition flag is set by a X86ISD::CMP, then use it as the condition
5844 // setting operand in place of the X86ISD::SETCC.
5845 if (Cond.getOpcode() == X86ISD::SETCC) {
5846 CC = Cond.getOperand(0);
5848 SDValue Cmp = Cond.getOperand(1);
5849 unsigned Opc = Cmp.getOpcode();
5850 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
5851 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
5855 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
5859 // These can only come from an arithmetic instruction with overflow,
5860 // e.g. SADDO, UADDO.
5861 Cond = Cond.getNode()->getOperand(1);
5868 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
5869 SDValue Cmp = Cond.getOperand(0).getOperand(1);
5870 if (CondOpc == ISD::OR) {
5871 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
5872 // two branches instead of an explicit OR instruction with a
5874 if (Cmp == Cond.getOperand(1).getOperand(1) &&
5875 isX86LogicalCmp(Cmp)) {
5876 CC = Cond.getOperand(0).getOperand(0);
5877 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
5878 Chain, Dest, CC, Cmp);
5879 CC = Cond.getOperand(1).getOperand(0);
5883 } else { // ISD::AND
5884 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
5885 // two branches instead of an explicit AND instruction with a
5886 // separate test. However, we only do this if this block doesn't
5887 // have a fall-through edge, because this requires an explicit
5888 // jmp when the condition is false.
5889 if (Cmp == Cond.getOperand(1).getOperand(1) &&
5890 isX86LogicalCmp(Cmp) &&
5891 Op.getNode()->hasOneUse()) {
5892 X86::CondCode CCode =
5893 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
5894 CCode = X86::GetOppositeBranchCondition(CCode);
5895 CC = DAG.getConstant(CCode, MVT::i8);
5896 SDValue User = SDValue(*Op.getNode()->use_begin(), 0);
5897 // Look for an unconditional branch following this conditional branch.
5898 // We need this because we need to reverse the successors in order
5899 // to implement FCMP_OEQ.
5900 if (User.getOpcode() == ISD::BR) {
5901 SDValue FalseBB = User.getOperand(1);
5903 DAG.UpdateNodeOperands(User, User.getOperand(0), Dest);
5904 assert(NewBR == User);
5907 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
5908 Chain, Dest, CC, Cmp);
5909 X86::CondCode CCode =
5910 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
5911 CCode = X86::GetOppositeBranchCondition(CCode);
5912 CC = DAG.getConstant(CCode, MVT::i8);
5918 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
5919 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
5920 // It should be transformed during dag combiner except when the condition
5921 // is set by a arithmetics with overflow node.
5922 X86::CondCode CCode =
5923 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
5924 CCode = X86::GetOppositeBranchCondition(CCode);
5925 CC = DAG.getConstant(CCode, MVT::i8);
5926 Cond = Cond.getOperand(0).getOperand(1);
5932 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
5933 Cond = EmitTest(Cond, X86::COND_NE, DAG);
5935 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
5936 Chain, Dest, CC, Cond);
5940 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
5941 // Calls to _alloca is needed to probe the stack when allocating more than 4k
5942 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
5943 // that the guard pages used by the OS virtual memory manager are allocated in
5944 // correct sequence.
5946 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
5947 SelectionDAG &DAG) {
5948 assert(Subtarget->isTargetCygMing() &&
5949 "This should be used only on Cygwin/Mingw targets");
5950 DebugLoc dl = Op.getDebugLoc();
5953 SDValue Chain = Op.getOperand(0);
5954 SDValue Size = Op.getOperand(1);
5955 // FIXME: Ensure alignment here
5959 EVT IntPtr = getPointerTy();
5960 EVT SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32;
5962 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
5964 Chain = DAG.getCopyToReg(Chain, dl, X86::EAX, Size, Flag);
5965 Flag = Chain.getValue(1);
5967 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
5968 SDValue Ops[] = { Chain,
5969 DAG.getTargetExternalSymbol("_alloca", IntPtr),
5970 DAG.getRegister(X86::EAX, IntPtr),
5971 DAG.getRegister(X86StackPtr, SPTy),
5973 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops, 5);
5974 Flag = Chain.getValue(1);
5976 Chain = DAG.getCALLSEQ_END(Chain,
5977 DAG.getIntPtrConstant(0, true),
5978 DAG.getIntPtrConstant(0, true),
5981 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1);
5983 SDValue Ops1[2] = { Chain.getValue(0), Chain };
5984 return DAG.getMergeValues(Ops1, 2, dl);
5988 X86TargetLowering::EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl,
5990 SDValue Dst, SDValue Src,
5991 SDValue Size, unsigned Align,
5993 uint64_t DstSVOff) {
5994 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
5996 // If not DWORD aligned or size is more than the threshold, call the library.
5997 // The libc version is likely to be faster for these cases. It can use the
5998 // address value and run time information about the CPU.
5999 if ((Align & 3) != 0 ||
6001 ConstantSize->getZExtValue() >
6002 getSubtarget()->getMaxInlineSizeThreshold()) {
6003 SDValue InFlag(0, 0);
6005 // Check to see if there is a specialized entry-point for memory zeroing.
6006 ConstantSDNode *V = dyn_cast<ConstantSDNode>(Src);
6008 if (const char *bzeroEntry = V &&
6009 V->isNullValue() ? Subtarget->getBZeroEntry() : 0) {
6010 EVT IntPtr = getPointerTy();
6011 const Type *IntPtrTy = TD->getIntPtrType(*DAG.getContext());
6012 TargetLowering::ArgListTy Args;
6013 TargetLowering::ArgListEntry Entry;
6015 Entry.Ty = IntPtrTy;
6016 Args.push_back(Entry);
6018 Args.push_back(Entry);
6019 std::pair<SDValue,SDValue> CallResult =
6020 LowerCallTo(Chain, Type::getVoidTy(*DAG.getContext()),
6021 false, false, false, false,
6022 0, CallingConv::C, false, /*isReturnValueUsed=*/false,
6023 DAG.getExternalSymbol(bzeroEntry, IntPtr), Args, DAG, dl);
6024 return CallResult.second;
6027 // Otherwise have the target-independent code call memset.
6031 uint64_t SizeVal = ConstantSize->getZExtValue();
6032 SDValue InFlag(0, 0);
6035 ConstantSDNode *ValC = dyn_cast<ConstantSDNode>(Src);
6036 unsigned BytesLeft = 0;
6037 bool TwoRepStos = false;
6040 uint64_t Val = ValC->getZExtValue() & 255;
6042 // If the value is a constant, then we can potentially use larger sets.
6043 switch (Align & 3) {
6044 case 2: // WORD aligned
6047 Val = (Val << 8) | Val;
6049 case 0: // DWORD aligned
6052 Val = (Val << 8) | Val;
6053 Val = (Val << 16) | Val;
6054 if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) { // QWORD aligned
6057 Val = (Val << 32) | Val;
6060 default: // Byte aligned
6063 Count = DAG.getIntPtrConstant(SizeVal);
6067 if (AVT.bitsGT(MVT::i8)) {
6068 unsigned UBytes = AVT.getSizeInBits() / 8;
6069 Count = DAG.getIntPtrConstant(SizeVal / UBytes);
6070 BytesLeft = SizeVal % UBytes;
6073 Chain = DAG.getCopyToReg(Chain, dl, ValReg, DAG.getConstant(Val, AVT),
6075 InFlag = Chain.getValue(1);
6078 Count = DAG.getIntPtrConstant(SizeVal);
6079 Chain = DAG.getCopyToReg(Chain, dl, X86::AL, Src, InFlag);
6080 InFlag = Chain.getValue(1);
6083 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RCX :
6086 InFlag = Chain.getValue(1);
6087 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RDI :
6090 InFlag = Chain.getValue(1);
6092 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6093 SmallVector<SDValue, 8> Ops;
6094 Ops.push_back(Chain);
6095 Ops.push_back(DAG.getValueType(AVT));
6096 Ops.push_back(InFlag);
6097 Chain = DAG.getNode(X86ISD::REP_STOS, dl, Tys, &Ops[0], Ops.size());
6100 InFlag = Chain.getValue(1);
6102 EVT CVT = Count.getValueType();
6103 SDValue Left = DAG.getNode(ISD::AND, dl, CVT, Count,
6104 DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT));
6105 Chain = DAG.getCopyToReg(Chain, dl, (CVT == MVT::i64) ? X86::RCX :
6108 InFlag = Chain.getValue(1);
6109 Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6111 Ops.push_back(Chain);
6112 Ops.push_back(DAG.getValueType(MVT::i8));
6113 Ops.push_back(InFlag);
6114 Chain = DAG.getNode(X86ISD::REP_STOS, dl, Tys, &Ops[0], Ops.size());
6115 } else if (BytesLeft) {
6116 // Handle the last 1 - 7 bytes.
6117 unsigned Offset = SizeVal - BytesLeft;
6118 EVT AddrVT = Dst.getValueType();
6119 EVT SizeVT = Size.getValueType();
6121 Chain = DAG.getMemset(Chain, dl,
6122 DAG.getNode(ISD::ADD, dl, AddrVT, Dst,
6123 DAG.getConstant(Offset, AddrVT)),
6125 DAG.getConstant(BytesLeft, SizeVT),
6126 Align, DstSV, DstSVOff + Offset);
6129 // TODO: Use a Tokenfactor, as in memcpy, instead of a single chain.
6134 X86TargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
6135 SDValue Chain, SDValue Dst, SDValue Src,
6136 SDValue Size, unsigned Align,
6138 const Value *DstSV, uint64_t DstSVOff,
6139 const Value *SrcSV, uint64_t SrcSVOff) {
6140 // This requires the copy size to be a constant, preferrably
6141 // within a subtarget-specific limit.
6142 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
6145 uint64_t SizeVal = ConstantSize->getZExtValue();
6146 if (!AlwaysInline && SizeVal > getSubtarget()->getMaxInlineSizeThreshold())
6149 /// If not DWORD aligned, call the library.
6150 if ((Align & 3) != 0)
6155 if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) // QWORD aligned
6158 unsigned UBytes = AVT.getSizeInBits() / 8;
6159 unsigned CountVal = SizeVal / UBytes;
6160 SDValue Count = DAG.getIntPtrConstant(CountVal);
6161 unsigned BytesLeft = SizeVal % UBytes;
6163 SDValue InFlag(0, 0);
6164 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RCX :
6167 InFlag = Chain.getValue(1);
6168 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RDI :
6171 InFlag = Chain.getValue(1);
6172 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RSI :
6175 InFlag = Chain.getValue(1);
6177 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6178 SmallVector<SDValue, 8> Ops;
6179 Ops.push_back(Chain);
6180 Ops.push_back(DAG.getValueType(AVT));
6181 Ops.push_back(InFlag);
6182 SDValue RepMovs = DAG.getNode(X86ISD::REP_MOVS, dl, Tys, &Ops[0], Ops.size());
6184 SmallVector<SDValue, 4> Results;
6185 Results.push_back(RepMovs);
6187 // Handle the last 1 - 7 bytes.
6188 unsigned Offset = SizeVal - BytesLeft;
6189 EVT DstVT = Dst.getValueType();
6190 EVT SrcVT = Src.getValueType();
6191 EVT SizeVT = Size.getValueType();
6192 Results.push_back(DAG.getMemcpy(Chain, dl,
6193 DAG.getNode(ISD::ADD, dl, DstVT, Dst,
6194 DAG.getConstant(Offset, DstVT)),
6195 DAG.getNode(ISD::ADD, dl, SrcVT, Src,
6196 DAG.getConstant(Offset, SrcVT)),
6197 DAG.getConstant(BytesLeft, SizeVT),
6198 Align, AlwaysInline,
6199 DstSV, DstSVOff + Offset,
6200 SrcSV, SrcSVOff + Offset));
6203 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
6204 &Results[0], Results.size());
6207 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) {
6208 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
6209 DebugLoc dl = Op.getDebugLoc();
6211 if (!Subtarget->is64Bit()) {
6212 // vastart just stores the address of the VarArgsFrameIndex slot into the
6213 // memory location argument.
6214 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
6215 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0);
6219 // gp_offset (0 - 6 * 8)
6220 // fp_offset (48 - 48 + 8 * 16)
6221 // overflow_arg_area (point to parameters coming in memory).
6223 SmallVector<SDValue, 8> MemOps;
6224 SDValue FIN = Op.getOperand(1);
6226 SDValue Store = DAG.getStore(Op.getOperand(0), dl,
6227 DAG.getConstant(VarArgsGPOffset, MVT::i32),
6229 MemOps.push_back(Store);
6232 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6233 FIN, DAG.getIntPtrConstant(4));
6234 Store = DAG.getStore(Op.getOperand(0), dl,
6235 DAG.getConstant(VarArgsFPOffset, MVT::i32),
6237 MemOps.push_back(Store);
6239 // Store ptr to overflow_arg_area
6240 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6241 FIN, DAG.getIntPtrConstant(4));
6242 SDValue OVFIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
6243 Store = DAG.getStore(Op.getOperand(0), dl, OVFIN, FIN, SV, 0);
6244 MemOps.push_back(Store);
6246 // Store ptr to reg_save_area.
6247 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6248 FIN, DAG.getIntPtrConstant(8));
6249 SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
6250 Store = DAG.getStore(Op.getOperand(0), dl, RSFIN, FIN, SV, 0);
6251 MemOps.push_back(Store);
6252 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
6253 &MemOps[0], MemOps.size());
6256 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) {
6257 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
6258 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_arg!");
6259 SDValue Chain = Op.getOperand(0);
6260 SDValue SrcPtr = Op.getOperand(1);
6261 SDValue SrcSV = Op.getOperand(2);
6263 llvm_report_error("VAArgInst is not yet implemented for x86-64!");
6267 SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) {
6268 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
6269 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
6270 SDValue Chain = Op.getOperand(0);
6271 SDValue DstPtr = Op.getOperand(1);
6272 SDValue SrcPtr = Op.getOperand(2);
6273 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
6274 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
6275 DebugLoc dl = Op.getDebugLoc();
6277 return DAG.getMemcpy(Chain, dl, DstPtr, SrcPtr,
6278 DAG.getIntPtrConstant(24), 8, false,
6279 DstSV, 0, SrcSV, 0);
6283 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
6284 DebugLoc dl = Op.getDebugLoc();
6285 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
6287 default: return SDValue(); // Don't custom lower most intrinsics.
6288 // Comparison intrinsics.
6289 case Intrinsic::x86_sse_comieq_ss:
6290 case Intrinsic::x86_sse_comilt_ss:
6291 case Intrinsic::x86_sse_comile_ss:
6292 case Intrinsic::x86_sse_comigt_ss:
6293 case Intrinsic::x86_sse_comige_ss:
6294 case Intrinsic::x86_sse_comineq_ss:
6295 case Intrinsic::x86_sse_ucomieq_ss:
6296 case Intrinsic::x86_sse_ucomilt_ss:
6297 case Intrinsic::x86_sse_ucomile_ss:
6298 case Intrinsic::x86_sse_ucomigt_ss:
6299 case Intrinsic::x86_sse_ucomige_ss:
6300 case Intrinsic::x86_sse_ucomineq_ss:
6301 case Intrinsic::x86_sse2_comieq_sd:
6302 case Intrinsic::x86_sse2_comilt_sd:
6303 case Intrinsic::x86_sse2_comile_sd:
6304 case Intrinsic::x86_sse2_comigt_sd:
6305 case Intrinsic::x86_sse2_comige_sd:
6306 case Intrinsic::x86_sse2_comineq_sd:
6307 case Intrinsic::x86_sse2_ucomieq_sd:
6308 case Intrinsic::x86_sse2_ucomilt_sd:
6309 case Intrinsic::x86_sse2_ucomile_sd:
6310 case Intrinsic::x86_sse2_ucomigt_sd:
6311 case Intrinsic::x86_sse2_ucomige_sd:
6312 case Intrinsic::x86_sse2_ucomineq_sd: {
6314 ISD::CondCode CC = ISD::SETCC_INVALID;
6317 case Intrinsic::x86_sse_comieq_ss:
6318 case Intrinsic::x86_sse2_comieq_sd:
6322 case Intrinsic::x86_sse_comilt_ss:
6323 case Intrinsic::x86_sse2_comilt_sd:
6327 case Intrinsic::x86_sse_comile_ss:
6328 case Intrinsic::x86_sse2_comile_sd:
6332 case Intrinsic::x86_sse_comigt_ss:
6333 case Intrinsic::x86_sse2_comigt_sd:
6337 case Intrinsic::x86_sse_comige_ss:
6338 case Intrinsic::x86_sse2_comige_sd:
6342 case Intrinsic::x86_sse_comineq_ss:
6343 case Intrinsic::x86_sse2_comineq_sd:
6347 case Intrinsic::x86_sse_ucomieq_ss:
6348 case Intrinsic::x86_sse2_ucomieq_sd:
6349 Opc = X86ISD::UCOMI;
6352 case Intrinsic::x86_sse_ucomilt_ss:
6353 case Intrinsic::x86_sse2_ucomilt_sd:
6354 Opc = X86ISD::UCOMI;
6357 case Intrinsic::x86_sse_ucomile_ss:
6358 case Intrinsic::x86_sse2_ucomile_sd:
6359 Opc = X86ISD::UCOMI;
6362 case Intrinsic::x86_sse_ucomigt_ss:
6363 case Intrinsic::x86_sse2_ucomigt_sd:
6364 Opc = X86ISD::UCOMI;
6367 case Intrinsic::x86_sse_ucomige_ss:
6368 case Intrinsic::x86_sse2_ucomige_sd:
6369 Opc = X86ISD::UCOMI;
6372 case Intrinsic::x86_sse_ucomineq_ss:
6373 case Intrinsic::x86_sse2_ucomineq_sd:
6374 Opc = X86ISD::UCOMI;
6379 SDValue LHS = Op.getOperand(1);
6380 SDValue RHS = Op.getOperand(2);
6381 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
6382 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
6383 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
6384 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
6385 DAG.getConstant(X86CC, MVT::i8), Cond);
6386 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
6388 // ptest intrinsics. The intrinsic these come from are designed to return
6389 // an integer value, not just an instruction so lower it to the ptest
6390 // pattern and a setcc for the result.
6391 case Intrinsic::x86_sse41_ptestz:
6392 case Intrinsic::x86_sse41_ptestc:
6393 case Intrinsic::x86_sse41_ptestnzc:{
6396 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
6397 case Intrinsic::x86_sse41_ptestz:
6399 X86CC = X86::COND_E;
6401 case Intrinsic::x86_sse41_ptestc:
6403 X86CC = X86::COND_B;
6405 case Intrinsic::x86_sse41_ptestnzc:
6407 X86CC = X86::COND_A;
6411 SDValue LHS = Op.getOperand(1);
6412 SDValue RHS = Op.getOperand(2);
6413 SDValue Test = DAG.getNode(X86ISD::PTEST, dl, MVT::i32, LHS, RHS);
6414 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
6415 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
6416 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
6419 // Fix vector shift instructions where the last operand is a non-immediate
6421 case Intrinsic::x86_sse2_pslli_w:
6422 case Intrinsic::x86_sse2_pslli_d:
6423 case Intrinsic::x86_sse2_pslli_q:
6424 case Intrinsic::x86_sse2_psrli_w:
6425 case Intrinsic::x86_sse2_psrli_d:
6426 case Intrinsic::x86_sse2_psrli_q:
6427 case Intrinsic::x86_sse2_psrai_w:
6428 case Intrinsic::x86_sse2_psrai_d:
6429 case Intrinsic::x86_mmx_pslli_w:
6430 case Intrinsic::x86_mmx_pslli_d:
6431 case Intrinsic::x86_mmx_pslli_q:
6432 case Intrinsic::x86_mmx_psrli_w:
6433 case Intrinsic::x86_mmx_psrli_d:
6434 case Intrinsic::x86_mmx_psrli_q:
6435 case Intrinsic::x86_mmx_psrai_w:
6436 case Intrinsic::x86_mmx_psrai_d: {
6437 SDValue ShAmt = Op.getOperand(2);
6438 if (isa<ConstantSDNode>(ShAmt))
6441 unsigned NewIntNo = 0;
6442 EVT ShAmtVT = MVT::v4i32;
6444 case Intrinsic::x86_sse2_pslli_w:
6445 NewIntNo = Intrinsic::x86_sse2_psll_w;
6447 case Intrinsic::x86_sse2_pslli_d:
6448 NewIntNo = Intrinsic::x86_sse2_psll_d;
6450 case Intrinsic::x86_sse2_pslli_q:
6451 NewIntNo = Intrinsic::x86_sse2_psll_q;
6453 case Intrinsic::x86_sse2_psrli_w:
6454 NewIntNo = Intrinsic::x86_sse2_psrl_w;
6456 case Intrinsic::x86_sse2_psrli_d:
6457 NewIntNo = Intrinsic::x86_sse2_psrl_d;
6459 case Intrinsic::x86_sse2_psrli_q:
6460 NewIntNo = Intrinsic::x86_sse2_psrl_q;
6462 case Intrinsic::x86_sse2_psrai_w:
6463 NewIntNo = Intrinsic::x86_sse2_psra_w;
6465 case Intrinsic::x86_sse2_psrai_d:
6466 NewIntNo = Intrinsic::x86_sse2_psra_d;
6469 ShAmtVT = MVT::v2i32;
6471 case Intrinsic::x86_mmx_pslli_w:
6472 NewIntNo = Intrinsic::x86_mmx_psll_w;
6474 case Intrinsic::x86_mmx_pslli_d:
6475 NewIntNo = Intrinsic::x86_mmx_psll_d;
6477 case Intrinsic::x86_mmx_pslli_q:
6478 NewIntNo = Intrinsic::x86_mmx_psll_q;
6480 case Intrinsic::x86_mmx_psrli_w:
6481 NewIntNo = Intrinsic::x86_mmx_psrl_w;
6483 case Intrinsic::x86_mmx_psrli_d:
6484 NewIntNo = Intrinsic::x86_mmx_psrl_d;
6486 case Intrinsic::x86_mmx_psrli_q:
6487 NewIntNo = Intrinsic::x86_mmx_psrl_q;
6489 case Intrinsic::x86_mmx_psrai_w:
6490 NewIntNo = Intrinsic::x86_mmx_psra_w;
6492 case Intrinsic::x86_mmx_psrai_d:
6493 NewIntNo = Intrinsic::x86_mmx_psra_d;
6495 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
6501 // The vector shift intrinsics with scalars uses 32b shift amounts but
6502 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
6506 ShOps[1] = DAG.getConstant(0, MVT::i32);
6507 if (ShAmtVT == MVT::v4i32) {
6508 ShOps[2] = DAG.getUNDEF(MVT::i32);
6509 ShOps[3] = DAG.getUNDEF(MVT::i32);
6510 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 4);
6512 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2);
6515 EVT VT = Op.getValueType();
6516 ShAmt = DAG.getNode(ISD::BIT_CONVERT, dl, VT, ShAmt);
6517 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6518 DAG.getConstant(NewIntNo, MVT::i32),
6519 Op.getOperand(1), ShAmt);
6524 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) {
6525 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
6526 DebugLoc dl = Op.getDebugLoc();
6529 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
6531 DAG.getConstant(TD->getPointerSize(),
6532 Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
6533 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
6534 DAG.getNode(ISD::ADD, dl, getPointerTy(),
6539 // Just load the return address.
6540 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
6541 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
6542 RetAddrFI, NULL, 0);
6545 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) {
6546 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
6547 MFI->setFrameAddressIsTaken(true);
6548 EVT VT = Op.getValueType();
6549 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
6550 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
6551 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
6552 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
6554 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, NULL, 0);
6558 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
6559 SelectionDAG &DAG) {
6560 return DAG.getIntPtrConstant(2*TD->getPointerSize());
6563 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG)
6565 MachineFunction &MF = DAG.getMachineFunction();
6566 SDValue Chain = Op.getOperand(0);
6567 SDValue Offset = Op.getOperand(1);
6568 SDValue Handler = Op.getOperand(2);
6569 DebugLoc dl = Op.getDebugLoc();
6571 SDValue Frame = DAG.getRegister(Subtarget->is64Bit() ? X86::RBP : X86::EBP,
6573 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
6575 SDValue StoreAddr = DAG.getNode(ISD::SUB, dl, getPointerTy(), Frame,
6576 DAG.getIntPtrConstant(-TD->getPointerSize()));
6577 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
6578 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, NULL, 0);
6579 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
6580 MF.getRegInfo().addLiveOut(StoreAddrReg);
6582 return DAG.getNode(X86ISD::EH_RETURN, dl,
6584 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
6587 SDValue X86TargetLowering::LowerTRAMPOLINE(SDValue Op,
6588 SelectionDAG &DAG) {
6589 SDValue Root = Op.getOperand(0);
6590 SDValue Trmp = Op.getOperand(1); // trampoline
6591 SDValue FPtr = Op.getOperand(2); // nested function
6592 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
6593 DebugLoc dl = Op.getDebugLoc();
6595 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
6597 const X86InstrInfo *TII =
6598 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
6600 if (Subtarget->is64Bit()) {
6601 SDValue OutChains[6];
6603 // Large code-model.
6605 const unsigned char JMP64r = TII->getBaseOpcodeFor(X86::JMP64r);
6606 const unsigned char MOV64ri = TII->getBaseOpcodeFor(X86::MOV64ri);
6608 const unsigned char N86R10 = RegInfo->getX86RegNum(X86::R10);
6609 const unsigned char N86R11 = RegInfo->getX86RegNum(X86::R11);
6611 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
6613 // Load the pointer to the nested function into R11.
6614 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
6615 SDValue Addr = Trmp;
6616 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
6619 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
6620 DAG.getConstant(2, MVT::i64));
6621 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr, TrmpAddr, 2, false, 2);
6623 // Load the 'nest' parameter value into R10.
6624 // R10 is specified in X86CallingConv.td
6625 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
6626 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
6627 DAG.getConstant(10, MVT::i64));
6628 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
6629 Addr, TrmpAddr, 10);
6631 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
6632 DAG.getConstant(12, MVT::i64));
6633 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 12, false, 2);
6635 // Jump to the nested function.
6636 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
6637 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
6638 DAG.getConstant(20, MVT::i64));
6639 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
6640 Addr, TrmpAddr, 20);
6642 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
6643 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
6644 DAG.getConstant(22, MVT::i64));
6645 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
6649 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6) };
6650 return DAG.getMergeValues(Ops, 2, dl);
6652 const Function *Func =
6653 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
6654 CallingConv::ID CC = Func->getCallingConv();
6659 llvm_unreachable("Unsupported calling convention");
6660 case CallingConv::C:
6661 case CallingConv::X86_StdCall: {
6662 // Pass 'nest' parameter in ECX.
6663 // Must be kept in sync with X86CallingConv.td
6666 // Check that ECX wasn't needed by an 'inreg' parameter.
6667 const FunctionType *FTy = Func->getFunctionType();
6668 const AttrListPtr &Attrs = Func->getAttributes();
6670 if (!Attrs.isEmpty() && !Func->isVarArg()) {
6671 unsigned InRegCount = 0;
6674 for (FunctionType::param_iterator I = FTy->param_begin(),
6675 E = FTy->param_end(); I != E; ++I, ++Idx)
6676 if (Attrs.paramHasAttr(Idx, Attribute::InReg))
6677 // FIXME: should only count parameters that are lowered to integers.
6678 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
6680 if (InRegCount > 2) {
6681 llvm_report_error("Nest register in use - reduce number of inreg parameters!");
6686 case CallingConv::X86_FastCall:
6687 case CallingConv::Fast:
6688 // Pass 'nest' parameter in EAX.
6689 // Must be kept in sync with X86CallingConv.td
6694 SDValue OutChains[4];
6697 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
6698 DAG.getConstant(10, MVT::i32));
6699 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
6701 const unsigned char MOV32ri = TII->getBaseOpcodeFor(X86::MOV32ri);
6702 const unsigned char N86Reg = RegInfo->getX86RegNum(NestReg);
6703 OutChains[0] = DAG.getStore(Root, dl,
6704 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
6707 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
6708 DAG.getConstant(1, MVT::i32));
6709 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 1, false, 1);
6711 const unsigned char JMP = TII->getBaseOpcodeFor(X86::JMP);
6712 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
6713 DAG.getConstant(5, MVT::i32));
6714 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
6715 TrmpAddr, 5, false, 1);
6717 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
6718 DAG.getConstant(6, MVT::i32));
6719 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr, TrmpAddr, 6, false, 1);
6722 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4) };
6723 return DAG.getMergeValues(Ops, 2, dl);
6727 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) {
6729 The rounding mode is in bits 11:10 of FPSR, and has the following
6736 FLT_ROUNDS, on the other hand, expects the following:
6743 To perform the conversion, we do:
6744 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
6747 MachineFunction &MF = DAG.getMachineFunction();
6748 const TargetMachine &TM = MF.getTarget();
6749 const TargetFrameInfo &TFI = *TM.getFrameInfo();
6750 unsigned StackAlignment = TFI.getStackAlignment();
6751 EVT VT = Op.getValueType();
6752 DebugLoc dl = Op.getDebugLoc();
6754 // Save FP Control Word to stack slot
6755 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment);
6756 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
6758 SDValue Chain = DAG.getNode(X86ISD::FNSTCW16m, dl, MVT::Other,
6759 DAG.getEntryNode(), StackSlot);
6761 // Load FP Control Word from stack slot
6762 SDValue CWD = DAG.getLoad(MVT::i16, dl, Chain, StackSlot, NULL, 0);
6764 // Transform as necessary
6766 DAG.getNode(ISD::SRL, dl, MVT::i16,
6767 DAG.getNode(ISD::AND, dl, MVT::i16,
6768 CWD, DAG.getConstant(0x800, MVT::i16)),
6769 DAG.getConstant(11, MVT::i8));
6771 DAG.getNode(ISD::SRL, dl, MVT::i16,
6772 DAG.getNode(ISD::AND, dl, MVT::i16,
6773 CWD, DAG.getConstant(0x400, MVT::i16)),
6774 DAG.getConstant(9, MVT::i8));
6777 DAG.getNode(ISD::AND, dl, MVT::i16,
6778 DAG.getNode(ISD::ADD, dl, MVT::i16,
6779 DAG.getNode(ISD::OR, dl, MVT::i16, CWD1, CWD2),
6780 DAG.getConstant(1, MVT::i16)),
6781 DAG.getConstant(3, MVT::i16));
6784 return DAG.getNode((VT.getSizeInBits() < 16 ?
6785 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
6788 SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
6789 EVT VT = Op.getValueType();
6791 unsigned NumBits = VT.getSizeInBits();
6792 DebugLoc dl = Op.getDebugLoc();
6794 Op = Op.getOperand(0);
6795 if (VT == MVT::i8) {
6796 // Zero extend to i32 since there is not an i8 bsr.
6798 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
6801 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
6802 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
6803 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
6805 // If src is zero (i.e. bsr sets ZF), returns NumBits.
6806 SmallVector<SDValue, 4> Ops;
6808 Ops.push_back(DAG.getConstant(NumBits+NumBits-1, OpVT));
6809 Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8));
6810 Ops.push_back(Op.getValue(1));
6811 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, &Ops[0], 4);
6813 // Finally xor with NumBits-1.
6814 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
6817 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
6821 SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
6822 EVT VT = Op.getValueType();
6824 unsigned NumBits = VT.getSizeInBits();
6825 DebugLoc dl = Op.getDebugLoc();
6827 Op = Op.getOperand(0);
6828 if (VT == MVT::i8) {
6830 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
6833 // Issue a bsf (scan bits forward) which also sets EFLAGS.
6834 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
6835 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
6837 // If src is zero (i.e. bsf sets ZF), returns NumBits.
6838 SmallVector<SDValue, 4> Ops;
6840 Ops.push_back(DAG.getConstant(NumBits, OpVT));
6841 Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8));
6842 Ops.push_back(Op.getValue(1));
6843 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, &Ops[0], 4);
6846 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
6850 SDValue X86TargetLowering::LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG) {
6851 EVT VT = Op.getValueType();
6852 assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply");
6853 DebugLoc dl = Op.getDebugLoc();
6855 // ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32);
6856 // ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32);
6857 // ulong2 AloBlo = __builtin_ia32_pmuludq128( a, b );
6858 // ulong2 AloBhi = __builtin_ia32_pmuludq128( a, Bhi );
6859 // ulong2 AhiBlo = __builtin_ia32_pmuludq128( Ahi, b );
6861 // AloBhi = __builtin_ia32_psllqi128( AloBhi, 32 );
6862 // AhiBlo = __builtin_ia32_psllqi128( AhiBlo, 32 );
6863 // return AloBlo + AloBhi + AhiBlo;
6865 SDValue A = Op.getOperand(0);
6866 SDValue B = Op.getOperand(1);
6868 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6869 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
6870 A, DAG.getConstant(32, MVT::i32));
6871 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6872 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
6873 B, DAG.getConstant(32, MVT::i32));
6874 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6875 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
6877 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6878 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
6880 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6881 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
6883 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6884 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
6885 AloBhi, DAG.getConstant(32, MVT::i32));
6886 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6887 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
6888 AhiBlo, DAG.getConstant(32, MVT::i32));
6889 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
6890 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
6895 SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) {
6896 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
6897 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
6898 // looks for this combo and may remove the "setcc" instruction if the "setcc"
6899 // has only one use.
6900 SDNode *N = Op.getNode();
6901 SDValue LHS = N->getOperand(0);
6902 SDValue RHS = N->getOperand(1);
6903 unsigned BaseOp = 0;
6905 DebugLoc dl = Op.getDebugLoc();
6907 switch (Op.getOpcode()) {
6908 default: llvm_unreachable("Unknown ovf instruction!");
6910 // A subtract of one will be selected as a INC. Note that INC doesn't
6911 // set CF, so we can't do this for UADDO.
6912 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
6913 if (C->getAPIntValue() == 1) {
6914 BaseOp = X86ISD::INC;
6918 BaseOp = X86ISD::ADD;
6922 BaseOp = X86ISD::ADD;
6926 // A subtract of one will be selected as a DEC. Note that DEC doesn't
6927 // set CF, so we can't do this for USUBO.
6928 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
6929 if (C->getAPIntValue() == 1) {
6930 BaseOp = X86ISD::DEC;
6934 BaseOp = X86ISD::SUB;
6938 BaseOp = X86ISD::SUB;
6942 BaseOp = X86ISD::SMUL;
6946 BaseOp = X86ISD::UMUL;
6951 // Also sets EFLAGS.
6952 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
6953 SDValue Sum = DAG.getNode(BaseOp, dl, VTs, LHS, RHS);
6956 DAG.getNode(X86ISD::SETCC, dl, N->getValueType(1),
6957 DAG.getConstant(Cond, MVT::i32), SDValue(Sum.getNode(), 1));
6959 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SetCC);
6963 SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) {
6964 EVT T = Op.getValueType();
6965 DebugLoc dl = Op.getDebugLoc();
6968 switch(T.getSimpleVT().SimpleTy) {
6970 assert(false && "Invalid value type!");
6971 case MVT::i8: Reg = X86::AL; size = 1; break;
6972 case MVT::i16: Reg = X86::AX; size = 2; break;
6973 case MVT::i32: Reg = X86::EAX; size = 4; break;
6975 assert(Subtarget->is64Bit() && "Node not type legal!");
6976 Reg = X86::RAX; size = 8;
6979 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), dl, Reg,
6980 Op.getOperand(2), SDValue());
6981 SDValue Ops[] = { cpIn.getValue(0),
6984 DAG.getTargetConstant(size, MVT::i8),
6986 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6987 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG_DAG, dl, Tys, Ops, 5);
6989 DAG.getCopyFromReg(Result.getValue(0), dl, Reg, T, Result.getValue(1));
6993 SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
6994 SelectionDAG &DAG) {
6995 assert(Subtarget->is64Bit() && "Result not type legalized?");
6996 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6997 SDValue TheChain = Op.getOperand(0);
6998 DebugLoc dl = Op.getDebugLoc();
6999 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
7000 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
7001 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
7003 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
7004 DAG.getConstant(32, MVT::i8));
7006 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
7009 return DAG.getMergeValues(Ops, 2, dl);
7012 SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
7013 SDNode *Node = Op.getNode();
7014 DebugLoc dl = Node->getDebugLoc();
7015 EVT T = Node->getValueType(0);
7016 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
7017 DAG.getConstant(0, T), Node->getOperand(2));
7018 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
7019 cast<AtomicSDNode>(Node)->getMemoryVT(),
7020 Node->getOperand(0),
7021 Node->getOperand(1), negOp,
7022 cast<AtomicSDNode>(Node)->getSrcValue(),
7023 cast<AtomicSDNode>(Node)->getAlignment());
7026 /// LowerOperation - Provide custom lowering hooks for some operations.
7028 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
7029 switch (Op.getOpcode()) {
7030 default: llvm_unreachable("Should not custom lower this!");
7031 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG);
7032 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
7033 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
7034 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
7035 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
7036 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
7037 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
7038 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
7039 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
7040 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
7041 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
7042 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
7043 case ISD::SHL_PARTS:
7044 case ISD::SRA_PARTS:
7045 case ISD::SRL_PARTS: return LowerShift(Op, DAG);
7046 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
7047 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
7048 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
7049 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
7050 case ISD::FABS: return LowerFABS(Op, DAG);
7051 case ISD::FNEG: return LowerFNEG(Op, DAG);
7052 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
7053 case ISD::SETCC: return LowerSETCC(Op, DAG);
7054 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
7055 case ISD::SELECT: return LowerSELECT(Op, DAG);
7056 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
7057 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
7058 case ISD::VASTART: return LowerVASTART(Op, DAG);
7059 case ISD::VAARG: return LowerVAARG(Op, DAG);
7060 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
7061 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
7062 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
7063 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
7064 case ISD::FRAME_TO_ARGS_OFFSET:
7065 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
7066 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
7067 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
7068 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG);
7069 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
7070 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
7071 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
7072 case ISD::MUL: return LowerMUL_V2I64(Op, DAG);
7078 case ISD::UMULO: return LowerXALUO(Op, DAG);
7079 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
7083 void X86TargetLowering::
7084 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
7085 SelectionDAG &DAG, unsigned NewOp) {
7086 EVT T = Node->getValueType(0);
7087 DebugLoc dl = Node->getDebugLoc();
7088 assert (T == MVT::i64 && "Only know how to expand i64 atomics");
7090 SDValue Chain = Node->getOperand(0);
7091 SDValue In1 = Node->getOperand(1);
7092 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
7093 Node->getOperand(2), DAG.getIntPtrConstant(0));
7094 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
7095 Node->getOperand(2), DAG.getIntPtrConstant(1));
7096 SDValue Ops[] = { Chain, In1, In2L, In2H };
7097 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
7099 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64,
7100 cast<MemSDNode>(Node)->getMemOperand());
7101 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
7102 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
7103 Results.push_back(Result.getValue(2));
7106 /// ReplaceNodeResults - Replace a node with an illegal result type
7107 /// with a new node built out of custom code.
7108 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
7109 SmallVectorImpl<SDValue>&Results,
7110 SelectionDAG &DAG) {
7111 DebugLoc dl = N->getDebugLoc();
7112 switch (N->getOpcode()) {
7114 assert(false && "Do not know how to custom type legalize this operation!");
7116 case ISD::FP_TO_SINT: {
7117 std::pair<SDValue,SDValue> Vals =
7118 FP_TO_INTHelper(SDValue(N, 0), DAG, true);
7119 SDValue FIST = Vals.first, StackSlot = Vals.second;
7120 if (FIST.getNode() != 0) {
7121 EVT VT = N->getValueType(0);
7122 // Return a load from the stack slot.
7123 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot, NULL, 0));
7127 case ISD::READCYCLECOUNTER: {
7128 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
7129 SDValue TheChain = N->getOperand(0);
7130 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
7131 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
7133 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
7135 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
7136 SDValue Ops[] = { eax, edx };
7137 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
7138 Results.push_back(edx.getValue(1));
7141 case ISD::ATOMIC_CMP_SWAP: {
7142 EVT T = N->getValueType(0);
7143 assert (T == MVT::i64 && "Only know how to expand i64 Cmp and Swap");
7144 SDValue cpInL, cpInH;
7145 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
7146 DAG.getConstant(0, MVT::i32));
7147 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
7148 DAG.getConstant(1, MVT::i32));
7149 cpInL = DAG.getCopyToReg(N->getOperand(0), dl, X86::EAX, cpInL, SDValue());
7150 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl, X86::EDX, cpInH,
7152 SDValue swapInL, swapInH;
7153 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
7154 DAG.getConstant(0, MVT::i32));
7155 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
7156 DAG.getConstant(1, MVT::i32));
7157 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl, X86::EBX, swapInL,
7159 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl, X86::ECX, swapInH,
7160 swapInL.getValue(1));
7161 SDValue Ops[] = { swapInH.getValue(0),
7163 swapInH.getValue(1) };
7164 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
7165 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG8_DAG, dl, Tys, Ops, 3);
7166 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl, X86::EAX,
7167 MVT::i32, Result.getValue(1));
7168 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl, X86::EDX,
7169 MVT::i32, cpOutL.getValue(2));
7170 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
7171 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
7172 Results.push_back(cpOutH.getValue(1));
7175 case ISD::ATOMIC_LOAD_ADD:
7176 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG);
7178 case ISD::ATOMIC_LOAD_AND:
7179 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG);
7181 case ISD::ATOMIC_LOAD_NAND:
7182 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG);
7184 case ISD::ATOMIC_LOAD_OR:
7185 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG);
7187 case ISD::ATOMIC_LOAD_SUB:
7188 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG);
7190 case ISD::ATOMIC_LOAD_XOR:
7191 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG);
7193 case ISD::ATOMIC_SWAP:
7194 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG);
7199 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
7201 default: return NULL;
7202 case X86ISD::BSF: return "X86ISD::BSF";
7203 case X86ISD::BSR: return "X86ISD::BSR";
7204 case X86ISD::SHLD: return "X86ISD::SHLD";
7205 case X86ISD::SHRD: return "X86ISD::SHRD";
7206 case X86ISD::FAND: return "X86ISD::FAND";
7207 case X86ISD::FOR: return "X86ISD::FOR";
7208 case X86ISD::FXOR: return "X86ISD::FXOR";
7209 case X86ISD::FSRL: return "X86ISD::FSRL";
7210 case X86ISD::FILD: return "X86ISD::FILD";
7211 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
7212 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
7213 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
7214 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
7215 case X86ISD::FLD: return "X86ISD::FLD";
7216 case X86ISD::FST: return "X86ISD::FST";
7217 case X86ISD::CALL: return "X86ISD::CALL";
7218 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
7219 case X86ISD::BT: return "X86ISD::BT";
7220 case X86ISD::CMP: return "X86ISD::CMP";
7221 case X86ISD::COMI: return "X86ISD::COMI";
7222 case X86ISD::UCOMI: return "X86ISD::UCOMI";
7223 case X86ISD::SETCC: return "X86ISD::SETCC";
7224 case X86ISD::CMOV: return "X86ISD::CMOV";
7225 case X86ISD::BRCOND: return "X86ISD::BRCOND";
7226 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
7227 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
7228 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
7229 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
7230 case X86ISD::Wrapper: return "X86ISD::Wrapper";
7231 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
7232 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
7233 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
7234 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
7235 case X86ISD::PINSRB: return "X86ISD::PINSRB";
7236 case X86ISD::PINSRW: return "X86ISD::PINSRW";
7237 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
7238 case X86ISD::FMAX: return "X86ISD::FMAX";
7239 case X86ISD::FMIN: return "X86ISD::FMIN";
7240 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
7241 case X86ISD::FRCP: return "X86ISD::FRCP";
7242 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
7243 case X86ISD::SegmentBaseAddress: return "X86ISD::SegmentBaseAddress";
7244 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
7245 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
7246 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
7247 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
7248 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
7249 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
7250 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
7251 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
7252 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
7253 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
7254 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
7255 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
7256 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
7257 case X86ISD::VSHL: return "X86ISD::VSHL";
7258 case X86ISD::VSRL: return "X86ISD::VSRL";
7259 case X86ISD::CMPPD: return "X86ISD::CMPPD";
7260 case X86ISD::CMPPS: return "X86ISD::CMPPS";
7261 case X86ISD::PCMPEQB: return "X86ISD::PCMPEQB";
7262 case X86ISD::PCMPEQW: return "X86ISD::PCMPEQW";
7263 case X86ISD::PCMPEQD: return "X86ISD::PCMPEQD";
7264 case X86ISD::PCMPEQQ: return "X86ISD::PCMPEQQ";
7265 case X86ISD::PCMPGTB: return "X86ISD::PCMPGTB";
7266 case X86ISD::PCMPGTW: return "X86ISD::PCMPGTW";
7267 case X86ISD::PCMPGTD: return "X86ISD::PCMPGTD";
7268 case X86ISD::PCMPGTQ: return "X86ISD::PCMPGTQ";
7269 case X86ISD::ADD: return "X86ISD::ADD";
7270 case X86ISD::SUB: return "X86ISD::SUB";
7271 case X86ISD::SMUL: return "X86ISD::SMUL";
7272 case X86ISD::UMUL: return "X86ISD::UMUL";
7273 case X86ISD::INC: return "X86ISD::INC";
7274 case X86ISD::DEC: return "X86ISD::DEC";
7275 case X86ISD::OR: return "X86ISD::OR";
7276 case X86ISD::XOR: return "X86ISD::XOR";
7277 case X86ISD::AND: return "X86ISD::AND";
7278 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
7279 case X86ISD::PTEST: return "X86ISD::PTEST";
7280 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
7284 // isLegalAddressingMode - Return true if the addressing mode represented
7285 // by AM is legal for this target, for a load/store of the specified type.
7286 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
7287 const Type *Ty) const {
7288 // X86 supports extremely general addressing modes.
7289 CodeModel::Model M = getTargetMachine().getCodeModel();
7291 // X86 allows a sign-extended 32-bit immediate field as a displacement.
7292 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
7297 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
7299 // If a reference to this global requires an extra load, we can't fold it.
7300 if (isGlobalStubReference(GVFlags))
7303 // If BaseGV requires a register for the PIC base, we cannot also have a
7304 // BaseReg specified.
7305 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
7308 // If lower 4G is not available, then we must use rip-relative addressing.
7309 if (Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
7319 // These scales always work.
7324 // These scales are formed with basereg+scalereg. Only accept if there is
7329 default: // Other stuff never works.
7337 bool X86TargetLowering::isTruncateFree(const Type *Ty1, const Type *Ty2) const {
7338 if (!Ty1->isInteger() || !Ty2->isInteger())
7340 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
7341 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
7342 if (NumBits1 <= NumBits2)
7344 return Subtarget->is64Bit() || NumBits1 < 64;
7347 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
7348 if (!VT1.isInteger() || !VT2.isInteger())
7350 unsigned NumBits1 = VT1.getSizeInBits();
7351 unsigned NumBits2 = VT2.getSizeInBits();
7352 if (NumBits1 <= NumBits2)
7354 return Subtarget->is64Bit() || NumBits1 < 64;
7357 bool X86TargetLowering::isZExtFree(const Type *Ty1, const Type *Ty2) const {
7358 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
7359 return Ty1 == Type::getInt32Ty(Ty1->getContext()) &&
7360 Ty2 == Type::getInt64Ty(Ty1->getContext()) && Subtarget->is64Bit();
7363 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
7364 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
7365 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
7368 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
7369 // i16 instructions are longer (0x66 prefix) and potentially slower.
7370 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
7373 /// isShuffleMaskLegal - Targets can use this to indicate that they only
7374 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
7375 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
7376 /// are assumed to be legal.
7378 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
7380 // Only do shuffles on 128-bit vector types for now.
7381 if (VT.getSizeInBits() == 64)
7384 // FIXME: pshufb, blends, shifts.
7385 return (VT.getVectorNumElements() == 2 ||
7386 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
7387 isMOVLMask(M, VT) ||
7388 isSHUFPMask(M, VT) ||
7389 isPSHUFDMask(M, VT) ||
7390 isPSHUFHWMask(M, VT) ||
7391 isPSHUFLWMask(M, VT) ||
7392 isPALIGNRMask(M, VT, Subtarget->hasSSSE3()) ||
7393 isUNPCKLMask(M, VT) ||
7394 isUNPCKHMask(M, VT) ||
7395 isUNPCKL_v_undef_Mask(M, VT) ||
7396 isUNPCKH_v_undef_Mask(M, VT));
7400 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
7402 unsigned NumElts = VT.getVectorNumElements();
7403 // FIXME: This collection of masks seems suspect.
7406 if (NumElts == 4 && VT.getSizeInBits() == 128) {
7407 return (isMOVLMask(Mask, VT) ||
7408 isCommutedMOVLMask(Mask, VT, true) ||
7409 isSHUFPMask(Mask, VT) ||
7410 isCommutedSHUFPMask(Mask, VT));
7415 //===----------------------------------------------------------------------===//
7416 // X86 Scheduler Hooks
7417 //===----------------------------------------------------------------------===//
7419 // private utility function
7421 X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
7422 MachineBasicBlock *MBB,
7430 TargetRegisterClass *RC,
7431 bool invSrc) const {
7432 // For the atomic bitwise operator, we generate
7435 // ld t1 = [bitinstr.addr]
7436 // op t2 = t1, [bitinstr.val]
7438 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
7440 // fallthrough -->nextMBB
7441 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7442 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
7443 MachineFunction::iterator MBBIter = MBB;
7446 /// First build the CFG
7447 MachineFunction *F = MBB->getParent();
7448 MachineBasicBlock *thisMBB = MBB;
7449 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
7450 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
7451 F->insert(MBBIter, newMBB);
7452 F->insert(MBBIter, nextMBB);
7454 // Move all successors to thisMBB to nextMBB
7455 nextMBB->transferSuccessors(thisMBB);
7457 // Update thisMBB to fall through to newMBB
7458 thisMBB->addSuccessor(newMBB);
7460 // newMBB jumps to itself and fall through to nextMBB
7461 newMBB->addSuccessor(nextMBB);
7462 newMBB->addSuccessor(newMBB);
7464 // Insert instructions into newMBB based on incoming instruction
7465 assert(bInstr->getNumOperands() < X86AddrNumOperands + 4 &&
7466 "unexpected number of operands");
7467 DebugLoc dl = bInstr->getDebugLoc();
7468 MachineOperand& destOper = bInstr->getOperand(0);
7469 MachineOperand* argOpers[2 + X86AddrNumOperands];
7470 int numArgs = bInstr->getNumOperands() - 1;
7471 for (int i=0; i < numArgs; ++i)
7472 argOpers[i] = &bInstr->getOperand(i+1);
7474 // x86 address has 4 operands: base, index, scale, and displacement
7475 int lastAddrIndx = X86AddrNumOperands - 1; // [0,3]
7476 int valArgIndx = lastAddrIndx + 1;
7478 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
7479 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1);
7480 for (int i=0; i <= lastAddrIndx; ++i)
7481 (*MIB).addOperand(*argOpers[i]);
7483 unsigned tt = F->getRegInfo().createVirtualRegister(RC);
7485 MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1);
7490 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
7491 assert((argOpers[valArgIndx]->isReg() ||
7492 argOpers[valArgIndx]->isImm()) &&
7494 if (argOpers[valArgIndx]->isReg())
7495 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2);
7497 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2);
7499 (*MIB).addOperand(*argOpers[valArgIndx]);
7501 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), EAXreg);
7504 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc));
7505 for (int i=0; i <= lastAddrIndx; ++i)
7506 (*MIB).addOperand(*argOpers[i]);
7508 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
7509 (*MIB).setMemRefs(bInstr->memoperands_begin(),
7510 bInstr->memoperands_end());
7512 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), destOper.getReg());
7516 BuildMI(newMBB, dl, TII->get(X86::JNE)).addMBB(newMBB);
7518 F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now.
7522 // private utility function: 64 bit atomics on 32 bit host.
7524 X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
7525 MachineBasicBlock *MBB,
7530 bool invSrc) const {
7531 // For the atomic bitwise operator, we generate
7532 // thisMBB (instructions are in pairs, except cmpxchg8b)
7533 // ld t1,t2 = [bitinstr.addr]
7535 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4)
7536 // op t5, t6 <- out1, out2, [bitinstr.val]
7537 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val])
7538 // mov ECX, EBX <- t5, t6
7539 // mov EAX, EDX <- t1, t2
7540 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit]
7541 // mov t3, t4 <- EAX, EDX
7543 // result in out1, out2
7544 // fallthrough -->nextMBB
7546 const TargetRegisterClass *RC = X86::GR32RegisterClass;
7547 const unsigned LoadOpc = X86::MOV32rm;
7548 const unsigned copyOpc = X86::MOV32rr;
7549 const unsigned NotOpc = X86::NOT32r;
7550 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7551 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
7552 MachineFunction::iterator MBBIter = MBB;
7555 /// First build the CFG
7556 MachineFunction *F = MBB->getParent();
7557 MachineBasicBlock *thisMBB = MBB;
7558 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
7559 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
7560 F->insert(MBBIter, newMBB);
7561 F->insert(MBBIter, nextMBB);
7563 // Move all successors to thisMBB to nextMBB
7564 nextMBB->transferSuccessors(thisMBB);
7566 // Update thisMBB to fall through to newMBB
7567 thisMBB->addSuccessor(newMBB);
7569 // newMBB jumps to itself and fall through to nextMBB
7570 newMBB->addSuccessor(nextMBB);
7571 newMBB->addSuccessor(newMBB);
7573 DebugLoc dl = bInstr->getDebugLoc();
7574 // Insert instructions into newMBB based on incoming instruction
7575 // There are 8 "real" operands plus 9 implicit def/uses, ignored here.
7576 assert(bInstr->getNumOperands() < X86AddrNumOperands + 14 &&
7577 "unexpected number of operands");
7578 MachineOperand& dest1Oper = bInstr->getOperand(0);
7579 MachineOperand& dest2Oper = bInstr->getOperand(1);
7580 MachineOperand* argOpers[2 + X86AddrNumOperands];
7581 for (int i=0; i < 2 + X86AddrNumOperands; ++i)
7582 argOpers[i] = &bInstr->getOperand(i+2);
7584 // x86 address has 4 operands: base, index, scale, and displacement
7585 int lastAddrIndx = X86AddrNumOperands - 1; // [0,3]
7587 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
7588 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1);
7589 for (int i=0; i <= lastAddrIndx; ++i)
7590 (*MIB).addOperand(*argOpers[i]);
7591 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
7592 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2);
7593 // add 4 to displacement.
7594 for (int i=0; i <= lastAddrIndx-2; ++i)
7595 (*MIB).addOperand(*argOpers[i]);
7596 MachineOperand newOp3 = *(argOpers[3]);
7598 newOp3.setImm(newOp3.getImm()+4);
7600 newOp3.setOffset(newOp3.getOffset()+4);
7601 (*MIB).addOperand(newOp3);
7602 (*MIB).addOperand(*argOpers[lastAddrIndx]);
7604 // t3/4 are defined later, at the bottom of the loop
7605 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
7606 unsigned t4 = F->getRegInfo().createVirtualRegister(RC);
7607 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg())
7608 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB);
7609 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg())
7610 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB);
7612 unsigned tt1 = F->getRegInfo().createVirtualRegister(RC);
7613 unsigned tt2 = F->getRegInfo().createVirtualRegister(RC);
7615 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), tt1).addReg(t1);
7616 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), tt2).addReg(t2);
7622 int valArgIndx = lastAddrIndx + 1;
7623 assert((argOpers[valArgIndx]->isReg() ||
7624 argOpers[valArgIndx]->isImm()) &&
7626 unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
7627 unsigned t6 = F->getRegInfo().createVirtualRegister(RC);
7628 if (argOpers[valArgIndx]->isReg())
7629 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5);
7631 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5);
7632 if (regOpcL != X86::MOV32rr)
7634 (*MIB).addOperand(*argOpers[valArgIndx]);
7635 assert(argOpers[valArgIndx + 1]->isReg() ==
7636 argOpers[valArgIndx]->isReg());
7637 assert(argOpers[valArgIndx + 1]->isImm() ==
7638 argOpers[valArgIndx]->isImm());
7639 if (argOpers[valArgIndx + 1]->isReg())
7640 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6);
7642 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6);
7643 if (regOpcH != X86::MOV32rr)
7645 (*MIB).addOperand(*argOpers[valArgIndx + 1]);
7647 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EAX);
7649 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EDX);
7652 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EBX);
7654 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::ECX);
7657 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B));
7658 for (int i=0; i <= lastAddrIndx; ++i)
7659 (*MIB).addOperand(*argOpers[i]);
7661 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
7662 (*MIB).setMemRefs(bInstr->memoperands_begin(),
7663 bInstr->memoperands_end());
7665 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), t3);
7666 MIB.addReg(X86::EAX);
7667 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), t4);
7668 MIB.addReg(X86::EDX);
7671 BuildMI(newMBB, dl, TII->get(X86::JNE)).addMBB(newMBB);
7673 F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now.
7677 // private utility function
7679 X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
7680 MachineBasicBlock *MBB,
7681 unsigned cmovOpc) const {
7682 // For the atomic min/max operator, we generate
7685 // ld t1 = [min/max.addr]
7686 // mov t2 = [min/max.val]
7688 // cmov[cond] t2 = t1
7690 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
7692 // fallthrough -->nextMBB
7694 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7695 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
7696 MachineFunction::iterator MBBIter = MBB;
7699 /// First build the CFG
7700 MachineFunction *F = MBB->getParent();
7701 MachineBasicBlock *thisMBB = MBB;
7702 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
7703 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
7704 F->insert(MBBIter, newMBB);
7705 F->insert(MBBIter, nextMBB);
7707 // Move all successors of thisMBB to nextMBB
7708 nextMBB->transferSuccessors(thisMBB);
7710 // Update thisMBB to fall through to newMBB
7711 thisMBB->addSuccessor(newMBB);
7713 // newMBB jumps to newMBB and fall through to nextMBB
7714 newMBB->addSuccessor(nextMBB);
7715 newMBB->addSuccessor(newMBB);
7717 DebugLoc dl = mInstr->getDebugLoc();
7718 // Insert instructions into newMBB based on incoming instruction
7719 assert(mInstr->getNumOperands() < X86AddrNumOperands + 4 &&
7720 "unexpected number of operands");
7721 MachineOperand& destOper = mInstr->getOperand(0);
7722 MachineOperand* argOpers[2 + X86AddrNumOperands];
7723 int numArgs = mInstr->getNumOperands() - 1;
7724 for (int i=0; i < numArgs; ++i)
7725 argOpers[i] = &mInstr->getOperand(i+1);
7727 // x86 address has 4 operands: base, index, scale, and displacement
7728 int lastAddrIndx = X86AddrNumOperands - 1; // [0,3]
7729 int valArgIndx = lastAddrIndx + 1;
7731 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
7732 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1);
7733 for (int i=0; i <= lastAddrIndx; ++i)
7734 (*MIB).addOperand(*argOpers[i]);
7736 // We only support register and immediate values
7737 assert((argOpers[valArgIndx]->isReg() ||
7738 argOpers[valArgIndx]->isImm()) &&
7741 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
7742 if (argOpers[valArgIndx]->isReg())
7743 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
7745 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
7746 (*MIB).addOperand(*argOpers[valArgIndx]);
7748 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), X86::EAX);
7751 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr));
7756 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
7757 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3);
7761 // Cmp and exchange if none has modified the memory location
7762 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32));
7763 for (int i=0; i <= lastAddrIndx; ++i)
7764 (*MIB).addOperand(*argOpers[i]);
7766 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
7767 (*MIB).setMemRefs(mInstr->memoperands_begin(),
7768 mInstr->memoperands_end());
7770 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), destOper.getReg());
7771 MIB.addReg(X86::EAX);
7774 BuildMI(newMBB, dl, TII->get(X86::JNE)).addMBB(newMBB);
7776 F->DeleteMachineInstr(mInstr); // The pseudo instruction is gone now.
7780 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
7781 // all of this code can be replaced with that in the .td file.
7783 X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB,
7784 unsigned numArgs, bool memArg) const {
7786 MachineFunction *F = BB->getParent();
7787 DebugLoc dl = MI->getDebugLoc();
7788 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7792 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm;
7794 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr;
7796 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(Opc));
7798 for (unsigned i = 0; i < numArgs; ++i) {
7799 MachineOperand &Op = MI->getOperand(i+1);
7801 if (!(Op.isReg() && Op.isImplicit()))
7805 BuildMI(BB, dl, TII->get(X86::MOVAPSrr), MI->getOperand(0).getReg())
7808 F->DeleteMachineInstr(MI);
7814 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
7816 MachineBasicBlock *MBB) const {
7817 // Emit code to save XMM registers to the stack. The ABI says that the
7818 // number of registers to save is given in %al, so it's theoretically
7819 // possible to do an indirect jump trick to avoid saving all of them,
7820 // however this code takes a simpler approach and just executes all
7821 // of the stores if %al is non-zero. It's less code, and it's probably
7822 // easier on the hardware branch predictor, and stores aren't all that
7823 // expensive anyway.
7825 // Create the new basic blocks. One block contains all the XMM stores,
7826 // and one block is the final destination regardless of whether any
7827 // stores were performed.
7828 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
7829 MachineFunction *F = MBB->getParent();
7830 MachineFunction::iterator MBBIter = MBB;
7832 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
7833 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
7834 F->insert(MBBIter, XMMSaveMBB);
7835 F->insert(MBBIter, EndMBB);
7838 // Move any original successors of MBB to the end block.
7839 EndMBB->transferSuccessors(MBB);
7840 // The original block will now fall through to the XMM save block.
7841 MBB->addSuccessor(XMMSaveMBB);
7842 // The XMMSaveMBB will fall through to the end block.
7843 XMMSaveMBB->addSuccessor(EndMBB);
7845 // Now add the instructions.
7846 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7847 DebugLoc DL = MI->getDebugLoc();
7849 unsigned CountReg = MI->getOperand(0).getReg();
7850 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
7851 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
7853 if (!Subtarget->isTargetWin64()) {
7854 // If %al is 0, branch around the XMM save block.
7855 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
7856 BuildMI(MBB, DL, TII->get(X86::JE)).addMBB(EndMBB);
7857 MBB->addSuccessor(EndMBB);
7860 // In the XMM save block, save all the XMM argument registers.
7861 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
7862 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
7863 MachineMemOperand *MMO =
7864 F->getMachineMemOperand(
7865 PseudoSourceValue::getFixedStack(RegSaveFrameIndex),
7866 MachineMemOperand::MOStore, Offset,
7867 /*Size=*/16, /*Align=*/16);
7868 BuildMI(XMMSaveMBB, DL, TII->get(X86::MOVAPSmr))
7869 .addFrameIndex(RegSaveFrameIndex)
7870 .addImm(/*Scale=*/1)
7871 .addReg(/*IndexReg=*/0)
7872 .addImm(/*Disp=*/Offset)
7873 .addReg(/*Segment=*/0)
7874 .addReg(MI->getOperand(i).getReg())
7875 .addMemOperand(MMO);
7878 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
7884 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
7885 MachineBasicBlock *BB,
7886 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const {
7887 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7888 DebugLoc DL = MI->getDebugLoc();
7890 // To "insert" a SELECT_CC instruction, we actually have to insert the
7891 // diamond control-flow pattern. The incoming instruction knows the
7892 // destination vreg to set, the condition code register to branch on, the
7893 // true/false values to select between, and a branch opcode to use.
7894 const BasicBlock *LLVM_BB = BB->getBasicBlock();
7895 MachineFunction::iterator It = BB;
7901 // cmpTY ccX, r1, r2
7903 // fallthrough --> copy0MBB
7904 MachineBasicBlock *thisMBB = BB;
7905 MachineFunction *F = BB->getParent();
7906 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
7907 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
7909 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
7910 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
7911 F->insert(It, copy0MBB);
7912 F->insert(It, sinkMBB);
7913 // Update machine-CFG edges by first adding all successors of the current
7914 // block to the new block which will contain the Phi node for the select.
7915 // Also inform sdisel of the edge changes.
7916 for (MachineBasicBlock::succ_iterator I = BB->succ_begin(),
7917 E = BB->succ_end(); I != E; ++I) {
7918 EM->insert(std::make_pair(*I, sinkMBB));
7919 sinkMBB->addSuccessor(*I);
7921 // Next, remove all successors of the current block, and add the true
7922 // and fallthrough blocks as its successors.
7923 while (!BB->succ_empty())
7924 BB->removeSuccessor(BB->succ_begin());
7925 // Add the true and fallthrough blocks as its successors.
7926 BB->addSuccessor(copy0MBB);
7927 BB->addSuccessor(sinkMBB);
7930 // %FalseValue = ...
7931 // # fallthrough to sinkMBB
7934 // Update machine-CFG edges
7935 BB->addSuccessor(sinkMBB);
7938 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
7941 BuildMI(BB, DL, TII->get(X86::PHI), MI->getOperand(0).getReg())
7942 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
7943 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
7945 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
7951 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
7952 MachineBasicBlock *BB,
7953 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const {
7954 switch (MI->getOpcode()) {
7955 default: assert(false && "Unexpected instr type to insert");
7957 case X86::CMOV_V1I64:
7958 case X86::CMOV_FR32:
7959 case X86::CMOV_FR64:
7960 case X86::CMOV_V4F32:
7961 case X86::CMOV_V2F64:
7962 case X86::CMOV_V2I64:
7963 return EmitLoweredSelect(MI, BB, EM);
7965 case X86::FP32_TO_INT16_IN_MEM:
7966 case X86::FP32_TO_INT32_IN_MEM:
7967 case X86::FP32_TO_INT64_IN_MEM:
7968 case X86::FP64_TO_INT16_IN_MEM:
7969 case X86::FP64_TO_INT32_IN_MEM:
7970 case X86::FP64_TO_INT64_IN_MEM:
7971 case X86::FP80_TO_INT16_IN_MEM:
7972 case X86::FP80_TO_INT32_IN_MEM:
7973 case X86::FP80_TO_INT64_IN_MEM: {
7974 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7975 DebugLoc DL = MI->getDebugLoc();
7977 // Change the floating point control register to use "round towards zero"
7978 // mode when truncating to an integer value.
7979 MachineFunction *F = BB->getParent();
7980 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2);
7981 addFrameReference(BuildMI(BB, DL, TII->get(X86::FNSTCW16m)), CWFrameIdx);
7983 // Load the old value of the high byte of the control word...
7985 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass);
7986 addFrameReference(BuildMI(BB, DL, TII->get(X86::MOV16rm), OldCW),
7989 // Set the high part to be round to zero...
7990 addFrameReference(BuildMI(BB, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
7993 // Reload the modified control word now...
7994 addFrameReference(BuildMI(BB, DL, TII->get(X86::FLDCW16m)), CWFrameIdx);
7996 // Restore the memory image of control word to original value
7997 addFrameReference(BuildMI(BB, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
8000 // Get the X86 opcode to use.
8002 switch (MI->getOpcode()) {
8003 default: llvm_unreachable("illegal opcode!");
8004 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
8005 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
8006 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
8007 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
8008 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
8009 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
8010 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
8011 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
8012 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
8016 MachineOperand &Op = MI->getOperand(0);
8018 AM.BaseType = X86AddressMode::RegBase;
8019 AM.Base.Reg = Op.getReg();
8021 AM.BaseType = X86AddressMode::FrameIndexBase;
8022 AM.Base.FrameIndex = Op.getIndex();
8024 Op = MI->getOperand(1);
8026 AM.Scale = Op.getImm();
8027 Op = MI->getOperand(2);
8029 AM.IndexReg = Op.getImm();
8030 Op = MI->getOperand(3);
8031 if (Op.isGlobal()) {
8032 AM.GV = Op.getGlobal();
8034 AM.Disp = Op.getImm();
8036 addFullAddress(BuildMI(BB, DL, TII->get(Opc)), AM)
8037 .addReg(MI->getOperand(X86AddrNumOperands).getReg());
8039 // Reload the original control word now.
8040 addFrameReference(BuildMI(BB, DL, TII->get(X86::FLDCW16m)), CWFrameIdx);
8042 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
8045 // String/text processing lowering.
8046 case X86::PCMPISTRM128REG:
8047 return EmitPCMP(MI, BB, 3, false /* in-mem */);
8048 case X86::PCMPISTRM128MEM:
8049 return EmitPCMP(MI, BB, 3, true /* in-mem */);
8050 case X86::PCMPESTRM128REG:
8051 return EmitPCMP(MI, BB, 5, false /* in mem */);
8052 case X86::PCMPESTRM128MEM:
8053 return EmitPCMP(MI, BB, 5, true /* in mem */);
8056 case X86::ATOMAND32:
8057 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
8058 X86::AND32ri, X86::MOV32rm,
8059 X86::LCMPXCHG32, X86::MOV32rr,
8060 X86::NOT32r, X86::EAX,
8061 X86::GR32RegisterClass);
8063 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
8064 X86::OR32ri, X86::MOV32rm,
8065 X86::LCMPXCHG32, X86::MOV32rr,
8066 X86::NOT32r, X86::EAX,
8067 X86::GR32RegisterClass);
8068 case X86::ATOMXOR32:
8069 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
8070 X86::XOR32ri, X86::MOV32rm,
8071 X86::LCMPXCHG32, X86::MOV32rr,
8072 X86::NOT32r, X86::EAX,
8073 X86::GR32RegisterClass);
8074 case X86::ATOMNAND32:
8075 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
8076 X86::AND32ri, X86::MOV32rm,
8077 X86::LCMPXCHG32, X86::MOV32rr,
8078 X86::NOT32r, X86::EAX,
8079 X86::GR32RegisterClass, true);
8080 case X86::ATOMMIN32:
8081 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
8082 case X86::ATOMMAX32:
8083 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
8084 case X86::ATOMUMIN32:
8085 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
8086 case X86::ATOMUMAX32:
8087 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
8089 case X86::ATOMAND16:
8090 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
8091 X86::AND16ri, X86::MOV16rm,
8092 X86::LCMPXCHG16, X86::MOV16rr,
8093 X86::NOT16r, X86::AX,
8094 X86::GR16RegisterClass);
8096 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
8097 X86::OR16ri, X86::MOV16rm,
8098 X86::LCMPXCHG16, X86::MOV16rr,
8099 X86::NOT16r, X86::AX,
8100 X86::GR16RegisterClass);
8101 case X86::ATOMXOR16:
8102 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr,
8103 X86::XOR16ri, X86::MOV16rm,
8104 X86::LCMPXCHG16, X86::MOV16rr,
8105 X86::NOT16r, X86::AX,
8106 X86::GR16RegisterClass);
8107 case X86::ATOMNAND16:
8108 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
8109 X86::AND16ri, X86::MOV16rm,
8110 X86::LCMPXCHG16, X86::MOV16rr,
8111 X86::NOT16r, X86::AX,
8112 X86::GR16RegisterClass, true);
8113 case X86::ATOMMIN16:
8114 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr);
8115 case X86::ATOMMAX16:
8116 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr);
8117 case X86::ATOMUMIN16:
8118 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr);
8119 case X86::ATOMUMAX16:
8120 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr);
8123 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
8124 X86::AND8ri, X86::MOV8rm,
8125 X86::LCMPXCHG8, X86::MOV8rr,
8126 X86::NOT8r, X86::AL,
8127 X86::GR8RegisterClass);
8129 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
8130 X86::OR8ri, X86::MOV8rm,
8131 X86::LCMPXCHG8, X86::MOV8rr,
8132 X86::NOT8r, X86::AL,
8133 X86::GR8RegisterClass);
8135 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr,
8136 X86::XOR8ri, X86::MOV8rm,
8137 X86::LCMPXCHG8, X86::MOV8rr,
8138 X86::NOT8r, X86::AL,
8139 X86::GR8RegisterClass);
8140 case X86::ATOMNAND8:
8141 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
8142 X86::AND8ri, X86::MOV8rm,
8143 X86::LCMPXCHG8, X86::MOV8rr,
8144 X86::NOT8r, X86::AL,
8145 X86::GR8RegisterClass, true);
8146 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
8147 // This group is for 64-bit host.
8148 case X86::ATOMAND64:
8149 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
8150 X86::AND64ri32, X86::MOV64rm,
8151 X86::LCMPXCHG64, X86::MOV64rr,
8152 X86::NOT64r, X86::RAX,
8153 X86::GR64RegisterClass);
8155 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
8156 X86::OR64ri32, X86::MOV64rm,
8157 X86::LCMPXCHG64, X86::MOV64rr,
8158 X86::NOT64r, X86::RAX,
8159 X86::GR64RegisterClass);
8160 case X86::ATOMXOR64:
8161 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr,
8162 X86::XOR64ri32, X86::MOV64rm,
8163 X86::LCMPXCHG64, X86::MOV64rr,
8164 X86::NOT64r, X86::RAX,
8165 X86::GR64RegisterClass);
8166 case X86::ATOMNAND64:
8167 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
8168 X86::AND64ri32, X86::MOV64rm,
8169 X86::LCMPXCHG64, X86::MOV64rr,
8170 X86::NOT64r, X86::RAX,
8171 X86::GR64RegisterClass, true);
8172 case X86::ATOMMIN64:
8173 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr);
8174 case X86::ATOMMAX64:
8175 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr);
8176 case X86::ATOMUMIN64:
8177 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr);
8178 case X86::ATOMUMAX64:
8179 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr);
8181 // This group does 64-bit operations on a 32-bit host.
8182 case X86::ATOMAND6432:
8183 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8184 X86::AND32rr, X86::AND32rr,
8185 X86::AND32ri, X86::AND32ri,
8187 case X86::ATOMOR6432:
8188 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8189 X86::OR32rr, X86::OR32rr,
8190 X86::OR32ri, X86::OR32ri,
8192 case X86::ATOMXOR6432:
8193 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8194 X86::XOR32rr, X86::XOR32rr,
8195 X86::XOR32ri, X86::XOR32ri,
8197 case X86::ATOMNAND6432:
8198 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8199 X86::AND32rr, X86::AND32rr,
8200 X86::AND32ri, X86::AND32ri,
8202 case X86::ATOMADD6432:
8203 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8204 X86::ADD32rr, X86::ADC32rr,
8205 X86::ADD32ri, X86::ADC32ri,
8207 case X86::ATOMSUB6432:
8208 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8209 X86::SUB32rr, X86::SBB32rr,
8210 X86::SUB32ri, X86::SBB32ri,
8212 case X86::ATOMSWAP6432:
8213 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8214 X86::MOV32rr, X86::MOV32rr,
8215 X86::MOV32ri, X86::MOV32ri,
8217 case X86::VASTART_SAVE_XMM_REGS:
8218 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
8222 //===----------------------------------------------------------------------===//
8223 // X86 Optimization Hooks
8224 //===----------------------------------------------------------------------===//
8226 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
8230 const SelectionDAG &DAG,
8231 unsigned Depth) const {
8232 unsigned Opc = Op.getOpcode();
8233 assert((Opc >= ISD::BUILTIN_OP_END ||
8234 Opc == ISD::INTRINSIC_WO_CHAIN ||
8235 Opc == ISD::INTRINSIC_W_CHAIN ||
8236 Opc == ISD::INTRINSIC_VOID) &&
8237 "Should use MaskedValueIsZero if you don't know whether Op"
8238 " is a target node!");
8240 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything.
8252 // These nodes' second result is a boolean.
8253 if (Op.getResNo() == 0)
8257 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(),
8258 Mask.getBitWidth() - 1);
8263 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
8264 /// node is a GlobalAddress + offset.
8265 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
8266 GlobalValue* &GA, int64_t &Offset) const{
8267 if (N->getOpcode() == X86ISD::Wrapper) {
8268 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
8269 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
8270 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
8274 return TargetLowering::isGAPlusOffset(N, GA, Offset);
8277 static bool isBaseAlignmentOfN(unsigned N, SDNode *Base,
8278 const TargetLowering &TLI) {
8281 if (TLI.isGAPlusOffset(Base, GV, Offset))
8282 return (GV->getAlignment() >= N && (Offset % N) == 0);
8283 // DAG combine handles the stack object case.
8287 static bool EltsFromConsecutiveLoads(ShuffleVectorSDNode *N, unsigned NumElems,
8288 EVT EltVT, LoadSDNode *&LDBase,
8289 unsigned &LastLoadedElt,
8290 SelectionDAG &DAG, MachineFrameInfo *MFI,
8291 const TargetLowering &TLI) {
8293 LastLoadedElt = -1U;
8294 for (unsigned i = 0; i < NumElems; ++i) {
8295 if (N->getMaskElt(i) < 0) {
8301 SDValue Elt = DAG.getShuffleScalarElt(N, i);
8302 if (!Elt.getNode() ||
8303 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
8306 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
8308 LDBase = cast<LoadSDNode>(Elt.getNode());
8312 if (Elt.getOpcode() == ISD::UNDEF)
8315 LoadSDNode *LD = cast<LoadSDNode>(Elt);
8316 if (!TLI.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i, MFI))
8323 /// PerformShuffleCombine - Combine a vector_shuffle that is equal to
8324 /// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load
8325 /// if the load addresses are consecutive, non-overlapping, and in the right
8326 /// order. In the case of v2i64, it will see if it can rewrite the
8327 /// shuffle to be an appropriate build vector so it can take advantage of
8328 // performBuildVectorCombine.
8329 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
8330 const TargetLowering &TLI) {
8331 DebugLoc dl = N->getDebugLoc();
8332 EVT VT = N->getValueType(0);
8333 EVT EltVT = VT.getVectorElementType();
8334 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
8335 unsigned NumElems = VT.getVectorNumElements();
8337 if (VT.getSizeInBits() != 128)
8340 // Try to combine a vector_shuffle into a 128-bit load.
8341 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
8342 LoadSDNode *LD = NULL;
8343 unsigned LastLoadedElt;
8344 if (!EltsFromConsecutiveLoads(SVN, NumElems, EltVT, LD, LastLoadedElt, DAG,
8348 if (LastLoadedElt == NumElems - 1) {
8349 if (isBaseAlignmentOfN(16, LD->getBasePtr().getNode(), TLI))
8350 return DAG.getLoad(VT, dl, LD->getChain(), LD->getBasePtr(),
8351 LD->getSrcValue(), LD->getSrcValueOffset(),
8353 return DAG.getLoad(VT, dl, LD->getChain(), LD->getBasePtr(),
8354 LD->getSrcValue(), LD->getSrcValueOffset(),
8355 LD->isVolatile(), LD->getAlignment());
8356 } else if (NumElems == 4 && LastLoadedElt == 1) {
8357 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
8358 SDValue Ops[] = { LD->getChain(), LD->getBasePtr() };
8359 SDValue ResNode = DAG.getNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2);
8360 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, ResNode);
8365 /// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes.
8366 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
8367 const X86Subtarget *Subtarget) {
8368 DebugLoc DL = N->getDebugLoc();
8369 SDValue Cond = N->getOperand(0);
8370 // Get the LHS/RHS of the select.
8371 SDValue LHS = N->getOperand(1);
8372 SDValue RHS = N->getOperand(2);
8374 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
8375 // instructions have the peculiarity that if either operand is a NaN,
8376 // they chose what we call the RHS operand (and as such are not symmetric).
8377 // It happens that this matches the semantics of the common C idiom
8378 // x<y?x:y and related forms, so we can recognize these cases.
8379 if (Subtarget->hasSSE2() &&
8380 (LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64) &&
8381 Cond.getOpcode() == ISD::SETCC) {
8382 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
8384 unsigned Opcode = 0;
8385 // Check for x CC y ? x : y.
8386 if (LHS == Cond.getOperand(0) && RHS == Cond.getOperand(1)) {
8390 // This can be a min if we can prove that at least one of the operands
8392 if (!FiniteOnlyFPMath()) {
8393 if (DAG.isKnownNeverNaN(RHS)) {
8394 // Put the potential NaN in the RHS so that SSE will preserve it.
8395 std::swap(LHS, RHS);
8396 } else if (!DAG.isKnownNeverNaN(LHS))
8399 Opcode = X86ISD::FMIN;
8402 // This can be a min if we can prove that at least one of the operands
8404 if (!FiniteOnlyFPMath()) {
8405 if (DAG.isKnownNeverNaN(LHS)) {
8406 // Put the potential NaN in the RHS so that SSE will preserve it.
8407 std::swap(LHS, RHS);
8408 } else if (!DAG.isKnownNeverNaN(RHS))
8411 Opcode = X86ISD::FMIN;
8414 // This can be a min, but if either operand is a NaN we need it to
8415 // preserve the original LHS.
8416 std::swap(LHS, RHS);
8420 Opcode = X86ISD::FMIN;
8424 // This can be a max if we can prove that at least one of the operands
8426 if (!FiniteOnlyFPMath()) {
8427 if (DAG.isKnownNeverNaN(LHS)) {
8428 // Put the potential NaN in the RHS so that SSE will preserve it.
8429 std::swap(LHS, RHS);
8430 } else if (!DAG.isKnownNeverNaN(RHS))
8433 Opcode = X86ISD::FMAX;
8436 // This can be a max if we can prove that at least one of the operands
8438 if (!FiniteOnlyFPMath()) {
8439 if (DAG.isKnownNeverNaN(RHS)) {
8440 // Put the potential NaN in the RHS so that SSE will preserve it.
8441 std::swap(LHS, RHS);
8442 } else if (!DAG.isKnownNeverNaN(LHS))
8445 Opcode = X86ISD::FMAX;
8448 // This can be a max, but if either operand is a NaN we need it to
8449 // preserve the original LHS.
8450 std::swap(LHS, RHS);
8454 Opcode = X86ISD::FMAX;
8457 // Check for x CC y ? y : x -- a min/max with reversed arms.
8458 } else if (LHS == Cond.getOperand(1) && RHS == Cond.getOperand(0)) {
8462 // This can be a min if we can prove that at least one of the operands
8464 if (!FiniteOnlyFPMath()) {
8465 if (DAG.isKnownNeverNaN(RHS)) {
8466 // Put the potential NaN in the RHS so that SSE will preserve it.
8467 std::swap(LHS, RHS);
8468 } else if (!DAG.isKnownNeverNaN(LHS))
8471 Opcode = X86ISD::FMIN;
8474 // This can be a min if we can prove that at least one of the operands
8476 if (!FiniteOnlyFPMath()) {
8477 if (DAG.isKnownNeverNaN(LHS)) {
8478 // Put the potential NaN in the RHS so that SSE will preserve it.
8479 std::swap(LHS, RHS);
8480 } else if (!DAG.isKnownNeverNaN(RHS))
8483 Opcode = X86ISD::FMIN;
8486 // This can be a min, but if either operand is a NaN we need it to
8487 // preserve the original LHS.
8488 std::swap(LHS, RHS);
8492 Opcode = X86ISD::FMIN;
8496 // This can be a max if we can prove that at least one of the operands
8498 if (!FiniteOnlyFPMath()) {
8499 if (DAG.isKnownNeverNaN(LHS)) {
8500 // Put the potential NaN in the RHS so that SSE will preserve it.
8501 std::swap(LHS, RHS);
8502 } else if (!DAG.isKnownNeverNaN(RHS))
8505 Opcode = X86ISD::FMAX;
8508 // This can be a max if we can prove that at least one of the operands
8510 if (!FiniteOnlyFPMath()) {
8511 if (DAG.isKnownNeverNaN(RHS)) {
8512 // Put the potential NaN in the RHS so that SSE will preserve it.
8513 std::swap(LHS, RHS);
8514 } else if (!DAG.isKnownNeverNaN(LHS))
8517 Opcode = X86ISD::FMAX;
8520 // This can be a max, but if either operand is a NaN we need it to
8521 // preserve the original LHS.
8522 std::swap(LHS, RHS);
8526 Opcode = X86ISD::FMAX;
8532 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
8535 // If this is a select between two integer constants, try to do some
8537 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
8538 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
8539 // Don't do this for crazy integer types.
8540 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
8541 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
8542 // so that TrueC (the true value) is larger than FalseC.
8543 bool NeedsCondInvert = false;
8545 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
8546 // Efficiently invertible.
8547 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
8548 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
8549 isa<ConstantSDNode>(Cond.getOperand(1))))) {
8550 NeedsCondInvert = true;
8551 std::swap(TrueC, FalseC);
8554 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
8555 if (FalseC->getAPIntValue() == 0 &&
8556 TrueC->getAPIntValue().isPowerOf2()) {
8557 if (NeedsCondInvert) // Invert the condition if needed.
8558 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
8559 DAG.getConstant(1, Cond.getValueType()));
8561 // Zero extend the condition if needed.
8562 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
8564 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
8565 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
8566 DAG.getConstant(ShAmt, MVT::i8));
8569 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
8570 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
8571 if (NeedsCondInvert) // Invert the condition if needed.
8572 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
8573 DAG.getConstant(1, Cond.getValueType()));
8575 // Zero extend the condition if needed.
8576 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
8577 FalseC->getValueType(0), Cond);
8578 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
8579 SDValue(FalseC, 0));
8582 // Optimize cases that will turn into an LEA instruction. This requires
8583 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
8584 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
8585 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
8586 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
8588 bool isFastMultiplier = false;
8590 switch ((unsigned char)Diff) {
8592 case 1: // result = add base, cond
8593 case 2: // result = lea base( , cond*2)
8594 case 3: // result = lea base(cond, cond*2)
8595 case 4: // result = lea base( , cond*4)
8596 case 5: // result = lea base(cond, cond*4)
8597 case 8: // result = lea base( , cond*8)
8598 case 9: // result = lea base(cond, cond*8)
8599 isFastMultiplier = true;
8604 if (isFastMultiplier) {
8605 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
8606 if (NeedsCondInvert) // Invert the condition if needed.
8607 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
8608 DAG.getConstant(1, Cond.getValueType()));
8610 // Zero extend the condition if needed.
8611 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
8613 // Scale the condition by the difference.
8615 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
8616 DAG.getConstant(Diff, Cond.getValueType()));
8618 // Add the base if non-zero.
8619 if (FalseC->getAPIntValue() != 0)
8620 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
8621 SDValue(FalseC, 0));
8631 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
8632 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
8633 TargetLowering::DAGCombinerInfo &DCI) {
8634 DebugLoc DL = N->getDebugLoc();
8636 // If the flag operand isn't dead, don't touch this CMOV.
8637 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
8640 // If this is a select between two integer constants, try to do some
8641 // optimizations. Note that the operands are ordered the opposite of SELECT
8643 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
8644 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
8645 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
8646 // larger than FalseC (the false value).
8647 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
8649 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
8650 CC = X86::GetOppositeBranchCondition(CC);
8651 std::swap(TrueC, FalseC);
8654 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
8655 // This is efficient for any integer data type (including i8/i16) and
8657 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
8658 SDValue Cond = N->getOperand(3);
8659 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
8660 DAG.getConstant(CC, MVT::i8), Cond);
8662 // Zero extend the condition if needed.
8663 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
8665 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
8666 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
8667 DAG.getConstant(ShAmt, MVT::i8));
8668 if (N->getNumValues() == 2) // Dead flag value?
8669 return DCI.CombineTo(N, Cond, SDValue());
8673 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
8674 // for any integer data type, including i8/i16.
8675 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
8676 SDValue Cond = N->getOperand(3);
8677 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
8678 DAG.getConstant(CC, MVT::i8), Cond);
8680 // Zero extend the condition if needed.
8681 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
8682 FalseC->getValueType(0), Cond);
8683 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
8684 SDValue(FalseC, 0));
8686 if (N->getNumValues() == 2) // Dead flag value?
8687 return DCI.CombineTo(N, Cond, SDValue());
8691 // Optimize cases that will turn into an LEA instruction. This requires
8692 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
8693 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
8694 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
8695 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
8697 bool isFastMultiplier = false;
8699 switch ((unsigned char)Diff) {
8701 case 1: // result = add base, cond
8702 case 2: // result = lea base( , cond*2)
8703 case 3: // result = lea base(cond, cond*2)
8704 case 4: // result = lea base( , cond*4)
8705 case 5: // result = lea base(cond, cond*4)
8706 case 8: // result = lea base( , cond*8)
8707 case 9: // result = lea base(cond, cond*8)
8708 isFastMultiplier = true;
8713 if (isFastMultiplier) {
8714 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
8715 SDValue Cond = N->getOperand(3);
8716 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
8717 DAG.getConstant(CC, MVT::i8), Cond);
8718 // Zero extend the condition if needed.
8719 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
8721 // Scale the condition by the difference.
8723 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
8724 DAG.getConstant(Diff, Cond.getValueType()));
8726 // Add the base if non-zero.
8727 if (FalseC->getAPIntValue() != 0)
8728 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
8729 SDValue(FalseC, 0));
8730 if (N->getNumValues() == 2) // Dead flag value?
8731 return DCI.CombineTo(N, Cond, SDValue());
8741 /// PerformMulCombine - Optimize a single multiply with constant into two
8742 /// in order to implement it with two cheaper instructions, e.g.
8743 /// LEA + SHL, LEA + LEA.
8744 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
8745 TargetLowering::DAGCombinerInfo &DCI) {
8746 if (DAG.getMachineFunction().
8747 getFunction()->hasFnAttr(Attribute::OptimizeForSize))
8750 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
8753 EVT VT = N->getValueType(0);
8757 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
8760 uint64_t MulAmt = C->getZExtValue();
8761 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
8764 uint64_t MulAmt1 = 0;
8765 uint64_t MulAmt2 = 0;
8766 if ((MulAmt % 9) == 0) {
8768 MulAmt2 = MulAmt / 9;
8769 } else if ((MulAmt % 5) == 0) {
8771 MulAmt2 = MulAmt / 5;
8772 } else if ((MulAmt % 3) == 0) {
8774 MulAmt2 = MulAmt / 3;
8777 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
8778 DebugLoc DL = N->getDebugLoc();
8780 if (isPowerOf2_64(MulAmt2) &&
8781 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
8782 // If second multiplifer is pow2, issue it first. We want the multiply by
8783 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
8785 std::swap(MulAmt1, MulAmt2);
8788 if (isPowerOf2_64(MulAmt1))
8789 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
8790 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
8792 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
8793 DAG.getConstant(MulAmt1, VT));
8795 if (isPowerOf2_64(MulAmt2))
8796 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
8797 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
8799 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
8800 DAG.getConstant(MulAmt2, VT));
8802 // Do not add new nodes to DAG combiner worklist.
8803 DCI.CombineTo(N, NewMul, false);
8809 /// PerformShiftCombine - Transforms vector shift nodes to use vector shifts
8811 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
8812 const X86Subtarget *Subtarget) {
8813 // On X86 with SSE2 support, we can transform this to a vector shift if
8814 // all elements are shifted by the same amount. We can't do this in legalize
8815 // because the a constant vector is typically transformed to a constant pool
8816 // so we have no knowledge of the shift amount.
8817 if (!Subtarget->hasSSE2())
8820 EVT VT = N->getValueType(0);
8821 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
8824 SDValue ShAmtOp = N->getOperand(1);
8825 EVT EltVT = VT.getVectorElementType();
8826 DebugLoc DL = N->getDebugLoc();
8827 SDValue BaseShAmt = SDValue();
8828 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
8829 unsigned NumElts = VT.getVectorNumElements();
8831 for (; i != NumElts; ++i) {
8832 SDValue Arg = ShAmtOp.getOperand(i);
8833 if (Arg.getOpcode() == ISD::UNDEF) continue;
8837 for (; i != NumElts; ++i) {
8838 SDValue Arg = ShAmtOp.getOperand(i);
8839 if (Arg.getOpcode() == ISD::UNDEF) continue;
8840 if (Arg != BaseShAmt) {
8844 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
8845 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) {
8846 SDValue InVec = ShAmtOp.getOperand(0);
8847 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
8848 unsigned NumElts = InVec.getValueType().getVectorNumElements();
8850 for (; i != NumElts; ++i) {
8851 SDValue Arg = InVec.getOperand(i);
8852 if (Arg.getOpcode() == ISD::UNDEF) continue;
8856 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
8857 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
8858 unsigned SplatIdx = cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex();
8859 if (C->getZExtValue() == SplatIdx)
8860 BaseShAmt = InVec.getOperand(1);
8863 if (BaseShAmt.getNode() == 0)
8864 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
8865 DAG.getIntPtrConstant(0));
8869 // The shift amount is an i32.
8870 if (EltVT.bitsGT(MVT::i32))
8871 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt);
8872 else if (EltVT.bitsLT(MVT::i32))
8873 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt);
8875 // The shift amount is identical so we can do a vector shift.
8876 SDValue ValOp = N->getOperand(0);
8877 switch (N->getOpcode()) {
8879 llvm_unreachable("Unknown shift opcode!");
8882 if (VT == MVT::v2i64)
8883 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
8884 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
8886 if (VT == MVT::v4i32)
8887 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
8888 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
8890 if (VT == MVT::v8i16)
8891 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
8892 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
8896 if (VT == MVT::v4i32)
8897 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
8898 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32),
8900 if (VT == MVT::v8i16)
8901 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
8902 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32),
8906 if (VT == MVT::v2i64)
8907 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
8908 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
8910 if (VT == MVT::v4i32)
8911 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
8912 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32),
8914 if (VT == MVT::v8i16)
8915 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
8916 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32),
8923 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
8924 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
8925 const X86Subtarget *Subtarget) {
8926 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
8927 // the FP state in cases where an emms may be missing.
8928 // A preferable solution to the general problem is to figure out the right
8929 // places to insert EMMS. This qualifies as a quick hack.
8931 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
8932 StoreSDNode *St = cast<StoreSDNode>(N);
8933 EVT VT = St->getValue().getValueType();
8934 if (VT.getSizeInBits() != 64)
8937 const Function *F = DAG.getMachineFunction().getFunction();
8938 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
8939 bool F64IsLegal = !UseSoftFloat && !NoImplicitFloatOps
8940 && Subtarget->hasSSE2();
8941 if ((VT.isVector() ||
8942 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
8943 isa<LoadSDNode>(St->getValue()) &&
8944 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
8945 St->getChain().hasOneUse() && !St->isVolatile()) {
8946 SDNode* LdVal = St->getValue().getNode();
8948 int TokenFactorIndex = -1;
8949 SmallVector<SDValue, 8> Ops;
8950 SDNode* ChainVal = St->getChain().getNode();
8951 // Must be a store of a load. We currently handle two cases: the load
8952 // is a direct child, and it's under an intervening TokenFactor. It is
8953 // possible to dig deeper under nested TokenFactors.
8954 if (ChainVal == LdVal)
8955 Ld = cast<LoadSDNode>(St->getChain());
8956 else if (St->getValue().hasOneUse() &&
8957 ChainVal->getOpcode() == ISD::TokenFactor) {
8958 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) {
8959 if (ChainVal->getOperand(i).getNode() == LdVal) {
8960 TokenFactorIndex = i;
8961 Ld = cast<LoadSDNode>(St->getValue());
8963 Ops.push_back(ChainVal->getOperand(i));
8967 if (!Ld || !ISD::isNormalLoad(Ld))
8970 // If this is not the MMX case, i.e. we are just turning i64 load/store
8971 // into f64 load/store, avoid the transformation if there are multiple
8972 // uses of the loaded value.
8973 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
8976 DebugLoc LdDL = Ld->getDebugLoc();
8977 DebugLoc StDL = N->getDebugLoc();
8978 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
8979 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
8981 if (Subtarget->is64Bit() || F64IsLegal) {
8982 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
8983 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(),
8984 Ld->getBasePtr(), Ld->getSrcValue(),
8985 Ld->getSrcValueOffset(), Ld->isVolatile(),
8986 Ld->getAlignment());
8987 SDValue NewChain = NewLd.getValue(1);
8988 if (TokenFactorIndex != -1) {
8989 Ops.push_back(NewChain);
8990 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
8993 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
8994 St->getSrcValue(), St->getSrcValueOffset(),
8995 St->isVolatile(), St->getAlignment());
8998 // Otherwise, lower to two pairs of 32-bit loads / stores.
8999 SDValue LoAddr = Ld->getBasePtr();
9000 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
9001 DAG.getConstant(4, MVT::i32));
9003 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
9004 Ld->getSrcValue(), Ld->getSrcValueOffset(),
9005 Ld->isVolatile(), Ld->getAlignment());
9006 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
9007 Ld->getSrcValue(), Ld->getSrcValueOffset()+4,
9009 MinAlign(Ld->getAlignment(), 4));
9011 SDValue NewChain = LoLd.getValue(1);
9012 if (TokenFactorIndex != -1) {
9013 Ops.push_back(LoLd);
9014 Ops.push_back(HiLd);
9015 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
9019 LoAddr = St->getBasePtr();
9020 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
9021 DAG.getConstant(4, MVT::i32));
9023 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
9024 St->getSrcValue(), St->getSrcValueOffset(),
9025 St->isVolatile(), St->getAlignment());
9026 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
9028 St->getSrcValueOffset() + 4,
9030 MinAlign(St->getAlignment(), 4));
9031 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
9036 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
9037 /// X86ISD::FXOR nodes.
9038 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
9039 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
9040 // F[X]OR(0.0, x) -> x
9041 // F[X]OR(x, 0.0) -> x
9042 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
9043 if (C->getValueAPF().isPosZero())
9044 return N->getOperand(1);
9045 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
9046 if (C->getValueAPF().isPosZero())
9047 return N->getOperand(0);
9051 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
9052 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
9053 // FAND(0.0, x) -> 0.0
9054 // FAND(x, 0.0) -> 0.0
9055 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
9056 if (C->getValueAPF().isPosZero())
9057 return N->getOperand(0);
9058 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
9059 if (C->getValueAPF().isPosZero())
9060 return N->getOperand(1);
9064 static SDValue PerformBTCombine(SDNode *N,
9066 TargetLowering::DAGCombinerInfo &DCI) {
9067 // BT ignores high bits in the bit index operand.
9068 SDValue Op1 = N->getOperand(1);
9069 if (Op1.hasOneUse()) {
9070 unsigned BitWidth = Op1.getValueSizeInBits();
9071 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
9072 APInt KnownZero, KnownOne;
9073 TargetLowering::TargetLoweringOpt TLO(DAG);
9074 TargetLowering &TLI = DAG.getTargetLoweringInfo();
9075 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
9076 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
9077 DCI.CommitTargetLoweringOpt(TLO);
9082 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
9083 SDValue Op = N->getOperand(0);
9084 if (Op.getOpcode() == ISD::BIT_CONVERT)
9085 Op = Op.getOperand(0);
9086 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
9087 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
9088 VT.getVectorElementType().getSizeInBits() ==
9089 OpVT.getVectorElementType().getSizeInBits()) {
9090 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, Op);
9095 // On X86 and X86-64, atomic operations are lowered to locked instructions.
9096 // Locked instructions, in turn, have implicit fence semantics (all memory
9097 // operations are flushed before issuing the locked instruction, and the
9098 // are not buffered), so we can fold away the common pattern of
9099 // fence-atomic-fence.
9100 static SDValue PerformMEMBARRIERCombine(SDNode* N, SelectionDAG &DAG) {
9101 SDValue atomic = N->getOperand(0);
9102 switch (atomic.getOpcode()) {
9103 case ISD::ATOMIC_CMP_SWAP:
9104 case ISD::ATOMIC_SWAP:
9105 case ISD::ATOMIC_LOAD_ADD:
9106 case ISD::ATOMIC_LOAD_SUB:
9107 case ISD::ATOMIC_LOAD_AND:
9108 case ISD::ATOMIC_LOAD_OR:
9109 case ISD::ATOMIC_LOAD_XOR:
9110 case ISD::ATOMIC_LOAD_NAND:
9111 case ISD::ATOMIC_LOAD_MIN:
9112 case ISD::ATOMIC_LOAD_MAX:
9113 case ISD::ATOMIC_LOAD_UMIN:
9114 case ISD::ATOMIC_LOAD_UMAX:
9120 SDValue fence = atomic.getOperand(0);
9121 if (fence.getOpcode() != ISD::MEMBARRIER)
9124 switch (atomic.getOpcode()) {
9125 case ISD::ATOMIC_CMP_SWAP:
9126 return DAG.UpdateNodeOperands(atomic, fence.getOperand(0),
9127 atomic.getOperand(1), atomic.getOperand(2),
9128 atomic.getOperand(3));
9129 case ISD::ATOMIC_SWAP:
9130 case ISD::ATOMIC_LOAD_ADD:
9131 case ISD::ATOMIC_LOAD_SUB:
9132 case ISD::ATOMIC_LOAD_AND:
9133 case ISD::ATOMIC_LOAD_OR:
9134 case ISD::ATOMIC_LOAD_XOR:
9135 case ISD::ATOMIC_LOAD_NAND:
9136 case ISD::ATOMIC_LOAD_MIN:
9137 case ISD::ATOMIC_LOAD_MAX:
9138 case ISD::ATOMIC_LOAD_UMIN:
9139 case ISD::ATOMIC_LOAD_UMAX:
9140 return DAG.UpdateNodeOperands(atomic, fence.getOperand(0),
9141 atomic.getOperand(1), atomic.getOperand(2));
9147 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
9148 DAGCombinerInfo &DCI) const {
9149 SelectionDAG &DAG = DCI.DAG;
9150 switch (N->getOpcode()) {
9152 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, *this);
9153 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget);
9154 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI);
9155 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
9158 case ISD::SRL: return PerformShiftCombine(N, DAG, Subtarget);
9159 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
9161 case X86ISD::FOR: return PerformFORCombine(N, DAG);
9162 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
9163 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
9164 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
9165 case ISD::MEMBARRIER: return PerformMEMBARRIERCombine(N, DAG);
9171 //===----------------------------------------------------------------------===//
9172 // X86 Inline Assembly Support
9173 //===----------------------------------------------------------------------===//
9175 static bool LowerToBSwap(CallInst *CI) {
9176 // FIXME: this should verify that we are targetting a 486 or better. If not,
9177 // we will turn this bswap into something that will be lowered to logical ops
9178 // instead of emitting the bswap asm. For now, we don't support 486 or lower
9179 // so don't worry about this.
9181 // Verify this is a simple bswap.
9182 if (CI->getNumOperands() != 2 ||
9183 CI->getType() != CI->getOperand(1)->getType() ||
9184 !CI->getType()->isInteger())
9187 const IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
9188 if (!Ty || Ty->getBitWidth() % 16 != 0)
9191 // Okay, we can do this xform, do so now.
9192 const Type *Tys[] = { Ty };
9193 Module *M = CI->getParent()->getParent()->getParent();
9194 Constant *Int = Intrinsic::getDeclaration(M, Intrinsic::bswap, Tys, 1);
9196 Value *Op = CI->getOperand(1);
9197 Op = CallInst::Create(Int, Op, CI->getName(), CI);
9199 CI->replaceAllUsesWith(Op);
9200 CI->eraseFromParent();
9204 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
9205 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
9206 std::vector<InlineAsm::ConstraintInfo> Constraints = IA->ParseConstraints();
9208 std::string AsmStr = IA->getAsmString();
9210 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
9211 std::vector<std::string> AsmPieces;
9212 SplitString(AsmStr, AsmPieces, "\n"); // ; as separator?
9214 switch (AsmPieces.size()) {
9215 default: return false;
9217 AsmStr = AsmPieces[0];
9219 SplitString(AsmStr, AsmPieces, " \t"); // Split with whitespace.
9222 if (AsmPieces.size() == 2 &&
9223 (AsmPieces[0] == "bswap" ||
9224 AsmPieces[0] == "bswapq" ||
9225 AsmPieces[0] == "bswapl") &&
9226 (AsmPieces[1] == "$0" ||
9227 AsmPieces[1] == "${0:q}")) {
9228 // No need to check constraints, nothing other than the equivalent of
9229 // "=r,0" would be valid here.
9230 return LowerToBSwap(CI);
9232 // rorw $$8, ${0:w} --> llvm.bswap.i16
9233 if (CI->getType() == Type::getInt16Ty(CI->getContext()) &&
9234 AsmPieces.size() == 3 &&
9235 AsmPieces[0] == "rorw" &&
9236 AsmPieces[1] == "$$8," &&
9237 AsmPieces[2] == "${0:w}" &&
9238 IA->getConstraintString() == "=r,0,~{dirflag},~{fpsr},~{flags},~{cc}") {
9239 return LowerToBSwap(CI);
9243 if (CI->getType() == Type::getInt64Ty(CI->getContext()) &&
9244 Constraints.size() >= 2 &&
9245 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
9246 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
9247 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
9248 std::vector<std::string> Words;
9249 SplitString(AsmPieces[0], Words, " \t");
9250 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%eax") {
9252 SplitString(AsmPieces[1], Words, " \t");
9253 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%edx") {
9255 SplitString(AsmPieces[2], Words, " \t,");
9256 if (Words.size() == 3 && Words[0] == "xchgl" && Words[1] == "%eax" &&
9257 Words[2] == "%edx") {
9258 return LowerToBSwap(CI);
9270 /// getConstraintType - Given a constraint letter, return the type of
9271 /// constraint it is for this target.
9272 X86TargetLowering::ConstraintType
9273 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
9274 if (Constraint.size() == 1) {
9275 switch (Constraint[0]) {
9287 return C_RegisterClass;
9295 return TargetLowering::getConstraintType(Constraint);
9298 /// LowerXConstraint - try to replace an X constraint, which matches anything,
9299 /// with another that has more specific requirements based on the type of the
9300 /// corresponding operand.
9301 const char *X86TargetLowering::
9302 LowerXConstraint(EVT ConstraintVT) const {
9303 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
9304 // 'f' like normal targets.
9305 if (ConstraintVT.isFloatingPoint()) {
9306 if (Subtarget->hasSSE2())
9308 if (Subtarget->hasSSE1())
9312 return TargetLowering::LowerXConstraint(ConstraintVT);
9315 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
9316 /// vector. If it is invalid, don't add anything to Ops.
9317 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
9320 std::vector<SDValue>&Ops,
9321 SelectionDAG &DAG) const {
9322 SDValue Result(0, 0);
9324 switch (Constraint) {
9327 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
9328 if (C->getZExtValue() <= 31) {
9329 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
9335 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
9336 if (C->getZExtValue() <= 63) {
9337 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
9343 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
9344 if ((int8_t)C->getSExtValue() == C->getSExtValue()) {
9345 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
9351 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
9352 if (C->getZExtValue() <= 255) {
9353 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
9359 // 32-bit signed value
9360 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
9361 const ConstantInt *CI = C->getConstantIntValue();
9362 if (CI->isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
9363 C->getSExtValue())) {
9364 // Widen to 64 bits here to get it sign extended.
9365 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
9368 // FIXME gcc accepts some relocatable values here too, but only in certain
9369 // memory models; it's complicated.
9374 // 32-bit unsigned value
9375 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
9376 const ConstantInt *CI = C->getConstantIntValue();
9377 if (CI->isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
9378 C->getZExtValue())) {
9379 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
9383 // FIXME gcc accepts some relocatable values here too, but only in certain
9384 // memory models; it's complicated.
9388 // Literal immediates are always ok.
9389 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
9390 // Widen to 64 bits here to get it sign extended.
9391 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
9395 // If we are in non-pic codegen mode, we allow the address of a global (with
9396 // an optional displacement) to be used with 'i'.
9397 GlobalAddressSDNode *GA = 0;
9400 // Match either (GA), (GA+C), (GA+C1+C2), etc.
9402 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
9403 Offset += GA->getOffset();
9405 } else if (Op.getOpcode() == ISD::ADD) {
9406 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
9407 Offset += C->getZExtValue();
9408 Op = Op.getOperand(0);
9411 } else if (Op.getOpcode() == ISD::SUB) {
9412 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
9413 Offset += -C->getZExtValue();
9414 Op = Op.getOperand(0);
9419 // Otherwise, this isn't something we can handle, reject it.
9423 GlobalValue *GV = GA->getGlobal();
9424 // If we require an extra load to get this address, as in PIC mode, we
9426 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
9427 getTargetMachine())))
9431 Op = LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
9433 Op = DAG.getTargetGlobalAddress(GV, GA->getValueType(0), Offset);
9439 if (Result.getNode()) {
9440 Ops.push_back(Result);
9443 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, hasMemory,
9447 std::vector<unsigned> X86TargetLowering::
9448 getRegClassForInlineAsmConstraint(const std::string &Constraint,
9450 if (Constraint.size() == 1) {
9451 // FIXME: not handling fp-stack yet!
9452 switch (Constraint[0]) { // GCC X86 Constraint Letters
9453 default: break; // Unknown constraint letter
9454 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
9455 if (Subtarget->is64Bit()) {
9457 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX,
9458 X86::ESI, X86::EDI, X86::R8D, X86::R9D,
9459 X86::R10D,X86::R11D,X86::R12D,
9460 X86::R13D,X86::R14D,X86::R15D,
9461 X86::EBP, X86::ESP, 0);
9462 else if (VT == MVT::i16)
9463 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX,
9464 X86::SI, X86::DI, X86::R8W,X86::R9W,
9465 X86::R10W,X86::R11W,X86::R12W,
9466 X86::R13W,X86::R14W,X86::R15W,
9467 X86::BP, X86::SP, 0);
9468 else if (VT == MVT::i8)
9469 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL,
9470 X86::SIL, X86::DIL, X86::R8B,X86::R9B,
9471 X86::R10B,X86::R11B,X86::R12B,
9472 X86::R13B,X86::R14B,X86::R15B,
9473 X86::BPL, X86::SPL, 0);
9475 else if (VT == MVT::i64)
9476 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX,
9477 X86::RSI, X86::RDI, X86::R8, X86::R9,
9478 X86::R10, X86::R11, X86::R12,
9479 X86::R13, X86::R14, X86::R15,
9480 X86::RBP, X86::RSP, 0);
9484 // 32-bit fallthrough
9487 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0);
9488 else if (VT == MVT::i16)
9489 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0);
9490 else if (VT == MVT::i8)
9491 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 0);
9492 else if (VT == MVT::i64)
9493 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, 0);
9498 return std::vector<unsigned>();
9501 std::pair<unsigned, const TargetRegisterClass*>
9502 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
9504 // First, see if this is a constraint that directly corresponds to an LLVM
9506 if (Constraint.size() == 1) {
9507 // GCC Constraint Letters
9508 switch (Constraint[0]) {
9510 case 'r': // GENERAL_REGS
9511 case 'l': // INDEX_REGS
9513 return std::make_pair(0U, X86::GR8RegisterClass);
9515 return std::make_pair(0U, X86::GR16RegisterClass);
9516 if (VT == MVT::i32 || !Subtarget->is64Bit())
9517 return std::make_pair(0U, X86::GR32RegisterClass);
9518 return std::make_pair(0U, X86::GR64RegisterClass);
9519 case 'R': // LEGACY_REGS
9521 return std::make_pair(0U, X86::GR8_NOREXRegisterClass);
9523 return std::make_pair(0U, X86::GR16_NOREXRegisterClass);
9524 if (VT == MVT::i32 || !Subtarget->is64Bit())
9525 return std::make_pair(0U, X86::GR32_NOREXRegisterClass);
9526 return std::make_pair(0U, X86::GR64_NOREXRegisterClass);
9527 case 'f': // FP Stack registers.
9528 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
9529 // value to the correct fpstack register class.
9530 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
9531 return std::make_pair(0U, X86::RFP32RegisterClass);
9532 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
9533 return std::make_pair(0U, X86::RFP64RegisterClass);
9534 return std::make_pair(0U, X86::RFP80RegisterClass);
9535 case 'y': // MMX_REGS if MMX allowed.
9536 if (!Subtarget->hasMMX()) break;
9537 return std::make_pair(0U, X86::VR64RegisterClass);
9538 case 'Y': // SSE_REGS if SSE2 allowed
9539 if (!Subtarget->hasSSE2()) break;
9541 case 'x': // SSE_REGS if SSE1 allowed
9542 if (!Subtarget->hasSSE1()) break;
9544 switch (VT.getSimpleVT().SimpleTy) {
9546 // Scalar SSE types.
9549 return std::make_pair(0U, X86::FR32RegisterClass);
9552 return std::make_pair(0U, X86::FR64RegisterClass);
9560 return std::make_pair(0U, X86::VR128RegisterClass);
9566 // Use the default implementation in TargetLowering to convert the register
9567 // constraint into a member of a register class.
9568 std::pair<unsigned, const TargetRegisterClass*> Res;
9569 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
9571 // Not found as a standard register?
9572 if (Res.second == 0) {
9573 // Map st(0) -> st(7) -> ST0
9574 if (Constraint.size() == 7 && Constraint[0] == '{' &&
9575 tolower(Constraint[1]) == 's' &&
9576 tolower(Constraint[2]) == 't' &&
9577 Constraint[3] == '(' &&
9578 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
9579 Constraint[5] == ')' &&
9580 Constraint[6] == '}') {
9582 Res.first = X86::ST0+Constraint[4]-'0';
9583 Res.second = X86::RFP80RegisterClass;
9587 // GCC allows "st(0)" to be called just plain "st".
9588 if (StringsEqualNoCase("{st}", Constraint)) {
9589 Res.first = X86::ST0;
9590 Res.second = X86::RFP80RegisterClass;
9595 if (StringsEqualNoCase("{flags}", Constraint)) {
9596 Res.first = X86::EFLAGS;
9597 Res.second = X86::CCRRegisterClass;
9601 // 'A' means EAX + EDX.
9602 if (Constraint == "A") {
9603 Res.first = X86::EAX;
9604 Res.second = X86::GR32_ADRegisterClass;
9610 // Otherwise, check to see if this is a register class of the wrong value
9611 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
9612 // turn into {ax},{dx}.
9613 if (Res.second->hasType(VT))
9614 return Res; // Correct type already, nothing to do.
9616 // All of the single-register GCC register classes map their values onto
9617 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
9618 // really want an 8-bit or 32-bit register, map to the appropriate register
9619 // class and return the appropriate register.
9620 if (Res.second == X86::GR16RegisterClass) {
9621 if (VT == MVT::i8) {
9622 unsigned DestReg = 0;
9623 switch (Res.first) {
9625 case X86::AX: DestReg = X86::AL; break;
9626 case X86::DX: DestReg = X86::DL; break;
9627 case X86::CX: DestReg = X86::CL; break;
9628 case X86::BX: DestReg = X86::BL; break;
9631 Res.first = DestReg;
9632 Res.second = X86::GR8RegisterClass;
9634 } else if (VT == MVT::i32) {
9635 unsigned DestReg = 0;
9636 switch (Res.first) {
9638 case X86::AX: DestReg = X86::EAX; break;
9639 case X86::DX: DestReg = X86::EDX; break;
9640 case X86::CX: DestReg = X86::ECX; break;
9641 case X86::BX: DestReg = X86::EBX; break;
9642 case X86::SI: DestReg = X86::ESI; break;
9643 case X86::DI: DestReg = X86::EDI; break;
9644 case X86::BP: DestReg = X86::EBP; break;
9645 case X86::SP: DestReg = X86::ESP; break;
9648 Res.first = DestReg;
9649 Res.second = X86::GR32RegisterClass;
9651 } else if (VT == MVT::i64) {
9652 unsigned DestReg = 0;
9653 switch (Res.first) {
9655 case X86::AX: DestReg = X86::RAX; break;
9656 case X86::DX: DestReg = X86::RDX; break;
9657 case X86::CX: DestReg = X86::RCX; break;
9658 case X86::BX: DestReg = X86::RBX; break;
9659 case X86::SI: DestReg = X86::RSI; break;
9660 case X86::DI: DestReg = X86::RDI; break;
9661 case X86::BP: DestReg = X86::RBP; break;
9662 case X86::SP: DestReg = X86::RSP; break;
9665 Res.first = DestReg;
9666 Res.second = X86::GR64RegisterClass;
9669 } else if (Res.second == X86::FR32RegisterClass ||
9670 Res.second == X86::FR64RegisterClass ||
9671 Res.second == X86::VR128RegisterClass) {
9672 // Handle references to XMM physical registers that got mapped into the
9673 // wrong class. This can happen with constraints like {xmm0} where the
9674 // target independent register mapper will just pick the first match it can
9675 // find, ignoring the required type.
9677 Res.second = X86::FR32RegisterClass;
9678 else if (VT == MVT::f64)
9679 Res.second = X86::FR64RegisterClass;
9680 else if (X86::VR128RegisterClass->hasType(VT))
9681 Res.second = X86::VR128RegisterClass;
9687 //===----------------------------------------------------------------------===//
9688 // X86 Widen vector type
9689 //===----------------------------------------------------------------------===//
9691 /// getWidenVectorType: given a vector type, returns the type to widen
9692 /// to (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself.
9693 /// If there is no vector type that we want to widen to, returns MVT::Other
9694 /// When and where to widen is target dependent based on the cost of
9695 /// scalarizing vs using the wider vector type.
9697 EVT X86TargetLowering::getWidenVectorType(EVT VT) const {
9698 assert(VT.isVector());
9699 if (isTypeLegal(VT))
9702 // TODO: In computeRegisterProperty, we can compute the list of legal vector
9703 // type based on element type. This would speed up our search (though
9704 // it may not be worth it since the size of the list is relatively
9706 EVT EltVT = VT.getVectorElementType();
9707 unsigned NElts = VT.getVectorNumElements();
9709 // On X86, it make sense to widen any vector wider than 1
9713 for (unsigned nVT = MVT::FIRST_VECTOR_VALUETYPE;
9714 nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
9715 EVT SVT = (MVT::SimpleValueType)nVT;
9717 if (isTypeLegal(SVT) &&
9718 SVT.getVectorElementType() == EltVT &&
9719 SVT.getVectorNumElements() > NElts)