1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
16 #include "X86InstrBuilder.h"
17 #include "X86ISelLowering.h"
18 #include "X86MachineFunctionInfo.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/CallingConv.h"
21 #include "llvm/Constants.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/Function.h"
24 #include "llvm/Intrinsics.h"
25 #include "llvm/ADT/VectorExtras.h"
26 #include "llvm/Analysis/ScalarEvolutionExpressions.h"
27 #include "llvm/CodeGen/CallingConvLower.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/SelectionDAG.h"
32 #include "llvm/CodeGen/SSARegMap.h"
33 #include "llvm/Support/MathExtras.h"
34 #include "llvm/Target/TargetOptions.h"
35 #include "llvm/ADT/StringExtras.h"
38 X86TargetLowering::X86TargetLowering(TargetMachine &TM)
39 : TargetLowering(TM) {
40 Subtarget = &TM.getSubtarget<X86Subtarget>();
41 X86ScalarSSE = Subtarget->hasSSE2();
42 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
44 // Set up the TargetLowering object.
46 // X86 is weird, it always uses i8 for shift amounts and setcc results.
47 setShiftAmountType(MVT::i8);
48 setSetCCResultType(MVT::i8);
49 setSetCCResultContents(ZeroOrOneSetCCResult);
50 setSchedulingPreference(SchedulingForRegPressure);
51 setShiftAmountFlavor(Mask); // shl X, 32 == shl X, 0
52 setStackPointerRegisterToSaveRestore(X86StackPtr);
54 if (Subtarget->isTargetDarwin()) {
55 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
56 setUseUnderscoreSetJmp(false);
57 setUseUnderscoreLongJmp(false);
58 } else if (Subtarget->isTargetMingw()) {
59 // MS runtime is weird: it exports _setjmp, but longjmp!
60 setUseUnderscoreSetJmp(true);
61 setUseUnderscoreLongJmp(false);
63 setUseUnderscoreSetJmp(true);
64 setUseUnderscoreLongJmp(true);
67 // Set up the register classes.
68 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
69 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
70 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
71 if (Subtarget->is64Bit())
72 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
74 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Expand);
76 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
78 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
79 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
80 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
82 if (Subtarget->is64Bit()) {
83 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand);
84 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
87 // If SSE i64 SINT_TO_FP is not available, expand i32 UINT_TO_FP.
88 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Expand);
90 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
93 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
95 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
96 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
97 // SSE has no i16 to fp conversion, only i32
99 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
101 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
102 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
105 if (!Subtarget->is64Bit()) {
106 // Custom lower SINT_TO_FP and FP_TO_SINT from/to i64 in 32-bit mode.
107 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
108 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
111 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
113 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
114 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
117 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
119 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
120 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
123 // Handle FP_TO_UINT by promoting the destination to a larger signed
125 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
126 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
127 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
129 if (Subtarget->is64Bit()) {
130 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
131 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
133 if (X86ScalarSSE && !Subtarget->hasSSE3())
134 // Expand FP_TO_UINT into a select.
135 // FIXME: We would like to use a Custom expander here eventually to do
136 // the optimal thing for SSE vs. the default expansion in the legalizer.
137 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
139 // With SSE3 we can use fisttpll to convert to a signed i64.
140 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
143 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
145 setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand);
146 setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand);
149 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
150 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
151 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
152 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
153 setOperationAction(ISD::MEMMOVE , MVT::Other, Expand);
154 if (Subtarget->is64Bit())
155 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Expand);
156 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Expand);
157 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
158 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
159 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
160 setOperationAction(ISD::FREM , MVT::f64 , Expand);
162 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
163 setOperationAction(ISD::CTTZ , MVT::i8 , Expand);
164 setOperationAction(ISD::CTLZ , MVT::i8 , Expand);
165 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
166 setOperationAction(ISD::CTTZ , MVT::i16 , Expand);
167 setOperationAction(ISD::CTLZ , MVT::i16 , Expand);
168 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
169 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
170 setOperationAction(ISD::CTLZ , MVT::i32 , Expand);
171 if (Subtarget->is64Bit()) {
172 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
173 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
174 setOperationAction(ISD::CTLZ , MVT::i64 , Expand);
177 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
178 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
180 // These should be promoted to a larger select which is supported.
181 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
182 setOperationAction(ISD::SELECT , MVT::i8 , Promote);
183 // X86 wants to expand cmov itself.
184 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
185 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
186 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
187 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
188 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
189 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
190 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
191 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
192 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
193 if (Subtarget->is64Bit()) {
194 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
195 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
197 // X86 ret instruction may pop stack.
198 setOperationAction(ISD::RET , MVT::Other, Custom);
200 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
201 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
202 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
203 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
204 if (Subtarget->is64Bit()) {
205 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
206 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
207 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
208 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
210 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
211 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
212 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
213 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
214 // X86 wants to expand memset / memcpy itself.
215 setOperationAction(ISD::MEMSET , MVT::Other, Custom);
216 setOperationAction(ISD::MEMCPY , MVT::Other, Custom);
218 // We don't have line number support yet.
219 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
220 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
221 // FIXME - use subtarget debug flags
222 if (!Subtarget->isTargetDarwin() &&
223 !Subtarget->isTargetELF() &&
224 !Subtarget->isTargetCygMing())
225 setOperationAction(ISD::LABEL, MVT::Other, Expand);
227 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
228 setOperationAction(ISD::VASTART , MVT::Other, Custom);
229 setOperationAction(ISD::VAARG , MVT::Other, Expand);
230 setOperationAction(ISD::VAEND , MVT::Other, Expand);
231 if (Subtarget->is64Bit())
232 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
234 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
236 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
237 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
238 if (Subtarget->is64Bit())
239 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
240 if (Subtarget->isTargetCygMing())
241 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
243 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
246 // Set up the FP register classes.
247 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
248 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
250 // Use ANDPD to simulate FABS.
251 setOperationAction(ISD::FABS , MVT::f64, Custom);
252 setOperationAction(ISD::FABS , MVT::f32, Custom);
254 // Use XORP to simulate FNEG.
255 setOperationAction(ISD::FNEG , MVT::f64, Custom);
256 setOperationAction(ISD::FNEG , MVT::f32, Custom);
258 // Use ANDPD and ORPD to simulate FCOPYSIGN.
259 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
260 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
262 // We don't support sin/cos/fmod
263 setOperationAction(ISD::FSIN , MVT::f64, Expand);
264 setOperationAction(ISD::FCOS , MVT::f64, Expand);
265 setOperationAction(ISD::FREM , MVT::f64, Expand);
266 setOperationAction(ISD::FSIN , MVT::f32, Expand);
267 setOperationAction(ISD::FCOS , MVT::f32, Expand);
268 setOperationAction(ISD::FREM , MVT::f32, Expand);
270 // Expand FP immediates into loads from the stack, except for the special
272 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
273 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
274 addLegalFPImmediate(+0.0); // xorps / xorpd
276 // Set up the FP register classes.
277 addRegisterClass(MVT::f64, X86::RFPRegisterClass);
279 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
280 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
281 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
284 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
285 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
288 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
289 addLegalFPImmediate(+0.0); // FLD0
290 addLegalFPImmediate(+1.0); // FLD1
291 addLegalFPImmediate(-0.0); // FLD0/FCHS
292 addLegalFPImmediate(-1.0); // FLD1/FCHS
295 // First set operation action for all vector types to expand. Then we
296 // will selectively turn on ones that can be effectively codegen'd.
297 for (unsigned VT = (unsigned)MVT::Vector + 1;
298 VT != (unsigned)MVT::LAST_VALUETYPE; VT++) {
299 setOperationAction(ISD::ADD , (MVT::ValueType)VT, Expand);
300 setOperationAction(ISD::SUB , (MVT::ValueType)VT, Expand);
301 setOperationAction(ISD::FADD, (MVT::ValueType)VT, Expand);
302 setOperationAction(ISD::FSUB, (MVT::ValueType)VT, Expand);
303 setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand);
304 setOperationAction(ISD::FMUL, (MVT::ValueType)VT, Expand);
305 setOperationAction(ISD::SDIV, (MVT::ValueType)VT, Expand);
306 setOperationAction(ISD::UDIV, (MVT::ValueType)VT, Expand);
307 setOperationAction(ISD::FDIV, (MVT::ValueType)VT, Expand);
308 setOperationAction(ISD::SREM, (MVT::ValueType)VT, Expand);
309 setOperationAction(ISD::UREM, (MVT::ValueType)VT, Expand);
310 setOperationAction(ISD::LOAD, (MVT::ValueType)VT, Expand);
311 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Expand);
312 setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
313 setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
316 if (Subtarget->hasMMX()) {
317 addRegisterClass(MVT::v8i8, X86::VR64RegisterClass);
318 addRegisterClass(MVT::v4i16, X86::VR64RegisterClass);
319 addRegisterClass(MVT::v2i32, X86::VR64RegisterClass);
320 addRegisterClass(MVT::v1i64, X86::VR64RegisterClass);
322 // FIXME: add MMX packed arithmetics
324 setOperationAction(ISD::ADD, MVT::v8i8, Legal);
325 setOperationAction(ISD::ADD, MVT::v4i16, Legal);
326 setOperationAction(ISD::ADD, MVT::v2i32, Legal);
327 setOperationAction(ISD::ADD, MVT::v1i64, Legal);
329 setOperationAction(ISD::SUB, MVT::v8i8, Legal);
330 setOperationAction(ISD::SUB, MVT::v4i16, Legal);
331 setOperationAction(ISD::SUB, MVT::v2i32, Legal);
333 setOperationAction(ISD::MULHS, MVT::v4i16, Legal);
334 setOperationAction(ISD::MUL, MVT::v4i16, Legal);
336 setOperationAction(ISD::AND, MVT::v8i8, Promote);
337 AddPromotedToType (ISD::AND, MVT::v8i8, MVT::v1i64);
338 setOperationAction(ISD::AND, MVT::v4i16, Promote);
339 AddPromotedToType (ISD::AND, MVT::v4i16, MVT::v1i64);
340 setOperationAction(ISD::AND, MVT::v2i32, Promote);
341 AddPromotedToType (ISD::AND, MVT::v2i32, MVT::v1i64);
342 setOperationAction(ISD::AND, MVT::v1i64, Legal);
344 setOperationAction(ISD::OR, MVT::v8i8, Promote);
345 AddPromotedToType (ISD::OR, MVT::v8i8, MVT::v1i64);
346 setOperationAction(ISD::OR, MVT::v4i16, Promote);
347 AddPromotedToType (ISD::OR, MVT::v4i16, MVT::v1i64);
348 setOperationAction(ISD::OR, MVT::v2i32, Promote);
349 AddPromotedToType (ISD::OR, MVT::v2i32, MVT::v1i64);
350 setOperationAction(ISD::OR, MVT::v1i64, Legal);
352 setOperationAction(ISD::XOR, MVT::v8i8, Promote);
353 AddPromotedToType (ISD::XOR, MVT::v8i8, MVT::v1i64);
354 setOperationAction(ISD::XOR, MVT::v4i16, Promote);
355 AddPromotedToType (ISD::XOR, MVT::v4i16, MVT::v1i64);
356 setOperationAction(ISD::XOR, MVT::v2i32, Promote);
357 AddPromotedToType (ISD::XOR, MVT::v2i32, MVT::v1i64);
358 setOperationAction(ISD::XOR, MVT::v1i64, Legal);
360 setOperationAction(ISD::LOAD, MVT::v8i8, Promote);
361 AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v1i64);
362 setOperationAction(ISD::LOAD, MVT::v4i16, Promote);
363 AddPromotedToType (ISD::LOAD, MVT::v4i16, MVT::v1i64);
364 setOperationAction(ISD::LOAD, MVT::v2i32, Promote);
365 AddPromotedToType (ISD::LOAD, MVT::v2i32, MVT::v1i64);
366 setOperationAction(ISD::LOAD, MVT::v1i64, Legal);
368 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Custom);
369 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom);
370 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Custom);
371 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i64, Custom);
373 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom);
374 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
375 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i32, Custom);
376 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v1i64, Custom);
378 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Custom);
379 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Custom);
382 if (Subtarget->hasSSE1()) {
383 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
385 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
386 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
387 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
388 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
389 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
390 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
391 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
392 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
393 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
396 if (Subtarget->hasSSE2()) {
397 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
398 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
399 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
400 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
401 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
403 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
404 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
405 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
406 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
407 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
408 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
409 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
410 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
411 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
412 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
413 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
414 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
415 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
417 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
418 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
419 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
420 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
421 // Implement v4f32 insert_vector_elt in terms of SSE2 v8i16 ones.
422 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
424 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
425 for (unsigned VT = (unsigned)MVT::v16i8; VT != (unsigned)MVT::v2i64; VT++) {
426 setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Custom);
427 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Custom);
428 setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Custom);
430 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
431 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
432 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
433 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
434 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
435 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
437 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
438 for (unsigned VT = (unsigned)MVT::v16i8; VT != (unsigned)MVT::v2i64; VT++) {
439 setOperationAction(ISD::AND, (MVT::ValueType)VT, Promote);
440 AddPromotedToType (ISD::AND, (MVT::ValueType)VT, MVT::v2i64);
441 setOperationAction(ISD::OR, (MVT::ValueType)VT, Promote);
442 AddPromotedToType (ISD::OR, (MVT::ValueType)VT, MVT::v2i64);
443 setOperationAction(ISD::XOR, (MVT::ValueType)VT, Promote);
444 AddPromotedToType (ISD::XOR, (MVT::ValueType)VT, MVT::v2i64);
445 setOperationAction(ISD::LOAD, (MVT::ValueType)VT, Promote);
446 AddPromotedToType (ISD::LOAD, (MVT::ValueType)VT, MVT::v2i64);
447 setOperationAction(ISD::SELECT, (MVT::ValueType)VT, Promote);
448 AddPromotedToType (ISD::SELECT, (MVT::ValueType)VT, MVT::v2i64);
451 // Custom lower v2i64 and v2f64 selects.
452 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
453 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
454 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
455 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
458 // We want to custom lower some of our intrinsics.
459 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
461 // We have target-specific dag combine patterns for the following nodes:
462 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
463 setTargetDAGCombine(ISD::SELECT);
465 computeRegisterProperties();
467 // FIXME: These should be based on subtarget info. Plus, the values should
468 // be smaller when we are in optimizing for size mode.
469 maxStoresPerMemset = 16; // For %llvm.memset -> sequence of stores
470 maxStoresPerMemcpy = 16; // For %llvm.memcpy -> sequence of stores
471 maxStoresPerMemmove = 16; // For %llvm.memmove -> sequence of stores
472 allowUnalignedMemoryAccesses = true; // x86 supports it!
476 //===----------------------------------------------------------------------===//
477 // Return Value Calling Convention Implementation
478 //===----------------------------------------------------------------------===//
480 #include "X86GenCallingConv.inc"
482 /// LowerRET - Lower an ISD::RET node.
483 SDOperand X86TargetLowering::LowerRET(SDOperand Op, SelectionDAG &DAG) {
484 assert((Op.getNumOperands() & 1) == 1 && "ISD::RET should have odd # args");
486 SmallVector<CCValAssign, 16> RVLocs;
487 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
488 CCState CCInfo(CC, getTargetMachine(), RVLocs);
489 CCInfo.AnalyzeReturn(Op.Val, RetCC_X86);
492 // If this is the first return lowered for this function, add the regs to the
493 // liveout set for the function.
494 if (DAG.getMachineFunction().liveout_empty()) {
495 for (unsigned i = 0; i != RVLocs.size(); ++i)
496 if (RVLocs[i].isRegLoc())
497 DAG.getMachineFunction().addLiveOut(RVLocs[i].getLocReg());
500 SDOperand Chain = Op.getOperand(0);
503 // Copy the result values into the output registers.
504 if (RVLocs.size() != 1 || !RVLocs[0].isRegLoc() ||
505 RVLocs[0].getLocReg() != X86::ST0) {
506 for (unsigned i = 0; i != RVLocs.size(); ++i) {
507 CCValAssign &VA = RVLocs[i];
508 assert(VA.isRegLoc() && "Can only return in registers!");
509 Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), Op.getOperand(i*2+1),
511 Flag = Chain.getValue(1);
514 // We need to handle a destination of ST0 specially, because it isn't really
516 SDOperand Value = Op.getOperand(1);
518 // If this is an FP return with ScalarSSE, we need to move the value from
519 // an XMM register onto the fp-stack.
523 // If this is a load into a scalarsse value, don't store the loaded value
524 // back to the stack, only to reload it: just replace the scalar-sse load.
525 if (ISD::isNON_EXTLoad(Value.Val) &&
526 (Chain == Value.getValue(1) || Chain == Value.getOperand(0))) {
527 Chain = Value.getOperand(0);
528 MemLoc = Value.getOperand(1);
530 // Spill the value to memory and reload it into top of stack.
531 unsigned Size = MVT::getSizeInBits(RVLocs[0].getValVT())/8;
532 MachineFunction &MF = DAG.getMachineFunction();
533 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
534 MemLoc = DAG.getFrameIndex(SSFI, getPointerTy());
535 Chain = DAG.getStore(Op.getOperand(0), Value, MemLoc, NULL, 0);
537 SDVTList Tys = DAG.getVTList(MVT::f64, MVT::Other);
538 SDOperand Ops[] = {Chain, MemLoc, DAG.getValueType(RVLocs[0].getValVT())};
539 Value = DAG.getNode(X86ISD::FLD, Tys, Ops, 3);
540 Chain = Value.getValue(1);
543 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
544 SDOperand Ops[] = { Chain, Value };
545 Chain = DAG.getNode(X86ISD::FP_SET_RESULT, Tys, Ops, 2);
546 Flag = Chain.getValue(1);
549 SDOperand BytesToPop = DAG.getConstant(getBytesToPopOnReturn(), MVT::i16);
551 return DAG.getNode(X86ISD::RET_FLAG, MVT::Other, Chain, BytesToPop, Flag);
553 return DAG.getNode(X86ISD::RET_FLAG, MVT::Other, Chain, BytesToPop);
557 /// LowerCallResult - Lower the result values of an ISD::CALL into the
558 /// appropriate copies out of appropriate physical registers. This assumes that
559 /// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
560 /// being lowered. The returns a SDNode with the same number of values as the
562 SDNode *X86TargetLowering::
563 LowerCallResult(SDOperand Chain, SDOperand InFlag, SDNode *TheCall,
564 unsigned CallingConv, SelectionDAG &DAG) {
566 // Assign locations to each value returned by this call.
567 SmallVector<CCValAssign, 16> RVLocs;
568 CCState CCInfo(CallingConv, getTargetMachine(), RVLocs);
569 CCInfo.AnalyzeCallResult(TheCall, RetCC_X86);
572 SmallVector<SDOperand, 8> ResultVals;
574 // Copy all of the result registers out of their specified physreg.
575 if (RVLocs.size() != 1 || RVLocs[0].getLocReg() != X86::ST0) {
576 for (unsigned i = 0; i != RVLocs.size(); ++i) {
577 Chain = DAG.getCopyFromReg(Chain, RVLocs[i].getLocReg(),
578 RVLocs[i].getValVT(), InFlag).getValue(1);
579 InFlag = Chain.getValue(2);
580 ResultVals.push_back(Chain.getValue(0));
583 // Copies from the FP stack are special, as ST0 isn't a valid register
584 // before the fp stackifier runs.
586 // Copy ST0 into an RFP register with FP_GET_RESULT.
587 SDVTList Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag);
588 SDOperand GROps[] = { Chain, InFlag };
589 SDOperand RetVal = DAG.getNode(X86ISD::FP_GET_RESULT, Tys, GROps, 2);
590 Chain = RetVal.getValue(1);
591 InFlag = RetVal.getValue(2);
593 // If we are using ScalarSSE, store ST(0) to the stack and reload it into
596 // FIXME: Currently the FST is flagged to the FP_GET_RESULT. This
597 // shouldn't be necessary except that RFP cannot be live across
598 // multiple blocks. When stackifier is fixed, they can be uncoupled.
599 MachineFunction &MF = DAG.getMachineFunction();
600 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
601 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
603 Chain, RetVal, StackSlot, DAG.getValueType(RVLocs[0].getValVT()), InFlag
605 Chain = DAG.getNode(X86ISD::FST, MVT::Other, Ops, 5);
606 RetVal = DAG.getLoad(RVLocs[0].getValVT(), Chain, StackSlot, NULL, 0);
607 Chain = RetVal.getValue(1);
610 if (RVLocs[0].getValVT() == MVT::f32 && !X86ScalarSSE)
611 // FIXME: we would really like to remember that this FP_ROUND
612 // operation is okay to eliminate if we allow excess FP precision.
613 RetVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, RetVal);
614 ResultVals.push_back(RetVal);
617 // Merge everything together with a MERGE_VALUES node.
618 ResultVals.push_back(Chain);
619 return DAG.getNode(ISD::MERGE_VALUES, TheCall->getVTList(),
620 &ResultVals[0], ResultVals.size()).Val;
624 //===----------------------------------------------------------------------===//
625 // C & StdCall Calling Convention implementation
626 //===----------------------------------------------------------------------===//
627 // StdCall calling convention seems to be standard for many Windows' API
628 // routines and around. It differs from C calling convention just a little:
629 // callee should clean up the stack, not caller. Symbols should be also
630 // decorated in some fancy way :) It doesn't support any vector arguments.
632 /// AddLiveIn - This helper function adds the specified physical register to the
633 /// MachineFunction as a live in value. It also creates a corresponding virtual
635 static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
636 const TargetRegisterClass *RC) {
637 assert(RC->contains(PReg) && "Not the correct regclass!");
638 unsigned VReg = MF.getSSARegMap()->createVirtualRegister(RC);
639 MF.addLiveIn(PReg, VReg);
643 SDOperand X86TargetLowering::LowerCCCArguments(SDOperand Op, SelectionDAG &DAG,
645 unsigned NumArgs = Op.Val->getNumValues() - 1;
646 MachineFunction &MF = DAG.getMachineFunction();
647 MachineFrameInfo *MFI = MF.getFrameInfo();
648 SDOperand Root = Op.getOperand(0);
649 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
651 // Assign locations to all of the incoming arguments.
652 SmallVector<CCValAssign, 16> ArgLocs;
653 CCState CCInfo(MF.getFunction()->getCallingConv(), getTargetMachine(),
655 CCInfo.AnalyzeFormalArguments(Op.Val, CC_X86_32_C);
657 SmallVector<SDOperand, 8> ArgValues;
658 unsigned LastVal = ~0U;
659 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
660 CCValAssign &VA = ArgLocs[i];
661 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
663 assert(VA.getValNo() != LastVal &&
664 "Don't support value assigned to multiple locs yet");
665 LastVal = VA.getValNo();
668 MVT::ValueType RegVT = VA.getLocVT();
669 TargetRegisterClass *RC;
670 if (RegVT == MVT::i32)
671 RC = X86::GR32RegisterClass;
673 assert(MVT::isVector(RegVT));
674 RC = X86::VR128RegisterClass;
677 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
678 SDOperand ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT);
680 // If this is an 8 or 16-bit value, it is really passed promoted to 32
681 // bits. Insert an assert[sz]ext to capture this, then truncate to the
683 if (VA.getLocInfo() == CCValAssign::SExt)
684 ArgValue = DAG.getNode(ISD::AssertSext, RegVT, ArgValue,
685 DAG.getValueType(VA.getValVT()));
686 else if (VA.getLocInfo() == CCValAssign::ZExt)
687 ArgValue = DAG.getNode(ISD::AssertZext, RegVT, ArgValue,
688 DAG.getValueType(VA.getValVT()));
690 if (VA.getLocInfo() != CCValAssign::Full)
691 ArgValue = DAG.getNode(ISD::TRUNCATE, VA.getValVT(), ArgValue);
693 ArgValues.push_back(ArgValue);
695 assert(VA.isMemLoc());
697 // Create the nodes corresponding to a load from this parameter slot.
698 int FI = MFI->CreateFixedObject(MVT::getSizeInBits(VA.getValVT())/8,
699 VA.getLocMemOffset());
700 SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy());
701 ArgValues.push_back(DAG.getLoad(VA.getValVT(), Root, FIN, NULL, 0));
705 unsigned StackSize = CCInfo.getNextStackOffset();
707 ArgValues.push_back(Root);
709 // If the function takes variable number of arguments, make a frame index for
710 // the start of the first vararg value... for expansion of llvm.va_start.
712 VarArgsFrameIndex = MFI->CreateFixedObject(1, StackSize);
714 if (isStdCall && !isVarArg) {
715 BytesToPopOnReturn = StackSize; // Callee pops everything..
716 BytesCallerReserves = 0;
718 BytesToPopOnReturn = 0; // Callee pops nothing.
720 // If this is an sret function, the return should pop the hidden pointer.
722 (cast<ConstantSDNode>(Op.getOperand(3))->getValue() &
723 ISD::ParamFlags::StructReturn))
724 BytesToPopOnReturn = 4;
726 BytesCallerReserves = StackSize;
729 RegSaveFrameIndex = 0xAAAAAAA; // X86-64 only.
730 ReturnAddrIndex = 0; // No return address slot generated yet.
732 MF.getInfo<X86MachineFunctionInfo>()
733 ->setBytesToPopOnReturn(BytesToPopOnReturn);
735 // Return the new list of results.
736 return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(),
737 &ArgValues[0], ArgValues.size()).getValue(Op.ResNo);
740 SDOperand X86TargetLowering::LowerCCCCallTo(SDOperand Op, SelectionDAG &DAG,
742 SDOperand Chain = Op.getOperand(0);
743 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
744 bool isTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0;
745 SDOperand Callee = Op.getOperand(4);
746 unsigned NumOps = (Op.getNumOperands() - 5) / 2;
748 // Analyze operands of the call, assigning locations to each operand.
749 SmallVector<CCValAssign, 16> ArgLocs;
750 CCState CCInfo(CC, getTargetMachine(), ArgLocs);
751 CCInfo.AnalyzeCallOperands(Op.Val, CC_X86_32_C);
753 // Get a count of how many bytes are to be pushed on the stack.
754 unsigned NumBytes = CCInfo.getNextStackOffset();
756 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes, getPointerTy()));
758 SmallVector<std::pair<unsigned, SDOperand>, 8> RegsToPass;
759 SmallVector<SDOperand, 8> MemOpChains;
763 // Walk the register/memloc assignments, inserting copies/loads.
764 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
765 CCValAssign &VA = ArgLocs[i];
766 SDOperand Arg = Op.getOperand(5+2*VA.getValNo());
768 // Promote the value if needed.
769 switch (VA.getLocInfo()) {
770 default: assert(0 && "Unknown loc info!");
771 case CCValAssign::Full: break;
772 case CCValAssign::SExt:
773 Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg);
775 case CCValAssign::ZExt:
776 Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg);
778 case CCValAssign::AExt:
779 Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg);
784 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
786 assert(VA.isMemLoc());
787 if (StackPtr.Val == 0)
788 StackPtr = DAG.getRegister(getStackPtrReg(), getPointerTy());
789 SDOperand PtrOff = DAG.getConstant(VA.getLocMemOffset(), getPointerTy());
790 PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
791 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
795 // If the first argument is an sret pointer, remember it.
796 bool isSRet = NumOps &&
797 (cast<ConstantSDNode>(Op.getOperand(6))->getValue() &
798 ISD::ParamFlags::StructReturn);
800 if (!MemOpChains.empty())
801 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
802 &MemOpChains[0], MemOpChains.size());
804 // Build a sequence of copy-to-reg nodes chained together with token chain
805 // and flag operands which copy the outgoing args into registers.
807 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
808 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
810 InFlag = Chain.getValue(1);
813 // ELF / PIC requires GOT in the EBX register before function calls via PLT
815 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
816 Subtarget->isPICStyleGOT()) {
817 Chain = DAG.getCopyToReg(Chain, X86::EBX,
818 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
820 InFlag = Chain.getValue(1);
823 // If the callee is a GlobalAddress node (quite common, every direct call is)
824 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
825 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
826 // We should use extra load for direct calls to dllimported functions in
828 if (!Subtarget->GVRequiresExtraLoad(G->getGlobal(),
829 getTargetMachine(), true))
830 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
831 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
832 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
834 // Returns a chain & a flag for retval copy to use.
835 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
836 SmallVector<SDOperand, 8> Ops;
837 Ops.push_back(Chain);
838 Ops.push_back(Callee);
840 // Add argument registers to the end of the list so that they are known live
842 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
843 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
844 RegsToPass[i].second.getValueType()));
846 // Add an implicit use GOT pointer in EBX.
847 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
848 Subtarget->isPICStyleGOT())
849 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
852 Ops.push_back(InFlag);
854 Chain = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL,
855 NodeTys, &Ops[0], Ops.size());
856 InFlag = Chain.getValue(1);
858 // Create the CALLSEQ_END node.
859 unsigned NumBytesForCalleeToPush = 0;
861 if (CC == CallingConv::X86_StdCall) {
863 NumBytesForCalleeToPush = isSRet ? 4 : 0;
865 NumBytesForCalleeToPush = NumBytes;
867 // If this is is a call to a struct-return function, the callee
868 // pops the hidden struct pointer, so we have to push it back.
869 // This is common for Darwin/X86, Linux & Mingw32 targets.
870 NumBytesForCalleeToPush = isSRet ? 4 : 0;
873 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
875 Ops.push_back(Chain);
876 Ops.push_back(DAG.getConstant(NumBytes, getPointerTy()));
877 Ops.push_back(DAG.getConstant(NumBytesForCalleeToPush, getPointerTy()));
878 Ops.push_back(InFlag);
879 Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0], Ops.size());
880 InFlag = Chain.getValue(1);
882 // Handle result values, copying them out of physregs into vregs that we
884 return SDOperand(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG), Op.ResNo);
888 //===----------------------------------------------------------------------===//
889 // FastCall Calling Convention implementation
890 //===----------------------------------------------------------------------===//
892 // The X86 'fastcall' calling convention passes up to two integer arguments in
893 // registers (an appropriate portion of ECX/EDX), passes arguments in C order,
894 // and requires that the callee pop its arguments off the stack (allowing proper
895 // tail calls), and has the same return value conventions as C calling convs.
897 // This calling convention always arranges for the callee pop value to be 8n+4
898 // bytes, which is needed for tail recursion elimination and stack alignment
901 X86TargetLowering::LowerFastCCArguments(SDOperand Op, SelectionDAG &DAG) {
902 MachineFunction &MF = DAG.getMachineFunction();
903 MachineFrameInfo *MFI = MF.getFrameInfo();
904 SDOperand Root = Op.getOperand(0);
906 // Assign locations to all of the incoming arguments.
907 SmallVector<CCValAssign, 16> ArgLocs;
908 CCState CCInfo(MF.getFunction()->getCallingConv(), getTargetMachine(),
910 CCInfo.AnalyzeFormalArguments(Op.Val, CC_X86_32_FastCall);
912 SmallVector<SDOperand, 8> ArgValues;
913 unsigned LastVal = ~0U;
914 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
915 CCValAssign &VA = ArgLocs[i];
916 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
918 assert(VA.getValNo() != LastVal &&
919 "Don't support value assigned to multiple locs yet");
920 LastVal = VA.getValNo();
923 MVT::ValueType RegVT = VA.getLocVT();
924 TargetRegisterClass *RC;
925 if (RegVT == MVT::i32)
926 RC = X86::GR32RegisterClass;
928 assert(MVT::isVector(RegVT));
929 RC = X86::VR128RegisterClass;
932 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
933 SDOperand ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT);
935 // If this is an 8 or 16-bit value, it is really passed promoted to 32
936 // bits. Insert an assert[sz]ext to capture this, then truncate to the
938 if (VA.getLocInfo() == CCValAssign::SExt)
939 ArgValue = DAG.getNode(ISD::AssertSext, RegVT, ArgValue,
940 DAG.getValueType(VA.getValVT()));
941 else if (VA.getLocInfo() == CCValAssign::ZExt)
942 ArgValue = DAG.getNode(ISD::AssertZext, RegVT, ArgValue,
943 DAG.getValueType(VA.getValVT()));
945 if (VA.getLocInfo() != CCValAssign::Full)
946 ArgValue = DAG.getNode(ISD::TRUNCATE, VA.getValVT(), ArgValue);
948 ArgValues.push_back(ArgValue);
950 assert(VA.isMemLoc());
952 // Create the nodes corresponding to a load from this parameter slot.
953 int FI = MFI->CreateFixedObject(MVT::getSizeInBits(VA.getValVT())/8,
954 VA.getLocMemOffset());
955 SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy());
956 ArgValues.push_back(DAG.getLoad(VA.getValVT(), Root, FIN, NULL, 0));
960 ArgValues.push_back(Root);
962 unsigned StackSize = CCInfo.getNextStackOffset();
964 if (!Subtarget->isTargetCygMing() && !Subtarget->isTargetWindows()) {
965 // Make sure the instruction takes 8n+4 bytes to make sure the start of the
966 // arguments and the arguments after the retaddr has been pushed are aligned.
967 if ((StackSize & 7) == 0)
971 VarArgsFrameIndex = 0xAAAAAAA; // fastcc functions can't have varargs.
972 RegSaveFrameIndex = 0xAAAAAAA; // X86-64 only.
973 ReturnAddrIndex = 0; // No return address slot generated yet.
974 BytesToPopOnReturn = StackSize; // Callee pops all stack arguments.
975 BytesCallerReserves = 0;
977 MF.getInfo<X86MachineFunctionInfo>()
978 ->setBytesToPopOnReturn(BytesToPopOnReturn);
980 // Return the new list of results.
981 return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(),
982 &ArgValues[0], ArgValues.size()).getValue(Op.ResNo);
985 SDOperand X86TargetLowering::LowerFastCCCallTo(SDOperand Op, SelectionDAG &DAG,
987 SDOperand Chain = Op.getOperand(0);
988 bool isTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0;
989 SDOperand Callee = Op.getOperand(4);
991 // Analyze operands of the call, assigning locations to each operand.
992 SmallVector<CCValAssign, 16> ArgLocs;
993 CCState CCInfo(CC, getTargetMachine(), ArgLocs);
994 CCInfo.AnalyzeCallOperands(Op.Val, CC_X86_32_FastCall);
996 // Get a count of how many bytes are to be pushed on the stack.
997 unsigned NumBytes = CCInfo.getNextStackOffset();
999 if (!Subtarget->isTargetCygMing() && !Subtarget->isTargetWindows()) {
1000 // Make sure the instruction takes 8n+4 bytes to make sure the start of the
1001 // arguments and the arguments after the retaddr has been pushed are aligned.
1002 if ((NumBytes & 7) == 0)
1006 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes, getPointerTy()));
1008 SmallVector<std::pair<unsigned, SDOperand>, 8> RegsToPass;
1009 SmallVector<SDOperand, 8> MemOpChains;
1013 // Walk the register/memloc assignments, inserting copies/loads.
1014 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1015 CCValAssign &VA = ArgLocs[i];
1016 SDOperand Arg = Op.getOperand(5+2*VA.getValNo());
1018 // Promote the value if needed.
1019 switch (VA.getLocInfo()) {
1020 default: assert(0 && "Unknown loc info!");
1021 case CCValAssign::Full: break;
1022 case CCValAssign::SExt:
1023 Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg);
1025 case CCValAssign::ZExt:
1026 Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg);
1028 case CCValAssign::AExt:
1029 Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg);
1033 if (VA.isRegLoc()) {
1034 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1036 assert(VA.isMemLoc());
1037 if (StackPtr.Val == 0)
1038 StackPtr = DAG.getRegister(getStackPtrReg(), getPointerTy());
1039 SDOperand PtrOff = DAG.getConstant(VA.getLocMemOffset(), getPointerTy());
1040 PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
1041 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
1045 if (!MemOpChains.empty())
1046 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
1047 &MemOpChains[0], MemOpChains.size());
1049 // Build a sequence of copy-to-reg nodes chained together with token chain
1050 // and flag operands which copy the outgoing args into registers.
1052 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1053 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
1055 InFlag = Chain.getValue(1);
1058 // If the callee is a GlobalAddress node (quite common, every direct call is)
1059 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
1060 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1061 // We should use extra load for direct calls to dllimported functions in
1063 if (!Subtarget->GVRequiresExtraLoad(G->getGlobal(),
1064 getTargetMachine(), true))
1065 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
1066 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
1067 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
1069 // ELF / PIC requires GOT in the EBX register before function calls via PLT
1071 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1072 Subtarget->isPICStyleGOT()) {
1073 Chain = DAG.getCopyToReg(Chain, X86::EBX,
1074 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
1076 InFlag = Chain.getValue(1);
1079 // Returns a chain & a flag for retval copy to use.
1080 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1081 SmallVector<SDOperand, 8> Ops;
1082 Ops.push_back(Chain);
1083 Ops.push_back(Callee);
1085 // Add argument registers to the end of the list so that they are known live
1087 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1088 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1089 RegsToPass[i].second.getValueType()));
1091 // Add an implicit use GOT pointer in EBX.
1092 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1093 Subtarget->isPICStyleGOT())
1094 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
1097 Ops.push_back(InFlag);
1099 // FIXME: Do not generate X86ISD::TAILCALL for now.
1100 Chain = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL,
1101 NodeTys, &Ops[0], Ops.size());
1102 InFlag = Chain.getValue(1);
1104 // Returns a flag for retval copy to use.
1105 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1107 Ops.push_back(Chain);
1108 Ops.push_back(DAG.getConstant(NumBytes, getPointerTy()));
1109 Ops.push_back(DAG.getConstant(NumBytes, getPointerTy()));
1110 Ops.push_back(InFlag);
1111 Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0], Ops.size());
1112 InFlag = Chain.getValue(1);
1114 // Handle result values, copying them out of physregs into vregs that we
1116 return SDOperand(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG), Op.ResNo);
1120 //===----------------------------------------------------------------------===//
1121 // X86-64 C Calling Convention implementation
1122 //===----------------------------------------------------------------------===//
1125 X86TargetLowering::LowerX86_64CCCArguments(SDOperand Op, SelectionDAG &DAG) {
1126 MachineFunction &MF = DAG.getMachineFunction();
1127 MachineFrameInfo *MFI = MF.getFrameInfo();
1128 SDOperand Root = Op.getOperand(0);
1129 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
1131 static const unsigned GPR64ArgRegs[] = {
1132 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1134 static const unsigned XMMArgRegs[] = {
1135 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1136 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1140 // Assign locations to all of the incoming arguments.
1141 SmallVector<CCValAssign, 16> ArgLocs;
1142 CCState CCInfo(MF.getFunction()->getCallingConv(), getTargetMachine(),
1144 CCInfo.AnalyzeFormalArguments(Op.Val, CC_X86_64_C);
1146 SmallVector<SDOperand, 8> ArgValues;
1147 unsigned LastVal = ~0U;
1148 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1149 CCValAssign &VA = ArgLocs[i];
1150 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1152 assert(VA.getValNo() != LastVal &&
1153 "Don't support value assigned to multiple locs yet");
1154 LastVal = VA.getValNo();
1156 if (VA.isRegLoc()) {
1157 MVT::ValueType RegVT = VA.getLocVT();
1158 TargetRegisterClass *RC;
1159 if (RegVT == MVT::i32)
1160 RC = X86::GR32RegisterClass;
1161 else if (RegVT == MVT::i64)
1162 RC = X86::GR64RegisterClass;
1163 else if (RegVT == MVT::f32)
1164 RC = X86::FR32RegisterClass;
1165 else if (RegVT == MVT::f64)
1166 RC = X86::FR64RegisterClass;
1168 assert(MVT::isVector(RegVT));
1169 RC = X86::VR128RegisterClass;
1172 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
1173 SDOperand ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT);
1175 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1176 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1178 if (VA.getLocInfo() == CCValAssign::SExt)
1179 ArgValue = DAG.getNode(ISD::AssertSext, RegVT, ArgValue,
1180 DAG.getValueType(VA.getValVT()));
1181 else if (VA.getLocInfo() == CCValAssign::ZExt)
1182 ArgValue = DAG.getNode(ISD::AssertZext, RegVT, ArgValue,
1183 DAG.getValueType(VA.getValVT()));
1185 if (VA.getLocInfo() != CCValAssign::Full)
1186 ArgValue = DAG.getNode(ISD::TRUNCATE, VA.getValVT(), ArgValue);
1188 ArgValues.push_back(ArgValue);
1190 assert(VA.isMemLoc());
1192 // Create the nodes corresponding to a load from this parameter slot.
1193 int FI = MFI->CreateFixedObject(MVT::getSizeInBits(VA.getValVT())/8,
1194 VA.getLocMemOffset());
1195 SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy());
1196 ArgValues.push_back(DAG.getLoad(VA.getValVT(), Root, FIN, NULL, 0));
1200 unsigned StackSize = CCInfo.getNextStackOffset();
1202 // If the function takes variable number of arguments, make a frame index for
1203 // the start of the first vararg value... for expansion of llvm.va_start.
1205 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs, 6);
1206 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
1208 // For X86-64, if there are vararg parameters that are passed via
1209 // registers, then we must store them to their spots on the stack so they
1210 // may be loaded by deferencing the result of va_next.
1211 VarArgsGPOffset = NumIntRegs * 8;
1212 VarArgsFPOffset = 6 * 8 + NumXMMRegs * 16;
1213 VarArgsFrameIndex = MFI->CreateFixedObject(1, StackSize);
1214 RegSaveFrameIndex = MFI->CreateStackObject(6 * 8 + 8 * 16, 16);
1216 // Store the integer parameter registers.
1217 SmallVector<SDOperand, 8> MemOps;
1218 SDOperand RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
1219 SDOperand FIN = DAG.getNode(ISD::ADD, getPointerTy(), RSFIN,
1220 DAG.getConstant(VarArgsGPOffset, getPointerTy()));
1221 for (; NumIntRegs != 6; ++NumIntRegs) {
1222 unsigned VReg = AddLiveIn(MF, GPR64ArgRegs[NumIntRegs],
1223 X86::GR64RegisterClass);
1224 SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::i64);
1225 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
1226 MemOps.push_back(Store);
1227 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
1228 DAG.getConstant(8, getPointerTy()));
1231 // Now store the XMM (fp + vector) parameter registers.
1232 FIN = DAG.getNode(ISD::ADD, getPointerTy(), RSFIN,
1233 DAG.getConstant(VarArgsFPOffset, getPointerTy()));
1234 for (; NumXMMRegs != 8; ++NumXMMRegs) {
1235 unsigned VReg = AddLiveIn(MF, XMMArgRegs[NumXMMRegs],
1236 X86::VR128RegisterClass);
1237 SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::v4f32);
1238 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
1239 MemOps.push_back(Store);
1240 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
1241 DAG.getConstant(16, getPointerTy()));
1243 if (!MemOps.empty())
1244 Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
1245 &MemOps[0], MemOps.size());
1248 ArgValues.push_back(Root);
1250 ReturnAddrIndex = 0; // No return address slot generated yet.
1251 BytesToPopOnReturn = 0; // Callee pops nothing.
1252 BytesCallerReserves = StackSize;
1254 // Return the new list of results.
1255 return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(),
1256 &ArgValues[0], ArgValues.size()).getValue(Op.ResNo);
1260 X86TargetLowering::LowerX86_64CCCCallTo(SDOperand Op, SelectionDAG &DAG,
1262 SDOperand Chain = Op.getOperand(0);
1263 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
1264 bool isTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0;
1265 SDOperand Callee = Op.getOperand(4);
1267 // Analyze operands of the call, assigning locations to each operand.
1268 SmallVector<CCValAssign, 16> ArgLocs;
1269 CCState CCInfo(CC, getTargetMachine(), ArgLocs);
1270 CCInfo.AnalyzeCallOperands(Op.Val, CC_X86_64_C);
1272 // Get a count of how many bytes are to be pushed on the stack.
1273 unsigned NumBytes = CCInfo.getNextStackOffset();
1274 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes, getPointerTy()));
1276 SmallVector<std::pair<unsigned, SDOperand>, 8> RegsToPass;
1277 SmallVector<SDOperand, 8> MemOpChains;
1281 // Walk the register/memloc assignments, inserting copies/loads.
1282 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1283 CCValAssign &VA = ArgLocs[i];
1284 SDOperand Arg = Op.getOperand(5+2*VA.getValNo());
1286 // Promote the value if needed.
1287 switch (VA.getLocInfo()) {
1288 default: assert(0 && "Unknown loc info!");
1289 case CCValAssign::Full: break;
1290 case CCValAssign::SExt:
1291 Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg);
1293 case CCValAssign::ZExt:
1294 Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg);
1296 case CCValAssign::AExt:
1297 Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg);
1301 if (VA.isRegLoc()) {
1302 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1304 assert(VA.isMemLoc());
1305 if (StackPtr.Val == 0)
1306 StackPtr = DAG.getRegister(getStackPtrReg(), getPointerTy());
1307 SDOperand PtrOff = DAG.getConstant(VA.getLocMemOffset(), getPointerTy());
1308 PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
1309 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
1313 if (!MemOpChains.empty())
1314 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
1315 &MemOpChains[0], MemOpChains.size());
1317 // Build a sequence of copy-to-reg nodes chained together with token chain
1318 // and flag operands which copy the outgoing args into registers.
1320 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1321 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
1323 InFlag = Chain.getValue(1);
1327 // From AMD64 ABI document:
1328 // For calls that may call functions that use varargs or stdargs
1329 // (prototype-less calls or calls to functions containing ellipsis (...) in
1330 // the declaration) %al is used as hidden argument to specify the number
1331 // of SSE registers used. The contents of %al do not need to match exactly
1332 // the number of registers, but must be an ubound on the number of SSE
1333 // registers used and is in the range 0 - 8 inclusive.
1335 // Count the number of XMM registers allocated.
1336 static const unsigned XMMArgRegs[] = {
1337 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1338 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1340 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
1342 Chain = DAG.getCopyToReg(Chain, X86::AL,
1343 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
1344 InFlag = Chain.getValue(1);
1347 // If the callee is a GlobalAddress node (quite common, every direct call is)
1348 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
1349 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1350 // We should use extra load for direct calls to dllimported functions in
1352 if (getTargetMachine().getCodeModel() != CodeModel::Large
1353 && !Subtarget->GVRequiresExtraLoad(G->getGlobal(),
1354 getTargetMachine(), true))
1355 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
1356 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
1357 if (getTargetMachine().getCodeModel() != CodeModel::Large)
1358 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
1360 // Returns a chain & a flag for retval copy to use.
1361 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1362 SmallVector<SDOperand, 8> Ops;
1363 Ops.push_back(Chain);
1364 Ops.push_back(Callee);
1366 // Add argument registers to the end of the list so that they are known live
1368 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1369 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1370 RegsToPass[i].second.getValueType()));
1373 Ops.push_back(InFlag);
1375 // FIXME: Do not generate X86ISD::TAILCALL for now.
1376 Chain = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL,
1377 NodeTys, &Ops[0], Ops.size());
1378 InFlag = Chain.getValue(1);
1380 // Returns a flag for retval copy to use.
1381 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1383 Ops.push_back(Chain);
1384 Ops.push_back(DAG.getConstant(NumBytes, getPointerTy()));
1385 Ops.push_back(DAG.getConstant(0, getPointerTy()));
1386 Ops.push_back(InFlag);
1387 Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0], Ops.size());
1388 InFlag = Chain.getValue(1);
1390 // Handle result values, copying them out of physregs into vregs that we
1392 return SDOperand(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG), Op.ResNo);
1396 //===----------------------------------------------------------------------===//
1397 // Other Lowering Hooks
1398 //===----------------------------------------------------------------------===//
1401 SDOperand X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) {
1402 if (ReturnAddrIndex == 0) {
1403 // Set up a frame object for the return address.
1404 MachineFunction &MF = DAG.getMachineFunction();
1405 if (Subtarget->is64Bit())
1406 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(8, -8);
1408 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(4, -4);
1411 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
1416 /// translateX86CC - do a one to one translation of a ISD::CondCode to the X86
1417 /// specific condition code. It returns a false if it cannot do a direct
1418 /// translation. X86CC is the translated CondCode. LHS/RHS are modified as
1420 static bool translateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
1421 unsigned &X86CC, SDOperand &LHS, SDOperand &RHS,
1422 SelectionDAG &DAG) {
1423 X86CC = X86::COND_INVALID;
1425 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
1426 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
1427 // X > -1 -> X == 0, jump !sign.
1428 RHS = DAG.getConstant(0, RHS.getValueType());
1429 X86CC = X86::COND_NS;
1431 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
1432 // X < 0 -> X == 0, jump on sign.
1433 X86CC = X86::COND_S;
1438 switch (SetCCOpcode) {
1440 case ISD::SETEQ: X86CC = X86::COND_E; break;
1441 case ISD::SETGT: X86CC = X86::COND_G; break;
1442 case ISD::SETGE: X86CC = X86::COND_GE; break;
1443 case ISD::SETLT: X86CC = X86::COND_L; break;
1444 case ISD::SETLE: X86CC = X86::COND_LE; break;
1445 case ISD::SETNE: X86CC = X86::COND_NE; break;
1446 case ISD::SETULT: X86CC = X86::COND_B; break;
1447 case ISD::SETUGT: X86CC = X86::COND_A; break;
1448 case ISD::SETULE: X86CC = X86::COND_BE; break;
1449 case ISD::SETUGE: X86CC = X86::COND_AE; break;
1452 // On a floating point condition, the flags are set as follows:
1454 // 0 | 0 | 0 | X > Y
1455 // 0 | 0 | 1 | X < Y
1456 // 1 | 0 | 0 | X == Y
1457 // 1 | 1 | 1 | unordered
1459 switch (SetCCOpcode) {
1462 case ISD::SETEQ: X86CC = X86::COND_E; break;
1463 case ISD::SETOLT: Flip = true; // Fallthrough
1465 case ISD::SETGT: X86CC = X86::COND_A; break;
1466 case ISD::SETOLE: Flip = true; // Fallthrough
1468 case ISD::SETGE: X86CC = X86::COND_AE; break;
1469 case ISD::SETUGT: Flip = true; // Fallthrough
1471 case ISD::SETLT: X86CC = X86::COND_B; break;
1472 case ISD::SETUGE: Flip = true; // Fallthrough
1474 case ISD::SETLE: X86CC = X86::COND_BE; break;
1476 case ISD::SETNE: X86CC = X86::COND_NE; break;
1477 case ISD::SETUO: X86CC = X86::COND_P; break;
1478 case ISD::SETO: X86CC = X86::COND_NP; break;
1481 std::swap(LHS, RHS);
1484 return X86CC != X86::COND_INVALID;
1487 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
1488 /// code. Current x86 isa includes the following FP cmov instructions:
1489 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
1490 static bool hasFPCMov(unsigned X86CC) {
1506 /// isUndefOrInRange - Op is either an undef node or a ConstantSDNode. Return
1507 /// true if Op is undef or if its value falls within the specified range (L, H].
1508 static bool isUndefOrInRange(SDOperand Op, unsigned Low, unsigned Hi) {
1509 if (Op.getOpcode() == ISD::UNDEF)
1512 unsigned Val = cast<ConstantSDNode>(Op)->getValue();
1513 return (Val >= Low && Val < Hi);
1516 /// isUndefOrEqual - Op is either an undef node or a ConstantSDNode. Return
1517 /// true if Op is undef or if its value equal to the specified value.
1518 static bool isUndefOrEqual(SDOperand Op, unsigned Val) {
1519 if (Op.getOpcode() == ISD::UNDEF)
1521 return cast<ConstantSDNode>(Op)->getValue() == Val;
1524 /// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand
1525 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
1526 bool X86::isPSHUFDMask(SDNode *N) {
1527 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1529 if (N->getNumOperands() != 4)
1532 // Check if the value doesn't reference the second vector.
1533 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1534 SDOperand Arg = N->getOperand(i);
1535 if (Arg.getOpcode() == ISD::UNDEF) continue;
1536 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1537 if (cast<ConstantSDNode>(Arg)->getValue() >= 4)
1544 /// isPSHUFHWMask - Return true if the specified VECTOR_SHUFFLE operand
1545 /// specifies a shuffle of elements that is suitable for input to PSHUFHW.
1546 bool X86::isPSHUFHWMask(SDNode *N) {
1547 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1549 if (N->getNumOperands() != 8)
1552 // Lower quadword copied in order.
1553 for (unsigned i = 0; i != 4; ++i) {
1554 SDOperand Arg = N->getOperand(i);
1555 if (Arg.getOpcode() == ISD::UNDEF) continue;
1556 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1557 if (cast<ConstantSDNode>(Arg)->getValue() != i)
1561 // Upper quadword shuffled.
1562 for (unsigned i = 4; i != 8; ++i) {
1563 SDOperand Arg = N->getOperand(i);
1564 if (Arg.getOpcode() == ISD::UNDEF) continue;
1565 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1566 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
1567 if (Val < 4 || Val > 7)
1574 /// isPSHUFLWMask - Return true if the specified VECTOR_SHUFFLE operand
1575 /// specifies a shuffle of elements that is suitable for input to PSHUFLW.
1576 bool X86::isPSHUFLWMask(SDNode *N) {
1577 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1579 if (N->getNumOperands() != 8)
1582 // Upper quadword copied in order.
1583 for (unsigned i = 4; i != 8; ++i)
1584 if (!isUndefOrEqual(N->getOperand(i), i))
1587 // Lower quadword shuffled.
1588 for (unsigned i = 0; i != 4; ++i)
1589 if (!isUndefOrInRange(N->getOperand(i), 0, 4))
1595 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
1596 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
1597 static bool isSHUFPMask(const SDOperand *Elems, unsigned NumElems) {
1598 if (NumElems != 2 && NumElems != 4) return false;
1600 unsigned Half = NumElems / 2;
1601 for (unsigned i = 0; i < Half; ++i)
1602 if (!isUndefOrInRange(Elems[i], 0, NumElems))
1604 for (unsigned i = Half; i < NumElems; ++i)
1605 if (!isUndefOrInRange(Elems[i], NumElems, NumElems*2))
1611 bool X86::isSHUFPMask(SDNode *N) {
1612 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1613 return ::isSHUFPMask(N->op_begin(), N->getNumOperands());
1616 /// isCommutedSHUFP - Returns true if the shuffle mask is except
1617 /// the reverse of what x86 shuffles want. x86 shuffles requires the lower
1618 /// half elements to come from vector 1 (which would equal the dest.) and
1619 /// the upper half to come from vector 2.
1620 static bool isCommutedSHUFP(const SDOperand *Ops, unsigned NumOps) {
1621 if (NumOps != 2 && NumOps != 4) return false;
1623 unsigned Half = NumOps / 2;
1624 for (unsigned i = 0; i < Half; ++i)
1625 if (!isUndefOrInRange(Ops[i], NumOps, NumOps*2))
1627 for (unsigned i = Half; i < NumOps; ++i)
1628 if (!isUndefOrInRange(Ops[i], 0, NumOps))
1633 static bool isCommutedSHUFP(SDNode *N) {
1634 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1635 return isCommutedSHUFP(N->op_begin(), N->getNumOperands());
1638 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
1639 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
1640 bool X86::isMOVHLPSMask(SDNode *N) {
1641 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1643 if (N->getNumOperands() != 4)
1646 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
1647 return isUndefOrEqual(N->getOperand(0), 6) &&
1648 isUndefOrEqual(N->getOperand(1), 7) &&
1649 isUndefOrEqual(N->getOperand(2), 2) &&
1650 isUndefOrEqual(N->getOperand(3), 3);
1653 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
1654 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
1656 bool X86::isMOVHLPS_v_undef_Mask(SDNode *N) {
1657 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1659 if (N->getNumOperands() != 4)
1662 // Expect bit0 == 2, bit1 == 3, bit2 == 2, bit3 == 3
1663 return isUndefOrEqual(N->getOperand(0), 2) &&
1664 isUndefOrEqual(N->getOperand(1), 3) &&
1665 isUndefOrEqual(N->getOperand(2), 2) &&
1666 isUndefOrEqual(N->getOperand(3), 3);
1669 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
1670 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
1671 bool X86::isMOVLPMask(SDNode *N) {
1672 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1674 unsigned NumElems = N->getNumOperands();
1675 if (NumElems != 2 && NumElems != 4)
1678 for (unsigned i = 0; i < NumElems/2; ++i)
1679 if (!isUndefOrEqual(N->getOperand(i), i + NumElems))
1682 for (unsigned i = NumElems/2; i < NumElems; ++i)
1683 if (!isUndefOrEqual(N->getOperand(i), i))
1689 /// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand
1690 /// specifies a shuffle of elements that is suitable for input to MOVHP{S|D}
1692 bool X86::isMOVHPMask(SDNode *N) {
1693 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1695 unsigned NumElems = N->getNumOperands();
1696 if (NumElems != 2 && NumElems != 4)
1699 for (unsigned i = 0; i < NumElems/2; ++i)
1700 if (!isUndefOrEqual(N->getOperand(i), i))
1703 for (unsigned i = 0; i < NumElems/2; ++i) {
1704 SDOperand Arg = N->getOperand(i + NumElems/2);
1705 if (!isUndefOrEqual(Arg, i + NumElems))
1712 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
1713 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
1714 bool static isUNPCKLMask(const SDOperand *Elts, unsigned NumElts,
1715 bool V2IsSplat = false) {
1716 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
1719 for (unsigned i = 0, j = 0; i != NumElts; i += 2, ++j) {
1720 SDOperand BitI = Elts[i];
1721 SDOperand BitI1 = Elts[i+1];
1722 if (!isUndefOrEqual(BitI, j))
1725 if (isUndefOrEqual(BitI1, NumElts))
1728 if (!isUndefOrEqual(BitI1, j + NumElts))
1736 bool X86::isUNPCKLMask(SDNode *N, bool V2IsSplat) {
1737 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1738 return ::isUNPCKLMask(N->op_begin(), N->getNumOperands(), V2IsSplat);
1741 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
1742 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
1743 bool static isUNPCKHMask(const SDOperand *Elts, unsigned NumElts,
1744 bool V2IsSplat = false) {
1745 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
1748 for (unsigned i = 0, j = 0; i != NumElts; i += 2, ++j) {
1749 SDOperand BitI = Elts[i];
1750 SDOperand BitI1 = Elts[i+1];
1751 if (!isUndefOrEqual(BitI, j + NumElts/2))
1754 if (isUndefOrEqual(BitI1, NumElts))
1757 if (!isUndefOrEqual(BitI1, j + NumElts/2 + NumElts))
1765 bool X86::isUNPCKHMask(SDNode *N, bool V2IsSplat) {
1766 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1767 return ::isUNPCKHMask(N->op_begin(), N->getNumOperands(), V2IsSplat);
1770 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
1771 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
1773 bool X86::isUNPCKL_v_undef_Mask(SDNode *N) {
1774 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1776 unsigned NumElems = N->getNumOperands();
1777 if (NumElems != 4 && NumElems != 8 && NumElems != 16)
1780 for (unsigned i = 0, j = 0; i != NumElems; i += 2, ++j) {
1781 SDOperand BitI = N->getOperand(i);
1782 SDOperand BitI1 = N->getOperand(i+1);
1784 if (!isUndefOrEqual(BitI, j))
1786 if (!isUndefOrEqual(BitI1, j))
1793 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
1794 /// specifies a shuffle of elements that is suitable for input to MOVSS,
1795 /// MOVSD, and MOVD, i.e. setting the lowest element.
1796 static bool isMOVLMask(const SDOperand *Elts, unsigned NumElts) {
1797 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
1800 if (!isUndefOrEqual(Elts[0], NumElts))
1803 for (unsigned i = 1; i < NumElts; ++i) {
1804 if (!isUndefOrEqual(Elts[i], i))
1811 bool X86::isMOVLMask(SDNode *N) {
1812 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1813 return ::isMOVLMask(N->op_begin(), N->getNumOperands());
1816 /// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
1817 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
1818 /// element of vector 2 and the other elements to come from vector 1 in order.
1819 static bool isCommutedMOVL(const SDOperand *Ops, unsigned NumOps,
1820 bool V2IsSplat = false,
1821 bool V2IsUndef = false) {
1822 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
1825 if (!isUndefOrEqual(Ops[0], 0))
1828 for (unsigned i = 1; i < NumOps; ++i) {
1829 SDOperand Arg = Ops[i];
1830 if (!(isUndefOrEqual(Arg, i+NumOps) ||
1831 (V2IsUndef && isUndefOrInRange(Arg, NumOps, NumOps*2)) ||
1832 (V2IsSplat && isUndefOrEqual(Arg, NumOps))))
1839 static bool isCommutedMOVL(SDNode *N, bool V2IsSplat = false,
1840 bool V2IsUndef = false) {
1841 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1842 return isCommutedMOVL(N->op_begin(), N->getNumOperands(),
1843 V2IsSplat, V2IsUndef);
1846 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
1847 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
1848 bool X86::isMOVSHDUPMask(SDNode *N) {
1849 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1851 if (N->getNumOperands() != 4)
1854 // Expect 1, 1, 3, 3
1855 for (unsigned i = 0; i < 2; ++i) {
1856 SDOperand Arg = N->getOperand(i);
1857 if (Arg.getOpcode() == ISD::UNDEF) continue;
1858 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1859 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
1860 if (Val != 1) return false;
1864 for (unsigned i = 2; i < 4; ++i) {
1865 SDOperand Arg = N->getOperand(i);
1866 if (Arg.getOpcode() == ISD::UNDEF) continue;
1867 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1868 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
1869 if (Val != 3) return false;
1873 // Don't use movshdup if it can be done with a shufps.
1877 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
1878 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
1879 bool X86::isMOVSLDUPMask(SDNode *N) {
1880 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1882 if (N->getNumOperands() != 4)
1885 // Expect 0, 0, 2, 2
1886 for (unsigned i = 0; i < 2; ++i) {
1887 SDOperand Arg = N->getOperand(i);
1888 if (Arg.getOpcode() == ISD::UNDEF) continue;
1889 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1890 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
1891 if (Val != 0) return false;
1895 for (unsigned i = 2; i < 4; ++i) {
1896 SDOperand Arg = N->getOperand(i);
1897 if (Arg.getOpcode() == ISD::UNDEF) continue;
1898 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1899 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
1900 if (Val != 2) return false;
1904 // Don't use movshdup if it can be done with a shufps.
1908 /// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies
1909 /// a splat of a single element.
1910 static bool isSplatMask(SDNode *N) {
1911 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1913 // This is a splat operation if each element of the permute is the same, and
1914 // if the value doesn't reference the second vector.
1915 unsigned NumElems = N->getNumOperands();
1916 SDOperand ElementBase;
1918 for (; i != NumElems; ++i) {
1919 SDOperand Elt = N->getOperand(i);
1920 if (isa<ConstantSDNode>(Elt)) {
1926 if (!ElementBase.Val)
1929 for (; i != NumElems; ++i) {
1930 SDOperand Arg = N->getOperand(i);
1931 if (Arg.getOpcode() == ISD::UNDEF) continue;
1932 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1933 if (Arg != ElementBase) return false;
1936 // Make sure it is a splat of the first vector operand.
1937 return cast<ConstantSDNode>(ElementBase)->getValue() < NumElems;
1940 /// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies
1941 /// a splat of a single element and it's a 2 or 4 element mask.
1942 bool X86::isSplatMask(SDNode *N) {
1943 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1945 // We can only splat 64-bit, and 32-bit quantities with a single instruction.
1946 if (N->getNumOperands() != 4 && N->getNumOperands() != 2)
1948 return ::isSplatMask(N);
1951 /// isSplatLoMask - Return true if the specified VECTOR_SHUFFLE operand
1952 /// specifies a splat of zero element.
1953 bool X86::isSplatLoMask(SDNode *N) {
1954 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1956 for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i)
1957 if (!isUndefOrEqual(N->getOperand(i), 0))
1962 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
1963 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP*
1965 unsigned X86::getShuffleSHUFImmediate(SDNode *N) {
1966 unsigned NumOperands = N->getNumOperands();
1967 unsigned Shift = (NumOperands == 4) ? 2 : 1;
1969 for (unsigned i = 0; i < NumOperands; ++i) {
1971 SDOperand Arg = N->getOperand(NumOperands-i-1);
1972 if (Arg.getOpcode() != ISD::UNDEF)
1973 Val = cast<ConstantSDNode>(Arg)->getValue();
1974 if (Val >= NumOperands) Val -= NumOperands;
1976 if (i != NumOperands - 1)
1983 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
1984 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFHW
1986 unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
1988 // 8 nodes, but we only care about the last 4.
1989 for (unsigned i = 7; i >= 4; --i) {
1991 SDOperand Arg = N->getOperand(i);
1992 if (Arg.getOpcode() != ISD::UNDEF)
1993 Val = cast<ConstantSDNode>(Arg)->getValue();
2002 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
2003 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFLW
2005 unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
2007 // 8 nodes, but we only care about the first 4.
2008 for (int i = 3; i >= 0; --i) {
2010 SDOperand Arg = N->getOperand(i);
2011 if (Arg.getOpcode() != ISD::UNDEF)
2012 Val = cast<ConstantSDNode>(Arg)->getValue();
2021 /// isPSHUFHW_PSHUFLWMask - true if the specified VECTOR_SHUFFLE operand
2022 /// specifies a 8 element shuffle that can be broken into a pair of
2023 /// PSHUFHW and PSHUFLW.
2024 static bool isPSHUFHW_PSHUFLWMask(SDNode *N) {
2025 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2027 if (N->getNumOperands() != 8)
2030 // Lower quadword shuffled.
2031 for (unsigned i = 0; i != 4; ++i) {
2032 SDOperand Arg = N->getOperand(i);
2033 if (Arg.getOpcode() == ISD::UNDEF) continue;
2034 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2035 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2040 // Upper quadword shuffled.
2041 for (unsigned i = 4; i != 8; ++i) {
2042 SDOperand Arg = N->getOperand(i);
2043 if (Arg.getOpcode() == ISD::UNDEF) continue;
2044 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2045 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2046 if (Val < 4 || Val > 7)
2053 /// CommuteVectorShuffle - Swap vector_shuffle operandsas well as
2054 /// values in ther permute mask.
2055 static SDOperand CommuteVectorShuffle(SDOperand Op, SDOperand &V1,
2056 SDOperand &V2, SDOperand &Mask,
2057 SelectionDAG &DAG) {
2058 MVT::ValueType VT = Op.getValueType();
2059 MVT::ValueType MaskVT = Mask.getValueType();
2060 MVT::ValueType EltVT = MVT::getVectorBaseType(MaskVT);
2061 unsigned NumElems = Mask.getNumOperands();
2062 SmallVector<SDOperand, 8> MaskVec;
2064 for (unsigned i = 0; i != NumElems; ++i) {
2065 SDOperand Arg = Mask.getOperand(i);
2066 if (Arg.getOpcode() == ISD::UNDEF) {
2067 MaskVec.push_back(DAG.getNode(ISD::UNDEF, EltVT));
2070 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2071 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2073 MaskVec.push_back(DAG.getConstant(Val + NumElems, EltVT));
2075 MaskVec.push_back(DAG.getConstant(Val - NumElems, EltVT));
2079 Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2080 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
2083 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
2084 /// match movhlps. The lower half elements should come from upper half of
2085 /// V1 (and in order), and the upper half elements should come from the upper
2086 /// half of V2 (and in order).
2087 static bool ShouldXformToMOVHLPS(SDNode *Mask) {
2088 unsigned NumElems = Mask->getNumOperands();
2091 for (unsigned i = 0, e = 2; i != e; ++i)
2092 if (!isUndefOrEqual(Mask->getOperand(i), i+2))
2094 for (unsigned i = 2; i != 4; ++i)
2095 if (!isUndefOrEqual(Mask->getOperand(i), i+4))
2100 /// isScalarLoadToVector - Returns true if the node is a scalar load that
2101 /// is promoted to a vector.
2102 static inline bool isScalarLoadToVector(SDNode *N) {
2103 if (N->getOpcode() == ISD::SCALAR_TO_VECTOR) {
2104 N = N->getOperand(0).Val;
2105 return ISD::isNON_EXTLoad(N);
2110 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
2111 /// match movlp{s|d}. The lower half elements should come from lower half of
2112 /// V1 (and in order), and the upper half elements should come from the upper
2113 /// half of V2 (and in order). And since V1 will become the source of the
2114 /// MOVLP, it must be either a vector load or a scalar load to vector.
2115 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2, SDNode *Mask) {
2116 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
2118 // Is V2 is a vector load, don't do this transformation. We will try to use
2119 // load folding shufps op.
2120 if (ISD::isNON_EXTLoad(V2))
2123 unsigned NumElems = Mask->getNumOperands();
2124 if (NumElems != 2 && NumElems != 4)
2126 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
2127 if (!isUndefOrEqual(Mask->getOperand(i), i))
2129 for (unsigned i = NumElems/2; i != NumElems; ++i)
2130 if (!isUndefOrEqual(Mask->getOperand(i), i+NumElems))
2135 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
2137 static bool isSplatVector(SDNode *N) {
2138 if (N->getOpcode() != ISD::BUILD_VECTOR)
2141 SDOperand SplatValue = N->getOperand(0);
2142 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
2143 if (N->getOperand(i) != SplatValue)
2148 /// isUndefShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
2150 static bool isUndefShuffle(SDNode *N) {
2151 if (N->getOpcode() != ISD::BUILD_VECTOR)
2154 SDOperand V1 = N->getOperand(0);
2155 SDOperand V2 = N->getOperand(1);
2156 SDOperand Mask = N->getOperand(2);
2157 unsigned NumElems = Mask.getNumOperands();
2158 for (unsigned i = 0; i != NumElems; ++i) {
2159 SDOperand Arg = Mask.getOperand(i);
2160 if (Arg.getOpcode() != ISD::UNDEF) {
2161 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2162 if (Val < NumElems && V1.getOpcode() != ISD::UNDEF)
2164 else if (Val >= NumElems && V2.getOpcode() != ISD::UNDEF)
2171 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
2172 /// that point to V2 points to its first element.
2173 static SDOperand NormalizeMask(SDOperand Mask, SelectionDAG &DAG) {
2174 assert(Mask.getOpcode() == ISD::BUILD_VECTOR);
2176 bool Changed = false;
2177 SmallVector<SDOperand, 8> MaskVec;
2178 unsigned NumElems = Mask.getNumOperands();
2179 for (unsigned i = 0; i != NumElems; ++i) {
2180 SDOperand Arg = Mask.getOperand(i);
2181 if (Arg.getOpcode() != ISD::UNDEF) {
2182 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2183 if (Val > NumElems) {
2184 Arg = DAG.getConstant(NumElems, Arg.getValueType());
2188 MaskVec.push_back(Arg);
2192 Mask = DAG.getNode(ISD::BUILD_VECTOR, Mask.getValueType(),
2193 &MaskVec[0], MaskVec.size());
2197 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
2198 /// operation of specified width.
2199 static SDOperand getMOVLMask(unsigned NumElems, SelectionDAG &DAG) {
2200 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2201 MVT::ValueType BaseVT = MVT::getVectorBaseType(MaskVT);
2203 SmallVector<SDOperand, 8> MaskVec;
2204 MaskVec.push_back(DAG.getConstant(NumElems, BaseVT));
2205 for (unsigned i = 1; i != NumElems; ++i)
2206 MaskVec.push_back(DAG.getConstant(i, BaseVT));
2207 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2210 /// getUnpacklMask - Returns a vector_shuffle mask for an unpackl operation
2211 /// of specified width.
2212 static SDOperand getUnpacklMask(unsigned NumElems, SelectionDAG &DAG) {
2213 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2214 MVT::ValueType BaseVT = MVT::getVectorBaseType(MaskVT);
2215 SmallVector<SDOperand, 8> MaskVec;
2216 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
2217 MaskVec.push_back(DAG.getConstant(i, BaseVT));
2218 MaskVec.push_back(DAG.getConstant(i + NumElems, BaseVT));
2220 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2223 /// getUnpackhMask - Returns a vector_shuffle mask for an unpackh operation
2224 /// of specified width.
2225 static SDOperand getUnpackhMask(unsigned NumElems, SelectionDAG &DAG) {
2226 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2227 MVT::ValueType BaseVT = MVT::getVectorBaseType(MaskVT);
2228 unsigned Half = NumElems/2;
2229 SmallVector<SDOperand, 8> MaskVec;
2230 for (unsigned i = 0; i != Half; ++i) {
2231 MaskVec.push_back(DAG.getConstant(i + Half, BaseVT));
2232 MaskVec.push_back(DAG.getConstant(i + NumElems + Half, BaseVT));
2234 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2237 /// getZeroVector - Returns a vector of specified type with all zero elements.
2239 static SDOperand getZeroVector(MVT::ValueType VT, SelectionDAG &DAG) {
2240 assert(MVT::isVector(VT) && "Expected a vector type");
2241 unsigned NumElems = getVectorNumElements(VT);
2242 MVT::ValueType EVT = MVT::getVectorBaseType(VT);
2243 bool isFP = MVT::isFloatingPoint(EVT);
2244 SDOperand Zero = isFP ? DAG.getConstantFP(0.0, EVT) : DAG.getConstant(0, EVT);
2245 SmallVector<SDOperand, 8> ZeroVec(NumElems, Zero);
2246 return DAG.getNode(ISD::BUILD_VECTOR, VT, &ZeroVec[0], ZeroVec.size());
2249 /// PromoteSplat - Promote a splat of v8i16 or v16i8 to v4i32.
2251 static SDOperand PromoteSplat(SDOperand Op, SelectionDAG &DAG) {
2252 SDOperand V1 = Op.getOperand(0);
2253 SDOperand Mask = Op.getOperand(2);
2254 MVT::ValueType VT = Op.getValueType();
2255 unsigned NumElems = Mask.getNumOperands();
2256 Mask = getUnpacklMask(NumElems, DAG);
2257 while (NumElems != 4) {
2258 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V1, Mask);
2261 V1 = DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, V1);
2263 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(4);
2264 Mask = getZeroVector(MaskVT, DAG);
2265 SDOperand Shuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v4i32, V1,
2266 DAG.getNode(ISD::UNDEF, MVT::v4i32), Mask);
2267 return DAG.getNode(ISD::BIT_CONVERT, VT, Shuffle);
2270 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
2272 static inline bool isZeroNode(SDOperand Elt) {
2273 return ((isa<ConstantSDNode>(Elt) &&
2274 cast<ConstantSDNode>(Elt)->getValue() == 0) ||
2275 (isa<ConstantFPSDNode>(Elt) &&
2276 cast<ConstantFPSDNode>(Elt)->isExactlyValue(0.0)));
2279 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
2280 /// vector and zero or undef vector.
2281 static SDOperand getShuffleVectorZeroOrUndef(SDOperand V2, MVT::ValueType VT,
2282 unsigned NumElems, unsigned Idx,
2283 bool isZero, SelectionDAG &DAG) {
2284 SDOperand V1 = isZero ? getZeroVector(VT, DAG) : DAG.getNode(ISD::UNDEF, VT);
2285 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2286 MVT::ValueType EVT = MVT::getVectorBaseType(MaskVT);
2287 SDOperand Zero = DAG.getConstant(0, EVT);
2288 SmallVector<SDOperand, 8> MaskVec(NumElems, Zero);
2289 MaskVec[Idx] = DAG.getConstant(NumElems, EVT);
2290 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2291 &MaskVec[0], MaskVec.size());
2292 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
2295 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
2297 static SDOperand LowerBuildVectorv16i8(SDOperand Op, unsigned NonZeros,
2298 unsigned NumNonZero, unsigned NumZero,
2299 SelectionDAG &DAG, TargetLowering &TLI) {
2305 for (unsigned i = 0; i < 16; ++i) {
2306 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
2307 if (ThisIsNonZero && First) {
2309 V = getZeroVector(MVT::v8i16, DAG);
2311 V = DAG.getNode(ISD::UNDEF, MVT::v8i16);
2316 SDOperand ThisElt(0, 0), LastElt(0, 0);
2317 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
2318 if (LastIsNonZero) {
2319 LastElt = DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, Op.getOperand(i-1));
2321 if (ThisIsNonZero) {
2322 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, Op.getOperand(i));
2323 ThisElt = DAG.getNode(ISD::SHL, MVT::i16,
2324 ThisElt, DAG.getConstant(8, MVT::i8));
2326 ThisElt = DAG.getNode(ISD::OR, MVT::i16, ThisElt, LastElt);
2331 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, V, ThisElt,
2332 DAG.getConstant(i/2, TLI.getPointerTy()));
2336 return DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, V);
2339 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
2341 static SDOperand LowerBuildVectorv8i16(SDOperand Op, unsigned NonZeros,
2342 unsigned NumNonZero, unsigned NumZero,
2343 SelectionDAG &DAG, TargetLowering &TLI) {
2349 for (unsigned i = 0; i < 8; ++i) {
2350 bool isNonZero = (NonZeros & (1 << i)) != 0;
2354 V = getZeroVector(MVT::v8i16, DAG);
2356 V = DAG.getNode(ISD::UNDEF, MVT::v8i16);
2359 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, V, Op.getOperand(i),
2360 DAG.getConstant(i, TLI.getPointerTy()));
2368 X86TargetLowering::LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) {
2369 // All zero's are handled with pxor.
2370 if (ISD::isBuildVectorAllZeros(Op.Val))
2373 // All one's are handled with pcmpeqd.
2374 if (ISD::isBuildVectorAllOnes(Op.Val))
2377 MVT::ValueType VT = Op.getValueType();
2378 MVT::ValueType EVT = MVT::getVectorBaseType(VT);
2379 unsigned EVTBits = MVT::getSizeInBits(EVT);
2381 unsigned NumElems = Op.getNumOperands();
2382 unsigned NumZero = 0;
2383 unsigned NumNonZero = 0;
2384 unsigned NonZeros = 0;
2385 std::set<SDOperand> Values;
2386 for (unsigned i = 0; i < NumElems; ++i) {
2387 SDOperand Elt = Op.getOperand(i);
2388 if (Elt.getOpcode() != ISD::UNDEF) {
2390 if (isZeroNode(Elt))
2393 NonZeros |= (1 << i);
2399 if (NumNonZero == 0)
2400 // Must be a mix of zero and undef. Return a zero vector.
2401 return getZeroVector(VT, DAG);
2403 // Splat is obviously ok. Let legalizer expand it to a shuffle.
2404 if (Values.size() == 1)
2407 // Special case for single non-zero element.
2408 if (NumNonZero == 1) {
2409 unsigned Idx = CountTrailingZeros_32(NonZeros);
2410 SDOperand Item = Op.getOperand(Idx);
2411 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Item);
2413 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
2414 return getShuffleVectorZeroOrUndef(Item, VT, NumElems, Idx,
2417 if (EVTBits == 32) {
2418 // Turn it into a shuffle of zero and zero-extended scalar to vector.
2419 Item = getShuffleVectorZeroOrUndef(Item, VT, NumElems, 0, NumZero > 0,
2421 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2422 MVT::ValueType MaskEVT = MVT::getVectorBaseType(MaskVT);
2423 SmallVector<SDOperand, 8> MaskVec;
2424 for (unsigned i = 0; i < NumElems; i++)
2425 MaskVec.push_back(DAG.getConstant((i == Idx) ? 0 : 1, MaskEVT));
2426 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2427 &MaskVec[0], MaskVec.size());
2428 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, Item,
2429 DAG.getNode(ISD::UNDEF, VT), Mask);
2433 // Let legalizer expand 2-wide build_vector's.
2437 // If element VT is < 32 bits, convert it to inserts into a zero vector.
2438 if (EVTBits == 8 && NumElems == 16) {
2439 SDOperand V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
2441 if (V.Val) return V;
2444 if (EVTBits == 16 && NumElems == 8) {
2445 SDOperand V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
2447 if (V.Val) return V;
2450 // If element VT is == 32 bits, turn it into a number of shuffles.
2451 SmallVector<SDOperand, 8> V;
2453 if (NumElems == 4 && NumZero > 0) {
2454 for (unsigned i = 0; i < 4; ++i) {
2455 bool isZero = !(NonZeros & (1 << i));
2457 V[i] = getZeroVector(VT, DAG);
2459 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(i));
2462 for (unsigned i = 0; i < 2; ++i) {
2463 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
2466 V[i] = V[i*2]; // Must be a zero vector.
2469 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2+1], V[i*2],
2470 getMOVLMask(NumElems, DAG));
2473 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2], V[i*2+1],
2474 getMOVLMask(NumElems, DAG));
2477 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2], V[i*2+1],
2478 getUnpacklMask(NumElems, DAG));
2483 // Take advantage of the fact GR32 to VR128 scalar_to_vector (i.e. movd)
2484 // clears the upper bits.
2485 // FIXME: we can do the same for v4f32 case when we know both parts of
2486 // the lower half come from scalar_to_vector (loadf32). We should do
2487 // that in post legalizer dag combiner with target specific hooks.
2488 if (MVT::isInteger(EVT) && (NonZeros & (0x3 << 2)) == 0)
2490 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2491 MVT::ValueType EVT = MVT::getVectorBaseType(MaskVT);
2492 SmallVector<SDOperand, 8> MaskVec;
2493 bool Reverse = (NonZeros & 0x3) == 2;
2494 for (unsigned i = 0; i < 2; ++i)
2496 MaskVec.push_back(DAG.getConstant(1-i, EVT));
2498 MaskVec.push_back(DAG.getConstant(i, EVT));
2499 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2;
2500 for (unsigned i = 0; i < 2; ++i)
2502 MaskVec.push_back(DAG.getConstant(1-i+NumElems, EVT));
2504 MaskVec.push_back(DAG.getConstant(i+NumElems, EVT));
2505 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2506 &MaskVec[0], MaskVec.size());
2507 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[0], V[1], ShufMask);
2510 if (Values.size() > 2) {
2511 // Expand into a number of unpckl*.
2513 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
2514 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
2515 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
2516 SDOperand UnpckMask = getUnpacklMask(NumElems, DAG);
2517 for (unsigned i = 0; i < NumElems; ++i)
2518 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(i));
2520 while (NumElems != 0) {
2521 for (unsigned i = 0; i < NumElems; ++i)
2522 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i], V[i + NumElems],
2533 X86TargetLowering::LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) {
2534 SDOperand V1 = Op.getOperand(0);
2535 SDOperand V2 = Op.getOperand(1);
2536 SDOperand PermMask = Op.getOperand(2);
2537 MVT::ValueType VT = Op.getValueType();
2538 unsigned NumElems = PermMask.getNumOperands();
2539 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
2540 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
2541 bool V1IsSplat = false;
2542 bool V2IsSplat = false;
2544 if (isUndefShuffle(Op.Val))
2545 return DAG.getNode(ISD::UNDEF, VT);
2547 if (isSplatMask(PermMask.Val)) {
2548 if (NumElems <= 4) return Op;
2549 // Promote it to a v4i32 splat.
2550 return PromoteSplat(Op, DAG);
2553 if (X86::isMOVLMask(PermMask.Val))
2554 return (V1IsUndef) ? V2 : Op;
2556 if (X86::isMOVSHDUPMask(PermMask.Val) ||
2557 X86::isMOVSLDUPMask(PermMask.Val) ||
2558 X86::isMOVHLPSMask(PermMask.Val) ||
2559 X86::isMOVHPMask(PermMask.Val) ||
2560 X86::isMOVLPMask(PermMask.Val))
2563 if (ShouldXformToMOVHLPS(PermMask.Val) ||
2564 ShouldXformToMOVLP(V1.Val, V2.Val, PermMask.Val))
2565 return CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
2567 bool Commuted = false;
2568 V1IsSplat = isSplatVector(V1.Val);
2569 V2IsSplat = isSplatVector(V2.Val);
2570 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) {
2571 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
2572 std::swap(V1IsSplat, V2IsSplat);
2573 std::swap(V1IsUndef, V2IsUndef);
2577 if (isCommutedMOVL(PermMask.Val, V2IsSplat, V2IsUndef)) {
2578 if (V2IsUndef) return V1;
2579 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
2581 // V2 is a splat, so the mask may be malformed. That is, it may point
2582 // to any V2 element. The instruction selectior won't like this. Get
2583 // a corrected mask and commute to form a proper MOVS{S|D}.
2584 SDOperand NewMask = getMOVLMask(NumElems, DAG);
2585 if (NewMask.Val != PermMask.Val)
2586 Op = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
2591 if (X86::isUNPCKL_v_undef_Mask(PermMask.Val) ||
2592 X86::isUNPCKLMask(PermMask.Val) ||
2593 X86::isUNPCKHMask(PermMask.Val))
2597 // Normalize mask so all entries that point to V2 points to its first
2598 // element then try to match unpck{h|l} again. If match, return a
2599 // new vector_shuffle with the corrected mask.
2600 SDOperand NewMask = NormalizeMask(PermMask, DAG);
2601 if (NewMask.Val != PermMask.Val) {
2602 if (X86::isUNPCKLMask(PermMask.Val, true)) {
2603 SDOperand NewMask = getUnpacklMask(NumElems, DAG);
2604 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
2605 } else if (X86::isUNPCKHMask(PermMask.Val, true)) {
2606 SDOperand NewMask = getUnpackhMask(NumElems, DAG);
2607 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
2612 // Normalize the node to match x86 shuffle ops if needed
2613 if (V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(PermMask.Val))
2614 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
2617 // Commute is back and try unpck* again.
2618 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
2619 if (X86::isUNPCKL_v_undef_Mask(PermMask.Val) ||
2620 X86::isUNPCKLMask(PermMask.Val) ||
2621 X86::isUNPCKHMask(PermMask.Val))
2625 // If VT is integer, try PSHUF* first, then SHUFP*.
2626 if (MVT::isInteger(VT)) {
2627 if (X86::isPSHUFDMask(PermMask.Val) ||
2628 X86::isPSHUFHWMask(PermMask.Val) ||
2629 X86::isPSHUFLWMask(PermMask.Val)) {
2630 if (V2.getOpcode() != ISD::UNDEF)
2631 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1,
2632 DAG.getNode(ISD::UNDEF, V1.getValueType()),PermMask);
2636 if (X86::isSHUFPMask(PermMask.Val))
2639 // Handle v8i16 shuffle high / low shuffle node pair.
2640 if (VT == MVT::v8i16 && isPSHUFHW_PSHUFLWMask(PermMask.Val)) {
2641 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2642 MVT::ValueType BaseVT = MVT::getVectorBaseType(MaskVT);
2643 SmallVector<SDOperand, 8> MaskVec;
2644 for (unsigned i = 0; i != 4; ++i)
2645 MaskVec.push_back(PermMask.getOperand(i));
2646 for (unsigned i = 4; i != 8; ++i)
2647 MaskVec.push_back(DAG.getConstant(i, BaseVT));
2648 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2649 &MaskVec[0], MaskVec.size());
2650 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
2652 for (unsigned i = 0; i != 4; ++i)
2653 MaskVec.push_back(DAG.getConstant(i, BaseVT));
2654 for (unsigned i = 4; i != 8; ++i)
2655 MaskVec.push_back(PermMask.getOperand(i));
2656 Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0],MaskVec.size());
2657 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
2660 // Floating point cases in the other order.
2661 if (X86::isSHUFPMask(PermMask.Val))
2663 if (X86::isPSHUFDMask(PermMask.Val) ||
2664 X86::isPSHUFHWMask(PermMask.Val) ||
2665 X86::isPSHUFLWMask(PermMask.Val)) {
2666 if (V2.getOpcode() != ISD::UNDEF)
2667 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1,
2668 DAG.getNode(ISD::UNDEF, V1.getValueType()),PermMask);
2673 if (NumElems == 4) {
2674 MVT::ValueType MaskVT = PermMask.getValueType();
2675 MVT::ValueType MaskEVT = MVT::getVectorBaseType(MaskVT);
2676 SmallVector<std::pair<int, int>, 8> Locs;
2677 Locs.reserve(NumElems);
2678 SmallVector<SDOperand, 8> Mask1(NumElems, DAG.getNode(ISD::UNDEF, MaskEVT));
2679 SmallVector<SDOperand, 8> Mask2(NumElems, DAG.getNode(ISD::UNDEF, MaskEVT));
2682 // If no more than two elements come from either vector. This can be
2683 // implemented with two shuffles. First shuffle gather the elements.
2684 // The second shuffle, which takes the first shuffle as both of its
2685 // vector operands, put the elements into the right order.
2686 for (unsigned i = 0; i != NumElems; ++i) {
2687 SDOperand Elt = PermMask.getOperand(i);
2688 if (Elt.getOpcode() == ISD::UNDEF) {
2689 Locs[i] = std::make_pair(-1, -1);
2691 unsigned Val = cast<ConstantSDNode>(Elt)->getValue();
2692 if (Val < NumElems) {
2693 Locs[i] = std::make_pair(0, NumLo);
2697 Locs[i] = std::make_pair(1, NumHi);
2698 if (2+NumHi < NumElems)
2699 Mask1[2+NumHi] = Elt;
2704 if (NumLo <= 2 && NumHi <= 2) {
2705 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
2706 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2707 &Mask1[0], Mask1.size()));
2708 for (unsigned i = 0; i != NumElems; ++i) {
2709 if (Locs[i].first == -1)
2712 unsigned Idx = (i < NumElems/2) ? 0 : NumElems;
2713 Idx += Locs[i].first * (NumElems/2) + Locs[i].second;
2714 Mask2[i] = DAG.getConstant(Idx, MaskEVT);
2718 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V1,
2719 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2720 &Mask2[0], Mask2.size()));
2723 // Break it into (shuffle shuffle_hi, shuffle_lo).
2725 SmallVector<SDOperand,8> LoMask(NumElems, DAG.getNode(ISD::UNDEF, MaskEVT));
2726 SmallVector<SDOperand,8> HiMask(NumElems, DAG.getNode(ISD::UNDEF, MaskEVT));
2727 SmallVector<SDOperand,8> *MaskPtr = &LoMask;
2728 unsigned MaskIdx = 0;
2730 unsigned HiIdx = NumElems/2;
2731 for (unsigned i = 0; i != NumElems; ++i) {
2732 if (i == NumElems/2) {
2738 SDOperand Elt = PermMask.getOperand(i);
2739 if (Elt.getOpcode() == ISD::UNDEF) {
2740 Locs[i] = std::make_pair(-1, -1);
2741 } else if (cast<ConstantSDNode>(Elt)->getValue() < NumElems) {
2742 Locs[i] = std::make_pair(MaskIdx, LoIdx);
2743 (*MaskPtr)[LoIdx] = Elt;
2746 Locs[i] = std::make_pair(MaskIdx, HiIdx);
2747 (*MaskPtr)[HiIdx] = Elt;
2752 SDOperand LoShuffle =
2753 DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
2754 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2755 &LoMask[0], LoMask.size()));
2756 SDOperand HiShuffle =
2757 DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
2758 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2759 &HiMask[0], HiMask.size()));
2760 SmallVector<SDOperand, 8> MaskOps;
2761 for (unsigned i = 0; i != NumElems; ++i) {
2762 if (Locs[i].first == -1) {
2763 MaskOps.push_back(DAG.getNode(ISD::UNDEF, MaskEVT));
2765 unsigned Idx = Locs[i].first * NumElems + Locs[i].second;
2766 MaskOps.push_back(DAG.getConstant(Idx, MaskEVT));
2769 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, LoShuffle, HiShuffle,
2770 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2771 &MaskOps[0], MaskOps.size()));
2778 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) {
2779 if (!isa<ConstantSDNode>(Op.getOperand(1)))
2782 MVT::ValueType VT = Op.getValueType();
2783 // TODO: handle v16i8.
2784 if (MVT::getSizeInBits(VT) == 16) {
2785 // Transform it so it match pextrw which produces a 32-bit result.
2786 MVT::ValueType EVT = (MVT::ValueType)(VT+1);
2787 SDOperand Extract = DAG.getNode(X86ISD::PEXTRW, EVT,
2788 Op.getOperand(0), Op.getOperand(1));
2789 SDOperand Assert = DAG.getNode(ISD::AssertZext, EVT, Extract,
2790 DAG.getValueType(VT));
2791 return DAG.getNode(ISD::TRUNCATE, VT, Assert);
2792 } else if (MVT::getSizeInBits(VT) == 32) {
2793 SDOperand Vec = Op.getOperand(0);
2794 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
2797 // SHUFPS the element to the lowest double word, then movss.
2798 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(4);
2799 SmallVector<SDOperand, 8> IdxVec;
2800 IdxVec.push_back(DAG.getConstant(Idx, MVT::getVectorBaseType(MaskVT)));
2801 IdxVec.push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorBaseType(MaskVT)));
2802 IdxVec.push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorBaseType(MaskVT)));
2803 IdxVec.push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorBaseType(MaskVT)));
2804 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2805 &IdxVec[0], IdxVec.size());
2806 Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(),
2807 Vec, DAG.getNode(ISD::UNDEF, Vec.getValueType()), Mask);
2808 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec,
2809 DAG.getConstant(0, getPointerTy()));
2810 } else if (MVT::getSizeInBits(VT) == 64) {
2811 SDOperand Vec = Op.getOperand(0);
2812 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
2816 // UNPCKHPD the element to the lowest double word, then movsd.
2817 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
2818 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
2819 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(4);
2820 SmallVector<SDOperand, 8> IdxVec;
2821 IdxVec.push_back(DAG.getConstant(1, MVT::getVectorBaseType(MaskVT)));
2822 IdxVec.push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorBaseType(MaskVT)));
2823 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2824 &IdxVec[0], IdxVec.size());
2825 Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(),
2826 Vec, DAG.getNode(ISD::UNDEF, Vec.getValueType()), Mask);
2827 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec,
2828 DAG.getConstant(0, getPointerTy()));
2835 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) {
2836 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
2837 // as its second argument.
2838 MVT::ValueType VT = Op.getValueType();
2839 MVT::ValueType BaseVT = MVT::getVectorBaseType(VT);
2840 SDOperand N0 = Op.getOperand(0);
2841 SDOperand N1 = Op.getOperand(1);
2842 SDOperand N2 = Op.getOperand(2);
2843 if (MVT::getSizeInBits(BaseVT) == 16) {
2844 if (N1.getValueType() != MVT::i32)
2845 N1 = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, N1);
2846 if (N2.getValueType() != MVT::i32)
2847 N2 = DAG.getConstant(cast<ConstantSDNode>(N2)->getValue(), MVT::i32);
2848 return DAG.getNode(X86ISD::PINSRW, VT, N0, N1, N2);
2849 } else if (MVT::getSizeInBits(BaseVT) == 32) {
2850 unsigned Idx = cast<ConstantSDNode>(N2)->getValue();
2853 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, N1);
2854 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(4);
2855 MVT::ValueType BaseVT = MVT::getVectorBaseType(MaskVT);
2856 SmallVector<SDOperand, 8> MaskVec;
2857 MaskVec.push_back(DAG.getConstant(4, BaseVT));
2858 for (unsigned i = 1; i <= 3; ++i)
2859 MaskVec.push_back(DAG.getConstant(i, BaseVT));
2860 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, N0, N1,
2861 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2862 &MaskVec[0], MaskVec.size()));
2864 // Use two pinsrw instructions to insert a 32 bit value.
2866 if (MVT::isFloatingPoint(N1.getValueType())) {
2867 if (ISD::isNON_EXTLoad(N1.Val)) {
2868 // Just load directly from f32mem to GR32.
2869 LoadSDNode *LD = cast<LoadSDNode>(N1);
2870 N1 = DAG.getLoad(MVT::i32, LD->getChain(), LD->getBasePtr(),
2871 LD->getSrcValue(), LD->getSrcValueOffset());
2873 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v4f32, N1);
2874 N1 = DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, N1);
2875 N1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i32, N1,
2876 DAG.getConstant(0, getPointerTy()));
2879 N0 = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, N0);
2880 N0 = DAG.getNode(X86ISD::PINSRW, MVT::v8i16, N0, N1,
2881 DAG.getConstant(Idx, getPointerTy()));
2882 N1 = DAG.getNode(ISD::SRL, MVT::i32, N1, DAG.getConstant(16, MVT::i8));
2883 N0 = DAG.getNode(X86ISD::PINSRW, MVT::v8i16, N0, N1,
2884 DAG.getConstant(Idx+1, getPointerTy()));
2885 return DAG.getNode(ISD::BIT_CONVERT, VT, N0);
2893 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG) {
2894 SDOperand AnyExt = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, Op.getOperand(0));
2895 return DAG.getNode(X86ISD::S2VEC, Op.getValueType(), AnyExt);
2898 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
2899 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
2900 // one of the above mentioned nodes. It has to be wrapped because otherwise
2901 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
2902 // be used to form addressing mode. These wrapped nodes will be selected
2905 X86TargetLowering::LowerConstantPool(SDOperand Op, SelectionDAG &DAG) {
2906 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
2907 SDOperand Result = DAG.getTargetConstantPool(CP->getConstVal(),
2909 CP->getAlignment());
2910 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
2911 // With PIC, the address is actually $g + Offset.
2912 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2913 !Subtarget->isPICStyleRIPRel()) {
2914 Result = DAG.getNode(ISD::ADD, getPointerTy(),
2915 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
2923 X86TargetLowering::LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG) {
2924 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2925 SDOperand Result = DAG.getTargetGlobalAddress(GV, getPointerTy());
2926 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
2927 // With PIC, the address is actually $g + Offset.
2928 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2929 !Subtarget->isPICStyleRIPRel()) {
2930 Result = DAG.getNode(ISD::ADD, getPointerTy(),
2931 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
2935 // For Darwin & Mingw32, external and weak symbols are indirect, so we want to
2936 // load the value at address GV, not the value of GV itself. This means that
2937 // the GlobalAddress must be in the base or index register of the address, not
2938 // the GV offset field. Platform check is inside GVRequiresExtraLoad() call
2939 // The same applies for external symbols during PIC codegen
2940 if (Subtarget->GVRequiresExtraLoad(GV, getTargetMachine(), false))
2941 Result = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), Result, NULL, 0);
2947 X86TargetLowering::LowerExternalSymbol(SDOperand Op, SelectionDAG &DAG) {
2948 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
2949 SDOperand Result = DAG.getTargetExternalSymbol(Sym, getPointerTy());
2950 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
2951 // With PIC, the address is actually $g + Offset.
2952 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2953 !Subtarget->isPICStyleRIPRel()) {
2954 Result = DAG.getNode(ISD::ADD, getPointerTy(),
2955 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
2962 SDOperand X86TargetLowering::LowerJumpTable(SDOperand Op, SelectionDAG &DAG) {
2963 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
2964 SDOperand Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy());
2965 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
2966 // With PIC, the address is actually $g + Offset.
2967 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2968 !Subtarget->isPICStyleRIPRel()) {
2969 Result = DAG.getNode(ISD::ADD, getPointerTy(),
2970 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
2977 SDOperand X86TargetLowering::LowerShift(SDOperand Op, SelectionDAG &DAG) {
2978 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 &&
2979 "Not an i64 shift!");
2980 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
2981 SDOperand ShOpLo = Op.getOperand(0);
2982 SDOperand ShOpHi = Op.getOperand(1);
2983 SDOperand ShAmt = Op.getOperand(2);
2984 SDOperand Tmp1 = isSRA ?
2985 DAG.getNode(ISD::SRA, MVT::i32, ShOpHi, DAG.getConstant(31, MVT::i8)) :
2986 DAG.getConstant(0, MVT::i32);
2988 SDOperand Tmp2, Tmp3;
2989 if (Op.getOpcode() == ISD::SHL_PARTS) {
2990 Tmp2 = DAG.getNode(X86ISD::SHLD, MVT::i32, ShOpHi, ShOpLo, ShAmt);
2991 Tmp3 = DAG.getNode(ISD::SHL, MVT::i32, ShOpLo, ShAmt);
2993 Tmp2 = DAG.getNode(X86ISD::SHRD, MVT::i32, ShOpLo, ShOpHi, ShAmt);
2994 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, MVT::i32, ShOpHi, ShAmt);
2997 const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::Other, MVT::Flag);
2998 SDOperand AndNode = DAG.getNode(ISD::AND, MVT::i8, ShAmt,
2999 DAG.getConstant(32, MVT::i8));
3000 SDOperand COps[]={DAG.getEntryNode(), AndNode, DAG.getConstant(0, MVT::i8)};
3001 SDOperand InFlag = DAG.getNode(X86ISD::CMP, VTs, 2, COps, 3).getValue(1);
3004 SDOperand CC = DAG.getConstant(X86::COND_NE, MVT::i8);
3006 VTs = DAG.getNodeValueTypes(MVT::i32, MVT::Flag);
3007 SmallVector<SDOperand, 4> Ops;
3008 if (Op.getOpcode() == ISD::SHL_PARTS) {
3009 Ops.push_back(Tmp2);
3010 Ops.push_back(Tmp3);
3012 Ops.push_back(InFlag);
3013 Hi = DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size());
3014 InFlag = Hi.getValue(1);
3017 Ops.push_back(Tmp3);
3018 Ops.push_back(Tmp1);
3020 Ops.push_back(InFlag);
3021 Lo = DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size());
3023 Ops.push_back(Tmp2);
3024 Ops.push_back(Tmp3);
3026 Ops.push_back(InFlag);
3027 Lo = DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size());
3028 InFlag = Lo.getValue(1);
3031 Ops.push_back(Tmp3);
3032 Ops.push_back(Tmp1);
3034 Ops.push_back(InFlag);
3035 Hi = DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size());
3038 VTs = DAG.getNodeValueTypes(MVT::i32, MVT::i32);
3042 return DAG.getNode(ISD::MERGE_VALUES, VTs, 2, &Ops[0], Ops.size());
3045 SDOperand X86TargetLowering::LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
3046 assert(Op.getOperand(0).getValueType() <= MVT::i64 &&
3047 Op.getOperand(0).getValueType() >= MVT::i16 &&
3048 "Unknown SINT_TO_FP to lower!");
3051 MVT::ValueType SrcVT = Op.getOperand(0).getValueType();
3052 unsigned Size = MVT::getSizeInBits(SrcVT)/8;
3053 MachineFunction &MF = DAG.getMachineFunction();
3054 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
3055 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
3056 SDOperand Chain = DAG.getStore(DAG.getEntryNode(), Op.getOperand(0),
3057 StackSlot, NULL, 0);
3062 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag);
3064 Tys = DAG.getVTList(MVT::f64, MVT::Other);
3065 SmallVector<SDOperand, 8> Ops;
3066 Ops.push_back(Chain);
3067 Ops.push_back(StackSlot);
3068 Ops.push_back(DAG.getValueType(SrcVT));
3069 Result = DAG.getNode(X86ScalarSSE ? X86ISD::FILD_FLAG :X86ISD::FILD,
3070 Tys, &Ops[0], Ops.size());
3073 Chain = Result.getValue(1);
3074 SDOperand InFlag = Result.getValue(2);
3076 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
3077 // shouldn't be necessary except that RFP cannot be live across
3078 // multiple blocks. When stackifier is fixed, they can be uncoupled.
3079 MachineFunction &MF = DAG.getMachineFunction();
3080 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
3081 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
3082 Tys = DAG.getVTList(MVT::Other);
3083 SmallVector<SDOperand, 8> Ops;
3084 Ops.push_back(Chain);
3085 Ops.push_back(Result);
3086 Ops.push_back(StackSlot);
3087 Ops.push_back(DAG.getValueType(Op.getValueType()));
3088 Ops.push_back(InFlag);
3089 Chain = DAG.getNode(X86ISD::FST, Tys, &Ops[0], Ops.size());
3090 Result = DAG.getLoad(Op.getValueType(), Chain, StackSlot, NULL, 0);
3096 SDOperand X86TargetLowering::LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) {
3097 assert(Op.getValueType() <= MVT::i64 && Op.getValueType() >= MVT::i16 &&
3098 "Unknown FP_TO_SINT to lower!");
3099 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
3101 MachineFunction &MF = DAG.getMachineFunction();
3102 unsigned MemSize = MVT::getSizeInBits(Op.getValueType())/8;
3103 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
3104 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
3107 switch (Op.getValueType()) {
3108 default: assert(0 && "Invalid FP_TO_SINT to lower!");
3109 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
3110 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
3111 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
3114 SDOperand Chain = DAG.getEntryNode();
3115 SDOperand Value = Op.getOperand(0);
3117 assert(Op.getValueType() == MVT::i64 && "Invalid FP_TO_SINT to lower!");
3118 Chain = DAG.getStore(Chain, Value, StackSlot, NULL, 0);
3119 SDVTList Tys = DAG.getVTList(MVT::f64, MVT::Other);
3121 Chain, StackSlot, DAG.getValueType(Op.getOperand(0).getValueType())
3123 Value = DAG.getNode(X86ISD::FLD, Tys, Ops, 3);
3124 Chain = Value.getValue(1);
3125 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
3126 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
3129 // Build the FP_TO_INT*_IN_MEM
3130 SDOperand Ops[] = { Chain, Value, StackSlot };
3131 SDOperand FIST = DAG.getNode(Opc, MVT::Other, Ops, 3);
3134 return DAG.getLoad(Op.getValueType(), FIST, StackSlot, NULL, 0);
3137 SDOperand X86TargetLowering::LowerFABS(SDOperand Op, SelectionDAG &DAG) {
3138 MVT::ValueType VT = Op.getValueType();
3139 const Type *OpNTy = MVT::getTypeForValueType(VT);
3140 std::vector<Constant*> CV;
3141 if (VT == MVT::f64) {
3142 CV.push_back(ConstantFP::get(OpNTy, BitsToDouble(~(1ULL << 63))));
3143 CV.push_back(ConstantFP::get(OpNTy, 0.0));
3145 CV.push_back(ConstantFP::get(OpNTy, BitsToFloat(~(1U << 31))));
3146 CV.push_back(ConstantFP::get(OpNTy, 0.0));
3147 CV.push_back(ConstantFP::get(OpNTy, 0.0));
3148 CV.push_back(ConstantFP::get(OpNTy, 0.0));
3150 Constant *CS = ConstantStruct::get(CV);
3151 SDOperand CPIdx = DAG.getConstantPool(CS, getPointerTy(), 4);
3152 SDVTList Tys = DAG.getVTList(VT, MVT::Other);
3153 SmallVector<SDOperand, 3> Ops;
3154 Ops.push_back(DAG.getEntryNode());
3155 Ops.push_back(CPIdx);
3156 Ops.push_back(DAG.getSrcValue(NULL));
3157 SDOperand Mask = DAG.getNode(X86ISD::LOAD_PACK, Tys, &Ops[0], Ops.size());
3158 return DAG.getNode(X86ISD::FAND, VT, Op.getOperand(0), Mask);
3161 SDOperand X86TargetLowering::LowerFNEG(SDOperand Op, SelectionDAG &DAG) {
3162 MVT::ValueType VT = Op.getValueType();
3163 const Type *OpNTy = MVT::getTypeForValueType(VT);
3164 std::vector<Constant*> CV;
3165 if (VT == MVT::f64) {
3166 CV.push_back(ConstantFP::get(OpNTy, BitsToDouble(1ULL << 63)));
3167 CV.push_back(ConstantFP::get(OpNTy, 0.0));
3169 CV.push_back(ConstantFP::get(OpNTy, BitsToFloat(1U << 31)));
3170 CV.push_back(ConstantFP::get(OpNTy, 0.0));
3171 CV.push_back(ConstantFP::get(OpNTy, 0.0));
3172 CV.push_back(ConstantFP::get(OpNTy, 0.0));
3174 Constant *CS = ConstantStruct::get(CV);
3175 SDOperand CPIdx = DAG.getConstantPool(CS, getPointerTy(), 4);
3176 SDVTList Tys = DAG.getVTList(VT, MVT::Other);
3177 SmallVector<SDOperand, 3> Ops;
3178 Ops.push_back(DAG.getEntryNode());
3179 Ops.push_back(CPIdx);
3180 Ops.push_back(DAG.getSrcValue(NULL));
3181 SDOperand Mask = DAG.getNode(X86ISD::LOAD_PACK, Tys, &Ops[0], Ops.size());
3182 return DAG.getNode(X86ISD::FXOR, VT, Op.getOperand(0), Mask);
3185 SDOperand X86TargetLowering::LowerFCOPYSIGN(SDOperand Op, SelectionDAG &DAG) {
3186 SDOperand Op0 = Op.getOperand(0);
3187 SDOperand Op1 = Op.getOperand(1);
3188 MVT::ValueType VT = Op.getValueType();
3189 MVT::ValueType SrcVT = Op1.getValueType();
3190 const Type *SrcTy = MVT::getTypeForValueType(SrcVT);
3192 // If second operand is smaller, extend it first.
3193 if (MVT::getSizeInBits(SrcVT) < MVT::getSizeInBits(VT)) {
3194 Op1 = DAG.getNode(ISD::FP_EXTEND, VT, Op1);
3198 // First get the sign bit of second operand.
3199 std::vector<Constant*> CV;
3200 if (SrcVT == MVT::f64) {
3201 CV.push_back(ConstantFP::get(SrcTy, BitsToDouble(1ULL << 63)));
3202 CV.push_back(ConstantFP::get(SrcTy, 0.0));
3204 CV.push_back(ConstantFP::get(SrcTy, BitsToFloat(1U << 31)));
3205 CV.push_back(ConstantFP::get(SrcTy, 0.0));
3206 CV.push_back(ConstantFP::get(SrcTy, 0.0));
3207 CV.push_back(ConstantFP::get(SrcTy, 0.0));
3209 Constant *CS = ConstantStruct::get(CV);
3210 SDOperand CPIdx = DAG.getConstantPool(CS, getPointerTy(), 4);
3211 SDVTList Tys = DAG.getVTList(SrcVT, MVT::Other);
3212 SmallVector<SDOperand, 3> Ops;
3213 Ops.push_back(DAG.getEntryNode());
3214 Ops.push_back(CPIdx);
3215 Ops.push_back(DAG.getSrcValue(NULL));
3216 SDOperand Mask1 = DAG.getNode(X86ISD::LOAD_PACK, Tys, &Ops[0], Ops.size());
3217 SDOperand SignBit = DAG.getNode(X86ISD::FAND, SrcVT, Op1, Mask1);
3219 // Shift sign bit right or left if the two operands have different types.
3220 if (MVT::getSizeInBits(SrcVT) > MVT::getSizeInBits(VT)) {
3221 // Op0 is MVT::f32, Op1 is MVT::f64.
3222 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v2f64, SignBit);
3223 SignBit = DAG.getNode(X86ISD::FSRL, MVT::v2f64, SignBit,
3224 DAG.getConstant(32, MVT::i32));
3225 SignBit = DAG.getNode(ISD::BIT_CONVERT, MVT::v4f32, SignBit);
3226 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::f32, SignBit,
3227 DAG.getConstant(0, getPointerTy()));
3230 // Clear first operand sign bit.
3232 if (VT == MVT::f64) {
3233 CV.push_back(ConstantFP::get(SrcTy, BitsToDouble(~(1ULL << 63))));
3234 CV.push_back(ConstantFP::get(SrcTy, 0.0));
3236 CV.push_back(ConstantFP::get(SrcTy, BitsToFloat(~(1U << 31))));
3237 CV.push_back(ConstantFP::get(SrcTy, 0.0));
3238 CV.push_back(ConstantFP::get(SrcTy, 0.0));
3239 CV.push_back(ConstantFP::get(SrcTy, 0.0));
3241 CS = ConstantStruct::get(CV);
3242 CPIdx = DAG.getConstantPool(CS, getPointerTy(), 4);
3243 Tys = DAG.getVTList(VT, MVT::Other);
3245 Ops.push_back(DAG.getEntryNode());
3246 Ops.push_back(CPIdx);
3247 Ops.push_back(DAG.getSrcValue(NULL));
3248 SDOperand Mask2 = DAG.getNode(X86ISD::LOAD_PACK, Tys, &Ops[0], Ops.size());
3249 SDOperand Val = DAG.getNode(X86ISD::FAND, VT, Op0, Mask2);
3251 // Or the value with the sign bit.
3252 return DAG.getNode(X86ISD::FOR, VT, Val, SignBit);
3255 SDOperand X86TargetLowering::LowerSETCC(SDOperand Op, SelectionDAG &DAG,
3257 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
3259 SDOperand Op0 = Op.getOperand(0);
3260 SDOperand Op1 = Op.getOperand(1);
3261 SDOperand CC = Op.getOperand(2);
3262 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
3263 const MVT::ValueType *VTs1 = DAG.getNodeValueTypes(MVT::Other, MVT::Flag);
3264 const MVT::ValueType *VTs2 = DAG.getNodeValueTypes(MVT::i8, MVT::Flag);
3265 bool isFP = MVT::isFloatingPoint(Op.getOperand(1).getValueType());
3268 if (translateX86CC(cast<CondCodeSDNode>(CC)->get(), isFP, X86CC,
3270 SDOperand Ops1[] = { Chain, Op0, Op1 };
3271 Cond = DAG.getNode(X86ISD::CMP, VTs1, 2, Ops1, 3).getValue(1);
3272 SDOperand Ops2[] = { DAG.getConstant(X86CC, MVT::i8), Cond };
3273 return DAG.getNode(X86ISD::SETCC, VTs2, 2, Ops2, 2);
3276 assert(isFP && "Illegal integer SetCC!");
3278 SDOperand COps[] = { Chain, Op0, Op1 };
3279 Cond = DAG.getNode(X86ISD::CMP, VTs1, 2, COps, 3).getValue(1);
3281 switch (SetCCOpcode) {
3282 default: assert(false && "Illegal floating point SetCC!");
3283 case ISD::SETOEQ: { // !PF & ZF
3284 SDOperand Ops1[] = { DAG.getConstant(X86::COND_NP, MVT::i8), Cond };
3285 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, VTs2, 2, Ops1, 2);
3286 SDOperand Ops2[] = { DAG.getConstant(X86::COND_E, MVT::i8),
3288 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, VTs2, 2, Ops2, 2);
3289 return DAG.getNode(ISD::AND, MVT::i8, Tmp1, Tmp2);
3291 case ISD::SETUNE: { // PF | !ZF
3292 SDOperand Ops1[] = { DAG.getConstant(X86::COND_P, MVT::i8), Cond };
3293 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, VTs2, 2, Ops1, 2);
3294 SDOperand Ops2[] = { DAG.getConstant(X86::COND_NE, MVT::i8),
3296 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, VTs2, 2, Ops2, 2);
3297 return DAG.getNode(ISD::OR, MVT::i8, Tmp1, Tmp2);
3302 SDOperand X86TargetLowering::LowerSELECT(SDOperand Op, SelectionDAG &DAG) {
3303 bool addTest = true;
3304 SDOperand Chain = DAG.getEntryNode();
3305 SDOperand Cond = Op.getOperand(0);
3307 const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::Other, MVT::Flag);
3309 if (Cond.getOpcode() == ISD::SETCC)
3310 Cond = LowerSETCC(Cond, DAG, Chain);
3312 if (Cond.getOpcode() == X86ISD::SETCC) {
3313 CC = Cond.getOperand(0);
3315 // If condition flag is set by a X86ISD::CMP, then make a copy of it
3316 // (since flag operand cannot be shared). Use it as the condition setting
3317 // operand in place of the X86ISD::SETCC.
3318 // If the X86ISD::SETCC has more than one use, then perhaps it's better
3319 // to use a test instead of duplicating the X86ISD::CMP (for register
3320 // pressure reason)?
3321 SDOperand Cmp = Cond.getOperand(1);
3322 unsigned Opc = Cmp.getOpcode();
3323 bool IllegalFPCMov = !X86ScalarSSE &&
3324 MVT::isFloatingPoint(Op.getValueType()) &&
3325 !hasFPCMov(cast<ConstantSDNode>(CC)->getSignExtended());
3326 if ((Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI) &&
3328 SDOperand Ops[] = { Chain, Cmp.getOperand(1), Cmp.getOperand(2) };
3329 Cond = DAG.getNode(Opc, VTs, 2, Ops, 3);
3335 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
3336 SDOperand Ops[] = { Chain, Cond, DAG.getConstant(0, MVT::i8) };
3337 Cond = DAG.getNode(X86ISD::CMP, VTs, 2, Ops, 3);
3340 VTs = DAG.getNodeValueTypes(Op.getValueType(), MVT::Flag);
3341 SmallVector<SDOperand, 4> Ops;
3342 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
3343 // condition is true.
3344 Ops.push_back(Op.getOperand(2));
3345 Ops.push_back(Op.getOperand(1));
3347 Ops.push_back(Cond.getValue(1));
3348 return DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size());
3351 SDOperand X86TargetLowering::LowerBRCOND(SDOperand Op, SelectionDAG &DAG) {
3352 bool addTest = true;
3353 SDOperand Chain = Op.getOperand(0);
3354 SDOperand Cond = Op.getOperand(1);
3355 SDOperand Dest = Op.getOperand(2);
3357 const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::Other, MVT::Flag);
3359 if (Cond.getOpcode() == ISD::SETCC)
3360 Cond = LowerSETCC(Cond, DAG, Chain);
3362 if (Cond.getOpcode() == X86ISD::SETCC) {
3363 CC = Cond.getOperand(0);
3365 // If condition flag is set by a X86ISD::CMP, then make a copy of it
3366 // (since flag operand cannot be shared). Use it as the condition setting
3367 // operand in place of the X86ISD::SETCC.
3368 // If the X86ISD::SETCC has more than one use, then perhaps it's better
3369 // to use a test instead of duplicating the X86ISD::CMP (for register
3370 // pressure reason)?
3371 SDOperand Cmp = Cond.getOperand(1);
3372 unsigned Opc = Cmp.getOpcode();
3373 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI) {
3374 SDOperand Ops[] = { Chain, Cmp.getOperand(1), Cmp.getOperand(2) };
3375 Cond = DAG.getNode(Opc, VTs, 2, Ops, 3);
3381 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
3382 SDOperand Ops[] = { Chain, Cond, DAG.getConstant(0, MVT::i8) };
3383 Cond = DAG.getNode(X86ISD::CMP, VTs, 2, Ops, 3);
3385 return DAG.getNode(X86ISD::BRCOND, Op.getValueType(),
3386 Cond, Op.getOperand(2), CC, Cond.getValue(1));
3389 SDOperand X86TargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) {
3390 unsigned CallingConv= cast<ConstantSDNode>(Op.getOperand(1))->getValue();
3392 if (Subtarget->is64Bit())
3393 return LowerX86_64CCCCallTo(Op, DAG, CallingConv);
3395 switch (CallingConv) {
3397 assert(0 && "Unsupported calling convention");
3398 case CallingConv::Fast:
3399 // TODO: Implement fastcc
3401 case CallingConv::C:
3402 case CallingConv::X86_StdCall:
3403 return LowerCCCCallTo(Op, DAG, CallingConv);
3404 case CallingConv::X86_FastCall:
3405 return LowerFastCCCallTo(Op, DAG, CallingConv);
3410 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
3411 // Calls to _alloca is needed to probe the stack when allocating more than 4k
3412 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
3413 // that the guard pages used by the OS virtual memory manager are allocated in
3414 // correct sequence.
3415 SDOperand X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDOperand Op,
3416 SelectionDAG &DAG) {
3417 assert(Subtarget->isTargetCygMing() &&
3418 "This should be used only on Cygwin/Mingw targets");
3421 SDOperand Chain = Op.getOperand(0);
3422 SDOperand Size = Op.getOperand(1);
3423 // FIXME: Ensure alignment here
3425 TargetLowering::ArgListTy Args;
3426 TargetLowering::ArgListEntry Entry;
3427 MVT::ValueType IntPtr = getPointerTy();
3428 MVT::ValueType SPTy = (Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
3429 const Type *IntPtrTy = getTargetData()->getIntPtrType();
3432 Entry.Ty = IntPtrTy;
3433 Entry.isInReg = true; // Should pass in EAX
3434 Args.push_back(Entry);
3435 std::pair<SDOperand, SDOperand> CallResult =
3436 LowerCallTo(Chain, IntPtrTy, false, false, CallingConv::C, false,
3437 DAG.getExternalSymbol("_alloca", IntPtr), Args, DAG);
3439 SDOperand SP = DAG.getCopyFromReg(CallResult.second, X86StackPtr, SPTy);
3441 std::vector<MVT::ValueType> Tys;
3442 Tys.push_back(SPTy);
3443 Tys.push_back(MVT::Other);
3444 SDOperand Ops[2] = { SP, CallResult.second };
3445 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops, 2);
3449 X86TargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) {
3450 MachineFunction &MF = DAG.getMachineFunction();
3451 const Function* Fn = MF.getFunction();
3452 if (Fn->hasExternalLinkage() &&
3453 Subtarget->isTargetCygMing() &&
3454 Fn->getName() == "main")
3455 MF.getInfo<X86MachineFunctionInfo>()->setForceFramePointer(true);
3457 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
3458 if (Subtarget->is64Bit())
3459 return LowerX86_64CCCArguments(Op, DAG);
3463 assert(0 && "Unsupported calling convention");
3464 case CallingConv::Fast:
3465 // TODO: implement fastcc.
3468 case CallingConv::C:
3469 return LowerCCCArguments(Op, DAG);
3470 case CallingConv::X86_StdCall:
3471 MF.getInfo<X86MachineFunctionInfo>()->setDecorationStyle(StdCall);
3472 return LowerCCCArguments(Op, DAG, true);
3473 case CallingConv::X86_FastCall:
3474 MF.getInfo<X86MachineFunctionInfo>()->setDecorationStyle(FastCall);
3475 return LowerFastCCArguments(Op, DAG);
3479 SDOperand X86TargetLowering::LowerMEMSET(SDOperand Op, SelectionDAG &DAG) {
3480 SDOperand InFlag(0, 0);
3481 SDOperand Chain = Op.getOperand(0);
3483 (unsigned)cast<ConstantSDNode>(Op.getOperand(4))->getValue();
3484 if (Align == 0) Align = 1;
3486 ConstantSDNode *I = dyn_cast<ConstantSDNode>(Op.getOperand(3));
3487 // If not DWORD aligned, call memset if size is less than the threshold.
3488 // It knows how to align to the right boundary first.
3489 if ((Align & 3) != 0 ||
3490 (I && I->getValue() < Subtarget->getMinRepStrSizeThreshold())) {
3491 MVT::ValueType IntPtr = getPointerTy();
3492 const Type *IntPtrTy = getTargetData()->getIntPtrType();
3493 TargetLowering::ArgListTy Args;
3494 TargetLowering::ArgListEntry Entry;
3495 Entry.Node = Op.getOperand(1);
3496 Entry.Ty = IntPtrTy;
3497 Args.push_back(Entry);
3498 // Extend the unsigned i8 argument to be an int value for the call.
3499 Entry.Node = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Op.getOperand(2));
3500 Entry.Ty = IntPtrTy;
3501 Args.push_back(Entry);
3502 Entry.Node = Op.getOperand(3);
3503 Args.push_back(Entry);
3504 std::pair<SDOperand,SDOperand> CallResult =
3505 LowerCallTo(Chain, Type::VoidTy, false, false, CallingConv::C, false,
3506 DAG.getExternalSymbol("memset", IntPtr), Args, DAG);
3507 return CallResult.second;
3512 ConstantSDNode *ValC = dyn_cast<ConstantSDNode>(Op.getOperand(2));
3513 unsigned BytesLeft = 0;
3514 bool TwoRepStos = false;
3517 uint64_t Val = ValC->getValue() & 255;
3519 // If the value is a constant, then we can potentially use larger sets.
3520 switch (Align & 3) {
3521 case 2: // WORD aligned
3524 Val = (Val << 8) | Val;
3526 case 0: // DWORD aligned
3529 Val = (Val << 8) | Val;
3530 Val = (Val << 16) | Val;
3531 if (Subtarget->is64Bit() && ((Align & 0xF) == 0)) { // QWORD aligned
3534 Val = (Val << 32) | Val;
3537 default: // Byte aligned
3540 Count = Op.getOperand(3);
3544 if (AVT > MVT::i8) {
3546 unsigned UBytes = MVT::getSizeInBits(AVT) / 8;
3547 Count = DAG.getConstant(I->getValue() / UBytes, getPointerTy());
3548 BytesLeft = I->getValue() % UBytes;
3550 assert(AVT >= MVT::i32 &&
3551 "Do not use rep;stos if not at least DWORD aligned");
3552 Count = DAG.getNode(ISD::SRL, Op.getOperand(3).getValueType(),
3553 Op.getOperand(3), DAG.getConstant(2, MVT::i8));
3558 Chain = DAG.getCopyToReg(Chain, ValReg, DAG.getConstant(Val, AVT),
3560 InFlag = Chain.getValue(1);
3563 Count = Op.getOperand(3);
3564 Chain = DAG.getCopyToReg(Chain, X86::AL, Op.getOperand(2), InFlag);
3565 InFlag = Chain.getValue(1);
3568 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RCX : X86::ECX,
3570 InFlag = Chain.getValue(1);
3571 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RDI : X86::EDI,
3572 Op.getOperand(1), InFlag);
3573 InFlag = Chain.getValue(1);
3575 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
3576 SmallVector<SDOperand, 8> Ops;
3577 Ops.push_back(Chain);
3578 Ops.push_back(DAG.getValueType(AVT));
3579 Ops.push_back(InFlag);
3580 Chain = DAG.getNode(X86ISD::REP_STOS, Tys, &Ops[0], Ops.size());
3583 InFlag = Chain.getValue(1);
3584 Count = Op.getOperand(3);
3585 MVT::ValueType CVT = Count.getValueType();
3586 SDOperand Left = DAG.getNode(ISD::AND, CVT, Count,
3587 DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT));
3588 Chain = DAG.getCopyToReg(Chain, (CVT == MVT::i64) ? X86::RCX : X86::ECX,
3590 InFlag = Chain.getValue(1);
3591 Tys = DAG.getVTList(MVT::Other, MVT::Flag);
3593 Ops.push_back(Chain);
3594 Ops.push_back(DAG.getValueType(MVT::i8));
3595 Ops.push_back(InFlag);
3596 Chain = DAG.getNode(X86ISD::REP_STOS, Tys, &Ops[0], Ops.size());
3597 } else if (BytesLeft) {
3598 // Issue stores for the last 1 - 7 bytes.
3600 unsigned Val = ValC->getValue() & 255;
3601 unsigned Offset = I->getValue() - BytesLeft;
3602 SDOperand DstAddr = Op.getOperand(1);
3603 MVT::ValueType AddrVT = DstAddr.getValueType();
3604 if (BytesLeft >= 4) {
3605 Val = (Val << 8) | Val;
3606 Val = (Val << 16) | Val;
3607 Value = DAG.getConstant(Val, MVT::i32);
3608 Chain = DAG.getStore(Chain, Value,
3609 DAG.getNode(ISD::ADD, AddrVT, DstAddr,
3610 DAG.getConstant(Offset, AddrVT)),
3615 if (BytesLeft >= 2) {
3616 Value = DAG.getConstant((Val << 8) | Val, MVT::i16);
3617 Chain = DAG.getStore(Chain, Value,
3618 DAG.getNode(ISD::ADD, AddrVT, DstAddr,
3619 DAG.getConstant(Offset, AddrVT)),
3624 if (BytesLeft == 1) {
3625 Value = DAG.getConstant(Val, MVT::i8);
3626 Chain = DAG.getStore(Chain, Value,
3627 DAG.getNode(ISD::ADD, AddrVT, DstAddr,
3628 DAG.getConstant(Offset, AddrVT)),
3636 SDOperand X86TargetLowering::LowerMEMCPY(SDOperand Op, SelectionDAG &DAG) {
3637 SDOperand Chain = Op.getOperand(0);
3639 (unsigned)cast<ConstantSDNode>(Op.getOperand(4))->getValue();
3640 if (Align == 0) Align = 1;
3642 ConstantSDNode *I = dyn_cast<ConstantSDNode>(Op.getOperand(3));
3643 // If not DWORD aligned, call memcpy if size is less than the threshold.
3644 // It knows how to align to the right boundary first.
3645 if ((Align & 3) != 0 ||
3646 (I && I->getValue() < Subtarget->getMinRepStrSizeThreshold())) {
3647 MVT::ValueType IntPtr = getPointerTy();
3648 TargetLowering::ArgListTy Args;
3649 TargetLowering::ArgListEntry Entry;
3650 Entry.Ty = getTargetData()->getIntPtrType();
3651 Entry.Node = Op.getOperand(1); Args.push_back(Entry);
3652 Entry.Node = Op.getOperand(2); Args.push_back(Entry);
3653 Entry.Node = Op.getOperand(3); Args.push_back(Entry);
3654 std::pair<SDOperand,SDOperand> CallResult =
3655 LowerCallTo(Chain, Type::VoidTy, false, false, CallingConv::C, false,
3656 DAG.getExternalSymbol("memcpy", IntPtr), Args, DAG);
3657 return CallResult.second;
3662 unsigned BytesLeft = 0;
3663 bool TwoRepMovs = false;
3664 switch (Align & 3) {
3665 case 2: // WORD aligned
3668 case 0: // DWORD aligned
3670 if (Subtarget->is64Bit() && ((Align & 0xF) == 0)) // QWORD aligned
3673 default: // Byte aligned
3675 Count = Op.getOperand(3);
3679 if (AVT > MVT::i8) {
3681 unsigned UBytes = MVT::getSizeInBits(AVT) / 8;
3682 Count = DAG.getConstant(I->getValue() / UBytes, getPointerTy());
3683 BytesLeft = I->getValue() % UBytes;
3685 assert(AVT >= MVT::i32 &&
3686 "Do not use rep;movs if not at least DWORD aligned");
3687 Count = DAG.getNode(ISD::SRL, Op.getOperand(3).getValueType(),
3688 Op.getOperand(3), DAG.getConstant(2, MVT::i8));
3693 SDOperand InFlag(0, 0);
3694 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RCX : X86::ECX,
3696 InFlag = Chain.getValue(1);
3697 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RDI : X86::EDI,
3698 Op.getOperand(1), InFlag);
3699 InFlag = Chain.getValue(1);
3700 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RSI : X86::ESI,
3701 Op.getOperand(2), InFlag);
3702 InFlag = Chain.getValue(1);
3704 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
3705 SmallVector<SDOperand, 8> Ops;
3706 Ops.push_back(Chain);
3707 Ops.push_back(DAG.getValueType(AVT));
3708 Ops.push_back(InFlag);
3709 Chain = DAG.getNode(X86ISD::REP_MOVS, Tys, &Ops[0], Ops.size());
3712 InFlag = Chain.getValue(1);
3713 Count = Op.getOperand(3);
3714 MVT::ValueType CVT = Count.getValueType();
3715 SDOperand Left = DAG.getNode(ISD::AND, CVT, Count,
3716 DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT));
3717 Chain = DAG.getCopyToReg(Chain, (CVT == MVT::i64) ? X86::RCX : X86::ECX,
3719 InFlag = Chain.getValue(1);
3720 Tys = DAG.getVTList(MVT::Other, MVT::Flag);
3722 Ops.push_back(Chain);
3723 Ops.push_back(DAG.getValueType(MVT::i8));
3724 Ops.push_back(InFlag);
3725 Chain = DAG.getNode(X86ISD::REP_MOVS, Tys, &Ops[0], Ops.size());
3726 } else if (BytesLeft) {
3727 // Issue loads and stores for the last 1 - 7 bytes.
3728 unsigned Offset = I->getValue() - BytesLeft;
3729 SDOperand DstAddr = Op.getOperand(1);
3730 MVT::ValueType DstVT = DstAddr.getValueType();
3731 SDOperand SrcAddr = Op.getOperand(2);
3732 MVT::ValueType SrcVT = SrcAddr.getValueType();
3734 if (BytesLeft >= 4) {
3735 Value = DAG.getLoad(MVT::i32, Chain,
3736 DAG.getNode(ISD::ADD, SrcVT, SrcAddr,
3737 DAG.getConstant(Offset, SrcVT)),
3739 Chain = Value.getValue(1);
3740 Chain = DAG.getStore(Chain, Value,
3741 DAG.getNode(ISD::ADD, DstVT, DstAddr,
3742 DAG.getConstant(Offset, DstVT)),
3747 if (BytesLeft >= 2) {
3748 Value = DAG.getLoad(MVT::i16, Chain,
3749 DAG.getNode(ISD::ADD, SrcVT, SrcAddr,
3750 DAG.getConstant(Offset, SrcVT)),
3752 Chain = Value.getValue(1);
3753 Chain = DAG.getStore(Chain, Value,
3754 DAG.getNode(ISD::ADD, DstVT, DstAddr,
3755 DAG.getConstant(Offset, DstVT)),
3761 if (BytesLeft == 1) {
3762 Value = DAG.getLoad(MVT::i8, Chain,
3763 DAG.getNode(ISD::ADD, SrcVT, SrcAddr,
3764 DAG.getConstant(Offset, SrcVT)),
3766 Chain = Value.getValue(1);
3767 Chain = DAG.getStore(Chain, Value,
3768 DAG.getNode(ISD::ADD, DstVT, DstAddr,
3769 DAG.getConstant(Offset, DstVT)),
3778 X86TargetLowering::LowerREADCYCLCECOUNTER(SDOperand Op, SelectionDAG &DAG) {
3779 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
3780 SDOperand TheOp = Op.getOperand(0);
3781 SDOperand rd = DAG.getNode(X86ISD::RDTSC_DAG, Tys, &TheOp, 1);
3782 if (Subtarget->is64Bit()) {
3783 SDOperand Copy1 = DAG.getCopyFromReg(rd, X86::RAX, MVT::i64, rd.getValue(1));
3784 SDOperand Copy2 = DAG.getCopyFromReg(Copy1.getValue(1), X86::RDX,
3785 MVT::i64, Copy1.getValue(2));
3786 SDOperand Tmp = DAG.getNode(ISD::SHL, MVT::i64, Copy2,
3787 DAG.getConstant(32, MVT::i8));
3789 DAG.getNode(ISD::OR, MVT::i64, Copy1, Tmp), Copy2.getValue(1)
3792 Tys = DAG.getVTList(MVT::i64, MVT::Other);
3793 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops, 2);
3796 SDOperand Copy1 = DAG.getCopyFromReg(rd, X86::EAX, MVT::i32, rd.getValue(1));
3797 SDOperand Copy2 = DAG.getCopyFromReg(Copy1.getValue(1), X86::EDX,
3798 MVT::i32, Copy1.getValue(2));
3799 SDOperand Ops[] = { Copy1, Copy2, Copy2.getValue(1) };
3800 Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
3801 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops, 3);
3804 SDOperand X86TargetLowering::LowerVASTART(SDOperand Op, SelectionDAG &DAG) {
3805 SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2));
3807 if (!Subtarget->is64Bit()) {
3808 // vastart just stores the address of the VarArgsFrameIndex slot into the
3809 // memory location argument.
3810 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
3811 return DAG.getStore(Op.getOperand(0), FR,Op.getOperand(1), SV->getValue(),
3816 // gp_offset (0 - 6 * 8)
3817 // fp_offset (48 - 48 + 8 * 16)
3818 // overflow_arg_area (point to parameters coming in memory).
3820 SmallVector<SDOperand, 8> MemOps;
3821 SDOperand FIN = Op.getOperand(1);
3823 SDOperand Store = DAG.getStore(Op.getOperand(0),
3824 DAG.getConstant(VarArgsGPOffset, MVT::i32),
3825 FIN, SV->getValue(), SV->getOffset());
3826 MemOps.push_back(Store);
3829 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
3830 DAG.getConstant(4, getPointerTy()));
3831 Store = DAG.getStore(Op.getOperand(0),
3832 DAG.getConstant(VarArgsFPOffset, MVT::i32),
3833 FIN, SV->getValue(), SV->getOffset());
3834 MemOps.push_back(Store);
3836 // Store ptr to overflow_arg_area
3837 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
3838 DAG.getConstant(4, getPointerTy()));
3839 SDOperand OVFIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
3840 Store = DAG.getStore(Op.getOperand(0), OVFIN, FIN, SV->getValue(),
3842 MemOps.push_back(Store);
3844 // Store ptr to reg_save_area.
3845 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
3846 DAG.getConstant(8, getPointerTy()));
3847 SDOperand RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
3848 Store = DAG.getStore(Op.getOperand(0), RSFIN, FIN, SV->getValue(),
3850 MemOps.push_back(Store);
3851 return DAG.getNode(ISD::TokenFactor, MVT::Other, &MemOps[0], MemOps.size());
3854 SDOperand X86TargetLowering::LowerVACOPY(SDOperand Op, SelectionDAG &DAG) {
3855 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
3856 SDOperand Chain = Op.getOperand(0);
3857 SDOperand DstPtr = Op.getOperand(1);
3858 SDOperand SrcPtr = Op.getOperand(2);
3859 SrcValueSDNode *DstSV = cast<SrcValueSDNode>(Op.getOperand(3));
3860 SrcValueSDNode *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4));
3862 SrcPtr = DAG.getLoad(getPointerTy(), Chain, SrcPtr,
3863 SrcSV->getValue(), SrcSV->getOffset());
3864 Chain = SrcPtr.getValue(1);
3865 for (unsigned i = 0; i < 3; ++i) {
3866 SDOperand Val = DAG.getLoad(MVT::i64, Chain, SrcPtr,
3867 SrcSV->getValue(), SrcSV->getOffset());
3868 Chain = Val.getValue(1);
3869 Chain = DAG.getStore(Chain, Val, DstPtr,
3870 DstSV->getValue(), DstSV->getOffset());
3873 SrcPtr = DAG.getNode(ISD::ADD, getPointerTy(), SrcPtr,
3874 DAG.getConstant(8, getPointerTy()));
3875 DstPtr = DAG.getNode(ISD::ADD, getPointerTy(), DstPtr,
3876 DAG.getConstant(8, getPointerTy()));
3882 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG) {
3883 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getValue();
3885 default: return SDOperand(); // Don't custom lower most intrinsics.
3886 // Comparison intrinsics.
3887 case Intrinsic::x86_sse_comieq_ss:
3888 case Intrinsic::x86_sse_comilt_ss:
3889 case Intrinsic::x86_sse_comile_ss:
3890 case Intrinsic::x86_sse_comigt_ss:
3891 case Intrinsic::x86_sse_comige_ss:
3892 case Intrinsic::x86_sse_comineq_ss:
3893 case Intrinsic::x86_sse_ucomieq_ss:
3894 case Intrinsic::x86_sse_ucomilt_ss:
3895 case Intrinsic::x86_sse_ucomile_ss:
3896 case Intrinsic::x86_sse_ucomigt_ss:
3897 case Intrinsic::x86_sse_ucomige_ss:
3898 case Intrinsic::x86_sse_ucomineq_ss:
3899 case Intrinsic::x86_sse2_comieq_sd:
3900 case Intrinsic::x86_sse2_comilt_sd:
3901 case Intrinsic::x86_sse2_comile_sd:
3902 case Intrinsic::x86_sse2_comigt_sd:
3903 case Intrinsic::x86_sse2_comige_sd:
3904 case Intrinsic::x86_sse2_comineq_sd:
3905 case Intrinsic::x86_sse2_ucomieq_sd:
3906 case Intrinsic::x86_sse2_ucomilt_sd:
3907 case Intrinsic::x86_sse2_ucomile_sd:
3908 case Intrinsic::x86_sse2_ucomigt_sd:
3909 case Intrinsic::x86_sse2_ucomige_sd:
3910 case Intrinsic::x86_sse2_ucomineq_sd: {
3912 ISD::CondCode CC = ISD::SETCC_INVALID;
3915 case Intrinsic::x86_sse_comieq_ss:
3916 case Intrinsic::x86_sse2_comieq_sd:
3920 case Intrinsic::x86_sse_comilt_ss:
3921 case Intrinsic::x86_sse2_comilt_sd:
3925 case Intrinsic::x86_sse_comile_ss:
3926 case Intrinsic::x86_sse2_comile_sd:
3930 case Intrinsic::x86_sse_comigt_ss:
3931 case Intrinsic::x86_sse2_comigt_sd:
3935 case Intrinsic::x86_sse_comige_ss:
3936 case Intrinsic::x86_sse2_comige_sd:
3940 case Intrinsic::x86_sse_comineq_ss:
3941 case Intrinsic::x86_sse2_comineq_sd:
3945 case Intrinsic::x86_sse_ucomieq_ss:
3946 case Intrinsic::x86_sse2_ucomieq_sd:
3947 Opc = X86ISD::UCOMI;
3950 case Intrinsic::x86_sse_ucomilt_ss:
3951 case Intrinsic::x86_sse2_ucomilt_sd:
3952 Opc = X86ISD::UCOMI;
3955 case Intrinsic::x86_sse_ucomile_ss:
3956 case Intrinsic::x86_sse2_ucomile_sd:
3957 Opc = X86ISD::UCOMI;
3960 case Intrinsic::x86_sse_ucomigt_ss:
3961 case Intrinsic::x86_sse2_ucomigt_sd:
3962 Opc = X86ISD::UCOMI;
3965 case Intrinsic::x86_sse_ucomige_ss:
3966 case Intrinsic::x86_sse2_ucomige_sd:
3967 Opc = X86ISD::UCOMI;
3970 case Intrinsic::x86_sse_ucomineq_ss:
3971 case Intrinsic::x86_sse2_ucomineq_sd:
3972 Opc = X86ISD::UCOMI;
3978 SDOperand LHS = Op.getOperand(1);
3979 SDOperand RHS = Op.getOperand(2);
3980 translateX86CC(CC, true, X86CC, LHS, RHS, DAG);
3982 const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::Other, MVT::Flag);
3983 SDOperand Ops1[] = { DAG.getEntryNode(), LHS, RHS };
3984 SDOperand Cond = DAG.getNode(Opc, VTs, 2, Ops1, 3);
3985 VTs = DAG.getNodeValueTypes(MVT::i8, MVT::Flag);
3986 SDOperand Ops2[] = { DAG.getConstant(X86CC, MVT::i8), Cond };
3987 SDOperand SetCC = DAG.getNode(X86ISD::SETCC, VTs, 2, Ops2, 2);
3988 return DAG.getNode(ISD::ANY_EXTEND, MVT::i32, SetCC);
3993 SDOperand X86TargetLowering::LowerRETURNADDR(SDOperand Op, SelectionDAG &DAG) {
3994 // Depths > 0 not supported yet!
3995 if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0)
3998 // Just load the return address
3999 SDOperand RetAddrFI = getReturnAddressFrameIndex(DAG);
4000 return DAG.getLoad(getPointerTy(), DAG.getEntryNode(), RetAddrFI, NULL, 0);
4003 SDOperand X86TargetLowering::LowerFRAMEADDR(SDOperand Op, SelectionDAG &DAG) {
4004 // Depths > 0 not supported yet!
4005 if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0)
4008 SDOperand RetAddrFI = getReturnAddressFrameIndex(DAG);
4009 return DAG.getNode(ISD::SUB, getPointerTy(), RetAddrFI,
4010 DAG.getConstant(4, getPointerTy()));
4013 /// LowerOperation - Provide custom lowering hooks for some operations.
4015 SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
4016 switch (Op.getOpcode()) {
4017 default: assert(0 && "Should not custom lower this!");
4018 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
4019 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
4020 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
4021 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
4022 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
4023 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
4024 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
4025 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
4026 case ISD::SHL_PARTS:
4027 case ISD::SRA_PARTS:
4028 case ISD::SRL_PARTS: return LowerShift(Op, DAG);
4029 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
4030 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
4031 case ISD::FABS: return LowerFABS(Op, DAG);
4032 case ISD::FNEG: return LowerFNEG(Op, DAG);
4033 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
4034 case ISD::SETCC: return LowerSETCC(Op, DAG, DAG.getEntryNode());
4035 case ISD::SELECT: return LowerSELECT(Op, DAG);
4036 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
4037 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
4038 case ISD::CALL: return LowerCALL(Op, DAG);
4039 case ISD::RET: return LowerRET(Op, DAG);
4040 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
4041 case ISD::MEMSET: return LowerMEMSET(Op, DAG);
4042 case ISD::MEMCPY: return LowerMEMCPY(Op, DAG);
4043 case ISD::READCYCLECOUNTER: return LowerREADCYCLCECOUNTER(Op, DAG);
4044 case ISD::VASTART: return LowerVASTART(Op, DAG);
4045 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
4046 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
4047 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
4048 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
4049 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
4054 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
4056 default: return NULL;
4057 case X86ISD::SHLD: return "X86ISD::SHLD";
4058 case X86ISD::SHRD: return "X86ISD::SHRD";
4059 case X86ISD::FAND: return "X86ISD::FAND";
4060 case X86ISD::FOR: return "X86ISD::FOR";
4061 case X86ISD::FXOR: return "X86ISD::FXOR";
4062 case X86ISD::FSRL: return "X86ISD::FSRL";
4063 case X86ISD::FILD: return "X86ISD::FILD";
4064 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
4065 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
4066 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
4067 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
4068 case X86ISD::FLD: return "X86ISD::FLD";
4069 case X86ISD::FST: return "X86ISD::FST";
4070 case X86ISD::FP_GET_RESULT: return "X86ISD::FP_GET_RESULT";
4071 case X86ISD::FP_SET_RESULT: return "X86ISD::FP_SET_RESULT";
4072 case X86ISD::CALL: return "X86ISD::CALL";
4073 case X86ISD::TAILCALL: return "X86ISD::TAILCALL";
4074 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
4075 case X86ISD::CMP: return "X86ISD::CMP";
4076 case X86ISD::COMI: return "X86ISD::COMI";
4077 case X86ISD::UCOMI: return "X86ISD::UCOMI";
4078 case X86ISD::SETCC: return "X86ISD::SETCC";
4079 case X86ISD::CMOV: return "X86ISD::CMOV";
4080 case X86ISD::BRCOND: return "X86ISD::BRCOND";
4081 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
4082 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
4083 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
4084 case X86ISD::LOAD_PACK: return "X86ISD::LOAD_PACK";
4085 case X86ISD::LOAD_UA: return "X86ISD::LOAD_UA";
4086 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
4087 case X86ISD::Wrapper: return "X86ISD::Wrapper";
4088 case X86ISD::S2VEC: return "X86ISD::S2VEC";
4089 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
4090 case X86ISD::PINSRW: return "X86ISD::PINSRW";
4091 case X86ISD::FMAX: return "X86ISD::FMAX";
4092 case X86ISD::FMIN: return "X86ISD::FMIN";
4096 // isLegalAddressingMode - Return true if the addressing mode represented
4097 // by AM is legal for this target, for a load/store of the specified type.
4098 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
4099 const Type *Ty) const {
4100 // X86 supports extremely general addressing modes.
4102 // X86 allows a sign-extended 32-bit immediate field as a displacement.
4103 if (AM.BaseOffs <= -(1LL << 32) || AM.BaseOffs >= (1LL << 32)-1)
4107 // X86-64 only supports addr of globals in small code model.
4108 if (Subtarget->is64Bit() &&
4109 getTargetMachine().getCodeModel() != CodeModel::Small)
4112 // We can only fold this if we don't need a load either.
4113 if (Subtarget->GVRequiresExtraLoad(AM.BaseGV, getTargetMachine(), false))
4123 // These scales always work.
4128 // These scales are formed with basereg+scalereg. Only accept if there is
4133 default: // Other stuff never works.
4141 /// isShuffleMaskLegal - Targets can use this to indicate that they only
4142 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
4143 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
4144 /// are assumed to be legal.
4146 X86TargetLowering::isShuffleMaskLegal(SDOperand Mask, MVT::ValueType VT) const {
4147 // Only do shuffles on 128-bit vector types for now.
4148 if (MVT::getSizeInBits(VT) == 64) return false;
4149 return (Mask.Val->getNumOperands() <= 4 ||
4150 isSplatMask(Mask.Val) ||
4151 isPSHUFHW_PSHUFLWMask(Mask.Val) ||
4152 X86::isUNPCKLMask(Mask.Val) ||
4153 X86::isUNPCKL_v_undef_Mask(Mask.Val) ||
4154 X86::isUNPCKHMask(Mask.Val));
4157 bool X86TargetLowering::isVectorClearMaskLegal(std::vector<SDOperand> &BVOps,
4159 SelectionDAG &DAG) const {
4160 unsigned NumElts = BVOps.size();
4161 // Only do shuffles on 128-bit vector types for now.
4162 if (MVT::getSizeInBits(EVT) * NumElts == 64) return false;
4163 if (NumElts == 2) return true;
4165 return (isMOVLMask(&BVOps[0], 4) ||
4166 isCommutedMOVL(&BVOps[0], 4, true) ||
4167 isSHUFPMask(&BVOps[0], 4) ||
4168 isCommutedSHUFP(&BVOps[0], 4));
4173 //===----------------------------------------------------------------------===//
4174 // X86 Scheduler Hooks
4175 //===----------------------------------------------------------------------===//
4178 X86TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
4179 MachineBasicBlock *BB) {
4180 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4181 switch (MI->getOpcode()) {
4182 default: assert(false && "Unexpected instr type to insert");
4183 case X86::CMOV_FR32:
4184 case X86::CMOV_FR64:
4185 case X86::CMOV_V4F32:
4186 case X86::CMOV_V2F64:
4187 case X86::CMOV_V2I64: {
4188 // To "insert" a SELECT_CC instruction, we actually have to insert the
4189 // diamond control-flow pattern. The incoming instruction knows the
4190 // destination vreg to set, the condition code register to branch on, the
4191 // true/false values to select between, and a branch opcode to use.
4192 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4193 ilist<MachineBasicBlock>::iterator It = BB;
4199 // cmpTY ccX, r1, r2
4201 // fallthrough --> copy0MBB
4202 MachineBasicBlock *thisMBB = BB;
4203 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
4204 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
4206 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
4207 BuildMI(BB, TII->get(Opc)).addMBB(sinkMBB);
4208 MachineFunction *F = BB->getParent();
4209 F->getBasicBlockList().insert(It, copy0MBB);
4210 F->getBasicBlockList().insert(It, sinkMBB);
4211 // Update machine-CFG edges by first adding all successors of the current
4212 // block to the new block which will contain the Phi node for the select.
4213 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
4214 e = BB->succ_end(); i != e; ++i)
4215 sinkMBB->addSuccessor(*i);
4216 // Next, remove all successors of the current block, and add the true
4217 // and fallthrough blocks as its successors.
4218 while(!BB->succ_empty())
4219 BB->removeSuccessor(BB->succ_begin());
4220 BB->addSuccessor(copy0MBB);
4221 BB->addSuccessor(sinkMBB);
4224 // %FalseValue = ...
4225 // # fallthrough to sinkMBB
4228 // Update machine-CFG edges
4229 BB->addSuccessor(sinkMBB);
4232 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
4235 BuildMI(BB, TII->get(X86::PHI), MI->getOperand(0).getReg())
4236 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
4237 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
4239 delete MI; // The pseudo instruction is gone now.
4243 case X86::FP_TO_INT16_IN_MEM:
4244 case X86::FP_TO_INT32_IN_MEM:
4245 case X86::FP_TO_INT64_IN_MEM: {
4246 // Change the floating point control register to use "round towards zero"
4247 // mode when truncating to an integer value.
4248 MachineFunction *F = BB->getParent();
4249 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2);
4250 addFrameReference(BuildMI(BB, TII->get(X86::FNSTCW16m)), CWFrameIdx);
4252 // Load the old value of the high byte of the control word...
4254 F->getSSARegMap()->createVirtualRegister(X86::GR16RegisterClass);
4255 addFrameReference(BuildMI(BB, TII->get(X86::MOV16rm), OldCW), CWFrameIdx);
4257 // Set the high part to be round to zero...
4258 addFrameReference(BuildMI(BB, TII->get(X86::MOV16mi)), CWFrameIdx)
4261 // Reload the modified control word now...
4262 addFrameReference(BuildMI(BB, TII->get(X86::FLDCW16m)), CWFrameIdx);
4264 // Restore the memory image of control word to original value
4265 addFrameReference(BuildMI(BB, TII->get(X86::MOV16mr)), CWFrameIdx)
4268 // Get the X86 opcode to use.
4270 switch (MI->getOpcode()) {
4271 default: assert(0 && "illegal opcode!");
4272 case X86::FP_TO_INT16_IN_MEM: Opc = X86::FpIST16m; break;
4273 case X86::FP_TO_INT32_IN_MEM: Opc = X86::FpIST32m; break;
4274 case X86::FP_TO_INT64_IN_MEM: Opc = X86::FpIST64m; break;
4278 MachineOperand &Op = MI->getOperand(0);
4279 if (Op.isRegister()) {
4280 AM.BaseType = X86AddressMode::RegBase;
4281 AM.Base.Reg = Op.getReg();
4283 AM.BaseType = X86AddressMode::FrameIndexBase;
4284 AM.Base.FrameIndex = Op.getFrameIndex();
4286 Op = MI->getOperand(1);
4287 if (Op.isImmediate())
4288 AM.Scale = Op.getImm();
4289 Op = MI->getOperand(2);
4290 if (Op.isImmediate())
4291 AM.IndexReg = Op.getImm();
4292 Op = MI->getOperand(3);
4293 if (Op.isGlobalAddress()) {
4294 AM.GV = Op.getGlobal();
4296 AM.Disp = Op.getImm();
4298 addFullAddress(BuildMI(BB, TII->get(Opc)), AM)
4299 .addReg(MI->getOperand(4).getReg());
4301 // Reload the original control word now.
4302 addFrameReference(BuildMI(BB, TII->get(X86::FLDCW16m)), CWFrameIdx);
4304 delete MI; // The pseudo instruction is gone now.
4310 //===----------------------------------------------------------------------===//
4311 // X86 Optimization Hooks
4312 //===----------------------------------------------------------------------===//
4314 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
4316 uint64_t &KnownZero,
4318 unsigned Depth) const {
4319 unsigned Opc = Op.getOpcode();
4320 assert((Opc >= ISD::BUILTIN_OP_END ||
4321 Opc == ISD::INTRINSIC_WO_CHAIN ||
4322 Opc == ISD::INTRINSIC_W_CHAIN ||
4323 Opc == ISD::INTRINSIC_VOID) &&
4324 "Should use MaskedValueIsZero if you don't know whether Op"
4325 " is a target node!");
4327 KnownZero = KnownOne = 0; // Don't know anything.
4331 KnownZero |= (MVT::getIntVTBitMask(Op.getValueType()) ^ 1ULL);
4336 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
4337 /// element of the result of the vector shuffle.
4338 static SDOperand getShuffleScalarElt(SDNode *N, unsigned i, SelectionDAG &DAG) {
4339 MVT::ValueType VT = N->getValueType(0);
4340 SDOperand PermMask = N->getOperand(2);
4341 unsigned NumElems = PermMask.getNumOperands();
4342 SDOperand V = (i < NumElems) ? N->getOperand(0) : N->getOperand(1);
4344 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR) {
4346 ? V.getOperand(0) : DAG.getNode(ISD::UNDEF, MVT::getVectorBaseType(VT));
4347 } else if (V.getOpcode() == ISD::VECTOR_SHUFFLE) {
4348 SDOperand Idx = PermMask.getOperand(i);
4349 if (Idx.getOpcode() == ISD::UNDEF)
4350 return DAG.getNode(ISD::UNDEF, MVT::getVectorBaseType(VT));
4351 return getShuffleScalarElt(V.Val,cast<ConstantSDNode>(Idx)->getValue(),DAG);
4356 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
4357 /// node is a GlobalAddress + an offset.
4358 static bool isGAPlusOffset(SDNode *N, GlobalValue* &GA, int64_t &Offset) {
4359 unsigned Opc = N->getOpcode();
4360 if (Opc == X86ISD::Wrapper) {
4361 if (dyn_cast<GlobalAddressSDNode>(N->getOperand(0))) {
4362 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
4365 } else if (Opc == ISD::ADD) {
4366 SDOperand N1 = N->getOperand(0);
4367 SDOperand N2 = N->getOperand(1);
4368 if (isGAPlusOffset(N1.Val, GA, Offset)) {
4369 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2);
4371 Offset += V->getSignExtended();
4374 } else if (isGAPlusOffset(N2.Val, GA, Offset)) {
4375 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1);
4377 Offset += V->getSignExtended();
4385 /// isConsecutiveLoad - Returns true if N is loading from an address of Base
4387 static bool isConsecutiveLoad(SDNode *N, SDNode *Base, int Dist, int Size,
4388 MachineFrameInfo *MFI) {
4389 if (N->getOperand(0).Val != Base->getOperand(0).Val)
4392 SDOperand Loc = N->getOperand(1);
4393 SDOperand BaseLoc = Base->getOperand(1);
4394 if (Loc.getOpcode() == ISD::FrameIndex) {
4395 if (BaseLoc.getOpcode() != ISD::FrameIndex)
4397 int FI = dyn_cast<FrameIndexSDNode>(Loc)->getIndex();
4398 int BFI = dyn_cast<FrameIndexSDNode>(BaseLoc)->getIndex();
4399 int FS = MFI->getObjectSize(FI);
4400 int BFS = MFI->getObjectSize(BFI);
4401 if (FS != BFS || FS != Size) return false;
4402 return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) + Dist*Size);
4404 GlobalValue *GV1 = NULL;
4405 GlobalValue *GV2 = NULL;
4406 int64_t Offset1 = 0;
4407 int64_t Offset2 = 0;
4408 bool isGA1 = isGAPlusOffset(Loc.Val, GV1, Offset1);
4409 bool isGA2 = isGAPlusOffset(BaseLoc.Val, GV2, Offset2);
4410 if (isGA1 && isGA2 && GV1 == GV2)
4411 return Offset1 == (Offset2 + Dist*Size);
4417 static bool isBaseAlignment16(SDNode *Base, MachineFrameInfo *MFI,
4418 const X86Subtarget *Subtarget) {
4421 if (isGAPlusOffset(Base, GV, Offset))
4422 return (GV->getAlignment() >= 16 && (Offset % 16) == 0);
4424 assert(Base->getOpcode() == ISD::FrameIndex && "Unexpected base node!");
4425 int BFI = dyn_cast<FrameIndexSDNode>(Base)->getIndex();
4427 // Fixed objects do not specify alignment, however the offsets are known.
4428 return ((Subtarget->getStackAlignment() % 16) == 0 &&
4429 (MFI->getObjectOffset(BFI) % 16) == 0);
4431 return MFI->getObjectAlignment(BFI) >= 16;
4437 /// PerformShuffleCombine - Combine a vector_shuffle that is equal to
4438 /// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load
4439 /// if the load addresses are consecutive, non-overlapping, and in the right
4441 static SDOperand PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
4442 const X86Subtarget *Subtarget) {
4443 MachineFunction &MF = DAG.getMachineFunction();
4444 MachineFrameInfo *MFI = MF.getFrameInfo();
4445 MVT::ValueType VT = N->getValueType(0);
4446 MVT::ValueType EVT = MVT::getVectorBaseType(VT);
4447 SDOperand PermMask = N->getOperand(2);
4448 int NumElems = (int)PermMask.getNumOperands();
4449 SDNode *Base = NULL;
4450 for (int i = 0; i < NumElems; ++i) {
4451 SDOperand Idx = PermMask.getOperand(i);
4452 if (Idx.getOpcode() == ISD::UNDEF) {
4453 if (!Base) return SDOperand();
4456 getShuffleScalarElt(N, cast<ConstantSDNode>(Idx)->getValue(), DAG);
4457 if (!Arg.Val || !ISD::isNON_EXTLoad(Arg.Val))
4461 else if (!isConsecutiveLoad(Arg.Val, Base,
4462 i, MVT::getSizeInBits(EVT)/8,MFI))
4467 bool isAlign16 = isBaseAlignment16(Base->getOperand(1).Val, MFI, Subtarget);
4469 LoadSDNode *LD = cast<LoadSDNode>(Base);
4470 return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(), LD->getSrcValue(),
4471 LD->getSrcValueOffset());
4473 // Just use movups, it's shorter.
4474 SDVTList Tys = DAG.getVTList(MVT::v4f32, MVT::Other);
4475 SmallVector<SDOperand, 3> Ops;
4476 Ops.push_back(Base->getOperand(0));
4477 Ops.push_back(Base->getOperand(1));
4478 Ops.push_back(Base->getOperand(2));
4479 return DAG.getNode(ISD::BIT_CONVERT, VT,
4480 DAG.getNode(X86ISD::LOAD_UA, Tys, &Ops[0], Ops.size()));
4484 /// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes.
4485 static SDOperand PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
4486 const X86Subtarget *Subtarget) {
4487 SDOperand Cond = N->getOperand(0);
4489 // If we have SSE[12] support, try to form min/max nodes.
4490 if (Subtarget->hasSSE2() &&
4491 (N->getValueType(0) == MVT::f32 || N->getValueType(0) == MVT::f64)) {
4492 if (Cond.getOpcode() == ISD::SETCC) {
4493 // Get the LHS/RHS of the select.
4494 SDOperand LHS = N->getOperand(1);
4495 SDOperand RHS = N->getOperand(2);
4496 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
4498 unsigned Opcode = 0;
4499 if (LHS == Cond.getOperand(0) && RHS == Cond.getOperand(1)) {
4502 case ISD::SETOLE: // (X <= Y) ? X : Y -> min
4505 if (!UnsafeFPMath) break;
4507 case ISD::SETOLT: // (X olt/lt Y) ? X : Y -> min
4509 Opcode = X86ISD::FMIN;
4512 case ISD::SETOGT: // (X > Y) ? X : Y -> max
4515 if (!UnsafeFPMath) break;
4517 case ISD::SETUGE: // (X uge/ge Y) ? X : Y -> max
4519 Opcode = X86ISD::FMAX;
4522 } else if (LHS == Cond.getOperand(1) && RHS == Cond.getOperand(0)) {
4525 case ISD::SETOGT: // (X > Y) ? Y : X -> min
4528 if (!UnsafeFPMath) break;
4530 case ISD::SETUGE: // (X uge/ge Y) ? Y : X -> min
4532 Opcode = X86ISD::FMIN;
4535 case ISD::SETOLE: // (X <= Y) ? Y : X -> max
4538 if (!UnsafeFPMath) break;
4540 case ISD::SETOLT: // (X olt/lt Y) ? Y : X -> max
4542 Opcode = X86ISD::FMAX;
4548 return DAG.getNode(Opcode, N->getValueType(0), LHS, RHS);
4557 SDOperand X86TargetLowering::PerformDAGCombine(SDNode *N,
4558 DAGCombinerInfo &DCI) const {
4559 SelectionDAG &DAG = DCI.DAG;
4560 switch (N->getOpcode()) {
4562 case ISD::VECTOR_SHUFFLE:
4563 return PerformShuffleCombine(N, DAG, Subtarget);
4565 return PerformSELECTCombine(N, DAG, Subtarget);
4571 //===----------------------------------------------------------------------===//
4572 // X86 Inline Assembly Support
4573 //===----------------------------------------------------------------------===//
4575 /// getConstraintType - Given a constraint letter, return the type of
4576 /// constraint it is for this target.
4577 X86TargetLowering::ConstraintType
4578 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
4579 if (Constraint.size() == 1) {
4580 switch (Constraint[0]) {
4589 return C_RegisterClass;
4594 return TargetLowering::getConstraintType(Constraint);
4597 /// isOperandValidForConstraint - Return the specified operand (possibly
4598 /// modified) if the specified SDOperand is valid for the specified target
4599 /// constraint letter, otherwise return null.
4600 SDOperand X86TargetLowering::
4601 isOperandValidForConstraint(SDOperand Op, char Constraint, SelectionDAG &DAG) {
4602 switch (Constraint) {
4605 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
4606 if (C->getValue() <= 31)
4609 return SDOperand(0,0);
4611 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
4612 if (C->getValue() <= 255)
4615 return SDOperand(0,0);
4617 // Literal immediates are always ok.
4618 if (isa<ConstantSDNode>(Op)) return Op;
4620 // If we are in non-pic codegen mode, we allow the address of a global to
4621 // be used with 'i'.
4622 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op)) {
4623 if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
4624 return SDOperand(0, 0);
4626 if (GA->getOpcode() != ISD::TargetGlobalAddress)
4627 Op = DAG.getTargetGlobalAddress(GA->getGlobal(), GA->getValueType(0),
4632 // Otherwise, not valid for this mode.
4633 return SDOperand(0, 0);
4635 return TargetLowering::isOperandValidForConstraint(Op, Constraint, DAG);
4638 std::vector<unsigned> X86TargetLowering::
4639 getRegClassForInlineAsmConstraint(const std::string &Constraint,
4640 MVT::ValueType VT) const {
4641 if (Constraint.size() == 1) {
4642 // FIXME: not handling fp-stack yet!
4643 switch (Constraint[0]) { // GCC X86 Constraint Letters
4644 default: break; // Unknown constraint letter
4645 case 'A': // EAX/EDX
4646 if (VT == MVT::i32 || VT == MVT::i64)
4647 return make_vector<unsigned>(X86::EAX, X86::EDX, 0);
4649 case 'q': // Q_REGS (GENERAL_REGS in 64-bit mode)
4652 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0);
4653 else if (VT == MVT::i16)
4654 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0);
4655 else if (VT == MVT::i8)
4656 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::DL, 0);
4661 return std::vector<unsigned>();
4664 std::pair<unsigned, const TargetRegisterClass*>
4665 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
4666 MVT::ValueType VT) const {
4667 // First, see if this is a constraint that directly corresponds to an LLVM
4669 if (Constraint.size() == 1) {
4670 // GCC Constraint Letters
4671 switch (Constraint[0]) {
4673 case 'r': // GENERAL_REGS
4674 case 'R': // LEGACY_REGS
4675 case 'l': // INDEX_REGS
4676 if (VT == MVT::i64 && Subtarget->is64Bit())
4677 return std::make_pair(0U, X86::GR64RegisterClass);
4679 return std::make_pair(0U, X86::GR32RegisterClass);
4680 else if (VT == MVT::i16)
4681 return std::make_pair(0U, X86::GR16RegisterClass);
4682 else if (VT == MVT::i8)
4683 return std::make_pair(0U, X86::GR8RegisterClass);
4685 case 'y': // MMX_REGS if MMX allowed.
4686 if (!Subtarget->hasMMX()) break;
4687 return std::make_pair(0U, X86::VR64RegisterClass);
4689 case 'Y': // SSE_REGS if SSE2 allowed
4690 if (!Subtarget->hasSSE2()) break;
4692 case 'x': // SSE_REGS if SSE1 allowed
4693 if (!Subtarget->hasSSE1()) break;
4697 // Scalar SSE types.
4700 return std::make_pair(0U, X86::FR32RegisterClass);
4703 return std::make_pair(0U, X86::FR64RegisterClass);
4712 return std::make_pair(0U, X86::VR128RegisterClass);
4718 // Use the default implementation in TargetLowering to convert the register
4719 // constraint into a member of a register class.
4720 std::pair<unsigned, const TargetRegisterClass*> Res;
4721 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
4723 // Not found as a standard register?
4724 if (Res.second == 0) {
4725 // GCC calls "st(0)" just plain "st".
4726 if (StringsEqualNoCase("{st}", Constraint)) {
4727 Res.first = X86::ST0;
4728 Res.second = X86::RSTRegisterClass;
4734 // Otherwise, check to see if this is a register class of the wrong value
4735 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
4736 // turn into {ax},{dx}.
4737 if (Res.second->hasType(VT))
4738 return Res; // Correct type already, nothing to do.
4740 // All of the single-register GCC register classes map their values onto
4741 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
4742 // really want an 8-bit or 32-bit register, map to the appropriate register
4743 // class and return the appropriate register.
4744 if (Res.second != X86::GR16RegisterClass)
4747 if (VT == MVT::i8) {
4748 unsigned DestReg = 0;
4749 switch (Res.first) {
4751 case X86::AX: DestReg = X86::AL; break;
4752 case X86::DX: DestReg = X86::DL; break;
4753 case X86::CX: DestReg = X86::CL; break;
4754 case X86::BX: DestReg = X86::BL; break;
4757 Res.first = DestReg;
4758 Res.second = Res.second = X86::GR8RegisterClass;
4760 } else if (VT == MVT::i32) {
4761 unsigned DestReg = 0;
4762 switch (Res.first) {
4764 case X86::AX: DestReg = X86::EAX; break;
4765 case X86::DX: DestReg = X86::EDX; break;
4766 case X86::CX: DestReg = X86::ECX; break;
4767 case X86::BX: DestReg = X86::EBX; break;
4768 case X86::SI: DestReg = X86::ESI; break;
4769 case X86::DI: DestReg = X86::EDI; break;
4770 case X86::BP: DestReg = X86::EBP; break;
4771 case X86::SP: DestReg = X86::ESP; break;
4774 Res.first = DestReg;
4775 Res.second = Res.second = X86::GR32RegisterClass;
4777 } else if (VT == MVT::i64) {
4778 unsigned DestReg = 0;
4779 switch (Res.first) {
4781 case X86::AX: DestReg = X86::RAX; break;
4782 case X86::DX: DestReg = X86::RDX; break;
4783 case X86::CX: DestReg = X86::RCX; break;
4784 case X86::BX: DestReg = X86::RBX; break;
4785 case X86::SI: DestReg = X86::RSI; break;
4786 case X86::DI: DestReg = X86::RDI; break;
4787 case X86::BP: DestReg = X86::RBP; break;
4788 case X86::SP: DestReg = X86::RSP; break;
4791 Res.first = DestReg;
4792 Res.second = Res.second = X86::GR64RegisterClass;