1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
16 #include "X86ISelLowering.h"
18 #include "X86InstrBuilder.h"
19 #include "X86TargetMachine.h"
20 #include "X86TargetObjectFile.h"
21 #include "Utils/X86ShuffleDecode.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/GlobalAlias.h"
26 #include "llvm/GlobalVariable.h"
27 #include "llvm/Function.h"
28 #include "llvm/Instructions.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/LLVMContext.h"
31 #include "llvm/CodeGen/IntrinsicLowering.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/CodeGen/MachineFunction.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineJumpTableInfo.h"
36 #include "llvm/CodeGen/MachineModuleInfo.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/MC/MCAsmInfo.h"
39 #include "llvm/MC/MCContext.h"
40 #include "llvm/MC/MCExpr.h"
41 #include "llvm/MC/MCSymbol.h"
42 #include "llvm/ADT/SmallSet.h"
43 #include "llvm/ADT/Statistic.h"
44 #include "llvm/ADT/StringExtras.h"
45 #include "llvm/ADT/VariadicFunction.h"
46 #include "llvm/Support/CallSite.h"
47 #include "llvm/Support/Debug.h"
48 #include "llvm/Support/ErrorHandling.h"
49 #include "llvm/Support/MathExtras.h"
50 #include "llvm/Target/TargetOptions.h"
54 STATISTIC(NumTailCalls, "Number of tail calls");
56 // Forward declarations.
57 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
60 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
61 /// sets things up to match to an AVX VEXTRACTF128 instruction or a
62 /// simple subregister reference. Idx is an index in the 128 bits we
63 /// want. It need not be aligned to a 128-bit bounday. That makes
64 /// lowering EXTRACT_VECTOR_ELT operations easier.
65 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
66 SelectionDAG &DAG, DebugLoc dl) {
67 EVT VT = Vec.getValueType();
68 assert(VT.getSizeInBits() == 256 && "Unexpected vector size!");
69 EVT ElVT = VT.getVectorElementType();
70 unsigned Factor = VT.getSizeInBits()/128;
71 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
72 VT.getVectorNumElements()/Factor);
74 // Extract from UNDEF is UNDEF.
75 if (Vec.getOpcode() == ISD::UNDEF)
76 return DAG.getUNDEF(ResultVT);
78 // Extract the relevant 128 bits. Generate an EXTRACT_SUBVECTOR
79 // we can match to VEXTRACTF128.
80 unsigned ElemsPerChunk = 128 / ElVT.getSizeInBits();
82 // This is the index of the first element of the 128-bit chunk
84 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / 128)
87 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
88 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
94 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
95 /// sets things up to match to an AVX VINSERTF128 instruction or a
96 /// simple superregister reference. Idx is an index in the 128 bits
97 /// we want. It need not be aligned to a 128-bit bounday. That makes
98 /// lowering INSERT_VECTOR_ELT operations easier.
99 static SDValue Insert128BitVector(SDValue Result, SDValue Vec,
100 unsigned IdxVal, SelectionDAG &DAG,
102 EVT VT = Vec.getValueType();
103 assert(VT.getSizeInBits() == 128 && "Unexpected vector size!");
105 EVT ElVT = VT.getVectorElementType();
106 EVT ResultVT = Result.getValueType();
108 // Insert the relevant 128 bits.
109 unsigned ElemsPerChunk = 128/ElVT.getSizeInBits();
111 // This is the index of the first element of the 128-bit chunk
113 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/128)
116 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
117 Result = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
122 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
123 /// instructions. This is used because creating CONCAT_VECTOR nodes of
124 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
125 /// large BUILD_VECTORS.
126 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
127 unsigned NumElems, SelectionDAG &DAG,
129 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
130 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
133 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
134 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
135 bool is64Bit = Subtarget->is64Bit();
137 if (Subtarget->isTargetEnvMacho()) {
139 return new X8664_MachoTargetObjectFile();
140 return new TargetLoweringObjectFileMachO();
143 if (Subtarget->isTargetELF())
144 return new TargetLoweringObjectFileELF();
145 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
146 return new TargetLoweringObjectFileCOFF();
147 llvm_unreachable("unknown subtarget type");
150 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
151 : TargetLowering(TM, createTLOF(TM)) {
152 Subtarget = &TM.getSubtarget<X86Subtarget>();
153 X86ScalarSSEf64 = Subtarget->hasSSE2();
154 X86ScalarSSEf32 = Subtarget->hasSSE1();
155 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
157 RegInfo = TM.getRegisterInfo();
158 TD = getTargetData();
160 // Set up the TargetLowering object.
161 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
163 // X86 is weird, it always uses i8 for shift amounts and setcc results.
164 setBooleanContents(ZeroOrOneBooleanContent);
165 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
166 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
168 // For 64-bit since we have so many registers use the ILP scheduler, for
169 // 32-bit code use the register pressure specific scheduling.
170 // For 32 bit Atom, use Hybrid (register pressure + latency) scheduling.
171 if (Subtarget->is64Bit())
172 setSchedulingPreference(Sched::ILP);
173 else if (Subtarget->isAtom())
174 setSchedulingPreference(Sched::Hybrid);
176 setSchedulingPreference(Sched::RegPressure);
177 setStackPointerRegisterToSaveRestore(X86StackPtr);
179 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) {
180 // Setup Windows compiler runtime calls.
181 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
182 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
183 setLibcallName(RTLIB::SREM_I64, "_allrem");
184 setLibcallName(RTLIB::UREM_I64, "_aullrem");
185 setLibcallName(RTLIB::MUL_I64, "_allmul");
186 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
187 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
188 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
189 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
190 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
192 // The _ftol2 runtime function has an unusual calling conv, which
193 // is modeled by a special pseudo-instruction.
194 setLibcallName(RTLIB::FPTOUINT_F64_I64, 0);
195 setLibcallName(RTLIB::FPTOUINT_F32_I64, 0);
196 setLibcallName(RTLIB::FPTOUINT_F64_I32, 0);
197 setLibcallName(RTLIB::FPTOUINT_F32_I32, 0);
200 if (Subtarget->isTargetDarwin()) {
201 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
202 setUseUnderscoreSetJmp(false);
203 setUseUnderscoreLongJmp(false);
204 } else if (Subtarget->isTargetMingw()) {
205 // MS runtime is weird: it exports _setjmp, but longjmp!
206 setUseUnderscoreSetJmp(true);
207 setUseUnderscoreLongJmp(false);
209 setUseUnderscoreSetJmp(true);
210 setUseUnderscoreLongJmp(true);
213 // Set up the register classes.
214 addRegisterClass(MVT::i8, &X86::GR8RegClass);
215 addRegisterClass(MVT::i16, &X86::GR16RegClass);
216 addRegisterClass(MVT::i32, &X86::GR32RegClass);
217 if (Subtarget->is64Bit())
218 addRegisterClass(MVT::i64, &X86::GR64RegClass);
220 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
222 // We don't accept any truncstore of integer registers.
223 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
224 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
225 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
226 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
227 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
228 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
230 // SETOEQ and SETUNE require checking two conditions.
231 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
232 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
233 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
234 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
235 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
236 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
238 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
240 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
241 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
242 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
244 if (Subtarget->is64Bit()) {
245 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
246 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
247 } else if (!TM.Options.UseSoftFloat) {
248 // We have an algorithm for SSE2->double, and we turn this into a
249 // 64-bit FILD followed by conditional FADD for other targets.
250 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
251 // We have an algorithm for SSE2, and we turn this into a 64-bit
252 // FILD for other targets.
253 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
256 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
258 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
259 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
261 if (!TM.Options.UseSoftFloat) {
262 // SSE has no i16 to fp conversion, only i32
263 if (X86ScalarSSEf32) {
264 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
265 // f32 and f64 cases are Legal, f80 case is not
266 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
268 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
269 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
272 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
273 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
276 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
277 // are Legal, f80 is custom lowered.
278 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
279 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
281 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
283 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
284 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
286 if (X86ScalarSSEf32) {
287 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
288 // f32 and f64 cases are Legal, f80 case is not
289 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
291 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
292 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
295 // Handle FP_TO_UINT by promoting the destination to a larger signed
297 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
298 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
299 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
301 if (Subtarget->is64Bit()) {
302 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
303 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
304 } else if (!TM.Options.UseSoftFloat) {
305 // Since AVX is a superset of SSE3, only check for SSE here.
306 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
307 // Expand FP_TO_UINT into a select.
308 // FIXME: We would like to use a Custom expander here eventually to do
309 // the optimal thing for SSE vs. the default expansion in the legalizer.
310 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
312 // With SSE3 we can use fisttpll to convert to a signed i64; without
313 // SSE, we're stuck with a fistpll.
314 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
317 if (isTargetFTOL()) {
318 // Use the _ftol2 runtime function, which has a pseudo-instruction
319 // to handle its weird calling convention.
320 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
323 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
324 if (!X86ScalarSSEf64) {
325 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
326 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
327 if (Subtarget->is64Bit()) {
328 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
329 // Without SSE, i64->f64 goes through memory.
330 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
334 // Scalar integer divide and remainder are lowered to use operations that
335 // produce two results, to match the available instructions. This exposes
336 // the two-result form to trivial CSE, which is able to combine x/y and x%y
337 // into a single instruction.
339 // Scalar integer multiply-high is also lowered to use two-result
340 // operations, to match the available instructions. However, plain multiply
341 // (low) operations are left as Legal, as there are single-result
342 // instructions for this in x86. Using the two-result multiply instructions
343 // when both high and low results are needed must be arranged by dagcombine.
344 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
346 setOperationAction(ISD::MULHS, VT, Expand);
347 setOperationAction(ISD::MULHU, VT, Expand);
348 setOperationAction(ISD::SDIV, VT, Expand);
349 setOperationAction(ISD::UDIV, VT, Expand);
350 setOperationAction(ISD::SREM, VT, Expand);
351 setOperationAction(ISD::UREM, VT, Expand);
353 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
354 setOperationAction(ISD::ADDC, VT, Custom);
355 setOperationAction(ISD::ADDE, VT, Custom);
356 setOperationAction(ISD::SUBC, VT, Custom);
357 setOperationAction(ISD::SUBE, VT, Custom);
360 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
361 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
362 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
363 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
364 if (Subtarget->is64Bit())
365 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
366 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
367 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
368 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
369 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
370 setOperationAction(ISD::FREM , MVT::f32 , Expand);
371 setOperationAction(ISD::FREM , MVT::f64 , Expand);
372 setOperationAction(ISD::FREM , MVT::f80 , Expand);
373 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
375 // Promote the i8 variants and force them on up to i32 which has a shorter
377 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
378 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
379 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
380 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
381 if (Subtarget->hasBMI()) {
382 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
383 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
384 if (Subtarget->is64Bit())
385 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
387 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
388 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
389 if (Subtarget->is64Bit())
390 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
393 if (Subtarget->hasLZCNT()) {
394 // When promoting the i8 variants, force them to i32 for a shorter
396 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
397 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
398 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
399 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
400 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
401 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
402 if (Subtarget->is64Bit())
403 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
405 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
406 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
407 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
408 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
409 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
410 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
411 if (Subtarget->is64Bit()) {
412 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
413 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
417 if (Subtarget->hasPOPCNT()) {
418 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
420 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
421 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
422 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
423 if (Subtarget->is64Bit())
424 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
427 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
428 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
430 // These should be promoted to a larger select which is supported.
431 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
432 // X86 wants to expand cmov itself.
433 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
434 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
435 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
436 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
437 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
438 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
439 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
440 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
441 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
442 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
443 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
444 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
445 if (Subtarget->is64Bit()) {
446 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
447 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
449 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
452 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
453 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
454 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
455 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
456 if (Subtarget->is64Bit())
457 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
458 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
459 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
460 if (Subtarget->is64Bit()) {
461 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
462 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
463 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
464 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
465 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
467 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
468 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
469 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
470 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
471 if (Subtarget->is64Bit()) {
472 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
473 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
474 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
477 if (Subtarget->hasSSE1())
478 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
480 setOperationAction(ISD::MEMBARRIER , MVT::Other, Custom);
481 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
483 // On X86 and X86-64, atomic operations are lowered to locked instructions.
484 // Locked instructions, in turn, have implicit fence semantics (all memory
485 // operations are flushed before issuing the locked instruction, and they
486 // are not buffered), so we can fold away the common pattern of
487 // fence-atomic-fence.
488 setShouldFoldAtomicFences(true);
490 // Expand certain atomics
491 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
493 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom);
494 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
495 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
498 if (!Subtarget->is64Bit()) {
499 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
500 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
501 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
502 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
503 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
504 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
505 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
506 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
509 if (Subtarget->hasCmpxchg16b()) {
510 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom);
513 // FIXME - use subtarget debug flags
514 if (!Subtarget->isTargetDarwin() &&
515 !Subtarget->isTargetELF() &&
516 !Subtarget->isTargetCygMing()) {
517 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
520 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
521 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
522 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
523 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
524 if (Subtarget->is64Bit()) {
525 setExceptionPointerRegister(X86::RAX);
526 setExceptionSelectorRegister(X86::RDX);
528 setExceptionPointerRegister(X86::EAX);
529 setExceptionSelectorRegister(X86::EDX);
531 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
532 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
534 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
535 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
537 setOperationAction(ISD::TRAP, MVT::Other, Legal);
539 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
540 setOperationAction(ISD::VASTART , MVT::Other, Custom);
541 setOperationAction(ISD::VAEND , MVT::Other, Expand);
542 if (Subtarget->is64Bit()) {
543 setOperationAction(ISD::VAARG , MVT::Other, Custom);
544 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
546 setOperationAction(ISD::VAARG , MVT::Other, Expand);
547 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
550 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
551 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
553 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
554 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
555 MVT::i64 : MVT::i32, Custom);
556 else if (TM.Options.EnableSegmentedStacks)
557 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
558 MVT::i64 : MVT::i32, Custom);
560 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
561 MVT::i64 : MVT::i32, Expand);
563 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
564 // f32 and f64 use SSE.
565 // Set up the FP register classes.
566 addRegisterClass(MVT::f32, &X86::FR32RegClass);
567 addRegisterClass(MVT::f64, &X86::FR64RegClass);
569 // Use ANDPD to simulate FABS.
570 setOperationAction(ISD::FABS , MVT::f64, Custom);
571 setOperationAction(ISD::FABS , MVT::f32, Custom);
573 // Use XORP to simulate FNEG.
574 setOperationAction(ISD::FNEG , MVT::f64, Custom);
575 setOperationAction(ISD::FNEG , MVT::f32, Custom);
577 // Use ANDPD and ORPD to simulate FCOPYSIGN.
578 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
579 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
581 // Lower this to FGETSIGNx86 plus an AND.
582 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
583 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
585 // We don't support sin/cos/fmod
586 setOperationAction(ISD::FSIN , MVT::f64, Expand);
587 setOperationAction(ISD::FCOS , MVT::f64, Expand);
588 setOperationAction(ISD::FSIN , MVT::f32, Expand);
589 setOperationAction(ISD::FCOS , MVT::f32, Expand);
591 // Expand FP immediates into loads from the stack, except for the special
593 addLegalFPImmediate(APFloat(+0.0)); // xorpd
594 addLegalFPImmediate(APFloat(+0.0f)); // xorps
595 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
596 // Use SSE for f32, x87 for f64.
597 // Set up the FP register classes.
598 addRegisterClass(MVT::f32, &X86::FR32RegClass);
599 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
601 // Use ANDPS to simulate FABS.
602 setOperationAction(ISD::FABS , MVT::f32, Custom);
604 // Use XORP to simulate FNEG.
605 setOperationAction(ISD::FNEG , MVT::f32, Custom);
607 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
609 // Use ANDPS and ORPS to simulate FCOPYSIGN.
610 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
611 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
613 // We don't support sin/cos/fmod
614 setOperationAction(ISD::FSIN , MVT::f32, Expand);
615 setOperationAction(ISD::FCOS , MVT::f32, Expand);
617 // Special cases we handle for FP constants.
618 addLegalFPImmediate(APFloat(+0.0f)); // xorps
619 addLegalFPImmediate(APFloat(+0.0)); // FLD0
620 addLegalFPImmediate(APFloat(+1.0)); // FLD1
621 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
622 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
624 if (!TM.Options.UnsafeFPMath) {
625 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
626 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
628 } else if (!TM.Options.UseSoftFloat) {
629 // f32 and f64 in x87.
630 // Set up the FP register classes.
631 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
632 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
634 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
635 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
636 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
637 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
639 if (!TM.Options.UnsafeFPMath) {
640 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
641 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
643 addLegalFPImmediate(APFloat(+0.0)); // FLD0
644 addLegalFPImmediate(APFloat(+1.0)); // FLD1
645 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
646 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
647 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
648 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
649 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
650 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
653 // We don't support FMA.
654 setOperationAction(ISD::FMA, MVT::f64, Expand);
655 setOperationAction(ISD::FMA, MVT::f32, Expand);
657 // Long double always uses X87.
658 if (!TM.Options.UseSoftFloat) {
659 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
660 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
661 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
663 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
664 addLegalFPImmediate(TmpFlt); // FLD0
666 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
669 APFloat TmpFlt2(+1.0);
670 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
672 addLegalFPImmediate(TmpFlt2); // FLD1
673 TmpFlt2.changeSign();
674 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
677 if (!TM.Options.UnsafeFPMath) {
678 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
679 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
682 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
683 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
684 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
685 setOperationAction(ISD::FRINT, MVT::f80, Expand);
686 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
687 setOperationAction(ISD::FMA, MVT::f80, Expand);
690 // Always use a library call for pow.
691 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
692 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
693 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
695 setOperationAction(ISD::FLOG, MVT::f80, Expand);
696 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
697 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
698 setOperationAction(ISD::FEXP, MVT::f80, Expand);
699 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
701 // First set operation action for all vector types to either promote
702 // (for widening) or expand (for scalarization). Then we will selectively
703 // turn on ones that can be effectively codegen'd.
704 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
705 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
706 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
707 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
708 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
709 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
710 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
711 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
712 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
713 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
714 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
715 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
716 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
717 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
718 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
719 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
720 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
721 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
722 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
723 setOperationAction(ISD::INSERT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
724 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
725 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
726 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
727 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
728 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
729 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
730 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
731 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
732 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
733 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
734 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
735 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
736 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
737 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
738 setOperationAction(ISD::CTTZ_ZERO_UNDEF, (MVT::SimpleValueType)VT, Expand);
739 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
740 setOperationAction(ISD::CTLZ_ZERO_UNDEF, (MVT::SimpleValueType)VT, Expand);
741 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
742 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
743 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
744 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
745 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
746 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
747 setOperationAction(ISD::SETCC, (MVT::SimpleValueType)VT, Expand);
748 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
749 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
750 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
751 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand);
752 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand);
753 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand);
754 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand);
755 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
756 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
757 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand);
758 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand);
759 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand);
760 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand);
761 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand);
762 setOperationAction(ISD::VSELECT, (MVT::SimpleValueType)VT, Expand);
763 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
764 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
765 setTruncStoreAction((MVT::SimpleValueType)VT,
766 (MVT::SimpleValueType)InnerVT, Expand);
767 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
768 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
769 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
772 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
773 // with -msoft-float, disable use of MMX as well.
774 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
775 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
776 // No operations on x86mmx supported, everything uses intrinsics.
779 // MMX-sized vectors (other than x86mmx) are expected to be expanded
780 // into smaller operations.
781 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
782 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
783 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
784 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
785 setOperationAction(ISD::AND, MVT::v8i8, Expand);
786 setOperationAction(ISD::AND, MVT::v4i16, Expand);
787 setOperationAction(ISD::AND, MVT::v2i32, Expand);
788 setOperationAction(ISD::AND, MVT::v1i64, Expand);
789 setOperationAction(ISD::OR, MVT::v8i8, Expand);
790 setOperationAction(ISD::OR, MVT::v4i16, Expand);
791 setOperationAction(ISD::OR, MVT::v2i32, Expand);
792 setOperationAction(ISD::OR, MVT::v1i64, Expand);
793 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
794 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
795 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
796 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
797 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
798 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
799 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
800 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
801 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
802 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
803 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
804 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
805 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
806 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
807 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
808 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
809 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
811 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
812 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
814 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
815 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
816 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
817 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
818 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
819 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
820 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
821 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
822 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
823 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
824 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
825 setOperationAction(ISD::SETCC, MVT::v4f32, Custom);
828 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
829 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
831 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
832 // registers cannot be used even for integer operations.
833 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
834 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
835 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
836 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
838 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
839 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
840 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
841 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
842 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
843 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
844 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
845 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
846 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
847 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
848 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
849 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
850 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
851 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
852 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
853 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
855 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
856 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
857 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
858 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
860 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
861 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
862 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
863 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
864 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
866 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Custom);
867 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Custom);
868 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom);
869 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom);
870 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
872 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
873 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) {
874 EVT VT = (MVT::SimpleValueType)i;
875 // Do not attempt to custom lower non-power-of-2 vectors
876 if (!isPowerOf2_32(VT.getVectorNumElements()))
878 // Do not attempt to custom lower non-128-bit vectors
879 if (!VT.is128BitVector())
881 setOperationAction(ISD::BUILD_VECTOR,
882 VT.getSimpleVT().SimpleTy, Custom);
883 setOperationAction(ISD::VECTOR_SHUFFLE,
884 VT.getSimpleVT().SimpleTy, Custom);
885 setOperationAction(ISD::EXTRACT_VECTOR_ELT,
886 VT.getSimpleVT().SimpleTy, Custom);
889 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
890 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
891 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
892 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
893 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
894 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
896 if (Subtarget->is64Bit()) {
897 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
898 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
901 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
902 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) {
903 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
906 // Do not attempt to promote non-128-bit vectors
907 if (!VT.is128BitVector())
910 setOperationAction(ISD::AND, SVT, Promote);
911 AddPromotedToType (ISD::AND, SVT, MVT::v2i64);
912 setOperationAction(ISD::OR, SVT, Promote);
913 AddPromotedToType (ISD::OR, SVT, MVT::v2i64);
914 setOperationAction(ISD::XOR, SVT, Promote);
915 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64);
916 setOperationAction(ISD::LOAD, SVT, Promote);
917 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64);
918 setOperationAction(ISD::SELECT, SVT, Promote);
919 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64);
922 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
924 // Custom lower v2i64 and v2f64 selects.
925 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
926 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
927 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
928 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
930 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
931 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
934 if (Subtarget->hasSSE41()) {
935 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
936 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
937 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
938 setOperationAction(ISD::FRINT, MVT::f32, Legal);
939 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
940 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
941 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
942 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
943 setOperationAction(ISD::FRINT, MVT::f64, Legal);
944 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
946 // FIXME: Do we need to handle scalar-to-vector here?
947 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
949 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
950 setOperationAction(ISD::VSELECT, MVT::v2i64, Legal);
951 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
952 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
953 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
955 // i8 and i16 vectors are custom , because the source register and source
956 // source memory operand types are not the same width. f32 vectors are
957 // custom since the immediate controlling the insert encodes additional
959 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
960 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
961 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
962 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
964 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
965 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
966 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
967 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
969 // FIXME: these should be Legal but thats only for the case where
970 // the index is constant. For now custom expand to deal with that.
971 if (Subtarget->is64Bit()) {
972 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
973 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
977 if (Subtarget->hasSSE2()) {
978 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
979 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
981 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
982 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
984 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
985 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
987 if (Subtarget->hasAVX2()) {
988 setOperationAction(ISD::SRL, MVT::v2i64, Legal);
989 setOperationAction(ISD::SRL, MVT::v4i32, Legal);
991 setOperationAction(ISD::SHL, MVT::v2i64, Legal);
992 setOperationAction(ISD::SHL, MVT::v4i32, Legal);
994 setOperationAction(ISD::SRA, MVT::v4i32, Legal);
996 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
997 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
999 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1000 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1002 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1006 if (Subtarget->hasSSE42())
1007 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
1009 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX()) {
1010 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1011 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1012 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1013 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1014 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1015 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1017 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1018 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1019 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1021 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1022 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1023 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1024 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1025 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1026 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1028 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1029 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1030 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1031 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1032 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1033 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1035 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1036 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1037 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1039 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f64, Custom);
1040 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i64, Custom);
1041 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom);
1042 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom);
1043 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i8, Custom);
1044 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i16, Custom);
1046 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1047 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1049 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1050 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1052 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1053 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1055 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1056 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1057 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1058 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1060 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1061 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1062 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1064 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal);
1065 setOperationAction(ISD::VSELECT, MVT::v4i64, Legal);
1066 setOperationAction(ISD::VSELECT, MVT::v8i32, Legal);
1067 setOperationAction(ISD::VSELECT, MVT::v8f32, Legal);
1069 if (Subtarget->hasAVX2()) {
1070 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1071 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1072 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1073 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1075 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1076 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1077 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1078 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1080 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1081 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1082 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1083 // Don't lower v32i8 because there is no 128-bit byte mul
1085 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1087 setOperationAction(ISD::SRL, MVT::v4i64, Legal);
1088 setOperationAction(ISD::SRL, MVT::v8i32, Legal);
1090 setOperationAction(ISD::SHL, MVT::v4i64, Legal);
1091 setOperationAction(ISD::SHL, MVT::v8i32, Legal);
1093 setOperationAction(ISD::SRA, MVT::v8i32, Legal);
1095 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1096 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1097 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1098 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1100 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1101 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1102 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1103 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1105 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1106 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1107 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1108 // Don't lower v32i8 because there is no 128-bit byte mul
1110 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1111 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1113 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1114 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1116 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1119 // Custom lower several nodes for 256-bit types.
1120 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
1121 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
1122 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
1125 // Extract subvector is special because the value type
1126 // (result) is 128-bit but the source is 256-bit wide.
1127 if (VT.is128BitVector())
1128 setOperationAction(ISD::EXTRACT_SUBVECTOR, SVT, Custom);
1130 // Do not attempt to custom lower other non-256-bit vectors
1131 if (!VT.is256BitVector())
1134 setOperationAction(ISD::BUILD_VECTOR, SVT, Custom);
1135 setOperationAction(ISD::VECTOR_SHUFFLE, SVT, Custom);
1136 setOperationAction(ISD::INSERT_VECTOR_ELT, SVT, Custom);
1137 setOperationAction(ISD::EXTRACT_VECTOR_ELT, SVT, Custom);
1138 setOperationAction(ISD::SCALAR_TO_VECTOR, SVT, Custom);
1139 setOperationAction(ISD::INSERT_SUBVECTOR, SVT, Custom);
1142 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1143 for (unsigned i = (unsigned)MVT::v32i8; i != (unsigned)MVT::v4i64; ++i) {
1144 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
1147 // Do not attempt to promote non-256-bit vectors
1148 if (!VT.is256BitVector())
1151 setOperationAction(ISD::AND, SVT, Promote);
1152 AddPromotedToType (ISD::AND, SVT, MVT::v4i64);
1153 setOperationAction(ISD::OR, SVT, Promote);
1154 AddPromotedToType (ISD::OR, SVT, MVT::v4i64);
1155 setOperationAction(ISD::XOR, SVT, Promote);
1156 AddPromotedToType (ISD::XOR, SVT, MVT::v4i64);
1157 setOperationAction(ISD::LOAD, SVT, Promote);
1158 AddPromotedToType (ISD::LOAD, SVT, MVT::v4i64);
1159 setOperationAction(ISD::SELECT, SVT, Promote);
1160 AddPromotedToType (ISD::SELECT, SVT, MVT::v4i64);
1164 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1165 // of this type with custom code.
1166 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
1167 VT != (unsigned)MVT::LAST_VECTOR_VALUETYPE; VT++) {
1168 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1172 // We want to custom lower some of our intrinsics.
1173 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1176 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1177 // handle type legalization for these operations here.
1179 // FIXME: We really should do custom legalization for addition and
1180 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1181 // than generic legalization for 64-bit multiplication-with-overflow, though.
1182 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1183 // Add/Sub/Mul with overflow operations are custom lowered.
1185 setOperationAction(ISD::SADDO, VT, Custom);
1186 setOperationAction(ISD::UADDO, VT, Custom);
1187 setOperationAction(ISD::SSUBO, VT, Custom);
1188 setOperationAction(ISD::USUBO, VT, Custom);
1189 setOperationAction(ISD::SMULO, VT, Custom);
1190 setOperationAction(ISD::UMULO, VT, Custom);
1193 // There are no 8-bit 3-address imul/mul instructions
1194 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1195 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1197 if (!Subtarget->is64Bit()) {
1198 // These libcalls are not available in 32-bit.
1199 setLibcallName(RTLIB::SHL_I128, 0);
1200 setLibcallName(RTLIB::SRL_I128, 0);
1201 setLibcallName(RTLIB::SRA_I128, 0);
1204 // We have target-specific dag combine patterns for the following nodes:
1205 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1206 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1207 setTargetDAGCombine(ISD::VSELECT);
1208 setTargetDAGCombine(ISD::SELECT);
1209 setTargetDAGCombine(ISD::SHL);
1210 setTargetDAGCombine(ISD::SRA);
1211 setTargetDAGCombine(ISD::SRL);
1212 setTargetDAGCombine(ISD::OR);
1213 setTargetDAGCombine(ISD::AND);
1214 setTargetDAGCombine(ISD::ADD);
1215 setTargetDAGCombine(ISD::FADD);
1216 setTargetDAGCombine(ISD::FSUB);
1217 setTargetDAGCombine(ISD::SUB);
1218 setTargetDAGCombine(ISD::LOAD);
1219 setTargetDAGCombine(ISD::STORE);
1220 setTargetDAGCombine(ISD::ZERO_EXTEND);
1221 setTargetDAGCombine(ISD::ANY_EXTEND);
1222 setTargetDAGCombine(ISD::SIGN_EXTEND);
1223 setTargetDAGCombine(ISD::TRUNCATE);
1224 setTargetDAGCombine(ISD::UINT_TO_FP);
1225 setTargetDAGCombine(ISD::SINT_TO_FP);
1226 setTargetDAGCombine(ISD::SETCC);
1227 setTargetDAGCombine(ISD::FP_TO_SINT);
1228 if (Subtarget->is64Bit())
1229 setTargetDAGCombine(ISD::MUL);
1230 if (Subtarget->hasBMI())
1231 setTargetDAGCombine(ISD::XOR);
1233 computeRegisterProperties();
1235 // On Darwin, -Os means optimize for size without hurting performance,
1236 // do not reduce the limit.
1237 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1238 maxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1239 maxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1240 maxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1241 maxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1242 maxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1243 setPrefLoopAlignment(4); // 2^4 bytes.
1244 benefitFromCodePlacementOpt = true;
1246 setPrefFunctionAlignment(4); // 2^4 bytes.
1250 EVT X86TargetLowering::getSetCCResultType(EVT VT) const {
1251 if (!VT.isVector()) return MVT::i8;
1252 return VT.changeVectorElementTypeToInteger();
1256 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1257 /// the desired ByVal argument alignment.
1258 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1261 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1262 if (VTy->getBitWidth() == 128)
1264 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1265 unsigned EltAlign = 0;
1266 getMaxByValAlign(ATy->getElementType(), EltAlign);
1267 if (EltAlign > MaxAlign)
1268 MaxAlign = EltAlign;
1269 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1270 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1271 unsigned EltAlign = 0;
1272 getMaxByValAlign(STy->getElementType(i), EltAlign);
1273 if (EltAlign > MaxAlign)
1274 MaxAlign = EltAlign;
1281 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1282 /// function arguments in the caller parameter area. For X86, aggregates
1283 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1284 /// are at 4-byte boundaries.
1285 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1286 if (Subtarget->is64Bit()) {
1287 // Max of 8 and alignment of type.
1288 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1295 if (Subtarget->hasSSE1())
1296 getMaxByValAlign(Ty, Align);
1300 /// getOptimalMemOpType - Returns the target specific optimal type for load
1301 /// and store operations as a result of memset, memcpy, and memmove
1302 /// lowering. If DstAlign is zero that means it's safe to destination
1303 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1304 /// means there isn't a need to check it against alignment requirement,
1305 /// probably because the source does not need to be loaded. If
1306 /// 'IsZeroVal' is true, that means it's safe to return a
1307 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
1308 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
1309 /// constant so it does not need to be loaded.
1310 /// It returns EVT::Other if the type should be determined using generic
1311 /// target-independent logic.
1313 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1314 unsigned DstAlign, unsigned SrcAlign,
1317 MachineFunction &MF) const {
1318 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like
1319 // linux. This is because the stack realignment code can't handle certain
1320 // cases like PR2962. This should be removed when PR2962 is fixed.
1321 const Function *F = MF.getFunction();
1323 !F->hasFnAttr(Attribute::NoImplicitFloat)) {
1325 (Subtarget->isUnalignedMemAccessFast() ||
1326 ((DstAlign == 0 || DstAlign >= 16) &&
1327 (SrcAlign == 0 || SrcAlign >= 16))) &&
1328 Subtarget->getStackAlignment() >= 16) {
1329 if (Subtarget->getStackAlignment() >= 32) {
1330 if (Subtarget->hasAVX2())
1332 if (Subtarget->hasAVX())
1335 if (Subtarget->hasSSE2())
1337 if (Subtarget->hasSSE1())
1339 } else if (!MemcpyStrSrc && Size >= 8 &&
1340 !Subtarget->is64Bit() &&
1341 Subtarget->getStackAlignment() >= 8 &&
1342 Subtarget->hasSSE2()) {
1343 // Do not use f64 to lower memcpy if source is string constant. It's
1344 // better to use i32 to avoid the loads.
1348 if (Subtarget->is64Bit() && Size >= 8)
1353 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1354 /// current function. The returned value is a member of the
1355 /// MachineJumpTableInfo::JTEntryKind enum.
1356 unsigned X86TargetLowering::getJumpTableEncoding() const {
1357 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1359 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1360 Subtarget->isPICStyleGOT())
1361 return MachineJumpTableInfo::EK_Custom32;
1363 // Otherwise, use the normal jump table encoding heuristics.
1364 return TargetLowering::getJumpTableEncoding();
1368 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1369 const MachineBasicBlock *MBB,
1370 unsigned uid,MCContext &Ctx) const{
1371 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1372 Subtarget->isPICStyleGOT());
1373 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1375 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1376 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1379 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1381 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1382 SelectionDAG &DAG) const {
1383 if (!Subtarget->is64Bit())
1384 // This doesn't have DebugLoc associated with it, but is not really the
1385 // same as a Register.
1386 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy());
1390 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1391 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1393 const MCExpr *X86TargetLowering::
1394 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1395 MCContext &Ctx) const {
1396 // X86-64 uses RIP relative addressing based on the jump table label.
1397 if (Subtarget->isPICStyleRIPRel())
1398 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1400 // Otherwise, the reference is relative to the PIC base.
1401 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1404 // FIXME: Why this routine is here? Move to RegInfo!
1405 std::pair<const TargetRegisterClass*, uint8_t>
1406 X86TargetLowering::findRepresentativeClass(EVT VT) const{
1407 const TargetRegisterClass *RRC = 0;
1409 switch (VT.getSimpleVT().SimpleTy) {
1411 return TargetLowering::findRepresentativeClass(VT);
1412 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1413 RRC = Subtarget->is64Bit() ?
1414 (const TargetRegisterClass*)&X86::GR64RegClass :
1415 (const TargetRegisterClass*)&X86::GR32RegClass;
1418 RRC = &X86::VR64RegClass;
1420 case MVT::f32: case MVT::f64:
1421 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1422 case MVT::v4f32: case MVT::v2f64:
1423 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1425 RRC = &X86::VR128RegClass;
1428 return std::make_pair(RRC, Cost);
1431 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1432 unsigned &Offset) const {
1433 if (!Subtarget->isTargetLinux())
1436 if (Subtarget->is64Bit()) {
1437 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1439 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1452 //===----------------------------------------------------------------------===//
1453 // Return Value Calling Convention Implementation
1454 //===----------------------------------------------------------------------===//
1456 #include "X86GenCallingConv.inc"
1459 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1460 MachineFunction &MF, bool isVarArg,
1461 const SmallVectorImpl<ISD::OutputArg> &Outs,
1462 LLVMContext &Context) const {
1463 SmallVector<CCValAssign, 16> RVLocs;
1464 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1466 return CCInfo.CheckReturn(Outs, RetCC_X86);
1470 X86TargetLowering::LowerReturn(SDValue Chain,
1471 CallingConv::ID CallConv, bool isVarArg,
1472 const SmallVectorImpl<ISD::OutputArg> &Outs,
1473 const SmallVectorImpl<SDValue> &OutVals,
1474 DebugLoc dl, SelectionDAG &DAG) const {
1475 MachineFunction &MF = DAG.getMachineFunction();
1476 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1478 SmallVector<CCValAssign, 16> RVLocs;
1479 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1480 RVLocs, *DAG.getContext());
1481 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1483 // Add the regs to the liveout set for the function.
1484 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
1485 for (unsigned i = 0; i != RVLocs.size(); ++i)
1486 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg()))
1487 MRI.addLiveOut(RVLocs[i].getLocReg());
1491 SmallVector<SDValue, 6> RetOps;
1492 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1493 // Operand #1 = Bytes To Pop
1494 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1497 // Copy the result values into the output registers.
1498 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1499 CCValAssign &VA = RVLocs[i];
1500 assert(VA.isRegLoc() && "Can only return in registers!");
1501 SDValue ValToCopy = OutVals[i];
1502 EVT ValVT = ValToCopy.getValueType();
1504 // If this is x86-64, and we disabled SSE, we can't return FP values,
1505 // or SSE or MMX vectors.
1506 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1507 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1508 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
1509 report_fatal_error("SSE register return with SSE disabled");
1511 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1512 // llvm-gcc has never done it right and no one has noticed, so this
1513 // should be OK for now.
1514 if (ValVT == MVT::f64 &&
1515 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
1516 report_fatal_error("SSE2 register return with SSE2 disabled");
1518 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1519 // the RET instruction and handled by the FP Stackifier.
1520 if (VA.getLocReg() == X86::ST0 ||
1521 VA.getLocReg() == X86::ST1) {
1522 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1523 // change the value to the FP stack register class.
1524 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1525 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1526 RetOps.push_back(ValToCopy);
1527 // Don't emit a copytoreg.
1531 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1532 // which is returned in RAX / RDX.
1533 if (Subtarget->is64Bit()) {
1534 if (ValVT == MVT::x86mmx) {
1535 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1536 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1537 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1539 // If we don't have SSE2 available, convert to v4f32 so the generated
1540 // register is legal.
1541 if (!Subtarget->hasSSE2())
1542 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1547 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1548 Flag = Chain.getValue(1);
1551 // The x86-64 ABI for returning structs by value requires that we copy
1552 // the sret argument into %rax for the return. We saved the argument into
1553 // a virtual register in the entry block, so now we copy the value out
1555 if (Subtarget->is64Bit() &&
1556 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1557 MachineFunction &MF = DAG.getMachineFunction();
1558 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1559 unsigned Reg = FuncInfo->getSRetReturnReg();
1561 "SRetReturnReg should have been set in LowerFormalArguments().");
1562 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1564 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag);
1565 Flag = Chain.getValue(1);
1567 // RAX now acts like a return value.
1568 MRI.addLiveOut(X86::RAX);
1571 RetOps[0] = Chain; // Update chain.
1573 // Add the flag if we have it.
1575 RetOps.push_back(Flag);
1577 return DAG.getNode(X86ISD::RET_FLAG, dl,
1578 MVT::Other, &RetOps[0], RetOps.size());
1581 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
1582 if (N->getNumValues() != 1)
1584 if (!N->hasNUsesOfValue(1, 0))
1587 SDValue TCChain = Chain;
1588 SDNode *Copy = *N->use_begin();
1589 if (Copy->getOpcode() == ISD::CopyToReg) {
1590 // If the copy has a glue operand, we conservatively assume it isn't safe to
1591 // perform a tail call.
1592 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
1594 TCChain = Copy->getOperand(0);
1595 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
1598 bool HasRet = false;
1599 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1601 if (UI->getOpcode() != X86ISD::RET_FLAG)
1614 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
1615 ISD::NodeType ExtendKind) const {
1617 // TODO: Is this also valid on 32-bit?
1618 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
1619 ReturnMVT = MVT::i8;
1621 ReturnMVT = MVT::i32;
1623 EVT MinVT = getRegisterType(Context, ReturnMVT);
1624 return VT.bitsLT(MinVT) ? MinVT : VT;
1627 /// LowerCallResult - Lower the result values of a call into the
1628 /// appropriate copies out of appropriate physical registers.
1631 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1632 CallingConv::ID CallConv, bool isVarArg,
1633 const SmallVectorImpl<ISD::InputArg> &Ins,
1634 DebugLoc dl, SelectionDAG &DAG,
1635 SmallVectorImpl<SDValue> &InVals) const {
1637 // Assign locations to each value returned by this call.
1638 SmallVector<CCValAssign, 16> RVLocs;
1639 bool Is64Bit = Subtarget->is64Bit();
1640 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1641 getTargetMachine(), RVLocs, *DAG.getContext());
1642 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1644 // Copy all of the result registers out of their specified physreg.
1645 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1646 CCValAssign &VA = RVLocs[i];
1647 EVT CopyVT = VA.getValVT();
1649 // If this is x86-64, and we disabled SSE, we can't return FP values
1650 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1651 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
1652 report_fatal_error("SSE register return with SSE disabled");
1657 // If this is a call to a function that returns an fp value on the floating
1658 // point stack, we must guarantee the the value is popped from the stack, so
1659 // a CopyFromReg is not good enough - the copy instruction may be eliminated
1660 // if the return value is not used. We use the FpPOP_RETVAL instruction
1662 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {
1663 // If we prefer to use the value in xmm registers, copy it out as f80 and
1664 // use a truncate to move it from fp stack reg to xmm reg.
1665 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
1666 SDValue Ops[] = { Chain, InFlag };
1667 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT,
1668 MVT::Other, MVT::Glue, Ops, 2), 1);
1669 Val = Chain.getValue(0);
1671 // Round the f80 to the right size, which also moves it to the appropriate
1673 if (CopyVT != VA.getValVT())
1674 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1675 // This truncation won't change the value.
1676 DAG.getIntPtrConstant(1));
1678 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1679 CopyVT, InFlag).getValue(1);
1680 Val = Chain.getValue(0);
1682 InFlag = Chain.getValue(2);
1683 InVals.push_back(Val);
1690 //===----------------------------------------------------------------------===//
1691 // C & StdCall & Fast Calling Convention implementation
1692 //===----------------------------------------------------------------------===//
1693 // StdCall calling convention seems to be standard for many Windows' API
1694 // routines and around. It differs from C calling convention just a little:
1695 // callee should clean up the stack, not caller. Symbols should be also
1696 // decorated in some fancy way :) It doesn't support any vector arguments.
1697 // For info on fast calling convention see Fast Calling Convention (tail call)
1698 // implementation LowerX86_32FastCCCallTo.
1700 /// CallIsStructReturn - Determines whether a call uses struct return
1702 static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
1706 return Outs[0].Flags.isSRet();
1709 /// ArgsAreStructReturn - Determines whether a function uses struct
1710 /// return semantics.
1712 ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
1716 return Ins[0].Flags.isSRet();
1719 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1720 /// by "Src" to address "Dst" with size and alignment information specified by
1721 /// the specific parameter attribute. The copy will be passed as a byval
1722 /// function parameter.
1724 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1725 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1727 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1729 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1730 /*isVolatile*/false, /*AlwaysInline=*/true,
1731 MachinePointerInfo(), MachinePointerInfo());
1734 /// IsTailCallConvention - Return true if the calling convention is one that
1735 /// supports tail call optimization.
1736 static bool IsTailCallConvention(CallingConv::ID CC) {
1737 return (CC == CallingConv::Fast || CC == CallingConv::GHC);
1740 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
1741 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
1745 CallingConv::ID CalleeCC = CS.getCallingConv();
1746 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C)
1752 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
1753 /// a tailcall target by changing its ABI.
1754 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
1755 bool GuaranteedTailCallOpt) {
1756 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
1760 X86TargetLowering::LowerMemArgument(SDValue Chain,
1761 CallingConv::ID CallConv,
1762 const SmallVectorImpl<ISD::InputArg> &Ins,
1763 DebugLoc dl, SelectionDAG &DAG,
1764 const CCValAssign &VA,
1765 MachineFrameInfo *MFI,
1767 // Create the nodes corresponding to a load from this parameter slot.
1768 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1769 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv,
1770 getTargetMachine().Options.GuaranteedTailCallOpt);
1771 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1774 // If value is passed by pointer we have address passed instead of the value
1776 if (VA.getLocInfo() == CCValAssign::Indirect)
1777 ValVT = VA.getLocVT();
1779 ValVT = VA.getValVT();
1781 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1782 // changed with more analysis.
1783 // In case of tail call optimization mark all arguments mutable. Since they
1784 // could be overwritten by lowering of arguments in case of a tail call.
1785 if (Flags.isByVal()) {
1786 unsigned Bytes = Flags.getByValSize();
1787 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
1788 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
1789 return DAG.getFrameIndex(FI, getPointerTy());
1791 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
1792 VA.getLocMemOffset(), isImmutable);
1793 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1794 return DAG.getLoad(ValVT, dl, Chain, FIN,
1795 MachinePointerInfo::getFixedStack(FI),
1796 false, false, false, 0);
1801 X86TargetLowering::LowerFormalArguments(SDValue Chain,
1802 CallingConv::ID CallConv,
1804 const SmallVectorImpl<ISD::InputArg> &Ins,
1807 SmallVectorImpl<SDValue> &InVals)
1809 MachineFunction &MF = DAG.getMachineFunction();
1810 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1812 const Function* Fn = MF.getFunction();
1813 if (Fn->hasExternalLinkage() &&
1814 Subtarget->isTargetCygMing() &&
1815 Fn->getName() == "main")
1816 FuncInfo->setForceFramePointer(true);
1818 MachineFrameInfo *MFI = MF.getFrameInfo();
1819 bool Is64Bit = Subtarget->is64Bit();
1820 bool IsWindows = Subtarget->isTargetWindows();
1821 bool IsWin64 = Subtarget->isTargetWin64();
1823 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
1824 "Var args not supported with calling convention fastcc or ghc");
1826 // Assign locations to all of the incoming arguments.
1827 SmallVector<CCValAssign, 16> ArgLocs;
1828 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1829 ArgLocs, *DAG.getContext());
1831 // Allocate shadow area for Win64
1833 CCInfo.AllocateStack(32, 8);
1836 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
1838 unsigned LastVal = ~0U;
1840 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1841 CCValAssign &VA = ArgLocs[i];
1842 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1844 assert(VA.getValNo() != LastVal &&
1845 "Don't support value assigned to multiple locs yet");
1847 LastVal = VA.getValNo();
1849 if (VA.isRegLoc()) {
1850 EVT RegVT = VA.getLocVT();
1851 const TargetRegisterClass *RC;
1852 if (RegVT == MVT::i32)
1853 RC = &X86::GR32RegClass;
1854 else if (Is64Bit && RegVT == MVT::i64)
1855 RC = &X86::GR64RegClass;
1856 else if (RegVT == MVT::f32)
1857 RC = &X86::FR32RegClass;
1858 else if (RegVT == MVT::f64)
1859 RC = &X86::FR64RegClass;
1860 else if (RegVT.isVector() && RegVT.getSizeInBits() == 256)
1861 RC = &X86::VR256RegClass;
1862 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128)
1863 RC = &X86::VR128RegClass;
1864 else if (RegVT == MVT::x86mmx)
1865 RC = &X86::VR64RegClass;
1867 llvm_unreachable("Unknown argument type!");
1869 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1870 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1872 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1873 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1875 if (VA.getLocInfo() == CCValAssign::SExt)
1876 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1877 DAG.getValueType(VA.getValVT()));
1878 else if (VA.getLocInfo() == CCValAssign::ZExt)
1879 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1880 DAG.getValueType(VA.getValVT()));
1881 else if (VA.getLocInfo() == CCValAssign::BCvt)
1882 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
1884 if (VA.isExtInLoc()) {
1885 // Handle MMX values passed in XMM regs.
1886 if (RegVT.isVector()) {
1887 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(),
1890 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1893 assert(VA.isMemLoc());
1894 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
1897 // If value is passed via pointer - do a load.
1898 if (VA.getLocInfo() == CCValAssign::Indirect)
1899 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
1900 MachinePointerInfo(), false, false, false, 0);
1902 InVals.push_back(ArgValue);
1905 // The x86-64 ABI for returning structs by value requires that we copy
1906 // the sret argument into %rax for the return. Save the argument into
1907 // a virtual register so that we can access it from the return points.
1908 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) {
1909 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1910 unsigned Reg = FuncInfo->getSRetReturnReg();
1912 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1913 FuncInfo->setSRetReturnReg(Reg);
1915 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
1916 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
1919 unsigned StackSize = CCInfo.getNextStackOffset();
1920 // Align stack specially for tail calls.
1921 if (FuncIsMadeTailCallSafe(CallConv,
1922 MF.getTarget().Options.GuaranteedTailCallOpt))
1923 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1925 // If the function takes variable number of arguments, make a frame index for
1926 // the start of the first vararg value... for expansion of llvm.va_start.
1928 if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
1929 CallConv != CallingConv::X86_ThisCall)) {
1930 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
1933 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
1935 // FIXME: We should really autogenerate these arrays
1936 static const uint16_t GPR64ArgRegsWin64[] = {
1937 X86::RCX, X86::RDX, X86::R8, X86::R9
1939 static const uint16_t GPR64ArgRegs64Bit[] = {
1940 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1942 static const uint16_t XMMArgRegs64Bit[] = {
1943 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1944 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1946 const uint16_t *GPR64ArgRegs;
1947 unsigned NumXMMRegs = 0;
1950 // The XMM registers which might contain var arg parameters are shadowed
1951 // in their paired GPR. So we only need to save the GPR to their home
1953 TotalNumIntRegs = 4;
1954 GPR64ArgRegs = GPR64ArgRegsWin64;
1956 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
1957 GPR64ArgRegs = GPR64ArgRegs64Bit;
1959 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit,
1962 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
1965 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat);
1966 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
1967 "SSE register cannot be used when SSE is disabled!");
1968 assert(!(NumXMMRegs && MF.getTarget().Options.UseSoftFloat &&
1969 NoImplicitFloatOps) &&
1970 "SSE register cannot be used when SSE is disabled!");
1971 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
1972 !Subtarget->hasSSE1())
1973 // Kernel mode asks for SSE to be disabled, so don't push them
1975 TotalNumXMMRegs = 0;
1978 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering();
1979 // Get to the caller-allocated home save location. Add 8 to account
1980 // for the return address.
1981 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
1982 FuncInfo->setRegSaveFrameIndex(
1983 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
1984 // Fixup to set vararg frame on shadow area (4 x i64).
1986 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
1988 // For X86-64, if there are vararg parameters that are passed via
1989 // registers, then we must store them to their spots on the stack so
1990 // they may be loaded by deferencing the result of va_next.
1991 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
1992 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
1993 FuncInfo->setRegSaveFrameIndex(
1994 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
1998 // Store the integer parameter registers.
1999 SmallVector<SDValue, 8> MemOps;
2000 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2002 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2003 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
2004 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2005 DAG.getIntPtrConstant(Offset));
2006 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
2007 &X86::GR64RegClass);
2008 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2010 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2011 MachinePointerInfo::getFixedStack(
2012 FuncInfo->getRegSaveFrameIndex(), Offset),
2014 MemOps.push_back(Store);
2018 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
2019 // Now store the XMM (fp + vector) parameter registers.
2020 SmallVector<SDValue, 11> SaveXMMOps;
2021 SaveXMMOps.push_back(Chain);
2023 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2024 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
2025 SaveXMMOps.push_back(ALVal);
2027 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2028 FuncInfo->getRegSaveFrameIndex()));
2029 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2030 FuncInfo->getVarArgsFPOffset()));
2032 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
2033 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs],
2034 &X86::VR128RegClass);
2035 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
2036 SaveXMMOps.push_back(Val);
2038 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2040 &SaveXMMOps[0], SaveXMMOps.size()));
2043 if (!MemOps.empty())
2044 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2045 &MemOps[0], MemOps.size());
2049 // Some CCs need callee pop.
2050 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2051 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2052 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2054 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2055 // If this is an sret function, the return should pop the hidden pointer.
2056 if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows &&
2057 ArgsAreStructReturn(Ins))
2058 FuncInfo->setBytesToPopOnReturn(4);
2062 // RegSaveFrameIndex is X86-64 only.
2063 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2064 if (CallConv == CallingConv::X86_FastCall ||
2065 CallConv == CallingConv::X86_ThisCall)
2066 // fastcc functions can't have varargs.
2067 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2070 FuncInfo->setArgumentStackSize(StackSize);
2076 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2077 SDValue StackPtr, SDValue Arg,
2078 DebugLoc dl, SelectionDAG &DAG,
2079 const CCValAssign &VA,
2080 ISD::ArgFlagsTy Flags) const {
2081 unsigned LocMemOffset = VA.getLocMemOffset();
2082 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2083 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2084 if (Flags.isByVal())
2085 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2087 return DAG.getStore(Chain, dl, Arg, PtrOff,
2088 MachinePointerInfo::getStack(LocMemOffset),
2092 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2093 /// optimization is performed and it is required.
2095 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2096 SDValue &OutRetAddr, SDValue Chain,
2097 bool IsTailCall, bool Is64Bit,
2098 int FPDiff, DebugLoc dl) const {
2099 // Adjust the Return address stack slot.
2100 EVT VT = getPointerTy();
2101 OutRetAddr = getReturnAddressFrameIndex(DAG);
2103 // Load the "old" Return address.
2104 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2105 false, false, false, 0);
2106 return SDValue(OutRetAddr.getNode(), 1);
2109 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2110 /// optimization is performed and it is required (FPDiff!=0).
2112 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
2113 SDValue Chain, SDValue RetAddrFrIdx,
2114 bool Is64Bit, int FPDiff, DebugLoc dl) {
2115 // Store the return address to the appropriate stack slot.
2116 if (!FPDiff) return Chain;
2117 // Calculate the new stack slot for the return address.
2118 int SlotSize = Is64Bit ? 8 : 4;
2119 int NewReturnAddrFI =
2120 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false);
2121 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
2122 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
2123 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2124 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2130 X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
2131 CallingConv::ID CallConv, bool isVarArg,
2132 bool doesNotRet, bool &isTailCall,
2133 const SmallVectorImpl<ISD::OutputArg> &Outs,
2134 const SmallVectorImpl<SDValue> &OutVals,
2135 const SmallVectorImpl<ISD::InputArg> &Ins,
2136 DebugLoc dl, SelectionDAG &DAG,
2137 SmallVectorImpl<SDValue> &InVals) const {
2138 MachineFunction &MF = DAG.getMachineFunction();
2139 bool Is64Bit = Subtarget->is64Bit();
2140 bool IsWin64 = Subtarget->isTargetWin64();
2141 bool IsWindows = Subtarget->isTargetWindows();
2142 bool IsStructRet = CallIsStructReturn(Outs);
2143 bool IsSibcall = false;
2145 if (MF.getTarget().Options.DisableTailCalls)
2149 // Check if it's really possible to do a tail call.
2150 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2151 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
2152 Outs, OutVals, Ins, DAG);
2154 // Sibcalls are automatically detected tailcalls which do not require
2156 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2163 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2164 "Var args not supported with calling convention fastcc or ghc");
2166 // Analyze operands of the call, assigning locations to each operand.
2167 SmallVector<CCValAssign, 16> ArgLocs;
2168 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
2169 ArgLocs, *DAG.getContext());
2171 // Allocate shadow area for Win64
2173 CCInfo.AllocateStack(32, 8);
2176 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2178 // Get a count of how many bytes are to be pushed on the stack.
2179 unsigned NumBytes = CCInfo.getNextStackOffset();
2181 // This is a sibcall. The memory operands are available in caller's
2182 // own caller's stack.
2184 else if (getTargetMachine().Options.GuaranteedTailCallOpt &&
2185 IsTailCallConvention(CallConv))
2186 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2189 if (isTailCall && !IsSibcall) {
2190 // Lower arguments at fp - stackoffset + fpdiff.
2191 unsigned NumBytesCallerPushed =
2192 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
2193 FPDiff = NumBytesCallerPushed - NumBytes;
2195 // Set the delta of movement of the returnaddr stackslot.
2196 // But only set if delta is greater than previous delta.
2197 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
2198 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
2202 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
2204 SDValue RetAddrFrIdx;
2205 // Load return address for tail calls.
2206 if (isTailCall && FPDiff)
2207 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2208 Is64Bit, FPDiff, dl);
2210 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2211 SmallVector<SDValue, 8> MemOpChains;
2214 // Walk the register/memloc assignments, inserting copies/loads. In the case
2215 // of tail call optimization arguments are handle later.
2216 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2217 CCValAssign &VA = ArgLocs[i];
2218 EVT RegVT = VA.getLocVT();
2219 SDValue Arg = OutVals[i];
2220 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2221 bool isByVal = Flags.isByVal();
2223 // Promote the value if needed.
2224 switch (VA.getLocInfo()) {
2225 default: llvm_unreachable("Unknown loc info!");
2226 case CCValAssign::Full: break;
2227 case CCValAssign::SExt:
2228 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2230 case CCValAssign::ZExt:
2231 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2233 case CCValAssign::AExt:
2234 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) {
2235 // Special case: passing MMX values in XMM registers.
2236 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2237 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2238 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2240 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2242 case CCValAssign::BCvt:
2243 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2245 case CCValAssign::Indirect: {
2246 // Store the argument.
2247 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2248 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2249 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2250 MachinePointerInfo::getFixedStack(FI),
2257 if (VA.isRegLoc()) {
2258 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2259 if (isVarArg && IsWin64) {
2260 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2261 // shadow reg if callee is a varargs function.
2262 unsigned ShadowReg = 0;
2263 switch (VA.getLocReg()) {
2264 case X86::XMM0: ShadowReg = X86::RCX; break;
2265 case X86::XMM1: ShadowReg = X86::RDX; break;
2266 case X86::XMM2: ShadowReg = X86::R8; break;
2267 case X86::XMM3: ShadowReg = X86::R9; break;
2270 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2272 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2273 assert(VA.isMemLoc());
2274 if (StackPtr.getNode() == 0)
2275 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy());
2276 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2277 dl, DAG, VA, Flags));
2281 if (!MemOpChains.empty())
2282 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2283 &MemOpChains[0], MemOpChains.size());
2285 // Build a sequence of copy-to-reg nodes chained together with token chain
2286 // and flag operands which copy the outgoing args into registers.
2288 // Tail call byval lowering might overwrite argument registers so in case of
2289 // tail call optimization the copies to registers are lowered later.
2291 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2292 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2293 RegsToPass[i].second, InFlag);
2294 InFlag = Chain.getValue(1);
2297 if (Subtarget->isPICStyleGOT()) {
2298 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2301 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX,
2302 DAG.getNode(X86ISD::GlobalBaseReg,
2303 DebugLoc(), getPointerTy()),
2305 InFlag = Chain.getValue(1);
2307 // If we are tail calling and generating PIC/GOT style code load the
2308 // address of the callee into ECX. The value in ecx is used as target of
2309 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2310 // for tail calls on PIC/GOT architectures. Normally we would just put the
2311 // address of GOT into ebx and then call target@PLT. But for tail calls
2312 // ebx would be restored (since ebx is callee saved) before jumping to the
2315 // Note: The actual moving to ECX is done further down.
2316 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2317 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2318 !G->getGlobal()->hasProtectedVisibility())
2319 Callee = LowerGlobalAddress(Callee, DAG);
2320 else if (isa<ExternalSymbolSDNode>(Callee))
2321 Callee = LowerExternalSymbol(Callee, DAG);
2325 if (Is64Bit && isVarArg && !IsWin64) {
2326 // From AMD64 ABI document:
2327 // For calls that may call functions that use varargs or stdargs
2328 // (prototype-less calls or calls to functions containing ellipsis (...) in
2329 // the declaration) %al is used as hidden argument to specify the number
2330 // of SSE registers used. The contents of %al do not need to match exactly
2331 // the number of registers, but must be an ubound on the number of SSE
2332 // registers used and is in the range 0 - 8 inclusive.
2334 // Count the number of XMM registers allocated.
2335 static const uint16_t XMMArgRegs[] = {
2336 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2337 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2339 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2340 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2341 && "SSE registers cannot be used when SSE is disabled");
2343 Chain = DAG.getCopyToReg(Chain, dl, X86::AL,
2344 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
2345 InFlag = Chain.getValue(1);
2349 // For tail calls lower the arguments to the 'real' stack slot.
2351 // Force all the incoming stack arguments to be loaded from the stack
2352 // before any new outgoing arguments are stored to the stack, because the
2353 // outgoing stack slots may alias the incoming argument stack slots, and
2354 // the alias isn't otherwise explicit. This is slightly more conservative
2355 // than necessary, because it means that each store effectively depends
2356 // on every argument instead of just those arguments it would clobber.
2357 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2359 SmallVector<SDValue, 8> MemOpChains2;
2362 // Do not flag preceding copytoreg stuff together with the following stuff.
2364 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2365 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2366 CCValAssign &VA = ArgLocs[i];
2369 assert(VA.isMemLoc());
2370 SDValue Arg = OutVals[i];
2371 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2372 // Create frame index.
2373 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2374 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2375 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2376 FIN = DAG.getFrameIndex(FI, getPointerTy());
2378 if (Flags.isByVal()) {
2379 // Copy relative to framepointer.
2380 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2381 if (StackPtr.getNode() == 0)
2382 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr,
2384 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2386 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2390 // Store relative to framepointer.
2391 MemOpChains2.push_back(
2392 DAG.getStore(ArgChain, dl, Arg, FIN,
2393 MachinePointerInfo::getFixedStack(FI),
2399 if (!MemOpChains2.empty())
2400 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2401 &MemOpChains2[0], MemOpChains2.size());
2403 // Copy arguments to their registers.
2404 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2405 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2406 RegsToPass[i].second, InFlag);
2407 InFlag = Chain.getValue(1);
2411 // Store the return address to the appropriate stack slot.
2412 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
2416 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2417 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2418 // In the 64-bit large code model, we have to make all calls
2419 // through a register, since the call instruction's 32-bit
2420 // pc-relative offset may not be large enough to hold the whole
2422 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2423 // If the callee is a GlobalAddress node (quite common, every direct call
2424 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2427 // We should use extra load for direct calls to dllimported functions in
2429 const GlobalValue *GV = G->getGlobal();
2430 if (!GV->hasDLLImportLinkage()) {
2431 unsigned char OpFlags = 0;
2432 bool ExtraLoad = false;
2433 unsigned WrapperKind = ISD::DELETED_NODE;
2435 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2436 // external symbols most go through the PLT in PIC mode. If the symbol
2437 // has hidden or protected visibility, or if it is static or local, then
2438 // we don't need to use the PLT - we can directly call it.
2439 if (Subtarget->isTargetELF() &&
2440 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2441 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2442 OpFlags = X86II::MO_PLT;
2443 } else if (Subtarget->isPICStyleStubAny() &&
2444 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2445 (!Subtarget->getTargetTriple().isMacOSX() ||
2446 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2447 // PC-relative references to external symbols should go through $stub,
2448 // unless we're building with the leopard linker or later, which
2449 // automatically synthesizes these stubs.
2450 OpFlags = X86II::MO_DARWIN_STUB;
2451 } else if (Subtarget->isPICStyleRIPRel() &&
2452 isa<Function>(GV) &&
2453 cast<Function>(GV)->hasFnAttr(Attribute::NonLazyBind)) {
2454 // If the function is marked as non-lazy, generate an indirect call
2455 // which loads from the GOT directly. This avoids runtime overhead
2456 // at the cost of eager binding (and one extra byte of encoding).
2457 OpFlags = X86II::MO_GOTPCREL;
2458 WrapperKind = X86ISD::WrapperRIP;
2462 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2463 G->getOffset(), OpFlags);
2465 // Add a wrapper if needed.
2466 if (WrapperKind != ISD::DELETED_NODE)
2467 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
2468 // Add extra indirection if needed.
2470 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
2471 MachinePointerInfo::getGOT(),
2472 false, false, false, 0);
2474 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2475 unsigned char OpFlags = 0;
2477 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
2478 // external symbols should go through the PLT.
2479 if (Subtarget->isTargetELF() &&
2480 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2481 OpFlags = X86II::MO_PLT;
2482 } else if (Subtarget->isPICStyleStubAny() &&
2483 (!Subtarget->getTargetTriple().isMacOSX() ||
2484 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2485 // PC-relative references to external symbols should go through $stub,
2486 // unless we're building with the leopard linker or later, which
2487 // automatically synthesizes these stubs.
2488 OpFlags = X86II::MO_DARWIN_STUB;
2491 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2495 // Returns a chain & a flag for retval copy to use.
2496 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2497 SmallVector<SDValue, 8> Ops;
2499 if (!IsSibcall && isTailCall) {
2500 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2501 DAG.getIntPtrConstant(0, true), InFlag);
2502 InFlag = Chain.getValue(1);
2505 Ops.push_back(Chain);
2506 Ops.push_back(Callee);
2509 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2511 // Add argument registers to the end of the list so that they are known live
2513 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2514 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2515 RegsToPass[i].second.getValueType()));
2517 // Add an implicit use GOT pointer in EBX.
2518 if (!isTailCall && Subtarget->isPICStyleGOT())
2519 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
2521 // Add an implicit use of AL for non-Windows x86 64-bit vararg functions.
2522 if (Is64Bit && isVarArg && !IsWin64)
2523 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
2525 // Add a register mask operand representing the call-preserved registers.
2526 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2527 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
2528 assert(Mask && "Missing call preserved mask for calling convention");
2529 Ops.push_back(DAG.getRegisterMask(Mask));
2531 if (InFlag.getNode())
2532 Ops.push_back(InFlag);
2536 //// If this is the first return lowered for this function, add the regs
2537 //// to the liveout set for the function.
2538 // This isn't right, although it's probably harmless on x86; liveouts
2539 // should be computed from returns not tail calls. Consider a void
2540 // function making a tail call to a function returning int.
2541 return DAG.getNode(X86ISD::TC_RETURN, dl,
2542 NodeTys, &Ops[0], Ops.size());
2545 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2546 InFlag = Chain.getValue(1);
2548 // Create the CALLSEQ_END node.
2549 unsigned NumBytesForCalleeToPush;
2550 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2551 getTargetMachine().Options.GuaranteedTailCallOpt))
2552 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2553 else if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows &&
2555 // If this is a call to a struct-return function, the callee
2556 // pops the hidden struct pointer, so we have to push it back.
2557 // This is common for Darwin/X86, Linux & Mingw32 targets.
2558 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
2559 NumBytesForCalleeToPush = 4;
2561 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2563 // Returns a flag for retval copy to use.
2565 Chain = DAG.getCALLSEQ_END(Chain,
2566 DAG.getIntPtrConstant(NumBytes, true),
2567 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2570 InFlag = Chain.getValue(1);
2573 // Handle result values, copying them out of physregs into vregs that we
2575 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2576 Ins, dl, DAG, InVals);
2580 //===----------------------------------------------------------------------===//
2581 // Fast Calling Convention (tail call) implementation
2582 //===----------------------------------------------------------------------===//
2584 // Like std call, callee cleans arguments, convention except that ECX is
2585 // reserved for storing the tail called function address. Only 2 registers are
2586 // free for argument passing (inreg). Tail call optimization is performed
2588 // * tailcallopt is enabled
2589 // * caller/callee are fastcc
2590 // On X86_64 architecture with GOT-style position independent code only local
2591 // (within module) calls are supported at the moment.
2592 // To keep the stack aligned according to platform abi the function
2593 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2594 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2595 // If a tail called function callee has more arguments than the caller the
2596 // caller needs to make sure that there is room to move the RETADDR to. This is
2597 // achieved by reserving an area the size of the argument delta right after the
2598 // original REtADDR, but before the saved framepointer or the spilled registers
2599 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2611 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2612 /// for a 16 byte align requirement.
2614 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2615 SelectionDAG& DAG) const {
2616 MachineFunction &MF = DAG.getMachineFunction();
2617 const TargetMachine &TM = MF.getTarget();
2618 const TargetFrameLowering &TFI = *TM.getFrameLowering();
2619 unsigned StackAlignment = TFI.getStackAlignment();
2620 uint64_t AlignMask = StackAlignment - 1;
2621 int64_t Offset = StackSize;
2622 uint64_t SlotSize = TD->getPointerSize();
2623 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2624 // Number smaller than 12 so just add the difference.
2625 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2627 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2628 Offset = ((~AlignMask) & Offset) + StackAlignment +
2629 (StackAlignment-SlotSize);
2634 /// MatchingStackOffset - Return true if the given stack call argument is
2635 /// already available in the same position (relatively) of the caller's
2636 /// incoming argument stack.
2638 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2639 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
2640 const X86InstrInfo *TII) {
2641 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
2643 if (Arg.getOpcode() == ISD::CopyFromReg) {
2644 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2645 if (!TargetRegisterInfo::isVirtualRegister(VR))
2647 MachineInstr *Def = MRI->getVRegDef(VR);
2650 if (!Flags.isByVal()) {
2651 if (!TII->isLoadFromStackSlot(Def, FI))
2654 unsigned Opcode = Def->getOpcode();
2655 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
2656 Def->getOperand(1).isFI()) {
2657 FI = Def->getOperand(1).getIndex();
2658 Bytes = Flags.getByValSize();
2662 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2663 if (Flags.isByVal())
2664 // ByVal argument is passed in as a pointer but it's now being
2665 // dereferenced. e.g.
2666 // define @foo(%struct.X* %A) {
2667 // tail call @bar(%struct.X* byval %A)
2670 SDValue Ptr = Ld->getBasePtr();
2671 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2674 FI = FINode->getIndex();
2675 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
2676 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
2677 FI = FINode->getIndex();
2678 Bytes = Flags.getByValSize();
2682 assert(FI != INT_MAX);
2683 if (!MFI->isFixedObjectIndex(FI))
2685 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
2688 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2689 /// for tail call optimization. Targets which want to do tail call
2690 /// optimization should implement this function.
2692 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2693 CallingConv::ID CalleeCC,
2695 bool isCalleeStructRet,
2696 bool isCallerStructRet,
2697 const SmallVectorImpl<ISD::OutputArg> &Outs,
2698 const SmallVectorImpl<SDValue> &OutVals,
2699 const SmallVectorImpl<ISD::InputArg> &Ins,
2700 SelectionDAG& DAG) const {
2701 if (!IsTailCallConvention(CalleeCC) &&
2702 CalleeCC != CallingConv::C)
2705 // If -tailcallopt is specified, make fastcc functions tail-callable.
2706 const MachineFunction &MF = DAG.getMachineFunction();
2707 const Function *CallerF = DAG.getMachineFunction().getFunction();
2708 CallingConv::ID CallerCC = CallerF->getCallingConv();
2709 bool CCMatch = CallerCC == CalleeCC;
2711 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2712 if (IsTailCallConvention(CalleeCC) && CCMatch)
2717 // Look for obvious safe cases to perform tail call optimization that do not
2718 // require ABI changes. This is what gcc calls sibcall.
2720 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
2721 // emit a special epilogue.
2722 if (RegInfo->needsStackRealignment(MF))
2725 // Also avoid sibcall optimization if either caller or callee uses struct
2726 // return semantics.
2727 if (isCalleeStructRet || isCallerStructRet)
2730 // An stdcall caller is expected to clean up its arguments; the callee
2731 // isn't going to do that.
2732 if (!CCMatch && CallerCC==CallingConv::X86_StdCall)
2735 // Do not sibcall optimize vararg calls unless all arguments are passed via
2737 if (isVarArg && !Outs.empty()) {
2739 // Optimizing for varargs on Win64 is unlikely to be safe without
2740 // additional testing.
2741 if (Subtarget->isTargetWin64())
2744 SmallVector<CCValAssign, 16> ArgLocs;
2745 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2746 getTargetMachine(), ArgLocs, *DAG.getContext());
2748 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2749 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
2750 if (!ArgLocs[i].isRegLoc())
2754 // If the call result is in ST0 / ST1, it needs to be popped off the x87
2755 // stack. Therefore, if it's not used by the call it is not safe to optimize
2756 // this into a sibcall.
2757 bool Unused = false;
2758 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
2765 SmallVector<CCValAssign, 16> RVLocs;
2766 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(),
2767 getTargetMachine(), RVLocs, *DAG.getContext());
2768 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2769 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2770 CCValAssign &VA = RVLocs[i];
2771 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
2776 // If the calling conventions do not match, then we'd better make sure the
2777 // results are returned in the same way as what the caller expects.
2779 SmallVector<CCValAssign, 16> RVLocs1;
2780 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
2781 getTargetMachine(), RVLocs1, *DAG.getContext());
2782 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
2784 SmallVector<CCValAssign, 16> RVLocs2;
2785 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
2786 getTargetMachine(), RVLocs2, *DAG.getContext());
2787 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
2789 if (RVLocs1.size() != RVLocs2.size())
2791 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2792 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2794 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2796 if (RVLocs1[i].isRegLoc()) {
2797 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2800 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2806 // If the callee takes no arguments then go on to check the results of the
2808 if (!Outs.empty()) {
2809 // Check if stack adjustment is needed. For now, do not do this if any
2810 // argument is passed on the stack.
2811 SmallVector<CCValAssign, 16> ArgLocs;
2812 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2813 getTargetMachine(), ArgLocs, *DAG.getContext());
2815 // Allocate shadow area for Win64
2816 if (Subtarget->isTargetWin64()) {
2817 CCInfo.AllocateStack(32, 8);
2820 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2821 if (CCInfo.getNextStackOffset()) {
2822 MachineFunction &MF = DAG.getMachineFunction();
2823 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
2826 // Check if the arguments are already laid out in the right way as
2827 // the caller's fixed stack objects.
2828 MachineFrameInfo *MFI = MF.getFrameInfo();
2829 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2830 const X86InstrInfo *TII =
2831 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
2832 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2833 CCValAssign &VA = ArgLocs[i];
2834 SDValue Arg = OutVals[i];
2835 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2836 if (VA.getLocInfo() == CCValAssign::Indirect)
2838 if (!VA.isRegLoc()) {
2839 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2846 // If the tailcall address may be in a register, then make sure it's
2847 // possible to register allocate for it. In 32-bit, the call address can
2848 // only target EAX, EDX, or ECX since the tail call must be scheduled after
2849 // callee-saved registers are restored. These happen to be the same
2850 // registers used to pass 'inreg' arguments so watch out for those.
2851 if (!Subtarget->is64Bit() &&
2852 !isa<GlobalAddressSDNode>(Callee) &&
2853 !isa<ExternalSymbolSDNode>(Callee)) {
2854 unsigned NumInRegs = 0;
2855 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2856 CCValAssign &VA = ArgLocs[i];
2859 unsigned Reg = VA.getLocReg();
2862 case X86::EAX: case X86::EDX: case X86::ECX:
2863 if (++NumInRegs == 3)
2875 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const {
2876 return X86::createFastISel(funcInfo);
2880 //===----------------------------------------------------------------------===//
2881 // Other Lowering Hooks
2882 //===----------------------------------------------------------------------===//
2884 static bool MayFoldLoad(SDValue Op) {
2885 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
2888 static bool MayFoldIntoStore(SDValue Op) {
2889 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
2892 static bool isTargetShuffle(unsigned Opcode) {
2894 default: return false;
2895 case X86ISD::PSHUFD:
2896 case X86ISD::PSHUFHW:
2897 case X86ISD::PSHUFLW:
2899 case X86ISD::PALIGN:
2900 case X86ISD::MOVLHPS:
2901 case X86ISD::MOVLHPD:
2902 case X86ISD::MOVHLPS:
2903 case X86ISD::MOVLPS:
2904 case X86ISD::MOVLPD:
2905 case X86ISD::MOVSHDUP:
2906 case X86ISD::MOVSLDUP:
2907 case X86ISD::MOVDDUP:
2910 case X86ISD::UNPCKL:
2911 case X86ISD::UNPCKH:
2912 case X86ISD::VPERMILP:
2913 case X86ISD::VPERM2X128:
2918 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2919 SDValue V1, SelectionDAG &DAG) {
2921 default: llvm_unreachable("Unknown x86 shuffle node");
2922 case X86ISD::MOVSHDUP:
2923 case X86ISD::MOVSLDUP:
2924 case X86ISD::MOVDDUP:
2925 return DAG.getNode(Opc, dl, VT, V1);
2929 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2930 SDValue V1, unsigned TargetMask,
2931 SelectionDAG &DAG) {
2933 default: llvm_unreachable("Unknown x86 shuffle node");
2934 case X86ISD::PSHUFD:
2935 case X86ISD::PSHUFHW:
2936 case X86ISD::PSHUFLW:
2937 case X86ISD::VPERMILP:
2938 case X86ISD::VPERMI:
2939 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
2943 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2944 SDValue V1, SDValue V2, unsigned TargetMask,
2945 SelectionDAG &DAG) {
2947 default: llvm_unreachable("Unknown x86 shuffle node");
2948 case X86ISD::PALIGN:
2950 case X86ISD::VPERM2X128:
2951 return DAG.getNode(Opc, dl, VT, V1, V2,
2952 DAG.getConstant(TargetMask, MVT::i8));
2956 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2957 SDValue V1, SDValue V2, SelectionDAG &DAG) {
2959 default: llvm_unreachable("Unknown x86 shuffle node");
2960 case X86ISD::MOVLHPS:
2961 case X86ISD::MOVLHPD:
2962 case X86ISD::MOVHLPS:
2963 case X86ISD::MOVLPS:
2964 case X86ISD::MOVLPD:
2967 case X86ISD::UNPCKL:
2968 case X86ISD::UNPCKH:
2969 return DAG.getNode(Opc, dl, VT, V1, V2);
2973 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
2974 MachineFunction &MF = DAG.getMachineFunction();
2975 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2976 int ReturnAddrIndex = FuncInfo->getRAIndex();
2978 if (ReturnAddrIndex == 0) {
2979 // Set up a frame object for the return address.
2980 uint64_t SlotSize = TD->getPointerSize();
2981 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
2983 FuncInfo->setRAIndex(ReturnAddrIndex);
2986 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
2990 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
2991 bool hasSymbolicDisplacement) {
2992 // Offset should fit into 32 bit immediate field.
2993 if (!isInt<32>(Offset))
2996 // If we don't have a symbolic displacement - we don't have any extra
2998 if (!hasSymbolicDisplacement)
3001 // FIXME: Some tweaks might be needed for medium code model.
3002 if (M != CodeModel::Small && M != CodeModel::Kernel)
3005 // For small code model we assume that latest object is 16MB before end of 31
3006 // bits boundary. We may also accept pretty large negative constants knowing
3007 // that all objects are in the positive half of address space.
3008 if (M == CodeModel::Small && Offset < 16*1024*1024)
3011 // For kernel code model we know that all object resist in the negative half
3012 // of 32bits address space. We may not accept negative offsets, since they may
3013 // be just off and we may accept pretty large positive ones.
3014 if (M == CodeModel::Kernel && Offset > 0)
3020 /// isCalleePop - Determines whether the callee is required to pop its
3021 /// own arguments. Callee pop is necessary to support tail calls.
3022 bool X86::isCalleePop(CallingConv::ID CallingConv,
3023 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3027 switch (CallingConv) {
3030 case CallingConv::X86_StdCall:
3032 case CallingConv::X86_FastCall:
3034 case CallingConv::X86_ThisCall:
3036 case CallingConv::Fast:
3038 case CallingConv::GHC:
3043 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3044 /// specific condition code, returning the condition code and the LHS/RHS of the
3045 /// comparison to make.
3046 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3047 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3049 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3050 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3051 // X > -1 -> X == 0, jump !sign.
3052 RHS = DAG.getConstant(0, RHS.getValueType());
3053 return X86::COND_NS;
3055 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3056 // X < 0 -> X == 0, jump on sign.
3059 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3061 RHS = DAG.getConstant(0, RHS.getValueType());
3062 return X86::COND_LE;
3066 switch (SetCCOpcode) {
3067 default: llvm_unreachable("Invalid integer condition!");
3068 case ISD::SETEQ: return X86::COND_E;
3069 case ISD::SETGT: return X86::COND_G;
3070 case ISD::SETGE: return X86::COND_GE;
3071 case ISD::SETLT: return X86::COND_L;
3072 case ISD::SETLE: return X86::COND_LE;
3073 case ISD::SETNE: return X86::COND_NE;
3074 case ISD::SETULT: return X86::COND_B;
3075 case ISD::SETUGT: return X86::COND_A;
3076 case ISD::SETULE: return X86::COND_BE;
3077 case ISD::SETUGE: return X86::COND_AE;
3081 // First determine if it is required or is profitable to flip the operands.
3083 // If LHS is a foldable load, but RHS is not, flip the condition.
3084 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3085 !ISD::isNON_EXTLoad(RHS.getNode())) {
3086 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3087 std::swap(LHS, RHS);
3090 switch (SetCCOpcode) {
3096 std::swap(LHS, RHS);
3100 // On a floating point condition, the flags are set as follows:
3102 // 0 | 0 | 0 | X > Y
3103 // 0 | 0 | 1 | X < Y
3104 // 1 | 0 | 0 | X == Y
3105 // 1 | 1 | 1 | unordered
3106 switch (SetCCOpcode) {
3107 default: llvm_unreachable("Condcode should be pre-legalized away");
3109 case ISD::SETEQ: return X86::COND_E;
3110 case ISD::SETOLT: // flipped
3112 case ISD::SETGT: return X86::COND_A;
3113 case ISD::SETOLE: // flipped
3115 case ISD::SETGE: return X86::COND_AE;
3116 case ISD::SETUGT: // flipped
3118 case ISD::SETLT: return X86::COND_B;
3119 case ISD::SETUGE: // flipped
3121 case ISD::SETLE: return X86::COND_BE;
3123 case ISD::SETNE: return X86::COND_NE;
3124 case ISD::SETUO: return X86::COND_P;
3125 case ISD::SETO: return X86::COND_NP;
3127 case ISD::SETUNE: return X86::COND_INVALID;
3131 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3132 /// code. Current x86 isa includes the following FP cmov instructions:
3133 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3134 static bool hasFPCMov(unsigned X86CC) {
3150 /// isFPImmLegal - Returns true if the target can instruction select the
3151 /// specified FP immediate natively. If false, the legalizer will
3152 /// materialize the FP immediate as a load from a constant pool.
3153 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3154 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3155 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3161 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3162 /// the specified range (L, H].
3163 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3164 return (Val < 0) || (Val >= Low && Val < Hi);
3167 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3168 /// specified value.
3169 static bool isUndefOrEqual(int Val, int CmpVal) {
3170 if (Val < 0 || Val == CmpVal)
3175 /// isSequentialOrUndefInRange - Return true if every element in Mask, begining
3176 /// from position Pos and ending in Pos+Size, falls within the specified
3177 /// sequential range (L, L+Pos]. or is undef.
3178 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3179 int Pos, int Size, int Low) {
3180 for (int i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3181 if (!isUndefOrEqual(Mask[i], Low))
3186 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3187 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3188 /// the second operand.
3189 static bool isPSHUFDMask(ArrayRef<int> Mask, EVT VT) {
3190 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3191 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3192 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3193 return (Mask[0] < 2 && Mask[1] < 2);
3197 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3198 /// is suitable for input to PSHUFHW.
3199 static bool isPSHUFHWMask(ArrayRef<int> Mask, EVT VT) {
3200 if (VT != MVT::v8i16)
3203 // Lower quadword copied in order or undef.
3204 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3207 // Upper quadword shuffled.
3208 for (unsigned i = 4; i != 8; ++i)
3209 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7))
3215 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3216 /// is suitable for input to PSHUFLW.
3217 static bool isPSHUFLWMask(ArrayRef<int> Mask, EVT VT) {
3218 if (VT != MVT::v8i16)
3221 // Upper quadword copied in order.
3222 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3225 // Lower quadword shuffled.
3226 for (unsigned i = 0; i != 4; ++i)
3233 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
3234 /// is suitable for input to PALIGNR.
3235 static bool isPALIGNRMask(ArrayRef<int> Mask, EVT VT,
3236 const X86Subtarget *Subtarget) {
3237 if ((VT.getSizeInBits() == 128 && !Subtarget->hasSSSE3()) ||
3238 (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2()))
3241 unsigned NumElts = VT.getVectorNumElements();
3242 unsigned NumLanes = VT.getSizeInBits()/128;
3243 unsigned NumLaneElts = NumElts/NumLanes;
3245 // Do not handle 64-bit element shuffles with palignr.
3246 if (NumLaneElts == 2)
3249 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3251 for (i = 0; i != NumLaneElts; ++i) {
3256 // Lane is all undef, go to next lane
3257 if (i == NumLaneElts)
3260 int Start = Mask[i+l];
3262 // Make sure its in this lane in one of the sources
3263 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3264 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3267 // If not lane 0, then we must match lane 0
3268 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3271 // Correct second source to be contiguous with first source
3272 if (Start >= (int)NumElts)
3273 Start -= NumElts - NumLaneElts;
3275 // Make sure we're shifting in the right direction.
3276 if (Start <= (int)(i+l))
3281 // Check the rest of the elements to see if they are consecutive.
3282 for (++i; i != NumLaneElts; ++i) {
3283 int Idx = Mask[i+l];
3285 // Make sure its in this lane
3286 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3287 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3290 // If not lane 0, then we must match lane 0
3291 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3294 if (Idx >= (int)NumElts)
3295 Idx -= NumElts - NumLaneElts;
3297 if (!isUndefOrEqual(Idx, Start+i))
3306 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3307 /// the two vector operands have swapped position.
3308 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
3309 unsigned NumElems) {
3310 for (unsigned i = 0; i != NumElems; ++i) {
3314 else if (idx < (int)NumElems)
3315 Mask[i] = idx + NumElems;
3317 Mask[i] = idx - NumElems;
3321 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
3322 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
3323 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
3324 /// reverse of what x86 shuffles want.
3325 static bool isSHUFPMask(ArrayRef<int> Mask, EVT VT, bool HasAVX,
3326 bool Commuted = false) {
3327 if (!HasAVX && VT.getSizeInBits() == 256)
3330 unsigned NumElems = VT.getVectorNumElements();
3331 unsigned NumLanes = VT.getSizeInBits()/128;
3332 unsigned NumLaneElems = NumElems/NumLanes;
3334 if (NumLaneElems != 2 && NumLaneElems != 4)
3337 // VSHUFPSY divides the resulting vector into 4 chunks.
3338 // The sources are also splitted into 4 chunks, and each destination
3339 // chunk must come from a different source chunk.
3341 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
3342 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
3344 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
3345 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
3347 // VSHUFPDY divides the resulting vector into 4 chunks.
3348 // The sources are also splitted into 4 chunks, and each destination
3349 // chunk must come from a different source chunk.
3351 // SRC1 => X3 X2 X1 X0
3352 // SRC2 => Y3 Y2 Y1 Y0
3354 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
3356 unsigned HalfLaneElems = NumLaneElems/2;
3357 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
3358 for (unsigned i = 0; i != NumLaneElems; ++i) {
3359 int Idx = Mask[i+l];
3360 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
3361 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
3363 // For VSHUFPSY, the mask of the second half must be the same as the
3364 // first but with the appropriate offsets. This works in the same way as
3365 // VPERMILPS works with masks.
3366 if (NumElems != 8 || l == 0 || Mask[i] < 0)
3368 if (!isUndefOrEqual(Idx, Mask[i]+l))
3376 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
3377 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
3378 static bool isMOVHLPSMask(ArrayRef<int> Mask, EVT VT) {
3379 unsigned NumElems = VT.getVectorNumElements();
3381 if (VT.getSizeInBits() != 128)
3387 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
3388 return isUndefOrEqual(Mask[0], 6) &&
3389 isUndefOrEqual(Mask[1], 7) &&
3390 isUndefOrEqual(Mask[2], 2) &&
3391 isUndefOrEqual(Mask[3], 3);
3394 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
3395 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
3397 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, EVT VT) {
3398 unsigned NumElems = VT.getVectorNumElements();
3400 if (VT.getSizeInBits() != 128)
3406 return isUndefOrEqual(Mask[0], 2) &&
3407 isUndefOrEqual(Mask[1], 3) &&
3408 isUndefOrEqual(Mask[2], 2) &&
3409 isUndefOrEqual(Mask[3], 3);
3412 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
3413 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
3414 static bool isMOVLPMask(ArrayRef<int> Mask, EVT VT) {
3415 if (VT.getSizeInBits() != 128)
3418 unsigned NumElems = VT.getVectorNumElements();
3420 if (NumElems != 2 && NumElems != 4)
3423 for (unsigned i = 0; i != NumElems/2; ++i)
3424 if (!isUndefOrEqual(Mask[i], i + NumElems))
3427 for (unsigned i = NumElems/2; i != NumElems; ++i)
3428 if (!isUndefOrEqual(Mask[i], i))
3434 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
3435 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
3436 static bool isMOVLHPSMask(ArrayRef<int> Mask, EVT VT) {
3437 unsigned NumElems = VT.getVectorNumElements();
3439 if ((NumElems != 2 && NumElems != 4)
3440 || VT.getSizeInBits() > 128)
3443 for (unsigned i = 0; i != NumElems/2; ++i)
3444 if (!isUndefOrEqual(Mask[i], i))
3447 for (unsigned i = 0; i != NumElems/2; ++i)
3448 if (!isUndefOrEqual(Mask[i + NumElems/2], i + NumElems))
3454 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
3455 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
3456 static bool isUNPCKLMask(ArrayRef<int> Mask, EVT VT,
3457 bool HasAVX2, bool V2IsSplat = false) {
3458 unsigned NumElts = VT.getVectorNumElements();
3460 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3461 "Unsupported vector type for unpckh");
3463 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3464 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3467 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3468 // independently on 128-bit lanes.
3469 unsigned NumLanes = VT.getSizeInBits()/128;
3470 unsigned NumLaneElts = NumElts/NumLanes;
3472 for (unsigned l = 0; l != NumLanes; ++l) {
3473 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts;
3474 i != (l+1)*NumLaneElts;
3477 int BitI1 = Mask[i+1];
3478 if (!isUndefOrEqual(BitI, j))
3481 if (!isUndefOrEqual(BitI1, NumElts))
3484 if (!isUndefOrEqual(BitI1, j + NumElts))
3493 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
3494 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
3495 static bool isUNPCKHMask(ArrayRef<int> Mask, EVT VT,
3496 bool HasAVX2, bool V2IsSplat = false) {
3497 unsigned NumElts = VT.getVectorNumElements();
3499 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3500 "Unsupported vector type for unpckh");
3502 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3503 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3506 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3507 // independently on 128-bit lanes.
3508 unsigned NumLanes = VT.getSizeInBits()/128;
3509 unsigned NumLaneElts = NumElts/NumLanes;
3511 for (unsigned l = 0; l != NumLanes; ++l) {
3512 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2;
3513 i != (l+1)*NumLaneElts; i += 2, ++j) {
3515 int BitI1 = Mask[i+1];
3516 if (!isUndefOrEqual(BitI, j))
3519 if (isUndefOrEqual(BitI1, NumElts))
3522 if (!isUndefOrEqual(BitI1, j+NumElts))
3530 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
3531 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
3533 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, EVT VT,
3535 unsigned NumElts = VT.getVectorNumElements();
3537 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3538 "Unsupported vector type for unpckh");
3540 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3541 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3544 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
3545 // FIXME: Need a better way to get rid of this, there's no latency difference
3546 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
3547 // the former later. We should also remove the "_undef" special mask.
3548 if (NumElts == 4 && VT.getSizeInBits() == 256)
3551 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3552 // independently on 128-bit lanes.
3553 unsigned NumLanes = VT.getSizeInBits()/128;
3554 unsigned NumLaneElts = NumElts/NumLanes;
3556 for (unsigned l = 0; l != NumLanes; ++l) {
3557 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts;
3558 i != (l+1)*NumLaneElts;
3561 int BitI1 = Mask[i+1];
3563 if (!isUndefOrEqual(BitI, j))
3565 if (!isUndefOrEqual(BitI1, j))
3573 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
3574 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
3576 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, EVT VT, bool HasAVX2) {
3577 unsigned NumElts = VT.getVectorNumElements();
3579 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3580 "Unsupported vector type for unpckh");
3582 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3583 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3586 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3587 // independently on 128-bit lanes.
3588 unsigned NumLanes = VT.getSizeInBits()/128;
3589 unsigned NumLaneElts = NumElts/NumLanes;
3591 for (unsigned l = 0; l != NumLanes; ++l) {
3592 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2;
3593 i != (l+1)*NumLaneElts; i += 2, ++j) {
3595 int BitI1 = Mask[i+1];
3596 if (!isUndefOrEqual(BitI, j))
3598 if (!isUndefOrEqual(BitI1, j))
3605 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
3606 /// specifies a shuffle of elements that is suitable for input to MOVSS,
3607 /// MOVSD, and MOVD, i.e. setting the lowest element.
3608 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
3609 if (VT.getVectorElementType().getSizeInBits() < 32)
3611 if (VT.getSizeInBits() == 256)
3614 unsigned NumElts = VT.getVectorNumElements();
3616 if (!isUndefOrEqual(Mask[0], NumElts))
3619 for (unsigned i = 1; i != NumElts; ++i)
3620 if (!isUndefOrEqual(Mask[i], i))
3626 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
3627 /// as permutations between 128-bit chunks or halves. As an example: this
3629 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
3630 /// The first half comes from the second half of V1 and the second half from the
3631 /// the second half of V2.
3632 static bool isVPERM2X128Mask(ArrayRef<int> Mask, EVT VT, bool HasAVX) {
3633 if (!HasAVX || VT.getSizeInBits() != 256)
3636 // The shuffle result is divided into half A and half B. In total the two
3637 // sources have 4 halves, namely: C, D, E, F. The final values of A and
3638 // B must come from C, D, E or F.
3639 unsigned HalfSize = VT.getVectorNumElements()/2;
3640 bool MatchA = false, MatchB = false;
3642 // Check if A comes from one of C, D, E, F.
3643 for (unsigned Half = 0; Half != 4; ++Half) {
3644 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
3650 // Check if B comes from one of C, D, E, F.
3651 for (unsigned Half = 0; Half != 4; ++Half) {
3652 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
3658 return MatchA && MatchB;
3661 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
3662 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
3663 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
3664 EVT VT = SVOp->getValueType(0);
3666 unsigned HalfSize = VT.getVectorNumElements()/2;
3668 unsigned FstHalf = 0, SndHalf = 0;
3669 for (unsigned i = 0; i < HalfSize; ++i) {
3670 if (SVOp->getMaskElt(i) > 0) {
3671 FstHalf = SVOp->getMaskElt(i)/HalfSize;
3675 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
3676 if (SVOp->getMaskElt(i) > 0) {
3677 SndHalf = SVOp->getMaskElt(i)/HalfSize;
3682 return (FstHalf | (SndHalf << 4));
3685 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
3686 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
3687 /// Note that VPERMIL mask matching is different depending whether theunderlying
3688 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
3689 /// to the same elements of the low, but to the higher half of the source.
3690 /// In VPERMILPD the two lanes could be shuffled independently of each other
3691 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
3692 static bool isVPERMILPMask(ArrayRef<int> Mask, EVT VT, bool HasAVX) {
3696 unsigned NumElts = VT.getVectorNumElements();
3697 // Only match 256-bit with 32/64-bit types
3698 if (VT.getSizeInBits() != 256 || (NumElts != 4 && NumElts != 8))
3701 unsigned NumLanes = VT.getSizeInBits()/128;
3702 unsigned LaneSize = NumElts/NumLanes;
3703 for (unsigned l = 0; l != NumElts; l += LaneSize) {
3704 for (unsigned i = 0; i != LaneSize; ++i) {
3705 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
3707 if (NumElts != 8 || l == 0)
3709 // VPERMILPS handling
3712 if (!isUndefOrEqual(Mask[i+l], Mask[i]+l))
3720 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
3721 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
3722 /// element of vector 2 and the other elements to come from vector 1 in order.
3723 static bool isCommutedMOVLMask(ArrayRef<int> Mask, EVT VT,
3724 bool V2IsSplat = false, bool V2IsUndef = false) {
3725 unsigned NumOps = VT.getVectorNumElements();
3726 if (VT.getSizeInBits() == 256)
3728 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
3731 if (!isUndefOrEqual(Mask[0], 0))
3734 for (unsigned i = 1; i != NumOps; ++i)
3735 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
3736 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
3737 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
3743 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3744 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
3745 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
3746 static bool isMOVSHDUPMask(ArrayRef<int> Mask, EVT VT,
3747 const X86Subtarget *Subtarget) {
3748 if (!Subtarget->hasSSE3())
3751 unsigned NumElems = VT.getVectorNumElements();
3753 if ((VT.getSizeInBits() == 128 && NumElems != 4) ||
3754 (VT.getSizeInBits() == 256 && NumElems != 8))
3757 // "i+1" is the value the indexed mask element must have
3758 for (unsigned i = 0; i != NumElems; i += 2)
3759 if (!isUndefOrEqual(Mask[i], i+1) ||
3760 !isUndefOrEqual(Mask[i+1], i+1))
3766 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3767 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
3768 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
3769 static bool isMOVSLDUPMask(ArrayRef<int> Mask, EVT VT,
3770 const X86Subtarget *Subtarget) {
3771 if (!Subtarget->hasSSE3())
3774 unsigned NumElems = VT.getVectorNumElements();
3776 if ((VT.getSizeInBits() == 128 && NumElems != 4) ||
3777 (VT.getSizeInBits() == 256 && NumElems != 8))
3780 // "i" is the value the indexed mask element must have
3781 for (unsigned i = 0; i != NumElems; i += 2)
3782 if (!isUndefOrEqual(Mask[i], i) ||
3783 !isUndefOrEqual(Mask[i+1], i))
3789 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
3790 /// specifies a shuffle of elements that is suitable for input to 256-bit
3791 /// version of MOVDDUP.
3792 static bool isMOVDDUPYMask(ArrayRef<int> Mask, EVT VT, bool HasAVX) {
3793 unsigned NumElts = VT.getVectorNumElements();
3795 if (!HasAVX || VT.getSizeInBits() != 256 || NumElts != 4)
3798 for (unsigned i = 0; i != NumElts/2; ++i)
3799 if (!isUndefOrEqual(Mask[i], 0))
3801 for (unsigned i = NumElts/2; i != NumElts; ++i)
3802 if (!isUndefOrEqual(Mask[i], NumElts/2))
3807 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3808 /// specifies a shuffle of elements that is suitable for input to 128-bit
3809 /// version of MOVDDUP.
3810 static bool isMOVDDUPMask(ArrayRef<int> Mask, EVT VT) {
3811 if (VT.getSizeInBits() != 128)
3814 unsigned e = VT.getVectorNumElements() / 2;
3815 for (unsigned i = 0; i != e; ++i)
3816 if (!isUndefOrEqual(Mask[i], i))
3818 for (unsigned i = 0; i != e; ++i)
3819 if (!isUndefOrEqual(Mask[e+i], i))
3824 /// isVEXTRACTF128Index - Return true if the specified
3825 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
3826 /// suitable for input to VEXTRACTF128.
3827 bool X86::isVEXTRACTF128Index(SDNode *N) {
3828 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3831 // The index should be aligned on a 128-bit boundary.
3833 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
3835 unsigned VL = N->getValueType(0).getVectorNumElements();
3836 unsigned VBits = N->getValueType(0).getSizeInBits();
3837 unsigned ElSize = VBits / VL;
3838 bool Result = (Index * ElSize) % 128 == 0;
3843 /// isVINSERTF128Index - Return true if the specified INSERT_SUBVECTOR
3844 /// operand specifies a subvector insert that is suitable for input to
3846 bool X86::isVINSERTF128Index(SDNode *N) {
3847 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
3850 // The index should be aligned on a 128-bit boundary.
3852 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
3854 unsigned VL = N->getValueType(0).getVectorNumElements();
3855 unsigned VBits = N->getValueType(0).getSizeInBits();
3856 unsigned ElSize = VBits / VL;
3857 bool Result = (Index * ElSize) % 128 == 0;
3862 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
3863 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
3864 /// Handles 128-bit and 256-bit.
3865 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
3866 EVT VT = N->getValueType(0);
3868 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3869 "Unsupported vector type for PSHUF/SHUFP");
3871 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
3872 // independently on 128-bit lanes.
3873 unsigned NumElts = VT.getVectorNumElements();
3874 unsigned NumLanes = VT.getSizeInBits()/128;
3875 unsigned NumLaneElts = NumElts/NumLanes;
3877 assert((NumLaneElts == 2 || NumLaneElts == 4) &&
3878 "Only supports 2 or 4 elements per lane");
3880 unsigned Shift = (NumLaneElts == 4) ? 1 : 0;
3882 for (unsigned i = 0; i != NumElts; ++i) {
3883 int Elt = N->getMaskElt(i);
3884 if (Elt < 0) continue;
3886 unsigned ShAmt = i << Shift;
3887 if (ShAmt >= 8) ShAmt -= 8;
3888 Mask |= Elt << ShAmt;
3894 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
3895 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
3896 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
3898 // 8 nodes, but we only care about the last 4.
3899 for (unsigned i = 7; i >= 4; --i) {
3900 int Val = N->getMaskElt(i);
3909 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
3910 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
3911 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
3913 // 8 nodes, but we only care about the first 4.
3914 for (int i = 3; i >= 0; --i) {
3915 int Val = N->getMaskElt(i);
3924 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
3925 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
3926 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
3927 EVT VT = SVOp->getValueType(0);
3928 unsigned EltSize = VT.getVectorElementType().getSizeInBits() >> 3;
3930 unsigned NumElts = VT.getVectorNumElements();
3931 unsigned NumLanes = VT.getSizeInBits()/128;
3932 unsigned NumLaneElts = NumElts/NumLanes;
3936 for (i = 0; i != NumElts; ++i) {
3937 Val = SVOp->getMaskElt(i);
3941 if (Val >= (int)NumElts)
3942 Val -= NumElts - NumLaneElts;
3944 assert(Val - i > 0 && "PALIGNR imm should be positive");
3945 return (Val - i) * EltSize;
3948 /// getExtractVEXTRACTF128Immediate - Return the appropriate immediate
3949 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
3951 unsigned X86::getExtractVEXTRACTF128Immediate(SDNode *N) {
3952 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3953 llvm_unreachable("Illegal extract subvector for VEXTRACTF128");
3956 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
3958 EVT VecVT = N->getOperand(0).getValueType();
3959 EVT ElVT = VecVT.getVectorElementType();
3961 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
3962 return Index / NumElemsPerChunk;
3965 /// getInsertVINSERTF128Immediate - Return the appropriate immediate
3966 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
3968 unsigned X86::getInsertVINSERTF128Immediate(SDNode *N) {
3969 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
3970 llvm_unreachable("Illegal insert subvector for VINSERTF128");
3973 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
3975 EVT VecVT = N->getValueType(0);
3976 EVT ElVT = VecVT.getVectorElementType();
3978 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
3979 return Index / NumElemsPerChunk;
3982 /// getShuffleCLImmediate - Return the appropriate immediate to shuffle
3983 /// the specified VECTOR_SHUFFLE mask with VPERMQ and VPERMPD instructions.
3984 /// Handles 256-bit.
3985 static unsigned getShuffleCLImmediate(ShuffleVectorSDNode *N) {
3986 EVT VT = N->getValueType(0);
3988 unsigned NumElts = VT.getVectorNumElements();
3990 assert((VT.is256BitVector() && NumElts == 4) &&
3991 "Unsupported vector type for VPERMQ/VPERMPD");
3994 for (unsigned i = 0; i != NumElts; ++i) {
3995 int Elt = N->getMaskElt(i);
3998 Mask |= Elt << (i*2);
4003 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4005 bool X86::isZeroNode(SDValue Elt) {
4006 return ((isa<ConstantSDNode>(Elt) &&
4007 cast<ConstantSDNode>(Elt)->isNullValue()) ||
4008 (isa<ConstantFPSDNode>(Elt) &&
4009 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
4012 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
4013 /// their permute mask.
4014 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
4015 SelectionDAG &DAG) {
4016 EVT VT = SVOp->getValueType(0);
4017 unsigned NumElems = VT.getVectorNumElements();
4018 SmallVector<int, 8> MaskVec;
4020 for (unsigned i = 0; i != NumElems; ++i) {
4021 int idx = SVOp->getMaskElt(i);
4023 MaskVec.push_back(idx);
4024 else if (idx < (int)NumElems)
4025 MaskVec.push_back(idx + NumElems);
4027 MaskVec.push_back(idx - NumElems);
4029 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1),
4030 SVOp->getOperand(0), &MaskVec[0]);
4033 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4034 /// match movhlps. The lower half elements should come from upper half of
4035 /// V1 (and in order), and the upper half elements should come from the upper
4036 /// half of V2 (and in order).
4037 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, EVT VT) {
4038 if (VT.getSizeInBits() != 128)
4040 if (VT.getVectorNumElements() != 4)
4042 for (unsigned i = 0, e = 2; i != e; ++i)
4043 if (!isUndefOrEqual(Mask[i], i+2))
4045 for (unsigned i = 2; i != 4; ++i)
4046 if (!isUndefOrEqual(Mask[i], i+4))
4051 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4052 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4054 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
4055 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4057 N = N->getOperand(0).getNode();
4058 if (!ISD::isNON_EXTLoad(N))
4061 *LD = cast<LoadSDNode>(N);
4065 // Test whether the given value is a vector value which will be legalized
4067 static bool WillBeConstantPoolLoad(SDNode *N) {
4068 if (N->getOpcode() != ISD::BUILD_VECTOR)
4071 // Check for any non-constant elements.
4072 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4073 switch (N->getOperand(i).getNode()->getOpcode()) {
4075 case ISD::ConstantFP:
4082 // Vectors of all-zeros and all-ones are materialized with special
4083 // instructions rather than being loaded.
4084 return !ISD::isBuildVectorAllZeros(N) &&
4085 !ISD::isBuildVectorAllOnes(N);
4088 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
4089 /// match movlp{s|d}. The lower half elements should come from lower half of
4090 /// V1 (and in order), and the upper half elements should come from the upper
4091 /// half of V2 (and in order). And since V1 will become the source of the
4092 /// MOVLP, it must be either a vector load or a scalar load to vector.
4093 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
4094 ArrayRef<int> Mask, EVT VT) {
4095 if (VT.getSizeInBits() != 128)
4098 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
4100 // Is V2 is a vector load, don't do this transformation. We will try to use
4101 // load folding shufps op.
4102 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
4105 unsigned NumElems = VT.getVectorNumElements();
4107 if (NumElems != 2 && NumElems != 4)
4109 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4110 if (!isUndefOrEqual(Mask[i], i))
4112 for (unsigned i = NumElems/2; i != NumElems; ++i)
4113 if (!isUndefOrEqual(Mask[i], i+NumElems))
4118 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
4120 static bool isSplatVector(SDNode *N) {
4121 if (N->getOpcode() != ISD::BUILD_VECTOR)
4124 SDValue SplatValue = N->getOperand(0);
4125 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
4126 if (N->getOperand(i) != SplatValue)
4131 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
4132 /// to an zero vector.
4133 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
4134 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
4135 SDValue V1 = N->getOperand(0);
4136 SDValue V2 = N->getOperand(1);
4137 unsigned NumElems = N->getValueType(0).getVectorNumElements();
4138 for (unsigned i = 0; i != NumElems; ++i) {
4139 int Idx = N->getMaskElt(i);
4140 if (Idx >= (int)NumElems) {
4141 unsigned Opc = V2.getOpcode();
4142 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
4144 if (Opc != ISD::BUILD_VECTOR ||
4145 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
4147 } else if (Idx >= 0) {
4148 unsigned Opc = V1.getOpcode();
4149 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
4151 if (Opc != ISD::BUILD_VECTOR ||
4152 !X86::isZeroNode(V1.getOperand(Idx)))
4159 /// getZeroVector - Returns a vector of specified type with all zero elements.
4161 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4162 SelectionDAG &DAG, DebugLoc dl) {
4163 assert(VT.isVector() && "Expected a vector type");
4164 unsigned Size = VT.getSizeInBits();
4166 // Always build SSE zero vectors as <4 x i32> bitcasted
4167 // to their dest type. This ensures they get CSE'd.
4169 if (Size == 128) { // SSE
4170 if (Subtarget->hasSSE2()) { // SSE2
4171 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4172 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4174 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4175 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4177 } else if (Size == 256) { // AVX
4178 if (Subtarget->hasAVX2()) { // AVX2
4179 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4180 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4181 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8);
4183 // 256-bit logic and arithmetic instructions in AVX are all
4184 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4185 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4186 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4187 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops, 8);
4190 llvm_unreachable("Unexpected vector type");
4192 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4195 /// getOnesVector - Returns a vector of specified type with all bits set.
4196 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4197 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4198 /// Then bitcast to their original type, ensuring they get CSE'd.
4199 static SDValue getOnesVector(EVT VT, bool HasAVX2, SelectionDAG &DAG,
4201 assert(VT.isVector() && "Expected a vector type");
4202 unsigned Size = VT.getSizeInBits();
4204 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
4207 if (HasAVX2) { // AVX2
4208 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4209 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8);
4211 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4212 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4214 } else if (Size == 128) {
4215 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4217 llvm_unreachable("Unexpected vector type");
4219 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4222 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
4223 /// that point to V2 points to its first element.
4224 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
4225 for (unsigned i = 0; i != NumElems; ++i) {
4226 if (Mask[i] > (int)NumElems) {
4232 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4233 /// operation of specified width.
4234 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4236 unsigned NumElems = VT.getVectorNumElements();
4237 SmallVector<int, 8> Mask;
4238 Mask.push_back(NumElems);
4239 for (unsigned i = 1; i != NumElems; ++i)
4241 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4244 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4245 static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4247 unsigned NumElems = VT.getVectorNumElements();
4248 SmallVector<int, 8> Mask;
4249 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4251 Mask.push_back(i + NumElems);
4253 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4256 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4257 static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4259 unsigned NumElems = VT.getVectorNumElements();
4260 unsigned Half = NumElems/2;
4261 SmallVector<int, 8> Mask;
4262 for (unsigned i = 0; i != Half; ++i) {
4263 Mask.push_back(i + Half);
4264 Mask.push_back(i + NumElems + Half);
4266 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4269 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
4270 // a generic shuffle instruction because the target has no such instructions.
4271 // Generate shuffles which repeat i16 and i8 several times until they can be
4272 // represented by v4f32 and then be manipulated by target suported shuffles.
4273 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
4274 EVT VT = V.getValueType();
4275 int NumElems = VT.getVectorNumElements();
4276 DebugLoc dl = V.getDebugLoc();
4278 while (NumElems > 4) {
4279 if (EltNo < NumElems/2) {
4280 V = getUnpackl(DAG, dl, VT, V, V);
4282 V = getUnpackh(DAG, dl, VT, V, V);
4283 EltNo -= NumElems/2;
4290 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
4291 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
4292 EVT VT = V.getValueType();
4293 DebugLoc dl = V.getDebugLoc();
4294 unsigned Size = VT.getSizeInBits();
4297 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
4298 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
4299 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
4301 } else if (Size == 256) {
4302 // To use VPERMILPS to splat scalars, the second half of indicies must
4303 // refer to the higher part, which is a duplication of the lower one,
4304 // because VPERMILPS can only handle in-lane permutations.
4305 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
4306 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
4308 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
4309 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
4312 llvm_unreachable("Vector size not supported");
4314 return DAG.getNode(ISD::BITCAST, dl, VT, V);
4317 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
4318 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
4319 EVT SrcVT = SV->getValueType(0);
4320 SDValue V1 = SV->getOperand(0);
4321 DebugLoc dl = SV->getDebugLoc();
4323 int EltNo = SV->getSplatIndex();
4324 int NumElems = SrcVT.getVectorNumElements();
4325 unsigned Size = SrcVT.getSizeInBits();
4327 assert(((Size == 128 && NumElems > 4) || Size == 256) &&
4328 "Unknown how to promote splat for type");
4330 // Extract the 128-bit part containing the splat element and update
4331 // the splat element index when it refers to the higher register.
4333 unsigned Idx = (EltNo >= NumElems/2) ? NumElems/2 : 0;
4334 V1 = Extract128BitVector(V1, Idx, DAG, dl);
4336 EltNo -= NumElems/2;
4339 // All i16 and i8 vector types can't be used directly by a generic shuffle
4340 // instruction because the target has no such instruction. Generate shuffles
4341 // which repeat i16 and i8 several times until they fit in i32, and then can
4342 // be manipulated by target suported shuffles.
4343 EVT EltVT = SrcVT.getVectorElementType();
4344 if (EltVT == MVT::i8 || EltVT == MVT::i16)
4345 V1 = PromoteSplati8i16(V1, DAG, EltNo);
4347 // Recreate the 256-bit vector and place the same 128-bit vector
4348 // into the low and high part. This is necessary because we want
4349 // to use VPERM* to shuffle the vectors
4351 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
4354 return getLegalSplat(DAG, V1, EltNo);
4357 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
4358 /// vector of zero or undef vector. This produces a shuffle where the low
4359 /// element of V2 is swizzled into the zero/undef vector, landing at element
4360 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4361 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4363 const X86Subtarget *Subtarget,
4364 SelectionDAG &DAG) {
4365 EVT VT = V2.getValueType();
4367 ? getZeroVector(VT, Subtarget, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT);
4368 unsigned NumElems = VT.getVectorNumElements();
4369 SmallVector<int, 16> MaskVec;
4370 for (unsigned i = 0; i != NumElems; ++i)
4371 // If this is the insertion idx, put the low elt of V2 here.
4372 MaskVec.push_back(i == Idx ? NumElems : i);
4373 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]);
4376 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
4377 /// target specific opcode. Returns true if the Mask could be calculated.
4378 /// Sets IsUnary to true if only uses one source.
4379 static bool getTargetShuffleMask(SDNode *N, EVT VT,
4380 SmallVectorImpl<int> &Mask, bool &IsUnary) {
4381 unsigned NumElems = VT.getVectorNumElements();
4385 switch(N->getOpcode()) {
4387 ImmN = N->getOperand(N->getNumOperands()-1);
4388 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4390 case X86ISD::UNPCKH:
4391 DecodeUNPCKHMask(VT, Mask);
4393 case X86ISD::UNPCKL:
4394 DecodeUNPCKLMask(VT, Mask);
4396 case X86ISD::MOVHLPS:
4397 DecodeMOVHLPSMask(NumElems, Mask);
4399 case X86ISD::MOVLHPS:
4400 DecodeMOVLHPSMask(NumElems, Mask);
4402 case X86ISD::PSHUFD:
4403 case X86ISD::VPERMILP:
4404 ImmN = N->getOperand(N->getNumOperands()-1);
4405 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4408 case X86ISD::PSHUFHW:
4409 ImmN = N->getOperand(N->getNumOperands()-1);
4410 DecodePSHUFHWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4413 case X86ISD::PSHUFLW:
4414 ImmN = N->getOperand(N->getNumOperands()-1);
4415 DecodePSHUFLWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4419 case X86ISD::MOVSD: {
4420 // The index 0 always comes from the first element of the second source,
4421 // this is why MOVSS and MOVSD are used in the first place. The other
4422 // elements come from the other positions of the first source vector
4423 Mask.push_back(NumElems);
4424 for (unsigned i = 1; i != NumElems; ++i) {
4429 case X86ISD::VPERM2X128:
4430 ImmN = N->getOperand(N->getNumOperands()-1);
4431 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4432 if (Mask.empty()) return false;
4434 case X86ISD::MOVDDUP:
4435 case X86ISD::MOVLHPD:
4436 case X86ISD::MOVLPD:
4437 case X86ISD::MOVLPS:
4438 case X86ISD::MOVSHDUP:
4439 case X86ISD::MOVSLDUP:
4440 case X86ISD::PALIGN:
4441 // Not yet implemented
4443 default: llvm_unreachable("unknown target shuffle node");
4449 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
4450 /// element of the result of the vector shuffle.
4451 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
4454 return SDValue(); // Limit search depth.
4456 SDValue V = SDValue(N, 0);
4457 EVT VT = V.getValueType();
4458 unsigned Opcode = V.getOpcode();
4460 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4461 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4462 int Elt = SV->getMaskElt(Index);
4465 return DAG.getUNDEF(VT.getVectorElementType());
4467 unsigned NumElems = VT.getVectorNumElements();
4468 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
4469 : SV->getOperand(1);
4470 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
4473 // Recurse into target specific vector shuffles to find scalars.
4474 if (isTargetShuffle(Opcode)) {
4475 unsigned NumElems = VT.getVectorNumElements();
4476 SmallVector<int, 16> ShuffleMask;
4480 if (!getTargetShuffleMask(N, VT, ShuffleMask, IsUnary))
4483 int Elt = ShuffleMask[Index];
4485 return DAG.getUNDEF(VT.getVectorElementType());
4487 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
4489 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
4493 // Actual nodes that may contain scalar elements
4494 if (Opcode == ISD::BITCAST) {
4495 V = V.getOperand(0);
4496 EVT SrcVT = V.getValueType();
4497 unsigned NumElems = VT.getVectorNumElements();
4499 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
4503 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
4504 return (Index == 0) ? V.getOperand(0)
4505 : DAG.getUNDEF(VT.getVectorElementType());
4507 if (V.getOpcode() == ISD::BUILD_VECTOR)
4508 return V.getOperand(Index);
4513 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
4514 /// shuffle operation which come from a consecutively from a zero. The
4515 /// search can start in two different directions, from left or right.
4517 unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp, unsigned NumElems,
4518 bool ZerosFromLeft, SelectionDAG &DAG) {
4520 for (i = 0; i != NumElems; ++i) {
4521 unsigned Index = ZerosFromLeft ? i : NumElems-i-1;
4522 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
4523 if (!(Elt.getNode() &&
4524 (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt))))
4531 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
4532 /// correspond consecutively to elements from one of the vector operands,
4533 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
4535 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
4536 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
4537 unsigned NumElems, unsigned &OpNum) {
4538 bool SeenV1 = false;
4539 bool SeenV2 = false;
4541 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
4542 int Idx = SVOp->getMaskElt(i);
4543 // Ignore undef indicies
4547 if (Idx < (int)NumElems)
4552 // Only accept consecutive elements from the same vector
4553 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
4557 OpNum = SeenV1 ? 0 : 1;
4561 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
4562 /// logical left shift of a vector.
4563 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4564 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4565 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4566 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4567 false /* check zeros from right */, DAG);
4573 // Considering the elements in the mask that are not consecutive zeros,
4574 // check if they consecutively come from only one of the source vectors.
4576 // V1 = {X, A, B, C} 0
4578 // vector_shuffle V1, V2 <1, 2, 3, X>
4580 if (!isShuffleMaskConsecutive(SVOp,
4581 0, // Mask Start Index
4582 NumElems-NumZeros, // Mask End Index(exclusive)
4583 NumZeros, // Where to start looking in the src vector
4584 NumElems, // Number of elements in vector
4585 OpSrc)) // Which source operand ?
4590 ShVal = SVOp->getOperand(OpSrc);
4594 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
4595 /// logical left shift of a vector.
4596 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4597 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4598 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4599 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4600 true /* check zeros from left */, DAG);
4606 // Considering the elements in the mask that are not consecutive zeros,
4607 // check if they consecutively come from only one of the source vectors.
4609 // 0 { A, B, X, X } = V2
4611 // vector_shuffle V1, V2 <X, X, 4, 5>
4613 if (!isShuffleMaskConsecutive(SVOp,
4614 NumZeros, // Mask Start Index
4615 NumElems, // Mask End Index(exclusive)
4616 0, // Where to start looking in the src vector
4617 NumElems, // Number of elements in vector
4618 OpSrc)) // Which source operand ?
4623 ShVal = SVOp->getOperand(OpSrc);
4627 /// isVectorShift - Returns true if the shuffle can be implemented as a
4628 /// logical left or right shift of a vector.
4629 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4630 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4631 // Although the logic below support any bitwidth size, there are no
4632 // shift instructions which handle more than 128-bit vectors.
4633 if (SVOp->getValueType(0).getSizeInBits() > 128)
4636 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
4637 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
4643 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
4645 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
4646 unsigned NumNonZero, unsigned NumZero,
4648 const X86Subtarget* Subtarget,
4649 const TargetLowering &TLI) {
4653 DebugLoc dl = Op.getDebugLoc();
4656 for (unsigned i = 0; i < 16; ++i) {
4657 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
4658 if (ThisIsNonZero && First) {
4660 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4662 V = DAG.getUNDEF(MVT::v8i16);
4667 SDValue ThisElt(0, 0), LastElt(0, 0);
4668 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
4669 if (LastIsNonZero) {
4670 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
4671 MVT::i16, Op.getOperand(i-1));
4673 if (ThisIsNonZero) {
4674 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
4675 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
4676 ThisElt, DAG.getConstant(8, MVT::i8));
4678 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
4682 if (ThisElt.getNode())
4683 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
4684 DAG.getIntPtrConstant(i/2));
4688 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
4691 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
4693 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
4694 unsigned NumNonZero, unsigned NumZero,
4696 const X86Subtarget* Subtarget,
4697 const TargetLowering &TLI) {
4701 DebugLoc dl = Op.getDebugLoc();
4704 for (unsigned i = 0; i < 8; ++i) {
4705 bool isNonZero = (NonZeros & (1 << i)) != 0;
4709 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4711 V = DAG.getUNDEF(MVT::v8i16);
4714 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4715 MVT::v8i16, V, Op.getOperand(i),
4716 DAG.getIntPtrConstant(i));
4723 /// getVShift - Return a vector logical shift node.
4725 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
4726 unsigned NumBits, SelectionDAG &DAG,
4727 const TargetLowering &TLI, DebugLoc dl) {
4728 assert(VT.getSizeInBits() == 128 && "Unknown type for VShift");
4729 EVT ShVT = MVT::v2i64;
4730 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
4731 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
4732 return DAG.getNode(ISD::BITCAST, dl, VT,
4733 DAG.getNode(Opc, dl, ShVT, SrcOp,
4734 DAG.getConstant(NumBits,
4735 TLI.getShiftAmountTy(SrcOp.getValueType()))));
4739 X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
4740 SelectionDAG &DAG) const {
4742 // Check if the scalar load can be widened into a vector load. And if
4743 // the address is "base + cst" see if the cst can be "absorbed" into
4744 // the shuffle mask.
4745 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
4746 SDValue Ptr = LD->getBasePtr();
4747 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
4749 EVT PVT = LD->getValueType(0);
4750 if (PVT != MVT::i32 && PVT != MVT::f32)
4755 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
4756 FI = FINode->getIndex();
4758 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
4759 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
4760 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
4761 Offset = Ptr.getConstantOperandVal(1);
4762 Ptr = Ptr.getOperand(0);
4767 // FIXME: 256-bit vector instructions don't require a strict alignment,
4768 // improve this code to support it better.
4769 unsigned RequiredAlign = VT.getSizeInBits()/8;
4770 SDValue Chain = LD->getChain();
4771 // Make sure the stack object alignment is at least 16 or 32.
4772 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4773 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
4774 if (MFI->isFixedObjectIndex(FI)) {
4775 // Can't change the alignment. FIXME: It's possible to compute
4776 // the exact stack offset and reference FI + adjust offset instead.
4777 // If someone *really* cares about this. That's the way to implement it.
4780 MFI->setObjectAlignment(FI, RequiredAlign);
4784 // (Offset % 16 or 32) must be multiple of 4. Then address is then
4785 // Ptr + (Offset & ~15).
4788 if ((Offset % RequiredAlign) & 3)
4790 int64_t StartOffset = Offset & ~(RequiredAlign-1);
4792 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(),
4793 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
4795 int EltNo = (Offset - StartOffset) >> 2;
4796 unsigned NumElems = VT.getVectorNumElements();
4798 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
4799 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
4800 LD->getPointerInfo().getWithOffset(StartOffset),
4801 false, false, false, 0);
4803 SmallVector<int, 8> Mask;
4804 for (unsigned i = 0; i != NumElems; ++i)
4805 Mask.push_back(EltNo);
4807 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
4813 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
4814 /// vector of type 'VT', see if the elements can be replaced by a single large
4815 /// load which has the same value as a build_vector whose operands are 'elts'.
4817 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
4819 /// FIXME: we'd also like to handle the case where the last elements are zero
4820 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
4821 /// There's even a handy isZeroNode for that purpose.
4822 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
4823 DebugLoc &DL, SelectionDAG &DAG) {
4824 EVT EltVT = VT.getVectorElementType();
4825 unsigned NumElems = Elts.size();
4827 LoadSDNode *LDBase = NULL;
4828 unsigned LastLoadedElt = -1U;
4830 // For each element in the initializer, see if we've found a load or an undef.
4831 // If we don't find an initial load element, or later load elements are
4832 // non-consecutive, bail out.
4833 for (unsigned i = 0; i < NumElems; ++i) {
4834 SDValue Elt = Elts[i];
4836 if (!Elt.getNode() ||
4837 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
4840 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
4842 LDBase = cast<LoadSDNode>(Elt.getNode());
4846 if (Elt.getOpcode() == ISD::UNDEF)
4849 LoadSDNode *LD = cast<LoadSDNode>(Elt);
4850 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
4855 // If we have found an entire vector of loads and undefs, then return a large
4856 // load of the entire vector width starting at the base pointer. If we found
4857 // consecutive loads for the low half, generate a vzext_load node.
4858 if (LastLoadedElt == NumElems - 1) {
4859 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
4860 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4861 LDBase->getPointerInfo(),
4862 LDBase->isVolatile(), LDBase->isNonTemporal(),
4863 LDBase->isInvariant(), 0);
4864 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4865 LDBase->getPointerInfo(),
4866 LDBase->isVolatile(), LDBase->isNonTemporal(),
4867 LDBase->isInvariant(), LDBase->getAlignment());
4869 if (NumElems == 4 && LastLoadedElt == 1 &&
4870 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
4871 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
4872 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
4874 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, 2, MVT::i64,
4875 LDBase->getPointerInfo(),
4876 LDBase->getAlignment(),
4877 false/*isVolatile*/, true/*ReadMem*/,
4879 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
4884 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
4885 /// to generate a splat value for the following cases:
4886 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
4887 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
4888 /// a scalar load, or a constant.
4889 /// The VBROADCAST node is returned when a pattern is found,
4890 /// or SDValue() otherwise.
4892 X86TargetLowering::LowerVectorBroadcast(SDValue &Op, SelectionDAG &DAG) const {
4893 if (!Subtarget->hasAVX())
4896 EVT VT = Op.getValueType();
4897 DebugLoc dl = Op.getDebugLoc();
4902 switch (Op.getOpcode()) {
4904 // Unknown pattern found.
4907 case ISD::BUILD_VECTOR: {
4908 // The BUILD_VECTOR node must be a splat.
4909 if (!isSplatVector(Op.getNode()))
4912 Ld = Op.getOperand(0);
4913 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
4914 Ld.getOpcode() == ISD::ConstantFP);
4916 // The suspected load node has several users. Make sure that all
4917 // of its users are from the BUILD_VECTOR node.
4918 // Constants may have multiple users.
4919 if (!ConstSplatVal && !Ld->hasNUsesOfValue(VT.getVectorNumElements(), 0))
4924 case ISD::VECTOR_SHUFFLE: {
4925 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
4927 // Shuffles must have a splat mask where the first element is
4929 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
4932 SDValue Sc = Op.getOperand(0);
4933 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR)
4936 Ld = Sc.getOperand(0);
4937 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
4938 Ld.getOpcode() == ISD::ConstantFP);
4940 // The scalar_to_vector node and the suspected
4941 // load node must have exactly one user.
4942 // Constants may have multiple users.
4943 if (!ConstSplatVal && (!Sc.hasOneUse() || !Ld.hasOneUse()))
4949 bool Is256 = VT.getSizeInBits() == 256;
4950 bool Is128 = VT.getSizeInBits() == 128;
4952 // Handle the broadcasting a single constant scalar from the constant pool
4953 // into a vector. On Sandybridge it is still better to load a constant vector
4954 // from the constant pool and not to broadcast it from a scalar.
4955 if (ConstSplatVal && Subtarget->hasAVX2()) {
4956 EVT CVT = Ld.getValueType();
4957 assert(!CVT.isVector() && "Must not broadcast a vector type");
4958 unsigned ScalarSize = CVT.getSizeInBits();
4960 if ((Is256 && (ScalarSize == 32 || ScalarSize == 64)) ||
4961 (Is128 && (ScalarSize == 32))) {
4963 const Constant *C = 0;
4964 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
4965 C = CI->getConstantIntValue();
4966 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
4967 C = CF->getConstantFPValue();
4969 assert(C && "Invalid constant type");
4971 SDValue CP = DAG.getConstantPool(C, getPointerTy());
4972 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
4973 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
4974 MachinePointerInfo::getConstantPool(),
4975 false, false, false, Alignment);
4977 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
4981 // The scalar source must be a normal load.
4982 if (!ISD::isNormalLoad(Ld.getNode()))
4985 // Reject loads that have uses of the chain result
4986 if (Ld->hasAnyUseOfValue(1))
4989 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
4991 // VBroadcast to YMM
4992 if (Is256 && (ScalarSize == 32 || ScalarSize == 64))
4993 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
4995 // VBroadcast to XMM
4996 if (Is128 && (ScalarSize == 32))
4997 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
4999 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5000 // double since there is vbroadcastsd xmm
5001 if (Subtarget->hasAVX2() && Ld.getValueType().isInteger()) {
5002 // VBroadcast to YMM
5003 if (Is256 && (ScalarSize == 8 || ScalarSize == 16))
5004 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5006 // VBroadcast to XMM
5007 if (Is128 && (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64))
5008 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5011 // Unsupported broadcast.
5016 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
5017 DebugLoc dl = Op.getDebugLoc();
5019 EVT VT = Op.getValueType();
5020 EVT ExtVT = VT.getVectorElementType();
5021 unsigned NumElems = Op.getNumOperands();
5023 // Vectors containing all zeros can be matched by pxor and xorps later
5024 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5025 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
5026 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
5027 if (VT == MVT::v4i32 || VT == MVT::v8i32)
5030 return getZeroVector(VT, Subtarget, DAG, dl);
5033 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
5034 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
5035 // vpcmpeqd on 256-bit vectors.
5036 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5037 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasAVX2()))
5040 return getOnesVector(VT, Subtarget->hasAVX2(), DAG, dl);
5043 SDValue Broadcast = LowerVectorBroadcast(Op, DAG);
5044 if (Broadcast.getNode())
5047 unsigned EVTBits = ExtVT.getSizeInBits();
5049 unsigned NumZero = 0;
5050 unsigned NumNonZero = 0;
5051 unsigned NonZeros = 0;
5052 bool IsAllConstants = true;
5053 SmallSet<SDValue, 8> Values;
5054 for (unsigned i = 0; i < NumElems; ++i) {
5055 SDValue Elt = Op.getOperand(i);
5056 if (Elt.getOpcode() == ISD::UNDEF)
5059 if (Elt.getOpcode() != ISD::Constant &&
5060 Elt.getOpcode() != ISD::ConstantFP)
5061 IsAllConstants = false;
5062 if (X86::isZeroNode(Elt))
5065 NonZeros |= (1 << i);
5070 // All undef vector. Return an UNDEF. All zero vectors were handled above.
5071 if (NumNonZero == 0)
5072 return DAG.getUNDEF(VT);
5074 // Special case for single non-zero, non-undef, element.
5075 if (NumNonZero == 1) {
5076 unsigned Idx = CountTrailingZeros_32(NonZeros);
5077 SDValue Item = Op.getOperand(Idx);
5079 // If this is an insertion of an i64 value on x86-32, and if the top bits of
5080 // the value are obviously zero, truncate the value to i32 and do the
5081 // insertion that way. Only do this if the value is non-constant or if the
5082 // value is a constant being inserted into element 0. It is cheaper to do
5083 // a constant pool load than it is to do a movd + shuffle.
5084 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
5085 (!IsAllConstants || Idx == 0)) {
5086 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
5088 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
5089 EVT VecVT = MVT::v4i32;
5090 unsigned VecElts = 4;
5092 // Truncate the value (which may itself be a constant) to i32, and
5093 // convert it to a vector with movd (S2V+shuffle to zero extend).
5094 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
5095 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
5096 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5098 // Now we have our 32-bit value zero extended in the low element of
5099 // a vector. If Idx != 0, swizzle it into place.
5101 SmallVector<int, 4> Mask;
5102 Mask.push_back(Idx);
5103 for (unsigned i = 1; i != VecElts; ++i)
5105 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
5108 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5112 // If we have a constant or non-constant insertion into the low element of
5113 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
5114 // the rest of the elements. This will be matched as movd/movq/movss/movsd
5115 // depending on what the source datatype is.
5118 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5120 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
5121 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
5122 if (VT.getSizeInBits() == 256) {
5123 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
5124 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
5125 Item, DAG.getIntPtrConstant(0));
5127 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!");
5128 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5129 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
5130 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5133 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
5134 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
5135 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5136 if (VT.getSizeInBits() == 256) {
5137 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
5138 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
5140 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!");
5141 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5143 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5147 // Is it a vector logical left shift?
5148 if (NumElems == 2 && Idx == 1 &&
5149 X86::isZeroNode(Op.getOperand(0)) &&
5150 !X86::isZeroNode(Op.getOperand(1))) {
5151 unsigned NumBits = VT.getSizeInBits();
5152 return getVShift(true, VT,
5153 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5154 VT, Op.getOperand(1)),
5155 NumBits/2, DAG, *this, dl);
5158 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
5161 // Otherwise, if this is a vector with i32 or f32 elements, and the element
5162 // is a non-constant being inserted into an element other than the low one,
5163 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
5164 // movd/movss) to move this into the low element, then shuffle it into
5166 if (EVTBits == 32) {
5167 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5169 // Turn it into a shuffle of zero and zero-extended scalar to vector.
5170 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
5171 SmallVector<int, 8> MaskVec;
5172 for (unsigned i = 0; i < NumElems; i++)
5173 MaskVec.push_back(i == Idx ? 0 : 1);
5174 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
5178 // Splat is obviously ok. Let legalizer expand it to a shuffle.
5179 if (Values.size() == 1) {
5180 if (EVTBits == 32) {
5181 // Instead of a shuffle like this:
5182 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
5183 // Check if it's possible to issue this instead.
5184 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
5185 unsigned Idx = CountTrailingZeros_32(NonZeros);
5186 SDValue Item = Op.getOperand(Idx);
5187 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
5188 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
5193 // A vector full of immediates; various special cases are already
5194 // handled, so this is best done with a single constant-pool load.
5198 // For AVX-length vectors, build the individual 128-bit pieces and use
5199 // shuffles to put them in place.
5200 if (VT.getSizeInBits() == 256) {
5201 SmallVector<SDValue, 32> V;
5202 for (unsigned i = 0; i != NumElems; ++i)
5203 V.push_back(Op.getOperand(i));
5205 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
5207 // Build both the lower and upper subvector.
5208 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2);
5209 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2],
5212 // Recreate the wider vector with the lower and upper part.
5213 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
5216 // Let legalizer expand 2-wide build_vectors.
5217 if (EVTBits == 64) {
5218 if (NumNonZero == 1) {
5219 // One half is zero or undef.
5220 unsigned Idx = CountTrailingZeros_32(NonZeros);
5221 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
5222 Op.getOperand(Idx));
5223 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
5228 // If element VT is < 32 bits, convert it to inserts into a zero vector.
5229 if (EVTBits == 8 && NumElems == 16) {
5230 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
5232 if (V.getNode()) return V;
5235 if (EVTBits == 16 && NumElems == 8) {
5236 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
5238 if (V.getNode()) return V;
5241 // If element VT is == 32 bits, turn it into a number of shuffles.
5242 SmallVector<SDValue, 8> V(NumElems);
5243 if (NumElems == 4 && NumZero > 0) {
5244 for (unsigned i = 0; i < 4; ++i) {
5245 bool isZero = !(NonZeros & (1 << i));
5247 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
5249 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5252 for (unsigned i = 0; i < 2; ++i) {
5253 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
5256 V[i] = V[i*2]; // Must be a zero vector.
5259 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
5262 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
5265 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
5270 bool Reverse1 = (NonZeros & 0x3) == 2;
5271 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
5275 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
5276 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
5278 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
5281 if (Values.size() > 1 && VT.getSizeInBits() == 128) {
5282 // Check for a build vector of consecutive loads.
5283 for (unsigned i = 0; i < NumElems; ++i)
5284 V[i] = Op.getOperand(i);
5286 // Check for elements which are consecutive loads.
5287 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG);
5291 // For SSE 4.1, use insertps to put the high elements into the low element.
5292 if (getSubtarget()->hasSSE41()) {
5294 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
5295 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
5297 Result = DAG.getUNDEF(VT);
5299 for (unsigned i = 1; i < NumElems; ++i) {
5300 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
5301 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
5302 Op.getOperand(i), DAG.getIntPtrConstant(i));
5307 // Otherwise, expand into a number of unpckl*, start by extending each of
5308 // our (non-undef) elements to the full vector width with the element in the
5309 // bottom slot of the vector (which generates no code for SSE).
5310 for (unsigned i = 0; i < NumElems; ++i) {
5311 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
5312 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5314 V[i] = DAG.getUNDEF(VT);
5317 // Next, we iteratively mix elements, e.g. for v4f32:
5318 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
5319 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
5320 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
5321 unsigned EltStride = NumElems >> 1;
5322 while (EltStride != 0) {
5323 for (unsigned i = 0; i < EltStride; ++i) {
5324 // If V[i+EltStride] is undef and this is the first round of mixing,
5325 // then it is safe to just drop this shuffle: V[i] is already in the
5326 // right place, the one element (since it's the first round) being
5327 // inserted as undef can be dropped. This isn't safe for successive
5328 // rounds because they will permute elements within both vectors.
5329 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
5330 EltStride == NumElems/2)
5333 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
5342 // LowerMMXCONCAT_VECTORS - We support concatenate two MMX registers and place
5343 // them in a MMX register. This is better than doing a stack convert.
5344 static SDValue LowerMMXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5345 DebugLoc dl = Op.getDebugLoc();
5346 EVT ResVT = Op.getValueType();
5348 assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 ||
5349 ResVT == MVT::v8i16 || ResVT == MVT::v16i8);
5351 SDValue InVec = DAG.getNode(ISD::BITCAST,dl, MVT::v1i64, Op.getOperand(0));
5352 SDValue VecOp = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
5353 InVec = Op.getOperand(1);
5354 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
5355 unsigned NumElts = ResVT.getVectorNumElements();
5356 VecOp = DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp);
5357 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp,
5358 InVec.getOperand(0), DAG.getIntPtrConstant(NumElts/2+1));
5360 InVec = DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, InVec);
5361 SDValue VecOp2 = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
5362 Mask[0] = 0; Mask[1] = 2;
5363 VecOp = DAG.getVectorShuffle(MVT::v2i64, dl, VecOp, VecOp2, Mask);
5365 return DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp);
5368 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
5369 // to create 256-bit vectors from two other 128-bit ones.
5370 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5371 DebugLoc dl = Op.getDebugLoc();
5372 EVT ResVT = Op.getValueType();
5374 assert(ResVT.getSizeInBits() == 256 && "Value type must be 256-bit wide");
5376 SDValue V1 = Op.getOperand(0);
5377 SDValue V2 = Op.getOperand(1);
5378 unsigned NumElems = ResVT.getVectorNumElements();
5380 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
5384 X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const {
5385 EVT ResVT = Op.getValueType();
5387 assert(Op.getNumOperands() == 2);
5388 assert((ResVT.getSizeInBits() == 128 || ResVT.getSizeInBits() == 256) &&
5389 "Unsupported CONCAT_VECTORS for value type");
5391 // We support concatenate two MMX registers and place them in a MMX register.
5392 // This is better than doing a stack convert.
5393 if (ResVT.is128BitVector())
5394 return LowerMMXCONCAT_VECTORS(Op, DAG);
5396 // 256-bit AVX can use the vinsertf128 instruction to create 256-bit vectors
5397 // from two other 128-bit ones.
5398 return LowerAVXCONCAT_VECTORS(Op, DAG);
5401 // Try to lower a shuffle node into a simple blend instruction.
5402 static SDValue LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
5403 const X86Subtarget *Subtarget,
5404 SelectionDAG &DAG) {
5405 SDValue V1 = SVOp->getOperand(0);
5406 SDValue V2 = SVOp->getOperand(1);
5407 DebugLoc dl = SVOp->getDebugLoc();
5408 MVT VT = SVOp->getValueType(0).getSimpleVT();
5409 unsigned NumElems = VT.getVectorNumElements();
5411 if (!Subtarget->hasSSE41())
5417 switch (VT.SimpleTy) {
5418 default: return SDValue();
5420 ISDNo = X86ISD::BLENDPW;
5425 ISDNo = X86ISD::BLENDPS;
5430 ISDNo = X86ISD::BLENDPD;
5435 if (!Subtarget->hasAVX())
5437 ISDNo = X86ISD::BLENDPS;
5442 if (!Subtarget->hasAVX())
5444 ISDNo = X86ISD::BLENDPD;
5448 assert(ISDNo && "Invalid Op Number");
5450 unsigned MaskVals = 0;
5452 for (unsigned i = 0; i != NumElems; ++i) {
5453 int EltIdx = SVOp->getMaskElt(i);
5454 if (EltIdx == (int)i || EltIdx < 0)
5456 else if (EltIdx == (int)(i + NumElems))
5457 continue; // Bit is set to zero;
5462 V1 = DAG.getNode(ISD::BITCAST, dl, OpTy, V1);
5463 V2 = DAG.getNode(ISD::BITCAST, dl, OpTy, V2);
5464 SDValue Ret = DAG.getNode(ISDNo, dl, OpTy, V1, V2,
5465 DAG.getConstant(MaskVals, MVT::i32));
5466 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
5469 // v8i16 shuffles - Prefer shuffles in the following order:
5470 // 1. [all] pshuflw, pshufhw, optional move
5471 // 2. [ssse3] 1 x pshufb
5472 // 3. [ssse3] 2 x pshufb + 1 x por
5473 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
5475 X86TargetLowering::LowerVECTOR_SHUFFLEv8i16(SDValue Op,
5476 SelectionDAG &DAG) const {
5477 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5478 SDValue V1 = SVOp->getOperand(0);
5479 SDValue V2 = SVOp->getOperand(1);
5480 DebugLoc dl = SVOp->getDebugLoc();
5481 SmallVector<int, 8> MaskVals;
5483 // Determine if more than 1 of the words in each of the low and high quadwords
5484 // of the result come from the same quadword of one of the two inputs. Undef
5485 // mask values count as coming from any quadword, for better codegen.
5486 unsigned LoQuad[] = { 0, 0, 0, 0 };
5487 unsigned HiQuad[] = { 0, 0, 0, 0 };
5488 std::bitset<4> InputQuads;
5489 for (unsigned i = 0; i < 8; ++i) {
5490 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
5491 int EltIdx = SVOp->getMaskElt(i);
5492 MaskVals.push_back(EltIdx);
5501 InputQuads.set(EltIdx / 4);
5504 int BestLoQuad = -1;
5505 unsigned MaxQuad = 1;
5506 for (unsigned i = 0; i < 4; ++i) {
5507 if (LoQuad[i] > MaxQuad) {
5509 MaxQuad = LoQuad[i];
5513 int BestHiQuad = -1;
5515 for (unsigned i = 0; i < 4; ++i) {
5516 if (HiQuad[i] > MaxQuad) {
5518 MaxQuad = HiQuad[i];
5522 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
5523 // of the two input vectors, shuffle them into one input vector so only a
5524 // single pshufb instruction is necessary. If There are more than 2 input
5525 // quads, disable the next transformation since it does not help SSSE3.
5526 bool V1Used = InputQuads[0] || InputQuads[1];
5527 bool V2Used = InputQuads[2] || InputQuads[3];
5528 if (Subtarget->hasSSSE3()) {
5529 if (InputQuads.count() == 2 && V1Used && V2Used) {
5530 BestLoQuad = InputQuads[0] ? 0 : 1;
5531 BestHiQuad = InputQuads[2] ? 2 : 3;
5533 if (InputQuads.count() > 2) {
5539 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
5540 // the shuffle mask. If a quad is scored as -1, that means that it contains
5541 // words from all 4 input quadwords.
5543 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
5545 BestLoQuad < 0 ? 0 : BestLoQuad,
5546 BestHiQuad < 0 ? 1 : BestHiQuad
5548 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
5549 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
5550 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
5551 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
5553 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
5554 // source words for the shuffle, to aid later transformations.
5555 bool AllWordsInNewV = true;
5556 bool InOrder[2] = { true, true };
5557 for (unsigned i = 0; i != 8; ++i) {
5558 int idx = MaskVals[i];
5560 InOrder[i/4] = false;
5561 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
5563 AllWordsInNewV = false;
5567 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
5568 if (AllWordsInNewV) {
5569 for (int i = 0; i != 8; ++i) {
5570 int idx = MaskVals[i];
5573 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
5574 if ((idx != i) && idx < 4)
5576 if ((idx != i) && idx > 3)
5585 // If we've eliminated the use of V2, and the new mask is a pshuflw or
5586 // pshufhw, that's as cheap as it gets. Return the new shuffle.
5587 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
5588 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
5589 unsigned TargetMask = 0;
5590 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
5591 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
5592 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
5593 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
5594 getShufflePSHUFLWImmediate(SVOp);
5595 V1 = NewV.getOperand(0);
5596 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
5600 // If we have SSSE3, and all words of the result are from 1 input vector,
5601 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
5602 // is present, fall back to case 4.
5603 if (Subtarget->hasSSSE3()) {
5604 SmallVector<SDValue,16> pshufbMask;
5606 // If we have elements from both input vectors, set the high bit of the
5607 // shuffle mask element to zero out elements that come from V2 in the V1
5608 // mask, and elements that come from V1 in the V2 mask, so that the two
5609 // results can be OR'd together.
5610 bool TwoInputs = V1Used && V2Used;
5611 for (unsigned i = 0; i != 8; ++i) {
5612 int EltIdx = MaskVals[i] * 2;
5613 if (TwoInputs && (EltIdx >= 16)) {
5614 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5615 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5618 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
5619 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8));
5621 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1);
5622 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5623 DAG.getNode(ISD::BUILD_VECTOR, dl,
5624 MVT::v16i8, &pshufbMask[0], 16));
5626 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5628 // Calculate the shuffle mask for the second input, shuffle it, and
5629 // OR it with the first shuffled input.
5631 for (unsigned i = 0; i != 8; ++i) {
5632 int EltIdx = MaskVals[i] * 2;
5634 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5635 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5638 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
5639 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8));
5641 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2);
5642 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
5643 DAG.getNode(ISD::BUILD_VECTOR, dl,
5644 MVT::v16i8, &pshufbMask[0], 16));
5645 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5646 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5649 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
5650 // and update MaskVals with new element order.
5651 std::bitset<8> InOrder;
5652 if (BestLoQuad >= 0) {
5653 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
5654 for (int i = 0; i != 4; ++i) {
5655 int idx = MaskVals[i];
5658 } else if ((idx / 4) == BestLoQuad) {
5663 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5666 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
5667 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
5668 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
5670 getShufflePSHUFLWImmediate(SVOp), DAG);
5674 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
5675 // and update MaskVals with the new element order.
5676 if (BestHiQuad >= 0) {
5677 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
5678 for (unsigned i = 4; i != 8; ++i) {
5679 int idx = MaskVals[i];
5682 } else if ((idx / 4) == BestHiQuad) {
5683 MaskV[i] = (idx & 3) + 4;
5687 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5690 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
5691 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
5692 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
5694 getShufflePSHUFHWImmediate(SVOp), DAG);
5698 // In case BestHi & BestLo were both -1, which means each quadword has a word
5699 // from each of the four input quadwords, calculate the InOrder bitvector now
5700 // before falling through to the insert/extract cleanup.
5701 if (BestLoQuad == -1 && BestHiQuad == -1) {
5703 for (int i = 0; i != 8; ++i)
5704 if (MaskVals[i] < 0 || MaskVals[i] == i)
5708 // The other elements are put in the right place using pextrw and pinsrw.
5709 for (unsigned i = 0; i != 8; ++i) {
5712 int EltIdx = MaskVals[i];
5715 SDValue ExtOp = (EltIdx < 8)
5716 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
5717 DAG.getIntPtrConstant(EltIdx))
5718 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
5719 DAG.getIntPtrConstant(EltIdx - 8));
5720 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
5721 DAG.getIntPtrConstant(i));
5726 // v16i8 shuffles - Prefer shuffles in the following order:
5727 // 1. [ssse3] 1 x pshufb
5728 // 2. [ssse3] 2 x pshufb + 1 x por
5729 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
5731 SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
5733 const X86TargetLowering &TLI) {
5734 SDValue V1 = SVOp->getOperand(0);
5735 SDValue V2 = SVOp->getOperand(1);
5736 DebugLoc dl = SVOp->getDebugLoc();
5737 ArrayRef<int> MaskVals = SVOp->getMask();
5739 // If we have SSSE3, case 1 is generated when all result bytes come from
5740 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
5741 // present, fall back to case 3.
5742 // FIXME: kill V2Only once shuffles are canonizalized by getNode.
5745 for (unsigned i = 0; i < 16; ++i) {
5746 int EltIdx = MaskVals[i];
5755 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
5756 if (TLI.getSubtarget()->hasSSSE3()) {
5757 SmallVector<SDValue,16> pshufbMask;
5759 // If all result elements are from one input vector, then only translate
5760 // undef mask values to 0x80 (zero out result) in the pshufb mask.
5762 // Otherwise, we have elements from both input vectors, and must zero out
5763 // elements that come from V2 in the first mask, and V1 in the second mask
5764 // so that we can OR them together.
5765 bool TwoInputs = !(V1Only || V2Only);
5766 for (unsigned i = 0; i != 16; ++i) {
5767 int EltIdx = MaskVals[i];
5768 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) {
5769 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5772 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
5774 // If all the elements are from V2, assign it to V1 and return after
5775 // building the first pshufb.
5778 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5779 DAG.getNode(ISD::BUILD_VECTOR, dl,
5780 MVT::v16i8, &pshufbMask[0], 16));
5784 // Calculate the shuffle mask for the second input, shuffle it, and
5785 // OR it with the first shuffled input.
5787 for (unsigned i = 0; i != 16; ++i) {
5788 int EltIdx = MaskVals[i];
5790 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5793 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
5795 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
5796 DAG.getNode(ISD::BUILD_VECTOR, dl,
5797 MVT::v16i8, &pshufbMask[0], 16));
5798 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5801 // No SSSE3 - Calculate in place words and then fix all out of place words
5802 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
5803 // the 16 different words that comprise the two doublequadword input vectors.
5804 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5805 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
5806 SDValue NewV = V2Only ? V2 : V1;
5807 for (int i = 0; i != 8; ++i) {
5808 int Elt0 = MaskVals[i*2];
5809 int Elt1 = MaskVals[i*2+1];
5811 // This word of the result is all undef, skip it.
5812 if (Elt0 < 0 && Elt1 < 0)
5815 // This word of the result is already in the correct place, skip it.
5816 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1))
5818 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17))
5821 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
5822 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
5825 // If Elt0 and Elt1 are defined, are consecutive, and can be load
5826 // using a single extract together, load it and store it.
5827 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
5828 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
5829 DAG.getIntPtrConstant(Elt1 / 2));
5830 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
5831 DAG.getIntPtrConstant(i));
5835 // If Elt1 is defined, extract it from the appropriate source. If the
5836 // source byte is not also odd, shift the extracted word left 8 bits
5837 // otherwise clear the bottom 8 bits if we need to do an or.
5839 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
5840 DAG.getIntPtrConstant(Elt1 / 2));
5841 if ((Elt1 & 1) == 0)
5842 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
5844 TLI.getShiftAmountTy(InsElt.getValueType())));
5846 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
5847 DAG.getConstant(0xFF00, MVT::i16));
5849 // If Elt0 is defined, extract it from the appropriate source. If the
5850 // source byte is not also even, shift the extracted word right 8 bits. If
5851 // Elt1 was also defined, OR the extracted values together before
5852 // inserting them in the result.
5854 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
5855 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
5856 if ((Elt0 & 1) != 0)
5857 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
5859 TLI.getShiftAmountTy(InsElt0.getValueType())));
5861 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
5862 DAG.getConstant(0x00FF, MVT::i16));
5863 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
5866 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
5867 DAG.getIntPtrConstant(i));
5869 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
5872 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
5873 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
5874 /// done when every pair / quad of shuffle mask elements point to elements in
5875 /// the right sequence. e.g.
5876 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
5878 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
5879 SelectionDAG &DAG, DebugLoc dl) {
5880 EVT VT = SVOp->getValueType(0);
5881 SDValue V1 = SVOp->getOperand(0);
5882 SDValue V2 = SVOp->getOperand(1);
5883 unsigned NumElems = VT.getVectorNumElements();
5884 unsigned NewWidth = (NumElems == 4) ? 2 : 4;
5886 switch (VT.getSimpleVT().SimpleTy) {
5887 default: llvm_unreachable("Unexpected!");
5888 case MVT::v4f32: NewVT = MVT::v2f64; break;
5889 case MVT::v4i32: NewVT = MVT::v2i64; break;
5890 case MVT::v8i16: NewVT = MVT::v4i32; break;
5891 case MVT::v16i8: NewVT = MVT::v4i32; break;
5894 int Scale = NumElems / NewWidth;
5895 SmallVector<int, 8> MaskVec;
5896 for (unsigned i = 0; i < NumElems; i += Scale) {
5898 for (int j = 0; j < Scale; ++j) {
5899 int EltIdx = SVOp->getMaskElt(i+j);
5903 StartIdx = EltIdx - (EltIdx % Scale);
5904 if (EltIdx != StartIdx + j)
5908 MaskVec.push_back(-1);
5910 MaskVec.push_back(StartIdx / Scale);
5913 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
5914 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
5915 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
5918 /// getVZextMovL - Return a zero-extending vector move low node.
5920 static SDValue getVZextMovL(EVT VT, EVT OpVT,
5921 SDValue SrcOp, SelectionDAG &DAG,
5922 const X86Subtarget *Subtarget, DebugLoc dl) {
5923 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
5924 LoadSDNode *LD = NULL;
5925 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
5926 LD = dyn_cast<LoadSDNode>(SrcOp);
5928 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
5930 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
5931 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
5932 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
5933 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
5934 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
5936 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
5937 return DAG.getNode(ISD::BITCAST, dl, VT,
5938 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
5939 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5947 return DAG.getNode(ISD::BITCAST, dl, VT,
5948 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
5949 DAG.getNode(ISD::BITCAST, dl,
5953 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
5954 /// which could not be matched by any known target speficic shuffle
5956 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
5957 EVT VT = SVOp->getValueType(0);
5959 unsigned NumElems = VT.getVectorNumElements();
5960 unsigned NumLaneElems = NumElems / 2;
5962 DebugLoc dl = SVOp->getDebugLoc();
5963 MVT EltVT = VT.getVectorElementType().getSimpleVT();
5964 EVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
5967 SmallVector<int, 16> Mask;
5968 for (unsigned l = 0; l < 2; ++l) {
5969 // Build a shuffle mask for the output, discovering on the fly which
5970 // input vectors to use as shuffle operands (recorded in InputUsed).
5971 // If building a suitable shuffle vector proves too hard, then bail
5972 // out with useBuildVector set.
5973 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
5974 unsigned LaneStart = l * NumLaneElems;
5975 for (unsigned i = 0; i != NumLaneElems; ++i) {
5976 // The mask element. This indexes into the input.
5977 int Idx = SVOp->getMaskElt(i+LaneStart);
5979 // the mask element does not index into any input vector.
5984 // The input vector this mask element indexes into.
5985 int Input = Idx / NumLaneElems;
5987 // Turn the index into an offset from the start of the input vector.
5988 Idx -= Input * NumLaneElems;
5990 // Find or create a shuffle vector operand to hold this input.
5992 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
5993 if (InputUsed[OpNo] == Input)
5994 // This input vector is already an operand.
5996 if (InputUsed[OpNo] < 0) {
5997 // Create a new operand for this input vector.
5998 InputUsed[OpNo] = Input;
6003 if (OpNo >= array_lengthof(InputUsed)) {
6004 // More than two input vectors used! Give up.
6008 // Add the mask index for the new shuffle vector.
6009 Mask.push_back(Idx + OpNo * NumLaneElems);
6012 if (InputUsed[0] < 0) {
6013 // No input vectors were used! The result is undefined.
6014 Shufs[l] = DAG.getUNDEF(NVT);
6016 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
6017 (InputUsed[0] % 2) * NumLaneElems,
6019 // If only one input was used, use an undefined vector for the other.
6020 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
6021 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
6022 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
6023 // At least one input vector was used. Create a new shuffle vector.
6024 Shufs[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
6030 // Concatenate the result back
6031 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Shufs[0], Shufs[1]);
6034 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
6035 /// 4 elements, and match them with several different shuffle types.
6037 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
6038 SDValue V1 = SVOp->getOperand(0);
6039 SDValue V2 = SVOp->getOperand(1);
6040 DebugLoc dl = SVOp->getDebugLoc();
6041 EVT VT = SVOp->getValueType(0);
6043 assert(VT.getSizeInBits() == 128 && "Unsupported vector size");
6045 std::pair<int, int> Locs[4];
6046 int Mask1[] = { -1, -1, -1, -1 };
6047 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
6051 for (unsigned i = 0; i != 4; ++i) {
6052 int Idx = PermMask[i];
6054 Locs[i] = std::make_pair(-1, -1);
6056 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
6058 Locs[i] = std::make_pair(0, NumLo);
6062 Locs[i] = std::make_pair(1, NumHi);
6064 Mask1[2+NumHi] = Idx;
6070 if (NumLo <= 2 && NumHi <= 2) {
6071 // If no more than two elements come from either vector. This can be
6072 // implemented with two shuffles. First shuffle gather the elements.
6073 // The second shuffle, which takes the first shuffle as both of its
6074 // vector operands, put the elements into the right order.
6075 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6077 int Mask2[] = { -1, -1, -1, -1 };
6079 for (unsigned i = 0; i != 4; ++i)
6080 if (Locs[i].first != -1) {
6081 unsigned Idx = (i < 2) ? 0 : 4;
6082 Idx += Locs[i].first * 2 + Locs[i].second;
6086 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
6089 if (NumLo == 3 || NumHi == 3) {
6090 // Otherwise, we must have three elements from one vector, call it X, and
6091 // one element from the other, call it Y. First, use a shufps to build an
6092 // intermediate vector with the one element from Y and the element from X
6093 // that will be in the same half in the final destination (the indexes don't
6094 // matter). Then, use a shufps to build the final vector, taking the half
6095 // containing the element from Y from the intermediate, and the other half
6098 // Normalize it so the 3 elements come from V1.
6099 CommuteVectorShuffleMask(PermMask, 4);
6103 // Find the element from V2.
6105 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
6106 int Val = PermMask[HiIndex];
6113 Mask1[0] = PermMask[HiIndex];
6115 Mask1[2] = PermMask[HiIndex^1];
6117 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6120 Mask1[0] = PermMask[0];
6121 Mask1[1] = PermMask[1];
6122 Mask1[2] = HiIndex & 1 ? 6 : 4;
6123 Mask1[3] = HiIndex & 1 ? 4 : 6;
6124 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6127 Mask1[0] = HiIndex & 1 ? 2 : 0;
6128 Mask1[1] = HiIndex & 1 ? 0 : 2;
6129 Mask1[2] = PermMask[2];
6130 Mask1[3] = PermMask[3];
6135 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
6138 // Break it into (shuffle shuffle_hi, shuffle_lo).
6139 int LoMask[] = { -1, -1, -1, -1 };
6140 int HiMask[] = { -1, -1, -1, -1 };
6142 int *MaskPtr = LoMask;
6143 unsigned MaskIdx = 0;
6146 for (unsigned i = 0; i != 4; ++i) {
6153 int Idx = PermMask[i];
6155 Locs[i] = std::make_pair(-1, -1);
6156 } else if (Idx < 4) {
6157 Locs[i] = std::make_pair(MaskIdx, LoIdx);
6158 MaskPtr[LoIdx] = Idx;
6161 Locs[i] = std::make_pair(MaskIdx, HiIdx);
6162 MaskPtr[HiIdx] = Idx;
6167 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
6168 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
6169 int MaskOps[] = { -1, -1, -1, -1 };
6170 for (unsigned i = 0; i != 4; ++i)
6171 if (Locs[i].first != -1)
6172 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
6173 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
6176 static bool MayFoldVectorLoad(SDValue V) {
6177 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6178 V = V.getOperand(0);
6179 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6180 V = V.getOperand(0);
6181 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
6182 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
6183 // BUILD_VECTOR (load), undef
6184 V = V.getOperand(0);
6190 // FIXME: the version above should always be used. Since there's
6191 // a bug where several vector shuffles can't be folded because the
6192 // DAG is not updated during lowering and a node claims to have two
6193 // uses while it only has one, use this version, and let isel match
6194 // another instruction if the load really happens to have more than
6195 // one use. Remove this version after this bug get fixed.
6196 // rdar://8434668, PR8156
6197 static bool RelaxedMayFoldVectorLoad(SDValue V) {
6198 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6199 V = V.getOperand(0);
6200 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6201 V = V.getOperand(0);
6202 if (ISD::isNormalLoad(V.getNode()))
6208 SDValue getMOVDDup(SDValue &Op, DebugLoc &dl, SDValue V1, SelectionDAG &DAG) {
6209 EVT VT = Op.getValueType();
6211 // Canonizalize to v2f64.
6212 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
6213 return DAG.getNode(ISD::BITCAST, dl, VT,
6214 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
6219 SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG,
6221 SDValue V1 = Op.getOperand(0);
6222 SDValue V2 = Op.getOperand(1);
6223 EVT VT = Op.getValueType();
6225 assert(VT != MVT::v2i64 && "unsupported shuffle type");
6227 if (HasSSE2 && VT == MVT::v2f64)
6228 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
6230 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
6231 return DAG.getNode(ISD::BITCAST, dl, VT,
6232 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
6233 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
6234 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
6238 SDValue getMOVHighToLow(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG) {
6239 SDValue V1 = Op.getOperand(0);
6240 SDValue V2 = Op.getOperand(1);
6241 EVT VT = Op.getValueType();
6243 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
6244 "unsupported shuffle type");
6246 if (V2.getOpcode() == ISD::UNDEF)
6250 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
6254 SDValue getMOVLP(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
6255 SDValue V1 = Op.getOperand(0);
6256 SDValue V2 = Op.getOperand(1);
6257 EVT VT = Op.getValueType();
6258 unsigned NumElems = VT.getVectorNumElements();
6260 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
6261 // operand of these instructions is only memory, so check if there's a
6262 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
6264 bool CanFoldLoad = false;
6266 // Trivial case, when V2 comes from a load.
6267 if (MayFoldVectorLoad(V2))
6270 // When V1 is a load, it can be folded later into a store in isel, example:
6271 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
6273 // (MOVLPSmr addr:$src1, VR128:$src2)
6274 // So, recognize this potential and also use MOVLPS or MOVLPD
6275 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
6278 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6280 if (HasSSE2 && NumElems == 2)
6281 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
6284 // If we don't care about the second element, procede to use movss.
6285 if (SVOp->getMaskElt(1) != -1)
6286 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
6289 // movl and movlp will both match v2i64, but v2i64 is never matched by
6290 // movl earlier because we make it strict to avoid messing with the movlp load
6291 // folding logic (see the code above getMOVLP call). Match it here then,
6292 // this is horrible, but will stay like this until we move all shuffle
6293 // matching to x86 specific nodes. Note that for the 1st condition all
6294 // types are matched with movsd.
6296 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
6297 // as to remove this logic from here, as much as possible
6298 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
6299 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6300 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6303 assert(VT != MVT::v4i32 && "unsupported shuffle type");
6305 // Invert the operand order and use SHUFPS to match it.
6306 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
6307 getShuffleSHUFImmediate(SVOp), DAG);
6311 X86TargetLowering::NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG) const {
6312 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6313 EVT VT = Op.getValueType();
6314 DebugLoc dl = Op.getDebugLoc();
6315 SDValue V1 = Op.getOperand(0);
6316 SDValue V2 = Op.getOperand(1);
6318 if (isZeroShuffle(SVOp))
6319 return getZeroVector(VT, Subtarget, DAG, dl);
6321 // Handle splat operations
6322 if (SVOp->isSplat()) {
6323 unsigned NumElem = VT.getVectorNumElements();
6324 int Size = VT.getSizeInBits();
6326 // Use vbroadcast whenever the splat comes from a foldable load
6327 SDValue Broadcast = LowerVectorBroadcast(Op, DAG);
6328 if (Broadcast.getNode())
6331 // Handle splats by matching through known shuffle masks
6332 if ((Size == 128 && NumElem <= 4) ||
6333 (Size == 256 && NumElem < 8))
6336 // All remaning splats are promoted to target supported vector shuffles.
6337 return PromoteSplat(SVOp, DAG);
6340 // If the shuffle can be profitably rewritten as a narrower shuffle, then
6342 if (VT == MVT::v8i16 || VT == MVT::v16i8) {
6343 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6344 if (NewOp.getNode())
6345 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
6346 } else if ((VT == MVT::v4i32 ||
6347 (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
6348 // FIXME: Figure out a cleaner way to do this.
6349 // Try to make use of movq to zero out the top part.
6350 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
6351 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6352 if (NewOp.getNode()) {
6353 EVT NewVT = NewOp.getValueType();
6354 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
6355 NewVT, true, false))
6356 return getVZextMovL(VT, NewVT, NewOp.getOperand(0),
6357 DAG, Subtarget, dl);
6359 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
6360 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6361 if (NewOp.getNode()) {
6362 EVT NewVT = NewOp.getValueType();
6363 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
6364 return getVZextMovL(VT, NewVT, NewOp.getOperand(1),
6365 DAG, Subtarget, dl);
6373 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
6374 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6375 SDValue V1 = Op.getOperand(0);
6376 SDValue V2 = Op.getOperand(1);
6377 EVT VT = Op.getValueType();
6378 DebugLoc dl = Op.getDebugLoc();
6379 unsigned NumElems = VT.getVectorNumElements();
6380 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
6381 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
6382 bool V1IsSplat = false;
6383 bool V2IsSplat = false;
6384 bool HasSSE2 = Subtarget->hasSSE2();
6385 bool HasAVX = Subtarget->hasAVX();
6386 bool HasAVX2 = Subtarget->hasAVX2();
6387 MachineFunction &MF = DAG.getMachineFunction();
6388 bool OptForSize = MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize);
6390 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
6392 if (V1IsUndef && V2IsUndef)
6393 return DAG.getUNDEF(VT);
6395 assert(!V1IsUndef && "Op 1 of shuffle should not be undef");
6397 // Vector shuffle lowering takes 3 steps:
6399 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
6400 // narrowing and commutation of operands should be handled.
6401 // 2) Matching of shuffles with known shuffle masks to x86 target specific
6403 // 3) Rewriting of unmatched masks into new generic shuffle operations,
6404 // so the shuffle can be broken into other shuffles and the legalizer can
6405 // try the lowering again.
6407 // The general idea is that no vector_shuffle operation should be left to
6408 // be matched during isel, all of them must be converted to a target specific
6411 // Normalize the input vectors. Here splats, zeroed vectors, profitable
6412 // narrowing and commutation of operands should be handled. The actual code
6413 // doesn't include all of those, work in progress...
6414 SDValue NewOp = NormalizeVectorShuffle(Op, DAG);
6415 if (NewOp.getNode())
6418 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
6420 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
6421 // unpckh_undef). Only use pshufd if speed is more important than size.
6422 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasAVX2))
6423 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6424 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasAVX2))
6425 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6427 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
6428 V2IsUndef && RelaxedMayFoldVectorLoad(V1))
6429 return getMOVDDup(Op, dl, V1, DAG);
6431 if (isMOVHLPS_v_undef_Mask(M, VT))
6432 return getMOVHighToLow(Op, dl, DAG);
6434 // Use to match splats
6435 if (HasSSE2 && isUNPCKHMask(M, VT, HasAVX2) && V2IsUndef &&
6436 (VT == MVT::v2f64 || VT == MVT::v2i64))
6437 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6439 if (isPSHUFDMask(M, VT)) {
6440 // The actual implementation will match the mask in the if above and then
6441 // during isel it can match several different instructions, not only pshufd
6442 // as its name says, sad but true, emulate the behavior for now...
6443 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
6444 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
6446 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
6448 if (HasAVX && (VT == MVT::v4f32 || VT == MVT::v2f64))
6449 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, TargetMask, DAG);
6451 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
6452 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
6454 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
6458 // Check if this can be converted into a logical shift.
6459 bool isLeft = false;
6462 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
6463 if (isShift && ShVal.hasOneUse()) {
6464 // If the shifted value has multiple uses, it may be cheaper to use
6465 // v_set0 + movlhps or movhlps, etc.
6466 EVT EltVT = VT.getVectorElementType();
6467 ShAmt *= EltVT.getSizeInBits();
6468 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6471 if (isMOVLMask(M, VT)) {
6472 if (ISD::isBuildVectorAllZeros(V1.getNode()))
6473 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
6474 if (!isMOVLPMask(M, VT)) {
6475 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
6476 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6478 if (VT == MVT::v4i32 || VT == MVT::v4f32)
6479 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6483 // FIXME: fold these into legal mask.
6484 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasAVX2))
6485 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
6487 if (isMOVHLPSMask(M, VT))
6488 return getMOVHighToLow(Op, dl, DAG);
6490 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
6491 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
6493 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
6494 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
6496 if (isMOVLPMask(M, VT))
6497 return getMOVLP(Op, dl, DAG, HasSSE2);
6499 if (ShouldXformToMOVHLPS(M, VT) ||
6500 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
6501 return CommuteVectorShuffle(SVOp, DAG);
6504 // No better options. Use a vshldq / vsrldq.
6505 EVT EltVT = VT.getVectorElementType();
6506 ShAmt *= EltVT.getSizeInBits();
6507 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6510 bool Commuted = false;
6511 // FIXME: This should also accept a bitcast of a splat? Be careful, not
6512 // 1,1,1,1 -> v8i16 though.
6513 V1IsSplat = isSplatVector(V1.getNode());
6514 V2IsSplat = isSplatVector(V2.getNode());
6516 // Canonicalize the splat or undef, if present, to be on the RHS.
6517 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
6518 CommuteVectorShuffleMask(M, NumElems);
6520 std::swap(V1IsSplat, V2IsSplat);
6524 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
6525 // Shuffling low element of v1 into undef, just return v1.
6528 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
6529 // the instruction selector will not match, so get a canonical MOVL with
6530 // swapped operands to undo the commute.
6531 return getMOVL(DAG, dl, VT, V2, V1);
6534 if (isUNPCKLMask(M, VT, HasAVX2))
6535 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
6537 if (isUNPCKHMask(M, VT, HasAVX2))
6538 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
6541 // Normalize mask so all entries that point to V2 points to its first
6542 // element then try to match unpck{h|l} again. If match, return a
6543 // new vector_shuffle with the corrected mask.p
6544 SmallVector<int, 8> NewMask(M.begin(), M.end());
6545 NormalizeMask(NewMask, NumElems);
6546 if (isUNPCKLMask(NewMask, VT, HasAVX2, true))
6547 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
6548 if (isUNPCKHMask(NewMask, VT, HasAVX2, true))
6549 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
6553 // Commute is back and try unpck* again.
6554 // FIXME: this seems wrong.
6555 CommuteVectorShuffleMask(M, NumElems);
6557 std::swap(V1IsSplat, V2IsSplat);
6560 if (isUNPCKLMask(M, VT, HasAVX2))
6561 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
6563 if (isUNPCKHMask(M, VT, HasAVX2))
6564 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
6567 // Normalize the node to match x86 shuffle ops if needed
6568 if (!V2IsUndef && (isSHUFPMask(M, VT, HasAVX, /* Commuted */ true)))
6569 return CommuteVectorShuffle(SVOp, DAG);
6571 // The checks below are all present in isShuffleMaskLegal, but they are
6572 // inlined here right now to enable us to directly emit target specific
6573 // nodes, and remove one by one until they don't return Op anymore.
6575 if (isPALIGNRMask(M, VT, Subtarget))
6576 return getTargetShuffleNode(X86ISD::PALIGN, dl, VT, V1, V2,
6577 getShufflePALIGNRImmediate(SVOp),
6580 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
6581 SVOp->getSplatIndex() == 0 && V2IsUndef) {
6582 if (VT == MVT::v2f64 || VT == MVT::v2i64)
6583 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6586 if (isPSHUFHWMask(M, VT))
6587 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
6588 getShufflePSHUFHWImmediate(SVOp),
6591 if (isPSHUFLWMask(M, VT))
6592 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
6593 getShufflePSHUFLWImmediate(SVOp),
6596 if (isSHUFPMask(M, VT, HasAVX))
6597 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
6598 getShuffleSHUFImmediate(SVOp), DAG);
6600 if (isUNPCKL_v_undef_Mask(M, VT, HasAVX2))
6601 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6602 if (isUNPCKH_v_undef_Mask(M, VT, HasAVX2))
6603 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6605 //===--------------------------------------------------------------------===//
6606 // Generate target specific nodes for 128 or 256-bit shuffles only
6607 // supported in the AVX instruction set.
6610 // Handle VMOVDDUPY permutations
6611 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasAVX))
6612 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
6614 // Handle VPERMILPS/D* permutations
6615 if (isVPERMILPMask(M, VT, HasAVX)) {
6616 if (HasAVX2 && VT == MVT::v8i32)
6617 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
6618 getShuffleSHUFImmediate(SVOp), DAG);
6619 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1,
6620 getShuffleSHUFImmediate(SVOp), DAG);
6623 // Handle VPERM2F128/VPERM2I128 permutations
6624 if (isVPERM2X128Mask(M, VT, HasAVX))
6625 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
6626 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
6628 SDValue BlendOp = LowerVECTOR_SHUFFLEtoBlend(SVOp, Subtarget, DAG);
6629 if (BlendOp.getNode())
6632 if (V2IsUndef && HasAVX2 && (VT == MVT::v8i32 || VT == MVT::v8f32)) {
6633 SmallVector<SDValue, 8> permclMask;
6634 for (unsigned i = 0; i != 8; ++i) {
6635 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MVT::i32));
6637 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32,
6639 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
6640 return DAG.getNode(X86ISD::VPERMV, dl, VT,
6641 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
6644 if (V2IsUndef && HasAVX2 && (VT == MVT::v4i64 || VT == MVT::v4f64))
6645 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1,
6646 getShuffleCLImmediate(SVOp), DAG);
6649 //===--------------------------------------------------------------------===//
6650 // Since no target specific shuffle was selected for this generic one,
6651 // lower it into other known shuffles. FIXME: this isn't true yet, but
6652 // this is the plan.
6655 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
6656 if (VT == MVT::v8i16) {
6657 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, DAG);
6658 if (NewOp.getNode())
6662 if (VT == MVT::v16i8) {
6663 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this);
6664 if (NewOp.getNode())
6668 // Handle all 128-bit wide vectors with 4 elements, and match them with
6669 // several different shuffle types.
6670 if (NumElems == 4 && VT.getSizeInBits() == 128)
6671 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
6673 // Handle general 256-bit shuffles
6674 if (VT.is256BitVector())
6675 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
6681 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
6682 SelectionDAG &DAG) const {
6683 EVT VT = Op.getValueType();
6684 DebugLoc dl = Op.getDebugLoc();
6686 if (Op.getOperand(0).getValueType().getSizeInBits() != 128)
6689 if (VT.getSizeInBits() == 8) {
6690 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
6691 Op.getOperand(0), Op.getOperand(1));
6692 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
6693 DAG.getValueType(VT));
6694 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6697 if (VT.getSizeInBits() == 16) {
6698 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6699 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
6701 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
6702 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6703 DAG.getNode(ISD::BITCAST, dl,
6707 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
6708 Op.getOperand(0), Op.getOperand(1));
6709 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
6710 DAG.getValueType(VT));
6711 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6714 if (VT == MVT::f32) {
6715 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
6716 // the result back to FR32 register. It's only worth matching if the
6717 // result has a single use which is a store or a bitcast to i32. And in
6718 // the case of a store, it's not worth it if the index is a constant 0,
6719 // because a MOVSSmr can be used instead, which is smaller and faster.
6720 if (!Op.hasOneUse())
6722 SDNode *User = *Op.getNode()->use_begin();
6723 if ((User->getOpcode() != ISD::STORE ||
6724 (isa<ConstantSDNode>(Op.getOperand(1)) &&
6725 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
6726 (User->getOpcode() != ISD::BITCAST ||
6727 User->getValueType(0) != MVT::i32))
6729 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6730 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
6733 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
6736 if (VT == MVT::i32 || VT == MVT::i64) {
6737 // ExtractPS/pextrq works with constant index.
6738 if (isa<ConstantSDNode>(Op.getOperand(1)))
6746 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
6747 SelectionDAG &DAG) const {
6748 if (!isa<ConstantSDNode>(Op.getOperand(1)))
6751 SDValue Vec = Op.getOperand(0);
6752 EVT VecVT = Vec.getValueType();
6754 // If this is a 256-bit vector result, first extract the 128-bit vector and
6755 // then extract the element from the 128-bit vector.
6756 if (VecVT.getSizeInBits() == 256) {
6757 DebugLoc dl = Op.getNode()->getDebugLoc();
6758 unsigned NumElems = VecVT.getVectorNumElements();
6759 SDValue Idx = Op.getOperand(1);
6760 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
6762 // Get the 128-bit vector.
6763 bool Upper = IdxVal >= NumElems/2;
6764 Vec = Extract128BitVector(Vec, Upper ? NumElems/2 : 0, DAG, dl);
6766 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
6767 Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : Idx);
6770 assert(Vec.getValueSizeInBits() <= 128 && "Unexpected vector length");
6772 if (Subtarget->hasSSE41()) {
6773 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
6778 EVT VT = Op.getValueType();
6779 DebugLoc dl = Op.getDebugLoc();
6780 // TODO: handle v16i8.
6781 if (VT.getSizeInBits() == 16) {
6782 SDValue Vec = Op.getOperand(0);
6783 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6785 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
6786 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6787 DAG.getNode(ISD::BITCAST, dl,
6790 // Transform it so it match pextrw which produces a 32-bit result.
6791 EVT EltVT = MVT::i32;
6792 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
6793 Op.getOperand(0), Op.getOperand(1));
6794 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
6795 DAG.getValueType(VT));
6796 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6799 if (VT.getSizeInBits() == 32) {
6800 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6804 // SHUFPS the element to the lowest double word, then movss.
6805 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
6806 EVT VVT = Op.getOperand(0).getValueType();
6807 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
6808 DAG.getUNDEF(VVT), Mask);
6809 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
6810 DAG.getIntPtrConstant(0));
6813 if (VT.getSizeInBits() == 64) {
6814 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
6815 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
6816 // to match extract_elt for f64.
6817 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6821 // UNPCKHPD the element to the lowest double word, then movsd.
6822 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
6823 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
6824 int Mask[2] = { 1, -1 };
6825 EVT VVT = Op.getOperand(0).getValueType();
6826 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
6827 DAG.getUNDEF(VVT), Mask);
6828 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
6829 DAG.getIntPtrConstant(0));
6836 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op,
6837 SelectionDAG &DAG) const {
6838 EVT VT = Op.getValueType();
6839 EVT EltVT = VT.getVectorElementType();
6840 DebugLoc dl = Op.getDebugLoc();
6842 SDValue N0 = Op.getOperand(0);
6843 SDValue N1 = Op.getOperand(1);
6844 SDValue N2 = Op.getOperand(2);
6846 if (VT.getSizeInBits() == 256)
6849 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
6850 isa<ConstantSDNode>(N2)) {
6852 if (VT == MVT::v8i16)
6853 Opc = X86ISD::PINSRW;
6854 else if (VT == MVT::v16i8)
6855 Opc = X86ISD::PINSRB;
6857 Opc = X86ISD::PINSRB;
6859 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
6861 if (N1.getValueType() != MVT::i32)
6862 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
6863 if (N2.getValueType() != MVT::i32)
6864 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
6865 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
6868 if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
6869 // Bits [7:6] of the constant are the source select. This will always be
6870 // zero here. The DAG Combiner may combine an extract_elt index into these
6871 // bits. For example (insert (extract, 3), 2) could be matched by putting
6872 // the '3' into bits [7:6] of X86ISD::INSERTPS.
6873 // Bits [5:4] of the constant are the destination select. This is the
6874 // value of the incoming immediate.
6875 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
6876 // combine either bitwise AND or insert of float 0.0 to set these bits.
6877 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
6878 // Create this as a scalar to vector..
6879 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
6880 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
6883 if ((EltVT == MVT::i32 || EltVT == MVT::i64) && isa<ConstantSDNode>(N2)) {
6884 // PINSR* works with constant index.
6891 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
6892 EVT VT = Op.getValueType();
6893 EVT EltVT = VT.getVectorElementType();
6895 DebugLoc dl = Op.getDebugLoc();
6896 SDValue N0 = Op.getOperand(0);
6897 SDValue N1 = Op.getOperand(1);
6898 SDValue N2 = Op.getOperand(2);
6900 // If this is a 256-bit vector result, first extract the 128-bit vector,
6901 // insert the element into the extracted half and then place it back.
6902 if (VT.getSizeInBits() == 256) {
6903 if (!isa<ConstantSDNode>(N2))
6906 // Get the desired 128-bit vector half.
6907 unsigned NumElems = VT.getVectorNumElements();
6908 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue();
6909 bool Upper = IdxVal >= NumElems/2;
6910 unsigned Ins128Idx = Upper ? NumElems/2 : 0;
6911 SDValue V = Extract128BitVector(N0, Ins128Idx, DAG, dl);
6913 // Insert the element into the desired half.
6914 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V,
6915 N1, Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : N2);
6917 // Insert the changed part back to the 256-bit vector
6918 return Insert128BitVector(N0, V, Ins128Idx, DAG, dl);
6921 if (Subtarget->hasSSE41())
6922 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
6924 if (EltVT == MVT::i8)
6927 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
6928 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
6929 // as its second argument.
6930 if (N1.getValueType() != MVT::i32)
6931 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
6932 if (N2.getValueType() != MVT::i32)
6933 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
6934 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
6940 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6941 LLVMContext *Context = DAG.getContext();
6942 DebugLoc dl = Op.getDebugLoc();
6943 EVT OpVT = Op.getValueType();
6945 // If this is a 256-bit vector result, first insert into a 128-bit
6946 // vector and then insert into the 256-bit vector.
6947 if (OpVT.getSizeInBits() > 128) {
6948 // Insert into a 128-bit vector.
6949 EVT VT128 = EVT::getVectorVT(*Context,
6950 OpVT.getVectorElementType(),
6951 OpVT.getVectorNumElements() / 2);
6953 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
6955 // Insert the 128-bit vector.
6956 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
6959 if (OpVT == MVT::v1i64 &&
6960 Op.getOperand(0).getValueType() == MVT::i64)
6961 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
6963 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
6964 assert(OpVT.getSizeInBits() == 128 && "Expected an SSE type!");
6965 return DAG.getNode(ISD::BITCAST, dl, OpVT,
6966 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
6969 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
6970 // a simple subregister reference or explicit instructions to grab
6971 // upper bits of a vector.
6973 X86TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const {
6974 if (Subtarget->hasAVX()) {
6975 DebugLoc dl = Op.getNode()->getDebugLoc();
6976 SDValue Vec = Op.getNode()->getOperand(0);
6977 SDValue Idx = Op.getNode()->getOperand(1);
6979 if (Op.getNode()->getValueType(0).getSizeInBits() == 128 &&
6980 Vec.getNode()->getValueType(0).getSizeInBits() == 256 &&
6981 isa<ConstantSDNode>(Idx)) {
6982 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
6983 return Extract128BitVector(Vec, IdxVal, DAG, dl);
6989 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
6990 // simple superregister reference or explicit instructions to insert
6991 // the upper bits of a vector.
6993 X86TargetLowering::LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const {
6994 if (Subtarget->hasAVX()) {
6995 DebugLoc dl = Op.getNode()->getDebugLoc();
6996 SDValue Vec = Op.getNode()->getOperand(0);
6997 SDValue SubVec = Op.getNode()->getOperand(1);
6998 SDValue Idx = Op.getNode()->getOperand(2);
7000 if (Op.getNode()->getValueType(0).getSizeInBits() == 256 &&
7001 SubVec.getNode()->getValueType(0).getSizeInBits() == 128 &&
7002 isa<ConstantSDNode>(Idx)) {
7003 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7004 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
7010 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
7011 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
7012 // one of the above mentioned nodes. It has to be wrapped because otherwise
7013 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
7014 // be used to form addressing mode. These wrapped nodes will be selected
7017 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
7018 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
7020 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7022 unsigned char OpFlag = 0;
7023 unsigned WrapperKind = X86ISD::Wrapper;
7024 CodeModel::Model M = getTargetMachine().getCodeModel();
7026 if (Subtarget->isPICStyleRIPRel() &&
7027 (M == CodeModel::Small || M == CodeModel::Kernel))
7028 WrapperKind = X86ISD::WrapperRIP;
7029 else if (Subtarget->isPICStyleGOT())
7030 OpFlag = X86II::MO_GOTOFF;
7031 else if (Subtarget->isPICStyleStubPIC())
7032 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7034 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
7036 CP->getOffset(), OpFlag);
7037 DebugLoc DL = CP->getDebugLoc();
7038 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7039 // With PIC, the address is actually $g + Offset.
7041 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7042 DAG.getNode(X86ISD::GlobalBaseReg,
7043 DebugLoc(), getPointerTy()),
7050 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
7051 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
7053 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7055 unsigned char OpFlag = 0;
7056 unsigned WrapperKind = X86ISD::Wrapper;
7057 CodeModel::Model M = getTargetMachine().getCodeModel();
7059 if (Subtarget->isPICStyleRIPRel() &&
7060 (M == CodeModel::Small || M == CodeModel::Kernel))
7061 WrapperKind = X86ISD::WrapperRIP;
7062 else if (Subtarget->isPICStyleGOT())
7063 OpFlag = X86II::MO_GOTOFF;
7064 else if (Subtarget->isPICStyleStubPIC())
7065 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7067 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
7069 DebugLoc DL = JT->getDebugLoc();
7070 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7072 // With PIC, the address is actually $g + Offset.
7074 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7075 DAG.getNode(X86ISD::GlobalBaseReg,
7076 DebugLoc(), getPointerTy()),
7083 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
7084 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
7086 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7088 unsigned char OpFlag = 0;
7089 unsigned WrapperKind = X86ISD::Wrapper;
7090 CodeModel::Model M = getTargetMachine().getCodeModel();
7092 if (Subtarget->isPICStyleRIPRel() &&
7093 (M == CodeModel::Small || M == CodeModel::Kernel)) {
7094 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
7095 OpFlag = X86II::MO_GOTPCREL;
7096 WrapperKind = X86ISD::WrapperRIP;
7097 } else if (Subtarget->isPICStyleGOT()) {
7098 OpFlag = X86II::MO_GOT;
7099 } else if (Subtarget->isPICStyleStubPIC()) {
7100 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
7101 } else if (Subtarget->isPICStyleStubNoDynamic()) {
7102 OpFlag = X86II::MO_DARWIN_NONLAZY;
7105 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
7107 DebugLoc DL = Op.getDebugLoc();
7108 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7111 // With PIC, the address is actually $g + Offset.
7112 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
7113 !Subtarget->is64Bit()) {
7114 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7115 DAG.getNode(X86ISD::GlobalBaseReg,
7116 DebugLoc(), getPointerTy()),
7120 // For symbols that require a load from a stub to get the address, emit the
7122 if (isGlobalStubReference(OpFlag))
7123 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
7124 MachinePointerInfo::getGOT(), false, false, false, 0);
7130 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
7131 // Create the TargetBlockAddressAddress node.
7132 unsigned char OpFlags =
7133 Subtarget->ClassifyBlockAddressReference();
7134 CodeModel::Model M = getTargetMachine().getCodeModel();
7135 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
7136 DebugLoc dl = Op.getDebugLoc();
7137 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(),
7138 /*isTarget=*/true, OpFlags);
7140 if (Subtarget->isPICStyleRIPRel() &&
7141 (M == CodeModel::Small || M == CodeModel::Kernel))
7142 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7144 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7146 // With PIC, the address is actually $g + Offset.
7147 if (isGlobalRelativeToPICBase(OpFlags)) {
7148 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7149 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7157 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
7159 SelectionDAG &DAG) const {
7160 // Create the TargetGlobalAddress node, folding in the constant
7161 // offset if it is legal.
7162 unsigned char OpFlags =
7163 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
7164 CodeModel::Model M = getTargetMachine().getCodeModel();
7166 if (OpFlags == X86II::MO_NO_FLAG &&
7167 X86::isOffsetSuitableForCodeModel(Offset, M)) {
7168 // A direct static reference to a global.
7169 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
7172 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
7175 if (Subtarget->isPICStyleRIPRel() &&
7176 (M == CodeModel::Small || M == CodeModel::Kernel))
7177 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7179 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7181 // With PIC, the address is actually $g + Offset.
7182 if (isGlobalRelativeToPICBase(OpFlags)) {
7183 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7184 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7188 // For globals that require a load from a stub to get the address, emit the
7190 if (isGlobalStubReference(OpFlags))
7191 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
7192 MachinePointerInfo::getGOT(), false, false, false, 0);
7194 // If there was a non-zero offset that we didn't fold, create an explicit
7197 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
7198 DAG.getConstant(Offset, getPointerTy()));
7204 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
7205 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
7206 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
7207 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
7211 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
7212 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
7213 unsigned char OperandFlags) {
7214 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7215 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7216 DebugLoc dl = GA->getDebugLoc();
7217 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7218 GA->getValueType(0),
7222 SDValue Ops[] = { Chain, TGA, *InFlag };
7223 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3);
7225 SDValue Ops[] = { Chain, TGA };
7226 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2);
7229 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
7230 MFI->setAdjustsStack(true);
7232 SDValue Flag = Chain.getValue(1);
7233 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
7236 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
7238 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7241 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
7242 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
7243 DAG.getNode(X86ISD::GlobalBaseReg,
7244 DebugLoc(), PtrVT), InFlag);
7245 InFlag = Chain.getValue(1);
7247 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
7250 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
7252 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7254 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
7255 X86::RAX, X86II::MO_TLSGD);
7258 // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
7259 // "local exec" model.
7260 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7261 const EVT PtrVT, TLSModel::Model model,
7263 DebugLoc dl = GA->getDebugLoc();
7265 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
7266 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
7267 is64Bit ? 257 : 256));
7269 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
7270 DAG.getIntPtrConstant(0),
7271 MachinePointerInfo(Ptr),
7272 false, false, false, 0);
7274 unsigned char OperandFlags = 0;
7275 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
7277 unsigned WrapperKind = X86ISD::Wrapper;
7278 if (model == TLSModel::LocalExec) {
7279 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
7280 } else if (is64Bit) {
7281 assert(model == TLSModel::InitialExec);
7282 OperandFlags = X86II::MO_GOTTPOFF;
7283 WrapperKind = X86ISD::WrapperRIP;
7285 assert(model == TLSModel::InitialExec);
7286 OperandFlags = X86II::MO_INDNTPOFF;
7289 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
7291 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7292 GA->getValueType(0),
7293 GA->getOffset(), OperandFlags);
7294 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
7296 if (model == TLSModel::InitialExec)
7297 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
7298 MachinePointerInfo::getGOT(), false, false, false, 0);
7300 // The address of the thread local variable is the add of the thread
7301 // pointer with the offset of the variable.
7302 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
7306 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
7308 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
7309 const GlobalValue *GV = GA->getGlobal();
7311 if (Subtarget->isTargetELF()) {
7312 // TODO: implement the "local dynamic" model
7313 // TODO: implement the "initial exec"model for pic executables
7315 // If GV is an alias then use the aliasee for determining
7316 // thread-localness.
7317 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
7318 GV = GA->resolveAliasedGlobal(false);
7320 TLSModel::Model model = getTargetMachine().getTLSModel(GV);
7323 case TLSModel::GeneralDynamic:
7324 case TLSModel::LocalDynamic: // not implemented
7325 if (Subtarget->is64Bit())
7326 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
7327 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
7329 case TLSModel::InitialExec:
7330 case TLSModel::LocalExec:
7331 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
7332 Subtarget->is64Bit());
7334 llvm_unreachable("Unknown TLS model.");
7337 if (Subtarget->isTargetDarwin()) {
7338 // Darwin only has one model of TLS. Lower to that.
7339 unsigned char OpFlag = 0;
7340 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
7341 X86ISD::WrapperRIP : X86ISD::Wrapper;
7343 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7345 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) &&
7346 !Subtarget->is64Bit();
7348 OpFlag = X86II::MO_TLVP_PIC_BASE;
7350 OpFlag = X86II::MO_TLVP;
7351 DebugLoc DL = Op.getDebugLoc();
7352 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
7353 GA->getValueType(0),
7354 GA->getOffset(), OpFlag);
7355 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7357 // With PIC32, the address is actually $g + Offset.
7359 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7360 DAG.getNode(X86ISD::GlobalBaseReg,
7361 DebugLoc(), getPointerTy()),
7364 // Lowering the machine isd will make sure everything is in the right
7366 SDValue Chain = DAG.getEntryNode();
7367 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7368 SDValue Args[] = { Chain, Offset };
7369 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2);
7371 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
7372 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7373 MFI->setAdjustsStack(true);
7375 // And our return value (tls address) is in the standard call return value
7377 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
7378 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
7382 if (Subtarget->isTargetWindows()) {
7383 // Just use the implicit TLS architecture
7384 // Need to generate someting similar to:
7385 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
7387 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
7388 // mov rcx, qword [rdx+rcx*8]
7389 // mov eax, .tls$:tlsvar
7390 // [rax+rcx] contains the address
7391 // Windows 64bit: gs:0x58
7392 // Windows 32bit: fs:__tls_array
7394 // If GV is an alias then use the aliasee for determining
7395 // thread-localness.
7396 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
7397 GV = GA->resolveAliasedGlobal(false);
7398 DebugLoc dl = GA->getDebugLoc();
7399 SDValue Chain = DAG.getEntryNode();
7401 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
7402 // %gs:0x58 (64-bit).
7403 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
7404 ? Type::getInt8PtrTy(*DAG.getContext(),
7406 : Type::getInt32PtrTy(*DAG.getContext(),
7409 SDValue ThreadPointer = DAG.getLoad(getPointerTy(), dl, Chain,
7410 Subtarget->is64Bit()
7411 ? DAG.getIntPtrConstant(0x58)
7412 : DAG.getExternalSymbol("_tls_array",
7414 MachinePointerInfo(Ptr),
7415 false, false, false, 0);
7417 // Load the _tls_index variable
7418 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
7419 if (Subtarget->is64Bit())
7420 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
7421 IDX, MachinePointerInfo(), MVT::i32,
7424 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
7425 false, false, false, 0);
7427 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
7429 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
7431 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
7432 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
7433 false, false, false, 0);
7435 // Get the offset of start of .tls section
7436 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7437 GA->getValueType(0),
7438 GA->getOffset(), X86II::MO_SECREL);
7439 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
7441 // The address of the thread local variable is the add of the thread
7442 // pointer with the offset of the variable.
7443 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
7446 llvm_unreachable("TLS not implemented for this target.");
7450 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
7451 /// and take a 2 x i32 value to shift plus a shift amount.
7452 SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const{
7453 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
7454 EVT VT = Op.getValueType();
7455 unsigned VTBits = VT.getSizeInBits();
7456 DebugLoc dl = Op.getDebugLoc();
7457 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
7458 SDValue ShOpLo = Op.getOperand(0);
7459 SDValue ShOpHi = Op.getOperand(1);
7460 SDValue ShAmt = Op.getOperand(2);
7461 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
7462 DAG.getConstant(VTBits - 1, MVT::i8))
7463 : DAG.getConstant(0, VT);
7466 if (Op.getOpcode() == ISD::SHL_PARTS) {
7467 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
7468 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
7470 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
7471 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
7474 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
7475 DAG.getConstant(VTBits, MVT::i8));
7476 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
7477 AndNode, DAG.getConstant(0, MVT::i8));
7480 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
7481 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
7482 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
7484 if (Op.getOpcode() == ISD::SHL_PARTS) {
7485 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7486 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7488 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7489 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7492 SDValue Ops[2] = { Lo, Hi };
7493 return DAG.getMergeValues(Ops, 2, dl);
7496 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
7497 SelectionDAG &DAG) const {
7498 EVT SrcVT = Op.getOperand(0).getValueType();
7500 if (SrcVT.isVector())
7503 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
7504 "Unknown SINT_TO_FP to lower!");
7506 // These are really Legal; return the operand so the caller accepts it as
7508 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
7510 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
7511 Subtarget->is64Bit()) {
7515 DebugLoc dl = Op.getDebugLoc();
7516 unsigned Size = SrcVT.getSizeInBits()/8;
7517 MachineFunction &MF = DAG.getMachineFunction();
7518 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
7519 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7520 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7522 MachinePointerInfo::getFixedStack(SSFI),
7524 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
7527 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
7529 SelectionDAG &DAG) const {
7531 DebugLoc DL = Op.getDebugLoc();
7533 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
7535 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
7537 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
7539 unsigned ByteSize = SrcVT.getSizeInBits()/8;
7541 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
7542 MachineMemOperand *MMO;
7544 int SSFI = FI->getIndex();
7546 DAG.getMachineFunction()
7547 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7548 MachineMemOperand::MOLoad, ByteSize, ByteSize);
7550 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
7551 StackSlot = StackSlot.getOperand(1);
7553 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
7554 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
7556 Tys, Ops, array_lengthof(Ops),
7560 Chain = Result.getValue(1);
7561 SDValue InFlag = Result.getValue(2);
7563 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
7564 // shouldn't be necessary except that RFP cannot be live across
7565 // multiple blocks. When stackifier is fixed, they can be uncoupled.
7566 MachineFunction &MF = DAG.getMachineFunction();
7567 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
7568 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
7569 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7570 Tys = DAG.getVTList(MVT::Other);
7572 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
7574 MachineMemOperand *MMO =
7575 DAG.getMachineFunction()
7576 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7577 MachineMemOperand::MOStore, SSFISize, SSFISize);
7579 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
7580 Ops, array_lengthof(Ops),
7581 Op.getValueType(), MMO);
7582 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
7583 MachinePointerInfo::getFixedStack(SSFI),
7584 false, false, false, 0);
7590 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
7591 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
7592 SelectionDAG &DAG) const {
7593 // This algorithm is not obvious. Here it is what we're trying to output:
7596 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
7597 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
7601 pshufd $0x4e, %xmm0, %xmm1
7606 DebugLoc dl = Op.getDebugLoc();
7607 LLVMContext *Context = DAG.getContext();
7609 // Build some magic constants.
7610 const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
7611 Constant *C0 = ConstantDataVector::get(*Context, CV0);
7612 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
7614 SmallVector<Constant*,2> CV1;
7616 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL))));
7618 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL))));
7619 Constant *C1 = ConstantVector::get(CV1);
7620 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
7622 // Load the 64-bit value into an XMM register.
7623 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
7625 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
7626 MachinePointerInfo::getConstantPool(),
7627 false, false, false, 16);
7628 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
7629 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
7632 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
7633 MachinePointerInfo::getConstantPool(),
7634 false, false, false, 16);
7635 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
7636 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
7639 if (Subtarget->hasSSE3()) {
7640 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
7641 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
7643 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
7644 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
7646 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
7647 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
7651 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
7652 DAG.getIntPtrConstant(0));
7655 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
7656 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
7657 SelectionDAG &DAG) const {
7658 DebugLoc dl = Op.getDebugLoc();
7659 // FP constant to bias correct the final result.
7660 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
7663 // Load the 32-bit value into an XMM register.
7664 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
7667 // Zero out the upper parts of the register.
7668 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
7670 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
7671 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
7672 DAG.getIntPtrConstant(0));
7674 // Or the load with the bias.
7675 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
7676 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7677 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
7679 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7680 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
7681 MVT::v2f64, Bias)));
7682 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
7683 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
7684 DAG.getIntPtrConstant(0));
7686 // Subtract the bias.
7687 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
7689 // Handle final rounding.
7690 EVT DestVT = Op.getValueType();
7692 if (DestVT.bitsLT(MVT::f64))
7693 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
7694 DAG.getIntPtrConstant(0));
7695 if (DestVT.bitsGT(MVT::f64))
7696 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
7698 // Handle final rounding.
7702 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
7703 SelectionDAG &DAG) const {
7704 SDValue N0 = Op.getOperand(0);
7705 DebugLoc dl = Op.getDebugLoc();
7707 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
7708 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
7709 // the optimization here.
7710 if (DAG.SignBitIsZero(N0))
7711 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
7713 EVT SrcVT = N0.getValueType();
7714 EVT DstVT = Op.getValueType();
7715 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
7716 return LowerUINT_TO_FP_i64(Op, DAG);
7717 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
7718 return LowerUINT_TO_FP_i32(Op, DAG);
7719 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
7722 // Make a 64-bit buffer, and use it to build an FILD.
7723 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
7724 if (SrcVT == MVT::i32) {
7725 SDValue WordOff = DAG.getConstant(4, getPointerTy());
7726 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
7727 getPointerTy(), StackSlot, WordOff);
7728 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7729 StackSlot, MachinePointerInfo(),
7731 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
7732 OffsetSlot, MachinePointerInfo(),
7734 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
7738 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
7739 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7740 StackSlot, MachinePointerInfo(),
7742 // For i64 source, we need to add the appropriate power of 2 if the input
7743 // was negative. This is the same as the optimization in
7744 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
7745 // we must be careful to do the computation in x87 extended precision, not
7746 // in SSE. (The generic code can't know it's OK to do this, or how to.)
7747 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
7748 MachineMemOperand *MMO =
7749 DAG.getMachineFunction()
7750 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7751 MachineMemOperand::MOLoad, 8, 8);
7753 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
7754 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
7755 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops, 3,
7758 APInt FF(32, 0x5F800000ULL);
7760 // Check whether the sign bit is set.
7761 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
7762 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
7765 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
7766 SDValue FudgePtr = DAG.getConstantPool(
7767 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
7770 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
7771 SDValue Zero = DAG.getIntPtrConstant(0);
7772 SDValue Four = DAG.getIntPtrConstant(4);
7773 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
7775 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
7777 // Load the value out, extending it from f32 to f80.
7778 // FIXME: Avoid the extend by constructing the right constant pool?
7779 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
7780 FudgePtr, MachinePointerInfo::getConstantPool(),
7781 MVT::f32, false, false, 4);
7782 // Extend everything to 80 bits to force it to be done on x87.
7783 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
7784 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
7787 std::pair<SDValue,SDValue> X86TargetLowering::
7788 FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned, bool IsReplace) const {
7789 DebugLoc DL = Op.getDebugLoc();
7791 EVT DstTy = Op.getValueType();
7793 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
7794 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
7798 assert(DstTy.getSimpleVT() <= MVT::i64 &&
7799 DstTy.getSimpleVT() >= MVT::i16 &&
7800 "Unknown FP_TO_INT to lower!");
7802 // These are really Legal.
7803 if (DstTy == MVT::i32 &&
7804 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
7805 return std::make_pair(SDValue(), SDValue());
7806 if (Subtarget->is64Bit() &&
7807 DstTy == MVT::i64 &&
7808 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
7809 return std::make_pair(SDValue(), SDValue());
7811 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
7812 // stack slot, or into the FTOL runtime function.
7813 MachineFunction &MF = DAG.getMachineFunction();
7814 unsigned MemSize = DstTy.getSizeInBits()/8;
7815 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
7816 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7819 if (!IsSigned && isIntegerTypeFTOL(DstTy))
7820 Opc = X86ISD::WIN_FTOL;
7822 switch (DstTy.getSimpleVT().SimpleTy) {
7823 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
7824 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
7825 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
7826 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
7829 SDValue Chain = DAG.getEntryNode();
7830 SDValue Value = Op.getOperand(0);
7831 EVT TheVT = Op.getOperand(0).getValueType();
7832 // FIXME This causes a redundant load/store if the SSE-class value is already
7833 // in memory, such as if it is on the callstack.
7834 if (isScalarFPTypeInSSEReg(TheVT)) {
7835 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
7836 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
7837 MachinePointerInfo::getFixedStack(SSFI),
7839 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
7841 Chain, StackSlot, DAG.getValueType(TheVT)
7844 MachineMemOperand *MMO =
7845 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7846 MachineMemOperand::MOLoad, MemSize, MemSize);
7847 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, 3,
7849 Chain = Value.getValue(1);
7850 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
7851 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7854 MachineMemOperand *MMO =
7855 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7856 MachineMemOperand::MOStore, MemSize, MemSize);
7858 if (Opc != X86ISD::WIN_FTOL) {
7859 // Build the FP_TO_INT*_IN_MEM
7860 SDValue Ops[] = { Chain, Value, StackSlot };
7861 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
7862 Ops, 3, DstTy, MMO);
7863 return std::make_pair(FIST, StackSlot);
7865 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
7866 DAG.getVTList(MVT::Other, MVT::Glue),
7868 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
7869 MVT::i32, ftol.getValue(1));
7870 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
7871 MVT::i32, eax.getValue(2));
7872 SDValue Ops[] = { eax, edx };
7873 SDValue pair = IsReplace
7874 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops, 2)
7875 : DAG.getMergeValues(Ops, 2, DL);
7876 return std::make_pair(pair, SDValue());
7880 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
7881 SelectionDAG &DAG) const {
7882 if (Op.getValueType().isVector())
7885 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
7886 /*IsSigned=*/ true, /*IsReplace=*/ false);
7887 SDValue FIST = Vals.first, StackSlot = Vals.second;
7888 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
7889 if (FIST.getNode() == 0) return Op;
7891 if (StackSlot.getNode())
7893 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
7894 FIST, StackSlot, MachinePointerInfo(),
7895 false, false, false, 0);
7897 // The node is the result.
7901 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
7902 SelectionDAG &DAG) const {
7903 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
7904 /*IsSigned=*/ false, /*IsReplace=*/ false);
7905 SDValue FIST = Vals.first, StackSlot = Vals.second;
7906 assert(FIST.getNode() && "Unexpected failure");
7908 if (StackSlot.getNode())
7910 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
7911 FIST, StackSlot, MachinePointerInfo(),
7912 false, false, false, 0);
7914 // The node is the result.
7918 SDValue X86TargetLowering::LowerFABS(SDValue Op,
7919 SelectionDAG &DAG) const {
7920 LLVMContext *Context = DAG.getContext();
7921 DebugLoc dl = Op.getDebugLoc();
7922 EVT VT = Op.getValueType();
7925 EltVT = VT.getVectorElementType();
7927 if (EltVT == MVT::f64) {
7928 C = ConstantVector::getSplat(2,
7929 ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
7931 C = ConstantVector::getSplat(4,
7932 ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
7934 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7935 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
7936 MachinePointerInfo::getConstantPool(),
7937 false, false, false, 16);
7938 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
7941 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const {
7942 LLVMContext *Context = DAG.getContext();
7943 DebugLoc dl = Op.getDebugLoc();
7944 EVT VT = Op.getValueType();
7946 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
7947 if (VT.isVector()) {
7948 EltVT = VT.getVectorElementType();
7949 NumElts = VT.getVectorNumElements();
7952 if (EltVT == MVT::f64)
7953 C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)));
7955 C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)));
7956 C = ConstantVector::getSplat(NumElts, C);
7957 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7958 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
7959 MachinePointerInfo::getConstantPool(),
7960 false, false, false, 16);
7961 if (VT.isVector()) {
7962 MVT XORVT = VT.getSizeInBits() == 128 ? MVT::v2i64 : MVT::v4i64;
7963 return DAG.getNode(ISD::BITCAST, dl, VT,
7964 DAG.getNode(ISD::XOR, dl, XORVT,
7965 DAG.getNode(ISD::BITCAST, dl, XORVT,
7967 DAG.getNode(ISD::BITCAST, dl, XORVT, Mask)));
7970 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
7973 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
7974 LLVMContext *Context = DAG.getContext();
7975 SDValue Op0 = Op.getOperand(0);
7976 SDValue Op1 = Op.getOperand(1);
7977 DebugLoc dl = Op.getDebugLoc();
7978 EVT VT = Op.getValueType();
7979 EVT SrcVT = Op1.getValueType();
7981 // If second operand is smaller, extend it first.
7982 if (SrcVT.bitsLT(VT)) {
7983 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
7986 // And if it is bigger, shrink it first.
7987 if (SrcVT.bitsGT(VT)) {
7988 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
7992 // At this point the operands and the result should have the same
7993 // type, and that won't be f80 since that is not custom lowered.
7995 // First get the sign bit of second operand.
7996 SmallVector<Constant*,4> CV;
7997 if (SrcVT == MVT::f64) {
7998 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))));
7999 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
8001 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))));
8002 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8003 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8004 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8006 Constant *C = ConstantVector::get(CV);
8007 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8008 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
8009 MachinePointerInfo::getConstantPool(),
8010 false, false, false, 16);
8011 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
8013 // Shift sign bit right or left if the two operands have different types.
8014 if (SrcVT.bitsGT(VT)) {
8015 // Op0 is MVT::f32, Op1 is MVT::f64.
8016 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
8017 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
8018 DAG.getConstant(32, MVT::i32));
8019 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
8020 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
8021 DAG.getIntPtrConstant(0));
8024 // Clear first operand sign bit.
8026 if (VT == MVT::f64) {
8027 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
8028 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
8030 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
8031 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8032 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8033 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8035 C = ConstantVector::get(CV);
8036 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8037 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8038 MachinePointerInfo::getConstantPool(),
8039 false, false, false, 16);
8040 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
8042 // Or the value with the sign bit.
8043 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
8046 SDValue X86TargetLowering::LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) const {
8047 SDValue N0 = Op.getOperand(0);
8048 DebugLoc dl = Op.getDebugLoc();
8049 EVT VT = Op.getValueType();
8051 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
8052 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
8053 DAG.getConstant(1, VT));
8054 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
8057 /// Emit nodes that will be selected as "test Op0,Op0", or something
8059 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
8060 SelectionDAG &DAG) const {
8061 DebugLoc dl = Op.getDebugLoc();
8063 // CF and OF aren't always set the way we want. Determine which
8064 // of these we need.
8065 bool NeedCF = false;
8066 bool NeedOF = false;
8069 case X86::COND_A: case X86::COND_AE:
8070 case X86::COND_B: case X86::COND_BE:
8073 case X86::COND_G: case X86::COND_GE:
8074 case X86::COND_L: case X86::COND_LE:
8075 case X86::COND_O: case X86::COND_NO:
8080 // See if we can use the EFLAGS value from the operand instead of
8081 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
8082 // we prove that the arithmetic won't overflow, we can't use OF or CF.
8083 if (Op.getResNo() != 0 || NeedOF || NeedCF)
8084 // Emit a CMP with 0, which is the TEST pattern.
8085 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
8086 DAG.getConstant(0, Op.getValueType()));
8088 unsigned Opcode = 0;
8089 unsigned NumOperands = 0;
8090 switch (Op.getNode()->getOpcode()) {
8092 // Due to an isel shortcoming, be conservative if this add is likely to be
8093 // selected as part of a load-modify-store instruction. When the root node
8094 // in a match is a store, isel doesn't know how to remap non-chain non-flag
8095 // uses of other nodes in the match, such as the ADD in this case. This
8096 // leads to the ADD being left around and reselected, with the result being
8097 // two adds in the output. Alas, even if none our users are stores, that
8098 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
8099 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
8100 // climbing the DAG back to the root, and it doesn't seem to be worth the
8102 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8103 UE = Op.getNode()->use_end(); UI != UE; ++UI)
8104 if (UI->getOpcode() != ISD::CopyToReg &&
8105 UI->getOpcode() != ISD::SETCC &&
8106 UI->getOpcode() != ISD::STORE)
8109 if (ConstantSDNode *C =
8110 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) {
8111 // An add of one will be selected as an INC.
8112 if (C->getAPIntValue() == 1) {
8113 Opcode = X86ISD::INC;
8118 // An add of negative one (subtract of one) will be selected as a DEC.
8119 if (C->getAPIntValue().isAllOnesValue()) {
8120 Opcode = X86ISD::DEC;
8126 // Otherwise use a regular EFLAGS-setting add.
8127 Opcode = X86ISD::ADD;
8131 // If the primary and result isn't used, don't bother using X86ISD::AND,
8132 // because a TEST instruction will be better.
8133 bool NonFlagUse = false;
8134 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8135 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
8137 unsigned UOpNo = UI.getOperandNo();
8138 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
8139 // Look pass truncate.
8140 UOpNo = User->use_begin().getOperandNo();
8141 User = *User->use_begin();
8144 if (User->getOpcode() != ISD::BRCOND &&
8145 User->getOpcode() != ISD::SETCC &&
8146 (User->getOpcode() != ISD::SELECT || UOpNo != 0)) {
8159 // Due to the ISEL shortcoming noted above, be conservative if this op is
8160 // likely to be selected as part of a load-modify-store instruction.
8161 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8162 UE = Op.getNode()->use_end(); UI != UE; ++UI)
8163 if (UI->getOpcode() == ISD::STORE)
8166 // Otherwise use a regular EFLAGS-setting instruction.
8167 switch (Op.getNode()->getOpcode()) {
8168 default: llvm_unreachable("unexpected operator!");
8169 case ISD::SUB: Opcode = X86ISD::SUB; break;
8170 case ISD::OR: Opcode = X86ISD::OR; break;
8171 case ISD::XOR: Opcode = X86ISD::XOR; break;
8172 case ISD::AND: Opcode = X86ISD::AND; break;
8184 return SDValue(Op.getNode(), 1);
8191 // Emit a CMP with 0, which is the TEST pattern.
8192 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
8193 DAG.getConstant(0, Op.getValueType()));
8195 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
8196 SmallVector<SDValue, 4> Ops;
8197 for (unsigned i = 0; i != NumOperands; ++i)
8198 Ops.push_back(Op.getOperand(i));
8200 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
8201 DAG.ReplaceAllUsesWith(Op, New);
8202 return SDValue(New.getNode(), 1);
8205 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
8207 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
8208 SelectionDAG &DAG) const {
8209 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
8210 if (C->getAPIntValue() == 0)
8211 return EmitTest(Op0, X86CC, DAG);
8213 DebugLoc dl = Op0.getDebugLoc();
8214 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
8217 /// Convert a comparison if required by the subtarget.
8218 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
8219 SelectionDAG &DAG) const {
8220 // If the subtarget does not support the FUCOMI instruction, floating-point
8221 // comparisons have to be converted.
8222 if (Subtarget->hasCMov() ||
8223 Cmp.getOpcode() != X86ISD::CMP ||
8224 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
8225 !Cmp.getOperand(1).getValueType().isFloatingPoint())
8228 // The instruction selector will select an FUCOM instruction instead of
8229 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
8230 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
8231 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
8232 DebugLoc dl = Cmp.getDebugLoc();
8233 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
8234 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
8235 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
8236 DAG.getConstant(8, MVT::i8));
8237 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
8238 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
8241 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
8242 /// if it's possible.
8243 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
8244 DebugLoc dl, SelectionDAG &DAG) const {
8245 SDValue Op0 = And.getOperand(0);
8246 SDValue Op1 = And.getOperand(1);
8247 if (Op0.getOpcode() == ISD::TRUNCATE)
8248 Op0 = Op0.getOperand(0);
8249 if (Op1.getOpcode() == ISD::TRUNCATE)
8250 Op1 = Op1.getOperand(0);
8253 if (Op1.getOpcode() == ISD::SHL)
8254 std::swap(Op0, Op1);
8255 if (Op0.getOpcode() == ISD::SHL) {
8256 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
8257 if (And00C->getZExtValue() == 1) {
8258 // If we looked past a truncate, check that it's only truncating away
8260 unsigned BitWidth = Op0.getValueSizeInBits();
8261 unsigned AndBitWidth = And.getValueSizeInBits();
8262 if (BitWidth > AndBitWidth) {
8264 DAG.ComputeMaskedBits(Op0, Zeros, Ones);
8265 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
8269 RHS = Op0.getOperand(1);
8271 } else if (Op1.getOpcode() == ISD::Constant) {
8272 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
8273 uint64_t AndRHSVal = AndRHS->getZExtValue();
8274 SDValue AndLHS = Op0;
8276 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
8277 LHS = AndLHS.getOperand(0);
8278 RHS = AndLHS.getOperand(1);
8281 // Use BT if the immediate can't be encoded in a TEST instruction.
8282 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
8284 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
8288 if (LHS.getNode()) {
8289 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
8290 // instruction. Since the shift amount is in-range-or-undefined, we know
8291 // that doing a bittest on the i32 value is ok. We extend to i32 because
8292 // the encoding for the i16 version is larger than the i32 version.
8293 // Also promote i16 to i32 for performance / code size reason.
8294 if (LHS.getValueType() == MVT::i8 ||
8295 LHS.getValueType() == MVT::i16)
8296 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
8298 // If the operand types disagree, extend the shift amount to match. Since
8299 // BT ignores high bits (like shifts) we can use anyextend.
8300 if (LHS.getValueType() != RHS.getValueType())
8301 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
8303 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
8304 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
8305 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8306 DAG.getConstant(Cond, MVT::i8), BT);
8312 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
8314 if (Op.getValueType().isVector()) return LowerVSETCC(Op, DAG);
8316 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
8317 SDValue Op0 = Op.getOperand(0);
8318 SDValue Op1 = Op.getOperand(1);
8319 DebugLoc dl = Op.getDebugLoc();
8320 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
8322 // Optimize to BT if possible.
8323 // Lower (X & (1 << N)) == 0 to BT(X, N).
8324 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
8325 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
8326 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
8327 Op1.getOpcode() == ISD::Constant &&
8328 cast<ConstantSDNode>(Op1)->isNullValue() &&
8329 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
8330 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
8331 if (NewSetCC.getNode())
8335 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
8337 if (Op1.getOpcode() == ISD::Constant &&
8338 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
8339 cast<ConstantSDNode>(Op1)->isNullValue()) &&
8340 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
8342 // If the input is a setcc, then reuse the input setcc or use a new one with
8343 // the inverted condition.
8344 if (Op0.getOpcode() == X86ISD::SETCC) {
8345 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
8346 bool Invert = (CC == ISD::SETNE) ^
8347 cast<ConstantSDNode>(Op1)->isNullValue();
8348 if (!Invert) return Op0;
8350 CCode = X86::GetOppositeBranchCondition(CCode);
8351 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8352 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1));
8356 bool isFP = Op1.getValueType().isFloatingPoint();
8357 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
8358 if (X86CC == X86::COND_INVALID)
8361 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG);
8362 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
8363 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8364 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
8367 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
8368 // ones, and then concatenate the result back.
8369 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
8370 EVT VT = Op.getValueType();
8372 assert(VT.getSizeInBits() == 256 && Op.getOpcode() == ISD::SETCC &&
8373 "Unsupported value type for operation");
8375 unsigned NumElems = VT.getVectorNumElements();
8376 DebugLoc dl = Op.getDebugLoc();
8377 SDValue CC = Op.getOperand(2);
8379 // Extract the LHS vectors
8380 SDValue LHS = Op.getOperand(0);
8381 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
8382 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
8384 // Extract the RHS vectors
8385 SDValue RHS = Op.getOperand(1);
8386 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
8387 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
8389 // Issue the operation on the smaller types and concatenate the result back
8390 MVT EltVT = VT.getVectorElementType().getSimpleVT();
8391 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
8392 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
8393 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
8394 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
8398 SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const {
8400 SDValue Op0 = Op.getOperand(0);
8401 SDValue Op1 = Op.getOperand(1);
8402 SDValue CC = Op.getOperand(2);
8403 EVT VT = Op.getValueType();
8404 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
8405 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
8406 DebugLoc dl = Op.getDebugLoc();
8410 EVT EltVT = Op0.getValueType().getVectorElementType();
8411 assert(EltVT == MVT::f32 || EltVT == MVT::f64); (void)EltVT;
8415 // SSE Condition code mapping:
8424 switch (SetCCOpcode) {
8427 case ISD::SETEQ: SSECC = 0; break;
8429 case ISD::SETGT: Swap = true; // Fallthrough
8431 case ISD::SETOLT: SSECC = 1; break;
8433 case ISD::SETGE: Swap = true; // Fallthrough
8435 case ISD::SETOLE: SSECC = 2; break;
8436 case ISD::SETUO: SSECC = 3; break;
8438 case ISD::SETNE: SSECC = 4; break;
8439 case ISD::SETULE: Swap = true;
8440 case ISD::SETUGE: SSECC = 5; break;
8441 case ISD::SETULT: Swap = true;
8442 case ISD::SETUGT: SSECC = 6; break;
8443 case ISD::SETO: SSECC = 7; break;
8446 std::swap(Op0, Op1);
8448 // In the two special cases we can't handle, emit two comparisons.
8450 if (SetCCOpcode == ISD::SETUEQ) {
8452 UNORD = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8453 DAG.getConstant(3, MVT::i8));
8454 EQ = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8455 DAG.getConstant(0, MVT::i8));
8456 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ);
8458 if (SetCCOpcode == ISD::SETONE) {
8460 ORD = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8461 DAG.getConstant(7, MVT::i8));
8462 NEQ = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8463 DAG.getConstant(4, MVT::i8));
8464 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ);
8466 llvm_unreachable("Illegal FP comparison");
8468 // Handle all other FP comparisons here.
8469 return DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8470 DAG.getConstant(SSECC, MVT::i8));
8473 // Break 256-bit integer vector compare into smaller ones.
8474 if (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2())
8475 return Lower256IntVSETCC(Op, DAG);
8477 // We are handling one of the integer comparisons here. Since SSE only has
8478 // GT and EQ comparisons for integer, swapping operands and multiple
8479 // operations may be required for some comparisons.
8481 bool Swap = false, Invert = false, FlipSigns = false;
8483 switch (SetCCOpcode) {
8485 case ISD::SETNE: Invert = true;
8486 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
8487 case ISD::SETLT: Swap = true;
8488 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
8489 case ISD::SETGE: Swap = true;
8490 case ISD::SETLE: Opc = X86ISD::PCMPGT; Invert = true; break;
8491 case ISD::SETULT: Swap = true;
8492 case ISD::SETUGT: Opc = X86ISD::PCMPGT; FlipSigns = true; break;
8493 case ISD::SETUGE: Swap = true;
8494 case ISD::SETULE: Opc = X86ISD::PCMPGT; FlipSigns = true; Invert = true; break;
8497 std::swap(Op0, Op1);
8499 // Check that the operation in question is available (most are plain SSE2,
8500 // but PCMPGTQ and PCMPEQQ have different requirements).
8501 if (Opc == X86ISD::PCMPGT && VT == MVT::v2i64 && !Subtarget->hasSSE42())
8503 if (Opc == X86ISD::PCMPEQ && VT == MVT::v2i64 && !Subtarget->hasSSE41())
8506 // Since SSE has no unsigned integer comparisons, we need to flip the sign
8507 // bits of the inputs before performing those operations.
8509 EVT EltVT = VT.getVectorElementType();
8510 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
8512 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
8513 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
8515 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
8516 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
8519 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
8521 // If the logical-not of the result is required, perform that now.
8523 Result = DAG.getNOT(dl, Result, VT);
8528 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
8529 static bool isX86LogicalCmp(SDValue Op) {
8530 unsigned Opc = Op.getNode()->getOpcode();
8531 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
8532 Opc == X86ISD::SAHF)
8534 if (Op.getResNo() == 1 &&
8535 (Opc == X86ISD::ADD ||
8536 Opc == X86ISD::SUB ||
8537 Opc == X86ISD::ADC ||
8538 Opc == X86ISD::SBB ||
8539 Opc == X86ISD::SMUL ||
8540 Opc == X86ISD::UMUL ||
8541 Opc == X86ISD::INC ||
8542 Opc == X86ISD::DEC ||
8543 Opc == X86ISD::OR ||
8544 Opc == X86ISD::XOR ||
8545 Opc == X86ISD::AND))
8548 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
8554 static bool isZero(SDValue V) {
8555 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
8556 return C && C->isNullValue();
8559 static bool isAllOnes(SDValue V) {
8560 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
8561 return C && C->isAllOnesValue();
8564 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
8565 bool addTest = true;
8566 SDValue Cond = Op.getOperand(0);
8567 SDValue Op1 = Op.getOperand(1);
8568 SDValue Op2 = Op.getOperand(2);
8569 DebugLoc DL = Op.getDebugLoc();
8572 if (Cond.getOpcode() == ISD::SETCC) {
8573 SDValue NewCond = LowerSETCC(Cond, DAG);
8574 if (NewCond.getNode())
8578 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
8579 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
8580 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
8581 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
8582 if (Cond.getOpcode() == X86ISD::SETCC &&
8583 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
8584 isZero(Cond.getOperand(1).getOperand(1))) {
8585 SDValue Cmp = Cond.getOperand(1);
8587 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
8589 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
8590 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
8591 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
8593 SDValue CmpOp0 = Cmp.getOperand(0);
8594 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
8595 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
8596 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
8598 SDValue Res = // Res = 0 or -1.
8599 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
8600 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
8602 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
8603 Res = DAG.getNOT(DL, Res, Res.getValueType());
8605 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
8606 if (N2C == 0 || !N2C->isNullValue())
8607 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
8612 // Look past (and (setcc_carry (cmp ...)), 1).
8613 if (Cond.getOpcode() == ISD::AND &&
8614 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
8615 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
8616 if (C && C->getAPIntValue() == 1)
8617 Cond = Cond.getOperand(0);
8620 // If condition flag is set by a X86ISD::CMP, then use it as the condition
8621 // setting operand in place of the X86ISD::SETCC.
8622 unsigned CondOpcode = Cond.getOpcode();
8623 if (CondOpcode == X86ISD::SETCC ||
8624 CondOpcode == X86ISD::SETCC_CARRY) {
8625 CC = Cond.getOperand(0);
8627 SDValue Cmp = Cond.getOperand(1);
8628 unsigned Opc = Cmp.getOpcode();
8629 EVT VT = Op.getValueType();
8631 bool IllegalFPCMov = false;
8632 if (VT.isFloatingPoint() && !VT.isVector() &&
8633 !isScalarFPTypeInSSEReg(VT)) // FPStack?
8634 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
8636 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
8637 Opc == X86ISD::BT) { // FIXME
8641 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
8642 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
8643 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
8644 Cond.getOperand(0).getValueType() != MVT::i8)) {
8645 SDValue LHS = Cond.getOperand(0);
8646 SDValue RHS = Cond.getOperand(1);
8650 switch (CondOpcode) {
8651 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
8652 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
8653 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
8654 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
8655 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
8656 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
8657 default: llvm_unreachable("unexpected overflowing operator");
8659 if (CondOpcode == ISD::UMULO)
8660 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
8663 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
8665 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
8667 if (CondOpcode == ISD::UMULO)
8668 Cond = X86Op.getValue(2);
8670 Cond = X86Op.getValue(1);
8672 CC = DAG.getConstant(X86Cond, MVT::i8);
8677 // Look pass the truncate.
8678 if (Cond.getOpcode() == ISD::TRUNCATE)
8679 Cond = Cond.getOperand(0);
8681 // We know the result of AND is compared against zero. Try to match
8683 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
8684 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
8685 if (NewSetCC.getNode()) {
8686 CC = NewSetCC.getOperand(0);
8687 Cond = NewSetCC.getOperand(1);
8694 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8695 Cond = EmitTest(Cond, X86::COND_NE, DAG);
8698 // a < b ? -1 : 0 -> RES = ~setcc_carry
8699 // a < b ? 0 : -1 -> RES = setcc_carry
8700 // a >= b ? -1 : 0 -> RES = setcc_carry
8701 // a >= b ? 0 : -1 -> RES = ~setcc_carry
8702 if (Cond.getOpcode() == X86ISD::CMP) {
8703 Cond = ConvertCmpIfNecessary(Cond, DAG);
8704 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
8706 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
8707 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
8708 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
8709 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
8710 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
8711 return DAG.getNOT(DL, Res, Res.getValueType());
8716 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
8717 // condition is true.
8718 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
8719 SDValue Ops[] = { Op2, Op1, CC, Cond };
8720 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops));
8723 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
8724 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
8725 // from the AND / OR.
8726 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
8727 Opc = Op.getOpcode();
8728 if (Opc != ISD::OR && Opc != ISD::AND)
8730 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
8731 Op.getOperand(0).hasOneUse() &&
8732 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
8733 Op.getOperand(1).hasOneUse());
8736 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
8737 // 1 and that the SETCC node has a single use.
8738 static bool isXor1OfSetCC(SDValue Op) {
8739 if (Op.getOpcode() != ISD::XOR)
8741 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
8742 if (N1C && N1C->getAPIntValue() == 1) {
8743 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
8744 Op.getOperand(0).hasOneUse();
8749 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
8750 bool addTest = true;
8751 SDValue Chain = Op.getOperand(0);
8752 SDValue Cond = Op.getOperand(1);
8753 SDValue Dest = Op.getOperand(2);
8754 DebugLoc dl = Op.getDebugLoc();
8756 bool Inverted = false;
8758 if (Cond.getOpcode() == ISD::SETCC) {
8759 // Check for setcc([su]{add,sub,mul}o == 0).
8760 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
8761 isa<ConstantSDNode>(Cond.getOperand(1)) &&
8762 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
8763 Cond.getOperand(0).getResNo() == 1 &&
8764 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
8765 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
8766 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
8767 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
8768 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
8769 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
8771 Cond = Cond.getOperand(0);
8773 SDValue NewCond = LowerSETCC(Cond, DAG);
8774 if (NewCond.getNode())
8779 // FIXME: LowerXALUO doesn't handle these!!
8780 else if (Cond.getOpcode() == X86ISD::ADD ||
8781 Cond.getOpcode() == X86ISD::SUB ||
8782 Cond.getOpcode() == X86ISD::SMUL ||
8783 Cond.getOpcode() == X86ISD::UMUL)
8784 Cond = LowerXALUO(Cond, DAG);
8787 // Look pass (and (setcc_carry (cmp ...)), 1).
8788 if (Cond.getOpcode() == ISD::AND &&
8789 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
8790 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
8791 if (C && C->getAPIntValue() == 1)
8792 Cond = Cond.getOperand(0);
8795 // If condition flag is set by a X86ISD::CMP, then use it as the condition
8796 // setting operand in place of the X86ISD::SETCC.
8797 unsigned CondOpcode = Cond.getOpcode();
8798 if (CondOpcode == X86ISD::SETCC ||
8799 CondOpcode == X86ISD::SETCC_CARRY) {
8800 CC = Cond.getOperand(0);
8802 SDValue Cmp = Cond.getOperand(1);
8803 unsigned Opc = Cmp.getOpcode();
8804 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
8805 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
8809 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
8813 // These can only come from an arithmetic instruction with overflow,
8814 // e.g. SADDO, UADDO.
8815 Cond = Cond.getNode()->getOperand(1);
8821 CondOpcode = Cond.getOpcode();
8822 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
8823 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
8824 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
8825 Cond.getOperand(0).getValueType() != MVT::i8)) {
8826 SDValue LHS = Cond.getOperand(0);
8827 SDValue RHS = Cond.getOperand(1);
8831 switch (CondOpcode) {
8832 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
8833 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
8834 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
8835 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
8836 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
8837 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
8838 default: llvm_unreachable("unexpected overflowing operator");
8841 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
8842 if (CondOpcode == ISD::UMULO)
8843 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
8846 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
8848 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
8850 if (CondOpcode == ISD::UMULO)
8851 Cond = X86Op.getValue(2);
8853 Cond = X86Op.getValue(1);
8855 CC = DAG.getConstant(X86Cond, MVT::i8);
8859 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
8860 SDValue Cmp = Cond.getOperand(0).getOperand(1);
8861 if (CondOpc == ISD::OR) {
8862 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
8863 // two branches instead of an explicit OR instruction with a
8865 if (Cmp == Cond.getOperand(1).getOperand(1) &&
8866 isX86LogicalCmp(Cmp)) {
8867 CC = Cond.getOperand(0).getOperand(0);
8868 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8869 Chain, Dest, CC, Cmp);
8870 CC = Cond.getOperand(1).getOperand(0);
8874 } else { // ISD::AND
8875 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
8876 // two branches instead of an explicit AND instruction with a
8877 // separate test. However, we only do this if this block doesn't
8878 // have a fall-through edge, because this requires an explicit
8879 // jmp when the condition is false.
8880 if (Cmp == Cond.getOperand(1).getOperand(1) &&
8881 isX86LogicalCmp(Cmp) &&
8882 Op.getNode()->hasOneUse()) {
8883 X86::CondCode CCode =
8884 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
8885 CCode = X86::GetOppositeBranchCondition(CCode);
8886 CC = DAG.getConstant(CCode, MVT::i8);
8887 SDNode *User = *Op.getNode()->use_begin();
8888 // Look for an unconditional branch following this conditional branch.
8889 // We need this because we need to reverse the successors in order
8890 // to implement FCMP_OEQ.
8891 if (User->getOpcode() == ISD::BR) {
8892 SDValue FalseBB = User->getOperand(1);
8894 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
8895 assert(NewBR == User);
8899 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8900 Chain, Dest, CC, Cmp);
8901 X86::CondCode CCode =
8902 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
8903 CCode = X86::GetOppositeBranchCondition(CCode);
8904 CC = DAG.getConstant(CCode, MVT::i8);
8910 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
8911 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
8912 // It should be transformed during dag combiner except when the condition
8913 // is set by a arithmetics with overflow node.
8914 X86::CondCode CCode =
8915 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
8916 CCode = X86::GetOppositeBranchCondition(CCode);
8917 CC = DAG.getConstant(CCode, MVT::i8);
8918 Cond = Cond.getOperand(0).getOperand(1);
8920 } else if (Cond.getOpcode() == ISD::SETCC &&
8921 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
8922 // For FCMP_OEQ, we can emit
8923 // two branches instead of an explicit AND instruction with a
8924 // separate test. However, we only do this if this block doesn't
8925 // have a fall-through edge, because this requires an explicit
8926 // jmp when the condition is false.
8927 if (Op.getNode()->hasOneUse()) {
8928 SDNode *User = *Op.getNode()->use_begin();
8929 // Look for an unconditional branch following this conditional branch.
8930 // We need this because we need to reverse the successors in order
8931 // to implement FCMP_OEQ.
8932 if (User->getOpcode() == ISD::BR) {
8933 SDValue FalseBB = User->getOperand(1);
8935 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
8936 assert(NewBR == User);
8940 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
8941 Cond.getOperand(0), Cond.getOperand(1));
8942 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
8943 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8944 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8945 Chain, Dest, CC, Cmp);
8946 CC = DAG.getConstant(X86::COND_P, MVT::i8);
8951 } else if (Cond.getOpcode() == ISD::SETCC &&
8952 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
8953 // For FCMP_UNE, we can emit
8954 // two branches instead of an explicit AND instruction with a
8955 // separate test. However, we only do this if this block doesn't
8956 // have a fall-through edge, because this requires an explicit
8957 // jmp when the condition is false.
8958 if (Op.getNode()->hasOneUse()) {
8959 SDNode *User = *Op.getNode()->use_begin();
8960 // Look for an unconditional branch following this conditional branch.
8961 // We need this because we need to reverse the successors in order
8962 // to implement FCMP_UNE.
8963 if (User->getOpcode() == ISD::BR) {
8964 SDValue FalseBB = User->getOperand(1);
8966 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
8967 assert(NewBR == User);
8970 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
8971 Cond.getOperand(0), Cond.getOperand(1));
8972 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
8973 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8974 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8975 Chain, Dest, CC, Cmp);
8976 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
8986 // Look pass the truncate.
8987 if (Cond.getOpcode() == ISD::TRUNCATE)
8988 Cond = Cond.getOperand(0);
8990 // We know the result of AND is compared against zero. Try to match
8992 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
8993 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
8994 if (NewSetCC.getNode()) {
8995 CC = NewSetCC.getOperand(0);
8996 Cond = NewSetCC.getOperand(1);
9003 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
9004 Cond = EmitTest(Cond, X86::COND_NE, DAG);
9006 Cond = ConvertCmpIfNecessary(Cond, DAG);
9007 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
9008 Chain, Dest, CC, Cond);
9012 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
9013 // Calls to _alloca is needed to probe the stack when allocating more than 4k
9014 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
9015 // that the guard pages used by the OS virtual memory manager are allocated in
9016 // correct sequence.
9018 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
9019 SelectionDAG &DAG) const {
9020 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows() ||
9021 getTargetMachine().Options.EnableSegmentedStacks) &&
9022 "This should be used only on Windows targets or when segmented stacks "
9024 assert(!Subtarget->isTargetEnvMacho() && "Not implemented");
9025 DebugLoc dl = Op.getDebugLoc();
9028 SDValue Chain = Op.getOperand(0);
9029 SDValue Size = Op.getOperand(1);
9030 // FIXME: Ensure alignment here
9032 bool Is64Bit = Subtarget->is64Bit();
9033 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32;
9035 if (getTargetMachine().Options.EnableSegmentedStacks) {
9036 MachineFunction &MF = DAG.getMachineFunction();
9037 MachineRegisterInfo &MRI = MF.getRegInfo();
9040 // The 64 bit implementation of segmented stacks needs to clobber both r10
9041 // r11. This makes it impossible to use it along with nested parameters.
9042 const Function *F = MF.getFunction();
9044 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
9046 if (I->hasNestAttr())
9047 report_fatal_error("Cannot use segmented stacks with functions that "
9048 "have nested arguments.");
9051 const TargetRegisterClass *AddrRegClass =
9052 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32);
9053 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
9054 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
9055 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
9056 DAG.getRegister(Vreg, SPTy));
9057 SDValue Ops1[2] = { Value, Chain };
9058 return DAG.getMergeValues(Ops1, 2, dl);
9061 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
9063 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
9064 Flag = Chain.getValue(1);
9065 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
9067 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
9068 Flag = Chain.getValue(1);
9070 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1);
9072 SDValue Ops1[2] = { Chain.getValue(0), Chain };
9073 return DAG.getMergeValues(Ops1, 2, dl);
9077 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
9078 MachineFunction &MF = DAG.getMachineFunction();
9079 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
9081 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
9082 DebugLoc DL = Op.getDebugLoc();
9084 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
9085 // vastart just stores the address of the VarArgsFrameIndex slot into the
9086 // memory location argument.
9087 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
9089 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
9090 MachinePointerInfo(SV), false, false, 0);
9094 // gp_offset (0 - 6 * 8)
9095 // fp_offset (48 - 48 + 8 * 16)
9096 // overflow_arg_area (point to parameters coming in memory).
9098 SmallVector<SDValue, 8> MemOps;
9099 SDValue FIN = Op.getOperand(1);
9101 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
9102 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
9104 FIN, MachinePointerInfo(SV), false, false, 0);
9105 MemOps.push_back(Store);
9108 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9109 FIN, DAG.getIntPtrConstant(4));
9110 Store = DAG.getStore(Op.getOperand(0), DL,
9111 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
9113 FIN, MachinePointerInfo(SV, 4), false, false, 0);
9114 MemOps.push_back(Store);
9116 // Store ptr to overflow_arg_area
9117 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9118 FIN, DAG.getIntPtrConstant(4));
9119 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
9121 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
9122 MachinePointerInfo(SV, 8),
9124 MemOps.push_back(Store);
9126 // Store ptr to reg_save_area.
9127 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9128 FIN, DAG.getIntPtrConstant(8));
9129 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
9131 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
9132 MachinePointerInfo(SV, 16), false, false, 0);
9133 MemOps.push_back(Store);
9134 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
9135 &MemOps[0], MemOps.size());
9138 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
9139 assert(Subtarget->is64Bit() &&
9140 "LowerVAARG only handles 64-bit va_arg!");
9141 assert((Subtarget->isTargetLinux() ||
9142 Subtarget->isTargetDarwin()) &&
9143 "Unhandled target in LowerVAARG");
9144 assert(Op.getNode()->getNumOperands() == 4);
9145 SDValue Chain = Op.getOperand(0);
9146 SDValue SrcPtr = Op.getOperand(1);
9147 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
9148 unsigned Align = Op.getConstantOperandVal(3);
9149 DebugLoc dl = Op.getDebugLoc();
9151 EVT ArgVT = Op.getNode()->getValueType(0);
9152 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
9153 uint32_t ArgSize = getTargetData()->getTypeAllocSize(ArgTy);
9156 // Decide which area this value should be read from.
9157 // TODO: Implement the AMD64 ABI in its entirety. This simple
9158 // selection mechanism works only for the basic types.
9159 if (ArgVT == MVT::f80) {
9160 llvm_unreachable("va_arg for f80 not yet implemented");
9161 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
9162 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
9163 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
9164 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
9166 llvm_unreachable("Unhandled argument type in LowerVAARG");
9170 // Sanity Check: Make sure using fp_offset makes sense.
9171 assert(!getTargetMachine().Options.UseSoftFloat &&
9172 !(DAG.getMachineFunction()
9173 .getFunction()->hasFnAttr(Attribute::NoImplicitFloat)) &&
9174 Subtarget->hasSSE1());
9177 // Insert VAARG_64 node into the DAG
9178 // VAARG_64 returns two values: Variable Argument Address, Chain
9179 SmallVector<SDValue, 11> InstOps;
9180 InstOps.push_back(Chain);
9181 InstOps.push_back(SrcPtr);
9182 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
9183 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
9184 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
9185 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
9186 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
9187 VTs, &InstOps[0], InstOps.size(),
9189 MachinePointerInfo(SV),
9194 Chain = VAARG.getValue(1);
9196 // Load the next argument and return it
9197 return DAG.getLoad(ArgVT, dl,
9200 MachinePointerInfo(),
9201 false, false, false, 0);
9204 SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const {
9205 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
9206 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
9207 SDValue Chain = Op.getOperand(0);
9208 SDValue DstPtr = Op.getOperand(1);
9209 SDValue SrcPtr = Op.getOperand(2);
9210 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
9211 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
9212 DebugLoc DL = Op.getDebugLoc();
9214 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
9215 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
9217 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
9220 // getTargetVShiftNOde - Handle vector element shifts where the shift amount
9221 // may or may not be a constant. Takes immediate version of shift as input.
9222 static SDValue getTargetVShiftNode(unsigned Opc, DebugLoc dl, EVT VT,
9223 SDValue SrcOp, SDValue ShAmt,
9224 SelectionDAG &DAG) {
9225 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
9227 if (isa<ConstantSDNode>(ShAmt)) {
9229 default: llvm_unreachable("Unknown target vector shift node");
9233 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
9237 // Change opcode to non-immediate version
9239 default: llvm_unreachable("Unknown target vector shift node");
9240 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
9241 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
9242 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
9245 // Need to build a vector containing shift amount
9246 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
9249 ShOps[1] = DAG.getConstant(0, MVT::i32);
9250 ShOps[2] = DAG.getUNDEF(MVT::i32);
9251 ShOps[3] = DAG.getUNDEF(MVT::i32);
9252 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, &ShOps[0], 4);
9253 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt);
9254 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
9258 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const {
9259 DebugLoc dl = Op.getDebugLoc();
9260 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9262 default: return SDValue(); // Don't custom lower most intrinsics.
9263 // Comparison intrinsics.
9264 case Intrinsic::x86_sse_comieq_ss:
9265 case Intrinsic::x86_sse_comilt_ss:
9266 case Intrinsic::x86_sse_comile_ss:
9267 case Intrinsic::x86_sse_comigt_ss:
9268 case Intrinsic::x86_sse_comige_ss:
9269 case Intrinsic::x86_sse_comineq_ss:
9270 case Intrinsic::x86_sse_ucomieq_ss:
9271 case Intrinsic::x86_sse_ucomilt_ss:
9272 case Intrinsic::x86_sse_ucomile_ss:
9273 case Intrinsic::x86_sse_ucomigt_ss:
9274 case Intrinsic::x86_sse_ucomige_ss:
9275 case Intrinsic::x86_sse_ucomineq_ss:
9276 case Intrinsic::x86_sse2_comieq_sd:
9277 case Intrinsic::x86_sse2_comilt_sd:
9278 case Intrinsic::x86_sse2_comile_sd:
9279 case Intrinsic::x86_sse2_comigt_sd:
9280 case Intrinsic::x86_sse2_comige_sd:
9281 case Intrinsic::x86_sse2_comineq_sd:
9282 case Intrinsic::x86_sse2_ucomieq_sd:
9283 case Intrinsic::x86_sse2_ucomilt_sd:
9284 case Intrinsic::x86_sse2_ucomile_sd:
9285 case Intrinsic::x86_sse2_ucomigt_sd:
9286 case Intrinsic::x86_sse2_ucomige_sd:
9287 case Intrinsic::x86_sse2_ucomineq_sd: {
9289 ISD::CondCode CC = ISD::SETCC_INVALID;
9291 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
9292 case Intrinsic::x86_sse_comieq_ss:
9293 case Intrinsic::x86_sse2_comieq_sd:
9297 case Intrinsic::x86_sse_comilt_ss:
9298 case Intrinsic::x86_sse2_comilt_sd:
9302 case Intrinsic::x86_sse_comile_ss:
9303 case Intrinsic::x86_sse2_comile_sd:
9307 case Intrinsic::x86_sse_comigt_ss:
9308 case Intrinsic::x86_sse2_comigt_sd:
9312 case Intrinsic::x86_sse_comige_ss:
9313 case Intrinsic::x86_sse2_comige_sd:
9317 case Intrinsic::x86_sse_comineq_ss:
9318 case Intrinsic::x86_sse2_comineq_sd:
9322 case Intrinsic::x86_sse_ucomieq_ss:
9323 case Intrinsic::x86_sse2_ucomieq_sd:
9324 Opc = X86ISD::UCOMI;
9327 case Intrinsic::x86_sse_ucomilt_ss:
9328 case Intrinsic::x86_sse2_ucomilt_sd:
9329 Opc = X86ISD::UCOMI;
9332 case Intrinsic::x86_sse_ucomile_ss:
9333 case Intrinsic::x86_sse2_ucomile_sd:
9334 Opc = X86ISD::UCOMI;
9337 case Intrinsic::x86_sse_ucomigt_ss:
9338 case Intrinsic::x86_sse2_ucomigt_sd:
9339 Opc = X86ISD::UCOMI;
9342 case Intrinsic::x86_sse_ucomige_ss:
9343 case Intrinsic::x86_sse2_ucomige_sd:
9344 Opc = X86ISD::UCOMI;
9347 case Intrinsic::x86_sse_ucomineq_ss:
9348 case Intrinsic::x86_sse2_ucomineq_sd:
9349 Opc = X86ISD::UCOMI;
9354 SDValue LHS = Op.getOperand(1);
9355 SDValue RHS = Op.getOperand(2);
9356 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
9357 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
9358 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
9359 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9360 DAG.getConstant(X86CC, MVT::i8), Cond);
9361 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
9363 // XOP comparison intrinsics
9364 case Intrinsic::x86_xop_vpcomltb:
9365 case Intrinsic::x86_xop_vpcomltw:
9366 case Intrinsic::x86_xop_vpcomltd:
9367 case Intrinsic::x86_xop_vpcomltq:
9368 case Intrinsic::x86_xop_vpcomltub:
9369 case Intrinsic::x86_xop_vpcomltuw:
9370 case Intrinsic::x86_xop_vpcomltud:
9371 case Intrinsic::x86_xop_vpcomltuq:
9372 case Intrinsic::x86_xop_vpcomleb:
9373 case Intrinsic::x86_xop_vpcomlew:
9374 case Intrinsic::x86_xop_vpcomled:
9375 case Intrinsic::x86_xop_vpcomleq:
9376 case Intrinsic::x86_xop_vpcomleub:
9377 case Intrinsic::x86_xop_vpcomleuw:
9378 case Intrinsic::x86_xop_vpcomleud:
9379 case Intrinsic::x86_xop_vpcomleuq:
9380 case Intrinsic::x86_xop_vpcomgtb:
9381 case Intrinsic::x86_xop_vpcomgtw:
9382 case Intrinsic::x86_xop_vpcomgtd:
9383 case Intrinsic::x86_xop_vpcomgtq:
9384 case Intrinsic::x86_xop_vpcomgtub:
9385 case Intrinsic::x86_xop_vpcomgtuw:
9386 case Intrinsic::x86_xop_vpcomgtud:
9387 case Intrinsic::x86_xop_vpcomgtuq:
9388 case Intrinsic::x86_xop_vpcomgeb:
9389 case Intrinsic::x86_xop_vpcomgew:
9390 case Intrinsic::x86_xop_vpcomged:
9391 case Intrinsic::x86_xop_vpcomgeq:
9392 case Intrinsic::x86_xop_vpcomgeub:
9393 case Intrinsic::x86_xop_vpcomgeuw:
9394 case Intrinsic::x86_xop_vpcomgeud:
9395 case Intrinsic::x86_xop_vpcomgeuq:
9396 case Intrinsic::x86_xop_vpcomeqb:
9397 case Intrinsic::x86_xop_vpcomeqw:
9398 case Intrinsic::x86_xop_vpcomeqd:
9399 case Intrinsic::x86_xop_vpcomeqq:
9400 case Intrinsic::x86_xop_vpcomequb:
9401 case Intrinsic::x86_xop_vpcomequw:
9402 case Intrinsic::x86_xop_vpcomequd:
9403 case Intrinsic::x86_xop_vpcomequq:
9404 case Intrinsic::x86_xop_vpcomneb:
9405 case Intrinsic::x86_xop_vpcomnew:
9406 case Intrinsic::x86_xop_vpcomned:
9407 case Intrinsic::x86_xop_vpcomneq:
9408 case Intrinsic::x86_xop_vpcomneub:
9409 case Intrinsic::x86_xop_vpcomneuw:
9410 case Intrinsic::x86_xop_vpcomneud:
9411 case Intrinsic::x86_xop_vpcomneuq:
9412 case Intrinsic::x86_xop_vpcomfalseb:
9413 case Intrinsic::x86_xop_vpcomfalsew:
9414 case Intrinsic::x86_xop_vpcomfalsed:
9415 case Intrinsic::x86_xop_vpcomfalseq:
9416 case Intrinsic::x86_xop_vpcomfalseub:
9417 case Intrinsic::x86_xop_vpcomfalseuw:
9418 case Intrinsic::x86_xop_vpcomfalseud:
9419 case Intrinsic::x86_xop_vpcomfalseuq:
9420 case Intrinsic::x86_xop_vpcomtrueb:
9421 case Intrinsic::x86_xop_vpcomtruew:
9422 case Intrinsic::x86_xop_vpcomtrued:
9423 case Intrinsic::x86_xop_vpcomtrueq:
9424 case Intrinsic::x86_xop_vpcomtrueub:
9425 case Intrinsic::x86_xop_vpcomtrueuw:
9426 case Intrinsic::x86_xop_vpcomtrueud:
9427 case Intrinsic::x86_xop_vpcomtrueuq: {
9432 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
9433 case Intrinsic::x86_xop_vpcomltb:
9434 case Intrinsic::x86_xop_vpcomltw:
9435 case Intrinsic::x86_xop_vpcomltd:
9436 case Intrinsic::x86_xop_vpcomltq:
9438 Opc = X86ISD::VPCOM;
9440 case Intrinsic::x86_xop_vpcomltub:
9441 case Intrinsic::x86_xop_vpcomltuw:
9442 case Intrinsic::x86_xop_vpcomltud:
9443 case Intrinsic::x86_xop_vpcomltuq:
9445 Opc = X86ISD::VPCOMU;
9447 case Intrinsic::x86_xop_vpcomleb:
9448 case Intrinsic::x86_xop_vpcomlew:
9449 case Intrinsic::x86_xop_vpcomled:
9450 case Intrinsic::x86_xop_vpcomleq:
9452 Opc = X86ISD::VPCOM;
9454 case Intrinsic::x86_xop_vpcomleub:
9455 case Intrinsic::x86_xop_vpcomleuw:
9456 case Intrinsic::x86_xop_vpcomleud:
9457 case Intrinsic::x86_xop_vpcomleuq:
9459 Opc = X86ISD::VPCOMU;
9461 case Intrinsic::x86_xop_vpcomgtb:
9462 case Intrinsic::x86_xop_vpcomgtw:
9463 case Intrinsic::x86_xop_vpcomgtd:
9464 case Intrinsic::x86_xop_vpcomgtq:
9466 Opc = X86ISD::VPCOM;
9468 case Intrinsic::x86_xop_vpcomgtub:
9469 case Intrinsic::x86_xop_vpcomgtuw:
9470 case Intrinsic::x86_xop_vpcomgtud:
9471 case Intrinsic::x86_xop_vpcomgtuq:
9473 Opc = X86ISD::VPCOMU;
9475 case Intrinsic::x86_xop_vpcomgeb:
9476 case Intrinsic::x86_xop_vpcomgew:
9477 case Intrinsic::x86_xop_vpcomged:
9478 case Intrinsic::x86_xop_vpcomgeq:
9480 Opc = X86ISD::VPCOM;
9482 case Intrinsic::x86_xop_vpcomgeub:
9483 case Intrinsic::x86_xop_vpcomgeuw:
9484 case Intrinsic::x86_xop_vpcomgeud:
9485 case Intrinsic::x86_xop_vpcomgeuq:
9487 Opc = X86ISD::VPCOMU;
9489 case Intrinsic::x86_xop_vpcomeqb:
9490 case Intrinsic::x86_xop_vpcomeqw:
9491 case Intrinsic::x86_xop_vpcomeqd:
9492 case Intrinsic::x86_xop_vpcomeqq:
9494 Opc = X86ISD::VPCOM;
9496 case Intrinsic::x86_xop_vpcomequb:
9497 case Intrinsic::x86_xop_vpcomequw:
9498 case Intrinsic::x86_xop_vpcomequd:
9499 case Intrinsic::x86_xop_vpcomequq:
9501 Opc = X86ISD::VPCOMU;
9503 case Intrinsic::x86_xop_vpcomneb:
9504 case Intrinsic::x86_xop_vpcomnew:
9505 case Intrinsic::x86_xop_vpcomned:
9506 case Intrinsic::x86_xop_vpcomneq:
9508 Opc = X86ISD::VPCOM;
9510 case Intrinsic::x86_xop_vpcomneub:
9511 case Intrinsic::x86_xop_vpcomneuw:
9512 case Intrinsic::x86_xop_vpcomneud:
9513 case Intrinsic::x86_xop_vpcomneuq:
9515 Opc = X86ISD::VPCOMU;
9517 case Intrinsic::x86_xop_vpcomfalseb:
9518 case Intrinsic::x86_xop_vpcomfalsew:
9519 case Intrinsic::x86_xop_vpcomfalsed:
9520 case Intrinsic::x86_xop_vpcomfalseq:
9522 Opc = X86ISD::VPCOM;
9524 case Intrinsic::x86_xop_vpcomfalseub:
9525 case Intrinsic::x86_xop_vpcomfalseuw:
9526 case Intrinsic::x86_xop_vpcomfalseud:
9527 case Intrinsic::x86_xop_vpcomfalseuq:
9529 Opc = X86ISD::VPCOMU;
9531 case Intrinsic::x86_xop_vpcomtrueb:
9532 case Intrinsic::x86_xop_vpcomtruew:
9533 case Intrinsic::x86_xop_vpcomtrued:
9534 case Intrinsic::x86_xop_vpcomtrueq:
9536 Opc = X86ISD::VPCOM;
9538 case Intrinsic::x86_xop_vpcomtrueub:
9539 case Intrinsic::x86_xop_vpcomtrueuw:
9540 case Intrinsic::x86_xop_vpcomtrueud:
9541 case Intrinsic::x86_xop_vpcomtrueuq:
9543 Opc = X86ISD::VPCOMU;
9547 SDValue LHS = Op.getOperand(1);
9548 SDValue RHS = Op.getOperand(2);
9549 return DAG.getNode(Opc, dl, Op.getValueType(), LHS, RHS,
9550 DAG.getConstant(CC, MVT::i8));
9553 // Arithmetic intrinsics.
9554 case Intrinsic::x86_sse2_pmulu_dq:
9555 case Intrinsic::x86_avx2_pmulu_dq:
9556 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
9557 Op.getOperand(1), Op.getOperand(2));
9558 case Intrinsic::x86_sse3_hadd_ps:
9559 case Intrinsic::x86_sse3_hadd_pd:
9560 case Intrinsic::x86_avx_hadd_ps_256:
9561 case Intrinsic::x86_avx_hadd_pd_256:
9562 return DAG.getNode(X86ISD::FHADD, dl, Op.getValueType(),
9563 Op.getOperand(1), Op.getOperand(2));
9564 case Intrinsic::x86_sse3_hsub_ps:
9565 case Intrinsic::x86_sse3_hsub_pd:
9566 case Intrinsic::x86_avx_hsub_ps_256:
9567 case Intrinsic::x86_avx_hsub_pd_256:
9568 return DAG.getNode(X86ISD::FHSUB, dl, Op.getValueType(),
9569 Op.getOperand(1), Op.getOperand(2));
9570 case Intrinsic::x86_ssse3_phadd_w_128:
9571 case Intrinsic::x86_ssse3_phadd_d_128:
9572 case Intrinsic::x86_avx2_phadd_w:
9573 case Intrinsic::x86_avx2_phadd_d:
9574 return DAG.getNode(X86ISD::HADD, dl, Op.getValueType(),
9575 Op.getOperand(1), Op.getOperand(2));
9576 case Intrinsic::x86_ssse3_phsub_w_128:
9577 case Intrinsic::x86_ssse3_phsub_d_128:
9578 case Intrinsic::x86_avx2_phsub_w:
9579 case Intrinsic::x86_avx2_phsub_d:
9580 return DAG.getNode(X86ISD::HSUB, dl, Op.getValueType(),
9581 Op.getOperand(1), Op.getOperand(2));
9582 case Intrinsic::x86_avx2_psllv_d:
9583 case Intrinsic::x86_avx2_psllv_q:
9584 case Intrinsic::x86_avx2_psllv_d_256:
9585 case Intrinsic::x86_avx2_psllv_q_256:
9586 return DAG.getNode(ISD::SHL, dl, Op.getValueType(),
9587 Op.getOperand(1), Op.getOperand(2));
9588 case Intrinsic::x86_avx2_psrlv_d:
9589 case Intrinsic::x86_avx2_psrlv_q:
9590 case Intrinsic::x86_avx2_psrlv_d_256:
9591 case Intrinsic::x86_avx2_psrlv_q_256:
9592 return DAG.getNode(ISD::SRL, dl, Op.getValueType(),
9593 Op.getOperand(1), Op.getOperand(2));
9594 case Intrinsic::x86_avx2_psrav_d:
9595 case Intrinsic::x86_avx2_psrav_d_256:
9596 return DAG.getNode(ISD::SRA, dl, Op.getValueType(),
9597 Op.getOperand(1), Op.getOperand(2));
9598 case Intrinsic::x86_ssse3_pshuf_b_128:
9599 case Intrinsic::x86_avx2_pshuf_b:
9600 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
9601 Op.getOperand(1), Op.getOperand(2));
9602 case Intrinsic::x86_ssse3_psign_b_128:
9603 case Intrinsic::x86_ssse3_psign_w_128:
9604 case Intrinsic::x86_ssse3_psign_d_128:
9605 case Intrinsic::x86_avx2_psign_b:
9606 case Intrinsic::x86_avx2_psign_w:
9607 case Intrinsic::x86_avx2_psign_d:
9608 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
9609 Op.getOperand(1), Op.getOperand(2));
9610 case Intrinsic::x86_sse41_insertps:
9611 return DAG.getNode(X86ISD::INSERTPS, dl, Op.getValueType(),
9612 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
9613 case Intrinsic::x86_avx_vperm2f128_ps_256:
9614 case Intrinsic::x86_avx_vperm2f128_pd_256:
9615 case Intrinsic::x86_avx_vperm2f128_si_256:
9616 case Intrinsic::x86_avx2_vperm2i128:
9617 return DAG.getNode(X86ISD::VPERM2X128, dl, Op.getValueType(),
9618 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
9619 case Intrinsic::x86_avx2_permd:
9620 case Intrinsic::x86_avx2_permps:
9621 // Operands intentionally swapped. Mask is last operand to intrinsic,
9622 // but second operand for node/intruction.
9623 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
9624 Op.getOperand(2), Op.getOperand(1));
9626 // ptest and testp intrinsics. The intrinsic these come from are designed to
9627 // return an integer value, not just an instruction so lower it to the ptest
9628 // or testp pattern and a setcc for the result.
9629 case Intrinsic::x86_sse41_ptestz:
9630 case Intrinsic::x86_sse41_ptestc:
9631 case Intrinsic::x86_sse41_ptestnzc:
9632 case Intrinsic::x86_avx_ptestz_256:
9633 case Intrinsic::x86_avx_ptestc_256:
9634 case Intrinsic::x86_avx_ptestnzc_256:
9635 case Intrinsic::x86_avx_vtestz_ps:
9636 case Intrinsic::x86_avx_vtestc_ps:
9637 case Intrinsic::x86_avx_vtestnzc_ps:
9638 case Intrinsic::x86_avx_vtestz_pd:
9639 case Intrinsic::x86_avx_vtestc_pd:
9640 case Intrinsic::x86_avx_vtestnzc_pd:
9641 case Intrinsic::x86_avx_vtestz_ps_256:
9642 case Intrinsic::x86_avx_vtestc_ps_256:
9643 case Intrinsic::x86_avx_vtestnzc_ps_256:
9644 case Intrinsic::x86_avx_vtestz_pd_256:
9645 case Intrinsic::x86_avx_vtestc_pd_256:
9646 case Intrinsic::x86_avx_vtestnzc_pd_256: {
9647 bool IsTestPacked = false;
9650 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
9651 case Intrinsic::x86_avx_vtestz_ps:
9652 case Intrinsic::x86_avx_vtestz_pd:
9653 case Intrinsic::x86_avx_vtestz_ps_256:
9654 case Intrinsic::x86_avx_vtestz_pd_256:
9655 IsTestPacked = true; // Fallthrough
9656 case Intrinsic::x86_sse41_ptestz:
9657 case Intrinsic::x86_avx_ptestz_256:
9659 X86CC = X86::COND_E;
9661 case Intrinsic::x86_avx_vtestc_ps:
9662 case Intrinsic::x86_avx_vtestc_pd:
9663 case Intrinsic::x86_avx_vtestc_ps_256:
9664 case Intrinsic::x86_avx_vtestc_pd_256:
9665 IsTestPacked = true; // Fallthrough
9666 case Intrinsic::x86_sse41_ptestc:
9667 case Intrinsic::x86_avx_ptestc_256:
9669 X86CC = X86::COND_B;
9671 case Intrinsic::x86_avx_vtestnzc_ps:
9672 case Intrinsic::x86_avx_vtestnzc_pd:
9673 case Intrinsic::x86_avx_vtestnzc_ps_256:
9674 case Intrinsic::x86_avx_vtestnzc_pd_256:
9675 IsTestPacked = true; // Fallthrough
9676 case Intrinsic::x86_sse41_ptestnzc:
9677 case Intrinsic::x86_avx_ptestnzc_256:
9679 X86CC = X86::COND_A;
9683 SDValue LHS = Op.getOperand(1);
9684 SDValue RHS = Op.getOperand(2);
9685 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
9686 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
9687 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
9688 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
9689 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
9692 // SSE/AVX shift intrinsics
9693 case Intrinsic::x86_sse2_psll_w:
9694 case Intrinsic::x86_sse2_psll_d:
9695 case Intrinsic::x86_sse2_psll_q:
9696 case Intrinsic::x86_avx2_psll_w:
9697 case Intrinsic::x86_avx2_psll_d:
9698 case Intrinsic::x86_avx2_psll_q:
9699 return DAG.getNode(X86ISD::VSHL, dl, Op.getValueType(),
9700 Op.getOperand(1), Op.getOperand(2));
9701 case Intrinsic::x86_sse2_psrl_w:
9702 case Intrinsic::x86_sse2_psrl_d:
9703 case Intrinsic::x86_sse2_psrl_q:
9704 case Intrinsic::x86_avx2_psrl_w:
9705 case Intrinsic::x86_avx2_psrl_d:
9706 case Intrinsic::x86_avx2_psrl_q:
9707 return DAG.getNode(X86ISD::VSRL, dl, Op.getValueType(),
9708 Op.getOperand(1), Op.getOperand(2));
9709 case Intrinsic::x86_sse2_psra_w:
9710 case Intrinsic::x86_sse2_psra_d:
9711 case Intrinsic::x86_avx2_psra_w:
9712 case Intrinsic::x86_avx2_psra_d:
9713 return DAG.getNode(X86ISD::VSRA, dl, Op.getValueType(),
9714 Op.getOperand(1), Op.getOperand(2));
9715 case Intrinsic::x86_sse2_pslli_w:
9716 case Intrinsic::x86_sse2_pslli_d:
9717 case Intrinsic::x86_sse2_pslli_q:
9718 case Intrinsic::x86_avx2_pslli_w:
9719 case Intrinsic::x86_avx2_pslli_d:
9720 case Intrinsic::x86_avx2_pslli_q:
9721 return getTargetVShiftNode(X86ISD::VSHLI, dl, Op.getValueType(),
9722 Op.getOperand(1), Op.getOperand(2), DAG);
9723 case Intrinsic::x86_sse2_psrli_w:
9724 case Intrinsic::x86_sse2_psrli_d:
9725 case Intrinsic::x86_sse2_psrli_q:
9726 case Intrinsic::x86_avx2_psrli_w:
9727 case Intrinsic::x86_avx2_psrli_d:
9728 case Intrinsic::x86_avx2_psrli_q:
9729 return getTargetVShiftNode(X86ISD::VSRLI, dl, Op.getValueType(),
9730 Op.getOperand(1), Op.getOperand(2), DAG);
9731 case Intrinsic::x86_sse2_psrai_w:
9732 case Intrinsic::x86_sse2_psrai_d:
9733 case Intrinsic::x86_avx2_psrai_w:
9734 case Intrinsic::x86_avx2_psrai_d:
9735 return getTargetVShiftNode(X86ISD::VSRAI, dl, Op.getValueType(),
9736 Op.getOperand(1), Op.getOperand(2), DAG);
9737 // Fix vector shift instructions where the last operand is a non-immediate
9739 case Intrinsic::x86_mmx_pslli_w:
9740 case Intrinsic::x86_mmx_pslli_d:
9741 case Intrinsic::x86_mmx_pslli_q:
9742 case Intrinsic::x86_mmx_psrli_w:
9743 case Intrinsic::x86_mmx_psrli_d:
9744 case Intrinsic::x86_mmx_psrli_q:
9745 case Intrinsic::x86_mmx_psrai_w:
9746 case Intrinsic::x86_mmx_psrai_d: {
9747 SDValue ShAmt = Op.getOperand(2);
9748 if (isa<ConstantSDNode>(ShAmt))
9751 unsigned NewIntNo = 0;
9753 case Intrinsic::x86_mmx_pslli_w:
9754 NewIntNo = Intrinsic::x86_mmx_psll_w;
9756 case Intrinsic::x86_mmx_pslli_d:
9757 NewIntNo = Intrinsic::x86_mmx_psll_d;
9759 case Intrinsic::x86_mmx_pslli_q:
9760 NewIntNo = Intrinsic::x86_mmx_psll_q;
9762 case Intrinsic::x86_mmx_psrli_w:
9763 NewIntNo = Intrinsic::x86_mmx_psrl_w;
9765 case Intrinsic::x86_mmx_psrli_d:
9766 NewIntNo = Intrinsic::x86_mmx_psrl_d;
9768 case Intrinsic::x86_mmx_psrli_q:
9769 NewIntNo = Intrinsic::x86_mmx_psrl_q;
9771 case Intrinsic::x86_mmx_psrai_w:
9772 NewIntNo = Intrinsic::x86_mmx_psra_w;
9774 case Intrinsic::x86_mmx_psrai_d:
9775 NewIntNo = Intrinsic::x86_mmx_psra_d;
9777 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
9780 // The vector shift intrinsics with scalars uses 32b shift amounts but
9781 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
9783 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, ShAmt,
9784 DAG.getConstant(0, MVT::i32));
9785 // FIXME this must be lowered to get rid of the invalid type.
9787 EVT VT = Op.getValueType();
9788 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt);
9789 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9790 DAG.getConstant(NewIntNo, MVT::i32),
9791 Op.getOperand(1), ShAmt);
9796 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
9797 SelectionDAG &DAG) const {
9798 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
9799 MFI->setReturnAddressIsTaken(true);
9801 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9802 DebugLoc dl = Op.getDebugLoc();
9805 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
9807 DAG.getConstant(TD->getPointerSize(),
9808 Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
9809 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9810 DAG.getNode(ISD::ADD, dl, getPointerTy(),
9812 MachinePointerInfo(), false, false, false, 0);
9815 // Just load the return address.
9816 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
9817 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9818 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
9821 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
9822 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
9823 MFI->setFrameAddressIsTaken(true);
9825 EVT VT = Op.getValueType();
9826 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
9827 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9828 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
9829 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
9831 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
9832 MachinePointerInfo(),
9833 false, false, false, 0);
9837 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
9838 SelectionDAG &DAG) const {
9839 return DAG.getIntPtrConstant(2*TD->getPointerSize());
9842 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
9843 MachineFunction &MF = DAG.getMachineFunction();
9844 SDValue Chain = Op.getOperand(0);
9845 SDValue Offset = Op.getOperand(1);
9846 SDValue Handler = Op.getOperand(2);
9847 DebugLoc dl = Op.getDebugLoc();
9849 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
9850 Subtarget->is64Bit() ? X86::RBP : X86::EBP,
9852 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
9854 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Frame,
9855 DAG.getIntPtrConstant(TD->getPointerSize()));
9856 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
9857 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
9859 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
9860 MF.getRegInfo().addLiveOut(StoreAddrReg);
9862 return DAG.getNode(X86ISD::EH_RETURN, dl,
9864 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
9867 SDValue X86TargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
9868 SelectionDAG &DAG) const {
9869 return Op.getOperand(0);
9872 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
9873 SelectionDAG &DAG) const {
9874 SDValue Root = Op.getOperand(0);
9875 SDValue Trmp = Op.getOperand(1); // trampoline
9876 SDValue FPtr = Op.getOperand(2); // nested function
9877 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
9878 DebugLoc dl = Op.getDebugLoc();
9880 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
9882 if (Subtarget->is64Bit()) {
9883 SDValue OutChains[6];
9885 // Large code-model.
9886 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
9887 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
9889 const unsigned char N86R10 = X86_MC::getX86RegNum(X86::R10);
9890 const unsigned char N86R11 = X86_MC::getX86RegNum(X86::R11);
9892 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
9894 // Load the pointer to the nested function into R11.
9895 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
9896 SDValue Addr = Trmp;
9897 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9898 Addr, MachinePointerInfo(TrmpAddr),
9901 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9902 DAG.getConstant(2, MVT::i64));
9903 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
9904 MachinePointerInfo(TrmpAddr, 2),
9907 // Load the 'nest' parameter value into R10.
9908 // R10 is specified in X86CallingConv.td
9909 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
9910 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9911 DAG.getConstant(10, MVT::i64));
9912 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9913 Addr, MachinePointerInfo(TrmpAddr, 10),
9916 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9917 DAG.getConstant(12, MVT::i64));
9918 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
9919 MachinePointerInfo(TrmpAddr, 12),
9922 // Jump to the nested function.
9923 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
9924 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9925 DAG.getConstant(20, MVT::i64));
9926 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9927 Addr, MachinePointerInfo(TrmpAddr, 20),
9930 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
9931 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9932 DAG.getConstant(22, MVT::i64));
9933 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
9934 MachinePointerInfo(TrmpAddr, 22),
9937 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6);
9939 const Function *Func =
9940 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
9941 CallingConv::ID CC = Func->getCallingConv();
9946 llvm_unreachable("Unsupported calling convention");
9947 case CallingConv::C:
9948 case CallingConv::X86_StdCall: {
9949 // Pass 'nest' parameter in ECX.
9950 // Must be kept in sync with X86CallingConv.td
9953 // Check that ECX wasn't needed by an 'inreg' parameter.
9954 FunctionType *FTy = Func->getFunctionType();
9955 const AttrListPtr &Attrs = Func->getAttributes();
9957 if (!Attrs.isEmpty() && !Func->isVarArg()) {
9958 unsigned InRegCount = 0;
9961 for (FunctionType::param_iterator I = FTy->param_begin(),
9962 E = FTy->param_end(); I != E; ++I, ++Idx)
9963 if (Attrs.paramHasAttr(Idx, Attribute::InReg))
9964 // FIXME: should only count parameters that are lowered to integers.
9965 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
9967 if (InRegCount > 2) {
9968 report_fatal_error("Nest register in use - reduce number of inreg"
9974 case CallingConv::X86_FastCall:
9975 case CallingConv::X86_ThisCall:
9976 case CallingConv::Fast:
9977 // Pass 'nest' parameter in EAX.
9978 // Must be kept in sync with X86CallingConv.td
9983 SDValue OutChains[4];
9986 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9987 DAG.getConstant(10, MVT::i32));
9988 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
9990 // This is storing the opcode for MOV32ri.
9991 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
9992 const unsigned char N86Reg = X86_MC::getX86RegNum(NestReg);
9993 OutChains[0] = DAG.getStore(Root, dl,
9994 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
9995 Trmp, MachinePointerInfo(TrmpAddr),
9998 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9999 DAG.getConstant(1, MVT::i32));
10000 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
10001 MachinePointerInfo(TrmpAddr, 1),
10004 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
10005 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
10006 DAG.getConstant(5, MVT::i32));
10007 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
10008 MachinePointerInfo(TrmpAddr, 5),
10011 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
10012 DAG.getConstant(6, MVT::i32));
10013 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
10014 MachinePointerInfo(TrmpAddr, 6),
10017 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4);
10021 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
10022 SelectionDAG &DAG) const {
10024 The rounding mode is in bits 11:10 of FPSR, and has the following
10026 00 Round to nearest
10031 FLT_ROUNDS, on the other hand, expects the following:
10038 To perform the conversion, we do:
10039 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
10042 MachineFunction &MF = DAG.getMachineFunction();
10043 const TargetMachine &TM = MF.getTarget();
10044 const TargetFrameLowering &TFI = *TM.getFrameLowering();
10045 unsigned StackAlignment = TFI.getStackAlignment();
10046 EVT VT = Op.getValueType();
10047 DebugLoc DL = Op.getDebugLoc();
10049 // Save FP Control Word to stack slot
10050 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
10051 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
10054 MachineMemOperand *MMO =
10055 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
10056 MachineMemOperand::MOStore, 2, 2);
10058 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
10059 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
10060 DAG.getVTList(MVT::Other),
10061 Ops, 2, MVT::i16, MMO);
10063 // Load FP Control Word from stack slot
10064 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
10065 MachinePointerInfo(), false, false, false, 0);
10067 // Transform as necessary
10069 DAG.getNode(ISD::SRL, DL, MVT::i16,
10070 DAG.getNode(ISD::AND, DL, MVT::i16,
10071 CWD, DAG.getConstant(0x800, MVT::i16)),
10072 DAG.getConstant(11, MVT::i8));
10074 DAG.getNode(ISD::SRL, DL, MVT::i16,
10075 DAG.getNode(ISD::AND, DL, MVT::i16,
10076 CWD, DAG.getConstant(0x400, MVT::i16)),
10077 DAG.getConstant(9, MVT::i8));
10080 DAG.getNode(ISD::AND, DL, MVT::i16,
10081 DAG.getNode(ISD::ADD, DL, MVT::i16,
10082 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
10083 DAG.getConstant(1, MVT::i16)),
10084 DAG.getConstant(3, MVT::i16));
10087 return DAG.getNode((VT.getSizeInBits() < 16 ?
10088 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
10091 SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const {
10092 EVT VT = Op.getValueType();
10094 unsigned NumBits = VT.getSizeInBits();
10095 DebugLoc dl = Op.getDebugLoc();
10097 Op = Op.getOperand(0);
10098 if (VT == MVT::i8) {
10099 // Zero extend to i32 since there is not an i8 bsr.
10101 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
10104 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
10105 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
10106 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
10108 // If src is zero (i.e. bsr sets ZF), returns NumBits.
10111 DAG.getConstant(NumBits+NumBits-1, OpVT),
10112 DAG.getConstant(X86::COND_E, MVT::i8),
10115 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
10117 // Finally xor with NumBits-1.
10118 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
10121 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
10125 SDValue X86TargetLowering::LowerCTLZ_ZERO_UNDEF(SDValue Op,
10126 SelectionDAG &DAG) const {
10127 EVT VT = Op.getValueType();
10129 unsigned NumBits = VT.getSizeInBits();
10130 DebugLoc dl = Op.getDebugLoc();
10132 Op = Op.getOperand(0);
10133 if (VT == MVT::i8) {
10134 // Zero extend to i32 since there is not an i8 bsr.
10136 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
10139 // Issue a bsr (scan bits in reverse).
10140 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
10141 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
10143 // And xor with NumBits-1.
10144 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
10147 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
10151 SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) const {
10152 EVT VT = Op.getValueType();
10153 unsigned NumBits = VT.getSizeInBits();
10154 DebugLoc dl = Op.getDebugLoc();
10155 Op = Op.getOperand(0);
10157 // Issue a bsf (scan bits forward) which also sets EFLAGS.
10158 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
10159 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
10161 // If src is zero (i.e. bsf sets ZF), returns NumBits.
10164 DAG.getConstant(NumBits, VT),
10165 DAG.getConstant(X86::COND_E, MVT::i8),
10168 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops, array_lengthof(Ops));
10171 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
10172 // ones, and then concatenate the result back.
10173 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
10174 EVT VT = Op.getValueType();
10176 assert(VT.getSizeInBits() == 256 && VT.isInteger() &&
10177 "Unsupported value type for operation");
10179 unsigned NumElems = VT.getVectorNumElements();
10180 DebugLoc dl = Op.getDebugLoc();
10182 // Extract the LHS vectors
10183 SDValue LHS = Op.getOperand(0);
10184 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
10185 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
10187 // Extract the RHS vectors
10188 SDValue RHS = Op.getOperand(1);
10189 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
10190 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
10192 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10193 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
10195 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
10196 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
10197 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
10200 SDValue X86TargetLowering::LowerADD(SDValue Op, SelectionDAG &DAG) const {
10201 assert(Op.getValueType().getSizeInBits() == 256 &&
10202 Op.getValueType().isInteger() &&
10203 "Only handle AVX 256-bit vector integer operation");
10204 return Lower256IntArith(Op, DAG);
10207 SDValue X86TargetLowering::LowerSUB(SDValue Op, SelectionDAG &DAG) const {
10208 assert(Op.getValueType().getSizeInBits() == 256 &&
10209 Op.getValueType().isInteger() &&
10210 "Only handle AVX 256-bit vector integer operation");
10211 return Lower256IntArith(Op, DAG);
10214 SDValue X86TargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
10215 EVT VT = Op.getValueType();
10217 // Decompose 256-bit ops into smaller 128-bit ops.
10218 if (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2())
10219 return Lower256IntArith(Op, DAG);
10221 assert((VT == MVT::v2i64 || VT == MVT::v4i64) &&
10222 "Only know how to lower V2I64/V4I64 multiply");
10224 DebugLoc dl = Op.getDebugLoc();
10226 // Ahi = psrlqi(a, 32);
10227 // Bhi = psrlqi(b, 32);
10229 // AloBlo = pmuludq(a, b);
10230 // AloBhi = pmuludq(a, Bhi);
10231 // AhiBlo = pmuludq(Ahi, b);
10233 // AloBhi = psllqi(AloBhi, 32);
10234 // AhiBlo = psllqi(AhiBlo, 32);
10235 // return AloBlo + AloBhi + AhiBlo;
10237 SDValue A = Op.getOperand(0);
10238 SDValue B = Op.getOperand(1);
10240 SDValue ShAmt = DAG.getConstant(32, MVT::i32);
10242 SDValue Ahi = DAG.getNode(X86ISD::VSRLI, dl, VT, A, ShAmt);
10243 SDValue Bhi = DAG.getNode(X86ISD::VSRLI, dl, VT, B, ShAmt);
10245 // Bit cast to 32-bit vectors for MULUDQ
10246 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 : MVT::v8i32;
10247 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
10248 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
10249 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
10250 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
10252 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
10253 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
10254 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
10256 AloBhi = DAG.getNode(X86ISD::VSHLI, dl, VT, AloBhi, ShAmt);
10257 AhiBlo = DAG.getNode(X86ISD::VSHLI, dl, VT, AhiBlo, ShAmt);
10259 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
10260 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
10263 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const {
10265 EVT VT = Op.getValueType();
10266 DebugLoc dl = Op.getDebugLoc();
10267 SDValue R = Op.getOperand(0);
10268 SDValue Amt = Op.getOperand(1);
10269 LLVMContext *Context = DAG.getContext();
10271 if (!Subtarget->hasSSE2())
10274 // Optimize shl/srl/sra with constant shift amount.
10275 if (isSplatVector(Amt.getNode())) {
10276 SDValue SclrAmt = Amt->getOperand(0);
10277 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
10278 uint64_t ShiftAmt = C->getZExtValue();
10280 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
10281 (Subtarget->hasAVX2() &&
10282 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16))) {
10283 if (Op.getOpcode() == ISD::SHL)
10284 return DAG.getNode(X86ISD::VSHLI, dl, VT, R,
10285 DAG.getConstant(ShiftAmt, MVT::i32));
10286 if (Op.getOpcode() == ISD::SRL)
10287 return DAG.getNode(X86ISD::VSRLI, dl, VT, R,
10288 DAG.getConstant(ShiftAmt, MVT::i32));
10289 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
10290 return DAG.getNode(X86ISD::VSRAI, dl, VT, R,
10291 DAG.getConstant(ShiftAmt, MVT::i32));
10294 if (VT == MVT::v16i8) {
10295 if (Op.getOpcode() == ISD::SHL) {
10296 // Make a large shift.
10297 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, R,
10298 DAG.getConstant(ShiftAmt, MVT::i32));
10299 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
10300 // Zero out the rightmost bits.
10301 SmallVector<SDValue, 16> V(16,
10302 DAG.getConstant(uint8_t(-1U << ShiftAmt),
10304 return DAG.getNode(ISD::AND, dl, VT, SHL,
10305 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
10307 if (Op.getOpcode() == ISD::SRL) {
10308 // Make a large shift.
10309 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v8i16, R,
10310 DAG.getConstant(ShiftAmt, MVT::i32));
10311 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
10312 // Zero out the leftmost bits.
10313 SmallVector<SDValue, 16> V(16,
10314 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
10316 return DAG.getNode(ISD::AND, dl, VT, SRL,
10317 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
10319 if (Op.getOpcode() == ISD::SRA) {
10320 if (ShiftAmt == 7) {
10321 // R s>> 7 === R s< 0
10322 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
10323 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
10326 // R s>> a === ((R u>> a) ^ m) - m
10327 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
10328 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
10330 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16);
10331 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
10332 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
10335 llvm_unreachable("Unknown shift opcode.");
10338 if (Subtarget->hasAVX2() && VT == MVT::v32i8) {
10339 if (Op.getOpcode() == ISD::SHL) {
10340 // Make a large shift.
10341 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v16i16, R,
10342 DAG.getConstant(ShiftAmt, MVT::i32));
10343 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
10344 // Zero out the rightmost bits.
10345 SmallVector<SDValue, 32> V(32,
10346 DAG.getConstant(uint8_t(-1U << ShiftAmt),
10348 return DAG.getNode(ISD::AND, dl, VT, SHL,
10349 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
10351 if (Op.getOpcode() == ISD::SRL) {
10352 // Make a large shift.
10353 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v16i16, R,
10354 DAG.getConstant(ShiftAmt, MVT::i32));
10355 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
10356 // Zero out the leftmost bits.
10357 SmallVector<SDValue, 32> V(32,
10358 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
10360 return DAG.getNode(ISD::AND, dl, VT, SRL,
10361 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
10363 if (Op.getOpcode() == ISD::SRA) {
10364 if (ShiftAmt == 7) {
10365 // R s>> 7 === R s< 0
10366 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
10367 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
10370 // R s>> a === ((R u>> a) ^ m) - m
10371 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
10372 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
10374 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32);
10375 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
10376 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
10379 llvm_unreachable("Unknown shift opcode.");
10384 // Lower SHL with variable shift amount.
10385 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
10386 Op = DAG.getNode(X86ISD::VSHLI, dl, VT, Op.getOperand(1),
10387 DAG.getConstant(23, MVT::i32));
10389 const uint32_t CV[] = { 0x3f800000U, 0x3f800000U, 0x3f800000U, 0x3f800000U};
10390 Constant *C = ConstantDataVector::get(*Context, CV);
10391 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
10392 SDValue Addend = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
10393 MachinePointerInfo::getConstantPool(),
10394 false, false, false, 16);
10396 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Addend);
10397 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
10398 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
10399 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
10401 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
10402 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
10405 Op = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, Op.getOperand(1),
10406 DAG.getConstant(5, MVT::i32));
10407 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
10409 // Turn 'a' into a mask suitable for VSELECT
10410 SDValue VSelM = DAG.getConstant(0x80, VT);
10411 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
10412 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
10414 SDValue CM1 = DAG.getConstant(0x0f, VT);
10415 SDValue CM2 = DAG.getConstant(0x3f, VT);
10417 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
10418 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
10419 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M,
10420 DAG.getConstant(4, MVT::i32), DAG);
10421 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
10422 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
10425 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
10426 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
10427 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
10429 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
10430 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
10431 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M,
10432 DAG.getConstant(2, MVT::i32), DAG);
10433 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
10434 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
10437 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
10438 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
10439 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
10441 // return VSELECT(r, r+r, a);
10442 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
10443 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
10447 // Decompose 256-bit shifts into smaller 128-bit shifts.
10448 if (VT.getSizeInBits() == 256) {
10449 unsigned NumElems = VT.getVectorNumElements();
10450 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10451 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
10453 // Extract the two vectors
10454 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
10455 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
10457 // Recreate the shift amount vectors
10458 SDValue Amt1, Amt2;
10459 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
10460 // Constant shift amount
10461 SmallVector<SDValue, 4> Amt1Csts;
10462 SmallVector<SDValue, 4> Amt2Csts;
10463 for (unsigned i = 0; i != NumElems/2; ++i)
10464 Amt1Csts.push_back(Amt->getOperand(i));
10465 for (unsigned i = NumElems/2; i != NumElems; ++i)
10466 Amt2Csts.push_back(Amt->getOperand(i));
10468 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
10469 &Amt1Csts[0], NumElems/2);
10470 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
10471 &Amt2Csts[0], NumElems/2);
10473 // Variable shift amount
10474 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
10475 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
10478 // Issue new vector shifts for the smaller types
10479 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
10480 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
10482 // Concatenate the result back
10483 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
10489 SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const {
10490 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
10491 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
10492 // looks for this combo and may remove the "setcc" instruction if the "setcc"
10493 // has only one use.
10494 SDNode *N = Op.getNode();
10495 SDValue LHS = N->getOperand(0);
10496 SDValue RHS = N->getOperand(1);
10497 unsigned BaseOp = 0;
10499 DebugLoc DL = Op.getDebugLoc();
10500 switch (Op.getOpcode()) {
10501 default: llvm_unreachable("Unknown ovf instruction!");
10503 // A subtract of one will be selected as a INC. Note that INC doesn't
10504 // set CF, so we can't do this for UADDO.
10505 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
10507 BaseOp = X86ISD::INC;
10508 Cond = X86::COND_O;
10511 BaseOp = X86ISD::ADD;
10512 Cond = X86::COND_O;
10515 BaseOp = X86ISD::ADD;
10516 Cond = X86::COND_B;
10519 // A subtract of one will be selected as a DEC. Note that DEC doesn't
10520 // set CF, so we can't do this for USUBO.
10521 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
10523 BaseOp = X86ISD::DEC;
10524 Cond = X86::COND_O;
10527 BaseOp = X86ISD::SUB;
10528 Cond = X86::COND_O;
10531 BaseOp = X86ISD::SUB;
10532 Cond = X86::COND_B;
10535 BaseOp = X86ISD::SMUL;
10536 Cond = X86::COND_O;
10538 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
10539 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
10541 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
10544 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
10545 DAG.getConstant(X86::COND_O, MVT::i32),
10546 SDValue(Sum.getNode(), 2));
10548 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
10552 // Also sets EFLAGS.
10553 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
10554 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
10557 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
10558 DAG.getConstant(Cond, MVT::i32),
10559 SDValue(Sum.getNode(), 1));
10561 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
10564 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
10565 SelectionDAG &DAG) const {
10566 DebugLoc dl = Op.getDebugLoc();
10567 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
10568 EVT VT = Op.getValueType();
10570 if (!Subtarget->hasSSE2() || !VT.isVector())
10573 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
10574 ExtraVT.getScalarType().getSizeInBits();
10575 SDValue ShAmt = DAG.getConstant(BitsDiff, MVT::i32);
10577 switch (VT.getSimpleVT().SimpleTy) {
10578 default: return SDValue();
10581 if (!Subtarget->hasAVX())
10583 if (!Subtarget->hasAVX2()) {
10584 // needs to be split
10585 unsigned NumElems = VT.getVectorNumElements();
10587 // Extract the LHS vectors
10588 SDValue LHS = Op.getOperand(0);
10589 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
10590 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
10592 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10593 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
10595 EVT ExtraEltVT = ExtraVT.getVectorElementType();
10596 int ExtraNumElems = ExtraVT.getVectorNumElements();
10597 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
10599 SDValue Extra = DAG.getValueType(ExtraVT);
10601 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
10602 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
10604 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);;
10609 SDValue Tmp1 = getTargetVShiftNode(X86ISD::VSHLI, dl, VT,
10610 Op.getOperand(0), ShAmt, DAG);
10611 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, Tmp1, ShAmt, DAG);
10617 SDValue X86TargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const{
10618 DebugLoc dl = Op.getDebugLoc();
10620 // Go ahead and emit the fence on x86-64 even if we asked for no-sse2.
10621 // There isn't any reason to disable it if the target processor supports it.
10622 if (!Subtarget->hasSSE2() && !Subtarget->is64Bit()) {
10623 SDValue Chain = Op.getOperand(0);
10624 SDValue Zero = DAG.getConstant(0, MVT::i32);
10626 DAG.getRegister(X86::ESP, MVT::i32), // Base
10627 DAG.getTargetConstant(1, MVT::i8), // Scale
10628 DAG.getRegister(0, MVT::i32), // Index
10629 DAG.getTargetConstant(0, MVT::i32), // Disp
10630 DAG.getRegister(0, MVT::i32), // Segment.
10635 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
10636 array_lengthof(Ops));
10637 return SDValue(Res, 0);
10640 unsigned isDev = cast<ConstantSDNode>(Op.getOperand(5))->getZExtValue();
10642 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
10644 unsigned Op1 = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10645 unsigned Op2 = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
10646 unsigned Op3 = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
10647 unsigned Op4 = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
10649 // def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
10650 if (!Op1 && !Op2 && !Op3 && Op4)
10651 return DAG.getNode(X86ISD::SFENCE, dl, MVT::Other, Op.getOperand(0));
10653 // def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
10654 if (Op1 && !Op2 && !Op3 && !Op4)
10655 return DAG.getNode(X86ISD::LFENCE, dl, MVT::Other, Op.getOperand(0));
10657 // def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm), (i8 1)),
10659 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
10662 SDValue X86TargetLowering::LowerATOMIC_FENCE(SDValue Op,
10663 SelectionDAG &DAG) const {
10664 DebugLoc dl = Op.getDebugLoc();
10665 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
10666 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
10667 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
10668 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
10670 // The only fence that needs an instruction is a sequentially-consistent
10671 // cross-thread fence.
10672 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
10673 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
10674 // no-sse2). There isn't any reason to disable it if the target processor
10676 if (Subtarget->hasSSE2() || Subtarget->is64Bit())
10677 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
10679 SDValue Chain = Op.getOperand(0);
10680 SDValue Zero = DAG.getConstant(0, MVT::i32);
10682 DAG.getRegister(X86::ESP, MVT::i32), // Base
10683 DAG.getTargetConstant(1, MVT::i8), // Scale
10684 DAG.getRegister(0, MVT::i32), // Index
10685 DAG.getTargetConstant(0, MVT::i32), // Disp
10686 DAG.getRegister(0, MVT::i32), // Segment.
10691 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
10692 array_lengthof(Ops));
10693 return SDValue(Res, 0);
10696 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
10697 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
10701 SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const {
10702 EVT T = Op.getValueType();
10703 DebugLoc DL = Op.getDebugLoc();
10706 switch(T.getSimpleVT().SimpleTy) {
10707 default: llvm_unreachable("Invalid value type!");
10708 case MVT::i8: Reg = X86::AL; size = 1; break;
10709 case MVT::i16: Reg = X86::AX; size = 2; break;
10710 case MVT::i32: Reg = X86::EAX; size = 4; break;
10712 assert(Subtarget->is64Bit() && "Node not type legal!");
10713 Reg = X86::RAX; size = 8;
10716 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
10717 Op.getOperand(2), SDValue());
10718 SDValue Ops[] = { cpIn.getValue(0),
10721 DAG.getTargetConstant(size, MVT::i8),
10722 cpIn.getValue(1) };
10723 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10724 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
10725 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
10728 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
10732 SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
10733 SelectionDAG &DAG) const {
10734 assert(Subtarget->is64Bit() && "Result not type legalized?");
10735 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10736 SDValue TheChain = Op.getOperand(0);
10737 DebugLoc dl = Op.getDebugLoc();
10738 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
10739 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
10740 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
10742 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
10743 DAG.getConstant(32, MVT::i8));
10745 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
10748 return DAG.getMergeValues(Ops, 2, dl);
10751 SDValue X86TargetLowering::LowerBITCAST(SDValue Op,
10752 SelectionDAG &DAG) const {
10753 EVT SrcVT = Op.getOperand(0).getValueType();
10754 EVT DstVT = Op.getValueType();
10755 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
10756 Subtarget->hasMMX() && "Unexpected custom BITCAST");
10757 assert((DstVT == MVT::i64 ||
10758 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
10759 "Unexpected custom BITCAST");
10760 // i64 <=> MMX conversions are Legal.
10761 if (SrcVT==MVT::i64 && DstVT.isVector())
10763 if (DstVT==MVT::i64 && SrcVT.isVector())
10765 // MMX <=> MMX conversions are Legal.
10766 if (SrcVT.isVector() && DstVT.isVector())
10768 // All other conversions need to be expanded.
10772 SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const {
10773 SDNode *Node = Op.getNode();
10774 DebugLoc dl = Node->getDebugLoc();
10775 EVT T = Node->getValueType(0);
10776 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
10777 DAG.getConstant(0, T), Node->getOperand(2));
10778 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
10779 cast<AtomicSDNode>(Node)->getMemoryVT(),
10780 Node->getOperand(0),
10781 Node->getOperand(1), negOp,
10782 cast<AtomicSDNode>(Node)->getSrcValue(),
10783 cast<AtomicSDNode>(Node)->getAlignment(),
10784 cast<AtomicSDNode>(Node)->getOrdering(),
10785 cast<AtomicSDNode>(Node)->getSynchScope());
10788 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
10789 SDNode *Node = Op.getNode();
10790 DebugLoc dl = Node->getDebugLoc();
10791 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
10793 // Convert seq_cst store -> xchg
10794 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
10795 // FIXME: On 32-bit, store -> fist or movq would be more efficient
10796 // (The only way to get a 16-byte store is cmpxchg16b)
10797 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
10798 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
10799 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
10800 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
10801 cast<AtomicSDNode>(Node)->getMemoryVT(),
10802 Node->getOperand(0),
10803 Node->getOperand(1), Node->getOperand(2),
10804 cast<AtomicSDNode>(Node)->getMemOperand(),
10805 cast<AtomicSDNode>(Node)->getOrdering(),
10806 cast<AtomicSDNode>(Node)->getSynchScope());
10807 return Swap.getValue(1);
10809 // Other atomic stores have a simple pattern.
10813 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
10814 EVT VT = Op.getNode()->getValueType(0);
10816 // Let legalize expand this if it isn't a legal type yet.
10817 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
10820 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
10823 bool ExtraOp = false;
10824 switch (Op.getOpcode()) {
10825 default: llvm_unreachable("Invalid code");
10826 case ISD::ADDC: Opc = X86ISD::ADD; break;
10827 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
10828 case ISD::SUBC: Opc = X86ISD::SUB; break;
10829 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
10833 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
10835 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
10836 Op.getOperand(1), Op.getOperand(2));
10839 /// LowerOperation - Provide custom lowering hooks for some operations.
10841 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
10842 switch (Op.getOpcode()) {
10843 default: llvm_unreachable("Should not custom lower this!");
10844 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
10845 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op,DAG);
10846 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op,DAG);
10847 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG);
10848 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
10849 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
10850 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
10851 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
10852 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
10853 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
10854 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
10855 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
10856 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, DAG);
10857 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
10858 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
10859 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
10860 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
10861 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
10862 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
10863 case ISD::SHL_PARTS:
10864 case ISD::SRA_PARTS:
10865 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
10866 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
10867 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
10868 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
10869 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
10870 case ISD::FABS: return LowerFABS(Op, DAG);
10871 case ISD::FNEG: return LowerFNEG(Op, DAG);
10872 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
10873 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
10874 case ISD::SETCC: return LowerSETCC(Op, DAG);
10875 case ISD::SELECT: return LowerSELECT(Op, DAG);
10876 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
10877 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
10878 case ISD::VASTART: return LowerVASTART(Op, DAG);
10879 case ISD::VAARG: return LowerVAARG(Op, DAG);
10880 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
10881 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
10882 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
10883 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
10884 case ISD::FRAME_TO_ARGS_OFFSET:
10885 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
10886 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
10887 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
10888 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
10889 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
10890 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
10891 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
10892 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
10893 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
10894 case ISD::MUL: return LowerMUL(Op, DAG);
10897 case ISD::SHL: return LowerShift(Op, DAG);
10903 case ISD::UMULO: return LowerXALUO(Op, DAG);
10904 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
10905 case ISD::BITCAST: return LowerBITCAST(Op, DAG);
10909 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
10910 case ISD::ADD: return LowerADD(Op, DAG);
10911 case ISD::SUB: return LowerSUB(Op, DAG);
10915 static void ReplaceATOMIC_LOAD(SDNode *Node,
10916 SmallVectorImpl<SDValue> &Results,
10917 SelectionDAG &DAG) {
10918 DebugLoc dl = Node->getDebugLoc();
10919 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
10921 // Convert wide load -> cmpxchg8b/cmpxchg16b
10922 // FIXME: On 32-bit, load -> fild or movq would be more efficient
10923 // (The only way to get a 16-byte load is cmpxchg16b)
10924 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment.
10925 SDValue Zero = DAG.getConstant(0, VT);
10926 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT,
10927 Node->getOperand(0),
10928 Node->getOperand(1), Zero, Zero,
10929 cast<AtomicSDNode>(Node)->getMemOperand(),
10930 cast<AtomicSDNode>(Node)->getOrdering(),
10931 cast<AtomicSDNode>(Node)->getSynchScope());
10932 Results.push_back(Swap.getValue(0));
10933 Results.push_back(Swap.getValue(1));
10936 void X86TargetLowering::
10937 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
10938 SelectionDAG &DAG, unsigned NewOp) const {
10939 DebugLoc dl = Node->getDebugLoc();
10940 assert (Node->getValueType(0) == MVT::i64 &&
10941 "Only know how to expand i64 atomics");
10943 SDValue Chain = Node->getOperand(0);
10944 SDValue In1 = Node->getOperand(1);
10945 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
10946 Node->getOperand(2), DAG.getIntPtrConstant(0));
10947 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
10948 Node->getOperand(2), DAG.getIntPtrConstant(1));
10949 SDValue Ops[] = { Chain, In1, In2L, In2H };
10950 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
10952 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64,
10953 cast<MemSDNode>(Node)->getMemOperand());
10954 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
10955 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
10956 Results.push_back(Result.getValue(2));
10959 /// ReplaceNodeResults - Replace a node with an illegal result type
10960 /// with a new node built out of custom code.
10961 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
10962 SmallVectorImpl<SDValue>&Results,
10963 SelectionDAG &DAG) const {
10964 DebugLoc dl = N->getDebugLoc();
10965 switch (N->getOpcode()) {
10967 llvm_unreachable("Do not know how to custom type legalize this operation!");
10968 case ISD::SIGN_EXTEND_INREG:
10973 // We don't want to expand or promote these.
10975 case ISD::FP_TO_SINT:
10976 case ISD::FP_TO_UINT: {
10977 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
10979 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
10982 std::pair<SDValue,SDValue> Vals =
10983 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
10984 SDValue FIST = Vals.first, StackSlot = Vals.second;
10985 if (FIST.getNode() != 0) {
10986 EVT VT = N->getValueType(0);
10987 // Return a load from the stack slot.
10988 if (StackSlot.getNode() != 0)
10989 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
10990 MachinePointerInfo(),
10991 false, false, false, 0));
10993 Results.push_back(FIST);
10997 case ISD::READCYCLECOUNTER: {
10998 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10999 SDValue TheChain = N->getOperand(0);
11000 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
11001 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
11003 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
11005 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
11006 SDValue Ops[] = { eax, edx };
11007 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
11008 Results.push_back(edx.getValue(1));
11011 case ISD::ATOMIC_CMP_SWAP: {
11012 EVT T = N->getValueType(0);
11013 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
11014 bool Regs64bit = T == MVT::i128;
11015 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
11016 SDValue cpInL, cpInH;
11017 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
11018 DAG.getConstant(0, HalfT));
11019 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
11020 DAG.getConstant(1, HalfT));
11021 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
11022 Regs64bit ? X86::RAX : X86::EAX,
11024 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
11025 Regs64bit ? X86::RDX : X86::EDX,
11026 cpInH, cpInL.getValue(1));
11027 SDValue swapInL, swapInH;
11028 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
11029 DAG.getConstant(0, HalfT));
11030 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
11031 DAG.getConstant(1, HalfT));
11032 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
11033 Regs64bit ? X86::RBX : X86::EBX,
11034 swapInL, cpInH.getValue(1));
11035 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
11036 Regs64bit ? X86::RCX : X86::ECX,
11037 swapInH, swapInL.getValue(1));
11038 SDValue Ops[] = { swapInH.getValue(0),
11040 swapInH.getValue(1) };
11041 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
11042 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
11043 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
11044 X86ISD::LCMPXCHG8_DAG;
11045 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys,
11047 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
11048 Regs64bit ? X86::RAX : X86::EAX,
11049 HalfT, Result.getValue(1));
11050 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
11051 Regs64bit ? X86::RDX : X86::EDX,
11052 HalfT, cpOutL.getValue(2));
11053 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
11054 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF, 2));
11055 Results.push_back(cpOutH.getValue(1));
11058 case ISD::ATOMIC_LOAD_ADD:
11059 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG);
11061 case ISD::ATOMIC_LOAD_AND:
11062 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG);
11064 case ISD::ATOMIC_LOAD_NAND:
11065 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG);
11067 case ISD::ATOMIC_LOAD_OR:
11068 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG);
11070 case ISD::ATOMIC_LOAD_SUB:
11071 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG);
11073 case ISD::ATOMIC_LOAD_XOR:
11074 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG);
11076 case ISD::ATOMIC_SWAP:
11077 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG);
11079 case ISD::ATOMIC_LOAD:
11080 ReplaceATOMIC_LOAD(N, Results, DAG);
11084 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
11086 default: return NULL;
11087 case X86ISD::BSF: return "X86ISD::BSF";
11088 case X86ISD::BSR: return "X86ISD::BSR";
11089 case X86ISD::SHLD: return "X86ISD::SHLD";
11090 case X86ISD::SHRD: return "X86ISD::SHRD";
11091 case X86ISD::FAND: return "X86ISD::FAND";
11092 case X86ISD::FOR: return "X86ISD::FOR";
11093 case X86ISD::FXOR: return "X86ISD::FXOR";
11094 case X86ISD::FSRL: return "X86ISD::FSRL";
11095 case X86ISD::FILD: return "X86ISD::FILD";
11096 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
11097 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
11098 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
11099 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
11100 case X86ISD::FLD: return "X86ISD::FLD";
11101 case X86ISD::FST: return "X86ISD::FST";
11102 case X86ISD::CALL: return "X86ISD::CALL";
11103 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
11104 case X86ISD::BT: return "X86ISD::BT";
11105 case X86ISD::CMP: return "X86ISD::CMP";
11106 case X86ISD::COMI: return "X86ISD::COMI";
11107 case X86ISD::UCOMI: return "X86ISD::UCOMI";
11108 case X86ISD::SETCC: return "X86ISD::SETCC";
11109 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
11110 case X86ISD::FSETCCsd: return "X86ISD::FSETCCsd";
11111 case X86ISD::FSETCCss: return "X86ISD::FSETCCss";
11112 case X86ISD::CMOV: return "X86ISD::CMOV";
11113 case X86ISD::BRCOND: return "X86ISD::BRCOND";
11114 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
11115 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
11116 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
11117 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
11118 case X86ISD::Wrapper: return "X86ISD::Wrapper";
11119 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
11120 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
11121 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
11122 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
11123 case X86ISD::PINSRB: return "X86ISD::PINSRB";
11124 case X86ISD::PINSRW: return "X86ISD::PINSRW";
11125 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
11126 case X86ISD::ANDNP: return "X86ISD::ANDNP";
11127 case X86ISD::PSIGN: return "X86ISD::PSIGN";
11128 case X86ISD::BLENDV: return "X86ISD::BLENDV";
11129 case X86ISD::BLENDPW: return "X86ISD::BLENDPW";
11130 case X86ISD::BLENDPS: return "X86ISD::BLENDPS";
11131 case X86ISD::BLENDPD: return "X86ISD::BLENDPD";
11132 case X86ISD::HADD: return "X86ISD::HADD";
11133 case X86ISD::HSUB: return "X86ISD::HSUB";
11134 case X86ISD::FHADD: return "X86ISD::FHADD";
11135 case X86ISD::FHSUB: return "X86ISD::FHSUB";
11136 case X86ISD::FMAX: return "X86ISD::FMAX";
11137 case X86ISD::FMIN: return "X86ISD::FMIN";
11138 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
11139 case X86ISD::FRCP: return "X86ISD::FRCP";
11140 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
11141 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
11142 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
11143 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
11144 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
11145 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
11146 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
11147 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
11148 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
11149 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
11150 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
11151 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
11152 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
11153 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
11154 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
11155 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
11156 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
11157 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
11158 case X86ISD::VSHL: return "X86ISD::VSHL";
11159 case X86ISD::VSRL: return "X86ISD::VSRL";
11160 case X86ISD::VSRA: return "X86ISD::VSRA";
11161 case X86ISD::VSHLI: return "X86ISD::VSHLI";
11162 case X86ISD::VSRLI: return "X86ISD::VSRLI";
11163 case X86ISD::VSRAI: return "X86ISD::VSRAI";
11164 case X86ISD::CMPP: return "X86ISD::CMPP";
11165 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
11166 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
11167 case X86ISD::ADD: return "X86ISD::ADD";
11168 case X86ISD::SUB: return "X86ISD::SUB";
11169 case X86ISD::ADC: return "X86ISD::ADC";
11170 case X86ISD::SBB: return "X86ISD::SBB";
11171 case X86ISD::SMUL: return "X86ISD::SMUL";
11172 case X86ISD::UMUL: return "X86ISD::UMUL";
11173 case X86ISD::INC: return "X86ISD::INC";
11174 case X86ISD::DEC: return "X86ISD::DEC";
11175 case X86ISD::OR: return "X86ISD::OR";
11176 case X86ISD::XOR: return "X86ISD::XOR";
11177 case X86ISD::AND: return "X86ISD::AND";
11178 case X86ISD::ANDN: return "X86ISD::ANDN";
11179 case X86ISD::BLSI: return "X86ISD::BLSI";
11180 case X86ISD::BLSMSK: return "X86ISD::BLSMSK";
11181 case X86ISD::BLSR: return "X86ISD::BLSR";
11182 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
11183 case X86ISD::PTEST: return "X86ISD::PTEST";
11184 case X86ISD::TESTP: return "X86ISD::TESTP";
11185 case X86ISD::PALIGN: return "X86ISD::PALIGN";
11186 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
11187 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
11188 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
11189 case X86ISD::SHUFP: return "X86ISD::SHUFP";
11190 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
11191 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
11192 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
11193 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
11194 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
11195 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
11196 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
11197 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
11198 case X86ISD::MOVSD: return "X86ISD::MOVSD";
11199 case X86ISD::MOVSS: return "X86ISD::MOVSS";
11200 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
11201 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
11202 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
11203 case X86ISD::VPERMILP: return "X86ISD::VPERMILP";
11204 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
11205 case X86ISD::VPERMV: return "X86ISD::VPERMV";
11206 case X86ISD::VPERMI: return "X86ISD::VPERMI";
11207 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
11208 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
11209 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
11210 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
11211 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
11212 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
11213 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
11214 case X86ISD::SAHF: return "X86ISD::SAHF";
11218 // isLegalAddressingMode - Return true if the addressing mode represented
11219 // by AM is legal for this target, for a load/store of the specified type.
11220 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
11222 // X86 supports extremely general addressing modes.
11223 CodeModel::Model M = getTargetMachine().getCodeModel();
11224 Reloc::Model R = getTargetMachine().getRelocationModel();
11226 // X86 allows a sign-extended 32-bit immediate field as a displacement.
11227 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
11232 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
11234 // If a reference to this global requires an extra load, we can't fold it.
11235 if (isGlobalStubReference(GVFlags))
11238 // If BaseGV requires a register for the PIC base, we cannot also have a
11239 // BaseReg specified.
11240 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
11243 // If lower 4G is not available, then we must use rip-relative addressing.
11244 if ((M != CodeModel::Small || R != Reloc::Static) &&
11245 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
11249 switch (AM.Scale) {
11255 // These scales always work.
11260 // These scales are formed with basereg+scalereg. Only accept if there is
11265 default: // Other stuff never works.
11273 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
11274 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
11276 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
11277 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
11278 if (NumBits1 <= NumBits2)
11283 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
11284 if (!VT1.isInteger() || !VT2.isInteger())
11286 unsigned NumBits1 = VT1.getSizeInBits();
11287 unsigned NumBits2 = VT2.getSizeInBits();
11288 if (NumBits1 <= NumBits2)
11293 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
11294 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
11295 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
11298 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
11299 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
11300 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
11303 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
11304 // i16 instructions are longer (0x66 prefix) and potentially slower.
11305 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
11308 /// isShuffleMaskLegal - Targets can use this to indicate that they only
11309 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
11310 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
11311 /// are assumed to be legal.
11313 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
11315 // Very little shuffling can be done for 64-bit vectors right now.
11316 if (VT.getSizeInBits() == 64)
11319 // FIXME: pshufb, blends, shifts.
11320 return (VT.getVectorNumElements() == 2 ||
11321 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
11322 isMOVLMask(M, VT) ||
11323 isSHUFPMask(M, VT, Subtarget->hasAVX()) ||
11324 isPSHUFDMask(M, VT) ||
11325 isPSHUFHWMask(M, VT) ||
11326 isPSHUFLWMask(M, VT) ||
11327 isPALIGNRMask(M, VT, Subtarget) ||
11328 isUNPCKLMask(M, VT, Subtarget->hasAVX2()) ||
11329 isUNPCKHMask(M, VT, Subtarget->hasAVX2()) ||
11330 isUNPCKL_v_undef_Mask(M, VT, Subtarget->hasAVX2()) ||
11331 isUNPCKH_v_undef_Mask(M, VT, Subtarget->hasAVX2()));
11335 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
11337 unsigned NumElts = VT.getVectorNumElements();
11338 // FIXME: This collection of masks seems suspect.
11341 if (NumElts == 4 && VT.getSizeInBits() == 128) {
11342 return (isMOVLMask(Mask, VT) ||
11343 isCommutedMOVLMask(Mask, VT, true) ||
11344 isSHUFPMask(Mask, VT, Subtarget->hasAVX()) ||
11345 isSHUFPMask(Mask, VT, Subtarget->hasAVX(), /* Commuted */ true));
11350 //===----------------------------------------------------------------------===//
11351 // X86 Scheduler Hooks
11352 //===----------------------------------------------------------------------===//
11354 // private utility function
11355 MachineBasicBlock *
11356 X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
11357 MachineBasicBlock *MBB,
11364 const TargetRegisterClass *RC,
11365 bool Invert) const {
11366 // For the atomic bitwise operator, we generate
11369 // ld t1 = [bitinstr.addr]
11370 // op t2 = t1, [bitinstr.val]
11371 // not t3 = t2 (if Invert)
11373 // lcs dest = [bitinstr.addr], t3 [EAX is implicit]
11375 // fallthrough -->nextMBB
11376 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11377 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11378 MachineFunction::iterator MBBIter = MBB;
11381 /// First build the CFG
11382 MachineFunction *F = MBB->getParent();
11383 MachineBasicBlock *thisMBB = MBB;
11384 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11385 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11386 F->insert(MBBIter, newMBB);
11387 F->insert(MBBIter, nextMBB);
11389 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11390 nextMBB->splice(nextMBB->begin(), thisMBB,
11391 llvm::next(MachineBasicBlock::iterator(bInstr)),
11393 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11395 // Update thisMBB to fall through to newMBB
11396 thisMBB->addSuccessor(newMBB);
11398 // newMBB jumps to itself and fall through to nextMBB
11399 newMBB->addSuccessor(nextMBB);
11400 newMBB->addSuccessor(newMBB);
11402 // Insert instructions into newMBB based on incoming instruction
11403 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
11404 "unexpected number of operands");
11405 DebugLoc dl = bInstr->getDebugLoc();
11406 MachineOperand& destOper = bInstr->getOperand(0);
11407 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11408 int numArgs = bInstr->getNumOperands() - 1;
11409 for (int i=0; i < numArgs; ++i)
11410 argOpers[i] = &bInstr->getOperand(i+1);
11412 // x86 address has 4 operands: base, index, scale, and displacement
11413 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11414 int valArgIndx = lastAddrIndx + 1;
11416 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
11417 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1);
11418 for (int i=0; i <= lastAddrIndx; ++i)
11419 (*MIB).addOperand(*argOpers[i]);
11421 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
11422 assert((argOpers[valArgIndx]->isReg() ||
11423 argOpers[valArgIndx]->isImm()) &&
11424 "invalid operand");
11425 if (argOpers[valArgIndx]->isReg())
11426 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2);
11428 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2);
11430 (*MIB).addOperand(*argOpers[valArgIndx]);
11432 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
11434 MIB = BuildMI(newMBB, dl, TII->get(notOpc), t3).addReg(t2);
11439 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), EAXreg);
11442 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc));
11443 for (int i=0; i <= lastAddrIndx; ++i)
11444 (*MIB).addOperand(*argOpers[i]);
11446 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11447 (*MIB).setMemRefs(bInstr->memoperands_begin(),
11448 bInstr->memoperands_end());
11450 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
11451 MIB.addReg(EAXreg);
11454 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11456 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
11460 // private utility function: 64 bit atomics on 32 bit host.
11461 MachineBasicBlock *
11462 X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
11463 MachineBasicBlock *MBB,
11468 bool Invert) const {
11469 // For the atomic bitwise operator, we generate
11470 // thisMBB (instructions are in pairs, except cmpxchg8b)
11471 // ld t1,t2 = [bitinstr.addr]
11473 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4)
11474 // op t5, t6 <- out1, out2, [bitinstr.val]
11475 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val])
11476 // neg t7, t8 < t5, t6 (if Invert)
11477 // mov ECX, EBX <- t5, t6
11478 // mov EAX, EDX <- t1, t2
11479 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit]
11480 // mov t3, t4 <- EAX, EDX
11482 // result in out1, out2
11483 // fallthrough -->nextMBB
11485 const TargetRegisterClass *RC = &X86::GR32RegClass;
11486 const unsigned LoadOpc = X86::MOV32rm;
11487 const unsigned NotOpc = X86::NOT32r;
11488 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11489 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11490 MachineFunction::iterator MBBIter = MBB;
11493 /// First build the CFG
11494 MachineFunction *F = MBB->getParent();
11495 MachineBasicBlock *thisMBB = MBB;
11496 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11497 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11498 F->insert(MBBIter, newMBB);
11499 F->insert(MBBIter, nextMBB);
11501 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11502 nextMBB->splice(nextMBB->begin(), thisMBB,
11503 llvm::next(MachineBasicBlock::iterator(bInstr)),
11505 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11507 // Update thisMBB to fall through to newMBB
11508 thisMBB->addSuccessor(newMBB);
11510 // newMBB jumps to itself and fall through to nextMBB
11511 newMBB->addSuccessor(nextMBB);
11512 newMBB->addSuccessor(newMBB);
11514 DebugLoc dl = bInstr->getDebugLoc();
11515 // Insert instructions into newMBB based on incoming instruction
11516 // There are 8 "real" operands plus 9 implicit def/uses, ignored here.
11517 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 14 &&
11518 "unexpected number of operands");
11519 MachineOperand& dest1Oper = bInstr->getOperand(0);
11520 MachineOperand& dest2Oper = bInstr->getOperand(1);
11521 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11522 for (int i=0; i < 2 + X86::AddrNumOperands; ++i) {
11523 argOpers[i] = &bInstr->getOperand(i+2);
11525 // We use some of the operands multiple times, so conservatively just
11526 // clear any kill flags that might be present.
11527 if (argOpers[i]->isReg() && argOpers[i]->isUse())
11528 argOpers[i]->setIsKill(false);
11531 // x86 address has 5 operands: base, index, scale, displacement, and segment.
11532 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11534 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
11535 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1);
11536 for (int i=0; i <= lastAddrIndx; ++i)
11537 (*MIB).addOperand(*argOpers[i]);
11538 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
11539 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2);
11540 // add 4 to displacement.
11541 for (int i=0; i <= lastAddrIndx-2; ++i)
11542 (*MIB).addOperand(*argOpers[i]);
11543 MachineOperand newOp3 = *(argOpers[3]);
11544 if (newOp3.isImm())
11545 newOp3.setImm(newOp3.getImm()+4);
11547 newOp3.setOffset(newOp3.getOffset()+4);
11548 (*MIB).addOperand(newOp3);
11549 (*MIB).addOperand(*argOpers[lastAddrIndx]);
11551 // t3/4 are defined later, at the bottom of the loop
11552 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
11553 unsigned t4 = F->getRegInfo().createVirtualRegister(RC);
11554 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg())
11555 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB);
11556 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg())
11557 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB);
11559 // The subsequent operations should be using the destination registers of
11560 // the PHI instructions.
11561 t1 = dest1Oper.getReg();
11562 t2 = dest2Oper.getReg();
11564 int valArgIndx = lastAddrIndx + 1;
11565 assert((argOpers[valArgIndx]->isReg() ||
11566 argOpers[valArgIndx]->isImm()) &&
11567 "invalid operand");
11568 unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
11569 unsigned t6 = F->getRegInfo().createVirtualRegister(RC);
11570 if (argOpers[valArgIndx]->isReg())
11571 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5);
11573 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5);
11574 if (regOpcL != X86::MOV32rr)
11576 (*MIB).addOperand(*argOpers[valArgIndx]);
11577 assert(argOpers[valArgIndx + 1]->isReg() ==
11578 argOpers[valArgIndx]->isReg());
11579 assert(argOpers[valArgIndx + 1]->isImm() ==
11580 argOpers[valArgIndx]->isImm());
11581 if (argOpers[valArgIndx + 1]->isReg())
11582 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6);
11584 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6);
11585 if (regOpcH != X86::MOV32rr)
11587 (*MIB).addOperand(*argOpers[valArgIndx + 1]);
11591 t7 = F->getRegInfo().createVirtualRegister(RC);
11592 t8 = F->getRegInfo().createVirtualRegister(RC);
11593 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t7).addReg(t5);
11594 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t8).addReg(t6);
11600 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
11602 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EDX);
11605 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EBX);
11607 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::ECX);
11610 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B));
11611 for (int i=0; i <= lastAddrIndx; ++i)
11612 (*MIB).addOperand(*argOpers[i]);
11614 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11615 (*MIB).setMemRefs(bInstr->memoperands_begin(),
11616 bInstr->memoperands_end());
11618 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t3);
11619 MIB.addReg(X86::EAX);
11620 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t4);
11621 MIB.addReg(X86::EDX);
11624 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11626 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
11630 // private utility function
11631 MachineBasicBlock *
11632 X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
11633 MachineBasicBlock *MBB,
11634 unsigned cmovOpc) const {
11635 // For the atomic min/max operator, we generate
11638 // ld t1 = [min/max.addr]
11639 // mov t2 = [min/max.val]
11641 // cmov[cond] t2 = t1
11643 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
11645 // fallthrough -->nextMBB
11647 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11648 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11649 MachineFunction::iterator MBBIter = MBB;
11652 /// First build the CFG
11653 MachineFunction *F = MBB->getParent();
11654 MachineBasicBlock *thisMBB = MBB;
11655 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11656 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11657 F->insert(MBBIter, newMBB);
11658 F->insert(MBBIter, nextMBB);
11660 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11661 nextMBB->splice(nextMBB->begin(), thisMBB,
11662 llvm::next(MachineBasicBlock::iterator(mInstr)),
11664 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11666 // Update thisMBB to fall through to newMBB
11667 thisMBB->addSuccessor(newMBB);
11669 // newMBB jumps to newMBB and fall through to nextMBB
11670 newMBB->addSuccessor(nextMBB);
11671 newMBB->addSuccessor(newMBB);
11673 DebugLoc dl = mInstr->getDebugLoc();
11674 // Insert instructions into newMBB based on incoming instruction
11675 assert(mInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
11676 "unexpected number of operands");
11677 MachineOperand& destOper = mInstr->getOperand(0);
11678 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11679 int numArgs = mInstr->getNumOperands() - 1;
11680 for (int i=0; i < numArgs; ++i)
11681 argOpers[i] = &mInstr->getOperand(i+1);
11683 // x86 address has 4 operands: base, index, scale, and displacement
11684 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11685 int valArgIndx = lastAddrIndx + 1;
11687 unsigned t1 = F->getRegInfo().createVirtualRegister(&X86::GR32RegClass);
11688 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1);
11689 for (int i=0; i <= lastAddrIndx; ++i)
11690 (*MIB).addOperand(*argOpers[i]);
11692 // We only support register and immediate values
11693 assert((argOpers[valArgIndx]->isReg() ||
11694 argOpers[valArgIndx]->isImm()) &&
11695 "invalid operand");
11697 unsigned t2 = F->getRegInfo().createVirtualRegister(&X86::GR32RegClass);
11698 if (argOpers[valArgIndx]->isReg())
11699 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t2);
11701 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
11702 (*MIB).addOperand(*argOpers[valArgIndx]);
11704 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
11707 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr));
11712 unsigned t3 = F->getRegInfo().createVirtualRegister(&X86::GR32RegClass);
11713 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3);
11717 // Cmp and exchange if none has modified the memory location
11718 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32));
11719 for (int i=0; i <= lastAddrIndx; ++i)
11720 (*MIB).addOperand(*argOpers[i]);
11722 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11723 (*MIB).setMemRefs(mInstr->memoperands_begin(),
11724 mInstr->memoperands_end());
11726 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
11727 MIB.addReg(X86::EAX);
11730 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11732 mInstr->eraseFromParent(); // The pseudo instruction is gone now.
11736 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
11737 // or XMM0_V32I8 in AVX all of this code can be replaced with that
11738 // in the .td file.
11739 MachineBasicBlock *
11740 X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB,
11741 unsigned numArgs, bool memArg) const {
11742 assert(Subtarget->hasSSE42() &&
11743 "Target must have SSE4.2 or AVX features enabled");
11745 DebugLoc dl = MI->getDebugLoc();
11746 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11748 if (!Subtarget->hasAVX()) {
11750 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm;
11752 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr;
11755 Opc = numArgs == 3 ? X86::VPCMPISTRM128rm : X86::VPCMPESTRM128rm;
11757 Opc = numArgs == 3 ? X86::VPCMPISTRM128rr : X86::VPCMPESTRM128rr;
11760 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
11761 for (unsigned i = 0; i < numArgs; ++i) {
11762 MachineOperand &Op = MI->getOperand(i+1);
11763 if (!(Op.isReg() && Op.isImplicit()))
11764 MIB.addOperand(Op);
11766 BuildMI(*BB, MI, dl,
11767 TII->get(Subtarget->hasAVX() ? X86::VMOVAPSrr : X86::MOVAPSrr),
11768 MI->getOperand(0).getReg())
11769 .addReg(X86::XMM0);
11771 MI->eraseFromParent();
11775 MachineBasicBlock *
11776 X86TargetLowering::EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB) const {
11777 DebugLoc dl = MI->getDebugLoc();
11778 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11780 // Address into RAX/EAX, other two args into ECX, EDX.
11781 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
11782 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
11783 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
11784 for (int i = 0; i < X86::AddrNumOperands; ++i)
11785 MIB.addOperand(MI->getOperand(i));
11787 unsigned ValOps = X86::AddrNumOperands;
11788 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
11789 .addReg(MI->getOperand(ValOps).getReg());
11790 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
11791 .addReg(MI->getOperand(ValOps+1).getReg());
11793 // The instruction doesn't actually take any operands though.
11794 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
11796 MI->eraseFromParent(); // The pseudo is gone now.
11800 MachineBasicBlock *
11801 X86TargetLowering::EmitMwait(MachineInstr *MI, MachineBasicBlock *BB) const {
11802 DebugLoc dl = MI->getDebugLoc();
11803 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11805 // First arg in ECX, the second in EAX.
11806 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
11807 .addReg(MI->getOperand(0).getReg());
11808 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EAX)
11809 .addReg(MI->getOperand(1).getReg());
11811 // The instruction doesn't actually take any operands though.
11812 BuildMI(*BB, MI, dl, TII->get(X86::MWAITrr));
11814 MI->eraseFromParent(); // The pseudo is gone now.
11818 MachineBasicBlock *
11819 X86TargetLowering::EmitVAARG64WithCustomInserter(
11821 MachineBasicBlock *MBB) const {
11822 // Emit va_arg instruction on X86-64.
11824 // Operands to this pseudo-instruction:
11825 // 0 ) Output : destination address (reg)
11826 // 1-5) Input : va_list address (addr, i64mem)
11827 // 6 ) ArgSize : Size (in bytes) of vararg type
11828 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
11829 // 8 ) Align : Alignment of type
11830 // 9 ) EFLAGS (implicit-def)
11832 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
11833 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
11835 unsigned DestReg = MI->getOperand(0).getReg();
11836 MachineOperand &Base = MI->getOperand(1);
11837 MachineOperand &Scale = MI->getOperand(2);
11838 MachineOperand &Index = MI->getOperand(3);
11839 MachineOperand &Disp = MI->getOperand(4);
11840 MachineOperand &Segment = MI->getOperand(5);
11841 unsigned ArgSize = MI->getOperand(6).getImm();
11842 unsigned ArgMode = MI->getOperand(7).getImm();
11843 unsigned Align = MI->getOperand(8).getImm();
11845 // Memory Reference
11846 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
11847 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
11848 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
11850 // Machine Information
11851 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11852 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
11853 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
11854 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
11855 DebugLoc DL = MI->getDebugLoc();
11857 // struct va_list {
11860 // i64 overflow_area (address)
11861 // i64 reg_save_area (address)
11863 // sizeof(va_list) = 24
11864 // alignment(va_list) = 8
11866 unsigned TotalNumIntRegs = 6;
11867 unsigned TotalNumXMMRegs = 8;
11868 bool UseGPOffset = (ArgMode == 1);
11869 bool UseFPOffset = (ArgMode == 2);
11870 unsigned MaxOffset = TotalNumIntRegs * 8 +
11871 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
11873 /* Align ArgSize to a multiple of 8 */
11874 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
11875 bool NeedsAlign = (Align > 8);
11877 MachineBasicBlock *thisMBB = MBB;
11878 MachineBasicBlock *overflowMBB;
11879 MachineBasicBlock *offsetMBB;
11880 MachineBasicBlock *endMBB;
11882 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
11883 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
11884 unsigned OffsetReg = 0;
11886 if (!UseGPOffset && !UseFPOffset) {
11887 // If we only pull from the overflow region, we don't create a branch.
11888 // We don't need to alter control flow.
11889 OffsetDestReg = 0; // unused
11890 OverflowDestReg = DestReg;
11893 overflowMBB = thisMBB;
11896 // First emit code to check if gp_offset (or fp_offset) is below the bound.
11897 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
11898 // If not, pull from overflow_area. (branch to overflowMBB)
11903 // offsetMBB overflowMBB
11908 // Registers for the PHI in endMBB
11909 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
11910 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
11912 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11913 MachineFunction *MF = MBB->getParent();
11914 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11915 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11916 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11918 MachineFunction::iterator MBBIter = MBB;
11921 // Insert the new basic blocks
11922 MF->insert(MBBIter, offsetMBB);
11923 MF->insert(MBBIter, overflowMBB);
11924 MF->insert(MBBIter, endMBB);
11926 // Transfer the remainder of MBB and its successor edges to endMBB.
11927 endMBB->splice(endMBB->begin(), thisMBB,
11928 llvm::next(MachineBasicBlock::iterator(MI)),
11930 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11932 // Make offsetMBB and overflowMBB successors of thisMBB
11933 thisMBB->addSuccessor(offsetMBB);
11934 thisMBB->addSuccessor(overflowMBB);
11936 // endMBB is a successor of both offsetMBB and overflowMBB
11937 offsetMBB->addSuccessor(endMBB);
11938 overflowMBB->addSuccessor(endMBB);
11940 // Load the offset value into a register
11941 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
11942 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
11946 .addDisp(Disp, UseFPOffset ? 4 : 0)
11947 .addOperand(Segment)
11948 .setMemRefs(MMOBegin, MMOEnd);
11950 // Check if there is enough room left to pull this argument.
11951 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
11953 .addImm(MaxOffset + 8 - ArgSizeA8);
11955 // Branch to "overflowMBB" if offset >= max
11956 // Fall through to "offsetMBB" otherwise
11957 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
11958 .addMBB(overflowMBB);
11961 // In offsetMBB, emit code to use the reg_save_area.
11963 assert(OffsetReg != 0);
11965 // Read the reg_save_area address.
11966 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
11967 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
11972 .addOperand(Segment)
11973 .setMemRefs(MMOBegin, MMOEnd);
11975 // Zero-extend the offset
11976 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
11977 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
11980 .addImm(X86::sub_32bit);
11982 // Add the offset to the reg_save_area to get the final address.
11983 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
11984 .addReg(OffsetReg64)
11985 .addReg(RegSaveReg);
11987 // Compute the offset for the next argument
11988 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
11989 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
11991 .addImm(UseFPOffset ? 16 : 8);
11993 // Store it back into the va_list.
11994 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
11998 .addDisp(Disp, UseFPOffset ? 4 : 0)
11999 .addOperand(Segment)
12000 .addReg(NextOffsetReg)
12001 .setMemRefs(MMOBegin, MMOEnd);
12004 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
12009 // Emit code to use overflow area
12012 // Load the overflow_area address into a register.
12013 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
12014 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
12019 .addOperand(Segment)
12020 .setMemRefs(MMOBegin, MMOEnd);
12022 // If we need to align it, do so. Otherwise, just copy the address
12023 // to OverflowDestReg.
12025 // Align the overflow address
12026 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
12027 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
12029 // aligned_addr = (addr + (align-1)) & ~(align-1)
12030 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
12031 .addReg(OverflowAddrReg)
12034 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
12036 .addImm(~(uint64_t)(Align-1));
12038 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
12039 .addReg(OverflowAddrReg);
12042 // Compute the next overflow address after this argument.
12043 // (the overflow address should be kept 8-byte aligned)
12044 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
12045 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
12046 .addReg(OverflowDestReg)
12047 .addImm(ArgSizeA8);
12049 // Store the new overflow address.
12050 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
12055 .addOperand(Segment)
12056 .addReg(NextAddrReg)
12057 .setMemRefs(MMOBegin, MMOEnd);
12059 // If we branched, emit the PHI to the front of endMBB.
12061 BuildMI(*endMBB, endMBB->begin(), DL,
12062 TII->get(X86::PHI), DestReg)
12063 .addReg(OffsetDestReg).addMBB(offsetMBB)
12064 .addReg(OverflowDestReg).addMBB(overflowMBB);
12067 // Erase the pseudo instruction
12068 MI->eraseFromParent();
12073 MachineBasicBlock *
12074 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
12076 MachineBasicBlock *MBB) const {
12077 // Emit code to save XMM registers to the stack. The ABI says that the
12078 // number of registers to save is given in %al, so it's theoretically
12079 // possible to do an indirect jump trick to avoid saving all of them,
12080 // however this code takes a simpler approach and just executes all
12081 // of the stores if %al is non-zero. It's less code, and it's probably
12082 // easier on the hardware branch predictor, and stores aren't all that
12083 // expensive anyway.
12085 // Create the new basic blocks. One block contains all the XMM stores,
12086 // and one block is the final destination regardless of whether any
12087 // stores were performed.
12088 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
12089 MachineFunction *F = MBB->getParent();
12090 MachineFunction::iterator MBBIter = MBB;
12092 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
12093 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
12094 F->insert(MBBIter, XMMSaveMBB);
12095 F->insert(MBBIter, EndMBB);
12097 // Transfer the remainder of MBB and its successor edges to EndMBB.
12098 EndMBB->splice(EndMBB->begin(), MBB,
12099 llvm::next(MachineBasicBlock::iterator(MI)),
12101 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
12103 // The original block will now fall through to the XMM save block.
12104 MBB->addSuccessor(XMMSaveMBB);
12105 // The XMMSaveMBB will fall through to the end block.
12106 XMMSaveMBB->addSuccessor(EndMBB);
12108 // Now add the instructions.
12109 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12110 DebugLoc DL = MI->getDebugLoc();
12112 unsigned CountReg = MI->getOperand(0).getReg();
12113 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
12114 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
12116 if (!Subtarget->isTargetWin64()) {
12117 // If %al is 0, branch around the XMM save block.
12118 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
12119 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
12120 MBB->addSuccessor(EndMBB);
12123 unsigned MOVOpc = Subtarget->hasAVX() ? X86::VMOVAPSmr : X86::MOVAPSmr;
12124 // In the XMM save block, save all the XMM argument registers.
12125 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
12126 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
12127 MachineMemOperand *MMO =
12128 F->getMachineMemOperand(
12129 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
12130 MachineMemOperand::MOStore,
12131 /*Size=*/16, /*Align=*/16);
12132 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
12133 .addFrameIndex(RegSaveFrameIndex)
12134 .addImm(/*Scale=*/1)
12135 .addReg(/*IndexReg=*/0)
12136 .addImm(/*Disp=*/Offset)
12137 .addReg(/*Segment=*/0)
12138 .addReg(MI->getOperand(i).getReg())
12139 .addMemOperand(MMO);
12142 MI->eraseFromParent(); // The pseudo instruction is gone now.
12147 // The EFLAGS operand of SelectItr might be missing a kill marker
12148 // because there were multiple uses of EFLAGS, and ISel didn't know
12149 // which to mark. Figure out whether SelectItr should have had a
12150 // kill marker, and set it if it should. Returns the correct kill
12152 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
12153 MachineBasicBlock* BB,
12154 const TargetRegisterInfo* TRI) {
12155 // Scan forward through BB for a use/def of EFLAGS.
12156 MachineBasicBlock::iterator miI(llvm::next(SelectItr));
12157 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
12158 const MachineInstr& mi = *miI;
12159 if (mi.readsRegister(X86::EFLAGS))
12161 if (mi.definesRegister(X86::EFLAGS))
12162 break; // Should have kill-flag - update below.
12165 // If we hit the end of the block, check whether EFLAGS is live into a
12167 if (miI == BB->end()) {
12168 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
12169 sEnd = BB->succ_end();
12170 sItr != sEnd; ++sItr) {
12171 MachineBasicBlock* succ = *sItr;
12172 if (succ->isLiveIn(X86::EFLAGS))
12177 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
12178 // out. SelectMI should have a kill flag on EFLAGS.
12179 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
12183 MachineBasicBlock *
12184 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
12185 MachineBasicBlock *BB) const {
12186 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12187 DebugLoc DL = MI->getDebugLoc();
12189 // To "insert" a SELECT_CC instruction, we actually have to insert the
12190 // diamond control-flow pattern. The incoming instruction knows the
12191 // destination vreg to set, the condition code register to branch on, the
12192 // true/false values to select between, and a branch opcode to use.
12193 const BasicBlock *LLVM_BB = BB->getBasicBlock();
12194 MachineFunction::iterator It = BB;
12200 // cmpTY ccX, r1, r2
12202 // fallthrough --> copy0MBB
12203 MachineBasicBlock *thisMBB = BB;
12204 MachineFunction *F = BB->getParent();
12205 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
12206 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
12207 F->insert(It, copy0MBB);
12208 F->insert(It, sinkMBB);
12210 // If the EFLAGS register isn't dead in the terminator, then claim that it's
12211 // live into the sink and copy blocks.
12212 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
12213 if (!MI->killsRegister(X86::EFLAGS) &&
12214 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
12215 copy0MBB->addLiveIn(X86::EFLAGS);
12216 sinkMBB->addLiveIn(X86::EFLAGS);
12219 // Transfer the remainder of BB and its successor edges to sinkMBB.
12220 sinkMBB->splice(sinkMBB->begin(), BB,
12221 llvm::next(MachineBasicBlock::iterator(MI)),
12223 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
12225 // Add the true and fallthrough blocks as its successors.
12226 BB->addSuccessor(copy0MBB);
12227 BB->addSuccessor(sinkMBB);
12229 // Create the conditional branch instruction.
12231 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
12232 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
12235 // %FalseValue = ...
12236 // # fallthrough to sinkMBB
12237 copy0MBB->addSuccessor(sinkMBB);
12240 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
12242 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
12243 TII->get(X86::PHI), MI->getOperand(0).getReg())
12244 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
12245 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
12247 MI->eraseFromParent(); // The pseudo instruction is gone now.
12251 MachineBasicBlock *
12252 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB,
12253 bool Is64Bit) const {
12254 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12255 DebugLoc DL = MI->getDebugLoc();
12256 MachineFunction *MF = BB->getParent();
12257 const BasicBlock *LLVM_BB = BB->getBasicBlock();
12259 assert(getTargetMachine().Options.EnableSegmentedStacks);
12261 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
12262 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30;
12265 // ... [Till the alloca]
12266 // If stacklet is not large enough, jump to mallocMBB
12269 // Allocate by subtracting from RSP
12270 // Jump to continueMBB
12273 // Allocate by call to runtime
12277 // [rest of original BB]
12280 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12281 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12282 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12284 MachineRegisterInfo &MRI = MF->getRegInfo();
12285 const TargetRegisterClass *AddrRegClass =
12286 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32);
12288 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
12289 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
12290 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
12291 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
12292 sizeVReg = MI->getOperand(1).getReg(),
12293 physSPReg = Is64Bit ? X86::RSP : X86::ESP;
12295 MachineFunction::iterator MBBIter = BB;
12298 MF->insert(MBBIter, bumpMBB);
12299 MF->insert(MBBIter, mallocMBB);
12300 MF->insert(MBBIter, continueMBB);
12302 continueMBB->splice(continueMBB->begin(), BB, llvm::next
12303 (MachineBasicBlock::iterator(MI)), BB->end());
12304 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
12306 // Add code to the main basic block to check if the stack limit has been hit,
12307 // and if so, jump to mallocMBB otherwise to bumpMBB.
12308 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
12309 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
12310 .addReg(tmpSPVReg).addReg(sizeVReg);
12311 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr))
12312 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
12313 .addReg(SPLimitVReg);
12314 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
12316 // bumpMBB simply decreases the stack pointer, since we know the current
12317 // stacklet has enough space.
12318 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
12319 .addReg(SPLimitVReg);
12320 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
12321 .addReg(SPLimitVReg);
12322 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
12324 // Calls into a routine in libgcc to allocate more space from the heap.
12325 const uint32_t *RegMask =
12326 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
12328 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
12330 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
12331 .addExternalSymbol("__morestack_allocate_stack_space").addReg(X86::RDI)
12332 .addRegMask(RegMask)
12333 .addReg(X86::RAX, RegState::ImplicitDefine);
12335 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
12337 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
12338 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
12339 .addExternalSymbol("__morestack_allocate_stack_space")
12340 .addRegMask(RegMask)
12341 .addReg(X86::EAX, RegState::ImplicitDefine);
12345 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
12348 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
12349 .addReg(Is64Bit ? X86::RAX : X86::EAX);
12350 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
12352 // Set up the CFG correctly.
12353 BB->addSuccessor(bumpMBB);
12354 BB->addSuccessor(mallocMBB);
12355 mallocMBB->addSuccessor(continueMBB);
12356 bumpMBB->addSuccessor(continueMBB);
12358 // Take care of the PHI nodes.
12359 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
12360 MI->getOperand(0).getReg())
12361 .addReg(mallocPtrVReg).addMBB(mallocMBB)
12362 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
12364 // Delete the original pseudo instruction.
12365 MI->eraseFromParent();
12368 return continueMBB;
12371 MachineBasicBlock *
12372 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
12373 MachineBasicBlock *BB) const {
12374 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12375 DebugLoc DL = MI->getDebugLoc();
12377 assert(!Subtarget->isTargetEnvMacho());
12379 // The lowering is pretty easy: we're just emitting the call to _alloca. The
12380 // non-trivial part is impdef of ESP.
12382 if (Subtarget->isTargetWin64()) {
12383 if (Subtarget->isTargetCygMing()) {
12384 // ___chkstk(Mingw64):
12385 // Clobbers R10, R11, RAX and EFLAGS.
12387 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
12388 .addExternalSymbol("___chkstk")
12389 .addReg(X86::RAX, RegState::Implicit)
12390 .addReg(X86::RSP, RegState::Implicit)
12391 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
12392 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
12393 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
12395 // __chkstk(MSVCRT): does not update stack pointer.
12396 // Clobbers R10, R11 and EFLAGS.
12397 // FIXME: RAX(allocated size) might be reused and not killed.
12398 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
12399 .addExternalSymbol("__chkstk")
12400 .addReg(X86::RAX, RegState::Implicit)
12401 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
12402 // RAX has the offset to subtracted from RSP.
12403 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
12408 const char *StackProbeSymbol =
12409 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca";
12411 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
12412 .addExternalSymbol(StackProbeSymbol)
12413 .addReg(X86::EAX, RegState::Implicit)
12414 .addReg(X86::ESP, RegState::Implicit)
12415 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
12416 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
12417 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
12420 MI->eraseFromParent(); // The pseudo instruction is gone now.
12424 MachineBasicBlock *
12425 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
12426 MachineBasicBlock *BB) const {
12427 // This is pretty easy. We're taking the value that we received from
12428 // our load from the relocation, sticking it in either RDI (x86-64)
12429 // or EAX and doing an indirect call. The return value will then
12430 // be in the normal return register.
12431 const X86InstrInfo *TII
12432 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo());
12433 DebugLoc DL = MI->getDebugLoc();
12434 MachineFunction *F = BB->getParent();
12436 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
12437 assert(MI->getOperand(3).isGlobal() && "This should be a global");
12439 // Get a register mask for the lowered call.
12440 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
12441 // proper register mask.
12442 const uint32_t *RegMask =
12443 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
12444 if (Subtarget->is64Bit()) {
12445 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
12446 TII->get(X86::MOV64rm), X86::RDI)
12448 .addImm(0).addReg(0)
12449 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
12450 MI->getOperand(3).getTargetFlags())
12452 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
12453 addDirectMem(MIB, X86::RDI);
12454 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
12455 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
12456 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
12457 TII->get(X86::MOV32rm), X86::EAX)
12459 .addImm(0).addReg(0)
12460 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
12461 MI->getOperand(3).getTargetFlags())
12463 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
12464 addDirectMem(MIB, X86::EAX);
12465 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
12467 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
12468 TII->get(X86::MOV32rm), X86::EAX)
12469 .addReg(TII->getGlobalBaseReg(F))
12470 .addImm(0).addReg(0)
12471 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
12472 MI->getOperand(3).getTargetFlags())
12474 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
12475 addDirectMem(MIB, X86::EAX);
12476 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
12479 MI->eraseFromParent(); // The pseudo instruction is gone now.
12483 MachineBasicBlock *
12484 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
12485 MachineBasicBlock *BB) const {
12486 switch (MI->getOpcode()) {
12487 default: llvm_unreachable("Unexpected instr type to insert");
12488 case X86::TAILJMPd64:
12489 case X86::TAILJMPr64:
12490 case X86::TAILJMPm64:
12491 llvm_unreachable("TAILJMP64 would not be touched here.");
12492 case X86::TCRETURNdi64:
12493 case X86::TCRETURNri64:
12494 case X86::TCRETURNmi64:
12496 case X86::WIN_ALLOCA:
12497 return EmitLoweredWinAlloca(MI, BB);
12498 case X86::SEG_ALLOCA_32:
12499 return EmitLoweredSegAlloca(MI, BB, false);
12500 case X86::SEG_ALLOCA_64:
12501 return EmitLoweredSegAlloca(MI, BB, true);
12502 case X86::TLSCall_32:
12503 case X86::TLSCall_64:
12504 return EmitLoweredTLSCall(MI, BB);
12505 case X86::CMOV_GR8:
12506 case X86::CMOV_FR32:
12507 case X86::CMOV_FR64:
12508 case X86::CMOV_V4F32:
12509 case X86::CMOV_V2F64:
12510 case X86::CMOV_V2I64:
12511 case X86::CMOV_V8F32:
12512 case X86::CMOV_V4F64:
12513 case X86::CMOV_V4I64:
12514 case X86::CMOV_GR16:
12515 case X86::CMOV_GR32:
12516 case X86::CMOV_RFP32:
12517 case X86::CMOV_RFP64:
12518 case X86::CMOV_RFP80:
12519 return EmitLoweredSelect(MI, BB);
12521 case X86::FP32_TO_INT16_IN_MEM:
12522 case X86::FP32_TO_INT32_IN_MEM:
12523 case X86::FP32_TO_INT64_IN_MEM:
12524 case X86::FP64_TO_INT16_IN_MEM:
12525 case X86::FP64_TO_INT32_IN_MEM:
12526 case X86::FP64_TO_INT64_IN_MEM:
12527 case X86::FP80_TO_INT16_IN_MEM:
12528 case X86::FP80_TO_INT32_IN_MEM:
12529 case X86::FP80_TO_INT64_IN_MEM: {
12530 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12531 DebugLoc DL = MI->getDebugLoc();
12533 // Change the floating point control register to use "round towards zero"
12534 // mode when truncating to an integer value.
12535 MachineFunction *F = BB->getParent();
12536 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
12537 addFrameReference(BuildMI(*BB, MI, DL,
12538 TII->get(X86::FNSTCW16m)), CWFrameIdx);
12540 // Load the old value of the high byte of the control word...
12542 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
12543 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
12546 // Set the high part to be round to zero...
12547 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
12550 // Reload the modified control word now...
12551 addFrameReference(BuildMI(*BB, MI, DL,
12552 TII->get(X86::FLDCW16m)), CWFrameIdx);
12554 // Restore the memory image of control word to original value
12555 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
12558 // Get the X86 opcode to use.
12560 switch (MI->getOpcode()) {
12561 default: llvm_unreachable("illegal opcode!");
12562 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
12563 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
12564 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
12565 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
12566 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
12567 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
12568 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
12569 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
12570 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
12574 MachineOperand &Op = MI->getOperand(0);
12576 AM.BaseType = X86AddressMode::RegBase;
12577 AM.Base.Reg = Op.getReg();
12579 AM.BaseType = X86AddressMode::FrameIndexBase;
12580 AM.Base.FrameIndex = Op.getIndex();
12582 Op = MI->getOperand(1);
12584 AM.Scale = Op.getImm();
12585 Op = MI->getOperand(2);
12587 AM.IndexReg = Op.getImm();
12588 Op = MI->getOperand(3);
12589 if (Op.isGlobal()) {
12590 AM.GV = Op.getGlobal();
12592 AM.Disp = Op.getImm();
12594 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
12595 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
12597 // Reload the original control word now.
12598 addFrameReference(BuildMI(*BB, MI, DL,
12599 TII->get(X86::FLDCW16m)), CWFrameIdx);
12601 MI->eraseFromParent(); // The pseudo instruction is gone now.
12604 // String/text processing lowering.
12605 case X86::PCMPISTRM128REG:
12606 case X86::VPCMPISTRM128REG:
12607 return EmitPCMP(MI, BB, 3, false /* in-mem */);
12608 case X86::PCMPISTRM128MEM:
12609 case X86::VPCMPISTRM128MEM:
12610 return EmitPCMP(MI, BB, 3, true /* in-mem */);
12611 case X86::PCMPESTRM128REG:
12612 case X86::VPCMPESTRM128REG:
12613 return EmitPCMP(MI, BB, 5, false /* in mem */);
12614 case X86::PCMPESTRM128MEM:
12615 case X86::VPCMPESTRM128MEM:
12616 return EmitPCMP(MI, BB, 5, true /* in mem */);
12618 // Thread synchronization.
12620 return EmitMonitor(MI, BB);
12622 return EmitMwait(MI, BB);
12624 // Atomic Lowering.
12625 case X86::ATOMAND32:
12626 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
12627 X86::AND32ri, X86::MOV32rm,
12629 X86::NOT32r, X86::EAX,
12630 &X86::GR32RegClass);
12631 case X86::ATOMOR32:
12632 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
12633 X86::OR32ri, X86::MOV32rm,
12635 X86::NOT32r, X86::EAX,
12636 &X86::GR32RegClass);
12637 case X86::ATOMXOR32:
12638 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
12639 X86::XOR32ri, X86::MOV32rm,
12641 X86::NOT32r, X86::EAX,
12642 &X86::GR32RegClass);
12643 case X86::ATOMNAND32:
12644 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
12645 X86::AND32ri, X86::MOV32rm,
12647 X86::NOT32r, X86::EAX,
12648 &X86::GR32RegClass, true);
12649 case X86::ATOMMIN32:
12650 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
12651 case X86::ATOMMAX32:
12652 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
12653 case X86::ATOMUMIN32:
12654 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
12655 case X86::ATOMUMAX32:
12656 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
12658 case X86::ATOMAND16:
12659 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
12660 X86::AND16ri, X86::MOV16rm,
12662 X86::NOT16r, X86::AX,
12663 &X86::GR16RegClass);
12664 case X86::ATOMOR16:
12665 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
12666 X86::OR16ri, X86::MOV16rm,
12668 X86::NOT16r, X86::AX,
12669 &X86::GR16RegClass);
12670 case X86::ATOMXOR16:
12671 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr,
12672 X86::XOR16ri, X86::MOV16rm,
12674 X86::NOT16r, X86::AX,
12675 &X86::GR16RegClass);
12676 case X86::ATOMNAND16:
12677 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
12678 X86::AND16ri, X86::MOV16rm,
12680 X86::NOT16r, X86::AX,
12681 &X86::GR16RegClass, true);
12682 case X86::ATOMMIN16:
12683 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr);
12684 case X86::ATOMMAX16:
12685 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr);
12686 case X86::ATOMUMIN16:
12687 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr);
12688 case X86::ATOMUMAX16:
12689 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr);
12691 case X86::ATOMAND8:
12692 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
12693 X86::AND8ri, X86::MOV8rm,
12695 X86::NOT8r, X86::AL,
12696 &X86::GR8RegClass);
12698 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
12699 X86::OR8ri, X86::MOV8rm,
12701 X86::NOT8r, X86::AL,
12702 &X86::GR8RegClass);
12703 case X86::ATOMXOR8:
12704 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr,
12705 X86::XOR8ri, X86::MOV8rm,
12707 X86::NOT8r, X86::AL,
12708 &X86::GR8RegClass);
12709 case X86::ATOMNAND8:
12710 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
12711 X86::AND8ri, X86::MOV8rm,
12713 X86::NOT8r, X86::AL,
12714 &X86::GR8RegClass, true);
12715 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
12716 // This group is for 64-bit host.
12717 case X86::ATOMAND64:
12718 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
12719 X86::AND64ri32, X86::MOV64rm,
12721 X86::NOT64r, X86::RAX,
12722 &X86::GR64RegClass);
12723 case X86::ATOMOR64:
12724 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
12725 X86::OR64ri32, X86::MOV64rm,
12727 X86::NOT64r, X86::RAX,
12728 &X86::GR64RegClass);
12729 case X86::ATOMXOR64:
12730 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr,
12731 X86::XOR64ri32, X86::MOV64rm,
12733 X86::NOT64r, X86::RAX,
12734 &X86::GR64RegClass);
12735 case X86::ATOMNAND64:
12736 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
12737 X86::AND64ri32, X86::MOV64rm,
12739 X86::NOT64r, X86::RAX,
12740 &X86::GR64RegClass, true);
12741 case X86::ATOMMIN64:
12742 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr);
12743 case X86::ATOMMAX64:
12744 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr);
12745 case X86::ATOMUMIN64:
12746 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr);
12747 case X86::ATOMUMAX64:
12748 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr);
12750 // This group does 64-bit operations on a 32-bit host.
12751 case X86::ATOMAND6432:
12752 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12753 X86::AND32rr, X86::AND32rr,
12754 X86::AND32ri, X86::AND32ri,
12756 case X86::ATOMOR6432:
12757 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12758 X86::OR32rr, X86::OR32rr,
12759 X86::OR32ri, X86::OR32ri,
12761 case X86::ATOMXOR6432:
12762 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12763 X86::XOR32rr, X86::XOR32rr,
12764 X86::XOR32ri, X86::XOR32ri,
12766 case X86::ATOMNAND6432:
12767 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12768 X86::AND32rr, X86::AND32rr,
12769 X86::AND32ri, X86::AND32ri,
12771 case X86::ATOMADD6432:
12772 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12773 X86::ADD32rr, X86::ADC32rr,
12774 X86::ADD32ri, X86::ADC32ri,
12776 case X86::ATOMSUB6432:
12777 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12778 X86::SUB32rr, X86::SBB32rr,
12779 X86::SUB32ri, X86::SBB32ri,
12781 case X86::ATOMSWAP6432:
12782 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12783 X86::MOV32rr, X86::MOV32rr,
12784 X86::MOV32ri, X86::MOV32ri,
12786 case X86::VASTART_SAVE_XMM_REGS:
12787 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
12789 case X86::VAARG_64:
12790 return EmitVAARG64WithCustomInserter(MI, BB);
12794 //===----------------------------------------------------------------------===//
12795 // X86 Optimization Hooks
12796 //===----------------------------------------------------------------------===//
12798 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
12801 const SelectionDAG &DAG,
12802 unsigned Depth) const {
12803 unsigned BitWidth = KnownZero.getBitWidth();
12804 unsigned Opc = Op.getOpcode();
12805 assert((Opc >= ISD::BUILTIN_OP_END ||
12806 Opc == ISD::INTRINSIC_WO_CHAIN ||
12807 Opc == ISD::INTRINSIC_W_CHAIN ||
12808 Opc == ISD::INTRINSIC_VOID) &&
12809 "Should use MaskedValueIsZero if you don't know whether Op"
12810 " is a target node!");
12812 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
12826 // These nodes' second result is a boolean.
12827 if (Op.getResNo() == 0)
12830 case X86ISD::SETCC:
12831 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
12833 case ISD::INTRINSIC_WO_CHAIN: {
12834 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
12835 unsigned NumLoBits = 0;
12838 case Intrinsic::x86_sse_movmsk_ps:
12839 case Intrinsic::x86_avx_movmsk_ps_256:
12840 case Intrinsic::x86_sse2_movmsk_pd:
12841 case Intrinsic::x86_avx_movmsk_pd_256:
12842 case Intrinsic::x86_mmx_pmovmskb:
12843 case Intrinsic::x86_sse2_pmovmskb_128:
12844 case Intrinsic::x86_avx2_pmovmskb: {
12845 // High bits of movmskp{s|d}, pmovmskb are known zero.
12847 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
12848 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
12849 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
12850 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
12851 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
12852 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
12853 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
12854 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
12856 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
12865 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
12866 unsigned Depth) const {
12867 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
12868 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
12869 return Op.getValueType().getScalarType().getSizeInBits();
12875 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
12876 /// node is a GlobalAddress + offset.
12877 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
12878 const GlobalValue* &GA,
12879 int64_t &Offset) const {
12880 if (N->getOpcode() == X86ISD::Wrapper) {
12881 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
12882 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
12883 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
12887 return TargetLowering::isGAPlusOffset(N, GA, Offset);
12890 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
12891 /// same as extracting the high 128-bit part of 256-bit vector and then
12892 /// inserting the result into the low part of a new 256-bit vector
12893 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
12894 EVT VT = SVOp->getValueType(0);
12895 unsigned NumElems = VT.getVectorNumElements();
12897 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
12898 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
12899 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
12900 SVOp->getMaskElt(j) >= 0)
12906 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
12907 /// same as extracting the low 128-bit part of 256-bit vector and then
12908 /// inserting the result into the high part of a new 256-bit vector
12909 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
12910 EVT VT = SVOp->getValueType(0);
12911 unsigned NumElems = VT.getVectorNumElements();
12913 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
12914 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
12915 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
12916 SVOp->getMaskElt(j) >= 0)
12922 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
12923 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
12924 TargetLowering::DAGCombinerInfo &DCI,
12925 const X86Subtarget* Subtarget) {
12926 DebugLoc dl = N->getDebugLoc();
12927 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
12928 SDValue V1 = SVOp->getOperand(0);
12929 SDValue V2 = SVOp->getOperand(1);
12930 EVT VT = SVOp->getValueType(0);
12931 unsigned NumElems = VT.getVectorNumElements();
12933 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
12934 V2.getOpcode() == ISD::CONCAT_VECTORS) {
12938 // V UNDEF BUILD_VECTOR UNDEF
12940 // CONCAT_VECTOR CONCAT_VECTOR
12943 // RESULT: V + zero extended
12945 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
12946 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
12947 V1.getOperand(1).getOpcode() != ISD::UNDEF)
12950 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
12953 // To match the shuffle mask, the first half of the mask should
12954 // be exactly the first vector, and all the rest a splat with the
12955 // first element of the second one.
12956 for (unsigned i = 0; i != NumElems/2; ++i)
12957 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
12958 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
12961 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
12962 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
12963 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
12964 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
12966 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2,
12968 Ld->getPointerInfo(),
12969 Ld->getAlignment(),
12970 false/*isVolatile*/, true/*ReadMem*/,
12971 false/*WriteMem*/);
12972 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
12975 // Emit a zeroed vector and insert the desired subvector on its
12977 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
12978 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
12979 return DCI.CombineTo(N, InsV);
12982 //===--------------------------------------------------------------------===//
12983 // Combine some shuffles into subvector extracts and inserts:
12986 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
12987 if (isShuffleHigh128VectorInsertLow(SVOp)) {
12988 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
12989 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
12990 return DCI.CombineTo(N, InsV);
12993 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
12994 if (isShuffleLow128VectorInsertHigh(SVOp)) {
12995 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
12996 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
12997 return DCI.CombineTo(N, InsV);
13003 /// PerformShuffleCombine - Performs several different shuffle combines.
13004 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
13005 TargetLowering::DAGCombinerInfo &DCI,
13006 const X86Subtarget *Subtarget) {
13007 DebugLoc dl = N->getDebugLoc();
13008 EVT VT = N->getValueType(0);
13010 // Don't create instructions with illegal types after legalize types has run.
13011 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13012 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
13015 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
13016 if (Subtarget->hasAVX() && VT.getSizeInBits() == 256 &&
13017 N->getOpcode() == ISD::VECTOR_SHUFFLE)
13018 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
13020 // Only handle 128 wide vector from here on.
13021 if (VT.getSizeInBits() != 128)
13024 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
13025 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
13026 // consecutive, non-overlapping, and in the right order.
13027 SmallVector<SDValue, 16> Elts;
13028 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
13029 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
13031 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG);
13035 /// DCI, PerformTruncateCombine - Converts truncate operation to
13036 /// a sequence of vector shuffle operations.
13037 /// It is possible when we truncate 256-bit vector to 128-bit vector
13039 SDValue X86TargetLowering::PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
13040 DAGCombinerInfo &DCI) const {
13041 if (!DCI.isBeforeLegalizeOps())
13044 if (!Subtarget->hasAVX())
13047 EVT VT = N->getValueType(0);
13048 SDValue Op = N->getOperand(0);
13049 EVT OpVT = Op.getValueType();
13050 DebugLoc dl = N->getDebugLoc();
13052 if ((VT == MVT::v4i32) && (OpVT == MVT::v4i64)) {
13054 if (Subtarget->hasAVX2()) {
13055 // AVX2: v4i64 -> v4i32
13058 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
13060 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v8i32, Op);
13061 Op = DAG.getVectorShuffle(MVT::v8i32, dl, Op, DAG.getUNDEF(MVT::v8i32),
13064 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, Op,
13065 DAG.getIntPtrConstant(0));
13068 // AVX: v4i64 -> v4i32
13069 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Op,
13070 DAG.getIntPtrConstant(0));
13072 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Op,
13073 DAG.getIntPtrConstant(2));
13075 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpLo);
13076 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpHi);
13079 static const int ShufMask1[] = {0, 2, 0, 0};
13081 OpLo = DAG.getVectorShuffle(VT, dl, OpLo, DAG.getUNDEF(VT), ShufMask1);
13082 OpHi = DAG.getVectorShuffle(VT, dl, OpHi, DAG.getUNDEF(VT), ShufMask1);
13085 static const int ShufMask2[] = {0, 1, 4, 5};
13087 return DAG.getVectorShuffle(VT, dl, OpLo, OpHi, ShufMask2);
13090 if ((VT == MVT::v8i16) && (OpVT == MVT::v8i32)) {
13092 if (Subtarget->hasAVX2()) {
13093 // AVX2: v8i32 -> v8i16
13095 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v32i8, Op);
13098 SmallVector<SDValue,32> pshufbMask;
13099 for (unsigned i = 0; i < 2; ++i) {
13100 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
13101 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
13102 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
13103 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
13104 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
13105 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
13106 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
13107 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
13108 for (unsigned j = 0; j < 8; ++j)
13109 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
13111 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v32i8,
13112 &pshufbMask[0], 32);
13113 Op = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v32i8, Op, BV);
13115 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4i64, Op);
13117 static const int ShufMask[] = {0, 2, -1, -1};
13118 Op = DAG.getVectorShuffle(MVT::v4i64, dl, Op, DAG.getUNDEF(MVT::v4i64),
13121 Op = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Op,
13122 DAG.getIntPtrConstant(0));
13124 return DAG.getNode(ISD::BITCAST, dl, VT, Op);
13127 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i32, Op,
13128 DAG.getIntPtrConstant(0));
13130 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i32, Op,
13131 DAG.getIntPtrConstant(4));
13133 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLo);
13134 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpHi);
13137 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
13138 -1, -1, -1, -1, -1, -1, -1, -1};
13140 OpLo = DAG.getVectorShuffle(MVT::v16i8, dl, OpLo, DAG.getUNDEF(MVT::v16i8),
13142 OpHi = DAG.getVectorShuffle(MVT::v16i8, dl, OpHi, DAG.getUNDEF(MVT::v16i8),
13145 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpLo);
13146 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpHi);
13149 static const int ShufMask2[] = {0, 1, 4, 5};
13151 SDValue res = DAG.getVectorShuffle(MVT::v4i32, dl, OpLo, OpHi, ShufMask2);
13152 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, res);
13158 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
13159 /// specific shuffle of a load can be folded into a single element load.
13160 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
13161 /// shuffles have been customed lowered so we need to handle those here.
13162 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
13163 TargetLowering::DAGCombinerInfo &DCI) {
13164 if (DCI.isBeforeLegalizeOps())
13167 SDValue InVec = N->getOperand(0);
13168 SDValue EltNo = N->getOperand(1);
13170 if (!isa<ConstantSDNode>(EltNo))
13173 EVT VT = InVec.getValueType();
13175 bool HasShuffleIntoBitcast = false;
13176 if (InVec.getOpcode() == ISD::BITCAST) {
13177 // Don't duplicate a load with other uses.
13178 if (!InVec.hasOneUse())
13180 EVT BCVT = InVec.getOperand(0).getValueType();
13181 if (BCVT.getVectorNumElements() != VT.getVectorNumElements())
13183 InVec = InVec.getOperand(0);
13184 HasShuffleIntoBitcast = true;
13187 if (!isTargetShuffle(InVec.getOpcode()))
13190 // Don't duplicate a load with other uses.
13191 if (!InVec.hasOneUse())
13194 SmallVector<int, 16> ShuffleMask;
13196 if (!getTargetShuffleMask(InVec.getNode(), VT, ShuffleMask, UnaryShuffle))
13199 // Select the input vector, guarding against out of range extract vector.
13200 unsigned NumElems = VT.getVectorNumElements();
13201 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
13202 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
13203 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
13204 : InVec.getOperand(1);
13206 // If inputs to shuffle are the same for both ops, then allow 2 uses
13207 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
13209 if (LdNode.getOpcode() == ISD::BITCAST) {
13210 // Don't duplicate a load with other uses.
13211 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
13214 AllowedUses = 1; // only allow 1 load use if we have a bitcast
13215 LdNode = LdNode.getOperand(0);
13218 if (!ISD::isNormalLoad(LdNode.getNode()))
13221 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
13223 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
13226 if (HasShuffleIntoBitcast) {
13227 // If there's a bitcast before the shuffle, check if the load type and
13228 // alignment is valid.
13229 unsigned Align = LN0->getAlignment();
13230 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13231 unsigned NewAlign = TLI.getTargetData()->
13232 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
13234 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
13238 // All checks match so transform back to vector_shuffle so that DAG combiner
13239 // can finish the job
13240 DebugLoc dl = N->getDebugLoc();
13242 // Create shuffle node taking into account the case that its a unary shuffle
13243 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1);
13244 Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl,
13245 InVec.getOperand(0), Shuffle,
13247 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
13248 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
13252 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
13253 /// generation and convert it from being a bunch of shuffles and extracts
13254 /// to a simple store and scalar loads to extract the elements.
13255 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
13256 TargetLowering::DAGCombinerInfo &DCI) {
13257 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
13258 if (NewOp.getNode())
13261 SDValue InputVector = N->getOperand(0);
13263 // Only operate on vectors of 4 elements, where the alternative shuffling
13264 // gets to be more expensive.
13265 if (InputVector.getValueType() != MVT::v4i32)
13268 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
13269 // single use which is a sign-extend or zero-extend, and all elements are
13271 SmallVector<SDNode *, 4> Uses;
13272 unsigned ExtractedElements = 0;
13273 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
13274 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
13275 if (UI.getUse().getResNo() != InputVector.getResNo())
13278 SDNode *Extract = *UI;
13279 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
13282 if (Extract->getValueType(0) != MVT::i32)
13284 if (!Extract->hasOneUse())
13286 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
13287 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
13289 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
13292 // Record which element was extracted.
13293 ExtractedElements |=
13294 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
13296 Uses.push_back(Extract);
13299 // If not all the elements were used, this may not be worthwhile.
13300 if (ExtractedElements != 15)
13303 // Ok, we've now decided to do the transformation.
13304 DebugLoc dl = InputVector.getDebugLoc();
13306 // Store the value to a temporary stack slot.
13307 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
13308 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
13309 MachinePointerInfo(), false, false, 0);
13311 // Replace each use (extract) with a load of the appropriate element.
13312 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
13313 UE = Uses.end(); UI != UE; ++UI) {
13314 SDNode *Extract = *UI;
13316 // cOMpute the element's address.
13317 SDValue Idx = Extract->getOperand(1);
13319 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
13320 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
13321 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13322 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
13324 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
13325 StackPtr, OffsetVal);
13327 // Load the scalar.
13328 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
13329 ScalarAddr, MachinePointerInfo(),
13330 false, false, false, 0);
13332 // Replace the exact with the load.
13333 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
13336 // The replacement was made in place; don't return anything.
13340 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
13342 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
13343 TargetLowering::DAGCombinerInfo &DCI,
13344 const X86Subtarget *Subtarget) {
13347 DebugLoc DL = N->getDebugLoc();
13348 SDValue Cond = N->getOperand(0);
13349 // Get the LHS/RHS of the select.
13350 SDValue LHS = N->getOperand(1);
13351 SDValue RHS = N->getOperand(2);
13352 EVT VT = LHS.getValueType();
13354 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
13355 // instructions match the semantics of the common C idiom x<y?x:y but not
13356 // x<=y?x:y, because of how they handle negative zero (which can be
13357 // ignored in unsafe-math mode).
13358 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
13359 VT != MVT::f80 && DAG.getTargetLoweringInfo().isTypeLegal(VT) &&
13360 (Subtarget->hasSSE2() ||
13361 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
13362 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
13364 unsigned Opcode = 0;
13365 // Check for x CC y ? x : y.
13366 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
13367 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
13371 // Converting this to a min would handle NaNs incorrectly, and swapping
13372 // the operands would cause it to handle comparisons between positive
13373 // and negative zero incorrectly.
13374 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
13375 if (!DAG.getTarget().Options.UnsafeFPMath &&
13376 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
13378 std::swap(LHS, RHS);
13380 Opcode = X86ISD::FMIN;
13383 // Converting this to a min would handle comparisons between positive
13384 // and negative zero incorrectly.
13385 if (!DAG.getTarget().Options.UnsafeFPMath &&
13386 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
13388 Opcode = X86ISD::FMIN;
13391 // Converting this to a min would handle both negative zeros and NaNs
13392 // incorrectly, but we can swap the operands to fix both.
13393 std::swap(LHS, RHS);
13397 Opcode = X86ISD::FMIN;
13401 // Converting this to a max would handle comparisons between positive
13402 // and negative zero incorrectly.
13403 if (!DAG.getTarget().Options.UnsafeFPMath &&
13404 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
13406 Opcode = X86ISD::FMAX;
13409 // Converting this to a max would handle NaNs incorrectly, and swapping
13410 // the operands would cause it to handle comparisons between positive
13411 // and negative zero incorrectly.
13412 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
13413 if (!DAG.getTarget().Options.UnsafeFPMath &&
13414 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
13416 std::swap(LHS, RHS);
13418 Opcode = X86ISD::FMAX;
13421 // Converting this to a max would handle both negative zeros and NaNs
13422 // incorrectly, but we can swap the operands to fix both.
13423 std::swap(LHS, RHS);
13427 Opcode = X86ISD::FMAX;
13430 // Check for x CC y ? y : x -- a min/max with reversed arms.
13431 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
13432 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
13436 // Converting this to a min would handle comparisons between positive
13437 // and negative zero incorrectly, and swapping the operands would
13438 // cause it to handle NaNs incorrectly.
13439 if (!DAG.getTarget().Options.UnsafeFPMath &&
13440 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
13441 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
13443 std::swap(LHS, RHS);
13445 Opcode = X86ISD::FMIN;
13448 // Converting this to a min would handle NaNs incorrectly.
13449 if (!DAG.getTarget().Options.UnsafeFPMath &&
13450 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
13452 Opcode = X86ISD::FMIN;
13455 // Converting this to a min would handle both negative zeros and NaNs
13456 // incorrectly, but we can swap the operands to fix both.
13457 std::swap(LHS, RHS);
13461 Opcode = X86ISD::FMIN;
13465 // Converting this to a max would handle NaNs incorrectly.
13466 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
13468 Opcode = X86ISD::FMAX;
13471 // Converting this to a max would handle comparisons between positive
13472 // and negative zero incorrectly, and swapping the operands would
13473 // cause it to handle NaNs incorrectly.
13474 if (!DAG.getTarget().Options.UnsafeFPMath &&
13475 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
13476 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
13478 std::swap(LHS, RHS);
13480 Opcode = X86ISD::FMAX;
13483 // Converting this to a max would handle both negative zeros and NaNs
13484 // incorrectly, but we can swap the operands to fix both.
13485 std::swap(LHS, RHS);
13489 Opcode = X86ISD::FMAX;
13495 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
13498 // If this is a select between two integer constants, try to do some
13500 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
13501 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
13502 // Don't do this for crazy integer types.
13503 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
13504 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
13505 // so that TrueC (the true value) is larger than FalseC.
13506 bool NeedsCondInvert = false;
13508 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
13509 // Efficiently invertible.
13510 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
13511 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
13512 isa<ConstantSDNode>(Cond.getOperand(1))))) {
13513 NeedsCondInvert = true;
13514 std::swap(TrueC, FalseC);
13517 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
13518 if (FalseC->getAPIntValue() == 0 &&
13519 TrueC->getAPIntValue().isPowerOf2()) {
13520 if (NeedsCondInvert) // Invert the condition if needed.
13521 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
13522 DAG.getConstant(1, Cond.getValueType()));
13524 // Zero extend the condition if needed.
13525 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
13527 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
13528 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
13529 DAG.getConstant(ShAmt, MVT::i8));
13532 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
13533 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
13534 if (NeedsCondInvert) // Invert the condition if needed.
13535 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
13536 DAG.getConstant(1, Cond.getValueType()));
13538 // Zero extend the condition if needed.
13539 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
13540 FalseC->getValueType(0), Cond);
13541 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13542 SDValue(FalseC, 0));
13545 // Optimize cases that will turn into an LEA instruction. This requires
13546 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
13547 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
13548 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
13549 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
13551 bool isFastMultiplier = false;
13553 switch ((unsigned char)Diff) {
13555 case 1: // result = add base, cond
13556 case 2: // result = lea base( , cond*2)
13557 case 3: // result = lea base(cond, cond*2)
13558 case 4: // result = lea base( , cond*4)
13559 case 5: // result = lea base(cond, cond*4)
13560 case 8: // result = lea base( , cond*8)
13561 case 9: // result = lea base(cond, cond*8)
13562 isFastMultiplier = true;
13567 if (isFastMultiplier) {
13568 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
13569 if (NeedsCondInvert) // Invert the condition if needed.
13570 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
13571 DAG.getConstant(1, Cond.getValueType()));
13573 // Zero extend the condition if needed.
13574 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
13576 // Scale the condition by the difference.
13578 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
13579 DAG.getConstant(Diff, Cond.getValueType()));
13581 // Add the base if non-zero.
13582 if (FalseC->getAPIntValue() != 0)
13583 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13584 SDValue(FalseC, 0));
13591 // Canonicalize max and min:
13592 // (x > y) ? x : y -> (x >= y) ? x : y
13593 // (x < y) ? x : y -> (x <= y) ? x : y
13594 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
13595 // the need for an extra compare
13596 // against zero. e.g.
13597 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
13599 // testl %edi, %edi
13601 // cmovgl %edi, %eax
13605 // cmovsl %eax, %edi
13606 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
13607 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
13608 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
13609 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
13614 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
13615 Cond = DAG.getSetCC(Cond.getDebugLoc(), Cond.getValueType(),
13616 Cond.getOperand(0), Cond.getOperand(1), NewCC);
13617 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
13622 // If we know that this node is legal then we know that it is going to be
13623 // matched by one of the SSE/AVX BLEND instructions. These instructions only
13624 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
13625 // to simplify previous instructions.
13626 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13627 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
13628 !DCI.isBeforeLegalize() &&
13629 TLI.isOperationLegal(ISD::VSELECT, VT)) {
13630 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
13631 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
13632 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
13634 APInt KnownZero, KnownOne;
13635 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
13636 DCI.isBeforeLegalizeOps());
13637 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
13638 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO))
13639 DCI.CommitTargetLoweringOpt(TLO);
13645 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
13646 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
13647 TargetLowering::DAGCombinerInfo &DCI) {
13648 DebugLoc DL = N->getDebugLoc();
13650 // If the flag operand isn't dead, don't touch this CMOV.
13651 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
13654 SDValue FalseOp = N->getOperand(0);
13655 SDValue TrueOp = N->getOperand(1);
13656 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
13657 SDValue Cond = N->getOperand(3);
13658 if (CC == X86::COND_E || CC == X86::COND_NE) {
13659 switch (Cond.getOpcode()) {
13663 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
13664 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
13665 return (CC == X86::COND_E) ? FalseOp : TrueOp;
13669 // If this is a select between two integer constants, try to do some
13670 // optimizations. Note that the operands are ordered the opposite of SELECT
13672 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
13673 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
13674 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
13675 // larger than FalseC (the false value).
13676 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
13677 CC = X86::GetOppositeBranchCondition(CC);
13678 std::swap(TrueC, FalseC);
13681 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
13682 // This is efficient for any integer data type (including i8/i16) and
13684 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
13685 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13686 DAG.getConstant(CC, MVT::i8), Cond);
13688 // Zero extend the condition if needed.
13689 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
13691 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
13692 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
13693 DAG.getConstant(ShAmt, MVT::i8));
13694 if (N->getNumValues() == 2) // Dead flag value?
13695 return DCI.CombineTo(N, Cond, SDValue());
13699 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
13700 // for any integer data type, including i8/i16.
13701 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
13702 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13703 DAG.getConstant(CC, MVT::i8), Cond);
13705 // Zero extend the condition if needed.
13706 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
13707 FalseC->getValueType(0), Cond);
13708 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13709 SDValue(FalseC, 0));
13711 if (N->getNumValues() == 2) // Dead flag value?
13712 return DCI.CombineTo(N, Cond, SDValue());
13716 // Optimize cases that will turn into an LEA instruction. This requires
13717 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
13718 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
13719 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
13720 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
13722 bool isFastMultiplier = false;
13724 switch ((unsigned char)Diff) {
13726 case 1: // result = add base, cond
13727 case 2: // result = lea base( , cond*2)
13728 case 3: // result = lea base(cond, cond*2)
13729 case 4: // result = lea base( , cond*4)
13730 case 5: // result = lea base(cond, cond*4)
13731 case 8: // result = lea base( , cond*8)
13732 case 9: // result = lea base(cond, cond*8)
13733 isFastMultiplier = true;
13738 if (isFastMultiplier) {
13739 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
13740 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13741 DAG.getConstant(CC, MVT::i8), Cond);
13742 // Zero extend the condition if needed.
13743 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
13745 // Scale the condition by the difference.
13747 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
13748 DAG.getConstant(Diff, Cond.getValueType()));
13750 // Add the base if non-zero.
13751 if (FalseC->getAPIntValue() != 0)
13752 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13753 SDValue(FalseC, 0));
13754 if (N->getNumValues() == 2) // Dead flag value?
13755 return DCI.CombineTo(N, Cond, SDValue());
13765 /// PerformMulCombine - Optimize a single multiply with constant into two
13766 /// in order to implement it with two cheaper instructions, e.g.
13767 /// LEA + SHL, LEA + LEA.
13768 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
13769 TargetLowering::DAGCombinerInfo &DCI) {
13770 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
13773 EVT VT = N->getValueType(0);
13774 if (VT != MVT::i64)
13777 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
13780 uint64_t MulAmt = C->getZExtValue();
13781 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
13784 uint64_t MulAmt1 = 0;
13785 uint64_t MulAmt2 = 0;
13786 if ((MulAmt % 9) == 0) {
13788 MulAmt2 = MulAmt / 9;
13789 } else if ((MulAmt % 5) == 0) {
13791 MulAmt2 = MulAmt / 5;
13792 } else if ((MulAmt % 3) == 0) {
13794 MulAmt2 = MulAmt / 3;
13797 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
13798 DebugLoc DL = N->getDebugLoc();
13800 if (isPowerOf2_64(MulAmt2) &&
13801 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
13802 // If second multiplifer is pow2, issue it first. We want the multiply by
13803 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
13805 std::swap(MulAmt1, MulAmt2);
13808 if (isPowerOf2_64(MulAmt1))
13809 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
13810 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
13812 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
13813 DAG.getConstant(MulAmt1, VT));
13815 if (isPowerOf2_64(MulAmt2))
13816 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
13817 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
13819 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
13820 DAG.getConstant(MulAmt2, VT));
13822 // Do not add new nodes to DAG combiner worklist.
13823 DCI.CombineTo(N, NewMul, false);
13828 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
13829 SDValue N0 = N->getOperand(0);
13830 SDValue N1 = N->getOperand(1);
13831 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
13832 EVT VT = N0.getValueType();
13834 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
13835 // since the result of setcc_c is all zero's or all ones.
13836 if (VT.isInteger() && !VT.isVector() &&
13837 N1C && N0.getOpcode() == ISD::AND &&
13838 N0.getOperand(1).getOpcode() == ISD::Constant) {
13839 SDValue N00 = N0.getOperand(0);
13840 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
13841 ((N00.getOpcode() == ISD::ANY_EXTEND ||
13842 N00.getOpcode() == ISD::ZERO_EXTEND) &&
13843 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
13844 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
13845 APInt ShAmt = N1C->getAPIntValue();
13846 Mask = Mask.shl(ShAmt);
13848 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
13849 N00, DAG.getConstant(Mask, VT));
13854 // Hardware support for vector shifts is sparse which makes us scalarize the
13855 // vector operations in many cases. Also, on sandybridge ADD is faster than
13857 // (shl V, 1) -> add V,V
13858 if (isSplatVector(N1.getNode())) {
13859 assert(N0.getValueType().isVector() && "Invalid vector shift type");
13860 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1->getOperand(0));
13861 // We shift all of the values by one. In many cases we do not have
13862 // hardware support for this operation. This is better expressed as an ADD
13864 if (N1C && (1 == N1C->getZExtValue())) {
13865 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, N0);
13872 /// PerformShiftCombine - Transforms vector shift nodes to use vector shifts
13874 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
13875 TargetLowering::DAGCombinerInfo &DCI,
13876 const X86Subtarget *Subtarget) {
13877 EVT VT = N->getValueType(0);
13878 if (N->getOpcode() == ISD::SHL) {
13879 SDValue V = PerformSHLCombine(N, DAG);
13880 if (V.getNode()) return V;
13883 // On X86 with SSE2 support, we can transform this to a vector shift if
13884 // all elements are shifted by the same amount. We can't do this in legalize
13885 // because the a constant vector is typically transformed to a constant pool
13886 // so we have no knowledge of the shift amount.
13887 if (!Subtarget->hasSSE2())
13890 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
13891 (!Subtarget->hasAVX2() ||
13892 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
13895 SDValue ShAmtOp = N->getOperand(1);
13896 EVT EltVT = VT.getVectorElementType();
13897 DebugLoc DL = N->getDebugLoc();
13898 SDValue BaseShAmt = SDValue();
13899 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
13900 unsigned NumElts = VT.getVectorNumElements();
13902 for (; i != NumElts; ++i) {
13903 SDValue Arg = ShAmtOp.getOperand(i);
13904 if (Arg.getOpcode() == ISD::UNDEF) continue;
13908 // Handle the case where the build_vector is all undef
13909 // FIXME: Should DAG allow this?
13913 for (; i != NumElts; ++i) {
13914 SDValue Arg = ShAmtOp.getOperand(i);
13915 if (Arg.getOpcode() == ISD::UNDEF) continue;
13916 if (Arg != BaseShAmt) {
13920 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
13921 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) {
13922 SDValue InVec = ShAmtOp.getOperand(0);
13923 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
13924 unsigned NumElts = InVec.getValueType().getVectorNumElements();
13926 for (; i != NumElts; ++i) {
13927 SDValue Arg = InVec.getOperand(i);
13928 if (Arg.getOpcode() == ISD::UNDEF) continue;
13932 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
13933 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
13934 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex();
13935 if (C->getZExtValue() == SplatIdx)
13936 BaseShAmt = InVec.getOperand(1);
13939 if (BaseShAmt.getNode() == 0) {
13940 // Don't create instructions with illegal types after legalize
13942 if (!DAG.getTargetLoweringInfo().isTypeLegal(EltVT) &&
13943 !DCI.isBeforeLegalize())
13946 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
13947 DAG.getIntPtrConstant(0));
13952 // The shift amount is an i32.
13953 if (EltVT.bitsGT(MVT::i32))
13954 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt);
13955 else if (EltVT.bitsLT(MVT::i32))
13956 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt);
13958 // The shift amount is identical so we can do a vector shift.
13959 SDValue ValOp = N->getOperand(0);
13960 switch (N->getOpcode()) {
13962 llvm_unreachable("Unknown shift opcode!");
13964 switch (VT.getSimpleVT().SimpleTy) {
13965 default: return SDValue();
13972 return getTargetVShiftNode(X86ISD::VSHLI, DL, VT, ValOp, BaseShAmt, DAG);
13975 switch (VT.getSimpleVT().SimpleTy) {
13976 default: return SDValue();
13981 return getTargetVShiftNode(X86ISD::VSRAI, DL, VT, ValOp, BaseShAmt, DAG);
13984 switch (VT.getSimpleVT().SimpleTy) {
13985 default: return SDValue();
13992 return getTargetVShiftNode(X86ISD::VSRLI, DL, VT, ValOp, BaseShAmt, DAG);
13998 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
13999 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
14000 // and friends. Likewise for OR -> CMPNEQSS.
14001 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
14002 TargetLowering::DAGCombinerInfo &DCI,
14003 const X86Subtarget *Subtarget) {
14006 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
14007 // we're requiring SSE2 for both.
14008 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
14009 SDValue N0 = N->getOperand(0);
14010 SDValue N1 = N->getOperand(1);
14011 SDValue CMP0 = N0->getOperand(1);
14012 SDValue CMP1 = N1->getOperand(1);
14013 DebugLoc DL = N->getDebugLoc();
14015 // The SETCCs should both refer to the same CMP.
14016 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
14019 SDValue CMP00 = CMP0->getOperand(0);
14020 SDValue CMP01 = CMP0->getOperand(1);
14021 EVT VT = CMP00.getValueType();
14023 if (VT == MVT::f32 || VT == MVT::f64) {
14024 bool ExpectingFlags = false;
14025 // Check for any users that want flags:
14026 for (SDNode::use_iterator UI = N->use_begin(),
14028 !ExpectingFlags && UI != UE; ++UI)
14029 switch (UI->getOpcode()) {
14034 ExpectingFlags = true;
14036 case ISD::CopyToReg:
14037 case ISD::SIGN_EXTEND:
14038 case ISD::ZERO_EXTEND:
14039 case ISD::ANY_EXTEND:
14043 if (!ExpectingFlags) {
14044 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
14045 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
14047 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
14048 X86::CondCode tmp = cc0;
14053 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
14054 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
14055 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
14056 X86ISD::NodeType NTOperator = is64BitFP ?
14057 X86ISD::FSETCCsd : X86ISD::FSETCCss;
14058 // FIXME: need symbolic constants for these magic numbers.
14059 // See X86ATTInstPrinter.cpp:printSSECC().
14060 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
14061 SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, MVT::f32, CMP00, CMP01,
14062 DAG.getConstant(x86cc, MVT::i8));
14063 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32,
14065 SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI,
14066 DAG.getConstant(1, MVT::i32));
14067 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
14068 return OneBitOfTruth;
14076 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
14077 /// so it can be folded inside ANDNP.
14078 static bool CanFoldXORWithAllOnes(const SDNode *N) {
14079 EVT VT = N->getValueType(0);
14081 // Match direct AllOnes for 128 and 256-bit vectors
14082 if (ISD::isBuildVectorAllOnes(N))
14085 // Look through a bit convert.
14086 if (N->getOpcode() == ISD::BITCAST)
14087 N = N->getOperand(0).getNode();
14089 // Sometimes the operand may come from a insert_subvector building a 256-bit
14091 if (VT.getSizeInBits() == 256 &&
14092 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
14093 SDValue V1 = N->getOperand(0);
14094 SDValue V2 = N->getOperand(1);
14096 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
14097 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
14098 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
14099 ISD::isBuildVectorAllOnes(V2.getNode()))
14106 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
14107 TargetLowering::DAGCombinerInfo &DCI,
14108 const X86Subtarget *Subtarget) {
14109 if (DCI.isBeforeLegalizeOps())
14112 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
14116 EVT VT = N->getValueType(0);
14118 // Create ANDN, BLSI, and BLSR instructions
14119 // BLSI is X & (-X)
14120 // BLSR is X & (X-1)
14121 if (Subtarget->hasBMI() && (VT == MVT::i32 || VT == MVT::i64)) {
14122 SDValue N0 = N->getOperand(0);
14123 SDValue N1 = N->getOperand(1);
14124 DebugLoc DL = N->getDebugLoc();
14126 // Check LHS for not
14127 if (N0.getOpcode() == ISD::XOR && isAllOnes(N0.getOperand(1)))
14128 return DAG.getNode(X86ISD::ANDN, DL, VT, N0.getOperand(0), N1);
14129 // Check RHS for not
14130 if (N1.getOpcode() == ISD::XOR && isAllOnes(N1.getOperand(1)))
14131 return DAG.getNode(X86ISD::ANDN, DL, VT, N1.getOperand(0), N0);
14133 // Check LHS for neg
14134 if (N0.getOpcode() == ISD::SUB && N0.getOperand(1) == N1 &&
14135 isZero(N0.getOperand(0)))
14136 return DAG.getNode(X86ISD::BLSI, DL, VT, N1);
14138 // Check RHS for neg
14139 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1) == N0 &&
14140 isZero(N1.getOperand(0)))
14141 return DAG.getNode(X86ISD::BLSI, DL, VT, N0);
14143 // Check LHS for X-1
14144 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
14145 isAllOnes(N0.getOperand(1)))
14146 return DAG.getNode(X86ISD::BLSR, DL, VT, N1);
14148 // Check RHS for X-1
14149 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
14150 isAllOnes(N1.getOperand(1)))
14151 return DAG.getNode(X86ISD::BLSR, DL, VT, N0);
14156 // Want to form ANDNP nodes:
14157 // 1) In the hopes of then easily combining them with OR and AND nodes
14158 // to form PBLEND/PSIGN.
14159 // 2) To match ANDN packed intrinsics
14160 if (VT != MVT::v2i64 && VT != MVT::v4i64)
14163 SDValue N0 = N->getOperand(0);
14164 SDValue N1 = N->getOperand(1);
14165 DebugLoc DL = N->getDebugLoc();
14167 // Check LHS for vnot
14168 if (N0.getOpcode() == ISD::XOR &&
14169 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
14170 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
14171 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
14173 // Check RHS for vnot
14174 if (N1.getOpcode() == ISD::XOR &&
14175 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
14176 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
14177 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
14182 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
14183 TargetLowering::DAGCombinerInfo &DCI,
14184 const X86Subtarget *Subtarget) {
14185 if (DCI.isBeforeLegalizeOps())
14188 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
14192 EVT VT = N->getValueType(0);
14194 SDValue N0 = N->getOperand(0);
14195 SDValue N1 = N->getOperand(1);
14197 // look for psign/blend
14198 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
14199 if (!Subtarget->hasSSSE3() ||
14200 (VT == MVT::v4i64 && !Subtarget->hasAVX2()))
14203 // Canonicalize pandn to RHS
14204 if (N0.getOpcode() == X86ISD::ANDNP)
14206 // or (and (m, y), (pandn m, x))
14207 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
14208 SDValue Mask = N1.getOperand(0);
14209 SDValue X = N1.getOperand(1);
14211 if (N0.getOperand(0) == Mask)
14212 Y = N0.getOperand(1);
14213 if (N0.getOperand(1) == Mask)
14214 Y = N0.getOperand(0);
14216 // Check to see if the mask appeared in both the AND and ANDNP and
14220 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
14221 // Look through mask bitcast.
14222 if (Mask.getOpcode() == ISD::BITCAST)
14223 Mask = Mask.getOperand(0);
14224 if (X.getOpcode() == ISD::BITCAST)
14225 X = X.getOperand(0);
14226 if (Y.getOpcode() == ISD::BITCAST)
14227 Y = Y.getOperand(0);
14229 EVT MaskVT = Mask.getValueType();
14231 // Validate that the Mask operand is a vector sra node.
14232 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
14233 // there is no psrai.b
14234 if (Mask.getOpcode() != X86ISD::VSRAI)
14237 // Check that the SRA is all signbits.
14238 SDValue SraC = Mask.getOperand(1);
14239 unsigned SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
14240 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
14241 if ((SraAmt + 1) != EltBits)
14244 DebugLoc DL = N->getDebugLoc();
14246 // Now we know we at least have a plendvb with the mask val. See if
14247 // we can form a psignb/w/d.
14248 // psign = x.type == y.type == mask.type && y = sub(0, x);
14249 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
14250 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
14251 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
14252 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
14253 "Unsupported VT for PSIGN");
14254 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
14255 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
14257 // PBLENDVB only available on SSE 4.1
14258 if (!Subtarget->hasSSE41())
14261 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
14263 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
14264 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
14265 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
14266 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
14267 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
14271 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
14274 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
14275 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
14277 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
14279 if (!N0.hasOneUse() || !N1.hasOneUse())
14282 SDValue ShAmt0 = N0.getOperand(1);
14283 if (ShAmt0.getValueType() != MVT::i8)
14285 SDValue ShAmt1 = N1.getOperand(1);
14286 if (ShAmt1.getValueType() != MVT::i8)
14288 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
14289 ShAmt0 = ShAmt0.getOperand(0);
14290 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
14291 ShAmt1 = ShAmt1.getOperand(0);
14293 DebugLoc DL = N->getDebugLoc();
14294 unsigned Opc = X86ISD::SHLD;
14295 SDValue Op0 = N0.getOperand(0);
14296 SDValue Op1 = N1.getOperand(0);
14297 if (ShAmt0.getOpcode() == ISD::SUB) {
14298 Opc = X86ISD::SHRD;
14299 std::swap(Op0, Op1);
14300 std::swap(ShAmt0, ShAmt1);
14303 unsigned Bits = VT.getSizeInBits();
14304 if (ShAmt1.getOpcode() == ISD::SUB) {
14305 SDValue Sum = ShAmt1.getOperand(0);
14306 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
14307 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
14308 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
14309 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
14310 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
14311 return DAG.getNode(Opc, DL, VT,
14313 DAG.getNode(ISD::TRUNCATE, DL,
14316 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
14317 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
14319 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
14320 return DAG.getNode(Opc, DL, VT,
14321 N0.getOperand(0), N1.getOperand(0),
14322 DAG.getNode(ISD::TRUNCATE, DL,
14329 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
14330 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
14331 TargetLowering::DAGCombinerInfo &DCI,
14332 const X86Subtarget *Subtarget) {
14333 if (DCI.isBeforeLegalizeOps())
14336 EVT VT = N->getValueType(0);
14338 if (VT != MVT::i32 && VT != MVT::i64)
14341 assert(Subtarget->hasBMI() && "Creating BLSMSK requires BMI instructions");
14343 // Create BLSMSK instructions by finding X ^ (X-1)
14344 SDValue N0 = N->getOperand(0);
14345 SDValue N1 = N->getOperand(1);
14346 DebugLoc DL = N->getDebugLoc();
14348 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
14349 isAllOnes(N0.getOperand(1)))
14350 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N1);
14352 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
14353 isAllOnes(N1.getOperand(1)))
14354 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N0);
14359 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
14360 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
14361 const X86Subtarget *Subtarget) {
14362 LoadSDNode *Ld = cast<LoadSDNode>(N);
14363 EVT RegVT = Ld->getValueType(0);
14364 EVT MemVT = Ld->getMemoryVT();
14365 DebugLoc dl = Ld->getDebugLoc();
14366 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14368 ISD::LoadExtType Ext = Ld->getExtensionType();
14370 // If this is a vector EXT Load then attempt to optimize it using a
14371 // shuffle. We need SSE4 for the shuffles.
14372 // TODO: It is possible to support ZExt by zeroing the undef values
14373 // during the shuffle phase or after the shuffle.
14374 if (RegVT.isVector() && RegVT.isInteger() &&
14375 Ext == ISD::EXTLOAD && Subtarget->hasSSE41()) {
14376 assert(MemVT != RegVT && "Cannot extend to the same type");
14377 assert(MemVT.isVector() && "Must load a vector from memory");
14379 unsigned NumElems = RegVT.getVectorNumElements();
14380 unsigned RegSz = RegVT.getSizeInBits();
14381 unsigned MemSz = MemVT.getSizeInBits();
14382 assert(RegSz > MemSz && "Register size must be greater than the mem size");
14383 // All sizes must be a power of two
14384 if (!isPowerOf2_32(RegSz * MemSz * NumElems)) return SDValue();
14386 // Attempt to load the original value using a single load op.
14387 // Find a scalar type which is equal to the loaded word size.
14388 MVT SclrLoadTy = MVT::i8;
14389 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
14390 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
14391 MVT Tp = (MVT::SimpleValueType)tp;
14392 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() == MemSz) {
14398 // Proceed if a load word is found.
14399 if (SclrLoadTy.getSizeInBits() != MemSz) return SDValue();
14401 EVT LoadUnitVecVT = EVT::getVectorVT(*DAG.getContext(), SclrLoadTy,
14402 RegSz/SclrLoadTy.getSizeInBits());
14404 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
14405 RegSz/MemVT.getScalarType().getSizeInBits());
14406 // Can't shuffle using an illegal type.
14407 if (!TLI.isTypeLegal(WideVecVT)) return SDValue();
14409 // Perform a single load.
14410 SDValue ScalarLoad = DAG.getLoad(SclrLoadTy, dl, Ld->getChain(),
14412 Ld->getPointerInfo(), Ld->isVolatile(),
14413 Ld->isNonTemporal(), Ld->isInvariant(),
14414 Ld->getAlignment());
14416 // Insert the word loaded into a vector.
14417 SDValue ScalarInVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
14418 LoadUnitVecVT, ScalarLoad);
14420 // Bitcast the loaded value to a vector of the original element type, in
14421 // the size of the target vector type.
14422 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT,
14424 unsigned SizeRatio = RegSz/MemSz;
14426 // Redistribute the loaded elements into the different locations.
14427 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
14428 for (unsigned i = 0; i < NumElems; i++) ShuffleVec[i*SizeRatio] = i;
14430 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
14431 DAG.getUNDEF(WideVecVT),
14434 // Bitcast to the requested type.
14435 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
14436 // Replace the original load with the new sequence
14437 // and return the new chain.
14438 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Shuff);
14439 return SDValue(ScalarLoad.getNode(), 1);
14445 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
14446 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
14447 const X86Subtarget *Subtarget) {
14448 StoreSDNode *St = cast<StoreSDNode>(N);
14449 EVT VT = St->getValue().getValueType();
14450 EVT StVT = St->getMemoryVT();
14451 DebugLoc dl = St->getDebugLoc();
14452 SDValue StoredVal = St->getOperand(1);
14453 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14455 // If we are saving a concatenation of two XMM registers, perform two stores.
14456 // This is better in Sandy Bridge cause one 256-bit mem op is done via two
14457 // 128-bit ones. If in the future the cost becomes only one memory access the
14458 // first version would be better.
14459 if (VT.getSizeInBits() == 256 &&
14460 StoredVal.getNode()->getOpcode() == ISD::CONCAT_VECTORS &&
14461 StoredVal.getNumOperands() == 2) {
14463 SDValue Value0 = StoredVal.getOperand(0);
14464 SDValue Value1 = StoredVal.getOperand(1);
14466 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
14467 SDValue Ptr0 = St->getBasePtr();
14468 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
14470 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
14471 St->getPointerInfo(), St->isVolatile(),
14472 St->isNonTemporal(), St->getAlignment());
14473 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
14474 St->getPointerInfo(), St->isVolatile(),
14475 St->isNonTemporal(), St->getAlignment());
14476 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
14479 // Optimize trunc store (of multiple scalars) to shuffle and store.
14480 // First, pack all of the elements in one place. Next, store to memory
14481 // in fewer chunks.
14482 if (St->isTruncatingStore() && VT.isVector()) {
14483 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14484 unsigned NumElems = VT.getVectorNumElements();
14485 assert(StVT != VT && "Cannot truncate to the same type");
14486 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
14487 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
14489 // From, To sizes and ElemCount must be pow of two
14490 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
14491 // We are going to use the original vector elt for storing.
14492 // Accumulated smaller vector elements must be a multiple of the store size.
14493 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
14495 unsigned SizeRatio = FromSz / ToSz;
14497 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
14499 // Create a type on which we perform the shuffle
14500 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
14501 StVT.getScalarType(), NumElems*SizeRatio);
14503 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
14505 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
14506 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
14507 for (unsigned i = 0; i < NumElems; i++ ) ShuffleVec[i] = i * SizeRatio;
14509 // Can't shuffle using an illegal type
14510 if (!TLI.isTypeLegal(WideVecVT)) return SDValue();
14512 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
14513 DAG.getUNDEF(WideVecVT),
14515 // At this point all of the data is stored at the bottom of the
14516 // register. We now need to save it to mem.
14518 // Find the largest store unit
14519 MVT StoreType = MVT::i8;
14520 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
14521 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
14522 MVT Tp = (MVT::SimpleValueType)tp;
14523 if (TLI.isTypeLegal(Tp) && StoreType.getSizeInBits() < NumElems * ToSz)
14527 // Bitcast the original vector into a vector of store-size units
14528 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
14529 StoreType, VT.getSizeInBits()/EVT(StoreType).getSizeInBits());
14530 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
14531 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
14532 SmallVector<SDValue, 8> Chains;
14533 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
14534 TLI.getPointerTy());
14535 SDValue Ptr = St->getBasePtr();
14537 // Perform one or more big stores into memory.
14538 for (unsigned i = 0; i < (ToSz*NumElems)/StoreType.getSizeInBits() ; i++) {
14539 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
14540 StoreType, ShuffWide,
14541 DAG.getIntPtrConstant(i));
14542 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
14543 St->getPointerInfo(), St->isVolatile(),
14544 St->isNonTemporal(), St->getAlignment());
14545 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
14546 Chains.push_back(Ch);
14549 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
14554 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
14555 // the FP state in cases where an emms may be missing.
14556 // A preferable solution to the general problem is to figure out the right
14557 // places to insert EMMS. This qualifies as a quick hack.
14559 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
14560 if (VT.getSizeInBits() != 64)
14563 const Function *F = DAG.getMachineFunction().getFunction();
14564 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
14565 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
14566 && Subtarget->hasSSE2();
14567 if ((VT.isVector() ||
14568 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
14569 isa<LoadSDNode>(St->getValue()) &&
14570 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
14571 St->getChain().hasOneUse() && !St->isVolatile()) {
14572 SDNode* LdVal = St->getValue().getNode();
14573 LoadSDNode *Ld = 0;
14574 int TokenFactorIndex = -1;
14575 SmallVector<SDValue, 8> Ops;
14576 SDNode* ChainVal = St->getChain().getNode();
14577 // Must be a store of a load. We currently handle two cases: the load
14578 // is a direct child, and it's under an intervening TokenFactor. It is
14579 // possible to dig deeper under nested TokenFactors.
14580 if (ChainVal == LdVal)
14581 Ld = cast<LoadSDNode>(St->getChain());
14582 else if (St->getValue().hasOneUse() &&
14583 ChainVal->getOpcode() == ISD::TokenFactor) {
14584 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
14585 if (ChainVal->getOperand(i).getNode() == LdVal) {
14586 TokenFactorIndex = i;
14587 Ld = cast<LoadSDNode>(St->getValue());
14589 Ops.push_back(ChainVal->getOperand(i));
14593 if (!Ld || !ISD::isNormalLoad(Ld))
14596 // If this is not the MMX case, i.e. we are just turning i64 load/store
14597 // into f64 load/store, avoid the transformation if there are multiple
14598 // uses of the loaded value.
14599 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
14602 DebugLoc LdDL = Ld->getDebugLoc();
14603 DebugLoc StDL = N->getDebugLoc();
14604 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
14605 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
14607 if (Subtarget->is64Bit() || F64IsLegal) {
14608 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
14609 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
14610 Ld->getPointerInfo(), Ld->isVolatile(),
14611 Ld->isNonTemporal(), Ld->isInvariant(),
14612 Ld->getAlignment());
14613 SDValue NewChain = NewLd.getValue(1);
14614 if (TokenFactorIndex != -1) {
14615 Ops.push_back(NewChain);
14616 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
14619 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
14620 St->getPointerInfo(),
14621 St->isVolatile(), St->isNonTemporal(),
14622 St->getAlignment());
14625 // Otherwise, lower to two pairs of 32-bit loads / stores.
14626 SDValue LoAddr = Ld->getBasePtr();
14627 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
14628 DAG.getConstant(4, MVT::i32));
14630 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
14631 Ld->getPointerInfo(),
14632 Ld->isVolatile(), Ld->isNonTemporal(),
14633 Ld->isInvariant(), Ld->getAlignment());
14634 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
14635 Ld->getPointerInfo().getWithOffset(4),
14636 Ld->isVolatile(), Ld->isNonTemporal(),
14638 MinAlign(Ld->getAlignment(), 4));
14640 SDValue NewChain = LoLd.getValue(1);
14641 if (TokenFactorIndex != -1) {
14642 Ops.push_back(LoLd);
14643 Ops.push_back(HiLd);
14644 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
14648 LoAddr = St->getBasePtr();
14649 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
14650 DAG.getConstant(4, MVT::i32));
14652 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
14653 St->getPointerInfo(),
14654 St->isVolatile(), St->isNonTemporal(),
14655 St->getAlignment());
14656 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
14657 St->getPointerInfo().getWithOffset(4),
14659 St->isNonTemporal(),
14660 MinAlign(St->getAlignment(), 4));
14661 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
14666 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
14667 /// and return the operands for the horizontal operation in LHS and RHS. A
14668 /// horizontal operation performs the binary operation on successive elements
14669 /// of its first operand, then on successive elements of its second operand,
14670 /// returning the resulting values in a vector. For example, if
14671 /// A = < float a0, float a1, float a2, float a3 >
14673 /// B = < float b0, float b1, float b2, float b3 >
14674 /// then the result of doing a horizontal operation on A and B is
14675 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
14676 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
14677 /// A horizontal-op B, for some already available A and B, and if so then LHS is
14678 /// set to A, RHS to B, and the routine returns 'true'.
14679 /// Note that the binary operation should have the property that if one of the
14680 /// operands is UNDEF then the result is UNDEF.
14681 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
14682 // Look for the following pattern: if
14683 // A = < float a0, float a1, float a2, float a3 >
14684 // B = < float b0, float b1, float b2, float b3 >
14686 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
14687 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
14688 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
14689 // which is A horizontal-op B.
14691 // At least one of the operands should be a vector shuffle.
14692 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
14693 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
14696 EVT VT = LHS.getValueType();
14698 assert((VT.is128BitVector() || VT.is256BitVector()) &&
14699 "Unsupported vector type for horizontal add/sub");
14701 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
14702 // operate independently on 128-bit lanes.
14703 unsigned NumElts = VT.getVectorNumElements();
14704 unsigned NumLanes = VT.getSizeInBits()/128;
14705 unsigned NumLaneElts = NumElts / NumLanes;
14706 assert((NumLaneElts % 2 == 0) &&
14707 "Vector type should have an even number of elements in each lane");
14708 unsigned HalfLaneElts = NumLaneElts/2;
14710 // View LHS in the form
14711 // LHS = VECTOR_SHUFFLE A, B, LMask
14712 // If LHS is not a shuffle then pretend it is the shuffle
14713 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
14714 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
14717 SmallVector<int, 16> LMask(NumElts);
14718 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
14719 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
14720 A = LHS.getOperand(0);
14721 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
14722 B = LHS.getOperand(1);
14723 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
14724 std::copy(Mask.begin(), Mask.end(), LMask.begin());
14726 if (LHS.getOpcode() != ISD::UNDEF)
14728 for (unsigned i = 0; i != NumElts; ++i)
14732 // Likewise, view RHS in the form
14733 // RHS = VECTOR_SHUFFLE C, D, RMask
14735 SmallVector<int, 16> RMask(NumElts);
14736 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
14737 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
14738 C = RHS.getOperand(0);
14739 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
14740 D = RHS.getOperand(1);
14741 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
14742 std::copy(Mask.begin(), Mask.end(), RMask.begin());
14744 if (RHS.getOpcode() != ISD::UNDEF)
14746 for (unsigned i = 0; i != NumElts; ++i)
14750 // Check that the shuffles are both shuffling the same vectors.
14751 if (!(A == C && B == D) && !(A == D && B == C))
14754 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
14755 if (!A.getNode() && !B.getNode())
14758 // If A and B occur in reverse order in RHS, then "swap" them (which means
14759 // rewriting the mask).
14761 CommuteVectorShuffleMask(RMask, NumElts);
14763 // At this point LHS and RHS are equivalent to
14764 // LHS = VECTOR_SHUFFLE A, B, LMask
14765 // RHS = VECTOR_SHUFFLE A, B, RMask
14766 // Check that the masks correspond to performing a horizontal operation.
14767 for (unsigned i = 0; i != NumElts; ++i) {
14768 int LIdx = LMask[i], RIdx = RMask[i];
14770 // Ignore any UNDEF components.
14771 if (LIdx < 0 || RIdx < 0 ||
14772 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
14773 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
14776 // Check that successive elements are being operated on. If not, this is
14777 // not a horizontal operation.
14778 unsigned Src = (i/HalfLaneElts) % 2; // each lane is split between srcs
14779 unsigned LaneStart = (i/NumLaneElts) * NumLaneElts;
14780 int Index = 2*(i%HalfLaneElts) + NumElts*Src + LaneStart;
14781 if (!(LIdx == Index && RIdx == Index + 1) &&
14782 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
14786 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
14787 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
14791 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
14792 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
14793 const X86Subtarget *Subtarget) {
14794 EVT VT = N->getValueType(0);
14795 SDValue LHS = N->getOperand(0);
14796 SDValue RHS = N->getOperand(1);
14798 // Try to synthesize horizontal adds from adds of shuffles.
14799 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
14800 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
14801 isHorizontalBinOp(LHS, RHS, true))
14802 return DAG.getNode(X86ISD::FHADD, N->getDebugLoc(), VT, LHS, RHS);
14806 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
14807 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
14808 const X86Subtarget *Subtarget) {
14809 EVT VT = N->getValueType(0);
14810 SDValue LHS = N->getOperand(0);
14811 SDValue RHS = N->getOperand(1);
14813 // Try to synthesize horizontal subs from subs of shuffles.
14814 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
14815 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
14816 isHorizontalBinOp(LHS, RHS, false))
14817 return DAG.getNode(X86ISD::FHSUB, N->getDebugLoc(), VT, LHS, RHS);
14821 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
14822 /// X86ISD::FXOR nodes.
14823 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
14824 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
14825 // F[X]OR(0.0, x) -> x
14826 // F[X]OR(x, 0.0) -> x
14827 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
14828 if (C->getValueAPF().isPosZero())
14829 return N->getOperand(1);
14830 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
14831 if (C->getValueAPF().isPosZero())
14832 return N->getOperand(0);
14836 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
14837 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
14838 // FAND(0.0, x) -> 0.0
14839 // FAND(x, 0.0) -> 0.0
14840 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
14841 if (C->getValueAPF().isPosZero())
14842 return N->getOperand(0);
14843 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
14844 if (C->getValueAPF().isPosZero())
14845 return N->getOperand(1);
14849 static SDValue PerformBTCombine(SDNode *N,
14851 TargetLowering::DAGCombinerInfo &DCI) {
14852 // BT ignores high bits in the bit index operand.
14853 SDValue Op1 = N->getOperand(1);
14854 if (Op1.hasOneUse()) {
14855 unsigned BitWidth = Op1.getValueSizeInBits();
14856 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
14857 APInt KnownZero, KnownOne;
14858 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
14859 !DCI.isBeforeLegalizeOps());
14860 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14861 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
14862 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
14863 DCI.CommitTargetLoweringOpt(TLO);
14868 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
14869 SDValue Op = N->getOperand(0);
14870 if (Op.getOpcode() == ISD::BITCAST)
14871 Op = Op.getOperand(0);
14872 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
14873 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
14874 VT.getVectorElementType().getSizeInBits() ==
14875 OpVT.getVectorElementType().getSizeInBits()) {
14876 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op);
14881 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
14882 TargetLowering::DAGCombinerInfo &DCI,
14883 const X86Subtarget *Subtarget) {
14884 if (!DCI.isBeforeLegalizeOps())
14887 if (!Subtarget->hasAVX())
14890 EVT VT = N->getValueType(0);
14891 SDValue Op = N->getOperand(0);
14892 EVT OpVT = Op.getValueType();
14893 DebugLoc dl = N->getDebugLoc();
14895 if ((VT == MVT::v4i64 && OpVT == MVT::v4i32) ||
14896 (VT == MVT::v8i32 && OpVT == MVT::v8i16)) {
14898 if (Subtarget->hasAVX2())
14899 return DAG.getNode(X86ISD::VSEXT_MOVL, dl, VT, Op);
14901 // Optimize vectors in AVX mode
14902 // Sign extend v8i16 to v8i32 and
14905 // Divide input vector into two parts
14906 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
14907 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
14908 // concat the vectors to original VT
14910 unsigned NumElems = OpVT.getVectorNumElements();
14911 SmallVector<int,8> ShufMask1(NumElems, -1);
14912 for (unsigned i = 0; i != NumElems/2; ++i)
14915 SDValue OpLo = DAG.getVectorShuffle(OpVT, dl, Op, DAG.getUNDEF(OpVT),
14918 SmallVector<int,8> ShufMask2(NumElems, -1);
14919 for (unsigned i = 0; i != NumElems/2; ++i)
14920 ShufMask2[i] = i + NumElems/2;
14922 SDValue OpHi = DAG.getVectorShuffle(OpVT, dl, Op, DAG.getUNDEF(OpVT),
14925 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), VT.getScalarType(),
14926 VT.getVectorNumElements()/2);
14928 OpLo = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpLo);
14929 OpHi = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpHi);
14931 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
14936 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
14937 TargetLowering::DAGCombinerInfo &DCI,
14938 const X86Subtarget *Subtarget) {
14939 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
14940 // (and (i32 x86isd::setcc_carry), 1)
14941 // This eliminates the zext. This transformation is necessary because
14942 // ISD::SETCC is always legalized to i8.
14943 DebugLoc dl = N->getDebugLoc();
14944 SDValue N0 = N->getOperand(0);
14945 EVT VT = N->getValueType(0);
14946 EVT OpVT = N0.getValueType();
14948 if (N0.getOpcode() == ISD::AND &&
14950 N0.getOperand(0).hasOneUse()) {
14951 SDValue N00 = N0.getOperand(0);
14952 if (N00.getOpcode() != X86ISD::SETCC_CARRY)
14954 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
14955 if (!C || C->getZExtValue() != 1)
14957 return DAG.getNode(ISD::AND, dl, VT,
14958 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
14959 N00.getOperand(0), N00.getOperand(1)),
14960 DAG.getConstant(1, VT));
14963 // Optimize vectors in AVX mode:
14966 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
14967 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
14968 // Concat upper and lower parts.
14971 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
14972 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
14973 // Concat upper and lower parts.
14975 if (!DCI.isBeforeLegalizeOps())
14978 if (!Subtarget->hasAVX())
14981 if (((VT == MVT::v8i32) && (OpVT == MVT::v8i16)) ||
14982 ((VT == MVT::v4i64) && (OpVT == MVT::v4i32))) {
14984 if (Subtarget->hasAVX2())
14985 return DAG.getNode(X86ISD::VZEXT_MOVL, dl, VT, N0);
14987 SDValue ZeroVec = getZeroVector(OpVT, Subtarget, DAG, dl);
14988 SDValue OpLo = getUnpackl(DAG, dl, OpVT, N0, ZeroVec);
14989 SDValue OpHi = getUnpackh(DAG, dl, OpVT, N0, ZeroVec);
14991 EVT HVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
14992 VT.getVectorNumElements()/2);
14994 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
14995 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
14997 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
15003 // Optimize x == -y --> x+y == 0
15004 // x != -y --> x+y != 0
15005 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG) {
15006 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
15007 SDValue LHS = N->getOperand(0);
15008 SDValue RHS = N->getOperand(1);
15010 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
15011 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
15012 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
15013 SDValue addV = DAG.getNode(ISD::ADD, N->getDebugLoc(),
15014 LHS.getValueType(), RHS, LHS.getOperand(1));
15015 return DAG.getSetCC(N->getDebugLoc(), N->getValueType(0),
15016 addV, DAG.getConstant(0, addV.getValueType()), CC);
15018 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
15019 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
15020 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
15021 SDValue addV = DAG.getNode(ISD::ADD, N->getDebugLoc(),
15022 RHS.getValueType(), LHS, RHS.getOperand(1));
15023 return DAG.getSetCC(N->getDebugLoc(), N->getValueType(0),
15024 addV, DAG.getConstant(0, addV.getValueType()), CC);
15029 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
15030 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG) {
15031 unsigned X86CC = N->getConstantOperandVal(0);
15032 SDValue EFLAG = N->getOperand(1);
15033 DebugLoc DL = N->getDebugLoc();
15035 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
15036 // a zext and produces an all-ones bit which is more useful than 0/1 in some
15038 if (X86CC == X86::COND_B)
15039 return DAG.getNode(ISD::AND, DL, MVT::i8,
15040 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
15041 DAG.getConstant(X86CC, MVT::i8), EFLAG),
15042 DAG.getConstant(1, MVT::i8));
15047 static SDValue PerformUINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG) {
15048 SDValue Op0 = N->getOperand(0);
15049 EVT InVT = Op0->getValueType(0);
15051 // UINT_TO_FP(v4i8) -> SINT_TO_FP(ZEXT(v4i8 to v4i32))
15052 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
15053 DebugLoc dl = N->getDebugLoc();
15054 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
15055 SDValue P = DAG.getNode(ISD::ZERO_EXTEND, dl, DstVT, Op0);
15056 // Notice that we use SINT_TO_FP because we know that the high bits
15057 // are zero and SINT_TO_FP is better supported by the hardware.
15058 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
15064 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
15065 const X86TargetLowering *XTLI) {
15066 SDValue Op0 = N->getOperand(0);
15067 EVT InVT = Op0->getValueType(0);
15069 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
15070 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
15071 DebugLoc dl = N->getDebugLoc();
15072 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
15073 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
15074 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
15077 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
15078 // a 32-bit target where SSE doesn't support i64->FP operations.
15079 if (Op0.getOpcode() == ISD::LOAD) {
15080 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
15081 EVT VT = Ld->getValueType(0);
15082 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
15083 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
15084 !XTLI->getSubtarget()->is64Bit() &&
15085 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
15086 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
15087 Ld->getChain(), Op0, DAG);
15088 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
15095 static SDValue PerformFP_TO_SINTCombine(SDNode *N, SelectionDAG &DAG) {
15096 EVT VT = N->getValueType(0);
15098 // v4i8 = FP_TO_SINT() -> v4i8 = TRUNCATE (V4i32 = FP_TO_SINT()
15099 if (VT == MVT::v8i8 || VT == MVT::v4i8) {
15100 DebugLoc dl = N->getDebugLoc();
15101 MVT DstVT = VT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
15102 SDValue I = DAG.getNode(ISD::FP_TO_SINT, dl, DstVT, N->getOperand(0));
15103 return DAG.getNode(ISD::TRUNCATE, dl, VT, I);
15109 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
15110 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
15111 X86TargetLowering::DAGCombinerInfo &DCI) {
15112 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
15113 // the result is either zero or one (depending on the input carry bit).
15114 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
15115 if (X86::isZeroNode(N->getOperand(0)) &&
15116 X86::isZeroNode(N->getOperand(1)) &&
15117 // We don't have a good way to replace an EFLAGS use, so only do this when
15119 SDValue(N, 1).use_empty()) {
15120 DebugLoc DL = N->getDebugLoc();
15121 EVT VT = N->getValueType(0);
15122 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
15123 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
15124 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
15125 DAG.getConstant(X86::COND_B,MVT::i8),
15127 DAG.getConstant(1, VT));
15128 return DCI.CombineTo(N, Res1, CarryOut);
15134 // fold (add Y, (sete X, 0)) -> adc 0, Y
15135 // (add Y, (setne X, 0)) -> sbb -1, Y
15136 // (sub (sete X, 0), Y) -> sbb 0, Y
15137 // (sub (setne X, 0), Y) -> adc -1, Y
15138 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
15139 DebugLoc DL = N->getDebugLoc();
15141 // Look through ZExts.
15142 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
15143 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
15146 SDValue SetCC = Ext.getOperand(0);
15147 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
15150 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
15151 if (CC != X86::COND_E && CC != X86::COND_NE)
15154 SDValue Cmp = SetCC.getOperand(1);
15155 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
15156 !X86::isZeroNode(Cmp.getOperand(1)) ||
15157 !Cmp.getOperand(0).getValueType().isInteger())
15160 SDValue CmpOp0 = Cmp.getOperand(0);
15161 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
15162 DAG.getConstant(1, CmpOp0.getValueType()));
15164 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
15165 if (CC == X86::COND_NE)
15166 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
15167 DL, OtherVal.getValueType(), OtherVal,
15168 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
15169 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
15170 DL, OtherVal.getValueType(), OtherVal,
15171 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
15174 /// PerformADDCombine - Do target-specific dag combines on integer adds.
15175 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
15176 const X86Subtarget *Subtarget) {
15177 EVT VT = N->getValueType(0);
15178 SDValue Op0 = N->getOperand(0);
15179 SDValue Op1 = N->getOperand(1);
15181 // Try to synthesize horizontal adds from adds of shuffles.
15182 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
15183 (Subtarget->hasAVX2() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
15184 isHorizontalBinOp(Op0, Op1, true))
15185 return DAG.getNode(X86ISD::HADD, N->getDebugLoc(), VT, Op0, Op1);
15187 return OptimizeConditionalInDecrement(N, DAG);
15190 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
15191 const X86Subtarget *Subtarget) {
15192 SDValue Op0 = N->getOperand(0);
15193 SDValue Op1 = N->getOperand(1);
15195 // X86 can't encode an immediate LHS of a sub. See if we can push the
15196 // negation into a preceding instruction.
15197 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
15198 // If the RHS of the sub is a XOR with one use and a constant, invert the
15199 // immediate. Then add one to the LHS of the sub so we can turn
15200 // X-Y -> X+~Y+1, saving one register.
15201 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
15202 isa<ConstantSDNode>(Op1.getOperand(1))) {
15203 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
15204 EVT VT = Op0.getValueType();
15205 SDValue NewXor = DAG.getNode(ISD::XOR, Op1.getDebugLoc(), VT,
15207 DAG.getConstant(~XorC, VT));
15208 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, NewXor,
15209 DAG.getConstant(C->getAPIntValue()+1, VT));
15213 // Try to synthesize horizontal adds from adds of shuffles.
15214 EVT VT = N->getValueType(0);
15215 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
15216 (Subtarget->hasAVX2() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
15217 isHorizontalBinOp(Op0, Op1, true))
15218 return DAG.getNode(X86ISD::HSUB, N->getDebugLoc(), VT, Op0, Op1);
15220 return OptimizeConditionalInDecrement(N, DAG);
15223 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
15224 DAGCombinerInfo &DCI) const {
15225 SelectionDAG &DAG = DCI.DAG;
15226 switch (N->getOpcode()) {
15228 case ISD::EXTRACT_VECTOR_ELT:
15229 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
15231 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget);
15232 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI);
15233 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
15234 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
15235 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
15236 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
15239 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
15240 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
15241 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
15242 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
15243 case ISD::LOAD: return PerformLOADCombine(N, DAG, Subtarget);
15244 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
15245 case ISD::UINT_TO_FP: return PerformUINT_TO_FPCombine(N, DAG);
15246 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
15247 case ISD::FP_TO_SINT: return PerformFP_TO_SINTCombine(N, DAG);
15248 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
15249 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
15251 case X86ISD::FOR: return PerformFORCombine(N, DAG);
15252 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
15253 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
15254 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
15255 case ISD::ANY_EXTEND:
15256 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
15257 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
15258 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG, DCI);
15259 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG);
15260 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG);
15261 case X86ISD::SHUFP: // Handle all target specific shuffles
15262 case X86ISD::PALIGN:
15263 case X86ISD::UNPCKH:
15264 case X86ISD::UNPCKL:
15265 case X86ISD::MOVHLPS:
15266 case X86ISD::MOVLHPS:
15267 case X86ISD::PSHUFD:
15268 case X86ISD::PSHUFHW:
15269 case X86ISD::PSHUFLW:
15270 case X86ISD::MOVSS:
15271 case X86ISD::MOVSD:
15272 case X86ISD::VPERMILP:
15273 case X86ISD::VPERM2X128:
15274 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
15280 /// isTypeDesirableForOp - Return true if the target has native support for
15281 /// the specified value type and it is 'desirable' to use the type for the
15282 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
15283 /// instruction encodings are longer and some i16 instructions are slow.
15284 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
15285 if (!isTypeLegal(VT))
15287 if (VT != MVT::i16)
15294 case ISD::SIGN_EXTEND:
15295 case ISD::ZERO_EXTEND:
15296 case ISD::ANY_EXTEND:
15309 /// IsDesirableToPromoteOp - This method query the target whether it is
15310 /// beneficial for dag combiner to promote the specified node. If true, it
15311 /// should return the desired promotion type by reference.
15312 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
15313 EVT VT = Op.getValueType();
15314 if (VT != MVT::i16)
15317 bool Promote = false;
15318 bool Commute = false;
15319 switch (Op.getOpcode()) {
15322 LoadSDNode *LD = cast<LoadSDNode>(Op);
15323 // If the non-extending load has a single use and it's not live out, then it
15324 // might be folded.
15325 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
15326 Op.hasOneUse()*/) {
15327 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
15328 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
15329 // The only case where we'd want to promote LOAD (rather then it being
15330 // promoted as an operand is when it's only use is liveout.
15331 if (UI->getOpcode() != ISD::CopyToReg)
15338 case ISD::SIGN_EXTEND:
15339 case ISD::ZERO_EXTEND:
15340 case ISD::ANY_EXTEND:
15345 SDValue N0 = Op.getOperand(0);
15346 // Look out for (store (shl (load), x)).
15347 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
15360 SDValue N0 = Op.getOperand(0);
15361 SDValue N1 = Op.getOperand(1);
15362 if (!Commute && MayFoldLoad(N1))
15364 // Avoid disabling potential load folding opportunities.
15365 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
15367 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
15377 //===----------------------------------------------------------------------===//
15378 // X86 Inline Assembly Support
15379 //===----------------------------------------------------------------------===//
15382 // Helper to match a string separated by whitespace.
15383 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
15384 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
15386 for (unsigned i = 0, e = args.size(); i != e; ++i) {
15387 StringRef piece(*args[i]);
15388 if (!s.startswith(piece)) // Check if the piece matches.
15391 s = s.substr(piece.size());
15392 StringRef::size_type pos = s.find_first_not_of(" \t");
15393 if (pos == 0) // We matched a prefix.
15401 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
15404 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
15405 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
15407 std::string AsmStr = IA->getAsmString();
15409 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
15410 if (!Ty || Ty->getBitWidth() % 16 != 0)
15413 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
15414 SmallVector<StringRef, 4> AsmPieces;
15415 SplitString(AsmStr, AsmPieces, ";\n");
15417 switch (AsmPieces.size()) {
15418 default: return false;
15420 // FIXME: this should verify that we are targeting a 486 or better. If not,
15421 // we will turn this bswap into something that will be lowered to logical
15422 // ops instead of emitting the bswap asm. For now, we don't support 486 or
15423 // lower so don't worry about this.
15425 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
15426 matchAsm(AsmPieces[0], "bswapl", "$0") ||
15427 matchAsm(AsmPieces[0], "bswapq", "$0") ||
15428 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
15429 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
15430 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
15431 // No need to check constraints, nothing other than the equivalent of
15432 // "=r,0" would be valid here.
15433 return IntrinsicLowering::LowerToByteSwap(CI);
15436 // rorw $$8, ${0:w} --> llvm.bswap.i16
15437 if (CI->getType()->isIntegerTy(16) &&
15438 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
15439 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
15440 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
15442 const std::string &ConstraintsStr = IA->getConstraintString();
15443 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
15444 std::sort(AsmPieces.begin(), AsmPieces.end());
15445 if (AsmPieces.size() == 4 &&
15446 AsmPieces[0] == "~{cc}" &&
15447 AsmPieces[1] == "~{dirflag}" &&
15448 AsmPieces[2] == "~{flags}" &&
15449 AsmPieces[3] == "~{fpsr}")
15450 return IntrinsicLowering::LowerToByteSwap(CI);
15454 if (CI->getType()->isIntegerTy(32) &&
15455 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
15456 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
15457 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
15458 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
15460 const std::string &ConstraintsStr = IA->getConstraintString();
15461 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
15462 std::sort(AsmPieces.begin(), AsmPieces.end());
15463 if (AsmPieces.size() == 4 &&
15464 AsmPieces[0] == "~{cc}" &&
15465 AsmPieces[1] == "~{dirflag}" &&
15466 AsmPieces[2] == "~{flags}" &&
15467 AsmPieces[3] == "~{fpsr}")
15468 return IntrinsicLowering::LowerToByteSwap(CI);
15471 if (CI->getType()->isIntegerTy(64)) {
15472 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
15473 if (Constraints.size() >= 2 &&
15474 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
15475 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
15476 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
15477 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
15478 matchAsm(AsmPieces[1], "bswap", "%edx") &&
15479 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
15480 return IntrinsicLowering::LowerToByteSwap(CI);
15490 /// getConstraintType - Given a constraint letter, return the type of
15491 /// constraint it is for this target.
15492 X86TargetLowering::ConstraintType
15493 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
15494 if (Constraint.size() == 1) {
15495 switch (Constraint[0]) {
15506 return C_RegisterClass;
15530 return TargetLowering::getConstraintType(Constraint);
15533 /// Examine constraint type and operand type and determine a weight value.
15534 /// This object must already have been set up with the operand type
15535 /// and the current alternative constraint selected.
15536 TargetLowering::ConstraintWeight
15537 X86TargetLowering::getSingleConstraintMatchWeight(
15538 AsmOperandInfo &info, const char *constraint) const {
15539 ConstraintWeight weight = CW_Invalid;
15540 Value *CallOperandVal = info.CallOperandVal;
15541 // If we don't have a value, we can't do a match,
15542 // but allow it at the lowest weight.
15543 if (CallOperandVal == NULL)
15545 Type *type = CallOperandVal->getType();
15546 // Look at the constraint type.
15547 switch (*constraint) {
15549 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
15560 if (CallOperandVal->getType()->isIntegerTy())
15561 weight = CW_SpecificReg;
15566 if (type->isFloatingPointTy())
15567 weight = CW_SpecificReg;
15570 if (type->isX86_MMXTy() && Subtarget->hasMMX())
15571 weight = CW_SpecificReg;
15575 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
15576 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasAVX()))
15577 weight = CW_Register;
15580 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
15581 if (C->getZExtValue() <= 31)
15582 weight = CW_Constant;
15586 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15587 if (C->getZExtValue() <= 63)
15588 weight = CW_Constant;
15592 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15593 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
15594 weight = CW_Constant;
15598 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15599 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
15600 weight = CW_Constant;
15604 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15605 if (C->getZExtValue() <= 3)
15606 weight = CW_Constant;
15610 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15611 if (C->getZExtValue() <= 0xff)
15612 weight = CW_Constant;
15617 if (dyn_cast<ConstantFP>(CallOperandVal)) {
15618 weight = CW_Constant;
15622 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15623 if ((C->getSExtValue() >= -0x80000000LL) &&
15624 (C->getSExtValue() <= 0x7fffffffLL))
15625 weight = CW_Constant;
15629 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15630 if (C->getZExtValue() <= 0xffffffff)
15631 weight = CW_Constant;
15638 /// LowerXConstraint - try to replace an X constraint, which matches anything,
15639 /// with another that has more specific requirements based on the type of the
15640 /// corresponding operand.
15641 const char *X86TargetLowering::
15642 LowerXConstraint(EVT ConstraintVT) const {
15643 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
15644 // 'f' like normal targets.
15645 if (ConstraintVT.isFloatingPoint()) {
15646 if (Subtarget->hasSSE2())
15648 if (Subtarget->hasSSE1())
15652 return TargetLowering::LowerXConstraint(ConstraintVT);
15655 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
15656 /// vector. If it is invalid, don't add anything to Ops.
15657 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
15658 std::string &Constraint,
15659 std::vector<SDValue>&Ops,
15660 SelectionDAG &DAG) const {
15661 SDValue Result(0, 0);
15663 // Only support length 1 constraints for now.
15664 if (Constraint.length() > 1) return;
15666 char ConstraintLetter = Constraint[0];
15667 switch (ConstraintLetter) {
15670 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15671 if (C->getZExtValue() <= 31) {
15672 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15678 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15679 if (C->getZExtValue() <= 63) {
15680 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15686 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15687 if ((int8_t)C->getSExtValue() == C->getSExtValue()) {
15688 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15694 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15695 if (C->getZExtValue() <= 255) {
15696 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15702 // 32-bit signed value
15703 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15704 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
15705 C->getSExtValue())) {
15706 // Widen to 64 bits here to get it sign extended.
15707 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
15710 // FIXME gcc accepts some relocatable values here too, but only in certain
15711 // memory models; it's complicated.
15716 // 32-bit unsigned value
15717 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15718 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
15719 C->getZExtValue())) {
15720 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15724 // FIXME gcc accepts some relocatable values here too, but only in certain
15725 // memory models; it's complicated.
15729 // Literal immediates are always ok.
15730 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
15731 // Widen to 64 bits here to get it sign extended.
15732 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
15736 // In any sort of PIC mode addresses need to be computed at runtime by
15737 // adding in a register or some sort of table lookup. These can't
15738 // be used as immediates.
15739 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
15742 // If we are in non-pic codegen mode, we allow the address of a global (with
15743 // an optional displacement) to be used with 'i'.
15744 GlobalAddressSDNode *GA = 0;
15745 int64_t Offset = 0;
15747 // Match either (GA), (GA+C), (GA+C1+C2), etc.
15749 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
15750 Offset += GA->getOffset();
15752 } else if (Op.getOpcode() == ISD::ADD) {
15753 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
15754 Offset += C->getZExtValue();
15755 Op = Op.getOperand(0);
15758 } else if (Op.getOpcode() == ISD::SUB) {
15759 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
15760 Offset += -C->getZExtValue();
15761 Op = Op.getOperand(0);
15766 // Otherwise, this isn't something we can handle, reject it.
15770 const GlobalValue *GV = GA->getGlobal();
15771 // If we require an extra load to get this address, as in PIC mode, we
15772 // can't accept it.
15773 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
15774 getTargetMachine())))
15777 Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(),
15778 GA->getValueType(0), Offset);
15783 if (Result.getNode()) {
15784 Ops.push_back(Result);
15787 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
15790 std::pair<unsigned, const TargetRegisterClass*>
15791 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
15793 // First, see if this is a constraint that directly corresponds to an LLVM
15795 if (Constraint.size() == 1) {
15796 // GCC Constraint Letters
15797 switch (Constraint[0]) {
15799 // TODO: Slight differences here in allocation order and leaving
15800 // RIP in the class. Do they matter any more here than they do
15801 // in the normal allocation?
15802 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
15803 if (Subtarget->is64Bit()) {
15804 if (VT == MVT::i32 || VT == MVT::f32)
15805 return std::make_pair(0U, &X86::GR32RegClass);
15806 if (VT == MVT::i16)
15807 return std::make_pair(0U, &X86::GR16RegClass);
15808 if (VT == MVT::i8 || VT == MVT::i1)
15809 return std::make_pair(0U, &X86::GR8RegClass);
15810 if (VT == MVT::i64 || VT == MVT::f64)
15811 return std::make_pair(0U, &X86::GR64RegClass);
15814 // 32-bit fallthrough
15815 case 'Q': // Q_REGS
15816 if (VT == MVT::i32 || VT == MVT::f32)
15817 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
15818 if (VT == MVT::i16)
15819 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
15820 if (VT == MVT::i8 || VT == MVT::i1)
15821 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
15822 if (VT == MVT::i64)
15823 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
15825 case 'r': // GENERAL_REGS
15826 case 'l': // INDEX_REGS
15827 if (VT == MVT::i8 || VT == MVT::i1)
15828 return std::make_pair(0U, &X86::GR8RegClass);
15829 if (VT == MVT::i16)
15830 return std::make_pair(0U, &X86::GR16RegClass);
15831 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
15832 return std::make_pair(0U, &X86::GR32RegClass);
15833 return std::make_pair(0U, &X86::GR64RegClass);
15834 case 'R': // LEGACY_REGS
15835 if (VT == MVT::i8 || VT == MVT::i1)
15836 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
15837 if (VT == MVT::i16)
15838 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
15839 if (VT == MVT::i32 || !Subtarget->is64Bit())
15840 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
15841 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
15842 case 'f': // FP Stack registers.
15843 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
15844 // value to the correct fpstack register class.
15845 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
15846 return std::make_pair(0U, &X86::RFP32RegClass);
15847 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
15848 return std::make_pair(0U, &X86::RFP64RegClass);
15849 return std::make_pair(0U, &X86::RFP80RegClass);
15850 case 'y': // MMX_REGS if MMX allowed.
15851 if (!Subtarget->hasMMX()) break;
15852 return std::make_pair(0U, &X86::VR64RegClass);
15853 case 'Y': // SSE_REGS if SSE2 allowed
15854 if (!Subtarget->hasSSE2()) break;
15856 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
15857 if (!Subtarget->hasSSE1()) break;
15859 switch (VT.getSimpleVT().SimpleTy) {
15861 // Scalar SSE types.
15864 return std::make_pair(0U, &X86::FR32RegClass);
15867 return std::make_pair(0U, &X86::FR64RegClass);
15875 return std::make_pair(0U, &X86::VR128RegClass);
15883 return std::make_pair(0U, &X86::VR256RegClass);
15889 // Use the default implementation in TargetLowering to convert the register
15890 // constraint into a member of a register class.
15891 std::pair<unsigned, const TargetRegisterClass*> Res;
15892 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
15894 // Not found as a standard register?
15895 if (Res.second == 0) {
15896 // Map st(0) -> st(7) -> ST0
15897 if (Constraint.size() == 7 && Constraint[0] == '{' &&
15898 tolower(Constraint[1]) == 's' &&
15899 tolower(Constraint[2]) == 't' &&
15900 Constraint[3] == '(' &&
15901 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
15902 Constraint[5] == ')' &&
15903 Constraint[6] == '}') {
15905 Res.first = X86::ST0+Constraint[4]-'0';
15906 Res.second = &X86::RFP80RegClass;
15910 // GCC allows "st(0)" to be called just plain "st".
15911 if (StringRef("{st}").equals_lower(Constraint)) {
15912 Res.first = X86::ST0;
15913 Res.second = &X86::RFP80RegClass;
15918 if (StringRef("{flags}").equals_lower(Constraint)) {
15919 Res.first = X86::EFLAGS;
15920 Res.second = &X86::CCRRegClass;
15924 // 'A' means EAX + EDX.
15925 if (Constraint == "A") {
15926 Res.first = X86::EAX;
15927 Res.second = &X86::GR32_ADRegClass;
15933 // Otherwise, check to see if this is a register class of the wrong value
15934 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
15935 // turn into {ax},{dx}.
15936 if (Res.second->hasType(VT))
15937 return Res; // Correct type already, nothing to do.
15939 // All of the single-register GCC register classes map their values onto
15940 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
15941 // really want an 8-bit or 32-bit register, map to the appropriate register
15942 // class and return the appropriate register.
15943 if (Res.second == &X86::GR16RegClass) {
15944 if (VT == MVT::i8) {
15945 unsigned DestReg = 0;
15946 switch (Res.first) {
15948 case X86::AX: DestReg = X86::AL; break;
15949 case X86::DX: DestReg = X86::DL; break;
15950 case X86::CX: DestReg = X86::CL; break;
15951 case X86::BX: DestReg = X86::BL; break;
15954 Res.first = DestReg;
15955 Res.second = &X86::GR8RegClass;
15957 } else if (VT == MVT::i32) {
15958 unsigned DestReg = 0;
15959 switch (Res.first) {
15961 case X86::AX: DestReg = X86::EAX; break;
15962 case X86::DX: DestReg = X86::EDX; break;
15963 case X86::CX: DestReg = X86::ECX; break;
15964 case X86::BX: DestReg = X86::EBX; break;
15965 case X86::SI: DestReg = X86::ESI; break;
15966 case X86::DI: DestReg = X86::EDI; break;
15967 case X86::BP: DestReg = X86::EBP; break;
15968 case X86::SP: DestReg = X86::ESP; break;
15971 Res.first = DestReg;
15972 Res.second = &X86::GR32RegClass;
15974 } else if (VT == MVT::i64) {
15975 unsigned DestReg = 0;
15976 switch (Res.first) {
15978 case X86::AX: DestReg = X86::RAX; break;
15979 case X86::DX: DestReg = X86::RDX; break;
15980 case X86::CX: DestReg = X86::RCX; break;
15981 case X86::BX: DestReg = X86::RBX; break;
15982 case X86::SI: DestReg = X86::RSI; break;
15983 case X86::DI: DestReg = X86::RDI; break;
15984 case X86::BP: DestReg = X86::RBP; break;
15985 case X86::SP: DestReg = X86::RSP; break;
15988 Res.first = DestReg;
15989 Res.second = &X86::GR64RegClass;
15992 } else if (Res.second == &X86::FR32RegClass ||
15993 Res.second == &X86::FR64RegClass ||
15994 Res.second == &X86::VR128RegClass) {
15995 // Handle references to XMM physical registers that got mapped into the
15996 // wrong class. This can happen with constraints like {xmm0} where the
15997 // target independent register mapper will just pick the first match it can
15998 // find, ignoring the required type.
15999 if (VT == MVT::f32)
16000 Res.second = &X86::FR32RegClass;
16001 else if (VT == MVT::f64)
16002 Res.second = &X86::FR64RegClass;
16003 else if (X86::VR128RegClass.hasType(VT))
16004 Res.second = &X86::VR128RegClass;