1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
16 #include "X86ISelLowering.h"
17 #include "Utils/X86ShuffleDecode.h"
19 #include "X86CallingConv.h"
20 #include "X86InstrBuilder.h"
21 #include "X86TargetMachine.h"
22 #include "X86TargetObjectFile.h"
23 #include "llvm/ADT/SmallSet.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/ADT/VariadicFunction.h"
27 #include "llvm/CodeGen/IntrinsicLowering.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineJumpTableInfo.h"
32 #include "llvm/CodeGen/MachineModuleInfo.h"
33 #include "llvm/CodeGen/MachineRegisterInfo.h"
34 #include "llvm/IR/CallingConv.h"
35 #include "llvm/IR/Constants.h"
36 #include "llvm/IR/DerivedTypes.h"
37 #include "llvm/IR/Function.h"
38 #include "llvm/IR/GlobalAlias.h"
39 #include "llvm/IR/GlobalVariable.h"
40 #include "llvm/IR/Instructions.h"
41 #include "llvm/IR/Intrinsics.h"
42 #include "llvm/IR/LLVMContext.h"
43 #include "llvm/MC/MCAsmInfo.h"
44 #include "llvm/MC/MCContext.h"
45 #include "llvm/MC/MCExpr.h"
46 #include "llvm/MC/MCSymbol.h"
47 #include "llvm/Support/CallSite.h"
48 #include "llvm/Support/Debug.h"
49 #include "llvm/Support/ErrorHandling.h"
50 #include "llvm/Support/MathExtras.h"
51 #include "llvm/Target/TargetOptions.h"
56 STATISTIC(NumTailCalls, "Number of tail calls");
58 // Forward declarations.
59 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
62 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
63 SelectionDAG &DAG, SDLoc dl,
64 unsigned vectorWidth) {
65 assert((vectorWidth == 128 || vectorWidth == 256) &&
66 "Unsupported vector width");
67 EVT VT = Vec.getValueType();
68 EVT ElVT = VT.getVectorElementType();
69 unsigned Factor = VT.getSizeInBits()/vectorWidth;
70 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
71 VT.getVectorNumElements()/Factor);
73 // Extract from UNDEF is UNDEF.
74 if (Vec.getOpcode() == ISD::UNDEF)
75 return DAG.getUNDEF(ResultVT);
77 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
78 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
80 // This is the index of the first element of the vectorWidth-bit chunk
82 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
85 // If the input is a buildvector just emit a smaller one.
86 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
87 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
88 Vec->op_begin()+NormalizedIdxVal, ElemsPerChunk);
90 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
91 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
97 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
98 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
99 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
100 /// instructions or a simple subregister reference. Idx is an index in the
101 /// 128 bits we want. It need not be aligned to a 128-bit bounday. That makes
102 /// lowering EXTRACT_VECTOR_ELT operations easier.
103 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
104 SelectionDAG &DAG, SDLoc dl) {
105 assert((Vec.getValueType().is256BitVector() ||
106 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
107 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
110 /// Generate a DAG to grab 256-bits from a 512-bit vector.
111 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
112 SelectionDAG &DAG, SDLoc dl) {
113 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
114 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
117 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
118 unsigned IdxVal, SelectionDAG &DAG,
119 SDLoc dl, unsigned vectorWidth) {
120 assert((vectorWidth == 128 || vectorWidth == 256) &&
121 "Unsupported vector width");
122 // Inserting UNDEF is Result
123 if (Vec.getOpcode() == ISD::UNDEF)
125 EVT VT = Vec.getValueType();
126 EVT ElVT = VT.getVectorElementType();
127 EVT ResultVT = Result.getValueType();
129 // Insert the relevant vectorWidth bits.
130 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
132 // This is the index of the first element of the vectorWidth-bit chunk
134 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
137 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
138 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
141 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
142 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
143 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
144 /// simple superregister reference. Idx is an index in the 128 bits
145 /// we want. It need not be aligned to a 128-bit bounday. That makes
146 /// lowering INSERT_VECTOR_ELT operations easier.
147 static SDValue Insert128BitVector(SDValue Result, SDValue Vec,
148 unsigned IdxVal, SelectionDAG &DAG,
150 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
151 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
154 static SDValue Insert256BitVector(SDValue Result, SDValue Vec,
155 unsigned IdxVal, SelectionDAG &DAG,
157 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
158 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
161 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
162 /// instructions. This is used because creating CONCAT_VECTOR nodes of
163 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
164 /// large BUILD_VECTORS.
165 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
166 unsigned NumElems, SelectionDAG &DAG,
168 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
169 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
172 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
173 unsigned NumElems, SelectionDAG &DAG,
175 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
176 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
179 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
180 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
181 bool is64Bit = Subtarget->is64Bit();
183 if (Subtarget->isTargetEnvMacho()) {
185 return new X86_64MachoTargetObjectFile();
186 return new TargetLoweringObjectFileMachO();
189 if (Subtarget->isTargetLinux())
190 return new X86LinuxTargetObjectFile();
191 if (Subtarget->isTargetELF())
192 return new TargetLoweringObjectFileELF();
193 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
194 return new TargetLoweringObjectFileCOFF();
195 llvm_unreachable("unknown subtarget type");
198 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
199 : TargetLowering(TM, createTLOF(TM)) {
200 Subtarget = &TM.getSubtarget<X86Subtarget>();
201 X86ScalarSSEf64 = Subtarget->hasSSE2();
202 X86ScalarSSEf32 = Subtarget->hasSSE1();
203 TD = getDataLayout();
205 resetOperationActions();
208 void X86TargetLowering::resetOperationActions() {
209 const TargetMachine &TM = getTargetMachine();
210 static bool FirstTimeThrough = true;
212 // If none of the target options have changed, then we don't need to reset the
213 // operation actions.
214 if (!FirstTimeThrough && TO == TM.Options) return;
216 if (!FirstTimeThrough) {
217 // Reinitialize the actions.
219 FirstTimeThrough = false;
224 // Set up the TargetLowering object.
225 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
227 // X86 is weird, it always uses i8 for shift amounts and setcc results.
228 setBooleanContents(ZeroOrOneBooleanContent);
229 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
230 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
232 // For 64-bit since we have so many registers use the ILP scheduler, for
233 // 32-bit code use the register pressure specific scheduling.
234 // For Atom, always use ILP scheduling.
235 if (Subtarget->isAtom())
236 setSchedulingPreference(Sched::ILP);
237 else if (Subtarget->is64Bit())
238 setSchedulingPreference(Sched::ILP);
240 setSchedulingPreference(Sched::RegPressure);
241 const X86RegisterInfo *RegInfo =
242 static_cast<const X86RegisterInfo*>(TM.getRegisterInfo());
243 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
245 // Bypass expensive divides on Atom when compiling with O2
246 if (Subtarget->hasSlowDivide() && TM.getOptLevel() >= CodeGenOpt::Default) {
247 addBypassSlowDiv(32, 8);
248 if (Subtarget->is64Bit())
249 addBypassSlowDiv(64, 16);
252 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) {
253 // Setup Windows compiler runtime calls.
254 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
255 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
256 setLibcallName(RTLIB::SREM_I64, "_allrem");
257 setLibcallName(RTLIB::UREM_I64, "_aullrem");
258 setLibcallName(RTLIB::MUL_I64, "_allmul");
259 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
260 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
261 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
262 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
263 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
265 // The _ftol2 runtime function has an unusual calling conv, which
266 // is modeled by a special pseudo-instruction.
267 setLibcallName(RTLIB::FPTOUINT_F64_I64, 0);
268 setLibcallName(RTLIB::FPTOUINT_F32_I64, 0);
269 setLibcallName(RTLIB::FPTOUINT_F64_I32, 0);
270 setLibcallName(RTLIB::FPTOUINT_F32_I32, 0);
273 if (Subtarget->isTargetDarwin()) {
274 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
275 setUseUnderscoreSetJmp(false);
276 setUseUnderscoreLongJmp(false);
277 } else if (Subtarget->isTargetMingw()) {
278 // MS runtime is weird: it exports _setjmp, but longjmp!
279 setUseUnderscoreSetJmp(true);
280 setUseUnderscoreLongJmp(false);
282 setUseUnderscoreSetJmp(true);
283 setUseUnderscoreLongJmp(true);
286 // Set up the register classes.
287 addRegisterClass(MVT::i8, &X86::GR8RegClass);
288 addRegisterClass(MVT::i16, &X86::GR16RegClass);
289 addRegisterClass(MVT::i32, &X86::GR32RegClass);
290 if (Subtarget->is64Bit())
291 addRegisterClass(MVT::i64, &X86::GR64RegClass);
293 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
295 // We don't accept any truncstore of integer registers.
296 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
297 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
298 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
299 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
300 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
301 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
303 // SETOEQ and SETUNE require checking two conditions.
304 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
305 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
306 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
307 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
308 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
309 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
311 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
313 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
314 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
315 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
317 if (Subtarget->is64Bit()) {
318 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
319 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
320 } else if (!TM.Options.UseSoftFloat) {
321 // We have an algorithm for SSE2->double, and we turn this into a
322 // 64-bit FILD followed by conditional FADD for other targets.
323 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
324 // We have an algorithm for SSE2, and we turn this into a 64-bit
325 // FILD for other targets.
326 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
329 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
331 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
332 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
334 if (!TM.Options.UseSoftFloat) {
335 // SSE has no i16 to fp conversion, only i32
336 if (X86ScalarSSEf32) {
337 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
338 // f32 and f64 cases are Legal, f80 case is not
339 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
341 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
342 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
345 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
346 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
349 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
350 // are Legal, f80 is custom lowered.
351 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
352 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
354 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
356 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
357 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
359 if (X86ScalarSSEf32) {
360 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
361 // f32 and f64 cases are Legal, f80 case is not
362 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
364 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
365 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
368 // Handle FP_TO_UINT by promoting the destination to a larger signed
370 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
371 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
372 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
374 if (Subtarget->is64Bit()) {
375 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
376 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
377 } else if (!TM.Options.UseSoftFloat) {
378 // Since AVX is a superset of SSE3, only check for SSE here.
379 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
380 // Expand FP_TO_UINT into a select.
381 // FIXME: We would like to use a Custom expander here eventually to do
382 // the optimal thing for SSE vs. the default expansion in the legalizer.
383 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
385 // With SSE3 we can use fisttpll to convert to a signed i64; without
386 // SSE, we're stuck with a fistpll.
387 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
390 if (isTargetFTOL()) {
391 // Use the _ftol2 runtime function, which has a pseudo-instruction
392 // to handle its weird calling convention.
393 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
396 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
397 if (!X86ScalarSSEf64) {
398 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
399 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
400 if (Subtarget->is64Bit()) {
401 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
402 // Without SSE, i64->f64 goes through memory.
403 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
407 // Scalar integer divide and remainder are lowered to use operations that
408 // produce two results, to match the available instructions. This exposes
409 // the two-result form to trivial CSE, which is able to combine x/y and x%y
410 // into a single instruction.
412 // Scalar integer multiply-high is also lowered to use two-result
413 // operations, to match the available instructions. However, plain multiply
414 // (low) operations are left as Legal, as there are single-result
415 // instructions for this in x86. Using the two-result multiply instructions
416 // when both high and low results are needed must be arranged by dagcombine.
417 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
419 setOperationAction(ISD::MULHS, VT, Expand);
420 setOperationAction(ISD::MULHU, VT, Expand);
421 setOperationAction(ISD::SDIV, VT, Expand);
422 setOperationAction(ISD::UDIV, VT, Expand);
423 setOperationAction(ISD::SREM, VT, Expand);
424 setOperationAction(ISD::UREM, VT, Expand);
426 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
427 setOperationAction(ISD::ADDC, VT, Custom);
428 setOperationAction(ISD::ADDE, VT, Custom);
429 setOperationAction(ISD::SUBC, VT, Custom);
430 setOperationAction(ISD::SUBE, VT, Custom);
433 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
434 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
435 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
436 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
437 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
438 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
439 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
440 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
441 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
442 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
443 if (Subtarget->is64Bit())
444 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
445 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
446 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
447 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
448 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
449 setOperationAction(ISD::FREM , MVT::f32 , Expand);
450 setOperationAction(ISD::FREM , MVT::f64 , Expand);
451 setOperationAction(ISD::FREM , MVT::f80 , Expand);
452 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
454 // Promote the i8 variants and force them on up to i32 which has a shorter
456 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
457 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
458 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
459 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
460 if (Subtarget->hasBMI()) {
461 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
462 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
463 if (Subtarget->is64Bit())
464 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
466 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
467 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
468 if (Subtarget->is64Bit())
469 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
472 if (Subtarget->hasLZCNT()) {
473 // When promoting the i8 variants, force them to i32 for a shorter
475 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
476 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
477 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
478 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
479 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
480 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
481 if (Subtarget->is64Bit())
482 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
484 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
485 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
486 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
487 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
488 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
489 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
490 if (Subtarget->is64Bit()) {
491 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
492 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
496 if (Subtarget->hasPOPCNT()) {
497 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
499 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
500 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
501 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
502 if (Subtarget->is64Bit())
503 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
506 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
507 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
509 // These should be promoted to a larger select which is supported.
510 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
511 // X86 wants to expand cmov itself.
512 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
513 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
514 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
515 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
516 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
517 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
518 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
519 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
520 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
521 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
522 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
523 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
524 if (Subtarget->is64Bit()) {
525 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
526 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
528 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
529 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
530 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
531 // support continuation, user-level threading, and etc.. As a result, no
532 // other SjLj exception interfaces are implemented and please don't build
533 // your own exception handling based on them.
534 // LLVM/Clang supports zero-cost DWARF exception handling.
535 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
536 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
539 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
540 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
541 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
542 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
543 if (Subtarget->is64Bit())
544 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
545 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
546 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
547 if (Subtarget->is64Bit()) {
548 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
549 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
550 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
551 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
552 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
554 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
555 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
556 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
557 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
558 if (Subtarget->is64Bit()) {
559 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
560 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
561 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
564 if (Subtarget->hasSSE1())
565 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
567 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
569 // Expand certain atomics
570 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
572 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom);
573 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
574 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
577 if (!Subtarget->is64Bit()) {
578 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
579 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
580 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
581 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
582 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
583 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
584 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
585 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
586 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i64, Custom);
587 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i64, Custom);
588 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i64, Custom);
589 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i64, Custom);
592 if (Subtarget->hasCmpxchg16b()) {
593 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom);
596 // FIXME - use subtarget debug flags
597 if (!Subtarget->isTargetDarwin() &&
598 !Subtarget->isTargetELF() &&
599 !Subtarget->isTargetCygMing()) {
600 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
603 if (Subtarget->is64Bit()) {
604 setExceptionPointerRegister(X86::RAX);
605 setExceptionSelectorRegister(X86::RDX);
607 setExceptionPointerRegister(X86::EAX);
608 setExceptionSelectorRegister(X86::EDX);
610 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
611 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
613 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
614 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
616 setOperationAction(ISD::TRAP, MVT::Other, Legal);
617 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
619 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
620 setOperationAction(ISD::VASTART , MVT::Other, Custom);
621 setOperationAction(ISD::VAEND , MVT::Other, Expand);
622 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
623 // TargetInfo::X86_64ABIBuiltinVaList
624 setOperationAction(ISD::VAARG , MVT::Other, Custom);
625 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
627 // TargetInfo::CharPtrBuiltinVaList
628 setOperationAction(ISD::VAARG , MVT::Other, Expand);
629 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
632 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
633 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
635 if (Subtarget->isOSWindows() && !Subtarget->isTargetEnvMacho())
636 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
637 MVT::i64 : MVT::i32, Custom);
638 else if (TM.Options.EnableSegmentedStacks)
639 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
640 MVT::i64 : MVT::i32, Custom);
642 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
643 MVT::i64 : MVT::i32, Expand);
645 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
646 // f32 and f64 use SSE.
647 // Set up the FP register classes.
648 addRegisterClass(MVT::f32, &X86::FR32RegClass);
649 addRegisterClass(MVT::f64, &X86::FR64RegClass);
651 // Use ANDPD to simulate FABS.
652 setOperationAction(ISD::FABS , MVT::f64, Custom);
653 setOperationAction(ISD::FABS , MVT::f32, Custom);
655 // Use XORP to simulate FNEG.
656 setOperationAction(ISD::FNEG , MVT::f64, Custom);
657 setOperationAction(ISD::FNEG , MVT::f32, Custom);
659 // Use ANDPD and ORPD to simulate FCOPYSIGN.
660 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
661 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
663 // Lower this to FGETSIGNx86 plus an AND.
664 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
665 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
667 // We don't support sin/cos/fmod
668 setOperationAction(ISD::FSIN , MVT::f64, Expand);
669 setOperationAction(ISD::FCOS , MVT::f64, Expand);
670 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
671 setOperationAction(ISD::FSIN , MVT::f32, Expand);
672 setOperationAction(ISD::FCOS , MVT::f32, Expand);
673 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
675 // Expand FP immediates into loads from the stack, except for the special
677 addLegalFPImmediate(APFloat(+0.0)); // xorpd
678 addLegalFPImmediate(APFloat(+0.0f)); // xorps
679 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
680 // Use SSE for f32, x87 for f64.
681 // Set up the FP register classes.
682 addRegisterClass(MVT::f32, &X86::FR32RegClass);
683 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
685 // Use ANDPS to simulate FABS.
686 setOperationAction(ISD::FABS , MVT::f32, Custom);
688 // Use XORP to simulate FNEG.
689 setOperationAction(ISD::FNEG , MVT::f32, Custom);
691 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
693 // Use ANDPS and ORPS to simulate FCOPYSIGN.
694 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
695 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
697 // We don't support sin/cos/fmod
698 setOperationAction(ISD::FSIN , MVT::f32, Expand);
699 setOperationAction(ISD::FCOS , MVT::f32, Expand);
700 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
702 // Special cases we handle for FP constants.
703 addLegalFPImmediate(APFloat(+0.0f)); // xorps
704 addLegalFPImmediate(APFloat(+0.0)); // FLD0
705 addLegalFPImmediate(APFloat(+1.0)); // FLD1
706 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
707 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
709 if (!TM.Options.UnsafeFPMath) {
710 setOperationAction(ISD::FSIN , MVT::f64, Expand);
711 setOperationAction(ISD::FCOS , MVT::f64, Expand);
712 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
714 } else if (!TM.Options.UseSoftFloat) {
715 // f32 and f64 in x87.
716 // Set up the FP register classes.
717 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
718 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
720 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
721 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
722 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
723 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
725 if (!TM.Options.UnsafeFPMath) {
726 setOperationAction(ISD::FSIN , MVT::f64, Expand);
727 setOperationAction(ISD::FSIN , MVT::f32, Expand);
728 setOperationAction(ISD::FCOS , MVT::f64, Expand);
729 setOperationAction(ISD::FCOS , MVT::f32, Expand);
730 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
731 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
733 addLegalFPImmediate(APFloat(+0.0)); // FLD0
734 addLegalFPImmediate(APFloat(+1.0)); // FLD1
735 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
736 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
737 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
738 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
739 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
740 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
743 // We don't support FMA.
744 setOperationAction(ISD::FMA, MVT::f64, Expand);
745 setOperationAction(ISD::FMA, MVT::f32, Expand);
747 // Long double always uses X87.
748 if (!TM.Options.UseSoftFloat) {
749 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
750 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
751 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
753 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
754 addLegalFPImmediate(TmpFlt); // FLD0
756 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
759 APFloat TmpFlt2(+1.0);
760 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
762 addLegalFPImmediate(TmpFlt2); // FLD1
763 TmpFlt2.changeSign();
764 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
767 if (!TM.Options.UnsafeFPMath) {
768 setOperationAction(ISD::FSIN , MVT::f80, Expand);
769 setOperationAction(ISD::FCOS , MVT::f80, Expand);
770 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
773 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
774 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
775 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
776 setOperationAction(ISD::FRINT, MVT::f80, Expand);
777 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
778 setOperationAction(ISD::FMA, MVT::f80, Expand);
781 // Always use a library call for pow.
782 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
783 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
784 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
786 setOperationAction(ISD::FLOG, MVT::f80, Expand);
787 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
788 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
789 setOperationAction(ISD::FEXP, MVT::f80, Expand);
790 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
792 // First set operation action for all vector types to either promote
793 // (for widening) or expand (for scalarization). Then we will selectively
794 // turn on ones that can be effectively codegen'd.
795 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
796 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
797 MVT VT = (MVT::SimpleValueType)i;
798 setOperationAction(ISD::ADD , VT, Expand);
799 setOperationAction(ISD::SUB , VT, Expand);
800 setOperationAction(ISD::FADD, VT, Expand);
801 setOperationAction(ISD::FNEG, VT, Expand);
802 setOperationAction(ISD::FSUB, VT, Expand);
803 setOperationAction(ISD::MUL , VT, Expand);
804 setOperationAction(ISD::FMUL, VT, Expand);
805 setOperationAction(ISD::SDIV, VT, Expand);
806 setOperationAction(ISD::UDIV, VT, Expand);
807 setOperationAction(ISD::FDIV, VT, Expand);
808 setOperationAction(ISD::SREM, VT, Expand);
809 setOperationAction(ISD::UREM, VT, Expand);
810 setOperationAction(ISD::LOAD, VT, Expand);
811 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
812 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
813 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
814 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
815 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
816 setOperationAction(ISD::FABS, VT, Expand);
817 setOperationAction(ISD::FSIN, VT, Expand);
818 setOperationAction(ISD::FSINCOS, VT, Expand);
819 setOperationAction(ISD::FCOS, VT, Expand);
820 setOperationAction(ISD::FSINCOS, VT, Expand);
821 setOperationAction(ISD::FREM, VT, Expand);
822 setOperationAction(ISD::FMA, VT, Expand);
823 setOperationAction(ISD::FPOWI, VT, Expand);
824 setOperationAction(ISD::FSQRT, VT, Expand);
825 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
826 setOperationAction(ISD::FFLOOR, VT, Expand);
827 setOperationAction(ISD::FCEIL, VT, Expand);
828 setOperationAction(ISD::FTRUNC, VT, Expand);
829 setOperationAction(ISD::FRINT, VT, Expand);
830 setOperationAction(ISD::FNEARBYINT, VT, Expand);
831 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
832 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
833 setOperationAction(ISD::SDIVREM, VT, Expand);
834 setOperationAction(ISD::UDIVREM, VT, Expand);
835 setOperationAction(ISD::FPOW, VT, Expand);
836 setOperationAction(ISD::CTPOP, VT, Expand);
837 setOperationAction(ISD::CTTZ, VT, Expand);
838 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
839 setOperationAction(ISD::CTLZ, VT, Expand);
840 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
841 setOperationAction(ISD::SHL, VT, Expand);
842 setOperationAction(ISD::SRA, VT, Expand);
843 setOperationAction(ISD::SRL, VT, Expand);
844 setOperationAction(ISD::ROTL, VT, Expand);
845 setOperationAction(ISD::ROTR, VT, Expand);
846 setOperationAction(ISD::BSWAP, VT, Expand);
847 setOperationAction(ISD::SETCC, VT, Expand);
848 setOperationAction(ISD::FLOG, VT, Expand);
849 setOperationAction(ISD::FLOG2, VT, Expand);
850 setOperationAction(ISD::FLOG10, VT, Expand);
851 setOperationAction(ISD::FEXP, VT, Expand);
852 setOperationAction(ISD::FEXP2, VT, Expand);
853 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
854 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
855 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
856 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
857 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
858 setOperationAction(ISD::TRUNCATE, VT, Expand);
859 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
860 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
861 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
862 setOperationAction(ISD::VSELECT, VT, Expand);
863 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
864 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
865 setTruncStoreAction(VT,
866 (MVT::SimpleValueType)InnerVT, Expand);
867 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
868 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
869 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
872 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
873 // with -msoft-float, disable use of MMX as well.
874 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
875 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
876 // No operations on x86mmx supported, everything uses intrinsics.
879 // MMX-sized vectors (other than x86mmx) are expected to be expanded
880 // into smaller operations.
881 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
882 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
883 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
884 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
885 setOperationAction(ISD::AND, MVT::v8i8, Expand);
886 setOperationAction(ISD::AND, MVT::v4i16, Expand);
887 setOperationAction(ISD::AND, MVT::v2i32, Expand);
888 setOperationAction(ISD::AND, MVT::v1i64, Expand);
889 setOperationAction(ISD::OR, MVT::v8i8, Expand);
890 setOperationAction(ISD::OR, MVT::v4i16, Expand);
891 setOperationAction(ISD::OR, MVT::v2i32, Expand);
892 setOperationAction(ISD::OR, MVT::v1i64, Expand);
893 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
894 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
895 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
896 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
897 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
898 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
899 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
900 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
901 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
902 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
903 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
904 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
905 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
906 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
907 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
908 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
909 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
911 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
912 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
914 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
915 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
916 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
917 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
918 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
919 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
920 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
921 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
922 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
923 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
924 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
925 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
928 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
929 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
931 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
932 // registers cannot be used even for integer operations.
933 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
934 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
935 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
936 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
938 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
939 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
940 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
941 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
942 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
943 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
944 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
945 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
946 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
947 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
948 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
949 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
950 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
951 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
952 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
953 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
954 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
955 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
957 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
958 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
959 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
960 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
962 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
963 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
964 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
965 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
966 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
968 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
969 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
970 MVT VT = (MVT::SimpleValueType)i;
971 // Do not attempt to custom lower non-power-of-2 vectors
972 if (!isPowerOf2_32(VT.getVectorNumElements()))
974 // Do not attempt to custom lower non-128-bit vectors
975 if (!VT.is128BitVector())
977 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
978 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
979 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
982 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
983 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
984 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
985 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
986 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
987 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
989 if (Subtarget->is64Bit()) {
990 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
991 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
994 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
995 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
996 MVT VT = (MVT::SimpleValueType)i;
998 // Do not attempt to promote non-128-bit vectors
999 if (!VT.is128BitVector())
1002 setOperationAction(ISD::AND, VT, Promote);
1003 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
1004 setOperationAction(ISD::OR, VT, Promote);
1005 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
1006 setOperationAction(ISD::XOR, VT, Promote);
1007 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
1008 setOperationAction(ISD::LOAD, VT, Promote);
1009 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
1010 setOperationAction(ISD::SELECT, VT, Promote);
1011 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
1014 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
1016 // Custom lower v2i64 and v2f64 selects.
1017 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1018 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
1019 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
1020 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1022 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1023 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1025 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1026 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1027 // As there is no 64-bit GPR available, we need build a special custom
1028 // sequence to convert from v2i32 to v2f32.
1029 if (!Subtarget->is64Bit())
1030 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
1032 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1033 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1035 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal);
1038 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
1039 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1040 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1041 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1042 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1043 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1044 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1045 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1046 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1047 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1048 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1050 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1051 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1052 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1053 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1054 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1055 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1056 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1057 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1058 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1059 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1061 // FIXME: Do we need to handle scalar-to-vector here?
1062 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1064 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
1065 setOperationAction(ISD::VSELECT, MVT::v2i64, Legal);
1066 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1067 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
1068 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
1070 // i8 and i16 vectors are custom , because the source register and source
1071 // source memory operand types are not the same width. f32 vectors are
1072 // custom since the immediate controlling the insert encodes additional
1074 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1075 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1076 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1077 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1079 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1080 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1081 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1082 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1084 // FIXME: these should be Legal but thats only for the case where
1085 // the index is constant. For now custom expand to deal with that.
1086 if (Subtarget->is64Bit()) {
1087 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1088 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1092 if (Subtarget->hasSSE2()) {
1093 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1094 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1096 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1097 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1099 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1100 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1102 // In the customized shift lowering, the legal cases in AVX2 will be
1104 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1105 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1107 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1108 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1110 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1112 setOperationAction(ISD::SDIV, MVT::v8i16, Custom);
1113 setOperationAction(ISD::SDIV, MVT::v4i32, Custom);
1116 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1117 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1118 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1119 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1120 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1121 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1122 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1124 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1125 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1126 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1128 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1129 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1130 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1131 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1132 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1133 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1134 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1135 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1136 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1137 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1138 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1139 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1141 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1142 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1143 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1144 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1145 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1146 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1147 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1148 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1149 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1150 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1151 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1152 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1154 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Custom);
1156 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1157 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1158 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1159 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1161 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1162 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1164 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal);
1166 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1167 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1169 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1170 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1172 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1173 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1175 setOperationAction(ISD::SDIV, MVT::v16i16, Custom);
1177 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1178 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1179 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1180 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1182 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1183 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1184 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1186 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal);
1187 setOperationAction(ISD::VSELECT, MVT::v4i64, Legal);
1188 setOperationAction(ISD::VSELECT, MVT::v8i32, Legal);
1189 setOperationAction(ISD::VSELECT, MVT::v8f32, Legal);
1191 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1192 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1193 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1194 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1195 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1196 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1197 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1198 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1199 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1200 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1201 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1202 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1204 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1205 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1206 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1207 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1208 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1209 setOperationAction(ISD::FMA, MVT::f32, Legal);
1210 setOperationAction(ISD::FMA, MVT::f64, Legal);
1213 if (Subtarget->hasInt256()) {
1214 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1215 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1216 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1217 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1219 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1220 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1221 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1222 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1224 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1225 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1226 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1227 // Don't lower v32i8 because there is no 128-bit byte mul
1229 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1231 setOperationAction(ISD::SDIV, MVT::v8i32, Custom);
1233 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1234 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1235 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1236 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1238 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1239 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1240 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1241 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1243 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1244 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1245 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1246 // Don't lower v32i8 because there is no 128-bit byte mul
1249 // In the customized shift lowering, the legal cases in AVX2 will be
1251 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1252 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1254 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1255 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1257 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1259 // Custom lower several nodes for 256-bit types.
1260 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1261 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1262 MVT VT = (MVT::SimpleValueType)i;
1264 // Extract subvector is special because the value type
1265 // (result) is 128-bit but the source is 256-bit wide.
1266 if (VT.is128BitVector())
1267 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1269 // Do not attempt to custom lower other non-256-bit vectors
1270 if (!VT.is256BitVector())
1273 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1274 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1275 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1276 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1277 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1278 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1279 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1282 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1283 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1284 MVT VT = (MVT::SimpleValueType)i;
1286 // Do not attempt to promote non-256-bit vectors
1287 if (!VT.is256BitVector())
1290 setOperationAction(ISD::AND, VT, Promote);
1291 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1292 setOperationAction(ISD::OR, VT, Promote);
1293 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1294 setOperationAction(ISD::XOR, VT, Promote);
1295 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1296 setOperationAction(ISD::LOAD, VT, Promote);
1297 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1298 setOperationAction(ISD::SELECT, VT, Promote);
1299 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1303 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) {
1304 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1305 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1306 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1307 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1309 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1310 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1312 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, Legal);
1313 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1314 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1315 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1316 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1317 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1319 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1320 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1321 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1322 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1323 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1324 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1326 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1327 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1328 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1329 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1330 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1331 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1332 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1333 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1334 setOperationAction(ISD::SDIV, MVT::v16i32, Custom);
1336 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1337 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1338 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1339 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1340 if (Subtarget->is64Bit()) {
1341 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1342 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1343 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1344 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1346 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1347 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1348 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1349 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1350 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1351 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1352 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1353 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1355 setOperationAction(ISD::TRUNCATE, MVT::i1, Legal);
1356 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1357 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1358 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1359 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1360 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1361 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1362 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1363 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1364 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1365 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1366 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1368 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1369 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1370 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1371 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1372 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1374 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1375 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1377 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1379 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1380 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1381 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1382 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1383 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1385 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1386 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1388 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1389 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1391 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1393 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1394 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1396 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1397 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1399 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1400 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1402 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1403 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1404 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1405 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1406 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1407 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1409 // Custom lower several nodes.
1410 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1411 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1412 MVT VT = (MVT::SimpleValueType)i;
1414 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1415 // Extract subvector is special because the value type
1416 // (result) is 256/128-bit but the source is 512-bit wide.
1417 if (VT.is128BitVector() || VT.is256BitVector())
1418 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1420 if (VT.getVectorElementType() == MVT::i1)
1421 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1423 // Do not attempt to custom lower other non-512-bit vectors
1424 if (!VT.is512BitVector())
1427 if ( EltSize >= 32) {
1428 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1429 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1430 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1431 setOperationAction(ISD::VSELECT, VT, Legal);
1432 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1433 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1434 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1437 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1438 MVT VT = (MVT::SimpleValueType)i;
1440 // Do not attempt to promote non-256-bit vectors
1441 if (!VT.is512BitVector())
1444 setOperationAction(ISD::SELECT, VT, Promote);
1445 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1449 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1450 // of this type with custom code.
1451 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1452 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1453 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1457 // We want to custom lower some of our intrinsics.
1458 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1459 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1460 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1462 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1463 // handle type legalization for these operations here.
1465 // FIXME: We really should do custom legalization for addition and
1466 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1467 // than generic legalization for 64-bit multiplication-with-overflow, though.
1468 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1469 // Add/Sub/Mul with overflow operations are custom lowered.
1471 setOperationAction(ISD::SADDO, VT, Custom);
1472 setOperationAction(ISD::UADDO, VT, Custom);
1473 setOperationAction(ISD::SSUBO, VT, Custom);
1474 setOperationAction(ISD::USUBO, VT, Custom);
1475 setOperationAction(ISD::SMULO, VT, Custom);
1476 setOperationAction(ISD::UMULO, VT, Custom);
1479 // There are no 8-bit 3-address imul/mul instructions
1480 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1481 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1483 if (!Subtarget->is64Bit()) {
1484 // These libcalls are not available in 32-bit.
1485 setLibcallName(RTLIB::SHL_I128, 0);
1486 setLibcallName(RTLIB::SRL_I128, 0);
1487 setLibcallName(RTLIB::SRA_I128, 0);
1490 // Combine sin / cos into one node or libcall if possible.
1491 if (Subtarget->hasSinCos()) {
1492 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1493 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1494 if (Subtarget->isTargetDarwin()) {
1495 // For MacOSX, we don't want to the normal expansion of a libcall to
1496 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
1498 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1499 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1503 // We have target-specific dag combine patterns for the following nodes:
1504 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1505 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1506 setTargetDAGCombine(ISD::VSELECT);
1507 setTargetDAGCombine(ISD::SELECT);
1508 setTargetDAGCombine(ISD::SHL);
1509 setTargetDAGCombine(ISD::SRA);
1510 setTargetDAGCombine(ISD::SRL);
1511 setTargetDAGCombine(ISD::OR);
1512 setTargetDAGCombine(ISD::AND);
1513 setTargetDAGCombine(ISD::ADD);
1514 setTargetDAGCombine(ISD::FADD);
1515 setTargetDAGCombine(ISD::FSUB);
1516 setTargetDAGCombine(ISD::FMA);
1517 setTargetDAGCombine(ISD::SUB);
1518 setTargetDAGCombine(ISD::LOAD);
1519 setTargetDAGCombine(ISD::STORE);
1520 setTargetDAGCombine(ISD::ZERO_EXTEND);
1521 setTargetDAGCombine(ISD::ANY_EXTEND);
1522 setTargetDAGCombine(ISD::SIGN_EXTEND);
1523 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1524 setTargetDAGCombine(ISD::TRUNCATE);
1525 setTargetDAGCombine(ISD::SINT_TO_FP);
1526 setTargetDAGCombine(ISD::SETCC);
1527 if (Subtarget->is64Bit())
1528 setTargetDAGCombine(ISD::MUL);
1529 setTargetDAGCombine(ISD::XOR);
1531 computeRegisterProperties();
1533 // On Darwin, -Os means optimize for size without hurting performance,
1534 // do not reduce the limit.
1535 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1536 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1537 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1538 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1539 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1540 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1541 setPrefLoopAlignment(4); // 2^4 bytes.
1543 // Predictable cmov don't hurt on atom because it's in-order.
1544 PredictableSelectIsExpensive = !Subtarget->isAtom();
1546 setPrefFunctionAlignment(4); // 2^4 bytes.
1549 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1550 if (!VT.isVector()) return MVT::i8;
1551 return VT.changeVectorElementTypeToInteger();
1554 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1555 /// the desired ByVal argument alignment.
1556 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1559 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1560 if (VTy->getBitWidth() == 128)
1562 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1563 unsigned EltAlign = 0;
1564 getMaxByValAlign(ATy->getElementType(), EltAlign);
1565 if (EltAlign > MaxAlign)
1566 MaxAlign = EltAlign;
1567 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1568 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1569 unsigned EltAlign = 0;
1570 getMaxByValAlign(STy->getElementType(i), EltAlign);
1571 if (EltAlign > MaxAlign)
1572 MaxAlign = EltAlign;
1579 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1580 /// function arguments in the caller parameter area. For X86, aggregates
1581 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1582 /// are at 4-byte boundaries.
1583 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1584 if (Subtarget->is64Bit()) {
1585 // Max of 8 and alignment of type.
1586 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1593 if (Subtarget->hasSSE1())
1594 getMaxByValAlign(Ty, Align);
1598 /// getOptimalMemOpType - Returns the target specific optimal type for load
1599 /// and store operations as a result of memset, memcpy, and memmove
1600 /// lowering. If DstAlign is zero that means it's safe to destination
1601 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1602 /// means there isn't a need to check it against alignment requirement,
1603 /// probably because the source does not need to be loaded. If 'IsMemset' is
1604 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1605 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1606 /// source is constant so it does not need to be loaded.
1607 /// It returns EVT::Other if the type should be determined using generic
1608 /// target-independent logic.
1610 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1611 unsigned DstAlign, unsigned SrcAlign,
1612 bool IsMemset, bool ZeroMemset,
1614 MachineFunction &MF) const {
1615 const Function *F = MF.getFunction();
1616 if ((!IsMemset || ZeroMemset) &&
1617 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1618 Attribute::NoImplicitFloat)) {
1620 (Subtarget->isUnalignedMemAccessFast() ||
1621 ((DstAlign == 0 || DstAlign >= 16) &&
1622 (SrcAlign == 0 || SrcAlign >= 16)))) {
1624 if (Subtarget->hasInt256())
1626 if (Subtarget->hasFp256())
1629 if (Subtarget->hasSSE2())
1631 if (Subtarget->hasSSE1())
1633 } else if (!MemcpyStrSrc && Size >= 8 &&
1634 !Subtarget->is64Bit() &&
1635 Subtarget->hasSSE2()) {
1636 // Do not use f64 to lower memcpy if source is string constant. It's
1637 // better to use i32 to avoid the loads.
1641 if (Subtarget->is64Bit() && Size >= 8)
1646 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1648 return X86ScalarSSEf32;
1649 else if (VT == MVT::f64)
1650 return X86ScalarSSEf64;
1655 X86TargetLowering::allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const {
1657 *Fast = Subtarget->isUnalignedMemAccessFast();
1661 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1662 /// current function. The returned value is a member of the
1663 /// MachineJumpTableInfo::JTEntryKind enum.
1664 unsigned X86TargetLowering::getJumpTableEncoding() const {
1665 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1667 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1668 Subtarget->isPICStyleGOT())
1669 return MachineJumpTableInfo::EK_Custom32;
1671 // Otherwise, use the normal jump table encoding heuristics.
1672 return TargetLowering::getJumpTableEncoding();
1676 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1677 const MachineBasicBlock *MBB,
1678 unsigned uid,MCContext &Ctx) const{
1679 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1680 Subtarget->isPICStyleGOT());
1681 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1683 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1684 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1687 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1689 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1690 SelectionDAG &DAG) const {
1691 if (!Subtarget->is64Bit())
1692 // This doesn't have SDLoc associated with it, but is not really the
1693 // same as a Register.
1694 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1698 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1699 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1701 const MCExpr *X86TargetLowering::
1702 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1703 MCContext &Ctx) const {
1704 // X86-64 uses RIP relative addressing based on the jump table label.
1705 if (Subtarget->isPICStyleRIPRel())
1706 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1708 // Otherwise, the reference is relative to the PIC base.
1709 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1712 // FIXME: Why this routine is here? Move to RegInfo!
1713 std::pair<const TargetRegisterClass*, uint8_t>
1714 X86TargetLowering::findRepresentativeClass(MVT VT) const{
1715 const TargetRegisterClass *RRC = 0;
1717 switch (VT.SimpleTy) {
1719 return TargetLowering::findRepresentativeClass(VT);
1720 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1721 RRC = Subtarget->is64Bit() ?
1722 (const TargetRegisterClass*)&X86::GR64RegClass :
1723 (const TargetRegisterClass*)&X86::GR32RegClass;
1726 RRC = &X86::VR64RegClass;
1728 case MVT::f32: case MVT::f64:
1729 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1730 case MVT::v4f32: case MVT::v2f64:
1731 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1733 RRC = &X86::VR128RegClass;
1736 return std::make_pair(RRC, Cost);
1739 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1740 unsigned &Offset) const {
1741 if (!Subtarget->isTargetLinux())
1744 if (Subtarget->is64Bit()) {
1745 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1747 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1759 //===----------------------------------------------------------------------===//
1760 // Return Value Calling Convention Implementation
1761 //===----------------------------------------------------------------------===//
1763 #include "X86GenCallingConv.inc"
1766 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1767 MachineFunction &MF, bool isVarArg,
1768 const SmallVectorImpl<ISD::OutputArg> &Outs,
1769 LLVMContext &Context) const {
1770 SmallVector<CCValAssign, 16> RVLocs;
1771 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1773 return CCInfo.CheckReturn(Outs, RetCC_X86);
1776 const uint16_t *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
1777 static const uint16_t ScratchRegs[] = { X86::R11, 0 };
1782 X86TargetLowering::LowerReturn(SDValue Chain,
1783 CallingConv::ID CallConv, bool isVarArg,
1784 const SmallVectorImpl<ISD::OutputArg> &Outs,
1785 const SmallVectorImpl<SDValue> &OutVals,
1786 SDLoc dl, SelectionDAG &DAG) const {
1787 MachineFunction &MF = DAG.getMachineFunction();
1788 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1790 SmallVector<CCValAssign, 16> RVLocs;
1791 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1792 RVLocs, *DAG.getContext());
1793 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1796 SmallVector<SDValue, 6> RetOps;
1797 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1798 // Operand #1 = Bytes To Pop
1799 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1802 // Copy the result values into the output registers.
1803 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1804 CCValAssign &VA = RVLocs[i];
1805 assert(VA.isRegLoc() && "Can only return in registers!");
1806 SDValue ValToCopy = OutVals[i];
1807 EVT ValVT = ValToCopy.getValueType();
1809 // Promote values to the appropriate types
1810 if (VA.getLocInfo() == CCValAssign::SExt)
1811 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
1812 else if (VA.getLocInfo() == CCValAssign::ZExt)
1813 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
1814 else if (VA.getLocInfo() == CCValAssign::AExt)
1815 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
1816 else if (VA.getLocInfo() == CCValAssign::BCvt)
1817 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
1819 // If this is x86-64, and we disabled SSE, we can't return FP values,
1820 // or SSE or MMX vectors.
1821 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1822 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1823 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
1824 report_fatal_error("SSE register return with SSE disabled");
1826 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1827 // llvm-gcc has never done it right and no one has noticed, so this
1828 // should be OK for now.
1829 if (ValVT == MVT::f64 &&
1830 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
1831 report_fatal_error("SSE2 register return with SSE2 disabled");
1833 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1834 // the RET instruction and handled by the FP Stackifier.
1835 if (VA.getLocReg() == X86::ST0 ||
1836 VA.getLocReg() == X86::ST1) {
1837 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1838 // change the value to the FP stack register class.
1839 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1840 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1841 RetOps.push_back(ValToCopy);
1842 // Don't emit a copytoreg.
1846 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1847 // which is returned in RAX / RDX.
1848 if (Subtarget->is64Bit()) {
1849 if (ValVT == MVT::x86mmx) {
1850 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1851 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1852 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1854 // If we don't have SSE2 available, convert to v4f32 so the generated
1855 // register is legal.
1856 if (!Subtarget->hasSSE2())
1857 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1862 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1863 Flag = Chain.getValue(1);
1864 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
1867 // The x86-64 ABIs require that for returning structs by value we copy
1868 // the sret argument into %rax/%eax (depending on ABI) for the return.
1869 // Win32 requires us to put the sret argument to %eax as well.
1870 // We saved the argument into a virtual register in the entry block,
1871 // so now we copy the value out and into %rax/%eax.
1872 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr() &&
1873 (Subtarget->is64Bit() || Subtarget->isTargetWindows())) {
1874 MachineFunction &MF = DAG.getMachineFunction();
1875 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1876 unsigned Reg = FuncInfo->getSRetReturnReg();
1878 "SRetReturnReg should have been set in LowerFormalArguments().");
1879 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1882 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
1883 X86::RAX : X86::EAX;
1884 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
1885 Flag = Chain.getValue(1);
1887 // RAX/EAX now acts like a return value.
1888 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
1891 RetOps[0] = Chain; // Update chain.
1893 // Add the flag if we have it.
1895 RetOps.push_back(Flag);
1897 return DAG.getNode(X86ISD::RET_FLAG, dl,
1898 MVT::Other, &RetOps[0], RetOps.size());
1901 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
1902 if (N->getNumValues() != 1)
1904 if (!N->hasNUsesOfValue(1, 0))
1907 SDValue TCChain = Chain;
1908 SDNode *Copy = *N->use_begin();
1909 if (Copy->getOpcode() == ISD::CopyToReg) {
1910 // If the copy has a glue operand, we conservatively assume it isn't safe to
1911 // perform a tail call.
1912 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
1914 TCChain = Copy->getOperand(0);
1915 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
1918 bool HasRet = false;
1919 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1921 if (UI->getOpcode() != X86ISD::RET_FLAG)
1934 X86TargetLowering::getTypeForExtArgOrReturn(MVT VT,
1935 ISD::NodeType ExtendKind) const {
1937 // TODO: Is this also valid on 32-bit?
1938 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
1939 ReturnMVT = MVT::i8;
1941 ReturnMVT = MVT::i32;
1943 MVT MinVT = getRegisterType(ReturnMVT);
1944 return VT.bitsLT(MinVT) ? MinVT : VT;
1947 /// LowerCallResult - Lower the result values of a call into the
1948 /// appropriate copies out of appropriate physical registers.
1951 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1952 CallingConv::ID CallConv, bool isVarArg,
1953 const SmallVectorImpl<ISD::InputArg> &Ins,
1954 SDLoc dl, SelectionDAG &DAG,
1955 SmallVectorImpl<SDValue> &InVals) const {
1957 // Assign locations to each value returned by this call.
1958 SmallVector<CCValAssign, 16> RVLocs;
1959 bool Is64Bit = Subtarget->is64Bit();
1960 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1961 getTargetMachine(), RVLocs, *DAG.getContext());
1962 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1964 // Copy all of the result registers out of their specified physreg.
1965 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
1966 CCValAssign &VA = RVLocs[i];
1967 EVT CopyVT = VA.getValVT();
1969 // If this is x86-64, and we disabled SSE, we can't return FP values
1970 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1971 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
1972 report_fatal_error("SSE register return with SSE disabled");
1977 // If this is a call to a function that returns an fp value on the floating
1978 // point stack, we must guarantee the value is popped from the stack, so
1979 // a CopyFromReg is not good enough - the copy instruction may be eliminated
1980 // if the return value is not used. We use the FpPOP_RETVAL instruction
1982 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {
1983 // If we prefer to use the value in xmm registers, copy it out as f80 and
1984 // use a truncate to move it from fp stack reg to xmm reg.
1985 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
1986 SDValue Ops[] = { Chain, InFlag };
1987 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT,
1988 MVT::Other, MVT::Glue, Ops), 1);
1989 Val = Chain.getValue(0);
1991 // Round the f80 to the right size, which also moves it to the appropriate
1993 if (CopyVT != VA.getValVT())
1994 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1995 // This truncation won't change the value.
1996 DAG.getIntPtrConstant(1));
1998 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1999 CopyVT, InFlag).getValue(1);
2000 Val = Chain.getValue(0);
2002 InFlag = Chain.getValue(2);
2003 InVals.push_back(Val);
2009 //===----------------------------------------------------------------------===//
2010 // C & StdCall & Fast Calling Convention implementation
2011 //===----------------------------------------------------------------------===//
2012 // StdCall calling convention seems to be standard for many Windows' API
2013 // routines and around. It differs from C calling convention just a little:
2014 // callee should clean up the stack, not caller. Symbols should be also
2015 // decorated in some fancy way :) It doesn't support any vector arguments.
2016 // For info on fast calling convention see Fast Calling Convention (tail call)
2017 // implementation LowerX86_32FastCCCallTo.
2019 /// CallIsStructReturn - Determines whether a call uses struct return
2021 enum StructReturnType {
2026 static StructReturnType
2027 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2029 return NotStructReturn;
2031 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2032 if (!Flags.isSRet())
2033 return NotStructReturn;
2034 if (Flags.isInReg())
2035 return RegStructReturn;
2036 return StackStructReturn;
2039 /// ArgsAreStructReturn - Determines whether a function uses struct
2040 /// return semantics.
2041 static StructReturnType
2042 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2044 return NotStructReturn;
2046 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2047 if (!Flags.isSRet())
2048 return NotStructReturn;
2049 if (Flags.isInReg())
2050 return RegStructReturn;
2051 return StackStructReturn;
2054 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2055 /// by "Src" to address "Dst" with size and alignment information specified by
2056 /// the specific parameter attribute. The copy will be passed as a byval
2057 /// function parameter.
2059 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2060 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2062 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2064 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2065 /*isVolatile*/false, /*AlwaysInline=*/true,
2066 MachinePointerInfo(), MachinePointerInfo());
2069 /// IsTailCallConvention - Return true if the calling convention is one that
2070 /// supports tail call optimization.
2071 static bool IsTailCallConvention(CallingConv::ID CC) {
2072 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2073 CC == CallingConv::HiPE);
2076 /// \brief Return true if the calling convention is a C calling convention.
2077 static bool IsCCallConvention(CallingConv::ID CC) {
2078 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2079 CC == CallingConv::X86_64_SysV);
2082 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2083 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2087 CallingConv::ID CalleeCC = CS.getCallingConv();
2088 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2094 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
2095 /// a tailcall target by changing its ABI.
2096 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2097 bool GuaranteedTailCallOpt) {
2098 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2102 X86TargetLowering::LowerMemArgument(SDValue Chain,
2103 CallingConv::ID CallConv,
2104 const SmallVectorImpl<ISD::InputArg> &Ins,
2105 SDLoc dl, SelectionDAG &DAG,
2106 const CCValAssign &VA,
2107 MachineFrameInfo *MFI,
2109 // Create the nodes corresponding to a load from this parameter slot.
2110 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2111 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv,
2112 getTargetMachine().Options.GuaranteedTailCallOpt);
2113 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2116 // If value is passed by pointer we have address passed instead of the value
2118 if (VA.getLocInfo() == CCValAssign::Indirect)
2119 ValVT = VA.getLocVT();
2121 ValVT = VA.getValVT();
2123 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2124 // changed with more analysis.
2125 // In case of tail call optimization mark all arguments mutable. Since they
2126 // could be overwritten by lowering of arguments in case of a tail call.
2127 if (Flags.isByVal()) {
2128 unsigned Bytes = Flags.getByValSize();
2129 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2130 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2131 return DAG.getFrameIndex(FI, getPointerTy());
2133 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2134 VA.getLocMemOffset(), isImmutable);
2135 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2136 return DAG.getLoad(ValVT, dl, Chain, FIN,
2137 MachinePointerInfo::getFixedStack(FI),
2138 false, false, false, 0);
2143 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2144 CallingConv::ID CallConv,
2146 const SmallVectorImpl<ISD::InputArg> &Ins,
2149 SmallVectorImpl<SDValue> &InVals)
2151 MachineFunction &MF = DAG.getMachineFunction();
2152 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2154 const Function* Fn = MF.getFunction();
2155 if (Fn->hasExternalLinkage() &&
2156 Subtarget->isTargetCygMing() &&
2157 Fn->getName() == "main")
2158 FuncInfo->setForceFramePointer(true);
2160 MachineFrameInfo *MFI = MF.getFrameInfo();
2161 bool Is64Bit = Subtarget->is64Bit();
2162 bool IsWindows = Subtarget->isTargetWindows();
2163 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2165 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2166 "Var args not supported with calling convention fastcc, ghc or hipe");
2168 // Assign locations to all of the incoming arguments.
2169 SmallVector<CCValAssign, 16> ArgLocs;
2170 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
2171 ArgLocs, *DAG.getContext());
2173 // Allocate shadow area for Win64
2175 CCInfo.AllocateStack(32, 8);
2177 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2179 unsigned LastVal = ~0U;
2181 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2182 CCValAssign &VA = ArgLocs[i];
2183 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2185 assert(VA.getValNo() != LastVal &&
2186 "Don't support value assigned to multiple locs yet");
2188 LastVal = VA.getValNo();
2190 if (VA.isRegLoc()) {
2191 EVT RegVT = VA.getLocVT();
2192 const TargetRegisterClass *RC;
2193 if (RegVT == MVT::i32)
2194 RC = &X86::GR32RegClass;
2195 else if (Is64Bit && RegVT == MVT::i64)
2196 RC = &X86::GR64RegClass;
2197 else if (RegVT == MVT::f32)
2198 RC = &X86::FR32RegClass;
2199 else if (RegVT == MVT::f64)
2200 RC = &X86::FR64RegClass;
2201 else if (RegVT.is512BitVector())
2202 RC = &X86::VR512RegClass;
2203 else if (RegVT.is256BitVector())
2204 RC = &X86::VR256RegClass;
2205 else if (RegVT.is128BitVector())
2206 RC = &X86::VR128RegClass;
2207 else if (RegVT == MVT::x86mmx)
2208 RC = &X86::VR64RegClass;
2209 else if (RegVT == MVT::v8i1)
2210 RC = &X86::VK8RegClass;
2211 else if (RegVT == MVT::v16i1)
2212 RC = &X86::VK16RegClass;
2214 llvm_unreachable("Unknown argument type!");
2216 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2217 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2219 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2220 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2222 if (VA.getLocInfo() == CCValAssign::SExt)
2223 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2224 DAG.getValueType(VA.getValVT()));
2225 else if (VA.getLocInfo() == CCValAssign::ZExt)
2226 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2227 DAG.getValueType(VA.getValVT()));
2228 else if (VA.getLocInfo() == CCValAssign::BCvt)
2229 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2231 if (VA.isExtInLoc()) {
2232 // Handle MMX values passed in XMM regs.
2233 if (RegVT.isVector())
2234 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2236 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2239 assert(VA.isMemLoc());
2240 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2243 // If value is passed via pointer - do a load.
2244 if (VA.getLocInfo() == CCValAssign::Indirect)
2245 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2246 MachinePointerInfo(), false, false, false, 0);
2248 InVals.push_back(ArgValue);
2251 // The x86-64 ABIs require that for returning structs by value we copy
2252 // the sret argument into %rax/%eax (depending on ABI) for the return.
2253 // Win32 requires us to put the sret argument to %eax as well.
2254 // Save the argument into a virtual register so that we can access it
2255 // from the return points.
2256 if (MF.getFunction()->hasStructRetAttr() &&
2257 (Subtarget->is64Bit() || Subtarget->isTargetWindows())) {
2258 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2259 unsigned Reg = FuncInfo->getSRetReturnReg();
2261 MVT PtrTy = getPointerTy();
2262 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2263 FuncInfo->setSRetReturnReg(Reg);
2265 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
2266 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2269 unsigned StackSize = CCInfo.getNextStackOffset();
2270 // Align stack specially for tail calls.
2271 if (FuncIsMadeTailCallSafe(CallConv,
2272 MF.getTarget().Options.GuaranteedTailCallOpt))
2273 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2275 // If the function takes variable number of arguments, make a frame index for
2276 // the start of the first vararg value... for expansion of llvm.va_start.
2278 if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2279 CallConv != CallingConv::X86_ThisCall)) {
2280 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
2283 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
2285 // FIXME: We should really autogenerate these arrays
2286 static const uint16_t GPR64ArgRegsWin64[] = {
2287 X86::RCX, X86::RDX, X86::R8, X86::R9
2289 static const uint16_t GPR64ArgRegs64Bit[] = {
2290 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2292 static const uint16_t XMMArgRegs64Bit[] = {
2293 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2294 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2296 const uint16_t *GPR64ArgRegs;
2297 unsigned NumXMMRegs = 0;
2300 // The XMM registers which might contain var arg parameters are shadowed
2301 // in their paired GPR. So we only need to save the GPR to their home
2303 TotalNumIntRegs = 4;
2304 GPR64ArgRegs = GPR64ArgRegsWin64;
2306 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
2307 GPR64ArgRegs = GPR64ArgRegs64Bit;
2309 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit,
2312 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
2315 bool NoImplicitFloatOps = Fn->getAttributes().
2316 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2317 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2318 "SSE register cannot be used when SSE is disabled!");
2319 assert(!(NumXMMRegs && MF.getTarget().Options.UseSoftFloat &&
2320 NoImplicitFloatOps) &&
2321 "SSE register cannot be used when SSE is disabled!");
2322 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2323 !Subtarget->hasSSE1())
2324 // Kernel mode asks for SSE to be disabled, so don't push them
2326 TotalNumXMMRegs = 0;
2329 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering();
2330 // Get to the caller-allocated home save location. Add 8 to account
2331 // for the return address.
2332 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2333 FuncInfo->setRegSaveFrameIndex(
2334 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2335 // Fixup to set vararg frame on shadow area (4 x i64).
2337 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2339 // For X86-64, if there are vararg parameters that are passed via
2340 // registers, then we must store them to their spots on the stack so
2341 // they may be loaded by deferencing the result of va_next.
2342 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2343 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
2344 FuncInfo->setRegSaveFrameIndex(
2345 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
2349 // Store the integer parameter registers.
2350 SmallVector<SDValue, 8> MemOps;
2351 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2353 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2354 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
2355 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2356 DAG.getIntPtrConstant(Offset));
2357 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
2358 &X86::GR64RegClass);
2359 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2361 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2362 MachinePointerInfo::getFixedStack(
2363 FuncInfo->getRegSaveFrameIndex(), Offset),
2365 MemOps.push_back(Store);
2369 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
2370 // Now store the XMM (fp + vector) parameter registers.
2371 SmallVector<SDValue, 11> SaveXMMOps;
2372 SaveXMMOps.push_back(Chain);
2374 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2375 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
2376 SaveXMMOps.push_back(ALVal);
2378 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2379 FuncInfo->getRegSaveFrameIndex()));
2380 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2381 FuncInfo->getVarArgsFPOffset()));
2383 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
2384 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs],
2385 &X86::VR128RegClass);
2386 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
2387 SaveXMMOps.push_back(Val);
2389 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2391 &SaveXMMOps[0], SaveXMMOps.size()));
2394 if (!MemOps.empty())
2395 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2396 &MemOps[0], MemOps.size());
2400 // Some CCs need callee pop.
2401 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2402 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2403 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2405 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2406 // If this is an sret function, the return should pop the hidden pointer.
2407 if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows &&
2408 argsAreStructReturn(Ins) == StackStructReturn)
2409 FuncInfo->setBytesToPopOnReturn(4);
2413 // RegSaveFrameIndex is X86-64 only.
2414 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2415 if (CallConv == CallingConv::X86_FastCall ||
2416 CallConv == CallingConv::X86_ThisCall)
2417 // fastcc functions can't have varargs.
2418 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2421 FuncInfo->setArgumentStackSize(StackSize);
2427 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2428 SDValue StackPtr, SDValue Arg,
2429 SDLoc dl, SelectionDAG &DAG,
2430 const CCValAssign &VA,
2431 ISD::ArgFlagsTy Flags) const {
2432 unsigned LocMemOffset = VA.getLocMemOffset();
2433 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2434 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2435 if (Flags.isByVal())
2436 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2438 return DAG.getStore(Chain, dl, Arg, PtrOff,
2439 MachinePointerInfo::getStack(LocMemOffset),
2443 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2444 /// optimization is performed and it is required.
2446 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2447 SDValue &OutRetAddr, SDValue Chain,
2448 bool IsTailCall, bool Is64Bit,
2449 int FPDiff, SDLoc dl) const {
2450 // Adjust the Return address stack slot.
2451 EVT VT = getPointerTy();
2452 OutRetAddr = getReturnAddressFrameIndex(DAG);
2454 // Load the "old" Return address.
2455 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2456 false, false, false, 0);
2457 return SDValue(OutRetAddr.getNode(), 1);
2460 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2461 /// optimization is performed and it is required (FPDiff!=0).
2463 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
2464 SDValue Chain, SDValue RetAddrFrIdx, EVT PtrVT,
2465 unsigned SlotSize, int FPDiff, SDLoc dl) {
2466 // Store the return address to the appropriate stack slot.
2467 if (!FPDiff) return Chain;
2468 // Calculate the new stack slot for the return address.
2469 int NewReturnAddrFI =
2470 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2472 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2473 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2474 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2480 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2481 SmallVectorImpl<SDValue> &InVals) const {
2482 SelectionDAG &DAG = CLI.DAG;
2484 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2485 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2486 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2487 SDValue Chain = CLI.Chain;
2488 SDValue Callee = CLI.Callee;
2489 CallingConv::ID CallConv = CLI.CallConv;
2490 bool &isTailCall = CLI.IsTailCall;
2491 bool isVarArg = CLI.IsVarArg;
2493 MachineFunction &MF = DAG.getMachineFunction();
2494 bool Is64Bit = Subtarget->is64Bit();
2495 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2496 bool IsWindows = Subtarget->isTargetWindows();
2497 StructReturnType SR = callIsStructReturn(Outs);
2498 bool IsSibcall = false;
2500 if (MF.getTarget().Options.DisableTailCalls)
2504 // Check if it's really possible to do a tail call.
2505 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2506 isVarArg, SR != NotStructReturn,
2507 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2508 Outs, OutVals, Ins, DAG);
2510 // Sibcalls are automatically detected tailcalls which do not require
2512 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2519 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2520 "Var args not supported with calling convention fastcc, ghc or hipe");
2522 // Analyze operands of the call, assigning locations to each operand.
2523 SmallVector<CCValAssign, 16> ArgLocs;
2524 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
2525 ArgLocs, *DAG.getContext());
2527 // Allocate shadow area for Win64
2529 CCInfo.AllocateStack(32, 8);
2531 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2533 // Get a count of how many bytes are to be pushed on the stack.
2534 unsigned NumBytes = CCInfo.getNextStackOffset();
2536 // This is a sibcall. The memory operands are available in caller's
2537 // own caller's stack.
2539 else if (getTargetMachine().Options.GuaranteedTailCallOpt &&
2540 IsTailCallConvention(CallConv))
2541 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2544 if (isTailCall && !IsSibcall) {
2545 // Lower arguments at fp - stackoffset + fpdiff.
2546 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2547 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2549 FPDiff = NumBytesCallerPushed - NumBytes;
2551 // Set the delta of movement of the returnaddr stackslot.
2552 // But only set if delta is greater than previous delta.
2553 if (FPDiff < X86Info->getTCReturnAddrDelta())
2554 X86Info->setTCReturnAddrDelta(FPDiff);
2558 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
2561 SDValue RetAddrFrIdx;
2562 // Load return address for tail calls.
2563 if (isTailCall && FPDiff)
2564 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2565 Is64Bit, FPDiff, dl);
2567 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2568 SmallVector<SDValue, 8> MemOpChains;
2571 // Walk the register/memloc assignments, inserting copies/loads. In the case
2572 // of tail call optimization arguments are handle later.
2573 const X86RegisterInfo *RegInfo =
2574 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
2575 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2576 CCValAssign &VA = ArgLocs[i];
2577 EVT RegVT = VA.getLocVT();
2578 SDValue Arg = OutVals[i];
2579 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2580 bool isByVal = Flags.isByVal();
2582 // Promote the value if needed.
2583 switch (VA.getLocInfo()) {
2584 default: llvm_unreachable("Unknown loc info!");
2585 case CCValAssign::Full: break;
2586 case CCValAssign::SExt:
2587 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2589 case CCValAssign::ZExt:
2590 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2592 case CCValAssign::AExt:
2593 if (RegVT.is128BitVector()) {
2594 // Special case: passing MMX values in XMM registers.
2595 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2596 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2597 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2599 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2601 case CCValAssign::BCvt:
2602 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2604 case CCValAssign::Indirect: {
2605 // Store the argument.
2606 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2607 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2608 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2609 MachinePointerInfo::getFixedStack(FI),
2616 if (VA.isRegLoc()) {
2617 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2618 if (isVarArg && IsWin64) {
2619 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2620 // shadow reg if callee is a varargs function.
2621 unsigned ShadowReg = 0;
2622 switch (VA.getLocReg()) {
2623 case X86::XMM0: ShadowReg = X86::RCX; break;
2624 case X86::XMM1: ShadowReg = X86::RDX; break;
2625 case X86::XMM2: ShadowReg = X86::R8; break;
2626 case X86::XMM3: ShadowReg = X86::R9; break;
2629 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2631 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2632 assert(VA.isMemLoc());
2633 if (StackPtr.getNode() == 0)
2634 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2636 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2637 dl, DAG, VA, Flags));
2641 if (!MemOpChains.empty())
2642 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2643 &MemOpChains[0], MemOpChains.size());
2645 if (Subtarget->isPICStyleGOT()) {
2646 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2649 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2650 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2652 // If we are tail calling and generating PIC/GOT style code load the
2653 // address of the callee into ECX. The value in ecx is used as target of
2654 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2655 // for tail calls on PIC/GOT architectures. Normally we would just put the
2656 // address of GOT into ebx and then call target@PLT. But for tail calls
2657 // ebx would be restored (since ebx is callee saved) before jumping to the
2660 // Note: The actual moving to ECX is done further down.
2661 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2662 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2663 !G->getGlobal()->hasProtectedVisibility())
2664 Callee = LowerGlobalAddress(Callee, DAG);
2665 else if (isa<ExternalSymbolSDNode>(Callee))
2666 Callee = LowerExternalSymbol(Callee, DAG);
2670 if (Is64Bit && isVarArg && !IsWin64) {
2671 // From AMD64 ABI document:
2672 // For calls that may call functions that use varargs or stdargs
2673 // (prototype-less calls or calls to functions containing ellipsis (...) in
2674 // the declaration) %al is used as hidden argument to specify the number
2675 // of SSE registers used. The contents of %al do not need to match exactly
2676 // the number of registers, but must be an ubound on the number of SSE
2677 // registers used and is in the range 0 - 8 inclusive.
2679 // Count the number of XMM registers allocated.
2680 static const uint16_t XMMArgRegs[] = {
2681 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2682 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2684 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2685 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2686 && "SSE registers cannot be used when SSE is disabled");
2688 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2689 DAG.getConstant(NumXMMRegs, MVT::i8)));
2692 // For tail calls lower the arguments to the 'real' stack slot.
2694 // Force all the incoming stack arguments to be loaded from the stack
2695 // before any new outgoing arguments are stored to the stack, because the
2696 // outgoing stack slots may alias the incoming argument stack slots, and
2697 // the alias isn't otherwise explicit. This is slightly more conservative
2698 // than necessary, because it means that each store effectively depends
2699 // on every argument instead of just those arguments it would clobber.
2700 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2702 SmallVector<SDValue, 8> MemOpChains2;
2705 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2706 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2707 CCValAssign &VA = ArgLocs[i];
2710 assert(VA.isMemLoc());
2711 SDValue Arg = OutVals[i];
2712 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2713 // Create frame index.
2714 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2715 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2716 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2717 FIN = DAG.getFrameIndex(FI, getPointerTy());
2719 if (Flags.isByVal()) {
2720 // Copy relative to framepointer.
2721 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2722 if (StackPtr.getNode() == 0)
2723 StackPtr = DAG.getCopyFromReg(Chain, dl,
2724 RegInfo->getStackRegister(),
2726 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2728 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2732 // Store relative to framepointer.
2733 MemOpChains2.push_back(
2734 DAG.getStore(ArgChain, dl, Arg, FIN,
2735 MachinePointerInfo::getFixedStack(FI),
2741 if (!MemOpChains2.empty())
2742 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2743 &MemOpChains2[0], MemOpChains2.size());
2745 // Store the return address to the appropriate stack slot.
2746 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
2747 getPointerTy(), RegInfo->getSlotSize(),
2751 // Build a sequence of copy-to-reg nodes chained together with token chain
2752 // and flag operands which copy the outgoing args into registers.
2754 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2755 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2756 RegsToPass[i].second, InFlag);
2757 InFlag = Chain.getValue(1);
2760 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2761 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2762 // In the 64-bit large code model, we have to make all calls
2763 // through a register, since the call instruction's 32-bit
2764 // pc-relative offset may not be large enough to hold the whole
2766 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2767 // If the callee is a GlobalAddress node (quite common, every direct call
2768 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2771 // We should use extra load for direct calls to dllimported functions in
2773 const GlobalValue *GV = G->getGlobal();
2774 if (!GV->hasDLLImportLinkage()) {
2775 unsigned char OpFlags = 0;
2776 bool ExtraLoad = false;
2777 unsigned WrapperKind = ISD::DELETED_NODE;
2779 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2780 // external symbols most go through the PLT in PIC mode. If the symbol
2781 // has hidden or protected visibility, or if it is static or local, then
2782 // we don't need to use the PLT - we can directly call it.
2783 if (Subtarget->isTargetELF() &&
2784 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2785 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2786 OpFlags = X86II::MO_PLT;
2787 } else if (Subtarget->isPICStyleStubAny() &&
2788 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2789 (!Subtarget->getTargetTriple().isMacOSX() ||
2790 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2791 // PC-relative references to external symbols should go through $stub,
2792 // unless we're building with the leopard linker or later, which
2793 // automatically synthesizes these stubs.
2794 OpFlags = X86II::MO_DARWIN_STUB;
2795 } else if (Subtarget->isPICStyleRIPRel() &&
2796 isa<Function>(GV) &&
2797 cast<Function>(GV)->getAttributes().
2798 hasAttribute(AttributeSet::FunctionIndex,
2799 Attribute::NonLazyBind)) {
2800 // If the function is marked as non-lazy, generate an indirect call
2801 // which loads from the GOT directly. This avoids runtime overhead
2802 // at the cost of eager binding (and one extra byte of encoding).
2803 OpFlags = X86II::MO_GOTPCREL;
2804 WrapperKind = X86ISD::WrapperRIP;
2808 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2809 G->getOffset(), OpFlags);
2811 // Add a wrapper if needed.
2812 if (WrapperKind != ISD::DELETED_NODE)
2813 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
2814 // Add extra indirection if needed.
2816 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
2817 MachinePointerInfo::getGOT(),
2818 false, false, false, 0);
2820 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2821 unsigned char OpFlags = 0;
2823 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
2824 // external symbols should go through the PLT.
2825 if (Subtarget->isTargetELF() &&
2826 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2827 OpFlags = X86II::MO_PLT;
2828 } else if (Subtarget->isPICStyleStubAny() &&
2829 (!Subtarget->getTargetTriple().isMacOSX() ||
2830 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2831 // PC-relative references to external symbols should go through $stub,
2832 // unless we're building with the leopard linker or later, which
2833 // automatically synthesizes these stubs.
2834 OpFlags = X86II::MO_DARWIN_STUB;
2837 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2841 // Returns a chain & a flag for retval copy to use.
2842 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2843 SmallVector<SDValue, 8> Ops;
2845 if (!IsSibcall && isTailCall) {
2846 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2847 DAG.getIntPtrConstant(0, true), InFlag, dl);
2848 InFlag = Chain.getValue(1);
2851 Ops.push_back(Chain);
2852 Ops.push_back(Callee);
2855 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2857 // Add argument registers to the end of the list so that they are known live
2859 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2860 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2861 RegsToPass[i].second.getValueType()));
2863 // Add a register mask operand representing the call-preserved registers.
2864 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2865 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
2866 assert(Mask && "Missing call preserved mask for calling convention");
2867 Ops.push_back(DAG.getRegisterMask(Mask));
2869 if (InFlag.getNode())
2870 Ops.push_back(InFlag);
2874 //// If this is the first return lowered for this function, add the regs
2875 //// to the liveout set for the function.
2876 // This isn't right, although it's probably harmless on x86; liveouts
2877 // should be computed from returns not tail calls. Consider a void
2878 // function making a tail call to a function returning int.
2879 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size());
2882 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2883 InFlag = Chain.getValue(1);
2885 // Create the CALLSEQ_END node.
2886 unsigned NumBytesForCalleeToPush;
2887 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2888 getTargetMachine().Options.GuaranteedTailCallOpt))
2889 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2890 else if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows &&
2891 SR == StackStructReturn)
2892 // If this is a call to a struct-return function, the callee
2893 // pops the hidden struct pointer, so we have to push it back.
2894 // This is common for Darwin/X86, Linux & Mingw32 targets.
2895 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
2896 NumBytesForCalleeToPush = 4;
2898 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2900 // Returns a flag for retval copy to use.
2902 Chain = DAG.getCALLSEQ_END(Chain,
2903 DAG.getIntPtrConstant(NumBytes, true),
2904 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2907 InFlag = Chain.getValue(1);
2910 // Handle result values, copying them out of physregs into vregs that we
2912 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2913 Ins, dl, DAG, InVals);
2916 //===----------------------------------------------------------------------===//
2917 // Fast Calling Convention (tail call) implementation
2918 //===----------------------------------------------------------------------===//
2920 // Like std call, callee cleans arguments, convention except that ECX is
2921 // reserved for storing the tail called function address. Only 2 registers are
2922 // free for argument passing (inreg). Tail call optimization is performed
2924 // * tailcallopt is enabled
2925 // * caller/callee are fastcc
2926 // On X86_64 architecture with GOT-style position independent code only local
2927 // (within module) calls are supported at the moment.
2928 // To keep the stack aligned according to platform abi the function
2929 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2930 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2931 // If a tail called function callee has more arguments than the caller the
2932 // caller needs to make sure that there is room to move the RETADDR to. This is
2933 // achieved by reserving an area the size of the argument delta right after the
2934 // original REtADDR, but before the saved framepointer or the spilled registers
2935 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2947 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2948 /// for a 16 byte align requirement.
2950 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2951 SelectionDAG& DAG) const {
2952 MachineFunction &MF = DAG.getMachineFunction();
2953 const TargetMachine &TM = MF.getTarget();
2954 const X86RegisterInfo *RegInfo =
2955 static_cast<const X86RegisterInfo*>(TM.getRegisterInfo());
2956 const TargetFrameLowering &TFI = *TM.getFrameLowering();
2957 unsigned StackAlignment = TFI.getStackAlignment();
2958 uint64_t AlignMask = StackAlignment - 1;
2959 int64_t Offset = StackSize;
2960 unsigned SlotSize = RegInfo->getSlotSize();
2961 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2962 // Number smaller than 12 so just add the difference.
2963 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2965 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2966 Offset = ((~AlignMask) & Offset) + StackAlignment +
2967 (StackAlignment-SlotSize);
2972 /// MatchingStackOffset - Return true if the given stack call argument is
2973 /// already available in the same position (relatively) of the caller's
2974 /// incoming argument stack.
2976 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2977 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
2978 const X86InstrInfo *TII) {
2979 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
2981 if (Arg.getOpcode() == ISD::CopyFromReg) {
2982 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2983 if (!TargetRegisterInfo::isVirtualRegister(VR))
2985 MachineInstr *Def = MRI->getVRegDef(VR);
2988 if (!Flags.isByVal()) {
2989 if (!TII->isLoadFromStackSlot(Def, FI))
2992 unsigned Opcode = Def->getOpcode();
2993 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
2994 Def->getOperand(1).isFI()) {
2995 FI = Def->getOperand(1).getIndex();
2996 Bytes = Flags.getByValSize();
3000 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3001 if (Flags.isByVal())
3002 // ByVal argument is passed in as a pointer but it's now being
3003 // dereferenced. e.g.
3004 // define @foo(%struct.X* %A) {
3005 // tail call @bar(%struct.X* byval %A)
3008 SDValue Ptr = Ld->getBasePtr();
3009 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3012 FI = FINode->getIndex();
3013 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3014 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3015 FI = FINode->getIndex();
3016 Bytes = Flags.getByValSize();
3020 assert(FI != INT_MAX);
3021 if (!MFI->isFixedObjectIndex(FI))
3023 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3026 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3027 /// for tail call optimization. Targets which want to do tail call
3028 /// optimization should implement this function.
3030 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3031 CallingConv::ID CalleeCC,
3033 bool isCalleeStructRet,
3034 bool isCallerStructRet,
3036 const SmallVectorImpl<ISD::OutputArg> &Outs,
3037 const SmallVectorImpl<SDValue> &OutVals,
3038 const SmallVectorImpl<ISD::InputArg> &Ins,
3039 SelectionDAG &DAG) const {
3040 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3043 // If -tailcallopt is specified, make fastcc functions tail-callable.
3044 const MachineFunction &MF = DAG.getMachineFunction();
3045 const Function *CallerF = MF.getFunction();
3047 // If the function return type is x86_fp80 and the callee return type is not,
3048 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3049 // perform a tailcall optimization here.
3050 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3053 CallingConv::ID CallerCC = CallerF->getCallingConv();
3054 bool CCMatch = CallerCC == CalleeCC;
3055 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3056 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3058 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
3059 if (IsTailCallConvention(CalleeCC) && CCMatch)
3064 // Look for obvious safe cases to perform tail call optimization that do not
3065 // require ABI changes. This is what gcc calls sibcall.
3067 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3068 // emit a special epilogue.
3069 const X86RegisterInfo *RegInfo =
3070 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
3071 if (RegInfo->needsStackRealignment(MF))
3074 // Also avoid sibcall optimization if either caller or callee uses struct
3075 // return semantics.
3076 if (isCalleeStructRet || isCallerStructRet)
3079 // An stdcall caller is expected to clean up its arguments; the callee
3080 // isn't going to do that.
3081 if (!CCMatch && CallerCC == CallingConv::X86_StdCall)
3084 // Do not sibcall optimize vararg calls unless all arguments are passed via
3086 if (isVarArg && !Outs.empty()) {
3088 // Optimizing for varargs on Win64 is unlikely to be safe without
3089 // additional testing.
3090 if (IsCalleeWin64 || IsCallerWin64)
3093 SmallVector<CCValAssign, 16> ArgLocs;
3094 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
3095 getTargetMachine(), ArgLocs, *DAG.getContext());
3097 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3098 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3099 if (!ArgLocs[i].isRegLoc())
3103 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3104 // stack. Therefore, if it's not used by the call it is not safe to optimize
3105 // this into a sibcall.
3106 bool Unused = false;
3107 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3114 SmallVector<CCValAssign, 16> RVLocs;
3115 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(),
3116 getTargetMachine(), RVLocs, *DAG.getContext());
3117 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3118 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3119 CCValAssign &VA = RVLocs[i];
3120 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
3125 // If the calling conventions do not match, then we'd better make sure the
3126 // results are returned in the same way as what the caller expects.
3128 SmallVector<CCValAssign, 16> RVLocs1;
3129 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
3130 getTargetMachine(), RVLocs1, *DAG.getContext());
3131 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3133 SmallVector<CCValAssign, 16> RVLocs2;
3134 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
3135 getTargetMachine(), RVLocs2, *DAG.getContext());
3136 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3138 if (RVLocs1.size() != RVLocs2.size())
3140 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3141 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3143 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3145 if (RVLocs1[i].isRegLoc()) {
3146 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3149 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3155 // If the callee takes no arguments then go on to check the results of the
3157 if (!Outs.empty()) {
3158 // Check if stack adjustment is needed. For now, do not do this if any
3159 // argument is passed on the stack.
3160 SmallVector<CCValAssign, 16> ArgLocs;
3161 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
3162 getTargetMachine(), ArgLocs, *DAG.getContext());
3164 // Allocate shadow area for Win64
3166 CCInfo.AllocateStack(32, 8);
3168 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3169 if (CCInfo.getNextStackOffset()) {
3170 MachineFunction &MF = DAG.getMachineFunction();
3171 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3174 // Check if the arguments are already laid out in the right way as
3175 // the caller's fixed stack objects.
3176 MachineFrameInfo *MFI = MF.getFrameInfo();
3177 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3178 const X86InstrInfo *TII =
3179 ((const X86TargetMachine&)getTargetMachine()).getInstrInfo();
3180 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3181 CCValAssign &VA = ArgLocs[i];
3182 SDValue Arg = OutVals[i];
3183 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3184 if (VA.getLocInfo() == CCValAssign::Indirect)
3186 if (!VA.isRegLoc()) {
3187 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3194 // If the tailcall address may be in a register, then make sure it's
3195 // possible to register allocate for it. In 32-bit, the call address can
3196 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3197 // callee-saved registers are restored. These happen to be the same
3198 // registers used to pass 'inreg' arguments so watch out for those.
3199 if (!Subtarget->is64Bit() &&
3200 ((!isa<GlobalAddressSDNode>(Callee) &&
3201 !isa<ExternalSymbolSDNode>(Callee)) ||
3202 getTargetMachine().getRelocationModel() == Reloc::PIC_)) {
3203 unsigned NumInRegs = 0;
3204 // In PIC we need an extra register to formulate the address computation
3206 unsigned MaxInRegs =
3207 (getTargetMachine().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3209 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3210 CCValAssign &VA = ArgLocs[i];
3213 unsigned Reg = VA.getLocReg();
3216 case X86::EAX: case X86::EDX: case X86::ECX:
3217 if (++NumInRegs == MaxInRegs)
3229 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3230 const TargetLibraryInfo *libInfo) const {
3231 return X86::createFastISel(funcInfo, libInfo);
3234 //===----------------------------------------------------------------------===//
3235 // Other Lowering Hooks
3236 //===----------------------------------------------------------------------===//
3238 static bool MayFoldLoad(SDValue Op) {
3239 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3242 static bool MayFoldIntoStore(SDValue Op) {
3243 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3246 static bool isTargetShuffle(unsigned Opcode) {
3248 default: return false;
3249 case X86ISD::PSHUFD:
3250 case X86ISD::PSHUFHW:
3251 case X86ISD::PSHUFLW:
3253 case X86ISD::PALIGNR:
3254 case X86ISD::MOVLHPS:
3255 case X86ISD::MOVLHPD:
3256 case X86ISD::MOVHLPS:
3257 case X86ISD::MOVLPS:
3258 case X86ISD::MOVLPD:
3259 case X86ISD::MOVSHDUP:
3260 case X86ISD::MOVSLDUP:
3261 case X86ISD::MOVDDUP:
3264 case X86ISD::UNPCKL:
3265 case X86ISD::UNPCKH:
3266 case X86ISD::VPERMILP:
3267 case X86ISD::VPERM2X128:
3268 case X86ISD::VPERMI:
3273 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3274 SDValue V1, SelectionDAG &DAG) {
3276 default: llvm_unreachable("Unknown x86 shuffle node");
3277 case X86ISD::MOVSHDUP:
3278 case X86ISD::MOVSLDUP:
3279 case X86ISD::MOVDDUP:
3280 return DAG.getNode(Opc, dl, VT, V1);
3284 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3285 SDValue V1, unsigned TargetMask,
3286 SelectionDAG &DAG) {
3288 default: llvm_unreachable("Unknown x86 shuffle node");
3289 case X86ISD::PSHUFD:
3290 case X86ISD::PSHUFHW:
3291 case X86ISD::PSHUFLW:
3292 case X86ISD::VPERMILP:
3293 case X86ISD::VPERMI:
3294 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3298 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3299 SDValue V1, SDValue V2, unsigned TargetMask,
3300 SelectionDAG &DAG) {
3302 default: llvm_unreachable("Unknown x86 shuffle node");
3303 case X86ISD::PALIGNR:
3305 case X86ISD::VPERM2X128:
3306 return DAG.getNode(Opc, dl, VT, V1, V2,
3307 DAG.getConstant(TargetMask, MVT::i8));
3311 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3312 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3314 default: llvm_unreachable("Unknown x86 shuffle node");
3315 case X86ISD::MOVLHPS:
3316 case X86ISD::MOVLHPD:
3317 case X86ISD::MOVHLPS:
3318 case X86ISD::MOVLPS:
3319 case X86ISD::MOVLPD:
3322 case X86ISD::UNPCKL:
3323 case X86ISD::UNPCKH:
3324 return DAG.getNode(Opc, dl, VT, V1, V2);
3328 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3329 MachineFunction &MF = DAG.getMachineFunction();
3330 const X86RegisterInfo *RegInfo =
3331 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
3332 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3333 int ReturnAddrIndex = FuncInfo->getRAIndex();
3335 if (ReturnAddrIndex == 0) {
3336 // Set up a frame object for the return address.
3337 unsigned SlotSize = RegInfo->getSlotSize();
3338 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3341 FuncInfo->setRAIndex(ReturnAddrIndex);
3344 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3347 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3348 bool hasSymbolicDisplacement) {
3349 // Offset should fit into 32 bit immediate field.
3350 if (!isInt<32>(Offset))
3353 // If we don't have a symbolic displacement - we don't have any extra
3355 if (!hasSymbolicDisplacement)
3358 // FIXME: Some tweaks might be needed for medium code model.
3359 if (M != CodeModel::Small && M != CodeModel::Kernel)
3362 // For small code model we assume that latest object is 16MB before end of 31
3363 // bits boundary. We may also accept pretty large negative constants knowing
3364 // that all objects are in the positive half of address space.
3365 if (M == CodeModel::Small && Offset < 16*1024*1024)
3368 // For kernel code model we know that all object resist in the negative half
3369 // of 32bits address space. We may not accept negative offsets, since they may
3370 // be just off and we may accept pretty large positive ones.
3371 if (M == CodeModel::Kernel && Offset > 0)
3377 /// isCalleePop - Determines whether the callee is required to pop its
3378 /// own arguments. Callee pop is necessary to support tail calls.
3379 bool X86::isCalleePop(CallingConv::ID CallingConv,
3380 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3384 switch (CallingConv) {
3387 case CallingConv::X86_StdCall:
3389 case CallingConv::X86_FastCall:
3391 case CallingConv::X86_ThisCall:
3393 case CallingConv::Fast:
3395 case CallingConv::GHC:
3397 case CallingConv::HiPE:
3402 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3403 /// specific condition code, returning the condition code and the LHS/RHS of the
3404 /// comparison to make.
3405 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3406 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3408 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3409 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3410 // X > -1 -> X == 0, jump !sign.
3411 RHS = DAG.getConstant(0, RHS.getValueType());
3412 return X86::COND_NS;
3414 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3415 // X < 0 -> X == 0, jump on sign.
3418 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3420 RHS = DAG.getConstant(0, RHS.getValueType());
3421 return X86::COND_LE;
3425 switch (SetCCOpcode) {
3426 default: llvm_unreachable("Invalid integer condition!");
3427 case ISD::SETEQ: return X86::COND_E;
3428 case ISD::SETGT: return X86::COND_G;
3429 case ISD::SETGE: return X86::COND_GE;
3430 case ISD::SETLT: return X86::COND_L;
3431 case ISD::SETLE: return X86::COND_LE;
3432 case ISD::SETNE: return X86::COND_NE;
3433 case ISD::SETULT: return X86::COND_B;
3434 case ISD::SETUGT: return X86::COND_A;
3435 case ISD::SETULE: return X86::COND_BE;
3436 case ISD::SETUGE: return X86::COND_AE;
3440 // First determine if it is required or is profitable to flip the operands.
3442 // If LHS is a foldable load, but RHS is not, flip the condition.
3443 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3444 !ISD::isNON_EXTLoad(RHS.getNode())) {
3445 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3446 std::swap(LHS, RHS);
3449 switch (SetCCOpcode) {
3455 std::swap(LHS, RHS);
3459 // On a floating point condition, the flags are set as follows:
3461 // 0 | 0 | 0 | X > Y
3462 // 0 | 0 | 1 | X < Y
3463 // 1 | 0 | 0 | X == Y
3464 // 1 | 1 | 1 | unordered
3465 switch (SetCCOpcode) {
3466 default: llvm_unreachable("Condcode should be pre-legalized away");
3468 case ISD::SETEQ: return X86::COND_E;
3469 case ISD::SETOLT: // flipped
3471 case ISD::SETGT: return X86::COND_A;
3472 case ISD::SETOLE: // flipped
3474 case ISD::SETGE: return X86::COND_AE;
3475 case ISD::SETUGT: // flipped
3477 case ISD::SETLT: return X86::COND_B;
3478 case ISD::SETUGE: // flipped
3480 case ISD::SETLE: return X86::COND_BE;
3482 case ISD::SETNE: return X86::COND_NE;
3483 case ISD::SETUO: return X86::COND_P;
3484 case ISD::SETO: return X86::COND_NP;
3486 case ISD::SETUNE: return X86::COND_INVALID;
3490 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3491 /// code. Current x86 isa includes the following FP cmov instructions:
3492 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3493 static bool hasFPCMov(unsigned X86CC) {
3509 /// isFPImmLegal - Returns true if the target can instruction select the
3510 /// specified FP immediate natively. If false, the legalizer will
3511 /// materialize the FP immediate as a load from a constant pool.
3512 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3513 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3514 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3520 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3521 /// the specified range (L, H].
3522 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3523 return (Val < 0) || (Val >= Low && Val < Hi);
3526 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3527 /// specified value.
3528 static bool isUndefOrEqual(int Val, int CmpVal) {
3529 return (Val < 0 || Val == CmpVal);
3532 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3533 /// from position Pos and ending in Pos+Size, falls within the specified
3534 /// sequential range (L, L+Pos]. or is undef.
3535 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3536 unsigned Pos, unsigned Size, int Low) {
3537 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3538 if (!isUndefOrEqual(Mask[i], Low))
3543 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3544 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3545 /// the second operand.
3546 static bool isPSHUFDMask(ArrayRef<int> Mask, MVT VT) {
3547 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3548 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3549 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3550 return (Mask[0] < 2 && Mask[1] < 2);
3554 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3555 /// is suitable for input to PSHUFHW.
3556 static bool isPSHUFHWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3557 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3560 // Lower quadword copied in order or undef.
3561 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3564 // Upper quadword shuffled.
3565 for (unsigned i = 4; i != 8; ++i)
3566 if (!isUndefOrInRange(Mask[i], 4, 8))
3569 if (VT == MVT::v16i16) {
3570 // Lower quadword copied in order or undef.
3571 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3574 // Upper quadword shuffled.
3575 for (unsigned i = 12; i != 16; ++i)
3576 if (!isUndefOrInRange(Mask[i], 12, 16))
3583 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3584 /// is suitable for input to PSHUFLW.
3585 static bool isPSHUFLWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3586 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3589 // Upper quadword copied in order.
3590 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3593 // Lower quadword shuffled.
3594 for (unsigned i = 0; i != 4; ++i)
3595 if (!isUndefOrInRange(Mask[i], 0, 4))
3598 if (VT == MVT::v16i16) {
3599 // Upper quadword copied in order.
3600 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3603 // Lower quadword shuffled.
3604 for (unsigned i = 8; i != 12; ++i)
3605 if (!isUndefOrInRange(Mask[i], 8, 12))
3612 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
3613 /// is suitable for input to PALIGNR.
3614 static bool isPALIGNRMask(ArrayRef<int> Mask, MVT VT,
3615 const X86Subtarget *Subtarget) {
3616 if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
3617 (VT.is256BitVector() && !Subtarget->hasInt256()))
3620 unsigned NumElts = VT.getVectorNumElements();
3621 unsigned NumLanes = VT.is512BitVector() ? 1: VT.getSizeInBits()/128;
3622 unsigned NumLaneElts = NumElts/NumLanes;
3624 // Do not handle 64-bit element shuffles with palignr.
3625 if (NumLaneElts == 2)
3628 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3630 for (i = 0; i != NumLaneElts; ++i) {
3635 // Lane is all undef, go to next lane
3636 if (i == NumLaneElts)
3639 int Start = Mask[i+l];
3641 // Make sure its in this lane in one of the sources
3642 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3643 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3646 // If not lane 0, then we must match lane 0
3647 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3650 // Correct second source to be contiguous with first source
3651 if (Start >= (int)NumElts)
3652 Start -= NumElts - NumLaneElts;
3654 // Make sure we're shifting in the right direction.
3655 if (Start <= (int)(i+l))
3660 // Check the rest of the elements to see if they are consecutive.
3661 for (++i; i != NumLaneElts; ++i) {
3662 int Idx = Mask[i+l];
3664 // Make sure its in this lane
3665 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3666 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3669 // If not lane 0, then we must match lane 0
3670 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3673 if (Idx >= (int)NumElts)
3674 Idx -= NumElts - NumLaneElts;
3676 if (!isUndefOrEqual(Idx, Start+i))
3685 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3686 /// the two vector operands have swapped position.
3687 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
3688 unsigned NumElems) {
3689 for (unsigned i = 0; i != NumElems; ++i) {
3693 else if (idx < (int)NumElems)
3694 Mask[i] = idx + NumElems;
3696 Mask[i] = idx - NumElems;
3700 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
3701 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
3702 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
3703 /// reverse of what x86 shuffles want.
3704 static bool isSHUFPMask(ArrayRef<int> Mask, MVT VT, bool Commuted = false) {
3706 unsigned NumElems = VT.getVectorNumElements();
3707 unsigned NumLanes = VT.getSizeInBits()/128;
3708 unsigned NumLaneElems = NumElems/NumLanes;
3710 if (NumLaneElems != 2 && NumLaneElems != 4)
3713 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3714 bool symetricMaskRequired =
3715 (VT.getSizeInBits() >= 256) && (EltSize == 32);
3717 // VSHUFPSY divides the resulting vector into 4 chunks.
3718 // The sources are also splitted into 4 chunks, and each destination
3719 // chunk must come from a different source chunk.
3721 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
3722 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
3724 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
3725 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
3727 // VSHUFPDY divides the resulting vector into 4 chunks.
3728 // The sources are also splitted into 4 chunks, and each destination
3729 // chunk must come from a different source chunk.
3731 // SRC1 => X3 X2 X1 X0
3732 // SRC2 => Y3 Y2 Y1 Y0
3734 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
3736 SmallVector<int, 4> MaskVal(NumLaneElems, -1);
3737 unsigned HalfLaneElems = NumLaneElems/2;
3738 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
3739 for (unsigned i = 0; i != NumLaneElems; ++i) {
3740 int Idx = Mask[i+l];
3741 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
3742 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
3744 // For VSHUFPSY, the mask of the second half must be the same as the
3745 // first but with the appropriate offsets. This works in the same way as
3746 // VPERMILPS works with masks.
3747 if (!symetricMaskRequired || Idx < 0)
3749 if (MaskVal[i] < 0) {
3750 MaskVal[i] = Idx - l;
3753 if ((signed)(Idx - l) != MaskVal[i])
3761 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
3762 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
3763 static bool isMOVHLPSMask(ArrayRef<int> Mask, MVT VT) {
3764 if (!VT.is128BitVector())
3767 unsigned NumElems = VT.getVectorNumElements();
3772 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
3773 return isUndefOrEqual(Mask[0], 6) &&
3774 isUndefOrEqual(Mask[1], 7) &&
3775 isUndefOrEqual(Mask[2], 2) &&
3776 isUndefOrEqual(Mask[3], 3);
3779 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
3780 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
3782 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, MVT VT) {
3783 if (!VT.is128BitVector())
3786 unsigned NumElems = VT.getVectorNumElements();
3791 return isUndefOrEqual(Mask[0], 2) &&
3792 isUndefOrEqual(Mask[1], 3) &&
3793 isUndefOrEqual(Mask[2], 2) &&
3794 isUndefOrEqual(Mask[3], 3);
3797 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
3798 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
3799 static bool isMOVLPMask(ArrayRef<int> Mask, MVT VT) {
3800 if (!VT.is128BitVector())
3803 unsigned NumElems = VT.getVectorNumElements();
3805 if (NumElems != 2 && NumElems != 4)
3808 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3809 if (!isUndefOrEqual(Mask[i], i + NumElems))
3812 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
3813 if (!isUndefOrEqual(Mask[i], i))
3819 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
3820 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
3821 static bool isMOVLHPSMask(ArrayRef<int> Mask, MVT VT) {
3822 if (!VT.is128BitVector())
3825 unsigned NumElems = VT.getVectorNumElements();
3827 if (NumElems != 2 && NumElems != 4)
3830 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3831 if (!isUndefOrEqual(Mask[i], i))
3834 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3835 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
3842 // Some special combinations that can be optimized.
3845 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
3846 SelectionDAG &DAG) {
3847 MVT VT = SVOp->getSimpleValueType(0);
3850 if (VT != MVT::v8i32 && VT != MVT::v8f32)
3853 ArrayRef<int> Mask = SVOp->getMask();
3855 // These are the special masks that may be optimized.
3856 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
3857 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
3858 bool MatchEvenMask = true;
3859 bool MatchOddMask = true;
3860 for (int i=0; i<8; ++i) {
3861 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
3862 MatchEvenMask = false;
3863 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
3864 MatchOddMask = false;
3867 if (!MatchEvenMask && !MatchOddMask)
3870 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
3872 SDValue Op0 = SVOp->getOperand(0);
3873 SDValue Op1 = SVOp->getOperand(1);
3875 if (MatchEvenMask) {
3876 // Shift the second operand right to 32 bits.
3877 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 };
3878 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
3880 // Shift the first operand left to 32 bits.
3881 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 };
3882 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
3884 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15};
3885 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
3888 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
3889 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
3890 static bool isUNPCKLMask(ArrayRef<int> Mask, MVT VT,
3891 bool HasInt256, bool V2IsSplat = false) {
3893 assert(VT.getSizeInBits() >= 128 &&
3894 "Unsupported vector type for unpckl");
3896 // AVX defines UNPCK* to operate independently on 128-bit lanes.
3898 unsigned NumOf256BitLanes;
3899 unsigned NumElts = VT.getVectorNumElements();
3900 if (VT.is256BitVector()) {
3901 if (NumElts != 4 && NumElts != 8 &&
3902 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
3905 NumOf256BitLanes = 1;
3906 } else if (VT.is512BitVector()) {
3907 assert(VT.getScalarType().getSizeInBits() >= 32 &&
3908 "Unsupported vector type for unpckh");
3910 NumOf256BitLanes = 2;
3913 NumOf256BitLanes = 1;
3916 unsigned NumEltsInStride = NumElts/NumOf256BitLanes;
3917 unsigned NumLaneElts = NumEltsInStride/NumLanes;
3919 for (unsigned l256 = 0; l256 < NumOf256BitLanes; l256 += 1) {
3920 for (unsigned l = 0; l != NumEltsInStride; l += NumLaneElts) {
3921 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
3922 int BitI = Mask[l256*NumEltsInStride+l+i];
3923 int BitI1 = Mask[l256*NumEltsInStride+l+i+1];
3924 if (!isUndefOrEqual(BitI, j+l256*NumElts))
3926 if (V2IsSplat && !isUndefOrEqual(BitI1, NumElts))
3928 if (!isUndefOrEqual(BitI1, j+l256*NumElts+NumEltsInStride))
3936 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
3937 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
3938 static bool isUNPCKHMask(ArrayRef<int> Mask, MVT VT,
3939 bool HasInt256, bool V2IsSplat = false) {
3940 assert(VT.getSizeInBits() >= 128 &&
3941 "Unsupported vector type for unpckh");
3943 // AVX defines UNPCK* to operate independently on 128-bit lanes.
3945 unsigned NumOf256BitLanes;
3946 unsigned NumElts = VT.getVectorNumElements();
3947 if (VT.is256BitVector()) {
3948 if (NumElts != 4 && NumElts != 8 &&
3949 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
3952 NumOf256BitLanes = 1;
3953 } else if (VT.is512BitVector()) {
3954 assert(VT.getScalarType().getSizeInBits() >= 32 &&
3955 "Unsupported vector type for unpckh");
3957 NumOf256BitLanes = 2;
3960 NumOf256BitLanes = 1;
3963 unsigned NumEltsInStride = NumElts/NumOf256BitLanes;
3964 unsigned NumLaneElts = NumEltsInStride/NumLanes;
3966 for (unsigned l256 = 0; l256 < NumOf256BitLanes; l256 += 1) {
3967 for (unsigned l = 0; l != NumEltsInStride; l += NumLaneElts) {
3968 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
3969 int BitI = Mask[l256*NumEltsInStride+l+i];
3970 int BitI1 = Mask[l256*NumEltsInStride+l+i+1];
3971 if (!isUndefOrEqual(BitI, j+l256*NumElts))
3973 if (V2IsSplat && !isUndefOrEqual(BitI1, NumElts))
3975 if (!isUndefOrEqual(BitI1, j+l256*NumElts+NumEltsInStride))
3983 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
3984 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
3986 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3987 unsigned NumElts = VT.getVectorNumElements();
3988 bool Is256BitVec = VT.is256BitVector();
3990 if (VT.is512BitVector())
3992 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3993 "Unsupported vector type for unpckh");
3995 if (Is256BitVec && NumElts != 4 && NumElts != 8 &&
3996 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
3999 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
4000 // FIXME: Need a better way to get rid of this, there's no latency difference
4001 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
4002 // the former later. We should also remove the "_undef" special mask.
4003 if (NumElts == 4 && Is256BitVec)
4006 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4007 // independently on 128-bit lanes.
4008 unsigned NumLanes = VT.getSizeInBits()/128;
4009 unsigned NumLaneElts = NumElts/NumLanes;
4011 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4012 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4013 int BitI = Mask[l+i];
4014 int BitI1 = Mask[l+i+1];
4016 if (!isUndefOrEqual(BitI, j))
4018 if (!isUndefOrEqual(BitI1, j))
4026 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
4027 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
4029 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4030 unsigned NumElts = VT.getVectorNumElements();
4032 if (VT.is512BitVector())
4035 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4036 "Unsupported vector type for unpckh");
4038 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4039 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4042 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4043 // independently on 128-bit lanes.
4044 unsigned NumLanes = VT.getSizeInBits()/128;
4045 unsigned NumLaneElts = NumElts/NumLanes;
4047 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4048 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4049 int BitI = Mask[l+i];
4050 int BitI1 = Mask[l+i+1];
4051 if (!isUndefOrEqual(BitI, j))
4053 if (!isUndefOrEqual(BitI1, j))
4060 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
4061 /// specifies a shuffle of elements that is suitable for input to MOVSS,
4062 /// MOVSD, and MOVD, i.e. setting the lowest element.
4063 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
4064 if (VT.getVectorElementType().getSizeInBits() < 32)
4066 if (!VT.is128BitVector())
4069 unsigned NumElts = VT.getVectorNumElements();
4071 if (!isUndefOrEqual(Mask[0], NumElts))
4074 for (unsigned i = 1; i != NumElts; ++i)
4075 if (!isUndefOrEqual(Mask[i], i))
4081 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
4082 /// as permutations between 128-bit chunks or halves. As an example: this
4084 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
4085 /// The first half comes from the second half of V1 and the second half from the
4086 /// the second half of V2.
4087 static bool isVPERM2X128Mask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4088 if (!HasFp256 || !VT.is256BitVector())
4091 // The shuffle result is divided into half A and half B. In total the two
4092 // sources have 4 halves, namely: C, D, E, F. The final values of A and
4093 // B must come from C, D, E or F.
4094 unsigned HalfSize = VT.getVectorNumElements()/2;
4095 bool MatchA = false, MatchB = false;
4097 // Check if A comes from one of C, D, E, F.
4098 for (unsigned Half = 0; Half != 4; ++Half) {
4099 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
4105 // Check if B comes from one of C, D, E, F.
4106 for (unsigned Half = 0; Half != 4; ++Half) {
4107 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
4113 return MatchA && MatchB;
4116 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
4117 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
4118 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
4119 MVT VT = SVOp->getSimpleValueType(0);
4121 unsigned HalfSize = VT.getVectorNumElements()/2;
4123 unsigned FstHalf = 0, SndHalf = 0;
4124 for (unsigned i = 0; i < HalfSize; ++i) {
4125 if (SVOp->getMaskElt(i) > 0) {
4126 FstHalf = SVOp->getMaskElt(i)/HalfSize;
4130 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
4131 if (SVOp->getMaskElt(i) > 0) {
4132 SndHalf = SVOp->getMaskElt(i)/HalfSize;
4137 return (FstHalf | (SndHalf << 4));
4140 // Symetric in-lane mask. Each lane has 4 elements (for imm8)
4141 static bool isPermImmMask(ArrayRef<int> Mask, MVT VT, unsigned& Imm8) {
4142 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4146 unsigned NumElts = VT.getVectorNumElements();
4148 if (VT.is128BitVector() || (VT.is256BitVector() && EltSize == 64)) {
4149 for (unsigned i = 0; i != NumElts; ++i) {
4152 Imm8 |= Mask[i] << (i*2);
4157 unsigned LaneSize = 4;
4158 SmallVector<int, 4> MaskVal(LaneSize, -1);
4160 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4161 for (unsigned i = 0; i != LaneSize; ++i) {
4162 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4166 if (MaskVal[i] < 0) {
4167 MaskVal[i] = Mask[i+l] - l;
4168 Imm8 |= MaskVal[i] << (i*2);
4171 if (Mask[i+l] != (signed)(MaskVal[i]+l))
4178 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
4179 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
4180 /// Note that VPERMIL mask matching is different depending whether theunderlying
4181 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
4182 /// to the same elements of the low, but to the higher half of the source.
4183 /// In VPERMILPD the two lanes could be shuffled independently of each other
4184 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
4185 static bool isVPERMILPMask(ArrayRef<int> Mask, MVT VT) {
4186 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4187 if (VT.getSizeInBits() < 256 || EltSize < 32)
4189 bool symetricMaskRequired = (EltSize == 32);
4190 unsigned NumElts = VT.getVectorNumElements();
4192 unsigned NumLanes = VT.getSizeInBits()/128;
4193 unsigned LaneSize = NumElts/NumLanes;
4194 // 2 or 4 elements in one lane
4196 SmallVector<int, 4> ExpectedMaskVal(LaneSize, -1);
4197 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4198 for (unsigned i = 0; i != LaneSize; ++i) {
4199 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4201 if (symetricMaskRequired) {
4202 if (ExpectedMaskVal[i] < 0 && Mask[i+l] >= 0) {
4203 ExpectedMaskVal[i] = Mask[i+l] - l;
4206 if (!isUndefOrEqual(Mask[i+l], ExpectedMaskVal[i]+l))
4214 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
4215 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
4216 /// element of vector 2 and the other elements to come from vector 1 in order.
4217 static bool isCommutedMOVLMask(ArrayRef<int> Mask, MVT VT,
4218 bool V2IsSplat = false, bool V2IsUndef = false) {
4219 if (!VT.is128BitVector())
4222 unsigned NumOps = VT.getVectorNumElements();
4223 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
4226 if (!isUndefOrEqual(Mask[0], 0))
4229 for (unsigned i = 1; i != NumOps; ++i)
4230 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
4231 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
4232 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
4238 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4239 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
4240 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
4241 static bool isMOVSHDUPMask(ArrayRef<int> Mask, MVT VT,
4242 const X86Subtarget *Subtarget) {
4243 if (!Subtarget->hasSSE3())
4246 unsigned NumElems = VT.getVectorNumElements();
4248 if ((VT.is128BitVector() && NumElems != 4) ||
4249 (VT.is256BitVector() && NumElems != 8) ||
4250 (VT.is512BitVector() && NumElems != 16))
4253 // "i+1" is the value the indexed mask element must have
4254 for (unsigned i = 0; i != NumElems; i += 2)
4255 if (!isUndefOrEqual(Mask[i], i+1) ||
4256 !isUndefOrEqual(Mask[i+1], i+1))
4262 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4263 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
4264 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
4265 static bool isMOVSLDUPMask(ArrayRef<int> Mask, MVT VT,
4266 const X86Subtarget *Subtarget) {
4267 if (!Subtarget->hasSSE3())
4270 unsigned NumElems = VT.getVectorNumElements();
4272 if ((VT.is128BitVector() && NumElems != 4) ||
4273 (VT.is256BitVector() && NumElems != 8) ||
4274 (VT.is512BitVector() && NumElems != 16))
4277 // "i" is the value the indexed mask element must have
4278 for (unsigned i = 0; i != NumElems; i += 2)
4279 if (!isUndefOrEqual(Mask[i], i) ||
4280 !isUndefOrEqual(Mask[i+1], i))
4286 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
4287 /// specifies a shuffle of elements that is suitable for input to 256-bit
4288 /// version of MOVDDUP.
4289 static bool isMOVDDUPYMask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4290 if (!HasFp256 || !VT.is256BitVector())
4293 unsigned NumElts = VT.getVectorNumElements();
4297 for (unsigned i = 0; i != NumElts/2; ++i)
4298 if (!isUndefOrEqual(Mask[i], 0))
4300 for (unsigned i = NumElts/2; i != NumElts; ++i)
4301 if (!isUndefOrEqual(Mask[i], NumElts/2))
4306 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4307 /// specifies a shuffle of elements that is suitable for input to 128-bit
4308 /// version of MOVDDUP.
4309 static bool isMOVDDUPMask(ArrayRef<int> Mask, MVT VT) {
4310 if (!VT.is128BitVector())
4313 unsigned e = VT.getVectorNumElements() / 2;
4314 for (unsigned i = 0; i != e; ++i)
4315 if (!isUndefOrEqual(Mask[i], i))
4317 for (unsigned i = 0; i != e; ++i)
4318 if (!isUndefOrEqual(Mask[e+i], i))
4323 /// isVEXTRACTIndex - Return true if the specified
4324 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
4325 /// suitable for instruction that extract 128 or 256 bit vectors
4326 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4327 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4328 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4331 // The index should be aligned on a vecWidth-bit boundary.
4333 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4335 MVT VT = N->getSimpleValueType(0);
4336 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4337 bool Result = (Index * ElSize) % vecWidth == 0;
4342 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
4343 /// operand specifies a subvector insert that is suitable for input to
4344 /// insertion of 128 or 256-bit subvectors
4345 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4346 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4347 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4349 // The index should be aligned on a vecWidth-bit boundary.
4351 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4353 MVT VT = N->getSimpleValueType(0);
4354 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4355 bool Result = (Index * ElSize) % vecWidth == 0;
4360 bool X86::isVINSERT128Index(SDNode *N) {
4361 return isVINSERTIndex(N, 128);
4364 bool X86::isVINSERT256Index(SDNode *N) {
4365 return isVINSERTIndex(N, 256);
4368 bool X86::isVEXTRACT128Index(SDNode *N) {
4369 return isVEXTRACTIndex(N, 128);
4372 bool X86::isVEXTRACT256Index(SDNode *N) {
4373 return isVEXTRACTIndex(N, 256);
4376 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4377 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4378 /// Handles 128-bit and 256-bit.
4379 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
4380 MVT VT = N->getSimpleValueType(0);
4382 assert((VT.getSizeInBits() >= 128) &&
4383 "Unsupported vector type for PSHUF/SHUFP");
4385 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
4386 // independently on 128-bit lanes.
4387 unsigned NumElts = VT.getVectorNumElements();
4388 unsigned NumLanes = VT.getSizeInBits()/128;
4389 unsigned NumLaneElts = NumElts/NumLanes;
4391 assert((NumLaneElts == 2 || NumLaneElts == 4 || NumLaneElts == 8) &&
4392 "Only supports 2, 4 or 8 elements per lane");
4394 unsigned Shift = (NumLaneElts >= 4) ? 1 : 0;
4396 for (unsigned i = 0; i != NumElts; ++i) {
4397 int Elt = N->getMaskElt(i);
4398 if (Elt < 0) continue;
4399 Elt &= NumLaneElts - 1;
4400 unsigned ShAmt = (i << Shift) % 8;
4401 Mask |= Elt << ShAmt;
4407 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4408 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4409 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4410 MVT VT = N->getSimpleValueType(0);
4412 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4413 "Unsupported vector type for PSHUFHW");
4415 unsigned NumElts = VT.getVectorNumElements();
4418 for (unsigned l = 0; l != NumElts; l += 8) {
4419 // 8 nodes per lane, but we only care about the last 4.
4420 for (unsigned i = 0; i < 4; ++i) {
4421 int Elt = N->getMaskElt(l+i+4);
4422 if (Elt < 0) continue;
4423 Elt &= 0x3; // only 2-bits.
4424 Mask |= Elt << (i * 2);
4431 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4432 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4433 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4434 MVT VT = N->getSimpleValueType(0);
4436 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4437 "Unsupported vector type for PSHUFHW");
4439 unsigned NumElts = VT.getVectorNumElements();
4442 for (unsigned l = 0; l != NumElts; l += 8) {
4443 // 8 nodes per lane, but we only care about the first 4.
4444 for (unsigned i = 0; i < 4; ++i) {
4445 int Elt = N->getMaskElt(l+i);
4446 if (Elt < 0) continue;
4447 Elt &= 0x3; // only 2-bits
4448 Mask |= Elt << (i * 2);
4455 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
4456 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
4457 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4458 MVT VT = SVOp->getSimpleValueType(0);
4459 unsigned EltSize = VT.is512BitVector() ? 1 :
4460 VT.getVectorElementType().getSizeInBits() >> 3;
4462 unsigned NumElts = VT.getVectorNumElements();
4463 unsigned NumLanes = VT.is512BitVector() ? 1 : VT.getSizeInBits()/128;
4464 unsigned NumLaneElts = NumElts/NumLanes;
4468 for (i = 0; i != NumElts; ++i) {
4469 Val = SVOp->getMaskElt(i);
4473 if (Val >= (int)NumElts)
4474 Val -= NumElts - NumLaneElts;
4476 assert(Val - i > 0 && "PALIGNR imm should be positive");
4477 return (Val - i) * EltSize;
4480 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4481 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4482 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4483 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4486 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4488 MVT VecVT = N->getOperand(0).getSimpleValueType();
4489 MVT ElVT = VecVT.getVectorElementType();
4491 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4492 return Index / NumElemsPerChunk;
4495 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4496 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4497 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4498 llvm_unreachable("Illegal insert subvector for VINSERT");
4501 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4503 MVT VecVT = N->getSimpleValueType(0);
4504 MVT ElVT = VecVT.getVectorElementType();
4506 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4507 return Index / NumElemsPerChunk;
4510 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
4511 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4512 /// and VINSERTI128 instructions.
4513 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4514 return getExtractVEXTRACTImmediate(N, 128);
4517 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
4518 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4519 /// and VINSERTI64x4 instructions.
4520 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4521 return getExtractVEXTRACTImmediate(N, 256);
4524 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4525 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4526 /// and VINSERTI128 instructions.
4527 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4528 return getInsertVINSERTImmediate(N, 128);
4531 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4532 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4533 /// and VINSERTI64x4 instructions.
4534 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4535 return getInsertVINSERTImmediate(N, 256);
4538 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4540 bool X86::isZeroNode(SDValue Elt) {
4541 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Elt))
4542 return CN->isNullValue();
4543 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4544 return CFP->getValueAPF().isPosZero();
4548 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
4549 /// their permute mask.
4550 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
4551 SelectionDAG &DAG) {
4552 MVT VT = SVOp->getSimpleValueType(0);
4553 unsigned NumElems = VT.getVectorNumElements();
4554 SmallVector<int, 8> MaskVec;
4556 for (unsigned i = 0; i != NumElems; ++i) {
4557 int Idx = SVOp->getMaskElt(i);
4559 if (Idx < (int)NumElems)
4564 MaskVec.push_back(Idx);
4566 return DAG.getVectorShuffle(VT, SDLoc(SVOp), SVOp->getOperand(1),
4567 SVOp->getOperand(0), &MaskVec[0]);
4570 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4571 /// match movhlps. The lower half elements should come from upper half of
4572 /// V1 (and in order), and the upper half elements should come from the upper
4573 /// half of V2 (and in order).
4574 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, MVT VT) {
4575 if (!VT.is128BitVector())
4577 if (VT.getVectorNumElements() != 4)
4579 for (unsigned i = 0, e = 2; i != e; ++i)
4580 if (!isUndefOrEqual(Mask[i], i+2))
4582 for (unsigned i = 2; i != 4; ++i)
4583 if (!isUndefOrEqual(Mask[i], i+4))
4588 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4589 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4591 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
4592 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4594 N = N->getOperand(0).getNode();
4595 if (!ISD::isNON_EXTLoad(N))
4598 *LD = cast<LoadSDNode>(N);
4602 // Test whether the given value is a vector value which will be legalized
4604 static bool WillBeConstantPoolLoad(SDNode *N) {
4605 if (N->getOpcode() != ISD::BUILD_VECTOR)
4608 // Check for any non-constant elements.
4609 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4610 switch (N->getOperand(i).getNode()->getOpcode()) {
4612 case ISD::ConstantFP:
4619 // Vectors of all-zeros and all-ones are materialized with special
4620 // instructions rather than being loaded.
4621 return !ISD::isBuildVectorAllZeros(N) &&
4622 !ISD::isBuildVectorAllOnes(N);
4625 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
4626 /// match movlp{s|d}. The lower half elements should come from lower half of
4627 /// V1 (and in order), and the upper half elements should come from the upper
4628 /// half of V2 (and in order). And since V1 will become the source of the
4629 /// MOVLP, it must be either a vector load or a scalar load to vector.
4630 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
4631 ArrayRef<int> Mask, MVT VT) {
4632 if (!VT.is128BitVector())
4635 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
4637 // Is V2 is a vector load, don't do this transformation. We will try to use
4638 // load folding shufps op.
4639 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
4642 unsigned NumElems = VT.getVectorNumElements();
4644 if (NumElems != 2 && NumElems != 4)
4646 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4647 if (!isUndefOrEqual(Mask[i], i))
4649 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4650 if (!isUndefOrEqual(Mask[i], i+NumElems))
4655 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
4657 static bool isSplatVector(SDNode *N) {
4658 if (N->getOpcode() != ISD::BUILD_VECTOR)
4661 SDValue SplatValue = N->getOperand(0);
4662 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
4663 if (N->getOperand(i) != SplatValue)
4668 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
4669 /// to an zero vector.
4670 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
4671 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
4672 SDValue V1 = N->getOperand(0);
4673 SDValue V2 = N->getOperand(1);
4674 unsigned NumElems = N->getValueType(0).getVectorNumElements();
4675 for (unsigned i = 0; i != NumElems; ++i) {
4676 int Idx = N->getMaskElt(i);
4677 if (Idx >= (int)NumElems) {
4678 unsigned Opc = V2.getOpcode();
4679 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
4681 if (Opc != ISD::BUILD_VECTOR ||
4682 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
4684 } else if (Idx >= 0) {
4685 unsigned Opc = V1.getOpcode();
4686 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
4688 if (Opc != ISD::BUILD_VECTOR ||
4689 !X86::isZeroNode(V1.getOperand(Idx)))
4696 /// getZeroVector - Returns a vector of specified type with all zero elements.
4698 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4699 SelectionDAG &DAG, SDLoc dl) {
4700 assert(VT.isVector() && "Expected a vector type");
4702 // Always build SSE zero vectors as <4 x i32> bitcasted
4703 // to their dest type. This ensures they get CSE'd.
4705 if (VT.is128BitVector()) { // SSE
4706 if (Subtarget->hasSSE2()) { // SSE2
4707 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4708 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4710 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4711 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4713 } else if (VT.is256BitVector()) { // AVX
4714 if (Subtarget->hasInt256()) { // AVX2
4715 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4716 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4717 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops,
4718 array_lengthof(Ops));
4720 // 256-bit logic and arithmetic instructions in AVX are all
4721 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4722 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4723 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4724 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops,
4725 array_lengthof(Ops));
4727 } else if (VT.is512BitVector()) { // AVX-512
4728 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4729 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4730 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4731 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops, 16);
4733 llvm_unreachable("Unexpected vector type");
4735 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4738 /// getOnesVector - Returns a vector of specified type with all bits set.
4739 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4740 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4741 /// Then bitcast to their original type, ensuring they get CSE'd.
4742 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
4744 assert(VT.isVector() && "Expected a vector type");
4746 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
4748 if (VT.is256BitVector()) {
4749 if (HasInt256) { // AVX2
4750 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4751 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops,
4752 array_lengthof(Ops));
4754 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4755 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4757 } else if (VT.is128BitVector()) {
4758 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4760 llvm_unreachable("Unexpected vector type");
4762 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4765 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
4766 /// that point to V2 points to its first element.
4767 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
4768 for (unsigned i = 0; i != NumElems; ++i) {
4769 if (Mask[i] > (int)NumElems) {
4775 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4776 /// operation of specified width.
4777 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
4779 unsigned NumElems = VT.getVectorNumElements();
4780 SmallVector<int, 8> Mask;
4781 Mask.push_back(NumElems);
4782 for (unsigned i = 1; i != NumElems; ++i)
4784 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4787 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4788 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4790 unsigned NumElems = VT.getVectorNumElements();
4791 SmallVector<int, 8> Mask;
4792 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4794 Mask.push_back(i + NumElems);
4796 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4799 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4800 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4802 unsigned NumElems = VT.getVectorNumElements();
4803 SmallVector<int, 8> Mask;
4804 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
4805 Mask.push_back(i + Half);
4806 Mask.push_back(i + NumElems + Half);
4808 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4811 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
4812 // a generic shuffle instruction because the target has no such instructions.
4813 // Generate shuffles which repeat i16 and i8 several times until they can be
4814 // represented by v4f32 and then be manipulated by target suported shuffles.
4815 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
4816 MVT VT = V.getSimpleValueType();
4817 int NumElems = VT.getVectorNumElements();
4820 while (NumElems > 4) {
4821 if (EltNo < NumElems/2) {
4822 V = getUnpackl(DAG, dl, VT, V, V);
4824 V = getUnpackh(DAG, dl, VT, V, V);
4825 EltNo -= NumElems/2;
4832 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
4833 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
4834 MVT VT = V.getSimpleValueType();
4837 if (VT.is128BitVector()) {
4838 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
4839 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
4840 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
4842 } else if (VT.is256BitVector()) {
4843 // To use VPERMILPS to splat scalars, the second half of indicies must
4844 // refer to the higher part, which is a duplication of the lower one,
4845 // because VPERMILPS can only handle in-lane permutations.
4846 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
4847 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
4849 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
4850 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
4853 llvm_unreachable("Vector size not supported");
4855 return DAG.getNode(ISD::BITCAST, dl, VT, V);
4858 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
4859 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
4860 MVT SrcVT = SV->getSimpleValueType(0);
4861 SDValue V1 = SV->getOperand(0);
4864 int EltNo = SV->getSplatIndex();
4865 int NumElems = SrcVT.getVectorNumElements();
4866 bool Is256BitVec = SrcVT.is256BitVector();
4868 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) &&
4869 "Unknown how to promote splat for type");
4871 // Extract the 128-bit part containing the splat element and update
4872 // the splat element index when it refers to the higher register.
4874 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
4875 if (EltNo >= NumElems/2)
4876 EltNo -= NumElems/2;
4879 // All i16 and i8 vector types can't be used directly by a generic shuffle
4880 // instruction because the target has no such instruction. Generate shuffles
4881 // which repeat i16 and i8 several times until they fit in i32, and then can
4882 // be manipulated by target suported shuffles.
4883 MVT EltVT = SrcVT.getVectorElementType();
4884 if (EltVT == MVT::i8 || EltVT == MVT::i16)
4885 V1 = PromoteSplati8i16(V1, DAG, EltNo);
4887 // Recreate the 256-bit vector and place the same 128-bit vector
4888 // into the low and high part. This is necessary because we want
4889 // to use VPERM* to shuffle the vectors
4891 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
4894 return getLegalSplat(DAG, V1, EltNo);
4897 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
4898 /// vector of zero or undef vector. This produces a shuffle where the low
4899 /// element of V2 is swizzled into the zero/undef vector, landing at element
4900 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4901 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4903 const X86Subtarget *Subtarget,
4904 SelectionDAG &DAG) {
4905 MVT VT = V2.getSimpleValueType();
4907 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
4908 unsigned NumElems = VT.getVectorNumElements();
4909 SmallVector<int, 16> MaskVec;
4910 for (unsigned i = 0; i != NumElems; ++i)
4911 // If this is the insertion idx, put the low elt of V2 here.
4912 MaskVec.push_back(i == Idx ? NumElems : i);
4913 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
4916 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
4917 /// target specific opcode. Returns true if the Mask could be calculated.
4918 /// Sets IsUnary to true if only uses one source.
4919 static bool getTargetShuffleMask(SDNode *N, MVT VT,
4920 SmallVectorImpl<int> &Mask, bool &IsUnary) {
4921 unsigned NumElems = VT.getVectorNumElements();
4925 switch(N->getOpcode()) {
4927 ImmN = N->getOperand(N->getNumOperands()-1);
4928 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4930 case X86ISD::UNPCKH:
4931 DecodeUNPCKHMask(VT, Mask);
4933 case X86ISD::UNPCKL:
4934 DecodeUNPCKLMask(VT, Mask);
4936 case X86ISD::MOVHLPS:
4937 DecodeMOVHLPSMask(NumElems, Mask);
4939 case X86ISD::MOVLHPS:
4940 DecodeMOVLHPSMask(NumElems, Mask);
4942 case X86ISD::PALIGNR:
4943 ImmN = N->getOperand(N->getNumOperands()-1);
4944 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4946 case X86ISD::PSHUFD:
4947 case X86ISD::VPERMILP:
4948 ImmN = N->getOperand(N->getNumOperands()-1);
4949 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4952 case X86ISD::PSHUFHW:
4953 ImmN = N->getOperand(N->getNumOperands()-1);
4954 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4957 case X86ISD::PSHUFLW:
4958 ImmN = N->getOperand(N->getNumOperands()-1);
4959 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4962 case X86ISD::VPERMI:
4963 ImmN = N->getOperand(N->getNumOperands()-1);
4964 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4968 case X86ISD::MOVSD: {
4969 // The index 0 always comes from the first element of the second source,
4970 // this is why MOVSS and MOVSD are used in the first place. The other
4971 // elements come from the other positions of the first source vector
4972 Mask.push_back(NumElems);
4973 for (unsigned i = 1; i != NumElems; ++i) {
4978 case X86ISD::VPERM2X128:
4979 ImmN = N->getOperand(N->getNumOperands()-1);
4980 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4981 if (Mask.empty()) return false;
4983 case X86ISD::MOVDDUP:
4984 case X86ISD::MOVLHPD:
4985 case X86ISD::MOVLPD:
4986 case X86ISD::MOVLPS:
4987 case X86ISD::MOVSHDUP:
4988 case X86ISD::MOVSLDUP:
4989 // Not yet implemented
4991 default: llvm_unreachable("unknown target shuffle node");
4997 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
4998 /// element of the result of the vector shuffle.
4999 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
5002 return SDValue(); // Limit search depth.
5004 SDValue V = SDValue(N, 0);
5005 EVT VT = V.getValueType();
5006 unsigned Opcode = V.getOpcode();
5008 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
5009 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
5010 int Elt = SV->getMaskElt(Index);
5013 return DAG.getUNDEF(VT.getVectorElementType());
5015 unsigned NumElems = VT.getVectorNumElements();
5016 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
5017 : SV->getOperand(1);
5018 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
5021 // Recurse into target specific vector shuffles to find scalars.
5022 if (isTargetShuffle(Opcode)) {
5023 MVT ShufVT = V.getSimpleValueType();
5024 unsigned NumElems = ShufVT.getVectorNumElements();
5025 SmallVector<int, 16> ShuffleMask;
5028 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
5031 int Elt = ShuffleMask[Index];
5033 return DAG.getUNDEF(ShufVT.getVectorElementType());
5035 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
5037 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
5041 // Actual nodes that may contain scalar elements
5042 if (Opcode == ISD::BITCAST) {
5043 V = V.getOperand(0);
5044 EVT SrcVT = V.getValueType();
5045 unsigned NumElems = VT.getVectorNumElements();
5047 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5051 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5052 return (Index == 0) ? V.getOperand(0)
5053 : DAG.getUNDEF(VT.getVectorElementType());
5055 if (V.getOpcode() == ISD::BUILD_VECTOR)
5056 return V.getOperand(Index);
5061 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
5062 /// shuffle operation which come from a consecutively from a zero. The
5063 /// search can start in two different directions, from left or right.
5064 /// We count undefs as zeros until PreferredNum is reached.
5065 static unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp,
5066 unsigned NumElems, bool ZerosFromLeft,
5068 unsigned PreferredNum = -1U) {
5069 unsigned NumZeros = 0;
5070 for (unsigned i = 0; i != NumElems; ++i) {
5071 unsigned Index = ZerosFromLeft ? i : NumElems - i - 1;
5072 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
5076 if (X86::isZeroNode(Elt))
5078 else if (Elt.getOpcode() == ISD::UNDEF) // Undef as zero up to PreferredNum.
5079 NumZeros = std::min(NumZeros + 1, PreferredNum);
5087 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
5088 /// correspond consecutively to elements from one of the vector operands,
5089 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
5091 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
5092 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
5093 unsigned NumElems, unsigned &OpNum) {
5094 bool SeenV1 = false;
5095 bool SeenV2 = false;
5097 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
5098 int Idx = SVOp->getMaskElt(i);
5099 // Ignore undef indicies
5103 if (Idx < (int)NumElems)
5108 // Only accept consecutive elements from the same vector
5109 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
5113 OpNum = SeenV1 ? 0 : 1;
5117 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
5118 /// logical left shift of a vector.
5119 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5120 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5122 SVOp->getSimpleValueType(0).getVectorNumElements();
5123 unsigned NumZeros = getNumOfConsecutiveZeros(
5124 SVOp, NumElems, false /* check zeros from right */, DAG,
5125 SVOp->getMaskElt(0));
5131 // Considering the elements in the mask that are not consecutive zeros,
5132 // check if they consecutively come from only one of the source vectors.
5134 // V1 = {X, A, B, C} 0
5136 // vector_shuffle V1, V2 <1, 2, 3, X>
5138 if (!isShuffleMaskConsecutive(SVOp,
5139 0, // Mask Start Index
5140 NumElems-NumZeros, // Mask End Index(exclusive)
5141 NumZeros, // Where to start looking in the src vector
5142 NumElems, // Number of elements in vector
5143 OpSrc)) // Which source operand ?
5148 ShVal = SVOp->getOperand(OpSrc);
5152 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
5153 /// logical left shift of a vector.
5154 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5155 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5157 SVOp->getSimpleValueType(0).getVectorNumElements();
5158 unsigned NumZeros = getNumOfConsecutiveZeros(
5159 SVOp, NumElems, true /* check zeros from left */, DAG,
5160 NumElems - SVOp->getMaskElt(NumElems - 1) - 1);
5166 // Considering the elements in the mask that are not consecutive zeros,
5167 // check if they consecutively come from only one of the source vectors.
5169 // 0 { A, B, X, X } = V2
5171 // vector_shuffle V1, V2 <X, X, 4, 5>
5173 if (!isShuffleMaskConsecutive(SVOp,
5174 NumZeros, // Mask Start Index
5175 NumElems, // Mask End Index(exclusive)
5176 0, // Where to start looking in the src vector
5177 NumElems, // Number of elements in vector
5178 OpSrc)) // Which source operand ?
5183 ShVal = SVOp->getOperand(OpSrc);
5187 /// isVectorShift - Returns true if the shuffle can be implemented as a
5188 /// logical left or right shift of a vector.
5189 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5190 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5191 // Although the logic below support any bitwidth size, there are no
5192 // shift instructions which handle more than 128-bit vectors.
5193 if (!SVOp->getSimpleValueType(0).is128BitVector())
5196 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
5197 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
5203 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
5205 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5206 unsigned NumNonZero, unsigned NumZero,
5208 const X86Subtarget* Subtarget,
5209 const TargetLowering &TLI) {
5216 for (unsigned i = 0; i < 16; ++i) {
5217 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5218 if (ThisIsNonZero && First) {
5220 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5222 V = DAG.getUNDEF(MVT::v8i16);
5227 SDValue ThisElt(0, 0), LastElt(0, 0);
5228 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5229 if (LastIsNonZero) {
5230 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5231 MVT::i16, Op.getOperand(i-1));
5233 if (ThisIsNonZero) {
5234 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5235 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5236 ThisElt, DAG.getConstant(8, MVT::i8));
5238 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5242 if (ThisElt.getNode())
5243 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5244 DAG.getIntPtrConstant(i/2));
5248 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
5251 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
5253 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5254 unsigned NumNonZero, unsigned NumZero,
5256 const X86Subtarget* Subtarget,
5257 const TargetLowering &TLI) {
5264 for (unsigned i = 0; i < 8; ++i) {
5265 bool isNonZero = (NonZeros & (1 << i)) != 0;
5269 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5271 V = DAG.getUNDEF(MVT::v8i16);
5274 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5275 MVT::v8i16, V, Op.getOperand(i),
5276 DAG.getIntPtrConstant(i));
5283 /// getVShift - Return a vector logical shift node.
5285 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5286 unsigned NumBits, SelectionDAG &DAG,
5287 const TargetLowering &TLI, SDLoc dl) {
5288 assert(VT.is128BitVector() && "Unknown type for VShift");
5289 EVT ShVT = MVT::v2i64;
5290 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5291 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
5292 return DAG.getNode(ISD::BITCAST, dl, VT,
5293 DAG.getNode(Opc, dl, ShVT, SrcOp,
5294 DAG.getConstant(NumBits,
5295 TLI.getScalarShiftAmountTy(SrcOp.getValueType()))));
5299 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5301 // Check if the scalar load can be widened into a vector load. And if
5302 // the address is "base + cst" see if the cst can be "absorbed" into
5303 // the shuffle mask.
5304 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5305 SDValue Ptr = LD->getBasePtr();
5306 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5308 EVT PVT = LD->getValueType(0);
5309 if (PVT != MVT::i32 && PVT != MVT::f32)
5314 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5315 FI = FINode->getIndex();
5317 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5318 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5319 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5320 Offset = Ptr.getConstantOperandVal(1);
5321 Ptr = Ptr.getOperand(0);
5326 // FIXME: 256-bit vector instructions don't require a strict alignment,
5327 // improve this code to support it better.
5328 unsigned RequiredAlign = VT.getSizeInBits()/8;
5329 SDValue Chain = LD->getChain();
5330 // Make sure the stack object alignment is at least 16 or 32.
5331 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5332 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5333 if (MFI->isFixedObjectIndex(FI)) {
5334 // Can't change the alignment. FIXME: It's possible to compute
5335 // the exact stack offset and reference FI + adjust offset instead.
5336 // If someone *really* cares about this. That's the way to implement it.
5339 MFI->setObjectAlignment(FI, RequiredAlign);
5343 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5344 // Ptr + (Offset & ~15).
5347 if ((Offset % RequiredAlign) & 3)
5349 int64_t StartOffset = Offset & ~(RequiredAlign-1);
5351 Ptr = DAG.getNode(ISD::ADD, SDLoc(Ptr), Ptr.getValueType(),
5352 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
5354 int EltNo = (Offset - StartOffset) >> 2;
5355 unsigned NumElems = VT.getVectorNumElements();
5357 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5358 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5359 LD->getPointerInfo().getWithOffset(StartOffset),
5360 false, false, false, 0);
5362 SmallVector<int, 8> Mask;
5363 for (unsigned i = 0; i != NumElems; ++i)
5364 Mask.push_back(EltNo);
5366 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5372 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
5373 /// vector of type 'VT', see if the elements can be replaced by a single large
5374 /// load which has the same value as a build_vector whose operands are 'elts'.
5376 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5378 /// FIXME: we'd also like to handle the case where the last elements are zero
5379 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5380 /// There's even a handy isZeroNode for that purpose.
5381 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
5382 SDLoc &DL, SelectionDAG &DAG) {
5383 EVT EltVT = VT.getVectorElementType();
5384 unsigned NumElems = Elts.size();
5386 LoadSDNode *LDBase = NULL;
5387 unsigned LastLoadedElt = -1U;
5389 // For each element in the initializer, see if we've found a load or an undef.
5390 // If we don't find an initial load element, or later load elements are
5391 // non-consecutive, bail out.
5392 for (unsigned i = 0; i < NumElems; ++i) {
5393 SDValue Elt = Elts[i];
5395 if (!Elt.getNode() ||
5396 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5399 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5401 LDBase = cast<LoadSDNode>(Elt.getNode());
5405 if (Elt.getOpcode() == ISD::UNDEF)
5408 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5409 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
5414 // If we have found an entire vector of loads and undefs, then return a large
5415 // load of the entire vector width starting at the base pointer. If we found
5416 // consecutive loads for the low half, generate a vzext_load node.
5417 if (LastLoadedElt == NumElems - 1) {
5418 SDValue NewLd = SDValue();
5419 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
5420 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5421 LDBase->getPointerInfo(),
5422 LDBase->isVolatile(), LDBase->isNonTemporal(),
5423 LDBase->isInvariant(), 0);
5424 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5425 LDBase->getPointerInfo(),
5426 LDBase->isVolatile(), LDBase->isNonTemporal(),
5427 LDBase->isInvariant(), LDBase->getAlignment());
5429 if (LDBase->hasAnyUseOfValue(1)) {
5430 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5432 SDValue(NewLd.getNode(), 1));
5433 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5434 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5435 SDValue(NewLd.getNode(), 1));
5440 if (NumElems == 4 && LastLoadedElt == 1 &&
5441 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5442 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5443 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5445 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops,
5446 array_lengthof(Ops), MVT::i64,
5447 LDBase->getPointerInfo(),
5448 LDBase->getAlignment(),
5449 false/*isVolatile*/, true/*ReadMem*/,
5452 // Make sure the newly-created LOAD is in the same position as LDBase in
5453 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5454 // update uses of LDBase's output chain to use the TokenFactor.
5455 if (LDBase->hasAnyUseOfValue(1)) {
5456 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5457 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5458 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5459 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5460 SDValue(ResNode.getNode(), 1));
5463 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
5468 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
5469 /// to generate a splat value for the following cases:
5470 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
5471 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
5472 /// a scalar load, or a constant.
5473 /// The VBROADCAST node is returned when a pattern is found,
5474 /// or SDValue() otherwise.
5475 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
5476 SelectionDAG &DAG) {
5477 if (!Subtarget->hasFp256())
5480 MVT VT = Op.getSimpleValueType();
5483 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
5484 "Unsupported vector type for broadcast.");
5489 switch (Op.getOpcode()) {
5491 // Unknown pattern found.
5494 case ISD::BUILD_VECTOR: {
5495 // The BUILD_VECTOR node must be a splat.
5496 if (!isSplatVector(Op.getNode()))
5499 Ld = Op.getOperand(0);
5500 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5501 Ld.getOpcode() == ISD::ConstantFP);
5503 // The suspected load node has several users. Make sure that all
5504 // of its users are from the BUILD_VECTOR node.
5505 // Constants may have multiple users.
5506 if (!ConstSplatVal && !Ld->hasNUsesOfValue(VT.getVectorNumElements(), 0))
5511 case ISD::VECTOR_SHUFFLE: {
5512 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5514 // Shuffles must have a splat mask where the first element is
5516 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
5519 SDValue Sc = Op.getOperand(0);
5520 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
5521 Sc.getOpcode() != ISD::BUILD_VECTOR) {
5523 if (!Subtarget->hasInt256())
5526 // Use the register form of the broadcast instruction available on AVX2.
5527 if (VT.getSizeInBits() >= 256)
5528 Sc = Extract128BitVector(Sc, 0, DAG, dl);
5529 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
5532 Ld = Sc.getOperand(0);
5533 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5534 Ld.getOpcode() == ISD::ConstantFP);
5536 // The scalar_to_vector node and the suspected
5537 // load node must have exactly one user.
5538 // Constants may have multiple users.
5540 // AVX-512 has register version of the broadcast
5541 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
5542 Ld.getValueType().getSizeInBits() >= 32;
5543 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
5550 bool IsGE256 = (VT.getSizeInBits() >= 256);
5552 // Handle the broadcasting a single constant scalar from the constant pool
5553 // into a vector. On Sandybridge it is still better to load a constant vector
5554 // from the constant pool and not to broadcast it from a scalar.
5555 if (ConstSplatVal && Subtarget->hasInt256()) {
5556 EVT CVT = Ld.getValueType();
5557 assert(!CVT.isVector() && "Must not broadcast a vector type");
5558 unsigned ScalarSize = CVT.getSizeInBits();
5560 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)) {
5561 const Constant *C = 0;
5562 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
5563 C = CI->getConstantIntValue();
5564 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
5565 C = CF->getConstantFPValue();
5567 assert(C && "Invalid constant type");
5569 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5570 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
5571 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
5572 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
5573 MachinePointerInfo::getConstantPool(),
5574 false, false, false, Alignment);
5576 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5580 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
5581 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5583 // Handle AVX2 in-register broadcasts.
5584 if (!IsLoad && Subtarget->hasInt256() &&
5585 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
5586 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5588 // The scalar source must be a normal load.
5592 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64))
5593 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5595 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5596 // double since there is no vbroadcastsd xmm
5597 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
5598 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
5599 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5602 // Unsupported broadcast.
5606 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
5607 MVT VT = Op.getSimpleValueType();
5609 // Skip if insert_vec_elt is not supported.
5610 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5611 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
5615 unsigned NumElems = Op.getNumOperands();
5619 SmallVector<unsigned, 4> InsertIndices;
5620 SmallVector<int, 8> Mask(NumElems, -1);
5622 for (unsigned i = 0; i != NumElems; ++i) {
5623 unsigned Opc = Op.getOperand(i).getOpcode();
5625 if (Opc == ISD::UNDEF)
5628 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
5629 // Quit if more than 1 elements need inserting.
5630 if (InsertIndices.size() > 1)
5633 InsertIndices.push_back(i);
5637 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
5638 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
5640 // Quit if extracted from vector of different type.
5641 if (ExtractedFromVec.getValueType() != VT)
5644 // Quit if non-constant index.
5645 if (!isa<ConstantSDNode>(ExtIdx))
5648 if (VecIn1.getNode() == 0)
5649 VecIn1 = ExtractedFromVec;
5650 else if (VecIn1 != ExtractedFromVec) {
5651 if (VecIn2.getNode() == 0)
5652 VecIn2 = ExtractedFromVec;
5653 else if (VecIn2 != ExtractedFromVec)
5654 // Quit if more than 2 vectors to shuffle
5658 unsigned Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
5660 if (ExtractedFromVec == VecIn1)
5662 else if (ExtractedFromVec == VecIn2)
5663 Mask[i] = Idx + NumElems;
5666 if (VecIn1.getNode() == 0)
5669 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
5670 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
5671 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
5672 unsigned Idx = InsertIndices[i];
5673 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
5674 DAG.getIntPtrConstant(Idx));
5680 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
5682 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
5684 MVT VT = Op.getSimpleValueType();
5685 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
5686 "Unexpected type in LowerBUILD_VECTORvXi1!");
5689 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5690 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
5691 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
5692 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5693 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
5694 Ops, VT.getVectorNumElements());
5697 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5698 SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
5699 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
5700 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5701 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
5702 Ops, VT.getVectorNumElements());
5705 bool AllContants = true;
5706 uint64_t Immediate = 0;
5707 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5708 SDValue In = Op.getOperand(idx);
5709 if (In.getOpcode() == ISD::UNDEF)
5711 if (!isa<ConstantSDNode>(In)) {
5712 AllContants = false;
5715 if (cast<ConstantSDNode>(In)->getZExtValue())
5716 Immediate |= (1ULL << idx);
5720 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
5721 DAG.getConstant(Immediate, MVT::i16));
5722 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
5723 DAG.getIntPtrConstant(0));
5726 // Splat vector (with undefs)
5727 SDValue In = Op.getOperand(0);
5728 for (unsigned i = 1, e = Op.getNumOperands(); i != e; ++i) {
5729 if (Op.getOperand(i) != In && Op.getOperand(i).getOpcode() != ISD::UNDEF)
5730 llvm_unreachable("Unsupported predicate operation");
5733 SDValue EFLAGS, X86CC;
5734 if (In.getOpcode() == ISD::SETCC) {
5735 SDValue Op0 = In.getOperand(0);
5736 SDValue Op1 = In.getOperand(1);
5737 ISD::CondCode CC = cast<CondCodeSDNode>(In.getOperand(2))->get();
5738 bool isFP = Op1.getValueType().isFloatingPoint();
5739 unsigned X86CCVal = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
5741 assert(X86CCVal != X86::COND_INVALID && "Unsupported predicate operation");
5743 X86CC = DAG.getConstant(X86CCVal, MVT::i8);
5744 EFLAGS = EmitCmp(Op0, Op1, X86CCVal, DAG);
5745 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
5746 } else if (In.getOpcode() == X86ISD::SETCC) {
5747 X86CC = In.getOperand(0);
5748 EFLAGS = In.getOperand(1);
5757 // res = allOnes ### CMOVNE -1, %res
5760 MVT InVT = In.getSimpleValueType();
5761 SDValue Bit1 = DAG.getNode(ISD::AND, dl, InVT, In, DAG.getConstant(1, InVT));
5762 EFLAGS = EmitTest(Bit1, X86::COND_NE, DAG);
5763 X86CC = DAG.getConstant(X86::COND_NE, MVT::i8);
5766 if (VT == MVT::v16i1) {
5767 SDValue Cst1 = DAG.getConstant(-1, MVT::i16);
5768 SDValue Cst0 = DAG.getConstant(0, MVT::i16);
5769 SDValue CmovOp = DAG.getNode(X86ISD::CMOV, dl, MVT::i16,
5770 Cst0, Cst1, X86CC, EFLAGS);
5771 return DAG.getNode(ISD::BITCAST, dl, VT, CmovOp);
5774 if (VT == MVT::v8i1) {
5775 SDValue Cst1 = DAG.getConstant(-1, MVT::i32);
5776 SDValue Cst0 = DAG.getConstant(0, MVT::i32);
5777 SDValue CmovOp = DAG.getNode(X86ISD::CMOV, dl, MVT::i32,
5778 Cst0, Cst1, X86CC, EFLAGS);
5779 CmovOp = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, CmovOp);
5780 return DAG.getNode(ISD::BITCAST, dl, VT, CmovOp);
5782 llvm_unreachable("Unsupported predicate operation");
5786 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
5789 MVT VT = Op.getSimpleValueType();
5790 MVT ExtVT = VT.getVectorElementType();
5791 unsigned NumElems = Op.getNumOperands();
5793 // Generate vectors for predicate vectors.
5794 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
5795 return LowerBUILD_VECTORvXi1(Op, DAG);
5797 // Vectors containing all zeros can be matched by pxor and xorps later
5798 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5799 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
5800 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
5801 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
5804 return getZeroVector(VT, Subtarget, DAG, dl);
5807 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
5808 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
5809 // vpcmpeqd on 256-bit vectors.
5810 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
5811 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
5814 if (!VT.is512BitVector())
5815 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
5818 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
5819 if (Broadcast.getNode())
5822 unsigned EVTBits = ExtVT.getSizeInBits();
5824 unsigned NumZero = 0;
5825 unsigned NumNonZero = 0;
5826 unsigned NonZeros = 0;
5827 bool IsAllConstants = true;
5828 SmallSet<SDValue, 8> Values;
5829 for (unsigned i = 0; i < NumElems; ++i) {
5830 SDValue Elt = Op.getOperand(i);
5831 if (Elt.getOpcode() == ISD::UNDEF)
5834 if (Elt.getOpcode() != ISD::Constant &&
5835 Elt.getOpcode() != ISD::ConstantFP)
5836 IsAllConstants = false;
5837 if (X86::isZeroNode(Elt))
5840 NonZeros |= (1 << i);
5845 // All undef vector. Return an UNDEF. All zero vectors were handled above.
5846 if (NumNonZero == 0)
5847 return DAG.getUNDEF(VT);
5849 // Special case for single non-zero, non-undef, element.
5850 if (NumNonZero == 1) {
5851 unsigned Idx = countTrailingZeros(NonZeros);
5852 SDValue Item = Op.getOperand(Idx);
5854 // If this is an insertion of an i64 value on x86-32, and if the top bits of
5855 // the value are obviously zero, truncate the value to i32 and do the
5856 // insertion that way. Only do this if the value is non-constant or if the
5857 // value is a constant being inserted into element 0. It is cheaper to do
5858 // a constant pool load than it is to do a movd + shuffle.
5859 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
5860 (!IsAllConstants || Idx == 0)) {
5861 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
5863 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
5864 EVT VecVT = MVT::v4i32;
5865 unsigned VecElts = 4;
5867 // Truncate the value (which may itself be a constant) to i32, and
5868 // convert it to a vector with movd (S2V+shuffle to zero extend).
5869 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
5870 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
5871 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5873 // Now we have our 32-bit value zero extended in the low element of
5874 // a vector. If Idx != 0, swizzle it into place.
5876 SmallVector<int, 4> Mask;
5877 Mask.push_back(Idx);
5878 for (unsigned i = 1; i != VecElts; ++i)
5880 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
5883 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5887 // If we have a constant or non-constant insertion into the low element of
5888 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
5889 // the rest of the elements. This will be matched as movd/movq/movss/movsd
5890 // depending on what the source datatype is.
5893 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5895 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
5896 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
5897 if (VT.is256BitVector() || VT.is512BitVector()) {
5898 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
5899 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
5900 Item, DAG.getIntPtrConstant(0));
5902 assert(VT.is128BitVector() && "Expected an SSE value type!");
5903 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5904 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
5905 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5908 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
5909 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
5910 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5911 if (VT.is256BitVector()) {
5912 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
5913 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
5915 assert(VT.is128BitVector() && "Expected an SSE value type!");
5916 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5918 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5922 // Is it a vector logical left shift?
5923 if (NumElems == 2 && Idx == 1 &&
5924 X86::isZeroNode(Op.getOperand(0)) &&
5925 !X86::isZeroNode(Op.getOperand(1))) {
5926 unsigned NumBits = VT.getSizeInBits();
5927 return getVShift(true, VT,
5928 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5929 VT, Op.getOperand(1)),
5930 NumBits/2, DAG, *this, dl);
5933 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
5936 // Otherwise, if this is a vector with i32 or f32 elements, and the element
5937 // is a non-constant being inserted into an element other than the low one,
5938 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
5939 // movd/movss) to move this into the low element, then shuffle it into
5941 if (EVTBits == 32) {
5942 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5944 // Turn it into a shuffle of zero and zero-extended scalar to vector.
5945 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
5946 SmallVector<int, 8> MaskVec;
5947 for (unsigned i = 0; i != NumElems; ++i)
5948 MaskVec.push_back(i == Idx ? 0 : 1);
5949 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
5953 // Splat is obviously ok. Let legalizer expand it to a shuffle.
5954 if (Values.size() == 1) {
5955 if (EVTBits == 32) {
5956 // Instead of a shuffle like this:
5957 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
5958 // Check if it's possible to issue this instead.
5959 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
5960 unsigned Idx = countTrailingZeros(NonZeros);
5961 SDValue Item = Op.getOperand(Idx);
5962 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
5963 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
5968 // A vector full of immediates; various special cases are already
5969 // handled, so this is best done with a single constant-pool load.
5973 // For AVX-length vectors, build the individual 128-bit pieces and use
5974 // shuffles to put them in place.
5975 if (VT.is256BitVector()) {
5976 SmallVector<SDValue, 32> V;
5977 for (unsigned i = 0; i != NumElems; ++i)
5978 V.push_back(Op.getOperand(i));
5980 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
5982 // Build both the lower and upper subvector.
5983 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2);
5984 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2],
5987 // Recreate the wider vector with the lower and upper part.
5988 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
5991 // Let legalizer expand 2-wide build_vectors.
5992 if (EVTBits == 64) {
5993 if (NumNonZero == 1) {
5994 // One half is zero or undef.
5995 unsigned Idx = countTrailingZeros(NonZeros);
5996 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
5997 Op.getOperand(Idx));
5998 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
6003 // If element VT is < 32 bits, convert it to inserts into a zero vector.
6004 if (EVTBits == 8 && NumElems == 16) {
6005 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
6007 if (V.getNode()) return V;
6010 if (EVTBits == 16 && NumElems == 8) {
6011 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
6013 if (V.getNode()) return V;
6016 // If element VT is == 32 bits, turn it into a number of shuffles.
6017 SmallVector<SDValue, 8> V(NumElems);
6018 if (NumElems == 4 && NumZero > 0) {
6019 for (unsigned i = 0; i < 4; ++i) {
6020 bool isZero = !(NonZeros & (1 << i));
6022 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
6024 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6027 for (unsigned i = 0; i < 2; ++i) {
6028 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
6031 V[i] = V[i*2]; // Must be a zero vector.
6034 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
6037 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
6040 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
6045 bool Reverse1 = (NonZeros & 0x3) == 2;
6046 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
6050 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
6051 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
6053 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
6056 if (Values.size() > 1 && VT.is128BitVector()) {
6057 // Check for a build vector of consecutive loads.
6058 for (unsigned i = 0; i < NumElems; ++i)
6059 V[i] = Op.getOperand(i);
6061 // Check for elements which are consecutive loads.
6062 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG);
6066 // Check for a build vector from mostly shuffle plus few inserting.
6067 SDValue Sh = buildFromShuffleMostly(Op, DAG);
6071 // For SSE 4.1, use insertps to put the high elements into the low element.
6072 if (getSubtarget()->hasSSE41()) {
6074 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
6075 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
6077 Result = DAG.getUNDEF(VT);
6079 for (unsigned i = 1; i < NumElems; ++i) {
6080 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
6081 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
6082 Op.getOperand(i), DAG.getIntPtrConstant(i));
6087 // Otherwise, expand into a number of unpckl*, start by extending each of
6088 // our (non-undef) elements to the full vector width with the element in the
6089 // bottom slot of the vector (which generates no code for SSE).
6090 for (unsigned i = 0; i < NumElems; ++i) {
6091 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
6092 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6094 V[i] = DAG.getUNDEF(VT);
6097 // Next, we iteratively mix elements, e.g. for v4f32:
6098 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
6099 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
6100 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
6101 unsigned EltStride = NumElems >> 1;
6102 while (EltStride != 0) {
6103 for (unsigned i = 0; i < EltStride; ++i) {
6104 // If V[i+EltStride] is undef and this is the first round of mixing,
6105 // then it is safe to just drop this shuffle: V[i] is already in the
6106 // right place, the one element (since it's the first round) being
6107 // inserted as undef can be dropped. This isn't safe for successive
6108 // rounds because they will permute elements within both vectors.
6109 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
6110 EltStride == NumElems/2)
6113 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
6122 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
6123 // to create 256-bit vectors from two other 128-bit ones.
6124 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6126 MVT ResVT = Op.getSimpleValueType();
6128 assert((ResVT.is256BitVector() ||
6129 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
6131 SDValue V1 = Op.getOperand(0);
6132 SDValue V2 = Op.getOperand(1);
6133 unsigned NumElems = ResVT.getVectorNumElements();
6134 if(ResVT.is256BitVector())
6135 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6137 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6140 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6141 assert(Op.getNumOperands() == 2);
6143 // AVX/AVX-512 can use the vinsertf128 instruction to create 256-bit vectors
6144 // from two other 128-bit ones.
6145 return LowerAVXCONCAT_VECTORS(Op, DAG);
6148 // Try to lower a shuffle node into a simple blend instruction.
6150 LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
6151 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
6152 SDValue V1 = SVOp->getOperand(0);
6153 SDValue V2 = SVOp->getOperand(1);
6155 MVT VT = SVOp->getSimpleValueType(0);
6156 MVT EltVT = VT.getVectorElementType();
6157 unsigned NumElems = VT.getVectorNumElements();
6159 // There is no blend with immediate in AVX-512.
6160 if (VT.is512BitVector())
6163 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
6165 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
6168 // Check the mask for BLEND and build the value.
6169 unsigned MaskValue = 0;
6170 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
6171 unsigned NumLanes = (NumElems-1)/8 + 1;
6172 unsigned NumElemsInLane = NumElems / NumLanes;
6174 // Blend for v16i16 should be symetric for the both lanes.
6175 for (unsigned i = 0; i < NumElemsInLane; ++i) {
6177 int SndLaneEltIdx = (NumLanes == 2) ?
6178 SVOp->getMaskElt(i + NumElemsInLane) : -1;
6179 int EltIdx = SVOp->getMaskElt(i);
6181 if ((EltIdx < 0 || EltIdx == (int)i) &&
6182 (SndLaneEltIdx < 0 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
6185 if (((unsigned)EltIdx == (i + NumElems)) &&
6186 (SndLaneEltIdx < 0 ||
6187 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
6188 MaskValue |= (1<<i);
6193 // Convert i32 vectors to floating point if it is not AVX2.
6194 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
6196 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
6197 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
6199 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
6200 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
6203 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
6204 DAG.getConstant(MaskValue, MVT::i32));
6205 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
6208 // v8i16 shuffles - Prefer shuffles in the following order:
6209 // 1. [all] pshuflw, pshufhw, optional move
6210 // 2. [ssse3] 1 x pshufb
6211 // 3. [ssse3] 2 x pshufb + 1 x por
6212 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
6214 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
6215 SelectionDAG &DAG) {
6216 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6217 SDValue V1 = SVOp->getOperand(0);
6218 SDValue V2 = SVOp->getOperand(1);
6220 SmallVector<int, 8> MaskVals;
6222 // Determine if more than 1 of the words in each of the low and high quadwords
6223 // of the result come from the same quadword of one of the two inputs. Undef
6224 // mask values count as coming from any quadword, for better codegen.
6225 unsigned LoQuad[] = { 0, 0, 0, 0 };
6226 unsigned HiQuad[] = { 0, 0, 0, 0 };
6227 std::bitset<4> InputQuads;
6228 for (unsigned i = 0; i < 8; ++i) {
6229 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
6230 int EltIdx = SVOp->getMaskElt(i);
6231 MaskVals.push_back(EltIdx);
6240 InputQuads.set(EltIdx / 4);
6243 int BestLoQuad = -1;
6244 unsigned MaxQuad = 1;
6245 for (unsigned i = 0; i < 4; ++i) {
6246 if (LoQuad[i] > MaxQuad) {
6248 MaxQuad = LoQuad[i];
6252 int BestHiQuad = -1;
6254 for (unsigned i = 0; i < 4; ++i) {
6255 if (HiQuad[i] > MaxQuad) {
6257 MaxQuad = HiQuad[i];
6261 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
6262 // of the two input vectors, shuffle them into one input vector so only a
6263 // single pshufb instruction is necessary. If There are more than 2 input
6264 // quads, disable the next transformation since it does not help SSSE3.
6265 bool V1Used = InputQuads[0] || InputQuads[1];
6266 bool V2Used = InputQuads[2] || InputQuads[3];
6267 if (Subtarget->hasSSSE3()) {
6268 if (InputQuads.count() == 2 && V1Used && V2Used) {
6269 BestLoQuad = InputQuads[0] ? 0 : 1;
6270 BestHiQuad = InputQuads[2] ? 2 : 3;
6272 if (InputQuads.count() > 2) {
6278 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
6279 // the shuffle mask. If a quad is scored as -1, that means that it contains
6280 // words from all 4 input quadwords.
6282 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
6284 BestLoQuad < 0 ? 0 : BestLoQuad,
6285 BestHiQuad < 0 ? 1 : BestHiQuad
6287 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
6288 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
6289 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
6290 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
6292 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
6293 // source words for the shuffle, to aid later transformations.
6294 bool AllWordsInNewV = true;
6295 bool InOrder[2] = { true, true };
6296 for (unsigned i = 0; i != 8; ++i) {
6297 int idx = MaskVals[i];
6299 InOrder[i/4] = false;
6300 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
6302 AllWordsInNewV = false;
6306 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
6307 if (AllWordsInNewV) {
6308 for (int i = 0; i != 8; ++i) {
6309 int idx = MaskVals[i];
6312 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
6313 if ((idx != i) && idx < 4)
6315 if ((idx != i) && idx > 3)
6324 // If we've eliminated the use of V2, and the new mask is a pshuflw or
6325 // pshufhw, that's as cheap as it gets. Return the new shuffle.
6326 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
6327 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
6328 unsigned TargetMask = 0;
6329 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
6330 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
6331 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
6332 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
6333 getShufflePSHUFLWImmediate(SVOp);
6334 V1 = NewV.getOperand(0);
6335 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
6339 // Promote splats to a larger type which usually leads to more efficient code.
6340 // FIXME: Is this true if pshufb is available?
6341 if (SVOp->isSplat())
6342 return PromoteSplat(SVOp, DAG);
6344 // If we have SSSE3, and all words of the result are from 1 input vector,
6345 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
6346 // is present, fall back to case 4.
6347 if (Subtarget->hasSSSE3()) {
6348 SmallVector<SDValue,16> pshufbMask;
6350 // If we have elements from both input vectors, set the high bit of the
6351 // shuffle mask element to zero out elements that come from V2 in the V1
6352 // mask, and elements that come from V1 in the V2 mask, so that the two
6353 // results can be OR'd together.
6354 bool TwoInputs = V1Used && V2Used;
6355 for (unsigned i = 0; i != 8; ++i) {
6356 int EltIdx = MaskVals[i] * 2;
6357 int Idx0 = (TwoInputs && (EltIdx >= 16)) ? 0x80 : EltIdx;
6358 int Idx1 = (TwoInputs && (EltIdx >= 16)) ? 0x80 : EltIdx+1;
6359 pshufbMask.push_back(DAG.getConstant(Idx0, MVT::i8));
6360 pshufbMask.push_back(DAG.getConstant(Idx1, MVT::i8));
6362 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1);
6363 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
6364 DAG.getNode(ISD::BUILD_VECTOR, dl,
6365 MVT::v16i8, &pshufbMask[0], 16));
6367 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
6369 // Calculate the shuffle mask for the second input, shuffle it, and
6370 // OR it with the first shuffled input.
6372 for (unsigned i = 0; i != 8; ++i) {
6373 int EltIdx = MaskVals[i] * 2;
6374 int Idx0 = (EltIdx < 16) ? 0x80 : EltIdx - 16;
6375 int Idx1 = (EltIdx < 16) ? 0x80 : EltIdx - 15;
6376 pshufbMask.push_back(DAG.getConstant(Idx0, MVT::i8));
6377 pshufbMask.push_back(DAG.getConstant(Idx1, MVT::i8));
6379 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2);
6380 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
6381 DAG.getNode(ISD::BUILD_VECTOR, dl,
6382 MVT::v16i8, &pshufbMask[0], 16));
6383 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
6384 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
6387 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
6388 // and update MaskVals with new element order.
6389 std::bitset<8> InOrder;
6390 if (BestLoQuad >= 0) {
6391 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
6392 for (int i = 0; i != 4; ++i) {
6393 int idx = MaskVals[i];
6396 } else if ((idx / 4) == BestLoQuad) {
6401 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
6404 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
6405 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
6406 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
6408 getShufflePSHUFLWImmediate(SVOp), DAG);
6412 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
6413 // and update MaskVals with the new element order.
6414 if (BestHiQuad >= 0) {
6415 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
6416 for (unsigned i = 4; i != 8; ++i) {
6417 int idx = MaskVals[i];
6420 } else if ((idx / 4) == BestHiQuad) {
6421 MaskV[i] = (idx & 3) + 4;
6425 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
6428 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
6429 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
6430 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
6432 getShufflePSHUFHWImmediate(SVOp), DAG);
6436 // In case BestHi & BestLo were both -1, which means each quadword has a word
6437 // from each of the four input quadwords, calculate the InOrder bitvector now
6438 // before falling through to the insert/extract cleanup.
6439 if (BestLoQuad == -1 && BestHiQuad == -1) {
6441 for (int i = 0; i != 8; ++i)
6442 if (MaskVals[i] < 0 || MaskVals[i] == i)
6446 // The other elements are put in the right place using pextrw and pinsrw.
6447 for (unsigned i = 0; i != 8; ++i) {
6450 int EltIdx = MaskVals[i];
6453 SDValue ExtOp = (EltIdx < 8) ?
6454 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
6455 DAG.getIntPtrConstant(EltIdx)) :
6456 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
6457 DAG.getIntPtrConstant(EltIdx - 8));
6458 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
6459 DAG.getIntPtrConstant(i));
6464 // v16i8 shuffles - Prefer shuffles in the following order:
6465 // 1. [ssse3] 1 x pshufb
6466 // 2. [ssse3] 2 x pshufb + 1 x por
6467 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
6468 static SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
6469 const X86Subtarget* Subtarget,
6470 SelectionDAG &DAG) {
6471 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6472 SDValue V1 = SVOp->getOperand(0);
6473 SDValue V2 = SVOp->getOperand(1);
6475 ArrayRef<int> MaskVals = SVOp->getMask();
6477 // Promote splats to a larger type which usually leads to more efficient code.
6478 // FIXME: Is this true if pshufb is available?
6479 if (SVOp->isSplat())
6480 return PromoteSplat(SVOp, DAG);
6482 // If we have SSSE3, case 1 is generated when all result bytes come from
6483 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
6484 // present, fall back to case 3.
6486 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
6487 if (Subtarget->hasSSSE3()) {
6488 SmallVector<SDValue,16> pshufbMask;
6490 // If all result elements are from one input vector, then only translate
6491 // undef mask values to 0x80 (zero out result) in the pshufb mask.
6493 // Otherwise, we have elements from both input vectors, and must zero out
6494 // elements that come from V2 in the first mask, and V1 in the second mask
6495 // so that we can OR them together.
6496 for (unsigned i = 0; i != 16; ++i) {
6497 int EltIdx = MaskVals[i];
6498 if (EltIdx < 0 || EltIdx >= 16)
6500 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
6502 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
6503 DAG.getNode(ISD::BUILD_VECTOR, dl,
6504 MVT::v16i8, &pshufbMask[0], 16));
6506 // As PSHUFB will zero elements with negative indices, it's safe to ignore
6507 // the 2nd operand if it's undefined or zero.
6508 if (V2.getOpcode() == ISD::UNDEF ||
6509 ISD::isBuildVectorAllZeros(V2.getNode()))
6512 // Calculate the shuffle mask for the second input, shuffle it, and
6513 // OR it with the first shuffled input.
6515 for (unsigned i = 0; i != 16; ++i) {
6516 int EltIdx = MaskVals[i];
6517 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
6518 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
6520 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
6521 DAG.getNode(ISD::BUILD_VECTOR, dl,
6522 MVT::v16i8, &pshufbMask[0], 16));
6523 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
6526 // No SSSE3 - Calculate in place words and then fix all out of place words
6527 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
6528 // the 16 different words that comprise the two doublequadword input vectors.
6529 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
6530 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
6532 for (int i = 0; i != 8; ++i) {
6533 int Elt0 = MaskVals[i*2];
6534 int Elt1 = MaskVals[i*2+1];
6536 // This word of the result is all undef, skip it.
6537 if (Elt0 < 0 && Elt1 < 0)
6540 // This word of the result is already in the correct place, skip it.
6541 if ((Elt0 == i*2) && (Elt1 == i*2+1))
6544 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
6545 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
6548 // If Elt0 and Elt1 are defined, are consecutive, and can be load
6549 // using a single extract together, load it and store it.
6550 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
6551 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
6552 DAG.getIntPtrConstant(Elt1 / 2));
6553 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
6554 DAG.getIntPtrConstant(i));
6558 // If Elt1 is defined, extract it from the appropriate source. If the
6559 // source byte is not also odd, shift the extracted word left 8 bits
6560 // otherwise clear the bottom 8 bits if we need to do an or.
6562 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
6563 DAG.getIntPtrConstant(Elt1 / 2));
6564 if ((Elt1 & 1) == 0)
6565 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
6567 TLI.getShiftAmountTy(InsElt.getValueType())));
6569 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
6570 DAG.getConstant(0xFF00, MVT::i16));
6572 // If Elt0 is defined, extract it from the appropriate source. If the
6573 // source byte is not also even, shift the extracted word right 8 bits. If
6574 // Elt1 was also defined, OR the extracted values together before
6575 // inserting them in the result.
6577 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
6578 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
6579 if ((Elt0 & 1) != 0)
6580 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
6582 TLI.getShiftAmountTy(InsElt0.getValueType())));
6584 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
6585 DAG.getConstant(0x00FF, MVT::i16));
6586 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
6589 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
6590 DAG.getIntPtrConstant(i));
6592 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
6595 // v32i8 shuffles - Translate to VPSHUFB if possible.
6597 SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
6598 const X86Subtarget *Subtarget,
6599 SelectionDAG &DAG) {
6600 MVT VT = SVOp->getSimpleValueType(0);
6601 SDValue V1 = SVOp->getOperand(0);
6602 SDValue V2 = SVOp->getOperand(1);
6604 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
6606 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
6607 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
6608 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
6610 // VPSHUFB may be generated if
6611 // (1) one of input vector is undefined or zeroinitializer.
6612 // The mask value 0x80 puts 0 in the corresponding slot of the vector.
6613 // And (2) the mask indexes don't cross the 128-bit lane.
6614 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
6615 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
6618 if (V1IsAllZero && !V2IsAllZero) {
6619 CommuteVectorShuffleMask(MaskVals, 32);
6622 SmallVector<SDValue, 32> pshufbMask;
6623 for (unsigned i = 0; i != 32; i++) {
6624 int EltIdx = MaskVals[i];
6625 if (EltIdx < 0 || EltIdx >= 32)
6628 if ((EltIdx >= 16 && i < 16) || (EltIdx < 16 && i >= 16))
6629 // Cross lane is not allowed.
6633 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
6635 return DAG.getNode(X86ISD::PSHUFB, dl, MVT::v32i8, V1,
6636 DAG.getNode(ISD::BUILD_VECTOR, dl,
6637 MVT::v32i8, &pshufbMask[0], 32));
6640 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
6641 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
6642 /// done when every pair / quad of shuffle mask elements point to elements in
6643 /// the right sequence. e.g.
6644 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
6646 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
6647 SelectionDAG &DAG) {
6648 MVT VT = SVOp->getSimpleValueType(0);
6650 unsigned NumElems = VT.getVectorNumElements();
6653 switch (VT.SimpleTy) {
6654 default: llvm_unreachable("Unexpected!");
6655 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
6656 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
6657 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
6658 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
6659 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
6660 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
6663 SmallVector<int, 8> MaskVec;
6664 for (unsigned i = 0; i != NumElems; i += Scale) {
6666 for (unsigned j = 0; j != Scale; ++j) {
6667 int EltIdx = SVOp->getMaskElt(i+j);
6671 StartIdx = (EltIdx / Scale);
6672 if (EltIdx != (int)(StartIdx*Scale + j))
6675 MaskVec.push_back(StartIdx);
6678 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
6679 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
6680 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
6683 /// getVZextMovL - Return a zero-extending vector move low node.
6685 static SDValue getVZextMovL(MVT VT, MVT OpVT,
6686 SDValue SrcOp, SelectionDAG &DAG,
6687 const X86Subtarget *Subtarget, SDLoc dl) {
6688 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
6689 LoadSDNode *LD = NULL;
6690 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
6691 LD = dyn_cast<LoadSDNode>(SrcOp);
6693 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
6695 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
6696 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
6697 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
6698 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
6699 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
6701 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
6702 return DAG.getNode(ISD::BITCAST, dl, VT,
6703 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
6704 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6712 return DAG.getNode(ISD::BITCAST, dl, VT,
6713 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
6714 DAG.getNode(ISD::BITCAST, dl,
6718 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
6719 /// which could not be matched by any known target speficic shuffle
6721 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
6723 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
6724 if (NewOp.getNode())
6727 MVT VT = SVOp->getSimpleValueType(0);
6729 unsigned NumElems = VT.getVectorNumElements();
6730 unsigned NumLaneElems = NumElems / 2;
6733 MVT EltVT = VT.getVectorElementType();
6734 MVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
6737 SmallVector<int, 16> Mask;
6738 for (unsigned l = 0; l < 2; ++l) {
6739 // Build a shuffle mask for the output, discovering on the fly which
6740 // input vectors to use as shuffle operands (recorded in InputUsed).
6741 // If building a suitable shuffle vector proves too hard, then bail
6742 // out with UseBuildVector set.
6743 bool UseBuildVector = false;
6744 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
6745 unsigned LaneStart = l * NumLaneElems;
6746 for (unsigned i = 0; i != NumLaneElems; ++i) {
6747 // The mask element. This indexes into the input.
6748 int Idx = SVOp->getMaskElt(i+LaneStart);
6750 // the mask element does not index into any input vector.
6755 // The input vector this mask element indexes into.
6756 int Input = Idx / NumLaneElems;
6758 // Turn the index into an offset from the start of the input vector.
6759 Idx -= Input * NumLaneElems;
6761 // Find or create a shuffle vector operand to hold this input.
6763 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
6764 if (InputUsed[OpNo] == Input)
6765 // This input vector is already an operand.
6767 if (InputUsed[OpNo] < 0) {
6768 // Create a new operand for this input vector.
6769 InputUsed[OpNo] = Input;
6774 if (OpNo >= array_lengthof(InputUsed)) {
6775 // More than two input vectors used! Give up on trying to create a
6776 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
6777 UseBuildVector = true;
6781 // Add the mask index for the new shuffle vector.
6782 Mask.push_back(Idx + OpNo * NumLaneElems);
6785 if (UseBuildVector) {
6786 SmallVector<SDValue, 16> SVOps;
6787 for (unsigned i = 0; i != NumLaneElems; ++i) {
6788 // The mask element. This indexes into the input.
6789 int Idx = SVOp->getMaskElt(i+LaneStart);
6791 SVOps.push_back(DAG.getUNDEF(EltVT));
6795 // The input vector this mask element indexes into.
6796 int Input = Idx / NumElems;
6798 // Turn the index into an offset from the start of the input vector.
6799 Idx -= Input * NumElems;
6801 // Extract the vector element by hand.
6802 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
6803 SVOp->getOperand(Input),
6804 DAG.getIntPtrConstant(Idx)));
6807 // Construct the output using a BUILD_VECTOR.
6808 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, &SVOps[0],
6810 } else if (InputUsed[0] < 0) {
6811 // No input vectors were used! The result is undefined.
6812 Output[l] = DAG.getUNDEF(NVT);
6814 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
6815 (InputUsed[0] % 2) * NumLaneElems,
6817 // If only one input was used, use an undefined vector for the other.
6818 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
6819 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
6820 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
6821 // At least one input vector was used. Create a new shuffle vector.
6822 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
6828 // Concatenate the result back
6829 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
6832 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
6833 /// 4 elements, and match them with several different shuffle types.
6835 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
6836 SDValue V1 = SVOp->getOperand(0);
6837 SDValue V2 = SVOp->getOperand(1);
6839 MVT VT = SVOp->getSimpleValueType(0);
6841 assert(VT.is128BitVector() && "Unsupported vector size");
6843 std::pair<int, int> Locs[4];
6844 int Mask1[] = { -1, -1, -1, -1 };
6845 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
6849 for (unsigned i = 0; i != 4; ++i) {
6850 int Idx = PermMask[i];
6852 Locs[i] = std::make_pair(-1, -1);
6854 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
6856 Locs[i] = std::make_pair(0, NumLo);
6860 Locs[i] = std::make_pair(1, NumHi);
6862 Mask1[2+NumHi] = Idx;
6868 if (NumLo <= 2 && NumHi <= 2) {
6869 // If no more than two elements come from either vector. This can be
6870 // implemented with two shuffles. First shuffle gather the elements.
6871 // The second shuffle, which takes the first shuffle as both of its
6872 // vector operands, put the elements into the right order.
6873 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6875 int Mask2[] = { -1, -1, -1, -1 };
6877 for (unsigned i = 0; i != 4; ++i)
6878 if (Locs[i].first != -1) {
6879 unsigned Idx = (i < 2) ? 0 : 4;
6880 Idx += Locs[i].first * 2 + Locs[i].second;
6884 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
6887 if (NumLo == 3 || NumHi == 3) {
6888 // Otherwise, we must have three elements from one vector, call it X, and
6889 // one element from the other, call it Y. First, use a shufps to build an
6890 // intermediate vector with the one element from Y and the element from X
6891 // that will be in the same half in the final destination (the indexes don't
6892 // matter). Then, use a shufps to build the final vector, taking the half
6893 // containing the element from Y from the intermediate, and the other half
6896 // Normalize it so the 3 elements come from V1.
6897 CommuteVectorShuffleMask(PermMask, 4);
6901 // Find the element from V2.
6903 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
6904 int Val = PermMask[HiIndex];
6911 Mask1[0] = PermMask[HiIndex];
6913 Mask1[2] = PermMask[HiIndex^1];
6915 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6918 Mask1[0] = PermMask[0];
6919 Mask1[1] = PermMask[1];
6920 Mask1[2] = HiIndex & 1 ? 6 : 4;
6921 Mask1[3] = HiIndex & 1 ? 4 : 6;
6922 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6925 Mask1[0] = HiIndex & 1 ? 2 : 0;
6926 Mask1[1] = HiIndex & 1 ? 0 : 2;
6927 Mask1[2] = PermMask[2];
6928 Mask1[3] = PermMask[3];
6933 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
6936 // Break it into (shuffle shuffle_hi, shuffle_lo).
6937 int LoMask[] = { -1, -1, -1, -1 };
6938 int HiMask[] = { -1, -1, -1, -1 };
6940 int *MaskPtr = LoMask;
6941 unsigned MaskIdx = 0;
6944 for (unsigned i = 0; i != 4; ++i) {
6951 int Idx = PermMask[i];
6953 Locs[i] = std::make_pair(-1, -1);
6954 } else if (Idx < 4) {
6955 Locs[i] = std::make_pair(MaskIdx, LoIdx);
6956 MaskPtr[LoIdx] = Idx;
6959 Locs[i] = std::make_pair(MaskIdx, HiIdx);
6960 MaskPtr[HiIdx] = Idx;
6965 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
6966 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
6967 int MaskOps[] = { -1, -1, -1, -1 };
6968 for (unsigned i = 0; i != 4; ++i)
6969 if (Locs[i].first != -1)
6970 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
6971 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
6974 static bool MayFoldVectorLoad(SDValue V) {
6975 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6976 V = V.getOperand(0);
6978 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6979 V = V.getOperand(0);
6980 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
6981 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
6982 // BUILD_VECTOR (load), undef
6983 V = V.getOperand(0);
6985 return MayFoldLoad(V);
6989 SDValue getMOVDDup(SDValue &Op, SDLoc &dl, SDValue V1, SelectionDAG &DAG) {
6990 MVT VT = Op.getSimpleValueType();
6992 // Canonizalize to v2f64.
6993 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
6994 return DAG.getNode(ISD::BITCAST, dl, VT,
6995 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
7000 SDValue getMOVLowToHigh(SDValue &Op, SDLoc &dl, SelectionDAG &DAG,
7002 SDValue V1 = Op.getOperand(0);
7003 SDValue V2 = Op.getOperand(1);
7004 MVT VT = Op.getSimpleValueType();
7006 assert(VT != MVT::v2i64 && "unsupported shuffle type");
7008 if (HasSSE2 && VT == MVT::v2f64)
7009 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
7011 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
7012 return DAG.getNode(ISD::BITCAST, dl, VT,
7013 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
7014 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
7015 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
7019 SDValue getMOVHighToLow(SDValue &Op, SDLoc &dl, SelectionDAG &DAG) {
7020 SDValue V1 = Op.getOperand(0);
7021 SDValue V2 = Op.getOperand(1);
7022 MVT VT = Op.getSimpleValueType();
7024 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
7025 "unsupported shuffle type");
7027 if (V2.getOpcode() == ISD::UNDEF)
7031 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
7035 SDValue getMOVLP(SDValue &Op, SDLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
7036 SDValue V1 = Op.getOperand(0);
7037 SDValue V2 = Op.getOperand(1);
7038 MVT VT = Op.getSimpleValueType();
7039 unsigned NumElems = VT.getVectorNumElements();
7041 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
7042 // operand of these instructions is only memory, so check if there's a
7043 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
7045 bool CanFoldLoad = false;
7047 // Trivial case, when V2 comes from a load.
7048 if (MayFoldVectorLoad(V2))
7051 // When V1 is a load, it can be folded later into a store in isel, example:
7052 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
7054 // (MOVLPSmr addr:$src1, VR128:$src2)
7055 // So, recognize this potential and also use MOVLPS or MOVLPD
7056 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
7059 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7061 if (HasSSE2 && NumElems == 2)
7062 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
7065 // If we don't care about the second element, proceed to use movss.
7066 if (SVOp->getMaskElt(1) != -1)
7067 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
7070 // movl and movlp will both match v2i64, but v2i64 is never matched by
7071 // movl earlier because we make it strict to avoid messing with the movlp load
7072 // folding logic (see the code above getMOVLP call). Match it here then,
7073 // this is horrible, but will stay like this until we move all shuffle
7074 // matching to x86 specific nodes. Note that for the 1st condition all
7075 // types are matched with movsd.
7077 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
7078 // as to remove this logic from here, as much as possible
7079 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
7080 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
7081 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
7084 assert(VT != MVT::v4i32 && "unsupported shuffle type");
7086 // Invert the operand order and use SHUFPS to match it.
7087 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
7088 getShuffleSHUFImmediate(SVOp), DAG);
7091 // Reduce a vector shuffle to zext.
7092 static SDValue LowerVectorIntExtend(SDValue Op, const X86Subtarget *Subtarget,
7093 SelectionDAG &DAG) {
7094 // PMOVZX is only available from SSE41.
7095 if (!Subtarget->hasSSE41())
7098 MVT VT = Op.getSimpleValueType();
7100 // Only AVX2 support 256-bit vector integer extending.
7101 if (!Subtarget->hasInt256() && VT.is256BitVector())
7104 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7106 SDValue V1 = Op.getOperand(0);
7107 SDValue V2 = Op.getOperand(1);
7108 unsigned NumElems = VT.getVectorNumElements();
7110 // Extending is an unary operation and the element type of the source vector
7111 // won't be equal to or larger than i64.
7112 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
7113 VT.getVectorElementType() == MVT::i64)
7116 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
7117 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
7118 while ((1U << Shift) < NumElems) {
7119 if (SVOp->getMaskElt(1U << Shift) == 1)
7122 // The maximal ratio is 8, i.e. from i8 to i64.
7127 // Check the shuffle mask.
7128 unsigned Mask = (1U << Shift) - 1;
7129 for (unsigned i = 0; i != NumElems; ++i) {
7130 int EltIdx = SVOp->getMaskElt(i);
7131 if ((i & Mask) != 0 && EltIdx != -1)
7133 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift))
7137 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
7138 MVT NeVT = MVT::getIntegerVT(NBits);
7139 MVT NVT = MVT::getVectorVT(NeVT, NumElems >> Shift);
7141 if (!DAG.getTargetLoweringInfo().isTypeLegal(NVT))
7144 // Simplify the operand as it's prepared to be fed into shuffle.
7145 unsigned SignificantBits = NVT.getSizeInBits() >> Shift;
7146 if (V1.getOpcode() == ISD::BITCAST &&
7147 V1.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
7148 V1.getOperand(0).getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
7149 V1.getOperand(0).getOperand(0)
7150 .getSimpleValueType().getSizeInBits() == SignificantBits) {
7151 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
7152 SDValue V = V1.getOperand(0).getOperand(0).getOperand(0);
7153 ConstantSDNode *CIdx =
7154 dyn_cast<ConstantSDNode>(V1.getOperand(0).getOperand(0).getOperand(1));
7155 // If it's foldable, i.e. normal load with single use, we will let code
7156 // selection to fold it. Otherwise, we will short the conversion sequence.
7157 if (CIdx && CIdx->getZExtValue() == 0 &&
7158 (!ISD::isNormalLoad(V.getNode()) || !V.hasOneUse())) {
7159 MVT FullVT = V.getSimpleValueType();
7160 MVT V1VT = V1.getSimpleValueType();
7161 if (FullVT.getSizeInBits() > V1VT.getSizeInBits()) {
7162 // The "ext_vec_elt" node is wider than the result node.
7163 // In this case we should extract subvector from V.
7164 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast (extract_subvector x)).
7165 unsigned Ratio = FullVT.getSizeInBits() / V1VT.getSizeInBits();
7166 MVT SubVecVT = MVT::getVectorVT(FullVT.getVectorElementType(),
7167 FullVT.getVectorNumElements()/Ratio);
7168 V = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVecVT, V,
7169 DAG.getIntPtrConstant(0));
7171 V1 = DAG.getNode(ISD::BITCAST, DL, V1VT, V);
7175 return DAG.getNode(ISD::BITCAST, DL, VT,
7176 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
7180 NormalizeVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
7181 SelectionDAG &DAG) {
7182 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7183 MVT VT = Op.getSimpleValueType();
7185 SDValue V1 = Op.getOperand(0);
7186 SDValue V2 = Op.getOperand(1);
7188 if (isZeroShuffle(SVOp))
7189 return getZeroVector(VT, Subtarget, DAG, dl);
7191 // Handle splat operations
7192 if (SVOp->isSplat()) {
7193 // Use vbroadcast whenever the splat comes from a foldable load
7194 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
7195 if (Broadcast.getNode())
7199 // Check integer expanding shuffles.
7200 SDValue NewOp = LowerVectorIntExtend(Op, Subtarget, DAG);
7201 if (NewOp.getNode())
7204 // If the shuffle can be profitably rewritten as a narrower shuffle, then
7206 if (VT == MVT::v8i16 || VT == MVT::v16i8 ||
7207 VT == MVT::v16i16 || VT == MVT::v32i8) {
7208 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
7209 if (NewOp.getNode())
7210 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
7211 } else if ((VT == MVT::v4i32 ||
7212 (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
7213 // FIXME: Figure out a cleaner way to do this.
7214 // Try to make use of movq to zero out the top part.
7215 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
7216 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
7217 if (NewOp.getNode()) {
7218 MVT NewVT = NewOp.getSimpleValueType();
7219 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
7220 NewVT, true, false))
7221 return getVZextMovL(VT, NewVT, NewOp.getOperand(0),
7222 DAG, Subtarget, dl);
7224 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
7225 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
7226 if (NewOp.getNode()) {
7227 MVT NewVT = NewOp.getSimpleValueType();
7228 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
7229 return getVZextMovL(VT, NewVT, NewOp.getOperand(1),
7230 DAG, Subtarget, dl);
7238 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
7239 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7240 SDValue V1 = Op.getOperand(0);
7241 SDValue V2 = Op.getOperand(1);
7242 MVT VT = Op.getSimpleValueType();
7244 unsigned NumElems = VT.getVectorNumElements();
7245 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
7246 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
7247 bool V1IsSplat = false;
7248 bool V2IsSplat = false;
7249 bool HasSSE2 = Subtarget->hasSSE2();
7250 bool HasFp256 = Subtarget->hasFp256();
7251 bool HasInt256 = Subtarget->hasInt256();
7252 MachineFunction &MF = DAG.getMachineFunction();
7253 bool OptForSize = MF.getFunction()->getAttributes().
7254 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
7256 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
7258 if (V1IsUndef && V2IsUndef)
7259 return DAG.getUNDEF(VT);
7261 assert(!V1IsUndef && "Op 1 of shuffle should not be undef");
7263 // Vector shuffle lowering takes 3 steps:
7265 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
7266 // narrowing and commutation of operands should be handled.
7267 // 2) Matching of shuffles with known shuffle masks to x86 target specific
7269 // 3) Rewriting of unmatched masks into new generic shuffle operations,
7270 // so the shuffle can be broken into other shuffles and the legalizer can
7271 // try the lowering again.
7273 // The general idea is that no vector_shuffle operation should be left to
7274 // be matched during isel, all of them must be converted to a target specific
7277 // Normalize the input vectors. Here splats, zeroed vectors, profitable
7278 // narrowing and commutation of operands should be handled. The actual code
7279 // doesn't include all of those, work in progress...
7280 SDValue NewOp = NormalizeVectorShuffle(Op, Subtarget, DAG);
7281 if (NewOp.getNode())
7284 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
7286 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
7287 // unpckh_undef). Only use pshufd if speed is more important than size.
7288 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
7289 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
7290 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
7291 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
7293 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
7294 V2IsUndef && MayFoldVectorLoad(V1))
7295 return getMOVDDup(Op, dl, V1, DAG);
7297 if (isMOVHLPS_v_undef_Mask(M, VT))
7298 return getMOVHighToLow(Op, dl, DAG);
7300 // Use to match splats
7301 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
7302 (VT == MVT::v2f64 || VT == MVT::v2i64))
7303 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
7305 if (isPSHUFDMask(M, VT)) {
7306 // The actual implementation will match the mask in the if above and then
7307 // during isel it can match several different instructions, not only pshufd
7308 // as its name says, sad but true, emulate the behavior for now...
7309 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
7310 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
7312 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
7314 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
7315 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
7317 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
7318 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, TargetMask,
7321 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
7325 if (isPALIGNRMask(M, VT, Subtarget))
7326 return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
7327 getShufflePALIGNRImmediate(SVOp),
7330 // Check if this can be converted into a logical shift.
7331 bool isLeft = false;
7334 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
7335 if (isShift && ShVal.hasOneUse()) {
7336 // If the shifted value has multiple uses, it may be cheaper to use
7337 // v_set0 + movlhps or movhlps, etc.
7338 MVT EltVT = VT.getVectorElementType();
7339 ShAmt *= EltVT.getSizeInBits();
7340 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
7343 if (isMOVLMask(M, VT)) {
7344 if (ISD::isBuildVectorAllZeros(V1.getNode()))
7345 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
7346 if (!isMOVLPMask(M, VT)) {
7347 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
7348 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
7350 if (VT == MVT::v4i32 || VT == MVT::v4f32)
7351 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
7355 // FIXME: fold these into legal mask.
7356 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
7357 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
7359 if (isMOVHLPSMask(M, VT))
7360 return getMOVHighToLow(Op, dl, DAG);
7362 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
7363 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
7365 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
7366 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
7368 if (isMOVLPMask(M, VT))
7369 return getMOVLP(Op, dl, DAG, HasSSE2);
7371 if (ShouldXformToMOVHLPS(M, VT) ||
7372 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
7373 return CommuteVectorShuffle(SVOp, DAG);
7376 // No better options. Use a vshldq / vsrldq.
7377 MVT EltVT = VT.getVectorElementType();
7378 ShAmt *= EltVT.getSizeInBits();
7379 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
7382 bool Commuted = false;
7383 // FIXME: This should also accept a bitcast of a splat? Be careful, not
7384 // 1,1,1,1 -> v8i16 though.
7385 V1IsSplat = isSplatVector(V1.getNode());
7386 V2IsSplat = isSplatVector(V2.getNode());
7388 // Canonicalize the splat or undef, if present, to be on the RHS.
7389 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
7390 CommuteVectorShuffleMask(M, NumElems);
7392 std::swap(V1IsSplat, V2IsSplat);
7396 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
7397 // Shuffling low element of v1 into undef, just return v1.
7400 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
7401 // the instruction selector will not match, so get a canonical MOVL with
7402 // swapped operands to undo the commute.
7403 return getMOVL(DAG, dl, VT, V2, V1);
7406 if (isUNPCKLMask(M, VT, HasInt256))
7407 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
7409 if (isUNPCKHMask(M, VT, HasInt256))
7410 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
7413 // Normalize mask so all entries that point to V2 points to its first
7414 // element then try to match unpck{h|l} again. If match, return a
7415 // new vector_shuffle with the corrected mask.p
7416 SmallVector<int, 8> NewMask(M.begin(), M.end());
7417 NormalizeMask(NewMask, NumElems);
7418 if (isUNPCKLMask(NewMask, VT, HasInt256, true))
7419 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
7420 if (isUNPCKHMask(NewMask, VT, HasInt256, true))
7421 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
7425 // Commute is back and try unpck* again.
7426 // FIXME: this seems wrong.
7427 CommuteVectorShuffleMask(M, NumElems);
7429 std::swap(V1IsSplat, V2IsSplat);
7432 if (isUNPCKLMask(M, VT, HasInt256))
7433 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
7435 if (isUNPCKHMask(M, VT, HasInt256))
7436 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
7439 // Normalize the node to match x86 shuffle ops if needed
7440 if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true)))
7441 return CommuteVectorShuffle(SVOp, DAG);
7443 // The checks below are all present in isShuffleMaskLegal, but they are
7444 // inlined here right now to enable us to directly emit target specific
7445 // nodes, and remove one by one until they don't return Op anymore.
7447 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
7448 SVOp->getSplatIndex() == 0 && V2IsUndef) {
7449 if (VT == MVT::v2f64 || VT == MVT::v2i64)
7450 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
7453 if (isPSHUFHWMask(M, VT, HasInt256))
7454 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
7455 getShufflePSHUFHWImmediate(SVOp),
7458 if (isPSHUFLWMask(M, VT, HasInt256))
7459 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
7460 getShufflePSHUFLWImmediate(SVOp),
7463 if (isSHUFPMask(M, VT))
7464 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
7465 getShuffleSHUFImmediate(SVOp), DAG);
7467 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
7468 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
7469 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
7470 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
7472 //===--------------------------------------------------------------------===//
7473 // Generate target specific nodes for 128 or 256-bit shuffles only
7474 // supported in the AVX instruction set.
7477 // Handle VMOVDDUPY permutations
7478 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
7479 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
7481 // Handle VPERMILPS/D* permutations
7482 if (isVPERMILPMask(M, VT)) {
7483 if ((HasInt256 && VT == MVT::v8i32) || VT == MVT::v16i32)
7484 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
7485 getShuffleSHUFImmediate(SVOp), DAG);
7486 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1,
7487 getShuffleSHUFImmediate(SVOp), DAG);
7490 // Handle VPERM2F128/VPERM2I128 permutations
7491 if (isVPERM2X128Mask(M, VT, HasFp256))
7492 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
7493 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
7495 SDValue BlendOp = LowerVECTOR_SHUFFLEtoBlend(SVOp, Subtarget, DAG);
7496 if (BlendOp.getNode())
7500 if (V2IsUndef && HasInt256 && isPermImmMask(M, VT, Imm8))
7501 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, Imm8, DAG);
7503 if ((V2IsUndef && HasInt256 && VT.is256BitVector() && NumElems == 8) ||
7504 VT.is512BitVector()) {
7505 MVT MaskEltVT = MVT::getIntegerVT(VT.getVectorElementType().getSizeInBits());
7506 MVT MaskVectorVT = MVT::getVectorVT(MaskEltVT, NumElems);
7507 SmallVector<SDValue, 16> permclMask;
7508 for (unsigned i = 0; i != NumElems; ++i) {
7509 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MaskEltVT));
7512 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVectorVT,
7513 &permclMask[0], NumElems);
7515 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
7516 return DAG.getNode(X86ISD::VPERMV, dl, VT,
7517 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
7518 return DAG.getNode(X86ISD::VPERMV3, dl, VT,
7519 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1, V2);
7522 //===--------------------------------------------------------------------===//
7523 // Since no target specific shuffle was selected for this generic one,
7524 // lower it into other known shuffles. FIXME: this isn't true yet, but
7525 // this is the plan.
7528 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
7529 if (VT == MVT::v8i16) {
7530 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
7531 if (NewOp.getNode())
7535 if (VT == MVT::v16i8) {
7536 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, Subtarget, DAG);
7537 if (NewOp.getNode())
7541 if (VT == MVT::v32i8) {
7542 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
7543 if (NewOp.getNode())
7547 // Handle all 128-bit wide vectors with 4 elements, and match them with
7548 // several different shuffle types.
7549 if (NumElems == 4 && VT.is128BitVector())
7550 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
7552 // Handle general 256-bit shuffles
7553 if (VT.is256BitVector())
7554 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
7559 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
7560 MVT VT = Op.getSimpleValueType();
7563 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
7566 if (VT.getSizeInBits() == 8) {
7567 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
7568 Op.getOperand(0), Op.getOperand(1));
7569 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
7570 DAG.getValueType(VT));
7571 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
7574 if (VT.getSizeInBits() == 16) {
7575 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7576 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
7578 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
7579 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
7580 DAG.getNode(ISD::BITCAST, dl,
7584 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
7585 Op.getOperand(0), Op.getOperand(1));
7586 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
7587 DAG.getValueType(VT));
7588 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
7591 if (VT == MVT::f32) {
7592 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
7593 // the result back to FR32 register. It's only worth matching if the
7594 // result has a single use which is a store or a bitcast to i32. And in
7595 // the case of a store, it's not worth it if the index is a constant 0,
7596 // because a MOVSSmr can be used instead, which is smaller and faster.
7597 if (!Op.hasOneUse())
7599 SDNode *User = *Op.getNode()->use_begin();
7600 if ((User->getOpcode() != ISD::STORE ||
7601 (isa<ConstantSDNode>(Op.getOperand(1)) &&
7602 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
7603 (User->getOpcode() != ISD::BITCAST ||
7604 User->getValueType(0) != MVT::i32))
7606 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
7607 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
7610 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
7613 if (VT == MVT::i32 || VT == MVT::i64) {
7614 // ExtractPS/pextrq works with constant index.
7615 if (isa<ConstantSDNode>(Op.getOperand(1)))
7622 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
7623 SelectionDAG &DAG) const {
7625 SDValue Vec = Op.getOperand(0);
7626 MVT VecVT = Vec.getSimpleValueType();
7627 SDValue Idx = Op.getOperand(1);
7628 if (!isa<ConstantSDNode>(Idx)) {
7629 if (VecVT.is512BitVector() ||
7630 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
7631 VecVT.getVectorElementType().getSizeInBits() == 32)) {
7634 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
7635 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
7636 MaskEltVT.getSizeInBits());
7638 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
7639 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
7640 getZeroVector(MaskVT, Subtarget, DAG, dl),
7641 Idx, DAG.getConstant(0, getPointerTy()));
7642 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
7643 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
7644 Perm, DAG.getConstant(0, getPointerTy()));
7649 // If this is a 256-bit vector result, first extract the 128-bit vector and
7650 // then extract the element from the 128-bit vector.
7651 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
7653 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7654 // Get the 128-bit vector.
7655 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
7656 MVT EltVT = VecVT.getVectorElementType();
7658 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
7660 //if (IdxVal >= NumElems/2)
7661 // IdxVal -= NumElems/2;
7662 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
7663 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
7664 DAG.getConstant(IdxVal, MVT::i32));
7667 assert(VecVT.is128BitVector() && "Unexpected vector length");
7669 if (Subtarget->hasSSE41()) {
7670 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
7675 MVT VT = Op.getSimpleValueType();
7676 // TODO: handle v16i8.
7677 if (VT.getSizeInBits() == 16) {
7678 SDValue Vec = Op.getOperand(0);
7679 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7681 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
7682 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
7683 DAG.getNode(ISD::BITCAST, dl,
7686 // Transform it so it match pextrw which produces a 32-bit result.
7687 MVT EltVT = MVT::i32;
7688 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
7689 Op.getOperand(0), Op.getOperand(1));
7690 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
7691 DAG.getValueType(VT));
7692 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
7695 if (VT.getSizeInBits() == 32) {
7696 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7700 // SHUFPS the element to the lowest double word, then movss.
7701 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
7702 MVT VVT = Op.getOperand(0).getSimpleValueType();
7703 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
7704 DAG.getUNDEF(VVT), Mask);
7705 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
7706 DAG.getIntPtrConstant(0));
7709 if (VT.getSizeInBits() == 64) {
7710 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
7711 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
7712 // to match extract_elt for f64.
7713 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7717 // UNPCKHPD the element to the lowest double word, then movsd.
7718 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
7719 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
7720 int Mask[2] = { 1, -1 };
7721 MVT VVT = Op.getOperand(0).getSimpleValueType();
7722 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
7723 DAG.getUNDEF(VVT), Mask);
7724 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
7725 DAG.getIntPtrConstant(0));
7731 static SDValue LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
7732 MVT VT = Op.getSimpleValueType();
7733 MVT EltVT = VT.getVectorElementType();
7736 SDValue N0 = Op.getOperand(0);
7737 SDValue N1 = Op.getOperand(1);
7738 SDValue N2 = Op.getOperand(2);
7740 if (!VT.is128BitVector())
7743 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
7744 isa<ConstantSDNode>(N2)) {
7746 if (VT == MVT::v8i16)
7747 Opc = X86ISD::PINSRW;
7748 else if (VT == MVT::v16i8)
7749 Opc = X86ISD::PINSRB;
7751 Opc = X86ISD::PINSRB;
7753 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
7755 if (N1.getValueType() != MVT::i32)
7756 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
7757 if (N2.getValueType() != MVT::i32)
7758 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
7759 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
7762 if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
7763 // Bits [7:6] of the constant are the source select. This will always be
7764 // zero here. The DAG Combiner may combine an extract_elt index into these
7765 // bits. For example (insert (extract, 3), 2) could be matched by putting
7766 // the '3' into bits [7:6] of X86ISD::INSERTPS.
7767 // Bits [5:4] of the constant are the destination select. This is the
7768 // value of the incoming immediate.
7769 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
7770 // combine either bitwise AND or insert of float 0.0 to set these bits.
7771 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
7772 // Create this as a scalar to vector..
7773 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
7774 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
7777 if ((EltVT == MVT::i32 || EltVT == MVT::i64) && isa<ConstantSDNode>(N2)) {
7778 // PINSR* works with constant index.
7785 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
7786 MVT VT = Op.getSimpleValueType();
7787 MVT EltVT = VT.getVectorElementType();
7790 SDValue N0 = Op.getOperand(0);
7791 SDValue N1 = Op.getOperand(1);
7792 SDValue N2 = Op.getOperand(2);
7794 // If this is a 256-bit vector result, first extract the 128-bit vector,
7795 // insert the element into the extracted half and then place it back.
7796 if (VT.is256BitVector() || VT.is512BitVector()) {
7797 if (!isa<ConstantSDNode>(N2))
7800 // Get the desired 128-bit vector half.
7801 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue();
7802 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
7804 // Insert the element into the desired half.
7805 unsigned NumEltsIn128 = 128/EltVT.getSizeInBits();
7806 unsigned IdxIn128 = IdxVal - (IdxVal/NumEltsIn128) * NumEltsIn128;
7808 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
7809 DAG.getConstant(IdxIn128, MVT::i32));
7811 // Insert the changed part back to the 256-bit vector
7812 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
7815 if (Subtarget->hasSSE41())
7816 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
7818 if (EltVT == MVT::i8)
7821 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
7822 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
7823 // as its second argument.
7824 if (N1.getValueType() != MVT::i32)
7825 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
7826 if (N2.getValueType() != MVT::i32)
7827 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
7828 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
7833 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
7835 MVT OpVT = Op.getSimpleValueType();
7837 // If this is a 256-bit vector result, first insert into a 128-bit
7838 // vector and then insert into the 256-bit vector.
7839 if (!OpVT.is128BitVector()) {
7840 // Insert into a 128-bit vector.
7841 unsigned SizeFactor = OpVT.getSizeInBits()/128;
7842 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
7843 OpVT.getVectorNumElements() / SizeFactor);
7845 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
7847 // Insert the 128-bit vector.
7848 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
7851 if (OpVT == MVT::v1i64 &&
7852 Op.getOperand(0).getValueType() == MVT::i64)
7853 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
7855 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
7856 assert(OpVT.is128BitVector() && "Expected an SSE type!");
7857 return DAG.getNode(ISD::BITCAST, dl, OpVT,
7858 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
7861 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
7862 // a simple subregister reference or explicit instructions to grab
7863 // upper bits of a vector.
7864 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
7865 SelectionDAG &DAG) {
7867 SDValue In = Op.getOperand(0);
7868 SDValue Idx = Op.getOperand(1);
7869 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7870 MVT ResVT = Op.getSimpleValueType();
7871 MVT InVT = In.getSimpleValueType();
7873 if (Subtarget->hasFp256()) {
7874 if (ResVT.is128BitVector() &&
7875 (InVT.is256BitVector() || InVT.is512BitVector()) &&
7876 isa<ConstantSDNode>(Idx)) {
7877 return Extract128BitVector(In, IdxVal, DAG, dl);
7879 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
7880 isa<ConstantSDNode>(Idx)) {
7881 return Extract256BitVector(In, IdxVal, DAG, dl);
7887 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
7888 // simple superregister reference or explicit instructions to insert
7889 // the upper bits of a vector.
7890 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
7891 SelectionDAG &DAG) {
7892 if (Subtarget->hasFp256()) {
7893 SDLoc dl(Op.getNode());
7894 SDValue Vec = Op.getNode()->getOperand(0);
7895 SDValue SubVec = Op.getNode()->getOperand(1);
7896 SDValue Idx = Op.getNode()->getOperand(2);
7898 if ((Op.getNode()->getSimpleValueType(0).is256BitVector() ||
7899 Op.getNode()->getSimpleValueType(0).is512BitVector()) &&
7900 SubVec.getNode()->getSimpleValueType(0).is128BitVector() &&
7901 isa<ConstantSDNode>(Idx)) {
7902 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7903 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
7906 if (Op.getNode()->getSimpleValueType(0).is512BitVector() &&
7907 SubVec.getNode()->getSimpleValueType(0).is256BitVector() &&
7908 isa<ConstantSDNode>(Idx)) {
7909 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7910 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
7916 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
7917 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
7918 // one of the above mentioned nodes. It has to be wrapped because otherwise
7919 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
7920 // be used to form addressing mode. These wrapped nodes will be selected
7923 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
7924 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
7926 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7928 unsigned char OpFlag = 0;
7929 unsigned WrapperKind = X86ISD::Wrapper;
7930 CodeModel::Model M = getTargetMachine().getCodeModel();
7932 if (Subtarget->isPICStyleRIPRel() &&
7933 (M == CodeModel::Small || M == CodeModel::Kernel))
7934 WrapperKind = X86ISD::WrapperRIP;
7935 else if (Subtarget->isPICStyleGOT())
7936 OpFlag = X86II::MO_GOTOFF;
7937 else if (Subtarget->isPICStyleStubPIC())
7938 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7940 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
7942 CP->getOffset(), OpFlag);
7944 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7945 // With PIC, the address is actually $g + Offset.
7947 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7948 DAG.getNode(X86ISD::GlobalBaseReg,
7949 SDLoc(), getPointerTy()),
7956 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
7957 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
7959 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7961 unsigned char OpFlag = 0;
7962 unsigned WrapperKind = X86ISD::Wrapper;
7963 CodeModel::Model M = getTargetMachine().getCodeModel();
7965 if (Subtarget->isPICStyleRIPRel() &&
7966 (M == CodeModel::Small || M == CodeModel::Kernel))
7967 WrapperKind = X86ISD::WrapperRIP;
7968 else if (Subtarget->isPICStyleGOT())
7969 OpFlag = X86II::MO_GOTOFF;
7970 else if (Subtarget->isPICStyleStubPIC())
7971 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7973 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
7976 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7978 // With PIC, the address is actually $g + Offset.
7980 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7981 DAG.getNode(X86ISD::GlobalBaseReg,
7982 SDLoc(), getPointerTy()),
7989 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
7990 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
7992 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7994 unsigned char OpFlag = 0;
7995 unsigned WrapperKind = X86ISD::Wrapper;
7996 CodeModel::Model M = getTargetMachine().getCodeModel();
7998 if (Subtarget->isPICStyleRIPRel() &&
7999 (M == CodeModel::Small || M == CodeModel::Kernel)) {
8000 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
8001 OpFlag = X86II::MO_GOTPCREL;
8002 WrapperKind = X86ISD::WrapperRIP;
8003 } else if (Subtarget->isPICStyleGOT()) {
8004 OpFlag = X86II::MO_GOT;
8005 } else if (Subtarget->isPICStyleStubPIC()) {
8006 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
8007 } else if (Subtarget->isPICStyleStubNoDynamic()) {
8008 OpFlag = X86II::MO_DARWIN_NONLAZY;
8011 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
8014 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
8016 // With PIC, the address is actually $g + Offset.
8017 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
8018 !Subtarget->is64Bit()) {
8019 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8020 DAG.getNode(X86ISD::GlobalBaseReg,
8021 SDLoc(), getPointerTy()),
8025 // For symbols that require a load from a stub to get the address, emit the
8027 if (isGlobalStubReference(OpFlag))
8028 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
8029 MachinePointerInfo::getGOT(), false, false, false, 0);
8035 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
8036 // Create the TargetBlockAddressAddress node.
8037 unsigned char OpFlags =
8038 Subtarget->ClassifyBlockAddressReference();
8039 CodeModel::Model M = getTargetMachine().getCodeModel();
8040 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
8041 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
8043 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
8046 if (Subtarget->isPICStyleRIPRel() &&
8047 (M == CodeModel::Small || M == CodeModel::Kernel))
8048 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
8050 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
8052 // With PIC, the address is actually $g + Offset.
8053 if (isGlobalRelativeToPICBase(OpFlags)) {
8054 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
8055 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
8063 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
8064 int64_t Offset, SelectionDAG &DAG) const {
8065 // Create the TargetGlobalAddress node, folding in the constant
8066 // offset if it is legal.
8067 unsigned char OpFlags =
8068 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
8069 CodeModel::Model M = getTargetMachine().getCodeModel();
8071 if (OpFlags == X86II::MO_NO_FLAG &&
8072 X86::isOffsetSuitableForCodeModel(Offset, M)) {
8073 // A direct static reference to a global.
8074 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
8077 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
8080 if (Subtarget->isPICStyleRIPRel() &&
8081 (M == CodeModel::Small || M == CodeModel::Kernel))
8082 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
8084 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
8086 // With PIC, the address is actually $g + Offset.
8087 if (isGlobalRelativeToPICBase(OpFlags)) {
8088 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
8089 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
8093 // For globals that require a load from a stub to get the address, emit the
8095 if (isGlobalStubReference(OpFlags))
8096 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
8097 MachinePointerInfo::getGOT(), false, false, false, 0);
8099 // If there was a non-zero offset that we didn't fold, create an explicit
8102 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
8103 DAG.getConstant(Offset, getPointerTy()));
8109 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
8110 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
8111 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
8112 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
8116 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
8117 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
8118 unsigned char OperandFlags, bool LocalDynamic = false) {
8119 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
8120 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
8122 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
8123 GA->getValueType(0),
8127 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
8131 SDValue Ops[] = { Chain, TGA, *InFlag };
8132 Chain = DAG.getNode(CallType, dl, NodeTys, Ops, array_lengthof(Ops));
8134 SDValue Ops[] = { Chain, TGA };
8135 Chain = DAG.getNode(CallType, dl, NodeTys, Ops, array_lengthof(Ops));
8138 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
8139 MFI->setAdjustsStack(true);
8141 SDValue Flag = Chain.getValue(1);
8142 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
8145 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
8147 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
8150 SDLoc dl(GA); // ? function entry point might be better
8151 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
8152 DAG.getNode(X86ISD::GlobalBaseReg,
8153 SDLoc(), PtrVT), InFlag);
8154 InFlag = Chain.getValue(1);
8156 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
8159 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
8161 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
8163 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
8164 X86::RAX, X86II::MO_TLSGD);
8167 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
8173 // Get the start address of the TLS block for this module.
8174 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
8175 .getInfo<X86MachineFunctionInfo>();
8176 MFI->incNumLocalDynamicTLSAccesses();
8180 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT, X86::RAX,
8181 X86II::MO_TLSLD, /*LocalDynamic=*/true);
8184 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
8185 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
8186 InFlag = Chain.getValue(1);
8187 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
8188 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
8191 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
8195 unsigned char OperandFlags = X86II::MO_DTPOFF;
8196 unsigned WrapperKind = X86ISD::Wrapper;
8197 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
8198 GA->getValueType(0),
8199 GA->getOffset(), OperandFlags);
8200 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
8202 // Add x@dtpoff with the base.
8203 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
8206 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
8207 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
8208 const EVT PtrVT, TLSModel::Model model,
8209 bool is64Bit, bool isPIC) {
8212 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
8213 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
8214 is64Bit ? 257 : 256));
8216 SDValue ThreadPointer =
8217 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0),
8218 MachinePointerInfo(Ptr), false, false, false, 0);
8220 unsigned char OperandFlags = 0;
8221 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
8223 unsigned WrapperKind = X86ISD::Wrapper;
8224 if (model == TLSModel::LocalExec) {
8225 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
8226 } else if (model == TLSModel::InitialExec) {
8228 OperandFlags = X86II::MO_GOTTPOFF;
8229 WrapperKind = X86ISD::WrapperRIP;
8231 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
8234 llvm_unreachable("Unexpected model");
8237 // emit "addl x@ntpoff,%eax" (local exec)
8238 // or "addl x@indntpoff,%eax" (initial exec)
8239 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
8241 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
8242 GA->getOffset(), OperandFlags);
8243 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
8245 if (model == TLSModel::InitialExec) {
8246 if (isPIC && !is64Bit) {
8247 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
8248 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
8252 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
8253 MachinePointerInfo::getGOT(), false, false, false, 0);
8256 // The address of the thread local variable is the add of the thread
8257 // pointer with the offset of the variable.
8258 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
8262 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
8264 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
8265 const GlobalValue *GV = GA->getGlobal();
8267 if (Subtarget->isTargetELF()) {
8268 TLSModel::Model model = getTargetMachine().getTLSModel(GV);
8271 case TLSModel::GeneralDynamic:
8272 if (Subtarget->is64Bit())
8273 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
8274 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
8275 case TLSModel::LocalDynamic:
8276 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
8277 Subtarget->is64Bit());
8278 case TLSModel::InitialExec:
8279 case TLSModel::LocalExec:
8280 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
8281 Subtarget->is64Bit(),
8282 getTargetMachine().getRelocationModel() == Reloc::PIC_);
8284 llvm_unreachable("Unknown TLS model.");
8287 if (Subtarget->isTargetDarwin()) {
8288 // Darwin only has one model of TLS. Lower to that.
8289 unsigned char OpFlag = 0;
8290 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
8291 X86ISD::WrapperRIP : X86ISD::Wrapper;
8293 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
8295 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) &&
8296 !Subtarget->is64Bit();
8298 OpFlag = X86II::MO_TLVP_PIC_BASE;
8300 OpFlag = X86II::MO_TLVP;
8302 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
8303 GA->getValueType(0),
8304 GA->getOffset(), OpFlag);
8305 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
8307 // With PIC32, the address is actually $g + Offset.
8309 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8310 DAG.getNode(X86ISD::GlobalBaseReg,
8311 SDLoc(), getPointerTy()),
8314 // Lowering the machine isd will make sure everything is in the right
8316 SDValue Chain = DAG.getEntryNode();
8317 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
8318 SDValue Args[] = { Chain, Offset };
8319 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2);
8321 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
8322 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
8323 MFI->setAdjustsStack(true);
8325 // And our return value (tls address) is in the standard call return value
8327 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
8328 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
8332 if (Subtarget->isTargetWindows() || Subtarget->isTargetMingw()) {
8333 // Just use the implicit TLS architecture
8334 // Need to generate someting similar to:
8335 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
8337 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
8338 // mov rcx, qword [rdx+rcx*8]
8339 // mov eax, .tls$:tlsvar
8340 // [rax+rcx] contains the address
8341 // Windows 64bit: gs:0x58
8342 // Windows 32bit: fs:__tls_array
8344 // If GV is an alias then use the aliasee for determining
8345 // thread-localness.
8346 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
8347 GV = GA->resolveAliasedGlobal(false);
8349 SDValue Chain = DAG.getEntryNode();
8351 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
8352 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
8353 // use its literal value of 0x2C.
8354 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
8355 ? Type::getInt8PtrTy(*DAG.getContext(),
8357 : Type::getInt32PtrTy(*DAG.getContext(),
8360 SDValue TlsArray = Subtarget->is64Bit() ? DAG.getIntPtrConstant(0x58) :
8361 (Subtarget->isTargetMingw() ? DAG.getIntPtrConstant(0x2C) :
8362 DAG.getExternalSymbol("_tls_array", getPointerTy()));
8364 SDValue ThreadPointer = DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
8365 MachinePointerInfo(Ptr),
8366 false, false, false, 0);
8368 // Load the _tls_index variable
8369 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
8370 if (Subtarget->is64Bit())
8371 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
8372 IDX, MachinePointerInfo(), MVT::i32,
8375 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
8376 false, false, false, 0);
8378 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
8380 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
8382 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
8383 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
8384 false, false, false, 0);
8386 // Get the offset of start of .tls section
8387 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
8388 GA->getValueType(0),
8389 GA->getOffset(), X86II::MO_SECREL);
8390 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
8392 // The address of the thread local variable is the add of the thread
8393 // pointer with the offset of the variable.
8394 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
8397 llvm_unreachable("TLS not implemented for this target.");
8400 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
8401 /// and take a 2 x i32 value to shift plus a shift amount.
8402 SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const{
8403 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
8404 EVT VT = Op.getValueType();
8405 unsigned VTBits = VT.getSizeInBits();
8407 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
8408 SDValue ShOpLo = Op.getOperand(0);
8409 SDValue ShOpHi = Op.getOperand(1);
8410 SDValue ShAmt = Op.getOperand(2);
8411 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
8412 DAG.getConstant(VTBits - 1, MVT::i8))
8413 : DAG.getConstant(0, VT);
8416 if (Op.getOpcode() == ISD::SHL_PARTS) {
8417 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
8418 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
8420 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
8421 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
8424 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
8425 DAG.getConstant(VTBits, MVT::i8));
8426 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
8427 AndNode, DAG.getConstant(0, MVT::i8));
8430 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8431 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
8432 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
8434 if (Op.getOpcode() == ISD::SHL_PARTS) {
8435 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
8436 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
8438 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
8439 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
8442 SDValue Ops[2] = { Lo, Hi };
8443 return DAG.getMergeValues(Ops, array_lengthof(Ops), dl);
8446 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
8447 SelectionDAG &DAG) const {
8448 EVT SrcVT = Op.getOperand(0).getValueType();
8450 if (SrcVT.isVector())
8453 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
8454 "Unknown SINT_TO_FP to lower!");
8456 // These are really Legal; return the operand so the caller accepts it as
8458 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
8460 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
8461 Subtarget->is64Bit()) {
8466 unsigned Size = SrcVT.getSizeInBits()/8;
8467 MachineFunction &MF = DAG.getMachineFunction();
8468 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
8469 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8470 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
8472 MachinePointerInfo::getFixedStack(SSFI),
8474 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
8477 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
8479 SelectionDAG &DAG) const {
8483 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
8485 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
8487 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
8489 unsigned ByteSize = SrcVT.getSizeInBits()/8;
8491 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
8492 MachineMemOperand *MMO;
8494 int SSFI = FI->getIndex();
8496 DAG.getMachineFunction()
8497 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8498 MachineMemOperand::MOLoad, ByteSize, ByteSize);
8500 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
8501 StackSlot = StackSlot.getOperand(1);
8503 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
8504 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
8506 Tys, Ops, array_lengthof(Ops),
8510 Chain = Result.getValue(1);
8511 SDValue InFlag = Result.getValue(2);
8513 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
8514 // shouldn't be necessary except that RFP cannot be live across
8515 // multiple blocks. When stackifier is fixed, they can be uncoupled.
8516 MachineFunction &MF = DAG.getMachineFunction();
8517 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
8518 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
8519 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8520 Tys = DAG.getVTList(MVT::Other);
8522 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
8524 MachineMemOperand *MMO =
8525 DAG.getMachineFunction()
8526 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8527 MachineMemOperand::MOStore, SSFISize, SSFISize);
8529 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
8530 Ops, array_lengthof(Ops),
8531 Op.getValueType(), MMO);
8532 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
8533 MachinePointerInfo::getFixedStack(SSFI),
8534 false, false, false, 0);
8540 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
8541 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
8542 SelectionDAG &DAG) const {
8543 // This algorithm is not obvious. Here it is what we're trying to output:
8546 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
8547 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
8551 pshufd $0x4e, %xmm0, %xmm1
8557 LLVMContext *Context = DAG.getContext();
8559 // Build some magic constants.
8560 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
8561 Constant *C0 = ConstantDataVector::get(*Context, CV0);
8562 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
8564 SmallVector<Constant*,2> CV1;
8566 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
8567 APInt(64, 0x4330000000000000ULL))));
8569 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
8570 APInt(64, 0x4530000000000000ULL))));
8571 Constant *C1 = ConstantVector::get(CV1);
8572 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
8574 // Load the 64-bit value into an XMM register.
8575 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
8577 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
8578 MachinePointerInfo::getConstantPool(),
8579 false, false, false, 16);
8580 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
8581 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
8584 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
8585 MachinePointerInfo::getConstantPool(),
8586 false, false, false, 16);
8587 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
8588 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
8591 if (Subtarget->hasSSE3()) {
8592 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
8593 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
8595 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
8596 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
8598 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
8599 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
8603 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
8604 DAG.getIntPtrConstant(0));
8607 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
8608 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
8609 SelectionDAG &DAG) const {
8611 // FP constant to bias correct the final result.
8612 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
8615 // Load the 32-bit value into an XMM register.
8616 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
8619 // Zero out the upper parts of the register.
8620 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
8622 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
8623 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
8624 DAG.getIntPtrConstant(0));
8626 // Or the load with the bias.
8627 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
8628 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
8629 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
8631 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
8632 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
8633 MVT::v2f64, Bias)));
8634 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
8635 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
8636 DAG.getIntPtrConstant(0));
8638 // Subtract the bias.
8639 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
8641 // Handle final rounding.
8642 EVT DestVT = Op.getValueType();
8644 if (DestVT.bitsLT(MVT::f64))
8645 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
8646 DAG.getIntPtrConstant(0));
8647 if (DestVT.bitsGT(MVT::f64))
8648 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
8650 // Handle final rounding.
8654 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
8655 SelectionDAG &DAG) const {
8656 SDValue N0 = Op.getOperand(0);
8657 EVT SVT = N0.getValueType();
8660 assert((SVT == MVT::v4i8 || SVT == MVT::v4i16 ||
8661 SVT == MVT::v8i8 || SVT == MVT::v8i16) &&
8662 "Custom UINT_TO_FP is not supported!");
8664 EVT NVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
8665 SVT.getVectorNumElements());
8666 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
8667 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
8670 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
8671 SelectionDAG &DAG) const {
8672 SDValue N0 = Op.getOperand(0);
8675 if (Op.getValueType().isVector())
8676 return lowerUINT_TO_FP_vec(Op, DAG);
8678 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
8679 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
8680 // the optimization here.
8681 if (DAG.SignBitIsZero(N0))
8682 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
8684 EVT SrcVT = N0.getValueType();
8685 EVT DstVT = Op.getValueType();
8686 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
8687 return LowerUINT_TO_FP_i64(Op, DAG);
8688 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
8689 return LowerUINT_TO_FP_i32(Op, DAG);
8690 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
8693 // Make a 64-bit buffer, and use it to build an FILD.
8694 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
8695 if (SrcVT == MVT::i32) {
8696 SDValue WordOff = DAG.getConstant(4, getPointerTy());
8697 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
8698 getPointerTy(), StackSlot, WordOff);
8699 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
8700 StackSlot, MachinePointerInfo(),
8702 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
8703 OffsetSlot, MachinePointerInfo(),
8705 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
8709 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
8710 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
8711 StackSlot, MachinePointerInfo(),
8713 // For i64 source, we need to add the appropriate power of 2 if the input
8714 // was negative. This is the same as the optimization in
8715 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
8716 // we must be careful to do the computation in x87 extended precision, not
8717 // in SSE. (The generic code can't know it's OK to do this, or how to.)
8718 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
8719 MachineMemOperand *MMO =
8720 DAG.getMachineFunction()
8721 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8722 MachineMemOperand::MOLoad, 8, 8);
8724 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
8725 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
8726 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
8727 array_lengthof(Ops), MVT::i64, MMO);
8729 APInt FF(32, 0x5F800000ULL);
8731 // Check whether the sign bit is set.
8732 SDValue SignSet = DAG.getSetCC(dl,
8733 getSetCCResultType(*DAG.getContext(), MVT::i64),
8734 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
8737 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
8738 SDValue FudgePtr = DAG.getConstantPool(
8739 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
8742 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
8743 SDValue Zero = DAG.getIntPtrConstant(0);
8744 SDValue Four = DAG.getIntPtrConstant(4);
8745 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
8747 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
8749 // Load the value out, extending it from f32 to f80.
8750 // FIXME: Avoid the extend by constructing the right constant pool?
8751 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
8752 FudgePtr, MachinePointerInfo::getConstantPool(),
8753 MVT::f32, false, false, 4);
8754 // Extend everything to 80 bits to force it to be done on x87.
8755 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
8756 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
8759 std::pair<SDValue,SDValue>
8760 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
8761 bool IsSigned, bool IsReplace) const {
8764 EVT DstTy = Op.getValueType();
8766 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
8767 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
8771 assert(DstTy.getSimpleVT() <= MVT::i64 &&
8772 DstTy.getSimpleVT() >= MVT::i16 &&
8773 "Unknown FP_TO_INT to lower!");
8775 // These are really Legal.
8776 if (DstTy == MVT::i32 &&
8777 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
8778 return std::make_pair(SDValue(), SDValue());
8779 if (Subtarget->is64Bit() &&
8780 DstTy == MVT::i64 &&
8781 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
8782 return std::make_pair(SDValue(), SDValue());
8784 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
8785 // stack slot, or into the FTOL runtime function.
8786 MachineFunction &MF = DAG.getMachineFunction();
8787 unsigned MemSize = DstTy.getSizeInBits()/8;
8788 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
8789 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8792 if (!IsSigned && isIntegerTypeFTOL(DstTy))
8793 Opc = X86ISD::WIN_FTOL;
8795 switch (DstTy.getSimpleVT().SimpleTy) {
8796 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
8797 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
8798 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
8799 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
8802 SDValue Chain = DAG.getEntryNode();
8803 SDValue Value = Op.getOperand(0);
8804 EVT TheVT = Op.getOperand(0).getValueType();
8805 // FIXME This causes a redundant load/store if the SSE-class value is already
8806 // in memory, such as if it is on the callstack.
8807 if (isScalarFPTypeInSSEReg(TheVT)) {
8808 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
8809 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
8810 MachinePointerInfo::getFixedStack(SSFI),
8812 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
8814 Chain, StackSlot, DAG.getValueType(TheVT)
8817 MachineMemOperand *MMO =
8818 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8819 MachineMemOperand::MOLoad, MemSize, MemSize);
8820 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops,
8821 array_lengthof(Ops), DstTy, MMO);
8822 Chain = Value.getValue(1);
8823 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
8824 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8827 MachineMemOperand *MMO =
8828 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8829 MachineMemOperand::MOStore, MemSize, MemSize);
8831 if (Opc != X86ISD::WIN_FTOL) {
8832 // Build the FP_TO_INT*_IN_MEM
8833 SDValue Ops[] = { Chain, Value, StackSlot };
8834 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
8835 Ops, array_lengthof(Ops), DstTy,
8837 return std::make_pair(FIST, StackSlot);
8839 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
8840 DAG.getVTList(MVT::Other, MVT::Glue),
8842 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
8843 MVT::i32, ftol.getValue(1));
8844 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
8845 MVT::i32, eax.getValue(2));
8846 SDValue Ops[] = { eax, edx };
8847 SDValue pair = IsReplace
8848 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops, array_lengthof(Ops))
8849 : DAG.getMergeValues(Ops, array_lengthof(Ops), DL);
8850 return std::make_pair(pair, SDValue());
8854 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
8855 const X86Subtarget *Subtarget) {
8856 MVT VT = Op->getSimpleValueType(0);
8857 SDValue In = Op->getOperand(0);
8858 MVT InVT = In.getSimpleValueType();
8861 // Optimize vectors in AVX mode:
8864 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
8865 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
8866 // Concat upper and lower parts.
8869 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
8870 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
8871 // Concat upper and lower parts.
8874 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
8875 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
8876 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
8879 if (Subtarget->hasInt256())
8880 return DAG.getNode(X86ISD::VZEXT_MOVL, dl, VT, In);
8882 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
8883 SDValue Undef = DAG.getUNDEF(InVT);
8884 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
8885 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
8886 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
8888 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
8889 VT.getVectorNumElements()/2);
8891 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
8892 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
8894 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
8897 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
8898 SelectionDAG &DAG) {
8899 MVT VT = Op->getValueType(0).getSimpleVT();
8900 SDValue In = Op->getOperand(0);
8901 MVT InVT = In.getValueType().getSimpleVT();
8903 unsigned int NumElts = VT.getVectorNumElements();
8904 if (NumElts != 8 && NumElts != 16)
8907 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
8908 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
8910 EVT ExtVT = (NumElts == 8)? MVT::v8i64 : MVT::v16i32;
8911 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8912 // Now we have only mask extension
8913 assert(InVT.getVectorElementType() == MVT::i1);
8914 SDValue Cst = DAG.getTargetConstant(1, ExtVT.getScalarType());
8915 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
8916 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
8917 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
8918 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
8919 MachinePointerInfo::getConstantPool(),
8920 false, false, false, Alignment);
8922 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, DL, ExtVT, In, Ld);
8923 if (VT.is512BitVector())
8925 return DAG.getNode(X86ISD::VTRUNC, DL, VT, Brcst);
8928 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
8929 SelectionDAG &DAG) {
8930 if (Subtarget->hasFp256()) {
8931 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
8939 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
8940 SelectionDAG &DAG) {
8942 MVT VT = Op.getSimpleValueType();
8943 SDValue In = Op.getOperand(0);
8944 MVT SVT = In.getSimpleValueType();
8946 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
8947 return LowerZERO_EXTEND_AVX512(Op, DAG);
8949 if (Subtarget->hasFp256()) {
8950 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
8955 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
8956 VT.getVectorNumElements() != SVT.getVectorNumElements());
8960 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
8962 MVT VT = Op.getSimpleValueType();
8963 SDValue In = Op.getOperand(0);
8964 MVT InVT = In.getSimpleValueType();
8965 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
8966 "Invalid TRUNCATE operation");
8968 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
8969 if (VT.getVectorElementType().getSizeInBits() >=8)
8970 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
8972 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
8973 unsigned NumElts = InVT.getVectorNumElements();
8974 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
8975 if (InVT.getSizeInBits() < 512) {
8976 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
8977 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
8980 SDValue Cst = DAG.getTargetConstant(1, InVT.getVectorElementType());
8981 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
8982 SDValue CP = DAG.getConstantPool(C, getPointerTy());
8983 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
8984 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
8985 MachinePointerInfo::getConstantPool(),
8986 false, false, false, Alignment);
8987 SDValue OneV = DAG.getNode(X86ISD::VBROADCAST, DL, InVT, Ld);
8988 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
8989 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
8992 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
8993 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
8994 if (Subtarget->hasInt256()) {
8995 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
8996 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
8997 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
8999 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
9000 DAG.getIntPtrConstant(0));
9003 // On AVX, v4i64 -> v4i32 becomes a sequence that uses PSHUFD and MOVLHPS.
9004 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
9005 DAG.getIntPtrConstant(0));
9006 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
9007 DAG.getIntPtrConstant(2));
9009 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
9010 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
9013 static const int ShufMask1[] = {0, 2, 0, 0};
9014 SDValue Undef = DAG.getUNDEF(VT);
9015 OpLo = DAG.getVectorShuffle(VT, DL, OpLo, Undef, ShufMask1);
9016 OpHi = DAG.getVectorShuffle(VT, DL, OpHi, Undef, ShufMask1);
9018 // The MOVLHPS mask:
9019 static const int ShufMask2[] = {0, 1, 4, 5};
9020 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask2);
9023 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
9024 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
9025 if (Subtarget->hasInt256()) {
9026 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
9028 SmallVector<SDValue,32> pshufbMask;
9029 for (unsigned i = 0; i < 2; ++i) {
9030 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
9031 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
9032 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
9033 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
9034 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
9035 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
9036 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
9037 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
9038 for (unsigned j = 0; j < 8; ++j)
9039 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
9041 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8,
9042 &pshufbMask[0], 32);
9043 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
9044 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
9046 static const int ShufMask[] = {0, 2, -1, -1};
9047 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
9049 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
9050 DAG.getIntPtrConstant(0));
9051 return DAG.getNode(ISD::BITCAST, DL, VT, In);
9054 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
9055 DAG.getIntPtrConstant(0));
9057 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
9058 DAG.getIntPtrConstant(4));
9060 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
9061 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
9064 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
9065 -1, -1, -1, -1, -1, -1, -1, -1};
9067 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
9068 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
9069 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
9071 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
9072 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
9074 // The MOVLHPS Mask:
9075 static const int ShufMask2[] = {0, 1, 4, 5};
9076 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
9077 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
9080 // Handle truncation of V256 to V128 using shuffles.
9081 if (!VT.is128BitVector() || !InVT.is256BitVector())
9084 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
9086 unsigned NumElems = VT.getVectorNumElements();
9087 EVT NVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
9090 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
9091 // Prepare truncation shuffle mask
9092 for (unsigned i = 0; i != NumElems; ++i)
9094 SDValue V = DAG.getVectorShuffle(NVT, DL,
9095 DAG.getNode(ISD::BITCAST, DL, NVT, In),
9096 DAG.getUNDEF(NVT), &MaskVec[0]);
9097 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
9098 DAG.getIntPtrConstant(0));
9101 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
9102 SelectionDAG &DAG) const {
9103 MVT VT = Op.getSimpleValueType();
9104 if (VT.isVector()) {
9105 if (VT == MVT::v8i16)
9106 return DAG.getNode(ISD::TRUNCATE, SDLoc(Op), VT,
9107 DAG.getNode(ISD::FP_TO_SINT, SDLoc(Op),
9108 MVT::v8i32, Op.getOperand(0)));
9112 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
9113 /*IsSigned=*/ true, /*IsReplace=*/ false);
9114 SDValue FIST = Vals.first, StackSlot = Vals.second;
9115 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
9116 if (FIST.getNode() == 0) return Op;
9118 if (StackSlot.getNode())
9120 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
9121 FIST, StackSlot, MachinePointerInfo(),
9122 false, false, false, 0);
9124 // The node is the result.
9128 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
9129 SelectionDAG &DAG) const {
9130 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
9131 /*IsSigned=*/ false, /*IsReplace=*/ false);
9132 SDValue FIST = Vals.first, StackSlot = Vals.second;
9133 assert(FIST.getNode() && "Unexpected failure");
9135 if (StackSlot.getNode())
9137 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
9138 FIST, StackSlot, MachinePointerInfo(),
9139 false, false, false, 0);
9141 // The node is the result.
9145 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
9147 MVT VT = Op.getSimpleValueType();
9148 SDValue In = Op.getOperand(0);
9149 MVT SVT = In.getSimpleValueType();
9151 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
9153 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
9154 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
9155 In, DAG.getUNDEF(SVT)));
9158 SDValue X86TargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) const {
9159 LLVMContext *Context = DAG.getContext();
9161 MVT VT = Op.getSimpleValueType();
9163 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
9164 if (VT.isVector()) {
9165 EltVT = VT.getVectorElementType();
9166 NumElts = VT.getVectorNumElements();
9169 if (EltVT == MVT::f64)
9170 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
9171 APInt(64, ~(1ULL << 63))));
9173 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEsingle,
9174 APInt(32, ~(1U << 31))));
9175 C = ConstantVector::getSplat(NumElts, C);
9176 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy());
9177 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
9178 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9179 MachinePointerInfo::getConstantPool(),
9180 false, false, false, Alignment);
9181 if (VT.isVector()) {
9182 MVT ANDVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
9183 return DAG.getNode(ISD::BITCAST, dl, VT,
9184 DAG.getNode(ISD::AND, dl, ANDVT,
9185 DAG.getNode(ISD::BITCAST, dl, ANDVT,
9187 DAG.getNode(ISD::BITCAST, dl, ANDVT, Mask)));
9189 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
9192 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const {
9193 LLVMContext *Context = DAG.getContext();
9195 MVT VT = Op.getSimpleValueType();
9197 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
9198 if (VT.isVector()) {
9199 EltVT = VT.getVectorElementType();
9200 NumElts = VT.getVectorNumElements();
9203 if (EltVT == MVT::f64)
9204 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
9205 APInt(64, 1ULL << 63)));
9207 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEsingle,
9208 APInt(32, 1U << 31)));
9209 C = ConstantVector::getSplat(NumElts, C);
9210 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy());
9211 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
9212 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9213 MachinePointerInfo::getConstantPool(),
9214 false, false, false, Alignment);
9215 if (VT.isVector()) {
9216 MVT XORVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits()/64);
9217 return DAG.getNode(ISD::BITCAST, dl, VT,
9218 DAG.getNode(ISD::XOR, dl, XORVT,
9219 DAG.getNode(ISD::BITCAST, dl, XORVT,
9221 DAG.getNode(ISD::BITCAST, dl, XORVT, Mask)));
9224 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
9227 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
9228 LLVMContext *Context = DAG.getContext();
9229 SDValue Op0 = Op.getOperand(0);
9230 SDValue Op1 = Op.getOperand(1);
9232 MVT VT = Op.getSimpleValueType();
9233 MVT SrcVT = Op1.getSimpleValueType();
9235 // If second operand is smaller, extend it first.
9236 if (SrcVT.bitsLT(VT)) {
9237 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
9240 // And if it is bigger, shrink it first.
9241 if (SrcVT.bitsGT(VT)) {
9242 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
9246 // At this point the operands and the result should have the same
9247 // type, and that won't be f80 since that is not custom lowered.
9249 // First get the sign bit of second operand.
9250 SmallVector<Constant*,4> CV;
9251 if (SrcVT == MVT::f64) {
9252 const fltSemantics &Sem = APFloat::IEEEdouble;
9253 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 1ULL << 63))));
9254 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
9256 const fltSemantics &Sem = APFloat::IEEEsingle;
9257 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 1U << 31))));
9258 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9259 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9260 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9262 Constant *C = ConstantVector::get(CV);
9263 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
9264 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
9265 MachinePointerInfo::getConstantPool(),
9266 false, false, false, 16);
9267 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
9269 // Shift sign bit right or left if the two operands have different types.
9270 if (SrcVT.bitsGT(VT)) {
9271 // Op0 is MVT::f32, Op1 is MVT::f64.
9272 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
9273 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
9274 DAG.getConstant(32, MVT::i32));
9275 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
9276 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
9277 DAG.getIntPtrConstant(0));
9280 // Clear first operand sign bit.
9282 if (VT == MVT::f64) {
9283 const fltSemantics &Sem = APFloat::IEEEdouble;
9284 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
9285 APInt(64, ~(1ULL << 63)))));
9286 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
9288 const fltSemantics &Sem = APFloat::IEEEsingle;
9289 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
9290 APInt(32, ~(1U << 31)))));
9291 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9292 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9293 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9295 C = ConstantVector::get(CV);
9296 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
9297 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9298 MachinePointerInfo::getConstantPool(),
9299 false, false, false, 16);
9300 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
9302 // Or the value with the sign bit.
9303 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
9306 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
9307 SDValue N0 = Op.getOperand(0);
9309 MVT VT = Op.getSimpleValueType();
9311 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
9312 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
9313 DAG.getConstant(1, VT));
9314 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
9317 // LowerVectorAllZeroTest - Check whether an OR'd tree is PTEST-able.
9319 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
9320 SelectionDAG &DAG) {
9321 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
9323 if (!Subtarget->hasSSE41())
9326 if (!Op->hasOneUse())
9329 SDNode *N = Op.getNode();
9332 SmallVector<SDValue, 8> Opnds;
9333 DenseMap<SDValue, unsigned> VecInMap;
9334 EVT VT = MVT::Other;
9336 // Recognize a special case where a vector is casted into wide integer to
9338 Opnds.push_back(N->getOperand(0));
9339 Opnds.push_back(N->getOperand(1));
9341 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
9342 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
9343 // BFS traverse all OR'd operands.
9344 if (I->getOpcode() == ISD::OR) {
9345 Opnds.push_back(I->getOperand(0));
9346 Opnds.push_back(I->getOperand(1));
9347 // Re-evaluate the number of nodes to be traversed.
9348 e += 2; // 2 more nodes (LHS and RHS) are pushed.
9352 // Quit if a non-EXTRACT_VECTOR_ELT
9353 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
9356 // Quit if without a constant index.
9357 SDValue Idx = I->getOperand(1);
9358 if (!isa<ConstantSDNode>(Idx))
9361 SDValue ExtractedFromVec = I->getOperand(0);
9362 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
9363 if (M == VecInMap.end()) {
9364 VT = ExtractedFromVec.getValueType();
9365 // Quit if not 128/256-bit vector.
9366 if (!VT.is128BitVector() && !VT.is256BitVector())
9368 // Quit if not the same type.
9369 if (VecInMap.begin() != VecInMap.end() &&
9370 VT != VecInMap.begin()->first.getValueType())
9372 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
9374 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
9377 assert((VT.is128BitVector() || VT.is256BitVector()) &&
9378 "Not extracted from 128-/256-bit vector.");
9380 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
9381 SmallVector<SDValue, 8> VecIns;
9383 for (DenseMap<SDValue, unsigned>::const_iterator
9384 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
9385 // Quit if not all elements are used.
9386 if (I->second != FullMask)
9388 VecIns.push_back(I->first);
9391 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
9393 // Cast all vectors into TestVT for PTEST.
9394 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
9395 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
9397 // If more than one full vectors are evaluated, OR them first before PTEST.
9398 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
9399 // Each iteration will OR 2 nodes and append the result until there is only
9400 // 1 node left, i.e. the final OR'd value of all vectors.
9401 SDValue LHS = VecIns[Slot];
9402 SDValue RHS = VecIns[Slot + 1];
9403 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
9406 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
9407 VecIns.back(), VecIns.back());
9410 /// Emit nodes that will be selected as "test Op0,Op0", or something
9412 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
9413 SelectionDAG &DAG) const {
9416 // CF and OF aren't always set the way we want. Determine which
9417 // of these we need.
9418 bool NeedCF = false;
9419 bool NeedOF = false;
9422 case X86::COND_A: case X86::COND_AE:
9423 case X86::COND_B: case X86::COND_BE:
9426 case X86::COND_G: case X86::COND_GE:
9427 case X86::COND_L: case X86::COND_LE:
9428 case X86::COND_O: case X86::COND_NO:
9433 // See if we can use the EFLAGS value from the operand instead of
9434 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
9435 // we prove that the arithmetic won't overflow, we can't use OF or CF.
9436 if (Op.getResNo() != 0 || NeedOF || NeedCF)
9437 // Emit a CMP with 0, which is the TEST pattern.
9438 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
9439 DAG.getConstant(0, Op.getValueType()));
9441 unsigned Opcode = 0;
9442 unsigned NumOperands = 0;
9444 // Truncate operations may prevent the merge of the SETCC instruction
9445 // and the arithmetic instruction before it. Attempt to truncate the operands
9446 // of the arithmetic instruction and use a reduced bit-width instruction.
9447 bool NeedTruncation = false;
9448 SDValue ArithOp = Op;
9449 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
9450 SDValue Arith = Op->getOperand(0);
9451 // Both the trunc and the arithmetic op need to have one user each.
9452 if (Arith->hasOneUse())
9453 switch (Arith.getOpcode()) {
9460 NeedTruncation = true;
9466 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
9467 // which may be the result of a CAST. We use the variable 'Op', which is the
9468 // non-casted variable when we check for possible users.
9469 switch (ArithOp.getOpcode()) {
9471 // Due to an isel shortcoming, be conservative if this add is likely to be
9472 // selected as part of a load-modify-store instruction. When the root node
9473 // in a match is a store, isel doesn't know how to remap non-chain non-flag
9474 // uses of other nodes in the match, such as the ADD in this case. This
9475 // leads to the ADD being left around and reselected, with the result being
9476 // two adds in the output. Alas, even if none our users are stores, that
9477 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
9478 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
9479 // climbing the DAG back to the root, and it doesn't seem to be worth the
9481 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
9482 UE = Op.getNode()->use_end(); UI != UE; ++UI)
9483 if (UI->getOpcode() != ISD::CopyToReg &&
9484 UI->getOpcode() != ISD::SETCC &&
9485 UI->getOpcode() != ISD::STORE)
9488 if (ConstantSDNode *C =
9489 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
9490 // An add of one will be selected as an INC.
9491 if (C->getAPIntValue() == 1) {
9492 Opcode = X86ISD::INC;
9497 // An add of negative one (subtract of one) will be selected as a DEC.
9498 if (C->getAPIntValue().isAllOnesValue()) {
9499 Opcode = X86ISD::DEC;
9505 // Otherwise use a regular EFLAGS-setting add.
9506 Opcode = X86ISD::ADD;
9510 // If the primary and result isn't used, don't bother using X86ISD::AND,
9511 // because a TEST instruction will be better.
9512 bool NonFlagUse = false;
9513 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
9514 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
9516 unsigned UOpNo = UI.getOperandNo();
9517 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
9518 // Look pass truncate.
9519 UOpNo = User->use_begin().getOperandNo();
9520 User = *User->use_begin();
9523 if (User->getOpcode() != ISD::BRCOND &&
9524 User->getOpcode() != ISD::SETCC &&
9525 !(User->getOpcode() == ISD::SELECT && UOpNo == 0)) {
9538 // Due to the ISEL shortcoming noted above, be conservative if this op is
9539 // likely to be selected as part of a load-modify-store instruction.
9540 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
9541 UE = Op.getNode()->use_end(); UI != UE; ++UI)
9542 if (UI->getOpcode() == ISD::STORE)
9545 // Otherwise use a regular EFLAGS-setting instruction.
9546 switch (ArithOp.getOpcode()) {
9547 default: llvm_unreachable("unexpected operator!");
9548 case ISD::SUB: Opcode = X86ISD::SUB; break;
9549 case ISD::XOR: Opcode = X86ISD::XOR; break;
9550 case ISD::AND: Opcode = X86ISD::AND; break;
9552 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
9553 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
9554 if (EFLAGS.getNode())
9557 Opcode = X86ISD::OR;
9571 return SDValue(Op.getNode(), 1);
9577 // If we found that truncation is beneficial, perform the truncation and
9579 if (NeedTruncation) {
9580 EVT VT = Op.getValueType();
9581 SDValue WideVal = Op->getOperand(0);
9582 EVT WideVT = WideVal.getValueType();
9583 unsigned ConvertedOp = 0;
9584 // Use a target machine opcode to prevent further DAGCombine
9585 // optimizations that may separate the arithmetic operations
9586 // from the setcc node.
9587 switch (WideVal.getOpcode()) {
9589 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
9590 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
9591 case ISD::AND: ConvertedOp = X86ISD::AND; break;
9592 case ISD::OR: ConvertedOp = X86ISD::OR; break;
9593 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
9597 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9598 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
9599 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
9600 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
9601 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
9607 // Emit a CMP with 0, which is the TEST pattern.
9608 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
9609 DAG.getConstant(0, Op.getValueType()));
9611 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
9612 SmallVector<SDValue, 4> Ops;
9613 for (unsigned i = 0; i != NumOperands; ++i)
9614 Ops.push_back(Op.getOperand(i));
9616 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
9617 DAG.ReplaceAllUsesWith(Op, New);
9618 return SDValue(New.getNode(), 1);
9621 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
9623 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
9624 SelectionDAG &DAG) const {
9625 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
9626 if (C->getAPIntValue() == 0)
9627 return EmitTest(Op0, X86CC, DAG);
9630 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
9631 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
9632 // Use SUB instead of CMP to enable CSE between SUB and CMP.
9633 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
9634 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
9636 return SDValue(Sub.getNode(), 1);
9638 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
9641 /// Convert a comparison if required by the subtarget.
9642 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
9643 SelectionDAG &DAG) const {
9644 // If the subtarget does not support the FUCOMI instruction, floating-point
9645 // comparisons have to be converted.
9646 if (Subtarget->hasCMov() ||
9647 Cmp.getOpcode() != X86ISD::CMP ||
9648 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
9649 !Cmp.getOperand(1).getValueType().isFloatingPoint())
9652 // The instruction selector will select an FUCOM instruction instead of
9653 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
9654 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
9655 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
9657 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
9658 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
9659 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
9660 DAG.getConstant(8, MVT::i8));
9661 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
9662 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
9665 static bool isAllOnes(SDValue V) {
9666 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
9667 return C && C->isAllOnesValue();
9670 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
9671 /// if it's possible.
9672 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
9673 SDLoc dl, SelectionDAG &DAG) const {
9674 SDValue Op0 = And.getOperand(0);
9675 SDValue Op1 = And.getOperand(1);
9676 if (Op0.getOpcode() == ISD::TRUNCATE)
9677 Op0 = Op0.getOperand(0);
9678 if (Op1.getOpcode() == ISD::TRUNCATE)
9679 Op1 = Op1.getOperand(0);
9682 if (Op1.getOpcode() == ISD::SHL)
9683 std::swap(Op0, Op1);
9684 if (Op0.getOpcode() == ISD::SHL) {
9685 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
9686 if (And00C->getZExtValue() == 1) {
9687 // If we looked past a truncate, check that it's only truncating away
9689 unsigned BitWidth = Op0.getValueSizeInBits();
9690 unsigned AndBitWidth = And.getValueSizeInBits();
9691 if (BitWidth > AndBitWidth) {
9693 DAG.ComputeMaskedBits(Op0, Zeros, Ones);
9694 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
9698 RHS = Op0.getOperand(1);
9700 } else if (Op1.getOpcode() == ISD::Constant) {
9701 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
9702 uint64_t AndRHSVal = AndRHS->getZExtValue();
9703 SDValue AndLHS = Op0;
9705 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
9706 LHS = AndLHS.getOperand(0);
9707 RHS = AndLHS.getOperand(1);
9710 // Use BT if the immediate can't be encoded in a TEST instruction.
9711 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
9713 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
9717 if (LHS.getNode()) {
9718 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
9719 // instruction. Since the shift amount is in-range-or-undefined, we know
9720 // that doing a bittest on the i32 value is ok. We extend to i32 because
9721 // the encoding for the i16 version is larger than the i32 version.
9722 // Also promote i16 to i32 for performance / code size reason.
9723 if (LHS.getValueType() == MVT::i8 ||
9724 LHS.getValueType() == MVT::i16)
9725 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
9727 // If the operand types disagree, extend the shift amount to match. Since
9728 // BT ignores high bits (like shifts) we can use anyextend.
9729 if (LHS.getValueType() != RHS.getValueType())
9730 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
9732 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
9733 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
9734 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9735 DAG.getConstant(Cond, MVT::i8), BT);
9741 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
9743 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
9748 // SSE Condition code mapping:
9757 switch (SetCCOpcode) {
9758 default: llvm_unreachable("Unexpected SETCC condition");
9760 case ISD::SETEQ: SSECC = 0; break;
9762 case ISD::SETGT: Swap = true; // Fallthrough
9764 case ISD::SETOLT: SSECC = 1; break;
9766 case ISD::SETGE: Swap = true; // Fallthrough
9768 case ISD::SETOLE: SSECC = 2; break;
9769 case ISD::SETUO: SSECC = 3; break;
9771 case ISD::SETNE: SSECC = 4; break;
9772 case ISD::SETULE: Swap = true; // Fallthrough
9773 case ISD::SETUGE: SSECC = 5; break;
9774 case ISD::SETULT: Swap = true; // Fallthrough
9775 case ISD::SETUGT: SSECC = 6; break;
9776 case ISD::SETO: SSECC = 7; break;
9778 case ISD::SETONE: SSECC = 8; break;
9781 std::swap(Op0, Op1);
9786 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
9787 // ones, and then concatenate the result back.
9788 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
9789 MVT VT = Op.getSimpleValueType();
9791 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
9792 "Unsupported value type for operation");
9794 unsigned NumElems = VT.getVectorNumElements();
9796 SDValue CC = Op.getOperand(2);
9798 // Extract the LHS vectors
9799 SDValue LHS = Op.getOperand(0);
9800 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
9801 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
9803 // Extract the RHS vectors
9804 SDValue RHS = Op.getOperand(1);
9805 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
9806 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
9808 // Issue the operation on the smaller types and concatenate the result back
9809 MVT EltVT = VT.getVectorElementType();
9810 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
9811 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
9812 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
9813 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
9816 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG) {
9817 SDValue Op0 = Op.getOperand(0);
9818 SDValue Op1 = Op.getOperand(1);
9819 SDValue CC = Op.getOperand(2);
9820 MVT VT = Op.getSimpleValueType();
9822 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 32 &&
9823 Op.getValueType().getScalarType() == MVT::i1 &&
9824 "Cannot set masked compare for this operation");
9826 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
9829 bool Unsigned = false;
9831 switch (SetCCOpcode) {
9832 default: llvm_unreachable("Unexpected SETCC condition");
9833 case ISD::SETNE: SSECC = 4; break;
9834 case ISD::SETEQ: SSECC = 0; break;
9835 case ISD::SETUGT: Unsigned = true;
9836 case ISD::SETGT: SSECC = 6; break; // NLE
9837 case ISD::SETULT: Unsigned = true;
9838 case ISD::SETLT: SSECC = 1; break;
9839 case ISD::SETUGE: Unsigned = true;
9840 case ISD::SETGE: SSECC = 5; break; // NLT
9841 case ISD::SETULE: Unsigned = true;
9842 case ISD::SETLE: SSECC = 2; break;
9844 unsigned Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
9845 return DAG.getNode(Opc, dl, VT, Op0, Op1,
9846 DAG.getConstant(SSECC, MVT::i8));
9850 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
9851 SelectionDAG &DAG) {
9852 SDValue Op0 = Op.getOperand(0);
9853 SDValue Op1 = Op.getOperand(1);
9854 SDValue CC = Op.getOperand(2);
9855 MVT VT = Op.getSimpleValueType();
9856 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
9857 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
9862 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
9863 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
9866 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
9867 unsigned Opc = X86ISD::CMPP;
9868 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
9869 assert(VT.getVectorNumElements() <= 16);
9872 // In the two special cases we can't handle, emit two comparisons.
9875 unsigned CombineOpc;
9876 if (SetCCOpcode == ISD::SETUEQ) {
9877 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
9879 assert(SetCCOpcode == ISD::SETONE);
9880 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
9883 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
9884 DAG.getConstant(CC0, MVT::i8));
9885 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
9886 DAG.getConstant(CC1, MVT::i8));
9887 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
9889 // Handle all other FP comparisons here.
9890 return DAG.getNode(Opc, dl, VT, Op0, Op1,
9891 DAG.getConstant(SSECC, MVT::i8));
9894 // Break 256-bit integer vector compare into smaller ones.
9895 if (VT.is256BitVector() && !Subtarget->hasInt256())
9896 return Lower256IntVSETCC(Op, DAG);
9898 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
9899 EVT OpVT = Op1.getValueType();
9900 if (Subtarget->hasAVX512()) {
9901 if (Op1.getValueType().is512BitVector() ||
9902 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
9903 return LowerIntVSETCC_AVX512(Op, DAG);
9905 // In AVX-512 architecture setcc returns mask with i1 elements,
9906 // But there is no compare instruction for i8 and i16 elements.
9907 // We are not talking about 512-bit operands in this case, these
9908 // types are illegal.
9910 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
9911 OpVT.getVectorElementType().getSizeInBits() >= 8))
9912 return DAG.getNode(ISD::TRUNCATE, dl, VT,
9913 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
9916 // We are handling one of the integer comparisons here. Since SSE only has
9917 // GT and EQ comparisons for integer, swapping operands and multiple
9918 // operations may be required for some comparisons.
9920 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
9922 switch (SetCCOpcode) {
9923 default: llvm_unreachable("Unexpected SETCC condition");
9924 case ISD::SETNE: Invert = true;
9925 case ISD::SETEQ: Opc = MaskResult? X86ISD::PCMPEQM: X86ISD::PCMPEQ; break;
9926 case ISD::SETLT: Swap = true;
9927 case ISD::SETGT: Opc = MaskResult? X86ISD::PCMPGTM: X86ISD::PCMPGT; break;
9928 case ISD::SETGE: Swap = true;
9929 case ISD::SETLE: Opc = MaskResult? X86ISD::PCMPGTM: X86ISD::PCMPGT;
9930 Invert = true; break;
9931 case ISD::SETULT: Swap = true;
9932 case ISD::SETUGT: Opc = MaskResult? X86ISD::PCMPGTM: X86ISD::PCMPGT;
9933 FlipSigns = true; break;
9934 case ISD::SETUGE: Swap = true;
9935 case ISD::SETULE: Opc = MaskResult? X86ISD::PCMPGTM: X86ISD::PCMPGT;
9936 FlipSigns = true; Invert = true; break;
9939 // Special case: Use min/max operations for SETULE/SETUGE
9940 MVT VET = VT.getVectorElementType();
9942 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
9943 || (Subtarget->hasSSE2() && (VET == MVT::i8));
9946 switch (SetCCOpcode) {
9948 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
9949 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
9952 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
9956 std::swap(Op0, Op1);
9958 // Check that the operation in question is available (most are plain SSE2,
9959 // but PCMPGTQ and PCMPEQQ have different requirements).
9960 if (VT == MVT::v2i64) {
9961 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
9962 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
9964 // First cast everything to the right type.
9965 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
9966 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
9968 // Since SSE has no unsigned integer comparisons, we need to flip the sign
9969 // bits of the inputs before performing those operations. The lower
9970 // compare is always unsigned.
9973 SB = DAG.getConstant(0x80000000U, MVT::v4i32);
9975 SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
9976 SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
9977 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
9978 Sign, Zero, Sign, Zero);
9980 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
9981 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
9983 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
9984 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
9985 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
9987 // Create masks for only the low parts/high parts of the 64 bit integers.
9988 static const int MaskHi[] = { 1, 1, 3, 3 };
9989 static const int MaskLo[] = { 0, 0, 2, 2 };
9990 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
9991 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
9992 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
9994 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
9995 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
9998 Result = DAG.getNOT(dl, Result, MVT::v4i32);
10000 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
10003 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
10004 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
10005 // pcmpeqd + pshufd + pand.
10006 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
10008 // First cast everything to the right type.
10009 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
10010 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
10013 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
10015 // Make sure the lower and upper halves are both all-ones.
10016 static const int Mask[] = { 1, 0, 3, 2 };
10017 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
10018 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
10021 Result = DAG.getNOT(dl, Result, MVT::v4i32);
10023 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
10027 // Since SSE has no unsigned integer comparisons, we need to flip the sign
10028 // bits of the inputs before performing those operations.
10030 EVT EltVT = VT.getVectorElementType();
10031 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
10032 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
10033 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
10036 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
10038 // If the logical-not of the result is required, perform that now.
10040 Result = DAG.getNOT(dl, Result, VT);
10043 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
10048 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
10050 MVT VT = Op.getSimpleValueType();
10052 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
10054 assert(VT == MVT::i8 && "SetCC type must be 8-bit integer");
10055 SDValue Op0 = Op.getOperand(0);
10056 SDValue Op1 = Op.getOperand(1);
10058 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
10060 // Optimize to BT if possible.
10061 // Lower (X & (1 << N)) == 0 to BT(X, N).
10062 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
10063 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
10064 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
10065 Op1.getOpcode() == ISD::Constant &&
10066 cast<ConstantSDNode>(Op1)->isNullValue() &&
10067 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
10068 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
10069 if (NewSetCC.getNode())
10073 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
10075 if (Op1.getOpcode() == ISD::Constant &&
10076 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
10077 cast<ConstantSDNode>(Op1)->isNullValue()) &&
10078 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
10080 // If the input is a setcc, then reuse the input setcc or use a new one with
10081 // the inverted condition.
10082 if (Op0.getOpcode() == X86ISD::SETCC) {
10083 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
10084 bool Invert = (CC == ISD::SETNE) ^
10085 cast<ConstantSDNode>(Op1)->isNullValue();
10086 if (!Invert) return Op0;
10088 CCode = X86::GetOppositeBranchCondition(CCode);
10089 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
10090 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1));
10094 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
10095 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
10096 if (X86CC == X86::COND_INVALID)
10099 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG);
10100 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
10101 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
10102 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
10105 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
10106 static bool isX86LogicalCmp(SDValue Op) {
10107 unsigned Opc = Op.getNode()->getOpcode();
10108 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
10109 Opc == X86ISD::SAHF)
10111 if (Op.getResNo() == 1 &&
10112 (Opc == X86ISD::ADD ||
10113 Opc == X86ISD::SUB ||
10114 Opc == X86ISD::ADC ||
10115 Opc == X86ISD::SBB ||
10116 Opc == X86ISD::SMUL ||
10117 Opc == X86ISD::UMUL ||
10118 Opc == X86ISD::INC ||
10119 Opc == X86ISD::DEC ||
10120 Opc == X86ISD::OR ||
10121 Opc == X86ISD::XOR ||
10122 Opc == X86ISD::AND))
10125 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
10131 static bool isZero(SDValue V) {
10132 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
10133 return C && C->isNullValue();
10136 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
10137 if (V.getOpcode() != ISD::TRUNCATE)
10140 SDValue VOp0 = V.getOperand(0);
10141 unsigned InBits = VOp0.getValueSizeInBits();
10142 unsigned Bits = V.getValueSizeInBits();
10143 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
10146 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
10147 bool addTest = true;
10148 SDValue Cond = Op.getOperand(0);
10149 SDValue Op1 = Op.getOperand(1);
10150 SDValue Op2 = Op.getOperand(2);
10152 EVT VT = Op1.getValueType();
10155 // Lower fp selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
10156 // are available. Otherwise fp cmovs get lowered into a less efficient branch
10157 // sequence later on.
10158 if (Cond.getOpcode() == ISD::SETCC &&
10159 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
10160 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
10161 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
10162 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
10163 int SSECC = translateX86FSETCC(
10164 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
10167 unsigned Opcode = VT == MVT::f32 ? X86ISD::FSETCCss : X86ISD::FSETCCsd;
10168 SDValue Cmp = DAG.getNode(Opcode, DL, VT, CondOp0, CondOp1,
10169 DAG.getConstant(SSECC, MVT::i8));
10170 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
10171 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
10172 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
10176 if (Cond.getOpcode() == ISD::SETCC) {
10177 SDValue NewCond = LowerSETCC(Cond, DAG);
10178 if (NewCond.getNode())
10182 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
10183 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
10184 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
10185 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
10186 if (Cond.getOpcode() == X86ISD::SETCC &&
10187 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
10188 isZero(Cond.getOperand(1).getOperand(1))) {
10189 SDValue Cmp = Cond.getOperand(1);
10191 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
10193 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
10194 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
10195 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
10197 SDValue CmpOp0 = Cmp.getOperand(0);
10198 // Apply further optimizations for special cases
10199 // (select (x != 0), -1, 0) -> neg & sbb
10200 // (select (x == 0), 0, -1) -> neg & sbb
10201 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
10202 if (YC->isNullValue() &&
10203 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
10204 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
10205 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
10206 DAG.getConstant(0, CmpOp0.getValueType()),
10208 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
10209 DAG.getConstant(X86::COND_B, MVT::i8),
10210 SDValue(Neg.getNode(), 1));
10214 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
10215 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
10216 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
10218 SDValue Res = // Res = 0 or -1.
10219 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
10220 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
10222 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
10223 Res = DAG.getNOT(DL, Res, Res.getValueType());
10225 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
10226 if (N2C == 0 || !N2C->isNullValue())
10227 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
10232 // Look past (and (setcc_carry (cmp ...)), 1).
10233 if (Cond.getOpcode() == ISD::AND &&
10234 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
10235 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
10236 if (C && C->getAPIntValue() == 1)
10237 Cond = Cond.getOperand(0);
10240 // If condition flag is set by a X86ISD::CMP, then use it as the condition
10241 // setting operand in place of the X86ISD::SETCC.
10242 unsigned CondOpcode = Cond.getOpcode();
10243 if (CondOpcode == X86ISD::SETCC ||
10244 CondOpcode == X86ISD::SETCC_CARRY) {
10245 CC = Cond.getOperand(0);
10247 SDValue Cmp = Cond.getOperand(1);
10248 unsigned Opc = Cmp.getOpcode();
10249 MVT VT = Op.getSimpleValueType();
10251 bool IllegalFPCMov = false;
10252 if (VT.isFloatingPoint() && !VT.isVector() &&
10253 !isScalarFPTypeInSSEReg(VT)) // FPStack?
10254 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
10256 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
10257 Opc == X86ISD::BT) { // FIXME
10261 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
10262 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
10263 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
10264 Cond.getOperand(0).getValueType() != MVT::i8)) {
10265 SDValue LHS = Cond.getOperand(0);
10266 SDValue RHS = Cond.getOperand(1);
10267 unsigned X86Opcode;
10270 switch (CondOpcode) {
10271 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
10272 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
10273 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
10274 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
10275 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
10276 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
10277 default: llvm_unreachable("unexpected overflowing operator");
10279 if (CondOpcode == ISD::UMULO)
10280 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
10283 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
10285 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
10287 if (CondOpcode == ISD::UMULO)
10288 Cond = X86Op.getValue(2);
10290 Cond = X86Op.getValue(1);
10292 CC = DAG.getConstant(X86Cond, MVT::i8);
10297 // Look pass the truncate if the high bits are known zero.
10298 if (isTruncWithZeroHighBitsInput(Cond, DAG))
10299 Cond = Cond.getOperand(0);
10301 // We know the result of AND is compared against zero. Try to match
10303 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
10304 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
10305 if (NewSetCC.getNode()) {
10306 CC = NewSetCC.getOperand(0);
10307 Cond = NewSetCC.getOperand(1);
10314 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
10315 Cond = EmitTest(Cond, X86::COND_NE, DAG);
10318 // a < b ? -1 : 0 -> RES = ~setcc_carry
10319 // a < b ? 0 : -1 -> RES = setcc_carry
10320 // a >= b ? -1 : 0 -> RES = setcc_carry
10321 // a >= b ? 0 : -1 -> RES = ~setcc_carry
10322 if (Cond.getOpcode() == X86ISD::SUB) {
10323 Cond = ConvertCmpIfNecessary(Cond, DAG);
10324 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
10326 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
10327 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
10328 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
10329 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
10330 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
10331 return DAG.getNOT(DL, Res, Res.getValueType());
10336 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
10337 // widen the cmov and push the truncate through. This avoids introducing a new
10338 // branch during isel and doesn't add any extensions.
10339 if (Op.getValueType() == MVT::i8 &&
10340 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
10341 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
10342 if (T1.getValueType() == T2.getValueType() &&
10343 // Blacklist CopyFromReg to avoid partial register stalls.
10344 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
10345 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
10346 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
10347 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
10351 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
10352 // condition is true.
10353 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
10354 SDValue Ops[] = { Op2, Op1, CC, Cond };
10355 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops));
10358 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, SelectionDAG &DAG) {
10359 MVT VT = Op->getSimpleValueType(0);
10360 SDValue In = Op->getOperand(0);
10361 MVT InVT = In.getSimpleValueType();
10364 unsigned int NumElts = VT.getVectorNumElements();
10365 if (NumElts != 8 && NumElts != 16)
10368 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
10369 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
10371 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
10372 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
10374 MVT ExtVT = (NumElts == 8) ? MVT::v8i64 : MVT::v16i32;
10375 Constant *C = ConstantInt::get(*DAG.getContext(),
10376 APInt::getAllOnesValue(ExtVT.getScalarType().getSizeInBits()));
10378 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
10379 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
10380 SDValue Ld = DAG.getLoad(ExtVT.getScalarType(), dl, DAG.getEntryNode(), CP,
10381 MachinePointerInfo::getConstantPool(),
10382 false, false, false, Alignment);
10383 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, dl, ExtVT, In, Ld);
10384 if (VT.is512BitVector())
10386 return DAG.getNode(X86ISD::VTRUNC, dl, VT, Brcst);
10389 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
10390 SelectionDAG &DAG) {
10391 MVT VT = Op->getSimpleValueType(0);
10392 SDValue In = Op->getOperand(0);
10393 MVT InVT = In.getSimpleValueType();
10396 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
10397 return LowerSIGN_EXTEND_AVX512(Op, DAG);
10399 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
10400 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
10401 (VT != MVT::v16i16 || InVT != MVT::v16i8))
10404 if (Subtarget->hasInt256())
10405 return DAG.getNode(X86ISD::VSEXT_MOVL, dl, VT, In);
10407 // Optimize vectors in AVX mode
10408 // Sign extend v8i16 to v8i32 and
10411 // Divide input vector into two parts
10412 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
10413 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
10414 // concat the vectors to original VT
10416 unsigned NumElems = InVT.getVectorNumElements();
10417 SDValue Undef = DAG.getUNDEF(InVT);
10419 SmallVector<int,8> ShufMask1(NumElems, -1);
10420 for (unsigned i = 0; i != NumElems/2; ++i)
10423 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
10425 SmallVector<int,8> ShufMask2(NumElems, -1);
10426 for (unsigned i = 0; i != NumElems/2; ++i)
10427 ShufMask2[i] = i + NumElems/2;
10429 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
10431 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
10432 VT.getVectorNumElements()/2);
10434 OpLo = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpLo);
10435 OpHi = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpHi);
10437 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
10440 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
10441 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
10442 // from the AND / OR.
10443 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
10444 Opc = Op.getOpcode();
10445 if (Opc != ISD::OR && Opc != ISD::AND)
10447 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
10448 Op.getOperand(0).hasOneUse() &&
10449 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
10450 Op.getOperand(1).hasOneUse());
10453 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
10454 // 1 and that the SETCC node has a single use.
10455 static bool isXor1OfSetCC(SDValue Op) {
10456 if (Op.getOpcode() != ISD::XOR)
10458 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
10459 if (N1C && N1C->getAPIntValue() == 1) {
10460 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
10461 Op.getOperand(0).hasOneUse();
10466 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
10467 bool addTest = true;
10468 SDValue Chain = Op.getOperand(0);
10469 SDValue Cond = Op.getOperand(1);
10470 SDValue Dest = Op.getOperand(2);
10473 bool Inverted = false;
10475 if (Cond.getOpcode() == ISD::SETCC) {
10476 // Check for setcc([su]{add,sub,mul}o == 0).
10477 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
10478 isa<ConstantSDNode>(Cond.getOperand(1)) &&
10479 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
10480 Cond.getOperand(0).getResNo() == 1 &&
10481 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
10482 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
10483 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
10484 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
10485 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
10486 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
10488 Cond = Cond.getOperand(0);
10490 SDValue NewCond = LowerSETCC(Cond, DAG);
10491 if (NewCond.getNode())
10496 // FIXME: LowerXALUO doesn't handle these!!
10497 else if (Cond.getOpcode() == X86ISD::ADD ||
10498 Cond.getOpcode() == X86ISD::SUB ||
10499 Cond.getOpcode() == X86ISD::SMUL ||
10500 Cond.getOpcode() == X86ISD::UMUL)
10501 Cond = LowerXALUO(Cond, DAG);
10504 // Look pass (and (setcc_carry (cmp ...)), 1).
10505 if (Cond.getOpcode() == ISD::AND &&
10506 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
10507 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
10508 if (C && C->getAPIntValue() == 1)
10509 Cond = Cond.getOperand(0);
10512 // If condition flag is set by a X86ISD::CMP, then use it as the condition
10513 // setting operand in place of the X86ISD::SETCC.
10514 unsigned CondOpcode = Cond.getOpcode();
10515 if (CondOpcode == X86ISD::SETCC ||
10516 CondOpcode == X86ISD::SETCC_CARRY) {
10517 CC = Cond.getOperand(0);
10519 SDValue Cmp = Cond.getOperand(1);
10520 unsigned Opc = Cmp.getOpcode();
10521 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
10522 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
10526 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
10530 // These can only come from an arithmetic instruction with overflow,
10531 // e.g. SADDO, UADDO.
10532 Cond = Cond.getNode()->getOperand(1);
10538 CondOpcode = Cond.getOpcode();
10539 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
10540 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
10541 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
10542 Cond.getOperand(0).getValueType() != MVT::i8)) {
10543 SDValue LHS = Cond.getOperand(0);
10544 SDValue RHS = Cond.getOperand(1);
10545 unsigned X86Opcode;
10548 switch (CondOpcode) {
10549 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
10550 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
10551 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
10552 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
10553 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
10554 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
10555 default: llvm_unreachable("unexpected overflowing operator");
10558 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
10559 if (CondOpcode == ISD::UMULO)
10560 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
10563 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
10565 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
10567 if (CondOpcode == ISD::UMULO)
10568 Cond = X86Op.getValue(2);
10570 Cond = X86Op.getValue(1);
10572 CC = DAG.getConstant(X86Cond, MVT::i8);
10576 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
10577 SDValue Cmp = Cond.getOperand(0).getOperand(1);
10578 if (CondOpc == ISD::OR) {
10579 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
10580 // two branches instead of an explicit OR instruction with a
10582 if (Cmp == Cond.getOperand(1).getOperand(1) &&
10583 isX86LogicalCmp(Cmp)) {
10584 CC = Cond.getOperand(0).getOperand(0);
10585 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10586 Chain, Dest, CC, Cmp);
10587 CC = Cond.getOperand(1).getOperand(0);
10591 } else { // ISD::AND
10592 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
10593 // two branches instead of an explicit AND instruction with a
10594 // separate test. However, we only do this if this block doesn't
10595 // have a fall-through edge, because this requires an explicit
10596 // jmp when the condition is false.
10597 if (Cmp == Cond.getOperand(1).getOperand(1) &&
10598 isX86LogicalCmp(Cmp) &&
10599 Op.getNode()->hasOneUse()) {
10600 X86::CondCode CCode =
10601 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
10602 CCode = X86::GetOppositeBranchCondition(CCode);
10603 CC = DAG.getConstant(CCode, MVT::i8);
10604 SDNode *User = *Op.getNode()->use_begin();
10605 // Look for an unconditional branch following this conditional branch.
10606 // We need this because we need to reverse the successors in order
10607 // to implement FCMP_OEQ.
10608 if (User->getOpcode() == ISD::BR) {
10609 SDValue FalseBB = User->getOperand(1);
10611 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
10612 assert(NewBR == User);
10616 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10617 Chain, Dest, CC, Cmp);
10618 X86::CondCode CCode =
10619 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
10620 CCode = X86::GetOppositeBranchCondition(CCode);
10621 CC = DAG.getConstant(CCode, MVT::i8);
10627 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
10628 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
10629 // It should be transformed during dag combiner except when the condition
10630 // is set by a arithmetics with overflow node.
10631 X86::CondCode CCode =
10632 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
10633 CCode = X86::GetOppositeBranchCondition(CCode);
10634 CC = DAG.getConstant(CCode, MVT::i8);
10635 Cond = Cond.getOperand(0).getOperand(1);
10637 } else if (Cond.getOpcode() == ISD::SETCC &&
10638 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
10639 // For FCMP_OEQ, we can emit
10640 // two branches instead of an explicit AND instruction with a
10641 // separate test. However, we only do this if this block doesn't
10642 // have a fall-through edge, because this requires an explicit
10643 // jmp when the condition is false.
10644 if (Op.getNode()->hasOneUse()) {
10645 SDNode *User = *Op.getNode()->use_begin();
10646 // Look for an unconditional branch following this conditional branch.
10647 // We need this because we need to reverse the successors in order
10648 // to implement FCMP_OEQ.
10649 if (User->getOpcode() == ISD::BR) {
10650 SDValue FalseBB = User->getOperand(1);
10652 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
10653 assert(NewBR == User);
10657 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
10658 Cond.getOperand(0), Cond.getOperand(1));
10659 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
10660 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
10661 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10662 Chain, Dest, CC, Cmp);
10663 CC = DAG.getConstant(X86::COND_P, MVT::i8);
10668 } else if (Cond.getOpcode() == ISD::SETCC &&
10669 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
10670 // For FCMP_UNE, we can emit
10671 // two branches instead of an explicit AND instruction with a
10672 // separate test. However, we only do this if this block doesn't
10673 // have a fall-through edge, because this requires an explicit
10674 // jmp when the condition is false.
10675 if (Op.getNode()->hasOneUse()) {
10676 SDNode *User = *Op.getNode()->use_begin();
10677 // Look for an unconditional branch following this conditional branch.
10678 // We need this because we need to reverse the successors in order
10679 // to implement FCMP_UNE.
10680 if (User->getOpcode() == ISD::BR) {
10681 SDValue FalseBB = User->getOperand(1);
10683 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
10684 assert(NewBR == User);
10687 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
10688 Cond.getOperand(0), Cond.getOperand(1));
10689 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
10690 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
10691 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10692 Chain, Dest, CC, Cmp);
10693 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
10703 // Look pass the truncate if the high bits are known zero.
10704 if (isTruncWithZeroHighBitsInput(Cond, DAG))
10705 Cond = Cond.getOperand(0);
10707 // We know the result of AND is compared against zero. Try to match
10709 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
10710 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
10711 if (NewSetCC.getNode()) {
10712 CC = NewSetCC.getOperand(0);
10713 Cond = NewSetCC.getOperand(1);
10720 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
10721 Cond = EmitTest(Cond, X86::COND_NE, DAG);
10723 Cond = ConvertCmpIfNecessary(Cond, DAG);
10724 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10725 Chain, Dest, CC, Cond);
10728 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
10729 // Calls to _alloca is needed to probe the stack when allocating more than 4k
10730 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
10731 // that the guard pages used by the OS virtual memory manager are allocated in
10732 // correct sequence.
10734 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
10735 SelectionDAG &DAG) const {
10736 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows() ||
10737 getTargetMachine().Options.EnableSegmentedStacks) &&
10738 "This should be used only on Windows targets or when segmented stacks "
10740 assert(!Subtarget->isTargetEnvMacho() && "Not implemented");
10744 SDValue Chain = Op.getOperand(0);
10745 SDValue Size = Op.getOperand(1);
10746 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
10747 EVT VT = Op.getNode()->getValueType(0);
10749 bool Is64Bit = Subtarget->is64Bit();
10750 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32;
10752 if (getTargetMachine().Options.EnableSegmentedStacks) {
10753 MachineFunction &MF = DAG.getMachineFunction();
10754 MachineRegisterInfo &MRI = MF.getRegInfo();
10757 // The 64 bit implementation of segmented stacks needs to clobber both r10
10758 // r11. This makes it impossible to use it along with nested parameters.
10759 const Function *F = MF.getFunction();
10761 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
10763 if (I->hasNestAttr())
10764 report_fatal_error("Cannot use segmented stacks with functions that "
10765 "have nested arguments.");
10768 const TargetRegisterClass *AddrRegClass =
10769 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32);
10770 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
10771 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
10772 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
10773 DAG.getRegister(Vreg, SPTy));
10774 SDValue Ops1[2] = { Value, Chain };
10775 return DAG.getMergeValues(Ops1, 2, dl);
10778 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
10780 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
10781 Flag = Chain.getValue(1);
10782 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
10784 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
10786 const X86RegisterInfo *RegInfo =
10787 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
10788 unsigned SPReg = RegInfo->getStackRegister();
10789 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
10790 Chain = SP.getValue(1);
10793 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
10794 DAG.getConstant(-(uint64_t)Align, VT));
10795 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
10798 SDValue Ops1[2] = { SP, Chain };
10799 return DAG.getMergeValues(Ops1, 2, dl);
10803 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
10804 MachineFunction &MF = DAG.getMachineFunction();
10805 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
10807 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
10810 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
10811 // vastart just stores the address of the VarArgsFrameIndex slot into the
10812 // memory location argument.
10813 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
10815 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
10816 MachinePointerInfo(SV), false, false, 0);
10820 // gp_offset (0 - 6 * 8)
10821 // fp_offset (48 - 48 + 8 * 16)
10822 // overflow_arg_area (point to parameters coming in memory).
10824 SmallVector<SDValue, 8> MemOps;
10825 SDValue FIN = Op.getOperand(1);
10827 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
10828 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
10830 FIN, MachinePointerInfo(SV), false, false, 0);
10831 MemOps.push_back(Store);
10834 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10835 FIN, DAG.getIntPtrConstant(4));
10836 Store = DAG.getStore(Op.getOperand(0), DL,
10837 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
10839 FIN, MachinePointerInfo(SV, 4), false, false, 0);
10840 MemOps.push_back(Store);
10842 // Store ptr to overflow_arg_area
10843 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10844 FIN, DAG.getIntPtrConstant(4));
10845 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
10847 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
10848 MachinePointerInfo(SV, 8),
10850 MemOps.push_back(Store);
10852 // Store ptr to reg_save_area.
10853 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10854 FIN, DAG.getIntPtrConstant(8));
10855 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
10857 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
10858 MachinePointerInfo(SV, 16), false, false, 0);
10859 MemOps.push_back(Store);
10860 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
10861 &MemOps[0], MemOps.size());
10864 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
10865 assert(Subtarget->is64Bit() &&
10866 "LowerVAARG only handles 64-bit va_arg!");
10867 assert((Subtarget->isTargetLinux() ||
10868 Subtarget->isTargetDarwin()) &&
10869 "Unhandled target in LowerVAARG");
10870 assert(Op.getNode()->getNumOperands() == 4);
10871 SDValue Chain = Op.getOperand(0);
10872 SDValue SrcPtr = Op.getOperand(1);
10873 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
10874 unsigned Align = Op.getConstantOperandVal(3);
10877 EVT ArgVT = Op.getNode()->getValueType(0);
10878 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
10879 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
10882 // Decide which area this value should be read from.
10883 // TODO: Implement the AMD64 ABI in its entirety. This simple
10884 // selection mechanism works only for the basic types.
10885 if (ArgVT == MVT::f80) {
10886 llvm_unreachable("va_arg for f80 not yet implemented");
10887 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
10888 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
10889 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
10890 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
10892 llvm_unreachable("Unhandled argument type in LowerVAARG");
10895 if (ArgMode == 2) {
10896 // Sanity Check: Make sure using fp_offset makes sense.
10897 assert(!getTargetMachine().Options.UseSoftFloat &&
10898 !(DAG.getMachineFunction()
10899 .getFunction()->getAttributes()
10900 .hasAttribute(AttributeSet::FunctionIndex,
10901 Attribute::NoImplicitFloat)) &&
10902 Subtarget->hasSSE1());
10905 // Insert VAARG_64 node into the DAG
10906 // VAARG_64 returns two values: Variable Argument Address, Chain
10907 SmallVector<SDValue, 11> InstOps;
10908 InstOps.push_back(Chain);
10909 InstOps.push_back(SrcPtr);
10910 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
10911 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
10912 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
10913 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
10914 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
10915 VTs, &InstOps[0], InstOps.size(),
10917 MachinePointerInfo(SV),
10919 /*Volatile=*/false,
10921 /*WriteMem=*/true);
10922 Chain = VAARG.getValue(1);
10924 // Load the next argument and return it
10925 return DAG.getLoad(ArgVT, dl,
10928 MachinePointerInfo(),
10929 false, false, false, 0);
10932 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
10933 SelectionDAG &DAG) {
10934 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
10935 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
10936 SDValue Chain = Op.getOperand(0);
10937 SDValue DstPtr = Op.getOperand(1);
10938 SDValue SrcPtr = Op.getOperand(2);
10939 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
10940 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
10943 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
10944 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
10946 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
10949 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
10950 // amount is a constant. Takes immediate version of shift as input.
10951 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, EVT VT,
10952 SDValue SrcOp, uint64_t ShiftAmt,
10953 SelectionDAG &DAG) {
10955 // Check for ShiftAmt >= element width
10956 if (ShiftAmt >= VT.getVectorElementType().getSizeInBits()) {
10957 if (Opc == X86ISD::VSRAI)
10958 ShiftAmt = VT.getVectorElementType().getSizeInBits() - 1;
10960 return DAG.getConstant(0, VT);
10963 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
10964 && "Unknown target vector shift-by-constant node");
10966 return DAG.getNode(Opc, dl, VT, SrcOp, DAG.getConstant(ShiftAmt, MVT::i8));
10969 // getTargetVShiftNode - Handle vector element shifts where the shift amount
10970 // may or may not be a constant. Takes immediate version of shift as input.
10971 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, EVT VT,
10972 SDValue SrcOp, SDValue ShAmt,
10973 SelectionDAG &DAG) {
10974 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
10976 // Catch shift-by-constant.
10977 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
10978 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
10979 CShAmt->getZExtValue(), DAG);
10981 // Change opcode to non-immediate version
10983 default: llvm_unreachable("Unknown target vector shift node");
10984 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
10985 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
10986 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
10989 // Need to build a vector containing shift amount
10990 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
10993 ShOps[1] = DAG.getConstant(0, MVT::i32);
10994 ShOps[2] = ShOps[3] = DAG.getUNDEF(MVT::i32);
10995 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, &ShOps[0], 4);
10997 // The return type has to be a 128-bit type with the same element
10998 // type as the input type.
10999 MVT EltVT = VT.getVectorElementType().getSimpleVT();
11000 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
11002 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
11003 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
11006 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
11008 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
11010 default: return SDValue(); // Don't custom lower most intrinsics.
11011 // Comparison intrinsics.
11012 case Intrinsic::x86_sse_comieq_ss:
11013 case Intrinsic::x86_sse_comilt_ss:
11014 case Intrinsic::x86_sse_comile_ss:
11015 case Intrinsic::x86_sse_comigt_ss:
11016 case Intrinsic::x86_sse_comige_ss:
11017 case Intrinsic::x86_sse_comineq_ss:
11018 case Intrinsic::x86_sse_ucomieq_ss:
11019 case Intrinsic::x86_sse_ucomilt_ss:
11020 case Intrinsic::x86_sse_ucomile_ss:
11021 case Intrinsic::x86_sse_ucomigt_ss:
11022 case Intrinsic::x86_sse_ucomige_ss:
11023 case Intrinsic::x86_sse_ucomineq_ss:
11024 case Intrinsic::x86_sse2_comieq_sd:
11025 case Intrinsic::x86_sse2_comilt_sd:
11026 case Intrinsic::x86_sse2_comile_sd:
11027 case Intrinsic::x86_sse2_comigt_sd:
11028 case Intrinsic::x86_sse2_comige_sd:
11029 case Intrinsic::x86_sse2_comineq_sd:
11030 case Intrinsic::x86_sse2_ucomieq_sd:
11031 case Intrinsic::x86_sse2_ucomilt_sd:
11032 case Intrinsic::x86_sse2_ucomile_sd:
11033 case Intrinsic::x86_sse2_ucomigt_sd:
11034 case Intrinsic::x86_sse2_ucomige_sd:
11035 case Intrinsic::x86_sse2_ucomineq_sd: {
11039 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11040 case Intrinsic::x86_sse_comieq_ss:
11041 case Intrinsic::x86_sse2_comieq_sd:
11042 Opc = X86ISD::COMI;
11045 case Intrinsic::x86_sse_comilt_ss:
11046 case Intrinsic::x86_sse2_comilt_sd:
11047 Opc = X86ISD::COMI;
11050 case Intrinsic::x86_sse_comile_ss:
11051 case Intrinsic::x86_sse2_comile_sd:
11052 Opc = X86ISD::COMI;
11055 case Intrinsic::x86_sse_comigt_ss:
11056 case Intrinsic::x86_sse2_comigt_sd:
11057 Opc = X86ISD::COMI;
11060 case Intrinsic::x86_sse_comige_ss:
11061 case Intrinsic::x86_sse2_comige_sd:
11062 Opc = X86ISD::COMI;
11065 case Intrinsic::x86_sse_comineq_ss:
11066 case Intrinsic::x86_sse2_comineq_sd:
11067 Opc = X86ISD::COMI;
11070 case Intrinsic::x86_sse_ucomieq_ss:
11071 case Intrinsic::x86_sse2_ucomieq_sd:
11072 Opc = X86ISD::UCOMI;
11075 case Intrinsic::x86_sse_ucomilt_ss:
11076 case Intrinsic::x86_sse2_ucomilt_sd:
11077 Opc = X86ISD::UCOMI;
11080 case Intrinsic::x86_sse_ucomile_ss:
11081 case Intrinsic::x86_sse2_ucomile_sd:
11082 Opc = X86ISD::UCOMI;
11085 case Intrinsic::x86_sse_ucomigt_ss:
11086 case Intrinsic::x86_sse2_ucomigt_sd:
11087 Opc = X86ISD::UCOMI;
11090 case Intrinsic::x86_sse_ucomige_ss:
11091 case Intrinsic::x86_sse2_ucomige_sd:
11092 Opc = X86ISD::UCOMI;
11095 case Intrinsic::x86_sse_ucomineq_ss:
11096 case Intrinsic::x86_sse2_ucomineq_sd:
11097 Opc = X86ISD::UCOMI;
11102 SDValue LHS = Op.getOperand(1);
11103 SDValue RHS = Op.getOperand(2);
11104 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
11105 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
11106 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
11107 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
11108 DAG.getConstant(X86CC, MVT::i8), Cond);
11109 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
11112 // Arithmetic intrinsics.
11113 case Intrinsic::x86_sse2_pmulu_dq:
11114 case Intrinsic::x86_avx2_pmulu_dq:
11115 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
11116 Op.getOperand(1), Op.getOperand(2));
11118 // SSE2/AVX2 sub with unsigned saturation intrinsics
11119 case Intrinsic::x86_sse2_psubus_b:
11120 case Intrinsic::x86_sse2_psubus_w:
11121 case Intrinsic::x86_avx2_psubus_b:
11122 case Intrinsic::x86_avx2_psubus_w:
11123 return DAG.getNode(X86ISD::SUBUS, dl, Op.getValueType(),
11124 Op.getOperand(1), Op.getOperand(2));
11126 // SSE3/AVX horizontal add/sub intrinsics
11127 case Intrinsic::x86_sse3_hadd_ps:
11128 case Intrinsic::x86_sse3_hadd_pd:
11129 case Intrinsic::x86_avx_hadd_ps_256:
11130 case Intrinsic::x86_avx_hadd_pd_256:
11131 case Intrinsic::x86_sse3_hsub_ps:
11132 case Intrinsic::x86_sse3_hsub_pd:
11133 case Intrinsic::x86_avx_hsub_ps_256:
11134 case Intrinsic::x86_avx_hsub_pd_256:
11135 case Intrinsic::x86_ssse3_phadd_w_128:
11136 case Intrinsic::x86_ssse3_phadd_d_128:
11137 case Intrinsic::x86_avx2_phadd_w:
11138 case Intrinsic::x86_avx2_phadd_d:
11139 case Intrinsic::x86_ssse3_phsub_w_128:
11140 case Intrinsic::x86_ssse3_phsub_d_128:
11141 case Intrinsic::x86_avx2_phsub_w:
11142 case Intrinsic::x86_avx2_phsub_d: {
11145 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11146 case Intrinsic::x86_sse3_hadd_ps:
11147 case Intrinsic::x86_sse3_hadd_pd:
11148 case Intrinsic::x86_avx_hadd_ps_256:
11149 case Intrinsic::x86_avx_hadd_pd_256:
11150 Opcode = X86ISD::FHADD;
11152 case Intrinsic::x86_sse3_hsub_ps:
11153 case Intrinsic::x86_sse3_hsub_pd:
11154 case Intrinsic::x86_avx_hsub_ps_256:
11155 case Intrinsic::x86_avx_hsub_pd_256:
11156 Opcode = X86ISD::FHSUB;
11158 case Intrinsic::x86_ssse3_phadd_w_128:
11159 case Intrinsic::x86_ssse3_phadd_d_128:
11160 case Intrinsic::x86_avx2_phadd_w:
11161 case Intrinsic::x86_avx2_phadd_d:
11162 Opcode = X86ISD::HADD;
11164 case Intrinsic::x86_ssse3_phsub_w_128:
11165 case Intrinsic::x86_ssse3_phsub_d_128:
11166 case Intrinsic::x86_avx2_phsub_w:
11167 case Intrinsic::x86_avx2_phsub_d:
11168 Opcode = X86ISD::HSUB;
11171 return DAG.getNode(Opcode, dl, Op.getValueType(),
11172 Op.getOperand(1), Op.getOperand(2));
11175 // SSE2/SSE41/AVX2 integer max/min intrinsics.
11176 case Intrinsic::x86_sse2_pmaxu_b:
11177 case Intrinsic::x86_sse41_pmaxuw:
11178 case Intrinsic::x86_sse41_pmaxud:
11179 case Intrinsic::x86_avx2_pmaxu_b:
11180 case Intrinsic::x86_avx2_pmaxu_w:
11181 case Intrinsic::x86_avx2_pmaxu_d:
11182 case Intrinsic::x86_avx512_pmaxu_d:
11183 case Intrinsic::x86_avx512_pmaxu_q:
11184 case Intrinsic::x86_sse2_pminu_b:
11185 case Intrinsic::x86_sse41_pminuw:
11186 case Intrinsic::x86_sse41_pminud:
11187 case Intrinsic::x86_avx2_pminu_b:
11188 case Intrinsic::x86_avx2_pminu_w:
11189 case Intrinsic::x86_avx2_pminu_d:
11190 case Intrinsic::x86_avx512_pminu_d:
11191 case Intrinsic::x86_avx512_pminu_q:
11192 case Intrinsic::x86_sse41_pmaxsb:
11193 case Intrinsic::x86_sse2_pmaxs_w:
11194 case Intrinsic::x86_sse41_pmaxsd:
11195 case Intrinsic::x86_avx2_pmaxs_b:
11196 case Intrinsic::x86_avx2_pmaxs_w:
11197 case Intrinsic::x86_avx2_pmaxs_d:
11198 case Intrinsic::x86_avx512_pmaxs_d:
11199 case Intrinsic::x86_avx512_pmaxs_q:
11200 case Intrinsic::x86_sse41_pminsb:
11201 case Intrinsic::x86_sse2_pmins_w:
11202 case Intrinsic::x86_sse41_pminsd:
11203 case Intrinsic::x86_avx2_pmins_b:
11204 case Intrinsic::x86_avx2_pmins_w:
11205 case Intrinsic::x86_avx2_pmins_d:
11206 case Intrinsic::x86_avx512_pmins_d:
11207 case Intrinsic::x86_avx512_pmins_q: {
11210 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11211 case Intrinsic::x86_sse2_pmaxu_b:
11212 case Intrinsic::x86_sse41_pmaxuw:
11213 case Intrinsic::x86_sse41_pmaxud:
11214 case Intrinsic::x86_avx2_pmaxu_b:
11215 case Intrinsic::x86_avx2_pmaxu_w:
11216 case Intrinsic::x86_avx2_pmaxu_d:
11217 case Intrinsic::x86_avx512_pmaxu_d:
11218 case Intrinsic::x86_avx512_pmaxu_q:
11219 Opcode = X86ISD::UMAX;
11221 case Intrinsic::x86_sse2_pminu_b:
11222 case Intrinsic::x86_sse41_pminuw:
11223 case Intrinsic::x86_sse41_pminud:
11224 case Intrinsic::x86_avx2_pminu_b:
11225 case Intrinsic::x86_avx2_pminu_w:
11226 case Intrinsic::x86_avx2_pminu_d:
11227 case Intrinsic::x86_avx512_pminu_d:
11228 case Intrinsic::x86_avx512_pminu_q:
11229 Opcode = X86ISD::UMIN;
11231 case Intrinsic::x86_sse41_pmaxsb:
11232 case Intrinsic::x86_sse2_pmaxs_w:
11233 case Intrinsic::x86_sse41_pmaxsd:
11234 case Intrinsic::x86_avx2_pmaxs_b:
11235 case Intrinsic::x86_avx2_pmaxs_w:
11236 case Intrinsic::x86_avx2_pmaxs_d:
11237 case Intrinsic::x86_avx512_pmaxs_d:
11238 case Intrinsic::x86_avx512_pmaxs_q:
11239 Opcode = X86ISD::SMAX;
11241 case Intrinsic::x86_sse41_pminsb:
11242 case Intrinsic::x86_sse2_pmins_w:
11243 case Intrinsic::x86_sse41_pminsd:
11244 case Intrinsic::x86_avx2_pmins_b:
11245 case Intrinsic::x86_avx2_pmins_w:
11246 case Intrinsic::x86_avx2_pmins_d:
11247 case Intrinsic::x86_avx512_pmins_d:
11248 case Intrinsic::x86_avx512_pmins_q:
11249 Opcode = X86ISD::SMIN;
11252 return DAG.getNode(Opcode, dl, Op.getValueType(),
11253 Op.getOperand(1), Op.getOperand(2));
11256 // SSE/SSE2/AVX floating point max/min intrinsics.
11257 case Intrinsic::x86_sse_max_ps:
11258 case Intrinsic::x86_sse2_max_pd:
11259 case Intrinsic::x86_avx_max_ps_256:
11260 case Intrinsic::x86_avx_max_pd_256:
11261 case Intrinsic::x86_avx512_max_ps_512:
11262 case Intrinsic::x86_avx512_max_pd_512:
11263 case Intrinsic::x86_sse_min_ps:
11264 case Intrinsic::x86_sse2_min_pd:
11265 case Intrinsic::x86_avx_min_ps_256:
11266 case Intrinsic::x86_avx_min_pd_256:
11267 case Intrinsic::x86_avx512_min_ps_512:
11268 case Intrinsic::x86_avx512_min_pd_512: {
11271 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11272 case Intrinsic::x86_sse_max_ps:
11273 case Intrinsic::x86_sse2_max_pd:
11274 case Intrinsic::x86_avx_max_ps_256:
11275 case Intrinsic::x86_avx_max_pd_256:
11276 case Intrinsic::x86_avx512_max_ps_512:
11277 case Intrinsic::x86_avx512_max_pd_512:
11278 Opcode = X86ISD::FMAX;
11280 case Intrinsic::x86_sse_min_ps:
11281 case Intrinsic::x86_sse2_min_pd:
11282 case Intrinsic::x86_avx_min_ps_256:
11283 case Intrinsic::x86_avx_min_pd_256:
11284 case Intrinsic::x86_avx512_min_ps_512:
11285 case Intrinsic::x86_avx512_min_pd_512:
11286 Opcode = X86ISD::FMIN;
11289 return DAG.getNode(Opcode, dl, Op.getValueType(),
11290 Op.getOperand(1), Op.getOperand(2));
11293 // AVX2 variable shift intrinsics
11294 case Intrinsic::x86_avx2_psllv_d:
11295 case Intrinsic::x86_avx2_psllv_q:
11296 case Intrinsic::x86_avx2_psllv_d_256:
11297 case Intrinsic::x86_avx2_psllv_q_256:
11298 case Intrinsic::x86_avx2_psrlv_d:
11299 case Intrinsic::x86_avx2_psrlv_q:
11300 case Intrinsic::x86_avx2_psrlv_d_256:
11301 case Intrinsic::x86_avx2_psrlv_q_256:
11302 case Intrinsic::x86_avx2_psrav_d:
11303 case Intrinsic::x86_avx2_psrav_d_256: {
11306 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11307 case Intrinsic::x86_avx2_psllv_d:
11308 case Intrinsic::x86_avx2_psllv_q:
11309 case Intrinsic::x86_avx2_psllv_d_256:
11310 case Intrinsic::x86_avx2_psllv_q_256:
11313 case Intrinsic::x86_avx2_psrlv_d:
11314 case Intrinsic::x86_avx2_psrlv_q:
11315 case Intrinsic::x86_avx2_psrlv_d_256:
11316 case Intrinsic::x86_avx2_psrlv_q_256:
11319 case Intrinsic::x86_avx2_psrav_d:
11320 case Intrinsic::x86_avx2_psrav_d_256:
11324 return DAG.getNode(Opcode, dl, Op.getValueType(),
11325 Op.getOperand(1), Op.getOperand(2));
11328 case Intrinsic::x86_ssse3_pshuf_b_128:
11329 case Intrinsic::x86_avx2_pshuf_b:
11330 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
11331 Op.getOperand(1), Op.getOperand(2));
11333 case Intrinsic::x86_ssse3_psign_b_128:
11334 case Intrinsic::x86_ssse3_psign_w_128:
11335 case Intrinsic::x86_ssse3_psign_d_128:
11336 case Intrinsic::x86_avx2_psign_b:
11337 case Intrinsic::x86_avx2_psign_w:
11338 case Intrinsic::x86_avx2_psign_d:
11339 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
11340 Op.getOperand(1), Op.getOperand(2));
11342 case Intrinsic::x86_sse41_insertps:
11343 return DAG.getNode(X86ISD::INSERTPS, dl, Op.getValueType(),
11344 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
11346 case Intrinsic::x86_avx_vperm2f128_ps_256:
11347 case Intrinsic::x86_avx_vperm2f128_pd_256:
11348 case Intrinsic::x86_avx_vperm2f128_si_256:
11349 case Intrinsic::x86_avx2_vperm2i128:
11350 return DAG.getNode(X86ISD::VPERM2X128, dl, Op.getValueType(),
11351 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
11353 case Intrinsic::x86_avx2_permd:
11354 case Intrinsic::x86_avx2_permps:
11355 // Operands intentionally swapped. Mask is last operand to intrinsic,
11356 // but second operand for node/instruction.
11357 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
11358 Op.getOperand(2), Op.getOperand(1));
11360 case Intrinsic::x86_sse_sqrt_ps:
11361 case Intrinsic::x86_sse2_sqrt_pd:
11362 case Intrinsic::x86_avx_sqrt_ps_256:
11363 case Intrinsic::x86_avx_sqrt_pd_256:
11364 return DAG.getNode(ISD::FSQRT, dl, Op.getValueType(), Op.getOperand(1));
11366 // ptest and testp intrinsics. The intrinsic these come from are designed to
11367 // return an integer value, not just an instruction so lower it to the ptest
11368 // or testp pattern and a setcc for the result.
11369 case Intrinsic::x86_sse41_ptestz:
11370 case Intrinsic::x86_sse41_ptestc:
11371 case Intrinsic::x86_sse41_ptestnzc:
11372 case Intrinsic::x86_avx_ptestz_256:
11373 case Intrinsic::x86_avx_ptestc_256:
11374 case Intrinsic::x86_avx_ptestnzc_256:
11375 case Intrinsic::x86_avx_vtestz_ps:
11376 case Intrinsic::x86_avx_vtestc_ps:
11377 case Intrinsic::x86_avx_vtestnzc_ps:
11378 case Intrinsic::x86_avx_vtestz_pd:
11379 case Intrinsic::x86_avx_vtestc_pd:
11380 case Intrinsic::x86_avx_vtestnzc_pd:
11381 case Intrinsic::x86_avx_vtestz_ps_256:
11382 case Intrinsic::x86_avx_vtestc_ps_256:
11383 case Intrinsic::x86_avx_vtestnzc_ps_256:
11384 case Intrinsic::x86_avx_vtestz_pd_256:
11385 case Intrinsic::x86_avx_vtestc_pd_256:
11386 case Intrinsic::x86_avx_vtestnzc_pd_256: {
11387 bool IsTestPacked = false;
11390 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
11391 case Intrinsic::x86_avx_vtestz_ps:
11392 case Intrinsic::x86_avx_vtestz_pd:
11393 case Intrinsic::x86_avx_vtestz_ps_256:
11394 case Intrinsic::x86_avx_vtestz_pd_256:
11395 IsTestPacked = true; // Fallthrough
11396 case Intrinsic::x86_sse41_ptestz:
11397 case Intrinsic::x86_avx_ptestz_256:
11399 X86CC = X86::COND_E;
11401 case Intrinsic::x86_avx_vtestc_ps:
11402 case Intrinsic::x86_avx_vtestc_pd:
11403 case Intrinsic::x86_avx_vtestc_ps_256:
11404 case Intrinsic::x86_avx_vtestc_pd_256:
11405 IsTestPacked = true; // Fallthrough
11406 case Intrinsic::x86_sse41_ptestc:
11407 case Intrinsic::x86_avx_ptestc_256:
11409 X86CC = X86::COND_B;
11411 case Intrinsic::x86_avx_vtestnzc_ps:
11412 case Intrinsic::x86_avx_vtestnzc_pd:
11413 case Intrinsic::x86_avx_vtestnzc_ps_256:
11414 case Intrinsic::x86_avx_vtestnzc_pd_256:
11415 IsTestPacked = true; // Fallthrough
11416 case Intrinsic::x86_sse41_ptestnzc:
11417 case Intrinsic::x86_avx_ptestnzc_256:
11419 X86CC = X86::COND_A;
11423 SDValue LHS = Op.getOperand(1);
11424 SDValue RHS = Op.getOperand(2);
11425 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
11426 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
11427 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
11428 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
11429 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
11431 case Intrinsic::x86_avx512_kortestz:
11432 case Intrinsic::x86_avx512_kortestc: {
11433 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz)? X86::COND_E: X86::COND_B;
11434 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
11435 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
11436 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
11437 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
11438 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
11439 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
11442 // SSE/AVX shift intrinsics
11443 case Intrinsic::x86_sse2_psll_w:
11444 case Intrinsic::x86_sse2_psll_d:
11445 case Intrinsic::x86_sse2_psll_q:
11446 case Intrinsic::x86_avx2_psll_w:
11447 case Intrinsic::x86_avx2_psll_d:
11448 case Intrinsic::x86_avx2_psll_q:
11449 case Intrinsic::x86_sse2_psrl_w:
11450 case Intrinsic::x86_sse2_psrl_d:
11451 case Intrinsic::x86_sse2_psrl_q:
11452 case Intrinsic::x86_avx2_psrl_w:
11453 case Intrinsic::x86_avx2_psrl_d:
11454 case Intrinsic::x86_avx2_psrl_q:
11455 case Intrinsic::x86_sse2_psra_w:
11456 case Intrinsic::x86_sse2_psra_d:
11457 case Intrinsic::x86_avx2_psra_w:
11458 case Intrinsic::x86_avx2_psra_d: {
11461 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11462 case Intrinsic::x86_sse2_psll_w:
11463 case Intrinsic::x86_sse2_psll_d:
11464 case Intrinsic::x86_sse2_psll_q:
11465 case Intrinsic::x86_avx2_psll_w:
11466 case Intrinsic::x86_avx2_psll_d:
11467 case Intrinsic::x86_avx2_psll_q:
11468 Opcode = X86ISD::VSHL;
11470 case Intrinsic::x86_sse2_psrl_w:
11471 case Intrinsic::x86_sse2_psrl_d:
11472 case Intrinsic::x86_sse2_psrl_q:
11473 case Intrinsic::x86_avx2_psrl_w:
11474 case Intrinsic::x86_avx2_psrl_d:
11475 case Intrinsic::x86_avx2_psrl_q:
11476 Opcode = X86ISD::VSRL;
11478 case Intrinsic::x86_sse2_psra_w:
11479 case Intrinsic::x86_sse2_psra_d:
11480 case Intrinsic::x86_avx2_psra_w:
11481 case Intrinsic::x86_avx2_psra_d:
11482 Opcode = X86ISD::VSRA;
11485 return DAG.getNode(Opcode, dl, Op.getValueType(),
11486 Op.getOperand(1), Op.getOperand(2));
11489 // SSE/AVX immediate shift intrinsics
11490 case Intrinsic::x86_sse2_pslli_w:
11491 case Intrinsic::x86_sse2_pslli_d:
11492 case Intrinsic::x86_sse2_pslli_q:
11493 case Intrinsic::x86_avx2_pslli_w:
11494 case Intrinsic::x86_avx2_pslli_d:
11495 case Intrinsic::x86_avx2_pslli_q:
11496 case Intrinsic::x86_sse2_psrli_w:
11497 case Intrinsic::x86_sse2_psrli_d:
11498 case Intrinsic::x86_sse2_psrli_q:
11499 case Intrinsic::x86_avx2_psrli_w:
11500 case Intrinsic::x86_avx2_psrli_d:
11501 case Intrinsic::x86_avx2_psrli_q:
11502 case Intrinsic::x86_sse2_psrai_w:
11503 case Intrinsic::x86_sse2_psrai_d:
11504 case Intrinsic::x86_avx2_psrai_w:
11505 case Intrinsic::x86_avx2_psrai_d: {
11508 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11509 case Intrinsic::x86_sse2_pslli_w:
11510 case Intrinsic::x86_sse2_pslli_d:
11511 case Intrinsic::x86_sse2_pslli_q:
11512 case Intrinsic::x86_avx2_pslli_w:
11513 case Intrinsic::x86_avx2_pslli_d:
11514 case Intrinsic::x86_avx2_pslli_q:
11515 Opcode = X86ISD::VSHLI;
11517 case Intrinsic::x86_sse2_psrli_w:
11518 case Intrinsic::x86_sse2_psrli_d:
11519 case Intrinsic::x86_sse2_psrli_q:
11520 case Intrinsic::x86_avx2_psrli_w:
11521 case Intrinsic::x86_avx2_psrli_d:
11522 case Intrinsic::x86_avx2_psrli_q:
11523 Opcode = X86ISD::VSRLI;
11525 case Intrinsic::x86_sse2_psrai_w:
11526 case Intrinsic::x86_sse2_psrai_d:
11527 case Intrinsic::x86_avx2_psrai_w:
11528 case Intrinsic::x86_avx2_psrai_d:
11529 Opcode = X86ISD::VSRAI;
11532 return getTargetVShiftNode(Opcode, dl, Op.getValueType(),
11533 Op.getOperand(1), Op.getOperand(2), DAG);
11536 case Intrinsic::x86_sse42_pcmpistria128:
11537 case Intrinsic::x86_sse42_pcmpestria128:
11538 case Intrinsic::x86_sse42_pcmpistric128:
11539 case Intrinsic::x86_sse42_pcmpestric128:
11540 case Intrinsic::x86_sse42_pcmpistrio128:
11541 case Intrinsic::x86_sse42_pcmpestrio128:
11542 case Intrinsic::x86_sse42_pcmpistris128:
11543 case Intrinsic::x86_sse42_pcmpestris128:
11544 case Intrinsic::x86_sse42_pcmpistriz128:
11545 case Intrinsic::x86_sse42_pcmpestriz128: {
11549 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11550 case Intrinsic::x86_sse42_pcmpistria128:
11551 Opcode = X86ISD::PCMPISTRI;
11552 X86CC = X86::COND_A;
11554 case Intrinsic::x86_sse42_pcmpestria128:
11555 Opcode = X86ISD::PCMPESTRI;
11556 X86CC = X86::COND_A;
11558 case Intrinsic::x86_sse42_pcmpistric128:
11559 Opcode = X86ISD::PCMPISTRI;
11560 X86CC = X86::COND_B;
11562 case Intrinsic::x86_sse42_pcmpestric128:
11563 Opcode = X86ISD::PCMPESTRI;
11564 X86CC = X86::COND_B;
11566 case Intrinsic::x86_sse42_pcmpistrio128:
11567 Opcode = X86ISD::PCMPISTRI;
11568 X86CC = X86::COND_O;
11570 case Intrinsic::x86_sse42_pcmpestrio128:
11571 Opcode = X86ISD::PCMPESTRI;
11572 X86CC = X86::COND_O;
11574 case Intrinsic::x86_sse42_pcmpistris128:
11575 Opcode = X86ISD::PCMPISTRI;
11576 X86CC = X86::COND_S;
11578 case Intrinsic::x86_sse42_pcmpestris128:
11579 Opcode = X86ISD::PCMPESTRI;
11580 X86CC = X86::COND_S;
11582 case Intrinsic::x86_sse42_pcmpistriz128:
11583 Opcode = X86ISD::PCMPISTRI;
11584 X86CC = X86::COND_E;
11586 case Intrinsic::x86_sse42_pcmpestriz128:
11587 Opcode = X86ISD::PCMPESTRI;
11588 X86CC = X86::COND_E;
11591 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
11592 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
11593 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps.data(), NewOps.size());
11594 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
11595 DAG.getConstant(X86CC, MVT::i8),
11596 SDValue(PCMP.getNode(), 1));
11597 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
11600 case Intrinsic::x86_sse42_pcmpistri128:
11601 case Intrinsic::x86_sse42_pcmpestri128: {
11603 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
11604 Opcode = X86ISD::PCMPISTRI;
11606 Opcode = X86ISD::PCMPESTRI;
11608 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
11609 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
11610 return DAG.getNode(Opcode, dl, VTs, NewOps.data(), NewOps.size());
11612 case Intrinsic::x86_fma_vfmadd_ps:
11613 case Intrinsic::x86_fma_vfmadd_pd:
11614 case Intrinsic::x86_fma_vfmsub_ps:
11615 case Intrinsic::x86_fma_vfmsub_pd:
11616 case Intrinsic::x86_fma_vfnmadd_ps:
11617 case Intrinsic::x86_fma_vfnmadd_pd:
11618 case Intrinsic::x86_fma_vfnmsub_ps:
11619 case Intrinsic::x86_fma_vfnmsub_pd:
11620 case Intrinsic::x86_fma_vfmaddsub_ps:
11621 case Intrinsic::x86_fma_vfmaddsub_pd:
11622 case Intrinsic::x86_fma_vfmsubadd_ps:
11623 case Intrinsic::x86_fma_vfmsubadd_pd:
11624 case Intrinsic::x86_fma_vfmadd_ps_256:
11625 case Intrinsic::x86_fma_vfmadd_pd_256:
11626 case Intrinsic::x86_fma_vfmsub_ps_256:
11627 case Intrinsic::x86_fma_vfmsub_pd_256:
11628 case Intrinsic::x86_fma_vfnmadd_ps_256:
11629 case Intrinsic::x86_fma_vfnmadd_pd_256:
11630 case Intrinsic::x86_fma_vfnmsub_ps_256:
11631 case Intrinsic::x86_fma_vfnmsub_pd_256:
11632 case Intrinsic::x86_fma_vfmaddsub_ps_256:
11633 case Intrinsic::x86_fma_vfmaddsub_pd_256:
11634 case Intrinsic::x86_fma_vfmsubadd_ps_256:
11635 case Intrinsic::x86_fma_vfmsubadd_pd_256: {
11638 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11639 case Intrinsic::x86_fma_vfmadd_ps:
11640 case Intrinsic::x86_fma_vfmadd_pd:
11641 case Intrinsic::x86_fma_vfmadd_ps_256:
11642 case Intrinsic::x86_fma_vfmadd_pd_256:
11643 Opc = X86ISD::FMADD;
11645 case Intrinsic::x86_fma_vfmsub_ps:
11646 case Intrinsic::x86_fma_vfmsub_pd:
11647 case Intrinsic::x86_fma_vfmsub_ps_256:
11648 case Intrinsic::x86_fma_vfmsub_pd_256:
11649 Opc = X86ISD::FMSUB;
11651 case Intrinsic::x86_fma_vfnmadd_ps:
11652 case Intrinsic::x86_fma_vfnmadd_pd:
11653 case Intrinsic::x86_fma_vfnmadd_ps_256:
11654 case Intrinsic::x86_fma_vfnmadd_pd_256:
11655 Opc = X86ISD::FNMADD;
11657 case Intrinsic::x86_fma_vfnmsub_ps:
11658 case Intrinsic::x86_fma_vfnmsub_pd:
11659 case Intrinsic::x86_fma_vfnmsub_ps_256:
11660 case Intrinsic::x86_fma_vfnmsub_pd_256:
11661 Opc = X86ISD::FNMSUB;
11663 case Intrinsic::x86_fma_vfmaddsub_ps:
11664 case Intrinsic::x86_fma_vfmaddsub_pd:
11665 case Intrinsic::x86_fma_vfmaddsub_ps_256:
11666 case Intrinsic::x86_fma_vfmaddsub_pd_256:
11667 Opc = X86ISD::FMADDSUB;
11669 case Intrinsic::x86_fma_vfmsubadd_ps:
11670 case Intrinsic::x86_fma_vfmsubadd_pd:
11671 case Intrinsic::x86_fma_vfmsubadd_ps_256:
11672 case Intrinsic::x86_fma_vfmsubadd_pd_256:
11673 Opc = X86ISD::FMSUBADD;
11677 return DAG.getNode(Opc, dl, Op.getValueType(), Op.getOperand(1),
11678 Op.getOperand(2), Op.getOperand(3));
11683 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
11684 SDValue Base, SDValue Index,
11685 SDValue ScaleOp, SDValue Chain,
11686 const X86Subtarget * Subtarget) {
11688 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
11689 assert(C && "Invalid scale type");
11690 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
11691 SDValue Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
11692 EVT MaskVT = MVT::getVectorVT(MVT::i1,
11693 Index.getValueType().getVectorNumElements());
11694 SDValue MaskInReg = DAG.getConstant(~0, MaskVT);
11695 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
11696 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
11697 SDValue Segment = DAG.getRegister(0, MVT::i32);
11698 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
11699 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
11700 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
11701 return DAG.getMergeValues(RetOps, array_lengthof(RetOps), dl);
11704 static SDValue getMGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
11705 SDValue Src, SDValue Mask, SDValue Base,
11706 SDValue Index, SDValue ScaleOp, SDValue Chain,
11707 const X86Subtarget * Subtarget) {
11709 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
11710 assert(C && "Invalid scale type");
11711 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
11712 EVT MaskVT = MVT::getVectorVT(MVT::i1,
11713 Index.getValueType().getVectorNumElements());
11714 SDValue MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
11715 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
11716 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
11717 SDValue Segment = DAG.getRegister(0, MVT::i32);
11718 if (Src.getOpcode() == ISD::UNDEF)
11719 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
11720 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
11721 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
11722 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
11723 return DAG.getMergeValues(RetOps, array_lengthof(RetOps), dl);
11726 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
11727 SDValue Src, SDValue Base, SDValue Index,
11728 SDValue ScaleOp, SDValue Chain) {
11730 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
11731 assert(C && "Invalid scale type");
11732 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
11733 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
11734 SDValue Segment = DAG.getRegister(0, MVT::i32);
11735 EVT MaskVT = MVT::getVectorVT(MVT::i1,
11736 Index.getValueType().getVectorNumElements());
11737 SDValue MaskInReg = DAG.getConstant(~0, MaskVT);
11738 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
11739 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
11740 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
11741 return SDValue(Res, 1);
11744 static SDValue getMScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
11745 SDValue Src, SDValue Mask, SDValue Base,
11746 SDValue Index, SDValue ScaleOp, SDValue Chain) {
11748 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
11749 assert(C && "Invalid scale type");
11750 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
11751 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
11752 SDValue Segment = DAG.getRegister(0, MVT::i32);
11753 EVT MaskVT = MVT::getVectorVT(MVT::i1,
11754 Index.getValueType().getVectorNumElements());
11755 SDValue MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
11756 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
11757 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
11758 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
11759 return SDValue(Res, 1);
11762 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
11763 SelectionDAG &DAG) {
11765 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11767 default: return SDValue(); // Don't custom lower most intrinsics.
11769 // RDRAND/RDSEED intrinsics.
11770 case Intrinsic::x86_rdrand_16:
11771 case Intrinsic::x86_rdrand_32:
11772 case Intrinsic::x86_rdrand_64:
11773 case Intrinsic::x86_rdseed_16:
11774 case Intrinsic::x86_rdseed_32:
11775 case Intrinsic::x86_rdseed_64: {
11776 unsigned Opcode = (IntNo == Intrinsic::x86_rdseed_16 ||
11777 IntNo == Intrinsic::x86_rdseed_32 ||
11778 IntNo == Intrinsic::x86_rdseed_64) ? X86ISD::RDSEED :
11780 // Emit the node with the right value type.
11781 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
11782 SDValue Result = DAG.getNode(Opcode, dl, VTs, Op.getOperand(0));
11784 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
11785 // Otherwise return the value from Rand, which is always 0, casted to i32.
11786 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
11787 DAG.getConstant(1, Op->getValueType(1)),
11788 DAG.getConstant(X86::COND_B, MVT::i32),
11789 SDValue(Result.getNode(), 1) };
11790 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
11791 DAG.getVTList(Op->getValueType(1), MVT::Glue),
11792 Ops, array_lengthof(Ops));
11794 // Return { result, isValid, chain }.
11795 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
11796 SDValue(Result.getNode(), 2));
11798 //int_gather(index, base, scale);
11799 case Intrinsic::x86_avx512_gather_qpd_512:
11800 case Intrinsic::x86_avx512_gather_qps_512:
11801 case Intrinsic::x86_avx512_gather_dpd_512:
11802 case Intrinsic::x86_avx512_gather_qpi_512:
11803 case Intrinsic::x86_avx512_gather_qpq_512:
11804 case Intrinsic::x86_avx512_gather_dpq_512:
11805 case Intrinsic::x86_avx512_gather_dps_512:
11806 case Intrinsic::x86_avx512_gather_dpi_512: {
11809 default: llvm_unreachable("Unexpected intrinsic!");
11810 case Intrinsic::x86_avx512_gather_qps_512: Opc = X86::VGATHERQPSZrm; break;
11811 case Intrinsic::x86_avx512_gather_qpd_512: Opc = X86::VGATHERQPDZrm; break;
11812 case Intrinsic::x86_avx512_gather_dpd_512: Opc = X86::VGATHERDPDZrm; break;
11813 case Intrinsic::x86_avx512_gather_dps_512: Opc = X86::VGATHERDPSZrm; break;
11814 case Intrinsic::x86_avx512_gather_qpi_512: Opc = X86::VPGATHERQDZrm; break;
11815 case Intrinsic::x86_avx512_gather_qpq_512: Opc = X86::VPGATHERQQZrm; break;
11816 case Intrinsic::x86_avx512_gather_dpi_512: Opc = X86::VPGATHERDDZrm; break;
11817 case Intrinsic::x86_avx512_gather_dpq_512: Opc = X86::VPGATHERDQZrm; break;
11819 SDValue Chain = Op.getOperand(0);
11820 SDValue Index = Op.getOperand(2);
11821 SDValue Base = Op.getOperand(3);
11822 SDValue Scale = Op.getOperand(4);
11823 return getGatherNode(Opc, Op, DAG, Base, Index, Scale, Chain, Subtarget);
11825 //int_gather_mask(v1, mask, index, base, scale);
11826 case Intrinsic::x86_avx512_gather_qps_mask_512:
11827 case Intrinsic::x86_avx512_gather_qpd_mask_512:
11828 case Intrinsic::x86_avx512_gather_dpd_mask_512:
11829 case Intrinsic::x86_avx512_gather_dps_mask_512:
11830 case Intrinsic::x86_avx512_gather_qpi_mask_512:
11831 case Intrinsic::x86_avx512_gather_qpq_mask_512:
11832 case Intrinsic::x86_avx512_gather_dpi_mask_512:
11833 case Intrinsic::x86_avx512_gather_dpq_mask_512: {
11836 default: llvm_unreachable("Unexpected intrinsic!");
11837 case Intrinsic::x86_avx512_gather_qps_mask_512:
11838 Opc = X86::VGATHERQPSZrm; break;
11839 case Intrinsic::x86_avx512_gather_qpd_mask_512:
11840 Opc = X86::VGATHERQPDZrm; break;
11841 case Intrinsic::x86_avx512_gather_dpd_mask_512:
11842 Opc = X86::VGATHERDPDZrm; break;
11843 case Intrinsic::x86_avx512_gather_dps_mask_512:
11844 Opc = X86::VGATHERDPSZrm; break;
11845 case Intrinsic::x86_avx512_gather_qpi_mask_512:
11846 Opc = X86::VPGATHERQDZrm; break;
11847 case Intrinsic::x86_avx512_gather_qpq_mask_512:
11848 Opc = X86::VPGATHERQQZrm; break;
11849 case Intrinsic::x86_avx512_gather_dpi_mask_512:
11850 Opc = X86::VPGATHERDDZrm; break;
11851 case Intrinsic::x86_avx512_gather_dpq_mask_512:
11852 Opc = X86::VPGATHERDQZrm; break;
11854 SDValue Chain = Op.getOperand(0);
11855 SDValue Src = Op.getOperand(2);
11856 SDValue Mask = Op.getOperand(3);
11857 SDValue Index = Op.getOperand(4);
11858 SDValue Base = Op.getOperand(5);
11859 SDValue Scale = Op.getOperand(6);
11860 return getMGatherNode(Opc, Op, DAG, Src, Mask, Base, Index, Scale, Chain,
11863 //int_scatter(base, index, v1, scale);
11864 case Intrinsic::x86_avx512_scatter_qpd_512:
11865 case Intrinsic::x86_avx512_scatter_qps_512:
11866 case Intrinsic::x86_avx512_scatter_dpd_512:
11867 case Intrinsic::x86_avx512_scatter_qpi_512:
11868 case Intrinsic::x86_avx512_scatter_qpq_512:
11869 case Intrinsic::x86_avx512_scatter_dpq_512:
11870 case Intrinsic::x86_avx512_scatter_dps_512:
11871 case Intrinsic::x86_avx512_scatter_dpi_512: {
11874 default: llvm_unreachable("Unexpected intrinsic!");
11875 case Intrinsic::x86_avx512_scatter_qpd_512:
11876 Opc = X86::VSCATTERQPDZmr; break;
11877 case Intrinsic::x86_avx512_scatter_qps_512:
11878 Opc = X86::VSCATTERQPSZmr; break;
11879 case Intrinsic::x86_avx512_scatter_dpd_512:
11880 Opc = X86::VSCATTERDPDZmr; break;
11881 case Intrinsic::x86_avx512_scatter_dps_512:
11882 Opc = X86::VSCATTERDPSZmr; break;
11883 case Intrinsic::x86_avx512_scatter_qpi_512:
11884 Opc = X86::VPSCATTERQDZmr; break;
11885 case Intrinsic::x86_avx512_scatter_qpq_512:
11886 Opc = X86::VPSCATTERQQZmr; break;
11887 case Intrinsic::x86_avx512_scatter_dpq_512:
11888 Opc = X86::VPSCATTERDQZmr; break;
11889 case Intrinsic::x86_avx512_scatter_dpi_512:
11890 Opc = X86::VPSCATTERDDZmr; break;
11892 SDValue Chain = Op.getOperand(0);
11893 SDValue Base = Op.getOperand(2);
11894 SDValue Index = Op.getOperand(3);
11895 SDValue Src = Op.getOperand(4);
11896 SDValue Scale = Op.getOperand(5);
11897 return getScatterNode(Opc, Op, DAG, Src, Base, Index, Scale, Chain);
11899 //int_scatter_mask(base, mask, index, v1, scale);
11900 case Intrinsic::x86_avx512_scatter_qps_mask_512:
11901 case Intrinsic::x86_avx512_scatter_qpd_mask_512:
11902 case Intrinsic::x86_avx512_scatter_dpd_mask_512:
11903 case Intrinsic::x86_avx512_scatter_dps_mask_512:
11904 case Intrinsic::x86_avx512_scatter_qpi_mask_512:
11905 case Intrinsic::x86_avx512_scatter_qpq_mask_512:
11906 case Intrinsic::x86_avx512_scatter_dpi_mask_512:
11907 case Intrinsic::x86_avx512_scatter_dpq_mask_512: {
11910 default: llvm_unreachable("Unexpected intrinsic!");
11911 case Intrinsic::x86_avx512_scatter_qpd_mask_512:
11912 Opc = X86::VSCATTERQPDZmr; break;
11913 case Intrinsic::x86_avx512_scatter_qps_mask_512:
11914 Opc = X86::VSCATTERQPSZmr; break;
11915 case Intrinsic::x86_avx512_scatter_dpd_mask_512:
11916 Opc = X86::VSCATTERDPDZmr; break;
11917 case Intrinsic::x86_avx512_scatter_dps_mask_512:
11918 Opc = X86::VSCATTERDPSZmr; break;
11919 case Intrinsic::x86_avx512_scatter_qpi_mask_512:
11920 Opc = X86::VPSCATTERQDZmr; break;
11921 case Intrinsic::x86_avx512_scatter_qpq_mask_512:
11922 Opc = X86::VPSCATTERQQZmr; break;
11923 case Intrinsic::x86_avx512_scatter_dpq_mask_512:
11924 Opc = X86::VPSCATTERDQZmr; break;
11925 case Intrinsic::x86_avx512_scatter_dpi_mask_512:
11926 Opc = X86::VPSCATTERDDZmr; break;
11928 SDValue Chain = Op.getOperand(0);
11929 SDValue Base = Op.getOperand(2);
11930 SDValue Mask = Op.getOperand(3);
11931 SDValue Index = Op.getOperand(4);
11932 SDValue Src = Op.getOperand(5);
11933 SDValue Scale = Op.getOperand(6);
11934 return getMScatterNode(Opc, Op, DAG, Src, Mask, Base, Index, Scale, Chain);
11936 // XTEST intrinsics.
11937 case Intrinsic::x86_xtest: {
11938 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
11939 SDValue InTrans = DAG.getNode(X86ISD::XTEST, dl, VTs, Op.getOperand(0));
11940 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
11941 DAG.getConstant(X86::COND_NE, MVT::i8),
11943 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
11944 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
11945 Ret, SDValue(InTrans.getNode(), 1));
11950 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
11951 SelectionDAG &DAG) const {
11952 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
11953 MFI->setReturnAddressIsTaken(true);
11955 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
11957 EVT PtrVT = getPointerTy();
11960 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
11961 const X86RegisterInfo *RegInfo =
11962 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
11963 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
11964 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
11965 DAG.getNode(ISD::ADD, dl, PtrVT,
11966 FrameAddr, Offset),
11967 MachinePointerInfo(), false, false, false, 0);
11970 // Just load the return address.
11971 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
11972 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
11973 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
11976 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
11977 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
11978 MFI->setFrameAddressIsTaken(true);
11980 EVT VT = Op.getValueType();
11981 SDLoc dl(Op); // FIXME probably not meaningful
11982 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
11983 const X86RegisterInfo *RegInfo =
11984 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
11985 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
11986 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
11987 (FrameReg == X86::EBP && VT == MVT::i32)) &&
11988 "Invalid Frame Register!");
11989 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
11991 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
11992 MachinePointerInfo(),
11993 false, false, false, 0);
11997 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
11998 SelectionDAG &DAG) const {
11999 const X86RegisterInfo *RegInfo =
12000 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
12001 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
12004 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
12005 SDValue Chain = Op.getOperand(0);
12006 SDValue Offset = Op.getOperand(1);
12007 SDValue Handler = Op.getOperand(2);
12010 EVT PtrVT = getPointerTy();
12011 const X86RegisterInfo *RegInfo =
12012 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
12013 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
12014 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
12015 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
12016 "Invalid Frame Register!");
12017 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
12018 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
12020 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
12021 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
12022 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
12023 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
12025 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
12027 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
12028 DAG.getRegister(StoreAddrReg, PtrVT));
12031 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
12032 SelectionDAG &DAG) const {
12034 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
12035 DAG.getVTList(MVT::i32, MVT::Other),
12036 Op.getOperand(0), Op.getOperand(1));
12039 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
12040 SelectionDAG &DAG) const {
12042 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
12043 Op.getOperand(0), Op.getOperand(1));
12046 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
12047 return Op.getOperand(0);
12050 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
12051 SelectionDAG &DAG) const {
12052 SDValue Root = Op.getOperand(0);
12053 SDValue Trmp = Op.getOperand(1); // trampoline
12054 SDValue FPtr = Op.getOperand(2); // nested function
12055 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
12058 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
12059 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
12061 if (Subtarget->is64Bit()) {
12062 SDValue OutChains[6];
12064 // Large code-model.
12065 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
12066 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
12068 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
12069 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
12071 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
12073 // Load the pointer to the nested function into R11.
12074 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
12075 SDValue Addr = Trmp;
12076 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
12077 Addr, MachinePointerInfo(TrmpAddr),
12080 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
12081 DAG.getConstant(2, MVT::i64));
12082 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
12083 MachinePointerInfo(TrmpAddr, 2),
12086 // Load the 'nest' parameter value into R10.
12087 // R10 is specified in X86CallingConv.td
12088 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
12089 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
12090 DAG.getConstant(10, MVT::i64));
12091 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
12092 Addr, MachinePointerInfo(TrmpAddr, 10),
12095 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
12096 DAG.getConstant(12, MVT::i64));
12097 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
12098 MachinePointerInfo(TrmpAddr, 12),
12101 // Jump to the nested function.
12102 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
12103 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
12104 DAG.getConstant(20, MVT::i64));
12105 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
12106 Addr, MachinePointerInfo(TrmpAddr, 20),
12109 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
12110 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
12111 DAG.getConstant(22, MVT::i64));
12112 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
12113 MachinePointerInfo(TrmpAddr, 22),
12116 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6);
12118 const Function *Func =
12119 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
12120 CallingConv::ID CC = Func->getCallingConv();
12125 llvm_unreachable("Unsupported calling convention");
12126 case CallingConv::C:
12127 case CallingConv::X86_StdCall: {
12128 // Pass 'nest' parameter in ECX.
12129 // Must be kept in sync with X86CallingConv.td
12130 NestReg = X86::ECX;
12132 // Check that ECX wasn't needed by an 'inreg' parameter.
12133 FunctionType *FTy = Func->getFunctionType();
12134 const AttributeSet &Attrs = Func->getAttributes();
12136 if (!Attrs.isEmpty() && !Func->isVarArg()) {
12137 unsigned InRegCount = 0;
12140 for (FunctionType::param_iterator I = FTy->param_begin(),
12141 E = FTy->param_end(); I != E; ++I, ++Idx)
12142 if (Attrs.hasAttribute(Idx, Attribute::InReg))
12143 // FIXME: should only count parameters that are lowered to integers.
12144 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
12146 if (InRegCount > 2) {
12147 report_fatal_error("Nest register in use - reduce number of inreg"
12153 case CallingConv::X86_FastCall:
12154 case CallingConv::X86_ThisCall:
12155 case CallingConv::Fast:
12156 // Pass 'nest' parameter in EAX.
12157 // Must be kept in sync with X86CallingConv.td
12158 NestReg = X86::EAX;
12162 SDValue OutChains[4];
12163 SDValue Addr, Disp;
12165 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
12166 DAG.getConstant(10, MVT::i32));
12167 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
12169 // This is storing the opcode for MOV32ri.
12170 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
12171 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
12172 OutChains[0] = DAG.getStore(Root, dl,
12173 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
12174 Trmp, MachinePointerInfo(TrmpAddr),
12177 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
12178 DAG.getConstant(1, MVT::i32));
12179 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
12180 MachinePointerInfo(TrmpAddr, 1),
12183 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
12184 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
12185 DAG.getConstant(5, MVT::i32));
12186 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
12187 MachinePointerInfo(TrmpAddr, 5),
12190 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
12191 DAG.getConstant(6, MVT::i32));
12192 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
12193 MachinePointerInfo(TrmpAddr, 6),
12196 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4);
12200 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
12201 SelectionDAG &DAG) const {
12203 The rounding mode is in bits 11:10 of FPSR, and has the following
12205 00 Round to nearest
12210 FLT_ROUNDS, on the other hand, expects the following:
12217 To perform the conversion, we do:
12218 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
12221 MachineFunction &MF = DAG.getMachineFunction();
12222 const TargetMachine &TM = MF.getTarget();
12223 const TargetFrameLowering &TFI = *TM.getFrameLowering();
12224 unsigned StackAlignment = TFI.getStackAlignment();
12225 EVT VT = Op.getValueType();
12228 // Save FP Control Word to stack slot
12229 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
12230 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
12232 MachineMemOperand *MMO =
12233 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12234 MachineMemOperand::MOStore, 2, 2);
12236 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
12237 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
12238 DAG.getVTList(MVT::Other),
12239 Ops, array_lengthof(Ops), MVT::i16,
12242 // Load FP Control Word from stack slot
12243 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
12244 MachinePointerInfo(), false, false, false, 0);
12246 // Transform as necessary
12248 DAG.getNode(ISD::SRL, DL, MVT::i16,
12249 DAG.getNode(ISD::AND, DL, MVT::i16,
12250 CWD, DAG.getConstant(0x800, MVT::i16)),
12251 DAG.getConstant(11, MVT::i8));
12253 DAG.getNode(ISD::SRL, DL, MVT::i16,
12254 DAG.getNode(ISD::AND, DL, MVT::i16,
12255 CWD, DAG.getConstant(0x400, MVT::i16)),
12256 DAG.getConstant(9, MVT::i8));
12259 DAG.getNode(ISD::AND, DL, MVT::i16,
12260 DAG.getNode(ISD::ADD, DL, MVT::i16,
12261 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
12262 DAG.getConstant(1, MVT::i16)),
12263 DAG.getConstant(3, MVT::i16));
12265 return DAG.getNode((VT.getSizeInBits() < 16 ?
12266 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
12269 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
12270 EVT VT = Op.getValueType();
12272 unsigned NumBits = VT.getSizeInBits();
12275 Op = Op.getOperand(0);
12276 if (VT == MVT::i8) {
12277 // Zero extend to i32 since there is not an i8 bsr.
12279 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
12282 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
12283 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
12284 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
12286 // If src is zero (i.e. bsr sets ZF), returns NumBits.
12289 DAG.getConstant(NumBits+NumBits-1, OpVT),
12290 DAG.getConstant(X86::COND_E, MVT::i8),
12293 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
12295 // Finally xor with NumBits-1.
12296 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
12299 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
12303 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
12304 EVT VT = Op.getValueType();
12306 unsigned NumBits = VT.getSizeInBits();
12309 Op = Op.getOperand(0);
12310 if (VT == MVT::i8) {
12311 // Zero extend to i32 since there is not an i8 bsr.
12313 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
12316 // Issue a bsr (scan bits in reverse).
12317 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
12318 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
12320 // And xor with NumBits-1.
12321 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
12324 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
12328 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
12329 EVT VT = Op.getValueType();
12330 unsigned NumBits = VT.getSizeInBits();
12332 Op = Op.getOperand(0);
12334 // Issue a bsf (scan bits forward) which also sets EFLAGS.
12335 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
12336 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
12338 // If src is zero (i.e. bsf sets ZF), returns NumBits.
12341 DAG.getConstant(NumBits, VT),
12342 DAG.getConstant(X86::COND_E, MVT::i8),
12345 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops, array_lengthof(Ops));
12348 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
12349 // ones, and then concatenate the result back.
12350 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
12351 EVT VT = Op.getValueType();
12353 assert(VT.is256BitVector() && VT.isInteger() &&
12354 "Unsupported value type for operation");
12356 unsigned NumElems = VT.getVectorNumElements();
12359 // Extract the LHS vectors
12360 SDValue LHS = Op.getOperand(0);
12361 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
12362 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
12364 // Extract the RHS vectors
12365 SDValue RHS = Op.getOperand(1);
12366 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
12367 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
12369 MVT EltVT = VT.getVectorElementType().getSimpleVT();
12370 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
12372 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
12373 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
12374 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
12377 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
12378 assert(Op.getValueType().is256BitVector() &&
12379 Op.getValueType().isInteger() &&
12380 "Only handle AVX 256-bit vector integer operation");
12381 return Lower256IntArith(Op, DAG);
12384 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
12385 assert(Op.getValueType().is256BitVector() &&
12386 Op.getValueType().isInteger() &&
12387 "Only handle AVX 256-bit vector integer operation");
12388 return Lower256IntArith(Op, DAG);
12391 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
12392 SelectionDAG &DAG) {
12394 EVT VT = Op.getValueType();
12396 // Decompose 256-bit ops into smaller 128-bit ops.
12397 if (VT.is256BitVector() && !Subtarget->hasInt256())
12398 return Lower256IntArith(Op, DAG);
12400 SDValue A = Op.getOperand(0);
12401 SDValue B = Op.getOperand(1);
12403 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
12404 if (VT == MVT::v4i32) {
12405 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
12406 "Should not custom lower when pmuldq is available!");
12408 // Extract the odd parts.
12409 static const int UnpackMask[] = { 1, -1, 3, -1 };
12410 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
12411 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
12413 // Multiply the even parts.
12414 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
12415 // Now multiply odd parts.
12416 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
12418 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
12419 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
12421 // Merge the two vectors back together with a shuffle. This expands into 2
12423 static const int ShufMask[] = { 0, 4, 2, 6 };
12424 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
12427 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
12428 "Only know how to lower V2I64/V4I64/V8I64 multiply");
12430 // Ahi = psrlqi(a, 32);
12431 // Bhi = psrlqi(b, 32);
12433 // AloBlo = pmuludq(a, b);
12434 // AloBhi = pmuludq(a, Bhi);
12435 // AhiBlo = pmuludq(Ahi, b);
12437 // AloBhi = psllqi(AloBhi, 32);
12438 // AhiBlo = psllqi(AhiBlo, 32);
12439 // return AloBlo + AloBhi + AhiBlo;
12441 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
12442 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
12444 // Bit cast to 32-bit vectors for MULUDQ
12445 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
12446 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
12447 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
12448 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
12449 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
12450 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
12452 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
12453 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
12454 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
12456 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
12457 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
12459 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
12460 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
12463 static SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG) {
12464 EVT VT = Op.getValueType();
12465 EVT EltTy = VT.getVectorElementType();
12466 unsigned NumElts = VT.getVectorNumElements();
12467 SDValue N0 = Op.getOperand(0);
12470 // Lower sdiv X, pow2-const.
12471 BuildVectorSDNode *C = dyn_cast<BuildVectorSDNode>(Op.getOperand(1));
12475 APInt SplatValue, SplatUndef;
12476 unsigned SplatBitSize;
12478 if (!C->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
12480 EltTy.getSizeInBits() < SplatBitSize)
12483 if ((SplatValue != 0) &&
12484 (SplatValue.isPowerOf2() || (-SplatValue).isPowerOf2())) {
12485 unsigned Lg2 = SplatValue.countTrailingZeros();
12486 // Splat the sign bit.
12487 SmallVector<SDValue, 16> Sz(NumElts,
12488 DAG.getConstant(EltTy.getSizeInBits() - 1,
12490 SDValue SGN = DAG.getNode(ISD::SRA, dl, VT, N0,
12491 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Sz[0],
12493 // Add (N0 < 0) ? abs2 - 1 : 0;
12494 SmallVector<SDValue, 16> Amt(NumElts,
12495 DAG.getConstant(EltTy.getSizeInBits() - Lg2,
12497 SDValue SRL = DAG.getNode(ISD::SRL, dl, VT, SGN,
12498 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Amt[0],
12500 SDValue ADD = DAG.getNode(ISD::ADD, dl, VT, N0, SRL);
12501 SmallVector<SDValue, 16> Lg2Amt(NumElts, DAG.getConstant(Lg2, EltTy));
12502 SDValue SRA = DAG.getNode(ISD::SRA, dl, VT, ADD,
12503 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Lg2Amt[0],
12506 // If we're dividing by a positive value, we're done. Otherwise, we must
12507 // negate the result.
12508 if (SplatValue.isNonNegative())
12511 SmallVector<SDValue, 16> V(NumElts, DAG.getConstant(0, EltTy));
12512 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], NumElts);
12513 return DAG.getNode(ISD::SUB, dl, VT, Zero, SRA);
12518 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
12519 const X86Subtarget *Subtarget) {
12520 EVT VT = Op.getValueType();
12522 SDValue R = Op.getOperand(0);
12523 SDValue Amt = Op.getOperand(1);
12525 // Optimize shl/srl/sra with constant shift amount.
12526 if (isSplatVector(Amt.getNode())) {
12527 SDValue SclrAmt = Amt->getOperand(0);
12528 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
12529 uint64_t ShiftAmt = C->getZExtValue();
12531 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
12532 (Subtarget->hasInt256() &&
12533 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16)) ||
12534 (Subtarget->hasAVX512() &&
12535 (VT == MVT::v8i64 || VT == MVT::v16i32))) {
12536 if (Op.getOpcode() == ISD::SHL)
12537 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
12539 if (Op.getOpcode() == ISD::SRL)
12540 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
12542 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
12543 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
12547 if (VT == MVT::v16i8) {
12548 if (Op.getOpcode() == ISD::SHL) {
12549 // Make a large shift.
12550 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
12551 MVT::v8i16, R, ShiftAmt,
12553 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
12554 // Zero out the rightmost bits.
12555 SmallVector<SDValue, 16> V(16,
12556 DAG.getConstant(uint8_t(-1U << ShiftAmt),
12558 return DAG.getNode(ISD::AND, dl, VT, SHL,
12559 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
12561 if (Op.getOpcode() == ISD::SRL) {
12562 // Make a large shift.
12563 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
12564 MVT::v8i16, R, ShiftAmt,
12566 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
12567 // Zero out the leftmost bits.
12568 SmallVector<SDValue, 16> V(16,
12569 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
12571 return DAG.getNode(ISD::AND, dl, VT, SRL,
12572 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
12574 if (Op.getOpcode() == ISD::SRA) {
12575 if (ShiftAmt == 7) {
12576 // R s>> 7 === R s< 0
12577 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
12578 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
12581 // R s>> a === ((R u>> a) ^ m) - m
12582 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
12583 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
12585 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16);
12586 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
12587 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
12590 llvm_unreachable("Unknown shift opcode.");
12593 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
12594 if (Op.getOpcode() == ISD::SHL) {
12595 // Make a large shift.
12596 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
12597 MVT::v16i16, R, ShiftAmt,
12599 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
12600 // Zero out the rightmost bits.
12601 SmallVector<SDValue, 32> V(32,
12602 DAG.getConstant(uint8_t(-1U << ShiftAmt),
12604 return DAG.getNode(ISD::AND, dl, VT, SHL,
12605 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
12607 if (Op.getOpcode() == ISD::SRL) {
12608 // Make a large shift.
12609 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
12610 MVT::v16i16, R, ShiftAmt,
12612 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
12613 // Zero out the leftmost bits.
12614 SmallVector<SDValue, 32> V(32,
12615 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
12617 return DAG.getNode(ISD::AND, dl, VT, SRL,
12618 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
12620 if (Op.getOpcode() == ISD::SRA) {
12621 if (ShiftAmt == 7) {
12622 // R s>> 7 === R s< 0
12623 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
12624 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
12627 // R s>> a === ((R u>> a) ^ m) - m
12628 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
12629 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
12631 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32);
12632 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
12633 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
12636 llvm_unreachable("Unknown shift opcode.");
12641 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
12642 if (!Subtarget->is64Bit() &&
12643 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
12644 Amt.getOpcode() == ISD::BITCAST &&
12645 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
12646 Amt = Amt.getOperand(0);
12647 unsigned Ratio = Amt.getValueType().getVectorNumElements() /
12648 VT.getVectorNumElements();
12649 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
12650 uint64_t ShiftAmt = 0;
12651 for (unsigned i = 0; i != Ratio; ++i) {
12652 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
12656 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
12658 // Check remaining shift amounts.
12659 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
12660 uint64_t ShAmt = 0;
12661 for (unsigned j = 0; j != Ratio; ++j) {
12662 ConstantSDNode *C =
12663 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
12667 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
12669 if (ShAmt != ShiftAmt)
12672 switch (Op.getOpcode()) {
12674 llvm_unreachable("Unknown shift opcode!");
12676 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
12679 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
12682 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
12690 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
12691 const X86Subtarget* Subtarget) {
12692 EVT VT = Op.getValueType();
12694 SDValue R = Op.getOperand(0);
12695 SDValue Amt = Op.getOperand(1);
12697 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
12698 VT == MVT::v4i32 || VT == MVT::v8i16 ||
12699 (Subtarget->hasInt256() &&
12700 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
12701 VT == MVT::v8i32 || VT == MVT::v16i16)) ||
12702 (Subtarget->hasAVX512() && (VT == MVT::v8i64 || VT == MVT::v16i32))) {
12704 EVT EltVT = VT.getVectorElementType();
12706 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
12707 unsigned NumElts = VT.getVectorNumElements();
12709 for (i = 0; i != NumElts; ++i) {
12710 if (Amt.getOperand(i).getOpcode() == ISD::UNDEF)
12714 for (j = i; j != NumElts; ++j) {
12715 SDValue Arg = Amt.getOperand(j);
12716 if (Arg.getOpcode() == ISD::UNDEF) continue;
12717 if (Arg != Amt.getOperand(i))
12720 if (i != NumElts && j == NumElts)
12721 BaseShAmt = Amt.getOperand(i);
12723 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
12724 Amt = Amt.getOperand(0);
12725 if (Amt.getOpcode() == ISD::VECTOR_SHUFFLE &&
12726 cast<ShuffleVectorSDNode>(Amt)->isSplat()) {
12727 SDValue InVec = Amt.getOperand(0);
12728 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
12729 unsigned NumElts = InVec.getValueType().getVectorNumElements();
12731 for (; i != NumElts; ++i) {
12732 SDValue Arg = InVec.getOperand(i);
12733 if (Arg.getOpcode() == ISD::UNDEF) continue;
12737 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
12738 if (ConstantSDNode *C =
12739 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
12740 unsigned SplatIdx =
12741 cast<ShuffleVectorSDNode>(Amt)->getSplatIndex();
12742 if (C->getZExtValue() == SplatIdx)
12743 BaseShAmt = InVec.getOperand(1);
12746 if (BaseShAmt.getNode() == 0)
12747 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Amt,
12748 DAG.getIntPtrConstant(0));
12752 if (BaseShAmt.getNode()) {
12753 if (EltVT.bitsGT(MVT::i32))
12754 BaseShAmt = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BaseShAmt);
12755 else if (EltVT.bitsLT(MVT::i32))
12756 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
12758 switch (Op.getOpcode()) {
12760 llvm_unreachable("Unknown shift opcode!");
12762 switch (VT.getSimpleVT().SimpleTy) {
12763 default: return SDValue();
12772 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
12775 switch (VT.getSimpleVT().SimpleTy) {
12776 default: return SDValue();
12783 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
12786 switch (VT.getSimpleVT().SimpleTy) {
12787 default: return SDValue();
12796 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);
12802 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
12803 if (!Subtarget->is64Bit() &&
12804 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64) ||
12805 (Subtarget->hasAVX512() && VT == MVT::v8i64)) &&
12806 Amt.getOpcode() == ISD::BITCAST &&
12807 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
12808 Amt = Amt.getOperand(0);
12809 unsigned Ratio = Amt.getValueType().getVectorNumElements() /
12810 VT.getVectorNumElements();
12811 std::vector<SDValue> Vals(Ratio);
12812 for (unsigned i = 0; i != Ratio; ++i)
12813 Vals[i] = Amt.getOperand(i);
12814 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
12815 for (unsigned j = 0; j != Ratio; ++j)
12816 if (Vals[j] != Amt.getOperand(i + j))
12819 switch (Op.getOpcode()) {
12821 llvm_unreachable("Unknown shift opcode!");
12823 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1));
12825 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1));
12827 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1));
12834 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
12835 SelectionDAG &DAG) {
12837 EVT VT = Op.getValueType();
12839 SDValue R = Op.getOperand(0);
12840 SDValue Amt = Op.getOperand(1);
12843 if (!Subtarget->hasSSE2())
12846 V = LowerScalarImmediateShift(Op, DAG, Subtarget);
12850 V = LowerScalarVariableShift(Op, DAG, Subtarget);
12854 if (Subtarget->hasAVX512() && (VT == MVT::v16i32 || VT == MVT::v8i64))
12856 // AVX2 has VPSLLV/VPSRAV/VPSRLV.
12857 if (Subtarget->hasInt256()) {
12858 if (Op.getOpcode() == ISD::SRL &&
12859 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
12860 VT == MVT::v4i64 || VT == MVT::v8i32))
12862 if (Op.getOpcode() == ISD::SHL &&
12863 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
12864 VT == MVT::v4i64 || VT == MVT::v8i32))
12866 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
12870 // Lower SHL with variable shift amount.
12871 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
12872 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
12874 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
12875 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
12876 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
12877 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
12879 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
12880 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
12883 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
12884 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
12886 // Turn 'a' into a mask suitable for VSELECT
12887 SDValue VSelM = DAG.getConstant(0x80, VT);
12888 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
12889 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
12891 SDValue CM1 = DAG.getConstant(0x0f, VT);
12892 SDValue CM2 = DAG.getConstant(0x3f, VT);
12894 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
12895 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
12896 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 4, DAG);
12897 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
12898 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
12901 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
12902 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
12903 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
12905 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
12906 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
12907 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 2, DAG);
12908 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
12909 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
12912 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
12913 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
12914 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
12916 // return VSELECT(r, r+r, a);
12917 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
12918 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
12922 // Decompose 256-bit shifts into smaller 128-bit shifts.
12923 if (VT.is256BitVector()) {
12924 unsigned NumElems = VT.getVectorNumElements();
12925 MVT EltVT = VT.getVectorElementType().getSimpleVT();
12926 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
12928 // Extract the two vectors
12929 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
12930 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
12932 // Recreate the shift amount vectors
12933 SDValue Amt1, Amt2;
12934 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
12935 // Constant shift amount
12936 SmallVector<SDValue, 4> Amt1Csts;
12937 SmallVector<SDValue, 4> Amt2Csts;
12938 for (unsigned i = 0; i != NumElems/2; ++i)
12939 Amt1Csts.push_back(Amt->getOperand(i));
12940 for (unsigned i = NumElems/2; i != NumElems; ++i)
12941 Amt2Csts.push_back(Amt->getOperand(i));
12943 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
12944 &Amt1Csts[0], NumElems/2);
12945 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
12946 &Amt2Csts[0], NumElems/2);
12948 // Variable shift amount
12949 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
12950 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
12953 // Issue new vector shifts for the smaller types
12954 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
12955 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
12957 // Concatenate the result back
12958 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
12964 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
12965 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
12966 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
12967 // looks for this combo and may remove the "setcc" instruction if the "setcc"
12968 // has only one use.
12969 SDNode *N = Op.getNode();
12970 SDValue LHS = N->getOperand(0);
12971 SDValue RHS = N->getOperand(1);
12972 unsigned BaseOp = 0;
12975 switch (Op.getOpcode()) {
12976 default: llvm_unreachable("Unknown ovf instruction!");
12978 // A subtract of one will be selected as a INC. Note that INC doesn't
12979 // set CF, so we can't do this for UADDO.
12980 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
12982 BaseOp = X86ISD::INC;
12983 Cond = X86::COND_O;
12986 BaseOp = X86ISD::ADD;
12987 Cond = X86::COND_O;
12990 BaseOp = X86ISD::ADD;
12991 Cond = X86::COND_B;
12994 // A subtract of one will be selected as a DEC. Note that DEC doesn't
12995 // set CF, so we can't do this for USUBO.
12996 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
12998 BaseOp = X86ISD::DEC;
12999 Cond = X86::COND_O;
13002 BaseOp = X86ISD::SUB;
13003 Cond = X86::COND_O;
13006 BaseOp = X86ISD::SUB;
13007 Cond = X86::COND_B;
13010 BaseOp = X86ISD::SMUL;
13011 Cond = X86::COND_O;
13013 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
13014 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
13016 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
13019 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13020 DAG.getConstant(X86::COND_O, MVT::i32),
13021 SDValue(Sum.getNode(), 2));
13023 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
13027 // Also sets EFLAGS.
13028 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
13029 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
13032 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
13033 DAG.getConstant(Cond, MVT::i32),
13034 SDValue(Sum.getNode(), 1));
13036 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
13039 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
13040 SelectionDAG &DAG) const {
13042 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
13043 EVT VT = Op.getValueType();
13045 if (!Subtarget->hasSSE2() || !VT.isVector())
13048 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
13049 ExtraVT.getScalarType().getSizeInBits();
13051 switch (VT.getSimpleVT().SimpleTy) {
13052 default: return SDValue();
13055 if (!Subtarget->hasFp256())
13057 if (!Subtarget->hasInt256()) {
13058 // needs to be split
13059 unsigned NumElems = VT.getVectorNumElements();
13061 // Extract the LHS vectors
13062 SDValue LHS = Op.getOperand(0);
13063 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
13064 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
13066 MVT EltVT = VT.getVectorElementType().getSimpleVT();
13067 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
13069 EVT ExtraEltVT = ExtraVT.getVectorElementType();
13070 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
13071 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
13073 SDValue Extra = DAG.getValueType(ExtraVT);
13075 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
13076 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
13078 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
13083 // (sext (vzext x)) -> (vsext x)
13084 SDValue Op0 = Op.getOperand(0);
13085 SDValue Op00 = Op0.getOperand(0);
13087 // Hopefully, this VECTOR_SHUFFLE is just a VZEXT.
13088 if (Op0.getOpcode() == ISD::BITCAST &&
13089 Op00.getOpcode() == ISD::VECTOR_SHUFFLE)
13090 Tmp1 = LowerVectorIntExtend(Op00, Subtarget, DAG);
13091 if (Tmp1.getNode()) {
13092 SDValue Tmp1Op0 = Tmp1.getOperand(0);
13093 assert(Tmp1Op0.getOpcode() == X86ISD::VZEXT &&
13094 "This optimization is invalid without a VZEXT.");
13095 return DAG.getNode(X86ISD::VSEXT, dl, VT, Tmp1Op0.getOperand(0));
13098 // If the above didn't work, then just use Shift-Left + Shift-Right.
13099 Tmp1 = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, Op0, BitsDiff,
13101 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, Tmp1, BitsDiff,
13107 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
13108 SelectionDAG &DAG) {
13110 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
13111 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
13112 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
13113 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
13115 // The only fence that needs an instruction is a sequentially-consistent
13116 // cross-thread fence.
13117 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
13118 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
13119 // no-sse2). There isn't any reason to disable it if the target processor
13121 if (Subtarget->hasSSE2() || Subtarget->is64Bit())
13122 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
13124 SDValue Chain = Op.getOperand(0);
13125 SDValue Zero = DAG.getConstant(0, MVT::i32);
13127 DAG.getRegister(X86::ESP, MVT::i32), // Base
13128 DAG.getTargetConstant(1, MVT::i8), // Scale
13129 DAG.getRegister(0, MVT::i32), // Index
13130 DAG.getTargetConstant(0, MVT::i32), // Disp
13131 DAG.getRegister(0, MVT::i32), // Segment.
13135 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
13136 return SDValue(Res, 0);
13139 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
13140 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
13143 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
13144 SelectionDAG &DAG) {
13145 EVT T = Op.getValueType();
13149 switch(T.getSimpleVT().SimpleTy) {
13150 default: llvm_unreachable("Invalid value type!");
13151 case MVT::i8: Reg = X86::AL; size = 1; break;
13152 case MVT::i16: Reg = X86::AX; size = 2; break;
13153 case MVT::i32: Reg = X86::EAX; size = 4; break;
13155 assert(Subtarget->is64Bit() && "Node not type legal!");
13156 Reg = X86::RAX; size = 8;
13159 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
13160 Op.getOperand(2), SDValue());
13161 SDValue Ops[] = { cpIn.getValue(0),
13164 DAG.getTargetConstant(size, MVT::i8),
13165 cpIn.getValue(1) };
13166 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
13167 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
13168 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
13169 Ops, array_lengthof(Ops), T, MMO);
13171 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
13175 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
13176 SelectionDAG &DAG) {
13177 assert(Subtarget->is64Bit() && "Result not type legalized?");
13178 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
13179 SDValue TheChain = Op.getOperand(0);
13181 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
13182 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
13183 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
13185 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
13186 DAG.getConstant(32, MVT::i8));
13188 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
13191 return DAG.getMergeValues(Ops, array_lengthof(Ops), dl);
13194 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
13195 SelectionDAG &DAG) {
13196 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
13197 MVT DstVT = Op.getSimpleValueType();
13198 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
13199 Subtarget->hasMMX() && "Unexpected custom BITCAST");
13200 assert((DstVT == MVT::i64 ||
13201 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
13202 "Unexpected custom BITCAST");
13203 // i64 <=> MMX conversions are Legal.
13204 if (SrcVT==MVT::i64 && DstVT.isVector())
13206 if (DstVT==MVT::i64 && SrcVT.isVector())
13208 // MMX <=> MMX conversions are Legal.
13209 if (SrcVT.isVector() && DstVT.isVector())
13211 // All other conversions need to be expanded.
13215 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
13216 SDNode *Node = Op.getNode();
13218 EVT T = Node->getValueType(0);
13219 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
13220 DAG.getConstant(0, T), Node->getOperand(2));
13221 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
13222 cast<AtomicSDNode>(Node)->getMemoryVT(),
13223 Node->getOperand(0),
13224 Node->getOperand(1), negOp,
13225 cast<AtomicSDNode>(Node)->getSrcValue(),
13226 cast<AtomicSDNode>(Node)->getAlignment(),
13227 cast<AtomicSDNode>(Node)->getOrdering(),
13228 cast<AtomicSDNode>(Node)->getSynchScope());
13231 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
13232 SDNode *Node = Op.getNode();
13234 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
13236 // Convert seq_cst store -> xchg
13237 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
13238 // FIXME: On 32-bit, store -> fist or movq would be more efficient
13239 // (The only way to get a 16-byte store is cmpxchg16b)
13240 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
13241 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
13242 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
13243 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
13244 cast<AtomicSDNode>(Node)->getMemoryVT(),
13245 Node->getOperand(0),
13246 Node->getOperand(1), Node->getOperand(2),
13247 cast<AtomicSDNode>(Node)->getMemOperand(),
13248 cast<AtomicSDNode>(Node)->getOrdering(),
13249 cast<AtomicSDNode>(Node)->getSynchScope());
13250 return Swap.getValue(1);
13252 // Other atomic stores have a simple pattern.
13256 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
13257 EVT VT = Op.getNode()->getValueType(0);
13259 // Let legalize expand this if it isn't a legal type yet.
13260 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
13263 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
13266 bool ExtraOp = false;
13267 switch (Op.getOpcode()) {
13268 default: llvm_unreachable("Invalid code");
13269 case ISD::ADDC: Opc = X86ISD::ADD; break;
13270 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
13271 case ISD::SUBC: Opc = X86ISD::SUB; break;
13272 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
13276 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
13278 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
13279 Op.getOperand(1), Op.getOperand(2));
13282 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
13283 SelectionDAG &DAG) {
13284 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
13286 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
13287 // which returns the values as { float, float } (in XMM0) or
13288 // { double, double } (which is returned in XMM0, XMM1).
13290 SDValue Arg = Op.getOperand(0);
13291 EVT ArgVT = Arg.getValueType();
13292 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
13294 TargetLowering::ArgListTy Args;
13295 TargetLowering::ArgListEntry Entry;
13299 Entry.isSExt = false;
13300 Entry.isZExt = false;
13301 Args.push_back(Entry);
13303 bool isF64 = ArgVT == MVT::f64;
13304 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
13305 // the small struct {f32, f32} is returned in (eax, edx). For f64,
13306 // the results are returned via SRet in memory.
13307 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
13308 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13309 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
13311 Type *RetTy = isF64
13312 ? (Type*)StructType::get(ArgTy, ArgTy, NULL)
13313 : (Type*)VectorType::get(ArgTy, 4);
13315 CallLoweringInfo CLI(DAG.getEntryNode(), RetTy,
13316 false, false, false, false, 0,
13317 CallingConv::C, /*isTaillCall=*/false,
13318 /*doesNotRet=*/false, /*isReturnValueUsed*/true,
13319 Callee, Args, DAG, dl);
13320 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
13323 // Returned in xmm0 and xmm1.
13324 return CallResult.first;
13326 // Returned in bits 0:31 and 32:64 xmm0.
13327 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
13328 CallResult.first, DAG.getIntPtrConstant(0));
13329 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
13330 CallResult.first, DAG.getIntPtrConstant(1));
13331 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
13332 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
13335 /// LowerOperation - Provide custom lowering hooks for some operations.
13337 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
13338 switch (Op.getOpcode()) {
13339 default: llvm_unreachable("Should not custom lower this!");
13340 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
13341 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
13342 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op, Subtarget, DAG);
13343 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
13344 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
13345 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
13346 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
13347 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
13348 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
13349 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
13350 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
13351 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
13352 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
13353 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
13354 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
13355 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
13356 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
13357 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
13358 case ISD::SHL_PARTS:
13359 case ISD::SRA_PARTS:
13360 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
13361 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
13362 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
13363 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
13364 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
13365 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
13366 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
13367 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
13368 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
13369 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
13370 case ISD::FABS: return LowerFABS(Op, DAG);
13371 case ISD::FNEG: return LowerFNEG(Op, DAG);
13372 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
13373 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
13374 case ISD::SETCC: return LowerSETCC(Op, DAG);
13375 case ISD::SELECT: return LowerSELECT(Op, DAG);
13376 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
13377 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
13378 case ISD::VASTART: return LowerVASTART(Op, DAG);
13379 case ISD::VAARG: return LowerVAARG(Op, DAG);
13380 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
13381 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
13382 case ISD::INTRINSIC_VOID:
13383 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
13384 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
13385 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
13386 case ISD::FRAME_TO_ARGS_OFFSET:
13387 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
13388 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
13389 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
13390 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
13391 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
13392 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
13393 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
13394 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
13395 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
13396 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
13397 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
13398 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
13401 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
13407 case ISD::UMULO: return LowerXALUO(Op, DAG);
13408 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
13409 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
13413 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
13414 case ISD::ADD: return LowerADD(Op, DAG);
13415 case ISD::SUB: return LowerSUB(Op, DAG);
13416 case ISD::SDIV: return LowerSDIV(Op, DAG);
13417 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
13421 static void ReplaceATOMIC_LOAD(SDNode *Node,
13422 SmallVectorImpl<SDValue> &Results,
13423 SelectionDAG &DAG) {
13425 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
13427 // Convert wide load -> cmpxchg8b/cmpxchg16b
13428 // FIXME: On 32-bit, load -> fild or movq would be more efficient
13429 // (The only way to get a 16-byte load is cmpxchg16b)
13430 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment.
13431 SDValue Zero = DAG.getConstant(0, VT);
13432 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT,
13433 Node->getOperand(0),
13434 Node->getOperand(1), Zero, Zero,
13435 cast<AtomicSDNode>(Node)->getMemOperand(),
13436 cast<AtomicSDNode>(Node)->getOrdering(),
13437 cast<AtomicSDNode>(Node)->getSynchScope());
13438 Results.push_back(Swap.getValue(0));
13439 Results.push_back(Swap.getValue(1));
13443 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
13444 SelectionDAG &DAG, unsigned NewOp) {
13446 assert (Node->getValueType(0) == MVT::i64 &&
13447 "Only know how to expand i64 atomics");
13449 SDValue Chain = Node->getOperand(0);
13450 SDValue In1 = Node->getOperand(1);
13451 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
13452 Node->getOperand(2), DAG.getIntPtrConstant(0));
13453 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
13454 Node->getOperand(2), DAG.getIntPtrConstant(1));
13455 SDValue Ops[] = { Chain, In1, In2L, In2H };
13456 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
13458 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, array_lengthof(Ops), MVT::i64,
13459 cast<MemSDNode>(Node)->getMemOperand());
13460 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
13461 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
13462 Results.push_back(Result.getValue(2));
13465 /// ReplaceNodeResults - Replace a node with an illegal result type
13466 /// with a new node built out of custom code.
13467 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
13468 SmallVectorImpl<SDValue>&Results,
13469 SelectionDAG &DAG) const {
13471 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13472 switch (N->getOpcode()) {
13474 llvm_unreachable("Do not know how to custom type legalize this operation!");
13475 case ISD::SIGN_EXTEND_INREG:
13480 // We don't want to expand or promote these.
13482 case ISD::FP_TO_SINT:
13483 case ISD::FP_TO_UINT: {
13484 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
13486 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
13489 std::pair<SDValue,SDValue> Vals =
13490 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
13491 SDValue FIST = Vals.first, StackSlot = Vals.second;
13492 if (FIST.getNode() != 0) {
13493 EVT VT = N->getValueType(0);
13494 // Return a load from the stack slot.
13495 if (StackSlot.getNode() != 0)
13496 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
13497 MachinePointerInfo(),
13498 false, false, false, 0));
13500 Results.push_back(FIST);
13504 case ISD::UINT_TO_FP: {
13505 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
13506 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
13507 N->getValueType(0) != MVT::v2f32)
13509 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
13511 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
13513 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
13514 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
13515 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
13516 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
13517 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
13518 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
13521 case ISD::FP_ROUND: {
13522 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
13524 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
13525 Results.push_back(V);
13528 case ISD::READCYCLECOUNTER: {
13529 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
13530 SDValue TheChain = N->getOperand(0);
13531 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
13532 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
13534 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
13536 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
13537 SDValue Ops[] = { eax, edx };
13538 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops,
13539 array_lengthof(Ops)));
13540 Results.push_back(edx.getValue(1));
13543 case ISD::ATOMIC_CMP_SWAP: {
13544 EVT T = N->getValueType(0);
13545 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
13546 bool Regs64bit = T == MVT::i128;
13547 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
13548 SDValue cpInL, cpInH;
13549 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
13550 DAG.getConstant(0, HalfT));
13551 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
13552 DAG.getConstant(1, HalfT));
13553 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
13554 Regs64bit ? X86::RAX : X86::EAX,
13556 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
13557 Regs64bit ? X86::RDX : X86::EDX,
13558 cpInH, cpInL.getValue(1));
13559 SDValue swapInL, swapInH;
13560 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
13561 DAG.getConstant(0, HalfT));
13562 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
13563 DAG.getConstant(1, HalfT));
13564 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
13565 Regs64bit ? X86::RBX : X86::EBX,
13566 swapInL, cpInH.getValue(1));
13567 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
13568 Regs64bit ? X86::RCX : X86::ECX,
13569 swapInH, swapInL.getValue(1));
13570 SDValue Ops[] = { swapInH.getValue(0),
13572 swapInH.getValue(1) };
13573 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
13574 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
13575 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
13576 X86ISD::LCMPXCHG8_DAG;
13577 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys,
13578 Ops, array_lengthof(Ops), T, MMO);
13579 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
13580 Regs64bit ? X86::RAX : X86::EAX,
13581 HalfT, Result.getValue(1));
13582 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
13583 Regs64bit ? X86::RDX : X86::EDX,
13584 HalfT, cpOutL.getValue(2));
13585 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
13586 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF, 2));
13587 Results.push_back(cpOutH.getValue(1));
13590 case ISD::ATOMIC_LOAD_ADD:
13591 case ISD::ATOMIC_LOAD_AND:
13592 case ISD::ATOMIC_LOAD_NAND:
13593 case ISD::ATOMIC_LOAD_OR:
13594 case ISD::ATOMIC_LOAD_SUB:
13595 case ISD::ATOMIC_LOAD_XOR:
13596 case ISD::ATOMIC_LOAD_MAX:
13597 case ISD::ATOMIC_LOAD_MIN:
13598 case ISD::ATOMIC_LOAD_UMAX:
13599 case ISD::ATOMIC_LOAD_UMIN:
13600 case ISD::ATOMIC_SWAP: {
13602 switch (N->getOpcode()) {
13603 default: llvm_unreachable("Unexpected opcode");
13604 case ISD::ATOMIC_LOAD_ADD:
13605 Opc = X86ISD::ATOMADD64_DAG;
13607 case ISD::ATOMIC_LOAD_AND:
13608 Opc = X86ISD::ATOMAND64_DAG;
13610 case ISD::ATOMIC_LOAD_NAND:
13611 Opc = X86ISD::ATOMNAND64_DAG;
13613 case ISD::ATOMIC_LOAD_OR:
13614 Opc = X86ISD::ATOMOR64_DAG;
13616 case ISD::ATOMIC_LOAD_SUB:
13617 Opc = X86ISD::ATOMSUB64_DAG;
13619 case ISD::ATOMIC_LOAD_XOR:
13620 Opc = X86ISD::ATOMXOR64_DAG;
13622 case ISD::ATOMIC_LOAD_MAX:
13623 Opc = X86ISD::ATOMMAX64_DAG;
13625 case ISD::ATOMIC_LOAD_MIN:
13626 Opc = X86ISD::ATOMMIN64_DAG;
13628 case ISD::ATOMIC_LOAD_UMAX:
13629 Opc = X86ISD::ATOMUMAX64_DAG;
13631 case ISD::ATOMIC_LOAD_UMIN:
13632 Opc = X86ISD::ATOMUMIN64_DAG;
13634 case ISD::ATOMIC_SWAP:
13635 Opc = X86ISD::ATOMSWAP64_DAG;
13638 ReplaceATOMIC_BINARY_64(N, Results, DAG, Opc);
13641 case ISD::ATOMIC_LOAD:
13642 ReplaceATOMIC_LOAD(N, Results, DAG);
13646 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
13648 default: return NULL;
13649 case X86ISD::BSF: return "X86ISD::BSF";
13650 case X86ISD::BSR: return "X86ISD::BSR";
13651 case X86ISD::SHLD: return "X86ISD::SHLD";
13652 case X86ISD::SHRD: return "X86ISD::SHRD";
13653 case X86ISD::FAND: return "X86ISD::FAND";
13654 case X86ISD::FANDN: return "X86ISD::FANDN";
13655 case X86ISD::FOR: return "X86ISD::FOR";
13656 case X86ISD::FXOR: return "X86ISD::FXOR";
13657 case X86ISD::FSRL: return "X86ISD::FSRL";
13658 case X86ISD::FILD: return "X86ISD::FILD";
13659 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
13660 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
13661 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
13662 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
13663 case X86ISD::FLD: return "X86ISD::FLD";
13664 case X86ISD::FST: return "X86ISD::FST";
13665 case X86ISD::CALL: return "X86ISD::CALL";
13666 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
13667 case X86ISD::BT: return "X86ISD::BT";
13668 case X86ISD::CMP: return "X86ISD::CMP";
13669 case X86ISD::COMI: return "X86ISD::COMI";
13670 case X86ISD::UCOMI: return "X86ISD::UCOMI";
13671 case X86ISD::CMPM: return "X86ISD::CMPM";
13672 case X86ISD::CMPMU: return "X86ISD::CMPMU";
13673 case X86ISD::SETCC: return "X86ISD::SETCC";
13674 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
13675 case X86ISD::FSETCCsd: return "X86ISD::FSETCCsd";
13676 case X86ISD::FSETCCss: return "X86ISD::FSETCCss";
13677 case X86ISD::CMOV: return "X86ISD::CMOV";
13678 case X86ISD::BRCOND: return "X86ISD::BRCOND";
13679 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
13680 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
13681 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
13682 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
13683 case X86ISD::Wrapper: return "X86ISD::Wrapper";
13684 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
13685 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
13686 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
13687 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
13688 case X86ISD::PINSRB: return "X86ISD::PINSRB";
13689 case X86ISD::PINSRW: return "X86ISD::PINSRW";
13690 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
13691 case X86ISD::ANDNP: return "X86ISD::ANDNP";
13692 case X86ISD::PSIGN: return "X86ISD::PSIGN";
13693 case X86ISD::BLENDV: return "X86ISD::BLENDV";
13694 case X86ISD::BLENDI: return "X86ISD::BLENDI";
13695 case X86ISD::SUBUS: return "X86ISD::SUBUS";
13696 case X86ISD::HADD: return "X86ISD::HADD";
13697 case X86ISD::HSUB: return "X86ISD::HSUB";
13698 case X86ISD::FHADD: return "X86ISD::FHADD";
13699 case X86ISD::FHSUB: return "X86ISD::FHSUB";
13700 case X86ISD::UMAX: return "X86ISD::UMAX";
13701 case X86ISD::UMIN: return "X86ISD::UMIN";
13702 case X86ISD::SMAX: return "X86ISD::SMAX";
13703 case X86ISD::SMIN: return "X86ISD::SMIN";
13704 case X86ISD::FMAX: return "X86ISD::FMAX";
13705 case X86ISD::FMIN: return "X86ISD::FMIN";
13706 case X86ISD::FMAXC: return "X86ISD::FMAXC";
13707 case X86ISD::FMINC: return "X86ISD::FMINC";
13708 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
13709 case X86ISD::FRCP: return "X86ISD::FRCP";
13710 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
13711 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
13712 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
13713 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
13714 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
13715 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
13716 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
13717 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
13718 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
13719 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
13720 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
13721 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
13722 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
13723 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
13724 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
13725 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
13726 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
13727 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
13728 case X86ISD::VSEXT_MOVL: return "X86ISD::VSEXT_MOVL";
13729 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
13730 case X86ISD::VZEXT: return "X86ISD::VZEXT";
13731 case X86ISD::VSEXT: return "X86ISD::VSEXT";
13732 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
13733 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
13734 case X86ISD::VINSERT: return "X86ISD::VINSERT";
13735 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
13736 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
13737 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
13738 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
13739 case X86ISD::VSHL: return "X86ISD::VSHL";
13740 case X86ISD::VSRL: return "X86ISD::VSRL";
13741 case X86ISD::VSRA: return "X86ISD::VSRA";
13742 case X86ISD::VSHLI: return "X86ISD::VSHLI";
13743 case X86ISD::VSRLI: return "X86ISD::VSRLI";
13744 case X86ISD::VSRAI: return "X86ISD::VSRAI";
13745 case X86ISD::CMPP: return "X86ISD::CMPP";
13746 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
13747 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
13748 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
13749 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
13750 case X86ISD::ADD: return "X86ISD::ADD";
13751 case X86ISD::SUB: return "X86ISD::SUB";
13752 case X86ISD::ADC: return "X86ISD::ADC";
13753 case X86ISD::SBB: return "X86ISD::SBB";
13754 case X86ISD::SMUL: return "X86ISD::SMUL";
13755 case X86ISD::UMUL: return "X86ISD::UMUL";
13756 case X86ISD::INC: return "X86ISD::INC";
13757 case X86ISD::DEC: return "X86ISD::DEC";
13758 case X86ISD::OR: return "X86ISD::OR";
13759 case X86ISD::XOR: return "X86ISD::XOR";
13760 case X86ISD::AND: return "X86ISD::AND";
13761 case X86ISD::BLSI: return "X86ISD::BLSI";
13762 case X86ISD::BLSMSK: return "X86ISD::BLSMSK";
13763 case X86ISD::BLSR: return "X86ISD::BLSR";
13764 case X86ISD::BZHI: return "X86ISD::BZHI";
13765 case X86ISD::BEXTR: return "X86ISD::BEXTR";
13766 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
13767 case X86ISD::PTEST: return "X86ISD::PTEST";
13768 case X86ISD::TESTP: return "X86ISD::TESTP";
13769 case X86ISD::TESTM: return "X86ISD::TESTM";
13770 case X86ISD::KORTEST: return "X86ISD::KORTEST";
13771 case X86ISD::KTEST: return "X86ISD::KTEST";
13772 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
13773 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
13774 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
13775 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
13776 case X86ISD::SHUFP: return "X86ISD::SHUFP";
13777 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
13778 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
13779 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
13780 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
13781 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
13782 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
13783 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
13784 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
13785 case X86ISD::MOVSD: return "X86ISD::MOVSD";
13786 case X86ISD::MOVSS: return "X86ISD::MOVSS";
13787 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
13788 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
13789 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
13790 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
13791 case X86ISD::VPERMILP: return "X86ISD::VPERMILP";
13792 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
13793 case X86ISD::VPERMV: return "X86ISD::VPERMV";
13794 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
13795 case X86ISD::VPERMI: return "X86ISD::VPERMI";
13796 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
13797 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
13798 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
13799 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
13800 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
13801 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
13802 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
13803 case X86ISD::SAHF: return "X86ISD::SAHF";
13804 case X86ISD::RDRAND: return "X86ISD::RDRAND";
13805 case X86ISD::RDSEED: return "X86ISD::RDSEED";
13806 case X86ISD::FMADD: return "X86ISD::FMADD";
13807 case X86ISD::FMSUB: return "X86ISD::FMSUB";
13808 case X86ISD::FNMADD: return "X86ISD::FNMADD";
13809 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
13810 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
13811 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
13812 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
13813 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
13814 case X86ISD::XTEST: return "X86ISD::XTEST";
13818 // isLegalAddressingMode - Return true if the addressing mode represented
13819 // by AM is legal for this target, for a load/store of the specified type.
13820 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
13822 // X86 supports extremely general addressing modes.
13823 CodeModel::Model M = getTargetMachine().getCodeModel();
13824 Reloc::Model R = getTargetMachine().getRelocationModel();
13826 // X86 allows a sign-extended 32-bit immediate field as a displacement.
13827 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
13832 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
13834 // If a reference to this global requires an extra load, we can't fold it.
13835 if (isGlobalStubReference(GVFlags))
13838 // If BaseGV requires a register for the PIC base, we cannot also have a
13839 // BaseReg specified.
13840 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
13843 // If lower 4G is not available, then we must use rip-relative addressing.
13844 if ((M != CodeModel::Small || R != Reloc::Static) &&
13845 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
13849 switch (AM.Scale) {
13855 // These scales always work.
13860 // These scales are formed with basereg+scalereg. Only accept if there is
13865 default: // Other stuff never works.
13872 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
13873 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
13875 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
13876 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
13877 return NumBits1 > NumBits2;
13880 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
13881 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
13884 if (!isTypeLegal(EVT::getEVT(Ty1)))
13887 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
13889 // Assuming the caller doesn't have a zeroext or signext return parameter,
13890 // truncation all the way down to i1 is valid.
13894 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
13895 return isInt<32>(Imm);
13898 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
13899 // Can also use sub to handle negated immediates.
13900 return isInt<32>(Imm);
13903 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
13904 if (!VT1.isInteger() || !VT2.isInteger())
13906 unsigned NumBits1 = VT1.getSizeInBits();
13907 unsigned NumBits2 = VT2.getSizeInBits();
13908 return NumBits1 > NumBits2;
13911 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
13912 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
13913 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
13916 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
13917 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
13918 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
13921 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
13922 EVT VT1 = Val.getValueType();
13923 if (isZExtFree(VT1, VT2))
13926 if (Val.getOpcode() != ISD::LOAD)
13929 if (!VT1.isSimple() || !VT1.isInteger() ||
13930 !VT2.isSimple() || !VT2.isInteger())
13933 switch (VT1.getSimpleVT().SimpleTy) {
13938 // X86 has 8, 16, and 32-bit zero-extending loads.
13946 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
13947 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
13950 VT = VT.getScalarType();
13952 if (!VT.isSimple())
13955 switch (VT.getSimpleVT().SimpleTy) {
13966 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
13967 // i16 instructions are longer (0x66 prefix) and potentially slower.
13968 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
13971 /// isShuffleMaskLegal - Targets can use this to indicate that they only
13972 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
13973 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
13974 /// are assumed to be legal.
13976 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
13978 if (!VT.isSimple())
13981 MVT SVT = VT.getSimpleVT();
13983 // Very little shuffling can be done for 64-bit vectors right now.
13984 if (VT.getSizeInBits() == 64)
13987 // FIXME: pshufb, blends, shifts.
13988 return (SVT.getVectorNumElements() == 2 ||
13989 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
13990 isMOVLMask(M, SVT) ||
13991 isSHUFPMask(M, SVT) ||
13992 isPSHUFDMask(M, SVT) ||
13993 isPSHUFHWMask(M, SVT, Subtarget->hasInt256()) ||
13994 isPSHUFLWMask(M, SVT, Subtarget->hasInt256()) ||
13995 isPALIGNRMask(M, SVT, Subtarget) ||
13996 isUNPCKLMask(M, SVT, Subtarget->hasInt256()) ||
13997 isUNPCKHMask(M, SVT, Subtarget->hasInt256()) ||
13998 isUNPCKL_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
13999 isUNPCKH_v_undef_Mask(M, SVT, Subtarget->hasInt256()));
14003 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
14005 if (!VT.isSimple())
14008 MVT SVT = VT.getSimpleVT();
14009 unsigned NumElts = SVT.getVectorNumElements();
14010 // FIXME: This collection of masks seems suspect.
14013 if (NumElts == 4 && SVT.is128BitVector()) {
14014 return (isMOVLMask(Mask, SVT) ||
14015 isCommutedMOVLMask(Mask, SVT, true) ||
14016 isSHUFPMask(Mask, SVT) ||
14017 isSHUFPMask(Mask, SVT, /* Commuted */ true));
14022 //===----------------------------------------------------------------------===//
14023 // X86 Scheduler Hooks
14024 //===----------------------------------------------------------------------===//
14026 /// Utility function to emit xbegin specifying the start of an RTM region.
14027 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
14028 const TargetInstrInfo *TII) {
14029 DebugLoc DL = MI->getDebugLoc();
14031 const BasicBlock *BB = MBB->getBasicBlock();
14032 MachineFunction::iterator I = MBB;
14035 // For the v = xbegin(), we generate
14046 MachineBasicBlock *thisMBB = MBB;
14047 MachineFunction *MF = MBB->getParent();
14048 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
14049 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
14050 MF->insert(I, mainMBB);
14051 MF->insert(I, sinkMBB);
14053 // Transfer the remainder of BB and its successor edges to sinkMBB.
14054 sinkMBB->splice(sinkMBB->begin(), MBB,
14055 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
14056 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
14060 // # fallthrough to mainMBB
14061 // # abortion to sinkMBB
14062 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
14063 thisMBB->addSuccessor(mainMBB);
14064 thisMBB->addSuccessor(sinkMBB);
14068 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
14069 mainMBB->addSuccessor(sinkMBB);
14072 // EAX is live into the sinkMBB
14073 sinkMBB->addLiveIn(X86::EAX);
14074 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
14075 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
14078 MI->eraseFromParent();
14082 // Get CMPXCHG opcode for the specified data type.
14083 static unsigned getCmpXChgOpcode(EVT VT) {
14084 switch (VT.getSimpleVT().SimpleTy) {
14085 case MVT::i8: return X86::LCMPXCHG8;
14086 case MVT::i16: return X86::LCMPXCHG16;
14087 case MVT::i32: return X86::LCMPXCHG32;
14088 case MVT::i64: return X86::LCMPXCHG64;
14092 llvm_unreachable("Invalid operand size!");
14095 // Get LOAD opcode for the specified data type.
14096 static unsigned getLoadOpcode(EVT VT) {
14097 switch (VT.getSimpleVT().SimpleTy) {
14098 case MVT::i8: return X86::MOV8rm;
14099 case MVT::i16: return X86::MOV16rm;
14100 case MVT::i32: return X86::MOV32rm;
14101 case MVT::i64: return X86::MOV64rm;
14105 llvm_unreachable("Invalid operand size!");
14108 // Get opcode of the non-atomic one from the specified atomic instruction.
14109 static unsigned getNonAtomicOpcode(unsigned Opc) {
14111 case X86::ATOMAND8: return X86::AND8rr;
14112 case X86::ATOMAND16: return X86::AND16rr;
14113 case X86::ATOMAND32: return X86::AND32rr;
14114 case X86::ATOMAND64: return X86::AND64rr;
14115 case X86::ATOMOR8: return X86::OR8rr;
14116 case X86::ATOMOR16: return X86::OR16rr;
14117 case X86::ATOMOR32: return X86::OR32rr;
14118 case X86::ATOMOR64: return X86::OR64rr;
14119 case X86::ATOMXOR8: return X86::XOR8rr;
14120 case X86::ATOMXOR16: return X86::XOR16rr;
14121 case X86::ATOMXOR32: return X86::XOR32rr;
14122 case X86::ATOMXOR64: return X86::XOR64rr;
14124 llvm_unreachable("Unhandled atomic-load-op opcode!");
14127 // Get opcode of the non-atomic one from the specified atomic instruction with
14129 static unsigned getNonAtomicOpcodeWithExtraOpc(unsigned Opc,
14130 unsigned &ExtraOpc) {
14132 case X86::ATOMNAND8: ExtraOpc = X86::NOT8r; return X86::AND8rr;
14133 case X86::ATOMNAND16: ExtraOpc = X86::NOT16r; return X86::AND16rr;
14134 case X86::ATOMNAND32: ExtraOpc = X86::NOT32r; return X86::AND32rr;
14135 case X86::ATOMNAND64: ExtraOpc = X86::NOT64r; return X86::AND64rr;
14136 case X86::ATOMMAX8: ExtraOpc = X86::CMP8rr; return X86::CMOVL32rr;
14137 case X86::ATOMMAX16: ExtraOpc = X86::CMP16rr; return X86::CMOVL16rr;
14138 case X86::ATOMMAX32: ExtraOpc = X86::CMP32rr; return X86::CMOVL32rr;
14139 case X86::ATOMMAX64: ExtraOpc = X86::CMP64rr; return X86::CMOVL64rr;
14140 case X86::ATOMMIN8: ExtraOpc = X86::CMP8rr; return X86::CMOVG32rr;
14141 case X86::ATOMMIN16: ExtraOpc = X86::CMP16rr; return X86::CMOVG16rr;
14142 case X86::ATOMMIN32: ExtraOpc = X86::CMP32rr; return X86::CMOVG32rr;
14143 case X86::ATOMMIN64: ExtraOpc = X86::CMP64rr; return X86::CMOVG64rr;
14144 case X86::ATOMUMAX8: ExtraOpc = X86::CMP8rr; return X86::CMOVB32rr;
14145 case X86::ATOMUMAX16: ExtraOpc = X86::CMP16rr; return X86::CMOVB16rr;
14146 case X86::ATOMUMAX32: ExtraOpc = X86::CMP32rr; return X86::CMOVB32rr;
14147 case X86::ATOMUMAX64: ExtraOpc = X86::CMP64rr; return X86::CMOVB64rr;
14148 case X86::ATOMUMIN8: ExtraOpc = X86::CMP8rr; return X86::CMOVA32rr;
14149 case X86::ATOMUMIN16: ExtraOpc = X86::CMP16rr; return X86::CMOVA16rr;
14150 case X86::ATOMUMIN32: ExtraOpc = X86::CMP32rr; return X86::CMOVA32rr;
14151 case X86::ATOMUMIN64: ExtraOpc = X86::CMP64rr; return X86::CMOVA64rr;
14153 llvm_unreachable("Unhandled atomic-load-op opcode!");
14156 // Get opcode of the non-atomic one from the specified atomic instruction for
14157 // 64-bit data type on 32-bit target.
14158 static unsigned getNonAtomic6432Opcode(unsigned Opc, unsigned &HiOpc) {
14160 case X86::ATOMAND6432: HiOpc = X86::AND32rr; return X86::AND32rr;
14161 case X86::ATOMOR6432: HiOpc = X86::OR32rr; return X86::OR32rr;
14162 case X86::ATOMXOR6432: HiOpc = X86::XOR32rr; return X86::XOR32rr;
14163 case X86::ATOMADD6432: HiOpc = X86::ADC32rr; return X86::ADD32rr;
14164 case X86::ATOMSUB6432: HiOpc = X86::SBB32rr; return X86::SUB32rr;
14165 case X86::ATOMSWAP6432: HiOpc = X86::MOV32rr; return X86::MOV32rr;
14166 case X86::ATOMMAX6432: HiOpc = X86::SETLr; return X86::SETLr;
14167 case X86::ATOMMIN6432: HiOpc = X86::SETGr; return X86::SETGr;
14168 case X86::ATOMUMAX6432: HiOpc = X86::SETBr; return X86::SETBr;
14169 case X86::ATOMUMIN6432: HiOpc = X86::SETAr; return X86::SETAr;
14171 llvm_unreachable("Unhandled atomic-load-op opcode!");
14174 // Get opcode of the non-atomic one from the specified atomic instruction for
14175 // 64-bit data type on 32-bit target with extra opcode.
14176 static unsigned getNonAtomic6432OpcodeWithExtraOpc(unsigned Opc,
14178 unsigned &ExtraOpc) {
14180 case X86::ATOMNAND6432:
14181 ExtraOpc = X86::NOT32r;
14182 HiOpc = X86::AND32rr;
14183 return X86::AND32rr;
14185 llvm_unreachable("Unhandled atomic-load-op opcode!");
14188 // Get pseudo CMOV opcode from the specified data type.
14189 static unsigned getPseudoCMOVOpc(EVT VT) {
14190 switch (VT.getSimpleVT().SimpleTy) {
14191 case MVT::i8: return X86::CMOV_GR8;
14192 case MVT::i16: return X86::CMOV_GR16;
14193 case MVT::i32: return X86::CMOV_GR32;
14197 llvm_unreachable("Unknown CMOV opcode!");
14200 // EmitAtomicLoadArith - emit the code sequence for pseudo atomic instructions.
14201 // They will be translated into a spin-loop or compare-exchange loop from
14204 // dst = atomic-fetch-op MI.addr, MI.val
14210 // t1 = LOAD MI.addr
14212 // t4 = phi(t1, t3 / loop)
14213 // t2 = OP MI.val, t4
14215 // LCMPXCHG [MI.addr], t2, [EAX is implicitly used & defined]
14221 MachineBasicBlock *
14222 X86TargetLowering::EmitAtomicLoadArith(MachineInstr *MI,
14223 MachineBasicBlock *MBB) const {
14224 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
14225 DebugLoc DL = MI->getDebugLoc();
14227 MachineFunction *MF = MBB->getParent();
14228 MachineRegisterInfo &MRI = MF->getRegInfo();
14230 const BasicBlock *BB = MBB->getBasicBlock();
14231 MachineFunction::iterator I = MBB;
14234 assert(MI->getNumOperands() <= X86::AddrNumOperands + 4 &&
14235 "Unexpected number of operands");
14237 assert(MI->hasOneMemOperand() &&
14238 "Expected atomic-load-op to have one memoperand");
14240 // Memory Reference
14241 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
14242 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
14244 unsigned DstReg, SrcReg;
14245 unsigned MemOpndSlot;
14247 unsigned CurOp = 0;
14249 DstReg = MI->getOperand(CurOp++).getReg();
14250 MemOpndSlot = CurOp;
14251 CurOp += X86::AddrNumOperands;
14252 SrcReg = MI->getOperand(CurOp++).getReg();
14254 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
14255 MVT::SimpleValueType VT = *RC->vt_begin();
14256 unsigned t1 = MRI.createVirtualRegister(RC);
14257 unsigned t2 = MRI.createVirtualRegister(RC);
14258 unsigned t3 = MRI.createVirtualRegister(RC);
14259 unsigned t4 = MRI.createVirtualRegister(RC);
14260 unsigned PhyReg = getX86SubSuperRegister(X86::EAX, VT);
14262 unsigned LCMPXCHGOpc = getCmpXChgOpcode(VT);
14263 unsigned LOADOpc = getLoadOpcode(VT);
14265 // For the atomic load-arith operator, we generate
14268 // t1 = LOAD [MI.addr]
14270 // t4 = phi(t1 / thisMBB, t3 / mainMBB)
14271 // t1 = OP MI.val, EAX
14273 // LCMPXCHG [MI.addr], t1, [EAX is implicitly used & defined]
14279 MachineBasicBlock *thisMBB = MBB;
14280 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
14281 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
14282 MF->insert(I, mainMBB);
14283 MF->insert(I, sinkMBB);
14285 MachineInstrBuilder MIB;
14287 // Transfer the remainder of BB and its successor edges to sinkMBB.
14288 sinkMBB->splice(sinkMBB->begin(), MBB,
14289 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
14290 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
14293 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), t1);
14294 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14295 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
14297 NewMO.setIsKill(false);
14298 MIB.addOperand(NewMO);
14300 for (MachineInstr::mmo_iterator MMOI = MMOBegin; MMOI != MMOEnd; ++MMOI) {
14301 unsigned flags = (*MMOI)->getFlags();
14302 flags = (flags & ~MachineMemOperand::MOStore) | MachineMemOperand::MOLoad;
14303 MachineMemOperand *MMO =
14304 MF->getMachineMemOperand((*MMOI)->getPointerInfo(), flags,
14305 (*MMOI)->getSize(),
14306 (*MMOI)->getBaseAlignment(),
14307 (*MMOI)->getTBAAInfo(),
14308 (*MMOI)->getRanges());
14309 MIB.addMemOperand(MMO);
14312 thisMBB->addSuccessor(mainMBB);
14315 MachineBasicBlock *origMainMBB = mainMBB;
14318 MachineInstr *Phi = BuildMI(mainMBB, DL, TII->get(X86::PHI), t4)
14319 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(mainMBB);
14321 unsigned Opc = MI->getOpcode();
14324 llvm_unreachable("Unhandled atomic-load-op opcode!");
14325 case X86::ATOMAND8:
14326 case X86::ATOMAND16:
14327 case X86::ATOMAND32:
14328 case X86::ATOMAND64:
14330 case X86::ATOMOR16:
14331 case X86::ATOMOR32:
14332 case X86::ATOMOR64:
14333 case X86::ATOMXOR8:
14334 case X86::ATOMXOR16:
14335 case X86::ATOMXOR32:
14336 case X86::ATOMXOR64: {
14337 unsigned ARITHOpc = getNonAtomicOpcode(Opc);
14338 BuildMI(mainMBB, DL, TII->get(ARITHOpc), t2).addReg(SrcReg)
14342 case X86::ATOMNAND8:
14343 case X86::ATOMNAND16:
14344 case X86::ATOMNAND32:
14345 case X86::ATOMNAND64: {
14346 unsigned Tmp = MRI.createVirtualRegister(RC);
14348 unsigned ANDOpc = getNonAtomicOpcodeWithExtraOpc(Opc, NOTOpc);
14349 BuildMI(mainMBB, DL, TII->get(ANDOpc), Tmp).addReg(SrcReg)
14351 BuildMI(mainMBB, DL, TII->get(NOTOpc), t2).addReg(Tmp);
14354 case X86::ATOMMAX8:
14355 case X86::ATOMMAX16:
14356 case X86::ATOMMAX32:
14357 case X86::ATOMMAX64:
14358 case X86::ATOMMIN8:
14359 case X86::ATOMMIN16:
14360 case X86::ATOMMIN32:
14361 case X86::ATOMMIN64:
14362 case X86::ATOMUMAX8:
14363 case X86::ATOMUMAX16:
14364 case X86::ATOMUMAX32:
14365 case X86::ATOMUMAX64:
14366 case X86::ATOMUMIN8:
14367 case X86::ATOMUMIN16:
14368 case X86::ATOMUMIN32:
14369 case X86::ATOMUMIN64: {
14371 unsigned CMOVOpc = getNonAtomicOpcodeWithExtraOpc(Opc, CMPOpc);
14373 BuildMI(mainMBB, DL, TII->get(CMPOpc))
14377 if (Subtarget->hasCMov()) {
14378 if (VT != MVT::i8) {
14380 BuildMI(mainMBB, DL, TII->get(CMOVOpc), t2)
14384 // Promote i8 to i32 to use CMOV32
14385 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
14386 const TargetRegisterClass *RC32 =
14387 TRI->getSubClassWithSubReg(getRegClassFor(MVT::i32), X86::sub_8bit);
14388 unsigned SrcReg32 = MRI.createVirtualRegister(RC32);
14389 unsigned AccReg32 = MRI.createVirtualRegister(RC32);
14390 unsigned Tmp = MRI.createVirtualRegister(RC32);
14392 unsigned Undef = MRI.createVirtualRegister(RC32);
14393 BuildMI(mainMBB, DL, TII->get(TargetOpcode::IMPLICIT_DEF), Undef);
14395 BuildMI(mainMBB, DL, TII->get(TargetOpcode::INSERT_SUBREG), SrcReg32)
14398 .addImm(X86::sub_8bit);
14399 BuildMI(mainMBB, DL, TII->get(TargetOpcode::INSERT_SUBREG), AccReg32)
14402 .addImm(X86::sub_8bit);
14404 BuildMI(mainMBB, DL, TII->get(CMOVOpc), Tmp)
14408 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t2)
14409 .addReg(Tmp, 0, X86::sub_8bit);
14412 // Use pseudo select and lower them.
14413 assert((VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32) &&
14414 "Invalid atomic-load-op transformation!");
14415 unsigned SelOpc = getPseudoCMOVOpc(VT);
14416 X86::CondCode CC = X86::getCondFromCMovOpc(CMOVOpc);
14417 assert(CC != X86::COND_INVALID && "Invalid atomic-load-op transformation!");
14418 MIB = BuildMI(mainMBB, DL, TII->get(SelOpc), t2)
14419 .addReg(SrcReg).addReg(t4)
14421 mainMBB = EmitLoweredSelect(MIB, mainMBB);
14422 // Replace the original PHI node as mainMBB is changed after CMOV
14424 BuildMI(*origMainMBB, Phi, DL, TII->get(X86::PHI), t4)
14425 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(mainMBB);
14426 Phi->eraseFromParent();
14432 // Copy PhyReg back from virtual register.
14433 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), PhyReg)
14436 MIB = BuildMI(mainMBB, DL, TII->get(LCMPXCHGOpc));
14437 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14438 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
14440 NewMO.setIsKill(false);
14441 MIB.addOperand(NewMO);
14444 MIB.setMemRefs(MMOBegin, MMOEnd);
14446 // Copy PhyReg back to virtual register.
14447 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t3)
14450 BuildMI(mainMBB, DL, TII->get(X86::JNE_4)).addMBB(origMainMBB);
14452 mainMBB->addSuccessor(origMainMBB);
14453 mainMBB->addSuccessor(sinkMBB);
14456 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
14457 TII->get(TargetOpcode::COPY), DstReg)
14460 MI->eraseFromParent();
14464 // EmitAtomicLoadArith6432 - emit the code sequence for pseudo atomic
14465 // instructions. They will be translated into a spin-loop or compare-exchange
14469 // dst = atomic-fetch-op MI.addr, MI.val
14475 // t1L = LOAD [MI.addr + 0]
14476 // t1H = LOAD [MI.addr + 4]
14478 // t4L = phi(t1L, t3L / loop)
14479 // t4H = phi(t1H, t3H / loop)
14480 // t2L = OP MI.val.lo, t4L
14481 // t2H = OP MI.val.hi, t4H
14486 // LCMPXCHG8B [MI.addr], [ECX:EBX & EDX:EAX are implicitly used and EDX:EAX is implicitly defined]
14494 MachineBasicBlock *
14495 X86TargetLowering::EmitAtomicLoadArith6432(MachineInstr *MI,
14496 MachineBasicBlock *MBB) const {
14497 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
14498 DebugLoc DL = MI->getDebugLoc();
14500 MachineFunction *MF = MBB->getParent();
14501 MachineRegisterInfo &MRI = MF->getRegInfo();
14503 const BasicBlock *BB = MBB->getBasicBlock();
14504 MachineFunction::iterator I = MBB;
14507 assert(MI->getNumOperands() <= X86::AddrNumOperands + 7 &&
14508 "Unexpected number of operands");
14510 assert(MI->hasOneMemOperand() &&
14511 "Expected atomic-load-op32 to have one memoperand");
14513 // Memory Reference
14514 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
14515 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
14517 unsigned DstLoReg, DstHiReg;
14518 unsigned SrcLoReg, SrcHiReg;
14519 unsigned MemOpndSlot;
14521 unsigned CurOp = 0;
14523 DstLoReg = MI->getOperand(CurOp++).getReg();
14524 DstHiReg = MI->getOperand(CurOp++).getReg();
14525 MemOpndSlot = CurOp;
14526 CurOp += X86::AddrNumOperands;
14527 SrcLoReg = MI->getOperand(CurOp++).getReg();
14528 SrcHiReg = MI->getOperand(CurOp++).getReg();
14530 const TargetRegisterClass *RC = &X86::GR32RegClass;
14531 const TargetRegisterClass *RC8 = &X86::GR8RegClass;
14533 unsigned t1L = MRI.createVirtualRegister(RC);
14534 unsigned t1H = MRI.createVirtualRegister(RC);
14535 unsigned t2L = MRI.createVirtualRegister(RC);
14536 unsigned t2H = MRI.createVirtualRegister(RC);
14537 unsigned t3L = MRI.createVirtualRegister(RC);
14538 unsigned t3H = MRI.createVirtualRegister(RC);
14539 unsigned t4L = MRI.createVirtualRegister(RC);
14540 unsigned t4H = MRI.createVirtualRegister(RC);
14542 unsigned LCMPXCHGOpc = X86::LCMPXCHG8B;
14543 unsigned LOADOpc = X86::MOV32rm;
14545 // For the atomic load-arith operator, we generate
14548 // t1L = LOAD [MI.addr + 0]
14549 // t1H = LOAD [MI.addr + 4]
14551 // t4L = phi(t1L / thisMBB, t3L / mainMBB)
14552 // t4H = phi(t1H / thisMBB, t3H / mainMBB)
14553 // t2L = OP MI.val.lo, t4L
14554 // t2H = OP MI.val.hi, t4H
14557 // LCMPXCHG8B [MI.addr], [ECX:EBX & EDX:EAX are implicitly used and EDX:EAX is implicitly defined]
14565 MachineBasicBlock *thisMBB = MBB;
14566 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
14567 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
14568 MF->insert(I, mainMBB);
14569 MF->insert(I, sinkMBB);
14571 MachineInstrBuilder MIB;
14573 // Transfer the remainder of BB and its successor edges to sinkMBB.
14574 sinkMBB->splice(sinkMBB->begin(), MBB,
14575 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
14576 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
14580 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), t1L);
14581 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14582 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
14584 NewMO.setIsKill(false);
14585 MIB.addOperand(NewMO);
14587 for (MachineInstr::mmo_iterator MMOI = MMOBegin; MMOI != MMOEnd; ++MMOI) {
14588 unsigned flags = (*MMOI)->getFlags();
14589 flags = (flags & ~MachineMemOperand::MOStore) | MachineMemOperand::MOLoad;
14590 MachineMemOperand *MMO =
14591 MF->getMachineMemOperand((*MMOI)->getPointerInfo(), flags,
14592 (*MMOI)->getSize(),
14593 (*MMOI)->getBaseAlignment(),
14594 (*MMOI)->getTBAAInfo(),
14595 (*MMOI)->getRanges());
14596 MIB.addMemOperand(MMO);
14598 MachineInstr *LowMI = MIB;
14601 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), t1H);
14602 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14603 if (i == X86::AddrDisp) {
14604 MIB.addDisp(MI->getOperand(MemOpndSlot + i), 4); // 4 == sizeof(i32)
14606 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
14608 NewMO.setIsKill(false);
14609 MIB.addOperand(NewMO);
14612 MIB.setMemRefs(LowMI->memoperands_begin(), LowMI->memoperands_end());
14614 thisMBB->addSuccessor(mainMBB);
14617 MachineBasicBlock *origMainMBB = mainMBB;
14620 MachineInstr *PhiL = BuildMI(mainMBB, DL, TII->get(X86::PHI), t4L)
14621 .addReg(t1L).addMBB(thisMBB).addReg(t3L).addMBB(mainMBB);
14622 MachineInstr *PhiH = BuildMI(mainMBB, DL, TII->get(X86::PHI), t4H)
14623 .addReg(t1H).addMBB(thisMBB).addReg(t3H).addMBB(mainMBB);
14625 unsigned Opc = MI->getOpcode();
14628 llvm_unreachable("Unhandled atomic-load-op6432 opcode!");
14629 case X86::ATOMAND6432:
14630 case X86::ATOMOR6432:
14631 case X86::ATOMXOR6432:
14632 case X86::ATOMADD6432:
14633 case X86::ATOMSUB6432: {
14635 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc);
14636 BuildMI(mainMBB, DL, TII->get(LoOpc), t2L).addReg(t4L)
14638 BuildMI(mainMBB, DL, TII->get(HiOpc), t2H).addReg(t4H)
14642 case X86::ATOMNAND6432: {
14643 unsigned HiOpc, NOTOpc;
14644 unsigned LoOpc = getNonAtomic6432OpcodeWithExtraOpc(Opc, HiOpc, NOTOpc);
14645 unsigned TmpL = MRI.createVirtualRegister(RC);
14646 unsigned TmpH = MRI.createVirtualRegister(RC);
14647 BuildMI(mainMBB, DL, TII->get(LoOpc), TmpL).addReg(SrcLoReg)
14649 BuildMI(mainMBB, DL, TII->get(HiOpc), TmpH).addReg(SrcHiReg)
14651 BuildMI(mainMBB, DL, TII->get(NOTOpc), t2L).addReg(TmpL);
14652 BuildMI(mainMBB, DL, TII->get(NOTOpc), t2H).addReg(TmpH);
14655 case X86::ATOMMAX6432:
14656 case X86::ATOMMIN6432:
14657 case X86::ATOMUMAX6432:
14658 case X86::ATOMUMIN6432: {
14660 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc);
14661 unsigned cL = MRI.createVirtualRegister(RC8);
14662 unsigned cH = MRI.createVirtualRegister(RC8);
14663 unsigned cL32 = MRI.createVirtualRegister(RC);
14664 unsigned cH32 = MRI.createVirtualRegister(RC);
14665 unsigned cc = MRI.createVirtualRegister(RC);
14666 // cl := cmp src_lo, lo
14667 BuildMI(mainMBB, DL, TII->get(X86::CMP32rr))
14668 .addReg(SrcLoReg).addReg(t4L);
14669 BuildMI(mainMBB, DL, TII->get(LoOpc), cL);
14670 BuildMI(mainMBB, DL, TII->get(X86::MOVZX32rr8), cL32).addReg(cL);
14671 // ch := cmp src_hi, hi
14672 BuildMI(mainMBB, DL, TII->get(X86::CMP32rr))
14673 .addReg(SrcHiReg).addReg(t4H);
14674 BuildMI(mainMBB, DL, TII->get(HiOpc), cH);
14675 BuildMI(mainMBB, DL, TII->get(X86::MOVZX32rr8), cH32).addReg(cH);
14676 // cc := if (src_hi == hi) ? cl : ch;
14677 if (Subtarget->hasCMov()) {
14678 BuildMI(mainMBB, DL, TII->get(X86::CMOVE32rr), cc)
14679 .addReg(cH32).addReg(cL32);
14681 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), cc)
14682 .addReg(cH32).addReg(cL32)
14683 .addImm(X86::COND_E);
14684 mainMBB = EmitLoweredSelect(MIB, mainMBB);
14686 BuildMI(mainMBB, DL, TII->get(X86::TEST32rr)).addReg(cc).addReg(cc);
14687 if (Subtarget->hasCMov()) {
14688 BuildMI(mainMBB, DL, TII->get(X86::CMOVNE32rr), t2L)
14689 .addReg(SrcLoReg).addReg(t4L);
14690 BuildMI(mainMBB, DL, TII->get(X86::CMOVNE32rr), t2H)
14691 .addReg(SrcHiReg).addReg(t4H);
14693 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), t2L)
14694 .addReg(SrcLoReg).addReg(t4L)
14695 .addImm(X86::COND_NE);
14696 mainMBB = EmitLoweredSelect(MIB, mainMBB);
14697 // As the lowered CMOV won't clobber EFLAGS, we could reuse it for the
14698 // 2nd CMOV lowering.
14699 mainMBB->addLiveIn(X86::EFLAGS);
14700 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), t2H)
14701 .addReg(SrcHiReg).addReg(t4H)
14702 .addImm(X86::COND_NE);
14703 mainMBB = EmitLoweredSelect(MIB, mainMBB);
14704 // Replace the original PHI node as mainMBB is changed after CMOV
14706 BuildMI(*origMainMBB, PhiL, DL, TII->get(X86::PHI), t4L)
14707 .addReg(t1L).addMBB(thisMBB).addReg(t3L).addMBB(mainMBB);
14708 BuildMI(*origMainMBB, PhiH, DL, TII->get(X86::PHI), t4H)
14709 .addReg(t1H).addMBB(thisMBB).addReg(t3H).addMBB(mainMBB);
14710 PhiL->eraseFromParent();
14711 PhiH->eraseFromParent();
14715 case X86::ATOMSWAP6432: {
14717 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc);
14718 BuildMI(mainMBB, DL, TII->get(LoOpc), t2L).addReg(SrcLoReg);
14719 BuildMI(mainMBB, DL, TII->get(HiOpc), t2H).addReg(SrcHiReg);
14724 // Copy EDX:EAX back from HiReg:LoReg
14725 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EAX).addReg(t4L);
14726 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EDX).addReg(t4H);
14727 // Copy ECX:EBX from t1H:t1L
14728 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EBX).addReg(t2L);
14729 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::ECX).addReg(t2H);
14731 MIB = BuildMI(mainMBB, DL, TII->get(LCMPXCHGOpc));
14732 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14733 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
14735 NewMO.setIsKill(false);
14736 MIB.addOperand(NewMO);
14738 MIB.setMemRefs(MMOBegin, MMOEnd);
14740 // Copy EDX:EAX back to t3H:t3L
14741 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t3L).addReg(X86::EAX);
14742 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t3H).addReg(X86::EDX);
14744 BuildMI(mainMBB, DL, TII->get(X86::JNE_4)).addMBB(origMainMBB);
14746 mainMBB->addSuccessor(origMainMBB);
14747 mainMBB->addSuccessor(sinkMBB);
14750 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
14751 TII->get(TargetOpcode::COPY), DstLoReg)
14753 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
14754 TII->get(TargetOpcode::COPY), DstHiReg)
14757 MI->eraseFromParent();
14761 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
14762 // or XMM0_V32I8 in AVX all of this code can be replaced with that
14763 // in the .td file.
14764 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
14765 const TargetInstrInfo *TII) {
14767 switch (MI->getOpcode()) {
14768 default: llvm_unreachable("illegal opcode!");
14769 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
14770 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
14771 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
14772 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
14773 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
14774 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
14775 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
14776 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
14779 DebugLoc dl = MI->getDebugLoc();
14780 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
14782 unsigned NumArgs = MI->getNumOperands();
14783 for (unsigned i = 1; i < NumArgs; ++i) {
14784 MachineOperand &Op = MI->getOperand(i);
14785 if (!(Op.isReg() && Op.isImplicit()))
14786 MIB.addOperand(Op);
14788 if (MI->hasOneMemOperand())
14789 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
14791 BuildMI(*BB, MI, dl,
14792 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
14793 .addReg(X86::XMM0);
14795 MI->eraseFromParent();
14799 // FIXME: Custom handling because TableGen doesn't support multiple implicit
14800 // defs in an instruction pattern
14801 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
14802 const TargetInstrInfo *TII) {
14804 switch (MI->getOpcode()) {
14805 default: llvm_unreachable("illegal opcode!");
14806 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
14807 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
14808 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
14809 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
14810 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
14811 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
14812 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
14813 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
14816 DebugLoc dl = MI->getDebugLoc();
14817 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
14819 unsigned NumArgs = MI->getNumOperands(); // remove the results
14820 for (unsigned i = 1; i < NumArgs; ++i) {
14821 MachineOperand &Op = MI->getOperand(i);
14822 if (!(Op.isReg() && Op.isImplicit()))
14823 MIB.addOperand(Op);
14825 if (MI->hasOneMemOperand())
14826 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
14828 BuildMI(*BB, MI, dl,
14829 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
14832 MI->eraseFromParent();
14836 static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
14837 const TargetInstrInfo *TII,
14838 const X86Subtarget* Subtarget) {
14839 DebugLoc dl = MI->getDebugLoc();
14841 // Address into RAX/EAX, other two args into ECX, EDX.
14842 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
14843 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
14844 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
14845 for (int i = 0; i < X86::AddrNumOperands; ++i)
14846 MIB.addOperand(MI->getOperand(i));
14848 unsigned ValOps = X86::AddrNumOperands;
14849 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
14850 .addReg(MI->getOperand(ValOps).getReg());
14851 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
14852 .addReg(MI->getOperand(ValOps+1).getReg());
14854 // The instruction doesn't actually take any operands though.
14855 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
14857 MI->eraseFromParent(); // The pseudo is gone now.
14861 MachineBasicBlock *
14862 X86TargetLowering::EmitVAARG64WithCustomInserter(
14864 MachineBasicBlock *MBB) const {
14865 // Emit va_arg instruction on X86-64.
14867 // Operands to this pseudo-instruction:
14868 // 0 ) Output : destination address (reg)
14869 // 1-5) Input : va_list address (addr, i64mem)
14870 // 6 ) ArgSize : Size (in bytes) of vararg type
14871 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
14872 // 8 ) Align : Alignment of type
14873 // 9 ) EFLAGS (implicit-def)
14875 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
14876 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
14878 unsigned DestReg = MI->getOperand(0).getReg();
14879 MachineOperand &Base = MI->getOperand(1);
14880 MachineOperand &Scale = MI->getOperand(2);
14881 MachineOperand &Index = MI->getOperand(3);
14882 MachineOperand &Disp = MI->getOperand(4);
14883 MachineOperand &Segment = MI->getOperand(5);
14884 unsigned ArgSize = MI->getOperand(6).getImm();
14885 unsigned ArgMode = MI->getOperand(7).getImm();
14886 unsigned Align = MI->getOperand(8).getImm();
14888 // Memory Reference
14889 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
14890 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
14891 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
14893 // Machine Information
14894 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
14895 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
14896 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
14897 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
14898 DebugLoc DL = MI->getDebugLoc();
14900 // struct va_list {
14903 // i64 overflow_area (address)
14904 // i64 reg_save_area (address)
14906 // sizeof(va_list) = 24
14907 // alignment(va_list) = 8
14909 unsigned TotalNumIntRegs = 6;
14910 unsigned TotalNumXMMRegs = 8;
14911 bool UseGPOffset = (ArgMode == 1);
14912 bool UseFPOffset = (ArgMode == 2);
14913 unsigned MaxOffset = TotalNumIntRegs * 8 +
14914 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
14916 /* Align ArgSize to a multiple of 8 */
14917 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
14918 bool NeedsAlign = (Align > 8);
14920 MachineBasicBlock *thisMBB = MBB;
14921 MachineBasicBlock *overflowMBB;
14922 MachineBasicBlock *offsetMBB;
14923 MachineBasicBlock *endMBB;
14925 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
14926 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
14927 unsigned OffsetReg = 0;
14929 if (!UseGPOffset && !UseFPOffset) {
14930 // If we only pull from the overflow region, we don't create a branch.
14931 // We don't need to alter control flow.
14932 OffsetDestReg = 0; // unused
14933 OverflowDestReg = DestReg;
14936 overflowMBB = thisMBB;
14939 // First emit code to check if gp_offset (or fp_offset) is below the bound.
14940 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
14941 // If not, pull from overflow_area. (branch to overflowMBB)
14946 // offsetMBB overflowMBB
14951 // Registers for the PHI in endMBB
14952 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
14953 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
14955 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
14956 MachineFunction *MF = MBB->getParent();
14957 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
14958 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
14959 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
14961 MachineFunction::iterator MBBIter = MBB;
14964 // Insert the new basic blocks
14965 MF->insert(MBBIter, offsetMBB);
14966 MF->insert(MBBIter, overflowMBB);
14967 MF->insert(MBBIter, endMBB);
14969 // Transfer the remainder of MBB and its successor edges to endMBB.
14970 endMBB->splice(endMBB->begin(), thisMBB,
14971 llvm::next(MachineBasicBlock::iterator(MI)),
14973 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
14975 // Make offsetMBB and overflowMBB successors of thisMBB
14976 thisMBB->addSuccessor(offsetMBB);
14977 thisMBB->addSuccessor(overflowMBB);
14979 // endMBB is a successor of both offsetMBB and overflowMBB
14980 offsetMBB->addSuccessor(endMBB);
14981 overflowMBB->addSuccessor(endMBB);
14983 // Load the offset value into a register
14984 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
14985 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
14989 .addDisp(Disp, UseFPOffset ? 4 : 0)
14990 .addOperand(Segment)
14991 .setMemRefs(MMOBegin, MMOEnd);
14993 // Check if there is enough room left to pull this argument.
14994 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
14996 .addImm(MaxOffset + 8 - ArgSizeA8);
14998 // Branch to "overflowMBB" if offset >= max
14999 // Fall through to "offsetMBB" otherwise
15000 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
15001 .addMBB(overflowMBB);
15004 // In offsetMBB, emit code to use the reg_save_area.
15006 assert(OffsetReg != 0);
15008 // Read the reg_save_area address.
15009 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
15010 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
15015 .addOperand(Segment)
15016 .setMemRefs(MMOBegin, MMOEnd);
15018 // Zero-extend the offset
15019 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
15020 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
15023 .addImm(X86::sub_32bit);
15025 // Add the offset to the reg_save_area to get the final address.
15026 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
15027 .addReg(OffsetReg64)
15028 .addReg(RegSaveReg);
15030 // Compute the offset for the next argument
15031 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
15032 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
15034 .addImm(UseFPOffset ? 16 : 8);
15036 // Store it back into the va_list.
15037 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
15041 .addDisp(Disp, UseFPOffset ? 4 : 0)
15042 .addOperand(Segment)
15043 .addReg(NextOffsetReg)
15044 .setMemRefs(MMOBegin, MMOEnd);
15047 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
15052 // Emit code to use overflow area
15055 // Load the overflow_area address into a register.
15056 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
15057 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
15062 .addOperand(Segment)
15063 .setMemRefs(MMOBegin, MMOEnd);
15065 // If we need to align it, do so. Otherwise, just copy the address
15066 // to OverflowDestReg.
15068 // Align the overflow address
15069 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
15070 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
15072 // aligned_addr = (addr + (align-1)) & ~(align-1)
15073 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
15074 .addReg(OverflowAddrReg)
15077 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
15079 .addImm(~(uint64_t)(Align-1));
15081 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
15082 .addReg(OverflowAddrReg);
15085 // Compute the next overflow address after this argument.
15086 // (the overflow address should be kept 8-byte aligned)
15087 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
15088 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
15089 .addReg(OverflowDestReg)
15090 .addImm(ArgSizeA8);
15092 // Store the new overflow address.
15093 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
15098 .addOperand(Segment)
15099 .addReg(NextAddrReg)
15100 .setMemRefs(MMOBegin, MMOEnd);
15102 // If we branched, emit the PHI to the front of endMBB.
15104 BuildMI(*endMBB, endMBB->begin(), DL,
15105 TII->get(X86::PHI), DestReg)
15106 .addReg(OffsetDestReg).addMBB(offsetMBB)
15107 .addReg(OverflowDestReg).addMBB(overflowMBB);
15110 // Erase the pseudo instruction
15111 MI->eraseFromParent();
15116 MachineBasicBlock *
15117 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
15119 MachineBasicBlock *MBB) const {
15120 // Emit code to save XMM registers to the stack. The ABI says that the
15121 // number of registers to save is given in %al, so it's theoretically
15122 // possible to do an indirect jump trick to avoid saving all of them,
15123 // however this code takes a simpler approach and just executes all
15124 // of the stores if %al is non-zero. It's less code, and it's probably
15125 // easier on the hardware branch predictor, and stores aren't all that
15126 // expensive anyway.
15128 // Create the new basic blocks. One block contains all the XMM stores,
15129 // and one block is the final destination regardless of whether any
15130 // stores were performed.
15131 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
15132 MachineFunction *F = MBB->getParent();
15133 MachineFunction::iterator MBBIter = MBB;
15135 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
15136 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
15137 F->insert(MBBIter, XMMSaveMBB);
15138 F->insert(MBBIter, EndMBB);
15140 // Transfer the remainder of MBB and its successor edges to EndMBB.
15141 EndMBB->splice(EndMBB->begin(), MBB,
15142 llvm::next(MachineBasicBlock::iterator(MI)),
15144 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
15146 // The original block will now fall through to the XMM save block.
15147 MBB->addSuccessor(XMMSaveMBB);
15148 // The XMMSaveMBB will fall through to the end block.
15149 XMMSaveMBB->addSuccessor(EndMBB);
15151 // Now add the instructions.
15152 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15153 DebugLoc DL = MI->getDebugLoc();
15155 unsigned CountReg = MI->getOperand(0).getReg();
15156 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
15157 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
15159 if (!Subtarget->isTargetWin64()) {
15160 // If %al is 0, branch around the XMM save block.
15161 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
15162 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
15163 MBB->addSuccessor(EndMBB);
15166 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
15167 // In the XMM save block, save all the XMM argument registers.
15168 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
15169 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
15170 MachineMemOperand *MMO =
15171 F->getMachineMemOperand(
15172 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
15173 MachineMemOperand::MOStore,
15174 /*Size=*/16, /*Align=*/16);
15175 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
15176 .addFrameIndex(RegSaveFrameIndex)
15177 .addImm(/*Scale=*/1)
15178 .addReg(/*IndexReg=*/0)
15179 .addImm(/*Disp=*/Offset)
15180 .addReg(/*Segment=*/0)
15181 .addReg(MI->getOperand(i).getReg())
15182 .addMemOperand(MMO);
15185 MI->eraseFromParent(); // The pseudo instruction is gone now.
15190 // The EFLAGS operand of SelectItr might be missing a kill marker
15191 // because there were multiple uses of EFLAGS, and ISel didn't know
15192 // which to mark. Figure out whether SelectItr should have had a
15193 // kill marker, and set it if it should. Returns the correct kill
15195 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
15196 MachineBasicBlock* BB,
15197 const TargetRegisterInfo* TRI) {
15198 // Scan forward through BB for a use/def of EFLAGS.
15199 MachineBasicBlock::iterator miI(llvm::next(SelectItr));
15200 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
15201 const MachineInstr& mi = *miI;
15202 if (mi.readsRegister(X86::EFLAGS))
15204 if (mi.definesRegister(X86::EFLAGS))
15205 break; // Should have kill-flag - update below.
15208 // If we hit the end of the block, check whether EFLAGS is live into a
15210 if (miI == BB->end()) {
15211 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
15212 sEnd = BB->succ_end();
15213 sItr != sEnd; ++sItr) {
15214 MachineBasicBlock* succ = *sItr;
15215 if (succ->isLiveIn(X86::EFLAGS))
15220 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
15221 // out. SelectMI should have a kill flag on EFLAGS.
15222 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
15226 MachineBasicBlock *
15227 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
15228 MachineBasicBlock *BB) const {
15229 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15230 DebugLoc DL = MI->getDebugLoc();
15232 // To "insert" a SELECT_CC instruction, we actually have to insert the
15233 // diamond control-flow pattern. The incoming instruction knows the
15234 // destination vreg to set, the condition code register to branch on, the
15235 // true/false values to select between, and a branch opcode to use.
15236 const BasicBlock *LLVM_BB = BB->getBasicBlock();
15237 MachineFunction::iterator It = BB;
15243 // cmpTY ccX, r1, r2
15245 // fallthrough --> copy0MBB
15246 MachineBasicBlock *thisMBB = BB;
15247 MachineFunction *F = BB->getParent();
15248 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
15249 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
15250 F->insert(It, copy0MBB);
15251 F->insert(It, sinkMBB);
15253 // If the EFLAGS register isn't dead in the terminator, then claim that it's
15254 // live into the sink and copy blocks.
15255 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
15256 if (!MI->killsRegister(X86::EFLAGS) &&
15257 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
15258 copy0MBB->addLiveIn(X86::EFLAGS);
15259 sinkMBB->addLiveIn(X86::EFLAGS);
15262 // Transfer the remainder of BB and its successor edges to sinkMBB.
15263 sinkMBB->splice(sinkMBB->begin(), BB,
15264 llvm::next(MachineBasicBlock::iterator(MI)),
15266 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
15268 // Add the true and fallthrough blocks as its successors.
15269 BB->addSuccessor(copy0MBB);
15270 BB->addSuccessor(sinkMBB);
15272 // Create the conditional branch instruction.
15274 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
15275 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
15278 // %FalseValue = ...
15279 // # fallthrough to sinkMBB
15280 copy0MBB->addSuccessor(sinkMBB);
15283 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
15285 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
15286 TII->get(X86::PHI), MI->getOperand(0).getReg())
15287 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
15288 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
15290 MI->eraseFromParent(); // The pseudo instruction is gone now.
15294 MachineBasicBlock *
15295 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB,
15296 bool Is64Bit) const {
15297 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15298 DebugLoc DL = MI->getDebugLoc();
15299 MachineFunction *MF = BB->getParent();
15300 const BasicBlock *LLVM_BB = BB->getBasicBlock();
15302 assert(getTargetMachine().Options.EnableSegmentedStacks);
15304 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
15305 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30;
15308 // ... [Till the alloca]
15309 // If stacklet is not large enough, jump to mallocMBB
15312 // Allocate by subtracting from RSP
15313 // Jump to continueMBB
15316 // Allocate by call to runtime
15320 // [rest of original BB]
15323 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
15324 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
15325 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
15327 MachineRegisterInfo &MRI = MF->getRegInfo();
15328 const TargetRegisterClass *AddrRegClass =
15329 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32);
15331 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
15332 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
15333 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
15334 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
15335 sizeVReg = MI->getOperand(1).getReg(),
15336 physSPReg = Is64Bit ? X86::RSP : X86::ESP;
15338 MachineFunction::iterator MBBIter = BB;
15341 MF->insert(MBBIter, bumpMBB);
15342 MF->insert(MBBIter, mallocMBB);
15343 MF->insert(MBBIter, continueMBB);
15345 continueMBB->splice(continueMBB->begin(), BB, llvm::next
15346 (MachineBasicBlock::iterator(MI)), BB->end());
15347 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
15349 // Add code to the main basic block to check if the stack limit has been hit,
15350 // and if so, jump to mallocMBB otherwise to bumpMBB.
15351 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
15352 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
15353 .addReg(tmpSPVReg).addReg(sizeVReg);
15354 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr))
15355 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
15356 .addReg(SPLimitVReg);
15357 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
15359 // bumpMBB simply decreases the stack pointer, since we know the current
15360 // stacklet has enough space.
15361 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
15362 .addReg(SPLimitVReg);
15363 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
15364 .addReg(SPLimitVReg);
15365 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
15367 // Calls into a routine in libgcc to allocate more space from the heap.
15368 const uint32_t *RegMask =
15369 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
15371 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
15373 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
15374 .addExternalSymbol("__morestack_allocate_stack_space")
15375 .addRegMask(RegMask)
15376 .addReg(X86::RDI, RegState::Implicit)
15377 .addReg(X86::RAX, RegState::ImplicitDefine);
15379 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
15381 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
15382 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
15383 .addExternalSymbol("__morestack_allocate_stack_space")
15384 .addRegMask(RegMask)
15385 .addReg(X86::EAX, RegState::ImplicitDefine);
15389 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
15392 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
15393 .addReg(Is64Bit ? X86::RAX : X86::EAX);
15394 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
15396 // Set up the CFG correctly.
15397 BB->addSuccessor(bumpMBB);
15398 BB->addSuccessor(mallocMBB);
15399 mallocMBB->addSuccessor(continueMBB);
15400 bumpMBB->addSuccessor(continueMBB);
15402 // Take care of the PHI nodes.
15403 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
15404 MI->getOperand(0).getReg())
15405 .addReg(mallocPtrVReg).addMBB(mallocMBB)
15406 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
15408 // Delete the original pseudo instruction.
15409 MI->eraseFromParent();
15412 return continueMBB;
15415 MachineBasicBlock *
15416 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
15417 MachineBasicBlock *BB) const {
15418 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15419 DebugLoc DL = MI->getDebugLoc();
15421 assert(!Subtarget->isTargetEnvMacho());
15423 // The lowering is pretty easy: we're just emitting the call to _alloca. The
15424 // non-trivial part is impdef of ESP.
15426 if (Subtarget->isTargetWin64()) {
15427 if (Subtarget->isTargetCygMing()) {
15428 // ___chkstk(Mingw64):
15429 // Clobbers R10, R11, RAX and EFLAGS.
15431 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
15432 .addExternalSymbol("___chkstk")
15433 .addReg(X86::RAX, RegState::Implicit)
15434 .addReg(X86::RSP, RegState::Implicit)
15435 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
15436 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
15437 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
15439 // __chkstk(MSVCRT): does not update stack pointer.
15440 // Clobbers R10, R11 and EFLAGS.
15441 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
15442 .addExternalSymbol("__chkstk")
15443 .addReg(X86::RAX, RegState::Implicit)
15444 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
15445 // RAX has the offset to be subtracted from RSP.
15446 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
15451 const char *StackProbeSymbol =
15452 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca";
15454 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
15455 .addExternalSymbol(StackProbeSymbol)
15456 .addReg(X86::EAX, RegState::Implicit)
15457 .addReg(X86::ESP, RegState::Implicit)
15458 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
15459 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
15460 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
15463 MI->eraseFromParent(); // The pseudo instruction is gone now.
15467 MachineBasicBlock *
15468 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
15469 MachineBasicBlock *BB) const {
15470 // This is pretty easy. We're taking the value that we received from
15471 // our load from the relocation, sticking it in either RDI (x86-64)
15472 // or EAX and doing an indirect call. The return value will then
15473 // be in the normal return register.
15474 const X86InstrInfo *TII
15475 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo());
15476 DebugLoc DL = MI->getDebugLoc();
15477 MachineFunction *F = BB->getParent();
15479 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
15480 assert(MI->getOperand(3).isGlobal() && "This should be a global");
15482 // Get a register mask for the lowered call.
15483 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
15484 // proper register mask.
15485 const uint32_t *RegMask =
15486 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
15487 if (Subtarget->is64Bit()) {
15488 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
15489 TII->get(X86::MOV64rm), X86::RDI)
15491 .addImm(0).addReg(0)
15492 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
15493 MI->getOperand(3).getTargetFlags())
15495 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
15496 addDirectMem(MIB, X86::RDI);
15497 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
15498 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
15499 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
15500 TII->get(X86::MOV32rm), X86::EAX)
15502 .addImm(0).addReg(0)
15503 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
15504 MI->getOperand(3).getTargetFlags())
15506 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
15507 addDirectMem(MIB, X86::EAX);
15508 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
15510 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
15511 TII->get(X86::MOV32rm), X86::EAX)
15512 .addReg(TII->getGlobalBaseReg(F))
15513 .addImm(0).addReg(0)
15514 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
15515 MI->getOperand(3).getTargetFlags())
15517 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
15518 addDirectMem(MIB, X86::EAX);
15519 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
15522 MI->eraseFromParent(); // The pseudo instruction is gone now.
15526 MachineBasicBlock *
15527 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
15528 MachineBasicBlock *MBB) const {
15529 DebugLoc DL = MI->getDebugLoc();
15530 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15532 MachineFunction *MF = MBB->getParent();
15533 MachineRegisterInfo &MRI = MF->getRegInfo();
15535 const BasicBlock *BB = MBB->getBasicBlock();
15536 MachineFunction::iterator I = MBB;
15539 // Memory Reference
15540 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
15541 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
15544 unsigned MemOpndSlot = 0;
15546 unsigned CurOp = 0;
15548 DstReg = MI->getOperand(CurOp++).getReg();
15549 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
15550 assert(RC->hasType(MVT::i32) && "Invalid destination!");
15551 unsigned mainDstReg = MRI.createVirtualRegister(RC);
15552 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
15554 MemOpndSlot = CurOp;
15556 MVT PVT = getPointerTy();
15557 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
15558 "Invalid Pointer Size!");
15560 // For v = setjmp(buf), we generate
15563 // buf[LabelOffset] = restoreMBB
15564 // SjLjSetup restoreMBB
15570 // v = phi(main, restore)
15575 MachineBasicBlock *thisMBB = MBB;
15576 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
15577 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
15578 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
15579 MF->insert(I, mainMBB);
15580 MF->insert(I, sinkMBB);
15581 MF->push_back(restoreMBB);
15583 MachineInstrBuilder MIB;
15585 // Transfer the remainder of BB and its successor edges to sinkMBB.
15586 sinkMBB->splice(sinkMBB->begin(), MBB,
15587 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
15588 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
15591 unsigned PtrStoreOpc = 0;
15592 unsigned LabelReg = 0;
15593 const int64_t LabelOffset = 1 * PVT.getStoreSize();
15594 Reloc::Model RM = getTargetMachine().getRelocationModel();
15595 bool UseImmLabel = (getTargetMachine().getCodeModel() == CodeModel::Small) &&
15596 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
15598 // Prepare IP either in reg or imm.
15599 if (!UseImmLabel) {
15600 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
15601 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
15602 LabelReg = MRI.createVirtualRegister(PtrRC);
15603 if (Subtarget->is64Bit()) {
15604 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
15608 .addMBB(restoreMBB)
15611 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
15612 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
15613 .addReg(XII->getGlobalBaseReg(MF))
15616 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
15620 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
15622 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
15623 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
15624 if (i == X86::AddrDisp)
15625 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
15627 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
15630 MIB.addReg(LabelReg);
15632 MIB.addMBB(restoreMBB);
15633 MIB.setMemRefs(MMOBegin, MMOEnd);
15635 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
15636 .addMBB(restoreMBB);
15638 const X86RegisterInfo *RegInfo =
15639 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
15640 MIB.addRegMask(RegInfo->getNoPreservedMask());
15641 thisMBB->addSuccessor(mainMBB);
15642 thisMBB->addSuccessor(restoreMBB);
15646 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
15647 mainMBB->addSuccessor(sinkMBB);
15650 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
15651 TII->get(X86::PHI), DstReg)
15652 .addReg(mainDstReg).addMBB(mainMBB)
15653 .addReg(restoreDstReg).addMBB(restoreMBB);
15656 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
15657 BuildMI(restoreMBB, DL, TII->get(X86::JMP_4)).addMBB(sinkMBB);
15658 restoreMBB->addSuccessor(sinkMBB);
15660 MI->eraseFromParent();
15664 MachineBasicBlock *
15665 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
15666 MachineBasicBlock *MBB) const {
15667 DebugLoc DL = MI->getDebugLoc();
15668 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15670 MachineFunction *MF = MBB->getParent();
15671 MachineRegisterInfo &MRI = MF->getRegInfo();
15673 // Memory Reference
15674 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
15675 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
15677 MVT PVT = getPointerTy();
15678 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
15679 "Invalid Pointer Size!");
15681 const TargetRegisterClass *RC =
15682 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
15683 unsigned Tmp = MRI.createVirtualRegister(RC);
15684 // Since FP is only updated here but NOT referenced, it's treated as GPR.
15685 const X86RegisterInfo *RegInfo =
15686 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
15687 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
15688 unsigned SP = RegInfo->getStackRegister();
15690 MachineInstrBuilder MIB;
15692 const int64_t LabelOffset = 1 * PVT.getStoreSize();
15693 const int64_t SPOffset = 2 * PVT.getStoreSize();
15695 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
15696 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
15699 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
15700 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
15701 MIB.addOperand(MI->getOperand(i));
15702 MIB.setMemRefs(MMOBegin, MMOEnd);
15704 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
15705 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
15706 if (i == X86::AddrDisp)
15707 MIB.addDisp(MI->getOperand(i), LabelOffset);
15709 MIB.addOperand(MI->getOperand(i));
15711 MIB.setMemRefs(MMOBegin, MMOEnd);
15713 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
15714 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
15715 if (i == X86::AddrDisp)
15716 MIB.addDisp(MI->getOperand(i), SPOffset);
15718 MIB.addOperand(MI->getOperand(i));
15720 MIB.setMemRefs(MMOBegin, MMOEnd);
15722 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
15724 MI->eraseFromParent();
15728 MachineBasicBlock *
15729 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
15730 MachineBasicBlock *BB) const {
15731 switch (MI->getOpcode()) {
15732 default: llvm_unreachable("Unexpected instr type to insert");
15733 case X86::TAILJMPd64:
15734 case X86::TAILJMPr64:
15735 case X86::TAILJMPm64:
15736 llvm_unreachable("TAILJMP64 would not be touched here.");
15737 case X86::TCRETURNdi64:
15738 case X86::TCRETURNri64:
15739 case X86::TCRETURNmi64:
15741 case X86::WIN_ALLOCA:
15742 return EmitLoweredWinAlloca(MI, BB);
15743 case X86::SEG_ALLOCA_32:
15744 return EmitLoweredSegAlloca(MI, BB, false);
15745 case X86::SEG_ALLOCA_64:
15746 return EmitLoweredSegAlloca(MI, BB, true);
15747 case X86::TLSCall_32:
15748 case X86::TLSCall_64:
15749 return EmitLoweredTLSCall(MI, BB);
15750 case X86::CMOV_GR8:
15751 case X86::CMOV_FR32:
15752 case X86::CMOV_FR64:
15753 case X86::CMOV_V4F32:
15754 case X86::CMOV_V2F64:
15755 case X86::CMOV_V2I64:
15756 case X86::CMOV_V8F32:
15757 case X86::CMOV_V4F64:
15758 case X86::CMOV_V4I64:
15759 case X86::CMOV_V16F32:
15760 case X86::CMOV_V8F64:
15761 case X86::CMOV_V8I64:
15762 case X86::CMOV_GR16:
15763 case X86::CMOV_GR32:
15764 case X86::CMOV_RFP32:
15765 case X86::CMOV_RFP64:
15766 case X86::CMOV_RFP80:
15767 return EmitLoweredSelect(MI, BB);
15769 case X86::FP32_TO_INT16_IN_MEM:
15770 case X86::FP32_TO_INT32_IN_MEM:
15771 case X86::FP32_TO_INT64_IN_MEM:
15772 case X86::FP64_TO_INT16_IN_MEM:
15773 case X86::FP64_TO_INT32_IN_MEM:
15774 case X86::FP64_TO_INT64_IN_MEM:
15775 case X86::FP80_TO_INT16_IN_MEM:
15776 case X86::FP80_TO_INT32_IN_MEM:
15777 case X86::FP80_TO_INT64_IN_MEM: {
15778 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15779 DebugLoc DL = MI->getDebugLoc();
15781 // Change the floating point control register to use "round towards zero"
15782 // mode when truncating to an integer value.
15783 MachineFunction *F = BB->getParent();
15784 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
15785 addFrameReference(BuildMI(*BB, MI, DL,
15786 TII->get(X86::FNSTCW16m)), CWFrameIdx);
15788 // Load the old value of the high byte of the control word...
15790 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
15791 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
15794 // Set the high part to be round to zero...
15795 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
15798 // Reload the modified control word now...
15799 addFrameReference(BuildMI(*BB, MI, DL,
15800 TII->get(X86::FLDCW16m)), CWFrameIdx);
15802 // Restore the memory image of control word to original value
15803 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
15806 // Get the X86 opcode to use.
15808 switch (MI->getOpcode()) {
15809 default: llvm_unreachable("illegal opcode!");
15810 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
15811 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
15812 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
15813 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
15814 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
15815 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
15816 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
15817 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
15818 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
15822 MachineOperand &Op = MI->getOperand(0);
15824 AM.BaseType = X86AddressMode::RegBase;
15825 AM.Base.Reg = Op.getReg();
15827 AM.BaseType = X86AddressMode::FrameIndexBase;
15828 AM.Base.FrameIndex = Op.getIndex();
15830 Op = MI->getOperand(1);
15832 AM.Scale = Op.getImm();
15833 Op = MI->getOperand(2);
15835 AM.IndexReg = Op.getImm();
15836 Op = MI->getOperand(3);
15837 if (Op.isGlobal()) {
15838 AM.GV = Op.getGlobal();
15840 AM.Disp = Op.getImm();
15842 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
15843 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
15845 // Reload the original control word now.
15846 addFrameReference(BuildMI(*BB, MI, DL,
15847 TII->get(X86::FLDCW16m)), CWFrameIdx);
15849 MI->eraseFromParent(); // The pseudo instruction is gone now.
15852 // String/text processing lowering.
15853 case X86::PCMPISTRM128REG:
15854 case X86::VPCMPISTRM128REG:
15855 case X86::PCMPISTRM128MEM:
15856 case X86::VPCMPISTRM128MEM:
15857 case X86::PCMPESTRM128REG:
15858 case X86::VPCMPESTRM128REG:
15859 case X86::PCMPESTRM128MEM:
15860 case X86::VPCMPESTRM128MEM:
15861 assert(Subtarget->hasSSE42() &&
15862 "Target must have SSE4.2 or AVX features enabled");
15863 return EmitPCMPSTRM(MI, BB, getTargetMachine().getInstrInfo());
15865 // String/text processing lowering.
15866 case X86::PCMPISTRIREG:
15867 case X86::VPCMPISTRIREG:
15868 case X86::PCMPISTRIMEM:
15869 case X86::VPCMPISTRIMEM:
15870 case X86::PCMPESTRIREG:
15871 case X86::VPCMPESTRIREG:
15872 case X86::PCMPESTRIMEM:
15873 case X86::VPCMPESTRIMEM:
15874 assert(Subtarget->hasSSE42() &&
15875 "Target must have SSE4.2 or AVX features enabled");
15876 return EmitPCMPSTRI(MI, BB, getTargetMachine().getInstrInfo());
15878 // Thread synchronization.
15880 return EmitMonitor(MI, BB, getTargetMachine().getInstrInfo(), Subtarget);
15884 return EmitXBegin(MI, BB, getTargetMachine().getInstrInfo());
15886 // Atomic Lowering.
15887 case X86::ATOMAND8:
15888 case X86::ATOMAND16:
15889 case X86::ATOMAND32:
15890 case X86::ATOMAND64:
15893 case X86::ATOMOR16:
15894 case X86::ATOMOR32:
15895 case X86::ATOMOR64:
15897 case X86::ATOMXOR16:
15898 case X86::ATOMXOR8:
15899 case X86::ATOMXOR32:
15900 case X86::ATOMXOR64:
15902 case X86::ATOMNAND8:
15903 case X86::ATOMNAND16:
15904 case X86::ATOMNAND32:
15905 case X86::ATOMNAND64:
15907 case X86::ATOMMAX8:
15908 case X86::ATOMMAX16:
15909 case X86::ATOMMAX32:
15910 case X86::ATOMMAX64:
15912 case X86::ATOMMIN8:
15913 case X86::ATOMMIN16:
15914 case X86::ATOMMIN32:
15915 case X86::ATOMMIN64:
15917 case X86::ATOMUMAX8:
15918 case X86::ATOMUMAX16:
15919 case X86::ATOMUMAX32:
15920 case X86::ATOMUMAX64:
15922 case X86::ATOMUMIN8:
15923 case X86::ATOMUMIN16:
15924 case X86::ATOMUMIN32:
15925 case X86::ATOMUMIN64:
15926 return EmitAtomicLoadArith(MI, BB);
15928 // This group does 64-bit operations on a 32-bit host.
15929 case X86::ATOMAND6432:
15930 case X86::ATOMOR6432:
15931 case X86::ATOMXOR6432:
15932 case X86::ATOMNAND6432:
15933 case X86::ATOMADD6432:
15934 case X86::ATOMSUB6432:
15935 case X86::ATOMMAX6432:
15936 case X86::ATOMMIN6432:
15937 case X86::ATOMUMAX6432:
15938 case X86::ATOMUMIN6432:
15939 case X86::ATOMSWAP6432:
15940 return EmitAtomicLoadArith6432(MI, BB);
15942 case X86::VASTART_SAVE_XMM_REGS:
15943 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
15945 case X86::VAARG_64:
15946 return EmitVAARG64WithCustomInserter(MI, BB);
15948 case X86::EH_SjLj_SetJmp32:
15949 case X86::EH_SjLj_SetJmp64:
15950 return emitEHSjLjSetJmp(MI, BB);
15952 case X86::EH_SjLj_LongJmp32:
15953 case X86::EH_SjLj_LongJmp64:
15954 return emitEHSjLjLongJmp(MI, BB);
15958 //===----------------------------------------------------------------------===//
15959 // X86 Optimization Hooks
15960 //===----------------------------------------------------------------------===//
15962 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
15965 const SelectionDAG &DAG,
15966 unsigned Depth) const {
15967 unsigned BitWidth = KnownZero.getBitWidth();
15968 unsigned Opc = Op.getOpcode();
15969 assert((Opc >= ISD::BUILTIN_OP_END ||
15970 Opc == ISD::INTRINSIC_WO_CHAIN ||
15971 Opc == ISD::INTRINSIC_W_CHAIN ||
15972 Opc == ISD::INTRINSIC_VOID) &&
15973 "Should use MaskedValueIsZero if you don't know whether Op"
15974 " is a target node!");
15976 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
15990 // These nodes' second result is a boolean.
15991 if (Op.getResNo() == 0)
15994 case X86ISD::SETCC:
15995 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
15997 case ISD::INTRINSIC_WO_CHAIN: {
15998 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15999 unsigned NumLoBits = 0;
16002 case Intrinsic::x86_sse_movmsk_ps:
16003 case Intrinsic::x86_avx_movmsk_ps_256:
16004 case Intrinsic::x86_sse2_movmsk_pd:
16005 case Intrinsic::x86_avx_movmsk_pd_256:
16006 case Intrinsic::x86_mmx_pmovmskb:
16007 case Intrinsic::x86_sse2_pmovmskb_128:
16008 case Intrinsic::x86_avx2_pmovmskb: {
16009 // High bits of movmskp{s|d}, pmovmskb are known zero.
16011 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16012 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
16013 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
16014 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
16015 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
16016 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
16017 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
16018 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
16020 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
16029 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
16030 unsigned Depth) const {
16031 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
16032 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
16033 return Op.getValueType().getScalarType().getSizeInBits();
16039 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
16040 /// node is a GlobalAddress + offset.
16041 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
16042 const GlobalValue* &GA,
16043 int64_t &Offset) const {
16044 if (N->getOpcode() == X86ISD::Wrapper) {
16045 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
16046 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
16047 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
16051 return TargetLowering::isGAPlusOffset(N, GA, Offset);
16054 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
16055 /// same as extracting the high 128-bit part of 256-bit vector and then
16056 /// inserting the result into the low part of a new 256-bit vector
16057 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
16058 EVT VT = SVOp->getValueType(0);
16059 unsigned NumElems = VT.getVectorNumElements();
16061 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
16062 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
16063 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
16064 SVOp->getMaskElt(j) >= 0)
16070 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
16071 /// same as extracting the low 128-bit part of 256-bit vector and then
16072 /// inserting the result into the high part of a new 256-bit vector
16073 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
16074 EVT VT = SVOp->getValueType(0);
16075 unsigned NumElems = VT.getVectorNumElements();
16077 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
16078 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
16079 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
16080 SVOp->getMaskElt(j) >= 0)
16086 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
16087 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
16088 TargetLowering::DAGCombinerInfo &DCI,
16089 const X86Subtarget* Subtarget) {
16091 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
16092 SDValue V1 = SVOp->getOperand(0);
16093 SDValue V2 = SVOp->getOperand(1);
16094 EVT VT = SVOp->getValueType(0);
16095 unsigned NumElems = VT.getVectorNumElements();
16097 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
16098 V2.getOpcode() == ISD::CONCAT_VECTORS) {
16102 // V UNDEF BUILD_VECTOR UNDEF
16104 // CONCAT_VECTOR CONCAT_VECTOR
16107 // RESULT: V + zero extended
16109 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
16110 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
16111 V1.getOperand(1).getOpcode() != ISD::UNDEF)
16114 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
16117 // To match the shuffle mask, the first half of the mask should
16118 // be exactly the first vector, and all the rest a splat with the
16119 // first element of the second one.
16120 for (unsigned i = 0; i != NumElems/2; ++i)
16121 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
16122 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
16125 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
16126 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
16127 if (Ld->hasNUsesOfValue(1, 0)) {
16128 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
16129 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
16131 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
16132 array_lengthof(Ops),
16134 Ld->getPointerInfo(),
16135 Ld->getAlignment(),
16136 false/*isVolatile*/, true/*ReadMem*/,
16137 false/*WriteMem*/);
16139 // Make sure the newly-created LOAD is in the same position as Ld in
16140 // terms of dependency. We create a TokenFactor for Ld and ResNode,
16141 // and update uses of Ld's output chain to use the TokenFactor.
16142 if (Ld->hasAnyUseOfValue(1)) {
16143 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
16144 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
16145 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
16146 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
16147 SDValue(ResNode.getNode(), 1));
16150 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
16154 // Emit a zeroed vector and insert the desired subvector on its
16156 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
16157 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
16158 return DCI.CombineTo(N, InsV);
16161 //===--------------------------------------------------------------------===//
16162 // Combine some shuffles into subvector extracts and inserts:
16165 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
16166 if (isShuffleHigh128VectorInsertLow(SVOp)) {
16167 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
16168 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
16169 return DCI.CombineTo(N, InsV);
16172 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
16173 if (isShuffleLow128VectorInsertHigh(SVOp)) {
16174 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
16175 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
16176 return DCI.CombineTo(N, InsV);
16182 /// PerformShuffleCombine - Performs several different shuffle combines.
16183 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
16184 TargetLowering::DAGCombinerInfo &DCI,
16185 const X86Subtarget *Subtarget) {
16187 EVT VT = N->getValueType(0);
16189 // Don't create instructions with illegal types after legalize types has run.
16190 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16191 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
16194 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
16195 if (Subtarget->hasFp256() && VT.is256BitVector() &&
16196 N->getOpcode() == ISD::VECTOR_SHUFFLE)
16197 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
16199 // Only handle 128 wide vector from here on.
16200 if (!VT.is128BitVector())
16203 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
16204 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
16205 // consecutive, non-overlapping, and in the right order.
16206 SmallVector<SDValue, 16> Elts;
16207 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
16208 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
16210 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG);
16213 /// PerformTruncateCombine - Converts truncate operation to
16214 /// a sequence of vector shuffle operations.
16215 /// It is possible when we truncate 256-bit vector to 128-bit vector
16216 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
16217 TargetLowering::DAGCombinerInfo &DCI,
16218 const X86Subtarget *Subtarget) {
16222 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
16223 /// specific shuffle of a load can be folded into a single element load.
16224 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
16225 /// shuffles have been customed lowered so we need to handle those here.
16226 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
16227 TargetLowering::DAGCombinerInfo &DCI) {
16228 if (DCI.isBeforeLegalizeOps())
16231 SDValue InVec = N->getOperand(0);
16232 SDValue EltNo = N->getOperand(1);
16234 if (!isa<ConstantSDNode>(EltNo))
16237 EVT VT = InVec.getValueType();
16239 bool HasShuffleIntoBitcast = false;
16240 if (InVec.getOpcode() == ISD::BITCAST) {
16241 // Don't duplicate a load with other uses.
16242 if (!InVec.hasOneUse())
16244 EVT BCVT = InVec.getOperand(0).getValueType();
16245 if (BCVT.getVectorNumElements() != VT.getVectorNumElements())
16247 InVec = InVec.getOperand(0);
16248 HasShuffleIntoBitcast = true;
16251 if (!isTargetShuffle(InVec.getOpcode()))
16254 // Don't duplicate a load with other uses.
16255 if (!InVec.hasOneUse())
16258 SmallVector<int, 16> ShuffleMask;
16260 if (!getTargetShuffleMask(InVec.getNode(), VT.getSimpleVT(), ShuffleMask,
16264 // Select the input vector, guarding against out of range extract vector.
16265 unsigned NumElems = VT.getVectorNumElements();
16266 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
16267 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
16268 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
16269 : InVec.getOperand(1);
16271 // If inputs to shuffle are the same for both ops, then allow 2 uses
16272 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
16274 if (LdNode.getOpcode() == ISD::BITCAST) {
16275 // Don't duplicate a load with other uses.
16276 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
16279 AllowedUses = 1; // only allow 1 load use if we have a bitcast
16280 LdNode = LdNode.getOperand(0);
16283 if (!ISD::isNormalLoad(LdNode.getNode()))
16286 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
16288 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
16291 if (HasShuffleIntoBitcast) {
16292 // If there's a bitcast before the shuffle, check if the load type and
16293 // alignment is valid.
16294 unsigned Align = LN0->getAlignment();
16295 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16296 unsigned NewAlign = TLI.getDataLayout()->
16297 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
16299 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
16303 // All checks match so transform back to vector_shuffle so that DAG combiner
16304 // can finish the job
16307 // Create shuffle node taking into account the case that its a unary shuffle
16308 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1);
16309 Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl,
16310 InVec.getOperand(0), Shuffle,
16312 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
16313 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
16317 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
16318 /// generation and convert it from being a bunch of shuffles and extracts
16319 /// to a simple store and scalar loads to extract the elements.
16320 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
16321 TargetLowering::DAGCombinerInfo &DCI) {
16322 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
16323 if (NewOp.getNode())
16326 SDValue InputVector = N->getOperand(0);
16327 // Detect whether we are trying to convert from mmx to i32 and the bitcast
16328 // from mmx to v2i32 has a single usage.
16329 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
16330 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
16331 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
16332 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
16333 N->getValueType(0),
16334 InputVector.getNode()->getOperand(0));
16336 // Only operate on vectors of 4 elements, where the alternative shuffling
16337 // gets to be more expensive.
16338 if (InputVector.getValueType() != MVT::v4i32)
16341 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
16342 // single use which is a sign-extend or zero-extend, and all elements are
16344 SmallVector<SDNode *, 4> Uses;
16345 unsigned ExtractedElements = 0;
16346 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
16347 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
16348 if (UI.getUse().getResNo() != InputVector.getResNo())
16351 SDNode *Extract = *UI;
16352 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
16355 if (Extract->getValueType(0) != MVT::i32)
16357 if (!Extract->hasOneUse())
16359 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
16360 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
16362 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
16365 // Record which element was extracted.
16366 ExtractedElements |=
16367 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
16369 Uses.push_back(Extract);
16372 // If not all the elements were used, this may not be worthwhile.
16373 if (ExtractedElements != 15)
16376 // Ok, we've now decided to do the transformation.
16377 SDLoc dl(InputVector);
16379 // Store the value to a temporary stack slot.
16380 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
16381 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
16382 MachinePointerInfo(), false, false, 0);
16384 // Replace each use (extract) with a load of the appropriate element.
16385 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
16386 UE = Uses.end(); UI != UE; ++UI) {
16387 SDNode *Extract = *UI;
16389 // cOMpute the element's address.
16390 SDValue Idx = Extract->getOperand(1);
16392 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
16393 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
16394 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16395 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
16397 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
16398 StackPtr, OffsetVal);
16400 // Load the scalar.
16401 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
16402 ScalarAddr, MachinePointerInfo(),
16403 false, false, false, 0);
16405 // Replace the exact with the load.
16406 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
16409 // The replacement was made in place; don't return anything.
16413 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
16414 static std::pair<unsigned, bool>
16415 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
16416 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
16417 if (!VT.isVector())
16418 return std::make_pair(0, false);
16420 bool NeedSplit = false;
16421 switch (VT.getSimpleVT().SimpleTy) {
16422 default: return std::make_pair(0, false);
16426 if (!Subtarget->hasAVX2())
16428 if (!Subtarget->hasAVX())
16429 return std::make_pair(0, false);
16434 if (!Subtarget->hasSSE2())
16435 return std::make_pair(0, false);
16438 // SSE2 has only a small subset of the operations.
16439 bool hasUnsigned = Subtarget->hasSSE41() ||
16440 (Subtarget->hasSSE2() && VT == MVT::v16i8);
16441 bool hasSigned = Subtarget->hasSSE41() ||
16442 (Subtarget->hasSSE2() && VT == MVT::v8i16);
16444 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
16447 // Check for x CC y ? x : y.
16448 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
16449 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
16454 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
16457 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
16460 Opc = hasSigned ? X86ISD::SMIN : 0; break;
16463 Opc = hasSigned ? X86ISD::SMAX : 0; break;
16465 // Check for x CC y ? y : x -- a min/max with reversed arms.
16466 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
16467 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
16472 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
16475 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
16478 Opc = hasSigned ? X86ISD::SMAX : 0; break;
16481 Opc = hasSigned ? X86ISD::SMIN : 0; break;
16485 return std::make_pair(Opc, NeedSplit);
16488 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
16490 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
16491 TargetLowering::DAGCombinerInfo &DCI,
16492 const X86Subtarget *Subtarget) {
16494 SDValue Cond = N->getOperand(0);
16495 // Get the LHS/RHS of the select.
16496 SDValue LHS = N->getOperand(1);
16497 SDValue RHS = N->getOperand(2);
16498 EVT VT = LHS.getValueType();
16499 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16501 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
16502 // instructions match the semantics of the common C idiom x<y?x:y but not
16503 // x<=y?x:y, because of how they handle negative zero (which can be
16504 // ignored in unsafe-math mode).
16505 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
16506 VT != MVT::f80 && TLI.isTypeLegal(VT) &&
16507 (Subtarget->hasSSE2() ||
16508 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
16509 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
16511 unsigned Opcode = 0;
16512 // Check for x CC y ? x : y.
16513 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
16514 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
16518 // Converting this to a min would handle NaNs incorrectly, and swapping
16519 // the operands would cause it to handle comparisons between positive
16520 // and negative zero incorrectly.
16521 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
16522 if (!DAG.getTarget().Options.UnsafeFPMath &&
16523 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
16525 std::swap(LHS, RHS);
16527 Opcode = X86ISD::FMIN;
16530 // Converting this to a min would handle comparisons between positive
16531 // and negative zero incorrectly.
16532 if (!DAG.getTarget().Options.UnsafeFPMath &&
16533 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
16535 Opcode = X86ISD::FMIN;
16538 // Converting this to a min would handle both negative zeros and NaNs
16539 // incorrectly, but we can swap the operands to fix both.
16540 std::swap(LHS, RHS);
16544 Opcode = X86ISD::FMIN;
16548 // Converting this to a max would handle comparisons between positive
16549 // and negative zero incorrectly.
16550 if (!DAG.getTarget().Options.UnsafeFPMath &&
16551 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
16553 Opcode = X86ISD::FMAX;
16556 // Converting this to a max would handle NaNs incorrectly, and swapping
16557 // the operands would cause it to handle comparisons between positive
16558 // and negative zero incorrectly.
16559 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
16560 if (!DAG.getTarget().Options.UnsafeFPMath &&
16561 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
16563 std::swap(LHS, RHS);
16565 Opcode = X86ISD::FMAX;
16568 // Converting this to a max would handle both negative zeros and NaNs
16569 // incorrectly, but we can swap the operands to fix both.
16570 std::swap(LHS, RHS);
16574 Opcode = X86ISD::FMAX;
16577 // Check for x CC y ? y : x -- a min/max with reversed arms.
16578 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
16579 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
16583 // Converting this to a min would handle comparisons between positive
16584 // and negative zero incorrectly, and swapping the operands would
16585 // cause it to handle NaNs incorrectly.
16586 if (!DAG.getTarget().Options.UnsafeFPMath &&
16587 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
16588 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
16590 std::swap(LHS, RHS);
16592 Opcode = X86ISD::FMIN;
16595 // Converting this to a min would handle NaNs incorrectly.
16596 if (!DAG.getTarget().Options.UnsafeFPMath &&
16597 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
16599 Opcode = X86ISD::FMIN;
16602 // Converting this to a min would handle both negative zeros and NaNs
16603 // incorrectly, but we can swap the operands to fix both.
16604 std::swap(LHS, RHS);
16608 Opcode = X86ISD::FMIN;
16612 // Converting this to a max would handle NaNs incorrectly.
16613 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
16615 Opcode = X86ISD::FMAX;
16618 // Converting this to a max would handle comparisons between positive
16619 // and negative zero incorrectly, and swapping the operands would
16620 // cause it to handle NaNs incorrectly.
16621 if (!DAG.getTarget().Options.UnsafeFPMath &&
16622 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
16623 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
16625 std::swap(LHS, RHS);
16627 Opcode = X86ISD::FMAX;
16630 // Converting this to a max would handle both negative zeros and NaNs
16631 // incorrectly, but we can swap the operands to fix both.
16632 std::swap(LHS, RHS);
16636 Opcode = X86ISD::FMAX;
16642 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
16645 EVT CondVT = Cond.getValueType();
16646 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
16647 CondVT.getVectorElementType() == MVT::i1) {
16648 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
16649 // lowering on AVX-512. In this case we convert it to
16650 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
16651 // The same situation for all 128 and 256-bit vectors of i8 and i16
16652 EVT OpVT = LHS.getValueType();
16653 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
16654 (OpVT.getVectorElementType() == MVT::i8 ||
16655 OpVT.getVectorElementType() == MVT::i16)) {
16656 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
16657 DCI.AddToWorklist(Cond.getNode());
16658 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
16661 // If this is a select between two integer constants, try to do some
16663 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
16664 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
16665 // Don't do this for crazy integer types.
16666 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
16667 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
16668 // so that TrueC (the true value) is larger than FalseC.
16669 bool NeedsCondInvert = false;
16671 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
16672 // Efficiently invertible.
16673 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
16674 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
16675 isa<ConstantSDNode>(Cond.getOperand(1))))) {
16676 NeedsCondInvert = true;
16677 std::swap(TrueC, FalseC);
16680 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
16681 if (FalseC->getAPIntValue() == 0 &&
16682 TrueC->getAPIntValue().isPowerOf2()) {
16683 if (NeedsCondInvert) // Invert the condition if needed.
16684 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
16685 DAG.getConstant(1, Cond.getValueType()));
16687 // Zero extend the condition if needed.
16688 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
16690 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
16691 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
16692 DAG.getConstant(ShAmt, MVT::i8));
16695 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
16696 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
16697 if (NeedsCondInvert) // Invert the condition if needed.
16698 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
16699 DAG.getConstant(1, Cond.getValueType()));
16701 // Zero extend the condition if needed.
16702 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
16703 FalseC->getValueType(0), Cond);
16704 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
16705 SDValue(FalseC, 0));
16708 // Optimize cases that will turn into an LEA instruction. This requires
16709 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
16710 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
16711 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
16712 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
16714 bool isFastMultiplier = false;
16716 switch ((unsigned char)Diff) {
16718 case 1: // result = add base, cond
16719 case 2: // result = lea base( , cond*2)
16720 case 3: // result = lea base(cond, cond*2)
16721 case 4: // result = lea base( , cond*4)
16722 case 5: // result = lea base(cond, cond*4)
16723 case 8: // result = lea base( , cond*8)
16724 case 9: // result = lea base(cond, cond*8)
16725 isFastMultiplier = true;
16730 if (isFastMultiplier) {
16731 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
16732 if (NeedsCondInvert) // Invert the condition if needed.
16733 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
16734 DAG.getConstant(1, Cond.getValueType()));
16736 // Zero extend the condition if needed.
16737 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
16739 // Scale the condition by the difference.
16741 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
16742 DAG.getConstant(Diff, Cond.getValueType()));
16744 // Add the base if non-zero.
16745 if (FalseC->getAPIntValue() != 0)
16746 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
16747 SDValue(FalseC, 0));
16754 // Canonicalize max and min:
16755 // (x > y) ? x : y -> (x >= y) ? x : y
16756 // (x < y) ? x : y -> (x <= y) ? x : y
16757 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
16758 // the need for an extra compare
16759 // against zero. e.g.
16760 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
16762 // testl %edi, %edi
16764 // cmovgl %edi, %eax
16768 // cmovsl %eax, %edi
16769 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
16770 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
16771 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
16772 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
16777 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
16778 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
16779 Cond.getOperand(0), Cond.getOperand(1), NewCC);
16780 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
16785 // Early exit check
16786 if (!TLI.isTypeLegal(VT))
16789 // Match VSELECTs into subs with unsigned saturation.
16790 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
16791 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
16792 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
16793 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
16794 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
16796 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
16797 // left side invert the predicate to simplify logic below.
16799 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
16801 CC = ISD::getSetCCInverse(CC, true);
16802 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
16806 if (Other.getNode() && Other->getNumOperands() == 2 &&
16807 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
16808 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
16809 SDValue CondRHS = Cond->getOperand(1);
16811 // Look for a general sub with unsigned saturation first.
16812 // x >= y ? x-y : 0 --> subus x, y
16813 // x > y ? x-y : 0 --> subus x, y
16814 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
16815 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
16816 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
16818 // If the RHS is a constant we have to reverse the const canonicalization.
16819 // x > C-1 ? x+-C : 0 --> subus x, C
16820 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
16821 isSplatVector(CondRHS.getNode()) && isSplatVector(OpRHS.getNode())) {
16822 APInt A = cast<ConstantSDNode>(OpRHS.getOperand(0))->getAPIntValue();
16823 if (CondRHS.getConstantOperandVal(0) == -A-1)
16824 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS,
16825 DAG.getConstant(-A, VT));
16828 // Another special case: If C was a sign bit, the sub has been
16829 // canonicalized into a xor.
16830 // FIXME: Would it be better to use ComputeMaskedBits to determine whether
16831 // it's safe to decanonicalize the xor?
16832 // x s< 0 ? x^C : 0 --> subus x, C
16833 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
16834 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
16835 isSplatVector(OpRHS.getNode())) {
16836 APInt A = cast<ConstantSDNode>(OpRHS.getOperand(0))->getAPIntValue();
16838 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
16843 // Try to match a min/max vector operation.
16844 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
16845 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
16846 unsigned Opc = ret.first;
16847 bool NeedSplit = ret.second;
16849 if (Opc && NeedSplit) {
16850 unsigned NumElems = VT.getVectorNumElements();
16851 // Extract the LHS vectors
16852 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
16853 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
16855 // Extract the RHS vectors
16856 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
16857 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
16859 // Create min/max for each subvector
16860 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
16861 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
16863 // Merge the result
16864 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
16866 return DAG.getNode(Opc, DL, VT, LHS, RHS);
16869 // Simplify vector selection if the selector will be produced by CMPP*/PCMP*.
16870 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
16871 // Check if SETCC has already been promoted
16872 TLI.getSetCCResultType(*DAG.getContext(), VT) == Cond.getValueType()) {
16874 assert(Cond.getValueType().isVector() &&
16875 "vector select expects a vector selector!");
16877 EVT IntVT = Cond.getValueType();
16878 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
16879 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
16881 if (!TValIsAllOnes && !FValIsAllZeros) {
16882 // Try invert the condition if true value is not all 1s and false value
16884 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
16885 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
16887 if (TValIsAllZeros || FValIsAllOnes) {
16888 SDValue CC = Cond.getOperand(2);
16889 ISD::CondCode NewCC =
16890 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
16891 Cond.getOperand(0).getValueType().isInteger());
16892 Cond = DAG.getSetCC(DL, IntVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
16893 std::swap(LHS, RHS);
16894 TValIsAllOnes = FValIsAllOnes;
16895 FValIsAllZeros = TValIsAllZeros;
16899 if (TValIsAllOnes || FValIsAllZeros) {
16902 if (TValIsAllOnes && FValIsAllZeros)
16904 else if (TValIsAllOnes)
16905 Ret = DAG.getNode(ISD::OR, DL, IntVT, Cond,
16906 DAG.getNode(ISD::BITCAST, DL, IntVT, RHS));
16907 else if (FValIsAllZeros)
16908 Ret = DAG.getNode(ISD::AND, DL, IntVT, Cond,
16909 DAG.getNode(ISD::BITCAST, DL, IntVT, LHS));
16911 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
16915 // If we know that this node is legal then we know that it is going to be
16916 // matched by one of the SSE/AVX BLEND instructions. These instructions only
16917 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
16918 // to simplify previous instructions.
16919 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
16920 !DCI.isBeforeLegalize() && TLI.isOperationLegal(ISD::VSELECT, VT)) {
16921 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
16923 // Don't optimize vector selects that map to mask-registers.
16927 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
16928 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
16930 APInt KnownZero, KnownOne;
16931 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
16932 DCI.isBeforeLegalizeOps());
16933 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
16934 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO))
16935 DCI.CommitTargetLoweringOpt(TLO);
16941 // Check whether a boolean test is testing a boolean value generated by
16942 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
16945 // Simplify the following patterns:
16946 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
16947 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
16948 // to (Op EFLAGS Cond)
16950 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
16951 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
16952 // to (Op EFLAGS !Cond)
16954 // where Op could be BRCOND or CMOV.
16956 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
16957 // Quit if not CMP and SUB with its value result used.
16958 if (Cmp.getOpcode() != X86ISD::CMP &&
16959 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
16962 // Quit if not used as a boolean value.
16963 if (CC != X86::COND_E && CC != X86::COND_NE)
16966 // Check CMP operands. One of them should be 0 or 1 and the other should be
16967 // an SetCC or extended from it.
16968 SDValue Op1 = Cmp.getOperand(0);
16969 SDValue Op2 = Cmp.getOperand(1);
16972 const ConstantSDNode* C = 0;
16973 bool needOppositeCond = (CC == X86::COND_E);
16974 bool checkAgainstTrue = false; // Is it a comparison against 1?
16976 if ((C = dyn_cast<ConstantSDNode>(Op1)))
16978 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
16980 else // Quit if all operands are not constants.
16983 if (C->getZExtValue() == 1) {
16984 needOppositeCond = !needOppositeCond;
16985 checkAgainstTrue = true;
16986 } else if (C->getZExtValue() != 0)
16987 // Quit if the constant is neither 0 or 1.
16990 bool truncatedToBoolWithAnd = false;
16991 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
16992 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
16993 SetCC.getOpcode() == ISD::TRUNCATE ||
16994 SetCC.getOpcode() == ISD::AND) {
16995 if (SetCC.getOpcode() == ISD::AND) {
16997 ConstantSDNode *CS;
16998 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
16999 CS->getZExtValue() == 1)
17001 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
17002 CS->getZExtValue() == 1)
17006 SetCC = SetCC.getOperand(OpIdx);
17007 truncatedToBoolWithAnd = true;
17009 SetCC = SetCC.getOperand(0);
17012 switch (SetCC.getOpcode()) {
17013 case X86ISD::SETCC_CARRY:
17014 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
17015 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
17016 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
17017 // truncated to i1 using 'and'.
17018 if (checkAgainstTrue && !truncatedToBoolWithAnd)
17020 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
17021 "Invalid use of SETCC_CARRY!");
17023 case X86ISD::SETCC:
17024 // Set the condition code or opposite one if necessary.
17025 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
17026 if (needOppositeCond)
17027 CC = X86::GetOppositeBranchCondition(CC);
17028 return SetCC.getOperand(1);
17029 case X86ISD::CMOV: {
17030 // Check whether false/true value has canonical one, i.e. 0 or 1.
17031 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
17032 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
17033 // Quit if true value is not a constant.
17036 // Quit if false value is not a constant.
17038 SDValue Op = SetCC.getOperand(0);
17039 // Skip 'zext' or 'trunc' node.
17040 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
17041 Op.getOpcode() == ISD::TRUNCATE)
17042 Op = Op.getOperand(0);
17043 // A special case for rdrand/rdseed, where 0 is set if false cond is
17045 if ((Op.getOpcode() != X86ISD::RDRAND &&
17046 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
17049 // Quit if false value is not the constant 0 or 1.
17050 bool FValIsFalse = true;
17051 if (FVal && FVal->getZExtValue() != 0) {
17052 if (FVal->getZExtValue() != 1)
17054 // If FVal is 1, opposite cond is needed.
17055 needOppositeCond = !needOppositeCond;
17056 FValIsFalse = false;
17058 // Quit if TVal is not the constant opposite of FVal.
17059 if (FValIsFalse && TVal->getZExtValue() != 1)
17061 if (!FValIsFalse && TVal->getZExtValue() != 0)
17063 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
17064 if (needOppositeCond)
17065 CC = X86::GetOppositeBranchCondition(CC);
17066 return SetCC.getOperand(3);
17073 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
17074 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
17075 TargetLowering::DAGCombinerInfo &DCI,
17076 const X86Subtarget *Subtarget) {
17079 // If the flag operand isn't dead, don't touch this CMOV.
17080 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
17083 SDValue FalseOp = N->getOperand(0);
17084 SDValue TrueOp = N->getOperand(1);
17085 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
17086 SDValue Cond = N->getOperand(3);
17088 if (CC == X86::COND_E || CC == X86::COND_NE) {
17089 switch (Cond.getOpcode()) {
17093 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
17094 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
17095 return (CC == X86::COND_E) ? FalseOp : TrueOp;
17101 Flags = checkBoolTestSetCCCombine(Cond, CC);
17102 if (Flags.getNode() &&
17103 // Extra check as FCMOV only supports a subset of X86 cond.
17104 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
17105 SDValue Ops[] = { FalseOp, TrueOp,
17106 DAG.getConstant(CC, MVT::i8), Flags };
17107 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(),
17108 Ops, array_lengthof(Ops));
17111 // If this is a select between two integer constants, try to do some
17112 // optimizations. Note that the operands are ordered the opposite of SELECT
17114 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
17115 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
17116 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
17117 // larger than FalseC (the false value).
17118 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
17119 CC = X86::GetOppositeBranchCondition(CC);
17120 std::swap(TrueC, FalseC);
17121 std::swap(TrueOp, FalseOp);
17124 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
17125 // This is efficient for any integer data type (including i8/i16) and
17127 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
17128 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
17129 DAG.getConstant(CC, MVT::i8), Cond);
17131 // Zero extend the condition if needed.
17132 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
17134 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
17135 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
17136 DAG.getConstant(ShAmt, MVT::i8));
17137 if (N->getNumValues() == 2) // Dead flag value?
17138 return DCI.CombineTo(N, Cond, SDValue());
17142 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
17143 // for any integer data type, including i8/i16.
17144 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
17145 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
17146 DAG.getConstant(CC, MVT::i8), Cond);
17148 // Zero extend the condition if needed.
17149 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
17150 FalseC->getValueType(0), Cond);
17151 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
17152 SDValue(FalseC, 0));
17154 if (N->getNumValues() == 2) // Dead flag value?
17155 return DCI.CombineTo(N, Cond, SDValue());
17159 // Optimize cases that will turn into an LEA instruction. This requires
17160 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
17161 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
17162 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
17163 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
17165 bool isFastMultiplier = false;
17167 switch ((unsigned char)Diff) {
17169 case 1: // result = add base, cond
17170 case 2: // result = lea base( , cond*2)
17171 case 3: // result = lea base(cond, cond*2)
17172 case 4: // result = lea base( , cond*4)
17173 case 5: // result = lea base(cond, cond*4)
17174 case 8: // result = lea base( , cond*8)
17175 case 9: // result = lea base(cond, cond*8)
17176 isFastMultiplier = true;
17181 if (isFastMultiplier) {
17182 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
17183 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
17184 DAG.getConstant(CC, MVT::i8), Cond);
17185 // Zero extend the condition if needed.
17186 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
17188 // Scale the condition by the difference.
17190 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
17191 DAG.getConstant(Diff, Cond.getValueType()));
17193 // Add the base if non-zero.
17194 if (FalseC->getAPIntValue() != 0)
17195 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
17196 SDValue(FalseC, 0));
17197 if (N->getNumValues() == 2) // Dead flag value?
17198 return DCI.CombineTo(N, Cond, SDValue());
17205 // Handle these cases:
17206 // (select (x != c), e, c) -> select (x != c), e, x),
17207 // (select (x == c), c, e) -> select (x == c), x, e)
17208 // where the c is an integer constant, and the "select" is the combination
17209 // of CMOV and CMP.
17211 // The rationale for this change is that the conditional-move from a constant
17212 // needs two instructions, however, conditional-move from a register needs
17213 // only one instruction.
17215 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
17216 // some instruction-combining opportunities. This opt needs to be
17217 // postponed as late as possible.
17219 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
17220 // the DCI.xxxx conditions are provided to postpone the optimization as
17221 // late as possible.
17223 ConstantSDNode *CmpAgainst = 0;
17224 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
17225 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
17226 !isa<ConstantSDNode>(Cond.getOperand(0))) {
17228 if (CC == X86::COND_NE &&
17229 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
17230 CC = X86::GetOppositeBranchCondition(CC);
17231 std::swap(TrueOp, FalseOp);
17234 if (CC == X86::COND_E &&
17235 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
17236 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
17237 DAG.getConstant(CC, MVT::i8), Cond };
17238 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops,
17239 array_lengthof(Ops));
17247 /// PerformMulCombine - Optimize a single multiply with constant into two
17248 /// in order to implement it with two cheaper instructions, e.g.
17249 /// LEA + SHL, LEA + LEA.
17250 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
17251 TargetLowering::DAGCombinerInfo &DCI) {
17252 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
17255 EVT VT = N->getValueType(0);
17256 if (VT != MVT::i64)
17259 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
17262 uint64_t MulAmt = C->getZExtValue();
17263 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
17266 uint64_t MulAmt1 = 0;
17267 uint64_t MulAmt2 = 0;
17268 if ((MulAmt % 9) == 0) {
17270 MulAmt2 = MulAmt / 9;
17271 } else if ((MulAmt % 5) == 0) {
17273 MulAmt2 = MulAmt / 5;
17274 } else if ((MulAmt % 3) == 0) {
17276 MulAmt2 = MulAmt / 3;
17279 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
17282 if (isPowerOf2_64(MulAmt2) &&
17283 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
17284 // If second multiplifer is pow2, issue it first. We want the multiply by
17285 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
17287 std::swap(MulAmt1, MulAmt2);
17290 if (isPowerOf2_64(MulAmt1))
17291 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
17292 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
17294 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
17295 DAG.getConstant(MulAmt1, VT));
17297 if (isPowerOf2_64(MulAmt2))
17298 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
17299 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
17301 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
17302 DAG.getConstant(MulAmt2, VT));
17304 // Do not add new nodes to DAG combiner worklist.
17305 DCI.CombineTo(N, NewMul, false);
17310 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
17311 SDValue N0 = N->getOperand(0);
17312 SDValue N1 = N->getOperand(1);
17313 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
17314 EVT VT = N0.getValueType();
17316 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
17317 // since the result of setcc_c is all zero's or all ones.
17318 if (VT.isInteger() && !VT.isVector() &&
17319 N1C && N0.getOpcode() == ISD::AND &&
17320 N0.getOperand(1).getOpcode() == ISD::Constant) {
17321 SDValue N00 = N0.getOperand(0);
17322 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
17323 ((N00.getOpcode() == ISD::ANY_EXTEND ||
17324 N00.getOpcode() == ISD::ZERO_EXTEND) &&
17325 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
17326 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
17327 APInt ShAmt = N1C->getAPIntValue();
17328 Mask = Mask.shl(ShAmt);
17330 return DAG.getNode(ISD::AND, SDLoc(N), VT,
17331 N00, DAG.getConstant(Mask, VT));
17335 // Hardware support for vector shifts is sparse which makes us scalarize the
17336 // vector operations in many cases. Also, on sandybridge ADD is faster than
17338 // (shl V, 1) -> add V,V
17339 if (isSplatVector(N1.getNode())) {
17340 assert(N0.getValueType().isVector() && "Invalid vector shift type");
17341 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1->getOperand(0));
17342 // We shift all of the values by one. In many cases we do not have
17343 // hardware support for this operation. This is better expressed as an ADD
17345 if (N1C && (1 == N1C->getZExtValue())) {
17346 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
17353 /// \brief Returns a vector of 0s if the node in input is a vector logical
17354 /// shift by a constant amount which is known to be bigger than or equal
17355 /// to the vector element size in bits.
17356 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
17357 const X86Subtarget *Subtarget) {
17358 EVT VT = N->getValueType(0);
17360 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
17361 (!Subtarget->hasInt256() ||
17362 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
17365 SDValue Amt = N->getOperand(1);
17367 if (isSplatVector(Amt.getNode())) {
17368 SDValue SclrAmt = Amt->getOperand(0);
17369 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
17370 APInt ShiftAmt = C->getAPIntValue();
17371 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
17373 // SSE2/AVX2 logical shifts always return a vector of 0s
17374 // if the shift amount is bigger than or equal to
17375 // the element size. The constant shift amount will be
17376 // encoded as a 8-bit immediate.
17377 if (ShiftAmt.trunc(8).uge(MaxAmount))
17378 return getZeroVector(VT, Subtarget, DAG, DL);
17385 /// PerformShiftCombine - Combine shifts.
17386 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
17387 TargetLowering::DAGCombinerInfo &DCI,
17388 const X86Subtarget *Subtarget) {
17389 if (N->getOpcode() == ISD::SHL) {
17390 SDValue V = PerformSHLCombine(N, DAG);
17391 if (V.getNode()) return V;
17394 if (N->getOpcode() != ISD::SRA) {
17395 // Try to fold this logical shift into a zero vector.
17396 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
17397 if (V.getNode()) return V;
17403 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
17404 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
17405 // and friends. Likewise for OR -> CMPNEQSS.
17406 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
17407 TargetLowering::DAGCombinerInfo &DCI,
17408 const X86Subtarget *Subtarget) {
17411 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
17412 // we're requiring SSE2 for both.
17413 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
17414 SDValue N0 = N->getOperand(0);
17415 SDValue N1 = N->getOperand(1);
17416 SDValue CMP0 = N0->getOperand(1);
17417 SDValue CMP1 = N1->getOperand(1);
17420 // The SETCCs should both refer to the same CMP.
17421 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
17424 SDValue CMP00 = CMP0->getOperand(0);
17425 SDValue CMP01 = CMP0->getOperand(1);
17426 EVT VT = CMP00.getValueType();
17428 if (VT == MVT::f32 || VT == MVT::f64) {
17429 bool ExpectingFlags = false;
17430 // Check for any users that want flags:
17431 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
17432 !ExpectingFlags && UI != UE; ++UI)
17433 switch (UI->getOpcode()) {
17438 ExpectingFlags = true;
17440 case ISD::CopyToReg:
17441 case ISD::SIGN_EXTEND:
17442 case ISD::ZERO_EXTEND:
17443 case ISD::ANY_EXTEND:
17447 if (!ExpectingFlags) {
17448 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
17449 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
17451 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
17452 X86::CondCode tmp = cc0;
17457 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
17458 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
17459 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
17460 X86ISD::NodeType NTOperator = is64BitFP ?
17461 X86ISD::FSETCCsd : X86ISD::FSETCCss;
17462 // FIXME: need symbolic constants for these magic numbers.
17463 // See X86ATTInstPrinter.cpp:printSSECC().
17464 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
17465 SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, MVT::f32, CMP00, CMP01,
17466 DAG.getConstant(x86cc, MVT::i8));
17467 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32,
17469 SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI,
17470 DAG.getConstant(1, MVT::i32));
17471 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
17472 return OneBitOfTruth;
17480 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
17481 /// so it can be folded inside ANDNP.
17482 static bool CanFoldXORWithAllOnes(const SDNode *N) {
17483 EVT VT = N->getValueType(0);
17485 // Match direct AllOnes for 128 and 256-bit vectors
17486 if (ISD::isBuildVectorAllOnes(N))
17489 // Look through a bit convert.
17490 if (N->getOpcode() == ISD::BITCAST)
17491 N = N->getOperand(0).getNode();
17493 // Sometimes the operand may come from a insert_subvector building a 256-bit
17495 if (VT.is256BitVector() &&
17496 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
17497 SDValue V1 = N->getOperand(0);
17498 SDValue V2 = N->getOperand(1);
17500 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
17501 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
17502 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
17503 ISD::isBuildVectorAllOnes(V2.getNode()))
17510 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
17511 // register. In most cases we actually compare or select YMM-sized registers
17512 // and mixing the two types creates horrible code. This method optimizes
17513 // some of the transition sequences.
17514 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
17515 TargetLowering::DAGCombinerInfo &DCI,
17516 const X86Subtarget *Subtarget) {
17517 EVT VT = N->getValueType(0);
17518 if (!VT.is256BitVector())
17521 assert((N->getOpcode() == ISD::ANY_EXTEND ||
17522 N->getOpcode() == ISD::ZERO_EXTEND ||
17523 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
17525 SDValue Narrow = N->getOperand(0);
17526 EVT NarrowVT = Narrow->getValueType(0);
17527 if (!NarrowVT.is128BitVector())
17530 if (Narrow->getOpcode() != ISD::XOR &&
17531 Narrow->getOpcode() != ISD::AND &&
17532 Narrow->getOpcode() != ISD::OR)
17535 SDValue N0 = Narrow->getOperand(0);
17536 SDValue N1 = Narrow->getOperand(1);
17539 // The Left side has to be a trunc.
17540 if (N0.getOpcode() != ISD::TRUNCATE)
17543 // The type of the truncated inputs.
17544 EVT WideVT = N0->getOperand(0)->getValueType(0);
17548 // The right side has to be a 'trunc' or a constant vector.
17549 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
17550 bool RHSConst = (isSplatVector(N1.getNode()) &&
17551 isa<ConstantSDNode>(N1->getOperand(0)));
17552 if (!RHSTrunc && !RHSConst)
17555 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17557 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
17560 // Set N0 and N1 to hold the inputs to the new wide operation.
17561 N0 = N0->getOperand(0);
17563 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
17564 N1->getOperand(0));
17565 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
17566 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, &C[0], C.size());
17567 } else if (RHSTrunc) {
17568 N1 = N1->getOperand(0);
17571 // Generate the wide operation.
17572 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
17573 unsigned Opcode = N->getOpcode();
17575 case ISD::ANY_EXTEND:
17577 case ISD::ZERO_EXTEND: {
17578 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
17579 APInt Mask = APInt::getAllOnesValue(InBits);
17580 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
17581 return DAG.getNode(ISD::AND, DL, VT,
17582 Op, DAG.getConstant(Mask, VT));
17584 case ISD::SIGN_EXTEND:
17585 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
17586 Op, DAG.getValueType(NarrowVT));
17588 llvm_unreachable("Unexpected opcode");
17592 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
17593 TargetLowering::DAGCombinerInfo &DCI,
17594 const X86Subtarget *Subtarget) {
17595 EVT VT = N->getValueType(0);
17596 if (DCI.isBeforeLegalizeOps())
17599 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
17603 // Create BLSI, BLSR, and BZHI instructions
17604 // BLSI is X & (-X)
17605 // BLSR is X & (X-1)
17606 // BZHI is X & ((1 << Y) - 1)
17607 // BEXTR is ((X >> imm) & (2**size-1))
17608 if (VT == MVT::i32 || VT == MVT::i64) {
17609 SDValue N0 = N->getOperand(0);
17610 SDValue N1 = N->getOperand(1);
17613 if (Subtarget->hasBMI()) {
17614 // Check LHS for neg
17615 if (N0.getOpcode() == ISD::SUB && N0.getOperand(1) == N1 &&
17616 isZero(N0.getOperand(0)))
17617 return DAG.getNode(X86ISD::BLSI, DL, VT, N1);
17619 // Check RHS for neg
17620 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1) == N0 &&
17621 isZero(N1.getOperand(0)))
17622 return DAG.getNode(X86ISD::BLSI, DL, VT, N0);
17624 // Check LHS for X-1
17625 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
17626 isAllOnes(N0.getOperand(1)))
17627 return DAG.getNode(X86ISD::BLSR, DL, VT, N1);
17629 // Check RHS for X-1
17630 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
17631 isAllOnes(N1.getOperand(1)))
17632 return DAG.getNode(X86ISD::BLSR, DL, VT, N0);
17635 if (Subtarget->hasBMI2()) {
17636 // Check for (and (add (shl 1, Y), -1), X)
17637 if (N0.getOpcode() == ISD::ADD && isAllOnes(N0.getOperand(1))) {
17638 SDValue N00 = N0.getOperand(0);
17639 if (N00.getOpcode() == ISD::SHL) {
17640 SDValue N001 = N00.getOperand(1);
17641 assert(N001.getValueType() == MVT::i8 && "unexpected type");
17642 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N00.getOperand(0));
17643 if (C && C->getZExtValue() == 1)
17644 return DAG.getNode(X86ISD::BZHI, DL, VT, N1, N001);
17648 // Check for (and X, (add (shl 1, Y), -1))
17649 if (N1.getOpcode() == ISD::ADD && isAllOnes(N1.getOperand(1))) {
17650 SDValue N10 = N1.getOperand(0);
17651 if (N10.getOpcode() == ISD::SHL) {
17652 SDValue N101 = N10.getOperand(1);
17653 assert(N101.getValueType() == MVT::i8 && "unexpected type");
17654 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N10.getOperand(0));
17655 if (C && C->getZExtValue() == 1)
17656 return DAG.getNode(X86ISD::BZHI, DL, VT, N0, N101);
17661 // Check for BEXTR.
17662 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
17663 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
17664 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
17665 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
17666 if (MaskNode && ShiftNode) {
17667 uint64_t Mask = MaskNode->getZExtValue();
17668 uint64_t Shift = ShiftNode->getZExtValue();
17669 if (isMask_64(Mask)) {
17670 uint64_t MaskSize = CountPopulation_64(Mask);
17671 if (Shift + MaskSize <= VT.getSizeInBits())
17672 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
17673 DAG.getConstant(Shift | (MaskSize << 8), VT));
17681 // Want to form ANDNP nodes:
17682 // 1) In the hopes of then easily combining them with OR and AND nodes
17683 // to form PBLEND/PSIGN.
17684 // 2) To match ANDN packed intrinsics
17685 if (VT != MVT::v2i64 && VT != MVT::v4i64)
17688 SDValue N0 = N->getOperand(0);
17689 SDValue N1 = N->getOperand(1);
17692 // Check LHS for vnot
17693 if (N0.getOpcode() == ISD::XOR &&
17694 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
17695 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
17696 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
17698 // Check RHS for vnot
17699 if (N1.getOpcode() == ISD::XOR &&
17700 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
17701 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
17702 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
17707 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
17708 TargetLowering::DAGCombinerInfo &DCI,
17709 const X86Subtarget *Subtarget) {
17710 EVT VT = N->getValueType(0);
17711 if (DCI.isBeforeLegalizeOps())
17714 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
17718 SDValue N0 = N->getOperand(0);
17719 SDValue N1 = N->getOperand(1);
17721 // look for psign/blend
17722 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
17723 if (!Subtarget->hasSSSE3() ||
17724 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
17727 // Canonicalize pandn to RHS
17728 if (N0.getOpcode() == X86ISD::ANDNP)
17730 // or (and (m, y), (pandn m, x))
17731 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
17732 SDValue Mask = N1.getOperand(0);
17733 SDValue X = N1.getOperand(1);
17735 if (N0.getOperand(0) == Mask)
17736 Y = N0.getOperand(1);
17737 if (N0.getOperand(1) == Mask)
17738 Y = N0.getOperand(0);
17740 // Check to see if the mask appeared in both the AND and ANDNP and
17744 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
17745 // Look through mask bitcast.
17746 if (Mask.getOpcode() == ISD::BITCAST)
17747 Mask = Mask.getOperand(0);
17748 if (X.getOpcode() == ISD::BITCAST)
17749 X = X.getOperand(0);
17750 if (Y.getOpcode() == ISD::BITCAST)
17751 Y = Y.getOperand(0);
17753 EVT MaskVT = Mask.getValueType();
17755 // Validate that the Mask operand is a vector sra node.
17756 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
17757 // there is no psrai.b
17758 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
17759 unsigned SraAmt = ~0;
17760 if (Mask.getOpcode() == ISD::SRA) {
17761 SDValue Amt = Mask.getOperand(1);
17762 if (isSplatVector(Amt.getNode())) {
17763 SDValue SclrAmt = Amt->getOperand(0);
17764 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt))
17765 SraAmt = C->getZExtValue();
17767 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
17768 SDValue SraC = Mask.getOperand(1);
17769 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
17771 if ((SraAmt + 1) != EltBits)
17776 // Now we know we at least have a plendvb with the mask val. See if
17777 // we can form a psignb/w/d.
17778 // psign = x.type == y.type == mask.type && y = sub(0, x);
17779 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
17780 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
17781 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
17782 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
17783 "Unsupported VT for PSIGN");
17784 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
17785 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
17787 // PBLENDVB only available on SSE 4.1
17788 if (!Subtarget->hasSSE41())
17791 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
17793 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
17794 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
17795 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
17796 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
17797 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
17801 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
17804 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
17805 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
17807 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
17809 if (!N0.hasOneUse() || !N1.hasOneUse())
17812 SDValue ShAmt0 = N0.getOperand(1);
17813 if (ShAmt0.getValueType() != MVT::i8)
17815 SDValue ShAmt1 = N1.getOperand(1);
17816 if (ShAmt1.getValueType() != MVT::i8)
17818 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
17819 ShAmt0 = ShAmt0.getOperand(0);
17820 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
17821 ShAmt1 = ShAmt1.getOperand(0);
17824 unsigned Opc = X86ISD::SHLD;
17825 SDValue Op0 = N0.getOperand(0);
17826 SDValue Op1 = N1.getOperand(0);
17827 if (ShAmt0.getOpcode() == ISD::SUB) {
17828 Opc = X86ISD::SHRD;
17829 std::swap(Op0, Op1);
17830 std::swap(ShAmt0, ShAmt1);
17833 unsigned Bits = VT.getSizeInBits();
17834 if (ShAmt1.getOpcode() == ISD::SUB) {
17835 SDValue Sum = ShAmt1.getOperand(0);
17836 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
17837 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
17838 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
17839 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
17840 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
17841 return DAG.getNode(Opc, DL, VT,
17843 DAG.getNode(ISD::TRUNCATE, DL,
17846 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
17847 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
17849 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
17850 return DAG.getNode(Opc, DL, VT,
17851 N0.getOperand(0), N1.getOperand(0),
17852 DAG.getNode(ISD::TRUNCATE, DL,
17859 // Generate NEG and CMOV for integer abs.
17860 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
17861 EVT VT = N->getValueType(0);
17863 // Since X86 does not have CMOV for 8-bit integer, we don't convert
17864 // 8-bit integer abs to NEG and CMOV.
17865 if (VT.isInteger() && VT.getSizeInBits() == 8)
17868 SDValue N0 = N->getOperand(0);
17869 SDValue N1 = N->getOperand(1);
17872 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
17873 // and change it to SUB and CMOV.
17874 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
17875 N0.getOpcode() == ISD::ADD &&
17876 N0.getOperand(1) == N1 &&
17877 N1.getOpcode() == ISD::SRA &&
17878 N1.getOperand(0) == N0.getOperand(0))
17879 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
17880 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
17881 // Generate SUB & CMOV.
17882 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
17883 DAG.getConstant(0, VT), N0.getOperand(0));
17885 SDValue Ops[] = { N0.getOperand(0), Neg,
17886 DAG.getConstant(X86::COND_GE, MVT::i8),
17887 SDValue(Neg.getNode(), 1) };
17888 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue),
17889 Ops, array_lengthof(Ops));
17894 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
17895 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
17896 TargetLowering::DAGCombinerInfo &DCI,
17897 const X86Subtarget *Subtarget) {
17898 EVT VT = N->getValueType(0);
17899 if (DCI.isBeforeLegalizeOps())
17902 if (Subtarget->hasCMov()) {
17903 SDValue RV = performIntegerAbsCombine(N, DAG);
17908 // Try forming BMI if it is available.
17909 if (!Subtarget->hasBMI())
17912 if (VT != MVT::i32 && VT != MVT::i64)
17915 assert(Subtarget->hasBMI() && "Creating BLSMSK requires BMI instructions");
17917 // Create BLSMSK instructions by finding X ^ (X-1)
17918 SDValue N0 = N->getOperand(0);
17919 SDValue N1 = N->getOperand(1);
17922 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
17923 isAllOnes(N0.getOperand(1)))
17924 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N1);
17926 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
17927 isAllOnes(N1.getOperand(1)))
17928 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N0);
17933 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
17934 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
17935 TargetLowering::DAGCombinerInfo &DCI,
17936 const X86Subtarget *Subtarget) {
17937 LoadSDNode *Ld = cast<LoadSDNode>(N);
17938 EVT RegVT = Ld->getValueType(0);
17939 EVT MemVT = Ld->getMemoryVT();
17941 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17942 unsigned RegSz = RegVT.getSizeInBits();
17944 // On Sandybridge unaligned 256bit loads are inefficient.
17945 ISD::LoadExtType Ext = Ld->getExtensionType();
17946 unsigned Alignment = Ld->getAlignment();
17947 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
17948 if (RegVT.is256BitVector() && !Subtarget->hasInt256() &&
17949 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
17950 unsigned NumElems = RegVT.getVectorNumElements();
17954 SDValue Ptr = Ld->getBasePtr();
17955 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
17957 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
17959 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
17960 Ld->getPointerInfo(), Ld->isVolatile(),
17961 Ld->isNonTemporal(), Ld->isInvariant(),
17963 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
17964 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
17965 Ld->getPointerInfo(), Ld->isVolatile(),
17966 Ld->isNonTemporal(), Ld->isInvariant(),
17967 std::min(16U, Alignment));
17968 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
17970 Load2.getValue(1));
17972 SDValue NewVec = DAG.getUNDEF(RegVT);
17973 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
17974 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
17975 return DCI.CombineTo(N, NewVec, TF, true);
17978 // If this is a vector EXT Load then attempt to optimize it using a
17979 // shuffle. If SSSE3 is not available we may emit an illegal shuffle but the
17980 // expansion is still better than scalar code.
17981 // We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise we'll
17982 // emit a shuffle and a arithmetic shift.
17983 // TODO: It is possible to support ZExt by zeroing the undef values
17984 // during the shuffle phase or after the shuffle.
17985 if (RegVT.isVector() && RegVT.isInteger() && Subtarget->hasSSE2() &&
17986 (Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)) {
17987 assert(MemVT != RegVT && "Cannot extend to the same type");
17988 assert(MemVT.isVector() && "Must load a vector from memory");
17990 unsigned NumElems = RegVT.getVectorNumElements();
17991 unsigned MemSz = MemVT.getSizeInBits();
17992 assert(RegSz > MemSz && "Register size must be greater than the mem size");
17994 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256())
17997 // All sizes must be a power of two.
17998 if (!isPowerOf2_32(RegSz * MemSz * NumElems))
18001 // Attempt to load the original value using scalar loads.
18002 // Find the largest scalar type that divides the total loaded size.
18003 MVT SclrLoadTy = MVT::i8;
18004 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
18005 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
18006 MVT Tp = (MVT::SimpleValueType)tp;
18007 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
18012 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
18013 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
18015 SclrLoadTy = MVT::f64;
18017 // Calculate the number of scalar loads that we need to perform
18018 // in order to load our vector from memory.
18019 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
18020 if (Ext == ISD::SEXTLOAD && NumLoads > 1)
18023 unsigned loadRegZize = RegSz;
18024 if (Ext == ISD::SEXTLOAD && RegSz == 256)
18027 // Represent our vector as a sequence of elements which are the
18028 // largest scalar that we can load.
18029 EVT LoadUnitVecVT = EVT::getVectorVT(*DAG.getContext(), SclrLoadTy,
18030 loadRegZize/SclrLoadTy.getSizeInBits());
18032 // Represent the data using the same element type that is stored in
18033 // memory. In practice, we ''widen'' MemVT.
18035 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
18036 loadRegZize/MemVT.getScalarType().getSizeInBits());
18038 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
18039 "Invalid vector type");
18041 // We can't shuffle using an illegal type.
18042 if (!TLI.isTypeLegal(WideVecVT))
18045 SmallVector<SDValue, 8> Chains;
18046 SDValue Ptr = Ld->getBasePtr();
18047 SDValue Increment = DAG.getConstant(SclrLoadTy.getSizeInBits()/8,
18048 TLI.getPointerTy());
18049 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
18051 for (unsigned i = 0; i < NumLoads; ++i) {
18052 // Perform a single load.
18053 SDValue ScalarLoad = DAG.getLoad(SclrLoadTy, dl, Ld->getChain(),
18054 Ptr, Ld->getPointerInfo(),
18055 Ld->isVolatile(), Ld->isNonTemporal(),
18056 Ld->isInvariant(), Ld->getAlignment());
18057 Chains.push_back(ScalarLoad.getValue(1));
18058 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
18059 // another round of DAGCombining.
18061 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
18063 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
18064 ScalarLoad, DAG.getIntPtrConstant(i));
18066 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
18069 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
18072 // Bitcast the loaded value to a vector of the original element type, in
18073 // the size of the target vector type.
18074 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
18075 unsigned SizeRatio = RegSz/MemSz;
18077 if (Ext == ISD::SEXTLOAD) {
18078 // If we have SSE4.1 we can directly emit a VSEXT node.
18079 if (Subtarget->hasSSE41()) {
18080 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
18081 return DCI.CombineTo(N, Sext, TF, true);
18084 // Otherwise we'll shuffle the small elements in the high bits of the
18085 // larger type and perform an arithmetic shift. If the shift is not legal
18086 // it's better to scalarize.
18087 if (!TLI.isOperationLegalOrCustom(ISD::SRA, RegVT))
18090 // Redistribute the loaded elements into the different locations.
18091 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
18092 for (unsigned i = 0; i != NumElems; ++i)
18093 ShuffleVec[i*SizeRatio + SizeRatio-1] = i;
18095 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
18096 DAG.getUNDEF(WideVecVT),
18099 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
18101 // Build the arithmetic shift.
18102 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
18103 MemVT.getVectorElementType().getSizeInBits();
18104 Shuff = DAG.getNode(ISD::SRA, dl, RegVT, Shuff,
18105 DAG.getConstant(Amt, RegVT));
18107 return DCI.CombineTo(N, Shuff, TF, true);
18110 // Redistribute the loaded elements into the different locations.
18111 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
18112 for (unsigned i = 0; i != NumElems; ++i)
18113 ShuffleVec[i*SizeRatio] = i;
18115 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
18116 DAG.getUNDEF(WideVecVT),
18119 // Bitcast to the requested type.
18120 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
18121 // Replace the original load with the new sequence
18122 // and return the new chain.
18123 return DCI.CombineTo(N, Shuff, TF, true);
18129 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
18130 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
18131 const X86Subtarget *Subtarget) {
18132 StoreSDNode *St = cast<StoreSDNode>(N);
18133 EVT VT = St->getValue().getValueType();
18134 EVT StVT = St->getMemoryVT();
18136 SDValue StoredVal = St->getOperand(1);
18137 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18139 // If we are saving a concatenation of two XMM registers, perform two stores.
18140 // On Sandy Bridge, 256-bit memory operations are executed by two
18141 // 128-bit ports. However, on Haswell it is better to issue a single 256-bit
18142 // memory operation.
18143 unsigned Alignment = St->getAlignment();
18144 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
18145 if (VT.is256BitVector() && !Subtarget->hasInt256() &&
18146 StVT == VT && !IsAligned) {
18147 unsigned NumElems = VT.getVectorNumElements();
18151 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
18152 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
18154 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
18155 SDValue Ptr0 = St->getBasePtr();
18156 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
18158 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
18159 St->getPointerInfo(), St->isVolatile(),
18160 St->isNonTemporal(), Alignment);
18161 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
18162 St->getPointerInfo(), St->isVolatile(),
18163 St->isNonTemporal(),
18164 std::min(16U, Alignment));
18165 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
18168 // Optimize trunc store (of multiple scalars) to shuffle and store.
18169 // First, pack all of the elements in one place. Next, store to memory
18170 // in fewer chunks.
18171 if (St->isTruncatingStore() && VT.isVector()) {
18172 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18173 unsigned NumElems = VT.getVectorNumElements();
18174 assert(StVT != VT && "Cannot truncate to the same type");
18175 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
18176 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
18178 // From, To sizes and ElemCount must be pow of two
18179 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
18180 // We are going to use the original vector elt for storing.
18181 // Accumulated smaller vector elements must be a multiple of the store size.
18182 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
18184 unsigned SizeRatio = FromSz / ToSz;
18186 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
18188 // Create a type on which we perform the shuffle
18189 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
18190 StVT.getScalarType(), NumElems*SizeRatio);
18192 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
18194 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
18195 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
18196 for (unsigned i = 0; i != NumElems; ++i)
18197 ShuffleVec[i] = i * SizeRatio;
18199 // Can't shuffle using an illegal type.
18200 if (!TLI.isTypeLegal(WideVecVT))
18203 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
18204 DAG.getUNDEF(WideVecVT),
18206 // At this point all of the data is stored at the bottom of the
18207 // register. We now need to save it to mem.
18209 // Find the largest store unit
18210 MVT StoreType = MVT::i8;
18211 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
18212 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
18213 MVT Tp = (MVT::SimpleValueType)tp;
18214 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
18218 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
18219 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
18220 (64 <= NumElems * ToSz))
18221 StoreType = MVT::f64;
18223 // Bitcast the original vector into a vector of store-size units
18224 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
18225 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
18226 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
18227 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
18228 SmallVector<SDValue, 8> Chains;
18229 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
18230 TLI.getPointerTy());
18231 SDValue Ptr = St->getBasePtr();
18233 // Perform one or more big stores into memory.
18234 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
18235 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
18236 StoreType, ShuffWide,
18237 DAG.getIntPtrConstant(i));
18238 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
18239 St->getPointerInfo(), St->isVolatile(),
18240 St->isNonTemporal(), St->getAlignment());
18241 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
18242 Chains.push_back(Ch);
18245 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
18249 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
18250 // the FP state in cases where an emms may be missing.
18251 // A preferable solution to the general problem is to figure out the right
18252 // places to insert EMMS. This qualifies as a quick hack.
18254 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
18255 if (VT.getSizeInBits() != 64)
18258 const Function *F = DAG.getMachineFunction().getFunction();
18259 bool NoImplicitFloatOps = F->getAttributes().
18260 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
18261 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
18262 && Subtarget->hasSSE2();
18263 if ((VT.isVector() ||
18264 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
18265 isa<LoadSDNode>(St->getValue()) &&
18266 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
18267 St->getChain().hasOneUse() && !St->isVolatile()) {
18268 SDNode* LdVal = St->getValue().getNode();
18269 LoadSDNode *Ld = 0;
18270 int TokenFactorIndex = -1;
18271 SmallVector<SDValue, 8> Ops;
18272 SDNode* ChainVal = St->getChain().getNode();
18273 // Must be a store of a load. We currently handle two cases: the load
18274 // is a direct child, and it's under an intervening TokenFactor. It is
18275 // possible to dig deeper under nested TokenFactors.
18276 if (ChainVal == LdVal)
18277 Ld = cast<LoadSDNode>(St->getChain());
18278 else if (St->getValue().hasOneUse() &&
18279 ChainVal->getOpcode() == ISD::TokenFactor) {
18280 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
18281 if (ChainVal->getOperand(i).getNode() == LdVal) {
18282 TokenFactorIndex = i;
18283 Ld = cast<LoadSDNode>(St->getValue());
18285 Ops.push_back(ChainVal->getOperand(i));
18289 if (!Ld || !ISD::isNormalLoad(Ld))
18292 // If this is not the MMX case, i.e. we are just turning i64 load/store
18293 // into f64 load/store, avoid the transformation if there are multiple
18294 // uses of the loaded value.
18295 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
18300 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
18301 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
18303 if (Subtarget->is64Bit() || F64IsLegal) {
18304 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
18305 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
18306 Ld->getPointerInfo(), Ld->isVolatile(),
18307 Ld->isNonTemporal(), Ld->isInvariant(),
18308 Ld->getAlignment());
18309 SDValue NewChain = NewLd.getValue(1);
18310 if (TokenFactorIndex != -1) {
18311 Ops.push_back(NewChain);
18312 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
18315 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
18316 St->getPointerInfo(),
18317 St->isVolatile(), St->isNonTemporal(),
18318 St->getAlignment());
18321 // Otherwise, lower to two pairs of 32-bit loads / stores.
18322 SDValue LoAddr = Ld->getBasePtr();
18323 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
18324 DAG.getConstant(4, MVT::i32));
18326 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
18327 Ld->getPointerInfo(),
18328 Ld->isVolatile(), Ld->isNonTemporal(),
18329 Ld->isInvariant(), Ld->getAlignment());
18330 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
18331 Ld->getPointerInfo().getWithOffset(4),
18332 Ld->isVolatile(), Ld->isNonTemporal(),
18334 MinAlign(Ld->getAlignment(), 4));
18336 SDValue NewChain = LoLd.getValue(1);
18337 if (TokenFactorIndex != -1) {
18338 Ops.push_back(LoLd);
18339 Ops.push_back(HiLd);
18340 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
18344 LoAddr = St->getBasePtr();
18345 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
18346 DAG.getConstant(4, MVT::i32));
18348 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
18349 St->getPointerInfo(),
18350 St->isVolatile(), St->isNonTemporal(),
18351 St->getAlignment());
18352 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
18353 St->getPointerInfo().getWithOffset(4),
18355 St->isNonTemporal(),
18356 MinAlign(St->getAlignment(), 4));
18357 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
18362 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
18363 /// and return the operands for the horizontal operation in LHS and RHS. A
18364 /// horizontal operation performs the binary operation on successive elements
18365 /// of its first operand, then on successive elements of its second operand,
18366 /// returning the resulting values in a vector. For example, if
18367 /// A = < float a0, float a1, float a2, float a3 >
18369 /// B = < float b0, float b1, float b2, float b3 >
18370 /// then the result of doing a horizontal operation on A and B is
18371 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
18372 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
18373 /// A horizontal-op B, for some already available A and B, and if so then LHS is
18374 /// set to A, RHS to B, and the routine returns 'true'.
18375 /// Note that the binary operation should have the property that if one of the
18376 /// operands is UNDEF then the result is UNDEF.
18377 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
18378 // Look for the following pattern: if
18379 // A = < float a0, float a1, float a2, float a3 >
18380 // B = < float b0, float b1, float b2, float b3 >
18382 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
18383 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
18384 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
18385 // which is A horizontal-op B.
18387 // At least one of the operands should be a vector shuffle.
18388 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
18389 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
18392 MVT VT = LHS.getSimpleValueType();
18394 assert((VT.is128BitVector() || VT.is256BitVector()) &&
18395 "Unsupported vector type for horizontal add/sub");
18397 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
18398 // operate independently on 128-bit lanes.
18399 unsigned NumElts = VT.getVectorNumElements();
18400 unsigned NumLanes = VT.getSizeInBits()/128;
18401 unsigned NumLaneElts = NumElts / NumLanes;
18402 assert((NumLaneElts % 2 == 0) &&
18403 "Vector type should have an even number of elements in each lane");
18404 unsigned HalfLaneElts = NumLaneElts/2;
18406 // View LHS in the form
18407 // LHS = VECTOR_SHUFFLE A, B, LMask
18408 // If LHS is not a shuffle then pretend it is the shuffle
18409 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
18410 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
18413 SmallVector<int, 16> LMask(NumElts);
18414 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
18415 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
18416 A = LHS.getOperand(0);
18417 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
18418 B = LHS.getOperand(1);
18419 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
18420 std::copy(Mask.begin(), Mask.end(), LMask.begin());
18422 if (LHS.getOpcode() != ISD::UNDEF)
18424 for (unsigned i = 0; i != NumElts; ++i)
18428 // Likewise, view RHS in the form
18429 // RHS = VECTOR_SHUFFLE C, D, RMask
18431 SmallVector<int, 16> RMask(NumElts);
18432 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
18433 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
18434 C = RHS.getOperand(0);
18435 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
18436 D = RHS.getOperand(1);
18437 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
18438 std::copy(Mask.begin(), Mask.end(), RMask.begin());
18440 if (RHS.getOpcode() != ISD::UNDEF)
18442 for (unsigned i = 0; i != NumElts; ++i)
18446 // Check that the shuffles are both shuffling the same vectors.
18447 if (!(A == C && B == D) && !(A == D && B == C))
18450 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
18451 if (!A.getNode() && !B.getNode())
18454 // If A and B occur in reverse order in RHS, then "swap" them (which means
18455 // rewriting the mask).
18457 CommuteVectorShuffleMask(RMask, NumElts);
18459 // At this point LHS and RHS are equivalent to
18460 // LHS = VECTOR_SHUFFLE A, B, LMask
18461 // RHS = VECTOR_SHUFFLE A, B, RMask
18462 // Check that the masks correspond to performing a horizontal operation.
18463 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
18464 for (unsigned i = 0; i != NumLaneElts; ++i) {
18465 int LIdx = LMask[i+l], RIdx = RMask[i+l];
18467 // Ignore any UNDEF components.
18468 if (LIdx < 0 || RIdx < 0 ||
18469 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
18470 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
18473 // Check that successive elements are being operated on. If not, this is
18474 // not a horizontal operation.
18475 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
18476 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
18477 if (!(LIdx == Index && RIdx == Index + 1) &&
18478 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
18483 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
18484 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
18488 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
18489 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
18490 const X86Subtarget *Subtarget) {
18491 EVT VT = N->getValueType(0);
18492 SDValue LHS = N->getOperand(0);
18493 SDValue RHS = N->getOperand(1);
18495 // Try to synthesize horizontal adds from adds of shuffles.
18496 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
18497 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
18498 isHorizontalBinOp(LHS, RHS, true))
18499 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
18503 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
18504 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
18505 const X86Subtarget *Subtarget) {
18506 EVT VT = N->getValueType(0);
18507 SDValue LHS = N->getOperand(0);
18508 SDValue RHS = N->getOperand(1);
18510 // Try to synthesize horizontal subs from subs of shuffles.
18511 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
18512 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
18513 isHorizontalBinOp(LHS, RHS, false))
18514 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
18518 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
18519 /// X86ISD::FXOR nodes.
18520 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
18521 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
18522 // F[X]OR(0.0, x) -> x
18523 // F[X]OR(x, 0.0) -> x
18524 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
18525 if (C->getValueAPF().isPosZero())
18526 return N->getOperand(1);
18527 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
18528 if (C->getValueAPF().isPosZero())
18529 return N->getOperand(0);
18533 /// PerformFMinFMaxCombine - Do target-specific dag combines on X86ISD::FMIN and
18534 /// X86ISD::FMAX nodes.
18535 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
18536 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
18538 // Only perform optimizations if UnsafeMath is used.
18539 if (!DAG.getTarget().Options.UnsafeFPMath)
18542 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
18543 // into FMINC and FMAXC, which are Commutative operations.
18544 unsigned NewOp = 0;
18545 switch (N->getOpcode()) {
18546 default: llvm_unreachable("unknown opcode");
18547 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
18548 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
18551 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
18552 N->getOperand(0), N->getOperand(1));
18555 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
18556 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
18557 // FAND(0.0, x) -> 0.0
18558 // FAND(x, 0.0) -> 0.0
18559 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
18560 if (C->getValueAPF().isPosZero())
18561 return N->getOperand(0);
18562 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
18563 if (C->getValueAPF().isPosZero())
18564 return N->getOperand(1);
18568 /// PerformFANDNCombine - Do target-specific dag combines on X86ISD::FANDN nodes
18569 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
18570 // FANDN(x, 0.0) -> 0.0
18571 // FANDN(0.0, x) -> x
18572 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
18573 if (C->getValueAPF().isPosZero())
18574 return N->getOperand(1);
18575 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
18576 if (C->getValueAPF().isPosZero())
18577 return N->getOperand(1);
18581 static SDValue PerformBTCombine(SDNode *N,
18583 TargetLowering::DAGCombinerInfo &DCI) {
18584 // BT ignores high bits in the bit index operand.
18585 SDValue Op1 = N->getOperand(1);
18586 if (Op1.hasOneUse()) {
18587 unsigned BitWidth = Op1.getValueSizeInBits();
18588 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
18589 APInt KnownZero, KnownOne;
18590 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
18591 !DCI.isBeforeLegalizeOps());
18592 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18593 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
18594 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
18595 DCI.CommitTargetLoweringOpt(TLO);
18600 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
18601 SDValue Op = N->getOperand(0);
18602 if (Op.getOpcode() == ISD::BITCAST)
18603 Op = Op.getOperand(0);
18604 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
18605 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
18606 VT.getVectorElementType().getSizeInBits() ==
18607 OpVT.getVectorElementType().getSizeInBits()) {
18608 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
18613 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
18614 const X86Subtarget *Subtarget) {
18615 EVT VT = N->getValueType(0);
18616 if (!VT.isVector())
18619 SDValue N0 = N->getOperand(0);
18620 SDValue N1 = N->getOperand(1);
18621 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
18624 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
18625 // both SSE and AVX2 since there is no sign-extended shift right
18626 // operation on a vector with 64-bit elements.
18627 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
18628 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
18629 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
18630 N0.getOpcode() == ISD::SIGN_EXTEND)) {
18631 SDValue N00 = N0.getOperand(0);
18633 // EXTLOAD has a better solution on AVX2,
18634 // it may be replaced with X86ISD::VSEXT node.
18635 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
18636 if (!ISD::isNormalLoad(N00.getNode()))
18639 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
18640 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
18642 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
18648 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
18649 TargetLowering::DAGCombinerInfo &DCI,
18650 const X86Subtarget *Subtarget) {
18651 if (!DCI.isBeforeLegalizeOps())
18654 if (!Subtarget->hasFp256())
18657 EVT VT = N->getValueType(0);
18658 if (VT.isVector() && VT.getSizeInBits() == 256) {
18659 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
18667 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
18668 const X86Subtarget* Subtarget) {
18670 EVT VT = N->getValueType(0);
18672 // Let legalize expand this if it isn't a legal type yet.
18673 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
18676 EVT ScalarVT = VT.getScalarType();
18677 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
18678 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
18681 SDValue A = N->getOperand(0);
18682 SDValue B = N->getOperand(1);
18683 SDValue C = N->getOperand(2);
18685 bool NegA = (A.getOpcode() == ISD::FNEG);
18686 bool NegB = (B.getOpcode() == ISD::FNEG);
18687 bool NegC = (C.getOpcode() == ISD::FNEG);
18689 // Negative multiplication when NegA xor NegB
18690 bool NegMul = (NegA != NegB);
18692 A = A.getOperand(0);
18694 B = B.getOperand(0);
18696 C = C.getOperand(0);
18700 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
18702 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
18704 return DAG.getNode(Opcode, dl, VT, A, B, C);
18707 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
18708 TargetLowering::DAGCombinerInfo &DCI,
18709 const X86Subtarget *Subtarget) {
18710 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
18711 // (and (i32 x86isd::setcc_carry), 1)
18712 // This eliminates the zext. This transformation is necessary because
18713 // ISD::SETCC is always legalized to i8.
18715 SDValue N0 = N->getOperand(0);
18716 EVT VT = N->getValueType(0);
18718 if (N0.getOpcode() == ISD::AND &&
18720 N0.getOperand(0).hasOneUse()) {
18721 SDValue N00 = N0.getOperand(0);
18722 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
18723 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
18724 if (!C || C->getZExtValue() != 1)
18726 return DAG.getNode(ISD::AND, dl, VT,
18727 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
18728 N00.getOperand(0), N00.getOperand(1)),
18729 DAG.getConstant(1, VT));
18733 if (VT.is256BitVector()) {
18734 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
18742 // Optimize x == -y --> x+y == 0
18743 // x != -y --> x+y != 0
18744 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG) {
18745 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
18746 SDValue LHS = N->getOperand(0);
18747 SDValue RHS = N->getOperand(1);
18749 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
18750 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
18751 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
18752 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
18753 LHS.getValueType(), RHS, LHS.getOperand(1));
18754 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
18755 addV, DAG.getConstant(0, addV.getValueType()), CC);
18757 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
18758 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
18759 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
18760 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
18761 RHS.getValueType(), LHS, RHS.getOperand(1));
18762 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
18763 addV, DAG.getConstant(0, addV.getValueType()), CC);
18768 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
18769 // as "sbb reg,reg", since it can be extended without zext and produces
18770 // an all-ones bit which is more useful than 0/1 in some cases.
18771 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG) {
18772 return DAG.getNode(ISD::AND, DL, MVT::i8,
18773 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
18774 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
18775 DAG.getConstant(1, MVT::i8));
18778 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
18779 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
18780 TargetLowering::DAGCombinerInfo &DCI,
18781 const X86Subtarget *Subtarget) {
18783 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
18784 SDValue EFLAGS = N->getOperand(1);
18786 if (CC == X86::COND_A) {
18787 // Try to convert COND_A into COND_B in an attempt to facilitate
18788 // materializing "setb reg".
18790 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
18791 // cannot take an immediate as its first operand.
18793 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
18794 EFLAGS.getValueType().isInteger() &&
18795 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
18796 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
18797 EFLAGS.getNode()->getVTList(),
18798 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
18799 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
18800 return MaterializeSETB(DL, NewEFLAGS, DAG);
18804 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
18805 // a zext and produces an all-ones bit which is more useful than 0/1 in some
18807 if (CC == X86::COND_B)
18808 return MaterializeSETB(DL, EFLAGS, DAG);
18812 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
18813 if (Flags.getNode()) {
18814 SDValue Cond = DAG.getConstant(CC, MVT::i8);
18815 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
18821 // Optimize branch condition evaluation.
18823 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
18824 TargetLowering::DAGCombinerInfo &DCI,
18825 const X86Subtarget *Subtarget) {
18827 SDValue Chain = N->getOperand(0);
18828 SDValue Dest = N->getOperand(1);
18829 SDValue EFLAGS = N->getOperand(3);
18830 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
18834 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
18835 if (Flags.getNode()) {
18836 SDValue Cond = DAG.getConstant(CC, MVT::i8);
18837 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
18844 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
18845 const X86TargetLowering *XTLI) {
18846 SDValue Op0 = N->getOperand(0);
18847 EVT InVT = Op0->getValueType(0);
18849 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
18850 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
18852 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
18853 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
18854 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
18857 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
18858 // a 32-bit target where SSE doesn't support i64->FP operations.
18859 if (Op0.getOpcode() == ISD::LOAD) {
18860 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
18861 EVT VT = Ld->getValueType(0);
18862 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
18863 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
18864 !XTLI->getSubtarget()->is64Bit() &&
18866 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
18867 Ld->getChain(), Op0, DAG);
18868 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
18875 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
18876 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
18877 X86TargetLowering::DAGCombinerInfo &DCI) {
18878 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
18879 // the result is either zero or one (depending on the input carry bit).
18880 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
18881 if (X86::isZeroNode(N->getOperand(0)) &&
18882 X86::isZeroNode(N->getOperand(1)) &&
18883 // We don't have a good way to replace an EFLAGS use, so only do this when
18885 SDValue(N, 1).use_empty()) {
18887 EVT VT = N->getValueType(0);
18888 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
18889 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
18890 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
18891 DAG.getConstant(X86::COND_B,MVT::i8),
18893 DAG.getConstant(1, VT));
18894 return DCI.CombineTo(N, Res1, CarryOut);
18900 // fold (add Y, (sete X, 0)) -> adc 0, Y
18901 // (add Y, (setne X, 0)) -> sbb -1, Y
18902 // (sub (sete X, 0), Y) -> sbb 0, Y
18903 // (sub (setne X, 0), Y) -> adc -1, Y
18904 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
18907 // Look through ZExts.
18908 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
18909 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
18912 SDValue SetCC = Ext.getOperand(0);
18913 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
18916 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
18917 if (CC != X86::COND_E && CC != X86::COND_NE)
18920 SDValue Cmp = SetCC.getOperand(1);
18921 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
18922 !X86::isZeroNode(Cmp.getOperand(1)) ||
18923 !Cmp.getOperand(0).getValueType().isInteger())
18926 SDValue CmpOp0 = Cmp.getOperand(0);
18927 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
18928 DAG.getConstant(1, CmpOp0.getValueType()));
18930 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
18931 if (CC == X86::COND_NE)
18932 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
18933 DL, OtherVal.getValueType(), OtherVal,
18934 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
18935 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
18936 DL, OtherVal.getValueType(), OtherVal,
18937 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
18940 /// PerformADDCombine - Do target-specific dag combines on integer adds.
18941 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
18942 const X86Subtarget *Subtarget) {
18943 EVT VT = N->getValueType(0);
18944 SDValue Op0 = N->getOperand(0);
18945 SDValue Op1 = N->getOperand(1);
18947 // Try to synthesize horizontal adds from adds of shuffles.
18948 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
18949 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
18950 isHorizontalBinOp(Op0, Op1, true))
18951 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
18953 return OptimizeConditionalInDecrement(N, DAG);
18956 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
18957 const X86Subtarget *Subtarget) {
18958 SDValue Op0 = N->getOperand(0);
18959 SDValue Op1 = N->getOperand(1);
18961 // X86 can't encode an immediate LHS of a sub. See if we can push the
18962 // negation into a preceding instruction.
18963 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
18964 // If the RHS of the sub is a XOR with one use and a constant, invert the
18965 // immediate. Then add one to the LHS of the sub so we can turn
18966 // X-Y -> X+~Y+1, saving one register.
18967 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
18968 isa<ConstantSDNode>(Op1.getOperand(1))) {
18969 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
18970 EVT VT = Op0.getValueType();
18971 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
18973 DAG.getConstant(~XorC, VT));
18974 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
18975 DAG.getConstant(C->getAPIntValue()+1, VT));
18979 // Try to synthesize horizontal adds from adds of shuffles.
18980 EVT VT = N->getValueType(0);
18981 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
18982 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
18983 isHorizontalBinOp(Op0, Op1, true))
18984 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
18986 return OptimizeConditionalInDecrement(N, DAG);
18989 /// performVZEXTCombine - Performs build vector combines
18990 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
18991 TargetLowering::DAGCombinerInfo &DCI,
18992 const X86Subtarget *Subtarget) {
18993 // (vzext (bitcast (vzext (x)) -> (vzext x)
18994 SDValue In = N->getOperand(0);
18995 while (In.getOpcode() == ISD::BITCAST)
18996 In = In.getOperand(0);
18998 if (In.getOpcode() != X86ISD::VZEXT)
19001 return DAG.getNode(X86ISD::VZEXT, SDLoc(N), N->getValueType(0),
19005 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
19006 DAGCombinerInfo &DCI) const {
19007 SelectionDAG &DAG = DCI.DAG;
19008 switch (N->getOpcode()) {
19010 case ISD::EXTRACT_VECTOR_ELT:
19011 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
19013 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget);
19014 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
19015 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
19016 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
19017 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
19018 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
19021 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
19022 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
19023 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
19024 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
19025 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
19026 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
19027 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
19028 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
19029 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
19031 case X86ISD::FOR: return PerformFORCombine(N, DAG);
19033 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
19034 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
19035 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
19036 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
19037 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
19038 case ISD::ANY_EXTEND:
19039 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
19040 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
19041 case ISD::SIGN_EXTEND_INREG: return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
19042 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
19043 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG);
19044 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
19045 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
19046 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
19047 case X86ISD::SHUFP: // Handle all target specific shuffles
19048 case X86ISD::PALIGNR:
19049 case X86ISD::UNPCKH:
19050 case X86ISD::UNPCKL:
19051 case X86ISD::MOVHLPS:
19052 case X86ISD::MOVLHPS:
19053 case X86ISD::PSHUFD:
19054 case X86ISD::PSHUFHW:
19055 case X86ISD::PSHUFLW:
19056 case X86ISD::MOVSS:
19057 case X86ISD::MOVSD:
19058 case X86ISD::VPERMILP:
19059 case X86ISD::VPERM2X128:
19060 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
19061 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
19067 /// isTypeDesirableForOp - Return true if the target has native support for
19068 /// the specified value type and it is 'desirable' to use the type for the
19069 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
19070 /// instruction encodings are longer and some i16 instructions are slow.
19071 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
19072 if (!isTypeLegal(VT))
19074 if (VT != MVT::i16)
19081 case ISD::SIGN_EXTEND:
19082 case ISD::ZERO_EXTEND:
19083 case ISD::ANY_EXTEND:
19096 /// IsDesirableToPromoteOp - This method query the target whether it is
19097 /// beneficial for dag combiner to promote the specified node. If true, it
19098 /// should return the desired promotion type by reference.
19099 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
19100 EVT VT = Op.getValueType();
19101 if (VT != MVT::i16)
19104 bool Promote = false;
19105 bool Commute = false;
19106 switch (Op.getOpcode()) {
19109 LoadSDNode *LD = cast<LoadSDNode>(Op);
19110 // If the non-extending load has a single use and it's not live out, then it
19111 // might be folded.
19112 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
19113 Op.hasOneUse()*/) {
19114 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
19115 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
19116 // The only case where we'd want to promote LOAD (rather then it being
19117 // promoted as an operand is when it's only use is liveout.
19118 if (UI->getOpcode() != ISD::CopyToReg)
19125 case ISD::SIGN_EXTEND:
19126 case ISD::ZERO_EXTEND:
19127 case ISD::ANY_EXTEND:
19132 SDValue N0 = Op.getOperand(0);
19133 // Look out for (store (shl (load), x)).
19134 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
19147 SDValue N0 = Op.getOperand(0);
19148 SDValue N1 = Op.getOperand(1);
19149 if (!Commute && MayFoldLoad(N1))
19151 // Avoid disabling potential load folding opportunities.
19152 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
19154 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
19164 //===----------------------------------------------------------------------===//
19165 // X86 Inline Assembly Support
19166 //===----------------------------------------------------------------------===//
19169 // Helper to match a string separated by whitespace.
19170 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
19171 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
19173 for (unsigned i = 0, e = args.size(); i != e; ++i) {
19174 StringRef piece(*args[i]);
19175 if (!s.startswith(piece)) // Check if the piece matches.
19178 s = s.substr(piece.size());
19179 StringRef::size_type pos = s.find_first_not_of(" \t");
19180 if (pos == 0) // We matched a prefix.
19188 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
19191 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
19193 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
19194 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
19195 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
19196 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
19198 if (AsmPieces.size() == 3)
19200 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
19207 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
19208 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
19210 std::string AsmStr = IA->getAsmString();
19212 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
19213 if (!Ty || Ty->getBitWidth() % 16 != 0)
19216 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
19217 SmallVector<StringRef, 4> AsmPieces;
19218 SplitString(AsmStr, AsmPieces, ";\n");
19220 switch (AsmPieces.size()) {
19221 default: return false;
19223 // FIXME: this should verify that we are targeting a 486 or better. If not,
19224 // we will turn this bswap into something that will be lowered to logical
19225 // ops instead of emitting the bswap asm. For now, we don't support 486 or
19226 // lower so don't worry about this.
19228 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
19229 matchAsm(AsmPieces[0], "bswapl", "$0") ||
19230 matchAsm(AsmPieces[0], "bswapq", "$0") ||
19231 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
19232 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
19233 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
19234 // No need to check constraints, nothing other than the equivalent of
19235 // "=r,0" would be valid here.
19236 return IntrinsicLowering::LowerToByteSwap(CI);
19239 // rorw $$8, ${0:w} --> llvm.bswap.i16
19240 if (CI->getType()->isIntegerTy(16) &&
19241 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
19242 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
19243 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
19245 const std::string &ConstraintsStr = IA->getConstraintString();
19246 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
19247 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
19248 if (clobbersFlagRegisters(AsmPieces))
19249 return IntrinsicLowering::LowerToByteSwap(CI);
19253 if (CI->getType()->isIntegerTy(32) &&
19254 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
19255 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
19256 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
19257 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
19259 const std::string &ConstraintsStr = IA->getConstraintString();
19260 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
19261 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
19262 if (clobbersFlagRegisters(AsmPieces))
19263 return IntrinsicLowering::LowerToByteSwap(CI);
19266 if (CI->getType()->isIntegerTy(64)) {
19267 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
19268 if (Constraints.size() >= 2 &&
19269 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
19270 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
19271 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
19272 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
19273 matchAsm(AsmPieces[1], "bswap", "%edx") &&
19274 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
19275 return IntrinsicLowering::LowerToByteSwap(CI);
19283 /// getConstraintType - Given a constraint letter, return the type of
19284 /// constraint it is for this target.
19285 X86TargetLowering::ConstraintType
19286 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
19287 if (Constraint.size() == 1) {
19288 switch (Constraint[0]) {
19299 return C_RegisterClass;
19323 return TargetLowering::getConstraintType(Constraint);
19326 /// Examine constraint type and operand type and determine a weight value.
19327 /// This object must already have been set up with the operand type
19328 /// and the current alternative constraint selected.
19329 TargetLowering::ConstraintWeight
19330 X86TargetLowering::getSingleConstraintMatchWeight(
19331 AsmOperandInfo &info, const char *constraint) const {
19332 ConstraintWeight weight = CW_Invalid;
19333 Value *CallOperandVal = info.CallOperandVal;
19334 // If we don't have a value, we can't do a match,
19335 // but allow it at the lowest weight.
19336 if (CallOperandVal == NULL)
19338 Type *type = CallOperandVal->getType();
19339 // Look at the constraint type.
19340 switch (*constraint) {
19342 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
19353 if (CallOperandVal->getType()->isIntegerTy())
19354 weight = CW_SpecificReg;
19359 if (type->isFloatingPointTy())
19360 weight = CW_SpecificReg;
19363 if (type->isX86_MMXTy() && Subtarget->hasMMX())
19364 weight = CW_SpecificReg;
19368 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
19369 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
19370 weight = CW_Register;
19373 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
19374 if (C->getZExtValue() <= 31)
19375 weight = CW_Constant;
19379 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19380 if (C->getZExtValue() <= 63)
19381 weight = CW_Constant;
19385 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19386 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
19387 weight = CW_Constant;
19391 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19392 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
19393 weight = CW_Constant;
19397 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19398 if (C->getZExtValue() <= 3)
19399 weight = CW_Constant;
19403 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19404 if (C->getZExtValue() <= 0xff)
19405 weight = CW_Constant;
19410 if (dyn_cast<ConstantFP>(CallOperandVal)) {
19411 weight = CW_Constant;
19415 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19416 if ((C->getSExtValue() >= -0x80000000LL) &&
19417 (C->getSExtValue() <= 0x7fffffffLL))
19418 weight = CW_Constant;
19422 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19423 if (C->getZExtValue() <= 0xffffffff)
19424 weight = CW_Constant;
19431 /// LowerXConstraint - try to replace an X constraint, which matches anything,
19432 /// with another that has more specific requirements based on the type of the
19433 /// corresponding operand.
19434 const char *X86TargetLowering::
19435 LowerXConstraint(EVT ConstraintVT) const {
19436 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
19437 // 'f' like normal targets.
19438 if (ConstraintVT.isFloatingPoint()) {
19439 if (Subtarget->hasSSE2())
19441 if (Subtarget->hasSSE1())
19445 return TargetLowering::LowerXConstraint(ConstraintVT);
19448 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
19449 /// vector. If it is invalid, don't add anything to Ops.
19450 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
19451 std::string &Constraint,
19452 std::vector<SDValue>&Ops,
19453 SelectionDAG &DAG) const {
19454 SDValue Result(0, 0);
19456 // Only support length 1 constraints for now.
19457 if (Constraint.length() > 1) return;
19459 char ConstraintLetter = Constraint[0];
19460 switch (ConstraintLetter) {
19463 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
19464 if (C->getZExtValue() <= 31) {
19465 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
19471 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
19472 if (C->getZExtValue() <= 63) {
19473 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
19479 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
19480 if (isInt<8>(C->getSExtValue())) {
19481 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
19487 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
19488 if (C->getZExtValue() <= 255) {
19489 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
19495 // 32-bit signed value
19496 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
19497 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
19498 C->getSExtValue())) {
19499 // Widen to 64 bits here to get it sign extended.
19500 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
19503 // FIXME gcc accepts some relocatable values here too, but only in certain
19504 // memory models; it's complicated.
19509 // 32-bit unsigned value
19510 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
19511 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
19512 C->getZExtValue())) {
19513 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
19517 // FIXME gcc accepts some relocatable values here too, but only in certain
19518 // memory models; it's complicated.
19522 // Literal immediates are always ok.
19523 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
19524 // Widen to 64 bits here to get it sign extended.
19525 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
19529 // In any sort of PIC mode addresses need to be computed at runtime by
19530 // adding in a register or some sort of table lookup. These can't
19531 // be used as immediates.
19532 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
19535 // If we are in non-pic codegen mode, we allow the address of a global (with
19536 // an optional displacement) to be used with 'i'.
19537 GlobalAddressSDNode *GA = 0;
19538 int64_t Offset = 0;
19540 // Match either (GA), (GA+C), (GA+C1+C2), etc.
19542 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
19543 Offset += GA->getOffset();
19545 } else if (Op.getOpcode() == ISD::ADD) {
19546 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
19547 Offset += C->getZExtValue();
19548 Op = Op.getOperand(0);
19551 } else if (Op.getOpcode() == ISD::SUB) {
19552 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
19553 Offset += -C->getZExtValue();
19554 Op = Op.getOperand(0);
19559 // Otherwise, this isn't something we can handle, reject it.
19563 const GlobalValue *GV = GA->getGlobal();
19564 // If we require an extra load to get this address, as in PIC mode, we
19565 // can't accept it.
19566 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
19567 getTargetMachine())))
19570 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
19571 GA->getValueType(0), Offset);
19576 if (Result.getNode()) {
19577 Ops.push_back(Result);
19580 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
19583 std::pair<unsigned, const TargetRegisterClass*>
19584 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
19586 // First, see if this is a constraint that directly corresponds to an LLVM
19588 if (Constraint.size() == 1) {
19589 // GCC Constraint Letters
19590 switch (Constraint[0]) {
19592 // TODO: Slight differences here in allocation order and leaving
19593 // RIP in the class. Do they matter any more here than they do
19594 // in the normal allocation?
19595 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
19596 if (Subtarget->is64Bit()) {
19597 if (VT == MVT::i32 || VT == MVT::f32)
19598 return std::make_pair(0U, &X86::GR32RegClass);
19599 if (VT == MVT::i16)
19600 return std::make_pair(0U, &X86::GR16RegClass);
19601 if (VT == MVT::i8 || VT == MVT::i1)
19602 return std::make_pair(0U, &X86::GR8RegClass);
19603 if (VT == MVT::i64 || VT == MVT::f64)
19604 return std::make_pair(0U, &X86::GR64RegClass);
19607 // 32-bit fallthrough
19608 case 'Q': // Q_REGS
19609 if (VT == MVT::i32 || VT == MVT::f32)
19610 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
19611 if (VT == MVT::i16)
19612 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
19613 if (VT == MVT::i8 || VT == MVT::i1)
19614 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
19615 if (VT == MVT::i64)
19616 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
19618 case 'r': // GENERAL_REGS
19619 case 'l': // INDEX_REGS
19620 if (VT == MVT::i8 || VT == MVT::i1)
19621 return std::make_pair(0U, &X86::GR8RegClass);
19622 if (VT == MVT::i16)
19623 return std::make_pair(0U, &X86::GR16RegClass);
19624 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
19625 return std::make_pair(0U, &X86::GR32RegClass);
19626 return std::make_pair(0U, &X86::GR64RegClass);
19627 case 'R': // LEGACY_REGS
19628 if (VT == MVT::i8 || VT == MVT::i1)
19629 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
19630 if (VT == MVT::i16)
19631 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
19632 if (VT == MVT::i32 || !Subtarget->is64Bit())
19633 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
19634 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
19635 case 'f': // FP Stack registers.
19636 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
19637 // value to the correct fpstack register class.
19638 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
19639 return std::make_pair(0U, &X86::RFP32RegClass);
19640 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
19641 return std::make_pair(0U, &X86::RFP64RegClass);
19642 return std::make_pair(0U, &X86::RFP80RegClass);
19643 case 'y': // MMX_REGS if MMX allowed.
19644 if (!Subtarget->hasMMX()) break;
19645 return std::make_pair(0U, &X86::VR64RegClass);
19646 case 'Y': // SSE_REGS if SSE2 allowed
19647 if (!Subtarget->hasSSE2()) break;
19649 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
19650 if (!Subtarget->hasSSE1()) break;
19652 switch (VT.SimpleTy) {
19654 // Scalar SSE types.
19657 return std::make_pair(0U, &X86::FR32RegClass);
19660 return std::make_pair(0U, &X86::FR64RegClass);
19668 return std::make_pair(0U, &X86::VR128RegClass);
19676 return std::make_pair(0U, &X86::VR256RegClass);
19681 return std::make_pair(0U, &X86::VR512RegClass);
19687 // Use the default implementation in TargetLowering to convert the register
19688 // constraint into a member of a register class.
19689 std::pair<unsigned, const TargetRegisterClass*> Res;
19690 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
19692 // Not found as a standard register?
19693 if (Res.second == 0) {
19694 // Map st(0) -> st(7) -> ST0
19695 if (Constraint.size() == 7 && Constraint[0] == '{' &&
19696 tolower(Constraint[1]) == 's' &&
19697 tolower(Constraint[2]) == 't' &&
19698 Constraint[3] == '(' &&
19699 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
19700 Constraint[5] == ')' &&
19701 Constraint[6] == '}') {
19703 Res.first = X86::ST0+Constraint[4]-'0';
19704 Res.second = &X86::RFP80RegClass;
19708 // GCC allows "st(0)" to be called just plain "st".
19709 if (StringRef("{st}").equals_lower(Constraint)) {
19710 Res.first = X86::ST0;
19711 Res.second = &X86::RFP80RegClass;
19716 if (StringRef("{flags}").equals_lower(Constraint)) {
19717 Res.first = X86::EFLAGS;
19718 Res.second = &X86::CCRRegClass;
19722 // 'A' means EAX + EDX.
19723 if (Constraint == "A") {
19724 Res.first = X86::EAX;
19725 Res.second = &X86::GR32_ADRegClass;
19731 // Otherwise, check to see if this is a register class of the wrong value
19732 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
19733 // turn into {ax},{dx}.
19734 if (Res.second->hasType(VT))
19735 return Res; // Correct type already, nothing to do.
19737 // All of the single-register GCC register classes map their values onto
19738 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
19739 // really want an 8-bit or 32-bit register, map to the appropriate register
19740 // class and return the appropriate register.
19741 if (Res.second == &X86::GR16RegClass) {
19742 if (VT == MVT::i8 || VT == MVT::i1) {
19743 unsigned DestReg = 0;
19744 switch (Res.first) {
19746 case X86::AX: DestReg = X86::AL; break;
19747 case X86::DX: DestReg = X86::DL; break;
19748 case X86::CX: DestReg = X86::CL; break;
19749 case X86::BX: DestReg = X86::BL; break;
19752 Res.first = DestReg;
19753 Res.second = &X86::GR8RegClass;
19755 } else if (VT == MVT::i32 || VT == MVT::f32) {
19756 unsigned DestReg = 0;
19757 switch (Res.first) {
19759 case X86::AX: DestReg = X86::EAX; break;
19760 case X86::DX: DestReg = X86::EDX; break;
19761 case X86::CX: DestReg = X86::ECX; break;
19762 case X86::BX: DestReg = X86::EBX; break;
19763 case X86::SI: DestReg = X86::ESI; break;
19764 case X86::DI: DestReg = X86::EDI; break;
19765 case X86::BP: DestReg = X86::EBP; break;
19766 case X86::SP: DestReg = X86::ESP; break;
19769 Res.first = DestReg;
19770 Res.second = &X86::GR32RegClass;
19772 } else if (VT == MVT::i64 || VT == MVT::f64) {
19773 unsigned DestReg = 0;
19774 switch (Res.first) {
19776 case X86::AX: DestReg = X86::RAX; break;
19777 case X86::DX: DestReg = X86::RDX; break;
19778 case X86::CX: DestReg = X86::RCX; break;
19779 case X86::BX: DestReg = X86::RBX; break;
19780 case X86::SI: DestReg = X86::RSI; break;
19781 case X86::DI: DestReg = X86::RDI; break;
19782 case X86::BP: DestReg = X86::RBP; break;
19783 case X86::SP: DestReg = X86::RSP; break;
19786 Res.first = DestReg;
19787 Res.second = &X86::GR64RegClass;
19790 } else if (Res.second == &X86::FR32RegClass ||
19791 Res.second == &X86::FR64RegClass ||
19792 Res.second == &X86::VR128RegClass ||
19793 Res.second == &X86::VR256RegClass ||
19794 Res.second == &X86::FR32XRegClass ||
19795 Res.second == &X86::FR64XRegClass ||
19796 Res.second == &X86::VR128XRegClass ||
19797 Res.second == &X86::VR256XRegClass ||
19798 Res.second == &X86::VR512RegClass) {
19799 // Handle references to XMM physical registers that got mapped into the
19800 // wrong class. This can happen with constraints like {xmm0} where the
19801 // target independent register mapper will just pick the first match it can
19802 // find, ignoring the required type.
19804 if (VT == MVT::f32 || VT == MVT::i32)
19805 Res.second = &X86::FR32RegClass;
19806 else if (VT == MVT::f64 || VT == MVT::i64)
19807 Res.second = &X86::FR64RegClass;
19808 else if (X86::VR128RegClass.hasType(VT))
19809 Res.second = &X86::VR128RegClass;
19810 else if (X86::VR256RegClass.hasType(VT))
19811 Res.second = &X86::VR256RegClass;
19812 else if (X86::VR512RegClass.hasType(VT))
19813 Res.second = &X86::VR512RegClass;