1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
16 #include "X86InstrBuilder.h"
17 #include "X86ISelLowering.h"
18 #include "X86TargetMachine.h"
19 #include "X86TargetObjectFile.h"
20 #include "llvm/CallingConv.h"
21 #include "llvm/Constants.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/GlobalAlias.h"
24 #include "llvm/GlobalVariable.h"
25 #include "llvm/Function.h"
26 #include "llvm/Instructions.h"
27 #include "llvm/Intrinsics.h"
28 #include "llvm/LLVMContext.h"
29 #include "llvm/ADT/BitVector.h"
30 #include "llvm/ADT/VectorExtras.h"
31 #include "llvm/CodeGen/MachineFrameInfo.h"
32 #include "llvm/CodeGen/MachineFunction.h"
33 #include "llvm/CodeGen/MachineInstrBuilder.h"
34 #include "llvm/CodeGen/MachineModuleInfo.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/PseudoSourceValue.h"
37 #include "llvm/Support/MathExtras.h"
38 #include "llvm/Support/Debug.h"
39 #include "llvm/Support/ErrorHandling.h"
40 #include "llvm/Target/TargetOptions.h"
41 #include "llvm/ADT/SmallSet.h"
42 #include "llvm/ADT/StringExtras.h"
43 #include "llvm/Support/CommandLine.h"
44 #include "llvm/Support/raw_ostream.h"
48 DisableMMX("disable-mmx", cl::Hidden, cl::desc("Disable use of MMX"));
50 // Disable16Bit - 16-bit operations typically have a larger encoding than
51 // corresponding 32-bit instructions, and 16-bit code is slow on some
52 // processors. This is an experimental flag to disable 16-bit operations
53 // (which forces them to be Legalized to 32-bit operations).
55 Disable16Bit("disable-16bit", cl::Hidden,
56 cl::desc("Disable use of 16-bit instructions"));
58 // Forward declarations.
59 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
62 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
63 switch (TM.getSubtarget<X86Subtarget>().TargetType) {
64 default: llvm_unreachable("unknown subtarget type");
65 case X86Subtarget::isDarwin:
66 if (TM.getSubtarget<X86Subtarget>().is64Bit())
67 return new X8664_MachoTargetObjectFile();
68 return new X8632_MachoTargetObjectFile();
69 case X86Subtarget::isELF:
70 return new TargetLoweringObjectFileELF();
71 case X86Subtarget::isMingw:
72 case X86Subtarget::isCygwin:
73 case X86Subtarget::isWindows:
74 return new TargetLoweringObjectFileCOFF();
79 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
80 : TargetLowering(TM, createTLOF(TM)) {
81 Subtarget = &TM.getSubtarget<X86Subtarget>();
82 X86ScalarSSEf64 = Subtarget->hasSSE2();
83 X86ScalarSSEf32 = Subtarget->hasSSE1();
84 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
86 RegInfo = TM.getRegisterInfo();
89 // Set up the TargetLowering object.
91 // X86 is weird, it always uses i8 for shift amounts and setcc results.
92 setShiftAmountType(MVT::i8);
93 setBooleanContents(ZeroOrOneBooleanContent);
94 setSchedulingPreference(SchedulingForRegPressure);
95 setStackPointerRegisterToSaveRestore(X86StackPtr);
97 if (Subtarget->isTargetDarwin()) {
98 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
99 setUseUnderscoreSetJmp(false);
100 setUseUnderscoreLongJmp(false);
101 } else if (Subtarget->isTargetMingw()) {
102 // MS runtime is weird: it exports _setjmp, but longjmp!
103 setUseUnderscoreSetJmp(true);
104 setUseUnderscoreLongJmp(false);
106 setUseUnderscoreSetJmp(true);
107 setUseUnderscoreLongJmp(true);
110 // Set up the register classes.
111 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
113 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
114 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
115 if (Subtarget->is64Bit())
116 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
118 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
120 // We don't accept any truncstore of integer registers.
121 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
123 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
124 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
126 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
127 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
128 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
130 // SETOEQ and SETUNE require checking two conditions.
131 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
132 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
133 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
134 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
135 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
136 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
138 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
140 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
141 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
142 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
144 if (Subtarget->is64Bit()) {
145 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
146 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand);
147 } else if (!UseSoftFloat) {
148 if (X86ScalarSSEf64) {
149 // We have an impenetrably clever algorithm for ui64->double only.
150 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
152 // We have an algorithm for SSE2, and we turn this into a 64-bit
153 // FILD for other targets.
154 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
157 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
159 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
160 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
163 // SSE has no i16 to fp conversion, only i32
164 if (X86ScalarSSEf32) {
165 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
166 // f32 and f64 cases are Legal, f80 case is not
167 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
169 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
170 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
173 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
174 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
177 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
178 // are Legal, f80 is custom lowered.
179 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
180 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
182 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
184 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
185 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
187 if (X86ScalarSSEf32) {
188 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
189 // f32 and f64 cases are Legal, f80 case is not
190 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
192 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
193 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
196 // Handle FP_TO_UINT by promoting the destination to a larger signed
198 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
199 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
200 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
202 if (Subtarget->is64Bit()) {
203 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
204 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
205 } else if (!UseSoftFloat) {
206 if (X86ScalarSSEf32 && !Subtarget->hasSSE3())
207 // Expand FP_TO_UINT into a select.
208 // FIXME: We would like to use a Custom expander here eventually to do
209 // the optimal thing for SSE vs. the default expansion in the legalizer.
210 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
212 // With SSE3 we can use fisttpll to convert to a signed i64; without
213 // SSE, we're stuck with a fistpll.
214 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
217 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
218 if (!X86ScalarSSEf64) {
219 setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand);
220 setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand);
223 // Scalar integer divide and remainder are lowered to use operations that
224 // produce two results, to match the available instructions. This exposes
225 // the two-result form to trivial CSE, which is able to combine x/y and x%y
226 // into a single instruction.
228 // Scalar integer multiply-high is also lowered to use two-result
229 // operations, to match the available instructions. However, plain multiply
230 // (low) operations are left as Legal, as there are single-result
231 // instructions for this in x86. Using the two-result multiply instructions
232 // when both high and low results are needed must be arranged by dagcombine.
233 setOperationAction(ISD::MULHS , MVT::i8 , Expand);
234 setOperationAction(ISD::MULHU , MVT::i8 , Expand);
235 setOperationAction(ISD::SDIV , MVT::i8 , Expand);
236 setOperationAction(ISD::UDIV , MVT::i8 , Expand);
237 setOperationAction(ISD::SREM , MVT::i8 , Expand);
238 setOperationAction(ISD::UREM , MVT::i8 , Expand);
239 setOperationAction(ISD::MULHS , MVT::i16 , Expand);
240 setOperationAction(ISD::MULHU , MVT::i16 , Expand);
241 setOperationAction(ISD::SDIV , MVT::i16 , Expand);
242 setOperationAction(ISD::UDIV , MVT::i16 , Expand);
243 setOperationAction(ISD::SREM , MVT::i16 , Expand);
244 setOperationAction(ISD::UREM , MVT::i16 , Expand);
245 setOperationAction(ISD::MULHS , MVT::i32 , Expand);
246 setOperationAction(ISD::MULHU , MVT::i32 , Expand);
247 setOperationAction(ISD::SDIV , MVT::i32 , Expand);
248 setOperationAction(ISD::UDIV , MVT::i32 , Expand);
249 setOperationAction(ISD::SREM , MVT::i32 , Expand);
250 setOperationAction(ISD::UREM , MVT::i32 , Expand);
251 setOperationAction(ISD::MULHS , MVT::i64 , Expand);
252 setOperationAction(ISD::MULHU , MVT::i64 , Expand);
253 setOperationAction(ISD::SDIV , MVT::i64 , Expand);
254 setOperationAction(ISD::UDIV , MVT::i64 , Expand);
255 setOperationAction(ISD::SREM , MVT::i64 , Expand);
256 setOperationAction(ISD::UREM , MVT::i64 , Expand);
258 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
259 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
260 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
261 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
262 if (Subtarget->is64Bit())
263 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
264 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
265 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
266 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
267 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
268 setOperationAction(ISD::FREM , MVT::f32 , Expand);
269 setOperationAction(ISD::FREM , MVT::f64 , Expand);
270 setOperationAction(ISD::FREM , MVT::f80 , Expand);
271 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
273 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
274 setOperationAction(ISD::CTTZ , MVT::i8 , Custom);
275 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
276 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
278 setOperationAction(ISD::CTTZ , MVT::i16 , Expand);
279 setOperationAction(ISD::CTLZ , MVT::i16 , Expand);
281 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
282 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
284 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
285 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
286 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
287 if (Subtarget->is64Bit()) {
288 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
289 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
290 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
293 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
294 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
296 // These should be promoted to a larger select which is supported.
297 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
298 // X86 wants to expand cmov itself.
299 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
301 setOperationAction(ISD::SELECT , MVT::i16 , Expand);
303 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
304 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
305 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
306 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
307 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
308 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
310 setOperationAction(ISD::SETCC , MVT::i16 , Expand);
312 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
313 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
314 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
315 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
316 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
317 if (Subtarget->is64Bit()) {
318 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
319 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
321 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
324 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
325 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
326 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
327 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
328 if (Subtarget->is64Bit())
329 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
330 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
331 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
332 if (Subtarget->is64Bit()) {
333 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
334 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
335 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
336 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
337 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
339 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
340 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
341 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
342 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
343 if (Subtarget->is64Bit()) {
344 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
345 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
346 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
349 if (Subtarget->hasSSE1())
350 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
352 if (!Subtarget->hasSSE2())
353 setOperationAction(ISD::MEMBARRIER , MVT::Other, Expand);
355 // Expand certain atomics
356 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i8, Custom);
357 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i16, Custom);
358 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom);
359 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom);
361 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i8, Custom);
362 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i16, Custom);
363 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Custom);
364 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
366 if (!Subtarget->is64Bit()) {
367 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
368 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
369 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
370 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
371 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
372 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
373 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
376 // FIXME - use subtarget debug flags
377 if (!Subtarget->isTargetDarwin() &&
378 !Subtarget->isTargetELF() &&
379 !Subtarget->isTargetCygMing()) {
380 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
383 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
384 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
385 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
386 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
387 if (Subtarget->is64Bit()) {
388 setExceptionPointerRegister(X86::RAX);
389 setExceptionSelectorRegister(X86::RDX);
391 setExceptionPointerRegister(X86::EAX);
392 setExceptionSelectorRegister(X86::EDX);
394 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
395 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
397 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom);
399 setOperationAction(ISD::TRAP, MVT::Other, Legal);
401 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
402 setOperationAction(ISD::VASTART , MVT::Other, Custom);
403 setOperationAction(ISD::VAEND , MVT::Other, Expand);
404 if (Subtarget->is64Bit()) {
405 setOperationAction(ISD::VAARG , MVT::Other, Custom);
406 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
408 setOperationAction(ISD::VAARG , MVT::Other, Expand);
409 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
412 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
413 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
414 if (Subtarget->is64Bit())
415 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
416 if (Subtarget->isTargetCygMing())
417 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
419 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
421 if (!UseSoftFloat && X86ScalarSSEf64) {
422 // f32 and f64 use SSE.
423 // Set up the FP register classes.
424 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
425 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
427 // Use ANDPD to simulate FABS.
428 setOperationAction(ISD::FABS , MVT::f64, Custom);
429 setOperationAction(ISD::FABS , MVT::f32, Custom);
431 // Use XORP to simulate FNEG.
432 setOperationAction(ISD::FNEG , MVT::f64, Custom);
433 setOperationAction(ISD::FNEG , MVT::f32, Custom);
435 // Use ANDPD and ORPD to simulate FCOPYSIGN.
436 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
437 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
439 // We don't support sin/cos/fmod
440 setOperationAction(ISD::FSIN , MVT::f64, Expand);
441 setOperationAction(ISD::FCOS , MVT::f64, Expand);
442 setOperationAction(ISD::FSIN , MVT::f32, Expand);
443 setOperationAction(ISD::FCOS , MVT::f32, Expand);
445 // Expand FP immediates into loads from the stack, except for the special
447 addLegalFPImmediate(APFloat(+0.0)); // xorpd
448 addLegalFPImmediate(APFloat(+0.0f)); // xorps
449 } else if (!UseSoftFloat && X86ScalarSSEf32) {
450 // Use SSE for f32, x87 for f64.
451 // Set up the FP register classes.
452 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
453 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
455 // Use ANDPS to simulate FABS.
456 setOperationAction(ISD::FABS , MVT::f32, Custom);
458 // Use XORP to simulate FNEG.
459 setOperationAction(ISD::FNEG , MVT::f32, Custom);
461 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
463 // Use ANDPS and ORPS to simulate FCOPYSIGN.
464 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
465 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
467 // We don't support sin/cos/fmod
468 setOperationAction(ISD::FSIN , MVT::f32, Expand);
469 setOperationAction(ISD::FCOS , MVT::f32, Expand);
471 // Special cases we handle for FP constants.
472 addLegalFPImmediate(APFloat(+0.0f)); // xorps
473 addLegalFPImmediate(APFloat(+0.0)); // FLD0
474 addLegalFPImmediate(APFloat(+1.0)); // FLD1
475 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
476 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
479 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
480 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
482 } else if (!UseSoftFloat) {
483 // f32 and f64 in x87.
484 // Set up the FP register classes.
485 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
486 addRegisterClass(MVT::f32, X86::RFP32RegisterClass);
488 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
489 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
490 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
491 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
494 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
495 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
497 addLegalFPImmediate(APFloat(+0.0)); // FLD0
498 addLegalFPImmediate(APFloat(+1.0)); // FLD1
499 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
500 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
501 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
502 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
503 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
504 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
507 // Long double always uses X87.
509 addRegisterClass(MVT::f80, X86::RFP80RegisterClass);
510 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
511 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
514 APFloat TmpFlt(+0.0);
515 TmpFlt.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
517 addLegalFPImmediate(TmpFlt); // FLD0
519 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
520 APFloat TmpFlt2(+1.0);
521 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
523 addLegalFPImmediate(TmpFlt2); // FLD1
524 TmpFlt2.changeSign();
525 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
529 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
530 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
534 // Always use a library call for pow.
535 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
536 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
537 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
539 setOperationAction(ISD::FLOG, MVT::f80, Expand);
540 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
541 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
542 setOperationAction(ISD::FEXP, MVT::f80, Expand);
543 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
545 // First set operation action for all vector types to either promote
546 // (for widening) or expand (for scalarization). Then we will selectively
547 // turn on ones that can be effectively codegen'd.
548 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
549 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
550 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
551 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
552 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
553 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
554 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
555 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
556 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
557 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
558 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
559 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
560 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
561 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
562 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
563 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
564 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
565 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
566 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
567 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
568 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
569 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
570 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
571 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
572 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
573 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
574 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
575 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
576 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
577 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
578 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
579 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
580 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
581 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
582 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
583 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
584 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
585 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
586 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
587 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
588 setOperationAction(ISD::VSETCC, (MVT::SimpleValueType)VT, Expand);
589 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
590 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
591 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
592 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand);
593 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand);
594 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand);
595 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand);
596 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
597 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
598 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand);
599 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand);
600 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand);
601 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand);
602 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand);
603 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
604 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
605 setTruncStoreAction((MVT::SimpleValueType)VT,
606 (MVT::SimpleValueType)InnerVT, Expand);
607 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
608 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
609 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
612 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
613 // with -msoft-float, disable use of MMX as well.
614 if (!UseSoftFloat && !DisableMMX && Subtarget->hasMMX()) {
615 addRegisterClass(MVT::v8i8, X86::VR64RegisterClass);
616 addRegisterClass(MVT::v4i16, X86::VR64RegisterClass);
617 addRegisterClass(MVT::v2i32, X86::VR64RegisterClass);
618 addRegisterClass(MVT::v2f32, X86::VR64RegisterClass);
619 addRegisterClass(MVT::v1i64, X86::VR64RegisterClass);
621 setOperationAction(ISD::ADD, MVT::v8i8, Legal);
622 setOperationAction(ISD::ADD, MVT::v4i16, Legal);
623 setOperationAction(ISD::ADD, MVT::v2i32, Legal);
624 setOperationAction(ISD::ADD, MVT::v1i64, Legal);
626 setOperationAction(ISD::SUB, MVT::v8i8, Legal);
627 setOperationAction(ISD::SUB, MVT::v4i16, Legal);
628 setOperationAction(ISD::SUB, MVT::v2i32, Legal);
629 setOperationAction(ISD::SUB, MVT::v1i64, Legal);
631 setOperationAction(ISD::MULHS, MVT::v4i16, Legal);
632 setOperationAction(ISD::MUL, MVT::v4i16, Legal);
634 setOperationAction(ISD::AND, MVT::v8i8, Promote);
635 AddPromotedToType (ISD::AND, MVT::v8i8, MVT::v1i64);
636 setOperationAction(ISD::AND, MVT::v4i16, Promote);
637 AddPromotedToType (ISD::AND, MVT::v4i16, MVT::v1i64);
638 setOperationAction(ISD::AND, MVT::v2i32, Promote);
639 AddPromotedToType (ISD::AND, MVT::v2i32, MVT::v1i64);
640 setOperationAction(ISD::AND, MVT::v1i64, Legal);
642 setOperationAction(ISD::OR, MVT::v8i8, Promote);
643 AddPromotedToType (ISD::OR, MVT::v8i8, MVT::v1i64);
644 setOperationAction(ISD::OR, MVT::v4i16, Promote);
645 AddPromotedToType (ISD::OR, MVT::v4i16, MVT::v1i64);
646 setOperationAction(ISD::OR, MVT::v2i32, Promote);
647 AddPromotedToType (ISD::OR, MVT::v2i32, MVT::v1i64);
648 setOperationAction(ISD::OR, MVT::v1i64, Legal);
650 setOperationAction(ISD::XOR, MVT::v8i8, Promote);
651 AddPromotedToType (ISD::XOR, MVT::v8i8, MVT::v1i64);
652 setOperationAction(ISD::XOR, MVT::v4i16, Promote);
653 AddPromotedToType (ISD::XOR, MVT::v4i16, MVT::v1i64);
654 setOperationAction(ISD::XOR, MVT::v2i32, Promote);
655 AddPromotedToType (ISD::XOR, MVT::v2i32, MVT::v1i64);
656 setOperationAction(ISD::XOR, MVT::v1i64, Legal);
658 setOperationAction(ISD::LOAD, MVT::v8i8, Promote);
659 AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v1i64);
660 setOperationAction(ISD::LOAD, MVT::v4i16, Promote);
661 AddPromotedToType (ISD::LOAD, MVT::v4i16, MVT::v1i64);
662 setOperationAction(ISD::LOAD, MVT::v2i32, Promote);
663 AddPromotedToType (ISD::LOAD, MVT::v2i32, MVT::v1i64);
664 setOperationAction(ISD::LOAD, MVT::v2f32, Promote);
665 AddPromotedToType (ISD::LOAD, MVT::v2f32, MVT::v1i64);
666 setOperationAction(ISD::LOAD, MVT::v1i64, Legal);
668 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Custom);
669 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom);
670 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Custom);
671 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f32, Custom);
672 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i64, Custom);
674 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom);
675 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
676 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i32, Custom);
677 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v1i64, Custom);
679 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f32, Custom);
680 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Custom);
681 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Custom);
682 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Custom);
684 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i16, Custom);
686 setOperationAction(ISD::SELECT, MVT::v8i8, Promote);
687 setOperationAction(ISD::SELECT, MVT::v4i16, Promote);
688 setOperationAction(ISD::SELECT, MVT::v2i32, Promote);
689 setOperationAction(ISD::SELECT, MVT::v1i64, Custom);
690 setOperationAction(ISD::VSETCC, MVT::v8i8, Custom);
691 setOperationAction(ISD::VSETCC, MVT::v4i16, Custom);
692 setOperationAction(ISD::VSETCC, MVT::v2i32, Custom);
695 if (!UseSoftFloat && Subtarget->hasSSE1()) {
696 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
698 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
699 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
700 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
701 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
702 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
703 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
704 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
705 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
706 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
707 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
708 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
709 setOperationAction(ISD::VSETCC, MVT::v4f32, Custom);
712 if (!UseSoftFloat && Subtarget->hasSSE2()) {
713 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
715 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
716 // registers cannot be used even for integer operations.
717 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
718 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
719 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
720 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
722 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
723 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
724 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
725 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
726 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
727 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
728 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
729 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
730 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
731 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
732 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
733 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
734 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
735 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
736 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
737 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
739 setOperationAction(ISD::VSETCC, MVT::v2f64, Custom);
740 setOperationAction(ISD::VSETCC, MVT::v16i8, Custom);
741 setOperationAction(ISD::VSETCC, MVT::v8i16, Custom);
742 setOperationAction(ISD::VSETCC, MVT::v4i32, Custom);
744 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
745 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
746 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
747 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
748 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
750 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
751 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) {
752 EVT VT = (MVT::SimpleValueType)i;
753 // Do not attempt to custom lower non-power-of-2 vectors
754 if (!isPowerOf2_32(VT.getVectorNumElements()))
756 // Do not attempt to custom lower non-128-bit vectors
757 if (!VT.is128BitVector())
759 setOperationAction(ISD::BUILD_VECTOR,
760 VT.getSimpleVT().SimpleTy, Custom);
761 setOperationAction(ISD::VECTOR_SHUFFLE,
762 VT.getSimpleVT().SimpleTy, Custom);
763 setOperationAction(ISD::EXTRACT_VECTOR_ELT,
764 VT.getSimpleVT().SimpleTy, Custom);
767 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
768 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
769 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
770 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
771 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
772 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
774 if (Subtarget->is64Bit()) {
775 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
776 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
779 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
780 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) {
781 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
784 // Do not attempt to promote non-128-bit vectors
785 if (!VT.is128BitVector()) {
788 setOperationAction(ISD::AND, SVT, Promote);
789 AddPromotedToType (ISD::AND, SVT, MVT::v2i64);
790 setOperationAction(ISD::OR, SVT, Promote);
791 AddPromotedToType (ISD::OR, SVT, MVT::v2i64);
792 setOperationAction(ISD::XOR, SVT, Promote);
793 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64);
794 setOperationAction(ISD::LOAD, SVT, Promote);
795 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64);
796 setOperationAction(ISD::SELECT, SVT, Promote);
797 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64);
800 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
802 // Custom lower v2i64 and v2f64 selects.
803 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
804 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
805 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
806 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
808 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
809 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
810 if (!DisableMMX && Subtarget->hasMMX()) {
811 setOperationAction(ISD::FP_TO_SINT, MVT::v2i32, Custom);
812 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
816 if (Subtarget->hasSSE41()) {
817 // FIXME: Do we need to handle scalar-to-vector here?
818 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
820 // i8 and i16 vectors are custom , because the source register and source
821 // source memory operand types are not the same width. f32 vectors are
822 // custom since the immediate controlling the insert encodes additional
824 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
825 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
826 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
827 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
829 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
830 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
831 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
832 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
834 if (Subtarget->is64Bit()) {
835 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal);
836 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal);
840 if (Subtarget->hasSSE42()) {
841 setOperationAction(ISD::VSETCC, MVT::v2i64, Custom);
844 if (!UseSoftFloat && Subtarget->hasAVX()) {
845 addRegisterClass(MVT::v8f32, X86::VR256RegisterClass);
846 addRegisterClass(MVT::v4f64, X86::VR256RegisterClass);
847 addRegisterClass(MVT::v8i32, X86::VR256RegisterClass);
848 addRegisterClass(MVT::v4i64, X86::VR256RegisterClass);
850 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
851 setOperationAction(ISD::LOAD, MVT::v8i32, Legal);
852 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
853 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
854 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
855 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
856 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
857 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
858 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
859 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
860 //setOperationAction(ISD::BUILD_VECTOR, MVT::v8f32, Custom);
861 //setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Custom);
862 //setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8f32, Custom);
863 //setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
864 //setOperationAction(ISD::VSETCC, MVT::v8f32, Custom);
866 // Operations to consider commented out -v16i16 v32i8
867 //setOperationAction(ISD::ADD, MVT::v16i16, Legal);
868 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
869 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
870 //setOperationAction(ISD::SUB, MVT::v32i8, Legal);
871 //setOperationAction(ISD::SUB, MVT::v16i16, Legal);
872 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
873 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
874 //setOperationAction(ISD::MUL, MVT::v16i16, Legal);
875 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
876 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
877 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
878 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
879 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
880 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
882 setOperationAction(ISD::VSETCC, MVT::v4f64, Custom);
883 // setOperationAction(ISD::VSETCC, MVT::v32i8, Custom);
884 // setOperationAction(ISD::VSETCC, MVT::v16i16, Custom);
885 setOperationAction(ISD::VSETCC, MVT::v8i32, Custom);
887 // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v32i8, Custom);
888 // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i16, Custom);
889 // setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i16, Custom);
890 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i32, Custom);
891 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8f32, Custom);
893 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f64, Custom);
894 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i64, Custom);
895 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f64, Custom);
896 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i64, Custom);
897 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f64, Custom);
898 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f64, Custom);
901 // Not sure we want to do this since there are no 256-bit integer
904 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
905 // This includes 256-bit vectors
906 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; ++i) {
907 EVT VT = (MVT::SimpleValueType)i;
909 // Do not attempt to custom lower non-power-of-2 vectors
910 if (!isPowerOf2_32(VT.getVectorNumElements()))
913 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
914 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
915 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
918 if (Subtarget->is64Bit()) {
919 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i64, Custom);
920 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i64, Custom);
925 // Not sure we want to do this since there are no 256-bit integer
928 // Promote v32i8, v16i16, v8i32 load, select, and, or, xor to v4i64.
929 // Including 256-bit vectors
930 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; i++) {
931 EVT VT = (MVT::SimpleValueType)i;
933 if (!VT.is256BitVector()) {
936 setOperationAction(ISD::AND, VT, Promote);
937 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
938 setOperationAction(ISD::OR, VT, Promote);
939 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
940 setOperationAction(ISD::XOR, VT, Promote);
941 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
942 setOperationAction(ISD::LOAD, VT, Promote);
943 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
944 setOperationAction(ISD::SELECT, VT, Promote);
945 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
948 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
952 // We want to custom lower some of our intrinsics.
953 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
955 // Add/Sub/Mul with overflow operations are custom lowered.
956 setOperationAction(ISD::SADDO, MVT::i32, Custom);
957 setOperationAction(ISD::SADDO, MVT::i64, Custom);
958 setOperationAction(ISD::UADDO, MVT::i32, Custom);
959 setOperationAction(ISD::UADDO, MVT::i64, Custom);
960 setOperationAction(ISD::SSUBO, MVT::i32, Custom);
961 setOperationAction(ISD::SSUBO, MVT::i64, Custom);
962 setOperationAction(ISD::USUBO, MVT::i32, Custom);
963 setOperationAction(ISD::USUBO, MVT::i64, Custom);
964 setOperationAction(ISD::SMULO, MVT::i32, Custom);
965 setOperationAction(ISD::SMULO, MVT::i64, Custom);
967 if (!Subtarget->is64Bit()) {
968 // These libcalls are not available in 32-bit.
969 setLibcallName(RTLIB::SHL_I128, 0);
970 setLibcallName(RTLIB::SRL_I128, 0);
971 setLibcallName(RTLIB::SRA_I128, 0);
974 // We have target-specific dag combine patterns for the following nodes:
975 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
976 setTargetDAGCombine(ISD::BUILD_VECTOR);
977 setTargetDAGCombine(ISD::SELECT);
978 setTargetDAGCombine(ISD::SHL);
979 setTargetDAGCombine(ISD::SRA);
980 setTargetDAGCombine(ISD::SRL);
981 setTargetDAGCombine(ISD::OR);
982 setTargetDAGCombine(ISD::STORE);
983 setTargetDAGCombine(ISD::MEMBARRIER);
984 setTargetDAGCombine(ISD::ZERO_EXTEND);
985 if (Subtarget->is64Bit())
986 setTargetDAGCombine(ISD::MUL);
988 computeRegisterProperties();
990 // Divide and reminder operations have no vector equivalent and can
991 // trap. Do a custom widening for these operations in which we never
992 // generate more divides/remainder than the original vector width.
993 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
994 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
995 if (!isTypeLegal((MVT::SimpleValueType)VT)) {
996 setOperationAction(ISD::SDIV, (MVT::SimpleValueType) VT, Custom);
997 setOperationAction(ISD::UDIV, (MVT::SimpleValueType) VT, Custom);
998 setOperationAction(ISD::SREM, (MVT::SimpleValueType) VT, Custom);
999 setOperationAction(ISD::UREM, (MVT::SimpleValueType) VT, Custom);
1003 // FIXME: These should be based on subtarget info. Plus, the values should
1004 // be smaller when we are in optimizing for size mode.
1005 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1006 maxStoresPerMemcpy = 16; // For @llvm.memcpy -> sequence of stores
1007 maxStoresPerMemmove = 3; // For @llvm.memmove -> sequence of stores
1008 setPrefLoopAlignment(16);
1009 benefitFromCodePlacementOpt = true;
1013 MVT::SimpleValueType X86TargetLowering::getSetCCResultType(EVT VT) const {
1018 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1019 /// the desired ByVal argument alignment.
1020 static void getMaxByValAlign(const Type *Ty, unsigned &MaxAlign) {
1023 if (const VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1024 if (VTy->getBitWidth() == 128)
1026 } else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1027 unsigned EltAlign = 0;
1028 getMaxByValAlign(ATy->getElementType(), EltAlign);
1029 if (EltAlign > MaxAlign)
1030 MaxAlign = EltAlign;
1031 } else if (const StructType *STy = dyn_cast<StructType>(Ty)) {
1032 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1033 unsigned EltAlign = 0;
1034 getMaxByValAlign(STy->getElementType(i), EltAlign);
1035 if (EltAlign > MaxAlign)
1036 MaxAlign = EltAlign;
1044 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1045 /// function arguments in the caller parameter area. For X86, aggregates
1046 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1047 /// are at 4-byte boundaries.
1048 unsigned X86TargetLowering::getByValTypeAlignment(const Type *Ty) const {
1049 if (Subtarget->is64Bit()) {
1050 // Max of 8 and alignment of type.
1051 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1058 if (Subtarget->hasSSE1())
1059 getMaxByValAlign(Ty, Align);
1063 /// getOptimalMemOpType - Returns the target specific optimal type for load
1064 /// and store operations as a result of memset, memcpy, and memmove
1065 /// lowering. It returns MVT::iAny if SelectionDAG should be responsible for
1068 X86TargetLowering::getOptimalMemOpType(uint64_t Size, unsigned Align,
1069 bool isSrcConst, bool isSrcStr,
1070 SelectionDAG &DAG) const {
1071 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like
1072 // linux. This is because the stack realignment code can't handle certain
1073 // cases like PR2962. This should be removed when PR2962 is fixed.
1074 const Function *F = DAG.getMachineFunction().getFunction();
1075 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
1076 if (!NoImplicitFloatOps && Subtarget->getStackAlignment() >= 16) {
1077 if ((isSrcConst || isSrcStr) && Subtarget->hasSSE2() && Size >= 16)
1079 if ((isSrcConst || isSrcStr) && Subtarget->hasSSE1() && Size >= 16)
1082 if (Subtarget->is64Bit() && Size >= 8)
1087 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1089 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1090 SelectionDAG &DAG) const {
1091 if (usesGlobalOffsetTable())
1092 return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy());
1093 if (!Subtarget->is64Bit())
1094 // This doesn't have DebugLoc associated with it, but is not really the
1095 // same as a Register.
1096 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc::getUnknownLoc(),
1101 /// getFunctionAlignment - Return the Log2 alignment of this function.
1102 unsigned X86TargetLowering::getFunctionAlignment(const Function *F) const {
1103 return F->hasFnAttr(Attribute::OptimizeForSize) ? 0 : 4;
1106 //===----------------------------------------------------------------------===//
1107 // Return Value Calling Convention Implementation
1108 //===----------------------------------------------------------------------===//
1110 #include "X86GenCallingConv.inc"
1113 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
1114 const SmallVectorImpl<EVT> &OutTys,
1115 const SmallVectorImpl<ISD::ArgFlagsTy> &ArgsFlags,
1116 SelectionDAG &DAG) {
1117 SmallVector<CCValAssign, 16> RVLocs;
1118 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1119 RVLocs, *DAG.getContext());
1120 return CCInfo.CheckReturn(OutTys, ArgsFlags, RetCC_X86);
1124 X86TargetLowering::LowerReturn(SDValue Chain,
1125 CallingConv::ID CallConv, bool isVarArg,
1126 const SmallVectorImpl<ISD::OutputArg> &Outs,
1127 DebugLoc dl, SelectionDAG &DAG) {
1129 SmallVector<CCValAssign, 16> RVLocs;
1130 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1131 RVLocs, *DAG.getContext());
1132 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1134 // If this is the first return lowered for this function, add the regs to the
1135 // liveout set for the function.
1136 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1137 for (unsigned i = 0; i != RVLocs.size(); ++i)
1138 if (RVLocs[i].isRegLoc())
1139 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1144 SmallVector<SDValue, 6> RetOps;
1145 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1146 // Operand #1 = Bytes To Pop
1147 RetOps.push_back(DAG.getTargetConstant(getBytesToPopOnReturn(), MVT::i16));
1149 // Copy the result values into the output registers.
1150 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1151 CCValAssign &VA = RVLocs[i];
1152 assert(VA.isRegLoc() && "Can only return in registers!");
1153 SDValue ValToCopy = Outs[i].Val;
1155 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1156 // the RET instruction and handled by the FP Stackifier.
1157 if (VA.getLocReg() == X86::ST0 ||
1158 VA.getLocReg() == X86::ST1) {
1159 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1160 // change the value to the FP stack register class.
1161 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1162 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1163 RetOps.push_back(ValToCopy);
1164 // Don't emit a copytoreg.
1168 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1169 // which is returned in RAX / RDX.
1170 if (Subtarget->is64Bit()) {
1171 EVT ValVT = ValToCopy.getValueType();
1172 if (ValVT.isVector() && ValVT.getSizeInBits() == 64) {
1173 ValToCopy = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, ValToCopy);
1174 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1)
1175 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, ValToCopy);
1179 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1180 Flag = Chain.getValue(1);
1183 // The x86-64 ABI for returning structs by value requires that we copy
1184 // the sret argument into %rax for the return. We saved the argument into
1185 // a virtual register in the entry block, so now we copy the value out
1187 if (Subtarget->is64Bit() &&
1188 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1189 MachineFunction &MF = DAG.getMachineFunction();
1190 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1191 unsigned Reg = FuncInfo->getSRetReturnReg();
1193 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1194 FuncInfo->setSRetReturnReg(Reg);
1196 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1198 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag);
1199 Flag = Chain.getValue(1);
1201 // RAX now acts like a return value.
1202 MF.getRegInfo().addLiveOut(X86::RAX);
1205 RetOps[0] = Chain; // Update chain.
1207 // Add the flag if we have it.
1209 RetOps.push_back(Flag);
1211 return DAG.getNode(X86ISD::RET_FLAG, dl,
1212 MVT::Other, &RetOps[0], RetOps.size());
1215 /// LowerCallResult - Lower the result values of a call into the
1216 /// appropriate copies out of appropriate physical registers.
1219 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1220 CallingConv::ID CallConv, bool isVarArg,
1221 const SmallVectorImpl<ISD::InputArg> &Ins,
1222 DebugLoc dl, SelectionDAG &DAG,
1223 SmallVectorImpl<SDValue> &InVals) {
1225 // Assign locations to each value returned by this call.
1226 SmallVector<CCValAssign, 16> RVLocs;
1227 bool Is64Bit = Subtarget->is64Bit();
1228 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1229 RVLocs, *DAG.getContext());
1230 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1232 // Copy all of the result registers out of their specified physreg.
1233 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1234 CCValAssign &VA = RVLocs[i];
1235 EVT CopyVT = VA.getValVT();
1237 // If this is x86-64, and we disabled SSE, we can't return FP values
1238 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1239 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
1240 llvm_report_error("SSE register return with SSE disabled");
1243 // If this is a call to a function that returns an fp value on the floating
1244 // point stack, but where we prefer to use the value in xmm registers, copy
1245 // it out as F80 and use a truncate to move it from fp stack reg to xmm reg.
1246 if ((VA.getLocReg() == X86::ST0 ||
1247 VA.getLocReg() == X86::ST1) &&
1248 isScalarFPTypeInSSEReg(VA.getValVT())) {
1253 if (Is64Bit && CopyVT.isVector() && CopyVT.getSizeInBits() == 64) {
1254 // For x86-64, MMX values are returned in XMM0 / XMM1 except for v1i64.
1255 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1256 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1257 MVT::v2i64, InFlag).getValue(1);
1258 Val = Chain.getValue(0);
1259 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64,
1260 Val, DAG.getConstant(0, MVT::i64));
1262 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1263 MVT::i64, InFlag).getValue(1);
1264 Val = Chain.getValue(0);
1266 Val = DAG.getNode(ISD::BIT_CONVERT, dl, CopyVT, Val);
1268 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1269 CopyVT, InFlag).getValue(1);
1270 Val = Chain.getValue(0);
1272 InFlag = Chain.getValue(2);
1274 if (CopyVT != VA.getValVT()) {
1275 // Round the F80 the right size, which also moves to the appropriate xmm
1277 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1278 // This truncation won't change the value.
1279 DAG.getIntPtrConstant(1));
1282 InVals.push_back(Val);
1289 //===----------------------------------------------------------------------===//
1290 // C & StdCall & Fast Calling Convention implementation
1291 //===----------------------------------------------------------------------===//
1292 // StdCall calling convention seems to be standard for many Windows' API
1293 // routines and around. It differs from C calling convention just a little:
1294 // callee should clean up the stack, not caller. Symbols should be also
1295 // decorated in some fancy way :) It doesn't support any vector arguments.
1296 // For info on fast calling convention see Fast Calling Convention (tail call)
1297 // implementation LowerX86_32FastCCCallTo.
1299 /// CallIsStructReturn - Determines whether a call uses struct return
1301 static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
1305 return Outs[0].Flags.isSRet();
1308 /// ArgsAreStructReturn - Determines whether a function uses struct
1309 /// return semantics.
1311 ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
1315 return Ins[0].Flags.isSRet();
1318 /// IsCalleePop - Determines whether the callee is required to pop its
1319 /// own arguments. Callee pop is necessary to support tail calls.
1320 bool X86TargetLowering::IsCalleePop(bool IsVarArg, CallingConv::ID CallingConv){
1324 switch (CallingConv) {
1327 case CallingConv::X86_StdCall:
1328 return !Subtarget->is64Bit();
1329 case CallingConv::X86_FastCall:
1330 return !Subtarget->is64Bit();
1331 case CallingConv::Fast:
1332 return PerformTailCallOpt;
1336 /// CCAssignFnForNode - Selects the correct CCAssignFn for a the
1337 /// given CallingConvention value.
1338 CCAssignFn *X86TargetLowering::CCAssignFnForNode(CallingConv::ID CC) const {
1339 if (Subtarget->is64Bit()) {
1340 if (Subtarget->isTargetWin64())
1341 return CC_X86_Win64_C;
1346 if (CC == CallingConv::X86_FastCall)
1347 return CC_X86_32_FastCall;
1348 else if (CC == CallingConv::Fast)
1349 return CC_X86_32_FastCC;
1354 /// NameDecorationForCallConv - Selects the appropriate decoration to
1355 /// apply to a MachineFunction containing a given calling convention.
1357 X86TargetLowering::NameDecorationForCallConv(CallingConv::ID CallConv) {
1358 if (CallConv == CallingConv::X86_FastCall)
1360 else if (CallConv == CallingConv::X86_StdCall)
1366 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1367 /// by "Src" to address "Dst" with size and alignment information specified by
1368 /// the specific parameter attribute. The copy will be passed as a byval
1369 /// function parameter.
1371 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1372 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1374 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1375 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1376 /*AlwaysInline=*/true, NULL, 0, NULL, 0);
1380 X86TargetLowering::LowerMemArgument(SDValue Chain,
1381 CallingConv::ID CallConv,
1382 const SmallVectorImpl<ISD::InputArg> &Ins,
1383 DebugLoc dl, SelectionDAG &DAG,
1384 const CCValAssign &VA,
1385 MachineFrameInfo *MFI,
1388 // Create the nodes corresponding to a load from this parameter slot.
1389 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1390 bool AlwaysUseMutable = (CallConv==CallingConv::Fast) && PerformTailCallOpt;
1391 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1394 // If value is passed by pointer we have address passed instead of the value
1396 if (VA.getLocInfo() == CCValAssign::Indirect)
1397 ValVT = VA.getLocVT();
1399 ValVT = VA.getValVT();
1401 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1402 // changed with more analysis.
1403 // In case of tail call optimization mark all arguments mutable. Since they
1404 // could be overwritten by lowering of arguments in case of a tail call.
1405 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
1406 VA.getLocMemOffset(), isImmutable, false);
1407 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1408 if (Flags.isByVal())
1410 return DAG.getLoad(ValVT, dl, Chain, FIN,
1411 PseudoSourceValue::getFixedStack(FI), 0);
1415 X86TargetLowering::LowerFormalArguments(SDValue Chain,
1416 CallingConv::ID CallConv,
1418 const SmallVectorImpl<ISD::InputArg> &Ins,
1421 SmallVectorImpl<SDValue> &InVals) {
1423 MachineFunction &MF = DAG.getMachineFunction();
1424 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1426 const Function* Fn = MF.getFunction();
1427 if (Fn->hasExternalLinkage() &&
1428 Subtarget->isTargetCygMing() &&
1429 Fn->getName() == "main")
1430 FuncInfo->setForceFramePointer(true);
1432 // Decorate the function name.
1433 FuncInfo->setDecorationStyle(NameDecorationForCallConv(CallConv));
1435 MachineFrameInfo *MFI = MF.getFrameInfo();
1436 bool Is64Bit = Subtarget->is64Bit();
1437 bool IsWin64 = Subtarget->isTargetWin64();
1439 assert(!(isVarArg && CallConv == CallingConv::Fast) &&
1440 "Var args not supported with calling convention fastcc");
1442 // Assign locations to all of the incoming arguments.
1443 SmallVector<CCValAssign, 16> ArgLocs;
1444 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1445 ArgLocs, *DAG.getContext());
1446 CCInfo.AnalyzeFormalArguments(Ins, CCAssignFnForNode(CallConv));
1448 unsigned LastVal = ~0U;
1450 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1451 CCValAssign &VA = ArgLocs[i];
1452 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1454 assert(VA.getValNo() != LastVal &&
1455 "Don't support value assigned to multiple locs yet");
1456 LastVal = VA.getValNo();
1458 if (VA.isRegLoc()) {
1459 EVT RegVT = VA.getLocVT();
1460 TargetRegisterClass *RC = NULL;
1461 if (RegVT == MVT::i32)
1462 RC = X86::GR32RegisterClass;
1463 else if (Is64Bit && RegVT == MVT::i64)
1464 RC = X86::GR64RegisterClass;
1465 else if (RegVT == MVT::f32)
1466 RC = X86::FR32RegisterClass;
1467 else if (RegVT == MVT::f64)
1468 RC = X86::FR64RegisterClass;
1469 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128)
1470 RC = X86::VR128RegisterClass;
1471 else if (RegVT.isVector() && RegVT.getSizeInBits() == 64)
1472 RC = X86::VR64RegisterClass;
1474 llvm_unreachable("Unknown argument type!");
1476 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1477 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1479 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1480 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1482 if (VA.getLocInfo() == CCValAssign::SExt)
1483 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1484 DAG.getValueType(VA.getValVT()));
1485 else if (VA.getLocInfo() == CCValAssign::ZExt)
1486 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1487 DAG.getValueType(VA.getValVT()));
1488 else if (VA.getLocInfo() == CCValAssign::BCvt)
1489 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue);
1491 if (VA.isExtInLoc()) {
1492 // Handle MMX values passed in XMM regs.
1493 if (RegVT.isVector()) {
1494 ArgValue = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64,
1495 ArgValue, DAG.getConstant(0, MVT::i64));
1496 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue);
1498 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1501 assert(VA.isMemLoc());
1502 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
1505 // If value is passed via pointer - do a load.
1506 if (VA.getLocInfo() == CCValAssign::Indirect)
1507 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue, NULL, 0);
1509 InVals.push_back(ArgValue);
1512 // The x86-64 ABI for returning structs by value requires that we copy
1513 // the sret argument into %rax for the return. Save the argument into
1514 // a virtual register so that we can access it from the return points.
1515 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) {
1516 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1517 unsigned Reg = FuncInfo->getSRetReturnReg();
1519 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1520 FuncInfo->setSRetReturnReg(Reg);
1522 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
1523 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
1526 unsigned StackSize = CCInfo.getNextStackOffset();
1527 // align stack specially for tail calls
1528 if (PerformTailCallOpt && CallConv == CallingConv::Fast)
1529 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1531 // If the function takes variable number of arguments, make a frame index for
1532 // the start of the first vararg value... for expansion of llvm.va_start.
1534 if (Is64Bit || CallConv != CallingConv::X86_FastCall) {
1535 VarArgsFrameIndex = MFI->CreateFixedObject(1, StackSize, true, false);
1538 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
1540 // FIXME: We should really autogenerate these arrays
1541 static const unsigned GPR64ArgRegsWin64[] = {
1542 X86::RCX, X86::RDX, X86::R8, X86::R9
1544 static const unsigned XMMArgRegsWin64[] = {
1545 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
1547 static const unsigned GPR64ArgRegs64Bit[] = {
1548 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1550 static const unsigned XMMArgRegs64Bit[] = {
1551 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1552 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1554 const unsigned *GPR64ArgRegs, *XMMArgRegs;
1557 TotalNumIntRegs = 4; TotalNumXMMRegs = 4;
1558 GPR64ArgRegs = GPR64ArgRegsWin64;
1559 XMMArgRegs = XMMArgRegsWin64;
1561 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
1562 GPR64ArgRegs = GPR64ArgRegs64Bit;
1563 XMMArgRegs = XMMArgRegs64Bit;
1565 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
1567 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs,
1570 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat);
1571 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
1572 "SSE register cannot be used when SSE is disabled!");
1573 assert(!(NumXMMRegs && UseSoftFloat && NoImplicitFloatOps) &&
1574 "SSE register cannot be used when SSE is disabled!");
1575 if (UseSoftFloat || NoImplicitFloatOps || !Subtarget->hasSSE1())
1576 // Kernel mode asks for SSE to be disabled, so don't push them
1578 TotalNumXMMRegs = 0;
1580 // For X86-64, if there are vararg parameters that are passed via
1581 // registers, then we must store them to their spots on the stack so they
1582 // may be loaded by deferencing the result of va_next.
1583 VarArgsGPOffset = NumIntRegs * 8;
1584 VarArgsFPOffset = TotalNumIntRegs * 8 + NumXMMRegs * 16;
1585 RegSaveFrameIndex = MFI->CreateStackObject(TotalNumIntRegs * 8 +
1586 TotalNumXMMRegs * 16, 16,
1589 // Store the integer parameter registers.
1590 SmallVector<SDValue, 8> MemOps;
1591 SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
1592 unsigned Offset = VarArgsGPOffset;
1593 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
1594 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
1595 DAG.getIntPtrConstant(Offset));
1596 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
1597 X86::GR64RegisterClass);
1598 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
1600 DAG.getStore(Val.getValue(1), dl, Val, FIN,
1601 PseudoSourceValue::getFixedStack(RegSaveFrameIndex),
1603 MemOps.push_back(Store);
1607 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
1608 // Now store the XMM (fp + vector) parameter registers.
1609 SmallVector<SDValue, 11> SaveXMMOps;
1610 SaveXMMOps.push_back(Chain);
1612 unsigned AL = MF.addLiveIn(X86::AL, X86::GR8RegisterClass);
1613 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
1614 SaveXMMOps.push_back(ALVal);
1616 SaveXMMOps.push_back(DAG.getIntPtrConstant(RegSaveFrameIndex));
1617 SaveXMMOps.push_back(DAG.getIntPtrConstant(VarArgsFPOffset));
1619 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
1620 unsigned VReg = MF.addLiveIn(XMMArgRegs[NumXMMRegs],
1621 X86::VR128RegisterClass);
1622 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
1623 SaveXMMOps.push_back(Val);
1625 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
1627 &SaveXMMOps[0], SaveXMMOps.size()));
1630 if (!MemOps.empty())
1631 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1632 &MemOps[0], MemOps.size());
1636 // Some CCs need callee pop.
1637 if (IsCalleePop(isVarArg, CallConv)) {
1638 BytesToPopOnReturn = StackSize; // Callee pops everything.
1639 BytesCallerReserves = 0;
1641 BytesToPopOnReturn = 0; // Callee pops nothing.
1642 // If this is an sret function, the return should pop the hidden pointer.
1643 if (!Is64Bit && CallConv != CallingConv::Fast && ArgsAreStructReturn(Ins))
1644 BytesToPopOnReturn = 4;
1645 BytesCallerReserves = StackSize;
1649 RegSaveFrameIndex = 0xAAAAAAA; // RegSaveFrameIndex is X86-64 only.
1650 if (CallConv == CallingConv::X86_FastCall)
1651 VarArgsFrameIndex = 0xAAAAAAA; // fastcc functions can't have varargs.
1654 FuncInfo->setBytesToPopOnReturn(BytesToPopOnReturn);
1660 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
1661 SDValue StackPtr, SDValue Arg,
1662 DebugLoc dl, SelectionDAG &DAG,
1663 const CCValAssign &VA,
1664 ISD::ArgFlagsTy Flags) {
1665 const unsigned FirstStackArgOffset = (Subtarget->isTargetWin64() ? 32 : 0);
1666 unsigned LocMemOffset = FirstStackArgOffset + VA.getLocMemOffset();
1667 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1668 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1669 if (Flags.isByVal()) {
1670 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
1672 return DAG.getStore(Chain, dl, Arg, PtrOff,
1673 PseudoSourceValue::getStack(), LocMemOffset);
1676 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
1677 /// optimization is performed and it is required.
1679 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
1680 SDValue &OutRetAddr,
1686 if (!IsTailCall || FPDiff==0) return Chain;
1688 // Adjust the Return address stack slot.
1689 EVT VT = getPointerTy();
1690 OutRetAddr = getReturnAddressFrameIndex(DAG);
1692 // Load the "old" Return address.
1693 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, NULL, 0);
1694 return SDValue(OutRetAddr.getNode(), 1);
1697 /// EmitTailCallStoreRetAddr - Emit a store of the return adress if tail call
1698 /// optimization is performed and it is required (FPDiff!=0).
1700 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
1701 SDValue Chain, SDValue RetAddrFrIdx,
1702 bool Is64Bit, int FPDiff, DebugLoc dl) {
1703 // Store the return address to the appropriate stack slot.
1704 if (!FPDiff) return Chain;
1705 // Calculate the new stack slot for the return address.
1706 int SlotSize = Is64Bit ? 8 : 4;
1707 int NewReturnAddrFI =
1708 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize,
1710 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
1711 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
1712 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
1713 PseudoSourceValue::getFixedStack(NewReturnAddrFI), 0);
1718 X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
1719 CallingConv::ID CallConv, bool isVarArg,
1721 const SmallVectorImpl<ISD::OutputArg> &Outs,
1722 const SmallVectorImpl<ISD::InputArg> &Ins,
1723 DebugLoc dl, SelectionDAG &DAG,
1724 SmallVectorImpl<SDValue> &InVals) {
1726 MachineFunction &MF = DAG.getMachineFunction();
1727 bool Is64Bit = Subtarget->is64Bit();
1728 bool IsStructRet = CallIsStructReturn(Outs);
1730 assert((!isTailCall ||
1731 (CallConv == CallingConv::Fast && PerformTailCallOpt)) &&
1732 "IsEligibleForTailCallOptimization missed a case!");
1733 assert(!(isVarArg && CallConv == CallingConv::Fast) &&
1734 "Var args not supported with calling convention fastcc");
1736 // Analyze operands of the call, assigning locations to each operand.
1737 SmallVector<CCValAssign, 16> ArgLocs;
1738 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1739 ArgLocs, *DAG.getContext());
1740 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForNode(CallConv));
1742 // Get a count of how many bytes are to be pushed on the stack.
1743 unsigned NumBytes = CCInfo.getNextStackOffset();
1744 if (PerformTailCallOpt && CallConv == CallingConv::Fast)
1745 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
1749 // Lower arguments at fp - stackoffset + fpdiff.
1750 unsigned NumBytesCallerPushed =
1751 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
1752 FPDiff = NumBytesCallerPushed - NumBytes;
1754 // Set the delta of movement of the returnaddr stackslot.
1755 // But only set if delta is greater than previous delta.
1756 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
1757 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
1760 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
1762 SDValue RetAddrFrIdx;
1763 // Load return adress for tail calls.
1764 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall, Is64Bit,
1767 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
1768 SmallVector<SDValue, 8> MemOpChains;
1771 // Walk the register/memloc assignments, inserting copies/loads. In the case
1772 // of tail call optimization arguments are handle later.
1773 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1774 CCValAssign &VA = ArgLocs[i];
1775 EVT RegVT = VA.getLocVT();
1776 SDValue Arg = Outs[i].Val;
1777 ISD::ArgFlagsTy Flags = Outs[i].Flags;
1778 bool isByVal = Flags.isByVal();
1780 // Promote the value if needed.
1781 switch (VA.getLocInfo()) {
1782 default: llvm_unreachable("Unknown loc info!");
1783 case CCValAssign::Full: break;
1784 case CCValAssign::SExt:
1785 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
1787 case CCValAssign::ZExt:
1788 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
1790 case CCValAssign::AExt:
1791 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) {
1792 // Special case: passing MMX values in XMM registers.
1793 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, Arg);
1794 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
1795 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
1797 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
1799 case CCValAssign::BCvt:
1800 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, RegVT, Arg);
1802 case CCValAssign::Indirect: {
1803 // Store the argument.
1804 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
1805 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
1806 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
1807 PseudoSourceValue::getFixedStack(FI), 0);
1813 if (VA.isRegLoc()) {
1814 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1816 if (!isTailCall || (isTailCall && isByVal)) {
1817 assert(VA.isMemLoc());
1818 if (StackPtr.getNode() == 0)
1819 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy());
1821 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
1822 dl, DAG, VA, Flags));
1827 if (!MemOpChains.empty())
1828 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1829 &MemOpChains[0], MemOpChains.size());
1831 // Build a sequence of copy-to-reg nodes chained together with token chain
1832 // and flag operands which copy the outgoing args into registers.
1834 // Tail call byval lowering might overwrite argument registers so in case of
1835 // tail call optimization the copies to registers are lowered later.
1837 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1838 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1839 RegsToPass[i].second, InFlag);
1840 InFlag = Chain.getValue(1);
1844 if (Subtarget->isPICStyleGOT()) {
1845 // ELF / PIC requires GOT in the EBX register before function calls via PLT
1848 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX,
1849 DAG.getNode(X86ISD::GlobalBaseReg,
1850 DebugLoc::getUnknownLoc(),
1853 InFlag = Chain.getValue(1);
1855 // If we are tail calling and generating PIC/GOT style code load the
1856 // address of the callee into ECX. The value in ecx is used as target of
1857 // the tail jump. This is done to circumvent the ebx/callee-saved problem
1858 // for tail calls on PIC/GOT architectures. Normally we would just put the
1859 // address of GOT into ebx and then call target@PLT. But for tail calls
1860 // ebx would be restored (since ebx is callee saved) before jumping to the
1863 // Note: The actual moving to ECX is done further down.
1864 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
1865 if (G && !G->getGlobal()->hasHiddenVisibility() &&
1866 !G->getGlobal()->hasProtectedVisibility())
1867 Callee = LowerGlobalAddress(Callee, DAG);
1868 else if (isa<ExternalSymbolSDNode>(Callee))
1869 Callee = LowerExternalSymbol(Callee, DAG);
1873 if (Is64Bit && isVarArg) {
1874 // From AMD64 ABI document:
1875 // For calls that may call functions that use varargs or stdargs
1876 // (prototype-less calls or calls to functions containing ellipsis (...) in
1877 // the declaration) %al is used as hidden argument to specify the number
1878 // of SSE registers used. The contents of %al do not need to match exactly
1879 // the number of registers, but must be an ubound on the number of SSE
1880 // registers used and is in the range 0 - 8 inclusive.
1882 // FIXME: Verify this on Win64
1883 // Count the number of XMM registers allocated.
1884 static const unsigned XMMArgRegs[] = {
1885 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1886 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1888 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
1889 assert((Subtarget->hasSSE1() || !NumXMMRegs)
1890 && "SSE registers cannot be used when SSE is disabled");
1892 Chain = DAG.getCopyToReg(Chain, dl, X86::AL,
1893 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
1894 InFlag = Chain.getValue(1);
1898 // For tail calls lower the arguments to the 'real' stack slot.
1900 // Force all the incoming stack arguments to be loaded from the stack
1901 // before any new outgoing arguments are stored to the stack, because the
1902 // outgoing stack slots may alias the incoming argument stack slots, and
1903 // the alias isn't otherwise explicit. This is slightly more conservative
1904 // than necessary, because it means that each store effectively depends
1905 // on every argument instead of just those arguments it would clobber.
1906 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
1908 SmallVector<SDValue, 8> MemOpChains2;
1911 // Do not flag preceeding copytoreg stuff together with the following stuff.
1913 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1914 CCValAssign &VA = ArgLocs[i];
1915 if (!VA.isRegLoc()) {
1916 assert(VA.isMemLoc());
1917 SDValue Arg = Outs[i].Val;
1918 ISD::ArgFlagsTy Flags = Outs[i].Flags;
1919 // Create frame index.
1920 int32_t Offset = VA.getLocMemOffset()+FPDiff;
1921 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
1922 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true, false);
1923 FIN = DAG.getFrameIndex(FI, getPointerTy());
1925 if (Flags.isByVal()) {
1926 // Copy relative to framepointer.
1927 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
1928 if (StackPtr.getNode() == 0)
1929 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr,
1931 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
1933 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
1937 // Store relative to framepointer.
1938 MemOpChains2.push_back(
1939 DAG.getStore(ArgChain, dl, Arg, FIN,
1940 PseudoSourceValue::getFixedStack(FI), 0));
1945 if (!MemOpChains2.empty())
1946 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1947 &MemOpChains2[0], MemOpChains2.size());
1949 // Copy arguments to their registers.
1950 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1951 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1952 RegsToPass[i].second, InFlag);
1953 InFlag = Chain.getValue(1);
1957 // Store the return address to the appropriate stack slot.
1958 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
1962 bool WasGlobalOrExternal = false;
1963 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
1964 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
1965 // In the 64-bit large code model, we have to make all calls
1966 // through a register, since the call instruction's 32-bit
1967 // pc-relative offset may not be large enough to hold the whole
1969 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1970 WasGlobalOrExternal = true;
1971 // If the callee is a GlobalAddress node (quite common, every direct call
1972 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
1975 // We should use extra load for direct calls to dllimported functions in
1977 GlobalValue *GV = G->getGlobal();
1978 if (!GV->hasDLLImportLinkage()) {
1979 unsigned char OpFlags = 0;
1981 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
1982 // external symbols most go through the PLT in PIC mode. If the symbol
1983 // has hidden or protected visibility, or if it is static or local, then
1984 // we don't need to use the PLT - we can directly call it.
1985 if (Subtarget->isTargetELF() &&
1986 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1987 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
1988 OpFlags = X86II::MO_PLT;
1989 } else if (Subtarget->isPICStyleStubAny() &&
1990 (GV->isDeclaration() || GV->isWeakForLinker()) &&
1991 Subtarget->getDarwinVers() < 9) {
1992 // PC-relative references to external symbols should go through $stub,
1993 // unless we're building with the leopard linker or later, which
1994 // automatically synthesizes these stubs.
1995 OpFlags = X86II::MO_DARWIN_STUB;
1998 Callee = DAG.getTargetGlobalAddress(GV, getPointerTy(),
1999 G->getOffset(), OpFlags);
2001 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2002 WasGlobalOrExternal = true;
2003 unsigned char OpFlags = 0;
2005 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to external
2006 // symbols should go through the PLT.
2007 if (Subtarget->isTargetELF() &&
2008 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2009 OpFlags = X86II::MO_PLT;
2010 } else if (Subtarget->isPICStyleStubAny() &&
2011 Subtarget->getDarwinVers() < 9) {
2012 // PC-relative references to external symbols should go through $stub,
2013 // unless we're building with the leopard linker or later, which
2014 // automatically synthesizes these stubs.
2015 OpFlags = X86II::MO_DARWIN_STUB;
2018 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2022 if (isTailCall && !WasGlobalOrExternal) {
2023 unsigned Opc = Is64Bit ? X86::R11 : X86::EAX;
2025 Chain = DAG.getCopyToReg(Chain, dl,
2026 DAG.getRegister(Opc, getPointerTy()),
2028 Callee = DAG.getRegister(Opc, getPointerTy());
2029 // Add register as live out.
2030 MF.getRegInfo().addLiveOut(Opc);
2033 // Returns a chain & a flag for retval copy to use.
2034 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
2035 SmallVector<SDValue, 8> Ops;
2038 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2039 DAG.getIntPtrConstant(0, true), InFlag);
2040 InFlag = Chain.getValue(1);
2043 Ops.push_back(Chain);
2044 Ops.push_back(Callee);
2047 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2049 // Add argument registers to the end of the list so that they are known live
2051 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2052 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2053 RegsToPass[i].second.getValueType()));
2055 // Add an implicit use GOT pointer in EBX.
2056 if (!isTailCall && Subtarget->isPICStyleGOT())
2057 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
2059 // Add an implicit use of AL for x86 vararg functions.
2060 if (Is64Bit && isVarArg)
2061 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
2063 if (InFlag.getNode())
2064 Ops.push_back(InFlag);
2067 // If this is the first return lowered for this function, add the regs
2068 // to the liveout set for the function.
2069 if (MF.getRegInfo().liveout_empty()) {
2070 SmallVector<CCValAssign, 16> RVLocs;
2071 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs,
2073 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2074 for (unsigned i = 0; i != RVLocs.size(); ++i)
2075 if (RVLocs[i].isRegLoc())
2076 MF.getRegInfo().addLiveOut(RVLocs[i].getLocReg());
2079 assert(((Callee.getOpcode() == ISD::Register &&
2080 (cast<RegisterSDNode>(Callee)->getReg() == X86::EAX ||
2081 cast<RegisterSDNode>(Callee)->getReg() == X86::R9)) ||
2082 Callee.getOpcode() == ISD::TargetExternalSymbol ||
2083 Callee.getOpcode() == ISD::TargetGlobalAddress) &&
2084 "Expecting an global address, external symbol, or register");
2086 return DAG.getNode(X86ISD::TC_RETURN, dl,
2087 NodeTys, &Ops[0], Ops.size());
2090 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2091 InFlag = Chain.getValue(1);
2093 // Create the CALLSEQ_END node.
2094 unsigned NumBytesForCalleeToPush;
2095 if (IsCalleePop(isVarArg, CallConv))
2096 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2097 else if (!Is64Bit && CallConv != CallingConv::Fast && IsStructRet)
2098 // If this is is a call to a struct-return function, the callee
2099 // pops the hidden struct pointer, so we have to push it back.
2100 // This is common for Darwin/X86, Linux & Mingw32 targets.
2101 NumBytesForCalleeToPush = 4;
2103 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2105 // Returns a flag for retval copy to use.
2106 Chain = DAG.getCALLSEQ_END(Chain,
2107 DAG.getIntPtrConstant(NumBytes, true),
2108 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2111 InFlag = Chain.getValue(1);
2113 // Handle result values, copying them out of physregs into vregs that we
2115 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2116 Ins, dl, DAG, InVals);
2120 //===----------------------------------------------------------------------===//
2121 // Fast Calling Convention (tail call) implementation
2122 //===----------------------------------------------------------------------===//
2124 // Like std call, callee cleans arguments, convention except that ECX is
2125 // reserved for storing the tail called function address. Only 2 registers are
2126 // free for argument passing (inreg). Tail call optimization is performed
2128 // * tailcallopt is enabled
2129 // * caller/callee are fastcc
2130 // On X86_64 architecture with GOT-style position independent code only local
2131 // (within module) calls are supported at the moment.
2132 // To keep the stack aligned according to platform abi the function
2133 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2134 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2135 // If a tail called function callee has more arguments than the caller the
2136 // caller needs to make sure that there is room to move the RETADDR to. This is
2137 // achieved by reserving an area the size of the argument delta right after the
2138 // original REtADDR, but before the saved framepointer or the spilled registers
2139 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2151 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2152 /// for a 16 byte align requirement.
2153 unsigned X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2154 SelectionDAG& DAG) {
2155 MachineFunction &MF = DAG.getMachineFunction();
2156 const TargetMachine &TM = MF.getTarget();
2157 const TargetFrameInfo &TFI = *TM.getFrameInfo();
2158 unsigned StackAlignment = TFI.getStackAlignment();
2159 uint64_t AlignMask = StackAlignment - 1;
2160 int64_t Offset = StackSize;
2161 uint64_t SlotSize = TD->getPointerSize();
2162 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2163 // Number smaller than 12 so just add the difference.
2164 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2166 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2167 Offset = ((~AlignMask) & Offset) + StackAlignment +
2168 (StackAlignment-SlotSize);
2173 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2174 /// for tail call optimization. Targets which want to do tail call
2175 /// optimization should implement this function.
2177 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2178 CallingConv::ID CalleeCC,
2180 const SmallVectorImpl<ISD::InputArg> &Ins,
2181 SelectionDAG& DAG) const {
2182 MachineFunction &MF = DAG.getMachineFunction();
2183 CallingConv::ID CallerCC = MF.getFunction()->getCallingConv();
2184 return CalleeCC == CallingConv::Fast && CallerCC == CalleeCC;
2188 X86TargetLowering::createFastISel(MachineFunction &mf,
2189 MachineModuleInfo *mmo,
2191 DenseMap<const Value *, unsigned> &vm,
2192 DenseMap<const BasicBlock *,
2193 MachineBasicBlock *> &bm,
2194 DenseMap<const AllocaInst *, int> &am
2196 , SmallSet<Instruction*, 8> &cil
2199 return X86::createFastISel(mf, mmo, dw, vm, bm, am
2207 //===----------------------------------------------------------------------===//
2208 // Other Lowering Hooks
2209 //===----------------------------------------------------------------------===//
2212 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) {
2213 MachineFunction &MF = DAG.getMachineFunction();
2214 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2215 int ReturnAddrIndex = FuncInfo->getRAIndex();
2217 if (ReturnAddrIndex == 0) {
2218 // Set up a frame object for the return address.
2219 uint64_t SlotSize = TD->getPointerSize();
2220 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
2222 FuncInfo->setRAIndex(ReturnAddrIndex);
2225 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
2229 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
2230 bool hasSymbolicDisplacement) {
2231 // Offset should fit into 32 bit immediate field.
2232 if (!isInt32(Offset))
2235 // If we don't have a symbolic displacement - we don't have any extra
2237 if (!hasSymbolicDisplacement)
2240 // FIXME: Some tweaks might be needed for medium code model.
2241 if (M != CodeModel::Small && M != CodeModel::Kernel)
2244 // For small code model we assume that latest object is 16MB before end of 31
2245 // bits boundary. We may also accept pretty large negative constants knowing
2246 // that all objects are in the positive half of address space.
2247 if (M == CodeModel::Small && Offset < 16*1024*1024)
2250 // For kernel code model we know that all object resist in the negative half
2251 // of 32bits address space. We may not accept negative offsets, since they may
2252 // be just off and we may accept pretty large positive ones.
2253 if (M == CodeModel::Kernel && Offset > 0)
2259 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
2260 /// specific condition code, returning the condition code and the LHS/RHS of the
2261 /// comparison to make.
2262 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
2263 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
2265 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
2266 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
2267 // X > -1 -> X == 0, jump !sign.
2268 RHS = DAG.getConstant(0, RHS.getValueType());
2269 return X86::COND_NS;
2270 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
2271 // X < 0 -> X == 0, jump on sign.
2273 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
2275 RHS = DAG.getConstant(0, RHS.getValueType());
2276 return X86::COND_LE;
2280 switch (SetCCOpcode) {
2281 default: llvm_unreachable("Invalid integer condition!");
2282 case ISD::SETEQ: return X86::COND_E;
2283 case ISD::SETGT: return X86::COND_G;
2284 case ISD::SETGE: return X86::COND_GE;
2285 case ISD::SETLT: return X86::COND_L;
2286 case ISD::SETLE: return X86::COND_LE;
2287 case ISD::SETNE: return X86::COND_NE;
2288 case ISD::SETULT: return X86::COND_B;
2289 case ISD::SETUGT: return X86::COND_A;
2290 case ISD::SETULE: return X86::COND_BE;
2291 case ISD::SETUGE: return X86::COND_AE;
2295 // First determine if it is required or is profitable to flip the operands.
2297 // If LHS is a foldable load, but RHS is not, flip the condition.
2298 if ((ISD::isNON_EXTLoad(LHS.getNode()) && LHS.hasOneUse()) &&
2299 !(ISD::isNON_EXTLoad(RHS.getNode()) && RHS.hasOneUse())) {
2300 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
2301 std::swap(LHS, RHS);
2304 switch (SetCCOpcode) {
2310 std::swap(LHS, RHS);
2314 // On a floating point condition, the flags are set as follows:
2316 // 0 | 0 | 0 | X > Y
2317 // 0 | 0 | 1 | X < Y
2318 // 1 | 0 | 0 | X == Y
2319 // 1 | 1 | 1 | unordered
2320 switch (SetCCOpcode) {
2321 default: llvm_unreachable("Condcode should be pre-legalized away");
2323 case ISD::SETEQ: return X86::COND_E;
2324 case ISD::SETOLT: // flipped
2326 case ISD::SETGT: return X86::COND_A;
2327 case ISD::SETOLE: // flipped
2329 case ISD::SETGE: return X86::COND_AE;
2330 case ISD::SETUGT: // flipped
2332 case ISD::SETLT: return X86::COND_B;
2333 case ISD::SETUGE: // flipped
2335 case ISD::SETLE: return X86::COND_BE;
2337 case ISD::SETNE: return X86::COND_NE;
2338 case ISD::SETUO: return X86::COND_P;
2339 case ISD::SETO: return X86::COND_NP;
2341 case ISD::SETUNE: return X86::COND_INVALID;
2345 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
2346 /// code. Current x86 isa includes the following FP cmov instructions:
2347 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
2348 static bool hasFPCMov(unsigned X86CC) {
2364 /// isFPImmLegal - Returns true if the target can instruction select the
2365 /// specified FP immediate natively. If false, the legalizer will
2366 /// materialize the FP immediate as a load from a constant pool.
2367 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
2368 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
2369 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
2375 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
2376 /// the specified range (L, H].
2377 static bool isUndefOrInRange(int Val, int Low, int Hi) {
2378 return (Val < 0) || (Val >= Low && Val < Hi);
2381 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
2382 /// specified value.
2383 static bool isUndefOrEqual(int Val, int CmpVal) {
2384 if (Val < 0 || Val == CmpVal)
2389 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
2390 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
2391 /// the second operand.
2392 static bool isPSHUFDMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2393 if (VT == MVT::v4f32 || VT == MVT::v4i32 || VT == MVT::v4i16)
2394 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
2395 if (VT == MVT::v2f64 || VT == MVT::v2i64)
2396 return (Mask[0] < 2 && Mask[1] < 2);
2400 bool X86::isPSHUFDMask(ShuffleVectorSDNode *N) {
2401 SmallVector<int, 8> M;
2403 return ::isPSHUFDMask(M, N->getValueType(0));
2406 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
2407 /// is suitable for input to PSHUFHW.
2408 static bool isPSHUFHWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2409 if (VT != MVT::v8i16)
2412 // Lower quadword copied in order or undef.
2413 for (int i = 0; i != 4; ++i)
2414 if (Mask[i] >= 0 && Mask[i] != i)
2417 // Upper quadword shuffled.
2418 for (int i = 4; i != 8; ++i)
2419 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7))
2425 bool X86::isPSHUFHWMask(ShuffleVectorSDNode *N) {
2426 SmallVector<int, 8> M;
2428 return ::isPSHUFHWMask(M, N->getValueType(0));
2431 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
2432 /// is suitable for input to PSHUFLW.
2433 static bool isPSHUFLWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2434 if (VT != MVT::v8i16)
2437 // Upper quadword copied in order.
2438 for (int i = 4; i != 8; ++i)
2439 if (Mask[i] >= 0 && Mask[i] != i)
2442 // Lower quadword shuffled.
2443 for (int i = 0; i != 4; ++i)
2450 bool X86::isPSHUFLWMask(ShuffleVectorSDNode *N) {
2451 SmallVector<int, 8> M;
2453 return ::isPSHUFLWMask(M, N->getValueType(0));
2456 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
2457 /// is suitable for input to PALIGNR.
2458 static bool isPALIGNRMask(const SmallVectorImpl<int> &Mask, EVT VT,
2460 int i, e = VT.getVectorNumElements();
2462 // Do not handle v2i64 / v2f64 shuffles with palignr.
2463 if (e < 4 || !hasSSSE3)
2466 for (i = 0; i != e; ++i)
2470 // All undef, not a palignr.
2474 // Determine if it's ok to perform a palignr with only the LHS, since we
2475 // don't have access to the actual shuffle elements to see if RHS is undef.
2476 bool Unary = Mask[i] < (int)e;
2477 bool NeedsUnary = false;
2479 int s = Mask[i] - i;
2481 // Check the rest of the elements to see if they are consecutive.
2482 for (++i; i != e; ++i) {
2487 Unary = Unary && (m < (int)e);
2488 NeedsUnary = NeedsUnary || (m < s);
2490 if (NeedsUnary && !Unary)
2492 if (Unary && m != ((s+i) & (e-1)))
2494 if (!Unary && m != (s+i))
2500 bool X86::isPALIGNRMask(ShuffleVectorSDNode *N) {
2501 SmallVector<int, 8> M;
2503 return ::isPALIGNRMask(M, N->getValueType(0), true);
2506 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
2507 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
2508 static bool isSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2509 int NumElems = VT.getVectorNumElements();
2510 if (NumElems != 2 && NumElems != 4)
2513 int Half = NumElems / 2;
2514 for (int i = 0; i < Half; ++i)
2515 if (!isUndefOrInRange(Mask[i], 0, NumElems))
2517 for (int i = Half; i < NumElems; ++i)
2518 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
2524 bool X86::isSHUFPMask(ShuffleVectorSDNode *N) {
2525 SmallVector<int, 8> M;
2527 return ::isSHUFPMask(M, N->getValueType(0));
2530 /// isCommutedSHUFP - Returns true if the shuffle mask is exactly
2531 /// the reverse of what x86 shuffles want. x86 shuffles requires the lower
2532 /// half elements to come from vector 1 (which would equal the dest.) and
2533 /// the upper half to come from vector 2.
2534 static bool isCommutedSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2535 int NumElems = VT.getVectorNumElements();
2537 if (NumElems != 2 && NumElems != 4)
2540 int Half = NumElems / 2;
2541 for (int i = 0; i < Half; ++i)
2542 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
2544 for (int i = Half; i < NumElems; ++i)
2545 if (!isUndefOrInRange(Mask[i], 0, NumElems))
2550 static bool isCommutedSHUFP(ShuffleVectorSDNode *N) {
2551 SmallVector<int, 8> M;
2553 return isCommutedSHUFPMask(M, N->getValueType(0));
2556 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
2557 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
2558 bool X86::isMOVHLPSMask(ShuffleVectorSDNode *N) {
2559 if (N->getValueType(0).getVectorNumElements() != 4)
2562 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
2563 return isUndefOrEqual(N->getMaskElt(0), 6) &&
2564 isUndefOrEqual(N->getMaskElt(1), 7) &&
2565 isUndefOrEqual(N->getMaskElt(2), 2) &&
2566 isUndefOrEqual(N->getMaskElt(3), 3);
2569 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
2570 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
2572 bool X86::isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N) {
2573 unsigned NumElems = N->getValueType(0).getVectorNumElements();
2578 return isUndefOrEqual(N->getMaskElt(0), 2) &&
2579 isUndefOrEqual(N->getMaskElt(1), 3) &&
2580 isUndefOrEqual(N->getMaskElt(2), 2) &&
2581 isUndefOrEqual(N->getMaskElt(3), 3);
2584 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
2585 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
2586 bool X86::isMOVLPMask(ShuffleVectorSDNode *N) {
2587 unsigned NumElems = N->getValueType(0).getVectorNumElements();
2589 if (NumElems != 2 && NumElems != 4)
2592 for (unsigned i = 0; i < NumElems/2; ++i)
2593 if (!isUndefOrEqual(N->getMaskElt(i), i + NumElems))
2596 for (unsigned i = NumElems/2; i < NumElems; ++i)
2597 if (!isUndefOrEqual(N->getMaskElt(i), i))
2603 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
2604 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
2605 bool X86::isMOVLHPSMask(ShuffleVectorSDNode *N) {
2606 unsigned NumElems = N->getValueType(0).getVectorNumElements();
2608 if (NumElems != 2 && NumElems != 4)
2611 for (unsigned i = 0; i < NumElems/2; ++i)
2612 if (!isUndefOrEqual(N->getMaskElt(i), i))
2615 for (unsigned i = 0; i < NumElems/2; ++i)
2616 if (!isUndefOrEqual(N->getMaskElt(i + NumElems/2), i + NumElems))
2622 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
2623 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
2624 static bool isUNPCKLMask(const SmallVectorImpl<int> &Mask, EVT VT,
2625 bool V2IsSplat = false) {
2626 int NumElts = VT.getVectorNumElements();
2627 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
2630 for (int i = 0, j = 0; i != NumElts; i += 2, ++j) {
2632 int BitI1 = Mask[i+1];
2633 if (!isUndefOrEqual(BitI, j))
2636 if (!isUndefOrEqual(BitI1, NumElts))
2639 if (!isUndefOrEqual(BitI1, j + NumElts))
2646 bool X86::isUNPCKLMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
2647 SmallVector<int, 8> M;
2649 return ::isUNPCKLMask(M, N->getValueType(0), V2IsSplat);
2652 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
2653 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
2654 static bool isUNPCKHMask(const SmallVectorImpl<int> &Mask, EVT VT,
2655 bool V2IsSplat = false) {
2656 int NumElts = VT.getVectorNumElements();
2657 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
2660 for (int i = 0, j = 0; i != NumElts; i += 2, ++j) {
2662 int BitI1 = Mask[i+1];
2663 if (!isUndefOrEqual(BitI, j + NumElts/2))
2666 if (isUndefOrEqual(BitI1, NumElts))
2669 if (!isUndefOrEqual(BitI1, j + NumElts/2 + NumElts))
2676 bool X86::isUNPCKHMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
2677 SmallVector<int, 8> M;
2679 return ::isUNPCKHMask(M, N->getValueType(0), V2IsSplat);
2682 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
2683 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
2685 static bool isUNPCKL_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) {
2686 int NumElems = VT.getVectorNumElements();
2687 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
2690 for (int i = 0, j = 0; i != NumElems; i += 2, ++j) {
2692 int BitI1 = Mask[i+1];
2693 if (!isUndefOrEqual(BitI, j))
2695 if (!isUndefOrEqual(BitI1, j))
2701 bool X86::isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N) {
2702 SmallVector<int, 8> M;
2704 return ::isUNPCKL_v_undef_Mask(M, N->getValueType(0));
2707 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
2708 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
2710 static bool isUNPCKH_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) {
2711 int NumElems = VT.getVectorNumElements();
2712 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
2715 for (int i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) {
2717 int BitI1 = Mask[i+1];
2718 if (!isUndefOrEqual(BitI, j))
2720 if (!isUndefOrEqual(BitI1, j))
2726 bool X86::isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N) {
2727 SmallVector<int, 8> M;
2729 return ::isUNPCKH_v_undef_Mask(M, N->getValueType(0));
2732 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
2733 /// specifies a shuffle of elements that is suitable for input to MOVSS,
2734 /// MOVSD, and MOVD, i.e. setting the lowest element.
2735 static bool isMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2736 if (VT.getVectorElementType().getSizeInBits() < 32)
2739 int NumElts = VT.getVectorNumElements();
2741 if (!isUndefOrEqual(Mask[0], NumElts))
2744 for (int i = 1; i < NumElts; ++i)
2745 if (!isUndefOrEqual(Mask[i], i))
2751 bool X86::isMOVLMask(ShuffleVectorSDNode *N) {
2752 SmallVector<int, 8> M;
2754 return ::isMOVLMask(M, N->getValueType(0));
2757 /// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
2758 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
2759 /// element of vector 2 and the other elements to come from vector 1 in order.
2760 static bool isCommutedMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT,
2761 bool V2IsSplat = false, bool V2IsUndef = false) {
2762 int NumOps = VT.getVectorNumElements();
2763 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
2766 if (!isUndefOrEqual(Mask[0], 0))
2769 for (int i = 1; i < NumOps; ++i)
2770 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
2771 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
2772 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
2778 static bool isCommutedMOVL(ShuffleVectorSDNode *N, bool V2IsSplat = false,
2779 bool V2IsUndef = false) {
2780 SmallVector<int, 8> M;
2782 return isCommutedMOVLMask(M, N->getValueType(0), V2IsSplat, V2IsUndef);
2785 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2786 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
2787 bool X86::isMOVSHDUPMask(ShuffleVectorSDNode *N) {
2788 if (N->getValueType(0).getVectorNumElements() != 4)
2791 // Expect 1, 1, 3, 3
2792 for (unsigned i = 0; i < 2; ++i) {
2793 int Elt = N->getMaskElt(i);
2794 if (Elt >= 0 && Elt != 1)
2799 for (unsigned i = 2; i < 4; ++i) {
2800 int Elt = N->getMaskElt(i);
2801 if (Elt >= 0 && Elt != 3)
2806 // Don't use movshdup if it can be done with a shufps.
2807 // FIXME: verify that matching u, u, 3, 3 is what we want.
2811 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2812 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
2813 bool X86::isMOVSLDUPMask(ShuffleVectorSDNode *N) {
2814 if (N->getValueType(0).getVectorNumElements() != 4)
2817 // Expect 0, 0, 2, 2
2818 for (unsigned i = 0; i < 2; ++i)
2819 if (N->getMaskElt(i) > 0)
2823 for (unsigned i = 2; i < 4; ++i) {
2824 int Elt = N->getMaskElt(i);
2825 if (Elt >= 0 && Elt != 2)
2830 // Don't use movsldup if it can be done with a shufps.
2834 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2835 /// specifies a shuffle of elements that is suitable for input to MOVDDUP.
2836 bool X86::isMOVDDUPMask(ShuffleVectorSDNode *N) {
2837 int e = N->getValueType(0).getVectorNumElements() / 2;
2839 for (int i = 0; i < e; ++i)
2840 if (!isUndefOrEqual(N->getMaskElt(i), i))
2842 for (int i = 0; i < e; ++i)
2843 if (!isUndefOrEqual(N->getMaskElt(e+i), i))
2848 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
2849 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
2850 unsigned X86::getShuffleSHUFImmediate(SDNode *N) {
2851 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
2852 int NumOperands = SVOp->getValueType(0).getVectorNumElements();
2854 unsigned Shift = (NumOperands == 4) ? 2 : 1;
2856 for (int i = 0; i < NumOperands; ++i) {
2857 int Val = SVOp->getMaskElt(NumOperands-i-1);
2858 if (Val < 0) Val = 0;
2859 if (Val >= NumOperands) Val -= NumOperands;
2861 if (i != NumOperands - 1)
2867 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
2868 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
2869 unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
2870 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
2872 // 8 nodes, but we only care about the last 4.
2873 for (unsigned i = 7; i >= 4; --i) {
2874 int Val = SVOp->getMaskElt(i);
2883 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
2884 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
2885 unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
2886 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
2888 // 8 nodes, but we only care about the first 4.
2889 for (int i = 3; i >= 0; --i) {
2890 int Val = SVOp->getMaskElt(i);
2899 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
2900 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
2901 unsigned X86::getShufflePALIGNRImmediate(SDNode *N) {
2902 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
2903 EVT VVT = N->getValueType(0);
2904 unsigned EltSize = VVT.getVectorElementType().getSizeInBits() >> 3;
2908 for (i = 0, e = VVT.getVectorNumElements(); i != e; ++i) {
2909 Val = SVOp->getMaskElt(i);
2913 return (Val - i) * EltSize;
2916 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
2918 bool X86::isZeroNode(SDValue Elt) {
2919 return ((isa<ConstantSDNode>(Elt) &&
2920 cast<ConstantSDNode>(Elt)->getZExtValue() == 0) ||
2921 (isa<ConstantFPSDNode>(Elt) &&
2922 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
2925 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
2926 /// their permute mask.
2927 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
2928 SelectionDAG &DAG) {
2929 EVT VT = SVOp->getValueType(0);
2930 unsigned NumElems = VT.getVectorNumElements();
2931 SmallVector<int, 8> MaskVec;
2933 for (unsigned i = 0; i != NumElems; ++i) {
2934 int idx = SVOp->getMaskElt(i);
2936 MaskVec.push_back(idx);
2937 else if (idx < (int)NumElems)
2938 MaskVec.push_back(idx + NumElems);
2940 MaskVec.push_back(idx - NumElems);
2942 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1),
2943 SVOp->getOperand(0), &MaskVec[0]);
2946 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
2947 /// the two vector operands have swapped position.
2948 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, EVT VT) {
2949 unsigned NumElems = VT.getVectorNumElements();
2950 for (unsigned i = 0; i != NumElems; ++i) {
2954 else if (idx < (int)NumElems)
2955 Mask[i] = idx + NumElems;
2957 Mask[i] = idx - NumElems;
2961 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
2962 /// match movhlps. The lower half elements should come from upper half of
2963 /// V1 (and in order), and the upper half elements should come from the upper
2964 /// half of V2 (and in order).
2965 static bool ShouldXformToMOVHLPS(ShuffleVectorSDNode *Op) {
2966 if (Op->getValueType(0).getVectorNumElements() != 4)
2968 for (unsigned i = 0, e = 2; i != e; ++i)
2969 if (!isUndefOrEqual(Op->getMaskElt(i), i+2))
2971 for (unsigned i = 2; i != 4; ++i)
2972 if (!isUndefOrEqual(Op->getMaskElt(i), i+4))
2977 /// isScalarLoadToVector - Returns true if the node is a scalar load that
2978 /// is promoted to a vector. It also returns the LoadSDNode by reference if
2980 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
2981 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
2983 N = N->getOperand(0).getNode();
2984 if (!ISD::isNON_EXTLoad(N))
2987 *LD = cast<LoadSDNode>(N);
2991 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
2992 /// match movlp{s|d}. The lower half elements should come from lower half of
2993 /// V1 (and in order), and the upper half elements should come from the upper
2994 /// half of V2 (and in order). And since V1 will become the source of the
2995 /// MOVLP, it must be either a vector load or a scalar load to vector.
2996 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
2997 ShuffleVectorSDNode *Op) {
2998 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
3000 // Is V2 is a vector load, don't do this transformation. We will try to use
3001 // load folding shufps op.
3002 if (ISD::isNON_EXTLoad(V2))
3005 unsigned NumElems = Op->getValueType(0).getVectorNumElements();
3007 if (NumElems != 2 && NumElems != 4)
3009 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3010 if (!isUndefOrEqual(Op->getMaskElt(i), i))
3012 for (unsigned i = NumElems/2; i != NumElems; ++i)
3013 if (!isUndefOrEqual(Op->getMaskElt(i), i+NumElems))
3018 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
3020 static bool isSplatVector(SDNode *N) {
3021 if (N->getOpcode() != ISD::BUILD_VECTOR)
3024 SDValue SplatValue = N->getOperand(0);
3025 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
3026 if (N->getOperand(i) != SplatValue)
3031 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
3032 /// to an zero vector.
3033 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
3034 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
3035 SDValue V1 = N->getOperand(0);
3036 SDValue V2 = N->getOperand(1);
3037 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3038 for (unsigned i = 0; i != NumElems; ++i) {
3039 int Idx = N->getMaskElt(i);
3040 if (Idx >= (int)NumElems) {
3041 unsigned Opc = V2.getOpcode();
3042 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
3044 if (Opc != ISD::BUILD_VECTOR ||
3045 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
3047 } else if (Idx >= 0) {
3048 unsigned Opc = V1.getOpcode();
3049 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
3051 if (Opc != ISD::BUILD_VECTOR ||
3052 !X86::isZeroNode(V1.getOperand(Idx)))
3059 /// getZeroVector - Returns a vector of specified type with all zero elements.
3061 static SDValue getZeroVector(EVT VT, bool HasSSE2, SelectionDAG &DAG,
3063 assert(VT.isVector() && "Expected a vector type");
3065 // Always build zero vectors as <4 x i32> or <2 x i32> bitcasted to their dest
3066 // type. This ensures they get CSE'd.
3068 if (VT.getSizeInBits() == 64) { // MMX
3069 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
3070 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
3071 } else if (HasSSE2) { // SSE2
3072 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
3073 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
3075 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
3076 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
3078 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
3081 /// getOnesVector - Returns a vector of specified type with all bits set.
3083 static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
3084 assert(VT.isVector() && "Expected a vector type");
3086 // Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest
3087 // type. This ensures they get CSE'd.
3088 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
3090 if (VT.getSizeInBits() == 64) // MMX
3091 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
3093 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
3094 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
3098 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
3099 /// that point to V2 points to its first element.
3100 static SDValue NormalizeMask(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
3101 EVT VT = SVOp->getValueType(0);
3102 unsigned NumElems = VT.getVectorNumElements();
3104 bool Changed = false;
3105 SmallVector<int, 8> MaskVec;
3106 SVOp->getMask(MaskVec);
3108 for (unsigned i = 0; i != NumElems; ++i) {
3109 if (MaskVec[i] > (int)NumElems) {
3110 MaskVec[i] = NumElems;
3115 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(0),
3116 SVOp->getOperand(1), &MaskVec[0]);
3117 return SDValue(SVOp, 0);
3120 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
3121 /// operation of specified width.
3122 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3124 unsigned NumElems = VT.getVectorNumElements();
3125 SmallVector<int, 8> Mask;
3126 Mask.push_back(NumElems);
3127 for (unsigned i = 1; i != NumElems; ++i)
3129 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3132 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
3133 static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3135 unsigned NumElems = VT.getVectorNumElements();
3136 SmallVector<int, 8> Mask;
3137 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
3139 Mask.push_back(i + NumElems);
3141 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3144 /// getUnpackhMask - Returns a vector_shuffle node for an unpackh operation.
3145 static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3147 unsigned NumElems = VT.getVectorNumElements();
3148 unsigned Half = NumElems/2;
3149 SmallVector<int, 8> Mask;
3150 for (unsigned i = 0; i != Half; ++i) {
3151 Mask.push_back(i + Half);
3152 Mask.push_back(i + NumElems + Half);
3154 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3157 /// PromoteSplat - Promote a splat of v4f32, v8i16 or v16i8 to v4i32.
3158 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG,
3160 if (SV->getValueType(0).getVectorNumElements() <= 4)
3161 return SDValue(SV, 0);
3163 EVT PVT = MVT::v4f32;
3164 EVT VT = SV->getValueType(0);
3165 DebugLoc dl = SV->getDebugLoc();
3166 SDValue V1 = SV->getOperand(0);
3167 int NumElems = VT.getVectorNumElements();
3168 int EltNo = SV->getSplatIndex();
3170 // unpack elements to the correct location
3171 while (NumElems > 4) {
3172 if (EltNo < NumElems/2) {
3173 V1 = getUnpackl(DAG, dl, VT, V1, V1);
3175 V1 = getUnpackh(DAG, dl, VT, V1, V1);
3176 EltNo -= NumElems/2;
3181 // Perform the splat.
3182 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
3183 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, PVT, V1);
3184 V1 = DAG.getVectorShuffle(PVT, dl, V1, DAG.getUNDEF(PVT), &SplatMask[0]);
3185 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, V1);
3188 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
3189 /// vector of zero or undef vector. This produces a shuffle where the low
3190 /// element of V2 is swizzled into the zero/undef vector, landing at element
3191 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
3192 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
3193 bool isZero, bool HasSSE2,
3194 SelectionDAG &DAG) {
3195 EVT VT = V2.getValueType();
3197 ? getZeroVector(VT, HasSSE2, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT);
3198 unsigned NumElems = VT.getVectorNumElements();
3199 SmallVector<int, 16> MaskVec;
3200 for (unsigned i = 0; i != NumElems; ++i)
3201 // If this is the insertion idx, put the low elt of V2 here.
3202 MaskVec.push_back(i == Idx ? NumElems : i);
3203 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]);
3206 /// getNumOfConsecutiveZeros - Return the number of elements in a result of
3207 /// a shuffle that is zero.
3209 unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp, int NumElems,
3210 bool Low, SelectionDAG &DAG) {
3211 unsigned NumZeros = 0;
3212 for (int i = 0; i < NumElems; ++i) {
3213 unsigned Index = Low ? i : NumElems-i-1;
3214 int Idx = SVOp->getMaskElt(Index);
3219 SDValue Elt = DAG.getShuffleScalarElt(SVOp, Index);
3220 if (Elt.getNode() && X86::isZeroNode(Elt))
3228 /// isVectorShift - Returns true if the shuffle can be implemented as a
3229 /// logical left or right shift of a vector.
3230 /// FIXME: split into pslldqi, psrldqi, palignr variants.
3231 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
3232 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
3233 int NumElems = SVOp->getValueType(0).getVectorNumElements();
3236 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, true, DAG);
3239 NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, false, DAG);
3243 bool SeenV1 = false;
3244 bool SeenV2 = false;
3245 for (int i = NumZeros; i < NumElems; ++i) {
3246 int Val = isLeft ? (i - NumZeros) : i;
3247 int Idx = SVOp->getMaskElt(isLeft ? i : (i - NumZeros));
3259 if (SeenV1 && SeenV2)
3262 ShVal = SeenV1 ? SVOp->getOperand(0) : SVOp->getOperand(1);
3268 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
3270 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
3271 unsigned NumNonZero, unsigned NumZero,
3272 SelectionDAG &DAG, TargetLowering &TLI) {
3276 DebugLoc dl = Op.getDebugLoc();
3279 for (unsigned i = 0; i < 16; ++i) {
3280 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
3281 if (ThisIsNonZero && First) {
3283 V = getZeroVector(MVT::v8i16, true, DAG, dl);
3285 V = DAG.getUNDEF(MVT::v8i16);
3290 SDValue ThisElt(0, 0), LastElt(0, 0);
3291 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
3292 if (LastIsNonZero) {
3293 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
3294 MVT::i16, Op.getOperand(i-1));
3296 if (ThisIsNonZero) {
3297 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
3298 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
3299 ThisElt, DAG.getConstant(8, MVT::i8));
3301 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
3305 if (ThisElt.getNode())
3306 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
3307 DAG.getIntPtrConstant(i/2));
3311 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V);
3314 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
3316 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
3317 unsigned NumNonZero, unsigned NumZero,
3318 SelectionDAG &DAG, TargetLowering &TLI) {
3322 DebugLoc dl = Op.getDebugLoc();
3325 for (unsigned i = 0; i < 8; ++i) {
3326 bool isNonZero = (NonZeros & (1 << i)) != 0;
3330 V = getZeroVector(MVT::v8i16, true, DAG, dl);
3332 V = DAG.getUNDEF(MVT::v8i16);
3335 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
3336 MVT::v8i16, V, Op.getOperand(i),
3337 DAG.getIntPtrConstant(i));
3344 /// getVShift - Return a vector logical shift node.
3346 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
3347 unsigned NumBits, SelectionDAG &DAG,
3348 const TargetLowering &TLI, DebugLoc dl) {
3349 bool isMMX = VT.getSizeInBits() == 64;
3350 EVT ShVT = isMMX ? MVT::v1i64 : MVT::v2i64;
3351 unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL;
3352 SrcOp = DAG.getNode(ISD::BIT_CONVERT, dl, ShVT, SrcOp);
3353 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
3354 DAG.getNode(Opc, dl, ShVT, SrcOp,
3355 DAG.getConstant(NumBits, TLI.getShiftAmountTy())));
3359 X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
3360 SelectionDAG &DAG) {
3362 // Check if the scalar load can be widened into a vector load. And if
3363 // the address is "base + cst" see if the cst can be "absorbed" into
3364 // the shuffle mask.
3365 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
3366 SDValue Ptr = LD->getBasePtr();
3367 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
3369 EVT PVT = LD->getValueType(0);
3370 if (PVT != MVT::i32 && PVT != MVT::f32)
3375 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
3376 FI = FINode->getIndex();
3378 } else if (Ptr.getOpcode() == ISD::ADD &&
3379 isa<ConstantSDNode>(Ptr.getOperand(1)) &&
3380 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
3381 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
3382 Offset = Ptr.getConstantOperandVal(1);
3383 Ptr = Ptr.getOperand(0);
3388 SDValue Chain = LD->getChain();
3389 // Make sure the stack object alignment is at least 16.
3390 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
3391 if (DAG.InferPtrAlignment(Ptr) < 16) {
3392 if (MFI->isFixedObjectIndex(FI)) {
3393 // Can't change the alignment. Reference stack + offset explicitly
3394 // if stack pointer is at least 16-byte aligned.
3395 unsigned StackAlign = Subtarget->getStackAlignment();
3396 if (StackAlign < 16)
3398 Offset = MFI->getObjectOffset(FI) + Offset;
3399 SDValue StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr,
3401 Ptr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr,
3402 DAG.getConstant(Offset & ~15, getPointerTy()));
3405 MFI->setObjectAlignment(FI, 16);
3409 // (Offset % 16) must be multiple of 4. Then address is then
3410 // Ptr + (Offset & ~15).
3413 if ((Offset % 16) & 3)
3415 int64_t StartOffset = Offset & ~15;
3417 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(),
3418 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
3420 int EltNo = (Offset - StartOffset) >> 2;
3421 int Mask[4] = { EltNo, EltNo, EltNo, EltNo };
3422 EVT VT = (PVT == MVT::i32) ? MVT::v4i32 : MVT::v4f32;
3423 SDValue V1 = DAG.getLoad(VT, dl, Chain, Ptr,LD->getSrcValue(),0);
3424 // Canonicalize it to a v4i32 shuffle.
3425 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32, V1);
3426 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
3427 DAG.getVectorShuffle(MVT::v4i32, dl, V1,
3428 DAG.getUNDEF(MVT::v4i32), &Mask[0]));
3435 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
3436 DebugLoc dl = Op.getDebugLoc();
3437 // All zero's are handled with pxor, all one's are handled with pcmpeqd.
3438 if (ISD::isBuildVectorAllZeros(Op.getNode())
3439 || ISD::isBuildVectorAllOnes(Op.getNode())) {
3440 // Canonicalize this to either <4 x i32> or <2 x i32> (SSE vs MMX) to
3441 // 1) ensure the zero vectors are CSE'd, and 2) ensure that i64 scalars are
3442 // eliminated on x86-32 hosts.
3443 if (Op.getValueType() == MVT::v4i32 || Op.getValueType() == MVT::v2i32)
3446 if (ISD::isBuildVectorAllOnes(Op.getNode()))
3447 return getOnesVector(Op.getValueType(), DAG, dl);
3448 return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(), DAG, dl);
3451 EVT VT = Op.getValueType();
3452 EVT ExtVT = VT.getVectorElementType();
3453 unsigned EVTBits = ExtVT.getSizeInBits();
3455 unsigned NumElems = Op.getNumOperands();
3456 unsigned NumZero = 0;
3457 unsigned NumNonZero = 0;
3458 unsigned NonZeros = 0;
3459 bool IsAllConstants = true;
3460 SmallSet<SDValue, 8> Values;
3461 for (unsigned i = 0; i < NumElems; ++i) {
3462 SDValue Elt = Op.getOperand(i);
3463 if (Elt.getOpcode() == ISD::UNDEF)
3466 if (Elt.getOpcode() != ISD::Constant &&
3467 Elt.getOpcode() != ISD::ConstantFP)
3468 IsAllConstants = false;
3469 if (X86::isZeroNode(Elt))
3472 NonZeros |= (1 << i);
3477 if (NumNonZero == 0) {
3478 // All undef vector. Return an UNDEF. All zero vectors were handled above.
3479 return DAG.getUNDEF(VT);
3482 // Special case for single non-zero, non-undef, element.
3483 if (NumNonZero == 1) {
3484 unsigned Idx = CountTrailingZeros_32(NonZeros);
3485 SDValue Item = Op.getOperand(Idx);
3487 // If this is an insertion of an i64 value on x86-32, and if the top bits of
3488 // the value are obviously zero, truncate the value to i32 and do the
3489 // insertion that way. Only do this if the value is non-constant or if the
3490 // value is a constant being inserted into element 0. It is cheaper to do
3491 // a constant pool load than it is to do a movd + shuffle.
3492 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
3493 (!IsAllConstants || Idx == 0)) {
3494 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
3495 // Handle MMX and SSE both.
3496 EVT VecVT = VT == MVT::v2i64 ? MVT::v4i32 : MVT::v2i32;
3497 unsigned VecElts = VT == MVT::v2i64 ? 4 : 2;
3499 // Truncate the value (which may itself be a constant) to i32, and
3500 // convert it to a vector with movd (S2V+shuffle to zero extend).
3501 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
3502 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
3503 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
3504 Subtarget->hasSSE2(), DAG);
3506 // Now we have our 32-bit value zero extended in the low element of
3507 // a vector. If Idx != 0, swizzle it into place.
3509 SmallVector<int, 4> Mask;
3510 Mask.push_back(Idx);
3511 for (unsigned i = 1; i != VecElts; ++i)
3513 Item = DAG.getVectorShuffle(VecVT, dl, Item,
3514 DAG.getUNDEF(Item.getValueType()),
3517 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Item);
3521 // If we have a constant or non-constant insertion into the low element of
3522 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
3523 // the rest of the elements. This will be matched as movd/movq/movss/movsd
3524 // depending on what the source datatype is.
3527 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
3528 } else if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
3529 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
3530 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
3531 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
3532 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget->hasSSE2(),
3534 } else if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
3535 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
3536 EVT MiddleVT = VT.getSizeInBits() == 64 ? MVT::v2i32 : MVT::v4i32;
3537 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MiddleVT, Item);
3538 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
3539 Subtarget->hasSSE2(), DAG);
3540 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Item);
3544 // Is it a vector logical left shift?
3545 if (NumElems == 2 && Idx == 1 &&
3546 X86::isZeroNode(Op.getOperand(0)) &&
3547 !X86::isZeroNode(Op.getOperand(1))) {
3548 unsigned NumBits = VT.getSizeInBits();
3549 return getVShift(true, VT,
3550 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
3551 VT, Op.getOperand(1)),
3552 NumBits/2, DAG, *this, dl);
3555 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
3558 // Otherwise, if this is a vector with i32 or f32 elements, and the element
3559 // is a non-constant being inserted into an element other than the low one,
3560 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
3561 // movd/movss) to move this into the low element, then shuffle it into
3563 if (EVTBits == 32) {
3564 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
3566 // Turn it into a shuffle of zero and zero-extended scalar to vector.
3567 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0,
3568 Subtarget->hasSSE2(), DAG);
3569 SmallVector<int, 8> MaskVec;
3570 for (unsigned i = 0; i < NumElems; i++)
3571 MaskVec.push_back(i == Idx ? 0 : 1);
3572 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
3576 // Splat is obviously ok. Let legalizer expand it to a shuffle.
3577 if (Values.size() == 1) {
3578 if (EVTBits == 32) {
3579 // Instead of a shuffle like this:
3580 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
3581 // Check if it's possible to issue this instead.
3582 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
3583 unsigned Idx = CountTrailingZeros_32(NonZeros);
3584 SDValue Item = Op.getOperand(Idx);
3585 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
3586 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
3591 // A vector full of immediates; various special cases are already
3592 // handled, so this is best done with a single constant-pool load.
3596 // Let legalizer expand 2-wide build_vectors.
3597 if (EVTBits == 64) {
3598 if (NumNonZero == 1) {
3599 // One half is zero or undef.
3600 unsigned Idx = CountTrailingZeros_32(NonZeros);
3601 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
3602 Op.getOperand(Idx));
3603 return getShuffleVectorZeroOrUndef(V2, Idx, true,
3604 Subtarget->hasSSE2(), DAG);
3609 // If element VT is < 32 bits, convert it to inserts into a zero vector.
3610 if (EVTBits == 8 && NumElems == 16) {
3611 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
3613 if (V.getNode()) return V;
3616 if (EVTBits == 16 && NumElems == 8) {
3617 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
3619 if (V.getNode()) return V;
3622 // If element VT is == 32 bits, turn it into a number of shuffles.
3623 SmallVector<SDValue, 8> V;
3625 if (NumElems == 4 && NumZero > 0) {
3626 for (unsigned i = 0; i < 4; ++i) {
3627 bool isZero = !(NonZeros & (1 << i));
3629 V[i] = getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
3631 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
3634 for (unsigned i = 0; i < 2; ++i) {
3635 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
3638 V[i] = V[i*2]; // Must be a zero vector.
3641 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
3644 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
3647 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
3652 SmallVector<int, 8> MaskVec;
3653 bool Reverse = (NonZeros & 0x3) == 2;
3654 for (unsigned i = 0; i < 2; ++i)
3655 MaskVec.push_back(Reverse ? 1-i : i);
3656 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2;
3657 for (unsigned i = 0; i < 2; ++i)
3658 MaskVec.push_back(Reverse ? 1-i+NumElems : i+NumElems);
3659 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
3662 if (Values.size() > 2) {
3663 // If we have SSE 4.1, Expand into a number of inserts unless the number of
3664 // values to be inserted is equal to the number of elements, in which case
3665 // use the unpack code below in the hopes of matching the consecutive elts
3666 // load merge pattern for shuffles.
3667 // FIXME: We could probably just check that here directly.
3668 if (Values.size() < NumElems && VT.getSizeInBits() == 128 &&
3669 getSubtarget()->hasSSE41()) {
3670 V[0] = DAG.getUNDEF(VT);
3671 for (unsigned i = 0; i < NumElems; ++i)
3672 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
3673 V[0] = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, V[0],
3674 Op.getOperand(i), DAG.getIntPtrConstant(i));
3677 // Expand into a number of unpckl*.
3679 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
3680 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
3681 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
3682 for (unsigned i = 0; i < NumElems; ++i)
3683 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
3685 while (NumElems != 0) {
3686 for (unsigned i = 0; i < NumElems; ++i)
3687 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + NumElems]);
3696 // v8i16 shuffles - Prefer shuffles in the following order:
3697 // 1. [all] pshuflw, pshufhw, optional move
3698 // 2. [ssse3] 1 x pshufb
3699 // 3. [ssse3] 2 x pshufb + 1 x por
3700 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
3702 SDValue LowerVECTOR_SHUFFLEv8i16(ShuffleVectorSDNode *SVOp,
3703 SelectionDAG &DAG, X86TargetLowering &TLI) {
3704 SDValue V1 = SVOp->getOperand(0);
3705 SDValue V2 = SVOp->getOperand(1);
3706 DebugLoc dl = SVOp->getDebugLoc();
3707 SmallVector<int, 8> MaskVals;
3709 // Determine if more than 1 of the words in each of the low and high quadwords
3710 // of the result come from the same quadword of one of the two inputs. Undef
3711 // mask values count as coming from any quadword, for better codegen.
3712 SmallVector<unsigned, 4> LoQuad(4);
3713 SmallVector<unsigned, 4> HiQuad(4);
3714 BitVector InputQuads(4);
3715 for (unsigned i = 0; i < 8; ++i) {
3716 SmallVectorImpl<unsigned> &Quad = i < 4 ? LoQuad : HiQuad;
3717 int EltIdx = SVOp->getMaskElt(i);
3718 MaskVals.push_back(EltIdx);
3727 InputQuads.set(EltIdx / 4);
3730 int BestLoQuad = -1;
3731 unsigned MaxQuad = 1;
3732 for (unsigned i = 0; i < 4; ++i) {
3733 if (LoQuad[i] > MaxQuad) {
3735 MaxQuad = LoQuad[i];
3739 int BestHiQuad = -1;
3741 for (unsigned i = 0; i < 4; ++i) {
3742 if (HiQuad[i] > MaxQuad) {
3744 MaxQuad = HiQuad[i];
3748 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
3749 // of the two input vectors, shuffle them into one input vector so only a
3750 // single pshufb instruction is necessary. If There are more than 2 input
3751 // quads, disable the next transformation since it does not help SSSE3.
3752 bool V1Used = InputQuads[0] || InputQuads[1];
3753 bool V2Used = InputQuads[2] || InputQuads[3];
3754 if (TLI.getSubtarget()->hasSSSE3()) {
3755 if (InputQuads.count() == 2 && V1Used && V2Used) {
3756 BestLoQuad = InputQuads.find_first();
3757 BestHiQuad = InputQuads.find_next(BestLoQuad);
3759 if (InputQuads.count() > 2) {
3765 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
3766 // the shuffle mask. If a quad is scored as -1, that means that it contains
3767 // words from all 4 input quadwords.
3769 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
3770 SmallVector<int, 8> MaskV;
3771 MaskV.push_back(BestLoQuad < 0 ? 0 : BestLoQuad);
3772 MaskV.push_back(BestHiQuad < 0 ? 1 : BestHiQuad);
3773 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
3774 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V1),
3775 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V2), &MaskV[0]);
3776 NewV = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, NewV);
3778 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
3779 // source words for the shuffle, to aid later transformations.
3780 bool AllWordsInNewV = true;
3781 bool InOrder[2] = { true, true };
3782 for (unsigned i = 0; i != 8; ++i) {
3783 int idx = MaskVals[i];
3785 InOrder[i/4] = false;
3786 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
3788 AllWordsInNewV = false;
3792 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
3793 if (AllWordsInNewV) {
3794 for (int i = 0; i != 8; ++i) {
3795 int idx = MaskVals[i];
3798 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
3799 if ((idx != i) && idx < 4)
3801 if ((idx != i) && idx > 3)
3810 // If we've eliminated the use of V2, and the new mask is a pshuflw or
3811 // pshufhw, that's as cheap as it gets. Return the new shuffle.
3812 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
3813 return DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
3814 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
3818 // If we have SSSE3, and all words of the result are from 1 input vector,
3819 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
3820 // is present, fall back to case 4.
3821 if (TLI.getSubtarget()->hasSSSE3()) {
3822 SmallVector<SDValue,16> pshufbMask;
3824 // If we have elements from both input vectors, set the high bit of the
3825 // shuffle mask element to zero out elements that come from V2 in the V1
3826 // mask, and elements that come from V1 in the V2 mask, so that the two
3827 // results can be OR'd together.
3828 bool TwoInputs = V1Used && V2Used;
3829 for (unsigned i = 0; i != 8; ++i) {
3830 int EltIdx = MaskVals[i] * 2;
3831 if (TwoInputs && (EltIdx >= 16)) {
3832 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
3833 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
3836 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
3837 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8));
3839 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V1);
3840 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
3841 DAG.getNode(ISD::BUILD_VECTOR, dl,
3842 MVT::v16i8, &pshufbMask[0], 16));
3844 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
3846 // Calculate the shuffle mask for the second input, shuffle it, and
3847 // OR it with the first shuffled input.
3849 for (unsigned i = 0; i != 8; ++i) {
3850 int EltIdx = MaskVals[i] * 2;
3852 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
3853 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
3856 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
3857 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8));
3859 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V2);
3860 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
3861 DAG.getNode(ISD::BUILD_VECTOR, dl,
3862 MVT::v16i8, &pshufbMask[0], 16));
3863 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
3864 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
3867 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
3868 // and update MaskVals with new element order.
3869 BitVector InOrder(8);
3870 if (BestLoQuad >= 0) {
3871 SmallVector<int, 8> MaskV;
3872 for (int i = 0; i != 4; ++i) {
3873 int idx = MaskVals[i];
3875 MaskV.push_back(-1);
3877 } else if ((idx / 4) == BestLoQuad) {
3878 MaskV.push_back(idx & 3);
3881 MaskV.push_back(-1);
3884 for (unsigned i = 4; i != 8; ++i)
3886 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
3890 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
3891 // and update MaskVals with the new element order.
3892 if (BestHiQuad >= 0) {
3893 SmallVector<int, 8> MaskV;
3894 for (unsigned i = 0; i != 4; ++i)
3896 for (unsigned i = 4; i != 8; ++i) {
3897 int idx = MaskVals[i];
3899 MaskV.push_back(-1);
3901 } else if ((idx / 4) == BestHiQuad) {
3902 MaskV.push_back((idx & 3) + 4);
3905 MaskV.push_back(-1);
3908 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
3912 // In case BestHi & BestLo were both -1, which means each quadword has a word
3913 // from each of the four input quadwords, calculate the InOrder bitvector now
3914 // before falling through to the insert/extract cleanup.
3915 if (BestLoQuad == -1 && BestHiQuad == -1) {
3917 for (int i = 0; i != 8; ++i)
3918 if (MaskVals[i] < 0 || MaskVals[i] == i)
3922 // The other elements are put in the right place using pextrw and pinsrw.
3923 for (unsigned i = 0; i != 8; ++i) {
3926 int EltIdx = MaskVals[i];
3929 SDValue ExtOp = (EltIdx < 8)
3930 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
3931 DAG.getIntPtrConstant(EltIdx))
3932 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
3933 DAG.getIntPtrConstant(EltIdx - 8));
3934 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
3935 DAG.getIntPtrConstant(i));
3940 // v16i8 shuffles - Prefer shuffles in the following order:
3941 // 1. [ssse3] 1 x pshufb
3942 // 2. [ssse3] 2 x pshufb + 1 x por
3943 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
3945 SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
3946 SelectionDAG &DAG, X86TargetLowering &TLI) {
3947 SDValue V1 = SVOp->getOperand(0);
3948 SDValue V2 = SVOp->getOperand(1);
3949 DebugLoc dl = SVOp->getDebugLoc();
3950 SmallVector<int, 16> MaskVals;
3951 SVOp->getMask(MaskVals);
3953 // If we have SSSE3, case 1 is generated when all result bytes come from
3954 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
3955 // present, fall back to case 3.
3956 // FIXME: kill V2Only once shuffles are canonizalized by getNode.
3959 for (unsigned i = 0; i < 16; ++i) {
3960 int EltIdx = MaskVals[i];
3969 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
3970 if (TLI.getSubtarget()->hasSSSE3()) {
3971 SmallVector<SDValue,16> pshufbMask;
3973 // If all result elements are from one input vector, then only translate
3974 // undef mask values to 0x80 (zero out result) in the pshufb mask.
3976 // Otherwise, we have elements from both input vectors, and must zero out
3977 // elements that come from V2 in the first mask, and V1 in the second mask
3978 // so that we can OR them together.
3979 bool TwoInputs = !(V1Only || V2Only);
3980 for (unsigned i = 0; i != 16; ++i) {
3981 int EltIdx = MaskVals[i];
3982 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) {
3983 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
3986 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
3988 // If all the elements are from V2, assign it to V1 and return after
3989 // building the first pshufb.
3992 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
3993 DAG.getNode(ISD::BUILD_VECTOR, dl,
3994 MVT::v16i8, &pshufbMask[0], 16));
3998 // Calculate the shuffle mask for the second input, shuffle it, and
3999 // OR it with the first shuffled input.
4001 for (unsigned i = 0; i != 16; ++i) {
4002 int EltIdx = MaskVals[i];
4004 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4007 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
4009 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
4010 DAG.getNode(ISD::BUILD_VECTOR, dl,
4011 MVT::v16i8, &pshufbMask[0], 16));
4012 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
4015 // No SSSE3 - Calculate in place words and then fix all out of place words
4016 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
4017 // the 16 different words that comprise the two doublequadword input vectors.
4018 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
4019 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V2);
4020 SDValue NewV = V2Only ? V2 : V1;
4021 for (int i = 0; i != 8; ++i) {
4022 int Elt0 = MaskVals[i*2];
4023 int Elt1 = MaskVals[i*2+1];
4025 // This word of the result is all undef, skip it.
4026 if (Elt0 < 0 && Elt1 < 0)
4029 // This word of the result is already in the correct place, skip it.
4030 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1))
4032 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17))
4035 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
4036 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
4039 // If Elt0 and Elt1 are defined, are consecutive, and can be load
4040 // using a single extract together, load it and store it.
4041 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
4042 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
4043 DAG.getIntPtrConstant(Elt1 / 2));
4044 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
4045 DAG.getIntPtrConstant(i));
4049 // If Elt1 is defined, extract it from the appropriate source. If the
4050 // source byte is not also odd, shift the extracted word left 8 bits
4051 // otherwise clear the bottom 8 bits if we need to do an or.
4053 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
4054 DAG.getIntPtrConstant(Elt1 / 2));
4055 if ((Elt1 & 1) == 0)
4056 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
4057 DAG.getConstant(8, TLI.getShiftAmountTy()));
4059 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
4060 DAG.getConstant(0xFF00, MVT::i16));
4062 // If Elt0 is defined, extract it from the appropriate source. If the
4063 // source byte is not also even, shift the extracted word right 8 bits. If
4064 // Elt1 was also defined, OR the extracted values together before
4065 // inserting them in the result.
4067 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
4068 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
4069 if ((Elt0 & 1) != 0)
4070 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
4071 DAG.getConstant(8, TLI.getShiftAmountTy()));
4073 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
4074 DAG.getConstant(0x00FF, MVT::i16));
4075 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
4078 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
4079 DAG.getIntPtrConstant(i));
4081 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, NewV);
4084 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
4085 /// ones, or rewriting v4i32 / v2f32 as 2 wide ones if possible. This can be
4086 /// done when every pair / quad of shuffle mask elements point to elements in
4087 /// the right sequence. e.g.
4088 /// vector_shuffle <>, <>, < 3, 4, | 10, 11, | 0, 1, | 14, 15>
4090 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
4092 TargetLowering &TLI, DebugLoc dl) {
4093 EVT VT = SVOp->getValueType(0);
4094 SDValue V1 = SVOp->getOperand(0);
4095 SDValue V2 = SVOp->getOperand(1);
4096 unsigned NumElems = VT.getVectorNumElements();
4097 unsigned NewWidth = (NumElems == 4) ? 2 : 4;
4098 EVT MaskVT = MVT::getIntVectorWithNumElements(NewWidth);
4099 EVT MaskEltVT = MaskVT.getVectorElementType();
4101 switch (VT.getSimpleVT().SimpleTy) {
4102 default: assert(false && "Unexpected!");
4103 case MVT::v4f32: NewVT = MVT::v2f64; break;
4104 case MVT::v4i32: NewVT = MVT::v2i64; break;
4105 case MVT::v8i16: NewVT = MVT::v4i32; break;
4106 case MVT::v16i8: NewVT = MVT::v4i32; break;
4109 if (NewWidth == 2) {
4115 int Scale = NumElems / NewWidth;
4116 SmallVector<int, 8> MaskVec;
4117 for (unsigned i = 0; i < NumElems; i += Scale) {
4119 for (int j = 0; j < Scale; ++j) {
4120 int EltIdx = SVOp->getMaskElt(i+j);
4124 StartIdx = EltIdx - (EltIdx % Scale);
4125 if (EltIdx != StartIdx + j)
4129 MaskVec.push_back(-1);
4131 MaskVec.push_back(StartIdx / Scale);
4134 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V1);
4135 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V2);
4136 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
4139 /// getVZextMovL - Return a zero-extending vector move low node.
4141 static SDValue getVZextMovL(EVT VT, EVT OpVT,
4142 SDValue SrcOp, SelectionDAG &DAG,
4143 const X86Subtarget *Subtarget, DebugLoc dl) {
4144 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
4145 LoadSDNode *LD = NULL;
4146 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
4147 LD = dyn_cast<LoadSDNode>(SrcOp);
4149 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
4151 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
4152 if ((ExtVT.SimpleTy != MVT::i64 || Subtarget->is64Bit()) &&
4153 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
4154 SrcOp.getOperand(0).getOpcode() == ISD::BIT_CONVERT &&
4155 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
4157 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
4158 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
4159 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
4160 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
4168 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
4169 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
4170 DAG.getNode(ISD::BIT_CONVERT, dl,
4174 /// LowerVECTOR_SHUFFLE_4wide - Handle all 4 wide cases with a number of
4177 LowerVECTOR_SHUFFLE_4wide(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
4178 SDValue V1 = SVOp->getOperand(0);
4179 SDValue V2 = SVOp->getOperand(1);
4180 DebugLoc dl = SVOp->getDebugLoc();
4181 EVT VT = SVOp->getValueType(0);
4183 SmallVector<std::pair<int, int>, 8> Locs;
4185 SmallVector<int, 8> Mask1(4U, -1);
4186 SmallVector<int, 8> PermMask;
4187 SVOp->getMask(PermMask);
4191 for (unsigned i = 0; i != 4; ++i) {
4192 int Idx = PermMask[i];
4194 Locs[i] = std::make_pair(-1, -1);
4196 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
4198 Locs[i] = std::make_pair(0, NumLo);
4202 Locs[i] = std::make_pair(1, NumHi);
4204 Mask1[2+NumHi] = Idx;
4210 if (NumLo <= 2 && NumHi <= 2) {
4211 // If no more than two elements come from either vector. This can be
4212 // implemented with two shuffles. First shuffle gather the elements.
4213 // The second shuffle, which takes the first shuffle as both of its
4214 // vector operands, put the elements into the right order.
4215 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
4217 SmallVector<int, 8> Mask2(4U, -1);
4219 for (unsigned i = 0; i != 4; ++i) {
4220 if (Locs[i].first == -1)
4223 unsigned Idx = (i < 2) ? 0 : 4;
4224 Idx += Locs[i].first * 2 + Locs[i].second;
4229 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
4230 } else if (NumLo == 3 || NumHi == 3) {
4231 // Otherwise, we must have three elements from one vector, call it X, and
4232 // one element from the other, call it Y. First, use a shufps to build an
4233 // intermediate vector with the one element from Y and the element from X
4234 // that will be in the same half in the final destination (the indexes don't
4235 // matter). Then, use a shufps to build the final vector, taking the half
4236 // containing the element from Y from the intermediate, and the other half
4239 // Normalize it so the 3 elements come from V1.
4240 CommuteVectorShuffleMask(PermMask, VT);
4244 // Find the element from V2.
4246 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
4247 int Val = PermMask[HiIndex];
4254 Mask1[0] = PermMask[HiIndex];
4256 Mask1[2] = PermMask[HiIndex^1];
4258 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
4261 Mask1[0] = PermMask[0];
4262 Mask1[1] = PermMask[1];
4263 Mask1[2] = HiIndex & 1 ? 6 : 4;
4264 Mask1[3] = HiIndex & 1 ? 4 : 6;
4265 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
4267 Mask1[0] = HiIndex & 1 ? 2 : 0;
4268 Mask1[1] = HiIndex & 1 ? 0 : 2;
4269 Mask1[2] = PermMask[2];
4270 Mask1[3] = PermMask[3];
4275 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
4279 // Break it into (shuffle shuffle_hi, shuffle_lo).
4281 SmallVector<int,8> LoMask(4U, -1);
4282 SmallVector<int,8> HiMask(4U, -1);
4284 SmallVector<int,8> *MaskPtr = &LoMask;
4285 unsigned MaskIdx = 0;
4288 for (unsigned i = 0; i != 4; ++i) {
4295 int Idx = PermMask[i];
4297 Locs[i] = std::make_pair(-1, -1);
4298 } else if (Idx < 4) {
4299 Locs[i] = std::make_pair(MaskIdx, LoIdx);
4300 (*MaskPtr)[LoIdx] = Idx;
4303 Locs[i] = std::make_pair(MaskIdx, HiIdx);
4304 (*MaskPtr)[HiIdx] = Idx;
4309 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
4310 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
4311 SmallVector<int, 8> MaskOps;
4312 for (unsigned i = 0; i != 4; ++i) {
4313 if (Locs[i].first == -1) {
4314 MaskOps.push_back(-1);
4316 unsigned Idx = Locs[i].first * 4 + Locs[i].second;
4317 MaskOps.push_back(Idx);
4320 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
4324 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
4325 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
4326 SDValue V1 = Op.getOperand(0);
4327 SDValue V2 = Op.getOperand(1);
4328 EVT VT = Op.getValueType();
4329 DebugLoc dl = Op.getDebugLoc();
4330 unsigned NumElems = VT.getVectorNumElements();
4331 bool isMMX = VT.getSizeInBits() == 64;
4332 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
4333 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
4334 bool V1IsSplat = false;
4335 bool V2IsSplat = false;
4337 if (isZeroShuffle(SVOp))
4338 return getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
4340 // Promote splats to v4f32.
4341 if (SVOp->isSplat()) {
4342 if (isMMX || NumElems < 4)
4344 return PromoteSplat(SVOp, DAG, Subtarget->hasSSE2());
4347 // If the shuffle can be profitably rewritten as a narrower shuffle, then
4349 if (VT == MVT::v8i16 || VT == MVT::v16i8) {
4350 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl);
4351 if (NewOp.getNode())
4352 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
4353 LowerVECTOR_SHUFFLE(NewOp, DAG));
4354 } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
4355 // FIXME: Figure out a cleaner way to do this.
4356 // Try to make use of movq to zero out the top part.
4357 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
4358 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl);
4359 if (NewOp.getNode()) {
4360 if (isCommutedMOVL(cast<ShuffleVectorSDNode>(NewOp), true, false))
4361 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(0),
4362 DAG, Subtarget, dl);
4364 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
4365 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl);
4366 if (NewOp.getNode() && X86::isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)))
4367 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1),
4368 DAG, Subtarget, dl);
4372 if (X86::isPSHUFDMask(SVOp))
4375 // Check if this can be converted into a logical shift.
4376 bool isLeft = false;
4379 bool isShift = getSubtarget()->hasSSE2() &&
4380 isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
4381 if (isShift && ShVal.hasOneUse()) {
4382 // If the shifted value has multiple uses, it may be cheaper to use
4383 // v_set0 + movlhps or movhlps, etc.
4384 EVT EltVT = VT.getVectorElementType();
4385 ShAmt *= EltVT.getSizeInBits();
4386 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
4389 if (X86::isMOVLMask(SVOp)) {
4392 if (ISD::isBuildVectorAllZeros(V1.getNode()))
4393 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
4398 // FIXME: fold these into legal mask.
4399 if (!isMMX && (X86::isMOVSHDUPMask(SVOp) ||
4400 X86::isMOVSLDUPMask(SVOp) ||
4401 X86::isMOVHLPSMask(SVOp) ||
4402 X86::isMOVLHPSMask(SVOp) ||
4403 X86::isMOVLPMask(SVOp)))
4406 if (ShouldXformToMOVHLPS(SVOp) ||
4407 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), SVOp))
4408 return CommuteVectorShuffle(SVOp, DAG);
4411 // No better options. Use a vshl / vsrl.
4412 EVT EltVT = VT.getVectorElementType();
4413 ShAmt *= EltVT.getSizeInBits();
4414 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
4417 bool Commuted = false;
4418 // FIXME: This should also accept a bitcast of a splat? Be careful, not
4419 // 1,1,1,1 -> v8i16 though.
4420 V1IsSplat = isSplatVector(V1.getNode());
4421 V2IsSplat = isSplatVector(V2.getNode());
4423 // Canonicalize the splat or undef, if present, to be on the RHS.
4424 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) {
4425 Op = CommuteVectorShuffle(SVOp, DAG);
4426 SVOp = cast<ShuffleVectorSDNode>(Op);
4427 V1 = SVOp->getOperand(0);
4428 V2 = SVOp->getOperand(1);
4429 std::swap(V1IsSplat, V2IsSplat);
4430 std::swap(V1IsUndef, V2IsUndef);
4434 if (isCommutedMOVL(SVOp, V2IsSplat, V2IsUndef)) {
4435 // Shuffling low element of v1 into undef, just return v1.
4438 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
4439 // the instruction selector will not match, so get a canonical MOVL with
4440 // swapped operands to undo the commute.
4441 return getMOVL(DAG, dl, VT, V2, V1);
4444 if (X86::isUNPCKL_v_undef_Mask(SVOp) ||
4445 X86::isUNPCKH_v_undef_Mask(SVOp) ||
4446 X86::isUNPCKLMask(SVOp) ||
4447 X86::isUNPCKHMask(SVOp))
4451 // Normalize mask so all entries that point to V2 points to its first
4452 // element then try to match unpck{h|l} again. If match, return a
4453 // new vector_shuffle with the corrected mask.
4454 SDValue NewMask = NormalizeMask(SVOp, DAG);
4455 ShuffleVectorSDNode *NSVOp = cast<ShuffleVectorSDNode>(NewMask);
4456 if (NSVOp != SVOp) {
4457 if (X86::isUNPCKLMask(NSVOp, true)) {
4459 } else if (X86::isUNPCKHMask(NSVOp, true)) {
4466 // Commute is back and try unpck* again.
4467 // FIXME: this seems wrong.
4468 SDValue NewOp = CommuteVectorShuffle(SVOp, DAG);
4469 ShuffleVectorSDNode *NewSVOp = cast<ShuffleVectorSDNode>(NewOp);
4470 if (X86::isUNPCKL_v_undef_Mask(NewSVOp) ||
4471 X86::isUNPCKH_v_undef_Mask(NewSVOp) ||
4472 X86::isUNPCKLMask(NewSVOp) ||
4473 X86::isUNPCKHMask(NewSVOp))
4477 // FIXME: for mmx, bitcast v2i32 to v4i16 for shuffle.
4479 // Normalize the node to match x86 shuffle ops if needed
4480 if (!isMMX && V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(SVOp))
4481 return CommuteVectorShuffle(SVOp, DAG);
4483 // Check for legal shuffle and return?
4484 SmallVector<int, 16> PermMask;
4485 SVOp->getMask(PermMask);
4486 if (isShuffleMaskLegal(PermMask, VT))
4489 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
4490 if (VT == MVT::v8i16) {
4491 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(SVOp, DAG, *this);
4492 if (NewOp.getNode())
4496 if (VT == MVT::v16i8) {
4497 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this);
4498 if (NewOp.getNode())
4502 // Handle all 4 wide cases with a number of shuffles except for MMX.
4503 if (NumElems == 4 && !isMMX)
4504 return LowerVECTOR_SHUFFLE_4wide(SVOp, DAG);
4510 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
4511 SelectionDAG &DAG) {
4512 EVT VT = Op.getValueType();
4513 DebugLoc dl = Op.getDebugLoc();
4514 if (VT.getSizeInBits() == 8) {
4515 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
4516 Op.getOperand(0), Op.getOperand(1));
4517 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
4518 DAG.getValueType(VT));
4519 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
4520 } else if (VT.getSizeInBits() == 16) {
4521 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4522 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
4524 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
4525 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
4526 DAG.getNode(ISD::BIT_CONVERT, dl,
4530 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
4531 Op.getOperand(0), Op.getOperand(1));
4532 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
4533 DAG.getValueType(VT));
4534 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
4535 } else if (VT == MVT::f32) {
4536 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
4537 // the result back to FR32 register. It's only worth matching if the
4538 // result has a single use which is a store or a bitcast to i32. And in
4539 // the case of a store, it's not worth it if the index is a constant 0,
4540 // because a MOVSSmr can be used instead, which is smaller and faster.
4541 if (!Op.hasOneUse())
4543 SDNode *User = *Op.getNode()->use_begin();
4544 if ((User->getOpcode() != ISD::STORE ||
4545 (isa<ConstantSDNode>(Op.getOperand(1)) &&
4546 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
4547 (User->getOpcode() != ISD::BIT_CONVERT ||
4548 User->getValueType(0) != MVT::i32))
4550 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
4551 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32,
4554 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Extract);
4555 } else if (VT == MVT::i32) {
4556 // ExtractPS works with constant index.
4557 if (isa<ConstantSDNode>(Op.getOperand(1)))
4565 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
4566 if (!isa<ConstantSDNode>(Op.getOperand(1)))
4569 if (Subtarget->hasSSE41()) {
4570 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
4575 EVT VT = Op.getValueType();
4576 DebugLoc dl = Op.getDebugLoc();
4577 // TODO: handle v16i8.
4578 if (VT.getSizeInBits() == 16) {
4579 SDValue Vec = Op.getOperand(0);
4580 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4582 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
4583 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
4584 DAG.getNode(ISD::BIT_CONVERT, dl,
4587 // Transform it so it match pextrw which produces a 32-bit result.
4588 EVT EltVT = MVT::i32;
4589 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
4590 Op.getOperand(0), Op.getOperand(1));
4591 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
4592 DAG.getValueType(VT));
4593 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
4594 } else if (VT.getSizeInBits() == 32) {
4595 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4599 // SHUFPS the element to the lowest double word, then movss.
4600 int Mask[4] = { Idx, -1, -1, -1 };
4601 EVT VVT = Op.getOperand(0).getValueType();
4602 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
4603 DAG.getUNDEF(VVT), Mask);
4604 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
4605 DAG.getIntPtrConstant(0));
4606 } else if (VT.getSizeInBits() == 64) {
4607 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
4608 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
4609 // to match extract_elt for f64.
4610 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4614 // UNPCKHPD the element to the lowest double word, then movsd.
4615 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
4616 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
4617 int Mask[2] = { 1, -1 };
4618 EVT VVT = Op.getOperand(0).getValueType();
4619 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
4620 DAG.getUNDEF(VVT), Mask);
4621 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
4622 DAG.getIntPtrConstant(0));
4629 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG){
4630 EVT VT = Op.getValueType();
4631 EVT EltVT = VT.getVectorElementType();
4632 DebugLoc dl = Op.getDebugLoc();
4634 SDValue N0 = Op.getOperand(0);
4635 SDValue N1 = Op.getOperand(1);
4636 SDValue N2 = Op.getOperand(2);
4638 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
4639 isa<ConstantSDNode>(N2)) {
4640 unsigned Opc = (EltVT.getSizeInBits() == 8) ? X86ISD::PINSRB
4642 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
4644 if (N1.getValueType() != MVT::i32)
4645 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
4646 if (N2.getValueType() != MVT::i32)
4647 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
4648 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
4649 } else if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
4650 // Bits [7:6] of the constant are the source select. This will always be
4651 // zero here. The DAG Combiner may combine an extract_elt index into these
4652 // bits. For example (insert (extract, 3), 2) could be matched by putting
4653 // the '3' into bits [7:6] of X86ISD::INSERTPS.
4654 // Bits [5:4] of the constant are the destination select. This is the
4655 // value of the incoming immediate.
4656 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
4657 // combine either bitwise AND or insert of float 0.0 to set these bits.
4658 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
4659 // Create this as a scalar to vector..
4660 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
4661 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
4662 } else if (EltVT == MVT::i32 && isa<ConstantSDNode>(N2)) {
4663 // PINSR* works with constant index.
4670 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
4671 EVT VT = Op.getValueType();
4672 EVT EltVT = VT.getVectorElementType();
4674 if (Subtarget->hasSSE41())
4675 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
4677 if (EltVT == MVT::i8)
4680 DebugLoc dl = Op.getDebugLoc();
4681 SDValue N0 = Op.getOperand(0);
4682 SDValue N1 = Op.getOperand(1);
4683 SDValue N2 = Op.getOperand(2);
4685 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
4686 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
4687 // as its second argument.
4688 if (N1.getValueType() != MVT::i32)
4689 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
4690 if (N2.getValueType() != MVT::i32)
4691 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
4692 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
4698 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
4699 DebugLoc dl = Op.getDebugLoc();
4700 if (Op.getValueType() == MVT::v2f32)
4701 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f32,
4702 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i32,
4703 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32,
4704 Op.getOperand(0))));
4706 if (Op.getValueType() == MVT::v1i64 && Op.getOperand(0).getValueType() == MVT::i64)
4707 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
4709 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
4710 EVT VT = MVT::v2i32;
4711 switch (Op.getValueType().getSimpleVT().SimpleTy) {
4718 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(),
4719 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, AnyExt));
4722 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
4723 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
4724 // one of the above mentioned nodes. It has to be wrapped because otherwise
4725 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
4726 // be used to form addressing mode. These wrapped nodes will be selected
4729 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
4730 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
4732 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
4734 unsigned char OpFlag = 0;
4735 unsigned WrapperKind = X86ISD::Wrapper;
4736 CodeModel::Model M = getTargetMachine().getCodeModel();
4738 if (Subtarget->isPICStyleRIPRel() &&
4739 (M == CodeModel::Small || M == CodeModel::Kernel))
4740 WrapperKind = X86ISD::WrapperRIP;
4741 else if (Subtarget->isPICStyleGOT())
4742 OpFlag = X86II::MO_GOTOFF;
4743 else if (Subtarget->isPICStyleStubPIC())
4744 OpFlag = X86II::MO_PIC_BASE_OFFSET;
4746 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
4748 CP->getOffset(), OpFlag);
4749 DebugLoc DL = CP->getDebugLoc();
4750 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
4751 // With PIC, the address is actually $g + Offset.
4753 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
4754 DAG.getNode(X86ISD::GlobalBaseReg,
4755 DebugLoc::getUnknownLoc(), getPointerTy()),
4762 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) {
4763 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
4765 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
4767 unsigned char OpFlag = 0;
4768 unsigned WrapperKind = X86ISD::Wrapper;
4769 CodeModel::Model M = getTargetMachine().getCodeModel();
4771 if (Subtarget->isPICStyleRIPRel() &&
4772 (M == CodeModel::Small || M == CodeModel::Kernel))
4773 WrapperKind = X86ISD::WrapperRIP;
4774 else if (Subtarget->isPICStyleGOT())
4775 OpFlag = X86II::MO_GOTOFF;
4776 else if (Subtarget->isPICStyleStubPIC())
4777 OpFlag = X86II::MO_PIC_BASE_OFFSET;
4779 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
4781 DebugLoc DL = JT->getDebugLoc();
4782 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
4784 // With PIC, the address is actually $g + Offset.
4786 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
4787 DAG.getNode(X86ISD::GlobalBaseReg,
4788 DebugLoc::getUnknownLoc(), getPointerTy()),
4796 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) {
4797 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
4799 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
4801 unsigned char OpFlag = 0;
4802 unsigned WrapperKind = X86ISD::Wrapper;
4803 CodeModel::Model M = getTargetMachine().getCodeModel();
4805 if (Subtarget->isPICStyleRIPRel() &&
4806 (M == CodeModel::Small || M == CodeModel::Kernel))
4807 WrapperKind = X86ISD::WrapperRIP;
4808 else if (Subtarget->isPICStyleGOT())
4809 OpFlag = X86II::MO_GOTOFF;
4810 else if (Subtarget->isPICStyleStubPIC())
4811 OpFlag = X86II::MO_PIC_BASE_OFFSET;
4813 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
4815 DebugLoc DL = Op.getDebugLoc();
4816 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
4819 // With PIC, the address is actually $g + Offset.
4820 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
4821 !Subtarget->is64Bit()) {
4822 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
4823 DAG.getNode(X86ISD::GlobalBaseReg,
4824 DebugLoc::getUnknownLoc(),
4833 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) {
4834 // Create the TargetBlockAddressAddress node.
4835 unsigned char OpFlags =
4836 Subtarget->ClassifyBlockAddressReference();
4837 CodeModel::Model M = getTargetMachine().getCodeModel();
4838 BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
4839 DebugLoc dl = Op.getDebugLoc();
4840 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(),
4841 /*isTarget=*/true, OpFlags);
4843 if (Subtarget->isPICStyleRIPRel() &&
4844 (M == CodeModel::Small || M == CodeModel::Kernel))
4845 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
4847 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
4849 // With PIC, the address is actually $g + Offset.
4850 if (isGlobalRelativeToPICBase(OpFlags)) {
4851 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
4852 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
4860 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
4862 SelectionDAG &DAG) const {
4863 // Create the TargetGlobalAddress node, folding in the constant
4864 // offset if it is legal.
4865 unsigned char OpFlags =
4866 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
4867 CodeModel::Model M = getTargetMachine().getCodeModel();
4869 if (OpFlags == X86II::MO_NO_FLAG &&
4870 X86::isOffsetSuitableForCodeModel(Offset, M)) {
4871 // A direct static reference to a global.
4872 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), Offset);
4875 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), 0, OpFlags);
4878 if (Subtarget->isPICStyleRIPRel() &&
4879 (M == CodeModel::Small || M == CodeModel::Kernel))
4880 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
4882 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
4884 // With PIC, the address is actually $g + Offset.
4885 if (isGlobalRelativeToPICBase(OpFlags)) {
4886 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
4887 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
4891 // For globals that require a load from a stub to get the address, emit the
4893 if (isGlobalStubReference(OpFlags))
4894 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
4895 PseudoSourceValue::getGOT(), 0);
4897 // If there was a non-zero offset that we didn't fold, create an explicit
4900 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
4901 DAG.getConstant(Offset, getPointerTy()));
4907 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) {
4908 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
4909 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
4910 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
4914 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
4915 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
4916 unsigned char OperandFlags) {
4917 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4918 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
4919 DebugLoc dl = GA->getDebugLoc();
4920 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
4921 GA->getValueType(0),
4925 SDValue Ops[] = { Chain, TGA, *InFlag };
4926 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3);
4928 SDValue Ops[] = { Chain, TGA };
4929 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2);
4932 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
4933 MFI->setHasCalls(true);
4935 SDValue Flag = Chain.getValue(1);
4936 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
4939 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
4941 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
4944 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
4945 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
4946 DAG.getNode(X86ISD::GlobalBaseReg,
4947 DebugLoc::getUnknownLoc(),
4949 InFlag = Chain.getValue(1);
4951 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
4954 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
4956 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
4958 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
4959 X86::RAX, X86II::MO_TLSGD);
4962 // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
4963 // "local exec" model.
4964 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
4965 const EVT PtrVT, TLSModel::Model model,
4967 DebugLoc dl = GA->getDebugLoc();
4968 // Get the Thread Pointer
4969 SDValue Base = DAG.getNode(X86ISD::SegmentBaseAddress,
4970 DebugLoc::getUnknownLoc(), PtrVT,
4971 DAG.getRegister(is64Bit? X86::FS : X86::GS,
4974 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Base,
4977 unsigned char OperandFlags = 0;
4978 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
4980 unsigned WrapperKind = X86ISD::Wrapper;
4981 if (model == TLSModel::LocalExec) {
4982 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
4983 } else if (is64Bit) {
4984 assert(model == TLSModel::InitialExec);
4985 OperandFlags = X86II::MO_GOTTPOFF;
4986 WrapperKind = X86ISD::WrapperRIP;
4988 assert(model == TLSModel::InitialExec);
4989 OperandFlags = X86II::MO_INDNTPOFF;
4992 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
4994 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), GA->getValueType(0),
4995 GA->getOffset(), OperandFlags);
4996 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
4998 if (model == TLSModel::InitialExec)
4999 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
5000 PseudoSourceValue::getGOT(), 0);
5002 // The address of the thread local variable is the add of the thread
5003 // pointer with the offset of the variable.
5004 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
5008 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) {
5009 // TODO: implement the "local dynamic" model
5010 // TODO: implement the "initial exec"model for pic executables
5011 assert(Subtarget->isTargetELF() &&
5012 "TLS not implemented for non-ELF targets");
5013 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
5014 const GlobalValue *GV = GA->getGlobal();
5016 // If GV is an alias then use the aliasee for determining
5017 // thread-localness.
5018 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
5019 GV = GA->resolveAliasedGlobal(false);
5021 TLSModel::Model model = getTLSModel(GV,
5022 getTargetMachine().getRelocationModel());
5025 case TLSModel::GeneralDynamic:
5026 case TLSModel::LocalDynamic: // not implemented
5027 if (Subtarget->is64Bit())
5028 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
5029 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
5031 case TLSModel::InitialExec:
5032 case TLSModel::LocalExec:
5033 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
5034 Subtarget->is64Bit());
5037 llvm_unreachable("Unreachable");
5042 /// LowerShift - Lower SRA_PARTS and friends, which return two i32 values and
5043 /// take a 2 x i32 value to shift plus a shift amount.
5044 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) {
5045 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
5046 EVT VT = Op.getValueType();
5047 unsigned VTBits = VT.getSizeInBits();
5048 DebugLoc dl = Op.getDebugLoc();
5049 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
5050 SDValue ShOpLo = Op.getOperand(0);
5051 SDValue ShOpHi = Op.getOperand(1);
5052 SDValue ShAmt = Op.getOperand(2);
5053 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
5054 DAG.getConstant(VTBits - 1, MVT::i8))
5055 : DAG.getConstant(0, VT);
5058 if (Op.getOpcode() == ISD::SHL_PARTS) {
5059 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
5060 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
5062 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
5063 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
5066 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
5067 DAG.getConstant(VTBits, MVT::i8));
5068 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, VT,
5069 AndNode, DAG.getConstant(0, MVT::i8));
5072 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
5073 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
5074 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
5076 if (Op.getOpcode() == ISD::SHL_PARTS) {
5077 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
5078 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
5080 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
5081 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
5084 SDValue Ops[2] = { Lo, Hi };
5085 return DAG.getMergeValues(Ops, 2, dl);
5088 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
5089 EVT SrcVT = Op.getOperand(0).getValueType();
5091 if (SrcVT.isVector()) {
5092 if (SrcVT == MVT::v2i32 && Op.getValueType() == MVT::v2f64) {
5098 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
5099 "Unknown SINT_TO_FP to lower!");
5101 // These are really Legal; return the operand so the caller accepts it as
5103 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
5105 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
5106 Subtarget->is64Bit()) {
5110 DebugLoc dl = Op.getDebugLoc();
5111 unsigned Size = SrcVT.getSizeInBits()/8;
5112 MachineFunction &MF = DAG.getMachineFunction();
5113 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
5114 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5115 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
5117 PseudoSourceValue::getFixedStack(SSFI), 0);
5118 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
5121 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
5123 SelectionDAG &DAG) {
5125 DebugLoc dl = Op.getDebugLoc();
5127 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
5129 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag);
5131 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
5132 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
5133 SDValue Result = DAG.getNode(useSSE ? X86ISD::FILD_FLAG : X86ISD::FILD, dl,
5134 Tys, Ops, array_lengthof(Ops));
5137 Chain = Result.getValue(1);
5138 SDValue InFlag = Result.getValue(2);
5140 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
5141 // shouldn't be necessary except that RFP cannot be live across
5142 // multiple blocks. When stackifier is fixed, they can be uncoupled.
5143 MachineFunction &MF = DAG.getMachineFunction();
5144 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
5145 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5146 Tys = DAG.getVTList(MVT::Other);
5148 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
5150 Chain = DAG.getNode(X86ISD::FST, dl, Tys, Ops, array_lengthof(Ops));
5151 Result = DAG.getLoad(Op.getValueType(), dl, Chain, StackSlot,
5152 PseudoSourceValue::getFixedStack(SSFI), 0);
5158 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
5159 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) {
5160 // This algorithm is not obvious. Here it is in C code, more or less:
5162 double uint64_to_double( uint32_t hi, uint32_t lo ) {
5163 static const __m128i exp = { 0x4330000045300000ULL, 0 };
5164 static const __m128d bias = { 0x1.0p84, 0x1.0p52 };
5166 // Copy ints to xmm registers.
5167 __m128i xh = _mm_cvtsi32_si128( hi );
5168 __m128i xl = _mm_cvtsi32_si128( lo );
5170 // Combine into low half of a single xmm register.
5171 __m128i x = _mm_unpacklo_epi32( xh, xl );
5175 // Merge in appropriate exponents to give the integer bits the right
5177 x = _mm_unpacklo_epi32( x, exp );
5179 // Subtract away the biases to deal with the IEEE-754 double precision
5181 d = _mm_sub_pd( (__m128d) x, bias );
5183 // All conversions up to here are exact. The correctly rounded result is
5184 // calculated using the current rounding mode using the following
5186 d = _mm_add_sd( d, _mm_unpackhi_pd( d, d ) );
5187 _mm_store_sd( &sd, d ); // Because we are returning doubles in XMM, this
5188 // store doesn't really need to be here (except
5189 // maybe to zero the other double)
5194 DebugLoc dl = Op.getDebugLoc();
5195 LLVMContext *Context = DAG.getContext();
5197 // Build some magic constants.
5198 std::vector<Constant*> CV0;
5199 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x45300000)));
5200 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x43300000)));
5201 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
5202 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
5203 Constant *C0 = ConstantVector::get(CV0);
5204 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
5206 std::vector<Constant*> CV1;
5208 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL))));
5210 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL))));
5211 Constant *C1 = ConstantVector::get(CV1);
5212 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
5214 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
5215 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
5217 DAG.getIntPtrConstant(1)));
5218 SDValue XR2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
5219 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
5221 DAG.getIntPtrConstant(0)));
5222 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, XR1, XR2);
5223 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
5224 PseudoSourceValue::getConstantPool(), 0,
5226 SDValue Unpck2 = getUnpackl(DAG, dl, MVT::v4i32, Unpck1, CLod0);
5227 SDValue XR2F = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Unpck2);
5228 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
5229 PseudoSourceValue::getConstantPool(), 0,
5231 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
5233 // Add the halves; easiest way is to swap them into another reg first.
5234 int ShufMask[2] = { 1, -1 };
5235 SDValue Shuf = DAG.getVectorShuffle(MVT::v2f64, dl, Sub,
5236 DAG.getUNDEF(MVT::v2f64), ShufMask);
5237 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::v2f64, Shuf, Sub);
5238 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Add,
5239 DAG.getIntPtrConstant(0));
5242 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
5243 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) {
5244 DebugLoc dl = Op.getDebugLoc();
5245 // FP constant to bias correct the final result.
5246 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
5249 // Load the 32-bit value into an XMM register.
5250 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
5251 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
5253 DAG.getIntPtrConstant(0)));
5255 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
5256 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Load),
5257 DAG.getIntPtrConstant(0));
5259 // Or the load with the bias.
5260 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
5261 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
5262 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5264 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
5265 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5266 MVT::v2f64, Bias)));
5267 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
5268 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Or),
5269 DAG.getIntPtrConstant(0));
5271 // Subtract the bias.
5272 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
5274 // Handle final rounding.
5275 EVT DestVT = Op.getValueType();
5277 if (DestVT.bitsLT(MVT::f64)) {
5278 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
5279 DAG.getIntPtrConstant(0));
5280 } else if (DestVT.bitsGT(MVT::f64)) {
5281 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
5284 // Handle final rounding.
5288 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
5289 SDValue N0 = Op.getOperand(0);
5290 DebugLoc dl = Op.getDebugLoc();
5292 // Now not UINT_TO_FP is legal (it's marked custom), dag combiner won't
5293 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
5294 // the optimization here.
5295 if (DAG.SignBitIsZero(N0))
5296 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
5298 EVT SrcVT = N0.getValueType();
5299 if (SrcVT == MVT::i64) {
5300 // We only handle SSE2 f64 target here; caller can expand the rest.
5301 if (Op.getValueType() != MVT::f64 || !X86ScalarSSEf64)
5304 return LowerUINT_TO_FP_i64(Op, DAG);
5305 } else if (SrcVT == MVT::i32 && X86ScalarSSEf64) {
5306 return LowerUINT_TO_FP_i32(Op, DAG);
5309 assert(SrcVT == MVT::i32 && "Unknown UINT_TO_FP to lower!");
5311 // Make a 64-bit buffer, and use it to build an FILD.
5312 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
5313 SDValue WordOff = DAG.getConstant(4, getPointerTy());
5314 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
5315 getPointerTy(), StackSlot, WordOff);
5316 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
5317 StackSlot, NULL, 0);
5318 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
5319 OffsetSlot, NULL, 0);
5320 return BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
5323 std::pair<SDValue,SDValue> X86TargetLowering::
5324 FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) {
5325 DebugLoc dl = Op.getDebugLoc();
5327 EVT DstTy = Op.getValueType();
5330 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
5334 assert(DstTy.getSimpleVT() <= MVT::i64 &&
5335 DstTy.getSimpleVT() >= MVT::i16 &&
5336 "Unknown FP_TO_SINT to lower!");
5338 // These are really Legal.
5339 if (DstTy == MVT::i32 &&
5340 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
5341 return std::make_pair(SDValue(), SDValue());
5342 if (Subtarget->is64Bit() &&
5343 DstTy == MVT::i64 &&
5344 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
5345 return std::make_pair(SDValue(), SDValue());
5347 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
5349 MachineFunction &MF = DAG.getMachineFunction();
5350 unsigned MemSize = DstTy.getSizeInBits()/8;
5351 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
5352 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5355 switch (DstTy.getSimpleVT().SimpleTy) {
5356 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
5357 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
5358 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
5359 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
5362 SDValue Chain = DAG.getEntryNode();
5363 SDValue Value = Op.getOperand(0);
5364 if (isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) {
5365 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
5366 Chain = DAG.getStore(Chain, dl, Value, StackSlot,
5367 PseudoSourceValue::getFixedStack(SSFI), 0);
5368 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
5370 Chain, StackSlot, DAG.getValueType(Op.getOperand(0).getValueType())
5372 Value = DAG.getNode(X86ISD::FLD, dl, Tys, Ops, 3);
5373 Chain = Value.getValue(1);
5374 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
5375 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5378 // Build the FP_TO_INT*_IN_MEM
5379 SDValue Ops[] = { Chain, Value, StackSlot };
5380 SDValue FIST = DAG.getNode(Opc, dl, MVT::Other, Ops, 3);
5382 return std::make_pair(FIST, StackSlot);
5385 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) {
5386 if (Op.getValueType().isVector()) {
5387 if (Op.getValueType() == MVT::v2i32 &&
5388 Op.getOperand(0).getValueType() == MVT::v2f64) {
5394 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, true);
5395 SDValue FIST = Vals.first, StackSlot = Vals.second;
5396 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
5397 if (FIST.getNode() == 0) return Op;
5400 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
5401 FIST, StackSlot, NULL, 0);
5404 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) {
5405 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, false);
5406 SDValue FIST = Vals.first, StackSlot = Vals.second;
5407 assert(FIST.getNode() && "Unexpected failure");
5410 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
5411 FIST, StackSlot, NULL, 0);
5414 SDValue X86TargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) {
5415 LLVMContext *Context = DAG.getContext();
5416 DebugLoc dl = Op.getDebugLoc();
5417 EVT VT = Op.getValueType();
5420 EltVT = VT.getVectorElementType();
5421 std::vector<Constant*> CV;
5422 if (EltVT == MVT::f64) {
5423 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))));
5427 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))));
5433 Constant *C = ConstantVector::get(CV);
5434 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5435 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
5436 PseudoSourceValue::getConstantPool(), 0,
5438 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
5441 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) {
5442 LLVMContext *Context = DAG.getContext();
5443 DebugLoc dl = Op.getDebugLoc();
5444 EVT VT = Op.getValueType();
5447 EltVT = VT.getVectorElementType();
5448 std::vector<Constant*> CV;
5449 if (EltVT == MVT::f64) {
5450 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)));
5454 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)));
5460 Constant *C = ConstantVector::get(CV);
5461 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5462 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
5463 PseudoSourceValue::getConstantPool(), 0,
5465 if (VT.isVector()) {
5466 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
5467 DAG.getNode(ISD::XOR, dl, MVT::v2i64,
5468 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
5470 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, Mask)));
5472 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
5476 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
5477 LLVMContext *Context = DAG.getContext();
5478 SDValue Op0 = Op.getOperand(0);
5479 SDValue Op1 = Op.getOperand(1);
5480 DebugLoc dl = Op.getDebugLoc();
5481 EVT VT = Op.getValueType();
5482 EVT SrcVT = Op1.getValueType();
5484 // If second operand is smaller, extend it first.
5485 if (SrcVT.bitsLT(VT)) {
5486 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
5489 // And if it is bigger, shrink it first.
5490 if (SrcVT.bitsGT(VT)) {
5491 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
5495 // At this point the operands and the result should have the same
5496 // type, and that won't be f80 since that is not custom lowered.
5498 // First get the sign bit of second operand.
5499 std::vector<Constant*> CV;
5500 if (SrcVT == MVT::f64) {
5501 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))));
5502 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
5504 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))));
5505 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5506 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5507 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5509 Constant *C = ConstantVector::get(CV);
5510 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5511 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
5512 PseudoSourceValue::getConstantPool(), 0,
5514 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
5516 // Shift sign bit right or left if the two operands have different types.
5517 if (SrcVT.bitsGT(VT)) {
5518 // Op0 is MVT::f32, Op1 is MVT::f64.
5519 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
5520 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
5521 DAG.getConstant(32, MVT::i32));
5522 SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4f32, SignBit);
5523 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
5524 DAG.getIntPtrConstant(0));
5527 // Clear first operand sign bit.
5529 if (VT == MVT::f64) {
5530 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
5531 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
5533 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
5534 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5535 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5536 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5538 C = ConstantVector::get(CV);
5539 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5540 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
5541 PseudoSourceValue::getConstantPool(), 0,
5543 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
5545 // Or the value with the sign bit.
5546 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
5549 /// Emit nodes that will be selected as "test Op0,Op0", or something
5551 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
5552 SelectionDAG &DAG) {
5553 DebugLoc dl = Op.getDebugLoc();
5555 // CF and OF aren't always set the way we want. Determine which
5556 // of these we need.
5557 bool NeedCF = false;
5558 bool NeedOF = false;
5560 case X86::COND_A: case X86::COND_AE:
5561 case X86::COND_B: case X86::COND_BE:
5564 case X86::COND_G: case X86::COND_GE:
5565 case X86::COND_L: case X86::COND_LE:
5566 case X86::COND_O: case X86::COND_NO:
5572 // See if we can use the EFLAGS value from the operand instead of
5573 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
5574 // we prove that the arithmetic won't overflow, we can't use OF or CF.
5575 if (Op.getResNo() == 0 && !NeedOF && !NeedCF) {
5576 unsigned Opcode = 0;
5577 unsigned NumOperands = 0;
5578 switch (Op.getNode()->getOpcode()) {
5580 // Due to an isel shortcoming, be conservative if this add is likely to
5581 // be selected as part of a load-modify-store instruction. When the root
5582 // node in a match is a store, isel doesn't know how to remap non-chain
5583 // non-flag uses of other nodes in the match, such as the ADD in this
5584 // case. This leads to the ADD being left around and reselected, with
5585 // the result being two adds in the output.
5586 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
5587 UE = Op.getNode()->use_end(); UI != UE; ++UI)
5588 if (UI->getOpcode() == ISD::STORE)
5590 if (ConstantSDNode *C =
5591 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) {
5592 // An add of one will be selected as an INC.
5593 if (C->getAPIntValue() == 1) {
5594 Opcode = X86ISD::INC;
5598 // An add of negative one (subtract of one) will be selected as a DEC.
5599 if (C->getAPIntValue().isAllOnesValue()) {
5600 Opcode = X86ISD::DEC;
5605 // Otherwise use a regular EFLAGS-setting add.
5606 Opcode = X86ISD::ADD;
5610 // If the primary and result isn't used, don't bother using X86ISD::AND,
5611 // because a TEST instruction will be better.
5612 bool NonFlagUse = false;
5613 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
5614 UE = Op.getNode()->use_end(); UI != UE; ++UI)
5615 if (UI->getOpcode() != ISD::BRCOND &&
5616 (UI->getOpcode() != ISD::SELECT || UI.getOperandNo() != 0) &&
5617 UI->getOpcode() != ISD::SETCC) {
5628 // Due to the ISEL shortcoming noted above, be conservative if this op is
5629 // likely to be selected as part of a load-modify-store instruction.
5630 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
5631 UE = Op.getNode()->use_end(); UI != UE; ++UI)
5632 if (UI->getOpcode() == ISD::STORE)
5634 // Otherwise use a regular EFLAGS-setting instruction.
5635 switch (Op.getNode()->getOpcode()) {
5636 case ISD::SUB: Opcode = X86ISD::SUB; break;
5637 case ISD::OR: Opcode = X86ISD::OR; break;
5638 case ISD::XOR: Opcode = X86ISD::XOR; break;
5639 case ISD::AND: Opcode = X86ISD::AND; break;
5640 default: llvm_unreachable("unexpected operator!");
5651 return SDValue(Op.getNode(), 1);
5657 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
5658 SmallVector<SDValue, 4> Ops;
5659 for (unsigned i = 0; i != NumOperands; ++i)
5660 Ops.push_back(Op.getOperand(i));
5661 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
5662 DAG.ReplaceAllUsesWith(Op, New);
5663 return SDValue(New.getNode(), 1);
5667 // Otherwise just emit a CMP with 0, which is the TEST pattern.
5668 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
5669 DAG.getConstant(0, Op.getValueType()));
5672 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
5674 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
5675 SelectionDAG &DAG) {
5676 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
5677 if (C->getAPIntValue() == 0)
5678 return EmitTest(Op0, X86CC, DAG);
5680 DebugLoc dl = Op0.getDebugLoc();
5681 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
5684 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
5685 /// if it's possible.
5686 static SDValue LowerToBT(SDValue Op0, ISD::CondCode CC,
5687 DebugLoc dl, SelectionDAG &DAG) {
5689 if (Op0.getOperand(1).getOpcode() == ISD::SHL) {
5690 if (ConstantSDNode *Op010C =
5691 dyn_cast<ConstantSDNode>(Op0.getOperand(1).getOperand(0)))
5692 if (Op010C->getZExtValue() == 1) {
5693 LHS = Op0.getOperand(0);
5694 RHS = Op0.getOperand(1).getOperand(1);
5696 } else if (Op0.getOperand(0).getOpcode() == ISD::SHL) {
5697 if (ConstantSDNode *Op000C =
5698 dyn_cast<ConstantSDNode>(Op0.getOperand(0).getOperand(0)))
5699 if (Op000C->getZExtValue() == 1) {
5700 LHS = Op0.getOperand(1);
5701 RHS = Op0.getOperand(0).getOperand(1);
5703 } else if (Op0.getOperand(1).getOpcode() == ISD::Constant) {
5704 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op0.getOperand(1));
5705 SDValue AndLHS = Op0.getOperand(0);
5706 if (AndRHS->getZExtValue() == 1 && AndLHS.getOpcode() == ISD::SRL) {
5707 LHS = AndLHS.getOperand(0);
5708 RHS = AndLHS.getOperand(1);
5712 if (LHS.getNode()) {
5713 // If LHS is i8, promote it to i16 with any_extend. There is no i8 BT
5714 // instruction. Since the shift amount is in-range-or-undefined, we know
5715 // that doing a bittest on the i16 value is ok. We extend to i32 because
5716 // the encoding for the i16 version is larger than the i32 version.
5717 if (LHS.getValueType() == MVT::i8)
5718 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
5720 // If the operand types disagree, extend the shift amount to match. Since
5721 // BT ignores high bits (like shifts) we can use anyextend.
5722 if (LHS.getValueType() != RHS.getValueType())
5723 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
5725 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
5726 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
5727 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
5728 DAG.getConstant(Cond, MVT::i8), BT);
5734 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) {
5735 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
5736 SDValue Op0 = Op.getOperand(0);
5737 SDValue Op1 = Op.getOperand(1);
5738 DebugLoc dl = Op.getDebugLoc();
5739 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
5741 // Optimize to BT if possible.
5742 // Lower (X & (1 << N)) == 0 to BT(X, N).
5743 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
5744 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
5745 if (Op0.getOpcode() == ISD::AND &&
5747 Op1.getOpcode() == ISD::Constant &&
5748 cast<ConstantSDNode>(Op1)->getZExtValue() == 0 &&
5749 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
5750 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
5751 if (NewSetCC.getNode())
5755 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
5756 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
5757 if (X86CC == X86::COND_INVALID)
5760 SDValue Cond = EmitCmp(Op0, Op1, X86CC, DAG);
5762 // Use sbb x, x to materialize carry bit into a GPR.
5763 if (X86CC == X86::COND_B)
5764 return DAG.getNode(ISD::AND, dl, MVT::i8,
5765 DAG.getNode(X86ISD::SETCC_CARRY, dl, MVT::i8,
5766 DAG.getConstant(X86CC, MVT::i8), Cond),
5767 DAG.getConstant(1, MVT::i8));
5769 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
5770 DAG.getConstant(X86CC, MVT::i8), Cond);
5773 SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
5775 SDValue Op0 = Op.getOperand(0);
5776 SDValue Op1 = Op.getOperand(1);
5777 SDValue CC = Op.getOperand(2);
5778 EVT VT = Op.getValueType();
5779 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
5780 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
5781 DebugLoc dl = Op.getDebugLoc();
5785 EVT VT0 = Op0.getValueType();
5786 assert(VT0 == MVT::v4f32 || VT0 == MVT::v2f64);
5787 unsigned Opc = VT0 == MVT::v4f32 ? X86ISD::CMPPS : X86ISD::CMPPD;
5790 switch (SetCCOpcode) {
5793 case ISD::SETEQ: SSECC = 0; break;
5795 case ISD::SETGT: Swap = true; // Fallthrough
5797 case ISD::SETOLT: SSECC = 1; break;
5799 case ISD::SETGE: Swap = true; // Fallthrough
5801 case ISD::SETOLE: SSECC = 2; break;
5802 case ISD::SETUO: SSECC = 3; break;
5804 case ISD::SETNE: SSECC = 4; break;
5805 case ISD::SETULE: Swap = true;
5806 case ISD::SETUGE: SSECC = 5; break;
5807 case ISD::SETULT: Swap = true;
5808 case ISD::SETUGT: SSECC = 6; break;
5809 case ISD::SETO: SSECC = 7; break;
5812 std::swap(Op0, Op1);
5814 // In the two special cases we can't handle, emit two comparisons.
5816 if (SetCCOpcode == ISD::SETUEQ) {
5818 UNORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(3, MVT::i8));
5819 EQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(0, MVT::i8));
5820 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ);
5822 else if (SetCCOpcode == ISD::SETONE) {
5824 ORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(7, MVT::i8));
5825 NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, MVT::i8));
5826 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ);
5828 llvm_unreachable("Illegal FP comparison");
5830 // Handle all other FP comparisons here.
5831 return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8));
5834 // We are handling one of the integer comparisons here. Since SSE only has
5835 // GT and EQ comparisons for integer, swapping operands and multiple
5836 // operations may be required for some comparisons.
5837 unsigned Opc = 0, EQOpc = 0, GTOpc = 0;
5838 bool Swap = false, Invert = false, FlipSigns = false;
5840 switch (VT.getSimpleVT().SimpleTy) {
5843 case MVT::v16i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break;
5845 case MVT::v8i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break;
5847 case MVT::v4i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break;
5848 case MVT::v2i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break;
5851 switch (SetCCOpcode) {
5853 case ISD::SETNE: Invert = true;
5854 case ISD::SETEQ: Opc = EQOpc; break;
5855 case ISD::SETLT: Swap = true;
5856 case ISD::SETGT: Opc = GTOpc; break;
5857 case ISD::SETGE: Swap = true;
5858 case ISD::SETLE: Opc = GTOpc; Invert = true; break;
5859 case ISD::SETULT: Swap = true;
5860 case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break;
5861 case ISD::SETUGE: Swap = true;
5862 case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break;
5865 std::swap(Op0, Op1);
5867 // Since SSE has no unsigned integer comparisons, we need to flip the sign
5868 // bits of the inputs before performing those operations.
5870 EVT EltVT = VT.getVectorElementType();
5871 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
5873 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
5874 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
5876 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
5877 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
5880 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
5882 // If the logical-not of the result is required, perform that now.
5884 Result = DAG.getNOT(dl, Result, VT);
5889 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
5890 static bool isX86LogicalCmp(SDValue Op) {
5891 unsigned Opc = Op.getNode()->getOpcode();
5892 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI)
5894 if (Op.getResNo() == 1 &&
5895 (Opc == X86ISD::ADD ||
5896 Opc == X86ISD::SUB ||
5897 Opc == X86ISD::SMUL ||
5898 Opc == X86ISD::UMUL ||
5899 Opc == X86ISD::INC ||
5900 Opc == X86ISD::DEC ||
5901 Opc == X86ISD::OR ||
5902 Opc == X86ISD::XOR ||
5903 Opc == X86ISD::AND))
5909 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) {
5910 bool addTest = true;
5911 SDValue Cond = Op.getOperand(0);
5912 DebugLoc dl = Op.getDebugLoc();
5915 if (Cond.getOpcode() == ISD::SETCC) {
5916 SDValue NewCond = LowerSETCC(Cond, DAG);
5917 if (NewCond.getNode())
5921 // Look pass (and (setcc_carry (cmp ...)), 1).
5922 if (Cond.getOpcode() == ISD::AND &&
5923 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
5924 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
5925 if (C && C->getAPIntValue() == 1)
5926 Cond = Cond.getOperand(0);
5929 // If condition flag is set by a X86ISD::CMP, then use it as the condition
5930 // setting operand in place of the X86ISD::SETCC.
5931 if (Cond.getOpcode() == X86ISD::SETCC ||
5932 Cond.getOpcode() == X86ISD::SETCC_CARRY) {
5933 CC = Cond.getOperand(0);
5935 SDValue Cmp = Cond.getOperand(1);
5936 unsigned Opc = Cmp.getOpcode();
5937 EVT VT = Op.getValueType();
5939 bool IllegalFPCMov = false;
5940 if (VT.isFloatingPoint() && !VT.isVector() &&
5941 !isScalarFPTypeInSSEReg(VT)) // FPStack?
5942 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
5944 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
5945 Opc == X86ISD::BT) { // FIXME
5952 // Look pass the truncate.
5953 if (Cond.getOpcode() == ISD::TRUNCATE)
5954 Cond = Cond.getOperand(0);
5956 // We know the result of AND is compared against zero. Try to match
5958 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
5959 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
5960 if (NewSetCC.getNode()) {
5961 CC = NewSetCC.getOperand(0);
5962 Cond = NewSetCC.getOperand(1);
5969 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
5970 Cond = EmitTest(Cond, X86::COND_NE, DAG);
5973 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag);
5974 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
5975 // condition is true.
5976 SDValue Ops[] = { Op.getOperand(2), Op.getOperand(1), CC, Cond };
5977 return DAG.getNode(X86ISD::CMOV, dl, VTs, Ops, array_lengthof(Ops));
5980 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
5981 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
5982 // from the AND / OR.
5983 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
5984 Opc = Op.getOpcode();
5985 if (Opc != ISD::OR && Opc != ISD::AND)
5987 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
5988 Op.getOperand(0).hasOneUse() &&
5989 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
5990 Op.getOperand(1).hasOneUse());
5993 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
5994 // 1 and that the SETCC node has a single use.
5995 static bool isXor1OfSetCC(SDValue Op) {
5996 if (Op.getOpcode() != ISD::XOR)
5998 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
5999 if (N1C && N1C->getAPIntValue() == 1) {
6000 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
6001 Op.getOperand(0).hasOneUse();
6006 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) {
6007 bool addTest = true;
6008 SDValue Chain = Op.getOperand(0);
6009 SDValue Cond = Op.getOperand(1);
6010 SDValue Dest = Op.getOperand(2);
6011 DebugLoc dl = Op.getDebugLoc();
6014 if (Cond.getOpcode() == ISD::SETCC) {
6015 SDValue NewCond = LowerSETCC(Cond, DAG);
6016 if (NewCond.getNode())
6020 // FIXME: LowerXALUO doesn't handle these!!
6021 else if (Cond.getOpcode() == X86ISD::ADD ||
6022 Cond.getOpcode() == X86ISD::SUB ||
6023 Cond.getOpcode() == X86ISD::SMUL ||
6024 Cond.getOpcode() == X86ISD::UMUL)
6025 Cond = LowerXALUO(Cond, DAG);
6028 // Look pass (and (setcc_carry (cmp ...)), 1).
6029 if (Cond.getOpcode() == ISD::AND &&
6030 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
6031 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
6032 if (C && C->getAPIntValue() == 1)
6033 Cond = Cond.getOperand(0);
6036 // If condition flag is set by a X86ISD::CMP, then use it as the condition
6037 // setting operand in place of the X86ISD::SETCC.
6038 if (Cond.getOpcode() == X86ISD::SETCC ||
6039 Cond.getOpcode() == X86ISD::SETCC_CARRY) {
6040 CC = Cond.getOperand(0);
6042 SDValue Cmp = Cond.getOperand(1);
6043 unsigned Opc = Cmp.getOpcode();
6044 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
6045 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
6049 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
6053 // These can only come from an arithmetic instruction with overflow,
6054 // e.g. SADDO, UADDO.
6055 Cond = Cond.getNode()->getOperand(1);
6062 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
6063 SDValue Cmp = Cond.getOperand(0).getOperand(1);
6064 if (CondOpc == ISD::OR) {
6065 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
6066 // two branches instead of an explicit OR instruction with a
6068 if (Cmp == Cond.getOperand(1).getOperand(1) &&
6069 isX86LogicalCmp(Cmp)) {
6070 CC = Cond.getOperand(0).getOperand(0);
6071 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
6072 Chain, Dest, CC, Cmp);
6073 CC = Cond.getOperand(1).getOperand(0);
6077 } else { // ISD::AND
6078 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
6079 // two branches instead of an explicit AND instruction with a
6080 // separate test. However, we only do this if this block doesn't
6081 // have a fall-through edge, because this requires an explicit
6082 // jmp when the condition is false.
6083 if (Cmp == Cond.getOperand(1).getOperand(1) &&
6084 isX86LogicalCmp(Cmp) &&
6085 Op.getNode()->hasOneUse()) {
6086 X86::CondCode CCode =
6087 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
6088 CCode = X86::GetOppositeBranchCondition(CCode);
6089 CC = DAG.getConstant(CCode, MVT::i8);
6090 SDValue User = SDValue(*Op.getNode()->use_begin(), 0);
6091 // Look for an unconditional branch following this conditional branch.
6092 // We need this because we need to reverse the successors in order
6093 // to implement FCMP_OEQ.
6094 if (User.getOpcode() == ISD::BR) {
6095 SDValue FalseBB = User.getOperand(1);
6097 DAG.UpdateNodeOperands(User, User.getOperand(0), Dest);
6098 assert(NewBR == User);
6101 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
6102 Chain, Dest, CC, Cmp);
6103 X86::CondCode CCode =
6104 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
6105 CCode = X86::GetOppositeBranchCondition(CCode);
6106 CC = DAG.getConstant(CCode, MVT::i8);
6112 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
6113 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
6114 // It should be transformed during dag combiner except when the condition
6115 // is set by a arithmetics with overflow node.
6116 X86::CondCode CCode =
6117 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
6118 CCode = X86::GetOppositeBranchCondition(CCode);
6119 CC = DAG.getConstant(CCode, MVT::i8);
6120 Cond = Cond.getOperand(0).getOperand(1);
6126 // Look pass the truncate.
6127 if (Cond.getOpcode() == ISD::TRUNCATE)
6128 Cond = Cond.getOperand(0);
6130 // We know the result of AND is compared against zero. Try to match
6132 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
6133 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
6134 if (NewSetCC.getNode()) {
6135 CC = NewSetCC.getOperand(0);
6136 Cond = NewSetCC.getOperand(1);
6143 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
6144 Cond = EmitTest(Cond, X86::COND_NE, DAG);
6146 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
6147 Chain, Dest, CC, Cond);
6151 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
6152 // Calls to _alloca is needed to probe the stack when allocating more than 4k
6153 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
6154 // that the guard pages used by the OS virtual memory manager are allocated in
6155 // correct sequence.
6157 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
6158 SelectionDAG &DAG) {
6159 assert(Subtarget->isTargetCygMing() &&
6160 "This should be used only on Cygwin/Mingw targets");
6161 DebugLoc dl = Op.getDebugLoc();
6164 SDValue Chain = Op.getOperand(0);
6165 SDValue Size = Op.getOperand(1);
6166 // FIXME: Ensure alignment here
6170 EVT IntPtr = getPointerTy();
6171 EVT SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32;
6173 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
6175 Chain = DAG.getCopyToReg(Chain, dl, X86::EAX, Size, Flag);
6176 Flag = Chain.getValue(1);
6178 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
6179 SDValue Ops[] = { Chain,
6180 DAG.getTargetExternalSymbol("_alloca", IntPtr),
6181 DAG.getRegister(X86::EAX, IntPtr),
6182 DAG.getRegister(X86StackPtr, SPTy),
6184 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops, 5);
6185 Flag = Chain.getValue(1);
6187 Chain = DAG.getCALLSEQ_END(Chain,
6188 DAG.getIntPtrConstant(0, true),
6189 DAG.getIntPtrConstant(0, true),
6192 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1);
6194 SDValue Ops1[2] = { Chain.getValue(0), Chain };
6195 return DAG.getMergeValues(Ops1, 2, dl);
6199 X86TargetLowering::EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl,
6201 SDValue Dst, SDValue Src,
6202 SDValue Size, unsigned Align,
6204 uint64_t DstSVOff) {
6205 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
6207 // If not DWORD aligned or size is more than the threshold, call the library.
6208 // The libc version is likely to be faster for these cases. It can use the
6209 // address value and run time information about the CPU.
6210 if ((Align & 3) != 0 ||
6212 ConstantSize->getZExtValue() >
6213 getSubtarget()->getMaxInlineSizeThreshold()) {
6214 SDValue InFlag(0, 0);
6216 // Check to see if there is a specialized entry-point for memory zeroing.
6217 ConstantSDNode *V = dyn_cast<ConstantSDNode>(Src);
6219 if (const char *bzeroEntry = V &&
6220 V->isNullValue() ? Subtarget->getBZeroEntry() : 0) {
6221 EVT IntPtr = getPointerTy();
6222 const Type *IntPtrTy = TD->getIntPtrType(*DAG.getContext());
6223 TargetLowering::ArgListTy Args;
6224 TargetLowering::ArgListEntry Entry;
6226 Entry.Ty = IntPtrTy;
6227 Args.push_back(Entry);
6229 Args.push_back(Entry);
6230 std::pair<SDValue,SDValue> CallResult =
6231 LowerCallTo(Chain, Type::getVoidTy(*DAG.getContext()),
6232 false, false, false, false,
6233 0, CallingConv::C, false, /*isReturnValueUsed=*/false,
6234 DAG.getExternalSymbol(bzeroEntry, IntPtr), Args, DAG, dl,
6235 DAG.GetOrdering(Chain.getNode()));
6236 return CallResult.second;
6239 // Otherwise have the target-independent code call memset.
6243 uint64_t SizeVal = ConstantSize->getZExtValue();
6244 SDValue InFlag(0, 0);
6247 ConstantSDNode *ValC = dyn_cast<ConstantSDNode>(Src);
6248 unsigned BytesLeft = 0;
6249 bool TwoRepStos = false;
6252 uint64_t Val = ValC->getZExtValue() & 255;
6254 // If the value is a constant, then we can potentially use larger sets.
6255 switch (Align & 3) {
6256 case 2: // WORD aligned
6259 Val = (Val << 8) | Val;
6261 case 0: // DWORD aligned
6264 Val = (Val << 8) | Val;
6265 Val = (Val << 16) | Val;
6266 if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) { // QWORD aligned
6269 Val = (Val << 32) | Val;
6272 default: // Byte aligned
6275 Count = DAG.getIntPtrConstant(SizeVal);
6279 if (AVT.bitsGT(MVT::i8)) {
6280 unsigned UBytes = AVT.getSizeInBits() / 8;
6281 Count = DAG.getIntPtrConstant(SizeVal / UBytes);
6282 BytesLeft = SizeVal % UBytes;
6285 Chain = DAG.getCopyToReg(Chain, dl, ValReg, DAG.getConstant(Val, AVT),
6287 InFlag = Chain.getValue(1);
6290 Count = DAG.getIntPtrConstant(SizeVal);
6291 Chain = DAG.getCopyToReg(Chain, dl, X86::AL, Src, InFlag);
6292 InFlag = Chain.getValue(1);
6295 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RCX :
6298 InFlag = Chain.getValue(1);
6299 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RDI :
6302 InFlag = Chain.getValue(1);
6304 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6305 SDValue Ops[] = { Chain, DAG.getValueType(AVT), InFlag };
6306 Chain = DAG.getNode(X86ISD::REP_STOS, dl, Tys, Ops, array_lengthof(Ops));
6309 InFlag = Chain.getValue(1);
6311 EVT CVT = Count.getValueType();
6312 SDValue Left = DAG.getNode(ISD::AND, dl, CVT, Count,
6313 DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT));
6314 Chain = DAG.getCopyToReg(Chain, dl, (CVT == MVT::i64) ? X86::RCX :
6317 InFlag = Chain.getValue(1);
6318 Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6319 SDValue Ops[] = { Chain, DAG.getValueType(MVT::i8), InFlag };
6320 Chain = DAG.getNode(X86ISD::REP_STOS, dl, Tys, Ops, array_lengthof(Ops));
6321 } else if (BytesLeft) {
6322 // Handle the last 1 - 7 bytes.
6323 unsigned Offset = SizeVal - BytesLeft;
6324 EVT AddrVT = Dst.getValueType();
6325 EVT SizeVT = Size.getValueType();
6327 Chain = DAG.getMemset(Chain, dl,
6328 DAG.getNode(ISD::ADD, dl, AddrVT, Dst,
6329 DAG.getConstant(Offset, AddrVT)),
6331 DAG.getConstant(BytesLeft, SizeVT),
6332 Align, DstSV, DstSVOff + Offset);
6335 // TODO: Use a Tokenfactor, as in memcpy, instead of a single chain.
6340 X86TargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
6341 SDValue Chain, SDValue Dst, SDValue Src,
6342 SDValue Size, unsigned Align,
6344 const Value *DstSV, uint64_t DstSVOff,
6345 const Value *SrcSV, uint64_t SrcSVOff) {
6346 // This requires the copy size to be a constant, preferrably
6347 // within a subtarget-specific limit.
6348 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
6351 uint64_t SizeVal = ConstantSize->getZExtValue();
6352 if (!AlwaysInline && SizeVal > getSubtarget()->getMaxInlineSizeThreshold())
6355 /// If not DWORD aligned, call the library.
6356 if ((Align & 3) != 0)
6361 if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) // QWORD aligned
6364 unsigned UBytes = AVT.getSizeInBits() / 8;
6365 unsigned CountVal = SizeVal / UBytes;
6366 SDValue Count = DAG.getIntPtrConstant(CountVal);
6367 unsigned BytesLeft = SizeVal % UBytes;
6369 SDValue InFlag(0, 0);
6370 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RCX :
6373 InFlag = Chain.getValue(1);
6374 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RDI :
6377 InFlag = Chain.getValue(1);
6378 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RSI :
6381 InFlag = Chain.getValue(1);
6383 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6384 SDValue Ops[] = { Chain, DAG.getValueType(AVT), InFlag };
6385 SDValue RepMovs = DAG.getNode(X86ISD::REP_MOVS, dl, Tys, Ops,
6386 array_lengthof(Ops));
6388 SmallVector<SDValue, 4> Results;
6389 Results.push_back(RepMovs);
6391 // Handle the last 1 - 7 bytes.
6392 unsigned Offset = SizeVal - BytesLeft;
6393 EVT DstVT = Dst.getValueType();
6394 EVT SrcVT = Src.getValueType();
6395 EVT SizeVT = Size.getValueType();
6396 Results.push_back(DAG.getMemcpy(Chain, dl,
6397 DAG.getNode(ISD::ADD, dl, DstVT, Dst,
6398 DAG.getConstant(Offset, DstVT)),
6399 DAG.getNode(ISD::ADD, dl, SrcVT, Src,
6400 DAG.getConstant(Offset, SrcVT)),
6401 DAG.getConstant(BytesLeft, SizeVT),
6402 Align, AlwaysInline,
6403 DstSV, DstSVOff + Offset,
6404 SrcSV, SrcSVOff + Offset));
6407 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
6408 &Results[0], Results.size());
6411 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) {
6412 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
6413 DebugLoc dl = Op.getDebugLoc();
6415 if (!Subtarget->is64Bit()) {
6416 // vastart just stores the address of the VarArgsFrameIndex slot into the
6417 // memory location argument.
6418 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
6419 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0);
6423 // gp_offset (0 - 6 * 8)
6424 // fp_offset (48 - 48 + 8 * 16)
6425 // overflow_arg_area (point to parameters coming in memory).
6427 SmallVector<SDValue, 8> MemOps;
6428 SDValue FIN = Op.getOperand(1);
6430 SDValue Store = DAG.getStore(Op.getOperand(0), dl,
6431 DAG.getConstant(VarArgsGPOffset, MVT::i32),
6433 MemOps.push_back(Store);
6436 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6437 FIN, DAG.getIntPtrConstant(4));
6438 Store = DAG.getStore(Op.getOperand(0), dl,
6439 DAG.getConstant(VarArgsFPOffset, MVT::i32),
6441 MemOps.push_back(Store);
6443 // Store ptr to overflow_arg_area
6444 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6445 FIN, DAG.getIntPtrConstant(4));
6446 SDValue OVFIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
6447 Store = DAG.getStore(Op.getOperand(0), dl, OVFIN, FIN, SV, 0);
6448 MemOps.push_back(Store);
6450 // Store ptr to reg_save_area.
6451 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6452 FIN, DAG.getIntPtrConstant(8));
6453 SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
6454 Store = DAG.getStore(Op.getOperand(0), dl, RSFIN, FIN, SV, 0);
6455 MemOps.push_back(Store);
6456 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
6457 &MemOps[0], MemOps.size());
6460 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) {
6461 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
6462 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_arg!");
6463 SDValue Chain = Op.getOperand(0);
6464 SDValue SrcPtr = Op.getOperand(1);
6465 SDValue SrcSV = Op.getOperand(2);
6467 llvm_report_error("VAArgInst is not yet implemented for x86-64!");
6471 SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) {
6472 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
6473 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
6474 SDValue Chain = Op.getOperand(0);
6475 SDValue DstPtr = Op.getOperand(1);
6476 SDValue SrcPtr = Op.getOperand(2);
6477 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
6478 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
6479 DebugLoc dl = Op.getDebugLoc();
6481 return DAG.getMemcpy(Chain, dl, DstPtr, SrcPtr,
6482 DAG.getIntPtrConstant(24), 8, false,
6483 DstSV, 0, SrcSV, 0);
6487 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
6488 DebugLoc dl = Op.getDebugLoc();
6489 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
6491 default: return SDValue(); // Don't custom lower most intrinsics.
6492 // Comparison intrinsics.
6493 case Intrinsic::x86_sse_comieq_ss:
6494 case Intrinsic::x86_sse_comilt_ss:
6495 case Intrinsic::x86_sse_comile_ss:
6496 case Intrinsic::x86_sse_comigt_ss:
6497 case Intrinsic::x86_sse_comige_ss:
6498 case Intrinsic::x86_sse_comineq_ss:
6499 case Intrinsic::x86_sse_ucomieq_ss:
6500 case Intrinsic::x86_sse_ucomilt_ss:
6501 case Intrinsic::x86_sse_ucomile_ss:
6502 case Intrinsic::x86_sse_ucomigt_ss:
6503 case Intrinsic::x86_sse_ucomige_ss:
6504 case Intrinsic::x86_sse_ucomineq_ss:
6505 case Intrinsic::x86_sse2_comieq_sd:
6506 case Intrinsic::x86_sse2_comilt_sd:
6507 case Intrinsic::x86_sse2_comile_sd:
6508 case Intrinsic::x86_sse2_comigt_sd:
6509 case Intrinsic::x86_sse2_comige_sd:
6510 case Intrinsic::x86_sse2_comineq_sd:
6511 case Intrinsic::x86_sse2_ucomieq_sd:
6512 case Intrinsic::x86_sse2_ucomilt_sd:
6513 case Intrinsic::x86_sse2_ucomile_sd:
6514 case Intrinsic::x86_sse2_ucomigt_sd:
6515 case Intrinsic::x86_sse2_ucomige_sd:
6516 case Intrinsic::x86_sse2_ucomineq_sd: {
6518 ISD::CondCode CC = ISD::SETCC_INVALID;
6521 case Intrinsic::x86_sse_comieq_ss:
6522 case Intrinsic::x86_sse2_comieq_sd:
6526 case Intrinsic::x86_sse_comilt_ss:
6527 case Intrinsic::x86_sse2_comilt_sd:
6531 case Intrinsic::x86_sse_comile_ss:
6532 case Intrinsic::x86_sse2_comile_sd:
6536 case Intrinsic::x86_sse_comigt_ss:
6537 case Intrinsic::x86_sse2_comigt_sd:
6541 case Intrinsic::x86_sse_comige_ss:
6542 case Intrinsic::x86_sse2_comige_sd:
6546 case Intrinsic::x86_sse_comineq_ss:
6547 case Intrinsic::x86_sse2_comineq_sd:
6551 case Intrinsic::x86_sse_ucomieq_ss:
6552 case Intrinsic::x86_sse2_ucomieq_sd:
6553 Opc = X86ISD::UCOMI;
6556 case Intrinsic::x86_sse_ucomilt_ss:
6557 case Intrinsic::x86_sse2_ucomilt_sd:
6558 Opc = X86ISD::UCOMI;
6561 case Intrinsic::x86_sse_ucomile_ss:
6562 case Intrinsic::x86_sse2_ucomile_sd:
6563 Opc = X86ISD::UCOMI;
6566 case Intrinsic::x86_sse_ucomigt_ss:
6567 case Intrinsic::x86_sse2_ucomigt_sd:
6568 Opc = X86ISD::UCOMI;
6571 case Intrinsic::x86_sse_ucomige_ss:
6572 case Intrinsic::x86_sse2_ucomige_sd:
6573 Opc = X86ISD::UCOMI;
6576 case Intrinsic::x86_sse_ucomineq_ss:
6577 case Intrinsic::x86_sse2_ucomineq_sd:
6578 Opc = X86ISD::UCOMI;
6583 SDValue LHS = Op.getOperand(1);
6584 SDValue RHS = Op.getOperand(2);
6585 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
6586 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
6587 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
6588 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
6589 DAG.getConstant(X86CC, MVT::i8), Cond);
6590 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
6592 // ptest intrinsics. The intrinsic these come from are designed to return
6593 // an integer value, not just an instruction so lower it to the ptest
6594 // pattern and a setcc for the result.
6595 case Intrinsic::x86_sse41_ptestz:
6596 case Intrinsic::x86_sse41_ptestc:
6597 case Intrinsic::x86_sse41_ptestnzc:{
6600 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
6601 case Intrinsic::x86_sse41_ptestz:
6603 X86CC = X86::COND_E;
6605 case Intrinsic::x86_sse41_ptestc:
6607 X86CC = X86::COND_B;
6609 case Intrinsic::x86_sse41_ptestnzc:
6611 X86CC = X86::COND_A;
6615 SDValue LHS = Op.getOperand(1);
6616 SDValue RHS = Op.getOperand(2);
6617 SDValue Test = DAG.getNode(X86ISD::PTEST, dl, MVT::i32, LHS, RHS);
6618 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
6619 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
6620 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
6623 // Fix vector shift instructions where the last operand is a non-immediate
6625 case Intrinsic::x86_sse2_pslli_w:
6626 case Intrinsic::x86_sse2_pslli_d:
6627 case Intrinsic::x86_sse2_pslli_q:
6628 case Intrinsic::x86_sse2_psrli_w:
6629 case Intrinsic::x86_sse2_psrli_d:
6630 case Intrinsic::x86_sse2_psrli_q:
6631 case Intrinsic::x86_sse2_psrai_w:
6632 case Intrinsic::x86_sse2_psrai_d:
6633 case Intrinsic::x86_mmx_pslli_w:
6634 case Intrinsic::x86_mmx_pslli_d:
6635 case Intrinsic::x86_mmx_pslli_q:
6636 case Intrinsic::x86_mmx_psrli_w:
6637 case Intrinsic::x86_mmx_psrli_d:
6638 case Intrinsic::x86_mmx_psrli_q:
6639 case Intrinsic::x86_mmx_psrai_w:
6640 case Intrinsic::x86_mmx_psrai_d: {
6641 SDValue ShAmt = Op.getOperand(2);
6642 if (isa<ConstantSDNode>(ShAmt))
6645 unsigned NewIntNo = 0;
6646 EVT ShAmtVT = MVT::v4i32;
6648 case Intrinsic::x86_sse2_pslli_w:
6649 NewIntNo = Intrinsic::x86_sse2_psll_w;
6651 case Intrinsic::x86_sse2_pslli_d:
6652 NewIntNo = Intrinsic::x86_sse2_psll_d;
6654 case Intrinsic::x86_sse2_pslli_q:
6655 NewIntNo = Intrinsic::x86_sse2_psll_q;
6657 case Intrinsic::x86_sse2_psrli_w:
6658 NewIntNo = Intrinsic::x86_sse2_psrl_w;
6660 case Intrinsic::x86_sse2_psrli_d:
6661 NewIntNo = Intrinsic::x86_sse2_psrl_d;
6663 case Intrinsic::x86_sse2_psrli_q:
6664 NewIntNo = Intrinsic::x86_sse2_psrl_q;
6666 case Intrinsic::x86_sse2_psrai_w:
6667 NewIntNo = Intrinsic::x86_sse2_psra_w;
6669 case Intrinsic::x86_sse2_psrai_d:
6670 NewIntNo = Intrinsic::x86_sse2_psra_d;
6673 ShAmtVT = MVT::v2i32;
6675 case Intrinsic::x86_mmx_pslli_w:
6676 NewIntNo = Intrinsic::x86_mmx_psll_w;
6678 case Intrinsic::x86_mmx_pslli_d:
6679 NewIntNo = Intrinsic::x86_mmx_psll_d;
6681 case Intrinsic::x86_mmx_pslli_q:
6682 NewIntNo = Intrinsic::x86_mmx_psll_q;
6684 case Intrinsic::x86_mmx_psrli_w:
6685 NewIntNo = Intrinsic::x86_mmx_psrl_w;
6687 case Intrinsic::x86_mmx_psrli_d:
6688 NewIntNo = Intrinsic::x86_mmx_psrl_d;
6690 case Intrinsic::x86_mmx_psrli_q:
6691 NewIntNo = Intrinsic::x86_mmx_psrl_q;
6693 case Intrinsic::x86_mmx_psrai_w:
6694 NewIntNo = Intrinsic::x86_mmx_psra_w;
6696 case Intrinsic::x86_mmx_psrai_d:
6697 NewIntNo = Intrinsic::x86_mmx_psra_d;
6699 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
6705 // The vector shift intrinsics with scalars uses 32b shift amounts but
6706 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
6710 ShOps[1] = DAG.getConstant(0, MVT::i32);
6711 if (ShAmtVT == MVT::v4i32) {
6712 ShOps[2] = DAG.getUNDEF(MVT::i32);
6713 ShOps[3] = DAG.getUNDEF(MVT::i32);
6714 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 4);
6716 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2);
6719 EVT VT = Op.getValueType();
6720 ShAmt = DAG.getNode(ISD::BIT_CONVERT, dl, VT, ShAmt);
6721 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6722 DAG.getConstant(NewIntNo, MVT::i32),
6723 Op.getOperand(1), ShAmt);
6728 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) {
6729 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
6730 DebugLoc dl = Op.getDebugLoc();
6733 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
6735 DAG.getConstant(TD->getPointerSize(),
6736 Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
6737 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
6738 DAG.getNode(ISD::ADD, dl, getPointerTy(),
6743 // Just load the return address.
6744 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
6745 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
6746 RetAddrFI, NULL, 0);
6749 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) {
6750 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
6751 MFI->setFrameAddressIsTaken(true);
6752 EVT VT = Op.getValueType();
6753 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
6754 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
6755 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
6756 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
6758 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, NULL, 0);
6762 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
6763 SelectionDAG &DAG) {
6764 return DAG.getIntPtrConstant(2*TD->getPointerSize());
6767 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG)
6769 MachineFunction &MF = DAG.getMachineFunction();
6770 SDValue Chain = Op.getOperand(0);
6771 SDValue Offset = Op.getOperand(1);
6772 SDValue Handler = Op.getOperand(2);
6773 DebugLoc dl = Op.getDebugLoc();
6775 SDValue Frame = DAG.getRegister(Subtarget->is64Bit() ? X86::RBP : X86::EBP,
6777 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
6779 SDValue StoreAddr = DAG.getNode(ISD::SUB, dl, getPointerTy(), Frame,
6780 DAG.getIntPtrConstant(-TD->getPointerSize()));
6781 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
6782 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, NULL, 0);
6783 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
6784 MF.getRegInfo().addLiveOut(StoreAddrReg);
6786 return DAG.getNode(X86ISD::EH_RETURN, dl,
6788 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
6791 SDValue X86TargetLowering::LowerTRAMPOLINE(SDValue Op,
6792 SelectionDAG &DAG) {
6793 SDValue Root = Op.getOperand(0);
6794 SDValue Trmp = Op.getOperand(1); // trampoline
6795 SDValue FPtr = Op.getOperand(2); // nested function
6796 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
6797 DebugLoc dl = Op.getDebugLoc();
6799 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
6801 const X86InstrInfo *TII =
6802 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
6804 if (Subtarget->is64Bit()) {
6805 SDValue OutChains[6];
6807 // Large code-model.
6809 const unsigned char JMP64r = TII->getBaseOpcodeFor(X86::JMP64r);
6810 const unsigned char MOV64ri = TII->getBaseOpcodeFor(X86::MOV64ri);
6812 const unsigned char N86R10 = RegInfo->getX86RegNum(X86::R10);
6813 const unsigned char N86R11 = RegInfo->getX86RegNum(X86::R11);
6815 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
6817 // Load the pointer to the nested function into R11.
6818 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
6819 SDValue Addr = Trmp;
6820 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
6823 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
6824 DAG.getConstant(2, MVT::i64));
6825 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr, TrmpAddr, 2, false, 2);
6827 // Load the 'nest' parameter value into R10.
6828 // R10 is specified in X86CallingConv.td
6829 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
6830 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
6831 DAG.getConstant(10, MVT::i64));
6832 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
6833 Addr, TrmpAddr, 10);
6835 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
6836 DAG.getConstant(12, MVT::i64));
6837 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 12, false, 2);
6839 // Jump to the nested function.
6840 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
6841 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
6842 DAG.getConstant(20, MVT::i64));
6843 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
6844 Addr, TrmpAddr, 20);
6846 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
6847 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
6848 DAG.getConstant(22, MVT::i64));
6849 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
6853 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6) };
6854 return DAG.getMergeValues(Ops, 2, dl);
6856 const Function *Func =
6857 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
6858 CallingConv::ID CC = Func->getCallingConv();
6863 llvm_unreachable("Unsupported calling convention");
6864 case CallingConv::C:
6865 case CallingConv::X86_StdCall: {
6866 // Pass 'nest' parameter in ECX.
6867 // Must be kept in sync with X86CallingConv.td
6870 // Check that ECX wasn't needed by an 'inreg' parameter.
6871 const FunctionType *FTy = Func->getFunctionType();
6872 const AttrListPtr &Attrs = Func->getAttributes();
6874 if (!Attrs.isEmpty() && !Func->isVarArg()) {
6875 unsigned InRegCount = 0;
6878 for (FunctionType::param_iterator I = FTy->param_begin(),
6879 E = FTy->param_end(); I != E; ++I, ++Idx)
6880 if (Attrs.paramHasAttr(Idx, Attribute::InReg))
6881 // FIXME: should only count parameters that are lowered to integers.
6882 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
6884 if (InRegCount > 2) {
6885 llvm_report_error("Nest register in use - reduce number of inreg parameters!");
6890 case CallingConv::X86_FastCall:
6891 case CallingConv::Fast:
6892 // Pass 'nest' parameter in EAX.
6893 // Must be kept in sync with X86CallingConv.td
6898 SDValue OutChains[4];
6901 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
6902 DAG.getConstant(10, MVT::i32));
6903 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
6905 const unsigned char MOV32ri = TII->getBaseOpcodeFor(X86::MOV32ri);
6906 const unsigned char N86Reg = RegInfo->getX86RegNum(NestReg);
6907 OutChains[0] = DAG.getStore(Root, dl,
6908 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
6911 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
6912 DAG.getConstant(1, MVT::i32));
6913 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 1, false, 1);
6915 const unsigned char JMP = TII->getBaseOpcodeFor(X86::JMP);
6916 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
6917 DAG.getConstant(5, MVT::i32));
6918 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
6919 TrmpAddr, 5, false, 1);
6921 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
6922 DAG.getConstant(6, MVT::i32));
6923 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr, TrmpAddr, 6, false, 1);
6926 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4) };
6927 return DAG.getMergeValues(Ops, 2, dl);
6931 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) {
6933 The rounding mode is in bits 11:10 of FPSR, and has the following
6940 FLT_ROUNDS, on the other hand, expects the following:
6947 To perform the conversion, we do:
6948 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
6951 MachineFunction &MF = DAG.getMachineFunction();
6952 const TargetMachine &TM = MF.getTarget();
6953 const TargetFrameInfo &TFI = *TM.getFrameInfo();
6954 unsigned StackAlignment = TFI.getStackAlignment();
6955 EVT VT = Op.getValueType();
6956 DebugLoc dl = Op.getDebugLoc();
6958 // Save FP Control Word to stack slot
6959 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
6960 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
6962 SDValue Chain = DAG.getNode(X86ISD::FNSTCW16m, dl, MVT::Other,
6963 DAG.getEntryNode(), StackSlot);
6965 // Load FP Control Word from stack slot
6966 SDValue CWD = DAG.getLoad(MVT::i16, dl, Chain, StackSlot, NULL, 0);
6968 // Transform as necessary
6970 DAG.getNode(ISD::SRL, dl, MVT::i16,
6971 DAG.getNode(ISD::AND, dl, MVT::i16,
6972 CWD, DAG.getConstant(0x800, MVT::i16)),
6973 DAG.getConstant(11, MVT::i8));
6975 DAG.getNode(ISD::SRL, dl, MVT::i16,
6976 DAG.getNode(ISD::AND, dl, MVT::i16,
6977 CWD, DAG.getConstant(0x400, MVT::i16)),
6978 DAG.getConstant(9, MVT::i8));
6981 DAG.getNode(ISD::AND, dl, MVT::i16,
6982 DAG.getNode(ISD::ADD, dl, MVT::i16,
6983 DAG.getNode(ISD::OR, dl, MVT::i16, CWD1, CWD2),
6984 DAG.getConstant(1, MVT::i16)),
6985 DAG.getConstant(3, MVT::i16));
6988 return DAG.getNode((VT.getSizeInBits() < 16 ?
6989 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
6992 SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
6993 EVT VT = Op.getValueType();
6995 unsigned NumBits = VT.getSizeInBits();
6996 DebugLoc dl = Op.getDebugLoc();
6998 Op = Op.getOperand(0);
6999 if (VT == MVT::i8) {
7000 // Zero extend to i32 since there is not an i8 bsr.
7002 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
7005 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
7006 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
7007 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
7009 // If src is zero (i.e. bsr sets ZF), returns NumBits.
7012 DAG.getConstant(NumBits+NumBits-1, OpVT),
7013 DAG.getConstant(X86::COND_E, MVT::i8),
7016 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
7018 // Finally xor with NumBits-1.
7019 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
7022 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
7026 SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
7027 EVT VT = Op.getValueType();
7029 unsigned NumBits = VT.getSizeInBits();
7030 DebugLoc dl = Op.getDebugLoc();
7032 Op = Op.getOperand(0);
7033 if (VT == MVT::i8) {
7035 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
7038 // Issue a bsf (scan bits forward) which also sets EFLAGS.
7039 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
7040 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
7042 // If src is zero (i.e. bsf sets ZF), returns NumBits.
7045 DAG.getConstant(NumBits, OpVT),
7046 DAG.getConstant(X86::COND_E, MVT::i8),
7049 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
7052 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
7056 SDValue X86TargetLowering::LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG) {
7057 EVT VT = Op.getValueType();
7058 assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply");
7059 DebugLoc dl = Op.getDebugLoc();
7061 // ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32);
7062 // ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32);
7063 // ulong2 AloBlo = __builtin_ia32_pmuludq128( a, b );
7064 // ulong2 AloBhi = __builtin_ia32_pmuludq128( a, Bhi );
7065 // ulong2 AhiBlo = __builtin_ia32_pmuludq128( Ahi, b );
7067 // AloBhi = __builtin_ia32_psllqi128( AloBhi, 32 );
7068 // AhiBlo = __builtin_ia32_psllqi128( AhiBlo, 32 );
7069 // return AloBlo + AloBhi + AhiBlo;
7071 SDValue A = Op.getOperand(0);
7072 SDValue B = Op.getOperand(1);
7074 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7075 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
7076 A, DAG.getConstant(32, MVT::i32));
7077 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7078 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
7079 B, DAG.getConstant(32, MVT::i32));
7080 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7081 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
7083 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7084 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
7086 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7087 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
7089 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7090 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
7091 AloBhi, DAG.getConstant(32, MVT::i32));
7092 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7093 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
7094 AhiBlo, DAG.getConstant(32, MVT::i32));
7095 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
7096 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
7101 SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) {
7102 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
7103 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
7104 // looks for this combo and may remove the "setcc" instruction if the "setcc"
7105 // has only one use.
7106 SDNode *N = Op.getNode();
7107 SDValue LHS = N->getOperand(0);
7108 SDValue RHS = N->getOperand(1);
7109 unsigned BaseOp = 0;
7111 DebugLoc dl = Op.getDebugLoc();
7113 switch (Op.getOpcode()) {
7114 default: llvm_unreachable("Unknown ovf instruction!");
7116 // A subtract of one will be selected as a INC. Note that INC doesn't
7117 // set CF, so we can't do this for UADDO.
7118 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
7119 if (C->getAPIntValue() == 1) {
7120 BaseOp = X86ISD::INC;
7124 BaseOp = X86ISD::ADD;
7128 BaseOp = X86ISD::ADD;
7132 // A subtract of one will be selected as a DEC. Note that DEC doesn't
7133 // set CF, so we can't do this for USUBO.
7134 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
7135 if (C->getAPIntValue() == 1) {
7136 BaseOp = X86ISD::DEC;
7140 BaseOp = X86ISD::SUB;
7144 BaseOp = X86ISD::SUB;
7148 BaseOp = X86ISD::SMUL;
7152 BaseOp = X86ISD::UMUL;
7157 // Also sets EFLAGS.
7158 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
7159 SDValue Sum = DAG.getNode(BaseOp, dl, VTs, LHS, RHS);
7162 DAG.getNode(X86ISD::SETCC, dl, N->getValueType(1),
7163 DAG.getConstant(Cond, MVT::i32), SDValue(Sum.getNode(), 1));
7165 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SetCC);
7169 SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) {
7170 EVT T = Op.getValueType();
7171 DebugLoc dl = Op.getDebugLoc();
7174 switch(T.getSimpleVT().SimpleTy) {
7176 assert(false && "Invalid value type!");
7177 case MVT::i8: Reg = X86::AL; size = 1; break;
7178 case MVT::i16: Reg = X86::AX; size = 2; break;
7179 case MVT::i32: Reg = X86::EAX; size = 4; break;
7181 assert(Subtarget->is64Bit() && "Node not type legal!");
7182 Reg = X86::RAX; size = 8;
7185 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), dl, Reg,
7186 Op.getOperand(2), SDValue());
7187 SDValue Ops[] = { cpIn.getValue(0),
7190 DAG.getTargetConstant(size, MVT::i8),
7192 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
7193 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG_DAG, dl, Tys, Ops, 5);
7195 DAG.getCopyFromReg(Result.getValue(0), dl, Reg, T, Result.getValue(1));
7199 SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
7200 SelectionDAG &DAG) {
7201 assert(Subtarget->is64Bit() && "Result not type legalized?");
7202 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
7203 SDValue TheChain = Op.getOperand(0);
7204 DebugLoc dl = Op.getDebugLoc();
7205 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
7206 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
7207 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
7209 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
7210 DAG.getConstant(32, MVT::i8));
7212 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
7215 return DAG.getMergeValues(Ops, 2, dl);
7218 SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
7219 SDNode *Node = Op.getNode();
7220 DebugLoc dl = Node->getDebugLoc();
7221 EVT T = Node->getValueType(0);
7222 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
7223 DAG.getConstant(0, T), Node->getOperand(2));
7224 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
7225 cast<AtomicSDNode>(Node)->getMemoryVT(),
7226 Node->getOperand(0),
7227 Node->getOperand(1), negOp,
7228 cast<AtomicSDNode>(Node)->getSrcValue(),
7229 cast<AtomicSDNode>(Node)->getAlignment());
7232 /// LowerOperation - Provide custom lowering hooks for some operations.
7234 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
7235 switch (Op.getOpcode()) {
7236 default: llvm_unreachable("Should not custom lower this!");
7237 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG);
7238 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
7239 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
7240 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
7241 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
7242 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
7243 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
7244 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
7245 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
7246 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
7247 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
7248 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
7249 case ISD::SHL_PARTS:
7250 case ISD::SRA_PARTS:
7251 case ISD::SRL_PARTS: return LowerShift(Op, DAG);
7252 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
7253 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
7254 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
7255 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
7256 case ISD::FABS: return LowerFABS(Op, DAG);
7257 case ISD::FNEG: return LowerFNEG(Op, DAG);
7258 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
7259 case ISD::SETCC: return LowerSETCC(Op, DAG);
7260 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
7261 case ISD::SELECT: return LowerSELECT(Op, DAG);
7262 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
7263 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
7264 case ISD::VASTART: return LowerVASTART(Op, DAG);
7265 case ISD::VAARG: return LowerVAARG(Op, DAG);
7266 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
7267 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
7268 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
7269 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
7270 case ISD::FRAME_TO_ARGS_OFFSET:
7271 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
7272 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
7273 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
7274 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG);
7275 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
7276 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
7277 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
7278 case ISD::MUL: return LowerMUL_V2I64(Op, DAG);
7284 case ISD::UMULO: return LowerXALUO(Op, DAG);
7285 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
7289 void X86TargetLowering::
7290 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
7291 SelectionDAG &DAG, unsigned NewOp) {
7292 EVT T = Node->getValueType(0);
7293 DebugLoc dl = Node->getDebugLoc();
7294 assert (T == MVT::i64 && "Only know how to expand i64 atomics");
7296 SDValue Chain = Node->getOperand(0);
7297 SDValue In1 = Node->getOperand(1);
7298 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
7299 Node->getOperand(2), DAG.getIntPtrConstant(0));
7300 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
7301 Node->getOperand(2), DAG.getIntPtrConstant(1));
7302 SDValue Ops[] = { Chain, In1, In2L, In2H };
7303 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
7305 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64,
7306 cast<MemSDNode>(Node)->getMemOperand());
7307 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
7308 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
7309 Results.push_back(Result.getValue(2));
7312 /// ReplaceNodeResults - Replace a node with an illegal result type
7313 /// with a new node built out of custom code.
7314 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
7315 SmallVectorImpl<SDValue>&Results,
7316 SelectionDAG &DAG) {
7317 DebugLoc dl = N->getDebugLoc();
7318 switch (N->getOpcode()) {
7320 assert(false && "Do not know how to custom type legalize this operation!");
7322 case ISD::FP_TO_SINT: {
7323 std::pair<SDValue,SDValue> Vals =
7324 FP_TO_INTHelper(SDValue(N, 0), DAG, true);
7325 SDValue FIST = Vals.first, StackSlot = Vals.second;
7326 if (FIST.getNode() != 0) {
7327 EVT VT = N->getValueType(0);
7328 // Return a load from the stack slot.
7329 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot, NULL, 0));
7333 case ISD::READCYCLECOUNTER: {
7334 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
7335 SDValue TheChain = N->getOperand(0);
7336 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
7337 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
7339 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
7341 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
7342 SDValue Ops[] = { eax, edx };
7343 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
7344 Results.push_back(edx.getValue(1));
7351 EVT WidenVT = getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
7352 Results.push_back(DAG.UnrollVectorOp(N, WidenVT.getVectorNumElements()));
7355 case ISD::ATOMIC_CMP_SWAP: {
7356 EVT T = N->getValueType(0);
7357 assert (T == MVT::i64 && "Only know how to expand i64 Cmp and Swap");
7358 SDValue cpInL, cpInH;
7359 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
7360 DAG.getConstant(0, MVT::i32));
7361 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
7362 DAG.getConstant(1, MVT::i32));
7363 cpInL = DAG.getCopyToReg(N->getOperand(0), dl, X86::EAX, cpInL, SDValue());
7364 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl, X86::EDX, cpInH,
7366 SDValue swapInL, swapInH;
7367 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
7368 DAG.getConstant(0, MVT::i32));
7369 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
7370 DAG.getConstant(1, MVT::i32));
7371 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl, X86::EBX, swapInL,
7373 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl, X86::ECX, swapInH,
7374 swapInL.getValue(1));
7375 SDValue Ops[] = { swapInH.getValue(0),
7377 swapInH.getValue(1) };
7378 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
7379 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG8_DAG, dl, Tys, Ops, 3);
7380 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl, X86::EAX,
7381 MVT::i32, Result.getValue(1));
7382 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl, X86::EDX,
7383 MVT::i32, cpOutL.getValue(2));
7384 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
7385 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
7386 Results.push_back(cpOutH.getValue(1));
7389 case ISD::ATOMIC_LOAD_ADD:
7390 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG);
7392 case ISD::ATOMIC_LOAD_AND:
7393 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG);
7395 case ISD::ATOMIC_LOAD_NAND:
7396 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG);
7398 case ISD::ATOMIC_LOAD_OR:
7399 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG);
7401 case ISD::ATOMIC_LOAD_SUB:
7402 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG);
7404 case ISD::ATOMIC_LOAD_XOR:
7405 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG);
7407 case ISD::ATOMIC_SWAP:
7408 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG);
7413 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
7415 default: return NULL;
7416 case X86ISD::BSF: return "X86ISD::BSF";
7417 case X86ISD::BSR: return "X86ISD::BSR";
7418 case X86ISD::SHLD: return "X86ISD::SHLD";
7419 case X86ISD::SHRD: return "X86ISD::SHRD";
7420 case X86ISD::FAND: return "X86ISD::FAND";
7421 case X86ISD::FOR: return "X86ISD::FOR";
7422 case X86ISD::FXOR: return "X86ISD::FXOR";
7423 case X86ISD::FSRL: return "X86ISD::FSRL";
7424 case X86ISD::FILD: return "X86ISD::FILD";
7425 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
7426 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
7427 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
7428 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
7429 case X86ISD::FLD: return "X86ISD::FLD";
7430 case X86ISD::FST: return "X86ISD::FST";
7431 case X86ISD::CALL: return "X86ISD::CALL";
7432 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
7433 case X86ISD::BT: return "X86ISD::BT";
7434 case X86ISD::CMP: return "X86ISD::CMP";
7435 case X86ISD::COMI: return "X86ISD::COMI";
7436 case X86ISD::UCOMI: return "X86ISD::UCOMI";
7437 case X86ISD::SETCC: return "X86ISD::SETCC";
7438 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
7439 case X86ISD::CMOV: return "X86ISD::CMOV";
7440 case X86ISD::BRCOND: return "X86ISD::BRCOND";
7441 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
7442 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
7443 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
7444 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
7445 case X86ISD::Wrapper: return "X86ISD::Wrapper";
7446 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
7447 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
7448 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
7449 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
7450 case X86ISD::PINSRB: return "X86ISD::PINSRB";
7451 case X86ISD::PINSRW: return "X86ISD::PINSRW";
7452 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
7453 case X86ISD::FMAX: return "X86ISD::FMAX";
7454 case X86ISD::FMIN: return "X86ISD::FMIN";
7455 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
7456 case X86ISD::FRCP: return "X86ISD::FRCP";
7457 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
7458 case X86ISD::SegmentBaseAddress: return "X86ISD::SegmentBaseAddress";
7459 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
7460 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
7461 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
7462 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
7463 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
7464 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
7465 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
7466 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
7467 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
7468 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
7469 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
7470 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
7471 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
7472 case X86ISD::VSHL: return "X86ISD::VSHL";
7473 case X86ISD::VSRL: return "X86ISD::VSRL";
7474 case X86ISD::CMPPD: return "X86ISD::CMPPD";
7475 case X86ISD::CMPPS: return "X86ISD::CMPPS";
7476 case X86ISD::PCMPEQB: return "X86ISD::PCMPEQB";
7477 case X86ISD::PCMPEQW: return "X86ISD::PCMPEQW";
7478 case X86ISD::PCMPEQD: return "X86ISD::PCMPEQD";
7479 case X86ISD::PCMPEQQ: return "X86ISD::PCMPEQQ";
7480 case X86ISD::PCMPGTB: return "X86ISD::PCMPGTB";
7481 case X86ISD::PCMPGTW: return "X86ISD::PCMPGTW";
7482 case X86ISD::PCMPGTD: return "X86ISD::PCMPGTD";
7483 case X86ISD::PCMPGTQ: return "X86ISD::PCMPGTQ";
7484 case X86ISD::ADD: return "X86ISD::ADD";
7485 case X86ISD::SUB: return "X86ISD::SUB";
7486 case X86ISD::SMUL: return "X86ISD::SMUL";
7487 case X86ISD::UMUL: return "X86ISD::UMUL";
7488 case X86ISD::INC: return "X86ISD::INC";
7489 case X86ISD::DEC: return "X86ISD::DEC";
7490 case X86ISD::OR: return "X86ISD::OR";
7491 case X86ISD::XOR: return "X86ISD::XOR";
7492 case X86ISD::AND: return "X86ISD::AND";
7493 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
7494 case X86ISD::PTEST: return "X86ISD::PTEST";
7495 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
7499 // isLegalAddressingMode - Return true if the addressing mode represented
7500 // by AM is legal for this target, for a load/store of the specified type.
7501 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
7502 const Type *Ty) const {
7503 // X86 supports extremely general addressing modes.
7504 CodeModel::Model M = getTargetMachine().getCodeModel();
7506 // X86 allows a sign-extended 32-bit immediate field as a displacement.
7507 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
7512 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
7514 // If a reference to this global requires an extra load, we can't fold it.
7515 if (isGlobalStubReference(GVFlags))
7518 // If BaseGV requires a register for the PIC base, we cannot also have a
7519 // BaseReg specified.
7520 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
7523 // If lower 4G is not available, then we must use rip-relative addressing.
7524 if (Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
7534 // These scales always work.
7539 // These scales are formed with basereg+scalereg. Only accept if there is
7544 default: // Other stuff never works.
7552 bool X86TargetLowering::isTruncateFree(const Type *Ty1, const Type *Ty2) const {
7553 if (!Ty1->isInteger() || !Ty2->isInteger())
7555 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
7556 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
7557 if (NumBits1 <= NumBits2)
7559 return Subtarget->is64Bit() || NumBits1 < 64;
7562 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
7563 if (!VT1.isInteger() || !VT2.isInteger())
7565 unsigned NumBits1 = VT1.getSizeInBits();
7566 unsigned NumBits2 = VT2.getSizeInBits();
7567 if (NumBits1 <= NumBits2)
7569 return Subtarget->is64Bit() || NumBits1 < 64;
7572 bool X86TargetLowering::isZExtFree(const Type *Ty1, const Type *Ty2) const {
7573 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
7574 return Ty1->isInteger(64) && Ty2->isInteger(64) && Subtarget->is64Bit();
7577 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
7578 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
7579 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
7582 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
7583 // i16 instructions are longer (0x66 prefix) and potentially slower.
7584 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
7587 /// isShuffleMaskLegal - Targets can use this to indicate that they only
7588 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
7589 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
7590 /// are assumed to be legal.
7592 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
7594 // Only do shuffles on 128-bit vector types for now.
7595 if (VT.getSizeInBits() == 64)
7598 // FIXME: pshufb, blends, shifts.
7599 return (VT.getVectorNumElements() == 2 ||
7600 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
7601 isMOVLMask(M, VT) ||
7602 isSHUFPMask(M, VT) ||
7603 isPSHUFDMask(M, VT) ||
7604 isPSHUFHWMask(M, VT) ||
7605 isPSHUFLWMask(M, VT) ||
7606 isPALIGNRMask(M, VT, Subtarget->hasSSSE3()) ||
7607 isUNPCKLMask(M, VT) ||
7608 isUNPCKHMask(M, VT) ||
7609 isUNPCKL_v_undef_Mask(M, VT) ||
7610 isUNPCKH_v_undef_Mask(M, VT));
7614 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
7616 unsigned NumElts = VT.getVectorNumElements();
7617 // FIXME: This collection of masks seems suspect.
7620 if (NumElts == 4 && VT.getSizeInBits() == 128) {
7621 return (isMOVLMask(Mask, VT) ||
7622 isCommutedMOVLMask(Mask, VT, true) ||
7623 isSHUFPMask(Mask, VT) ||
7624 isCommutedSHUFPMask(Mask, VT));
7629 //===----------------------------------------------------------------------===//
7630 // X86 Scheduler Hooks
7631 //===----------------------------------------------------------------------===//
7633 // private utility function
7635 X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
7636 MachineBasicBlock *MBB,
7644 TargetRegisterClass *RC,
7645 bool invSrc) const {
7646 // For the atomic bitwise operator, we generate
7649 // ld t1 = [bitinstr.addr]
7650 // op t2 = t1, [bitinstr.val]
7652 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
7654 // fallthrough -->nextMBB
7655 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7656 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
7657 MachineFunction::iterator MBBIter = MBB;
7660 /// First build the CFG
7661 MachineFunction *F = MBB->getParent();
7662 MachineBasicBlock *thisMBB = MBB;
7663 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
7664 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
7665 F->insert(MBBIter, newMBB);
7666 F->insert(MBBIter, nextMBB);
7668 // Move all successors to thisMBB to nextMBB
7669 nextMBB->transferSuccessors(thisMBB);
7671 // Update thisMBB to fall through to newMBB
7672 thisMBB->addSuccessor(newMBB);
7674 // newMBB jumps to itself and fall through to nextMBB
7675 newMBB->addSuccessor(nextMBB);
7676 newMBB->addSuccessor(newMBB);
7678 // Insert instructions into newMBB based on incoming instruction
7679 assert(bInstr->getNumOperands() < X86AddrNumOperands + 4 &&
7680 "unexpected number of operands");
7681 DebugLoc dl = bInstr->getDebugLoc();
7682 MachineOperand& destOper = bInstr->getOperand(0);
7683 MachineOperand* argOpers[2 + X86AddrNumOperands];
7684 int numArgs = bInstr->getNumOperands() - 1;
7685 for (int i=0; i < numArgs; ++i)
7686 argOpers[i] = &bInstr->getOperand(i+1);
7688 // x86 address has 4 operands: base, index, scale, and displacement
7689 int lastAddrIndx = X86AddrNumOperands - 1; // [0,3]
7690 int valArgIndx = lastAddrIndx + 1;
7692 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
7693 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1);
7694 for (int i=0; i <= lastAddrIndx; ++i)
7695 (*MIB).addOperand(*argOpers[i]);
7697 unsigned tt = F->getRegInfo().createVirtualRegister(RC);
7699 MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1);
7704 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
7705 assert((argOpers[valArgIndx]->isReg() ||
7706 argOpers[valArgIndx]->isImm()) &&
7708 if (argOpers[valArgIndx]->isReg())
7709 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2);
7711 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2);
7713 (*MIB).addOperand(*argOpers[valArgIndx]);
7715 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), EAXreg);
7718 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc));
7719 for (int i=0; i <= lastAddrIndx; ++i)
7720 (*MIB).addOperand(*argOpers[i]);
7722 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
7723 (*MIB).setMemRefs(bInstr->memoperands_begin(),
7724 bInstr->memoperands_end());
7726 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), destOper.getReg());
7730 BuildMI(newMBB, dl, TII->get(X86::JNE)).addMBB(newMBB);
7732 F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now.
7736 // private utility function: 64 bit atomics on 32 bit host.
7738 X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
7739 MachineBasicBlock *MBB,
7744 bool invSrc) const {
7745 // For the atomic bitwise operator, we generate
7746 // thisMBB (instructions are in pairs, except cmpxchg8b)
7747 // ld t1,t2 = [bitinstr.addr]
7749 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4)
7750 // op t5, t6 <- out1, out2, [bitinstr.val]
7751 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val])
7752 // mov ECX, EBX <- t5, t6
7753 // mov EAX, EDX <- t1, t2
7754 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit]
7755 // mov t3, t4 <- EAX, EDX
7757 // result in out1, out2
7758 // fallthrough -->nextMBB
7760 const TargetRegisterClass *RC = X86::GR32RegisterClass;
7761 const unsigned LoadOpc = X86::MOV32rm;
7762 const unsigned copyOpc = X86::MOV32rr;
7763 const unsigned NotOpc = X86::NOT32r;
7764 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7765 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
7766 MachineFunction::iterator MBBIter = MBB;
7769 /// First build the CFG
7770 MachineFunction *F = MBB->getParent();
7771 MachineBasicBlock *thisMBB = MBB;
7772 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
7773 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
7774 F->insert(MBBIter, newMBB);
7775 F->insert(MBBIter, nextMBB);
7777 // Move all successors to thisMBB to nextMBB
7778 nextMBB->transferSuccessors(thisMBB);
7780 // Update thisMBB to fall through to newMBB
7781 thisMBB->addSuccessor(newMBB);
7783 // newMBB jumps to itself and fall through to nextMBB
7784 newMBB->addSuccessor(nextMBB);
7785 newMBB->addSuccessor(newMBB);
7787 DebugLoc dl = bInstr->getDebugLoc();
7788 // Insert instructions into newMBB based on incoming instruction
7789 // There are 8 "real" operands plus 9 implicit def/uses, ignored here.
7790 assert(bInstr->getNumOperands() < X86AddrNumOperands + 14 &&
7791 "unexpected number of operands");
7792 MachineOperand& dest1Oper = bInstr->getOperand(0);
7793 MachineOperand& dest2Oper = bInstr->getOperand(1);
7794 MachineOperand* argOpers[2 + X86AddrNumOperands];
7795 for (int i=0; i < 2 + X86AddrNumOperands; ++i)
7796 argOpers[i] = &bInstr->getOperand(i+2);
7798 // x86 address has 4 operands: base, index, scale, and displacement
7799 int lastAddrIndx = X86AddrNumOperands - 1; // [0,3]
7801 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
7802 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1);
7803 for (int i=0; i <= lastAddrIndx; ++i)
7804 (*MIB).addOperand(*argOpers[i]);
7805 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
7806 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2);
7807 // add 4 to displacement.
7808 for (int i=0; i <= lastAddrIndx-2; ++i)
7809 (*MIB).addOperand(*argOpers[i]);
7810 MachineOperand newOp3 = *(argOpers[3]);
7812 newOp3.setImm(newOp3.getImm()+4);
7814 newOp3.setOffset(newOp3.getOffset()+4);
7815 (*MIB).addOperand(newOp3);
7816 (*MIB).addOperand(*argOpers[lastAddrIndx]);
7818 // t3/4 are defined later, at the bottom of the loop
7819 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
7820 unsigned t4 = F->getRegInfo().createVirtualRegister(RC);
7821 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg())
7822 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB);
7823 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg())
7824 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB);
7826 unsigned tt1 = F->getRegInfo().createVirtualRegister(RC);
7827 unsigned tt2 = F->getRegInfo().createVirtualRegister(RC);
7829 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), tt1).addReg(t1);
7830 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), tt2).addReg(t2);
7836 int valArgIndx = lastAddrIndx + 1;
7837 assert((argOpers[valArgIndx]->isReg() ||
7838 argOpers[valArgIndx]->isImm()) &&
7840 unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
7841 unsigned t6 = F->getRegInfo().createVirtualRegister(RC);
7842 if (argOpers[valArgIndx]->isReg())
7843 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5);
7845 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5);
7846 if (regOpcL != X86::MOV32rr)
7848 (*MIB).addOperand(*argOpers[valArgIndx]);
7849 assert(argOpers[valArgIndx + 1]->isReg() ==
7850 argOpers[valArgIndx]->isReg());
7851 assert(argOpers[valArgIndx + 1]->isImm() ==
7852 argOpers[valArgIndx]->isImm());
7853 if (argOpers[valArgIndx + 1]->isReg())
7854 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6);
7856 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6);
7857 if (regOpcH != X86::MOV32rr)
7859 (*MIB).addOperand(*argOpers[valArgIndx + 1]);
7861 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EAX);
7863 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EDX);
7866 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EBX);
7868 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::ECX);
7871 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B));
7872 for (int i=0; i <= lastAddrIndx; ++i)
7873 (*MIB).addOperand(*argOpers[i]);
7875 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
7876 (*MIB).setMemRefs(bInstr->memoperands_begin(),
7877 bInstr->memoperands_end());
7879 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), t3);
7880 MIB.addReg(X86::EAX);
7881 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), t4);
7882 MIB.addReg(X86::EDX);
7885 BuildMI(newMBB, dl, TII->get(X86::JNE)).addMBB(newMBB);
7887 F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now.
7891 // private utility function
7893 X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
7894 MachineBasicBlock *MBB,
7895 unsigned cmovOpc) const {
7896 // For the atomic min/max operator, we generate
7899 // ld t1 = [min/max.addr]
7900 // mov t2 = [min/max.val]
7902 // cmov[cond] t2 = t1
7904 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
7906 // fallthrough -->nextMBB
7908 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7909 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
7910 MachineFunction::iterator MBBIter = MBB;
7913 /// First build the CFG
7914 MachineFunction *F = MBB->getParent();
7915 MachineBasicBlock *thisMBB = MBB;
7916 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
7917 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
7918 F->insert(MBBIter, newMBB);
7919 F->insert(MBBIter, nextMBB);
7921 // Move all successors of thisMBB to nextMBB
7922 nextMBB->transferSuccessors(thisMBB);
7924 // Update thisMBB to fall through to newMBB
7925 thisMBB->addSuccessor(newMBB);
7927 // newMBB jumps to newMBB and fall through to nextMBB
7928 newMBB->addSuccessor(nextMBB);
7929 newMBB->addSuccessor(newMBB);
7931 DebugLoc dl = mInstr->getDebugLoc();
7932 // Insert instructions into newMBB based on incoming instruction
7933 assert(mInstr->getNumOperands() < X86AddrNumOperands + 4 &&
7934 "unexpected number of operands");
7935 MachineOperand& destOper = mInstr->getOperand(0);
7936 MachineOperand* argOpers[2 + X86AddrNumOperands];
7937 int numArgs = mInstr->getNumOperands() - 1;
7938 for (int i=0; i < numArgs; ++i)
7939 argOpers[i] = &mInstr->getOperand(i+1);
7941 // x86 address has 4 operands: base, index, scale, and displacement
7942 int lastAddrIndx = X86AddrNumOperands - 1; // [0,3]
7943 int valArgIndx = lastAddrIndx + 1;
7945 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
7946 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1);
7947 for (int i=0; i <= lastAddrIndx; ++i)
7948 (*MIB).addOperand(*argOpers[i]);
7950 // We only support register and immediate values
7951 assert((argOpers[valArgIndx]->isReg() ||
7952 argOpers[valArgIndx]->isImm()) &&
7955 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
7956 if (argOpers[valArgIndx]->isReg())
7957 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
7959 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
7960 (*MIB).addOperand(*argOpers[valArgIndx]);
7962 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), X86::EAX);
7965 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr));
7970 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
7971 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3);
7975 // Cmp and exchange if none has modified the memory location
7976 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32));
7977 for (int i=0; i <= lastAddrIndx; ++i)
7978 (*MIB).addOperand(*argOpers[i]);
7980 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
7981 (*MIB).setMemRefs(mInstr->memoperands_begin(),
7982 mInstr->memoperands_end());
7984 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), destOper.getReg());
7985 MIB.addReg(X86::EAX);
7988 BuildMI(newMBB, dl, TII->get(X86::JNE)).addMBB(newMBB);
7990 F->DeleteMachineInstr(mInstr); // The pseudo instruction is gone now.
7994 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
7995 // all of this code can be replaced with that in the .td file.
7997 X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB,
7998 unsigned numArgs, bool memArg) const {
8000 MachineFunction *F = BB->getParent();
8001 DebugLoc dl = MI->getDebugLoc();
8002 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8006 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm;
8008 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr;
8010 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(Opc));
8012 for (unsigned i = 0; i < numArgs; ++i) {
8013 MachineOperand &Op = MI->getOperand(i+1);
8015 if (!(Op.isReg() && Op.isImplicit()))
8019 BuildMI(BB, dl, TII->get(X86::MOVAPSrr), MI->getOperand(0).getReg())
8022 F->DeleteMachineInstr(MI);
8028 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
8030 MachineBasicBlock *MBB) const {
8031 // Emit code to save XMM registers to the stack. The ABI says that the
8032 // number of registers to save is given in %al, so it's theoretically
8033 // possible to do an indirect jump trick to avoid saving all of them,
8034 // however this code takes a simpler approach and just executes all
8035 // of the stores if %al is non-zero. It's less code, and it's probably
8036 // easier on the hardware branch predictor, and stores aren't all that
8037 // expensive anyway.
8039 // Create the new basic blocks. One block contains all the XMM stores,
8040 // and one block is the final destination regardless of whether any
8041 // stores were performed.
8042 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
8043 MachineFunction *F = MBB->getParent();
8044 MachineFunction::iterator MBBIter = MBB;
8046 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
8047 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
8048 F->insert(MBBIter, XMMSaveMBB);
8049 F->insert(MBBIter, EndMBB);
8052 // Move any original successors of MBB to the end block.
8053 EndMBB->transferSuccessors(MBB);
8054 // The original block will now fall through to the XMM save block.
8055 MBB->addSuccessor(XMMSaveMBB);
8056 // The XMMSaveMBB will fall through to the end block.
8057 XMMSaveMBB->addSuccessor(EndMBB);
8059 // Now add the instructions.
8060 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8061 DebugLoc DL = MI->getDebugLoc();
8063 unsigned CountReg = MI->getOperand(0).getReg();
8064 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
8065 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
8067 if (!Subtarget->isTargetWin64()) {
8068 // If %al is 0, branch around the XMM save block.
8069 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
8070 BuildMI(MBB, DL, TII->get(X86::JE)).addMBB(EndMBB);
8071 MBB->addSuccessor(EndMBB);
8074 // In the XMM save block, save all the XMM argument registers.
8075 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
8076 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
8077 MachineMemOperand *MMO =
8078 F->getMachineMemOperand(
8079 PseudoSourceValue::getFixedStack(RegSaveFrameIndex),
8080 MachineMemOperand::MOStore, Offset,
8081 /*Size=*/16, /*Align=*/16);
8082 BuildMI(XMMSaveMBB, DL, TII->get(X86::MOVAPSmr))
8083 .addFrameIndex(RegSaveFrameIndex)
8084 .addImm(/*Scale=*/1)
8085 .addReg(/*IndexReg=*/0)
8086 .addImm(/*Disp=*/Offset)
8087 .addReg(/*Segment=*/0)
8088 .addReg(MI->getOperand(i).getReg())
8089 .addMemOperand(MMO);
8092 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
8098 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
8099 MachineBasicBlock *BB,
8100 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const {
8101 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8102 DebugLoc DL = MI->getDebugLoc();
8104 // To "insert" a SELECT_CC instruction, we actually have to insert the
8105 // diamond control-flow pattern. The incoming instruction knows the
8106 // destination vreg to set, the condition code register to branch on, the
8107 // true/false values to select between, and a branch opcode to use.
8108 const BasicBlock *LLVM_BB = BB->getBasicBlock();
8109 MachineFunction::iterator It = BB;
8115 // cmpTY ccX, r1, r2
8117 // fallthrough --> copy0MBB
8118 MachineBasicBlock *thisMBB = BB;
8119 MachineFunction *F = BB->getParent();
8120 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
8121 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
8123 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
8124 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
8125 F->insert(It, copy0MBB);
8126 F->insert(It, sinkMBB);
8127 // Update machine-CFG edges by first adding all successors of the current
8128 // block to the new block which will contain the Phi node for the select.
8129 // Also inform sdisel of the edge changes.
8130 for (MachineBasicBlock::succ_iterator I = BB->succ_begin(),
8131 E = BB->succ_end(); I != E; ++I) {
8132 EM->insert(std::make_pair(*I, sinkMBB));
8133 sinkMBB->addSuccessor(*I);
8135 // Next, remove all successors of the current block, and add the true
8136 // and fallthrough blocks as its successors.
8137 while (!BB->succ_empty())
8138 BB->removeSuccessor(BB->succ_begin());
8139 // Add the true and fallthrough blocks as its successors.
8140 BB->addSuccessor(copy0MBB);
8141 BB->addSuccessor(sinkMBB);
8144 // %FalseValue = ...
8145 // # fallthrough to sinkMBB
8148 // Update machine-CFG edges
8149 BB->addSuccessor(sinkMBB);
8152 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
8155 BuildMI(BB, DL, TII->get(X86::PHI), MI->getOperand(0).getReg())
8156 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
8157 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
8159 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
8165 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
8166 MachineBasicBlock *BB,
8167 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const {
8168 switch (MI->getOpcode()) {
8169 default: assert(false && "Unexpected instr type to insert");
8171 case X86::CMOV_V1I64:
8172 case X86::CMOV_FR32:
8173 case X86::CMOV_FR64:
8174 case X86::CMOV_V4F32:
8175 case X86::CMOV_V2F64:
8176 case X86::CMOV_V2I64:
8177 return EmitLoweredSelect(MI, BB, EM);
8179 case X86::FP32_TO_INT16_IN_MEM:
8180 case X86::FP32_TO_INT32_IN_MEM:
8181 case X86::FP32_TO_INT64_IN_MEM:
8182 case X86::FP64_TO_INT16_IN_MEM:
8183 case X86::FP64_TO_INT32_IN_MEM:
8184 case X86::FP64_TO_INT64_IN_MEM:
8185 case X86::FP80_TO_INT16_IN_MEM:
8186 case X86::FP80_TO_INT32_IN_MEM:
8187 case X86::FP80_TO_INT64_IN_MEM: {
8188 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8189 DebugLoc DL = MI->getDebugLoc();
8191 // Change the floating point control register to use "round towards zero"
8192 // mode when truncating to an integer value.
8193 MachineFunction *F = BB->getParent();
8194 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
8195 addFrameReference(BuildMI(BB, DL, TII->get(X86::FNSTCW16m)), CWFrameIdx);
8197 // Load the old value of the high byte of the control word...
8199 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass);
8200 addFrameReference(BuildMI(BB, DL, TII->get(X86::MOV16rm), OldCW),
8203 // Set the high part to be round to zero...
8204 addFrameReference(BuildMI(BB, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
8207 // Reload the modified control word now...
8208 addFrameReference(BuildMI(BB, DL, TII->get(X86::FLDCW16m)), CWFrameIdx);
8210 // Restore the memory image of control word to original value
8211 addFrameReference(BuildMI(BB, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
8214 // Get the X86 opcode to use.
8216 switch (MI->getOpcode()) {
8217 default: llvm_unreachable("illegal opcode!");
8218 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
8219 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
8220 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
8221 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
8222 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
8223 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
8224 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
8225 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
8226 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
8230 MachineOperand &Op = MI->getOperand(0);
8232 AM.BaseType = X86AddressMode::RegBase;
8233 AM.Base.Reg = Op.getReg();
8235 AM.BaseType = X86AddressMode::FrameIndexBase;
8236 AM.Base.FrameIndex = Op.getIndex();
8238 Op = MI->getOperand(1);
8240 AM.Scale = Op.getImm();
8241 Op = MI->getOperand(2);
8243 AM.IndexReg = Op.getImm();
8244 Op = MI->getOperand(3);
8245 if (Op.isGlobal()) {
8246 AM.GV = Op.getGlobal();
8248 AM.Disp = Op.getImm();
8250 addFullAddress(BuildMI(BB, DL, TII->get(Opc)), AM)
8251 .addReg(MI->getOperand(X86AddrNumOperands).getReg());
8253 // Reload the original control word now.
8254 addFrameReference(BuildMI(BB, DL, TII->get(X86::FLDCW16m)), CWFrameIdx);
8256 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
8259 // String/text processing lowering.
8260 case X86::PCMPISTRM128REG:
8261 return EmitPCMP(MI, BB, 3, false /* in-mem */);
8262 case X86::PCMPISTRM128MEM:
8263 return EmitPCMP(MI, BB, 3, true /* in-mem */);
8264 case X86::PCMPESTRM128REG:
8265 return EmitPCMP(MI, BB, 5, false /* in mem */);
8266 case X86::PCMPESTRM128MEM:
8267 return EmitPCMP(MI, BB, 5, true /* in mem */);
8270 case X86::ATOMAND32:
8271 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
8272 X86::AND32ri, X86::MOV32rm,
8273 X86::LCMPXCHG32, X86::MOV32rr,
8274 X86::NOT32r, X86::EAX,
8275 X86::GR32RegisterClass);
8277 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
8278 X86::OR32ri, X86::MOV32rm,
8279 X86::LCMPXCHG32, X86::MOV32rr,
8280 X86::NOT32r, X86::EAX,
8281 X86::GR32RegisterClass);
8282 case X86::ATOMXOR32:
8283 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
8284 X86::XOR32ri, X86::MOV32rm,
8285 X86::LCMPXCHG32, X86::MOV32rr,
8286 X86::NOT32r, X86::EAX,
8287 X86::GR32RegisterClass);
8288 case X86::ATOMNAND32:
8289 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
8290 X86::AND32ri, X86::MOV32rm,
8291 X86::LCMPXCHG32, X86::MOV32rr,
8292 X86::NOT32r, X86::EAX,
8293 X86::GR32RegisterClass, true);
8294 case X86::ATOMMIN32:
8295 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
8296 case X86::ATOMMAX32:
8297 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
8298 case X86::ATOMUMIN32:
8299 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
8300 case X86::ATOMUMAX32:
8301 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
8303 case X86::ATOMAND16:
8304 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
8305 X86::AND16ri, X86::MOV16rm,
8306 X86::LCMPXCHG16, X86::MOV16rr,
8307 X86::NOT16r, X86::AX,
8308 X86::GR16RegisterClass);
8310 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
8311 X86::OR16ri, X86::MOV16rm,
8312 X86::LCMPXCHG16, X86::MOV16rr,
8313 X86::NOT16r, X86::AX,
8314 X86::GR16RegisterClass);
8315 case X86::ATOMXOR16:
8316 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr,
8317 X86::XOR16ri, X86::MOV16rm,
8318 X86::LCMPXCHG16, X86::MOV16rr,
8319 X86::NOT16r, X86::AX,
8320 X86::GR16RegisterClass);
8321 case X86::ATOMNAND16:
8322 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
8323 X86::AND16ri, X86::MOV16rm,
8324 X86::LCMPXCHG16, X86::MOV16rr,
8325 X86::NOT16r, X86::AX,
8326 X86::GR16RegisterClass, true);
8327 case X86::ATOMMIN16:
8328 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr);
8329 case X86::ATOMMAX16:
8330 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr);
8331 case X86::ATOMUMIN16:
8332 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr);
8333 case X86::ATOMUMAX16:
8334 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr);
8337 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
8338 X86::AND8ri, X86::MOV8rm,
8339 X86::LCMPXCHG8, X86::MOV8rr,
8340 X86::NOT8r, X86::AL,
8341 X86::GR8RegisterClass);
8343 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
8344 X86::OR8ri, X86::MOV8rm,
8345 X86::LCMPXCHG8, X86::MOV8rr,
8346 X86::NOT8r, X86::AL,
8347 X86::GR8RegisterClass);
8349 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr,
8350 X86::XOR8ri, X86::MOV8rm,
8351 X86::LCMPXCHG8, X86::MOV8rr,
8352 X86::NOT8r, X86::AL,
8353 X86::GR8RegisterClass);
8354 case X86::ATOMNAND8:
8355 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
8356 X86::AND8ri, X86::MOV8rm,
8357 X86::LCMPXCHG8, X86::MOV8rr,
8358 X86::NOT8r, X86::AL,
8359 X86::GR8RegisterClass, true);
8360 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
8361 // This group is for 64-bit host.
8362 case X86::ATOMAND64:
8363 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
8364 X86::AND64ri32, X86::MOV64rm,
8365 X86::LCMPXCHG64, X86::MOV64rr,
8366 X86::NOT64r, X86::RAX,
8367 X86::GR64RegisterClass);
8369 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
8370 X86::OR64ri32, X86::MOV64rm,
8371 X86::LCMPXCHG64, X86::MOV64rr,
8372 X86::NOT64r, X86::RAX,
8373 X86::GR64RegisterClass);
8374 case X86::ATOMXOR64:
8375 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr,
8376 X86::XOR64ri32, X86::MOV64rm,
8377 X86::LCMPXCHG64, X86::MOV64rr,
8378 X86::NOT64r, X86::RAX,
8379 X86::GR64RegisterClass);
8380 case X86::ATOMNAND64:
8381 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
8382 X86::AND64ri32, X86::MOV64rm,
8383 X86::LCMPXCHG64, X86::MOV64rr,
8384 X86::NOT64r, X86::RAX,
8385 X86::GR64RegisterClass, true);
8386 case X86::ATOMMIN64:
8387 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr);
8388 case X86::ATOMMAX64:
8389 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr);
8390 case X86::ATOMUMIN64:
8391 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr);
8392 case X86::ATOMUMAX64:
8393 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr);
8395 // This group does 64-bit operations on a 32-bit host.
8396 case X86::ATOMAND6432:
8397 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8398 X86::AND32rr, X86::AND32rr,
8399 X86::AND32ri, X86::AND32ri,
8401 case X86::ATOMOR6432:
8402 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8403 X86::OR32rr, X86::OR32rr,
8404 X86::OR32ri, X86::OR32ri,
8406 case X86::ATOMXOR6432:
8407 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8408 X86::XOR32rr, X86::XOR32rr,
8409 X86::XOR32ri, X86::XOR32ri,
8411 case X86::ATOMNAND6432:
8412 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8413 X86::AND32rr, X86::AND32rr,
8414 X86::AND32ri, X86::AND32ri,
8416 case X86::ATOMADD6432:
8417 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8418 X86::ADD32rr, X86::ADC32rr,
8419 X86::ADD32ri, X86::ADC32ri,
8421 case X86::ATOMSUB6432:
8422 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8423 X86::SUB32rr, X86::SBB32rr,
8424 X86::SUB32ri, X86::SBB32ri,
8426 case X86::ATOMSWAP6432:
8427 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8428 X86::MOV32rr, X86::MOV32rr,
8429 X86::MOV32ri, X86::MOV32ri,
8431 case X86::VASTART_SAVE_XMM_REGS:
8432 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
8436 //===----------------------------------------------------------------------===//
8437 // X86 Optimization Hooks
8438 //===----------------------------------------------------------------------===//
8440 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
8444 const SelectionDAG &DAG,
8445 unsigned Depth) const {
8446 unsigned Opc = Op.getOpcode();
8447 assert((Opc >= ISD::BUILTIN_OP_END ||
8448 Opc == ISD::INTRINSIC_WO_CHAIN ||
8449 Opc == ISD::INTRINSIC_W_CHAIN ||
8450 Opc == ISD::INTRINSIC_VOID) &&
8451 "Should use MaskedValueIsZero if you don't know whether Op"
8452 " is a target node!");
8454 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything.
8466 // These nodes' second result is a boolean.
8467 if (Op.getResNo() == 0)
8471 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(),
8472 Mask.getBitWidth() - 1);
8477 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
8478 /// node is a GlobalAddress + offset.
8479 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
8480 GlobalValue* &GA, int64_t &Offset) const{
8481 if (N->getOpcode() == X86ISD::Wrapper) {
8482 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
8483 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
8484 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
8488 return TargetLowering::isGAPlusOffset(N, GA, Offset);
8491 static bool EltsFromConsecutiveLoads(ShuffleVectorSDNode *N, unsigned NumElems,
8492 EVT EltVT, LoadSDNode *&LDBase,
8493 unsigned &LastLoadedElt,
8494 SelectionDAG &DAG, MachineFrameInfo *MFI,
8495 const TargetLowering &TLI) {
8497 LastLoadedElt = -1U;
8498 for (unsigned i = 0; i < NumElems; ++i) {
8499 if (N->getMaskElt(i) < 0) {
8505 SDValue Elt = DAG.getShuffleScalarElt(N, i);
8506 if (!Elt.getNode() ||
8507 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
8510 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
8512 LDBase = cast<LoadSDNode>(Elt.getNode());
8516 if (Elt.getOpcode() == ISD::UNDEF)
8519 LoadSDNode *LD = cast<LoadSDNode>(Elt);
8520 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
8527 /// PerformShuffleCombine - Combine a vector_shuffle that is equal to
8528 /// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load
8529 /// if the load addresses are consecutive, non-overlapping, and in the right
8530 /// order. In the case of v2i64, it will see if it can rewrite the
8531 /// shuffle to be an appropriate build vector so it can take advantage of
8532 // performBuildVectorCombine.
8533 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
8534 const TargetLowering &TLI) {
8535 DebugLoc dl = N->getDebugLoc();
8536 EVT VT = N->getValueType(0);
8537 EVT EltVT = VT.getVectorElementType();
8538 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
8539 unsigned NumElems = VT.getVectorNumElements();
8541 if (VT.getSizeInBits() != 128)
8544 // Try to combine a vector_shuffle into a 128-bit load.
8545 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
8546 LoadSDNode *LD = NULL;
8547 unsigned LastLoadedElt;
8548 if (!EltsFromConsecutiveLoads(SVN, NumElems, EltVT, LD, LastLoadedElt, DAG,
8552 if (LastLoadedElt == NumElems - 1) {
8553 if (DAG.InferPtrAlignment(LD->getBasePtr()) >= 16)
8554 return DAG.getLoad(VT, dl, LD->getChain(), LD->getBasePtr(),
8555 LD->getSrcValue(), LD->getSrcValueOffset(),
8557 return DAG.getLoad(VT, dl, LD->getChain(), LD->getBasePtr(),
8558 LD->getSrcValue(), LD->getSrcValueOffset(),
8559 LD->isVolatile(), LD->getAlignment());
8560 } else if (NumElems == 4 && LastLoadedElt == 1) {
8561 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
8562 SDValue Ops[] = { LD->getChain(), LD->getBasePtr() };
8563 SDValue ResNode = DAG.getNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2);
8564 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, ResNode);
8569 /// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes.
8570 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
8571 const X86Subtarget *Subtarget) {
8572 DebugLoc DL = N->getDebugLoc();
8573 SDValue Cond = N->getOperand(0);
8574 // Get the LHS/RHS of the select.
8575 SDValue LHS = N->getOperand(1);
8576 SDValue RHS = N->getOperand(2);
8578 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
8579 // instructions have the peculiarity that if either operand is a NaN,
8580 // they chose what we call the RHS operand (and as such are not symmetric).
8581 // It happens that this matches the semantics of the common C idiom
8582 // x<y?x:y and related forms, so we can recognize these cases.
8583 if (Subtarget->hasSSE2() &&
8584 (LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64) &&
8585 Cond.getOpcode() == ISD::SETCC) {
8586 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
8588 unsigned Opcode = 0;
8589 // Check for x CC y ? x : y.
8590 if (LHS == Cond.getOperand(0) && RHS == Cond.getOperand(1)) {
8594 // This can be a min if we can prove that at least one of the operands
8596 if (!FiniteOnlyFPMath()) {
8597 if (DAG.isKnownNeverNaN(RHS)) {
8598 // Put the potential NaN in the RHS so that SSE will preserve it.
8599 std::swap(LHS, RHS);
8600 } else if (!DAG.isKnownNeverNaN(LHS))
8603 Opcode = X86ISD::FMIN;
8606 // This can be a min if we can prove that at least one of the operands
8608 if (!FiniteOnlyFPMath()) {
8609 if (DAG.isKnownNeverNaN(LHS)) {
8610 // Put the potential NaN in the RHS so that SSE will preserve it.
8611 std::swap(LHS, RHS);
8612 } else if (!DAG.isKnownNeverNaN(RHS))
8615 Opcode = X86ISD::FMIN;
8618 // This can be a min, but if either operand is a NaN we need it to
8619 // preserve the original LHS.
8620 std::swap(LHS, RHS);
8624 Opcode = X86ISD::FMIN;
8628 // This can be a max if we can prove that at least one of the operands
8630 if (!FiniteOnlyFPMath()) {
8631 if (DAG.isKnownNeverNaN(LHS)) {
8632 // Put the potential NaN in the RHS so that SSE will preserve it.
8633 std::swap(LHS, RHS);
8634 } else if (!DAG.isKnownNeverNaN(RHS))
8637 Opcode = X86ISD::FMAX;
8640 // This can be a max if we can prove that at least one of the operands
8642 if (!FiniteOnlyFPMath()) {
8643 if (DAG.isKnownNeverNaN(RHS)) {
8644 // Put the potential NaN in the RHS so that SSE will preserve it.
8645 std::swap(LHS, RHS);
8646 } else if (!DAG.isKnownNeverNaN(LHS))
8649 Opcode = X86ISD::FMAX;
8652 // This can be a max, but if either operand is a NaN we need it to
8653 // preserve the original LHS.
8654 std::swap(LHS, RHS);
8658 Opcode = X86ISD::FMAX;
8661 // Check for x CC y ? y : x -- a min/max with reversed arms.
8662 } else if (LHS == Cond.getOperand(1) && RHS == Cond.getOperand(0)) {
8666 // This can be a min if we can prove that at least one of the operands
8668 if (!FiniteOnlyFPMath()) {
8669 if (DAG.isKnownNeverNaN(RHS)) {
8670 // Put the potential NaN in the RHS so that SSE will preserve it.
8671 std::swap(LHS, RHS);
8672 } else if (!DAG.isKnownNeverNaN(LHS))
8675 Opcode = X86ISD::FMIN;
8678 // This can be a min if we can prove that at least one of the operands
8680 if (!FiniteOnlyFPMath()) {
8681 if (DAG.isKnownNeverNaN(LHS)) {
8682 // Put the potential NaN in the RHS so that SSE will preserve it.
8683 std::swap(LHS, RHS);
8684 } else if (!DAG.isKnownNeverNaN(RHS))
8687 Opcode = X86ISD::FMIN;
8690 // This can be a min, but if either operand is a NaN we need it to
8691 // preserve the original LHS.
8692 std::swap(LHS, RHS);
8696 Opcode = X86ISD::FMIN;
8700 // This can be a max if we can prove that at least one of the operands
8702 if (!FiniteOnlyFPMath()) {
8703 if (DAG.isKnownNeverNaN(LHS)) {
8704 // Put the potential NaN in the RHS so that SSE will preserve it.
8705 std::swap(LHS, RHS);
8706 } else if (!DAG.isKnownNeverNaN(RHS))
8709 Opcode = X86ISD::FMAX;
8712 // This can be a max if we can prove that at least one of the operands
8714 if (!FiniteOnlyFPMath()) {
8715 if (DAG.isKnownNeverNaN(RHS)) {
8716 // Put the potential NaN in the RHS so that SSE will preserve it.
8717 std::swap(LHS, RHS);
8718 } else if (!DAG.isKnownNeverNaN(LHS))
8721 Opcode = X86ISD::FMAX;
8724 // This can be a max, but if either operand is a NaN we need it to
8725 // preserve the original LHS.
8726 std::swap(LHS, RHS);
8730 Opcode = X86ISD::FMAX;
8736 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
8739 // If this is a select between two integer constants, try to do some
8741 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
8742 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
8743 // Don't do this for crazy integer types.
8744 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
8745 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
8746 // so that TrueC (the true value) is larger than FalseC.
8747 bool NeedsCondInvert = false;
8749 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
8750 // Efficiently invertible.
8751 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
8752 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
8753 isa<ConstantSDNode>(Cond.getOperand(1))))) {
8754 NeedsCondInvert = true;
8755 std::swap(TrueC, FalseC);
8758 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
8759 if (FalseC->getAPIntValue() == 0 &&
8760 TrueC->getAPIntValue().isPowerOf2()) {
8761 if (NeedsCondInvert) // Invert the condition if needed.
8762 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
8763 DAG.getConstant(1, Cond.getValueType()));
8765 // Zero extend the condition if needed.
8766 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
8768 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
8769 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
8770 DAG.getConstant(ShAmt, MVT::i8));
8773 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
8774 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
8775 if (NeedsCondInvert) // Invert the condition if needed.
8776 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
8777 DAG.getConstant(1, Cond.getValueType()));
8779 // Zero extend the condition if needed.
8780 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
8781 FalseC->getValueType(0), Cond);
8782 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
8783 SDValue(FalseC, 0));
8786 // Optimize cases that will turn into an LEA instruction. This requires
8787 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
8788 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
8789 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
8790 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
8792 bool isFastMultiplier = false;
8794 switch ((unsigned char)Diff) {
8796 case 1: // result = add base, cond
8797 case 2: // result = lea base( , cond*2)
8798 case 3: // result = lea base(cond, cond*2)
8799 case 4: // result = lea base( , cond*4)
8800 case 5: // result = lea base(cond, cond*4)
8801 case 8: // result = lea base( , cond*8)
8802 case 9: // result = lea base(cond, cond*8)
8803 isFastMultiplier = true;
8808 if (isFastMultiplier) {
8809 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
8810 if (NeedsCondInvert) // Invert the condition if needed.
8811 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
8812 DAG.getConstant(1, Cond.getValueType()));
8814 // Zero extend the condition if needed.
8815 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
8817 // Scale the condition by the difference.
8819 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
8820 DAG.getConstant(Diff, Cond.getValueType()));
8822 // Add the base if non-zero.
8823 if (FalseC->getAPIntValue() != 0)
8824 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
8825 SDValue(FalseC, 0));
8835 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
8836 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
8837 TargetLowering::DAGCombinerInfo &DCI) {
8838 DebugLoc DL = N->getDebugLoc();
8840 // If the flag operand isn't dead, don't touch this CMOV.
8841 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
8844 // If this is a select between two integer constants, try to do some
8845 // optimizations. Note that the operands are ordered the opposite of SELECT
8847 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
8848 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
8849 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
8850 // larger than FalseC (the false value).
8851 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
8853 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
8854 CC = X86::GetOppositeBranchCondition(CC);
8855 std::swap(TrueC, FalseC);
8858 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
8859 // This is efficient for any integer data type (including i8/i16) and
8861 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
8862 SDValue Cond = N->getOperand(3);
8863 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
8864 DAG.getConstant(CC, MVT::i8), Cond);
8866 // Zero extend the condition if needed.
8867 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
8869 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
8870 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
8871 DAG.getConstant(ShAmt, MVT::i8));
8872 if (N->getNumValues() == 2) // Dead flag value?
8873 return DCI.CombineTo(N, Cond, SDValue());
8877 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
8878 // for any integer data type, including i8/i16.
8879 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
8880 SDValue Cond = N->getOperand(3);
8881 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
8882 DAG.getConstant(CC, MVT::i8), Cond);
8884 // Zero extend the condition if needed.
8885 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
8886 FalseC->getValueType(0), Cond);
8887 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
8888 SDValue(FalseC, 0));
8890 if (N->getNumValues() == 2) // Dead flag value?
8891 return DCI.CombineTo(N, Cond, SDValue());
8895 // Optimize cases that will turn into an LEA instruction. This requires
8896 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
8897 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
8898 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
8899 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
8901 bool isFastMultiplier = false;
8903 switch ((unsigned char)Diff) {
8905 case 1: // result = add base, cond
8906 case 2: // result = lea base( , cond*2)
8907 case 3: // result = lea base(cond, cond*2)
8908 case 4: // result = lea base( , cond*4)
8909 case 5: // result = lea base(cond, cond*4)
8910 case 8: // result = lea base( , cond*8)
8911 case 9: // result = lea base(cond, cond*8)
8912 isFastMultiplier = true;
8917 if (isFastMultiplier) {
8918 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
8919 SDValue Cond = N->getOperand(3);
8920 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
8921 DAG.getConstant(CC, MVT::i8), Cond);
8922 // Zero extend the condition if needed.
8923 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
8925 // Scale the condition by the difference.
8927 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
8928 DAG.getConstant(Diff, Cond.getValueType()));
8930 // Add the base if non-zero.
8931 if (FalseC->getAPIntValue() != 0)
8932 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
8933 SDValue(FalseC, 0));
8934 if (N->getNumValues() == 2) // Dead flag value?
8935 return DCI.CombineTo(N, Cond, SDValue());
8945 /// PerformMulCombine - Optimize a single multiply with constant into two
8946 /// in order to implement it with two cheaper instructions, e.g.
8947 /// LEA + SHL, LEA + LEA.
8948 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
8949 TargetLowering::DAGCombinerInfo &DCI) {
8950 if (DAG.getMachineFunction().
8951 getFunction()->hasFnAttr(Attribute::OptimizeForSize))
8954 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
8957 EVT VT = N->getValueType(0);
8961 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
8964 uint64_t MulAmt = C->getZExtValue();
8965 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
8968 uint64_t MulAmt1 = 0;
8969 uint64_t MulAmt2 = 0;
8970 if ((MulAmt % 9) == 0) {
8972 MulAmt2 = MulAmt / 9;
8973 } else if ((MulAmt % 5) == 0) {
8975 MulAmt2 = MulAmt / 5;
8976 } else if ((MulAmt % 3) == 0) {
8978 MulAmt2 = MulAmt / 3;
8981 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
8982 DebugLoc DL = N->getDebugLoc();
8984 if (isPowerOf2_64(MulAmt2) &&
8985 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
8986 // If second multiplifer is pow2, issue it first. We want the multiply by
8987 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
8989 std::swap(MulAmt1, MulAmt2);
8992 if (isPowerOf2_64(MulAmt1))
8993 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
8994 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
8996 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
8997 DAG.getConstant(MulAmt1, VT));
8999 if (isPowerOf2_64(MulAmt2))
9000 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
9001 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
9003 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
9004 DAG.getConstant(MulAmt2, VT));
9006 // Do not add new nodes to DAG combiner worklist.
9007 DCI.CombineTo(N, NewMul, false);
9012 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
9013 SDValue N0 = N->getOperand(0);
9014 SDValue N1 = N->getOperand(1);
9015 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
9016 EVT VT = N0.getValueType();
9018 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
9019 // since the result of setcc_c is all zero's or all ones.
9020 if (N1C && N0.getOpcode() == ISD::AND &&
9021 N0.getOperand(1).getOpcode() == ISD::Constant) {
9022 SDValue N00 = N0.getOperand(0);
9023 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
9024 ((N00.getOpcode() == ISD::ANY_EXTEND ||
9025 N00.getOpcode() == ISD::ZERO_EXTEND) &&
9026 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
9027 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
9028 APInt ShAmt = N1C->getAPIntValue();
9029 Mask = Mask.shl(ShAmt);
9031 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
9032 N00, DAG.getConstant(Mask, VT));
9039 /// PerformShiftCombine - Transforms vector shift nodes to use vector shifts
9041 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
9042 const X86Subtarget *Subtarget) {
9043 EVT VT = N->getValueType(0);
9044 if (!VT.isVector() && VT.isInteger() &&
9045 N->getOpcode() == ISD::SHL)
9046 return PerformSHLCombine(N, DAG);
9048 // On X86 with SSE2 support, we can transform this to a vector shift if
9049 // all elements are shifted by the same amount. We can't do this in legalize
9050 // because the a constant vector is typically transformed to a constant pool
9051 // so we have no knowledge of the shift amount.
9052 if (!Subtarget->hasSSE2())
9055 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
9058 SDValue ShAmtOp = N->getOperand(1);
9059 EVT EltVT = VT.getVectorElementType();
9060 DebugLoc DL = N->getDebugLoc();
9061 SDValue BaseShAmt = SDValue();
9062 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
9063 unsigned NumElts = VT.getVectorNumElements();
9065 for (; i != NumElts; ++i) {
9066 SDValue Arg = ShAmtOp.getOperand(i);
9067 if (Arg.getOpcode() == ISD::UNDEF) continue;
9071 for (; i != NumElts; ++i) {
9072 SDValue Arg = ShAmtOp.getOperand(i);
9073 if (Arg.getOpcode() == ISD::UNDEF) continue;
9074 if (Arg != BaseShAmt) {
9078 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
9079 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) {
9080 SDValue InVec = ShAmtOp.getOperand(0);
9081 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
9082 unsigned NumElts = InVec.getValueType().getVectorNumElements();
9084 for (; i != NumElts; ++i) {
9085 SDValue Arg = InVec.getOperand(i);
9086 if (Arg.getOpcode() == ISD::UNDEF) continue;
9090 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
9091 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
9092 unsigned SplatIdx = cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex();
9093 if (C->getZExtValue() == SplatIdx)
9094 BaseShAmt = InVec.getOperand(1);
9097 if (BaseShAmt.getNode() == 0)
9098 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
9099 DAG.getIntPtrConstant(0));
9103 // The shift amount is an i32.
9104 if (EltVT.bitsGT(MVT::i32))
9105 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt);
9106 else if (EltVT.bitsLT(MVT::i32))
9107 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt);
9109 // The shift amount is identical so we can do a vector shift.
9110 SDValue ValOp = N->getOperand(0);
9111 switch (N->getOpcode()) {
9113 llvm_unreachable("Unknown shift opcode!");
9116 if (VT == MVT::v2i64)
9117 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9118 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
9120 if (VT == MVT::v4i32)
9121 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9122 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
9124 if (VT == MVT::v8i16)
9125 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9126 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
9130 if (VT == MVT::v4i32)
9131 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9132 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32),
9134 if (VT == MVT::v8i16)
9135 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9136 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32),
9140 if (VT == MVT::v2i64)
9141 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9142 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
9144 if (VT == MVT::v4i32)
9145 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9146 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32),
9148 if (VT == MVT::v8i16)
9149 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9150 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32),
9157 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
9158 const X86Subtarget *Subtarget) {
9159 EVT VT = N->getValueType(0);
9160 if (VT != MVT::i64 || !Subtarget->is64Bit())
9163 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
9164 SDValue N0 = N->getOperand(0);
9165 SDValue N1 = N->getOperand(1);
9166 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
9168 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
9171 SDValue ShAmt0 = N0.getOperand(1);
9172 if (ShAmt0.getValueType() != MVT::i8)
9174 SDValue ShAmt1 = N1.getOperand(1);
9175 if (ShAmt1.getValueType() != MVT::i8)
9177 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
9178 ShAmt0 = ShAmt0.getOperand(0);
9179 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
9180 ShAmt1 = ShAmt1.getOperand(0);
9182 DebugLoc DL = N->getDebugLoc();
9183 unsigned Opc = X86ISD::SHLD;
9184 SDValue Op0 = N0.getOperand(0);
9185 SDValue Op1 = N1.getOperand(0);
9186 if (ShAmt0.getOpcode() == ISD::SUB) {
9188 std::swap(Op0, Op1);
9189 std::swap(ShAmt0, ShAmt1);
9192 if (ShAmt1.getOpcode() == ISD::SUB) {
9193 SDValue Sum = ShAmt1.getOperand(0);
9194 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
9195 if (SumC->getSExtValue() == 64 &&
9196 ShAmt1.getOperand(1) == ShAmt0)
9197 return DAG.getNode(Opc, DL, VT,
9199 DAG.getNode(ISD::TRUNCATE, DL,
9202 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
9203 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
9205 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == 64)
9206 return DAG.getNode(Opc, DL, VT,
9207 N0.getOperand(0), N1.getOperand(0),
9208 DAG.getNode(ISD::TRUNCATE, DL,
9215 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
9216 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
9217 const X86Subtarget *Subtarget) {
9218 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
9219 // the FP state in cases where an emms may be missing.
9220 // A preferable solution to the general problem is to figure out the right
9221 // places to insert EMMS. This qualifies as a quick hack.
9223 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
9224 StoreSDNode *St = cast<StoreSDNode>(N);
9225 EVT VT = St->getValue().getValueType();
9226 if (VT.getSizeInBits() != 64)
9229 const Function *F = DAG.getMachineFunction().getFunction();
9230 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
9231 bool F64IsLegal = !UseSoftFloat && !NoImplicitFloatOps
9232 && Subtarget->hasSSE2();
9233 if ((VT.isVector() ||
9234 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
9235 isa<LoadSDNode>(St->getValue()) &&
9236 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
9237 St->getChain().hasOneUse() && !St->isVolatile()) {
9238 SDNode* LdVal = St->getValue().getNode();
9240 int TokenFactorIndex = -1;
9241 SmallVector<SDValue, 8> Ops;
9242 SDNode* ChainVal = St->getChain().getNode();
9243 // Must be a store of a load. We currently handle two cases: the load
9244 // is a direct child, and it's under an intervening TokenFactor. It is
9245 // possible to dig deeper under nested TokenFactors.
9246 if (ChainVal == LdVal)
9247 Ld = cast<LoadSDNode>(St->getChain());
9248 else if (St->getValue().hasOneUse() &&
9249 ChainVal->getOpcode() == ISD::TokenFactor) {
9250 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) {
9251 if (ChainVal->getOperand(i).getNode() == LdVal) {
9252 TokenFactorIndex = i;
9253 Ld = cast<LoadSDNode>(St->getValue());
9255 Ops.push_back(ChainVal->getOperand(i));
9259 if (!Ld || !ISD::isNormalLoad(Ld))
9262 // If this is not the MMX case, i.e. we are just turning i64 load/store
9263 // into f64 load/store, avoid the transformation if there are multiple
9264 // uses of the loaded value.
9265 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
9268 DebugLoc LdDL = Ld->getDebugLoc();
9269 DebugLoc StDL = N->getDebugLoc();
9270 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
9271 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
9273 if (Subtarget->is64Bit() || F64IsLegal) {
9274 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
9275 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(),
9276 Ld->getBasePtr(), Ld->getSrcValue(),
9277 Ld->getSrcValueOffset(), Ld->isVolatile(),
9278 Ld->getAlignment());
9279 SDValue NewChain = NewLd.getValue(1);
9280 if (TokenFactorIndex != -1) {
9281 Ops.push_back(NewChain);
9282 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
9285 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
9286 St->getSrcValue(), St->getSrcValueOffset(),
9287 St->isVolatile(), St->getAlignment());
9290 // Otherwise, lower to two pairs of 32-bit loads / stores.
9291 SDValue LoAddr = Ld->getBasePtr();
9292 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
9293 DAG.getConstant(4, MVT::i32));
9295 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
9296 Ld->getSrcValue(), Ld->getSrcValueOffset(),
9297 Ld->isVolatile(), Ld->getAlignment());
9298 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
9299 Ld->getSrcValue(), Ld->getSrcValueOffset()+4,
9301 MinAlign(Ld->getAlignment(), 4));
9303 SDValue NewChain = LoLd.getValue(1);
9304 if (TokenFactorIndex != -1) {
9305 Ops.push_back(LoLd);
9306 Ops.push_back(HiLd);
9307 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
9311 LoAddr = St->getBasePtr();
9312 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
9313 DAG.getConstant(4, MVT::i32));
9315 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
9316 St->getSrcValue(), St->getSrcValueOffset(),
9317 St->isVolatile(), St->getAlignment());
9318 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
9320 St->getSrcValueOffset() + 4,
9322 MinAlign(St->getAlignment(), 4));
9323 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
9328 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
9329 /// X86ISD::FXOR nodes.
9330 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
9331 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
9332 // F[X]OR(0.0, x) -> x
9333 // F[X]OR(x, 0.0) -> x
9334 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
9335 if (C->getValueAPF().isPosZero())
9336 return N->getOperand(1);
9337 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
9338 if (C->getValueAPF().isPosZero())
9339 return N->getOperand(0);
9343 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
9344 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
9345 // FAND(0.0, x) -> 0.0
9346 // FAND(x, 0.0) -> 0.0
9347 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
9348 if (C->getValueAPF().isPosZero())
9349 return N->getOperand(0);
9350 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
9351 if (C->getValueAPF().isPosZero())
9352 return N->getOperand(1);
9356 static SDValue PerformBTCombine(SDNode *N,
9358 TargetLowering::DAGCombinerInfo &DCI) {
9359 // BT ignores high bits in the bit index operand.
9360 SDValue Op1 = N->getOperand(1);
9361 if (Op1.hasOneUse()) {
9362 unsigned BitWidth = Op1.getValueSizeInBits();
9363 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
9364 APInt KnownZero, KnownOne;
9365 TargetLowering::TargetLoweringOpt TLO(DAG);
9366 TargetLowering &TLI = DAG.getTargetLoweringInfo();
9367 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
9368 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
9369 DCI.CommitTargetLoweringOpt(TLO);
9374 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
9375 SDValue Op = N->getOperand(0);
9376 if (Op.getOpcode() == ISD::BIT_CONVERT)
9377 Op = Op.getOperand(0);
9378 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
9379 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
9380 VT.getVectorElementType().getSizeInBits() ==
9381 OpVT.getVectorElementType().getSizeInBits()) {
9382 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, Op);
9387 // On X86 and X86-64, atomic operations are lowered to locked instructions.
9388 // Locked instructions, in turn, have implicit fence semantics (all memory
9389 // operations are flushed before issuing the locked instruction, and the
9390 // are not buffered), so we can fold away the common pattern of
9391 // fence-atomic-fence.
9392 static SDValue PerformMEMBARRIERCombine(SDNode* N, SelectionDAG &DAG) {
9393 SDValue atomic = N->getOperand(0);
9394 switch (atomic.getOpcode()) {
9395 case ISD::ATOMIC_CMP_SWAP:
9396 case ISD::ATOMIC_SWAP:
9397 case ISD::ATOMIC_LOAD_ADD:
9398 case ISD::ATOMIC_LOAD_SUB:
9399 case ISD::ATOMIC_LOAD_AND:
9400 case ISD::ATOMIC_LOAD_OR:
9401 case ISD::ATOMIC_LOAD_XOR:
9402 case ISD::ATOMIC_LOAD_NAND:
9403 case ISD::ATOMIC_LOAD_MIN:
9404 case ISD::ATOMIC_LOAD_MAX:
9405 case ISD::ATOMIC_LOAD_UMIN:
9406 case ISD::ATOMIC_LOAD_UMAX:
9412 SDValue fence = atomic.getOperand(0);
9413 if (fence.getOpcode() != ISD::MEMBARRIER)
9416 switch (atomic.getOpcode()) {
9417 case ISD::ATOMIC_CMP_SWAP:
9418 return DAG.UpdateNodeOperands(atomic, fence.getOperand(0),
9419 atomic.getOperand(1), atomic.getOperand(2),
9420 atomic.getOperand(3));
9421 case ISD::ATOMIC_SWAP:
9422 case ISD::ATOMIC_LOAD_ADD:
9423 case ISD::ATOMIC_LOAD_SUB:
9424 case ISD::ATOMIC_LOAD_AND:
9425 case ISD::ATOMIC_LOAD_OR:
9426 case ISD::ATOMIC_LOAD_XOR:
9427 case ISD::ATOMIC_LOAD_NAND:
9428 case ISD::ATOMIC_LOAD_MIN:
9429 case ISD::ATOMIC_LOAD_MAX:
9430 case ISD::ATOMIC_LOAD_UMIN:
9431 case ISD::ATOMIC_LOAD_UMAX:
9432 return DAG.UpdateNodeOperands(atomic, fence.getOperand(0),
9433 atomic.getOperand(1), atomic.getOperand(2));
9439 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG) {
9440 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
9441 // (and (i32 x86isd::setcc_carry), 1)
9442 // This eliminates the zext. This transformation is necessary because
9443 // ISD::SETCC is always legalized to i8.
9444 DebugLoc dl = N->getDebugLoc();
9445 SDValue N0 = N->getOperand(0);
9446 EVT VT = N->getValueType(0);
9447 if (N0.getOpcode() == ISD::AND &&
9449 N0.getOperand(0).hasOneUse()) {
9450 SDValue N00 = N0.getOperand(0);
9451 if (N00.getOpcode() != X86ISD::SETCC_CARRY)
9453 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
9454 if (!C || C->getZExtValue() != 1)
9456 return DAG.getNode(ISD::AND, dl, VT,
9457 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
9458 N00.getOperand(0), N00.getOperand(1)),
9459 DAG.getConstant(1, VT));
9465 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
9466 DAGCombinerInfo &DCI) const {
9467 SelectionDAG &DAG = DCI.DAG;
9468 switch (N->getOpcode()) {
9470 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, *this);
9471 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget);
9472 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI);
9473 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
9476 case ISD::SRL: return PerformShiftCombine(N, DAG, Subtarget);
9477 case ISD::OR: return PerformOrCombine(N, DAG, Subtarget);
9478 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
9480 case X86ISD::FOR: return PerformFORCombine(N, DAG);
9481 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
9482 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
9483 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
9484 case ISD::MEMBARRIER: return PerformMEMBARRIERCombine(N, DAG);
9485 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG);
9491 //===----------------------------------------------------------------------===//
9492 // X86 Inline Assembly Support
9493 //===----------------------------------------------------------------------===//
9495 static bool LowerToBSwap(CallInst *CI) {
9496 // FIXME: this should verify that we are targetting a 486 or better. If not,
9497 // we will turn this bswap into something that will be lowered to logical ops
9498 // instead of emitting the bswap asm. For now, we don't support 486 or lower
9499 // so don't worry about this.
9501 // Verify this is a simple bswap.
9502 if (CI->getNumOperands() != 2 ||
9503 CI->getType() != CI->getOperand(1)->getType() ||
9504 !CI->getType()->isInteger())
9507 const IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
9508 if (!Ty || Ty->getBitWidth() % 16 != 0)
9511 // Okay, we can do this xform, do so now.
9512 const Type *Tys[] = { Ty };
9513 Module *M = CI->getParent()->getParent()->getParent();
9514 Constant *Int = Intrinsic::getDeclaration(M, Intrinsic::bswap, Tys, 1);
9516 Value *Op = CI->getOperand(1);
9517 Op = CallInst::Create(Int, Op, CI->getName(), CI);
9519 CI->replaceAllUsesWith(Op);
9520 CI->eraseFromParent();
9524 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
9525 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
9526 std::vector<InlineAsm::ConstraintInfo> Constraints = IA->ParseConstraints();
9528 std::string AsmStr = IA->getAsmString();
9530 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
9531 std::vector<std::string> AsmPieces;
9532 SplitString(AsmStr, AsmPieces, "\n"); // ; as separator?
9534 switch (AsmPieces.size()) {
9535 default: return false;
9537 AsmStr = AsmPieces[0];
9539 SplitString(AsmStr, AsmPieces, " \t"); // Split with whitespace.
9542 if (AsmPieces.size() == 2 &&
9543 (AsmPieces[0] == "bswap" ||
9544 AsmPieces[0] == "bswapq" ||
9545 AsmPieces[0] == "bswapl") &&
9546 (AsmPieces[1] == "$0" ||
9547 AsmPieces[1] == "${0:q}")) {
9548 // No need to check constraints, nothing other than the equivalent of
9549 // "=r,0" would be valid here.
9550 return LowerToBSwap(CI);
9552 // rorw $$8, ${0:w} --> llvm.bswap.i16
9553 if (CI->getType()->isInteger(16) &&
9554 AsmPieces.size() == 3 &&
9555 AsmPieces[0] == "rorw" &&
9556 AsmPieces[1] == "$$8," &&
9557 AsmPieces[2] == "${0:w}" &&
9558 IA->getConstraintString() == "=r,0,~{dirflag},~{fpsr},~{flags},~{cc}") {
9559 return LowerToBSwap(CI);
9563 if (CI->getType()->isInteger(64) &&
9564 Constraints.size() >= 2 &&
9565 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
9566 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
9567 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
9568 std::vector<std::string> Words;
9569 SplitString(AsmPieces[0], Words, " \t");
9570 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%eax") {
9572 SplitString(AsmPieces[1], Words, " \t");
9573 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%edx") {
9575 SplitString(AsmPieces[2], Words, " \t,");
9576 if (Words.size() == 3 && Words[0] == "xchgl" && Words[1] == "%eax" &&
9577 Words[2] == "%edx") {
9578 return LowerToBSwap(CI);
9590 /// getConstraintType - Given a constraint letter, return the type of
9591 /// constraint it is for this target.
9592 X86TargetLowering::ConstraintType
9593 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
9594 if (Constraint.size() == 1) {
9595 switch (Constraint[0]) {
9607 return C_RegisterClass;
9615 return TargetLowering::getConstraintType(Constraint);
9618 /// LowerXConstraint - try to replace an X constraint, which matches anything,
9619 /// with another that has more specific requirements based on the type of the
9620 /// corresponding operand.
9621 const char *X86TargetLowering::
9622 LowerXConstraint(EVT ConstraintVT) const {
9623 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
9624 // 'f' like normal targets.
9625 if (ConstraintVT.isFloatingPoint()) {
9626 if (Subtarget->hasSSE2())
9628 if (Subtarget->hasSSE1())
9632 return TargetLowering::LowerXConstraint(ConstraintVT);
9635 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
9636 /// vector. If it is invalid, don't add anything to Ops.
9637 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
9640 std::vector<SDValue>&Ops,
9641 SelectionDAG &DAG) const {
9642 SDValue Result(0, 0);
9644 switch (Constraint) {
9647 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
9648 if (C->getZExtValue() <= 31) {
9649 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
9655 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
9656 if (C->getZExtValue() <= 63) {
9657 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
9663 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
9664 if ((int8_t)C->getSExtValue() == C->getSExtValue()) {
9665 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
9671 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
9672 if (C->getZExtValue() <= 255) {
9673 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
9679 // 32-bit signed value
9680 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
9681 const ConstantInt *CI = C->getConstantIntValue();
9682 if (CI->isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
9683 C->getSExtValue())) {
9684 // Widen to 64 bits here to get it sign extended.
9685 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
9688 // FIXME gcc accepts some relocatable values here too, but only in certain
9689 // memory models; it's complicated.
9694 // 32-bit unsigned value
9695 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
9696 const ConstantInt *CI = C->getConstantIntValue();
9697 if (CI->isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
9698 C->getZExtValue())) {
9699 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
9703 // FIXME gcc accepts some relocatable values here too, but only in certain
9704 // memory models; it's complicated.
9708 // Literal immediates are always ok.
9709 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
9710 // Widen to 64 bits here to get it sign extended.
9711 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
9715 // If we are in non-pic codegen mode, we allow the address of a global (with
9716 // an optional displacement) to be used with 'i'.
9717 GlobalAddressSDNode *GA = 0;
9720 // Match either (GA), (GA+C), (GA+C1+C2), etc.
9722 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
9723 Offset += GA->getOffset();
9725 } else if (Op.getOpcode() == ISD::ADD) {
9726 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
9727 Offset += C->getZExtValue();
9728 Op = Op.getOperand(0);
9731 } else if (Op.getOpcode() == ISD::SUB) {
9732 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
9733 Offset += -C->getZExtValue();
9734 Op = Op.getOperand(0);
9739 // Otherwise, this isn't something we can handle, reject it.
9743 GlobalValue *GV = GA->getGlobal();
9744 // If we require an extra load to get this address, as in PIC mode, we
9746 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
9747 getTargetMachine())))
9751 Op = LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
9753 Op = DAG.getTargetGlobalAddress(GV, GA->getValueType(0), Offset);
9759 if (Result.getNode()) {
9760 Ops.push_back(Result);
9763 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, hasMemory,
9767 std::vector<unsigned> X86TargetLowering::
9768 getRegClassForInlineAsmConstraint(const std::string &Constraint,
9770 if (Constraint.size() == 1) {
9771 // FIXME: not handling fp-stack yet!
9772 switch (Constraint[0]) { // GCC X86 Constraint Letters
9773 default: break; // Unknown constraint letter
9774 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
9775 if (Subtarget->is64Bit()) {
9777 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX,
9778 X86::ESI, X86::EDI, X86::R8D, X86::R9D,
9779 X86::R10D,X86::R11D,X86::R12D,
9780 X86::R13D,X86::R14D,X86::R15D,
9781 X86::EBP, X86::ESP, 0);
9782 else if (VT == MVT::i16)
9783 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX,
9784 X86::SI, X86::DI, X86::R8W,X86::R9W,
9785 X86::R10W,X86::R11W,X86::R12W,
9786 X86::R13W,X86::R14W,X86::R15W,
9787 X86::BP, X86::SP, 0);
9788 else if (VT == MVT::i8)
9789 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL,
9790 X86::SIL, X86::DIL, X86::R8B,X86::R9B,
9791 X86::R10B,X86::R11B,X86::R12B,
9792 X86::R13B,X86::R14B,X86::R15B,
9793 X86::BPL, X86::SPL, 0);
9795 else if (VT == MVT::i64)
9796 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX,
9797 X86::RSI, X86::RDI, X86::R8, X86::R9,
9798 X86::R10, X86::R11, X86::R12,
9799 X86::R13, X86::R14, X86::R15,
9800 X86::RBP, X86::RSP, 0);
9804 // 32-bit fallthrough
9807 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0);
9808 else if (VT == MVT::i16)
9809 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0);
9810 else if (VT == MVT::i8)
9811 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 0);
9812 else if (VT == MVT::i64)
9813 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, 0);
9818 return std::vector<unsigned>();
9821 std::pair<unsigned, const TargetRegisterClass*>
9822 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
9824 // First, see if this is a constraint that directly corresponds to an LLVM
9826 if (Constraint.size() == 1) {
9827 // GCC Constraint Letters
9828 switch (Constraint[0]) {
9830 case 'r': // GENERAL_REGS
9831 case 'l': // INDEX_REGS
9833 return std::make_pair(0U, X86::GR8RegisterClass);
9835 return std::make_pair(0U, X86::GR16RegisterClass);
9836 if (VT == MVT::i32 || !Subtarget->is64Bit())
9837 return std::make_pair(0U, X86::GR32RegisterClass);
9838 return std::make_pair(0U, X86::GR64RegisterClass);
9839 case 'R': // LEGACY_REGS
9841 return std::make_pair(0U, X86::GR8_NOREXRegisterClass);
9843 return std::make_pair(0U, X86::GR16_NOREXRegisterClass);
9844 if (VT == MVT::i32 || !Subtarget->is64Bit())
9845 return std::make_pair(0U, X86::GR32_NOREXRegisterClass);
9846 return std::make_pair(0U, X86::GR64_NOREXRegisterClass);
9847 case 'f': // FP Stack registers.
9848 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
9849 // value to the correct fpstack register class.
9850 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
9851 return std::make_pair(0U, X86::RFP32RegisterClass);
9852 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
9853 return std::make_pair(0U, X86::RFP64RegisterClass);
9854 return std::make_pair(0U, X86::RFP80RegisterClass);
9855 case 'y': // MMX_REGS if MMX allowed.
9856 if (!Subtarget->hasMMX()) break;
9857 return std::make_pair(0U, X86::VR64RegisterClass);
9858 case 'Y': // SSE_REGS if SSE2 allowed
9859 if (!Subtarget->hasSSE2()) break;
9861 case 'x': // SSE_REGS if SSE1 allowed
9862 if (!Subtarget->hasSSE1()) break;
9864 switch (VT.getSimpleVT().SimpleTy) {
9866 // Scalar SSE types.
9869 return std::make_pair(0U, X86::FR32RegisterClass);
9872 return std::make_pair(0U, X86::FR64RegisterClass);
9880 return std::make_pair(0U, X86::VR128RegisterClass);
9886 // Use the default implementation in TargetLowering to convert the register
9887 // constraint into a member of a register class.
9888 std::pair<unsigned, const TargetRegisterClass*> Res;
9889 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
9891 // Not found as a standard register?
9892 if (Res.second == 0) {
9893 // Map st(0) -> st(7) -> ST0
9894 if (Constraint.size() == 7 && Constraint[0] == '{' &&
9895 tolower(Constraint[1]) == 's' &&
9896 tolower(Constraint[2]) == 't' &&
9897 Constraint[3] == '(' &&
9898 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
9899 Constraint[5] == ')' &&
9900 Constraint[6] == '}') {
9902 Res.first = X86::ST0+Constraint[4]-'0';
9903 Res.second = X86::RFP80RegisterClass;
9907 // GCC allows "st(0)" to be called just plain "st".
9908 if (StringRef("{st}").equals_lower(Constraint)) {
9909 Res.first = X86::ST0;
9910 Res.second = X86::RFP80RegisterClass;
9915 if (StringRef("{flags}").equals_lower(Constraint)) {
9916 Res.first = X86::EFLAGS;
9917 Res.second = X86::CCRRegisterClass;
9921 // 'A' means EAX + EDX.
9922 if (Constraint == "A") {
9923 Res.first = X86::EAX;
9924 Res.second = X86::GR32_ADRegisterClass;
9930 // Otherwise, check to see if this is a register class of the wrong value
9931 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
9932 // turn into {ax},{dx}.
9933 if (Res.second->hasType(VT))
9934 return Res; // Correct type already, nothing to do.
9936 // All of the single-register GCC register classes map their values onto
9937 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
9938 // really want an 8-bit or 32-bit register, map to the appropriate register
9939 // class and return the appropriate register.
9940 if (Res.second == X86::GR16RegisterClass) {
9941 if (VT == MVT::i8) {
9942 unsigned DestReg = 0;
9943 switch (Res.first) {
9945 case X86::AX: DestReg = X86::AL; break;
9946 case X86::DX: DestReg = X86::DL; break;
9947 case X86::CX: DestReg = X86::CL; break;
9948 case X86::BX: DestReg = X86::BL; break;
9951 Res.first = DestReg;
9952 Res.second = X86::GR8RegisterClass;
9954 } else if (VT == MVT::i32) {
9955 unsigned DestReg = 0;
9956 switch (Res.first) {
9958 case X86::AX: DestReg = X86::EAX; break;
9959 case X86::DX: DestReg = X86::EDX; break;
9960 case X86::CX: DestReg = X86::ECX; break;
9961 case X86::BX: DestReg = X86::EBX; break;
9962 case X86::SI: DestReg = X86::ESI; break;
9963 case X86::DI: DestReg = X86::EDI; break;
9964 case X86::BP: DestReg = X86::EBP; break;
9965 case X86::SP: DestReg = X86::ESP; break;
9968 Res.first = DestReg;
9969 Res.second = X86::GR32RegisterClass;
9971 } else if (VT == MVT::i64) {
9972 unsigned DestReg = 0;
9973 switch (Res.first) {
9975 case X86::AX: DestReg = X86::RAX; break;
9976 case X86::DX: DestReg = X86::RDX; break;
9977 case X86::CX: DestReg = X86::RCX; break;
9978 case X86::BX: DestReg = X86::RBX; break;
9979 case X86::SI: DestReg = X86::RSI; break;
9980 case X86::DI: DestReg = X86::RDI; break;
9981 case X86::BP: DestReg = X86::RBP; break;
9982 case X86::SP: DestReg = X86::RSP; break;
9985 Res.first = DestReg;
9986 Res.second = X86::GR64RegisterClass;
9989 } else if (Res.second == X86::FR32RegisterClass ||
9990 Res.second == X86::FR64RegisterClass ||
9991 Res.second == X86::VR128RegisterClass) {
9992 // Handle references to XMM physical registers that got mapped into the
9993 // wrong class. This can happen with constraints like {xmm0} where the
9994 // target independent register mapper will just pick the first match it can
9995 // find, ignoring the required type.
9997 Res.second = X86::FR32RegisterClass;
9998 else if (VT == MVT::f64)
9999 Res.second = X86::FR64RegisterClass;
10000 else if (X86::VR128RegisterClass->hasType(VT))
10001 Res.second = X86::VR128RegisterClass;
10007 //===----------------------------------------------------------------------===//
10008 // X86 Widen vector type
10009 //===----------------------------------------------------------------------===//
10011 /// getWidenVectorType: given a vector type, returns the type to widen
10012 /// to (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself.
10013 /// If there is no vector type that we want to widen to, returns MVT::Other
10014 /// When and where to widen is target dependent based on the cost of
10015 /// scalarizing vs using the wider vector type.
10017 EVT X86TargetLowering::getWidenVectorType(EVT VT) const {
10018 assert(VT.isVector());
10019 if (isTypeLegal(VT))
10022 // TODO: In computeRegisterProperty, we can compute the list of legal vector
10023 // type based on element type. This would speed up our search (though
10024 // it may not be worth it since the size of the list is relatively
10026 EVT EltVT = VT.getVectorElementType();
10027 unsigned NElts = VT.getVectorNumElements();
10029 // On X86, it make sense to widen any vector wider than 1
10033 for (unsigned nVT = MVT::FIRST_VECTOR_VALUETYPE;
10034 nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
10035 EVT SVT = (MVT::SimpleValueType)nVT;
10037 if (isTypeLegal(SVT) &&
10038 SVT.getVectorElementType() == EltVT &&
10039 SVT.getVectorNumElements() > NElts)