1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
16 #include "X86ISelLowering.h"
17 #include "Utils/X86ShuffleDecode.h"
19 #include "X86InstrBuilder.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/ADT/SmallSet.h"
23 #include "llvm/ADT/Statistic.h"
24 #include "llvm/ADT/StringExtras.h"
25 #include "llvm/ADT/VariadicFunction.h"
26 #include "llvm/CodeGen/IntrinsicLowering.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineJumpTableInfo.h"
31 #include "llvm/CodeGen/MachineModuleInfo.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/IR/CallingConv.h"
34 #include "llvm/IR/Constants.h"
35 #include "llvm/IR/DerivedTypes.h"
36 #include "llvm/IR/Function.h"
37 #include "llvm/IR/GlobalAlias.h"
38 #include "llvm/IR/GlobalVariable.h"
39 #include "llvm/IR/Instructions.h"
40 #include "llvm/IR/Intrinsics.h"
41 #include "llvm/IR/LLVMContext.h"
42 #include "llvm/MC/MCAsmInfo.h"
43 #include "llvm/MC/MCContext.h"
44 #include "llvm/MC/MCExpr.h"
45 #include "llvm/MC/MCSymbol.h"
46 #include "llvm/Support/CallSite.h"
47 #include "llvm/Support/Debug.h"
48 #include "llvm/Support/ErrorHandling.h"
49 #include "llvm/Support/MathExtras.h"
50 #include "llvm/Target/TargetOptions.h"
55 STATISTIC(NumTailCalls, "Number of tail calls");
57 // Forward declarations.
58 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
61 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
62 /// sets things up to match to an AVX VEXTRACTF128 instruction or a
63 /// simple subregister reference. Idx is an index in the 128 bits we
64 /// want. It need not be aligned to a 128-bit bounday. That makes
65 /// lowering EXTRACT_VECTOR_ELT operations easier.
66 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
67 SelectionDAG &DAG, DebugLoc dl) {
68 EVT VT = Vec.getValueType();
69 assert(VT.is256BitVector() && "Unexpected vector size!");
70 EVT ElVT = VT.getVectorElementType();
71 unsigned Factor = VT.getSizeInBits()/128;
72 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
73 VT.getVectorNumElements()/Factor);
75 // Extract from UNDEF is UNDEF.
76 if (Vec.getOpcode() == ISD::UNDEF)
77 return DAG.getUNDEF(ResultVT);
79 // Extract the relevant 128 bits. Generate an EXTRACT_SUBVECTOR
80 // we can match to VEXTRACTF128.
81 unsigned ElemsPerChunk = 128 / ElVT.getSizeInBits();
83 // This is the index of the first element of the 128-bit chunk
85 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / 128)
88 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
89 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
95 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
96 /// sets things up to match to an AVX VINSERTF128 instruction or a
97 /// simple superregister reference. Idx is an index in the 128 bits
98 /// we want. It need not be aligned to a 128-bit bounday. That makes
99 /// lowering INSERT_VECTOR_ELT operations easier.
100 static SDValue Insert128BitVector(SDValue Result, SDValue Vec,
101 unsigned IdxVal, SelectionDAG &DAG,
103 // Inserting UNDEF is Result
104 if (Vec.getOpcode() == ISD::UNDEF)
107 EVT VT = Vec.getValueType();
108 assert(VT.is128BitVector() && "Unexpected vector size!");
110 EVT ElVT = VT.getVectorElementType();
111 EVT ResultVT = Result.getValueType();
113 // Insert the relevant 128 bits.
114 unsigned ElemsPerChunk = 128/ElVT.getSizeInBits();
116 // This is the index of the first element of the 128-bit chunk
118 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/128)
121 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
122 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
126 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
127 /// instructions. This is used because creating CONCAT_VECTOR nodes of
128 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
129 /// large BUILD_VECTORS.
130 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
131 unsigned NumElems, SelectionDAG &DAG,
133 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
134 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
137 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
138 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
139 bool is64Bit = Subtarget->is64Bit();
141 if (Subtarget->isTargetEnvMacho()) {
143 return new X86_64MachoTargetObjectFile();
144 return new TargetLoweringObjectFileMachO();
147 if (Subtarget->isTargetLinux())
148 return new X86LinuxTargetObjectFile();
149 if (Subtarget->isTargetELF())
150 return new TargetLoweringObjectFileELF();
151 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
152 return new TargetLoweringObjectFileCOFF();
153 llvm_unreachable("unknown subtarget type");
156 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
157 : TargetLowering(TM, createTLOF(TM)) {
158 Subtarget = &TM.getSubtarget<X86Subtarget>();
159 X86ScalarSSEf64 = Subtarget->hasSSE2();
160 X86ScalarSSEf32 = Subtarget->hasSSE1();
162 RegInfo = TM.getRegisterInfo();
163 TD = getDataLayout();
165 // Set up the TargetLowering object.
166 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
168 // X86 is weird, it always uses i8 for shift amounts and setcc results.
169 setBooleanContents(ZeroOrOneBooleanContent);
170 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
171 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
173 // For 64-bit since we have so many registers use the ILP scheduler, for
174 // 32-bit code use the register pressure specific scheduling.
175 // For Atom, always use ILP scheduling.
176 if (Subtarget->isAtom())
177 setSchedulingPreference(Sched::ILP);
178 else if (Subtarget->is64Bit())
179 setSchedulingPreference(Sched::ILP);
181 setSchedulingPreference(Sched::RegPressure);
182 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
184 // Bypass i32 with i8 on Atom when compiling with O2
185 if (Subtarget->hasSlowDivide() && TM.getOptLevel() >= CodeGenOpt::Default)
186 addBypassSlowDiv(32, 8);
188 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) {
189 // Setup Windows compiler runtime calls.
190 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
191 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
192 setLibcallName(RTLIB::SREM_I64, "_allrem");
193 setLibcallName(RTLIB::UREM_I64, "_aullrem");
194 setLibcallName(RTLIB::MUL_I64, "_allmul");
195 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
196 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
197 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
198 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
199 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
201 // The _ftol2 runtime function has an unusual calling conv, which
202 // is modeled by a special pseudo-instruction.
203 setLibcallName(RTLIB::FPTOUINT_F64_I64, 0);
204 setLibcallName(RTLIB::FPTOUINT_F32_I64, 0);
205 setLibcallName(RTLIB::FPTOUINT_F64_I32, 0);
206 setLibcallName(RTLIB::FPTOUINT_F32_I32, 0);
209 if (Subtarget->isTargetDarwin()) {
210 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
211 setUseUnderscoreSetJmp(false);
212 setUseUnderscoreLongJmp(false);
213 } else if (Subtarget->isTargetMingw()) {
214 // MS runtime is weird: it exports _setjmp, but longjmp!
215 setUseUnderscoreSetJmp(true);
216 setUseUnderscoreLongJmp(false);
218 setUseUnderscoreSetJmp(true);
219 setUseUnderscoreLongJmp(true);
222 // Set up the register classes.
223 addRegisterClass(MVT::i8, &X86::GR8RegClass);
224 addRegisterClass(MVT::i16, &X86::GR16RegClass);
225 addRegisterClass(MVT::i32, &X86::GR32RegClass);
226 if (Subtarget->is64Bit())
227 addRegisterClass(MVT::i64, &X86::GR64RegClass);
229 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
231 // We don't accept any truncstore of integer registers.
232 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
233 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
234 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
235 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
236 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
237 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
239 // SETOEQ and SETUNE require checking two conditions.
240 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
241 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
242 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
243 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
244 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
245 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
247 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
249 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
250 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
251 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
253 if (Subtarget->is64Bit()) {
254 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
255 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
256 } else if (!TM.Options.UseSoftFloat) {
257 // We have an algorithm for SSE2->double, and we turn this into a
258 // 64-bit FILD followed by conditional FADD for other targets.
259 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
260 // We have an algorithm for SSE2, and we turn this into a 64-bit
261 // FILD for other targets.
262 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
265 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
267 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
268 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
270 if (!TM.Options.UseSoftFloat) {
271 // SSE has no i16 to fp conversion, only i32
272 if (X86ScalarSSEf32) {
273 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
274 // f32 and f64 cases are Legal, f80 case is not
275 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
277 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
278 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
281 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
282 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
285 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
286 // are Legal, f80 is custom lowered.
287 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
288 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
290 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
292 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
293 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
295 if (X86ScalarSSEf32) {
296 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
297 // f32 and f64 cases are Legal, f80 case is not
298 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
300 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
301 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
304 // Handle FP_TO_UINT by promoting the destination to a larger signed
306 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
307 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
308 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
310 if (Subtarget->is64Bit()) {
311 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
312 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
313 } else if (!TM.Options.UseSoftFloat) {
314 // Since AVX is a superset of SSE3, only check for SSE here.
315 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
316 // Expand FP_TO_UINT into a select.
317 // FIXME: We would like to use a Custom expander here eventually to do
318 // the optimal thing for SSE vs. the default expansion in the legalizer.
319 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
321 // With SSE3 we can use fisttpll to convert to a signed i64; without
322 // SSE, we're stuck with a fistpll.
323 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
326 if (isTargetFTOL()) {
327 // Use the _ftol2 runtime function, which has a pseudo-instruction
328 // to handle its weird calling convention.
329 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
332 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
333 if (!X86ScalarSSEf64) {
334 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
335 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
336 if (Subtarget->is64Bit()) {
337 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
338 // Without SSE, i64->f64 goes through memory.
339 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
343 // Scalar integer divide and remainder are lowered to use operations that
344 // produce two results, to match the available instructions. This exposes
345 // the two-result form to trivial CSE, which is able to combine x/y and x%y
346 // into a single instruction.
348 // Scalar integer multiply-high is also lowered to use two-result
349 // operations, to match the available instructions. However, plain multiply
350 // (low) operations are left as Legal, as there are single-result
351 // instructions for this in x86. Using the two-result multiply instructions
352 // when both high and low results are needed must be arranged by dagcombine.
353 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
355 setOperationAction(ISD::MULHS, VT, Expand);
356 setOperationAction(ISD::MULHU, VT, Expand);
357 setOperationAction(ISD::SDIV, VT, Expand);
358 setOperationAction(ISD::UDIV, VT, Expand);
359 setOperationAction(ISD::SREM, VT, Expand);
360 setOperationAction(ISD::UREM, VT, Expand);
362 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
363 setOperationAction(ISD::ADDC, VT, Custom);
364 setOperationAction(ISD::ADDE, VT, Custom);
365 setOperationAction(ISD::SUBC, VT, Custom);
366 setOperationAction(ISD::SUBE, VT, Custom);
369 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
370 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
371 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
372 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
373 if (Subtarget->is64Bit())
374 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
375 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
376 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
377 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
378 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
379 setOperationAction(ISD::FREM , MVT::f32 , Expand);
380 setOperationAction(ISD::FREM , MVT::f64 , Expand);
381 setOperationAction(ISD::FREM , MVT::f80 , Expand);
382 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
384 // Promote the i8 variants and force them on up to i32 which has a shorter
386 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
387 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
388 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
389 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
390 if (Subtarget->hasBMI()) {
391 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
392 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
393 if (Subtarget->is64Bit())
394 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
396 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
397 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
398 if (Subtarget->is64Bit())
399 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
402 if (Subtarget->hasLZCNT()) {
403 // When promoting the i8 variants, force them to i32 for a shorter
405 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
406 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
407 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
408 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
409 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
410 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
411 if (Subtarget->is64Bit())
412 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
414 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
415 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
416 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
417 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
418 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
419 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
420 if (Subtarget->is64Bit()) {
421 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
422 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
426 if (Subtarget->hasPOPCNT()) {
427 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
429 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
430 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
431 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
432 if (Subtarget->is64Bit())
433 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
436 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
437 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
439 // These should be promoted to a larger select which is supported.
440 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
441 // X86 wants to expand cmov itself.
442 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
443 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
444 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
445 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
446 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
447 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
448 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
449 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
450 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
451 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
452 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
453 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
454 if (Subtarget->is64Bit()) {
455 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
456 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
458 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
459 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intened to support
460 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
461 // support continuation, user-level threading, and etc.. As a result, no
462 // other SjLj exception interfaces are implemented and please don't build
463 // your own exception handling based on them.
464 // LLVM/Clang supports zero-cost DWARF exception handling.
465 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
466 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
469 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
470 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
471 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
472 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
473 if (Subtarget->is64Bit())
474 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
475 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
476 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
477 if (Subtarget->is64Bit()) {
478 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
479 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
480 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
481 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
482 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
484 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
485 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
486 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
487 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
488 if (Subtarget->is64Bit()) {
489 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
490 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
491 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
494 if (Subtarget->hasSSE1())
495 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
497 setOperationAction(ISD::MEMBARRIER , MVT::Other, Custom);
498 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
500 // On X86 and X86-64, atomic operations are lowered to locked instructions.
501 // Locked instructions, in turn, have implicit fence semantics (all memory
502 // operations are flushed before issuing the locked instruction, and they
503 // are not buffered), so we can fold away the common pattern of
504 // fence-atomic-fence.
505 setShouldFoldAtomicFences(true);
507 // Expand certain atomics
508 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
510 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom);
511 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
512 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
515 if (!Subtarget->is64Bit()) {
516 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
517 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
518 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
519 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
520 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
521 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
522 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
523 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
524 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i64, Custom);
525 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i64, Custom);
526 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i64, Custom);
527 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i64, Custom);
530 if (Subtarget->hasCmpxchg16b()) {
531 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom);
534 // FIXME - use subtarget debug flags
535 if (!Subtarget->isTargetDarwin() &&
536 !Subtarget->isTargetELF() &&
537 !Subtarget->isTargetCygMing()) {
538 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
541 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
542 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
543 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
544 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
545 if (Subtarget->is64Bit()) {
546 setExceptionPointerRegister(X86::RAX);
547 setExceptionSelectorRegister(X86::RDX);
549 setExceptionPointerRegister(X86::EAX);
550 setExceptionSelectorRegister(X86::EDX);
552 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
553 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
555 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
556 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
558 setOperationAction(ISD::TRAP, MVT::Other, Legal);
559 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
561 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
562 setOperationAction(ISD::VASTART , MVT::Other, Custom);
563 setOperationAction(ISD::VAEND , MVT::Other, Expand);
564 if (Subtarget->is64Bit()) {
565 setOperationAction(ISD::VAARG , MVT::Other, Custom);
566 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
568 setOperationAction(ISD::VAARG , MVT::Other, Expand);
569 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
572 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
573 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
575 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
576 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
577 MVT::i64 : MVT::i32, Custom);
578 else if (TM.Options.EnableSegmentedStacks)
579 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
580 MVT::i64 : MVT::i32, Custom);
582 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
583 MVT::i64 : MVT::i32, Expand);
585 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
586 // f32 and f64 use SSE.
587 // Set up the FP register classes.
588 addRegisterClass(MVT::f32, &X86::FR32RegClass);
589 addRegisterClass(MVT::f64, &X86::FR64RegClass);
591 // Use ANDPD to simulate FABS.
592 setOperationAction(ISD::FABS , MVT::f64, Custom);
593 setOperationAction(ISD::FABS , MVT::f32, Custom);
595 // Use XORP to simulate FNEG.
596 setOperationAction(ISD::FNEG , MVT::f64, Custom);
597 setOperationAction(ISD::FNEG , MVT::f32, Custom);
599 // Use ANDPD and ORPD to simulate FCOPYSIGN.
600 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
601 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
603 // Lower this to FGETSIGNx86 plus an AND.
604 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
605 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
607 // We don't support sin/cos/fmod
608 setOperationAction(ISD::FSIN , MVT::f64, Expand);
609 setOperationAction(ISD::FCOS , MVT::f64, Expand);
610 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
611 setOperationAction(ISD::FSIN , MVT::f32, Expand);
612 setOperationAction(ISD::FCOS , MVT::f32, Expand);
613 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
615 // Expand FP immediates into loads from the stack, except for the special
617 addLegalFPImmediate(APFloat(+0.0)); // xorpd
618 addLegalFPImmediate(APFloat(+0.0f)); // xorps
619 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
620 // Use SSE for f32, x87 for f64.
621 // Set up the FP register classes.
622 addRegisterClass(MVT::f32, &X86::FR32RegClass);
623 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
625 // Use ANDPS to simulate FABS.
626 setOperationAction(ISD::FABS , MVT::f32, Custom);
628 // Use XORP to simulate FNEG.
629 setOperationAction(ISD::FNEG , MVT::f32, Custom);
631 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
633 // Use ANDPS and ORPS to simulate FCOPYSIGN.
634 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
635 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
637 // We don't support sin/cos/fmod
638 setOperationAction(ISD::FSIN , MVT::f32, Expand);
639 setOperationAction(ISD::FCOS , MVT::f32, Expand);
640 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
642 // Special cases we handle for FP constants.
643 addLegalFPImmediate(APFloat(+0.0f)); // xorps
644 addLegalFPImmediate(APFloat(+0.0)); // FLD0
645 addLegalFPImmediate(APFloat(+1.0)); // FLD1
646 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
647 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
649 if (!TM.Options.UnsafeFPMath) {
650 setOperationAction(ISD::FSIN , MVT::f64, Expand);
651 setOperationAction(ISD::FCOS , MVT::f64, Expand);
652 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
654 } else if (!TM.Options.UseSoftFloat) {
655 // f32 and f64 in x87.
656 // Set up the FP register classes.
657 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
658 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
660 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
661 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
662 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
663 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
665 if (!TM.Options.UnsafeFPMath) {
666 setOperationAction(ISD::FSIN , MVT::f64, Expand);
667 setOperationAction(ISD::FSIN , MVT::f32, Expand);
668 setOperationAction(ISD::FCOS , MVT::f64, Expand);
669 setOperationAction(ISD::FCOS , MVT::f32, Expand);
670 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
671 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
673 addLegalFPImmediate(APFloat(+0.0)); // FLD0
674 addLegalFPImmediate(APFloat(+1.0)); // FLD1
675 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
676 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
677 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
678 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
679 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
680 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
683 // We don't support FMA.
684 setOperationAction(ISD::FMA, MVT::f64, Expand);
685 setOperationAction(ISD::FMA, MVT::f32, Expand);
687 // Long double always uses X87.
688 if (!TM.Options.UseSoftFloat) {
689 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
690 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
691 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
693 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
694 addLegalFPImmediate(TmpFlt); // FLD0
696 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
699 APFloat TmpFlt2(+1.0);
700 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
702 addLegalFPImmediate(TmpFlt2); // FLD1
703 TmpFlt2.changeSign();
704 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
707 if (!TM.Options.UnsafeFPMath) {
708 setOperationAction(ISD::FSIN , MVT::f80, Expand);
709 setOperationAction(ISD::FCOS , MVT::f80, Expand);
710 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
713 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
714 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
715 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
716 setOperationAction(ISD::FRINT, MVT::f80, Expand);
717 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
718 setOperationAction(ISD::FMA, MVT::f80, Expand);
721 // Always use a library call for pow.
722 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
723 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
724 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
726 setOperationAction(ISD::FLOG, MVT::f80, Expand);
727 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
728 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
729 setOperationAction(ISD::FEXP, MVT::f80, Expand);
730 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
732 // First set operation action for all vector types to either promote
733 // (for widening) or expand (for scalarization). Then we will selectively
734 // turn on ones that can be effectively codegen'd.
735 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
736 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
737 MVT VT = (MVT::SimpleValueType)i;
738 setOperationAction(ISD::ADD , VT, Expand);
739 setOperationAction(ISD::SUB , VT, Expand);
740 setOperationAction(ISD::FADD, VT, Expand);
741 setOperationAction(ISD::FNEG, VT, Expand);
742 setOperationAction(ISD::FSUB, VT, Expand);
743 setOperationAction(ISD::MUL , VT, Expand);
744 setOperationAction(ISD::FMUL, VT, Expand);
745 setOperationAction(ISD::SDIV, VT, Expand);
746 setOperationAction(ISD::UDIV, VT, Expand);
747 setOperationAction(ISD::FDIV, VT, Expand);
748 setOperationAction(ISD::SREM, VT, Expand);
749 setOperationAction(ISD::UREM, VT, Expand);
750 setOperationAction(ISD::LOAD, VT, Expand);
751 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
752 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
753 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
754 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
755 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
756 setOperationAction(ISD::FABS, VT, Expand);
757 setOperationAction(ISD::FSIN, VT, Expand);
758 setOperationAction(ISD::FSINCOS, VT, Expand);
759 setOperationAction(ISD::FCOS, VT, Expand);
760 setOperationAction(ISD::FSINCOS, VT, Expand);
761 setOperationAction(ISD::FREM, VT, Expand);
762 setOperationAction(ISD::FMA, VT, Expand);
763 setOperationAction(ISD::FPOWI, VT, Expand);
764 setOperationAction(ISD::FSQRT, VT, Expand);
765 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
766 setOperationAction(ISD::FFLOOR, VT, Expand);
767 setOperationAction(ISD::FCEIL, VT, Expand);
768 setOperationAction(ISD::FTRUNC, VT, Expand);
769 setOperationAction(ISD::FRINT, VT, Expand);
770 setOperationAction(ISD::FNEARBYINT, VT, Expand);
771 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
772 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
773 setOperationAction(ISD::SDIVREM, VT, Expand);
774 setOperationAction(ISD::UDIVREM, VT, Expand);
775 setOperationAction(ISD::FPOW, VT, Expand);
776 setOperationAction(ISD::CTPOP, VT, Expand);
777 setOperationAction(ISD::CTTZ, VT, Expand);
778 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
779 setOperationAction(ISD::CTLZ, VT, Expand);
780 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
781 setOperationAction(ISD::SHL, VT, Expand);
782 setOperationAction(ISD::SRA, VT, Expand);
783 setOperationAction(ISD::SRL, VT, Expand);
784 setOperationAction(ISD::ROTL, VT, Expand);
785 setOperationAction(ISD::ROTR, VT, Expand);
786 setOperationAction(ISD::BSWAP, VT, Expand);
787 setOperationAction(ISD::SETCC, VT, Expand);
788 setOperationAction(ISD::FLOG, VT, Expand);
789 setOperationAction(ISD::FLOG2, VT, Expand);
790 setOperationAction(ISD::FLOG10, VT, Expand);
791 setOperationAction(ISD::FEXP, VT, Expand);
792 setOperationAction(ISD::FEXP2, VT, Expand);
793 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
794 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
795 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
796 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
797 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
798 setOperationAction(ISD::TRUNCATE, VT, Expand);
799 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
800 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
801 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
802 setOperationAction(ISD::VSELECT, VT, Expand);
803 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
804 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
805 setTruncStoreAction(VT,
806 (MVT::SimpleValueType)InnerVT, Expand);
807 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
808 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
809 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
812 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
813 // with -msoft-float, disable use of MMX as well.
814 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
815 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
816 // No operations on x86mmx supported, everything uses intrinsics.
819 // MMX-sized vectors (other than x86mmx) are expected to be expanded
820 // into smaller operations.
821 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
822 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
823 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
824 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
825 setOperationAction(ISD::AND, MVT::v8i8, Expand);
826 setOperationAction(ISD::AND, MVT::v4i16, Expand);
827 setOperationAction(ISD::AND, MVT::v2i32, Expand);
828 setOperationAction(ISD::AND, MVT::v1i64, Expand);
829 setOperationAction(ISD::OR, MVT::v8i8, Expand);
830 setOperationAction(ISD::OR, MVT::v4i16, Expand);
831 setOperationAction(ISD::OR, MVT::v2i32, Expand);
832 setOperationAction(ISD::OR, MVT::v1i64, Expand);
833 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
834 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
835 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
836 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
837 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
838 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
839 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
840 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
841 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
842 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
843 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
844 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
845 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
846 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
847 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
848 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
849 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
851 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
852 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
854 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
855 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
856 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
857 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
858 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
859 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
860 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
861 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
862 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
863 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
864 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
865 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
868 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
869 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
871 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
872 // registers cannot be used even for integer operations.
873 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
874 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
875 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
876 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
878 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
879 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
880 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
881 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
882 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
883 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
884 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
885 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
886 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
887 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
888 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
889 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
890 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
891 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
892 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
893 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
894 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
895 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
897 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
898 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
899 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
900 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
902 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
903 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
904 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
905 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
906 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
908 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
909 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
910 MVT VT = (MVT::SimpleValueType)i;
911 // Do not attempt to custom lower non-power-of-2 vectors
912 if (!isPowerOf2_32(VT.getVectorNumElements()))
914 // Do not attempt to custom lower non-128-bit vectors
915 if (!VT.is128BitVector())
917 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
918 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
919 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
922 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
923 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
924 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
925 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
926 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
927 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
929 if (Subtarget->is64Bit()) {
930 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
931 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
934 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
935 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
936 MVT VT = (MVT::SimpleValueType)i;
938 // Do not attempt to promote non-128-bit vectors
939 if (!VT.is128BitVector())
942 setOperationAction(ISD::AND, VT, Promote);
943 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
944 setOperationAction(ISD::OR, VT, Promote);
945 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
946 setOperationAction(ISD::XOR, VT, Promote);
947 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
948 setOperationAction(ISD::LOAD, VT, Promote);
949 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
950 setOperationAction(ISD::SELECT, VT, Promote);
951 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
954 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
956 // Custom lower v2i64 and v2f64 selects.
957 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
958 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
959 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
960 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
962 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
963 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
965 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
966 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
967 // As there is no 64-bit GPR available, we need build a special custom
968 // sequence to convert from v2i32 to v2f32.
969 if (!Subtarget->is64Bit())
970 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
972 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
973 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
975 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal);
978 if (Subtarget->hasSSE41()) {
979 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
980 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
981 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
982 setOperationAction(ISD::FRINT, MVT::f32, Legal);
983 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
984 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
985 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
986 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
987 setOperationAction(ISD::FRINT, MVT::f64, Legal);
988 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
990 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
991 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
992 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
993 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
994 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
995 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
996 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
997 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
998 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
999 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1001 // FIXME: Do we need to handle scalar-to-vector here?
1002 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1004 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
1005 setOperationAction(ISD::VSELECT, MVT::v2i64, Legal);
1006 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1007 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
1008 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
1010 // i8 and i16 vectors are custom , because the source register and source
1011 // source memory operand types are not the same width. f32 vectors are
1012 // custom since the immediate controlling the insert encodes additional
1014 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1015 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1016 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1017 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1019 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1020 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1021 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1022 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1024 // FIXME: these should be Legal but thats only for the case where
1025 // the index is constant. For now custom expand to deal with that.
1026 if (Subtarget->is64Bit()) {
1027 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1028 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1032 if (Subtarget->hasSSE2()) {
1033 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1034 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1036 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1037 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1039 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1040 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1042 if (Subtarget->hasInt256()) {
1043 setOperationAction(ISD::SRL, MVT::v2i64, Legal);
1044 setOperationAction(ISD::SRL, MVT::v4i32, Legal);
1046 setOperationAction(ISD::SHL, MVT::v2i64, Legal);
1047 setOperationAction(ISD::SHL, MVT::v4i32, Legal);
1049 setOperationAction(ISD::SRA, MVT::v4i32, Legal);
1051 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1052 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1054 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1055 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1057 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1059 setOperationAction(ISD::SDIV, MVT::v8i16, Custom);
1060 setOperationAction(ISD::SDIV, MVT::v4i32, Custom);
1063 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1064 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1065 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1066 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1067 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1068 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1069 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1071 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1072 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1073 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1075 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1076 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1077 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1078 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1079 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1080 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1081 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1082 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1083 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1084 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1085 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1086 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1088 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1089 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1090 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1091 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1092 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1093 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1094 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1095 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1096 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1097 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1098 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1099 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1101 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1102 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1104 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Custom);
1106 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1107 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1108 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1110 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1111 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1112 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1114 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal);
1116 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1117 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1119 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1120 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1122 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1123 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1125 setOperationAction(ISD::SDIV, MVT::v16i16, Custom);
1127 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1128 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1129 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1130 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1132 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1133 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1134 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1136 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal);
1137 setOperationAction(ISD::VSELECT, MVT::v4i64, Legal);
1138 setOperationAction(ISD::VSELECT, MVT::v8i32, Legal);
1139 setOperationAction(ISD::VSELECT, MVT::v8f32, Legal);
1141 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1142 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1143 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1144 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1145 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1146 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1148 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1149 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1150 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1151 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1152 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1153 setOperationAction(ISD::FMA, MVT::f32, Legal);
1154 setOperationAction(ISD::FMA, MVT::f64, Legal);
1157 if (Subtarget->hasInt256()) {
1158 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1159 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1160 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1161 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1163 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1164 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1165 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1166 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1168 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1169 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1170 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1171 // Don't lower v32i8 because there is no 128-bit byte mul
1173 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1175 setOperationAction(ISD::SRL, MVT::v4i64, Legal);
1176 setOperationAction(ISD::SRL, MVT::v8i32, Legal);
1178 setOperationAction(ISD::SHL, MVT::v4i64, Legal);
1179 setOperationAction(ISD::SHL, MVT::v8i32, Legal);
1181 setOperationAction(ISD::SRA, MVT::v8i32, Legal);
1183 setOperationAction(ISD::SDIV, MVT::v8i32, Custom);
1185 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1186 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1187 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1188 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1190 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1191 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1192 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1193 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1195 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1196 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1197 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1198 // Don't lower v32i8 because there is no 128-bit byte mul
1200 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1201 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1203 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1204 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1206 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1209 // Custom lower several nodes for 256-bit types.
1210 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1211 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1212 MVT VT = (MVT::SimpleValueType)i;
1214 // Extract subvector is special because the value type
1215 // (result) is 128-bit but the source is 256-bit wide.
1216 if (VT.is128BitVector())
1217 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1219 // Do not attempt to custom lower other non-256-bit vectors
1220 if (!VT.is256BitVector())
1223 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1224 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1225 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1226 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1227 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1228 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1229 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1232 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1233 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1234 MVT VT = (MVT::SimpleValueType)i;
1236 // Do not attempt to promote non-256-bit vectors
1237 if (!VT.is256BitVector())
1240 setOperationAction(ISD::AND, VT, Promote);
1241 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1242 setOperationAction(ISD::OR, VT, Promote);
1243 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1244 setOperationAction(ISD::XOR, VT, Promote);
1245 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1246 setOperationAction(ISD::LOAD, VT, Promote);
1247 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1248 setOperationAction(ISD::SELECT, VT, Promote);
1249 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1253 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1254 // of this type with custom code.
1255 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1256 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1257 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1261 // We want to custom lower some of our intrinsics.
1262 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1263 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1265 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1266 // handle type legalization for these operations here.
1268 // FIXME: We really should do custom legalization for addition and
1269 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1270 // than generic legalization for 64-bit multiplication-with-overflow, though.
1271 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1272 // Add/Sub/Mul with overflow operations are custom lowered.
1274 setOperationAction(ISD::SADDO, VT, Custom);
1275 setOperationAction(ISD::UADDO, VT, Custom);
1276 setOperationAction(ISD::SSUBO, VT, Custom);
1277 setOperationAction(ISD::USUBO, VT, Custom);
1278 setOperationAction(ISD::SMULO, VT, Custom);
1279 setOperationAction(ISD::UMULO, VT, Custom);
1282 // There are no 8-bit 3-address imul/mul instructions
1283 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1284 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1286 if (!Subtarget->is64Bit()) {
1287 // These libcalls are not available in 32-bit.
1288 setLibcallName(RTLIB::SHL_I128, 0);
1289 setLibcallName(RTLIB::SRL_I128, 0);
1290 setLibcallName(RTLIB::SRA_I128, 0);
1293 // Combine sin / cos into one node or libcall if possible.
1294 if (Subtarget->hasSinCos()) {
1295 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1296 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1297 if (Subtarget->isTargetDarwin()) {
1298 // For MacOSX, we don't want to the normal expansion of a libcall to
1299 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
1301 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1302 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1306 // We have target-specific dag combine patterns for the following nodes:
1307 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1308 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1309 setTargetDAGCombine(ISD::VSELECT);
1310 setTargetDAGCombine(ISD::SELECT);
1311 setTargetDAGCombine(ISD::SHL);
1312 setTargetDAGCombine(ISD::SRA);
1313 setTargetDAGCombine(ISD::SRL);
1314 setTargetDAGCombine(ISD::OR);
1315 setTargetDAGCombine(ISD::AND);
1316 setTargetDAGCombine(ISD::ADD);
1317 setTargetDAGCombine(ISD::FADD);
1318 setTargetDAGCombine(ISD::FSUB);
1319 setTargetDAGCombine(ISD::FMA);
1320 setTargetDAGCombine(ISD::SUB);
1321 setTargetDAGCombine(ISD::LOAD);
1322 setTargetDAGCombine(ISD::STORE);
1323 setTargetDAGCombine(ISD::ZERO_EXTEND);
1324 setTargetDAGCombine(ISD::ANY_EXTEND);
1325 setTargetDAGCombine(ISD::SIGN_EXTEND);
1326 setTargetDAGCombine(ISD::TRUNCATE);
1327 setTargetDAGCombine(ISD::SINT_TO_FP);
1328 setTargetDAGCombine(ISD::SETCC);
1329 if (Subtarget->is64Bit())
1330 setTargetDAGCombine(ISD::MUL);
1331 setTargetDAGCombine(ISD::XOR);
1333 computeRegisterProperties();
1335 // On Darwin, -Os means optimize for size without hurting performance,
1336 // do not reduce the limit.
1337 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1338 maxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1339 maxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1340 maxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1341 maxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1342 maxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1343 setPrefLoopAlignment(4); // 2^4 bytes.
1344 benefitFromCodePlacementOpt = true;
1346 // Predictable cmov don't hurt on atom because it's in-order.
1347 predictableSelectIsExpensive = !Subtarget->isAtom();
1349 setPrefFunctionAlignment(4); // 2^4 bytes.
1352 EVT X86TargetLowering::getSetCCResultType(EVT VT) const {
1353 if (!VT.isVector()) return MVT::i8;
1354 return VT.changeVectorElementTypeToInteger();
1357 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1358 /// the desired ByVal argument alignment.
1359 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1362 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1363 if (VTy->getBitWidth() == 128)
1365 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1366 unsigned EltAlign = 0;
1367 getMaxByValAlign(ATy->getElementType(), EltAlign);
1368 if (EltAlign > MaxAlign)
1369 MaxAlign = EltAlign;
1370 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1371 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1372 unsigned EltAlign = 0;
1373 getMaxByValAlign(STy->getElementType(i), EltAlign);
1374 if (EltAlign > MaxAlign)
1375 MaxAlign = EltAlign;
1382 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1383 /// function arguments in the caller parameter area. For X86, aggregates
1384 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1385 /// are at 4-byte boundaries.
1386 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1387 if (Subtarget->is64Bit()) {
1388 // Max of 8 and alignment of type.
1389 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1396 if (Subtarget->hasSSE1())
1397 getMaxByValAlign(Ty, Align);
1401 /// getOptimalMemOpType - Returns the target specific optimal type for load
1402 /// and store operations as a result of memset, memcpy, and memmove
1403 /// lowering. If DstAlign is zero that means it's safe to destination
1404 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1405 /// means there isn't a need to check it against alignment requirement,
1406 /// probably because the source does not need to be loaded. If 'IsMemset' is
1407 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1408 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1409 /// source is constant so it does not need to be loaded.
1410 /// It returns EVT::Other if the type should be determined using generic
1411 /// target-independent logic.
1413 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1414 unsigned DstAlign, unsigned SrcAlign,
1415 bool IsMemset, bool ZeroMemset,
1417 MachineFunction &MF) const {
1418 const Function *F = MF.getFunction();
1419 if ((!IsMemset || ZeroMemset) &&
1420 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1421 Attribute::NoImplicitFloat)) {
1423 (Subtarget->isUnalignedMemAccessFast() ||
1424 ((DstAlign == 0 || DstAlign >= 16) &&
1425 (SrcAlign == 0 || SrcAlign >= 16)))) {
1427 if (Subtarget->hasInt256())
1429 if (Subtarget->hasFp256())
1432 if (Subtarget->hasSSE2())
1434 if (Subtarget->hasSSE1())
1436 } else if (!MemcpyStrSrc && Size >= 8 &&
1437 !Subtarget->is64Bit() &&
1438 Subtarget->hasSSE2()) {
1439 // Do not use f64 to lower memcpy if source is string constant. It's
1440 // better to use i32 to avoid the loads.
1444 if (Subtarget->is64Bit() && Size >= 8)
1449 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1451 return X86ScalarSSEf32;
1452 else if (VT == MVT::f64)
1453 return X86ScalarSSEf64;
1458 X86TargetLowering::allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const {
1460 *Fast = Subtarget->isUnalignedMemAccessFast();
1464 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1465 /// current function. The returned value is a member of the
1466 /// MachineJumpTableInfo::JTEntryKind enum.
1467 unsigned X86TargetLowering::getJumpTableEncoding() const {
1468 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1470 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1471 Subtarget->isPICStyleGOT())
1472 return MachineJumpTableInfo::EK_Custom32;
1474 // Otherwise, use the normal jump table encoding heuristics.
1475 return TargetLowering::getJumpTableEncoding();
1479 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1480 const MachineBasicBlock *MBB,
1481 unsigned uid,MCContext &Ctx) const{
1482 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1483 Subtarget->isPICStyleGOT());
1484 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1486 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1487 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1490 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1492 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1493 SelectionDAG &DAG) const {
1494 if (!Subtarget->is64Bit())
1495 // This doesn't have DebugLoc associated with it, but is not really the
1496 // same as a Register.
1497 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy());
1501 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1502 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1504 const MCExpr *X86TargetLowering::
1505 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1506 MCContext &Ctx) const {
1507 // X86-64 uses RIP relative addressing based on the jump table label.
1508 if (Subtarget->isPICStyleRIPRel())
1509 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1511 // Otherwise, the reference is relative to the PIC base.
1512 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1515 // FIXME: Why this routine is here? Move to RegInfo!
1516 std::pair<const TargetRegisterClass*, uint8_t>
1517 X86TargetLowering::findRepresentativeClass(MVT VT) const{
1518 const TargetRegisterClass *RRC = 0;
1520 switch (VT.SimpleTy) {
1522 return TargetLowering::findRepresentativeClass(VT);
1523 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1524 RRC = Subtarget->is64Bit() ?
1525 (const TargetRegisterClass*)&X86::GR64RegClass :
1526 (const TargetRegisterClass*)&X86::GR32RegClass;
1529 RRC = &X86::VR64RegClass;
1531 case MVT::f32: case MVT::f64:
1532 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1533 case MVT::v4f32: case MVT::v2f64:
1534 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1536 RRC = &X86::VR128RegClass;
1539 return std::make_pair(RRC, Cost);
1542 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1543 unsigned &Offset) const {
1544 if (!Subtarget->isTargetLinux())
1547 if (Subtarget->is64Bit()) {
1548 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1550 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1562 //===----------------------------------------------------------------------===//
1563 // Return Value Calling Convention Implementation
1564 //===----------------------------------------------------------------------===//
1566 #include "X86GenCallingConv.inc"
1569 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1570 MachineFunction &MF, bool isVarArg,
1571 const SmallVectorImpl<ISD::OutputArg> &Outs,
1572 LLVMContext &Context) const {
1573 SmallVector<CCValAssign, 16> RVLocs;
1574 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1576 return CCInfo.CheckReturn(Outs, RetCC_X86);
1580 X86TargetLowering::LowerReturn(SDValue Chain,
1581 CallingConv::ID CallConv, bool isVarArg,
1582 const SmallVectorImpl<ISD::OutputArg> &Outs,
1583 const SmallVectorImpl<SDValue> &OutVals,
1584 DebugLoc dl, SelectionDAG &DAG) const {
1585 MachineFunction &MF = DAG.getMachineFunction();
1586 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1588 SmallVector<CCValAssign, 16> RVLocs;
1589 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1590 RVLocs, *DAG.getContext());
1591 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1594 SmallVector<SDValue, 6> RetOps;
1595 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1596 // Operand #1 = Bytes To Pop
1597 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1600 // Copy the result values into the output registers.
1601 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1602 CCValAssign &VA = RVLocs[i];
1603 assert(VA.isRegLoc() && "Can only return in registers!");
1604 SDValue ValToCopy = OutVals[i];
1605 EVT ValVT = ValToCopy.getValueType();
1607 // Promote values to the appropriate types
1608 if (VA.getLocInfo() == CCValAssign::SExt)
1609 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
1610 else if (VA.getLocInfo() == CCValAssign::ZExt)
1611 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
1612 else if (VA.getLocInfo() == CCValAssign::AExt)
1613 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
1614 else if (VA.getLocInfo() == CCValAssign::BCvt)
1615 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
1617 // If this is x86-64, and we disabled SSE, we can't return FP values,
1618 // or SSE or MMX vectors.
1619 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1620 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1621 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
1622 report_fatal_error("SSE register return with SSE disabled");
1624 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1625 // llvm-gcc has never done it right and no one has noticed, so this
1626 // should be OK for now.
1627 if (ValVT == MVT::f64 &&
1628 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
1629 report_fatal_error("SSE2 register return with SSE2 disabled");
1631 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1632 // the RET instruction and handled by the FP Stackifier.
1633 if (VA.getLocReg() == X86::ST0 ||
1634 VA.getLocReg() == X86::ST1) {
1635 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1636 // change the value to the FP stack register class.
1637 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1638 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1639 RetOps.push_back(ValToCopy);
1640 // Don't emit a copytoreg.
1644 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1645 // which is returned in RAX / RDX.
1646 if (Subtarget->is64Bit()) {
1647 if (ValVT == MVT::x86mmx) {
1648 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1649 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1650 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1652 // If we don't have SSE2 available, convert to v4f32 so the generated
1653 // register is legal.
1654 if (!Subtarget->hasSSE2())
1655 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1660 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1661 Flag = Chain.getValue(1);
1662 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
1665 // The x86-64 ABIs require that for returning structs by value we copy
1666 // the sret argument into %rax/%eax (depending on ABI) for the return.
1667 // We saved the argument into a virtual register in the entry block,
1668 // so now we copy the value out and into %rax/%eax.
1669 if (Subtarget->is64Bit() &&
1670 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1671 MachineFunction &MF = DAG.getMachineFunction();
1672 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1673 unsigned Reg = FuncInfo->getSRetReturnReg();
1675 "SRetReturnReg should have been set in LowerFormalArguments().");
1676 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1678 unsigned RetValReg = Subtarget->isTarget64BitILP32() ? X86::EAX : X86::RAX;
1679 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
1680 Flag = Chain.getValue(1);
1682 // RAX/EAX now acts like a return value.
1683 RetOps.push_back(DAG.getRegister(RetValReg, MVT::i64));
1686 RetOps[0] = Chain; // Update chain.
1688 // Add the flag if we have it.
1690 RetOps.push_back(Flag);
1692 return DAG.getNode(X86ISD::RET_FLAG, dl,
1693 MVT::Other, &RetOps[0], RetOps.size());
1696 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
1697 if (N->getNumValues() != 1)
1699 if (!N->hasNUsesOfValue(1, 0))
1702 SDValue TCChain = Chain;
1703 SDNode *Copy = *N->use_begin();
1704 if (Copy->getOpcode() == ISD::CopyToReg) {
1705 // If the copy has a glue operand, we conservatively assume it isn't safe to
1706 // perform a tail call.
1707 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
1709 TCChain = Copy->getOperand(0);
1710 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
1713 bool HasRet = false;
1714 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1716 if (UI->getOpcode() != X86ISD::RET_FLAG)
1729 X86TargetLowering::getTypeForExtArgOrReturn(MVT VT,
1730 ISD::NodeType ExtendKind) const {
1732 // TODO: Is this also valid on 32-bit?
1733 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
1734 ReturnMVT = MVT::i8;
1736 ReturnMVT = MVT::i32;
1738 MVT MinVT = getRegisterType(ReturnMVT);
1739 return VT.bitsLT(MinVT) ? MinVT : VT;
1742 /// LowerCallResult - Lower the result values of a call into the
1743 /// appropriate copies out of appropriate physical registers.
1746 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1747 CallingConv::ID CallConv, bool isVarArg,
1748 const SmallVectorImpl<ISD::InputArg> &Ins,
1749 DebugLoc dl, SelectionDAG &DAG,
1750 SmallVectorImpl<SDValue> &InVals) const {
1752 // Assign locations to each value returned by this call.
1753 SmallVector<CCValAssign, 16> RVLocs;
1754 bool Is64Bit = Subtarget->is64Bit();
1755 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1756 getTargetMachine(), RVLocs, *DAG.getContext());
1757 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1759 // Copy all of the result registers out of their specified physreg.
1760 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
1761 CCValAssign &VA = RVLocs[i];
1762 EVT CopyVT = VA.getValVT();
1764 // If this is x86-64, and we disabled SSE, we can't return FP values
1765 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1766 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
1767 report_fatal_error("SSE register return with SSE disabled");
1772 // If this is a call to a function that returns an fp value on the floating
1773 // point stack, we must guarantee the value is popped from the stack, so
1774 // a CopyFromReg is not good enough - the copy instruction may be eliminated
1775 // if the return value is not used. We use the FpPOP_RETVAL instruction
1777 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {
1778 // If we prefer to use the value in xmm registers, copy it out as f80 and
1779 // use a truncate to move it from fp stack reg to xmm reg.
1780 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
1781 SDValue Ops[] = { Chain, InFlag };
1782 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT,
1783 MVT::Other, MVT::Glue, Ops, 2), 1);
1784 Val = Chain.getValue(0);
1786 // Round the f80 to the right size, which also moves it to the appropriate
1788 if (CopyVT != VA.getValVT())
1789 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1790 // This truncation won't change the value.
1791 DAG.getIntPtrConstant(1));
1793 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1794 CopyVT, InFlag).getValue(1);
1795 Val = Chain.getValue(0);
1797 InFlag = Chain.getValue(2);
1798 InVals.push_back(Val);
1804 //===----------------------------------------------------------------------===//
1805 // C & StdCall & Fast Calling Convention implementation
1806 //===----------------------------------------------------------------------===//
1807 // StdCall calling convention seems to be standard for many Windows' API
1808 // routines and around. It differs from C calling convention just a little:
1809 // callee should clean up the stack, not caller. Symbols should be also
1810 // decorated in some fancy way :) It doesn't support any vector arguments.
1811 // For info on fast calling convention see Fast Calling Convention (tail call)
1812 // implementation LowerX86_32FastCCCallTo.
1814 /// CallIsStructReturn - Determines whether a call uses struct return
1816 enum StructReturnType {
1821 static StructReturnType
1822 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
1824 return NotStructReturn;
1826 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
1827 if (!Flags.isSRet())
1828 return NotStructReturn;
1829 if (Flags.isInReg())
1830 return RegStructReturn;
1831 return StackStructReturn;
1834 /// ArgsAreStructReturn - Determines whether a function uses struct
1835 /// return semantics.
1836 static StructReturnType
1837 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
1839 return NotStructReturn;
1841 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
1842 if (!Flags.isSRet())
1843 return NotStructReturn;
1844 if (Flags.isInReg())
1845 return RegStructReturn;
1846 return StackStructReturn;
1849 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1850 /// by "Src" to address "Dst" with size and alignment information specified by
1851 /// the specific parameter attribute. The copy will be passed as a byval
1852 /// function parameter.
1854 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1855 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1857 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1859 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1860 /*isVolatile*/false, /*AlwaysInline=*/true,
1861 MachinePointerInfo(), MachinePointerInfo());
1864 /// IsTailCallConvention - Return true if the calling convention is one that
1865 /// supports tail call optimization.
1866 static bool IsTailCallConvention(CallingConv::ID CC) {
1867 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
1868 CC == CallingConv::HiPE);
1871 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
1872 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
1876 CallingConv::ID CalleeCC = CS.getCallingConv();
1877 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C)
1883 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
1884 /// a tailcall target by changing its ABI.
1885 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
1886 bool GuaranteedTailCallOpt) {
1887 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
1891 X86TargetLowering::LowerMemArgument(SDValue Chain,
1892 CallingConv::ID CallConv,
1893 const SmallVectorImpl<ISD::InputArg> &Ins,
1894 DebugLoc dl, SelectionDAG &DAG,
1895 const CCValAssign &VA,
1896 MachineFrameInfo *MFI,
1898 // Create the nodes corresponding to a load from this parameter slot.
1899 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1900 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv,
1901 getTargetMachine().Options.GuaranteedTailCallOpt);
1902 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1905 // If value is passed by pointer we have address passed instead of the value
1907 if (VA.getLocInfo() == CCValAssign::Indirect)
1908 ValVT = VA.getLocVT();
1910 ValVT = VA.getValVT();
1912 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1913 // changed with more analysis.
1914 // In case of tail call optimization mark all arguments mutable. Since they
1915 // could be overwritten by lowering of arguments in case of a tail call.
1916 if (Flags.isByVal()) {
1917 unsigned Bytes = Flags.getByValSize();
1918 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
1919 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
1920 return DAG.getFrameIndex(FI, getPointerTy());
1922 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
1923 VA.getLocMemOffset(), isImmutable);
1924 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1925 return DAG.getLoad(ValVT, dl, Chain, FIN,
1926 MachinePointerInfo::getFixedStack(FI),
1927 false, false, false, 0);
1932 X86TargetLowering::LowerFormalArguments(SDValue Chain,
1933 CallingConv::ID CallConv,
1935 const SmallVectorImpl<ISD::InputArg> &Ins,
1938 SmallVectorImpl<SDValue> &InVals)
1940 MachineFunction &MF = DAG.getMachineFunction();
1941 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1943 const Function* Fn = MF.getFunction();
1944 if (Fn->hasExternalLinkage() &&
1945 Subtarget->isTargetCygMing() &&
1946 Fn->getName() == "main")
1947 FuncInfo->setForceFramePointer(true);
1949 MachineFrameInfo *MFI = MF.getFrameInfo();
1950 bool Is64Bit = Subtarget->is64Bit();
1951 bool IsWindows = Subtarget->isTargetWindows();
1952 bool IsWin64 = Subtarget->isTargetWin64();
1954 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
1955 "Var args not supported with calling convention fastcc, ghc or hipe");
1957 // Assign locations to all of the incoming arguments.
1958 SmallVector<CCValAssign, 16> ArgLocs;
1959 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1960 ArgLocs, *DAG.getContext());
1962 // Allocate shadow area for Win64
1964 CCInfo.AllocateStack(32, 8);
1967 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
1969 unsigned LastVal = ~0U;
1971 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1972 CCValAssign &VA = ArgLocs[i];
1973 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1975 assert(VA.getValNo() != LastVal &&
1976 "Don't support value assigned to multiple locs yet");
1978 LastVal = VA.getValNo();
1980 if (VA.isRegLoc()) {
1981 EVT RegVT = VA.getLocVT();
1982 const TargetRegisterClass *RC;
1983 if (RegVT == MVT::i32)
1984 RC = &X86::GR32RegClass;
1985 else if (Is64Bit && RegVT == MVT::i64)
1986 RC = &X86::GR64RegClass;
1987 else if (RegVT == MVT::f32)
1988 RC = &X86::FR32RegClass;
1989 else if (RegVT == MVT::f64)
1990 RC = &X86::FR64RegClass;
1991 else if (RegVT.is256BitVector())
1992 RC = &X86::VR256RegClass;
1993 else if (RegVT.is128BitVector())
1994 RC = &X86::VR128RegClass;
1995 else if (RegVT == MVT::x86mmx)
1996 RC = &X86::VR64RegClass;
1998 llvm_unreachable("Unknown argument type!");
2000 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2001 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2003 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2004 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2006 if (VA.getLocInfo() == CCValAssign::SExt)
2007 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2008 DAG.getValueType(VA.getValVT()));
2009 else if (VA.getLocInfo() == CCValAssign::ZExt)
2010 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2011 DAG.getValueType(VA.getValVT()));
2012 else if (VA.getLocInfo() == CCValAssign::BCvt)
2013 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2015 if (VA.isExtInLoc()) {
2016 // Handle MMX values passed in XMM regs.
2017 if (RegVT.isVector())
2018 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2020 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2023 assert(VA.isMemLoc());
2024 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2027 // If value is passed via pointer - do a load.
2028 if (VA.getLocInfo() == CCValAssign::Indirect)
2029 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2030 MachinePointerInfo(), false, false, false, 0);
2032 InVals.push_back(ArgValue);
2035 // The x86-64 ABIs require that for returning structs by value we copy
2036 // the sret argument into %rax/%eax (depending on ABI) for the return.
2037 // Save the argument into a virtual register so that we can access it
2038 // from the return points.
2039 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) {
2040 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2041 unsigned Reg = FuncInfo->getSRetReturnReg();
2043 MVT PtrTy = getPointerTy();
2044 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2045 FuncInfo->setSRetReturnReg(Reg);
2047 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
2048 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2051 unsigned StackSize = CCInfo.getNextStackOffset();
2052 // Align stack specially for tail calls.
2053 if (FuncIsMadeTailCallSafe(CallConv,
2054 MF.getTarget().Options.GuaranteedTailCallOpt))
2055 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2057 // If the function takes variable number of arguments, make a frame index for
2058 // the start of the first vararg value... for expansion of llvm.va_start.
2060 if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2061 CallConv != CallingConv::X86_ThisCall)) {
2062 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
2065 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
2067 // FIXME: We should really autogenerate these arrays
2068 static const uint16_t GPR64ArgRegsWin64[] = {
2069 X86::RCX, X86::RDX, X86::R8, X86::R9
2071 static const uint16_t GPR64ArgRegs64Bit[] = {
2072 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2074 static const uint16_t XMMArgRegs64Bit[] = {
2075 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2076 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2078 const uint16_t *GPR64ArgRegs;
2079 unsigned NumXMMRegs = 0;
2082 // The XMM registers which might contain var arg parameters are shadowed
2083 // in their paired GPR. So we only need to save the GPR to their home
2085 TotalNumIntRegs = 4;
2086 GPR64ArgRegs = GPR64ArgRegsWin64;
2088 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
2089 GPR64ArgRegs = GPR64ArgRegs64Bit;
2091 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit,
2094 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
2097 bool NoImplicitFloatOps = Fn->getAttributes().
2098 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2099 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2100 "SSE register cannot be used when SSE is disabled!");
2101 assert(!(NumXMMRegs && MF.getTarget().Options.UseSoftFloat &&
2102 NoImplicitFloatOps) &&
2103 "SSE register cannot be used when SSE is disabled!");
2104 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2105 !Subtarget->hasSSE1())
2106 // Kernel mode asks for SSE to be disabled, so don't push them
2108 TotalNumXMMRegs = 0;
2111 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering();
2112 // Get to the caller-allocated home save location. Add 8 to account
2113 // for the return address.
2114 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2115 FuncInfo->setRegSaveFrameIndex(
2116 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2117 // Fixup to set vararg frame on shadow area (4 x i64).
2119 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2121 // For X86-64, if there are vararg parameters that are passed via
2122 // registers, then we must store them to their spots on the stack so
2123 // they may be loaded by deferencing the result of va_next.
2124 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2125 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
2126 FuncInfo->setRegSaveFrameIndex(
2127 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
2131 // Store the integer parameter registers.
2132 SmallVector<SDValue, 8> MemOps;
2133 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2135 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2136 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
2137 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2138 DAG.getIntPtrConstant(Offset));
2139 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
2140 &X86::GR64RegClass);
2141 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2143 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2144 MachinePointerInfo::getFixedStack(
2145 FuncInfo->getRegSaveFrameIndex(), Offset),
2147 MemOps.push_back(Store);
2151 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
2152 // Now store the XMM (fp + vector) parameter registers.
2153 SmallVector<SDValue, 11> SaveXMMOps;
2154 SaveXMMOps.push_back(Chain);
2156 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2157 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
2158 SaveXMMOps.push_back(ALVal);
2160 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2161 FuncInfo->getRegSaveFrameIndex()));
2162 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2163 FuncInfo->getVarArgsFPOffset()));
2165 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
2166 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs],
2167 &X86::VR128RegClass);
2168 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
2169 SaveXMMOps.push_back(Val);
2171 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2173 &SaveXMMOps[0], SaveXMMOps.size()));
2176 if (!MemOps.empty())
2177 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2178 &MemOps[0], MemOps.size());
2182 // Some CCs need callee pop.
2183 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2184 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2185 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2187 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2188 // If this is an sret function, the return should pop the hidden pointer.
2189 if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows &&
2190 argsAreStructReturn(Ins) == StackStructReturn)
2191 FuncInfo->setBytesToPopOnReturn(4);
2195 // RegSaveFrameIndex is X86-64 only.
2196 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2197 if (CallConv == CallingConv::X86_FastCall ||
2198 CallConv == CallingConv::X86_ThisCall)
2199 // fastcc functions can't have varargs.
2200 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2203 FuncInfo->setArgumentStackSize(StackSize);
2209 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2210 SDValue StackPtr, SDValue Arg,
2211 DebugLoc dl, SelectionDAG &DAG,
2212 const CCValAssign &VA,
2213 ISD::ArgFlagsTy Flags) const {
2214 unsigned LocMemOffset = VA.getLocMemOffset();
2215 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2216 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2217 if (Flags.isByVal())
2218 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2220 return DAG.getStore(Chain, dl, Arg, PtrOff,
2221 MachinePointerInfo::getStack(LocMemOffset),
2225 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2226 /// optimization is performed and it is required.
2228 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2229 SDValue &OutRetAddr, SDValue Chain,
2230 bool IsTailCall, bool Is64Bit,
2231 int FPDiff, DebugLoc dl) const {
2232 // Adjust the Return address stack slot.
2233 EVT VT = getPointerTy();
2234 OutRetAddr = getReturnAddressFrameIndex(DAG);
2236 // Load the "old" Return address.
2237 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2238 false, false, false, 0);
2239 return SDValue(OutRetAddr.getNode(), 1);
2242 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2243 /// optimization is performed and it is required (FPDiff!=0).
2245 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
2246 SDValue Chain, SDValue RetAddrFrIdx, EVT PtrVT,
2247 unsigned SlotSize, int FPDiff, DebugLoc dl) {
2248 // Store the return address to the appropriate stack slot.
2249 if (!FPDiff) return Chain;
2250 // Calculate the new stack slot for the return address.
2251 int NewReturnAddrFI =
2252 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false);
2253 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2254 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2255 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2261 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2262 SmallVectorImpl<SDValue> &InVals) const {
2263 SelectionDAG &DAG = CLI.DAG;
2264 DebugLoc &dl = CLI.DL;
2265 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
2266 SmallVector<SDValue, 32> &OutVals = CLI.OutVals;
2267 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;
2268 SDValue Chain = CLI.Chain;
2269 SDValue Callee = CLI.Callee;
2270 CallingConv::ID CallConv = CLI.CallConv;
2271 bool &isTailCall = CLI.IsTailCall;
2272 bool isVarArg = CLI.IsVarArg;
2274 MachineFunction &MF = DAG.getMachineFunction();
2275 bool Is64Bit = Subtarget->is64Bit();
2276 bool IsWin64 = Subtarget->isTargetWin64();
2277 bool IsWindows = Subtarget->isTargetWindows();
2278 StructReturnType SR = callIsStructReturn(Outs);
2279 bool IsSibcall = false;
2281 if (MF.getTarget().Options.DisableTailCalls)
2285 // Check if it's really possible to do a tail call.
2286 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2287 isVarArg, SR != NotStructReturn,
2288 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2289 Outs, OutVals, Ins, DAG);
2291 // Sibcalls are automatically detected tailcalls which do not require
2293 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2300 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2301 "Var args not supported with calling convention fastcc, ghc or hipe");
2303 // Analyze operands of the call, assigning locations to each operand.
2304 SmallVector<CCValAssign, 16> ArgLocs;
2305 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
2306 ArgLocs, *DAG.getContext());
2308 // Allocate shadow area for Win64
2310 CCInfo.AllocateStack(32, 8);
2313 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2315 // Get a count of how many bytes are to be pushed on the stack.
2316 unsigned NumBytes = CCInfo.getNextStackOffset();
2318 // This is a sibcall. The memory operands are available in caller's
2319 // own caller's stack.
2321 else if (getTargetMachine().Options.GuaranteedTailCallOpt &&
2322 IsTailCallConvention(CallConv))
2323 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2326 if (isTailCall && !IsSibcall) {
2327 // Lower arguments at fp - stackoffset + fpdiff.
2328 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2329 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2331 FPDiff = NumBytesCallerPushed - NumBytes;
2333 // Set the delta of movement of the returnaddr stackslot.
2334 // But only set if delta is greater than previous delta.
2335 if (FPDiff < X86Info->getTCReturnAddrDelta())
2336 X86Info->setTCReturnAddrDelta(FPDiff);
2340 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
2342 SDValue RetAddrFrIdx;
2343 // Load return address for tail calls.
2344 if (isTailCall && FPDiff)
2345 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2346 Is64Bit, FPDiff, dl);
2348 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2349 SmallVector<SDValue, 8> MemOpChains;
2352 // Walk the register/memloc assignments, inserting copies/loads. In the case
2353 // of tail call optimization arguments are handle later.
2354 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2355 CCValAssign &VA = ArgLocs[i];
2356 EVT RegVT = VA.getLocVT();
2357 SDValue Arg = OutVals[i];
2358 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2359 bool isByVal = Flags.isByVal();
2361 // Promote the value if needed.
2362 switch (VA.getLocInfo()) {
2363 default: llvm_unreachable("Unknown loc info!");
2364 case CCValAssign::Full: break;
2365 case CCValAssign::SExt:
2366 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2368 case CCValAssign::ZExt:
2369 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2371 case CCValAssign::AExt:
2372 if (RegVT.is128BitVector()) {
2373 // Special case: passing MMX values in XMM registers.
2374 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2375 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2376 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2378 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2380 case CCValAssign::BCvt:
2381 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2383 case CCValAssign::Indirect: {
2384 // Store the argument.
2385 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2386 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2387 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2388 MachinePointerInfo::getFixedStack(FI),
2395 if (VA.isRegLoc()) {
2396 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2397 if (isVarArg && IsWin64) {
2398 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2399 // shadow reg if callee is a varargs function.
2400 unsigned ShadowReg = 0;
2401 switch (VA.getLocReg()) {
2402 case X86::XMM0: ShadowReg = X86::RCX; break;
2403 case X86::XMM1: ShadowReg = X86::RDX; break;
2404 case X86::XMM2: ShadowReg = X86::R8; break;
2405 case X86::XMM3: ShadowReg = X86::R9; break;
2408 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2410 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2411 assert(VA.isMemLoc());
2412 if (StackPtr.getNode() == 0)
2413 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2415 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2416 dl, DAG, VA, Flags));
2420 if (!MemOpChains.empty())
2421 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2422 &MemOpChains[0], MemOpChains.size());
2424 if (Subtarget->isPICStyleGOT()) {
2425 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2428 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2429 DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy())));
2431 // If we are tail calling and generating PIC/GOT style code load the
2432 // address of the callee into ECX. The value in ecx is used as target of
2433 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2434 // for tail calls on PIC/GOT architectures. Normally we would just put the
2435 // address of GOT into ebx and then call target@PLT. But for tail calls
2436 // ebx would be restored (since ebx is callee saved) before jumping to the
2439 // Note: The actual moving to ECX is done further down.
2440 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2441 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2442 !G->getGlobal()->hasProtectedVisibility())
2443 Callee = LowerGlobalAddress(Callee, DAG);
2444 else if (isa<ExternalSymbolSDNode>(Callee))
2445 Callee = LowerExternalSymbol(Callee, DAG);
2449 if (Is64Bit && isVarArg && !IsWin64) {
2450 // From AMD64 ABI document:
2451 // For calls that may call functions that use varargs or stdargs
2452 // (prototype-less calls or calls to functions containing ellipsis (...) in
2453 // the declaration) %al is used as hidden argument to specify the number
2454 // of SSE registers used. The contents of %al do not need to match exactly
2455 // the number of registers, but must be an ubound on the number of SSE
2456 // registers used and is in the range 0 - 8 inclusive.
2458 // Count the number of XMM registers allocated.
2459 static const uint16_t XMMArgRegs[] = {
2460 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2461 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2463 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2464 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2465 && "SSE registers cannot be used when SSE is disabled");
2467 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2468 DAG.getConstant(NumXMMRegs, MVT::i8)));
2471 // For tail calls lower the arguments to the 'real' stack slot.
2473 // Force all the incoming stack arguments to be loaded from the stack
2474 // before any new outgoing arguments are stored to the stack, because the
2475 // outgoing stack slots may alias the incoming argument stack slots, and
2476 // the alias isn't otherwise explicit. This is slightly more conservative
2477 // than necessary, because it means that each store effectively depends
2478 // on every argument instead of just those arguments it would clobber.
2479 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2481 SmallVector<SDValue, 8> MemOpChains2;
2484 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2485 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2486 CCValAssign &VA = ArgLocs[i];
2489 assert(VA.isMemLoc());
2490 SDValue Arg = OutVals[i];
2491 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2492 // Create frame index.
2493 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2494 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2495 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2496 FIN = DAG.getFrameIndex(FI, getPointerTy());
2498 if (Flags.isByVal()) {
2499 // Copy relative to framepointer.
2500 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2501 if (StackPtr.getNode() == 0)
2502 StackPtr = DAG.getCopyFromReg(Chain, dl,
2503 RegInfo->getStackRegister(),
2505 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2507 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2511 // Store relative to framepointer.
2512 MemOpChains2.push_back(
2513 DAG.getStore(ArgChain, dl, Arg, FIN,
2514 MachinePointerInfo::getFixedStack(FI),
2520 if (!MemOpChains2.empty())
2521 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2522 &MemOpChains2[0], MemOpChains2.size());
2524 // Store the return address to the appropriate stack slot.
2525 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
2526 getPointerTy(), RegInfo->getSlotSize(),
2530 // Build a sequence of copy-to-reg nodes chained together with token chain
2531 // and flag operands which copy the outgoing args into registers.
2533 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2534 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2535 RegsToPass[i].second, InFlag);
2536 InFlag = Chain.getValue(1);
2539 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2540 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2541 // In the 64-bit large code model, we have to make all calls
2542 // through a register, since the call instruction's 32-bit
2543 // pc-relative offset may not be large enough to hold the whole
2545 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2546 // If the callee is a GlobalAddress node (quite common, every direct call
2547 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2550 // We should use extra load for direct calls to dllimported functions in
2552 const GlobalValue *GV = G->getGlobal();
2553 if (!GV->hasDLLImportLinkage()) {
2554 unsigned char OpFlags = 0;
2555 bool ExtraLoad = false;
2556 unsigned WrapperKind = ISD::DELETED_NODE;
2558 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2559 // external symbols most go through the PLT in PIC mode. If the symbol
2560 // has hidden or protected visibility, or if it is static or local, then
2561 // we don't need to use the PLT - we can directly call it.
2562 if (Subtarget->isTargetELF() &&
2563 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2564 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2565 OpFlags = X86II::MO_PLT;
2566 } else if (Subtarget->isPICStyleStubAny() &&
2567 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2568 (!Subtarget->getTargetTriple().isMacOSX() ||
2569 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2570 // PC-relative references to external symbols should go through $stub,
2571 // unless we're building with the leopard linker or later, which
2572 // automatically synthesizes these stubs.
2573 OpFlags = X86II::MO_DARWIN_STUB;
2574 } else if (Subtarget->isPICStyleRIPRel() &&
2575 isa<Function>(GV) &&
2576 cast<Function>(GV)->getAttributes().
2577 hasAttribute(AttributeSet::FunctionIndex,
2578 Attribute::NonLazyBind)) {
2579 // If the function is marked as non-lazy, generate an indirect call
2580 // which loads from the GOT directly. This avoids runtime overhead
2581 // at the cost of eager binding (and one extra byte of encoding).
2582 OpFlags = X86II::MO_GOTPCREL;
2583 WrapperKind = X86ISD::WrapperRIP;
2587 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2588 G->getOffset(), OpFlags);
2590 // Add a wrapper if needed.
2591 if (WrapperKind != ISD::DELETED_NODE)
2592 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
2593 // Add extra indirection if needed.
2595 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
2596 MachinePointerInfo::getGOT(),
2597 false, false, false, 0);
2599 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2600 unsigned char OpFlags = 0;
2602 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
2603 // external symbols should go through the PLT.
2604 if (Subtarget->isTargetELF() &&
2605 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2606 OpFlags = X86II::MO_PLT;
2607 } else if (Subtarget->isPICStyleStubAny() &&
2608 (!Subtarget->getTargetTriple().isMacOSX() ||
2609 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2610 // PC-relative references to external symbols should go through $stub,
2611 // unless we're building with the leopard linker or later, which
2612 // automatically synthesizes these stubs.
2613 OpFlags = X86II::MO_DARWIN_STUB;
2616 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2620 // Returns a chain & a flag for retval copy to use.
2621 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2622 SmallVector<SDValue, 8> Ops;
2624 if (!IsSibcall && isTailCall) {
2625 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2626 DAG.getIntPtrConstant(0, true), InFlag);
2627 InFlag = Chain.getValue(1);
2630 Ops.push_back(Chain);
2631 Ops.push_back(Callee);
2634 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2636 // Add argument registers to the end of the list so that they are known live
2638 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2639 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2640 RegsToPass[i].second.getValueType()));
2642 // Add a register mask operand representing the call-preserved registers.
2643 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2644 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
2645 assert(Mask && "Missing call preserved mask for calling convention");
2646 Ops.push_back(DAG.getRegisterMask(Mask));
2648 if (InFlag.getNode())
2649 Ops.push_back(InFlag);
2653 //// If this is the first return lowered for this function, add the regs
2654 //// to the liveout set for the function.
2655 // This isn't right, although it's probably harmless on x86; liveouts
2656 // should be computed from returns not tail calls. Consider a void
2657 // function making a tail call to a function returning int.
2658 return DAG.getNode(X86ISD::TC_RETURN, dl,
2659 NodeTys, &Ops[0], Ops.size());
2662 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2663 InFlag = Chain.getValue(1);
2665 // Create the CALLSEQ_END node.
2666 unsigned NumBytesForCalleeToPush;
2667 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2668 getTargetMachine().Options.GuaranteedTailCallOpt))
2669 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2670 else if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows &&
2671 SR == StackStructReturn)
2672 // If this is a call to a struct-return function, the callee
2673 // pops the hidden struct pointer, so we have to push it back.
2674 // This is common for Darwin/X86, Linux & Mingw32 targets.
2675 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
2676 NumBytesForCalleeToPush = 4;
2678 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2680 // Returns a flag for retval copy to use.
2682 Chain = DAG.getCALLSEQ_END(Chain,
2683 DAG.getIntPtrConstant(NumBytes, true),
2684 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2687 InFlag = Chain.getValue(1);
2690 // Handle result values, copying them out of physregs into vregs that we
2692 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2693 Ins, dl, DAG, InVals);
2696 //===----------------------------------------------------------------------===//
2697 // Fast Calling Convention (tail call) implementation
2698 //===----------------------------------------------------------------------===//
2700 // Like std call, callee cleans arguments, convention except that ECX is
2701 // reserved for storing the tail called function address. Only 2 registers are
2702 // free for argument passing (inreg). Tail call optimization is performed
2704 // * tailcallopt is enabled
2705 // * caller/callee are fastcc
2706 // On X86_64 architecture with GOT-style position independent code only local
2707 // (within module) calls are supported at the moment.
2708 // To keep the stack aligned according to platform abi the function
2709 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2710 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2711 // If a tail called function callee has more arguments than the caller the
2712 // caller needs to make sure that there is room to move the RETADDR to. This is
2713 // achieved by reserving an area the size of the argument delta right after the
2714 // original REtADDR, but before the saved framepointer or the spilled registers
2715 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2727 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2728 /// for a 16 byte align requirement.
2730 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2731 SelectionDAG& DAG) const {
2732 MachineFunction &MF = DAG.getMachineFunction();
2733 const TargetMachine &TM = MF.getTarget();
2734 const TargetFrameLowering &TFI = *TM.getFrameLowering();
2735 unsigned StackAlignment = TFI.getStackAlignment();
2736 uint64_t AlignMask = StackAlignment - 1;
2737 int64_t Offset = StackSize;
2738 unsigned SlotSize = RegInfo->getSlotSize();
2739 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2740 // Number smaller than 12 so just add the difference.
2741 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2743 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2744 Offset = ((~AlignMask) & Offset) + StackAlignment +
2745 (StackAlignment-SlotSize);
2750 /// MatchingStackOffset - Return true if the given stack call argument is
2751 /// already available in the same position (relatively) of the caller's
2752 /// incoming argument stack.
2754 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2755 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
2756 const X86InstrInfo *TII) {
2757 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
2759 if (Arg.getOpcode() == ISD::CopyFromReg) {
2760 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2761 if (!TargetRegisterInfo::isVirtualRegister(VR))
2763 MachineInstr *Def = MRI->getVRegDef(VR);
2766 if (!Flags.isByVal()) {
2767 if (!TII->isLoadFromStackSlot(Def, FI))
2770 unsigned Opcode = Def->getOpcode();
2771 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
2772 Def->getOperand(1).isFI()) {
2773 FI = Def->getOperand(1).getIndex();
2774 Bytes = Flags.getByValSize();
2778 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2779 if (Flags.isByVal())
2780 // ByVal argument is passed in as a pointer but it's now being
2781 // dereferenced. e.g.
2782 // define @foo(%struct.X* %A) {
2783 // tail call @bar(%struct.X* byval %A)
2786 SDValue Ptr = Ld->getBasePtr();
2787 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2790 FI = FINode->getIndex();
2791 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
2792 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
2793 FI = FINode->getIndex();
2794 Bytes = Flags.getByValSize();
2798 assert(FI != INT_MAX);
2799 if (!MFI->isFixedObjectIndex(FI))
2801 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
2804 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2805 /// for tail call optimization. Targets which want to do tail call
2806 /// optimization should implement this function.
2808 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2809 CallingConv::ID CalleeCC,
2811 bool isCalleeStructRet,
2812 bool isCallerStructRet,
2814 const SmallVectorImpl<ISD::OutputArg> &Outs,
2815 const SmallVectorImpl<SDValue> &OutVals,
2816 const SmallVectorImpl<ISD::InputArg> &Ins,
2817 SelectionDAG& DAG) const {
2818 if (!IsTailCallConvention(CalleeCC) &&
2819 CalleeCC != CallingConv::C)
2822 // If -tailcallopt is specified, make fastcc functions tail-callable.
2823 const MachineFunction &MF = DAG.getMachineFunction();
2824 const Function *CallerF = DAG.getMachineFunction().getFunction();
2826 // If the function return type is x86_fp80 and the callee return type is not,
2827 // then the FP_EXTEND of the call result is not a nop. It's not safe to
2828 // perform a tailcall optimization here.
2829 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
2832 CallingConv::ID CallerCC = CallerF->getCallingConv();
2833 bool CCMatch = CallerCC == CalleeCC;
2835 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2836 if (IsTailCallConvention(CalleeCC) && CCMatch)
2841 // Look for obvious safe cases to perform tail call optimization that do not
2842 // require ABI changes. This is what gcc calls sibcall.
2844 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
2845 // emit a special epilogue.
2846 if (RegInfo->needsStackRealignment(MF))
2849 // Also avoid sibcall optimization if either caller or callee uses struct
2850 // return semantics.
2851 if (isCalleeStructRet || isCallerStructRet)
2854 // An stdcall caller is expected to clean up its arguments; the callee
2855 // isn't going to do that.
2856 if (!CCMatch && CallerCC==CallingConv::X86_StdCall)
2859 // Do not sibcall optimize vararg calls unless all arguments are passed via
2861 if (isVarArg && !Outs.empty()) {
2863 // Optimizing for varargs on Win64 is unlikely to be safe without
2864 // additional testing.
2865 if (Subtarget->isTargetWin64())
2868 SmallVector<CCValAssign, 16> ArgLocs;
2869 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2870 getTargetMachine(), ArgLocs, *DAG.getContext());
2872 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2873 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
2874 if (!ArgLocs[i].isRegLoc())
2878 // If the call result is in ST0 / ST1, it needs to be popped off the x87
2879 // stack. Therefore, if it's not used by the call it is not safe to optimize
2880 // this into a sibcall.
2881 bool Unused = false;
2882 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
2889 SmallVector<CCValAssign, 16> RVLocs;
2890 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(),
2891 getTargetMachine(), RVLocs, *DAG.getContext());
2892 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2893 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2894 CCValAssign &VA = RVLocs[i];
2895 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
2900 // If the calling conventions do not match, then we'd better make sure the
2901 // results are returned in the same way as what the caller expects.
2903 SmallVector<CCValAssign, 16> RVLocs1;
2904 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
2905 getTargetMachine(), RVLocs1, *DAG.getContext());
2906 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
2908 SmallVector<CCValAssign, 16> RVLocs2;
2909 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
2910 getTargetMachine(), RVLocs2, *DAG.getContext());
2911 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
2913 if (RVLocs1.size() != RVLocs2.size())
2915 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2916 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2918 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2920 if (RVLocs1[i].isRegLoc()) {
2921 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2924 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2930 // If the callee takes no arguments then go on to check the results of the
2932 if (!Outs.empty()) {
2933 // Check if stack adjustment is needed. For now, do not do this if any
2934 // argument is passed on the stack.
2935 SmallVector<CCValAssign, 16> ArgLocs;
2936 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2937 getTargetMachine(), ArgLocs, *DAG.getContext());
2939 // Allocate shadow area for Win64
2940 if (Subtarget->isTargetWin64()) {
2941 CCInfo.AllocateStack(32, 8);
2944 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2945 if (CCInfo.getNextStackOffset()) {
2946 MachineFunction &MF = DAG.getMachineFunction();
2947 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
2950 // Check if the arguments are already laid out in the right way as
2951 // the caller's fixed stack objects.
2952 MachineFrameInfo *MFI = MF.getFrameInfo();
2953 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2954 const X86InstrInfo *TII =
2955 ((const X86TargetMachine&)getTargetMachine()).getInstrInfo();
2956 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2957 CCValAssign &VA = ArgLocs[i];
2958 SDValue Arg = OutVals[i];
2959 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2960 if (VA.getLocInfo() == CCValAssign::Indirect)
2962 if (!VA.isRegLoc()) {
2963 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2970 // If the tailcall address may be in a register, then make sure it's
2971 // possible to register allocate for it. In 32-bit, the call address can
2972 // only target EAX, EDX, or ECX since the tail call must be scheduled after
2973 // callee-saved registers are restored. These happen to be the same
2974 // registers used to pass 'inreg' arguments so watch out for those.
2975 if (!Subtarget->is64Bit() &&
2976 !isa<GlobalAddressSDNode>(Callee) &&
2977 !isa<ExternalSymbolSDNode>(Callee)) {
2978 unsigned NumInRegs = 0;
2979 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2980 CCValAssign &VA = ArgLocs[i];
2983 unsigned Reg = VA.getLocReg();
2986 case X86::EAX: case X86::EDX: case X86::ECX:
2987 if (++NumInRegs == 3)
2999 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3000 const TargetLibraryInfo *libInfo) const {
3001 return X86::createFastISel(funcInfo, libInfo);
3004 //===----------------------------------------------------------------------===//
3005 // Other Lowering Hooks
3006 //===----------------------------------------------------------------------===//
3008 static bool MayFoldLoad(SDValue Op) {
3009 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3012 static bool MayFoldIntoStore(SDValue Op) {
3013 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3016 static bool isTargetShuffle(unsigned Opcode) {
3018 default: return false;
3019 case X86ISD::PSHUFD:
3020 case X86ISD::PSHUFHW:
3021 case X86ISD::PSHUFLW:
3023 case X86ISD::PALIGNR:
3024 case X86ISD::MOVLHPS:
3025 case X86ISD::MOVLHPD:
3026 case X86ISD::MOVHLPS:
3027 case X86ISD::MOVLPS:
3028 case X86ISD::MOVLPD:
3029 case X86ISD::MOVSHDUP:
3030 case X86ISD::MOVSLDUP:
3031 case X86ISD::MOVDDUP:
3034 case X86ISD::UNPCKL:
3035 case X86ISD::UNPCKH:
3036 case X86ISD::VPERMILP:
3037 case X86ISD::VPERM2X128:
3038 case X86ISD::VPERMI:
3043 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
3044 SDValue V1, SelectionDAG &DAG) {
3046 default: llvm_unreachable("Unknown x86 shuffle node");
3047 case X86ISD::MOVSHDUP:
3048 case X86ISD::MOVSLDUP:
3049 case X86ISD::MOVDDUP:
3050 return DAG.getNode(Opc, dl, VT, V1);
3054 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
3055 SDValue V1, unsigned TargetMask,
3056 SelectionDAG &DAG) {
3058 default: llvm_unreachable("Unknown x86 shuffle node");
3059 case X86ISD::PSHUFD:
3060 case X86ISD::PSHUFHW:
3061 case X86ISD::PSHUFLW:
3062 case X86ISD::VPERMILP:
3063 case X86ISD::VPERMI:
3064 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3068 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
3069 SDValue V1, SDValue V2, unsigned TargetMask,
3070 SelectionDAG &DAG) {
3072 default: llvm_unreachable("Unknown x86 shuffle node");
3073 case X86ISD::PALIGNR:
3075 case X86ISD::VPERM2X128:
3076 return DAG.getNode(Opc, dl, VT, V1, V2,
3077 DAG.getConstant(TargetMask, MVT::i8));
3081 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
3082 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3084 default: llvm_unreachable("Unknown x86 shuffle node");
3085 case X86ISD::MOVLHPS:
3086 case X86ISD::MOVLHPD:
3087 case X86ISD::MOVHLPS:
3088 case X86ISD::MOVLPS:
3089 case X86ISD::MOVLPD:
3092 case X86ISD::UNPCKL:
3093 case X86ISD::UNPCKH:
3094 return DAG.getNode(Opc, dl, VT, V1, V2);
3098 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3099 MachineFunction &MF = DAG.getMachineFunction();
3100 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3101 int ReturnAddrIndex = FuncInfo->getRAIndex();
3103 if (ReturnAddrIndex == 0) {
3104 // Set up a frame object for the return address.
3105 unsigned SlotSize = RegInfo->getSlotSize();
3106 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
3108 FuncInfo->setRAIndex(ReturnAddrIndex);
3111 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3114 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3115 bool hasSymbolicDisplacement) {
3116 // Offset should fit into 32 bit immediate field.
3117 if (!isInt<32>(Offset))
3120 // If we don't have a symbolic displacement - we don't have any extra
3122 if (!hasSymbolicDisplacement)
3125 // FIXME: Some tweaks might be needed for medium code model.
3126 if (M != CodeModel::Small && M != CodeModel::Kernel)
3129 // For small code model we assume that latest object is 16MB before end of 31
3130 // bits boundary. We may also accept pretty large negative constants knowing
3131 // that all objects are in the positive half of address space.
3132 if (M == CodeModel::Small && Offset < 16*1024*1024)
3135 // For kernel code model we know that all object resist in the negative half
3136 // of 32bits address space. We may not accept negative offsets, since they may
3137 // be just off and we may accept pretty large positive ones.
3138 if (M == CodeModel::Kernel && Offset > 0)
3144 /// isCalleePop - Determines whether the callee is required to pop its
3145 /// own arguments. Callee pop is necessary to support tail calls.
3146 bool X86::isCalleePop(CallingConv::ID CallingConv,
3147 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3151 switch (CallingConv) {
3154 case CallingConv::X86_StdCall:
3156 case CallingConv::X86_FastCall:
3158 case CallingConv::X86_ThisCall:
3160 case CallingConv::Fast:
3162 case CallingConv::GHC:
3164 case CallingConv::HiPE:
3169 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3170 /// specific condition code, returning the condition code and the LHS/RHS of the
3171 /// comparison to make.
3172 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3173 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3175 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3176 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3177 // X > -1 -> X == 0, jump !sign.
3178 RHS = DAG.getConstant(0, RHS.getValueType());
3179 return X86::COND_NS;
3181 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3182 // X < 0 -> X == 0, jump on sign.
3185 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3187 RHS = DAG.getConstant(0, RHS.getValueType());
3188 return X86::COND_LE;
3192 switch (SetCCOpcode) {
3193 default: llvm_unreachable("Invalid integer condition!");
3194 case ISD::SETEQ: return X86::COND_E;
3195 case ISD::SETGT: return X86::COND_G;
3196 case ISD::SETGE: return X86::COND_GE;
3197 case ISD::SETLT: return X86::COND_L;
3198 case ISD::SETLE: return X86::COND_LE;
3199 case ISD::SETNE: return X86::COND_NE;
3200 case ISD::SETULT: return X86::COND_B;
3201 case ISD::SETUGT: return X86::COND_A;
3202 case ISD::SETULE: return X86::COND_BE;
3203 case ISD::SETUGE: return X86::COND_AE;
3207 // First determine if it is required or is profitable to flip the operands.
3209 // If LHS is a foldable load, but RHS is not, flip the condition.
3210 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3211 !ISD::isNON_EXTLoad(RHS.getNode())) {
3212 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3213 std::swap(LHS, RHS);
3216 switch (SetCCOpcode) {
3222 std::swap(LHS, RHS);
3226 // On a floating point condition, the flags are set as follows:
3228 // 0 | 0 | 0 | X > Y
3229 // 0 | 0 | 1 | X < Y
3230 // 1 | 0 | 0 | X == Y
3231 // 1 | 1 | 1 | unordered
3232 switch (SetCCOpcode) {
3233 default: llvm_unreachable("Condcode should be pre-legalized away");
3235 case ISD::SETEQ: return X86::COND_E;
3236 case ISD::SETOLT: // flipped
3238 case ISD::SETGT: return X86::COND_A;
3239 case ISD::SETOLE: // flipped
3241 case ISD::SETGE: return X86::COND_AE;
3242 case ISD::SETUGT: // flipped
3244 case ISD::SETLT: return X86::COND_B;
3245 case ISD::SETUGE: // flipped
3247 case ISD::SETLE: return X86::COND_BE;
3249 case ISD::SETNE: return X86::COND_NE;
3250 case ISD::SETUO: return X86::COND_P;
3251 case ISD::SETO: return X86::COND_NP;
3253 case ISD::SETUNE: return X86::COND_INVALID;
3257 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3258 /// code. Current x86 isa includes the following FP cmov instructions:
3259 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3260 static bool hasFPCMov(unsigned X86CC) {
3276 /// isFPImmLegal - Returns true if the target can instruction select the
3277 /// specified FP immediate natively. If false, the legalizer will
3278 /// materialize the FP immediate as a load from a constant pool.
3279 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3280 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3281 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3287 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3288 /// the specified range (L, H].
3289 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3290 return (Val < 0) || (Val >= Low && Val < Hi);
3293 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3294 /// specified value.
3295 static bool isUndefOrEqual(int Val, int CmpVal) {
3296 return (Val < 0 || Val == CmpVal);
3299 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3300 /// from position Pos and ending in Pos+Size, falls within the specified
3301 /// sequential range (L, L+Pos]. or is undef.
3302 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3303 unsigned Pos, unsigned Size, int Low) {
3304 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3305 if (!isUndefOrEqual(Mask[i], Low))
3310 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3311 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3312 /// the second operand.
3313 static bool isPSHUFDMask(ArrayRef<int> Mask, EVT VT) {
3314 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3315 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3316 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3317 return (Mask[0] < 2 && Mask[1] < 2);
3321 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3322 /// is suitable for input to PSHUFHW.
3323 static bool isPSHUFHWMask(ArrayRef<int> Mask, EVT VT, bool HasInt256) {
3324 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3327 // Lower quadword copied in order or undef.
3328 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3331 // Upper quadword shuffled.
3332 for (unsigned i = 4; i != 8; ++i)
3333 if (!isUndefOrInRange(Mask[i], 4, 8))
3336 if (VT == MVT::v16i16) {
3337 // Lower quadword copied in order or undef.
3338 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3341 // Upper quadword shuffled.
3342 for (unsigned i = 12; i != 16; ++i)
3343 if (!isUndefOrInRange(Mask[i], 12, 16))
3350 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3351 /// is suitable for input to PSHUFLW.
3352 static bool isPSHUFLWMask(ArrayRef<int> Mask, EVT VT, bool HasInt256) {
3353 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3356 // Upper quadword copied in order.
3357 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3360 // Lower quadword shuffled.
3361 for (unsigned i = 0; i != 4; ++i)
3362 if (!isUndefOrInRange(Mask[i], 0, 4))
3365 if (VT == MVT::v16i16) {
3366 // Upper quadword copied in order.
3367 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3370 // Lower quadword shuffled.
3371 for (unsigned i = 8; i != 12; ++i)
3372 if (!isUndefOrInRange(Mask[i], 8, 12))
3379 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
3380 /// is suitable for input to PALIGNR.
3381 static bool isPALIGNRMask(ArrayRef<int> Mask, EVT VT,
3382 const X86Subtarget *Subtarget) {
3383 if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
3384 (VT.is256BitVector() && !Subtarget->hasInt256()))
3387 unsigned NumElts = VT.getVectorNumElements();
3388 unsigned NumLanes = VT.getSizeInBits()/128;
3389 unsigned NumLaneElts = NumElts/NumLanes;
3391 // Do not handle 64-bit element shuffles with palignr.
3392 if (NumLaneElts == 2)
3395 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3397 for (i = 0; i != NumLaneElts; ++i) {
3402 // Lane is all undef, go to next lane
3403 if (i == NumLaneElts)
3406 int Start = Mask[i+l];
3408 // Make sure its in this lane in one of the sources
3409 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3410 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3413 // If not lane 0, then we must match lane 0
3414 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3417 // Correct second source to be contiguous with first source
3418 if (Start >= (int)NumElts)
3419 Start -= NumElts - NumLaneElts;
3421 // Make sure we're shifting in the right direction.
3422 if (Start <= (int)(i+l))
3427 // Check the rest of the elements to see if they are consecutive.
3428 for (++i; i != NumLaneElts; ++i) {
3429 int Idx = Mask[i+l];
3431 // Make sure its in this lane
3432 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3433 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3436 // If not lane 0, then we must match lane 0
3437 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3440 if (Idx >= (int)NumElts)
3441 Idx -= NumElts - NumLaneElts;
3443 if (!isUndefOrEqual(Idx, Start+i))
3452 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3453 /// the two vector operands have swapped position.
3454 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
3455 unsigned NumElems) {
3456 for (unsigned i = 0; i != NumElems; ++i) {
3460 else if (idx < (int)NumElems)
3461 Mask[i] = idx + NumElems;
3463 Mask[i] = idx - NumElems;
3467 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
3468 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
3469 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
3470 /// reverse of what x86 shuffles want.
3471 static bool isSHUFPMask(ArrayRef<int> Mask, EVT VT, bool HasFp256,
3472 bool Commuted = false) {
3473 if (!HasFp256 && VT.is256BitVector())
3476 unsigned NumElems = VT.getVectorNumElements();
3477 unsigned NumLanes = VT.getSizeInBits()/128;
3478 unsigned NumLaneElems = NumElems/NumLanes;
3480 if (NumLaneElems != 2 && NumLaneElems != 4)
3483 // VSHUFPSY divides the resulting vector into 4 chunks.
3484 // The sources are also splitted into 4 chunks, and each destination
3485 // chunk must come from a different source chunk.
3487 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
3488 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
3490 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
3491 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
3493 // VSHUFPDY divides the resulting vector into 4 chunks.
3494 // The sources are also splitted into 4 chunks, and each destination
3495 // chunk must come from a different source chunk.
3497 // SRC1 => X3 X2 X1 X0
3498 // SRC2 => Y3 Y2 Y1 Y0
3500 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
3502 unsigned HalfLaneElems = NumLaneElems/2;
3503 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
3504 for (unsigned i = 0; i != NumLaneElems; ++i) {
3505 int Idx = Mask[i+l];
3506 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
3507 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
3509 // For VSHUFPSY, the mask of the second half must be the same as the
3510 // first but with the appropriate offsets. This works in the same way as
3511 // VPERMILPS works with masks.
3512 if (NumElems != 8 || l == 0 || Mask[i] < 0)
3514 if (!isUndefOrEqual(Idx, Mask[i]+l))
3522 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
3523 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
3524 static bool isMOVHLPSMask(ArrayRef<int> Mask, EVT VT) {
3525 if (!VT.is128BitVector())
3528 unsigned NumElems = VT.getVectorNumElements();
3533 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
3534 return isUndefOrEqual(Mask[0], 6) &&
3535 isUndefOrEqual(Mask[1], 7) &&
3536 isUndefOrEqual(Mask[2], 2) &&
3537 isUndefOrEqual(Mask[3], 3);
3540 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
3541 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
3543 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, EVT VT) {
3544 if (!VT.is128BitVector())
3547 unsigned NumElems = VT.getVectorNumElements();
3552 return isUndefOrEqual(Mask[0], 2) &&
3553 isUndefOrEqual(Mask[1], 3) &&
3554 isUndefOrEqual(Mask[2], 2) &&
3555 isUndefOrEqual(Mask[3], 3);
3558 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
3559 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
3560 static bool isMOVLPMask(ArrayRef<int> Mask, EVT VT) {
3561 if (!VT.is128BitVector())
3564 unsigned NumElems = VT.getVectorNumElements();
3566 if (NumElems != 2 && NumElems != 4)
3569 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3570 if (!isUndefOrEqual(Mask[i], i + NumElems))
3573 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
3574 if (!isUndefOrEqual(Mask[i], i))
3580 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
3581 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
3582 static bool isMOVLHPSMask(ArrayRef<int> Mask, EVT VT) {
3583 if (!VT.is128BitVector())
3586 unsigned NumElems = VT.getVectorNumElements();
3588 if (NumElems != 2 && NumElems != 4)
3591 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3592 if (!isUndefOrEqual(Mask[i], i))
3595 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3596 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
3603 // Some special combinations that can be optimized.
3606 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
3607 SelectionDAG &DAG) {
3608 MVT VT = SVOp->getValueType(0).getSimpleVT();
3609 DebugLoc dl = SVOp->getDebugLoc();
3611 if (VT != MVT::v8i32 && VT != MVT::v8f32)
3614 ArrayRef<int> Mask = SVOp->getMask();
3616 // These are the special masks that may be optimized.
3617 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
3618 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
3619 bool MatchEvenMask = true;
3620 bool MatchOddMask = true;
3621 for (int i=0; i<8; ++i) {
3622 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
3623 MatchEvenMask = false;
3624 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
3625 MatchOddMask = false;
3628 if (!MatchEvenMask && !MatchOddMask)
3631 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
3633 SDValue Op0 = SVOp->getOperand(0);
3634 SDValue Op1 = SVOp->getOperand(1);
3636 if (MatchEvenMask) {
3637 // Shift the second operand right to 32 bits.
3638 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 };
3639 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
3641 // Shift the first operand left to 32 bits.
3642 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 };
3643 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
3645 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15};
3646 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
3649 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
3650 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
3651 static bool isUNPCKLMask(ArrayRef<int> Mask, EVT VT,
3652 bool HasInt256, bool V2IsSplat = false) {
3653 unsigned NumElts = VT.getVectorNumElements();
3655 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3656 "Unsupported vector type for unpckh");
3658 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
3659 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
3662 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3663 // independently on 128-bit lanes.
3664 unsigned NumLanes = VT.getSizeInBits()/128;
3665 unsigned NumLaneElts = NumElts/NumLanes;
3667 for (unsigned l = 0; l != NumLanes; ++l) {
3668 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts;
3669 i != (l+1)*NumLaneElts;
3672 int BitI1 = Mask[i+1];
3673 if (!isUndefOrEqual(BitI, j))
3676 if (!isUndefOrEqual(BitI1, NumElts))
3679 if (!isUndefOrEqual(BitI1, j + NumElts))
3688 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
3689 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
3690 static bool isUNPCKHMask(ArrayRef<int> Mask, EVT VT,
3691 bool HasInt256, bool V2IsSplat = false) {
3692 unsigned NumElts = VT.getVectorNumElements();
3694 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3695 "Unsupported vector type for unpckh");
3697 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
3698 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
3701 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3702 // independently on 128-bit lanes.
3703 unsigned NumLanes = VT.getSizeInBits()/128;
3704 unsigned NumLaneElts = NumElts/NumLanes;
3706 for (unsigned l = 0; l != NumLanes; ++l) {
3707 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2;
3708 i != (l+1)*NumLaneElts; i += 2, ++j) {
3710 int BitI1 = Mask[i+1];
3711 if (!isUndefOrEqual(BitI, j))
3714 if (isUndefOrEqual(BitI1, NumElts))
3717 if (!isUndefOrEqual(BitI1, j+NumElts))
3725 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
3726 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
3728 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, EVT VT, bool HasInt256) {
3729 unsigned NumElts = VT.getVectorNumElements();
3730 bool Is256BitVec = VT.is256BitVector();
3732 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3733 "Unsupported vector type for unpckh");
3735 if (Is256BitVec && NumElts != 4 && NumElts != 8 &&
3736 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
3739 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
3740 // FIXME: Need a better way to get rid of this, there's no latency difference
3741 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
3742 // the former later. We should also remove the "_undef" special mask.
3743 if (NumElts == 4 && Is256BitVec)
3746 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3747 // independently on 128-bit lanes.
3748 unsigned NumLanes = VT.getSizeInBits()/128;
3749 unsigned NumLaneElts = NumElts/NumLanes;
3751 for (unsigned l = 0; l != NumLanes; ++l) {
3752 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts;
3753 i != (l+1)*NumLaneElts;
3756 int BitI1 = Mask[i+1];
3758 if (!isUndefOrEqual(BitI, j))
3760 if (!isUndefOrEqual(BitI1, j))
3768 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
3769 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
3771 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, EVT VT, bool HasInt256) {
3772 unsigned NumElts = VT.getVectorNumElements();
3774 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3775 "Unsupported vector type for unpckh");
3777 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
3778 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
3781 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3782 // independently on 128-bit lanes.
3783 unsigned NumLanes = VT.getSizeInBits()/128;
3784 unsigned NumLaneElts = NumElts/NumLanes;
3786 for (unsigned l = 0; l != NumLanes; ++l) {
3787 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2;
3788 i != (l+1)*NumLaneElts; i += 2, ++j) {
3790 int BitI1 = Mask[i+1];
3791 if (!isUndefOrEqual(BitI, j))
3793 if (!isUndefOrEqual(BitI1, j))
3800 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
3801 /// specifies a shuffle of elements that is suitable for input to MOVSS,
3802 /// MOVSD, and MOVD, i.e. setting the lowest element.
3803 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
3804 if (VT.getVectorElementType().getSizeInBits() < 32)
3806 if (!VT.is128BitVector())
3809 unsigned NumElts = VT.getVectorNumElements();
3811 if (!isUndefOrEqual(Mask[0], NumElts))
3814 for (unsigned i = 1; i != NumElts; ++i)
3815 if (!isUndefOrEqual(Mask[i], i))
3821 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
3822 /// as permutations between 128-bit chunks or halves. As an example: this
3824 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
3825 /// The first half comes from the second half of V1 and the second half from the
3826 /// the second half of V2.
3827 static bool isVPERM2X128Mask(ArrayRef<int> Mask, EVT VT, bool HasFp256) {
3828 if (!HasFp256 || !VT.is256BitVector())
3831 // The shuffle result is divided into half A and half B. In total the two
3832 // sources have 4 halves, namely: C, D, E, F. The final values of A and
3833 // B must come from C, D, E or F.
3834 unsigned HalfSize = VT.getVectorNumElements()/2;
3835 bool MatchA = false, MatchB = false;
3837 // Check if A comes from one of C, D, E, F.
3838 for (unsigned Half = 0; Half != 4; ++Half) {
3839 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
3845 // Check if B comes from one of C, D, E, F.
3846 for (unsigned Half = 0; Half != 4; ++Half) {
3847 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
3853 return MatchA && MatchB;
3856 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
3857 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
3858 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
3859 MVT VT = SVOp->getValueType(0).getSimpleVT();
3861 unsigned HalfSize = VT.getVectorNumElements()/2;
3863 unsigned FstHalf = 0, SndHalf = 0;
3864 for (unsigned i = 0; i < HalfSize; ++i) {
3865 if (SVOp->getMaskElt(i) > 0) {
3866 FstHalf = SVOp->getMaskElt(i)/HalfSize;
3870 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
3871 if (SVOp->getMaskElt(i) > 0) {
3872 SndHalf = SVOp->getMaskElt(i)/HalfSize;
3877 return (FstHalf | (SndHalf << 4));
3880 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
3881 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
3882 /// Note that VPERMIL mask matching is different depending whether theunderlying
3883 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
3884 /// to the same elements of the low, but to the higher half of the source.
3885 /// In VPERMILPD the two lanes could be shuffled independently of each other
3886 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
3887 static bool isVPERMILPMask(ArrayRef<int> Mask, EVT VT, bool HasFp256) {
3891 unsigned NumElts = VT.getVectorNumElements();
3892 // Only match 256-bit with 32/64-bit types
3893 if (!VT.is256BitVector() || (NumElts != 4 && NumElts != 8))
3896 unsigned NumLanes = VT.getSizeInBits()/128;
3897 unsigned LaneSize = NumElts/NumLanes;
3898 for (unsigned l = 0; l != NumElts; l += LaneSize) {
3899 for (unsigned i = 0; i != LaneSize; ++i) {
3900 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
3902 if (NumElts != 8 || l == 0)
3904 // VPERMILPS handling
3907 if (!isUndefOrEqual(Mask[i+l], Mask[i]+l))
3915 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
3916 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
3917 /// element of vector 2 and the other elements to come from vector 1 in order.
3918 static bool isCommutedMOVLMask(ArrayRef<int> Mask, EVT VT,
3919 bool V2IsSplat = false, bool V2IsUndef = false) {
3920 if (!VT.is128BitVector())
3923 unsigned NumOps = VT.getVectorNumElements();
3924 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
3927 if (!isUndefOrEqual(Mask[0], 0))
3930 for (unsigned i = 1; i != NumOps; ++i)
3931 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
3932 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
3933 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
3939 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3940 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
3941 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
3942 static bool isMOVSHDUPMask(ArrayRef<int> Mask, EVT VT,
3943 const X86Subtarget *Subtarget) {
3944 if (!Subtarget->hasSSE3())
3947 unsigned NumElems = VT.getVectorNumElements();
3949 if ((VT.is128BitVector() && NumElems != 4) ||
3950 (VT.is256BitVector() && NumElems != 8))
3953 // "i+1" is the value the indexed mask element must have
3954 for (unsigned i = 0; i != NumElems; i += 2)
3955 if (!isUndefOrEqual(Mask[i], i+1) ||
3956 !isUndefOrEqual(Mask[i+1], i+1))
3962 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3963 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
3964 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
3965 static bool isMOVSLDUPMask(ArrayRef<int> Mask, EVT VT,
3966 const X86Subtarget *Subtarget) {
3967 if (!Subtarget->hasSSE3())
3970 unsigned NumElems = VT.getVectorNumElements();
3972 if ((VT.is128BitVector() && NumElems != 4) ||
3973 (VT.is256BitVector() && NumElems != 8))
3976 // "i" is the value the indexed mask element must have
3977 for (unsigned i = 0; i != NumElems; i += 2)
3978 if (!isUndefOrEqual(Mask[i], i) ||
3979 !isUndefOrEqual(Mask[i+1], i))
3985 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
3986 /// specifies a shuffle of elements that is suitable for input to 256-bit
3987 /// version of MOVDDUP.
3988 static bool isMOVDDUPYMask(ArrayRef<int> Mask, EVT VT, bool HasFp256) {
3989 if (!HasFp256 || !VT.is256BitVector())
3992 unsigned NumElts = VT.getVectorNumElements();
3996 for (unsigned i = 0; i != NumElts/2; ++i)
3997 if (!isUndefOrEqual(Mask[i], 0))
3999 for (unsigned i = NumElts/2; i != NumElts; ++i)
4000 if (!isUndefOrEqual(Mask[i], NumElts/2))
4005 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4006 /// specifies a shuffle of elements that is suitable for input to 128-bit
4007 /// version of MOVDDUP.
4008 static bool isMOVDDUPMask(ArrayRef<int> Mask, EVT VT) {
4009 if (!VT.is128BitVector())
4012 unsigned e = VT.getVectorNumElements() / 2;
4013 for (unsigned i = 0; i != e; ++i)
4014 if (!isUndefOrEqual(Mask[i], i))
4016 for (unsigned i = 0; i != e; ++i)
4017 if (!isUndefOrEqual(Mask[e+i], i))
4022 /// isVEXTRACTF128Index - Return true if the specified
4023 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
4024 /// suitable for input to VEXTRACTF128.
4025 bool X86::isVEXTRACTF128Index(SDNode *N) {
4026 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4029 // The index should be aligned on a 128-bit boundary.
4031 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4033 MVT VT = N->getValueType(0).getSimpleVT();
4034 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4035 bool Result = (Index * ElSize) % 128 == 0;
4040 /// isVINSERTF128Index - Return true if the specified INSERT_SUBVECTOR
4041 /// operand specifies a subvector insert that is suitable for input to
4043 bool X86::isVINSERTF128Index(SDNode *N) {
4044 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4047 // The index should be aligned on a 128-bit boundary.
4049 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4051 MVT VT = N->getValueType(0).getSimpleVT();
4052 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4053 bool Result = (Index * ElSize) % 128 == 0;
4058 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4059 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4060 /// Handles 128-bit and 256-bit.
4061 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
4062 MVT VT = N->getValueType(0).getSimpleVT();
4064 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4065 "Unsupported vector type for PSHUF/SHUFP");
4067 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
4068 // independently on 128-bit lanes.
4069 unsigned NumElts = VT.getVectorNumElements();
4070 unsigned NumLanes = VT.getSizeInBits()/128;
4071 unsigned NumLaneElts = NumElts/NumLanes;
4073 assert((NumLaneElts == 2 || NumLaneElts == 4) &&
4074 "Only supports 2 or 4 elements per lane");
4076 unsigned Shift = (NumLaneElts == 4) ? 1 : 0;
4078 for (unsigned i = 0; i != NumElts; ++i) {
4079 int Elt = N->getMaskElt(i);
4080 if (Elt < 0) continue;
4081 Elt &= NumLaneElts - 1;
4082 unsigned ShAmt = (i << Shift) % 8;
4083 Mask |= Elt << ShAmt;
4089 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4090 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4091 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4092 MVT VT = N->getValueType(0).getSimpleVT();
4094 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4095 "Unsupported vector type for PSHUFHW");
4097 unsigned NumElts = VT.getVectorNumElements();
4100 for (unsigned l = 0; l != NumElts; l += 8) {
4101 // 8 nodes per lane, but we only care about the last 4.
4102 for (unsigned i = 0; i < 4; ++i) {
4103 int Elt = N->getMaskElt(l+i+4);
4104 if (Elt < 0) continue;
4105 Elt &= 0x3; // only 2-bits.
4106 Mask |= Elt << (i * 2);
4113 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4114 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4115 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4116 MVT VT = N->getValueType(0).getSimpleVT();
4118 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4119 "Unsupported vector type for PSHUFHW");
4121 unsigned NumElts = VT.getVectorNumElements();
4124 for (unsigned l = 0; l != NumElts; l += 8) {
4125 // 8 nodes per lane, but we only care about the first 4.
4126 for (unsigned i = 0; i < 4; ++i) {
4127 int Elt = N->getMaskElt(l+i);
4128 if (Elt < 0) continue;
4129 Elt &= 0x3; // only 2-bits
4130 Mask |= Elt << (i * 2);
4137 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
4138 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
4139 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4140 MVT VT = SVOp->getValueType(0).getSimpleVT();
4141 unsigned EltSize = VT.getVectorElementType().getSizeInBits() >> 3;
4143 unsigned NumElts = VT.getVectorNumElements();
4144 unsigned NumLanes = VT.getSizeInBits()/128;
4145 unsigned NumLaneElts = NumElts/NumLanes;
4149 for (i = 0; i != NumElts; ++i) {
4150 Val = SVOp->getMaskElt(i);
4154 if (Val >= (int)NumElts)
4155 Val -= NumElts - NumLaneElts;
4157 assert(Val - i > 0 && "PALIGNR imm should be positive");
4158 return (Val - i) * EltSize;
4161 /// getExtractVEXTRACTF128Immediate - Return the appropriate immediate
4162 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4164 unsigned X86::getExtractVEXTRACTF128Immediate(SDNode *N) {
4165 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4166 llvm_unreachable("Illegal extract subvector for VEXTRACTF128");
4169 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4171 MVT VecVT = N->getOperand(0).getValueType().getSimpleVT();
4172 MVT ElVT = VecVT.getVectorElementType();
4174 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
4175 return Index / NumElemsPerChunk;
4178 /// getInsertVINSERTF128Immediate - Return the appropriate immediate
4179 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4181 unsigned X86::getInsertVINSERTF128Immediate(SDNode *N) {
4182 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4183 llvm_unreachable("Illegal insert subvector for VINSERTF128");
4186 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4188 MVT VecVT = N->getValueType(0).getSimpleVT();
4189 MVT ElVT = VecVT.getVectorElementType();
4191 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
4192 return Index / NumElemsPerChunk;
4195 /// getShuffleCLImmediate - Return the appropriate immediate to shuffle
4196 /// the specified VECTOR_SHUFFLE mask with VPERMQ and VPERMPD instructions.
4197 /// Handles 256-bit.
4198 static unsigned getShuffleCLImmediate(ShuffleVectorSDNode *N) {
4199 MVT VT = N->getValueType(0).getSimpleVT();
4201 unsigned NumElts = VT.getVectorNumElements();
4203 assert((VT.is256BitVector() && NumElts == 4) &&
4204 "Unsupported vector type for VPERMQ/VPERMPD");
4207 for (unsigned i = 0; i != NumElts; ++i) {
4208 int Elt = N->getMaskElt(i);
4211 Mask |= Elt << (i*2);
4216 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4218 bool X86::isZeroNode(SDValue Elt) {
4219 return ((isa<ConstantSDNode>(Elt) &&
4220 cast<ConstantSDNode>(Elt)->isNullValue()) ||
4221 (isa<ConstantFPSDNode>(Elt) &&
4222 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
4225 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
4226 /// their permute mask.
4227 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
4228 SelectionDAG &DAG) {
4229 MVT VT = SVOp->getValueType(0).getSimpleVT();
4230 unsigned NumElems = VT.getVectorNumElements();
4231 SmallVector<int, 8> MaskVec;
4233 for (unsigned i = 0; i != NumElems; ++i) {
4234 int Idx = SVOp->getMaskElt(i);
4236 if (Idx < (int)NumElems)
4241 MaskVec.push_back(Idx);
4243 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1),
4244 SVOp->getOperand(0), &MaskVec[0]);
4247 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4248 /// match movhlps. The lower half elements should come from upper half of
4249 /// V1 (and in order), and the upper half elements should come from the upper
4250 /// half of V2 (and in order).
4251 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, EVT VT) {
4252 if (!VT.is128BitVector())
4254 if (VT.getVectorNumElements() != 4)
4256 for (unsigned i = 0, e = 2; i != e; ++i)
4257 if (!isUndefOrEqual(Mask[i], i+2))
4259 for (unsigned i = 2; i != 4; ++i)
4260 if (!isUndefOrEqual(Mask[i], i+4))
4265 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4266 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4268 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
4269 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4271 N = N->getOperand(0).getNode();
4272 if (!ISD::isNON_EXTLoad(N))
4275 *LD = cast<LoadSDNode>(N);
4279 // Test whether the given value is a vector value which will be legalized
4281 static bool WillBeConstantPoolLoad(SDNode *N) {
4282 if (N->getOpcode() != ISD::BUILD_VECTOR)
4285 // Check for any non-constant elements.
4286 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4287 switch (N->getOperand(i).getNode()->getOpcode()) {
4289 case ISD::ConstantFP:
4296 // Vectors of all-zeros and all-ones are materialized with special
4297 // instructions rather than being loaded.
4298 return !ISD::isBuildVectorAllZeros(N) &&
4299 !ISD::isBuildVectorAllOnes(N);
4302 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
4303 /// match movlp{s|d}. The lower half elements should come from lower half of
4304 /// V1 (and in order), and the upper half elements should come from the upper
4305 /// half of V2 (and in order). And since V1 will become the source of the
4306 /// MOVLP, it must be either a vector load or a scalar load to vector.
4307 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
4308 ArrayRef<int> Mask, EVT VT) {
4309 if (!VT.is128BitVector())
4312 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
4314 // Is V2 is a vector load, don't do this transformation. We will try to use
4315 // load folding shufps op.
4316 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
4319 unsigned NumElems = VT.getVectorNumElements();
4321 if (NumElems != 2 && NumElems != 4)
4323 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4324 if (!isUndefOrEqual(Mask[i], i))
4326 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4327 if (!isUndefOrEqual(Mask[i], i+NumElems))
4332 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
4334 static bool isSplatVector(SDNode *N) {
4335 if (N->getOpcode() != ISD::BUILD_VECTOR)
4338 SDValue SplatValue = N->getOperand(0);
4339 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
4340 if (N->getOperand(i) != SplatValue)
4345 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
4346 /// to an zero vector.
4347 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
4348 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
4349 SDValue V1 = N->getOperand(0);
4350 SDValue V2 = N->getOperand(1);
4351 unsigned NumElems = N->getValueType(0).getVectorNumElements();
4352 for (unsigned i = 0; i != NumElems; ++i) {
4353 int Idx = N->getMaskElt(i);
4354 if (Idx >= (int)NumElems) {
4355 unsigned Opc = V2.getOpcode();
4356 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
4358 if (Opc != ISD::BUILD_VECTOR ||
4359 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
4361 } else if (Idx >= 0) {
4362 unsigned Opc = V1.getOpcode();
4363 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
4365 if (Opc != ISD::BUILD_VECTOR ||
4366 !X86::isZeroNode(V1.getOperand(Idx)))
4373 /// getZeroVector - Returns a vector of specified type with all zero elements.
4375 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4376 SelectionDAG &DAG, DebugLoc dl) {
4377 assert(VT.isVector() && "Expected a vector type");
4379 // Always build SSE zero vectors as <4 x i32> bitcasted
4380 // to their dest type. This ensures they get CSE'd.
4382 if (VT.is128BitVector()) { // SSE
4383 if (Subtarget->hasSSE2()) { // SSE2
4384 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4385 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4387 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4388 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4390 } else if (VT.is256BitVector()) { // AVX
4391 if (Subtarget->hasInt256()) { // AVX2
4392 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4393 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4394 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8);
4396 // 256-bit logic and arithmetic instructions in AVX are all
4397 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4398 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4399 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4400 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops, 8);
4403 llvm_unreachable("Unexpected vector type");
4405 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4408 /// getOnesVector - Returns a vector of specified type with all bits set.
4409 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4410 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4411 /// Then bitcast to their original type, ensuring they get CSE'd.
4412 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
4414 assert(VT.isVector() && "Expected a vector type");
4416 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
4418 if (VT.is256BitVector()) {
4419 if (HasInt256) { // AVX2
4420 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4421 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8);
4423 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4424 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4426 } else if (VT.is128BitVector()) {
4427 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4429 llvm_unreachable("Unexpected vector type");
4431 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4434 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
4435 /// that point to V2 points to its first element.
4436 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
4437 for (unsigned i = 0; i != NumElems; ++i) {
4438 if (Mask[i] > (int)NumElems) {
4444 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4445 /// operation of specified width.
4446 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4448 unsigned NumElems = VT.getVectorNumElements();
4449 SmallVector<int, 8> Mask;
4450 Mask.push_back(NumElems);
4451 for (unsigned i = 1; i != NumElems; ++i)
4453 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4456 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4457 static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4459 unsigned NumElems = VT.getVectorNumElements();
4460 SmallVector<int, 8> Mask;
4461 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4463 Mask.push_back(i + NumElems);
4465 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4468 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4469 static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4471 unsigned NumElems = VT.getVectorNumElements();
4472 SmallVector<int, 8> Mask;
4473 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
4474 Mask.push_back(i + Half);
4475 Mask.push_back(i + NumElems + Half);
4477 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4480 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
4481 // a generic shuffle instruction because the target has no such instructions.
4482 // Generate shuffles which repeat i16 and i8 several times until they can be
4483 // represented by v4f32 and then be manipulated by target suported shuffles.
4484 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
4485 EVT VT = V.getValueType();
4486 int NumElems = VT.getVectorNumElements();
4487 DebugLoc dl = V.getDebugLoc();
4489 while (NumElems > 4) {
4490 if (EltNo < NumElems/2) {
4491 V = getUnpackl(DAG, dl, VT, V, V);
4493 V = getUnpackh(DAG, dl, VT, V, V);
4494 EltNo -= NumElems/2;
4501 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
4502 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
4503 EVT VT = V.getValueType();
4504 DebugLoc dl = V.getDebugLoc();
4506 if (VT.is128BitVector()) {
4507 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
4508 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
4509 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
4511 } else if (VT.is256BitVector()) {
4512 // To use VPERMILPS to splat scalars, the second half of indicies must
4513 // refer to the higher part, which is a duplication of the lower one,
4514 // because VPERMILPS can only handle in-lane permutations.
4515 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
4516 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
4518 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
4519 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
4522 llvm_unreachable("Vector size not supported");
4524 return DAG.getNode(ISD::BITCAST, dl, VT, V);
4527 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
4528 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
4529 EVT SrcVT = SV->getValueType(0);
4530 SDValue V1 = SV->getOperand(0);
4531 DebugLoc dl = SV->getDebugLoc();
4533 int EltNo = SV->getSplatIndex();
4534 int NumElems = SrcVT.getVectorNumElements();
4535 bool Is256BitVec = SrcVT.is256BitVector();
4537 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) &&
4538 "Unknown how to promote splat for type");
4540 // Extract the 128-bit part containing the splat element and update
4541 // the splat element index when it refers to the higher register.
4543 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
4544 if (EltNo >= NumElems/2)
4545 EltNo -= NumElems/2;
4548 // All i16 and i8 vector types can't be used directly by a generic shuffle
4549 // instruction because the target has no such instruction. Generate shuffles
4550 // which repeat i16 and i8 several times until they fit in i32, and then can
4551 // be manipulated by target suported shuffles.
4552 EVT EltVT = SrcVT.getVectorElementType();
4553 if (EltVT == MVT::i8 || EltVT == MVT::i16)
4554 V1 = PromoteSplati8i16(V1, DAG, EltNo);
4556 // Recreate the 256-bit vector and place the same 128-bit vector
4557 // into the low and high part. This is necessary because we want
4558 // to use VPERM* to shuffle the vectors
4560 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
4563 return getLegalSplat(DAG, V1, EltNo);
4566 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
4567 /// vector of zero or undef vector. This produces a shuffle where the low
4568 /// element of V2 is swizzled into the zero/undef vector, landing at element
4569 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4570 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4572 const X86Subtarget *Subtarget,
4573 SelectionDAG &DAG) {
4574 EVT VT = V2.getValueType();
4576 ? getZeroVector(VT, Subtarget, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT);
4577 unsigned NumElems = VT.getVectorNumElements();
4578 SmallVector<int, 16> MaskVec;
4579 for (unsigned i = 0; i != NumElems; ++i)
4580 // If this is the insertion idx, put the low elt of V2 here.
4581 MaskVec.push_back(i == Idx ? NumElems : i);
4582 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]);
4585 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
4586 /// target specific opcode. Returns true if the Mask could be calculated.
4587 /// Sets IsUnary to true if only uses one source.
4588 static bool getTargetShuffleMask(SDNode *N, MVT VT,
4589 SmallVectorImpl<int> &Mask, bool &IsUnary) {
4590 unsigned NumElems = VT.getVectorNumElements();
4594 switch(N->getOpcode()) {
4596 ImmN = N->getOperand(N->getNumOperands()-1);
4597 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4599 case X86ISD::UNPCKH:
4600 DecodeUNPCKHMask(VT, Mask);
4602 case X86ISD::UNPCKL:
4603 DecodeUNPCKLMask(VT, Mask);
4605 case X86ISD::MOVHLPS:
4606 DecodeMOVHLPSMask(NumElems, Mask);
4608 case X86ISD::MOVLHPS:
4609 DecodeMOVLHPSMask(NumElems, Mask);
4611 case X86ISD::PALIGNR:
4612 ImmN = N->getOperand(N->getNumOperands()-1);
4613 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4615 case X86ISD::PSHUFD:
4616 case X86ISD::VPERMILP:
4617 ImmN = N->getOperand(N->getNumOperands()-1);
4618 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4621 case X86ISD::PSHUFHW:
4622 ImmN = N->getOperand(N->getNumOperands()-1);
4623 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4626 case X86ISD::PSHUFLW:
4627 ImmN = N->getOperand(N->getNumOperands()-1);
4628 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4631 case X86ISD::VPERMI:
4632 ImmN = N->getOperand(N->getNumOperands()-1);
4633 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4637 case X86ISD::MOVSD: {
4638 // The index 0 always comes from the first element of the second source,
4639 // this is why MOVSS and MOVSD are used in the first place. The other
4640 // elements come from the other positions of the first source vector
4641 Mask.push_back(NumElems);
4642 for (unsigned i = 1; i != NumElems; ++i) {
4647 case X86ISD::VPERM2X128:
4648 ImmN = N->getOperand(N->getNumOperands()-1);
4649 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4650 if (Mask.empty()) return false;
4652 case X86ISD::MOVDDUP:
4653 case X86ISD::MOVLHPD:
4654 case X86ISD::MOVLPD:
4655 case X86ISD::MOVLPS:
4656 case X86ISD::MOVSHDUP:
4657 case X86ISD::MOVSLDUP:
4658 // Not yet implemented
4660 default: llvm_unreachable("unknown target shuffle node");
4666 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
4667 /// element of the result of the vector shuffle.
4668 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
4671 return SDValue(); // Limit search depth.
4673 SDValue V = SDValue(N, 0);
4674 EVT VT = V.getValueType();
4675 unsigned Opcode = V.getOpcode();
4677 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4678 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4679 int Elt = SV->getMaskElt(Index);
4682 return DAG.getUNDEF(VT.getVectorElementType());
4684 unsigned NumElems = VT.getVectorNumElements();
4685 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
4686 : SV->getOperand(1);
4687 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
4690 // Recurse into target specific vector shuffles to find scalars.
4691 if (isTargetShuffle(Opcode)) {
4692 MVT ShufVT = V.getValueType().getSimpleVT();
4693 unsigned NumElems = ShufVT.getVectorNumElements();
4694 SmallVector<int, 16> ShuffleMask;
4697 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
4700 int Elt = ShuffleMask[Index];
4702 return DAG.getUNDEF(ShufVT.getVectorElementType());
4704 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
4706 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
4710 // Actual nodes that may contain scalar elements
4711 if (Opcode == ISD::BITCAST) {
4712 V = V.getOperand(0);
4713 EVT SrcVT = V.getValueType();
4714 unsigned NumElems = VT.getVectorNumElements();
4716 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
4720 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
4721 return (Index == 0) ? V.getOperand(0)
4722 : DAG.getUNDEF(VT.getVectorElementType());
4724 if (V.getOpcode() == ISD::BUILD_VECTOR)
4725 return V.getOperand(Index);
4730 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
4731 /// shuffle operation which come from a consecutively from a zero. The
4732 /// search can start in two different directions, from left or right.
4734 unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp, unsigned NumElems,
4735 bool ZerosFromLeft, SelectionDAG &DAG) {
4737 for (i = 0; i != NumElems; ++i) {
4738 unsigned Index = ZerosFromLeft ? i : NumElems-i-1;
4739 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
4740 if (!(Elt.getNode() &&
4741 (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt))))
4748 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
4749 /// correspond consecutively to elements from one of the vector operands,
4750 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
4752 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
4753 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
4754 unsigned NumElems, unsigned &OpNum) {
4755 bool SeenV1 = false;
4756 bool SeenV2 = false;
4758 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
4759 int Idx = SVOp->getMaskElt(i);
4760 // Ignore undef indicies
4764 if (Idx < (int)NumElems)
4769 // Only accept consecutive elements from the same vector
4770 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
4774 OpNum = SeenV1 ? 0 : 1;
4778 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
4779 /// logical left shift of a vector.
4780 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4781 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4782 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4783 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4784 false /* check zeros from right */, DAG);
4790 // Considering the elements in the mask that are not consecutive zeros,
4791 // check if they consecutively come from only one of the source vectors.
4793 // V1 = {X, A, B, C} 0
4795 // vector_shuffle V1, V2 <1, 2, 3, X>
4797 if (!isShuffleMaskConsecutive(SVOp,
4798 0, // Mask Start Index
4799 NumElems-NumZeros, // Mask End Index(exclusive)
4800 NumZeros, // Where to start looking in the src vector
4801 NumElems, // Number of elements in vector
4802 OpSrc)) // Which source operand ?
4807 ShVal = SVOp->getOperand(OpSrc);
4811 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
4812 /// logical left shift of a vector.
4813 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4814 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4815 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4816 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4817 true /* check zeros from left */, DAG);
4823 // Considering the elements in the mask that are not consecutive zeros,
4824 // check if they consecutively come from only one of the source vectors.
4826 // 0 { A, B, X, X } = V2
4828 // vector_shuffle V1, V2 <X, X, 4, 5>
4830 if (!isShuffleMaskConsecutive(SVOp,
4831 NumZeros, // Mask Start Index
4832 NumElems, // Mask End Index(exclusive)
4833 0, // Where to start looking in the src vector
4834 NumElems, // Number of elements in vector
4835 OpSrc)) // Which source operand ?
4840 ShVal = SVOp->getOperand(OpSrc);
4844 /// isVectorShift - Returns true if the shuffle can be implemented as a
4845 /// logical left or right shift of a vector.
4846 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4847 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4848 // Although the logic below support any bitwidth size, there are no
4849 // shift instructions which handle more than 128-bit vectors.
4850 if (!SVOp->getValueType(0).is128BitVector())
4853 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
4854 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
4860 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
4862 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
4863 unsigned NumNonZero, unsigned NumZero,
4865 const X86Subtarget* Subtarget,
4866 const TargetLowering &TLI) {
4870 DebugLoc dl = Op.getDebugLoc();
4873 for (unsigned i = 0; i < 16; ++i) {
4874 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
4875 if (ThisIsNonZero && First) {
4877 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4879 V = DAG.getUNDEF(MVT::v8i16);
4884 SDValue ThisElt(0, 0), LastElt(0, 0);
4885 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
4886 if (LastIsNonZero) {
4887 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
4888 MVT::i16, Op.getOperand(i-1));
4890 if (ThisIsNonZero) {
4891 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
4892 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
4893 ThisElt, DAG.getConstant(8, MVT::i8));
4895 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
4899 if (ThisElt.getNode())
4900 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
4901 DAG.getIntPtrConstant(i/2));
4905 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
4908 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
4910 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
4911 unsigned NumNonZero, unsigned NumZero,
4913 const X86Subtarget* Subtarget,
4914 const TargetLowering &TLI) {
4918 DebugLoc dl = Op.getDebugLoc();
4921 for (unsigned i = 0; i < 8; ++i) {
4922 bool isNonZero = (NonZeros & (1 << i)) != 0;
4926 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4928 V = DAG.getUNDEF(MVT::v8i16);
4931 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4932 MVT::v8i16, V, Op.getOperand(i),
4933 DAG.getIntPtrConstant(i));
4940 /// getVShift - Return a vector logical shift node.
4942 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
4943 unsigned NumBits, SelectionDAG &DAG,
4944 const TargetLowering &TLI, DebugLoc dl) {
4945 assert(VT.is128BitVector() && "Unknown type for VShift");
4946 EVT ShVT = MVT::v2i64;
4947 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
4948 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
4949 return DAG.getNode(ISD::BITCAST, dl, VT,
4950 DAG.getNode(Opc, dl, ShVT, SrcOp,
4951 DAG.getConstant(NumBits,
4952 TLI.getShiftAmountTy(SrcOp.getValueType()))));
4956 X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
4957 SelectionDAG &DAG) const {
4959 // Check if the scalar load can be widened into a vector load. And if
4960 // the address is "base + cst" see if the cst can be "absorbed" into
4961 // the shuffle mask.
4962 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
4963 SDValue Ptr = LD->getBasePtr();
4964 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
4966 EVT PVT = LD->getValueType(0);
4967 if (PVT != MVT::i32 && PVT != MVT::f32)
4972 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
4973 FI = FINode->getIndex();
4975 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
4976 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
4977 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
4978 Offset = Ptr.getConstantOperandVal(1);
4979 Ptr = Ptr.getOperand(0);
4984 // FIXME: 256-bit vector instructions don't require a strict alignment,
4985 // improve this code to support it better.
4986 unsigned RequiredAlign = VT.getSizeInBits()/8;
4987 SDValue Chain = LD->getChain();
4988 // Make sure the stack object alignment is at least 16 or 32.
4989 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4990 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
4991 if (MFI->isFixedObjectIndex(FI)) {
4992 // Can't change the alignment. FIXME: It's possible to compute
4993 // the exact stack offset and reference FI + adjust offset instead.
4994 // If someone *really* cares about this. That's the way to implement it.
4997 MFI->setObjectAlignment(FI, RequiredAlign);
5001 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5002 // Ptr + (Offset & ~15).
5005 if ((Offset % RequiredAlign) & 3)
5007 int64_t StartOffset = Offset & ~(RequiredAlign-1);
5009 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(),
5010 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
5012 int EltNo = (Offset - StartOffset) >> 2;
5013 unsigned NumElems = VT.getVectorNumElements();
5015 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5016 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5017 LD->getPointerInfo().getWithOffset(StartOffset),
5018 false, false, false, 0);
5020 SmallVector<int, 8> Mask;
5021 for (unsigned i = 0; i != NumElems; ++i)
5022 Mask.push_back(EltNo);
5024 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5030 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
5031 /// vector of type 'VT', see if the elements can be replaced by a single large
5032 /// load which has the same value as a build_vector whose operands are 'elts'.
5034 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5036 /// FIXME: we'd also like to handle the case where the last elements are zero
5037 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5038 /// There's even a handy isZeroNode for that purpose.
5039 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
5040 DebugLoc &DL, SelectionDAG &DAG) {
5041 EVT EltVT = VT.getVectorElementType();
5042 unsigned NumElems = Elts.size();
5044 LoadSDNode *LDBase = NULL;
5045 unsigned LastLoadedElt = -1U;
5047 // For each element in the initializer, see if we've found a load or an undef.
5048 // If we don't find an initial load element, or later load elements are
5049 // non-consecutive, bail out.
5050 for (unsigned i = 0; i < NumElems; ++i) {
5051 SDValue Elt = Elts[i];
5053 if (!Elt.getNode() ||
5054 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5057 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5059 LDBase = cast<LoadSDNode>(Elt.getNode());
5063 if (Elt.getOpcode() == ISD::UNDEF)
5066 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5067 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
5072 // If we have found an entire vector of loads and undefs, then return a large
5073 // load of the entire vector width starting at the base pointer. If we found
5074 // consecutive loads for the low half, generate a vzext_load node.
5075 if (LastLoadedElt == NumElems - 1) {
5076 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
5077 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5078 LDBase->getPointerInfo(),
5079 LDBase->isVolatile(), LDBase->isNonTemporal(),
5080 LDBase->isInvariant(), 0);
5081 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5082 LDBase->getPointerInfo(),
5083 LDBase->isVolatile(), LDBase->isNonTemporal(),
5084 LDBase->isInvariant(), LDBase->getAlignment());
5086 if (NumElems == 4 && LastLoadedElt == 1 &&
5087 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5088 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5089 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5091 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, 2, MVT::i64,
5092 LDBase->getPointerInfo(),
5093 LDBase->getAlignment(),
5094 false/*isVolatile*/, true/*ReadMem*/,
5097 // Make sure the newly-created LOAD is in the same position as LDBase in
5098 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5099 // update uses of LDBase's output chain to use the TokenFactor.
5100 if (LDBase->hasAnyUseOfValue(1)) {
5101 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5102 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5103 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5104 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5105 SDValue(ResNode.getNode(), 1));
5108 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
5113 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
5114 /// to generate a splat value for the following cases:
5115 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
5116 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
5117 /// a scalar load, or a constant.
5118 /// The VBROADCAST node is returned when a pattern is found,
5119 /// or SDValue() otherwise.
5121 X86TargetLowering::LowerVectorBroadcast(SDValue Op, SelectionDAG &DAG) const {
5122 if (!Subtarget->hasFp256())
5125 MVT VT = Op.getValueType().getSimpleVT();
5126 DebugLoc dl = Op.getDebugLoc();
5128 assert((VT.is128BitVector() || VT.is256BitVector()) &&
5129 "Unsupported vector type for broadcast.");
5134 switch (Op.getOpcode()) {
5136 // Unknown pattern found.
5139 case ISD::BUILD_VECTOR: {
5140 // The BUILD_VECTOR node must be a splat.
5141 if (!isSplatVector(Op.getNode()))
5144 Ld = Op.getOperand(0);
5145 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5146 Ld.getOpcode() == ISD::ConstantFP);
5148 // The suspected load node has several users. Make sure that all
5149 // of its users are from the BUILD_VECTOR node.
5150 // Constants may have multiple users.
5151 if (!ConstSplatVal && !Ld->hasNUsesOfValue(VT.getVectorNumElements(), 0))
5156 case ISD::VECTOR_SHUFFLE: {
5157 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5159 // Shuffles must have a splat mask where the first element is
5161 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
5164 SDValue Sc = Op.getOperand(0);
5165 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
5166 Sc.getOpcode() != ISD::BUILD_VECTOR) {
5168 if (!Subtarget->hasInt256())
5171 // Use the register form of the broadcast instruction available on AVX2.
5172 if (VT.is256BitVector())
5173 Sc = Extract128BitVector(Sc, 0, DAG, dl);
5174 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
5177 Ld = Sc.getOperand(0);
5178 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5179 Ld.getOpcode() == ISD::ConstantFP);
5181 // The scalar_to_vector node and the suspected
5182 // load node must have exactly one user.
5183 // Constants may have multiple users.
5184 if (!ConstSplatVal && (!Sc.hasOneUse() || !Ld.hasOneUse()))
5190 bool Is256 = VT.is256BitVector();
5192 // Handle the broadcasting a single constant scalar from the constant pool
5193 // into a vector. On Sandybridge it is still better to load a constant vector
5194 // from the constant pool and not to broadcast it from a scalar.
5195 if (ConstSplatVal && Subtarget->hasInt256()) {
5196 EVT CVT = Ld.getValueType();
5197 assert(!CVT.isVector() && "Must not broadcast a vector type");
5198 unsigned ScalarSize = CVT.getSizeInBits();
5200 if (ScalarSize == 32 || (Is256 && ScalarSize == 64)) {
5201 const Constant *C = 0;
5202 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
5203 C = CI->getConstantIntValue();
5204 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
5205 C = CF->getConstantFPValue();
5207 assert(C && "Invalid constant type");
5209 SDValue CP = DAG.getConstantPool(C, getPointerTy());
5210 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
5211 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
5212 MachinePointerInfo::getConstantPool(),
5213 false, false, false, Alignment);
5215 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5219 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
5220 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5222 // Handle AVX2 in-register broadcasts.
5223 if (!IsLoad && Subtarget->hasInt256() &&
5224 (ScalarSize == 32 || (Is256 && ScalarSize == 64)))
5225 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5227 // The scalar source must be a normal load.
5231 if (ScalarSize == 32 || (Is256 && ScalarSize == 64))
5232 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5234 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5235 // double since there is no vbroadcastsd xmm
5236 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
5237 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
5238 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5241 // Unsupported broadcast.
5246 X86TargetLowering::buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) const {
5247 EVT VT = Op.getValueType();
5249 // Skip if insert_vec_elt is not supported.
5250 if (!isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
5253 DebugLoc DL = Op.getDebugLoc();
5254 unsigned NumElems = Op.getNumOperands();
5258 SmallVector<unsigned, 4> InsertIndices;
5259 SmallVector<int, 8> Mask(NumElems, -1);
5261 for (unsigned i = 0; i != NumElems; ++i) {
5262 unsigned Opc = Op.getOperand(i).getOpcode();
5264 if (Opc == ISD::UNDEF)
5267 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
5268 // Quit if more than 1 elements need inserting.
5269 if (InsertIndices.size() > 1)
5272 InsertIndices.push_back(i);
5276 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
5277 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
5279 // Quit if extracted from vector of different type.
5280 if (ExtractedFromVec.getValueType() != VT)
5283 // Quit if non-constant index.
5284 if (!isa<ConstantSDNode>(ExtIdx))
5287 if (VecIn1.getNode() == 0)
5288 VecIn1 = ExtractedFromVec;
5289 else if (VecIn1 != ExtractedFromVec) {
5290 if (VecIn2.getNode() == 0)
5291 VecIn2 = ExtractedFromVec;
5292 else if (VecIn2 != ExtractedFromVec)
5293 // Quit if more than 2 vectors to shuffle
5297 unsigned Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
5299 if (ExtractedFromVec == VecIn1)
5301 else if (ExtractedFromVec == VecIn2)
5302 Mask[i] = Idx + NumElems;
5305 if (VecIn1.getNode() == 0)
5308 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
5309 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
5310 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
5311 unsigned Idx = InsertIndices[i];
5312 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
5313 DAG.getIntPtrConstant(Idx));
5320 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
5321 DebugLoc dl = Op.getDebugLoc();
5323 MVT VT = Op.getValueType().getSimpleVT();
5324 MVT ExtVT = VT.getVectorElementType();
5325 unsigned NumElems = Op.getNumOperands();
5327 // Vectors containing all zeros can be matched by pxor and xorps later
5328 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5329 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
5330 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
5331 if (VT == MVT::v4i32 || VT == MVT::v8i32)
5334 return getZeroVector(VT, Subtarget, DAG, dl);
5337 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
5338 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
5339 // vpcmpeqd on 256-bit vectors.
5340 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5341 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
5344 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
5347 SDValue Broadcast = LowerVectorBroadcast(Op, DAG);
5348 if (Broadcast.getNode())
5351 unsigned EVTBits = ExtVT.getSizeInBits();
5353 unsigned NumZero = 0;
5354 unsigned NumNonZero = 0;
5355 unsigned NonZeros = 0;
5356 bool IsAllConstants = true;
5357 SmallSet<SDValue, 8> Values;
5358 for (unsigned i = 0; i < NumElems; ++i) {
5359 SDValue Elt = Op.getOperand(i);
5360 if (Elt.getOpcode() == ISD::UNDEF)
5363 if (Elt.getOpcode() != ISD::Constant &&
5364 Elt.getOpcode() != ISD::ConstantFP)
5365 IsAllConstants = false;
5366 if (X86::isZeroNode(Elt))
5369 NonZeros |= (1 << i);
5374 // All undef vector. Return an UNDEF. All zero vectors were handled above.
5375 if (NumNonZero == 0)
5376 return DAG.getUNDEF(VT);
5378 // Special case for single non-zero, non-undef, element.
5379 if (NumNonZero == 1) {
5380 unsigned Idx = CountTrailingZeros_32(NonZeros);
5381 SDValue Item = Op.getOperand(Idx);
5383 // If this is an insertion of an i64 value on x86-32, and if the top bits of
5384 // the value are obviously zero, truncate the value to i32 and do the
5385 // insertion that way. Only do this if the value is non-constant or if the
5386 // value is a constant being inserted into element 0. It is cheaper to do
5387 // a constant pool load than it is to do a movd + shuffle.
5388 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
5389 (!IsAllConstants || Idx == 0)) {
5390 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
5392 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
5393 EVT VecVT = MVT::v4i32;
5394 unsigned VecElts = 4;
5396 // Truncate the value (which may itself be a constant) to i32, and
5397 // convert it to a vector with movd (S2V+shuffle to zero extend).
5398 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
5399 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
5400 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5402 // Now we have our 32-bit value zero extended in the low element of
5403 // a vector. If Idx != 0, swizzle it into place.
5405 SmallVector<int, 4> Mask;
5406 Mask.push_back(Idx);
5407 for (unsigned i = 1; i != VecElts; ++i)
5409 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
5412 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5416 // If we have a constant or non-constant insertion into the low element of
5417 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
5418 // the rest of the elements. This will be matched as movd/movq/movss/movsd
5419 // depending on what the source datatype is.
5422 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5424 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
5425 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
5426 if (VT.is256BitVector()) {
5427 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
5428 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
5429 Item, DAG.getIntPtrConstant(0));
5431 assert(VT.is128BitVector() && "Expected an SSE value type!");
5432 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5433 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
5434 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5437 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
5438 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
5439 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5440 if (VT.is256BitVector()) {
5441 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
5442 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
5444 assert(VT.is128BitVector() && "Expected an SSE value type!");
5445 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5447 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5451 // Is it a vector logical left shift?
5452 if (NumElems == 2 && Idx == 1 &&
5453 X86::isZeroNode(Op.getOperand(0)) &&
5454 !X86::isZeroNode(Op.getOperand(1))) {
5455 unsigned NumBits = VT.getSizeInBits();
5456 return getVShift(true, VT,
5457 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5458 VT, Op.getOperand(1)),
5459 NumBits/2, DAG, *this, dl);
5462 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
5465 // Otherwise, if this is a vector with i32 or f32 elements, and the element
5466 // is a non-constant being inserted into an element other than the low one,
5467 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
5468 // movd/movss) to move this into the low element, then shuffle it into
5470 if (EVTBits == 32) {
5471 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5473 // Turn it into a shuffle of zero and zero-extended scalar to vector.
5474 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
5475 SmallVector<int, 8> MaskVec;
5476 for (unsigned i = 0; i != NumElems; ++i)
5477 MaskVec.push_back(i == Idx ? 0 : 1);
5478 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
5482 // Splat is obviously ok. Let legalizer expand it to a shuffle.
5483 if (Values.size() == 1) {
5484 if (EVTBits == 32) {
5485 // Instead of a shuffle like this:
5486 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
5487 // Check if it's possible to issue this instead.
5488 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
5489 unsigned Idx = CountTrailingZeros_32(NonZeros);
5490 SDValue Item = Op.getOperand(Idx);
5491 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
5492 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
5497 // A vector full of immediates; various special cases are already
5498 // handled, so this is best done with a single constant-pool load.
5502 // For AVX-length vectors, build the individual 128-bit pieces and use
5503 // shuffles to put them in place.
5504 if (VT.is256BitVector()) {
5505 SmallVector<SDValue, 32> V;
5506 for (unsigned i = 0; i != NumElems; ++i)
5507 V.push_back(Op.getOperand(i));
5509 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
5511 // Build both the lower and upper subvector.
5512 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2);
5513 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2],
5516 // Recreate the wider vector with the lower and upper part.
5517 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
5520 // Let legalizer expand 2-wide build_vectors.
5521 if (EVTBits == 64) {
5522 if (NumNonZero == 1) {
5523 // One half is zero or undef.
5524 unsigned Idx = CountTrailingZeros_32(NonZeros);
5525 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
5526 Op.getOperand(Idx));
5527 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
5532 // If element VT is < 32 bits, convert it to inserts into a zero vector.
5533 if (EVTBits == 8 && NumElems == 16) {
5534 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
5536 if (V.getNode()) return V;
5539 if (EVTBits == 16 && NumElems == 8) {
5540 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
5542 if (V.getNode()) return V;
5545 // If element VT is == 32 bits, turn it into a number of shuffles.
5546 SmallVector<SDValue, 8> V(NumElems);
5547 if (NumElems == 4 && NumZero > 0) {
5548 for (unsigned i = 0; i < 4; ++i) {
5549 bool isZero = !(NonZeros & (1 << i));
5551 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
5553 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5556 for (unsigned i = 0; i < 2; ++i) {
5557 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
5560 V[i] = V[i*2]; // Must be a zero vector.
5563 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
5566 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
5569 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
5574 bool Reverse1 = (NonZeros & 0x3) == 2;
5575 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
5579 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
5580 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
5582 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
5585 if (Values.size() > 1 && VT.is128BitVector()) {
5586 // Check for a build vector of consecutive loads.
5587 for (unsigned i = 0; i < NumElems; ++i)
5588 V[i] = Op.getOperand(i);
5590 // Check for elements which are consecutive loads.
5591 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG);
5595 // Check for a build vector from mostly shuffle plus few inserting.
5596 SDValue Sh = buildFromShuffleMostly(Op, DAG);
5600 // For SSE 4.1, use insertps to put the high elements into the low element.
5601 if (getSubtarget()->hasSSE41()) {
5603 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
5604 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
5606 Result = DAG.getUNDEF(VT);
5608 for (unsigned i = 1; i < NumElems; ++i) {
5609 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
5610 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
5611 Op.getOperand(i), DAG.getIntPtrConstant(i));
5616 // Otherwise, expand into a number of unpckl*, start by extending each of
5617 // our (non-undef) elements to the full vector width with the element in the
5618 // bottom slot of the vector (which generates no code for SSE).
5619 for (unsigned i = 0; i < NumElems; ++i) {
5620 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
5621 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5623 V[i] = DAG.getUNDEF(VT);
5626 // Next, we iteratively mix elements, e.g. for v4f32:
5627 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
5628 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
5629 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
5630 unsigned EltStride = NumElems >> 1;
5631 while (EltStride != 0) {
5632 for (unsigned i = 0; i < EltStride; ++i) {
5633 // If V[i+EltStride] is undef and this is the first round of mixing,
5634 // then it is safe to just drop this shuffle: V[i] is already in the
5635 // right place, the one element (since it's the first round) being
5636 // inserted as undef can be dropped. This isn't safe for successive
5637 // rounds because they will permute elements within both vectors.
5638 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
5639 EltStride == NumElems/2)
5642 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
5651 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
5652 // to create 256-bit vectors from two other 128-bit ones.
5653 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5654 DebugLoc dl = Op.getDebugLoc();
5655 MVT ResVT = Op.getValueType().getSimpleVT();
5657 assert(ResVT.is256BitVector() && "Value type must be 256-bit wide");
5659 SDValue V1 = Op.getOperand(0);
5660 SDValue V2 = Op.getOperand(1);
5661 unsigned NumElems = ResVT.getVectorNumElements();
5663 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
5666 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5667 assert(Op.getNumOperands() == 2);
5669 // 256-bit AVX can use the vinsertf128 instruction to create 256-bit vectors
5670 // from two other 128-bit ones.
5671 return LowerAVXCONCAT_VECTORS(Op, DAG);
5674 // Try to lower a shuffle node into a simple blend instruction.
5676 LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
5677 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
5678 SDValue V1 = SVOp->getOperand(0);
5679 SDValue V2 = SVOp->getOperand(1);
5680 DebugLoc dl = SVOp->getDebugLoc();
5681 MVT VT = SVOp->getValueType(0).getSimpleVT();
5682 MVT EltVT = VT.getVectorElementType();
5683 unsigned NumElems = VT.getVectorNumElements();
5685 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
5687 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
5690 // Check the mask for BLEND and build the value.
5691 unsigned MaskValue = 0;
5692 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
5693 unsigned NumLanes = (NumElems-1)/8 + 1;
5694 unsigned NumElemsInLane = NumElems / NumLanes;
5696 // Blend for v16i16 should be symetric for the both lanes.
5697 for (unsigned i = 0; i < NumElemsInLane; ++i) {
5699 int SndLaneEltIdx = (NumLanes == 2) ?
5700 SVOp->getMaskElt(i + NumElemsInLane) : -1;
5701 int EltIdx = SVOp->getMaskElt(i);
5703 if ((EltIdx < 0 || EltIdx == (int)i) &&
5704 (SndLaneEltIdx < 0 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
5707 if (((unsigned)EltIdx == (i + NumElems)) &&
5708 (SndLaneEltIdx < 0 ||
5709 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
5710 MaskValue |= (1<<i);
5715 // Convert i32 vectors to floating point if it is not AVX2.
5716 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
5718 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
5719 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
5721 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
5722 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
5725 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
5726 DAG.getConstant(MaskValue, MVT::i32));
5727 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
5730 // v8i16 shuffles - Prefer shuffles in the following order:
5731 // 1. [all] pshuflw, pshufhw, optional move
5732 // 2. [ssse3] 1 x pshufb
5733 // 3. [ssse3] 2 x pshufb + 1 x por
5734 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
5736 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
5737 SelectionDAG &DAG) {
5738 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5739 SDValue V1 = SVOp->getOperand(0);
5740 SDValue V2 = SVOp->getOperand(1);
5741 DebugLoc dl = SVOp->getDebugLoc();
5742 SmallVector<int, 8> MaskVals;
5744 // Determine if more than 1 of the words in each of the low and high quadwords
5745 // of the result come from the same quadword of one of the two inputs. Undef
5746 // mask values count as coming from any quadword, for better codegen.
5747 unsigned LoQuad[] = { 0, 0, 0, 0 };
5748 unsigned HiQuad[] = { 0, 0, 0, 0 };
5749 std::bitset<4> InputQuads;
5750 for (unsigned i = 0; i < 8; ++i) {
5751 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
5752 int EltIdx = SVOp->getMaskElt(i);
5753 MaskVals.push_back(EltIdx);
5762 InputQuads.set(EltIdx / 4);
5765 int BestLoQuad = -1;
5766 unsigned MaxQuad = 1;
5767 for (unsigned i = 0; i < 4; ++i) {
5768 if (LoQuad[i] > MaxQuad) {
5770 MaxQuad = LoQuad[i];
5774 int BestHiQuad = -1;
5776 for (unsigned i = 0; i < 4; ++i) {
5777 if (HiQuad[i] > MaxQuad) {
5779 MaxQuad = HiQuad[i];
5783 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
5784 // of the two input vectors, shuffle them into one input vector so only a
5785 // single pshufb instruction is necessary. If There are more than 2 input
5786 // quads, disable the next transformation since it does not help SSSE3.
5787 bool V1Used = InputQuads[0] || InputQuads[1];
5788 bool V2Used = InputQuads[2] || InputQuads[3];
5789 if (Subtarget->hasSSSE3()) {
5790 if (InputQuads.count() == 2 && V1Used && V2Used) {
5791 BestLoQuad = InputQuads[0] ? 0 : 1;
5792 BestHiQuad = InputQuads[2] ? 2 : 3;
5794 if (InputQuads.count() > 2) {
5800 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
5801 // the shuffle mask. If a quad is scored as -1, that means that it contains
5802 // words from all 4 input quadwords.
5804 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
5806 BestLoQuad < 0 ? 0 : BestLoQuad,
5807 BestHiQuad < 0 ? 1 : BestHiQuad
5809 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
5810 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
5811 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
5812 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
5814 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
5815 // source words for the shuffle, to aid later transformations.
5816 bool AllWordsInNewV = true;
5817 bool InOrder[2] = { true, true };
5818 for (unsigned i = 0; i != 8; ++i) {
5819 int idx = MaskVals[i];
5821 InOrder[i/4] = false;
5822 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
5824 AllWordsInNewV = false;
5828 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
5829 if (AllWordsInNewV) {
5830 for (int i = 0; i != 8; ++i) {
5831 int idx = MaskVals[i];
5834 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
5835 if ((idx != i) && idx < 4)
5837 if ((idx != i) && idx > 3)
5846 // If we've eliminated the use of V2, and the new mask is a pshuflw or
5847 // pshufhw, that's as cheap as it gets. Return the new shuffle.
5848 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
5849 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
5850 unsigned TargetMask = 0;
5851 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
5852 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
5853 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
5854 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
5855 getShufflePSHUFLWImmediate(SVOp);
5856 V1 = NewV.getOperand(0);
5857 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
5861 // Promote splats to a larger type which usually leads to more efficient code.
5862 // FIXME: Is this true if pshufb is available?
5863 if (SVOp->isSplat())
5864 return PromoteSplat(SVOp, DAG);
5866 // If we have SSSE3, and all words of the result are from 1 input vector,
5867 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
5868 // is present, fall back to case 4.
5869 if (Subtarget->hasSSSE3()) {
5870 SmallVector<SDValue,16> pshufbMask;
5872 // If we have elements from both input vectors, set the high bit of the
5873 // shuffle mask element to zero out elements that come from V2 in the V1
5874 // mask, and elements that come from V1 in the V2 mask, so that the two
5875 // results can be OR'd together.
5876 bool TwoInputs = V1Used && V2Used;
5877 for (unsigned i = 0; i != 8; ++i) {
5878 int EltIdx = MaskVals[i] * 2;
5879 int Idx0 = (TwoInputs && (EltIdx >= 16)) ? 0x80 : EltIdx;
5880 int Idx1 = (TwoInputs && (EltIdx >= 16)) ? 0x80 : EltIdx+1;
5881 pshufbMask.push_back(DAG.getConstant(Idx0, MVT::i8));
5882 pshufbMask.push_back(DAG.getConstant(Idx1, MVT::i8));
5884 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1);
5885 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5886 DAG.getNode(ISD::BUILD_VECTOR, dl,
5887 MVT::v16i8, &pshufbMask[0], 16));
5889 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5891 // Calculate the shuffle mask for the second input, shuffle it, and
5892 // OR it with the first shuffled input.
5894 for (unsigned i = 0; i != 8; ++i) {
5895 int EltIdx = MaskVals[i] * 2;
5896 int Idx0 = (EltIdx < 16) ? 0x80 : EltIdx - 16;
5897 int Idx1 = (EltIdx < 16) ? 0x80 : EltIdx - 15;
5898 pshufbMask.push_back(DAG.getConstant(Idx0, MVT::i8));
5899 pshufbMask.push_back(DAG.getConstant(Idx1, MVT::i8));
5901 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2);
5902 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
5903 DAG.getNode(ISD::BUILD_VECTOR, dl,
5904 MVT::v16i8, &pshufbMask[0], 16));
5905 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5906 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5909 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
5910 // and update MaskVals with new element order.
5911 std::bitset<8> InOrder;
5912 if (BestLoQuad >= 0) {
5913 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
5914 for (int i = 0; i != 4; ++i) {
5915 int idx = MaskVals[i];
5918 } else if ((idx / 4) == BestLoQuad) {
5923 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5926 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
5927 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
5928 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
5930 getShufflePSHUFLWImmediate(SVOp), DAG);
5934 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
5935 // and update MaskVals with the new element order.
5936 if (BestHiQuad >= 0) {
5937 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
5938 for (unsigned i = 4; i != 8; ++i) {
5939 int idx = MaskVals[i];
5942 } else if ((idx / 4) == BestHiQuad) {
5943 MaskV[i] = (idx & 3) + 4;
5947 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5950 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
5951 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
5952 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
5954 getShufflePSHUFHWImmediate(SVOp), DAG);
5958 // In case BestHi & BestLo were both -1, which means each quadword has a word
5959 // from each of the four input quadwords, calculate the InOrder bitvector now
5960 // before falling through to the insert/extract cleanup.
5961 if (BestLoQuad == -1 && BestHiQuad == -1) {
5963 for (int i = 0; i != 8; ++i)
5964 if (MaskVals[i] < 0 || MaskVals[i] == i)
5968 // The other elements are put in the right place using pextrw and pinsrw.
5969 for (unsigned i = 0; i != 8; ++i) {
5972 int EltIdx = MaskVals[i];
5975 SDValue ExtOp = (EltIdx < 8) ?
5976 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
5977 DAG.getIntPtrConstant(EltIdx)) :
5978 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
5979 DAG.getIntPtrConstant(EltIdx - 8));
5980 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
5981 DAG.getIntPtrConstant(i));
5986 // v16i8 shuffles - Prefer shuffles in the following order:
5987 // 1. [ssse3] 1 x pshufb
5988 // 2. [ssse3] 2 x pshufb + 1 x por
5989 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
5991 SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
5993 const X86TargetLowering &TLI) {
5994 SDValue V1 = SVOp->getOperand(0);
5995 SDValue V2 = SVOp->getOperand(1);
5996 DebugLoc dl = SVOp->getDebugLoc();
5997 ArrayRef<int> MaskVals = SVOp->getMask();
5999 // Promote splats to a larger type which usually leads to more efficient code.
6000 // FIXME: Is this true if pshufb is available?
6001 if (SVOp->isSplat())
6002 return PromoteSplat(SVOp, DAG);
6004 // If we have SSSE3, case 1 is generated when all result bytes come from
6005 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
6006 // present, fall back to case 3.
6008 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
6009 if (TLI.getSubtarget()->hasSSSE3()) {
6010 SmallVector<SDValue,16> pshufbMask;
6012 // If all result elements are from one input vector, then only translate
6013 // undef mask values to 0x80 (zero out result) in the pshufb mask.
6015 // Otherwise, we have elements from both input vectors, and must zero out
6016 // elements that come from V2 in the first mask, and V1 in the second mask
6017 // so that we can OR them together.
6018 for (unsigned i = 0; i != 16; ++i) {
6019 int EltIdx = MaskVals[i];
6020 if (EltIdx < 0 || EltIdx >= 16)
6022 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
6024 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
6025 DAG.getNode(ISD::BUILD_VECTOR, dl,
6026 MVT::v16i8, &pshufbMask[0], 16));
6028 // As PSHUFB will zero elements with negative indices, it's safe to ignore
6029 // the 2nd operand if it's undefined or zero.
6030 if (V2.getOpcode() == ISD::UNDEF ||
6031 ISD::isBuildVectorAllZeros(V2.getNode()))
6034 // Calculate the shuffle mask for the second input, shuffle it, and
6035 // OR it with the first shuffled input.
6037 for (unsigned i = 0; i != 16; ++i) {
6038 int EltIdx = MaskVals[i];
6039 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
6040 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
6042 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
6043 DAG.getNode(ISD::BUILD_VECTOR, dl,
6044 MVT::v16i8, &pshufbMask[0], 16));
6045 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
6048 // No SSSE3 - Calculate in place words and then fix all out of place words
6049 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
6050 // the 16 different words that comprise the two doublequadword input vectors.
6051 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
6052 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
6054 for (int i = 0; i != 8; ++i) {
6055 int Elt0 = MaskVals[i*2];
6056 int Elt1 = MaskVals[i*2+1];
6058 // This word of the result is all undef, skip it.
6059 if (Elt0 < 0 && Elt1 < 0)
6062 // This word of the result is already in the correct place, skip it.
6063 if ((Elt0 == i*2) && (Elt1 == i*2+1))
6066 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
6067 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
6070 // If Elt0 and Elt1 are defined, are consecutive, and can be load
6071 // using a single extract together, load it and store it.
6072 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
6073 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
6074 DAG.getIntPtrConstant(Elt1 / 2));
6075 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
6076 DAG.getIntPtrConstant(i));
6080 // If Elt1 is defined, extract it from the appropriate source. If the
6081 // source byte is not also odd, shift the extracted word left 8 bits
6082 // otherwise clear the bottom 8 bits if we need to do an or.
6084 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
6085 DAG.getIntPtrConstant(Elt1 / 2));
6086 if ((Elt1 & 1) == 0)
6087 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
6089 TLI.getShiftAmountTy(InsElt.getValueType())));
6091 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
6092 DAG.getConstant(0xFF00, MVT::i16));
6094 // If Elt0 is defined, extract it from the appropriate source. If the
6095 // source byte is not also even, shift the extracted word right 8 bits. If
6096 // Elt1 was also defined, OR the extracted values together before
6097 // inserting them in the result.
6099 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
6100 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
6101 if ((Elt0 & 1) != 0)
6102 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
6104 TLI.getShiftAmountTy(InsElt0.getValueType())));
6106 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
6107 DAG.getConstant(0x00FF, MVT::i16));
6108 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
6111 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
6112 DAG.getIntPtrConstant(i));
6114 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
6117 // v32i8 shuffles - Translate to VPSHUFB if possible.
6119 SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
6120 const X86Subtarget *Subtarget,
6121 SelectionDAG &DAG) {
6122 MVT VT = SVOp->getValueType(0).getSimpleVT();
6123 SDValue V1 = SVOp->getOperand(0);
6124 SDValue V2 = SVOp->getOperand(1);
6125 DebugLoc dl = SVOp->getDebugLoc();
6126 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
6128 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
6129 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
6130 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
6132 // VPSHUFB may be generated if
6133 // (1) one of input vector is undefined or zeroinitializer.
6134 // The mask value 0x80 puts 0 in the corresponding slot of the vector.
6135 // And (2) the mask indexes don't cross the 128-bit lane.
6136 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
6137 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
6140 if (V1IsAllZero && !V2IsAllZero) {
6141 CommuteVectorShuffleMask(MaskVals, 32);
6144 SmallVector<SDValue, 32> pshufbMask;
6145 for (unsigned i = 0; i != 32; i++) {
6146 int EltIdx = MaskVals[i];
6147 if (EltIdx < 0 || EltIdx >= 32)
6150 if ((EltIdx >= 16 && i < 16) || (EltIdx < 16 && i >= 16))
6151 // Cross lane is not allowed.
6155 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
6157 return DAG.getNode(X86ISD::PSHUFB, dl, MVT::v32i8, V1,
6158 DAG.getNode(ISD::BUILD_VECTOR, dl,
6159 MVT::v32i8, &pshufbMask[0], 32));
6162 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
6163 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
6164 /// done when every pair / quad of shuffle mask elements point to elements in
6165 /// the right sequence. e.g.
6166 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
6168 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
6169 SelectionDAG &DAG) {
6170 MVT VT = SVOp->getValueType(0).getSimpleVT();
6171 DebugLoc dl = SVOp->getDebugLoc();
6172 unsigned NumElems = VT.getVectorNumElements();
6175 switch (VT.SimpleTy) {
6176 default: llvm_unreachable("Unexpected!");
6177 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
6178 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
6179 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
6180 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
6181 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
6182 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
6185 SmallVector<int, 8> MaskVec;
6186 for (unsigned i = 0; i != NumElems; i += Scale) {
6188 for (unsigned j = 0; j != Scale; ++j) {
6189 int EltIdx = SVOp->getMaskElt(i+j);
6193 StartIdx = (EltIdx / Scale);
6194 if (EltIdx != (int)(StartIdx*Scale + j))
6197 MaskVec.push_back(StartIdx);
6200 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
6201 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
6202 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
6205 /// getVZextMovL - Return a zero-extending vector move low node.
6207 static SDValue getVZextMovL(MVT VT, EVT OpVT,
6208 SDValue SrcOp, SelectionDAG &DAG,
6209 const X86Subtarget *Subtarget, DebugLoc dl) {
6210 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
6211 LoadSDNode *LD = NULL;
6212 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
6213 LD = dyn_cast<LoadSDNode>(SrcOp);
6215 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
6217 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
6218 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
6219 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
6220 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
6221 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
6223 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
6224 return DAG.getNode(ISD::BITCAST, dl, VT,
6225 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
6226 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6234 return DAG.getNode(ISD::BITCAST, dl, VT,
6235 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
6236 DAG.getNode(ISD::BITCAST, dl,
6240 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
6241 /// which could not be matched by any known target speficic shuffle
6243 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
6245 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
6246 if (NewOp.getNode())
6249 MVT VT = SVOp->getValueType(0).getSimpleVT();
6251 unsigned NumElems = VT.getVectorNumElements();
6252 unsigned NumLaneElems = NumElems / 2;
6254 DebugLoc dl = SVOp->getDebugLoc();
6255 MVT EltVT = VT.getVectorElementType();
6256 MVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
6259 SmallVector<int, 16> Mask;
6260 for (unsigned l = 0; l < 2; ++l) {
6261 // Build a shuffle mask for the output, discovering on the fly which
6262 // input vectors to use as shuffle operands (recorded in InputUsed).
6263 // If building a suitable shuffle vector proves too hard, then bail
6264 // out with UseBuildVector set.
6265 bool UseBuildVector = false;
6266 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
6267 unsigned LaneStart = l * NumLaneElems;
6268 for (unsigned i = 0; i != NumLaneElems; ++i) {
6269 // The mask element. This indexes into the input.
6270 int Idx = SVOp->getMaskElt(i+LaneStart);
6272 // the mask element does not index into any input vector.
6277 // The input vector this mask element indexes into.
6278 int Input = Idx / NumLaneElems;
6280 // Turn the index into an offset from the start of the input vector.
6281 Idx -= Input * NumLaneElems;
6283 // Find or create a shuffle vector operand to hold this input.
6285 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
6286 if (InputUsed[OpNo] == Input)
6287 // This input vector is already an operand.
6289 if (InputUsed[OpNo] < 0) {
6290 // Create a new operand for this input vector.
6291 InputUsed[OpNo] = Input;
6296 if (OpNo >= array_lengthof(InputUsed)) {
6297 // More than two input vectors used! Give up on trying to create a
6298 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
6299 UseBuildVector = true;
6303 // Add the mask index for the new shuffle vector.
6304 Mask.push_back(Idx + OpNo * NumLaneElems);
6307 if (UseBuildVector) {
6308 SmallVector<SDValue, 16> SVOps;
6309 for (unsigned i = 0; i != NumLaneElems; ++i) {
6310 // The mask element. This indexes into the input.
6311 int Idx = SVOp->getMaskElt(i+LaneStart);
6313 SVOps.push_back(DAG.getUNDEF(EltVT));
6317 // The input vector this mask element indexes into.
6318 int Input = Idx / NumElems;
6320 // Turn the index into an offset from the start of the input vector.
6321 Idx -= Input * NumElems;
6323 // Extract the vector element by hand.
6324 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
6325 SVOp->getOperand(Input),
6326 DAG.getIntPtrConstant(Idx)));
6329 // Construct the output using a BUILD_VECTOR.
6330 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, &SVOps[0],
6332 } else if (InputUsed[0] < 0) {
6333 // No input vectors were used! The result is undefined.
6334 Output[l] = DAG.getUNDEF(NVT);
6336 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
6337 (InputUsed[0] % 2) * NumLaneElems,
6339 // If only one input was used, use an undefined vector for the other.
6340 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
6341 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
6342 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
6343 // At least one input vector was used. Create a new shuffle vector.
6344 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
6350 // Concatenate the result back
6351 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
6354 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
6355 /// 4 elements, and match them with several different shuffle types.
6357 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
6358 SDValue V1 = SVOp->getOperand(0);
6359 SDValue V2 = SVOp->getOperand(1);
6360 DebugLoc dl = SVOp->getDebugLoc();
6361 MVT VT = SVOp->getValueType(0).getSimpleVT();
6363 assert(VT.is128BitVector() && "Unsupported vector size");
6365 std::pair<int, int> Locs[4];
6366 int Mask1[] = { -1, -1, -1, -1 };
6367 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
6371 for (unsigned i = 0; i != 4; ++i) {
6372 int Idx = PermMask[i];
6374 Locs[i] = std::make_pair(-1, -1);
6376 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
6378 Locs[i] = std::make_pair(0, NumLo);
6382 Locs[i] = std::make_pair(1, NumHi);
6384 Mask1[2+NumHi] = Idx;
6390 if (NumLo <= 2 && NumHi <= 2) {
6391 // If no more than two elements come from either vector. This can be
6392 // implemented with two shuffles. First shuffle gather the elements.
6393 // The second shuffle, which takes the first shuffle as both of its
6394 // vector operands, put the elements into the right order.
6395 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6397 int Mask2[] = { -1, -1, -1, -1 };
6399 for (unsigned i = 0; i != 4; ++i)
6400 if (Locs[i].first != -1) {
6401 unsigned Idx = (i < 2) ? 0 : 4;
6402 Idx += Locs[i].first * 2 + Locs[i].second;
6406 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
6409 if (NumLo == 3 || NumHi == 3) {
6410 // Otherwise, we must have three elements from one vector, call it X, and
6411 // one element from the other, call it Y. First, use a shufps to build an
6412 // intermediate vector with the one element from Y and the element from X
6413 // that will be in the same half in the final destination (the indexes don't
6414 // matter). Then, use a shufps to build the final vector, taking the half
6415 // containing the element from Y from the intermediate, and the other half
6418 // Normalize it so the 3 elements come from V1.
6419 CommuteVectorShuffleMask(PermMask, 4);
6423 // Find the element from V2.
6425 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
6426 int Val = PermMask[HiIndex];
6433 Mask1[0] = PermMask[HiIndex];
6435 Mask1[2] = PermMask[HiIndex^1];
6437 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6440 Mask1[0] = PermMask[0];
6441 Mask1[1] = PermMask[1];
6442 Mask1[2] = HiIndex & 1 ? 6 : 4;
6443 Mask1[3] = HiIndex & 1 ? 4 : 6;
6444 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6447 Mask1[0] = HiIndex & 1 ? 2 : 0;
6448 Mask1[1] = HiIndex & 1 ? 0 : 2;
6449 Mask1[2] = PermMask[2];
6450 Mask1[3] = PermMask[3];
6455 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
6458 // Break it into (shuffle shuffle_hi, shuffle_lo).
6459 int LoMask[] = { -1, -1, -1, -1 };
6460 int HiMask[] = { -1, -1, -1, -1 };
6462 int *MaskPtr = LoMask;
6463 unsigned MaskIdx = 0;
6466 for (unsigned i = 0; i != 4; ++i) {
6473 int Idx = PermMask[i];
6475 Locs[i] = std::make_pair(-1, -1);
6476 } else if (Idx < 4) {
6477 Locs[i] = std::make_pair(MaskIdx, LoIdx);
6478 MaskPtr[LoIdx] = Idx;
6481 Locs[i] = std::make_pair(MaskIdx, HiIdx);
6482 MaskPtr[HiIdx] = Idx;
6487 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
6488 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
6489 int MaskOps[] = { -1, -1, -1, -1 };
6490 for (unsigned i = 0; i != 4; ++i)
6491 if (Locs[i].first != -1)
6492 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
6493 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
6496 static bool MayFoldVectorLoad(SDValue V) {
6497 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6498 V = V.getOperand(0);
6500 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6501 V = V.getOperand(0);
6502 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
6503 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
6504 // BUILD_VECTOR (load), undef
6505 V = V.getOperand(0);
6507 return MayFoldLoad(V);
6511 SDValue getMOVDDup(SDValue &Op, DebugLoc &dl, SDValue V1, SelectionDAG &DAG) {
6512 EVT VT = Op.getValueType();
6514 // Canonizalize to v2f64.
6515 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
6516 return DAG.getNode(ISD::BITCAST, dl, VT,
6517 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
6522 SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG,
6524 SDValue V1 = Op.getOperand(0);
6525 SDValue V2 = Op.getOperand(1);
6526 EVT VT = Op.getValueType();
6528 assert(VT != MVT::v2i64 && "unsupported shuffle type");
6530 if (HasSSE2 && VT == MVT::v2f64)
6531 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
6533 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
6534 return DAG.getNode(ISD::BITCAST, dl, VT,
6535 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
6536 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
6537 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
6541 SDValue getMOVHighToLow(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG) {
6542 SDValue V1 = Op.getOperand(0);
6543 SDValue V2 = Op.getOperand(1);
6544 EVT VT = Op.getValueType();
6546 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
6547 "unsupported shuffle type");
6549 if (V2.getOpcode() == ISD::UNDEF)
6553 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
6557 SDValue getMOVLP(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
6558 SDValue V1 = Op.getOperand(0);
6559 SDValue V2 = Op.getOperand(1);
6560 EVT VT = Op.getValueType();
6561 unsigned NumElems = VT.getVectorNumElements();
6563 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
6564 // operand of these instructions is only memory, so check if there's a
6565 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
6567 bool CanFoldLoad = false;
6569 // Trivial case, when V2 comes from a load.
6570 if (MayFoldVectorLoad(V2))
6573 // When V1 is a load, it can be folded later into a store in isel, example:
6574 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
6576 // (MOVLPSmr addr:$src1, VR128:$src2)
6577 // So, recognize this potential and also use MOVLPS or MOVLPD
6578 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
6581 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6583 if (HasSSE2 && NumElems == 2)
6584 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
6587 // If we don't care about the second element, proceed to use movss.
6588 if (SVOp->getMaskElt(1) != -1)
6589 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
6592 // movl and movlp will both match v2i64, but v2i64 is never matched by
6593 // movl earlier because we make it strict to avoid messing with the movlp load
6594 // folding logic (see the code above getMOVLP call). Match it here then,
6595 // this is horrible, but will stay like this until we move all shuffle
6596 // matching to x86 specific nodes. Note that for the 1st condition all
6597 // types are matched with movsd.
6599 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
6600 // as to remove this logic from here, as much as possible
6601 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
6602 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6603 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6606 assert(VT != MVT::v4i32 && "unsupported shuffle type");
6608 // Invert the operand order and use SHUFPS to match it.
6609 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
6610 getShuffleSHUFImmediate(SVOp), DAG);
6613 // Reduce a vector shuffle to zext.
6615 X86TargetLowering::LowerVectorIntExtend(SDValue Op, SelectionDAG &DAG) const {
6616 // PMOVZX is only available from SSE41.
6617 if (!Subtarget->hasSSE41())
6620 EVT VT = Op.getValueType();
6622 // Only AVX2 support 256-bit vector integer extending.
6623 if (!Subtarget->hasInt256() && VT.is256BitVector())
6626 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6627 DebugLoc DL = Op.getDebugLoc();
6628 SDValue V1 = Op.getOperand(0);
6629 SDValue V2 = Op.getOperand(1);
6630 unsigned NumElems = VT.getVectorNumElements();
6632 // Extending is an unary operation and the element type of the source vector
6633 // won't be equal to or larger than i64.
6634 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
6635 VT.getVectorElementType() == MVT::i64)
6638 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
6639 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
6640 while ((1U << Shift) < NumElems) {
6641 if (SVOp->getMaskElt(1U << Shift) == 1)
6644 // The maximal ratio is 8, i.e. from i8 to i64.
6649 // Check the shuffle mask.
6650 unsigned Mask = (1U << Shift) - 1;
6651 for (unsigned i = 0; i != NumElems; ++i) {
6652 int EltIdx = SVOp->getMaskElt(i);
6653 if ((i & Mask) != 0 && EltIdx != -1)
6655 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift))
6659 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
6660 EVT NeVT = EVT::getIntegerVT(*DAG.getContext(), NBits);
6661 EVT NVT = EVT::getVectorVT(*DAG.getContext(), NeVT, NumElems >> Shift);
6663 if (!isTypeLegal(NVT))
6666 // Simplify the operand as it's prepared to be fed into shuffle.
6667 unsigned SignificantBits = NVT.getSizeInBits() >> Shift;
6668 if (V1.getOpcode() == ISD::BITCAST &&
6669 V1.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
6670 V1.getOperand(0).getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6672 .getOperand(0).getValueType().getSizeInBits() == SignificantBits) {
6673 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
6674 SDValue V = V1.getOperand(0).getOperand(0).getOperand(0);
6675 ConstantSDNode *CIdx =
6676 dyn_cast<ConstantSDNode>(V1.getOperand(0).getOperand(0).getOperand(1));
6677 // If it's foldable, i.e. normal load with single use, we will let code
6678 // selection to fold it. Otherwise, we will short the conversion sequence.
6679 if (CIdx && CIdx->getZExtValue() == 0 &&
6680 (!ISD::isNormalLoad(V.getNode()) || !V.hasOneUse()))
6681 V1 = DAG.getNode(ISD::BITCAST, DL, V1.getValueType(), V);
6684 return DAG.getNode(ISD::BITCAST, DL, VT,
6685 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
6689 X86TargetLowering::NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG) const {
6690 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6691 MVT VT = Op.getValueType().getSimpleVT();
6692 DebugLoc dl = Op.getDebugLoc();
6693 SDValue V1 = Op.getOperand(0);
6694 SDValue V2 = Op.getOperand(1);
6696 if (isZeroShuffle(SVOp))
6697 return getZeroVector(VT, Subtarget, DAG, dl);
6699 // Handle splat operations
6700 if (SVOp->isSplat()) {
6701 // Use vbroadcast whenever the splat comes from a foldable load
6702 SDValue Broadcast = LowerVectorBroadcast(Op, DAG);
6703 if (Broadcast.getNode())
6707 // Check integer expanding shuffles.
6708 SDValue NewOp = LowerVectorIntExtend(Op, DAG);
6709 if (NewOp.getNode())
6712 // If the shuffle can be profitably rewritten as a narrower shuffle, then
6714 if (VT == MVT::v8i16 || VT == MVT::v16i8 ||
6715 VT == MVT::v16i16 || VT == MVT::v32i8) {
6716 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
6717 if (NewOp.getNode())
6718 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
6719 } else if ((VT == MVT::v4i32 ||
6720 (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
6721 // FIXME: Figure out a cleaner way to do this.
6722 // Try to make use of movq to zero out the top part.
6723 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
6724 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
6725 if (NewOp.getNode()) {
6726 MVT NewVT = NewOp.getValueType().getSimpleVT();
6727 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
6728 NewVT, true, false))
6729 return getVZextMovL(VT, NewVT, NewOp.getOperand(0),
6730 DAG, Subtarget, dl);
6732 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
6733 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
6734 if (NewOp.getNode()) {
6735 MVT NewVT = NewOp.getValueType().getSimpleVT();
6736 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
6737 return getVZextMovL(VT, NewVT, NewOp.getOperand(1),
6738 DAG, Subtarget, dl);
6746 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
6747 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6748 SDValue V1 = Op.getOperand(0);
6749 SDValue V2 = Op.getOperand(1);
6750 MVT VT = Op.getValueType().getSimpleVT();
6751 DebugLoc dl = Op.getDebugLoc();
6752 unsigned NumElems = VT.getVectorNumElements();
6753 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
6754 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
6755 bool V1IsSplat = false;
6756 bool V2IsSplat = false;
6757 bool HasSSE2 = Subtarget->hasSSE2();
6758 bool HasFp256 = Subtarget->hasFp256();
6759 bool HasInt256 = Subtarget->hasInt256();
6760 MachineFunction &MF = DAG.getMachineFunction();
6761 bool OptForSize = MF.getFunction()->getAttributes().
6762 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
6764 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
6766 if (V1IsUndef && V2IsUndef)
6767 return DAG.getUNDEF(VT);
6769 assert(!V1IsUndef && "Op 1 of shuffle should not be undef");
6771 // Vector shuffle lowering takes 3 steps:
6773 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
6774 // narrowing and commutation of operands should be handled.
6775 // 2) Matching of shuffles with known shuffle masks to x86 target specific
6777 // 3) Rewriting of unmatched masks into new generic shuffle operations,
6778 // so the shuffle can be broken into other shuffles and the legalizer can
6779 // try the lowering again.
6781 // The general idea is that no vector_shuffle operation should be left to
6782 // be matched during isel, all of them must be converted to a target specific
6785 // Normalize the input vectors. Here splats, zeroed vectors, profitable
6786 // narrowing and commutation of operands should be handled. The actual code
6787 // doesn't include all of those, work in progress...
6788 SDValue NewOp = NormalizeVectorShuffle(Op, DAG);
6789 if (NewOp.getNode())
6792 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
6794 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
6795 // unpckh_undef). Only use pshufd if speed is more important than size.
6796 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
6797 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6798 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
6799 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6801 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
6802 V2IsUndef && MayFoldVectorLoad(V1))
6803 return getMOVDDup(Op, dl, V1, DAG);
6805 if (isMOVHLPS_v_undef_Mask(M, VT))
6806 return getMOVHighToLow(Op, dl, DAG);
6808 // Use to match splats
6809 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
6810 (VT == MVT::v2f64 || VT == MVT::v2i64))
6811 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6813 if (isPSHUFDMask(M, VT)) {
6814 // The actual implementation will match the mask in the if above and then
6815 // during isel it can match several different instructions, not only pshufd
6816 // as its name says, sad but true, emulate the behavior for now...
6817 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
6818 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
6820 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
6822 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
6823 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
6825 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
6826 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, TargetMask,
6829 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
6833 // Check if this can be converted into a logical shift.
6834 bool isLeft = false;
6837 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
6838 if (isShift && ShVal.hasOneUse()) {
6839 // If the shifted value has multiple uses, it may be cheaper to use
6840 // v_set0 + movlhps or movhlps, etc.
6841 MVT EltVT = VT.getVectorElementType();
6842 ShAmt *= EltVT.getSizeInBits();
6843 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6846 if (isMOVLMask(M, VT)) {
6847 if (ISD::isBuildVectorAllZeros(V1.getNode()))
6848 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
6849 if (!isMOVLPMask(M, VT)) {
6850 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
6851 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6853 if (VT == MVT::v4i32 || VT == MVT::v4f32)
6854 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6858 // FIXME: fold these into legal mask.
6859 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
6860 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
6862 if (isMOVHLPSMask(M, VT))
6863 return getMOVHighToLow(Op, dl, DAG);
6865 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
6866 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
6868 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
6869 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
6871 if (isMOVLPMask(M, VT))
6872 return getMOVLP(Op, dl, DAG, HasSSE2);
6874 if (ShouldXformToMOVHLPS(M, VT) ||
6875 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
6876 return CommuteVectorShuffle(SVOp, DAG);
6879 // No better options. Use a vshldq / vsrldq.
6880 MVT EltVT = VT.getVectorElementType();
6881 ShAmt *= EltVT.getSizeInBits();
6882 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6885 bool Commuted = false;
6886 // FIXME: This should also accept a bitcast of a splat? Be careful, not
6887 // 1,1,1,1 -> v8i16 though.
6888 V1IsSplat = isSplatVector(V1.getNode());
6889 V2IsSplat = isSplatVector(V2.getNode());
6891 // Canonicalize the splat or undef, if present, to be on the RHS.
6892 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
6893 CommuteVectorShuffleMask(M, NumElems);
6895 std::swap(V1IsSplat, V2IsSplat);
6899 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
6900 // Shuffling low element of v1 into undef, just return v1.
6903 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
6904 // the instruction selector will not match, so get a canonical MOVL with
6905 // swapped operands to undo the commute.
6906 return getMOVL(DAG, dl, VT, V2, V1);
6909 if (isUNPCKLMask(M, VT, HasInt256))
6910 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
6912 if (isUNPCKHMask(M, VT, HasInt256))
6913 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
6916 // Normalize mask so all entries that point to V2 points to its first
6917 // element then try to match unpck{h|l} again. If match, return a
6918 // new vector_shuffle with the corrected mask.p
6919 SmallVector<int, 8> NewMask(M.begin(), M.end());
6920 NormalizeMask(NewMask, NumElems);
6921 if (isUNPCKLMask(NewMask, VT, HasInt256, true))
6922 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
6923 if (isUNPCKHMask(NewMask, VT, HasInt256, true))
6924 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
6928 // Commute is back and try unpck* again.
6929 // FIXME: this seems wrong.
6930 CommuteVectorShuffleMask(M, NumElems);
6932 std::swap(V1IsSplat, V2IsSplat);
6935 if (isUNPCKLMask(M, VT, HasInt256))
6936 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
6938 if (isUNPCKHMask(M, VT, HasInt256))
6939 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
6942 // Normalize the node to match x86 shuffle ops if needed
6943 if (!V2IsUndef && (isSHUFPMask(M, VT, HasFp256, /* Commuted */ true)))
6944 return CommuteVectorShuffle(SVOp, DAG);
6946 // The checks below are all present in isShuffleMaskLegal, but they are
6947 // inlined here right now to enable us to directly emit target specific
6948 // nodes, and remove one by one until they don't return Op anymore.
6950 if (isPALIGNRMask(M, VT, Subtarget))
6951 return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
6952 getShufflePALIGNRImmediate(SVOp),
6955 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
6956 SVOp->getSplatIndex() == 0 && V2IsUndef) {
6957 if (VT == MVT::v2f64 || VT == MVT::v2i64)
6958 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6961 if (isPSHUFHWMask(M, VT, HasInt256))
6962 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
6963 getShufflePSHUFHWImmediate(SVOp),
6966 if (isPSHUFLWMask(M, VT, HasInt256))
6967 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
6968 getShufflePSHUFLWImmediate(SVOp),
6971 if (isSHUFPMask(M, VT, HasFp256))
6972 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
6973 getShuffleSHUFImmediate(SVOp), DAG);
6975 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
6976 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6977 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
6978 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6980 //===--------------------------------------------------------------------===//
6981 // Generate target specific nodes for 128 or 256-bit shuffles only
6982 // supported in the AVX instruction set.
6985 // Handle VMOVDDUPY permutations
6986 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
6987 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
6989 // Handle VPERMILPS/D* permutations
6990 if (isVPERMILPMask(M, VT, HasFp256)) {
6991 if (HasInt256 && VT == MVT::v8i32)
6992 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
6993 getShuffleSHUFImmediate(SVOp), DAG);
6994 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1,
6995 getShuffleSHUFImmediate(SVOp), DAG);
6998 // Handle VPERM2F128/VPERM2I128 permutations
6999 if (isVPERM2X128Mask(M, VT, HasFp256))
7000 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
7001 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
7003 SDValue BlendOp = LowerVECTOR_SHUFFLEtoBlend(SVOp, Subtarget, DAG);
7004 if (BlendOp.getNode())
7007 if (V2IsUndef && HasInt256 && (VT == MVT::v8i32 || VT == MVT::v8f32)) {
7008 SmallVector<SDValue, 8> permclMask;
7009 for (unsigned i = 0; i != 8; ++i) {
7010 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MVT::i32));
7012 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32,
7014 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
7015 return DAG.getNode(X86ISD::VPERMV, dl, VT,
7016 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
7019 if (V2IsUndef && HasInt256 && (VT == MVT::v4i64 || VT == MVT::v4f64))
7020 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1,
7021 getShuffleCLImmediate(SVOp), DAG);
7023 //===--------------------------------------------------------------------===//
7024 // Since no target specific shuffle was selected for this generic one,
7025 // lower it into other known shuffles. FIXME: this isn't true yet, but
7026 // this is the plan.
7029 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
7030 if (VT == MVT::v8i16) {
7031 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
7032 if (NewOp.getNode())
7036 if (VT == MVT::v16i8) {
7037 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this);
7038 if (NewOp.getNode())
7042 if (VT == MVT::v32i8) {
7043 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
7044 if (NewOp.getNode())
7048 // Handle all 128-bit wide vectors with 4 elements, and match them with
7049 // several different shuffle types.
7050 if (NumElems == 4 && VT.is128BitVector())
7051 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
7053 // Handle general 256-bit shuffles
7054 if (VT.is256BitVector())
7055 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
7060 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
7061 MVT VT = Op.getValueType().getSimpleVT();
7062 DebugLoc dl = Op.getDebugLoc();
7064 if (!Op.getOperand(0).getValueType().getSimpleVT().is128BitVector())
7067 if (VT.getSizeInBits() == 8) {
7068 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
7069 Op.getOperand(0), Op.getOperand(1));
7070 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
7071 DAG.getValueType(VT));
7072 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
7075 if (VT.getSizeInBits() == 16) {
7076 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7077 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
7079 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
7080 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
7081 DAG.getNode(ISD::BITCAST, dl,
7085 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
7086 Op.getOperand(0), Op.getOperand(1));
7087 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
7088 DAG.getValueType(VT));
7089 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
7092 if (VT == MVT::f32) {
7093 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
7094 // the result back to FR32 register. It's only worth matching if the
7095 // result has a single use which is a store or a bitcast to i32. And in
7096 // the case of a store, it's not worth it if the index is a constant 0,
7097 // because a MOVSSmr can be used instead, which is smaller and faster.
7098 if (!Op.hasOneUse())
7100 SDNode *User = *Op.getNode()->use_begin();
7101 if ((User->getOpcode() != ISD::STORE ||
7102 (isa<ConstantSDNode>(Op.getOperand(1)) &&
7103 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
7104 (User->getOpcode() != ISD::BITCAST ||
7105 User->getValueType(0) != MVT::i32))
7107 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
7108 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
7111 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
7114 if (VT == MVT::i32 || VT == MVT::i64) {
7115 // ExtractPS/pextrq works with constant index.
7116 if (isa<ConstantSDNode>(Op.getOperand(1)))
7123 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
7124 SelectionDAG &DAG) const {
7125 if (!isa<ConstantSDNode>(Op.getOperand(1)))
7128 SDValue Vec = Op.getOperand(0);
7129 MVT VecVT = Vec.getValueType().getSimpleVT();
7131 // If this is a 256-bit vector result, first extract the 128-bit vector and
7132 // then extract the element from the 128-bit vector.
7133 if (VecVT.is256BitVector()) {
7134 DebugLoc dl = Op.getNode()->getDebugLoc();
7135 unsigned NumElems = VecVT.getVectorNumElements();
7136 SDValue Idx = Op.getOperand(1);
7137 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7139 // Get the 128-bit vector.
7140 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
7142 if (IdxVal >= NumElems/2)
7143 IdxVal -= NumElems/2;
7144 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
7145 DAG.getConstant(IdxVal, MVT::i32));
7148 assert(VecVT.is128BitVector() && "Unexpected vector length");
7150 if (Subtarget->hasSSE41()) {
7151 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
7156 MVT VT = Op.getValueType().getSimpleVT();
7157 DebugLoc dl = Op.getDebugLoc();
7158 // TODO: handle v16i8.
7159 if (VT.getSizeInBits() == 16) {
7160 SDValue Vec = Op.getOperand(0);
7161 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7163 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
7164 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
7165 DAG.getNode(ISD::BITCAST, dl,
7168 // Transform it so it match pextrw which produces a 32-bit result.
7169 MVT EltVT = MVT::i32;
7170 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
7171 Op.getOperand(0), Op.getOperand(1));
7172 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
7173 DAG.getValueType(VT));
7174 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
7177 if (VT.getSizeInBits() == 32) {
7178 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7182 // SHUFPS the element to the lowest double word, then movss.
7183 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
7184 MVT VVT = Op.getOperand(0).getValueType().getSimpleVT();
7185 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
7186 DAG.getUNDEF(VVT), Mask);
7187 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
7188 DAG.getIntPtrConstant(0));
7191 if (VT.getSizeInBits() == 64) {
7192 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
7193 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
7194 // to match extract_elt for f64.
7195 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7199 // UNPCKHPD the element to the lowest double word, then movsd.
7200 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
7201 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
7202 int Mask[2] = { 1, -1 };
7203 MVT VVT = Op.getOperand(0).getValueType().getSimpleVT();
7204 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
7205 DAG.getUNDEF(VVT), Mask);
7206 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
7207 DAG.getIntPtrConstant(0));
7213 static SDValue LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
7214 MVT VT = Op.getValueType().getSimpleVT();
7215 MVT EltVT = VT.getVectorElementType();
7216 DebugLoc dl = Op.getDebugLoc();
7218 SDValue N0 = Op.getOperand(0);
7219 SDValue N1 = Op.getOperand(1);
7220 SDValue N2 = Op.getOperand(2);
7222 if (!VT.is128BitVector())
7225 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
7226 isa<ConstantSDNode>(N2)) {
7228 if (VT == MVT::v8i16)
7229 Opc = X86ISD::PINSRW;
7230 else if (VT == MVT::v16i8)
7231 Opc = X86ISD::PINSRB;
7233 Opc = X86ISD::PINSRB;
7235 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
7237 if (N1.getValueType() != MVT::i32)
7238 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
7239 if (N2.getValueType() != MVT::i32)
7240 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
7241 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
7244 if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
7245 // Bits [7:6] of the constant are the source select. This will always be
7246 // zero here. The DAG Combiner may combine an extract_elt index into these
7247 // bits. For example (insert (extract, 3), 2) could be matched by putting
7248 // the '3' into bits [7:6] of X86ISD::INSERTPS.
7249 // Bits [5:4] of the constant are the destination select. This is the
7250 // value of the incoming immediate.
7251 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
7252 // combine either bitwise AND or insert of float 0.0 to set these bits.
7253 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
7254 // Create this as a scalar to vector..
7255 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
7256 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
7259 if ((EltVT == MVT::i32 || EltVT == MVT::i64) && isa<ConstantSDNode>(N2)) {
7260 // PINSR* works with constant index.
7267 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
7268 MVT VT = Op.getValueType().getSimpleVT();
7269 MVT EltVT = VT.getVectorElementType();
7271 DebugLoc dl = Op.getDebugLoc();
7272 SDValue N0 = Op.getOperand(0);
7273 SDValue N1 = Op.getOperand(1);
7274 SDValue N2 = Op.getOperand(2);
7276 // If this is a 256-bit vector result, first extract the 128-bit vector,
7277 // insert the element into the extracted half and then place it back.
7278 if (VT.is256BitVector()) {
7279 if (!isa<ConstantSDNode>(N2))
7282 // Get the desired 128-bit vector half.
7283 unsigned NumElems = VT.getVectorNumElements();
7284 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue();
7285 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
7287 // Insert the element into the desired half.
7288 bool Upper = IdxVal >= NumElems/2;
7289 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
7290 DAG.getConstant(Upper ? IdxVal-NumElems/2 : IdxVal, MVT::i32));
7292 // Insert the changed part back to the 256-bit vector
7293 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
7296 if (Subtarget->hasSSE41())
7297 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
7299 if (EltVT == MVT::i8)
7302 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
7303 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
7304 // as its second argument.
7305 if (N1.getValueType() != MVT::i32)
7306 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
7307 if (N2.getValueType() != MVT::i32)
7308 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
7309 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
7314 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
7315 LLVMContext *Context = DAG.getContext();
7316 DebugLoc dl = Op.getDebugLoc();
7317 MVT OpVT = Op.getValueType().getSimpleVT();
7319 // If this is a 256-bit vector result, first insert into a 128-bit
7320 // vector and then insert into the 256-bit vector.
7321 if (!OpVT.is128BitVector()) {
7322 // Insert into a 128-bit vector.
7323 EVT VT128 = EVT::getVectorVT(*Context,
7324 OpVT.getVectorElementType(),
7325 OpVT.getVectorNumElements() / 2);
7327 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
7329 // Insert the 128-bit vector.
7330 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
7333 if (OpVT == MVT::v1i64 &&
7334 Op.getOperand(0).getValueType() == MVT::i64)
7335 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
7337 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
7338 assert(OpVT.is128BitVector() && "Expected an SSE type!");
7339 return DAG.getNode(ISD::BITCAST, dl, OpVT,
7340 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
7343 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
7344 // a simple subregister reference or explicit instructions to grab
7345 // upper bits of a vector.
7346 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
7347 SelectionDAG &DAG) {
7348 if (Subtarget->hasFp256()) {
7349 DebugLoc dl = Op.getNode()->getDebugLoc();
7350 SDValue Vec = Op.getNode()->getOperand(0);
7351 SDValue Idx = Op.getNode()->getOperand(1);
7353 if (Op.getNode()->getValueType(0).is128BitVector() &&
7354 Vec.getNode()->getValueType(0).is256BitVector() &&
7355 isa<ConstantSDNode>(Idx)) {
7356 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7357 return Extract128BitVector(Vec, IdxVal, DAG, dl);
7363 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
7364 // simple superregister reference or explicit instructions to insert
7365 // the upper bits of a vector.
7366 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
7367 SelectionDAG &DAG) {
7368 if (Subtarget->hasFp256()) {
7369 DebugLoc dl = Op.getNode()->getDebugLoc();
7370 SDValue Vec = Op.getNode()->getOperand(0);
7371 SDValue SubVec = Op.getNode()->getOperand(1);
7372 SDValue Idx = Op.getNode()->getOperand(2);
7374 if (Op.getNode()->getValueType(0).is256BitVector() &&
7375 SubVec.getNode()->getValueType(0).is128BitVector() &&
7376 isa<ConstantSDNode>(Idx)) {
7377 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7378 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
7384 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
7385 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
7386 // one of the above mentioned nodes. It has to be wrapped because otherwise
7387 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
7388 // be used to form addressing mode. These wrapped nodes will be selected
7391 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
7392 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
7394 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7396 unsigned char OpFlag = 0;
7397 unsigned WrapperKind = X86ISD::Wrapper;
7398 CodeModel::Model M = getTargetMachine().getCodeModel();
7400 if (Subtarget->isPICStyleRIPRel() &&
7401 (M == CodeModel::Small || M == CodeModel::Kernel))
7402 WrapperKind = X86ISD::WrapperRIP;
7403 else if (Subtarget->isPICStyleGOT())
7404 OpFlag = X86II::MO_GOTOFF;
7405 else if (Subtarget->isPICStyleStubPIC())
7406 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7408 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
7410 CP->getOffset(), OpFlag);
7411 DebugLoc DL = CP->getDebugLoc();
7412 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7413 // With PIC, the address is actually $g + Offset.
7415 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7416 DAG.getNode(X86ISD::GlobalBaseReg,
7417 DebugLoc(), getPointerTy()),
7424 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
7425 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
7427 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7429 unsigned char OpFlag = 0;
7430 unsigned WrapperKind = X86ISD::Wrapper;
7431 CodeModel::Model M = getTargetMachine().getCodeModel();
7433 if (Subtarget->isPICStyleRIPRel() &&
7434 (M == CodeModel::Small || M == CodeModel::Kernel))
7435 WrapperKind = X86ISD::WrapperRIP;
7436 else if (Subtarget->isPICStyleGOT())
7437 OpFlag = X86II::MO_GOTOFF;
7438 else if (Subtarget->isPICStyleStubPIC())
7439 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7441 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
7443 DebugLoc DL = JT->getDebugLoc();
7444 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7446 // With PIC, the address is actually $g + Offset.
7448 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7449 DAG.getNode(X86ISD::GlobalBaseReg,
7450 DebugLoc(), getPointerTy()),
7457 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
7458 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
7460 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7462 unsigned char OpFlag = 0;
7463 unsigned WrapperKind = X86ISD::Wrapper;
7464 CodeModel::Model M = getTargetMachine().getCodeModel();
7466 if (Subtarget->isPICStyleRIPRel() &&
7467 (M == CodeModel::Small || M == CodeModel::Kernel)) {
7468 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
7469 OpFlag = X86II::MO_GOTPCREL;
7470 WrapperKind = X86ISD::WrapperRIP;
7471 } else if (Subtarget->isPICStyleGOT()) {
7472 OpFlag = X86II::MO_GOT;
7473 } else if (Subtarget->isPICStyleStubPIC()) {
7474 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
7475 } else if (Subtarget->isPICStyleStubNoDynamic()) {
7476 OpFlag = X86II::MO_DARWIN_NONLAZY;
7479 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
7481 DebugLoc DL = Op.getDebugLoc();
7482 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7484 // With PIC, the address is actually $g + Offset.
7485 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
7486 !Subtarget->is64Bit()) {
7487 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7488 DAG.getNode(X86ISD::GlobalBaseReg,
7489 DebugLoc(), getPointerTy()),
7493 // For symbols that require a load from a stub to get the address, emit the
7495 if (isGlobalStubReference(OpFlag))
7496 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
7497 MachinePointerInfo::getGOT(), false, false, false, 0);
7503 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
7504 // Create the TargetBlockAddressAddress node.
7505 unsigned char OpFlags =
7506 Subtarget->ClassifyBlockAddressReference();
7507 CodeModel::Model M = getTargetMachine().getCodeModel();
7508 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
7509 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
7510 DebugLoc dl = Op.getDebugLoc();
7511 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
7514 if (Subtarget->isPICStyleRIPRel() &&
7515 (M == CodeModel::Small || M == CodeModel::Kernel))
7516 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7518 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7520 // With PIC, the address is actually $g + Offset.
7521 if (isGlobalRelativeToPICBase(OpFlags)) {
7522 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7523 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7531 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
7532 int64_t Offset, SelectionDAG &DAG) const {
7533 // Create the TargetGlobalAddress node, folding in the constant
7534 // offset if it is legal.
7535 unsigned char OpFlags =
7536 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
7537 CodeModel::Model M = getTargetMachine().getCodeModel();
7539 if (OpFlags == X86II::MO_NO_FLAG &&
7540 X86::isOffsetSuitableForCodeModel(Offset, M)) {
7541 // A direct static reference to a global.
7542 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
7545 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
7548 if (Subtarget->isPICStyleRIPRel() &&
7549 (M == CodeModel::Small || M == CodeModel::Kernel))
7550 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7552 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7554 // With PIC, the address is actually $g + Offset.
7555 if (isGlobalRelativeToPICBase(OpFlags)) {
7556 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7557 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7561 // For globals that require a load from a stub to get the address, emit the
7563 if (isGlobalStubReference(OpFlags))
7564 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
7565 MachinePointerInfo::getGOT(), false, false, false, 0);
7567 // If there was a non-zero offset that we didn't fold, create an explicit
7570 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
7571 DAG.getConstant(Offset, getPointerTy()));
7577 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
7578 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
7579 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
7580 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
7584 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
7585 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
7586 unsigned char OperandFlags, bool LocalDynamic = false) {
7587 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7588 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7589 DebugLoc dl = GA->getDebugLoc();
7590 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7591 GA->getValueType(0),
7595 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
7599 SDValue Ops[] = { Chain, TGA, *InFlag };
7600 Chain = DAG.getNode(CallType, dl, NodeTys, Ops, 3);
7602 SDValue Ops[] = { Chain, TGA };
7603 Chain = DAG.getNode(CallType, dl, NodeTys, Ops, 2);
7606 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
7607 MFI->setAdjustsStack(true);
7609 SDValue Flag = Chain.getValue(1);
7610 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
7613 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
7615 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7618 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
7619 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
7620 DAG.getNode(X86ISD::GlobalBaseReg,
7621 DebugLoc(), PtrVT), InFlag);
7622 InFlag = Chain.getValue(1);
7624 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
7627 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
7629 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7631 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
7632 X86::RAX, X86II::MO_TLSGD);
7635 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
7639 DebugLoc dl = GA->getDebugLoc();
7641 // Get the start address of the TLS block for this module.
7642 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
7643 .getInfo<X86MachineFunctionInfo>();
7644 MFI->incNumLocalDynamicTLSAccesses();
7648 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT, X86::RAX,
7649 X86II::MO_TLSLD, /*LocalDynamic=*/true);
7652 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
7653 DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), PtrVT), InFlag);
7654 InFlag = Chain.getValue(1);
7655 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
7656 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
7659 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
7663 unsigned char OperandFlags = X86II::MO_DTPOFF;
7664 unsigned WrapperKind = X86ISD::Wrapper;
7665 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7666 GA->getValueType(0),
7667 GA->getOffset(), OperandFlags);
7668 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
7670 // Add x@dtpoff with the base.
7671 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
7674 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
7675 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7676 const EVT PtrVT, TLSModel::Model model,
7677 bool is64Bit, bool isPIC) {
7678 DebugLoc dl = GA->getDebugLoc();
7680 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
7681 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
7682 is64Bit ? 257 : 256));
7684 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
7685 DAG.getIntPtrConstant(0),
7686 MachinePointerInfo(Ptr),
7687 false, false, false, 0);
7689 unsigned char OperandFlags = 0;
7690 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
7692 unsigned WrapperKind = X86ISD::Wrapper;
7693 if (model == TLSModel::LocalExec) {
7694 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
7695 } else if (model == TLSModel::InitialExec) {
7697 OperandFlags = X86II::MO_GOTTPOFF;
7698 WrapperKind = X86ISD::WrapperRIP;
7700 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
7703 llvm_unreachable("Unexpected model");
7706 // emit "addl x@ntpoff,%eax" (local exec)
7707 // or "addl x@indntpoff,%eax" (initial exec)
7708 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
7709 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7710 GA->getValueType(0),
7711 GA->getOffset(), OperandFlags);
7712 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
7714 if (model == TLSModel::InitialExec) {
7715 if (isPIC && !is64Bit) {
7716 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
7717 DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), PtrVT),
7721 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
7722 MachinePointerInfo::getGOT(), false, false, false,
7726 // The address of the thread local variable is the add of the thread
7727 // pointer with the offset of the variable.
7728 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
7732 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
7734 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
7735 const GlobalValue *GV = GA->getGlobal();
7737 if (Subtarget->isTargetELF()) {
7738 TLSModel::Model model = getTargetMachine().getTLSModel(GV);
7741 case TLSModel::GeneralDynamic:
7742 if (Subtarget->is64Bit())
7743 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
7744 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
7745 case TLSModel::LocalDynamic:
7746 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
7747 Subtarget->is64Bit());
7748 case TLSModel::InitialExec:
7749 case TLSModel::LocalExec:
7750 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
7751 Subtarget->is64Bit(),
7752 getTargetMachine().getRelocationModel() == Reloc::PIC_);
7754 llvm_unreachable("Unknown TLS model.");
7757 if (Subtarget->isTargetDarwin()) {
7758 // Darwin only has one model of TLS. Lower to that.
7759 unsigned char OpFlag = 0;
7760 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
7761 X86ISD::WrapperRIP : X86ISD::Wrapper;
7763 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7765 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) &&
7766 !Subtarget->is64Bit();
7768 OpFlag = X86II::MO_TLVP_PIC_BASE;
7770 OpFlag = X86II::MO_TLVP;
7771 DebugLoc DL = Op.getDebugLoc();
7772 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
7773 GA->getValueType(0),
7774 GA->getOffset(), OpFlag);
7775 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7777 // With PIC32, the address is actually $g + Offset.
7779 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7780 DAG.getNode(X86ISD::GlobalBaseReg,
7781 DebugLoc(), getPointerTy()),
7784 // Lowering the machine isd will make sure everything is in the right
7786 SDValue Chain = DAG.getEntryNode();
7787 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7788 SDValue Args[] = { Chain, Offset };
7789 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2);
7791 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
7792 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7793 MFI->setAdjustsStack(true);
7795 // And our return value (tls address) is in the standard call return value
7797 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
7798 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
7802 if (Subtarget->isTargetWindows()) {
7803 // Just use the implicit TLS architecture
7804 // Need to generate someting similar to:
7805 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
7807 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
7808 // mov rcx, qword [rdx+rcx*8]
7809 // mov eax, .tls$:tlsvar
7810 // [rax+rcx] contains the address
7811 // Windows 64bit: gs:0x58
7812 // Windows 32bit: fs:__tls_array
7814 // If GV is an alias then use the aliasee for determining
7815 // thread-localness.
7816 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
7817 GV = GA->resolveAliasedGlobal(false);
7818 DebugLoc dl = GA->getDebugLoc();
7819 SDValue Chain = DAG.getEntryNode();
7821 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
7822 // %gs:0x58 (64-bit).
7823 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
7824 ? Type::getInt8PtrTy(*DAG.getContext(),
7826 : Type::getInt32PtrTy(*DAG.getContext(),
7829 SDValue ThreadPointer = DAG.getLoad(getPointerTy(), dl, Chain,
7830 Subtarget->is64Bit()
7831 ? DAG.getIntPtrConstant(0x58)
7832 : DAG.getExternalSymbol("_tls_array",
7834 MachinePointerInfo(Ptr),
7835 false, false, false, 0);
7837 // Load the _tls_index variable
7838 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
7839 if (Subtarget->is64Bit())
7840 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
7841 IDX, MachinePointerInfo(), MVT::i32,
7844 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
7845 false, false, false, 0);
7847 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
7849 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
7851 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
7852 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
7853 false, false, false, 0);
7855 // Get the offset of start of .tls section
7856 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7857 GA->getValueType(0),
7858 GA->getOffset(), X86II::MO_SECREL);
7859 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
7861 // The address of the thread local variable is the add of the thread
7862 // pointer with the offset of the variable.
7863 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
7866 llvm_unreachable("TLS not implemented for this target.");
7869 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
7870 /// and take a 2 x i32 value to shift plus a shift amount.
7871 SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const{
7872 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
7873 EVT VT = Op.getValueType();
7874 unsigned VTBits = VT.getSizeInBits();
7875 DebugLoc dl = Op.getDebugLoc();
7876 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
7877 SDValue ShOpLo = Op.getOperand(0);
7878 SDValue ShOpHi = Op.getOperand(1);
7879 SDValue ShAmt = Op.getOperand(2);
7880 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
7881 DAG.getConstant(VTBits - 1, MVT::i8))
7882 : DAG.getConstant(0, VT);
7885 if (Op.getOpcode() == ISD::SHL_PARTS) {
7886 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
7887 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
7889 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
7890 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
7893 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
7894 DAG.getConstant(VTBits, MVT::i8));
7895 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
7896 AndNode, DAG.getConstant(0, MVT::i8));
7899 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
7900 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
7901 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
7903 if (Op.getOpcode() == ISD::SHL_PARTS) {
7904 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7905 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7907 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7908 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7911 SDValue Ops[2] = { Lo, Hi };
7912 return DAG.getMergeValues(Ops, 2, dl);
7915 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
7916 SelectionDAG &DAG) const {
7917 EVT SrcVT = Op.getOperand(0).getValueType();
7919 if (SrcVT.isVector())
7922 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
7923 "Unknown SINT_TO_FP to lower!");
7925 // These are really Legal; return the operand so the caller accepts it as
7927 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
7929 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
7930 Subtarget->is64Bit()) {
7934 DebugLoc dl = Op.getDebugLoc();
7935 unsigned Size = SrcVT.getSizeInBits()/8;
7936 MachineFunction &MF = DAG.getMachineFunction();
7937 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
7938 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7939 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7941 MachinePointerInfo::getFixedStack(SSFI),
7943 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
7946 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
7948 SelectionDAG &DAG) const {
7950 DebugLoc DL = Op.getDebugLoc();
7952 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
7954 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
7956 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
7958 unsigned ByteSize = SrcVT.getSizeInBits()/8;
7960 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
7961 MachineMemOperand *MMO;
7963 int SSFI = FI->getIndex();
7965 DAG.getMachineFunction()
7966 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7967 MachineMemOperand::MOLoad, ByteSize, ByteSize);
7969 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
7970 StackSlot = StackSlot.getOperand(1);
7972 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
7973 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
7975 Tys, Ops, array_lengthof(Ops),
7979 Chain = Result.getValue(1);
7980 SDValue InFlag = Result.getValue(2);
7982 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
7983 // shouldn't be necessary except that RFP cannot be live across
7984 // multiple blocks. When stackifier is fixed, they can be uncoupled.
7985 MachineFunction &MF = DAG.getMachineFunction();
7986 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
7987 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
7988 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7989 Tys = DAG.getVTList(MVT::Other);
7991 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
7993 MachineMemOperand *MMO =
7994 DAG.getMachineFunction()
7995 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7996 MachineMemOperand::MOStore, SSFISize, SSFISize);
7998 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
7999 Ops, array_lengthof(Ops),
8000 Op.getValueType(), MMO);
8001 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
8002 MachinePointerInfo::getFixedStack(SSFI),
8003 false, false, false, 0);
8009 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
8010 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
8011 SelectionDAG &DAG) const {
8012 // This algorithm is not obvious. Here it is what we're trying to output:
8015 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
8016 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
8020 pshufd $0x4e, %xmm0, %xmm1
8025 DebugLoc dl = Op.getDebugLoc();
8026 LLVMContext *Context = DAG.getContext();
8028 // Build some magic constants.
8029 const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
8030 Constant *C0 = ConstantDataVector::get(*Context, CV0);
8031 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
8033 SmallVector<Constant*,2> CV1;
8035 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
8036 APInt(64, 0x4330000000000000ULL))));
8038 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
8039 APInt(64, 0x4530000000000000ULL))));
8040 Constant *C1 = ConstantVector::get(CV1);
8041 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
8043 // Load the 64-bit value into an XMM register.
8044 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
8046 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
8047 MachinePointerInfo::getConstantPool(),
8048 false, false, false, 16);
8049 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
8050 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
8053 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
8054 MachinePointerInfo::getConstantPool(),
8055 false, false, false, 16);
8056 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
8057 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
8060 if (Subtarget->hasSSE3()) {
8061 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
8062 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
8064 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
8065 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
8067 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
8068 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
8072 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
8073 DAG.getIntPtrConstant(0));
8076 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
8077 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
8078 SelectionDAG &DAG) const {
8079 DebugLoc dl = Op.getDebugLoc();
8080 // FP constant to bias correct the final result.
8081 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
8084 // Load the 32-bit value into an XMM register.
8085 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
8088 // Zero out the upper parts of the register.
8089 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
8091 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
8092 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
8093 DAG.getIntPtrConstant(0));
8095 // Or the load with the bias.
8096 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
8097 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
8098 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
8100 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
8101 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
8102 MVT::v2f64, Bias)));
8103 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
8104 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
8105 DAG.getIntPtrConstant(0));
8107 // Subtract the bias.
8108 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
8110 // Handle final rounding.
8111 EVT DestVT = Op.getValueType();
8113 if (DestVT.bitsLT(MVT::f64))
8114 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
8115 DAG.getIntPtrConstant(0));
8116 if (DestVT.bitsGT(MVT::f64))
8117 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
8119 // Handle final rounding.
8123 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
8124 SelectionDAG &DAG) const {
8125 SDValue N0 = Op.getOperand(0);
8126 EVT SVT = N0.getValueType();
8127 DebugLoc dl = Op.getDebugLoc();
8129 assert((SVT == MVT::v4i8 || SVT == MVT::v4i16 ||
8130 SVT == MVT::v8i8 || SVT == MVT::v8i16) &&
8131 "Custom UINT_TO_FP is not supported!");
8133 EVT NVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
8134 SVT.getVectorNumElements());
8135 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
8136 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
8139 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
8140 SelectionDAG &DAG) const {
8141 SDValue N0 = Op.getOperand(0);
8142 DebugLoc dl = Op.getDebugLoc();
8144 if (Op.getValueType().isVector())
8145 return lowerUINT_TO_FP_vec(Op, DAG);
8147 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
8148 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
8149 // the optimization here.
8150 if (DAG.SignBitIsZero(N0))
8151 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
8153 EVT SrcVT = N0.getValueType();
8154 EVT DstVT = Op.getValueType();
8155 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
8156 return LowerUINT_TO_FP_i64(Op, DAG);
8157 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
8158 return LowerUINT_TO_FP_i32(Op, DAG);
8159 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
8162 // Make a 64-bit buffer, and use it to build an FILD.
8163 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
8164 if (SrcVT == MVT::i32) {
8165 SDValue WordOff = DAG.getConstant(4, getPointerTy());
8166 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
8167 getPointerTy(), StackSlot, WordOff);
8168 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
8169 StackSlot, MachinePointerInfo(),
8171 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
8172 OffsetSlot, MachinePointerInfo(),
8174 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
8178 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
8179 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
8180 StackSlot, MachinePointerInfo(),
8182 // For i64 source, we need to add the appropriate power of 2 if the input
8183 // was negative. This is the same as the optimization in
8184 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
8185 // we must be careful to do the computation in x87 extended precision, not
8186 // in SSE. (The generic code can't know it's OK to do this, or how to.)
8187 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
8188 MachineMemOperand *MMO =
8189 DAG.getMachineFunction()
8190 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8191 MachineMemOperand::MOLoad, 8, 8);
8193 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
8194 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
8195 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops, 3,
8198 APInt FF(32, 0x5F800000ULL);
8200 // Check whether the sign bit is set.
8201 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
8202 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
8205 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
8206 SDValue FudgePtr = DAG.getConstantPool(
8207 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
8210 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
8211 SDValue Zero = DAG.getIntPtrConstant(0);
8212 SDValue Four = DAG.getIntPtrConstant(4);
8213 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
8215 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
8217 // Load the value out, extending it from f32 to f80.
8218 // FIXME: Avoid the extend by constructing the right constant pool?
8219 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
8220 FudgePtr, MachinePointerInfo::getConstantPool(),
8221 MVT::f32, false, false, 4);
8222 // Extend everything to 80 bits to force it to be done on x87.
8223 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
8224 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
8227 std::pair<SDValue,SDValue>
8228 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
8229 bool IsSigned, bool IsReplace) const {
8230 DebugLoc DL = Op.getDebugLoc();
8232 EVT DstTy = Op.getValueType();
8234 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
8235 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
8239 assert(DstTy.getSimpleVT() <= MVT::i64 &&
8240 DstTy.getSimpleVT() >= MVT::i16 &&
8241 "Unknown FP_TO_INT to lower!");
8243 // These are really Legal.
8244 if (DstTy == MVT::i32 &&
8245 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
8246 return std::make_pair(SDValue(), SDValue());
8247 if (Subtarget->is64Bit() &&
8248 DstTy == MVT::i64 &&
8249 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
8250 return std::make_pair(SDValue(), SDValue());
8252 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
8253 // stack slot, or into the FTOL runtime function.
8254 MachineFunction &MF = DAG.getMachineFunction();
8255 unsigned MemSize = DstTy.getSizeInBits()/8;
8256 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
8257 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8260 if (!IsSigned && isIntegerTypeFTOL(DstTy))
8261 Opc = X86ISD::WIN_FTOL;
8263 switch (DstTy.getSimpleVT().SimpleTy) {
8264 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
8265 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
8266 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
8267 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
8270 SDValue Chain = DAG.getEntryNode();
8271 SDValue Value = Op.getOperand(0);
8272 EVT TheVT = Op.getOperand(0).getValueType();
8273 // FIXME This causes a redundant load/store if the SSE-class value is already
8274 // in memory, such as if it is on the callstack.
8275 if (isScalarFPTypeInSSEReg(TheVT)) {
8276 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
8277 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
8278 MachinePointerInfo::getFixedStack(SSFI),
8280 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
8282 Chain, StackSlot, DAG.getValueType(TheVT)
8285 MachineMemOperand *MMO =
8286 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8287 MachineMemOperand::MOLoad, MemSize, MemSize);
8288 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, 3,
8290 Chain = Value.getValue(1);
8291 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
8292 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8295 MachineMemOperand *MMO =
8296 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8297 MachineMemOperand::MOStore, MemSize, MemSize);
8299 if (Opc != X86ISD::WIN_FTOL) {
8300 // Build the FP_TO_INT*_IN_MEM
8301 SDValue Ops[] = { Chain, Value, StackSlot };
8302 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
8303 Ops, 3, DstTy, MMO);
8304 return std::make_pair(FIST, StackSlot);
8306 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
8307 DAG.getVTList(MVT::Other, MVT::Glue),
8309 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
8310 MVT::i32, ftol.getValue(1));
8311 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
8312 MVT::i32, eax.getValue(2));
8313 SDValue Ops[] = { eax, edx };
8314 SDValue pair = IsReplace
8315 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops, 2)
8316 : DAG.getMergeValues(Ops, 2, DL);
8317 return std::make_pair(pair, SDValue());
8321 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
8322 const X86Subtarget *Subtarget) {
8323 MVT VT = Op->getValueType(0).getSimpleVT();
8324 SDValue In = Op->getOperand(0);
8325 MVT InVT = In.getValueType().getSimpleVT();
8326 DebugLoc dl = Op->getDebugLoc();
8328 // Optimize vectors in AVX mode:
8331 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
8332 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
8333 // Concat upper and lower parts.
8336 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
8337 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
8338 // Concat upper and lower parts.
8341 if (((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
8342 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
8345 if (Subtarget->hasInt256())
8346 return DAG.getNode(X86ISD::VZEXT_MOVL, dl, VT, In);
8348 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
8349 SDValue Undef = DAG.getUNDEF(InVT);
8350 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
8351 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
8352 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
8354 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
8355 VT.getVectorNumElements()/2);
8357 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
8358 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
8360 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
8363 SDValue X86TargetLowering::LowerANY_EXTEND(SDValue Op,
8364 SelectionDAG &DAG) const {
8365 if (Subtarget->hasFp256()) {
8366 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
8373 SDValue X86TargetLowering::LowerZERO_EXTEND(SDValue Op,
8374 SelectionDAG &DAG) const {
8375 DebugLoc DL = Op.getDebugLoc();
8376 MVT VT = Op.getValueType().getSimpleVT();
8377 SDValue In = Op.getOperand(0);
8378 MVT SVT = In.getValueType().getSimpleVT();
8380 if (Subtarget->hasFp256()) {
8381 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
8386 if (!VT.is256BitVector() || !SVT.is128BitVector() ||
8387 VT.getVectorNumElements() != SVT.getVectorNumElements())
8390 assert(Subtarget->hasFp256() && "256-bit vector is observed without AVX!");
8392 // AVX2 has better support of integer extending.
8393 if (Subtarget->hasInt256())
8394 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
8396 SDValue Lo = DAG.getNode(X86ISD::VZEXT, DL, MVT::v4i32, In);
8397 static const int Mask[] = {4, 5, 6, 7, -1, -1, -1, -1};
8398 SDValue Hi = DAG.getNode(X86ISD::VZEXT, DL, MVT::v4i32,
8399 DAG.getVectorShuffle(MVT::v8i16, DL, In,
8400 DAG.getUNDEF(MVT::v8i16),
8403 return DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v8i32, Lo, Hi);
8406 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
8407 DebugLoc DL = Op.getDebugLoc();
8408 MVT VT = Op.getValueType().getSimpleVT();
8409 SDValue In = Op.getOperand(0);
8410 MVT SVT = In.getValueType().getSimpleVT();
8412 if ((VT == MVT::v4i32) && (SVT == MVT::v4i64)) {
8413 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
8414 if (Subtarget->hasInt256()) {
8415 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
8416 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
8417 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
8419 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
8420 DAG.getIntPtrConstant(0));
8423 // On AVX, v4i64 -> v4i32 becomes a sequence that uses PSHUFD and MOVLHPS.
8424 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
8425 DAG.getIntPtrConstant(0));
8426 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
8427 DAG.getIntPtrConstant(2));
8429 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
8430 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
8433 static const int ShufMask1[] = {0, 2, 0, 0};
8434 SDValue Undef = DAG.getUNDEF(VT);
8435 OpLo = DAG.getVectorShuffle(VT, DL, OpLo, Undef, ShufMask1);
8436 OpHi = DAG.getVectorShuffle(VT, DL, OpHi, Undef, ShufMask1);
8438 // The MOVLHPS mask:
8439 static const int ShufMask2[] = {0, 1, 4, 5};
8440 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask2);
8443 if ((VT == MVT::v8i16) && (SVT == MVT::v8i32)) {
8444 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
8445 if (Subtarget->hasInt256()) {
8446 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
8448 SmallVector<SDValue,32> pshufbMask;
8449 for (unsigned i = 0; i < 2; ++i) {
8450 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
8451 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
8452 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
8453 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
8454 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
8455 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
8456 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
8457 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
8458 for (unsigned j = 0; j < 8; ++j)
8459 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
8461 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8,
8462 &pshufbMask[0], 32);
8463 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
8464 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
8466 static const int ShufMask[] = {0, 2, -1, -1};
8467 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
8469 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
8470 DAG.getIntPtrConstant(0));
8471 return DAG.getNode(ISD::BITCAST, DL, VT, In);
8474 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
8475 DAG.getIntPtrConstant(0));
8477 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
8478 DAG.getIntPtrConstant(4));
8480 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
8481 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
8484 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
8485 -1, -1, -1, -1, -1, -1, -1, -1};
8487 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
8488 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
8489 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
8491 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
8492 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
8494 // The MOVLHPS Mask:
8495 static const int ShufMask2[] = {0, 1, 4, 5};
8496 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
8497 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
8500 // Handle truncation of V256 to V128 using shuffles.
8501 if (!VT.is128BitVector() || !SVT.is256BitVector())
8504 assert(VT.getVectorNumElements() != SVT.getVectorNumElements() &&
8506 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
8508 unsigned NumElems = VT.getVectorNumElements();
8509 EVT NVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
8512 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
8513 // Prepare truncation shuffle mask
8514 for (unsigned i = 0; i != NumElems; ++i)
8516 SDValue V = DAG.getVectorShuffle(NVT, DL,
8517 DAG.getNode(ISD::BITCAST, DL, NVT, In),
8518 DAG.getUNDEF(NVT), &MaskVec[0]);
8519 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
8520 DAG.getIntPtrConstant(0));
8523 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
8524 SelectionDAG &DAG) const {
8525 MVT VT = Op.getValueType().getSimpleVT();
8526 if (VT.isVector()) {
8527 if (VT == MVT::v8i16)
8528 return DAG.getNode(ISD::TRUNCATE, Op.getDebugLoc(), VT,
8529 DAG.getNode(ISD::FP_TO_SINT, Op.getDebugLoc(),
8530 MVT::v8i32, Op.getOperand(0)));
8534 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
8535 /*IsSigned=*/ true, /*IsReplace=*/ false);
8536 SDValue FIST = Vals.first, StackSlot = Vals.second;
8537 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
8538 if (FIST.getNode() == 0) return Op;
8540 if (StackSlot.getNode())
8542 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
8543 FIST, StackSlot, MachinePointerInfo(),
8544 false, false, false, 0);
8546 // The node is the result.
8550 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
8551 SelectionDAG &DAG) const {
8552 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
8553 /*IsSigned=*/ false, /*IsReplace=*/ false);
8554 SDValue FIST = Vals.first, StackSlot = Vals.second;
8555 assert(FIST.getNode() && "Unexpected failure");
8557 if (StackSlot.getNode())
8559 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
8560 FIST, StackSlot, MachinePointerInfo(),
8561 false, false, false, 0);
8563 // The node is the result.
8567 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
8568 DebugLoc DL = Op.getDebugLoc();
8569 MVT VT = Op.getValueType().getSimpleVT();
8570 SDValue In = Op.getOperand(0);
8571 MVT SVT = In.getValueType().getSimpleVT();
8573 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
8575 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
8576 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
8577 In, DAG.getUNDEF(SVT)));
8580 SDValue X86TargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) const {
8581 LLVMContext *Context = DAG.getContext();
8582 DebugLoc dl = Op.getDebugLoc();
8583 MVT VT = Op.getValueType().getSimpleVT();
8585 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
8586 if (VT.isVector()) {
8587 EltVT = VT.getVectorElementType();
8588 NumElts = VT.getVectorNumElements();
8591 if (EltVT == MVT::f64)
8592 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
8593 APInt(64, ~(1ULL << 63))));
8595 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEsingle,
8596 APInt(32, ~(1U << 31))));
8597 C = ConstantVector::getSplat(NumElts, C);
8598 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy());
8599 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
8600 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8601 MachinePointerInfo::getConstantPool(),
8602 false, false, false, Alignment);
8603 if (VT.isVector()) {
8604 MVT ANDVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
8605 return DAG.getNode(ISD::BITCAST, dl, VT,
8606 DAG.getNode(ISD::AND, dl, ANDVT,
8607 DAG.getNode(ISD::BITCAST, dl, ANDVT,
8609 DAG.getNode(ISD::BITCAST, dl, ANDVT, Mask)));
8611 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
8614 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const {
8615 LLVMContext *Context = DAG.getContext();
8616 DebugLoc dl = Op.getDebugLoc();
8617 MVT VT = Op.getValueType().getSimpleVT();
8619 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
8620 if (VT.isVector()) {
8621 EltVT = VT.getVectorElementType();
8622 NumElts = VT.getVectorNumElements();
8625 if (EltVT == MVT::f64)
8626 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
8627 APInt(64, 1ULL << 63)));
8629 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEsingle,
8630 APInt(32, 1U << 31)));
8631 C = ConstantVector::getSplat(NumElts, C);
8632 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy());
8633 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
8634 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8635 MachinePointerInfo::getConstantPool(),
8636 false, false, false, Alignment);
8637 if (VT.isVector()) {
8638 MVT XORVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
8639 return DAG.getNode(ISD::BITCAST, dl, VT,
8640 DAG.getNode(ISD::XOR, dl, XORVT,
8641 DAG.getNode(ISD::BITCAST, dl, XORVT,
8643 DAG.getNode(ISD::BITCAST, dl, XORVT, Mask)));
8646 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
8649 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
8650 LLVMContext *Context = DAG.getContext();
8651 SDValue Op0 = Op.getOperand(0);
8652 SDValue Op1 = Op.getOperand(1);
8653 DebugLoc dl = Op.getDebugLoc();
8654 MVT VT = Op.getValueType().getSimpleVT();
8655 MVT SrcVT = Op1.getValueType().getSimpleVT();
8657 // If second operand is smaller, extend it first.
8658 if (SrcVT.bitsLT(VT)) {
8659 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
8662 // And if it is bigger, shrink it first.
8663 if (SrcVT.bitsGT(VT)) {
8664 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
8668 // At this point the operands and the result should have the same
8669 // type, and that won't be f80 since that is not custom lowered.
8671 // First get the sign bit of second operand.
8672 SmallVector<Constant*,4> CV;
8673 if (SrcVT == MVT::f64) {
8674 const fltSemantics &Sem = APFloat::IEEEdouble;
8675 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 1ULL << 63))));
8676 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
8678 const fltSemantics &Sem = APFloat::IEEEsingle;
8679 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 1U << 31))));
8680 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
8681 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
8682 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
8684 Constant *C = ConstantVector::get(CV);
8685 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8686 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
8687 MachinePointerInfo::getConstantPool(),
8688 false, false, false, 16);
8689 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
8691 // Shift sign bit right or left if the two operands have different types.
8692 if (SrcVT.bitsGT(VT)) {
8693 // Op0 is MVT::f32, Op1 is MVT::f64.
8694 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
8695 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
8696 DAG.getConstant(32, MVT::i32));
8697 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
8698 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
8699 DAG.getIntPtrConstant(0));
8702 // Clear first operand sign bit.
8704 if (VT == MVT::f64) {
8705 const fltSemantics &Sem = APFloat::IEEEdouble;
8706 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
8707 APInt(64, ~(1ULL << 63)))));
8708 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
8710 const fltSemantics &Sem = APFloat::IEEEsingle;
8711 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
8712 APInt(32, ~(1U << 31)))));
8713 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
8714 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
8715 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
8717 C = ConstantVector::get(CV);
8718 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8719 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8720 MachinePointerInfo::getConstantPool(),
8721 false, false, false, 16);
8722 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
8724 // Or the value with the sign bit.
8725 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
8728 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
8729 SDValue N0 = Op.getOperand(0);
8730 DebugLoc dl = Op.getDebugLoc();
8731 MVT VT = Op.getValueType().getSimpleVT();
8733 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
8734 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
8735 DAG.getConstant(1, VT));
8736 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
8739 // LowerVectorAllZeroTest - Check whether an OR'd tree is PTEST-able.
8741 SDValue X86TargetLowering::LowerVectorAllZeroTest(SDValue Op,
8742 SelectionDAG &DAG) const {
8743 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
8745 if (!Subtarget->hasSSE41())
8748 if (!Op->hasOneUse())
8751 SDNode *N = Op.getNode();
8752 DebugLoc DL = N->getDebugLoc();
8754 SmallVector<SDValue, 8> Opnds;
8755 DenseMap<SDValue, unsigned> VecInMap;
8756 EVT VT = MVT::Other;
8758 // Recognize a special case where a vector is casted into wide integer to
8760 Opnds.push_back(N->getOperand(0));
8761 Opnds.push_back(N->getOperand(1));
8763 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
8764 SmallVector<SDValue, 8>::const_iterator I = Opnds.begin() + Slot;
8765 // BFS traverse all OR'd operands.
8766 if (I->getOpcode() == ISD::OR) {
8767 Opnds.push_back(I->getOperand(0));
8768 Opnds.push_back(I->getOperand(1));
8769 // Re-evaluate the number of nodes to be traversed.
8770 e += 2; // 2 more nodes (LHS and RHS) are pushed.
8774 // Quit if a non-EXTRACT_VECTOR_ELT
8775 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
8778 // Quit if without a constant index.
8779 SDValue Idx = I->getOperand(1);
8780 if (!isa<ConstantSDNode>(Idx))
8783 SDValue ExtractedFromVec = I->getOperand(0);
8784 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
8785 if (M == VecInMap.end()) {
8786 VT = ExtractedFromVec.getValueType();
8787 // Quit if not 128/256-bit vector.
8788 if (!VT.is128BitVector() && !VT.is256BitVector())
8790 // Quit if not the same type.
8791 if (VecInMap.begin() != VecInMap.end() &&
8792 VT != VecInMap.begin()->first.getValueType())
8794 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
8796 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
8799 assert((VT.is128BitVector() || VT.is256BitVector()) &&
8800 "Not extracted from 128-/256-bit vector.");
8802 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
8803 SmallVector<SDValue, 8> VecIns;
8805 for (DenseMap<SDValue, unsigned>::const_iterator
8806 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
8807 // Quit if not all elements are used.
8808 if (I->second != FullMask)
8810 VecIns.push_back(I->first);
8813 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
8815 // Cast all vectors into TestVT for PTEST.
8816 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
8817 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
8819 // If more than one full vectors are evaluated, OR them first before PTEST.
8820 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
8821 // Each iteration will OR 2 nodes and append the result until there is only
8822 // 1 node left, i.e. the final OR'd value of all vectors.
8823 SDValue LHS = VecIns[Slot];
8824 SDValue RHS = VecIns[Slot + 1];
8825 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
8828 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
8829 VecIns.back(), VecIns.back());
8832 /// Emit nodes that will be selected as "test Op0,Op0", or something
8834 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
8835 SelectionDAG &DAG) const {
8836 DebugLoc dl = Op.getDebugLoc();
8838 // CF and OF aren't always set the way we want. Determine which
8839 // of these we need.
8840 bool NeedCF = false;
8841 bool NeedOF = false;
8844 case X86::COND_A: case X86::COND_AE:
8845 case X86::COND_B: case X86::COND_BE:
8848 case X86::COND_G: case X86::COND_GE:
8849 case X86::COND_L: case X86::COND_LE:
8850 case X86::COND_O: case X86::COND_NO:
8855 // See if we can use the EFLAGS value from the operand instead of
8856 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
8857 // we prove that the arithmetic won't overflow, we can't use OF or CF.
8858 if (Op.getResNo() != 0 || NeedOF || NeedCF)
8859 // Emit a CMP with 0, which is the TEST pattern.
8860 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
8861 DAG.getConstant(0, Op.getValueType()));
8863 unsigned Opcode = 0;
8864 unsigned NumOperands = 0;
8866 // Truncate operations may prevent the merge of the SETCC instruction
8867 // and the arithmetic intruction before it. Attempt to truncate the operands
8868 // of the arithmetic instruction and use a reduced bit-width instruction.
8869 bool NeedTruncation = false;
8870 SDValue ArithOp = Op;
8871 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
8872 SDValue Arith = Op->getOperand(0);
8873 // Both the trunc and the arithmetic op need to have one user each.
8874 if (Arith->hasOneUse())
8875 switch (Arith.getOpcode()) {
8882 NeedTruncation = true;
8888 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
8889 // which may be the result of a CAST. We use the variable 'Op', which is the
8890 // non-casted variable when we check for possible users.
8891 switch (ArithOp.getOpcode()) {
8893 // Due to an isel shortcoming, be conservative if this add is likely to be
8894 // selected as part of a load-modify-store instruction. When the root node
8895 // in a match is a store, isel doesn't know how to remap non-chain non-flag
8896 // uses of other nodes in the match, such as the ADD in this case. This
8897 // leads to the ADD being left around and reselected, with the result being
8898 // two adds in the output. Alas, even if none our users are stores, that
8899 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
8900 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
8901 // climbing the DAG back to the root, and it doesn't seem to be worth the
8903 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8904 UE = Op.getNode()->use_end(); UI != UE; ++UI)
8905 if (UI->getOpcode() != ISD::CopyToReg &&
8906 UI->getOpcode() != ISD::SETCC &&
8907 UI->getOpcode() != ISD::STORE)
8910 if (ConstantSDNode *C =
8911 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
8912 // An add of one will be selected as an INC.
8913 if (C->getAPIntValue() == 1) {
8914 Opcode = X86ISD::INC;
8919 // An add of negative one (subtract of one) will be selected as a DEC.
8920 if (C->getAPIntValue().isAllOnesValue()) {
8921 Opcode = X86ISD::DEC;
8927 // Otherwise use a regular EFLAGS-setting add.
8928 Opcode = X86ISD::ADD;
8932 // If the primary and result isn't used, don't bother using X86ISD::AND,
8933 // because a TEST instruction will be better.
8934 bool NonFlagUse = false;
8935 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8936 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
8938 unsigned UOpNo = UI.getOperandNo();
8939 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
8940 // Look pass truncate.
8941 UOpNo = User->use_begin().getOperandNo();
8942 User = *User->use_begin();
8945 if (User->getOpcode() != ISD::BRCOND &&
8946 User->getOpcode() != ISD::SETCC &&
8947 !(User->getOpcode() == ISD::SELECT && UOpNo == 0)) {
8960 // Due to the ISEL shortcoming noted above, be conservative if this op is
8961 // likely to be selected as part of a load-modify-store instruction.
8962 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8963 UE = Op.getNode()->use_end(); UI != UE; ++UI)
8964 if (UI->getOpcode() == ISD::STORE)
8967 // Otherwise use a regular EFLAGS-setting instruction.
8968 switch (ArithOp.getOpcode()) {
8969 default: llvm_unreachable("unexpected operator!");
8970 case ISD::SUB: Opcode = X86ISD::SUB; break;
8971 case ISD::XOR: Opcode = X86ISD::XOR; break;
8972 case ISD::AND: Opcode = X86ISD::AND; break;
8974 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
8975 SDValue EFLAGS = LowerVectorAllZeroTest(Op, DAG);
8976 if (EFLAGS.getNode())
8979 Opcode = X86ISD::OR;
8993 return SDValue(Op.getNode(), 1);
8999 // If we found that truncation is beneficial, perform the truncation and
9001 if (NeedTruncation) {
9002 EVT VT = Op.getValueType();
9003 SDValue WideVal = Op->getOperand(0);
9004 EVT WideVT = WideVal.getValueType();
9005 unsigned ConvertedOp = 0;
9006 // Use a target machine opcode to prevent further DAGCombine
9007 // optimizations that may separate the arithmetic operations
9008 // from the setcc node.
9009 switch (WideVal.getOpcode()) {
9011 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
9012 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
9013 case ISD::AND: ConvertedOp = X86ISD::AND; break;
9014 case ISD::OR: ConvertedOp = X86ISD::OR; break;
9015 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
9019 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9020 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
9021 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
9022 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
9023 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
9029 // Emit a CMP with 0, which is the TEST pattern.
9030 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
9031 DAG.getConstant(0, Op.getValueType()));
9033 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
9034 SmallVector<SDValue, 4> Ops;
9035 for (unsigned i = 0; i != NumOperands; ++i)
9036 Ops.push_back(Op.getOperand(i));
9038 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
9039 DAG.ReplaceAllUsesWith(Op, New);
9040 return SDValue(New.getNode(), 1);
9043 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
9045 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
9046 SelectionDAG &DAG) const {
9047 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
9048 if (C->getAPIntValue() == 0)
9049 return EmitTest(Op0, X86CC, DAG);
9051 DebugLoc dl = Op0.getDebugLoc();
9052 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
9053 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
9054 // Use SUB instead of CMP to enable CSE between SUB and CMP.
9055 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
9056 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
9058 return SDValue(Sub.getNode(), 1);
9060 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
9063 /// Convert a comparison if required by the subtarget.
9064 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
9065 SelectionDAG &DAG) const {
9066 // If the subtarget does not support the FUCOMI instruction, floating-point
9067 // comparisons have to be converted.
9068 if (Subtarget->hasCMov() ||
9069 Cmp.getOpcode() != X86ISD::CMP ||
9070 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
9071 !Cmp.getOperand(1).getValueType().isFloatingPoint())
9074 // The instruction selector will select an FUCOM instruction instead of
9075 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
9076 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
9077 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
9078 DebugLoc dl = Cmp.getDebugLoc();
9079 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
9080 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
9081 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
9082 DAG.getConstant(8, MVT::i8));
9083 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
9084 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
9087 static bool isAllOnes(SDValue V) {
9088 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
9089 return C && C->isAllOnesValue();
9092 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
9093 /// if it's possible.
9094 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
9095 DebugLoc dl, SelectionDAG &DAG) const {
9096 SDValue Op0 = And.getOperand(0);
9097 SDValue Op1 = And.getOperand(1);
9098 if (Op0.getOpcode() == ISD::TRUNCATE)
9099 Op0 = Op0.getOperand(0);
9100 if (Op1.getOpcode() == ISD::TRUNCATE)
9101 Op1 = Op1.getOperand(0);
9104 if (Op1.getOpcode() == ISD::SHL)
9105 std::swap(Op0, Op1);
9106 if (Op0.getOpcode() == ISD::SHL) {
9107 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
9108 if (And00C->getZExtValue() == 1) {
9109 // If we looked past a truncate, check that it's only truncating away
9111 unsigned BitWidth = Op0.getValueSizeInBits();
9112 unsigned AndBitWidth = And.getValueSizeInBits();
9113 if (BitWidth > AndBitWidth) {
9115 DAG.ComputeMaskedBits(Op0, Zeros, Ones);
9116 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
9120 RHS = Op0.getOperand(1);
9122 } else if (Op1.getOpcode() == ISD::Constant) {
9123 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
9124 uint64_t AndRHSVal = AndRHS->getZExtValue();
9125 SDValue AndLHS = Op0;
9127 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
9128 LHS = AndLHS.getOperand(0);
9129 RHS = AndLHS.getOperand(1);
9132 // Use BT if the immediate can't be encoded in a TEST instruction.
9133 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
9135 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
9139 if (LHS.getNode()) {
9140 // If the LHS is of the form (x ^ -1) then replace the LHS with x and flip
9141 // the condition code later.
9142 bool Invert = false;
9143 if (LHS.getOpcode() == ISD::XOR && isAllOnes(LHS.getOperand(1))) {
9145 LHS = LHS.getOperand(0);
9148 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
9149 // instruction. Since the shift amount is in-range-or-undefined, we know
9150 // that doing a bittest on the i32 value is ok. We extend to i32 because
9151 // the encoding for the i16 version is larger than the i32 version.
9152 // Also promote i16 to i32 for performance / code size reason.
9153 if (LHS.getValueType() == MVT::i8 ||
9154 LHS.getValueType() == MVT::i16)
9155 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
9157 // If the operand types disagree, extend the shift amount to match. Since
9158 // BT ignores high bits (like shifts) we can use anyextend.
9159 if (LHS.getValueType() != RHS.getValueType())
9160 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
9162 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
9163 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
9164 // Flip the condition if the LHS was a not instruction
9166 Cond = X86::GetOppositeBranchCondition(Cond);
9167 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9168 DAG.getConstant(Cond, MVT::i8), BT);
9174 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
9175 // ones, and then concatenate the result back.
9176 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
9177 MVT VT = Op.getValueType().getSimpleVT();
9179 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
9180 "Unsupported value type for operation");
9182 unsigned NumElems = VT.getVectorNumElements();
9183 DebugLoc dl = Op.getDebugLoc();
9184 SDValue CC = Op.getOperand(2);
9186 // Extract the LHS vectors
9187 SDValue LHS = Op.getOperand(0);
9188 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
9189 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
9191 // Extract the RHS vectors
9192 SDValue RHS = Op.getOperand(1);
9193 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
9194 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
9196 // Issue the operation on the smaller types and concatenate the result back
9197 MVT EltVT = VT.getVectorElementType();
9198 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
9199 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
9200 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
9201 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
9204 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
9205 SelectionDAG &DAG) {
9207 SDValue Op0 = Op.getOperand(0);
9208 SDValue Op1 = Op.getOperand(1);
9209 SDValue CC = Op.getOperand(2);
9210 MVT VT = Op.getValueType().getSimpleVT();
9211 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
9212 bool isFP = Op.getOperand(1).getValueType().getSimpleVT().isFloatingPoint();
9213 DebugLoc dl = Op.getDebugLoc();
9217 MVT EltVT = Op0.getValueType().getVectorElementType().getSimpleVT();
9218 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
9224 // SSE Condition code mapping:
9233 switch (SetCCOpcode) {
9234 default: llvm_unreachable("Unexpected SETCC condition");
9236 case ISD::SETEQ: SSECC = 0; break;
9238 case ISD::SETGT: Swap = true; // Fallthrough
9240 case ISD::SETOLT: SSECC = 1; break;
9242 case ISD::SETGE: Swap = true; // Fallthrough
9244 case ISD::SETOLE: SSECC = 2; break;
9245 case ISD::SETUO: SSECC = 3; break;
9247 case ISD::SETNE: SSECC = 4; break;
9248 case ISD::SETULE: Swap = true; // Fallthrough
9249 case ISD::SETUGE: SSECC = 5; break;
9250 case ISD::SETULT: Swap = true; // Fallthrough
9251 case ISD::SETUGT: SSECC = 6; break;
9252 case ISD::SETO: SSECC = 7; break;
9254 case ISD::SETONE: SSECC = 8; break;
9257 std::swap(Op0, Op1);
9259 // In the two special cases we can't handle, emit two comparisons.
9262 unsigned CombineOpc;
9263 if (SetCCOpcode == ISD::SETUEQ) {
9264 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
9266 assert(SetCCOpcode == ISD::SETONE);
9267 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
9270 SDValue Cmp0 = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
9271 DAG.getConstant(CC0, MVT::i8));
9272 SDValue Cmp1 = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
9273 DAG.getConstant(CC1, MVT::i8));
9274 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
9276 // Handle all other FP comparisons here.
9277 return DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
9278 DAG.getConstant(SSECC, MVT::i8));
9281 // Break 256-bit integer vector compare into smaller ones.
9282 if (VT.is256BitVector() && !Subtarget->hasInt256())
9283 return Lower256IntVSETCC(Op, DAG);
9285 // We are handling one of the integer comparisons here. Since SSE only has
9286 // GT and EQ comparisons for integer, swapping operands and multiple
9287 // operations may be required for some comparisons.
9289 bool Swap = false, Invert = false, FlipSigns = false;
9291 switch (SetCCOpcode) {
9292 default: llvm_unreachable("Unexpected SETCC condition");
9293 case ISD::SETNE: Invert = true;
9294 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
9295 case ISD::SETLT: Swap = true;
9296 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
9297 case ISD::SETGE: Swap = true;
9298 case ISD::SETLE: Opc = X86ISD::PCMPGT; Invert = true; break;
9299 case ISD::SETULT: Swap = true;
9300 case ISD::SETUGT: Opc = X86ISD::PCMPGT; FlipSigns = true; break;
9301 case ISD::SETUGE: Swap = true;
9302 case ISD::SETULE: Opc = X86ISD::PCMPGT; FlipSigns = true; Invert = true; break;
9305 std::swap(Op0, Op1);
9307 // Check that the operation in question is available (most are plain SSE2,
9308 // but PCMPGTQ and PCMPEQQ have different requirements).
9309 if (VT == MVT::v2i64) {
9310 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42())
9312 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
9313 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
9314 // pcmpeqd + pshufd + pand.
9315 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
9317 // First cast everything to the right type,
9318 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
9319 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
9322 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
9324 // Make sure the lower and upper halves are both all-ones.
9325 const int Mask[] = { 1, 0, 3, 2 };
9326 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
9327 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
9330 Result = DAG.getNOT(dl, Result, MVT::v4i32);
9332 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
9336 // Since SSE has no unsigned integer comparisons, we need to flip the sign
9337 // bits of the inputs before performing those operations.
9339 EVT EltVT = VT.getVectorElementType();
9340 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
9342 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
9343 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
9345 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
9346 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
9349 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
9351 // If the logical-not of the result is required, perform that now.
9353 Result = DAG.getNOT(dl, Result, VT);
9358 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
9360 MVT VT = Op.getValueType().getSimpleVT();
9362 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
9364 assert(VT == MVT::i8 && "SetCC type must be 8-bit integer");
9365 SDValue Op0 = Op.getOperand(0);
9366 SDValue Op1 = Op.getOperand(1);
9367 DebugLoc dl = Op.getDebugLoc();
9368 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
9370 // Optimize to BT if possible.
9371 // Lower (X & (1 << N)) == 0 to BT(X, N).
9372 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
9373 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
9374 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
9375 Op1.getOpcode() == ISD::Constant &&
9376 cast<ConstantSDNode>(Op1)->isNullValue() &&
9377 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
9378 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
9379 if (NewSetCC.getNode())
9383 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
9385 if (Op1.getOpcode() == ISD::Constant &&
9386 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
9387 cast<ConstantSDNode>(Op1)->isNullValue()) &&
9388 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
9390 // If the input is a setcc, then reuse the input setcc or use a new one with
9391 // the inverted condition.
9392 if (Op0.getOpcode() == X86ISD::SETCC) {
9393 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
9394 bool Invert = (CC == ISD::SETNE) ^
9395 cast<ConstantSDNode>(Op1)->isNullValue();
9396 if (!Invert) return Op0;
9398 CCode = X86::GetOppositeBranchCondition(CCode);
9399 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9400 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1));
9404 bool isFP = Op1.getValueType().getSimpleVT().isFloatingPoint();
9405 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
9406 if (X86CC == X86::COND_INVALID)
9409 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG);
9410 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
9411 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9412 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
9415 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
9416 static bool isX86LogicalCmp(SDValue Op) {
9417 unsigned Opc = Op.getNode()->getOpcode();
9418 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
9419 Opc == X86ISD::SAHF)
9421 if (Op.getResNo() == 1 &&
9422 (Opc == X86ISD::ADD ||
9423 Opc == X86ISD::SUB ||
9424 Opc == X86ISD::ADC ||
9425 Opc == X86ISD::SBB ||
9426 Opc == X86ISD::SMUL ||
9427 Opc == X86ISD::UMUL ||
9428 Opc == X86ISD::INC ||
9429 Opc == X86ISD::DEC ||
9430 Opc == X86ISD::OR ||
9431 Opc == X86ISD::XOR ||
9432 Opc == X86ISD::AND))
9435 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
9441 static bool isZero(SDValue V) {
9442 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
9443 return C && C->isNullValue();
9446 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
9447 if (V.getOpcode() != ISD::TRUNCATE)
9450 SDValue VOp0 = V.getOperand(0);
9451 unsigned InBits = VOp0.getValueSizeInBits();
9452 unsigned Bits = V.getValueSizeInBits();
9453 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
9456 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
9457 bool addTest = true;
9458 SDValue Cond = Op.getOperand(0);
9459 SDValue Op1 = Op.getOperand(1);
9460 SDValue Op2 = Op.getOperand(2);
9461 DebugLoc DL = Op.getDebugLoc();
9464 if (Cond.getOpcode() == ISD::SETCC) {
9465 SDValue NewCond = LowerSETCC(Cond, DAG);
9466 if (NewCond.getNode())
9470 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
9471 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
9472 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
9473 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
9474 if (Cond.getOpcode() == X86ISD::SETCC &&
9475 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
9476 isZero(Cond.getOperand(1).getOperand(1))) {
9477 SDValue Cmp = Cond.getOperand(1);
9479 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
9481 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
9482 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
9483 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
9485 SDValue CmpOp0 = Cmp.getOperand(0);
9486 // Apply further optimizations for special cases
9487 // (select (x != 0), -1, 0) -> neg & sbb
9488 // (select (x == 0), 0, -1) -> neg & sbb
9489 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
9490 if (YC->isNullValue() &&
9491 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
9492 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
9493 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
9494 DAG.getConstant(0, CmpOp0.getValueType()),
9496 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
9497 DAG.getConstant(X86::COND_B, MVT::i8),
9498 SDValue(Neg.getNode(), 1));
9502 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
9503 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
9504 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
9506 SDValue Res = // Res = 0 or -1.
9507 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
9508 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
9510 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
9511 Res = DAG.getNOT(DL, Res, Res.getValueType());
9513 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
9514 if (N2C == 0 || !N2C->isNullValue())
9515 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
9520 // Look past (and (setcc_carry (cmp ...)), 1).
9521 if (Cond.getOpcode() == ISD::AND &&
9522 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
9523 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
9524 if (C && C->getAPIntValue() == 1)
9525 Cond = Cond.getOperand(0);
9528 // If condition flag is set by a X86ISD::CMP, then use it as the condition
9529 // setting operand in place of the X86ISD::SETCC.
9530 unsigned CondOpcode = Cond.getOpcode();
9531 if (CondOpcode == X86ISD::SETCC ||
9532 CondOpcode == X86ISD::SETCC_CARRY) {
9533 CC = Cond.getOperand(0);
9535 SDValue Cmp = Cond.getOperand(1);
9536 unsigned Opc = Cmp.getOpcode();
9537 MVT VT = Op.getValueType().getSimpleVT();
9539 bool IllegalFPCMov = false;
9540 if (VT.isFloatingPoint() && !VT.isVector() &&
9541 !isScalarFPTypeInSSEReg(VT)) // FPStack?
9542 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
9544 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
9545 Opc == X86ISD::BT) { // FIXME
9549 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
9550 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
9551 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
9552 Cond.getOperand(0).getValueType() != MVT::i8)) {
9553 SDValue LHS = Cond.getOperand(0);
9554 SDValue RHS = Cond.getOperand(1);
9558 switch (CondOpcode) {
9559 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
9560 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
9561 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
9562 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
9563 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
9564 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
9565 default: llvm_unreachable("unexpected overflowing operator");
9567 if (CondOpcode == ISD::UMULO)
9568 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
9571 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
9573 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
9575 if (CondOpcode == ISD::UMULO)
9576 Cond = X86Op.getValue(2);
9578 Cond = X86Op.getValue(1);
9580 CC = DAG.getConstant(X86Cond, MVT::i8);
9585 // Look pass the truncate if the high bits are known zero.
9586 if (isTruncWithZeroHighBitsInput(Cond, DAG))
9587 Cond = Cond.getOperand(0);
9589 // We know the result of AND is compared against zero. Try to match
9591 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
9592 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
9593 if (NewSetCC.getNode()) {
9594 CC = NewSetCC.getOperand(0);
9595 Cond = NewSetCC.getOperand(1);
9602 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
9603 Cond = EmitTest(Cond, X86::COND_NE, DAG);
9606 // a < b ? -1 : 0 -> RES = ~setcc_carry
9607 // a < b ? 0 : -1 -> RES = setcc_carry
9608 // a >= b ? -1 : 0 -> RES = setcc_carry
9609 // a >= b ? 0 : -1 -> RES = ~setcc_carry
9610 if (Cond.getOpcode() == X86ISD::SUB) {
9611 Cond = ConvertCmpIfNecessary(Cond, DAG);
9612 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
9614 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
9615 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
9616 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
9617 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
9618 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
9619 return DAG.getNOT(DL, Res, Res.getValueType());
9624 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
9625 // widen the cmov and push the truncate through. This avoids introducing a new
9626 // branch during isel and doesn't add any extensions.
9627 if (Op.getValueType() == MVT::i8 &&
9628 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
9629 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
9630 if (T1.getValueType() == T2.getValueType() &&
9631 // Blacklist CopyFromReg to avoid partial register stalls.
9632 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
9633 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
9634 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
9635 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
9639 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
9640 // condition is true.
9641 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
9642 SDValue Ops[] = { Op2, Op1, CC, Cond };
9643 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops));
9646 SDValue X86TargetLowering::LowerSIGN_EXTEND(SDValue Op,
9647 SelectionDAG &DAG) const {
9648 MVT VT = Op->getValueType(0).getSimpleVT();
9649 SDValue In = Op->getOperand(0);
9650 MVT InVT = In.getValueType().getSimpleVT();
9651 DebugLoc dl = Op->getDebugLoc();
9653 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
9654 (VT != MVT::v8i32 || InVT != MVT::v8i16))
9657 if (Subtarget->hasInt256())
9658 return DAG.getNode(X86ISD::VSEXT_MOVL, dl, VT, In);
9660 // Optimize vectors in AVX mode
9661 // Sign extend v8i16 to v8i32 and
9664 // Divide input vector into two parts
9665 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
9666 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
9667 // concat the vectors to original VT
9669 unsigned NumElems = InVT.getVectorNumElements();
9670 SDValue Undef = DAG.getUNDEF(InVT);
9672 SmallVector<int,8> ShufMask1(NumElems, -1);
9673 for (unsigned i = 0; i != NumElems/2; ++i)
9676 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
9678 SmallVector<int,8> ShufMask2(NumElems, -1);
9679 for (unsigned i = 0; i != NumElems/2; ++i)
9680 ShufMask2[i] = i + NumElems/2;
9682 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
9684 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
9685 VT.getVectorNumElements()/2);
9687 OpLo = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpLo);
9688 OpHi = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpHi);
9690 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
9693 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
9694 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
9695 // from the AND / OR.
9696 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
9697 Opc = Op.getOpcode();
9698 if (Opc != ISD::OR && Opc != ISD::AND)
9700 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
9701 Op.getOperand(0).hasOneUse() &&
9702 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
9703 Op.getOperand(1).hasOneUse());
9706 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
9707 // 1 and that the SETCC node has a single use.
9708 static bool isXor1OfSetCC(SDValue Op) {
9709 if (Op.getOpcode() != ISD::XOR)
9711 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
9712 if (N1C && N1C->getAPIntValue() == 1) {
9713 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
9714 Op.getOperand(0).hasOneUse();
9719 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
9720 bool addTest = true;
9721 SDValue Chain = Op.getOperand(0);
9722 SDValue Cond = Op.getOperand(1);
9723 SDValue Dest = Op.getOperand(2);
9724 DebugLoc dl = Op.getDebugLoc();
9726 bool Inverted = false;
9728 if (Cond.getOpcode() == ISD::SETCC) {
9729 // Check for setcc([su]{add,sub,mul}o == 0).
9730 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
9731 isa<ConstantSDNode>(Cond.getOperand(1)) &&
9732 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
9733 Cond.getOperand(0).getResNo() == 1 &&
9734 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
9735 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
9736 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
9737 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
9738 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
9739 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
9741 Cond = Cond.getOperand(0);
9743 SDValue NewCond = LowerSETCC(Cond, DAG);
9744 if (NewCond.getNode())
9749 // FIXME: LowerXALUO doesn't handle these!!
9750 else if (Cond.getOpcode() == X86ISD::ADD ||
9751 Cond.getOpcode() == X86ISD::SUB ||
9752 Cond.getOpcode() == X86ISD::SMUL ||
9753 Cond.getOpcode() == X86ISD::UMUL)
9754 Cond = LowerXALUO(Cond, DAG);
9757 // Look pass (and (setcc_carry (cmp ...)), 1).
9758 if (Cond.getOpcode() == ISD::AND &&
9759 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
9760 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
9761 if (C && C->getAPIntValue() == 1)
9762 Cond = Cond.getOperand(0);
9765 // If condition flag is set by a X86ISD::CMP, then use it as the condition
9766 // setting operand in place of the X86ISD::SETCC.
9767 unsigned CondOpcode = Cond.getOpcode();
9768 if (CondOpcode == X86ISD::SETCC ||
9769 CondOpcode == X86ISD::SETCC_CARRY) {
9770 CC = Cond.getOperand(0);
9772 SDValue Cmp = Cond.getOperand(1);
9773 unsigned Opc = Cmp.getOpcode();
9774 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
9775 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
9779 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
9783 // These can only come from an arithmetic instruction with overflow,
9784 // e.g. SADDO, UADDO.
9785 Cond = Cond.getNode()->getOperand(1);
9791 CondOpcode = Cond.getOpcode();
9792 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
9793 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
9794 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
9795 Cond.getOperand(0).getValueType() != MVT::i8)) {
9796 SDValue LHS = Cond.getOperand(0);
9797 SDValue RHS = Cond.getOperand(1);
9801 switch (CondOpcode) {
9802 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
9803 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
9804 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
9805 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
9806 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
9807 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
9808 default: llvm_unreachable("unexpected overflowing operator");
9811 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
9812 if (CondOpcode == ISD::UMULO)
9813 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
9816 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
9818 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
9820 if (CondOpcode == ISD::UMULO)
9821 Cond = X86Op.getValue(2);
9823 Cond = X86Op.getValue(1);
9825 CC = DAG.getConstant(X86Cond, MVT::i8);
9829 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
9830 SDValue Cmp = Cond.getOperand(0).getOperand(1);
9831 if (CondOpc == ISD::OR) {
9832 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
9833 // two branches instead of an explicit OR instruction with a
9835 if (Cmp == Cond.getOperand(1).getOperand(1) &&
9836 isX86LogicalCmp(Cmp)) {
9837 CC = Cond.getOperand(0).getOperand(0);
9838 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
9839 Chain, Dest, CC, Cmp);
9840 CC = Cond.getOperand(1).getOperand(0);
9844 } else { // ISD::AND
9845 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
9846 // two branches instead of an explicit AND instruction with a
9847 // separate test. However, we only do this if this block doesn't
9848 // have a fall-through edge, because this requires an explicit
9849 // jmp when the condition is false.
9850 if (Cmp == Cond.getOperand(1).getOperand(1) &&
9851 isX86LogicalCmp(Cmp) &&
9852 Op.getNode()->hasOneUse()) {
9853 X86::CondCode CCode =
9854 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
9855 CCode = X86::GetOppositeBranchCondition(CCode);
9856 CC = DAG.getConstant(CCode, MVT::i8);
9857 SDNode *User = *Op.getNode()->use_begin();
9858 // Look for an unconditional branch following this conditional branch.
9859 // We need this because we need to reverse the successors in order
9860 // to implement FCMP_OEQ.
9861 if (User->getOpcode() == ISD::BR) {
9862 SDValue FalseBB = User->getOperand(1);
9864 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
9865 assert(NewBR == User);
9869 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
9870 Chain, Dest, CC, Cmp);
9871 X86::CondCode CCode =
9872 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
9873 CCode = X86::GetOppositeBranchCondition(CCode);
9874 CC = DAG.getConstant(CCode, MVT::i8);
9880 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
9881 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
9882 // It should be transformed during dag combiner except when the condition
9883 // is set by a arithmetics with overflow node.
9884 X86::CondCode CCode =
9885 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
9886 CCode = X86::GetOppositeBranchCondition(CCode);
9887 CC = DAG.getConstant(CCode, MVT::i8);
9888 Cond = Cond.getOperand(0).getOperand(1);
9890 } else if (Cond.getOpcode() == ISD::SETCC &&
9891 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
9892 // For FCMP_OEQ, we can emit
9893 // two branches instead of an explicit AND instruction with a
9894 // separate test. However, we only do this if this block doesn't
9895 // have a fall-through edge, because this requires an explicit
9896 // jmp when the condition is false.
9897 if (Op.getNode()->hasOneUse()) {
9898 SDNode *User = *Op.getNode()->use_begin();
9899 // Look for an unconditional branch following this conditional branch.
9900 // We need this because we need to reverse the successors in order
9901 // to implement FCMP_OEQ.
9902 if (User->getOpcode() == ISD::BR) {
9903 SDValue FalseBB = User->getOperand(1);
9905 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
9906 assert(NewBR == User);
9910 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
9911 Cond.getOperand(0), Cond.getOperand(1));
9912 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
9913 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
9914 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
9915 Chain, Dest, CC, Cmp);
9916 CC = DAG.getConstant(X86::COND_P, MVT::i8);
9921 } else if (Cond.getOpcode() == ISD::SETCC &&
9922 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
9923 // For FCMP_UNE, we can emit
9924 // two branches instead of an explicit AND instruction with a
9925 // separate test. However, we only do this if this block doesn't
9926 // have a fall-through edge, because this requires an explicit
9927 // jmp when the condition is false.
9928 if (Op.getNode()->hasOneUse()) {
9929 SDNode *User = *Op.getNode()->use_begin();
9930 // Look for an unconditional branch following this conditional branch.
9931 // We need this because we need to reverse the successors in order
9932 // to implement FCMP_UNE.
9933 if (User->getOpcode() == ISD::BR) {
9934 SDValue FalseBB = User->getOperand(1);
9936 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
9937 assert(NewBR == User);
9940 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
9941 Cond.getOperand(0), Cond.getOperand(1));
9942 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
9943 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
9944 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
9945 Chain, Dest, CC, Cmp);
9946 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
9956 // Look pass the truncate if the high bits are known zero.
9957 if (isTruncWithZeroHighBitsInput(Cond, DAG))
9958 Cond = Cond.getOperand(0);
9960 // We know the result of AND is compared against zero. Try to match
9962 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
9963 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
9964 if (NewSetCC.getNode()) {
9965 CC = NewSetCC.getOperand(0);
9966 Cond = NewSetCC.getOperand(1);
9973 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
9974 Cond = EmitTest(Cond, X86::COND_NE, DAG);
9976 Cond = ConvertCmpIfNecessary(Cond, DAG);
9977 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
9978 Chain, Dest, CC, Cond);
9981 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
9982 // Calls to _alloca is needed to probe the stack when allocating more than 4k
9983 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
9984 // that the guard pages used by the OS virtual memory manager are allocated in
9985 // correct sequence.
9987 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
9988 SelectionDAG &DAG) const {
9989 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows() ||
9990 getTargetMachine().Options.EnableSegmentedStacks) &&
9991 "This should be used only on Windows targets or when segmented stacks "
9993 assert(!Subtarget->isTargetEnvMacho() && "Not implemented");
9994 DebugLoc dl = Op.getDebugLoc();
9997 SDValue Chain = Op.getOperand(0);
9998 SDValue Size = Op.getOperand(1);
9999 // FIXME: Ensure alignment here
10001 bool Is64Bit = Subtarget->is64Bit();
10002 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32;
10004 if (getTargetMachine().Options.EnableSegmentedStacks) {
10005 MachineFunction &MF = DAG.getMachineFunction();
10006 MachineRegisterInfo &MRI = MF.getRegInfo();
10009 // The 64 bit implementation of segmented stacks needs to clobber both r10
10010 // r11. This makes it impossible to use it along with nested parameters.
10011 const Function *F = MF.getFunction();
10013 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
10015 if (I->hasNestAttr())
10016 report_fatal_error("Cannot use segmented stacks with functions that "
10017 "have nested arguments.");
10020 const TargetRegisterClass *AddrRegClass =
10021 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32);
10022 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
10023 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
10024 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
10025 DAG.getRegister(Vreg, SPTy));
10026 SDValue Ops1[2] = { Value, Chain };
10027 return DAG.getMergeValues(Ops1, 2, dl);
10030 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
10032 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
10033 Flag = Chain.getValue(1);
10034 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
10036 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
10037 Flag = Chain.getValue(1);
10039 Chain = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
10042 SDValue Ops1[2] = { Chain.getValue(0), Chain };
10043 return DAG.getMergeValues(Ops1, 2, dl);
10047 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
10048 MachineFunction &MF = DAG.getMachineFunction();
10049 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
10051 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
10052 DebugLoc DL = Op.getDebugLoc();
10054 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
10055 // vastart just stores the address of the VarArgsFrameIndex slot into the
10056 // memory location argument.
10057 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
10059 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
10060 MachinePointerInfo(SV), false, false, 0);
10064 // gp_offset (0 - 6 * 8)
10065 // fp_offset (48 - 48 + 8 * 16)
10066 // overflow_arg_area (point to parameters coming in memory).
10068 SmallVector<SDValue, 8> MemOps;
10069 SDValue FIN = Op.getOperand(1);
10071 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
10072 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
10074 FIN, MachinePointerInfo(SV), false, false, 0);
10075 MemOps.push_back(Store);
10078 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10079 FIN, DAG.getIntPtrConstant(4));
10080 Store = DAG.getStore(Op.getOperand(0), DL,
10081 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
10083 FIN, MachinePointerInfo(SV, 4), false, false, 0);
10084 MemOps.push_back(Store);
10086 // Store ptr to overflow_arg_area
10087 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10088 FIN, DAG.getIntPtrConstant(4));
10089 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
10091 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
10092 MachinePointerInfo(SV, 8),
10094 MemOps.push_back(Store);
10096 // Store ptr to reg_save_area.
10097 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10098 FIN, DAG.getIntPtrConstant(8));
10099 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
10101 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
10102 MachinePointerInfo(SV, 16), false, false, 0);
10103 MemOps.push_back(Store);
10104 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
10105 &MemOps[0], MemOps.size());
10108 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
10109 assert(Subtarget->is64Bit() &&
10110 "LowerVAARG only handles 64-bit va_arg!");
10111 assert((Subtarget->isTargetLinux() ||
10112 Subtarget->isTargetDarwin()) &&
10113 "Unhandled target in LowerVAARG");
10114 assert(Op.getNode()->getNumOperands() == 4);
10115 SDValue Chain = Op.getOperand(0);
10116 SDValue SrcPtr = Op.getOperand(1);
10117 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
10118 unsigned Align = Op.getConstantOperandVal(3);
10119 DebugLoc dl = Op.getDebugLoc();
10121 EVT ArgVT = Op.getNode()->getValueType(0);
10122 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
10123 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
10126 // Decide which area this value should be read from.
10127 // TODO: Implement the AMD64 ABI in its entirety. This simple
10128 // selection mechanism works only for the basic types.
10129 if (ArgVT == MVT::f80) {
10130 llvm_unreachable("va_arg for f80 not yet implemented");
10131 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
10132 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
10133 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
10134 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
10136 llvm_unreachable("Unhandled argument type in LowerVAARG");
10139 if (ArgMode == 2) {
10140 // Sanity Check: Make sure using fp_offset makes sense.
10141 assert(!getTargetMachine().Options.UseSoftFloat &&
10142 !(DAG.getMachineFunction()
10143 .getFunction()->getAttributes()
10144 .hasAttribute(AttributeSet::FunctionIndex,
10145 Attribute::NoImplicitFloat)) &&
10146 Subtarget->hasSSE1());
10149 // Insert VAARG_64 node into the DAG
10150 // VAARG_64 returns two values: Variable Argument Address, Chain
10151 SmallVector<SDValue, 11> InstOps;
10152 InstOps.push_back(Chain);
10153 InstOps.push_back(SrcPtr);
10154 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
10155 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
10156 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
10157 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
10158 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
10159 VTs, &InstOps[0], InstOps.size(),
10161 MachinePointerInfo(SV),
10163 /*Volatile=*/false,
10165 /*WriteMem=*/true);
10166 Chain = VAARG.getValue(1);
10168 // Load the next argument and return it
10169 return DAG.getLoad(ArgVT, dl,
10172 MachinePointerInfo(),
10173 false, false, false, 0);
10176 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
10177 SelectionDAG &DAG) {
10178 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
10179 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
10180 SDValue Chain = Op.getOperand(0);
10181 SDValue DstPtr = Op.getOperand(1);
10182 SDValue SrcPtr = Op.getOperand(2);
10183 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
10184 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
10185 DebugLoc DL = Op.getDebugLoc();
10187 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
10188 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
10190 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
10193 // getTargetVShiftNOde - Handle vector element shifts where the shift amount
10194 // may or may not be a constant. Takes immediate version of shift as input.
10195 static SDValue getTargetVShiftNode(unsigned Opc, DebugLoc dl, EVT VT,
10196 SDValue SrcOp, SDValue ShAmt,
10197 SelectionDAG &DAG) {
10198 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
10200 if (isa<ConstantSDNode>(ShAmt)) {
10201 // Constant may be a TargetConstant. Use a regular constant.
10202 uint32_t ShiftAmt = cast<ConstantSDNode>(ShAmt)->getZExtValue();
10204 default: llvm_unreachable("Unknown target vector shift node");
10205 case X86ISD::VSHLI:
10206 case X86ISD::VSRLI:
10207 case X86ISD::VSRAI:
10208 return DAG.getNode(Opc, dl, VT, SrcOp,
10209 DAG.getConstant(ShiftAmt, MVT::i32));
10213 // Change opcode to non-immediate version
10215 default: llvm_unreachable("Unknown target vector shift node");
10216 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
10217 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
10218 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
10221 // Need to build a vector containing shift amount
10222 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
10225 ShOps[1] = DAG.getConstant(0, MVT::i32);
10226 ShOps[2] = ShOps[3] = DAG.getUNDEF(MVT::i32);
10227 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, &ShOps[0], 4);
10229 // The return type has to be a 128-bit type with the same element
10230 // type as the input type.
10231 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10232 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
10234 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
10235 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
10238 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
10239 DebugLoc dl = Op.getDebugLoc();
10240 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
10242 default: return SDValue(); // Don't custom lower most intrinsics.
10243 // Comparison intrinsics.
10244 case Intrinsic::x86_sse_comieq_ss:
10245 case Intrinsic::x86_sse_comilt_ss:
10246 case Intrinsic::x86_sse_comile_ss:
10247 case Intrinsic::x86_sse_comigt_ss:
10248 case Intrinsic::x86_sse_comige_ss:
10249 case Intrinsic::x86_sse_comineq_ss:
10250 case Intrinsic::x86_sse_ucomieq_ss:
10251 case Intrinsic::x86_sse_ucomilt_ss:
10252 case Intrinsic::x86_sse_ucomile_ss:
10253 case Intrinsic::x86_sse_ucomigt_ss:
10254 case Intrinsic::x86_sse_ucomige_ss:
10255 case Intrinsic::x86_sse_ucomineq_ss:
10256 case Intrinsic::x86_sse2_comieq_sd:
10257 case Intrinsic::x86_sse2_comilt_sd:
10258 case Intrinsic::x86_sse2_comile_sd:
10259 case Intrinsic::x86_sse2_comigt_sd:
10260 case Intrinsic::x86_sse2_comige_sd:
10261 case Intrinsic::x86_sse2_comineq_sd:
10262 case Intrinsic::x86_sse2_ucomieq_sd:
10263 case Intrinsic::x86_sse2_ucomilt_sd:
10264 case Intrinsic::x86_sse2_ucomile_sd:
10265 case Intrinsic::x86_sse2_ucomigt_sd:
10266 case Intrinsic::x86_sse2_ucomige_sd:
10267 case Intrinsic::x86_sse2_ucomineq_sd: {
10271 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
10272 case Intrinsic::x86_sse_comieq_ss:
10273 case Intrinsic::x86_sse2_comieq_sd:
10274 Opc = X86ISD::COMI;
10277 case Intrinsic::x86_sse_comilt_ss:
10278 case Intrinsic::x86_sse2_comilt_sd:
10279 Opc = X86ISD::COMI;
10282 case Intrinsic::x86_sse_comile_ss:
10283 case Intrinsic::x86_sse2_comile_sd:
10284 Opc = X86ISD::COMI;
10287 case Intrinsic::x86_sse_comigt_ss:
10288 case Intrinsic::x86_sse2_comigt_sd:
10289 Opc = X86ISD::COMI;
10292 case Intrinsic::x86_sse_comige_ss:
10293 case Intrinsic::x86_sse2_comige_sd:
10294 Opc = X86ISD::COMI;
10297 case Intrinsic::x86_sse_comineq_ss:
10298 case Intrinsic::x86_sse2_comineq_sd:
10299 Opc = X86ISD::COMI;
10302 case Intrinsic::x86_sse_ucomieq_ss:
10303 case Intrinsic::x86_sse2_ucomieq_sd:
10304 Opc = X86ISD::UCOMI;
10307 case Intrinsic::x86_sse_ucomilt_ss:
10308 case Intrinsic::x86_sse2_ucomilt_sd:
10309 Opc = X86ISD::UCOMI;
10312 case Intrinsic::x86_sse_ucomile_ss:
10313 case Intrinsic::x86_sse2_ucomile_sd:
10314 Opc = X86ISD::UCOMI;
10317 case Intrinsic::x86_sse_ucomigt_ss:
10318 case Intrinsic::x86_sse2_ucomigt_sd:
10319 Opc = X86ISD::UCOMI;
10322 case Intrinsic::x86_sse_ucomige_ss:
10323 case Intrinsic::x86_sse2_ucomige_sd:
10324 Opc = X86ISD::UCOMI;
10327 case Intrinsic::x86_sse_ucomineq_ss:
10328 case Intrinsic::x86_sse2_ucomineq_sd:
10329 Opc = X86ISD::UCOMI;
10334 SDValue LHS = Op.getOperand(1);
10335 SDValue RHS = Op.getOperand(2);
10336 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
10337 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
10338 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
10339 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
10340 DAG.getConstant(X86CC, MVT::i8), Cond);
10341 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
10344 // Arithmetic intrinsics.
10345 case Intrinsic::x86_sse2_pmulu_dq:
10346 case Intrinsic::x86_avx2_pmulu_dq:
10347 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
10348 Op.getOperand(1), Op.getOperand(2));
10350 // SSE2/AVX2 sub with unsigned saturation intrinsics
10351 case Intrinsic::x86_sse2_psubus_b:
10352 case Intrinsic::x86_sse2_psubus_w:
10353 case Intrinsic::x86_avx2_psubus_b:
10354 case Intrinsic::x86_avx2_psubus_w:
10355 return DAG.getNode(X86ISD::SUBUS, dl, Op.getValueType(),
10356 Op.getOperand(1), Op.getOperand(2));
10358 // SSE3/AVX horizontal add/sub intrinsics
10359 case Intrinsic::x86_sse3_hadd_ps:
10360 case Intrinsic::x86_sse3_hadd_pd:
10361 case Intrinsic::x86_avx_hadd_ps_256:
10362 case Intrinsic::x86_avx_hadd_pd_256:
10363 case Intrinsic::x86_sse3_hsub_ps:
10364 case Intrinsic::x86_sse3_hsub_pd:
10365 case Intrinsic::x86_avx_hsub_ps_256:
10366 case Intrinsic::x86_avx_hsub_pd_256:
10367 case Intrinsic::x86_ssse3_phadd_w_128:
10368 case Intrinsic::x86_ssse3_phadd_d_128:
10369 case Intrinsic::x86_avx2_phadd_w:
10370 case Intrinsic::x86_avx2_phadd_d:
10371 case Intrinsic::x86_ssse3_phsub_w_128:
10372 case Intrinsic::x86_ssse3_phsub_d_128:
10373 case Intrinsic::x86_avx2_phsub_w:
10374 case Intrinsic::x86_avx2_phsub_d: {
10377 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
10378 case Intrinsic::x86_sse3_hadd_ps:
10379 case Intrinsic::x86_sse3_hadd_pd:
10380 case Intrinsic::x86_avx_hadd_ps_256:
10381 case Intrinsic::x86_avx_hadd_pd_256:
10382 Opcode = X86ISD::FHADD;
10384 case Intrinsic::x86_sse3_hsub_ps:
10385 case Intrinsic::x86_sse3_hsub_pd:
10386 case Intrinsic::x86_avx_hsub_ps_256:
10387 case Intrinsic::x86_avx_hsub_pd_256:
10388 Opcode = X86ISD::FHSUB;
10390 case Intrinsic::x86_ssse3_phadd_w_128:
10391 case Intrinsic::x86_ssse3_phadd_d_128:
10392 case Intrinsic::x86_avx2_phadd_w:
10393 case Intrinsic::x86_avx2_phadd_d:
10394 Opcode = X86ISD::HADD;
10396 case Intrinsic::x86_ssse3_phsub_w_128:
10397 case Intrinsic::x86_ssse3_phsub_d_128:
10398 case Intrinsic::x86_avx2_phsub_w:
10399 case Intrinsic::x86_avx2_phsub_d:
10400 Opcode = X86ISD::HSUB;
10403 return DAG.getNode(Opcode, dl, Op.getValueType(),
10404 Op.getOperand(1), Op.getOperand(2));
10407 // SSE2/SSE41/AVX2 integer max/min intrinsics.
10408 case Intrinsic::x86_sse2_pmaxu_b:
10409 case Intrinsic::x86_sse41_pmaxuw:
10410 case Intrinsic::x86_sse41_pmaxud:
10411 case Intrinsic::x86_avx2_pmaxu_b:
10412 case Intrinsic::x86_avx2_pmaxu_w:
10413 case Intrinsic::x86_avx2_pmaxu_d:
10414 case Intrinsic::x86_sse2_pminu_b:
10415 case Intrinsic::x86_sse41_pminuw:
10416 case Intrinsic::x86_sse41_pminud:
10417 case Intrinsic::x86_avx2_pminu_b:
10418 case Intrinsic::x86_avx2_pminu_w:
10419 case Intrinsic::x86_avx2_pminu_d:
10420 case Intrinsic::x86_sse41_pmaxsb:
10421 case Intrinsic::x86_sse2_pmaxs_w:
10422 case Intrinsic::x86_sse41_pmaxsd:
10423 case Intrinsic::x86_avx2_pmaxs_b:
10424 case Intrinsic::x86_avx2_pmaxs_w:
10425 case Intrinsic::x86_avx2_pmaxs_d:
10426 case Intrinsic::x86_sse41_pminsb:
10427 case Intrinsic::x86_sse2_pmins_w:
10428 case Intrinsic::x86_sse41_pminsd:
10429 case Intrinsic::x86_avx2_pmins_b:
10430 case Intrinsic::x86_avx2_pmins_w:
10431 case Intrinsic::x86_avx2_pmins_d: {
10434 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
10435 case Intrinsic::x86_sse2_pmaxu_b:
10436 case Intrinsic::x86_sse41_pmaxuw:
10437 case Intrinsic::x86_sse41_pmaxud:
10438 case Intrinsic::x86_avx2_pmaxu_b:
10439 case Intrinsic::x86_avx2_pmaxu_w:
10440 case Intrinsic::x86_avx2_pmaxu_d:
10441 Opcode = X86ISD::UMAX;
10443 case Intrinsic::x86_sse2_pminu_b:
10444 case Intrinsic::x86_sse41_pminuw:
10445 case Intrinsic::x86_sse41_pminud:
10446 case Intrinsic::x86_avx2_pminu_b:
10447 case Intrinsic::x86_avx2_pminu_w:
10448 case Intrinsic::x86_avx2_pminu_d:
10449 Opcode = X86ISD::UMIN;
10451 case Intrinsic::x86_sse41_pmaxsb:
10452 case Intrinsic::x86_sse2_pmaxs_w:
10453 case Intrinsic::x86_sse41_pmaxsd:
10454 case Intrinsic::x86_avx2_pmaxs_b:
10455 case Intrinsic::x86_avx2_pmaxs_w:
10456 case Intrinsic::x86_avx2_pmaxs_d:
10457 Opcode = X86ISD::SMAX;
10459 case Intrinsic::x86_sse41_pminsb:
10460 case Intrinsic::x86_sse2_pmins_w:
10461 case Intrinsic::x86_sse41_pminsd:
10462 case Intrinsic::x86_avx2_pmins_b:
10463 case Intrinsic::x86_avx2_pmins_w:
10464 case Intrinsic::x86_avx2_pmins_d:
10465 Opcode = X86ISD::SMIN;
10468 return DAG.getNode(Opcode, dl, Op.getValueType(),
10469 Op.getOperand(1), Op.getOperand(2));
10472 // SSE/SSE2/AVX floating point max/min intrinsics.
10473 case Intrinsic::x86_sse_max_ps:
10474 case Intrinsic::x86_sse2_max_pd:
10475 case Intrinsic::x86_avx_max_ps_256:
10476 case Intrinsic::x86_avx_max_pd_256:
10477 case Intrinsic::x86_sse_min_ps:
10478 case Intrinsic::x86_sse2_min_pd:
10479 case Intrinsic::x86_avx_min_ps_256:
10480 case Intrinsic::x86_avx_min_pd_256: {
10483 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
10484 case Intrinsic::x86_sse_max_ps:
10485 case Intrinsic::x86_sse2_max_pd:
10486 case Intrinsic::x86_avx_max_ps_256:
10487 case Intrinsic::x86_avx_max_pd_256:
10488 Opcode = X86ISD::FMAX;
10490 case Intrinsic::x86_sse_min_ps:
10491 case Intrinsic::x86_sse2_min_pd:
10492 case Intrinsic::x86_avx_min_ps_256:
10493 case Intrinsic::x86_avx_min_pd_256:
10494 Opcode = X86ISD::FMIN;
10497 return DAG.getNode(Opcode, dl, Op.getValueType(),
10498 Op.getOperand(1), Op.getOperand(2));
10501 // AVX2 variable shift intrinsics
10502 case Intrinsic::x86_avx2_psllv_d:
10503 case Intrinsic::x86_avx2_psllv_q:
10504 case Intrinsic::x86_avx2_psllv_d_256:
10505 case Intrinsic::x86_avx2_psllv_q_256:
10506 case Intrinsic::x86_avx2_psrlv_d:
10507 case Intrinsic::x86_avx2_psrlv_q:
10508 case Intrinsic::x86_avx2_psrlv_d_256:
10509 case Intrinsic::x86_avx2_psrlv_q_256:
10510 case Intrinsic::x86_avx2_psrav_d:
10511 case Intrinsic::x86_avx2_psrav_d_256: {
10514 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
10515 case Intrinsic::x86_avx2_psllv_d:
10516 case Intrinsic::x86_avx2_psllv_q:
10517 case Intrinsic::x86_avx2_psllv_d_256:
10518 case Intrinsic::x86_avx2_psllv_q_256:
10521 case Intrinsic::x86_avx2_psrlv_d:
10522 case Intrinsic::x86_avx2_psrlv_q:
10523 case Intrinsic::x86_avx2_psrlv_d_256:
10524 case Intrinsic::x86_avx2_psrlv_q_256:
10527 case Intrinsic::x86_avx2_psrav_d:
10528 case Intrinsic::x86_avx2_psrav_d_256:
10532 return DAG.getNode(Opcode, dl, Op.getValueType(),
10533 Op.getOperand(1), Op.getOperand(2));
10536 case Intrinsic::x86_ssse3_pshuf_b_128:
10537 case Intrinsic::x86_avx2_pshuf_b:
10538 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
10539 Op.getOperand(1), Op.getOperand(2));
10541 case Intrinsic::x86_ssse3_psign_b_128:
10542 case Intrinsic::x86_ssse3_psign_w_128:
10543 case Intrinsic::x86_ssse3_psign_d_128:
10544 case Intrinsic::x86_avx2_psign_b:
10545 case Intrinsic::x86_avx2_psign_w:
10546 case Intrinsic::x86_avx2_psign_d:
10547 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
10548 Op.getOperand(1), Op.getOperand(2));
10550 case Intrinsic::x86_sse41_insertps:
10551 return DAG.getNode(X86ISD::INSERTPS, dl, Op.getValueType(),
10552 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
10554 case Intrinsic::x86_avx_vperm2f128_ps_256:
10555 case Intrinsic::x86_avx_vperm2f128_pd_256:
10556 case Intrinsic::x86_avx_vperm2f128_si_256:
10557 case Intrinsic::x86_avx2_vperm2i128:
10558 return DAG.getNode(X86ISD::VPERM2X128, dl, Op.getValueType(),
10559 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
10561 case Intrinsic::x86_avx2_permd:
10562 case Intrinsic::x86_avx2_permps:
10563 // Operands intentionally swapped. Mask is last operand to intrinsic,
10564 // but second operand for node/intruction.
10565 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
10566 Op.getOperand(2), Op.getOperand(1));
10568 case Intrinsic::x86_sse_sqrt_ps:
10569 case Intrinsic::x86_sse2_sqrt_pd:
10570 case Intrinsic::x86_avx_sqrt_ps_256:
10571 case Intrinsic::x86_avx_sqrt_pd_256:
10572 return DAG.getNode(ISD::FSQRT, dl, Op.getValueType(), Op.getOperand(1));
10574 // ptest and testp intrinsics. The intrinsic these come from are designed to
10575 // return an integer value, not just an instruction so lower it to the ptest
10576 // or testp pattern and a setcc for the result.
10577 case Intrinsic::x86_sse41_ptestz:
10578 case Intrinsic::x86_sse41_ptestc:
10579 case Intrinsic::x86_sse41_ptestnzc:
10580 case Intrinsic::x86_avx_ptestz_256:
10581 case Intrinsic::x86_avx_ptestc_256:
10582 case Intrinsic::x86_avx_ptestnzc_256:
10583 case Intrinsic::x86_avx_vtestz_ps:
10584 case Intrinsic::x86_avx_vtestc_ps:
10585 case Intrinsic::x86_avx_vtestnzc_ps:
10586 case Intrinsic::x86_avx_vtestz_pd:
10587 case Intrinsic::x86_avx_vtestc_pd:
10588 case Intrinsic::x86_avx_vtestnzc_pd:
10589 case Intrinsic::x86_avx_vtestz_ps_256:
10590 case Intrinsic::x86_avx_vtestc_ps_256:
10591 case Intrinsic::x86_avx_vtestnzc_ps_256:
10592 case Intrinsic::x86_avx_vtestz_pd_256:
10593 case Intrinsic::x86_avx_vtestc_pd_256:
10594 case Intrinsic::x86_avx_vtestnzc_pd_256: {
10595 bool IsTestPacked = false;
10598 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
10599 case Intrinsic::x86_avx_vtestz_ps:
10600 case Intrinsic::x86_avx_vtestz_pd:
10601 case Intrinsic::x86_avx_vtestz_ps_256:
10602 case Intrinsic::x86_avx_vtestz_pd_256:
10603 IsTestPacked = true; // Fallthrough
10604 case Intrinsic::x86_sse41_ptestz:
10605 case Intrinsic::x86_avx_ptestz_256:
10607 X86CC = X86::COND_E;
10609 case Intrinsic::x86_avx_vtestc_ps:
10610 case Intrinsic::x86_avx_vtestc_pd:
10611 case Intrinsic::x86_avx_vtestc_ps_256:
10612 case Intrinsic::x86_avx_vtestc_pd_256:
10613 IsTestPacked = true; // Fallthrough
10614 case Intrinsic::x86_sse41_ptestc:
10615 case Intrinsic::x86_avx_ptestc_256:
10617 X86CC = X86::COND_B;
10619 case Intrinsic::x86_avx_vtestnzc_ps:
10620 case Intrinsic::x86_avx_vtestnzc_pd:
10621 case Intrinsic::x86_avx_vtestnzc_ps_256:
10622 case Intrinsic::x86_avx_vtestnzc_pd_256:
10623 IsTestPacked = true; // Fallthrough
10624 case Intrinsic::x86_sse41_ptestnzc:
10625 case Intrinsic::x86_avx_ptestnzc_256:
10627 X86CC = X86::COND_A;
10631 SDValue LHS = Op.getOperand(1);
10632 SDValue RHS = Op.getOperand(2);
10633 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
10634 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
10635 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
10636 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
10637 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
10640 // SSE/AVX shift intrinsics
10641 case Intrinsic::x86_sse2_psll_w:
10642 case Intrinsic::x86_sse2_psll_d:
10643 case Intrinsic::x86_sse2_psll_q:
10644 case Intrinsic::x86_avx2_psll_w:
10645 case Intrinsic::x86_avx2_psll_d:
10646 case Intrinsic::x86_avx2_psll_q:
10647 case Intrinsic::x86_sse2_psrl_w:
10648 case Intrinsic::x86_sse2_psrl_d:
10649 case Intrinsic::x86_sse2_psrl_q:
10650 case Intrinsic::x86_avx2_psrl_w:
10651 case Intrinsic::x86_avx2_psrl_d:
10652 case Intrinsic::x86_avx2_psrl_q:
10653 case Intrinsic::x86_sse2_psra_w:
10654 case Intrinsic::x86_sse2_psra_d:
10655 case Intrinsic::x86_avx2_psra_w:
10656 case Intrinsic::x86_avx2_psra_d: {
10659 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
10660 case Intrinsic::x86_sse2_psll_w:
10661 case Intrinsic::x86_sse2_psll_d:
10662 case Intrinsic::x86_sse2_psll_q:
10663 case Intrinsic::x86_avx2_psll_w:
10664 case Intrinsic::x86_avx2_psll_d:
10665 case Intrinsic::x86_avx2_psll_q:
10666 Opcode = X86ISD::VSHL;
10668 case Intrinsic::x86_sse2_psrl_w:
10669 case Intrinsic::x86_sse2_psrl_d:
10670 case Intrinsic::x86_sse2_psrl_q:
10671 case Intrinsic::x86_avx2_psrl_w:
10672 case Intrinsic::x86_avx2_psrl_d:
10673 case Intrinsic::x86_avx2_psrl_q:
10674 Opcode = X86ISD::VSRL;
10676 case Intrinsic::x86_sse2_psra_w:
10677 case Intrinsic::x86_sse2_psra_d:
10678 case Intrinsic::x86_avx2_psra_w:
10679 case Intrinsic::x86_avx2_psra_d:
10680 Opcode = X86ISD::VSRA;
10683 return DAG.getNode(Opcode, dl, Op.getValueType(),
10684 Op.getOperand(1), Op.getOperand(2));
10687 // SSE/AVX immediate shift intrinsics
10688 case Intrinsic::x86_sse2_pslli_w:
10689 case Intrinsic::x86_sse2_pslli_d:
10690 case Intrinsic::x86_sse2_pslli_q:
10691 case Intrinsic::x86_avx2_pslli_w:
10692 case Intrinsic::x86_avx2_pslli_d:
10693 case Intrinsic::x86_avx2_pslli_q:
10694 case Intrinsic::x86_sse2_psrli_w:
10695 case Intrinsic::x86_sse2_psrli_d:
10696 case Intrinsic::x86_sse2_psrli_q:
10697 case Intrinsic::x86_avx2_psrli_w:
10698 case Intrinsic::x86_avx2_psrli_d:
10699 case Intrinsic::x86_avx2_psrli_q:
10700 case Intrinsic::x86_sse2_psrai_w:
10701 case Intrinsic::x86_sse2_psrai_d:
10702 case Intrinsic::x86_avx2_psrai_w:
10703 case Intrinsic::x86_avx2_psrai_d: {
10706 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
10707 case Intrinsic::x86_sse2_pslli_w:
10708 case Intrinsic::x86_sse2_pslli_d:
10709 case Intrinsic::x86_sse2_pslli_q:
10710 case Intrinsic::x86_avx2_pslli_w:
10711 case Intrinsic::x86_avx2_pslli_d:
10712 case Intrinsic::x86_avx2_pslli_q:
10713 Opcode = X86ISD::VSHLI;
10715 case Intrinsic::x86_sse2_psrli_w:
10716 case Intrinsic::x86_sse2_psrli_d:
10717 case Intrinsic::x86_sse2_psrli_q:
10718 case Intrinsic::x86_avx2_psrli_w:
10719 case Intrinsic::x86_avx2_psrli_d:
10720 case Intrinsic::x86_avx2_psrli_q:
10721 Opcode = X86ISD::VSRLI;
10723 case Intrinsic::x86_sse2_psrai_w:
10724 case Intrinsic::x86_sse2_psrai_d:
10725 case Intrinsic::x86_avx2_psrai_w:
10726 case Intrinsic::x86_avx2_psrai_d:
10727 Opcode = X86ISD::VSRAI;
10730 return getTargetVShiftNode(Opcode, dl, Op.getValueType(),
10731 Op.getOperand(1), Op.getOperand(2), DAG);
10734 case Intrinsic::x86_sse42_pcmpistria128:
10735 case Intrinsic::x86_sse42_pcmpestria128:
10736 case Intrinsic::x86_sse42_pcmpistric128:
10737 case Intrinsic::x86_sse42_pcmpestric128:
10738 case Intrinsic::x86_sse42_pcmpistrio128:
10739 case Intrinsic::x86_sse42_pcmpestrio128:
10740 case Intrinsic::x86_sse42_pcmpistris128:
10741 case Intrinsic::x86_sse42_pcmpestris128:
10742 case Intrinsic::x86_sse42_pcmpistriz128:
10743 case Intrinsic::x86_sse42_pcmpestriz128: {
10747 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
10748 case Intrinsic::x86_sse42_pcmpistria128:
10749 Opcode = X86ISD::PCMPISTRI;
10750 X86CC = X86::COND_A;
10752 case Intrinsic::x86_sse42_pcmpestria128:
10753 Opcode = X86ISD::PCMPESTRI;
10754 X86CC = X86::COND_A;
10756 case Intrinsic::x86_sse42_pcmpistric128:
10757 Opcode = X86ISD::PCMPISTRI;
10758 X86CC = X86::COND_B;
10760 case Intrinsic::x86_sse42_pcmpestric128:
10761 Opcode = X86ISD::PCMPESTRI;
10762 X86CC = X86::COND_B;
10764 case Intrinsic::x86_sse42_pcmpistrio128:
10765 Opcode = X86ISD::PCMPISTRI;
10766 X86CC = X86::COND_O;
10768 case Intrinsic::x86_sse42_pcmpestrio128:
10769 Opcode = X86ISD::PCMPESTRI;
10770 X86CC = X86::COND_O;
10772 case Intrinsic::x86_sse42_pcmpistris128:
10773 Opcode = X86ISD::PCMPISTRI;
10774 X86CC = X86::COND_S;
10776 case Intrinsic::x86_sse42_pcmpestris128:
10777 Opcode = X86ISD::PCMPESTRI;
10778 X86CC = X86::COND_S;
10780 case Intrinsic::x86_sse42_pcmpistriz128:
10781 Opcode = X86ISD::PCMPISTRI;
10782 X86CC = X86::COND_E;
10784 case Intrinsic::x86_sse42_pcmpestriz128:
10785 Opcode = X86ISD::PCMPESTRI;
10786 X86CC = X86::COND_E;
10789 SmallVector<SDValue, 5> NewOps;
10790 NewOps.append(Op->op_begin()+1, Op->op_end());
10791 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
10792 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps.data(), NewOps.size());
10793 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
10794 DAG.getConstant(X86CC, MVT::i8),
10795 SDValue(PCMP.getNode(), 1));
10796 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
10799 case Intrinsic::x86_sse42_pcmpistri128:
10800 case Intrinsic::x86_sse42_pcmpestri128: {
10802 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
10803 Opcode = X86ISD::PCMPISTRI;
10805 Opcode = X86ISD::PCMPESTRI;
10807 SmallVector<SDValue, 5> NewOps;
10808 NewOps.append(Op->op_begin()+1, Op->op_end());
10809 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
10810 return DAG.getNode(Opcode, dl, VTs, NewOps.data(), NewOps.size());
10812 case Intrinsic::x86_fma_vfmadd_ps:
10813 case Intrinsic::x86_fma_vfmadd_pd:
10814 case Intrinsic::x86_fma_vfmsub_ps:
10815 case Intrinsic::x86_fma_vfmsub_pd:
10816 case Intrinsic::x86_fma_vfnmadd_ps:
10817 case Intrinsic::x86_fma_vfnmadd_pd:
10818 case Intrinsic::x86_fma_vfnmsub_ps:
10819 case Intrinsic::x86_fma_vfnmsub_pd:
10820 case Intrinsic::x86_fma_vfmaddsub_ps:
10821 case Intrinsic::x86_fma_vfmaddsub_pd:
10822 case Intrinsic::x86_fma_vfmsubadd_ps:
10823 case Intrinsic::x86_fma_vfmsubadd_pd:
10824 case Intrinsic::x86_fma_vfmadd_ps_256:
10825 case Intrinsic::x86_fma_vfmadd_pd_256:
10826 case Intrinsic::x86_fma_vfmsub_ps_256:
10827 case Intrinsic::x86_fma_vfmsub_pd_256:
10828 case Intrinsic::x86_fma_vfnmadd_ps_256:
10829 case Intrinsic::x86_fma_vfnmadd_pd_256:
10830 case Intrinsic::x86_fma_vfnmsub_ps_256:
10831 case Intrinsic::x86_fma_vfnmsub_pd_256:
10832 case Intrinsic::x86_fma_vfmaddsub_ps_256:
10833 case Intrinsic::x86_fma_vfmaddsub_pd_256:
10834 case Intrinsic::x86_fma_vfmsubadd_ps_256:
10835 case Intrinsic::x86_fma_vfmsubadd_pd_256: {
10838 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
10839 case Intrinsic::x86_fma_vfmadd_ps:
10840 case Intrinsic::x86_fma_vfmadd_pd:
10841 case Intrinsic::x86_fma_vfmadd_ps_256:
10842 case Intrinsic::x86_fma_vfmadd_pd_256:
10843 Opc = X86ISD::FMADD;
10845 case Intrinsic::x86_fma_vfmsub_ps:
10846 case Intrinsic::x86_fma_vfmsub_pd:
10847 case Intrinsic::x86_fma_vfmsub_ps_256:
10848 case Intrinsic::x86_fma_vfmsub_pd_256:
10849 Opc = X86ISD::FMSUB;
10851 case Intrinsic::x86_fma_vfnmadd_ps:
10852 case Intrinsic::x86_fma_vfnmadd_pd:
10853 case Intrinsic::x86_fma_vfnmadd_ps_256:
10854 case Intrinsic::x86_fma_vfnmadd_pd_256:
10855 Opc = X86ISD::FNMADD;
10857 case Intrinsic::x86_fma_vfnmsub_ps:
10858 case Intrinsic::x86_fma_vfnmsub_pd:
10859 case Intrinsic::x86_fma_vfnmsub_ps_256:
10860 case Intrinsic::x86_fma_vfnmsub_pd_256:
10861 Opc = X86ISD::FNMSUB;
10863 case Intrinsic::x86_fma_vfmaddsub_ps:
10864 case Intrinsic::x86_fma_vfmaddsub_pd:
10865 case Intrinsic::x86_fma_vfmaddsub_ps_256:
10866 case Intrinsic::x86_fma_vfmaddsub_pd_256:
10867 Opc = X86ISD::FMADDSUB;
10869 case Intrinsic::x86_fma_vfmsubadd_ps:
10870 case Intrinsic::x86_fma_vfmsubadd_pd:
10871 case Intrinsic::x86_fma_vfmsubadd_ps_256:
10872 case Intrinsic::x86_fma_vfmsubadd_pd_256:
10873 Opc = X86ISD::FMSUBADD;
10877 return DAG.getNode(Opc, dl, Op.getValueType(), Op.getOperand(1),
10878 Op.getOperand(2), Op.getOperand(3));
10883 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) {
10884 DebugLoc dl = Op.getDebugLoc();
10885 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10887 default: return SDValue(); // Don't custom lower most intrinsics.
10889 // RDRAND intrinsics.
10890 case Intrinsic::x86_rdrand_16:
10891 case Intrinsic::x86_rdrand_32:
10892 case Intrinsic::x86_rdrand_64: {
10893 // Emit the node with the right value type.
10894 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
10895 SDValue Result = DAG.getNode(X86ISD::RDRAND, dl, VTs, Op.getOperand(0));
10897 // If the value returned by RDRAND was valid (CF=1), return 1. Otherwise
10898 // return the value from Rand, which is always 0, casted to i32.
10899 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
10900 DAG.getConstant(1, Op->getValueType(1)),
10901 DAG.getConstant(X86::COND_B, MVT::i32),
10902 SDValue(Result.getNode(), 1) };
10903 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
10904 DAG.getVTList(Op->getValueType(1), MVT::Glue),
10907 // Return { result, isValid, chain }.
10908 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
10909 SDValue(Result.getNode(), 2));
10914 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
10915 SelectionDAG &DAG) const {
10916 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
10917 MFI->setReturnAddressIsTaken(true);
10919 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
10920 DebugLoc dl = Op.getDebugLoc();
10921 EVT PtrVT = getPointerTy();
10924 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
10926 DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
10927 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
10928 DAG.getNode(ISD::ADD, dl, PtrVT,
10929 FrameAddr, Offset),
10930 MachinePointerInfo(), false, false, false, 0);
10933 // Just load the return address.
10934 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
10935 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
10936 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
10939 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
10940 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
10941 MFI->setFrameAddressIsTaken(true);
10943 EVT VT = Op.getValueType();
10944 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
10945 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
10946 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
10947 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
10949 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
10950 MachinePointerInfo(),
10951 false, false, false, 0);
10955 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
10956 SelectionDAG &DAG) const {
10957 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
10960 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
10961 SDValue Chain = Op.getOperand(0);
10962 SDValue Offset = Op.getOperand(1);
10963 SDValue Handler = Op.getOperand(2);
10964 DebugLoc dl = Op.getDebugLoc();
10966 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
10967 Subtarget->is64Bit() ? X86::RBP : X86::EBP,
10969 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
10971 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Frame,
10972 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
10973 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
10974 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
10976 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
10978 return DAG.getNode(X86ISD::EH_RETURN, dl,
10980 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
10983 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
10984 SelectionDAG &DAG) const {
10985 DebugLoc DL = Op.getDebugLoc();
10986 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
10987 DAG.getVTList(MVT::i32, MVT::Other),
10988 Op.getOperand(0), Op.getOperand(1));
10991 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
10992 SelectionDAG &DAG) const {
10993 DebugLoc DL = Op.getDebugLoc();
10994 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
10995 Op.getOperand(0), Op.getOperand(1));
10998 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
10999 return Op.getOperand(0);
11002 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
11003 SelectionDAG &DAG) const {
11004 SDValue Root = Op.getOperand(0);
11005 SDValue Trmp = Op.getOperand(1); // trampoline
11006 SDValue FPtr = Op.getOperand(2); // nested function
11007 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
11008 DebugLoc dl = Op.getDebugLoc();
11010 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
11011 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
11013 if (Subtarget->is64Bit()) {
11014 SDValue OutChains[6];
11016 // Large code-model.
11017 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
11018 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
11020 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
11021 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
11023 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
11025 // Load the pointer to the nested function into R11.
11026 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
11027 SDValue Addr = Trmp;
11028 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
11029 Addr, MachinePointerInfo(TrmpAddr),
11032 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
11033 DAG.getConstant(2, MVT::i64));
11034 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
11035 MachinePointerInfo(TrmpAddr, 2),
11038 // Load the 'nest' parameter value into R10.
11039 // R10 is specified in X86CallingConv.td
11040 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
11041 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
11042 DAG.getConstant(10, MVT::i64));
11043 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
11044 Addr, MachinePointerInfo(TrmpAddr, 10),
11047 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
11048 DAG.getConstant(12, MVT::i64));
11049 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
11050 MachinePointerInfo(TrmpAddr, 12),
11053 // Jump to the nested function.
11054 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
11055 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
11056 DAG.getConstant(20, MVT::i64));
11057 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
11058 Addr, MachinePointerInfo(TrmpAddr, 20),
11061 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
11062 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
11063 DAG.getConstant(22, MVT::i64));
11064 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
11065 MachinePointerInfo(TrmpAddr, 22),
11068 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6);
11070 const Function *Func =
11071 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
11072 CallingConv::ID CC = Func->getCallingConv();
11077 llvm_unreachable("Unsupported calling convention");
11078 case CallingConv::C:
11079 case CallingConv::X86_StdCall: {
11080 // Pass 'nest' parameter in ECX.
11081 // Must be kept in sync with X86CallingConv.td
11082 NestReg = X86::ECX;
11084 // Check that ECX wasn't needed by an 'inreg' parameter.
11085 FunctionType *FTy = Func->getFunctionType();
11086 const AttributeSet &Attrs = Func->getAttributes();
11088 if (!Attrs.isEmpty() && !Func->isVarArg()) {
11089 unsigned InRegCount = 0;
11092 for (FunctionType::param_iterator I = FTy->param_begin(),
11093 E = FTy->param_end(); I != E; ++I, ++Idx)
11094 if (Attrs.hasAttribute(Idx, Attribute::InReg))
11095 // FIXME: should only count parameters that are lowered to integers.
11096 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
11098 if (InRegCount > 2) {
11099 report_fatal_error("Nest register in use - reduce number of inreg"
11105 case CallingConv::X86_FastCall:
11106 case CallingConv::X86_ThisCall:
11107 case CallingConv::Fast:
11108 // Pass 'nest' parameter in EAX.
11109 // Must be kept in sync with X86CallingConv.td
11110 NestReg = X86::EAX;
11114 SDValue OutChains[4];
11115 SDValue Addr, Disp;
11117 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
11118 DAG.getConstant(10, MVT::i32));
11119 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
11121 // This is storing the opcode for MOV32ri.
11122 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
11123 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
11124 OutChains[0] = DAG.getStore(Root, dl,
11125 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
11126 Trmp, MachinePointerInfo(TrmpAddr),
11129 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
11130 DAG.getConstant(1, MVT::i32));
11131 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
11132 MachinePointerInfo(TrmpAddr, 1),
11135 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
11136 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
11137 DAG.getConstant(5, MVT::i32));
11138 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
11139 MachinePointerInfo(TrmpAddr, 5),
11142 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
11143 DAG.getConstant(6, MVT::i32));
11144 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
11145 MachinePointerInfo(TrmpAddr, 6),
11148 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4);
11152 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
11153 SelectionDAG &DAG) const {
11155 The rounding mode is in bits 11:10 of FPSR, and has the following
11157 00 Round to nearest
11162 FLT_ROUNDS, on the other hand, expects the following:
11169 To perform the conversion, we do:
11170 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
11173 MachineFunction &MF = DAG.getMachineFunction();
11174 const TargetMachine &TM = MF.getTarget();
11175 const TargetFrameLowering &TFI = *TM.getFrameLowering();
11176 unsigned StackAlignment = TFI.getStackAlignment();
11177 EVT VT = Op.getValueType();
11178 DebugLoc DL = Op.getDebugLoc();
11180 // Save FP Control Word to stack slot
11181 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
11182 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11184 MachineMemOperand *MMO =
11185 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11186 MachineMemOperand::MOStore, 2, 2);
11188 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
11189 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
11190 DAG.getVTList(MVT::Other),
11191 Ops, 2, MVT::i16, MMO);
11193 // Load FP Control Word from stack slot
11194 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
11195 MachinePointerInfo(), false, false, false, 0);
11197 // Transform as necessary
11199 DAG.getNode(ISD::SRL, DL, MVT::i16,
11200 DAG.getNode(ISD::AND, DL, MVT::i16,
11201 CWD, DAG.getConstant(0x800, MVT::i16)),
11202 DAG.getConstant(11, MVT::i8));
11204 DAG.getNode(ISD::SRL, DL, MVT::i16,
11205 DAG.getNode(ISD::AND, DL, MVT::i16,
11206 CWD, DAG.getConstant(0x400, MVT::i16)),
11207 DAG.getConstant(9, MVT::i8));
11210 DAG.getNode(ISD::AND, DL, MVT::i16,
11211 DAG.getNode(ISD::ADD, DL, MVT::i16,
11212 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
11213 DAG.getConstant(1, MVT::i16)),
11214 DAG.getConstant(3, MVT::i16));
11216 return DAG.getNode((VT.getSizeInBits() < 16 ?
11217 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
11220 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
11221 EVT VT = Op.getValueType();
11223 unsigned NumBits = VT.getSizeInBits();
11224 DebugLoc dl = Op.getDebugLoc();
11226 Op = Op.getOperand(0);
11227 if (VT == MVT::i8) {
11228 // Zero extend to i32 since there is not an i8 bsr.
11230 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
11233 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
11234 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
11235 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
11237 // If src is zero (i.e. bsr sets ZF), returns NumBits.
11240 DAG.getConstant(NumBits+NumBits-1, OpVT),
11241 DAG.getConstant(X86::COND_E, MVT::i8),
11244 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
11246 // Finally xor with NumBits-1.
11247 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
11250 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
11254 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
11255 EVT VT = Op.getValueType();
11257 unsigned NumBits = VT.getSizeInBits();
11258 DebugLoc dl = Op.getDebugLoc();
11260 Op = Op.getOperand(0);
11261 if (VT == MVT::i8) {
11262 // Zero extend to i32 since there is not an i8 bsr.
11264 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
11267 // Issue a bsr (scan bits in reverse).
11268 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
11269 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
11271 // And xor with NumBits-1.
11272 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
11275 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
11279 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
11280 EVT VT = Op.getValueType();
11281 unsigned NumBits = VT.getSizeInBits();
11282 DebugLoc dl = Op.getDebugLoc();
11283 Op = Op.getOperand(0);
11285 // Issue a bsf (scan bits forward) which also sets EFLAGS.
11286 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
11287 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
11289 // If src is zero (i.e. bsf sets ZF), returns NumBits.
11292 DAG.getConstant(NumBits, VT),
11293 DAG.getConstant(X86::COND_E, MVT::i8),
11296 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops, array_lengthof(Ops));
11299 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
11300 // ones, and then concatenate the result back.
11301 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
11302 EVT VT = Op.getValueType();
11304 assert(VT.is256BitVector() && VT.isInteger() &&
11305 "Unsupported value type for operation");
11307 unsigned NumElems = VT.getVectorNumElements();
11308 DebugLoc dl = Op.getDebugLoc();
11310 // Extract the LHS vectors
11311 SDValue LHS = Op.getOperand(0);
11312 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
11313 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
11315 // Extract the RHS vectors
11316 SDValue RHS = Op.getOperand(1);
11317 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
11318 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
11320 MVT EltVT = VT.getVectorElementType().getSimpleVT();
11321 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
11323 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
11324 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
11325 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
11328 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
11329 assert(Op.getValueType().is256BitVector() &&
11330 Op.getValueType().isInteger() &&
11331 "Only handle AVX 256-bit vector integer operation");
11332 return Lower256IntArith(Op, DAG);
11335 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
11336 assert(Op.getValueType().is256BitVector() &&
11337 Op.getValueType().isInteger() &&
11338 "Only handle AVX 256-bit vector integer operation");
11339 return Lower256IntArith(Op, DAG);
11342 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
11343 SelectionDAG &DAG) {
11344 DebugLoc dl = Op.getDebugLoc();
11345 EVT VT = Op.getValueType();
11347 // Decompose 256-bit ops into smaller 128-bit ops.
11348 if (VT.is256BitVector() && !Subtarget->hasInt256())
11349 return Lower256IntArith(Op, DAG);
11351 SDValue A = Op.getOperand(0);
11352 SDValue B = Op.getOperand(1);
11354 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
11355 if (VT == MVT::v4i32) {
11356 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
11357 "Should not custom lower when pmuldq is available!");
11359 // Extract the odd parts.
11360 const int UnpackMask[] = { 1, -1, 3, -1 };
11361 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
11362 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
11364 // Multiply the even parts.
11365 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
11366 // Now multiply odd parts.
11367 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
11369 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
11370 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
11372 // Merge the two vectors back together with a shuffle. This expands into 2
11374 const int ShufMask[] = { 0, 4, 2, 6 };
11375 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
11378 assert((VT == MVT::v2i64 || VT == MVT::v4i64) &&
11379 "Only know how to lower V2I64/V4I64 multiply");
11381 // Ahi = psrlqi(a, 32);
11382 // Bhi = psrlqi(b, 32);
11384 // AloBlo = pmuludq(a, b);
11385 // AloBhi = pmuludq(a, Bhi);
11386 // AhiBlo = pmuludq(Ahi, b);
11388 // AloBhi = psllqi(AloBhi, 32);
11389 // AhiBlo = psllqi(AhiBlo, 32);
11390 // return AloBlo + AloBhi + AhiBlo;
11392 SDValue ShAmt = DAG.getConstant(32, MVT::i32);
11394 SDValue Ahi = DAG.getNode(X86ISD::VSRLI, dl, VT, A, ShAmt);
11395 SDValue Bhi = DAG.getNode(X86ISD::VSRLI, dl, VT, B, ShAmt);
11397 // Bit cast to 32-bit vectors for MULUDQ
11398 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 : MVT::v8i32;
11399 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
11400 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
11401 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
11402 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
11404 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
11405 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
11406 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
11408 AloBhi = DAG.getNode(X86ISD::VSHLI, dl, VT, AloBhi, ShAmt);
11409 AhiBlo = DAG.getNode(X86ISD::VSHLI, dl, VT, AhiBlo, ShAmt);
11411 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
11412 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
11415 SDValue X86TargetLowering::LowerSDIV(SDValue Op, SelectionDAG &DAG) const {
11416 EVT VT = Op.getValueType();
11417 EVT EltTy = VT.getVectorElementType();
11418 unsigned NumElts = VT.getVectorNumElements();
11419 SDValue N0 = Op.getOperand(0);
11420 DebugLoc dl = Op.getDebugLoc();
11422 // Lower sdiv X, pow2-const.
11423 BuildVectorSDNode *C = dyn_cast<BuildVectorSDNode>(Op.getOperand(1));
11427 APInt SplatValue, SplatUndef;
11428 unsigned MinSplatBits;
11430 if (!C->isConstantSplat(SplatValue, SplatUndef, MinSplatBits, HasAnyUndefs))
11433 if ((SplatValue != 0) &&
11434 (SplatValue.isPowerOf2() || (-SplatValue).isPowerOf2())) {
11435 unsigned lg2 = SplatValue.countTrailingZeros();
11436 // Splat the sign bit.
11437 SDValue Sz = DAG.getConstant(EltTy.getSizeInBits()-1, MVT::i32);
11438 SDValue SGN = getTargetVShiftNode(X86ISD::VSRAI, dl, VT, N0, Sz, DAG);
11439 // Add (N0 < 0) ? abs2 - 1 : 0;
11440 SDValue Amt = DAG.getConstant(EltTy.getSizeInBits() - lg2, MVT::i32);
11441 SDValue SRL = getTargetVShiftNode(X86ISD::VSRLI, dl, VT, SGN, Amt, DAG);
11442 SDValue ADD = DAG.getNode(ISD::ADD, dl, VT, N0, SRL);
11443 SDValue Lg2Amt = DAG.getConstant(lg2, MVT::i32);
11444 SDValue SRA = getTargetVShiftNode(X86ISD::VSRAI, dl, VT, ADD, Lg2Amt, DAG);
11446 // If we're dividing by a positive value, we're done. Otherwise, we must
11447 // negate the result.
11448 if (SplatValue.isNonNegative())
11451 SmallVector<SDValue, 16> V(NumElts, DAG.getConstant(0, EltTy));
11452 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], NumElts);
11453 return DAG.getNode(ISD::SUB, dl, VT, Zero, SRA);
11458 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const {
11460 EVT VT = Op.getValueType();
11461 DebugLoc dl = Op.getDebugLoc();
11462 SDValue R = Op.getOperand(0);
11463 SDValue Amt = Op.getOperand(1);
11465 if (!Subtarget->hasSSE2())
11468 // Optimize shl/srl/sra with constant shift amount.
11469 if (isSplatVector(Amt.getNode())) {
11470 SDValue SclrAmt = Amt->getOperand(0);
11471 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
11472 uint64_t ShiftAmt = C->getZExtValue();
11474 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
11475 (Subtarget->hasInt256() &&
11476 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16))) {
11477 if (Op.getOpcode() == ISD::SHL)
11478 return DAG.getNode(X86ISD::VSHLI, dl, VT, R,
11479 DAG.getConstant(ShiftAmt, MVT::i32));
11480 if (Op.getOpcode() == ISD::SRL)
11481 return DAG.getNode(X86ISD::VSRLI, dl, VT, R,
11482 DAG.getConstant(ShiftAmt, MVT::i32));
11483 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
11484 return DAG.getNode(X86ISD::VSRAI, dl, VT, R,
11485 DAG.getConstant(ShiftAmt, MVT::i32));
11488 if (VT == MVT::v16i8) {
11489 if (Op.getOpcode() == ISD::SHL) {
11490 // Make a large shift.
11491 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, R,
11492 DAG.getConstant(ShiftAmt, MVT::i32));
11493 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
11494 // Zero out the rightmost bits.
11495 SmallVector<SDValue, 16> V(16,
11496 DAG.getConstant(uint8_t(-1U << ShiftAmt),
11498 return DAG.getNode(ISD::AND, dl, VT, SHL,
11499 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
11501 if (Op.getOpcode() == ISD::SRL) {
11502 // Make a large shift.
11503 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v8i16, R,
11504 DAG.getConstant(ShiftAmt, MVT::i32));
11505 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
11506 // Zero out the leftmost bits.
11507 SmallVector<SDValue, 16> V(16,
11508 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
11510 return DAG.getNode(ISD::AND, dl, VT, SRL,
11511 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
11513 if (Op.getOpcode() == ISD::SRA) {
11514 if (ShiftAmt == 7) {
11515 // R s>> 7 === R s< 0
11516 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
11517 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
11520 // R s>> a === ((R u>> a) ^ m) - m
11521 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
11522 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
11524 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16);
11525 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
11526 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
11529 llvm_unreachable("Unknown shift opcode.");
11532 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
11533 if (Op.getOpcode() == ISD::SHL) {
11534 // Make a large shift.
11535 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v16i16, R,
11536 DAG.getConstant(ShiftAmt, MVT::i32));
11537 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
11538 // Zero out the rightmost bits.
11539 SmallVector<SDValue, 32> V(32,
11540 DAG.getConstant(uint8_t(-1U << ShiftAmt),
11542 return DAG.getNode(ISD::AND, dl, VT, SHL,
11543 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
11545 if (Op.getOpcode() == ISD::SRL) {
11546 // Make a large shift.
11547 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v16i16, R,
11548 DAG.getConstant(ShiftAmt, MVT::i32));
11549 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
11550 // Zero out the leftmost bits.
11551 SmallVector<SDValue, 32> V(32,
11552 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
11554 return DAG.getNode(ISD::AND, dl, VT, SRL,
11555 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
11557 if (Op.getOpcode() == ISD::SRA) {
11558 if (ShiftAmt == 7) {
11559 // R s>> 7 === R s< 0
11560 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
11561 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
11564 // R s>> a === ((R u>> a) ^ m) - m
11565 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
11566 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
11568 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32);
11569 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
11570 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
11573 llvm_unreachable("Unknown shift opcode.");
11578 // Lower SHL with variable shift amount.
11579 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
11580 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
11582 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
11583 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
11584 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
11585 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
11587 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
11588 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
11591 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
11592 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
11594 // Turn 'a' into a mask suitable for VSELECT
11595 SDValue VSelM = DAG.getConstant(0x80, VT);
11596 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
11597 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
11599 SDValue CM1 = DAG.getConstant(0x0f, VT);
11600 SDValue CM2 = DAG.getConstant(0x3f, VT);
11602 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
11603 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
11604 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M,
11605 DAG.getConstant(4, MVT::i32), DAG);
11606 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
11607 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
11610 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
11611 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
11612 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
11614 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
11615 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
11616 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M,
11617 DAG.getConstant(2, MVT::i32), DAG);
11618 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
11619 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
11622 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
11623 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
11624 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
11626 // return VSELECT(r, r+r, a);
11627 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
11628 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
11632 // Decompose 256-bit shifts into smaller 128-bit shifts.
11633 if (VT.is256BitVector()) {
11634 unsigned NumElems = VT.getVectorNumElements();
11635 MVT EltVT = VT.getVectorElementType().getSimpleVT();
11636 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
11638 // Extract the two vectors
11639 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
11640 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
11642 // Recreate the shift amount vectors
11643 SDValue Amt1, Amt2;
11644 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
11645 // Constant shift amount
11646 SmallVector<SDValue, 4> Amt1Csts;
11647 SmallVector<SDValue, 4> Amt2Csts;
11648 for (unsigned i = 0; i != NumElems/2; ++i)
11649 Amt1Csts.push_back(Amt->getOperand(i));
11650 for (unsigned i = NumElems/2; i != NumElems; ++i)
11651 Amt2Csts.push_back(Amt->getOperand(i));
11653 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
11654 &Amt1Csts[0], NumElems/2);
11655 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
11656 &Amt2Csts[0], NumElems/2);
11658 // Variable shift amount
11659 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
11660 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
11663 // Issue new vector shifts for the smaller types
11664 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
11665 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
11667 // Concatenate the result back
11668 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
11674 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
11675 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
11676 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
11677 // looks for this combo and may remove the "setcc" instruction if the "setcc"
11678 // has only one use.
11679 SDNode *N = Op.getNode();
11680 SDValue LHS = N->getOperand(0);
11681 SDValue RHS = N->getOperand(1);
11682 unsigned BaseOp = 0;
11684 DebugLoc DL = Op.getDebugLoc();
11685 switch (Op.getOpcode()) {
11686 default: llvm_unreachable("Unknown ovf instruction!");
11688 // A subtract of one will be selected as a INC. Note that INC doesn't
11689 // set CF, so we can't do this for UADDO.
11690 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
11692 BaseOp = X86ISD::INC;
11693 Cond = X86::COND_O;
11696 BaseOp = X86ISD::ADD;
11697 Cond = X86::COND_O;
11700 BaseOp = X86ISD::ADD;
11701 Cond = X86::COND_B;
11704 // A subtract of one will be selected as a DEC. Note that DEC doesn't
11705 // set CF, so we can't do this for USUBO.
11706 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
11708 BaseOp = X86ISD::DEC;
11709 Cond = X86::COND_O;
11712 BaseOp = X86ISD::SUB;
11713 Cond = X86::COND_O;
11716 BaseOp = X86ISD::SUB;
11717 Cond = X86::COND_B;
11720 BaseOp = X86ISD::SMUL;
11721 Cond = X86::COND_O;
11723 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
11724 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
11726 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
11729 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
11730 DAG.getConstant(X86::COND_O, MVT::i32),
11731 SDValue(Sum.getNode(), 2));
11733 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
11737 // Also sets EFLAGS.
11738 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
11739 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
11742 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
11743 DAG.getConstant(Cond, MVT::i32),
11744 SDValue(Sum.getNode(), 1));
11746 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
11749 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
11750 SelectionDAG &DAG) const {
11751 DebugLoc dl = Op.getDebugLoc();
11752 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
11753 EVT VT = Op.getValueType();
11755 if (!Subtarget->hasSSE2() || !VT.isVector())
11758 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
11759 ExtraVT.getScalarType().getSizeInBits();
11760 SDValue ShAmt = DAG.getConstant(BitsDiff, MVT::i32);
11762 switch (VT.getSimpleVT().SimpleTy) {
11763 default: return SDValue();
11766 if (!Subtarget->hasFp256())
11768 if (!Subtarget->hasInt256()) {
11769 // needs to be split
11770 unsigned NumElems = VT.getVectorNumElements();
11772 // Extract the LHS vectors
11773 SDValue LHS = Op.getOperand(0);
11774 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
11775 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
11777 MVT EltVT = VT.getVectorElementType().getSimpleVT();
11778 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
11780 EVT ExtraEltVT = ExtraVT.getVectorElementType();
11781 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
11782 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
11784 SDValue Extra = DAG.getValueType(ExtraVT);
11786 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
11787 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
11789 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
11794 SDValue Tmp1 = getTargetVShiftNode(X86ISD::VSHLI, dl, VT,
11795 Op.getOperand(0), ShAmt, DAG);
11796 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, Tmp1, ShAmt, DAG);
11801 static SDValue LowerMEMBARRIER(SDValue Op, const X86Subtarget *Subtarget,
11802 SelectionDAG &DAG) {
11803 DebugLoc dl = Op.getDebugLoc();
11805 // Go ahead and emit the fence on x86-64 even if we asked for no-sse2.
11806 // There isn't any reason to disable it if the target processor supports it.
11807 if (!Subtarget->hasSSE2() && !Subtarget->is64Bit()) {
11808 SDValue Chain = Op.getOperand(0);
11809 SDValue Zero = DAG.getConstant(0, MVT::i32);
11811 DAG.getRegister(X86::ESP, MVT::i32), // Base
11812 DAG.getTargetConstant(1, MVT::i8), // Scale
11813 DAG.getRegister(0, MVT::i32), // Index
11814 DAG.getTargetConstant(0, MVT::i32), // Disp
11815 DAG.getRegister(0, MVT::i32), // Segment.
11820 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
11821 array_lengthof(Ops));
11822 return SDValue(Res, 0);
11825 unsigned isDev = cast<ConstantSDNode>(Op.getOperand(5))->getZExtValue();
11827 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
11829 unsigned Op1 = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11830 unsigned Op2 = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
11831 unsigned Op3 = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
11832 unsigned Op4 = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
11834 // def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
11835 if (!Op1 && !Op2 && !Op3 && Op4)
11836 return DAG.getNode(X86ISD::SFENCE, dl, MVT::Other, Op.getOperand(0));
11838 // def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
11839 if (Op1 && !Op2 && !Op3 && !Op4)
11840 return DAG.getNode(X86ISD::LFENCE, dl, MVT::Other, Op.getOperand(0));
11842 // def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm), (i8 1)),
11844 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
11847 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
11848 SelectionDAG &DAG) {
11849 DebugLoc dl = Op.getDebugLoc();
11850 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
11851 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
11852 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
11853 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
11855 // The only fence that needs an instruction is a sequentially-consistent
11856 // cross-thread fence.
11857 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
11858 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
11859 // no-sse2). There isn't any reason to disable it if the target processor
11861 if (Subtarget->hasSSE2() || Subtarget->is64Bit())
11862 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
11864 SDValue Chain = Op.getOperand(0);
11865 SDValue Zero = DAG.getConstant(0, MVT::i32);
11867 DAG.getRegister(X86::ESP, MVT::i32), // Base
11868 DAG.getTargetConstant(1, MVT::i8), // Scale
11869 DAG.getRegister(0, MVT::i32), // Index
11870 DAG.getTargetConstant(0, MVT::i32), // Disp
11871 DAG.getRegister(0, MVT::i32), // Segment.
11876 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
11877 array_lengthof(Ops));
11878 return SDValue(Res, 0);
11881 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
11882 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
11885 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
11886 SelectionDAG &DAG) {
11887 EVT T = Op.getValueType();
11888 DebugLoc DL = Op.getDebugLoc();
11891 switch(T.getSimpleVT().SimpleTy) {
11892 default: llvm_unreachable("Invalid value type!");
11893 case MVT::i8: Reg = X86::AL; size = 1; break;
11894 case MVT::i16: Reg = X86::AX; size = 2; break;
11895 case MVT::i32: Reg = X86::EAX; size = 4; break;
11897 assert(Subtarget->is64Bit() && "Node not type legal!");
11898 Reg = X86::RAX; size = 8;
11901 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
11902 Op.getOperand(2), SDValue());
11903 SDValue Ops[] = { cpIn.getValue(0),
11906 DAG.getTargetConstant(size, MVT::i8),
11907 cpIn.getValue(1) };
11908 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
11909 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
11910 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
11913 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
11917 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
11918 SelectionDAG &DAG) {
11919 assert(Subtarget->is64Bit() && "Result not type legalized?");
11920 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
11921 SDValue TheChain = Op.getOperand(0);
11922 DebugLoc dl = Op.getDebugLoc();
11923 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
11924 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
11925 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
11927 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
11928 DAG.getConstant(32, MVT::i8));
11930 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
11933 return DAG.getMergeValues(Ops, 2, dl);
11936 SDValue X86TargetLowering::LowerBITCAST(SDValue Op, SelectionDAG &DAG) const {
11937 EVT SrcVT = Op.getOperand(0).getValueType();
11938 EVT DstVT = Op.getValueType();
11939 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
11940 Subtarget->hasMMX() && "Unexpected custom BITCAST");
11941 assert((DstVT == MVT::i64 ||
11942 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
11943 "Unexpected custom BITCAST");
11944 // i64 <=> MMX conversions are Legal.
11945 if (SrcVT==MVT::i64 && DstVT.isVector())
11947 if (DstVT==MVT::i64 && SrcVT.isVector())
11949 // MMX <=> MMX conversions are Legal.
11950 if (SrcVT.isVector() && DstVT.isVector())
11952 // All other conversions need to be expanded.
11956 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
11957 SDNode *Node = Op.getNode();
11958 DebugLoc dl = Node->getDebugLoc();
11959 EVT T = Node->getValueType(0);
11960 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
11961 DAG.getConstant(0, T), Node->getOperand(2));
11962 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
11963 cast<AtomicSDNode>(Node)->getMemoryVT(),
11964 Node->getOperand(0),
11965 Node->getOperand(1), negOp,
11966 cast<AtomicSDNode>(Node)->getSrcValue(),
11967 cast<AtomicSDNode>(Node)->getAlignment(),
11968 cast<AtomicSDNode>(Node)->getOrdering(),
11969 cast<AtomicSDNode>(Node)->getSynchScope());
11972 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
11973 SDNode *Node = Op.getNode();
11974 DebugLoc dl = Node->getDebugLoc();
11975 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
11977 // Convert seq_cst store -> xchg
11978 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
11979 // FIXME: On 32-bit, store -> fist or movq would be more efficient
11980 // (The only way to get a 16-byte store is cmpxchg16b)
11981 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
11982 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
11983 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
11984 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
11985 cast<AtomicSDNode>(Node)->getMemoryVT(),
11986 Node->getOperand(0),
11987 Node->getOperand(1), Node->getOperand(2),
11988 cast<AtomicSDNode>(Node)->getMemOperand(),
11989 cast<AtomicSDNode>(Node)->getOrdering(),
11990 cast<AtomicSDNode>(Node)->getSynchScope());
11991 return Swap.getValue(1);
11993 // Other atomic stores have a simple pattern.
11997 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
11998 EVT VT = Op.getNode()->getValueType(0);
12000 // Let legalize expand this if it isn't a legal type yet.
12001 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
12004 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
12007 bool ExtraOp = false;
12008 switch (Op.getOpcode()) {
12009 default: llvm_unreachable("Invalid code");
12010 case ISD::ADDC: Opc = X86ISD::ADD; break;
12011 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
12012 case ISD::SUBC: Opc = X86ISD::SUB; break;
12013 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
12017 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
12019 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
12020 Op.getOperand(1), Op.getOperand(2));
12023 SDValue X86TargetLowering::LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const {
12024 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
12026 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
12027 // which returns the values in two XMM registers.
12028 DebugLoc dl = Op.getDebugLoc();
12029 SDValue Arg = Op.getOperand(0);
12030 EVT ArgVT = Arg.getValueType();
12031 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
12034 ArgListEntry Entry;
12038 Entry.isSExt = false;
12039 Entry.isZExt = false;
12040 Args.push_back(Entry);
12042 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
12043 // the small struct {f32, f32} is returned in (eax, edx). For f64,
12044 // the results are returned via SRet in memory.
12045 const char *LibcallName = (ArgVT == MVT::f64)
12046 ? "__sincos_stret" : "__sincosf_stret";
12047 SDValue Callee = DAG.getExternalSymbol(LibcallName, getPointerTy());
12049 StructType *RetTy = StructType::get(ArgTy, ArgTy, NULL);
12051 CallLoweringInfo CLI(DAG.getEntryNode(), RetTy,
12052 false, false, false, false, 0,
12053 CallingConv::C, /*isTaillCall=*/false,
12054 /*doesNotRet=*/false, /*isReturnValueUsed*/true,
12055 Callee, Args, DAG, dl);
12056 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
12057 return CallResult.first;
12060 /// LowerOperation - Provide custom lowering hooks for some operations.
12062 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
12063 switch (Op.getOpcode()) {
12064 default: llvm_unreachable("Should not custom lower this!");
12065 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
12066 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, Subtarget, DAG);
12067 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
12068 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op, Subtarget, DAG);
12069 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
12070 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
12071 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
12072 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
12073 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
12074 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
12075 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
12076 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
12077 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
12078 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
12079 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
12080 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
12081 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
12082 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
12083 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
12084 case ISD::SHL_PARTS:
12085 case ISD::SRA_PARTS:
12086 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
12087 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
12088 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
12089 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
12090 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, DAG);
12091 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, DAG);
12092 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, DAG);
12093 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
12094 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
12095 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
12096 case ISD::FABS: return LowerFABS(Op, DAG);
12097 case ISD::FNEG: return LowerFNEG(Op, DAG);
12098 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
12099 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
12100 case ISD::SETCC: return LowerSETCC(Op, DAG);
12101 case ISD::SELECT: return LowerSELECT(Op, DAG);
12102 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
12103 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
12104 case ISD::VASTART: return LowerVASTART(Op, DAG);
12105 case ISD::VAARG: return LowerVAARG(Op, DAG);
12106 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
12107 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
12108 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, DAG);
12109 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
12110 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
12111 case ISD::FRAME_TO_ARGS_OFFSET:
12112 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
12113 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
12114 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
12115 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
12116 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
12117 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
12118 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
12119 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
12120 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
12121 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
12122 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
12123 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
12126 case ISD::SHL: return LowerShift(Op, DAG);
12132 case ISD::UMULO: return LowerXALUO(Op, DAG);
12133 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
12134 case ISD::BITCAST: return LowerBITCAST(Op, DAG);
12138 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
12139 case ISD::ADD: return LowerADD(Op, DAG);
12140 case ISD::SUB: return LowerSUB(Op, DAG);
12141 case ISD::SDIV: return LowerSDIV(Op, DAG);
12142 case ISD::FSINCOS: return LowerFSINCOS(Op, DAG);
12146 static void ReplaceATOMIC_LOAD(SDNode *Node,
12147 SmallVectorImpl<SDValue> &Results,
12148 SelectionDAG &DAG) {
12149 DebugLoc dl = Node->getDebugLoc();
12150 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
12152 // Convert wide load -> cmpxchg8b/cmpxchg16b
12153 // FIXME: On 32-bit, load -> fild or movq would be more efficient
12154 // (The only way to get a 16-byte load is cmpxchg16b)
12155 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment.
12156 SDValue Zero = DAG.getConstant(0, VT);
12157 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT,
12158 Node->getOperand(0),
12159 Node->getOperand(1), Zero, Zero,
12160 cast<AtomicSDNode>(Node)->getMemOperand(),
12161 cast<AtomicSDNode>(Node)->getOrdering(),
12162 cast<AtomicSDNode>(Node)->getSynchScope());
12163 Results.push_back(Swap.getValue(0));
12164 Results.push_back(Swap.getValue(1));
12168 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
12169 SelectionDAG &DAG, unsigned NewOp) {
12170 DebugLoc dl = Node->getDebugLoc();
12171 assert (Node->getValueType(0) == MVT::i64 &&
12172 "Only know how to expand i64 atomics");
12174 SDValue Chain = Node->getOperand(0);
12175 SDValue In1 = Node->getOperand(1);
12176 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
12177 Node->getOperand(2), DAG.getIntPtrConstant(0));
12178 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
12179 Node->getOperand(2), DAG.getIntPtrConstant(1));
12180 SDValue Ops[] = { Chain, In1, In2L, In2H };
12181 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
12183 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64,
12184 cast<MemSDNode>(Node)->getMemOperand());
12185 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
12186 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
12187 Results.push_back(Result.getValue(2));
12190 /// ReplaceNodeResults - Replace a node with an illegal result type
12191 /// with a new node built out of custom code.
12192 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
12193 SmallVectorImpl<SDValue>&Results,
12194 SelectionDAG &DAG) const {
12195 DebugLoc dl = N->getDebugLoc();
12196 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12197 switch (N->getOpcode()) {
12199 llvm_unreachable("Do not know how to custom type legalize this operation!");
12200 case ISD::SIGN_EXTEND_INREG:
12205 // We don't want to expand or promote these.
12207 case ISD::FP_TO_SINT:
12208 case ISD::FP_TO_UINT: {
12209 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
12211 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
12214 std::pair<SDValue,SDValue> Vals =
12215 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
12216 SDValue FIST = Vals.first, StackSlot = Vals.second;
12217 if (FIST.getNode() != 0) {
12218 EVT VT = N->getValueType(0);
12219 // Return a load from the stack slot.
12220 if (StackSlot.getNode() != 0)
12221 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
12222 MachinePointerInfo(),
12223 false, false, false, 0));
12225 Results.push_back(FIST);
12229 case ISD::UINT_TO_FP: {
12230 if (N->getOperand(0).getValueType() != MVT::v2i32 &&
12231 N->getValueType(0) != MVT::v2f32)
12233 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
12235 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
12237 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
12238 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
12239 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
12240 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
12241 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
12242 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
12245 case ISD::FP_ROUND: {
12246 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
12248 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
12249 Results.push_back(V);
12252 case ISD::READCYCLECOUNTER: {
12253 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
12254 SDValue TheChain = N->getOperand(0);
12255 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
12256 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
12258 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
12260 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
12261 SDValue Ops[] = { eax, edx };
12262 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
12263 Results.push_back(edx.getValue(1));
12266 case ISD::ATOMIC_CMP_SWAP: {
12267 EVT T = N->getValueType(0);
12268 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
12269 bool Regs64bit = T == MVT::i128;
12270 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
12271 SDValue cpInL, cpInH;
12272 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
12273 DAG.getConstant(0, HalfT));
12274 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
12275 DAG.getConstant(1, HalfT));
12276 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
12277 Regs64bit ? X86::RAX : X86::EAX,
12279 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
12280 Regs64bit ? X86::RDX : X86::EDX,
12281 cpInH, cpInL.getValue(1));
12282 SDValue swapInL, swapInH;
12283 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
12284 DAG.getConstant(0, HalfT));
12285 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
12286 DAG.getConstant(1, HalfT));
12287 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
12288 Regs64bit ? X86::RBX : X86::EBX,
12289 swapInL, cpInH.getValue(1));
12290 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
12291 Regs64bit ? X86::RCX : X86::ECX,
12292 swapInH, swapInL.getValue(1));
12293 SDValue Ops[] = { swapInH.getValue(0),
12295 swapInH.getValue(1) };
12296 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
12297 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
12298 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
12299 X86ISD::LCMPXCHG8_DAG;
12300 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys,
12302 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
12303 Regs64bit ? X86::RAX : X86::EAX,
12304 HalfT, Result.getValue(1));
12305 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
12306 Regs64bit ? X86::RDX : X86::EDX,
12307 HalfT, cpOutL.getValue(2));
12308 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
12309 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF, 2));
12310 Results.push_back(cpOutH.getValue(1));
12313 case ISD::ATOMIC_LOAD_ADD:
12314 case ISD::ATOMIC_LOAD_AND:
12315 case ISD::ATOMIC_LOAD_NAND:
12316 case ISD::ATOMIC_LOAD_OR:
12317 case ISD::ATOMIC_LOAD_SUB:
12318 case ISD::ATOMIC_LOAD_XOR:
12319 case ISD::ATOMIC_LOAD_MAX:
12320 case ISD::ATOMIC_LOAD_MIN:
12321 case ISD::ATOMIC_LOAD_UMAX:
12322 case ISD::ATOMIC_LOAD_UMIN:
12323 case ISD::ATOMIC_SWAP: {
12325 switch (N->getOpcode()) {
12326 default: llvm_unreachable("Unexpected opcode");
12327 case ISD::ATOMIC_LOAD_ADD:
12328 Opc = X86ISD::ATOMADD64_DAG;
12330 case ISD::ATOMIC_LOAD_AND:
12331 Opc = X86ISD::ATOMAND64_DAG;
12333 case ISD::ATOMIC_LOAD_NAND:
12334 Opc = X86ISD::ATOMNAND64_DAG;
12336 case ISD::ATOMIC_LOAD_OR:
12337 Opc = X86ISD::ATOMOR64_DAG;
12339 case ISD::ATOMIC_LOAD_SUB:
12340 Opc = X86ISD::ATOMSUB64_DAG;
12342 case ISD::ATOMIC_LOAD_XOR:
12343 Opc = X86ISD::ATOMXOR64_DAG;
12345 case ISD::ATOMIC_LOAD_MAX:
12346 Opc = X86ISD::ATOMMAX64_DAG;
12348 case ISD::ATOMIC_LOAD_MIN:
12349 Opc = X86ISD::ATOMMIN64_DAG;
12351 case ISD::ATOMIC_LOAD_UMAX:
12352 Opc = X86ISD::ATOMUMAX64_DAG;
12354 case ISD::ATOMIC_LOAD_UMIN:
12355 Opc = X86ISD::ATOMUMIN64_DAG;
12357 case ISD::ATOMIC_SWAP:
12358 Opc = X86ISD::ATOMSWAP64_DAG;
12361 ReplaceATOMIC_BINARY_64(N, Results, DAG, Opc);
12364 case ISD::ATOMIC_LOAD:
12365 ReplaceATOMIC_LOAD(N, Results, DAG);
12369 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
12371 default: return NULL;
12372 case X86ISD::BSF: return "X86ISD::BSF";
12373 case X86ISD::BSR: return "X86ISD::BSR";
12374 case X86ISD::SHLD: return "X86ISD::SHLD";
12375 case X86ISD::SHRD: return "X86ISD::SHRD";
12376 case X86ISD::FAND: return "X86ISD::FAND";
12377 case X86ISD::FOR: return "X86ISD::FOR";
12378 case X86ISD::FXOR: return "X86ISD::FXOR";
12379 case X86ISD::FSRL: return "X86ISD::FSRL";
12380 case X86ISD::FILD: return "X86ISD::FILD";
12381 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
12382 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
12383 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
12384 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
12385 case X86ISD::FLD: return "X86ISD::FLD";
12386 case X86ISD::FST: return "X86ISD::FST";
12387 case X86ISD::CALL: return "X86ISD::CALL";
12388 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
12389 case X86ISD::BT: return "X86ISD::BT";
12390 case X86ISD::CMP: return "X86ISD::CMP";
12391 case X86ISD::COMI: return "X86ISD::COMI";
12392 case X86ISD::UCOMI: return "X86ISD::UCOMI";
12393 case X86ISD::SETCC: return "X86ISD::SETCC";
12394 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
12395 case X86ISD::FSETCCsd: return "X86ISD::FSETCCsd";
12396 case X86ISD::FSETCCss: return "X86ISD::FSETCCss";
12397 case X86ISD::CMOV: return "X86ISD::CMOV";
12398 case X86ISD::BRCOND: return "X86ISD::BRCOND";
12399 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
12400 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
12401 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
12402 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
12403 case X86ISD::Wrapper: return "X86ISD::Wrapper";
12404 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
12405 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
12406 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
12407 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
12408 case X86ISD::PINSRB: return "X86ISD::PINSRB";
12409 case X86ISD::PINSRW: return "X86ISD::PINSRW";
12410 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
12411 case X86ISD::ANDNP: return "X86ISD::ANDNP";
12412 case X86ISD::PSIGN: return "X86ISD::PSIGN";
12413 case X86ISD::BLENDV: return "X86ISD::BLENDV";
12414 case X86ISD::BLENDI: return "X86ISD::BLENDI";
12415 case X86ISD::SUBUS: return "X86ISD::SUBUS";
12416 case X86ISD::HADD: return "X86ISD::HADD";
12417 case X86ISD::HSUB: return "X86ISD::HSUB";
12418 case X86ISD::FHADD: return "X86ISD::FHADD";
12419 case X86ISD::FHSUB: return "X86ISD::FHSUB";
12420 case X86ISD::UMAX: return "X86ISD::UMAX";
12421 case X86ISD::UMIN: return "X86ISD::UMIN";
12422 case X86ISD::SMAX: return "X86ISD::SMAX";
12423 case X86ISD::SMIN: return "X86ISD::SMIN";
12424 case X86ISD::FMAX: return "X86ISD::FMAX";
12425 case X86ISD::FMIN: return "X86ISD::FMIN";
12426 case X86ISD::FMAXC: return "X86ISD::FMAXC";
12427 case X86ISD::FMINC: return "X86ISD::FMINC";
12428 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
12429 case X86ISD::FRCP: return "X86ISD::FRCP";
12430 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
12431 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
12432 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
12433 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
12434 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
12435 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
12436 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
12437 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
12438 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
12439 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
12440 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
12441 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
12442 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
12443 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
12444 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
12445 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
12446 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
12447 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
12448 case X86ISD::VSEXT_MOVL: return "X86ISD::VSEXT_MOVL";
12449 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
12450 case X86ISD::VZEXT: return "X86ISD::VZEXT";
12451 case X86ISD::VSEXT: return "X86ISD::VSEXT";
12452 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
12453 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
12454 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
12455 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
12456 case X86ISD::VSHL: return "X86ISD::VSHL";
12457 case X86ISD::VSRL: return "X86ISD::VSRL";
12458 case X86ISD::VSRA: return "X86ISD::VSRA";
12459 case X86ISD::VSHLI: return "X86ISD::VSHLI";
12460 case X86ISD::VSRLI: return "X86ISD::VSRLI";
12461 case X86ISD::VSRAI: return "X86ISD::VSRAI";
12462 case X86ISD::CMPP: return "X86ISD::CMPP";
12463 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
12464 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
12465 case X86ISD::ADD: return "X86ISD::ADD";
12466 case X86ISD::SUB: return "X86ISD::SUB";
12467 case X86ISD::ADC: return "X86ISD::ADC";
12468 case X86ISD::SBB: return "X86ISD::SBB";
12469 case X86ISD::SMUL: return "X86ISD::SMUL";
12470 case X86ISD::UMUL: return "X86ISD::UMUL";
12471 case X86ISD::INC: return "X86ISD::INC";
12472 case X86ISD::DEC: return "X86ISD::DEC";
12473 case X86ISD::OR: return "X86ISD::OR";
12474 case X86ISD::XOR: return "X86ISD::XOR";
12475 case X86ISD::AND: return "X86ISD::AND";
12476 case X86ISD::BLSI: return "X86ISD::BLSI";
12477 case X86ISD::BLSMSK: return "X86ISD::BLSMSK";
12478 case X86ISD::BLSR: return "X86ISD::BLSR";
12479 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
12480 case X86ISD::PTEST: return "X86ISD::PTEST";
12481 case X86ISD::TESTP: return "X86ISD::TESTP";
12482 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
12483 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
12484 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
12485 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
12486 case X86ISD::SHUFP: return "X86ISD::SHUFP";
12487 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
12488 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
12489 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
12490 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
12491 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
12492 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
12493 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
12494 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
12495 case X86ISD::MOVSD: return "X86ISD::MOVSD";
12496 case X86ISD::MOVSS: return "X86ISD::MOVSS";
12497 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
12498 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
12499 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
12500 case X86ISD::VPERMILP: return "X86ISD::VPERMILP";
12501 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
12502 case X86ISD::VPERMV: return "X86ISD::VPERMV";
12503 case X86ISD::VPERMI: return "X86ISD::VPERMI";
12504 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
12505 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
12506 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
12507 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
12508 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
12509 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
12510 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
12511 case X86ISD::SAHF: return "X86ISD::SAHF";
12512 case X86ISD::RDRAND: return "X86ISD::RDRAND";
12513 case X86ISD::FMADD: return "X86ISD::FMADD";
12514 case X86ISD::FMSUB: return "X86ISD::FMSUB";
12515 case X86ISD::FNMADD: return "X86ISD::FNMADD";
12516 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
12517 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
12518 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
12519 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
12520 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
12524 // isLegalAddressingMode - Return true if the addressing mode represented
12525 // by AM is legal for this target, for a load/store of the specified type.
12526 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
12528 // X86 supports extremely general addressing modes.
12529 CodeModel::Model M = getTargetMachine().getCodeModel();
12530 Reloc::Model R = getTargetMachine().getRelocationModel();
12532 // X86 allows a sign-extended 32-bit immediate field as a displacement.
12533 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
12538 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
12540 // If a reference to this global requires an extra load, we can't fold it.
12541 if (isGlobalStubReference(GVFlags))
12544 // If BaseGV requires a register for the PIC base, we cannot also have a
12545 // BaseReg specified.
12546 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
12549 // If lower 4G is not available, then we must use rip-relative addressing.
12550 if ((M != CodeModel::Small || R != Reloc::Static) &&
12551 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
12555 switch (AM.Scale) {
12561 // These scales always work.
12566 // These scales are formed with basereg+scalereg. Only accept if there is
12571 default: // Other stuff never works.
12578 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
12579 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
12581 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
12582 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
12583 return NumBits1 > NumBits2;
12586 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
12587 return isInt<32>(Imm);
12590 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
12591 // Can also use sub to handle negated immediates.
12592 return isInt<32>(Imm);
12595 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
12596 if (!VT1.isInteger() || !VT2.isInteger())
12598 unsigned NumBits1 = VT1.getSizeInBits();
12599 unsigned NumBits2 = VT2.getSizeInBits();
12600 return NumBits1 > NumBits2;
12603 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
12604 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
12605 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
12608 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
12609 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
12610 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
12613 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
12614 EVT VT1 = Val.getValueType();
12615 if (isZExtFree(VT1, VT2))
12618 if (Val.getOpcode() != ISD::LOAD)
12621 if (!VT1.isSimple() || !VT1.isInteger() ||
12622 !VT2.isSimple() || !VT2.isInteger())
12625 switch (VT1.getSimpleVT().SimpleTy) {
12630 // X86 has 8, 16, and 32-bit zero-extending loads.
12637 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
12638 // i16 instructions are longer (0x66 prefix) and potentially slower.
12639 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
12642 /// isShuffleMaskLegal - Targets can use this to indicate that they only
12643 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
12644 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
12645 /// are assumed to be legal.
12647 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
12649 // Very little shuffling can be done for 64-bit vectors right now.
12650 if (VT.getSizeInBits() == 64)
12653 // FIXME: pshufb, blends, shifts.
12654 return (VT.getVectorNumElements() == 2 ||
12655 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
12656 isMOVLMask(M, VT) ||
12657 isSHUFPMask(M, VT, Subtarget->hasFp256()) ||
12658 isPSHUFDMask(M, VT) ||
12659 isPSHUFHWMask(M, VT, Subtarget->hasInt256()) ||
12660 isPSHUFLWMask(M, VT, Subtarget->hasInt256()) ||
12661 isPALIGNRMask(M, VT, Subtarget) ||
12662 isUNPCKLMask(M, VT, Subtarget->hasInt256()) ||
12663 isUNPCKHMask(M, VT, Subtarget->hasInt256()) ||
12664 isUNPCKL_v_undef_Mask(M, VT, Subtarget->hasInt256()) ||
12665 isUNPCKH_v_undef_Mask(M, VT, Subtarget->hasInt256()));
12669 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
12671 unsigned NumElts = VT.getVectorNumElements();
12672 // FIXME: This collection of masks seems suspect.
12675 if (NumElts == 4 && VT.is128BitVector()) {
12676 return (isMOVLMask(Mask, VT) ||
12677 isCommutedMOVLMask(Mask, VT, true) ||
12678 isSHUFPMask(Mask, VT, Subtarget->hasFp256()) ||
12679 isSHUFPMask(Mask, VT, Subtarget->hasFp256(), /* Commuted */ true));
12684 //===----------------------------------------------------------------------===//
12685 // X86 Scheduler Hooks
12686 //===----------------------------------------------------------------------===//
12688 /// Utility function to emit xbegin specifying the start of an RTM region.
12689 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
12690 const TargetInstrInfo *TII) {
12691 DebugLoc DL = MI->getDebugLoc();
12693 const BasicBlock *BB = MBB->getBasicBlock();
12694 MachineFunction::iterator I = MBB;
12697 // For the v = xbegin(), we generate
12708 MachineBasicBlock *thisMBB = MBB;
12709 MachineFunction *MF = MBB->getParent();
12710 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
12711 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
12712 MF->insert(I, mainMBB);
12713 MF->insert(I, sinkMBB);
12715 // Transfer the remainder of BB and its successor edges to sinkMBB.
12716 sinkMBB->splice(sinkMBB->begin(), MBB,
12717 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
12718 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
12722 // # fallthrough to mainMBB
12723 // # abortion to sinkMBB
12724 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
12725 thisMBB->addSuccessor(mainMBB);
12726 thisMBB->addSuccessor(sinkMBB);
12730 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
12731 mainMBB->addSuccessor(sinkMBB);
12734 // EAX is live into the sinkMBB
12735 sinkMBB->addLiveIn(X86::EAX);
12736 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
12737 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
12740 MI->eraseFromParent();
12744 // Get CMPXCHG opcode for the specified data type.
12745 static unsigned getCmpXChgOpcode(EVT VT) {
12746 switch (VT.getSimpleVT().SimpleTy) {
12747 case MVT::i8: return X86::LCMPXCHG8;
12748 case MVT::i16: return X86::LCMPXCHG16;
12749 case MVT::i32: return X86::LCMPXCHG32;
12750 case MVT::i64: return X86::LCMPXCHG64;
12754 llvm_unreachable("Invalid operand size!");
12757 // Get LOAD opcode for the specified data type.
12758 static unsigned getLoadOpcode(EVT VT) {
12759 switch (VT.getSimpleVT().SimpleTy) {
12760 case MVT::i8: return X86::MOV8rm;
12761 case MVT::i16: return X86::MOV16rm;
12762 case MVT::i32: return X86::MOV32rm;
12763 case MVT::i64: return X86::MOV64rm;
12767 llvm_unreachable("Invalid operand size!");
12770 // Get opcode of the non-atomic one from the specified atomic instruction.
12771 static unsigned getNonAtomicOpcode(unsigned Opc) {
12773 case X86::ATOMAND8: return X86::AND8rr;
12774 case X86::ATOMAND16: return X86::AND16rr;
12775 case X86::ATOMAND32: return X86::AND32rr;
12776 case X86::ATOMAND64: return X86::AND64rr;
12777 case X86::ATOMOR8: return X86::OR8rr;
12778 case X86::ATOMOR16: return X86::OR16rr;
12779 case X86::ATOMOR32: return X86::OR32rr;
12780 case X86::ATOMOR64: return X86::OR64rr;
12781 case X86::ATOMXOR8: return X86::XOR8rr;
12782 case X86::ATOMXOR16: return X86::XOR16rr;
12783 case X86::ATOMXOR32: return X86::XOR32rr;
12784 case X86::ATOMXOR64: return X86::XOR64rr;
12786 llvm_unreachable("Unhandled atomic-load-op opcode!");
12789 // Get opcode of the non-atomic one from the specified atomic instruction with
12791 static unsigned getNonAtomicOpcodeWithExtraOpc(unsigned Opc,
12792 unsigned &ExtraOpc) {
12794 case X86::ATOMNAND8: ExtraOpc = X86::NOT8r; return X86::AND8rr;
12795 case X86::ATOMNAND16: ExtraOpc = X86::NOT16r; return X86::AND16rr;
12796 case X86::ATOMNAND32: ExtraOpc = X86::NOT32r; return X86::AND32rr;
12797 case X86::ATOMNAND64: ExtraOpc = X86::NOT64r; return X86::AND64rr;
12798 case X86::ATOMMAX8: ExtraOpc = X86::CMP8rr; return X86::CMOVL32rr;
12799 case X86::ATOMMAX16: ExtraOpc = X86::CMP16rr; return X86::CMOVL16rr;
12800 case X86::ATOMMAX32: ExtraOpc = X86::CMP32rr; return X86::CMOVL32rr;
12801 case X86::ATOMMAX64: ExtraOpc = X86::CMP64rr; return X86::CMOVL64rr;
12802 case X86::ATOMMIN8: ExtraOpc = X86::CMP8rr; return X86::CMOVG32rr;
12803 case X86::ATOMMIN16: ExtraOpc = X86::CMP16rr; return X86::CMOVG16rr;
12804 case X86::ATOMMIN32: ExtraOpc = X86::CMP32rr; return X86::CMOVG32rr;
12805 case X86::ATOMMIN64: ExtraOpc = X86::CMP64rr; return X86::CMOVG64rr;
12806 case X86::ATOMUMAX8: ExtraOpc = X86::CMP8rr; return X86::CMOVB32rr;
12807 case X86::ATOMUMAX16: ExtraOpc = X86::CMP16rr; return X86::CMOVB16rr;
12808 case X86::ATOMUMAX32: ExtraOpc = X86::CMP32rr; return X86::CMOVB32rr;
12809 case X86::ATOMUMAX64: ExtraOpc = X86::CMP64rr; return X86::CMOVB64rr;
12810 case X86::ATOMUMIN8: ExtraOpc = X86::CMP8rr; return X86::CMOVA32rr;
12811 case X86::ATOMUMIN16: ExtraOpc = X86::CMP16rr; return X86::CMOVA16rr;
12812 case X86::ATOMUMIN32: ExtraOpc = X86::CMP32rr; return X86::CMOVA32rr;
12813 case X86::ATOMUMIN64: ExtraOpc = X86::CMP64rr; return X86::CMOVA64rr;
12815 llvm_unreachable("Unhandled atomic-load-op opcode!");
12818 // Get opcode of the non-atomic one from the specified atomic instruction for
12819 // 64-bit data type on 32-bit target.
12820 static unsigned getNonAtomic6432Opcode(unsigned Opc, unsigned &HiOpc) {
12822 case X86::ATOMAND6432: HiOpc = X86::AND32rr; return X86::AND32rr;
12823 case X86::ATOMOR6432: HiOpc = X86::OR32rr; return X86::OR32rr;
12824 case X86::ATOMXOR6432: HiOpc = X86::XOR32rr; return X86::XOR32rr;
12825 case X86::ATOMADD6432: HiOpc = X86::ADC32rr; return X86::ADD32rr;
12826 case X86::ATOMSUB6432: HiOpc = X86::SBB32rr; return X86::SUB32rr;
12827 case X86::ATOMSWAP6432: HiOpc = X86::MOV32rr; return X86::MOV32rr;
12828 case X86::ATOMMAX6432: HiOpc = X86::SETLr; return X86::SETLr;
12829 case X86::ATOMMIN6432: HiOpc = X86::SETGr; return X86::SETGr;
12830 case X86::ATOMUMAX6432: HiOpc = X86::SETBr; return X86::SETBr;
12831 case X86::ATOMUMIN6432: HiOpc = X86::SETAr; return X86::SETAr;
12833 llvm_unreachable("Unhandled atomic-load-op opcode!");
12836 // Get opcode of the non-atomic one from the specified atomic instruction for
12837 // 64-bit data type on 32-bit target with extra opcode.
12838 static unsigned getNonAtomic6432OpcodeWithExtraOpc(unsigned Opc,
12840 unsigned &ExtraOpc) {
12842 case X86::ATOMNAND6432:
12843 ExtraOpc = X86::NOT32r;
12844 HiOpc = X86::AND32rr;
12845 return X86::AND32rr;
12847 llvm_unreachable("Unhandled atomic-load-op opcode!");
12850 // Get pseudo CMOV opcode from the specified data type.
12851 static unsigned getPseudoCMOVOpc(EVT VT) {
12852 switch (VT.getSimpleVT().SimpleTy) {
12853 case MVT::i8: return X86::CMOV_GR8;
12854 case MVT::i16: return X86::CMOV_GR16;
12855 case MVT::i32: return X86::CMOV_GR32;
12859 llvm_unreachable("Unknown CMOV opcode!");
12862 // EmitAtomicLoadArith - emit the code sequence for pseudo atomic instructions.
12863 // They will be translated into a spin-loop or compare-exchange loop from
12866 // dst = atomic-fetch-op MI.addr, MI.val
12872 // EAX = LOAD MI.addr
12874 // t1 = OP MI.val, EAX
12875 // LCMPXCHG [MI.addr], t1, [EAX is implicitly used & defined]
12880 MachineBasicBlock *
12881 X86TargetLowering::EmitAtomicLoadArith(MachineInstr *MI,
12882 MachineBasicBlock *MBB) const {
12883 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12884 DebugLoc DL = MI->getDebugLoc();
12886 MachineFunction *MF = MBB->getParent();
12887 MachineRegisterInfo &MRI = MF->getRegInfo();
12889 const BasicBlock *BB = MBB->getBasicBlock();
12890 MachineFunction::iterator I = MBB;
12893 assert(MI->getNumOperands() <= X86::AddrNumOperands + 4 &&
12894 "Unexpected number of operands");
12896 assert(MI->hasOneMemOperand() &&
12897 "Expected atomic-load-op to have one memoperand");
12899 // Memory Reference
12900 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
12901 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
12903 unsigned DstReg, SrcReg;
12904 unsigned MemOpndSlot;
12906 unsigned CurOp = 0;
12908 DstReg = MI->getOperand(CurOp++).getReg();
12909 MemOpndSlot = CurOp;
12910 CurOp += X86::AddrNumOperands;
12911 SrcReg = MI->getOperand(CurOp++).getReg();
12913 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
12914 MVT::SimpleValueType VT = *RC->vt_begin();
12915 unsigned AccPhyReg = getX86SubSuperRegister(X86::EAX, VT);
12917 unsigned LCMPXCHGOpc = getCmpXChgOpcode(VT);
12918 unsigned LOADOpc = getLoadOpcode(VT);
12920 // For the atomic load-arith operator, we generate
12923 // EAX = LOAD [MI.addr]
12925 // t1 = OP MI.val, EAX
12926 // LCMPXCHG [MI.addr], t1, [EAX is implicitly used & defined]
12930 MachineBasicBlock *thisMBB = MBB;
12931 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
12932 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
12933 MF->insert(I, mainMBB);
12934 MF->insert(I, sinkMBB);
12936 MachineInstrBuilder MIB;
12938 // Transfer the remainder of BB and its successor edges to sinkMBB.
12939 sinkMBB->splice(sinkMBB->begin(), MBB,
12940 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
12941 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
12944 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), AccPhyReg);
12945 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
12946 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
12947 MIB.setMemRefs(MMOBegin, MMOEnd);
12949 thisMBB->addSuccessor(mainMBB);
12952 MachineBasicBlock *origMainMBB = mainMBB;
12953 mainMBB->addLiveIn(AccPhyReg);
12955 // Copy AccPhyReg as it is used more than once.
12956 unsigned AccReg = MRI.createVirtualRegister(RC);
12957 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), AccReg)
12958 .addReg(AccPhyReg);
12960 unsigned t1 = MRI.createVirtualRegister(RC);
12961 unsigned Opc = MI->getOpcode();
12964 llvm_unreachable("Unhandled atomic-load-op opcode!");
12965 case X86::ATOMAND8:
12966 case X86::ATOMAND16:
12967 case X86::ATOMAND32:
12968 case X86::ATOMAND64:
12970 case X86::ATOMOR16:
12971 case X86::ATOMOR32:
12972 case X86::ATOMOR64:
12973 case X86::ATOMXOR8:
12974 case X86::ATOMXOR16:
12975 case X86::ATOMXOR32:
12976 case X86::ATOMXOR64: {
12977 unsigned ARITHOpc = getNonAtomicOpcode(Opc);
12978 BuildMI(mainMBB, DL, TII->get(ARITHOpc), t1).addReg(SrcReg)
12982 case X86::ATOMNAND8:
12983 case X86::ATOMNAND16:
12984 case X86::ATOMNAND32:
12985 case X86::ATOMNAND64: {
12986 unsigned t2 = MRI.createVirtualRegister(RC);
12988 unsigned ANDOpc = getNonAtomicOpcodeWithExtraOpc(Opc, NOTOpc);
12989 BuildMI(mainMBB, DL, TII->get(ANDOpc), t2).addReg(SrcReg)
12991 BuildMI(mainMBB, DL, TII->get(NOTOpc), t1).addReg(t2);
12994 case X86::ATOMMAX8:
12995 case X86::ATOMMAX16:
12996 case X86::ATOMMAX32:
12997 case X86::ATOMMAX64:
12998 case X86::ATOMMIN8:
12999 case X86::ATOMMIN16:
13000 case X86::ATOMMIN32:
13001 case X86::ATOMMIN64:
13002 case X86::ATOMUMAX8:
13003 case X86::ATOMUMAX16:
13004 case X86::ATOMUMAX32:
13005 case X86::ATOMUMAX64:
13006 case X86::ATOMUMIN8:
13007 case X86::ATOMUMIN16:
13008 case X86::ATOMUMIN32:
13009 case X86::ATOMUMIN64: {
13011 unsigned CMOVOpc = getNonAtomicOpcodeWithExtraOpc(Opc, CMPOpc);
13013 BuildMI(mainMBB, DL, TII->get(CMPOpc))
13017 if (Subtarget->hasCMov()) {
13018 if (VT != MVT::i8) {
13020 BuildMI(mainMBB, DL, TII->get(CMOVOpc), t1)
13024 // Promote i8 to i32 to use CMOV32
13025 const TargetRegisterClass *RC32 = getRegClassFor(MVT::i32);
13026 unsigned SrcReg32 = MRI.createVirtualRegister(RC32);
13027 unsigned AccReg32 = MRI.createVirtualRegister(RC32);
13028 unsigned t2 = MRI.createVirtualRegister(RC32);
13030 unsigned Undef = MRI.createVirtualRegister(RC32);
13031 BuildMI(mainMBB, DL, TII->get(TargetOpcode::IMPLICIT_DEF), Undef);
13033 BuildMI(mainMBB, DL, TII->get(TargetOpcode::INSERT_SUBREG), SrcReg32)
13036 .addImm(X86::sub_8bit);
13037 BuildMI(mainMBB, DL, TII->get(TargetOpcode::INSERT_SUBREG), AccReg32)
13040 .addImm(X86::sub_8bit);
13042 BuildMI(mainMBB, DL, TII->get(CMOVOpc), t2)
13046 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t1)
13047 .addReg(t2, 0, X86::sub_8bit);
13050 // Use pseudo select and lower them.
13051 assert((VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32) &&
13052 "Invalid atomic-load-op transformation!");
13053 unsigned SelOpc = getPseudoCMOVOpc(VT);
13054 X86::CondCode CC = X86::getCondFromCMovOpc(CMOVOpc);
13055 assert(CC != X86::COND_INVALID && "Invalid atomic-load-op transformation!");
13056 MIB = BuildMI(mainMBB, DL, TII->get(SelOpc), t1)
13057 .addReg(SrcReg).addReg(AccReg)
13059 mainMBB = EmitLoweredSelect(MIB, mainMBB);
13065 // Copy AccPhyReg back from virtual register.
13066 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), AccPhyReg)
13069 MIB = BuildMI(mainMBB, DL, TII->get(LCMPXCHGOpc));
13070 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
13071 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
13073 MIB.setMemRefs(MMOBegin, MMOEnd);
13075 BuildMI(mainMBB, DL, TII->get(X86::JNE_4)).addMBB(origMainMBB);
13077 mainMBB->addSuccessor(origMainMBB);
13078 mainMBB->addSuccessor(sinkMBB);
13081 sinkMBB->addLiveIn(AccPhyReg);
13083 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
13084 TII->get(TargetOpcode::COPY), DstReg)
13085 .addReg(AccPhyReg);
13087 MI->eraseFromParent();
13091 // EmitAtomicLoadArith6432 - emit the code sequence for pseudo atomic
13092 // instructions. They will be translated into a spin-loop or compare-exchange
13096 // dst = atomic-fetch-op MI.addr, MI.val
13102 // EAX = LOAD [MI.addr + 0]
13103 // EDX = LOAD [MI.addr + 4]
13105 // EBX = OP MI.val.lo, EAX
13106 // ECX = OP MI.val.hi, EDX
13107 // LCMPXCHG8B [MI.addr], [ECX:EBX & EDX:EAX are implicitly used and EDX:EAX is implicitly defined]
13112 MachineBasicBlock *
13113 X86TargetLowering::EmitAtomicLoadArith6432(MachineInstr *MI,
13114 MachineBasicBlock *MBB) const {
13115 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
13116 DebugLoc DL = MI->getDebugLoc();
13118 MachineFunction *MF = MBB->getParent();
13119 MachineRegisterInfo &MRI = MF->getRegInfo();
13121 const BasicBlock *BB = MBB->getBasicBlock();
13122 MachineFunction::iterator I = MBB;
13125 assert(MI->getNumOperands() <= X86::AddrNumOperands + 7 &&
13126 "Unexpected number of operands");
13128 assert(MI->hasOneMemOperand() &&
13129 "Expected atomic-load-op32 to have one memoperand");
13131 // Memory Reference
13132 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
13133 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
13135 unsigned DstLoReg, DstHiReg;
13136 unsigned SrcLoReg, SrcHiReg;
13137 unsigned MemOpndSlot;
13139 unsigned CurOp = 0;
13141 DstLoReg = MI->getOperand(CurOp++).getReg();
13142 DstHiReg = MI->getOperand(CurOp++).getReg();
13143 MemOpndSlot = CurOp;
13144 CurOp += X86::AddrNumOperands;
13145 SrcLoReg = MI->getOperand(CurOp++).getReg();
13146 SrcHiReg = MI->getOperand(CurOp++).getReg();
13148 const TargetRegisterClass *RC = &X86::GR32RegClass;
13149 const TargetRegisterClass *RC8 = &X86::GR8RegClass;
13151 unsigned LCMPXCHGOpc = X86::LCMPXCHG8B;
13152 unsigned LOADOpc = X86::MOV32rm;
13154 // For the atomic load-arith operator, we generate
13157 // EAX = LOAD [MI.addr + 0]
13158 // EDX = LOAD [MI.addr + 4]
13160 // EBX = OP MI.vallo, EAX
13161 // ECX = OP MI.valhi, EDX
13162 // LCMPXCHG8B [MI.addr], [ECX:EBX & EDX:EAX are implicitly used and EDX:EAX is implicitly defined]
13166 MachineBasicBlock *thisMBB = MBB;
13167 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
13168 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
13169 MF->insert(I, mainMBB);
13170 MF->insert(I, sinkMBB);
13172 MachineInstrBuilder MIB;
13174 // Transfer the remainder of BB and its successor edges to sinkMBB.
13175 sinkMBB->splice(sinkMBB->begin(), MBB,
13176 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
13177 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
13181 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), X86::EAX);
13182 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
13183 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
13184 MIB.setMemRefs(MMOBegin, MMOEnd);
13186 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), X86::EDX);
13187 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
13188 if (i == X86::AddrDisp)
13189 MIB.addDisp(MI->getOperand(MemOpndSlot + i), 4); // 4 == sizeof(i32)
13191 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
13193 MIB.setMemRefs(MMOBegin, MMOEnd);
13195 thisMBB->addSuccessor(mainMBB);
13198 MachineBasicBlock *origMainMBB = mainMBB;
13199 mainMBB->addLiveIn(X86::EAX);
13200 mainMBB->addLiveIn(X86::EDX);
13202 // Copy EDX:EAX as they are used more than once.
13203 unsigned LoReg = MRI.createVirtualRegister(RC);
13204 unsigned HiReg = MRI.createVirtualRegister(RC);
13205 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), LoReg).addReg(X86::EAX);
13206 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), HiReg).addReg(X86::EDX);
13208 unsigned t1L = MRI.createVirtualRegister(RC);
13209 unsigned t1H = MRI.createVirtualRegister(RC);
13211 unsigned Opc = MI->getOpcode();
13214 llvm_unreachable("Unhandled atomic-load-op6432 opcode!");
13215 case X86::ATOMAND6432:
13216 case X86::ATOMOR6432:
13217 case X86::ATOMXOR6432:
13218 case X86::ATOMADD6432:
13219 case X86::ATOMSUB6432: {
13221 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc);
13222 BuildMI(mainMBB, DL, TII->get(LoOpc), t1L).addReg(LoReg).addReg(SrcLoReg);
13223 BuildMI(mainMBB, DL, TII->get(HiOpc), t1H).addReg(HiReg).addReg(SrcHiReg);
13226 case X86::ATOMNAND6432: {
13227 unsigned HiOpc, NOTOpc;
13228 unsigned LoOpc = getNonAtomic6432OpcodeWithExtraOpc(Opc, HiOpc, NOTOpc);
13229 unsigned t2L = MRI.createVirtualRegister(RC);
13230 unsigned t2H = MRI.createVirtualRegister(RC);
13231 BuildMI(mainMBB, DL, TII->get(LoOpc), t2L).addReg(SrcLoReg).addReg(LoReg);
13232 BuildMI(mainMBB, DL, TII->get(HiOpc), t2H).addReg(SrcHiReg).addReg(HiReg);
13233 BuildMI(mainMBB, DL, TII->get(NOTOpc), t1L).addReg(t2L);
13234 BuildMI(mainMBB, DL, TII->get(NOTOpc), t1H).addReg(t2H);
13237 case X86::ATOMMAX6432:
13238 case X86::ATOMMIN6432:
13239 case X86::ATOMUMAX6432:
13240 case X86::ATOMUMIN6432: {
13242 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc);
13243 unsigned cL = MRI.createVirtualRegister(RC8);
13244 unsigned cH = MRI.createVirtualRegister(RC8);
13245 unsigned cL32 = MRI.createVirtualRegister(RC);
13246 unsigned cH32 = MRI.createVirtualRegister(RC);
13247 unsigned cc = MRI.createVirtualRegister(RC);
13248 // cl := cmp src_lo, lo
13249 BuildMI(mainMBB, DL, TII->get(X86::CMP32rr))
13250 .addReg(SrcLoReg).addReg(LoReg);
13251 BuildMI(mainMBB, DL, TII->get(LoOpc), cL);
13252 BuildMI(mainMBB, DL, TII->get(X86::MOVZX32rr8), cL32).addReg(cL);
13253 // ch := cmp src_hi, hi
13254 BuildMI(mainMBB, DL, TII->get(X86::CMP32rr))
13255 .addReg(SrcHiReg).addReg(HiReg);
13256 BuildMI(mainMBB, DL, TII->get(HiOpc), cH);
13257 BuildMI(mainMBB, DL, TII->get(X86::MOVZX32rr8), cH32).addReg(cH);
13258 // cc := if (src_hi == hi) ? cl : ch;
13259 if (Subtarget->hasCMov()) {
13260 BuildMI(mainMBB, DL, TII->get(X86::CMOVE32rr), cc)
13261 .addReg(cH32).addReg(cL32);
13263 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), cc)
13264 .addReg(cH32).addReg(cL32)
13265 .addImm(X86::COND_E);
13266 mainMBB = EmitLoweredSelect(MIB, mainMBB);
13268 BuildMI(mainMBB, DL, TII->get(X86::TEST32rr)).addReg(cc).addReg(cc);
13269 if (Subtarget->hasCMov()) {
13270 BuildMI(mainMBB, DL, TII->get(X86::CMOVNE32rr), t1L)
13271 .addReg(SrcLoReg).addReg(LoReg);
13272 BuildMI(mainMBB, DL, TII->get(X86::CMOVNE32rr), t1H)
13273 .addReg(SrcHiReg).addReg(HiReg);
13275 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), t1L)
13276 .addReg(SrcLoReg).addReg(LoReg)
13277 .addImm(X86::COND_NE);
13278 mainMBB = EmitLoweredSelect(MIB, mainMBB);
13279 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), t1H)
13280 .addReg(SrcHiReg).addReg(HiReg)
13281 .addImm(X86::COND_NE);
13282 mainMBB = EmitLoweredSelect(MIB, mainMBB);
13286 case X86::ATOMSWAP6432: {
13288 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc);
13289 BuildMI(mainMBB, DL, TII->get(LoOpc), t1L).addReg(SrcLoReg);
13290 BuildMI(mainMBB, DL, TII->get(HiOpc), t1H).addReg(SrcHiReg);
13295 // Copy EDX:EAX back from HiReg:LoReg
13296 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EAX).addReg(LoReg);
13297 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EDX).addReg(HiReg);
13298 // Copy ECX:EBX from t1H:t1L
13299 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EBX).addReg(t1L);
13300 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::ECX).addReg(t1H);
13302 MIB = BuildMI(mainMBB, DL, TII->get(LCMPXCHGOpc));
13303 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
13304 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
13305 MIB.setMemRefs(MMOBegin, MMOEnd);
13307 BuildMI(mainMBB, DL, TII->get(X86::JNE_4)).addMBB(origMainMBB);
13309 mainMBB->addSuccessor(origMainMBB);
13310 mainMBB->addSuccessor(sinkMBB);
13313 sinkMBB->addLiveIn(X86::EAX);
13314 sinkMBB->addLiveIn(X86::EDX);
13316 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
13317 TII->get(TargetOpcode::COPY), DstLoReg)
13319 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
13320 TII->get(TargetOpcode::COPY), DstHiReg)
13323 MI->eraseFromParent();
13327 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
13328 // or XMM0_V32I8 in AVX all of this code can be replaced with that
13329 // in the .td file.
13330 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
13331 const TargetInstrInfo *TII) {
13333 switch (MI->getOpcode()) {
13334 default: llvm_unreachable("illegal opcode!");
13335 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
13336 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
13337 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
13338 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
13339 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
13340 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
13341 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
13342 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
13345 DebugLoc dl = MI->getDebugLoc();
13346 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
13348 unsigned NumArgs = MI->getNumOperands();
13349 for (unsigned i = 1; i < NumArgs; ++i) {
13350 MachineOperand &Op = MI->getOperand(i);
13351 if (!(Op.isReg() && Op.isImplicit()))
13352 MIB.addOperand(Op);
13354 if (MI->hasOneMemOperand())
13355 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
13357 BuildMI(*BB, MI, dl,
13358 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
13359 .addReg(X86::XMM0);
13361 MI->eraseFromParent();
13365 // FIXME: Custom handling because TableGen doesn't support multiple implicit
13366 // defs in an instruction pattern
13367 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
13368 const TargetInstrInfo *TII) {
13370 switch (MI->getOpcode()) {
13371 default: llvm_unreachable("illegal opcode!");
13372 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
13373 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
13374 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
13375 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
13376 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
13377 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
13378 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
13379 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
13382 DebugLoc dl = MI->getDebugLoc();
13383 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
13385 unsigned NumArgs = MI->getNumOperands(); // remove the results
13386 for (unsigned i = 1; i < NumArgs; ++i) {
13387 MachineOperand &Op = MI->getOperand(i);
13388 if (!(Op.isReg() && Op.isImplicit()))
13389 MIB.addOperand(Op);
13391 if (MI->hasOneMemOperand())
13392 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
13394 BuildMI(*BB, MI, dl,
13395 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
13398 MI->eraseFromParent();
13402 static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
13403 const TargetInstrInfo *TII,
13404 const X86Subtarget* Subtarget) {
13405 DebugLoc dl = MI->getDebugLoc();
13407 // Address into RAX/EAX, other two args into ECX, EDX.
13408 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
13409 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
13410 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
13411 for (int i = 0; i < X86::AddrNumOperands; ++i)
13412 MIB.addOperand(MI->getOperand(i));
13414 unsigned ValOps = X86::AddrNumOperands;
13415 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
13416 .addReg(MI->getOperand(ValOps).getReg());
13417 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
13418 .addReg(MI->getOperand(ValOps+1).getReg());
13420 // The instruction doesn't actually take any operands though.
13421 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
13423 MI->eraseFromParent(); // The pseudo is gone now.
13427 MachineBasicBlock *
13428 X86TargetLowering::EmitVAARG64WithCustomInserter(
13430 MachineBasicBlock *MBB) const {
13431 // Emit va_arg instruction on X86-64.
13433 // Operands to this pseudo-instruction:
13434 // 0 ) Output : destination address (reg)
13435 // 1-5) Input : va_list address (addr, i64mem)
13436 // 6 ) ArgSize : Size (in bytes) of vararg type
13437 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
13438 // 8 ) Align : Alignment of type
13439 // 9 ) EFLAGS (implicit-def)
13441 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
13442 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
13444 unsigned DestReg = MI->getOperand(0).getReg();
13445 MachineOperand &Base = MI->getOperand(1);
13446 MachineOperand &Scale = MI->getOperand(2);
13447 MachineOperand &Index = MI->getOperand(3);
13448 MachineOperand &Disp = MI->getOperand(4);
13449 MachineOperand &Segment = MI->getOperand(5);
13450 unsigned ArgSize = MI->getOperand(6).getImm();
13451 unsigned ArgMode = MI->getOperand(7).getImm();
13452 unsigned Align = MI->getOperand(8).getImm();
13454 // Memory Reference
13455 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
13456 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
13457 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
13459 // Machine Information
13460 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
13461 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
13462 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
13463 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
13464 DebugLoc DL = MI->getDebugLoc();
13466 // struct va_list {
13469 // i64 overflow_area (address)
13470 // i64 reg_save_area (address)
13472 // sizeof(va_list) = 24
13473 // alignment(va_list) = 8
13475 unsigned TotalNumIntRegs = 6;
13476 unsigned TotalNumXMMRegs = 8;
13477 bool UseGPOffset = (ArgMode == 1);
13478 bool UseFPOffset = (ArgMode == 2);
13479 unsigned MaxOffset = TotalNumIntRegs * 8 +
13480 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
13482 /* Align ArgSize to a multiple of 8 */
13483 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
13484 bool NeedsAlign = (Align > 8);
13486 MachineBasicBlock *thisMBB = MBB;
13487 MachineBasicBlock *overflowMBB;
13488 MachineBasicBlock *offsetMBB;
13489 MachineBasicBlock *endMBB;
13491 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
13492 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
13493 unsigned OffsetReg = 0;
13495 if (!UseGPOffset && !UseFPOffset) {
13496 // If we only pull from the overflow region, we don't create a branch.
13497 // We don't need to alter control flow.
13498 OffsetDestReg = 0; // unused
13499 OverflowDestReg = DestReg;
13502 overflowMBB = thisMBB;
13505 // First emit code to check if gp_offset (or fp_offset) is below the bound.
13506 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
13507 // If not, pull from overflow_area. (branch to overflowMBB)
13512 // offsetMBB overflowMBB
13517 // Registers for the PHI in endMBB
13518 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
13519 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
13521 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
13522 MachineFunction *MF = MBB->getParent();
13523 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
13524 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
13525 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
13527 MachineFunction::iterator MBBIter = MBB;
13530 // Insert the new basic blocks
13531 MF->insert(MBBIter, offsetMBB);
13532 MF->insert(MBBIter, overflowMBB);
13533 MF->insert(MBBIter, endMBB);
13535 // Transfer the remainder of MBB and its successor edges to endMBB.
13536 endMBB->splice(endMBB->begin(), thisMBB,
13537 llvm::next(MachineBasicBlock::iterator(MI)),
13539 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
13541 // Make offsetMBB and overflowMBB successors of thisMBB
13542 thisMBB->addSuccessor(offsetMBB);
13543 thisMBB->addSuccessor(overflowMBB);
13545 // endMBB is a successor of both offsetMBB and overflowMBB
13546 offsetMBB->addSuccessor(endMBB);
13547 overflowMBB->addSuccessor(endMBB);
13549 // Load the offset value into a register
13550 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
13551 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
13555 .addDisp(Disp, UseFPOffset ? 4 : 0)
13556 .addOperand(Segment)
13557 .setMemRefs(MMOBegin, MMOEnd);
13559 // Check if there is enough room left to pull this argument.
13560 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
13562 .addImm(MaxOffset + 8 - ArgSizeA8);
13564 // Branch to "overflowMBB" if offset >= max
13565 // Fall through to "offsetMBB" otherwise
13566 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
13567 .addMBB(overflowMBB);
13570 // In offsetMBB, emit code to use the reg_save_area.
13572 assert(OffsetReg != 0);
13574 // Read the reg_save_area address.
13575 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
13576 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
13581 .addOperand(Segment)
13582 .setMemRefs(MMOBegin, MMOEnd);
13584 // Zero-extend the offset
13585 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
13586 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
13589 .addImm(X86::sub_32bit);
13591 // Add the offset to the reg_save_area to get the final address.
13592 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
13593 .addReg(OffsetReg64)
13594 .addReg(RegSaveReg);
13596 // Compute the offset for the next argument
13597 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
13598 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
13600 .addImm(UseFPOffset ? 16 : 8);
13602 // Store it back into the va_list.
13603 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
13607 .addDisp(Disp, UseFPOffset ? 4 : 0)
13608 .addOperand(Segment)
13609 .addReg(NextOffsetReg)
13610 .setMemRefs(MMOBegin, MMOEnd);
13613 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
13618 // Emit code to use overflow area
13621 // Load the overflow_area address into a register.
13622 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
13623 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
13628 .addOperand(Segment)
13629 .setMemRefs(MMOBegin, MMOEnd);
13631 // If we need to align it, do so. Otherwise, just copy the address
13632 // to OverflowDestReg.
13634 // Align the overflow address
13635 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
13636 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
13638 // aligned_addr = (addr + (align-1)) & ~(align-1)
13639 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
13640 .addReg(OverflowAddrReg)
13643 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
13645 .addImm(~(uint64_t)(Align-1));
13647 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
13648 .addReg(OverflowAddrReg);
13651 // Compute the next overflow address after this argument.
13652 // (the overflow address should be kept 8-byte aligned)
13653 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
13654 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
13655 .addReg(OverflowDestReg)
13656 .addImm(ArgSizeA8);
13658 // Store the new overflow address.
13659 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
13664 .addOperand(Segment)
13665 .addReg(NextAddrReg)
13666 .setMemRefs(MMOBegin, MMOEnd);
13668 // If we branched, emit the PHI to the front of endMBB.
13670 BuildMI(*endMBB, endMBB->begin(), DL,
13671 TII->get(X86::PHI), DestReg)
13672 .addReg(OffsetDestReg).addMBB(offsetMBB)
13673 .addReg(OverflowDestReg).addMBB(overflowMBB);
13676 // Erase the pseudo instruction
13677 MI->eraseFromParent();
13682 MachineBasicBlock *
13683 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
13685 MachineBasicBlock *MBB) const {
13686 // Emit code to save XMM registers to the stack. The ABI says that the
13687 // number of registers to save is given in %al, so it's theoretically
13688 // possible to do an indirect jump trick to avoid saving all of them,
13689 // however this code takes a simpler approach and just executes all
13690 // of the stores if %al is non-zero. It's less code, and it's probably
13691 // easier on the hardware branch predictor, and stores aren't all that
13692 // expensive anyway.
13694 // Create the new basic blocks. One block contains all the XMM stores,
13695 // and one block is the final destination regardless of whether any
13696 // stores were performed.
13697 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
13698 MachineFunction *F = MBB->getParent();
13699 MachineFunction::iterator MBBIter = MBB;
13701 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
13702 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
13703 F->insert(MBBIter, XMMSaveMBB);
13704 F->insert(MBBIter, EndMBB);
13706 // Transfer the remainder of MBB and its successor edges to EndMBB.
13707 EndMBB->splice(EndMBB->begin(), MBB,
13708 llvm::next(MachineBasicBlock::iterator(MI)),
13710 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
13712 // The original block will now fall through to the XMM save block.
13713 MBB->addSuccessor(XMMSaveMBB);
13714 // The XMMSaveMBB will fall through to the end block.
13715 XMMSaveMBB->addSuccessor(EndMBB);
13717 // Now add the instructions.
13718 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
13719 DebugLoc DL = MI->getDebugLoc();
13721 unsigned CountReg = MI->getOperand(0).getReg();
13722 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
13723 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
13725 if (!Subtarget->isTargetWin64()) {
13726 // If %al is 0, branch around the XMM save block.
13727 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
13728 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
13729 MBB->addSuccessor(EndMBB);
13732 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
13733 // In the XMM save block, save all the XMM argument registers.
13734 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
13735 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
13736 MachineMemOperand *MMO =
13737 F->getMachineMemOperand(
13738 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
13739 MachineMemOperand::MOStore,
13740 /*Size=*/16, /*Align=*/16);
13741 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
13742 .addFrameIndex(RegSaveFrameIndex)
13743 .addImm(/*Scale=*/1)
13744 .addReg(/*IndexReg=*/0)
13745 .addImm(/*Disp=*/Offset)
13746 .addReg(/*Segment=*/0)
13747 .addReg(MI->getOperand(i).getReg())
13748 .addMemOperand(MMO);
13751 MI->eraseFromParent(); // The pseudo instruction is gone now.
13756 // The EFLAGS operand of SelectItr might be missing a kill marker
13757 // because there were multiple uses of EFLAGS, and ISel didn't know
13758 // which to mark. Figure out whether SelectItr should have had a
13759 // kill marker, and set it if it should. Returns the correct kill
13761 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
13762 MachineBasicBlock* BB,
13763 const TargetRegisterInfo* TRI) {
13764 // Scan forward through BB for a use/def of EFLAGS.
13765 MachineBasicBlock::iterator miI(llvm::next(SelectItr));
13766 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
13767 const MachineInstr& mi = *miI;
13768 if (mi.readsRegister(X86::EFLAGS))
13770 if (mi.definesRegister(X86::EFLAGS))
13771 break; // Should have kill-flag - update below.
13774 // If we hit the end of the block, check whether EFLAGS is live into a
13776 if (miI == BB->end()) {
13777 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
13778 sEnd = BB->succ_end();
13779 sItr != sEnd; ++sItr) {
13780 MachineBasicBlock* succ = *sItr;
13781 if (succ->isLiveIn(X86::EFLAGS))
13786 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
13787 // out. SelectMI should have a kill flag on EFLAGS.
13788 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
13792 MachineBasicBlock *
13793 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
13794 MachineBasicBlock *BB) const {
13795 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
13796 DebugLoc DL = MI->getDebugLoc();
13798 // To "insert" a SELECT_CC instruction, we actually have to insert the
13799 // diamond control-flow pattern. The incoming instruction knows the
13800 // destination vreg to set, the condition code register to branch on, the
13801 // true/false values to select between, and a branch opcode to use.
13802 const BasicBlock *LLVM_BB = BB->getBasicBlock();
13803 MachineFunction::iterator It = BB;
13809 // cmpTY ccX, r1, r2
13811 // fallthrough --> copy0MBB
13812 MachineBasicBlock *thisMBB = BB;
13813 MachineFunction *F = BB->getParent();
13814 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
13815 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
13816 F->insert(It, copy0MBB);
13817 F->insert(It, sinkMBB);
13819 // If the EFLAGS register isn't dead in the terminator, then claim that it's
13820 // live into the sink and copy blocks.
13821 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
13822 if (!MI->killsRegister(X86::EFLAGS) &&
13823 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
13824 copy0MBB->addLiveIn(X86::EFLAGS);
13825 sinkMBB->addLiveIn(X86::EFLAGS);
13828 // Transfer the remainder of BB and its successor edges to sinkMBB.
13829 sinkMBB->splice(sinkMBB->begin(), BB,
13830 llvm::next(MachineBasicBlock::iterator(MI)),
13832 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
13834 // Add the true and fallthrough blocks as its successors.
13835 BB->addSuccessor(copy0MBB);
13836 BB->addSuccessor(sinkMBB);
13838 // Create the conditional branch instruction.
13840 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
13841 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
13844 // %FalseValue = ...
13845 // # fallthrough to sinkMBB
13846 copy0MBB->addSuccessor(sinkMBB);
13849 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
13851 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
13852 TII->get(X86::PHI), MI->getOperand(0).getReg())
13853 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
13854 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
13856 MI->eraseFromParent(); // The pseudo instruction is gone now.
13860 MachineBasicBlock *
13861 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB,
13862 bool Is64Bit) const {
13863 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
13864 DebugLoc DL = MI->getDebugLoc();
13865 MachineFunction *MF = BB->getParent();
13866 const BasicBlock *LLVM_BB = BB->getBasicBlock();
13868 assert(getTargetMachine().Options.EnableSegmentedStacks);
13870 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
13871 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30;
13874 // ... [Till the alloca]
13875 // If stacklet is not large enough, jump to mallocMBB
13878 // Allocate by subtracting from RSP
13879 // Jump to continueMBB
13882 // Allocate by call to runtime
13886 // [rest of original BB]
13889 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
13890 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
13891 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
13893 MachineRegisterInfo &MRI = MF->getRegInfo();
13894 const TargetRegisterClass *AddrRegClass =
13895 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32);
13897 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
13898 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
13899 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
13900 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
13901 sizeVReg = MI->getOperand(1).getReg(),
13902 physSPReg = Is64Bit ? X86::RSP : X86::ESP;
13904 MachineFunction::iterator MBBIter = BB;
13907 MF->insert(MBBIter, bumpMBB);
13908 MF->insert(MBBIter, mallocMBB);
13909 MF->insert(MBBIter, continueMBB);
13911 continueMBB->splice(continueMBB->begin(), BB, llvm::next
13912 (MachineBasicBlock::iterator(MI)), BB->end());
13913 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
13915 // Add code to the main basic block to check if the stack limit has been hit,
13916 // and if so, jump to mallocMBB otherwise to bumpMBB.
13917 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
13918 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
13919 .addReg(tmpSPVReg).addReg(sizeVReg);
13920 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr))
13921 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
13922 .addReg(SPLimitVReg);
13923 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
13925 // bumpMBB simply decreases the stack pointer, since we know the current
13926 // stacklet has enough space.
13927 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
13928 .addReg(SPLimitVReg);
13929 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
13930 .addReg(SPLimitVReg);
13931 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
13933 // Calls into a routine in libgcc to allocate more space from the heap.
13934 const uint32_t *RegMask =
13935 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
13937 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
13939 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
13940 .addExternalSymbol("__morestack_allocate_stack_space")
13941 .addRegMask(RegMask)
13942 .addReg(X86::RDI, RegState::Implicit)
13943 .addReg(X86::RAX, RegState::ImplicitDefine);
13945 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
13947 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
13948 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
13949 .addExternalSymbol("__morestack_allocate_stack_space")
13950 .addRegMask(RegMask)
13951 .addReg(X86::EAX, RegState::ImplicitDefine);
13955 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
13958 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
13959 .addReg(Is64Bit ? X86::RAX : X86::EAX);
13960 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
13962 // Set up the CFG correctly.
13963 BB->addSuccessor(bumpMBB);
13964 BB->addSuccessor(mallocMBB);
13965 mallocMBB->addSuccessor(continueMBB);
13966 bumpMBB->addSuccessor(continueMBB);
13968 // Take care of the PHI nodes.
13969 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
13970 MI->getOperand(0).getReg())
13971 .addReg(mallocPtrVReg).addMBB(mallocMBB)
13972 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
13974 // Delete the original pseudo instruction.
13975 MI->eraseFromParent();
13978 return continueMBB;
13981 MachineBasicBlock *
13982 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
13983 MachineBasicBlock *BB) const {
13984 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
13985 DebugLoc DL = MI->getDebugLoc();
13987 assert(!Subtarget->isTargetEnvMacho());
13989 // The lowering is pretty easy: we're just emitting the call to _alloca. The
13990 // non-trivial part is impdef of ESP.
13992 if (Subtarget->isTargetWin64()) {
13993 if (Subtarget->isTargetCygMing()) {
13994 // ___chkstk(Mingw64):
13995 // Clobbers R10, R11, RAX and EFLAGS.
13997 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
13998 .addExternalSymbol("___chkstk")
13999 .addReg(X86::RAX, RegState::Implicit)
14000 .addReg(X86::RSP, RegState::Implicit)
14001 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
14002 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
14003 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
14005 // __chkstk(MSVCRT): does not update stack pointer.
14006 // Clobbers R10, R11 and EFLAGS.
14007 // FIXME: RAX(allocated size) might be reused and not killed.
14008 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
14009 .addExternalSymbol("__chkstk")
14010 .addReg(X86::RAX, RegState::Implicit)
14011 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
14012 // RAX has the offset to subtracted from RSP.
14013 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
14018 const char *StackProbeSymbol =
14019 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca";
14021 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
14022 .addExternalSymbol(StackProbeSymbol)
14023 .addReg(X86::EAX, RegState::Implicit)
14024 .addReg(X86::ESP, RegState::Implicit)
14025 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
14026 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
14027 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
14030 MI->eraseFromParent(); // The pseudo instruction is gone now.
14034 MachineBasicBlock *
14035 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
14036 MachineBasicBlock *BB) const {
14037 // This is pretty easy. We're taking the value that we received from
14038 // our load from the relocation, sticking it in either RDI (x86-64)
14039 // or EAX and doing an indirect call. The return value will then
14040 // be in the normal return register.
14041 const X86InstrInfo *TII
14042 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo());
14043 DebugLoc DL = MI->getDebugLoc();
14044 MachineFunction *F = BB->getParent();
14046 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
14047 assert(MI->getOperand(3).isGlobal() && "This should be a global");
14049 // Get a register mask for the lowered call.
14050 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
14051 // proper register mask.
14052 const uint32_t *RegMask =
14053 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
14054 if (Subtarget->is64Bit()) {
14055 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
14056 TII->get(X86::MOV64rm), X86::RDI)
14058 .addImm(0).addReg(0)
14059 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
14060 MI->getOperand(3).getTargetFlags())
14062 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
14063 addDirectMem(MIB, X86::RDI);
14064 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
14065 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
14066 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
14067 TII->get(X86::MOV32rm), X86::EAX)
14069 .addImm(0).addReg(0)
14070 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
14071 MI->getOperand(3).getTargetFlags())
14073 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
14074 addDirectMem(MIB, X86::EAX);
14075 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
14077 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
14078 TII->get(X86::MOV32rm), X86::EAX)
14079 .addReg(TII->getGlobalBaseReg(F))
14080 .addImm(0).addReg(0)
14081 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
14082 MI->getOperand(3).getTargetFlags())
14084 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
14085 addDirectMem(MIB, X86::EAX);
14086 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
14089 MI->eraseFromParent(); // The pseudo instruction is gone now.
14093 MachineBasicBlock *
14094 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
14095 MachineBasicBlock *MBB) const {
14096 DebugLoc DL = MI->getDebugLoc();
14097 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
14099 MachineFunction *MF = MBB->getParent();
14100 MachineRegisterInfo &MRI = MF->getRegInfo();
14102 const BasicBlock *BB = MBB->getBasicBlock();
14103 MachineFunction::iterator I = MBB;
14106 // Memory Reference
14107 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
14108 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
14111 unsigned MemOpndSlot = 0;
14113 unsigned CurOp = 0;
14115 DstReg = MI->getOperand(CurOp++).getReg();
14116 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
14117 assert(RC->hasType(MVT::i32) && "Invalid destination!");
14118 unsigned mainDstReg = MRI.createVirtualRegister(RC);
14119 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
14121 MemOpndSlot = CurOp;
14123 MVT PVT = getPointerTy();
14124 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
14125 "Invalid Pointer Size!");
14127 // For v = setjmp(buf), we generate
14130 // buf[LabelOffset] = restoreMBB
14131 // SjLjSetup restoreMBB
14137 // v = phi(main, restore)
14142 MachineBasicBlock *thisMBB = MBB;
14143 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
14144 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
14145 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
14146 MF->insert(I, mainMBB);
14147 MF->insert(I, sinkMBB);
14148 MF->push_back(restoreMBB);
14150 MachineInstrBuilder MIB;
14152 // Transfer the remainder of BB and its successor edges to sinkMBB.
14153 sinkMBB->splice(sinkMBB->begin(), MBB,
14154 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
14155 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
14158 unsigned PtrStoreOpc = 0;
14159 unsigned LabelReg = 0;
14160 const int64_t LabelOffset = 1 * PVT.getStoreSize();
14161 Reloc::Model RM = getTargetMachine().getRelocationModel();
14162 bool UseImmLabel = (getTargetMachine().getCodeModel() == CodeModel::Small) &&
14163 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
14165 // Prepare IP either in reg or imm.
14166 if (!UseImmLabel) {
14167 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
14168 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
14169 LabelReg = MRI.createVirtualRegister(PtrRC);
14170 if (Subtarget->is64Bit()) {
14171 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
14175 .addMBB(restoreMBB)
14178 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
14179 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
14180 .addReg(XII->getGlobalBaseReg(MF))
14183 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
14187 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
14189 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
14190 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14191 if (i == X86::AddrDisp)
14192 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
14194 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
14197 MIB.addReg(LabelReg);
14199 MIB.addMBB(restoreMBB);
14200 MIB.setMemRefs(MMOBegin, MMOEnd);
14202 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
14203 .addMBB(restoreMBB);
14204 MIB.addRegMask(RegInfo->getNoPreservedMask());
14205 thisMBB->addSuccessor(mainMBB);
14206 thisMBB->addSuccessor(restoreMBB);
14210 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
14211 mainMBB->addSuccessor(sinkMBB);
14214 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
14215 TII->get(X86::PHI), DstReg)
14216 .addReg(mainDstReg).addMBB(mainMBB)
14217 .addReg(restoreDstReg).addMBB(restoreMBB);
14220 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
14221 BuildMI(restoreMBB, DL, TII->get(X86::JMP_4)).addMBB(sinkMBB);
14222 restoreMBB->addSuccessor(sinkMBB);
14224 MI->eraseFromParent();
14228 MachineBasicBlock *
14229 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
14230 MachineBasicBlock *MBB) const {
14231 DebugLoc DL = MI->getDebugLoc();
14232 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
14234 MachineFunction *MF = MBB->getParent();
14235 MachineRegisterInfo &MRI = MF->getRegInfo();
14237 // Memory Reference
14238 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
14239 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
14241 MVT PVT = getPointerTy();
14242 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
14243 "Invalid Pointer Size!");
14245 const TargetRegisterClass *RC =
14246 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
14247 unsigned Tmp = MRI.createVirtualRegister(RC);
14248 // Since FP is only updated here but NOT referenced, it's treated as GPR.
14249 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
14250 unsigned SP = RegInfo->getStackRegister();
14252 MachineInstrBuilder MIB;
14254 const int64_t LabelOffset = 1 * PVT.getStoreSize();
14255 const int64_t SPOffset = 2 * PVT.getStoreSize();
14257 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
14258 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
14261 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
14262 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
14263 MIB.addOperand(MI->getOperand(i));
14264 MIB.setMemRefs(MMOBegin, MMOEnd);
14266 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
14267 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14268 if (i == X86::AddrDisp)
14269 MIB.addDisp(MI->getOperand(i), LabelOffset);
14271 MIB.addOperand(MI->getOperand(i));
14273 MIB.setMemRefs(MMOBegin, MMOEnd);
14275 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
14276 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14277 if (i == X86::AddrDisp)
14278 MIB.addDisp(MI->getOperand(i), SPOffset);
14280 MIB.addOperand(MI->getOperand(i));
14282 MIB.setMemRefs(MMOBegin, MMOEnd);
14284 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
14286 MI->eraseFromParent();
14290 MachineBasicBlock *
14291 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
14292 MachineBasicBlock *BB) const {
14293 switch (MI->getOpcode()) {
14294 default: llvm_unreachable("Unexpected instr type to insert");
14295 case X86::TAILJMPd64:
14296 case X86::TAILJMPr64:
14297 case X86::TAILJMPm64:
14298 llvm_unreachable("TAILJMP64 would not be touched here.");
14299 case X86::TCRETURNdi64:
14300 case X86::TCRETURNri64:
14301 case X86::TCRETURNmi64:
14303 case X86::WIN_ALLOCA:
14304 return EmitLoweredWinAlloca(MI, BB);
14305 case X86::SEG_ALLOCA_32:
14306 return EmitLoweredSegAlloca(MI, BB, false);
14307 case X86::SEG_ALLOCA_64:
14308 return EmitLoweredSegAlloca(MI, BB, true);
14309 case X86::TLSCall_32:
14310 case X86::TLSCall_64:
14311 return EmitLoweredTLSCall(MI, BB);
14312 case X86::CMOV_GR8:
14313 case X86::CMOV_FR32:
14314 case X86::CMOV_FR64:
14315 case X86::CMOV_V4F32:
14316 case X86::CMOV_V2F64:
14317 case X86::CMOV_V2I64:
14318 case X86::CMOV_V8F32:
14319 case X86::CMOV_V4F64:
14320 case X86::CMOV_V4I64:
14321 case X86::CMOV_GR16:
14322 case X86::CMOV_GR32:
14323 case X86::CMOV_RFP32:
14324 case X86::CMOV_RFP64:
14325 case X86::CMOV_RFP80:
14326 return EmitLoweredSelect(MI, BB);
14328 case X86::FP32_TO_INT16_IN_MEM:
14329 case X86::FP32_TO_INT32_IN_MEM:
14330 case X86::FP32_TO_INT64_IN_MEM:
14331 case X86::FP64_TO_INT16_IN_MEM:
14332 case X86::FP64_TO_INT32_IN_MEM:
14333 case X86::FP64_TO_INT64_IN_MEM:
14334 case X86::FP80_TO_INT16_IN_MEM:
14335 case X86::FP80_TO_INT32_IN_MEM:
14336 case X86::FP80_TO_INT64_IN_MEM: {
14337 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
14338 DebugLoc DL = MI->getDebugLoc();
14340 // Change the floating point control register to use "round towards zero"
14341 // mode when truncating to an integer value.
14342 MachineFunction *F = BB->getParent();
14343 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
14344 addFrameReference(BuildMI(*BB, MI, DL,
14345 TII->get(X86::FNSTCW16m)), CWFrameIdx);
14347 // Load the old value of the high byte of the control word...
14349 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
14350 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
14353 // Set the high part to be round to zero...
14354 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
14357 // Reload the modified control word now...
14358 addFrameReference(BuildMI(*BB, MI, DL,
14359 TII->get(X86::FLDCW16m)), CWFrameIdx);
14361 // Restore the memory image of control word to original value
14362 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
14365 // Get the X86 opcode to use.
14367 switch (MI->getOpcode()) {
14368 default: llvm_unreachable("illegal opcode!");
14369 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
14370 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
14371 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
14372 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
14373 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
14374 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
14375 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
14376 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
14377 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
14381 MachineOperand &Op = MI->getOperand(0);
14383 AM.BaseType = X86AddressMode::RegBase;
14384 AM.Base.Reg = Op.getReg();
14386 AM.BaseType = X86AddressMode::FrameIndexBase;
14387 AM.Base.FrameIndex = Op.getIndex();
14389 Op = MI->getOperand(1);
14391 AM.Scale = Op.getImm();
14392 Op = MI->getOperand(2);
14394 AM.IndexReg = Op.getImm();
14395 Op = MI->getOperand(3);
14396 if (Op.isGlobal()) {
14397 AM.GV = Op.getGlobal();
14399 AM.Disp = Op.getImm();
14401 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
14402 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
14404 // Reload the original control word now.
14405 addFrameReference(BuildMI(*BB, MI, DL,
14406 TII->get(X86::FLDCW16m)), CWFrameIdx);
14408 MI->eraseFromParent(); // The pseudo instruction is gone now.
14411 // String/text processing lowering.
14412 case X86::PCMPISTRM128REG:
14413 case X86::VPCMPISTRM128REG:
14414 case X86::PCMPISTRM128MEM:
14415 case X86::VPCMPISTRM128MEM:
14416 case X86::PCMPESTRM128REG:
14417 case X86::VPCMPESTRM128REG:
14418 case X86::PCMPESTRM128MEM:
14419 case X86::VPCMPESTRM128MEM:
14420 assert(Subtarget->hasSSE42() &&
14421 "Target must have SSE4.2 or AVX features enabled");
14422 return EmitPCMPSTRM(MI, BB, getTargetMachine().getInstrInfo());
14424 // String/text processing lowering.
14425 case X86::PCMPISTRIREG:
14426 case X86::VPCMPISTRIREG:
14427 case X86::PCMPISTRIMEM:
14428 case X86::VPCMPISTRIMEM:
14429 case X86::PCMPESTRIREG:
14430 case X86::VPCMPESTRIREG:
14431 case X86::PCMPESTRIMEM:
14432 case X86::VPCMPESTRIMEM:
14433 assert(Subtarget->hasSSE42() &&
14434 "Target must have SSE4.2 or AVX features enabled");
14435 return EmitPCMPSTRI(MI, BB, getTargetMachine().getInstrInfo());
14437 // Thread synchronization.
14439 return EmitMonitor(MI, BB, getTargetMachine().getInstrInfo(), Subtarget);
14443 return EmitXBegin(MI, BB, getTargetMachine().getInstrInfo());
14445 // Atomic Lowering.
14446 case X86::ATOMAND8:
14447 case X86::ATOMAND16:
14448 case X86::ATOMAND32:
14449 case X86::ATOMAND64:
14452 case X86::ATOMOR16:
14453 case X86::ATOMOR32:
14454 case X86::ATOMOR64:
14456 case X86::ATOMXOR16:
14457 case X86::ATOMXOR8:
14458 case X86::ATOMXOR32:
14459 case X86::ATOMXOR64:
14461 case X86::ATOMNAND8:
14462 case X86::ATOMNAND16:
14463 case X86::ATOMNAND32:
14464 case X86::ATOMNAND64:
14466 case X86::ATOMMAX8:
14467 case X86::ATOMMAX16:
14468 case X86::ATOMMAX32:
14469 case X86::ATOMMAX64:
14471 case X86::ATOMMIN8:
14472 case X86::ATOMMIN16:
14473 case X86::ATOMMIN32:
14474 case X86::ATOMMIN64:
14476 case X86::ATOMUMAX8:
14477 case X86::ATOMUMAX16:
14478 case X86::ATOMUMAX32:
14479 case X86::ATOMUMAX64:
14481 case X86::ATOMUMIN8:
14482 case X86::ATOMUMIN16:
14483 case X86::ATOMUMIN32:
14484 case X86::ATOMUMIN64:
14485 return EmitAtomicLoadArith(MI, BB);
14487 // This group does 64-bit operations on a 32-bit host.
14488 case X86::ATOMAND6432:
14489 case X86::ATOMOR6432:
14490 case X86::ATOMXOR6432:
14491 case X86::ATOMNAND6432:
14492 case X86::ATOMADD6432:
14493 case X86::ATOMSUB6432:
14494 case X86::ATOMMAX6432:
14495 case X86::ATOMMIN6432:
14496 case X86::ATOMUMAX6432:
14497 case X86::ATOMUMIN6432:
14498 case X86::ATOMSWAP6432:
14499 return EmitAtomicLoadArith6432(MI, BB);
14501 case X86::VASTART_SAVE_XMM_REGS:
14502 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
14504 case X86::VAARG_64:
14505 return EmitVAARG64WithCustomInserter(MI, BB);
14507 case X86::EH_SjLj_SetJmp32:
14508 case X86::EH_SjLj_SetJmp64:
14509 return emitEHSjLjSetJmp(MI, BB);
14511 case X86::EH_SjLj_LongJmp32:
14512 case X86::EH_SjLj_LongJmp64:
14513 return emitEHSjLjLongJmp(MI, BB);
14517 //===----------------------------------------------------------------------===//
14518 // X86 Optimization Hooks
14519 //===----------------------------------------------------------------------===//
14521 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
14524 const SelectionDAG &DAG,
14525 unsigned Depth) const {
14526 unsigned BitWidth = KnownZero.getBitWidth();
14527 unsigned Opc = Op.getOpcode();
14528 assert((Opc >= ISD::BUILTIN_OP_END ||
14529 Opc == ISD::INTRINSIC_WO_CHAIN ||
14530 Opc == ISD::INTRINSIC_W_CHAIN ||
14531 Opc == ISD::INTRINSIC_VOID) &&
14532 "Should use MaskedValueIsZero if you don't know whether Op"
14533 " is a target node!");
14535 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
14549 // These nodes' second result is a boolean.
14550 if (Op.getResNo() == 0)
14553 case X86ISD::SETCC:
14554 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
14556 case ISD::INTRINSIC_WO_CHAIN: {
14557 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
14558 unsigned NumLoBits = 0;
14561 case Intrinsic::x86_sse_movmsk_ps:
14562 case Intrinsic::x86_avx_movmsk_ps_256:
14563 case Intrinsic::x86_sse2_movmsk_pd:
14564 case Intrinsic::x86_avx_movmsk_pd_256:
14565 case Intrinsic::x86_mmx_pmovmskb:
14566 case Intrinsic::x86_sse2_pmovmskb_128:
14567 case Intrinsic::x86_avx2_pmovmskb: {
14568 // High bits of movmskp{s|d}, pmovmskb are known zero.
14570 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
14571 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
14572 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
14573 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
14574 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
14575 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
14576 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
14577 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
14579 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
14588 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
14589 unsigned Depth) const {
14590 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
14591 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
14592 return Op.getValueType().getScalarType().getSizeInBits();
14598 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
14599 /// node is a GlobalAddress + offset.
14600 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
14601 const GlobalValue* &GA,
14602 int64_t &Offset) const {
14603 if (N->getOpcode() == X86ISD::Wrapper) {
14604 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
14605 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
14606 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
14610 return TargetLowering::isGAPlusOffset(N, GA, Offset);
14613 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
14614 /// same as extracting the high 128-bit part of 256-bit vector and then
14615 /// inserting the result into the low part of a new 256-bit vector
14616 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
14617 EVT VT = SVOp->getValueType(0);
14618 unsigned NumElems = VT.getVectorNumElements();
14620 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
14621 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
14622 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
14623 SVOp->getMaskElt(j) >= 0)
14629 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
14630 /// same as extracting the low 128-bit part of 256-bit vector and then
14631 /// inserting the result into the high part of a new 256-bit vector
14632 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
14633 EVT VT = SVOp->getValueType(0);
14634 unsigned NumElems = VT.getVectorNumElements();
14636 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
14637 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
14638 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
14639 SVOp->getMaskElt(j) >= 0)
14645 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
14646 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
14647 TargetLowering::DAGCombinerInfo &DCI,
14648 const X86Subtarget* Subtarget) {
14649 DebugLoc dl = N->getDebugLoc();
14650 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
14651 SDValue V1 = SVOp->getOperand(0);
14652 SDValue V2 = SVOp->getOperand(1);
14653 EVT VT = SVOp->getValueType(0);
14654 unsigned NumElems = VT.getVectorNumElements();
14656 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
14657 V2.getOpcode() == ISD::CONCAT_VECTORS) {
14661 // V UNDEF BUILD_VECTOR UNDEF
14663 // CONCAT_VECTOR CONCAT_VECTOR
14666 // RESULT: V + zero extended
14668 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
14669 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
14670 V1.getOperand(1).getOpcode() != ISD::UNDEF)
14673 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
14676 // To match the shuffle mask, the first half of the mask should
14677 // be exactly the first vector, and all the rest a splat with the
14678 // first element of the second one.
14679 for (unsigned i = 0; i != NumElems/2; ++i)
14680 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
14681 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
14684 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
14685 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
14686 if (Ld->hasNUsesOfValue(1, 0)) {
14687 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
14688 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
14690 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2,
14692 Ld->getPointerInfo(),
14693 Ld->getAlignment(),
14694 false/*isVolatile*/, true/*ReadMem*/,
14695 false/*WriteMem*/);
14697 // Make sure the newly-created LOAD is in the same position as Ld in
14698 // terms of dependency. We create a TokenFactor for Ld and ResNode,
14699 // and update uses of Ld's output chain to use the TokenFactor.
14700 if (Ld->hasAnyUseOfValue(1)) {
14701 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
14702 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
14703 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
14704 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
14705 SDValue(ResNode.getNode(), 1));
14708 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
14712 // Emit a zeroed vector and insert the desired subvector on its
14714 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
14715 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
14716 return DCI.CombineTo(N, InsV);
14719 //===--------------------------------------------------------------------===//
14720 // Combine some shuffles into subvector extracts and inserts:
14723 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
14724 if (isShuffleHigh128VectorInsertLow(SVOp)) {
14725 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
14726 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
14727 return DCI.CombineTo(N, InsV);
14730 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
14731 if (isShuffleLow128VectorInsertHigh(SVOp)) {
14732 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
14733 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
14734 return DCI.CombineTo(N, InsV);
14740 /// PerformShuffleCombine - Performs several different shuffle combines.
14741 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
14742 TargetLowering::DAGCombinerInfo &DCI,
14743 const X86Subtarget *Subtarget) {
14744 DebugLoc dl = N->getDebugLoc();
14745 EVT VT = N->getValueType(0);
14747 // Don't create instructions with illegal types after legalize types has run.
14748 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14749 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
14752 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
14753 if (Subtarget->hasFp256() && VT.is256BitVector() &&
14754 N->getOpcode() == ISD::VECTOR_SHUFFLE)
14755 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
14757 // Only handle 128 wide vector from here on.
14758 if (!VT.is128BitVector())
14761 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
14762 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
14763 // consecutive, non-overlapping, and in the right order.
14764 SmallVector<SDValue, 16> Elts;
14765 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
14766 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
14768 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG);
14771 /// PerformTruncateCombine - Converts truncate operation to
14772 /// a sequence of vector shuffle operations.
14773 /// It is possible when we truncate 256-bit vector to 128-bit vector
14774 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
14775 TargetLowering::DAGCombinerInfo &DCI,
14776 const X86Subtarget *Subtarget) {
14780 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
14781 /// specific shuffle of a load can be folded into a single element load.
14782 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
14783 /// shuffles have been customed lowered so we need to handle those here.
14784 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
14785 TargetLowering::DAGCombinerInfo &DCI) {
14786 if (DCI.isBeforeLegalizeOps())
14789 SDValue InVec = N->getOperand(0);
14790 SDValue EltNo = N->getOperand(1);
14792 if (!isa<ConstantSDNode>(EltNo))
14795 EVT VT = InVec.getValueType();
14797 bool HasShuffleIntoBitcast = false;
14798 if (InVec.getOpcode() == ISD::BITCAST) {
14799 // Don't duplicate a load with other uses.
14800 if (!InVec.hasOneUse())
14802 EVT BCVT = InVec.getOperand(0).getValueType();
14803 if (BCVT.getVectorNumElements() != VT.getVectorNumElements())
14805 InVec = InVec.getOperand(0);
14806 HasShuffleIntoBitcast = true;
14809 if (!isTargetShuffle(InVec.getOpcode()))
14812 // Don't duplicate a load with other uses.
14813 if (!InVec.hasOneUse())
14816 SmallVector<int, 16> ShuffleMask;
14818 if (!getTargetShuffleMask(InVec.getNode(), VT.getSimpleVT(), ShuffleMask,
14822 // Select the input vector, guarding against out of range extract vector.
14823 unsigned NumElems = VT.getVectorNumElements();
14824 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
14825 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
14826 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
14827 : InVec.getOperand(1);
14829 // If inputs to shuffle are the same for both ops, then allow 2 uses
14830 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
14832 if (LdNode.getOpcode() == ISD::BITCAST) {
14833 // Don't duplicate a load with other uses.
14834 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
14837 AllowedUses = 1; // only allow 1 load use if we have a bitcast
14838 LdNode = LdNode.getOperand(0);
14841 if (!ISD::isNormalLoad(LdNode.getNode()))
14844 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
14846 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
14849 if (HasShuffleIntoBitcast) {
14850 // If there's a bitcast before the shuffle, check if the load type and
14851 // alignment is valid.
14852 unsigned Align = LN0->getAlignment();
14853 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14854 unsigned NewAlign = TLI.getDataLayout()->
14855 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
14857 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
14861 // All checks match so transform back to vector_shuffle so that DAG combiner
14862 // can finish the job
14863 DebugLoc dl = N->getDebugLoc();
14865 // Create shuffle node taking into account the case that its a unary shuffle
14866 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1);
14867 Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl,
14868 InVec.getOperand(0), Shuffle,
14870 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
14871 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
14875 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
14876 /// generation and convert it from being a bunch of shuffles and extracts
14877 /// to a simple store and scalar loads to extract the elements.
14878 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
14879 TargetLowering::DAGCombinerInfo &DCI) {
14880 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
14881 if (NewOp.getNode())
14884 SDValue InputVector = N->getOperand(0);
14885 // Detect whether we are trying to convert from mmx to i32 and the bitcast
14886 // from mmx to v2i32 has a single usage.
14887 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
14888 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
14889 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
14890 return DAG.getNode(X86ISD::MMX_MOVD2W, InputVector.getDebugLoc(),
14891 N->getValueType(0),
14892 InputVector.getNode()->getOperand(0));
14894 // Only operate on vectors of 4 elements, where the alternative shuffling
14895 // gets to be more expensive.
14896 if (InputVector.getValueType() != MVT::v4i32)
14899 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
14900 // single use which is a sign-extend or zero-extend, and all elements are
14902 SmallVector<SDNode *, 4> Uses;
14903 unsigned ExtractedElements = 0;
14904 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
14905 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
14906 if (UI.getUse().getResNo() != InputVector.getResNo())
14909 SDNode *Extract = *UI;
14910 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
14913 if (Extract->getValueType(0) != MVT::i32)
14915 if (!Extract->hasOneUse())
14917 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
14918 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
14920 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
14923 // Record which element was extracted.
14924 ExtractedElements |=
14925 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
14927 Uses.push_back(Extract);
14930 // If not all the elements were used, this may not be worthwhile.
14931 if (ExtractedElements != 15)
14934 // Ok, we've now decided to do the transformation.
14935 DebugLoc dl = InputVector.getDebugLoc();
14937 // Store the value to a temporary stack slot.
14938 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
14939 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
14940 MachinePointerInfo(), false, false, 0);
14942 // Replace each use (extract) with a load of the appropriate element.
14943 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
14944 UE = Uses.end(); UI != UE; ++UI) {
14945 SDNode *Extract = *UI;
14947 // cOMpute the element's address.
14948 SDValue Idx = Extract->getOperand(1);
14950 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
14951 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
14952 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14953 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
14955 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
14956 StackPtr, OffsetVal);
14958 // Load the scalar.
14959 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
14960 ScalarAddr, MachinePointerInfo(),
14961 false, false, false, 0);
14963 // Replace the exact with the load.
14964 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
14967 // The replacement was made in place; don't return anything.
14971 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
14972 static unsigned matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS,
14973 SDValue RHS, SelectionDAG &DAG,
14974 const X86Subtarget *Subtarget) {
14975 if (!VT.isVector())
14978 switch (VT.getSimpleVT().SimpleTy) {
14983 if (!Subtarget->hasAVX2())
14988 if (!Subtarget->hasSSE2())
14992 // SSE2 has only a small subset of the operations.
14993 bool hasUnsigned = Subtarget->hasSSE41() ||
14994 (Subtarget->hasSSE2() && VT == MVT::v16i8);
14995 bool hasSigned = Subtarget->hasSSE41() ||
14996 (Subtarget->hasSSE2() && VT == MVT::v8i16);
14998 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
15000 // Check for x CC y ? x : y.
15001 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
15002 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
15007 return hasUnsigned ? X86ISD::UMIN : 0;
15010 return hasUnsigned ? X86ISD::UMAX : 0;
15013 return hasSigned ? X86ISD::SMIN : 0;
15016 return hasSigned ? X86ISD::SMAX : 0;
15018 // Check for x CC y ? y : x -- a min/max with reversed arms.
15019 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
15020 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
15025 return hasUnsigned ? X86ISD::UMAX : 0;
15028 return hasUnsigned ? X86ISD::UMIN : 0;
15031 return hasSigned ? X86ISD::SMAX : 0;
15034 return hasSigned ? X86ISD::SMIN : 0;
15041 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
15043 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
15044 TargetLowering::DAGCombinerInfo &DCI,
15045 const X86Subtarget *Subtarget) {
15046 DebugLoc DL = N->getDebugLoc();
15047 SDValue Cond = N->getOperand(0);
15048 // Get the LHS/RHS of the select.
15049 SDValue LHS = N->getOperand(1);
15050 SDValue RHS = N->getOperand(2);
15051 EVT VT = LHS.getValueType();
15053 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
15054 // instructions match the semantics of the common C idiom x<y?x:y but not
15055 // x<=y?x:y, because of how they handle negative zero (which can be
15056 // ignored in unsafe-math mode).
15057 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
15058 VT != MVT::f80 && DAG.getTargetLoweringInfo().isTypeLegal(VT) &&
15059 (Subtarget->hasSSE2() ||
15060 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
15061 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
15063 unsigned Opcode = 0;
15064 // Check for x CC y ? x : y.
15065 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
15066 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
15070 // Converting this to a min would handle NaNs incorrectly, and swapping
15071 // the operands would cause it to handle comparisons between positive
15072 // and negative zero incorrectly.
15073 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
15074 if (!DAG.getTarget().Options.UnsafeFPMath &&
15075 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
15077 std::swap(LHS, RHS);
15079 Opcode = X86ISD::FMIN;
15082 // Converting this to a min would handle comparisons between positive
15083 // and negative zero incorrectly.
15084 if (!DAG.getTarget().Options.UnsafeFPMath &&
15085 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
15087 Opcode = X86ISD::FMIN;
15090 // Converting this to a min would handle both negative zeros and NaNs
15091 // incorrectly, but we can swap the operands to fix both.
15092 std::swap(LHS, RHS);
15096 Opcode = X86ISD::FMIN;
15100 // Converting this to a max would handle comparisons between positive
15101 // and negative zero incorrectly.
15102 if (!DAG.getTarget().Options.UnsafeFPMath &&
15103 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
15105 Opcode = X86ISD::FMAX;
15108 // Converting this to a max would handle NaNs incorrectly, and swapping
15109 // the operands would cause it to handle comparisons between positive
15110 // and negative zero incorrectly.
15111 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
15112 if (!DAG.getTarget().Options.UnsafeFPMath &&
15113 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
15115 std::swap(LHS, RHS);
15117 Opcode = X86ISD::FMAX;
15120 // Converting this to a max would handle both negative zeros and NaNs
15121 // incorrectly, but we can swap the operands to fix both.
15122 std::swap(LHS, RHS);
15126 Opcode = X86ISD::FMAX;
15129 // Check for x CC y ? y : x -- a min/max with reversed arms.
15130 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
15131 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
15135 // Converting this to a min would handle comparisons between positive
15136 // and negative zero incorrectly, and swapping the operands would
15137 // cause it to handle NaNs incorrectly.
15138 if (!DAG.getTarget().Options.UnsafeFPMath &&
15139 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
15140 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
15142 std::swap(LHS, RHS);
15144 Opcode = X86ISD::FMIN;
15147 // Converting this to a min would handle NaNs incorrectly.
15148 if (!DAG.getTarget().Options.UnsafeFPMath &&
15149 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
15151 Opcode = X86ISD::FMIN;
15154 // Converting this to a min would handle both negative zeros and NaNs
15155 // incorrectly, but we can swap the operands to fix both.
15156 std::swap(LHS, RHS);
15160 Opcode = X86ISD::FMIN;
15164 // Converting this to a max would handle NaNs incorrectly.
15165 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
15167 Opcode = X86ISD::FMAX;
15170 // Converting this to a max would handle comparisons between positive
15171 // and negative zero incorrectly, and swapping the operands would
15172 // cause it to handle NaNs incorrectly.
15173 if (!DAG.getTarget().Options.UnsafeFPMath &&
15174 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
15175 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
15177 std::swap(LHS, RHS);
15179 Opcode = X86ISD::FMAX;
15182 // Converting this to a max would handle both negative zeros and NaNs
15183 // incorrectly, but we can swap the operands to fix both.
15184 std::swap(LHS, RHS);
15188 Opcode = X86ISD::FMAX;
15194 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
15197 // If this is a select between two integer constants, try to do some
15199 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
15200 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
15201 // Don't do this for crazy integer types.
15202 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
15203 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
15204 // so that TrueC (the true value) is larger than FalseC.
15205 bool NeedsCondInvert = false;
15207 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
15208 // Efficiently invertible.
15209 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
15210 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
15211 isa<ConstantSDNode>(Cond.getOperand(1))))) {
15212 NeedsCondInvert = true;
15213 std::swap(TrueC, FalseC);
15216 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
15217 if (FalseC->getAPIntValue() == 0 &&
15218 TrueC->getAPIntValue().isPowerOf2()) {
15219 if (NeedsCondInvert) // Invert the condition if needed.
15220 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
15221 DAG.getConstant(1, Cond.getValueType()));
15223 // Zero extend the condition if needed.
15224 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
15226 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
15227 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
15228 DAG.getConstant(ShAmt, MVT::i8));
15231 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
15232 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
15233 if (NeedsCondInvert) // Invert the condition if needed.
15234 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
15235 DAG.getConstant(1, Cond.getValueType()));
15237 // Zero extend the condition if needed.
15238 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
15239 FalseC->getValueType(0), Cond);
15240 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
15241 SDValue(FalseC, 0));
15244 // Optimize cases that will turn into an LEA instruction. This requires
15245 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
15246 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
15247 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
15248 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
15250 bool isFastMultiplier = false;
15252 switch ((unsigned char)Diff) {
15254 case 1: // result = add base, cond
15255 case 2: // result = lea base( , cond*2)
15256 case 3: // result = lea base(cond, cond*2)
15257 case 4: // result = lea base( , cond*4)
15258 case 5: // result = lea base(cond, cond*4)
15259 case 8: // result = lea base( , cond*8)
15260 case 9: // result = lea base(cond, cond*8)
15261 isFastMultiplier = true;
15266 if (isFastMultiplier) {
15267 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
15268 if (NeedsCondInvert) // Invert the condition if needed.
15269 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
15270 DAG.getConstant(1, Cond.getValueType()));
15272 // Zero extend the condition if needed.
15273 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
15275 // Scale the condition by the difference.
15277 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
15278 DAG.getConstant(Diff, Cond.getValueType()));
15280 // Add the base if non-zero.
15281 if (FalseC->getAPIntValue() != 0)
15282 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
15283 SDValue(FalseC, 0));
15290 // Canonicalize max and min:
15291 // (x > y) ? x : y -> (x >= y) ? x : y
15292 // (x < y) ? x : y -> (x <= y) ? x : y
15293 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
15294 // the need for an extra compare
15295 // against zero. e.g.
15296 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
15298 // testl %edi, %edi
15300 // cmovgl %edi, %eax
15304 // cmovsl %eax, %edi
15305 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
15306 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
15307 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
15308 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
15313 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
15314 Cond = DAG.getSetCC(Cond.getDebugLoc(), Cond.getValueType(),
15315 Cond.getOperand(0), Cond.getOperand(1), NewCC);
15316 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
15321 // Match VSELECTs into subs with unsigned saturation.
15322 if (!DCI.isBeforeLegalize() &&
15323 N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
15324 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
15325 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
15326 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
15327 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
15329 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
15330 // left side invert the predicate to simplify logic below.
15332 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
15334 CC = ISD::getSetCCInverse(CC, true);
15335 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
15339 if (Other.getNode() && Other->getNumOperands() == 2 &&
15340 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
15341 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
15342 SDValue CondRHS = Cond->getOperand(1);
15344 // Look for a general sub with unsigned saturation first.
15345 // x >= y ? x-y : 0 --> subus x, y
15346 // x > y ? x-y : 0 --> subus x, y
15347 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
15348 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
15349 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
15351 // If the RHS is a constant we have to reverse the const canonicalization.
15352 // x > C-1 ? x+-C : 0 --> subus x, C
15353 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
15354 isSplatVector(CondRHS.getNode()) && isSplatVector(OpRHS.getNode())) {
15355 APInt A = cast<ConstantSDNode>(OpRHS.getOperand(0))->getAPIntValue();
15356 if (CondRHS.getConstantOperandVal(0) == -A-1)
15357 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS,
15358 DAG.getConstant(-A, VT));
15361 // Another special case: If C was a sign bit, the sub has been
15362 // canonicalized into a xor.
15363 // FIXME: Would it be better to use ComputeMaskedBits to determine whether
15364 // it's safe to decanonicalize the xor?
15365 // x s< 0 ? x^C : 0 --> subus x, C
15366 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
15367 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
15368 isSplatVector(OpRHS.getNode())) {
15369 APInt A = cast<ConstantSDNode>(OpRHS.getOperand(0))->getAPIntValue();
15371 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
15376 // Try to match a min/max vector operation.
15377 if (!DCI.isBeforeLegalize() &&
15378 N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC)
15379 if (unsigned Op = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget))
15380 return DAG.getNode(Op, DL, N->getValueType(0), LHS, RHS);
15382 // If we know that this node is legal then we know that it is going to be
15383 // matched by one of the SSE/AVX BLEND instructions. These instructions only
15384 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
15385 // to simplify previous instructions.
15386 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15387 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
15388 !DCI.isBeforeLegalize() && TLI.isOperationLegal(ISD::VSELECT, VT)) {
15389 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
15391 // Don't optimize vector selects that map to mask-registers.
15395 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
15396 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
15398 APInt KnownZero, KnownOne;
15399 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
15400 DCI.isBeforeLegalizeOps());
15401 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
15402 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO))
15403 DCI.CommitTargetLoweringOpt(TLO);
15409 // Check whether a boolean test is testing a boolean value generated by
15410 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
15413 // Simplify the following patterns:
15414 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
15415 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
15416 // to (Op EFLAGS Cond)
15418 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
15419 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
15420 // to (Op EFLAGS !Cond)
15422 // where Op could be BRCOND or CMOV.
15424 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
15425 // Quit if not CMP and SUB with its value result used.
15426 if (Cmp.getOpcode() != X86ISD::CMP &&
15427 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
15430 // Quit if not used as a boolean value.
15431 if (CC != X86::COND_E && CC != X86::COND_NE)
15434 // Check CMP operands. One of them should be 0 or 1 and the other should be
15435 // an SetCC or extended from it.
15436 SDValue Op1 = Cmp.getOperand(0);
15437 SDValue Op2 = Cmp.getOperand(1);
15440 const ConstantSDNode* C = 0;
15441 bool needOppositeCond = (CC == X86::COND_E);
15443 if ((C = dyn_cast<ConstantSDNode>(Op1)))
15445 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
15447 else // Quit if all operands are not constants.
15450 if (C->getZExtValue() == 1)
15451 needOppositeCond = !needOppositeCond;
15452 else if (C->getZExtValue() != 0)
15453 // Quit if the constant is neither 0 or 1.
15456 // Skip 'zext' node.
15457 if (SetCC.getOpcode() == ISD::ZERO_EXTEND)
15458 SetCC = SetCC.getOperand(0);
15460 switch (SetCC.getOpcode()) {
15461 case X86ISD::SETCC:
15462 // Set the condition code or opposite one if necessary.
15463 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
15464 if (needOppositeCond)
15465 CC = X86::GetOppositeBranchCondition(CC);
15466 return SetCC.getOperand(1);
15467 case X86ISD::CMOV: {
15468 // Check whether false/true value has canonical one, i.e. 0 or 1.
15469 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
15470 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
15471 // Quit if true value is not a constant.
15474 // Quit if false value is not a constant.
15476 // A special case for rdrand, where 0 is set if false cond is found.
15477 SDValue Op = SetCC.getOperand(0);
15478 if (Op.getOpcode() != X86ISD::RDRAND)
15481 // Quit if false value is not the constant 0 or 1.
15482 bool FValIsFalse = true;
15483 if (FVal && FVal->getZExtValue() != 0) {
15484 if (FVal->getZExtValue() != 1)
15486 // If FVal is 1, opposite cond is needed.
15487 needOppositeCond = !needOppositeCond;
15488 FValIsFalse = false;
15490 // Quit if TVal is not the constant opposite of FVal.
15491 if (FValIsFalse && TVal->getZExtValue() != 1)
15493 if (!FValIsFalse && TVal->getZExtValue() != 0)
15495 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
15496 if (needOppositeCond)
15497 CC = X86::GetOppositeBranchCondition(CC);
15498 return SetCC.getOperand(3);
15505 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
15506 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
15507 TargetLowering::DAGCombinerInfo &DCI,
15508 const X86Subtarget *Subtarget) {
15509 DebugLoc DL = N->getDebugLoc();
15511 // If the flag operand isn't dead, don't touch this CMOV.
15512 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
15515 SDValue FalseOp = N->getOperand(0);
15516 SDValue TrueOp = N->getOperand(1);
15517 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
15518 SDValue Cond = N->getOperand(3);
15520 if (CC == X86::COND_E || CC == X86::COND_NE) {
15521 switch (Cond.getOpcode()) {
15525 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
15526 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
15527 return (CC == X86::COND_E) ? FalseOp : TrueOp;
15533 Flags = checkBoolTestSetCCCombine(Cond, CC);
15534 if (Flags.getNode() &&
15535 // Extra check as FCMOV only supports a subset of X86 cond.
15536 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
15537 SDValue Ops[] = { FalseOp, TrueOp,
15538 DAG.getConstant(CC, MVT::i8), Flags };
15539 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(),
15540 Ops, array_lengthof(Ops));
15543 // If this is a select between two integer constants, try to do some
15544 // optimizations. Note that the operands are ordered the opposite of SELECT
15546 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
15547 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
15548 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
15549 // larger than FalseC (the false value).
15550 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
15551 CC = X86::GetOppositeBranchCondition(CC);
15552 std::swap(TrueC, FalseC);
15553 std::swap(TrueOp, FalseOp);
15556 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
15557 // This is efficient for any integer data type (including i8/i16) and
15559 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
15560 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
15561 DAG.getConstant(CC, MVT::i8), Cond);
15563 // Zero extend the condition if needed.
15564 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
15566 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
15567 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
15568 DAG.getConstant(ShAmt, MVT::i8));
15569 if (N->getNumValues() == 2) // Dead flag value?
15570 return DCI.CombineTo(N, Cond, SDValue());
15574 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
15575 // for any integer data type, including i8/i16.
15576 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
15577 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
15578 DAG.getConstant(CC, MVT::i8), Cond);
15580 // Zero extend the condition if needed.
15581 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
15582 FalseC->getValueType(0), Cond);
15583 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
15584 SDValue(FalseC, 0));
15586 if (N->getNumValues() == 2) // Dead flag value?
15587 return DCI.CombineTo(N, Cond, SDValue());
15591 // Optimize cases that will turn into an LEA instruction. This requires
15592 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
15593 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
15594 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
15595 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
15597 bool isFastMultiplier = false;
15599 switch ((unsigned char)Diff) {
15601 case 1: // result = add base, cond
15602 case 2: // result = lea base( , cond*2)
15603 case 3: // result = lea base(cond, cond*2)
15604 case 4: // result = lea base( , cond*4)
15605 case 5: // result = lea base(cond, cond*4)
15606 case 8: // result = lea base( , cond*8)
15607 case 9: // result = lea base(cond, cond*8)
15608 isFastMultiplier = true;
15613 if (isFastMultiplier) {
15614 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
15615 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
15616 DAG.getConstant(CC, MVT::i8), Cond);
15617 // Zero extend the condition if needed.
15618 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
15620 // Scale the condition by the difference.
15622 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
15623 DAG.getConstant(Diff, Cond.getValueType()));
15625 // Add the base if non-zero.
15626 if (FalseC->getAPIntValue() != 0)
15627 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
15628 SDValue(FalseC, 0));
15629 if (N->getNumValues() == 2) // Dead flag value?
15630 return DCI.CombineTo(N, Cond, SDValue());
15637 // Handle these cases:
15638 // (select (x != c), e, c) -> select (x != c), e, x),
15639 // (select (x == c), c, e) -> select (x == c), x, e)
15640 // where the c is an integer constant, and the "select" is the combination
15641 // of CMOV and CMP.
15643 // The rationale for this change is that the conditional-move from a constant
15644 // needs two instructions, however, conditional-move from a register needs
15645 // only one instruction.
15647 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
15648 // some instruction-combining opportunities. This opt needs to be
15649 // postponed as late as possible.
15651 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
15652 // the DCI.xxxx conditions are provided to postpone the optimization as
15653 // late as possible.
15655 ConstantSDNode *CmpAgainst = 0;
15656 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
15657 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
15658 dyn_cast<ConstantSDNode>(Cond.getOperand(0)) == 0) {
15660 if (CC == X86::COND_NE &&
15661 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
15662 CC = X86::GetOppositeBranchCondition(CC);
15663 std::swap(TrueOp, FalseOp);
15666 if (CC == X86::COND_E &&
15667 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
15668 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
15669 DAG.getConstant(CC, MVT::i8), Cond };
15670 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops,
15671 array_lengthof(Ops));
15679 /// PerformMulCombine - Optimize a single multiply with constant into two
15680 /// in order to implement it with two cheaper instructions, e.g.
15681 /// LEA + SHL, LEA + LEA.
15682 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
15683 TargetLowering::DAGCombinerInfo &DCI) {
15684 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
15687 EVT VT = N->getValueType(0);
15688 if (VT != MVT::i64)
15691 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
15694 uint64_t MulAmt = C->getZExtValue();
15695 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
15698 uint64_t MulAmt1 = 0;
15699 uint64_t MulAmt2 = 0;
15700 if ((MulAmt % 9) == 0) {
15702 MulAmt2 = MulAmt / 9;
15703 } else if ((MulAmt % 5) == 0) {
15705 MulAmt2 = MulAmt / 5;
15706 } else if ((MulAmt % 3) == 0) {
15708 MulAmt2 = MulAmt / 3;
15711 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
15712 DebugLoc DL = N->getDebugLoc();
15714 if (isPowerOf2_64(MulAmt2) &&
15715 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
15716 // If second multiplifer is pow2, issue it first. We want the multiply by
15717 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
15719 std::swap(MulAmt1, MulAmt2);
15722 if (isPowerOf2_64(MulAmt1))
15723 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
15724 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
15726 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
15727 DAG.getConstant(MulAmt1, VT));
15729 if (isPowerOf2_64(MulAmt2))
15730 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
15731 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
15733 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
15734 DAG.getConstant(MulAmt2, VT));
15736 // Do not add new nodes to DAG combiner worklist.
15737 DCI.CombineTo(N, NewMul, false);
15742 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
15743 SDValue N0 = N->getOperand(0);
15744 SDValue N1 = N->getOperand(1);
15745 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
15746 EVT VT = N0.getValueType();
15748 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
15749 // since the result of setcc_c is all zero's or all ones.
15750 if (VT.isInteger() && !VT.isVector() &&
15751 N1C && N0.getOpcode() == ISD::AND &&
15752 N0.getOperand(1).getOpcode() == ISD::Constant) {
15753 SDValue N00 = N0.getOperand(0);
15754 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
15755 ((N00.getOpcode() == ISD::ANY_EXTEND ||
15756 N00.getOpcode() == ISD::ZERO_EXTEND) &&
15757 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
15758 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
15759 APInt ShAmt = N1C->getAPIntValue();
15760 Mask = Mask.shl(ShAmt);
15762 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
15763 N00, DAG.getConstant(Mask, VT));
15767 // Hardware support for vector shifts is sparse which makes us scalarize the
15768 // vector operations in many cases. Also, on sandybridge ADD is faster than
15770 // (shl V, 1) -> add V,V
15771 if (isSplatVector(N1.getNode())) {
15772 assert(N0.getValueType().isVector() && "Invalid vector shift type");
15773 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1->getOperand(0));
15774 // We shift all of the values by one. In many cases we do not have
15775 // hardware support for this operation. This is better expressed as an ADD
15777 if (N1C && (1 == N1C->getZExtValue())) {
15778 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, N0);
15785 /// PerformShiftCombine - Transforms vector shift nodes to use vector shifts
15787 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
15788 TargetLowering::DAGCombinerInfo &DCI,
15789 const X86Subtarget *Subtarget) {
15790 EVT VT = N->getValueType(0);
15791 if (N->getOpcode() == ISD::SHL) {
15792 SDValue V = PerformSHLCombine(N, DAG);
15793 if (V.getNode()) return V;
15796 // On X86 with SSE2 support, we can transform this to a vector shift if
15797 // all elements are shifted by the same amount. We can't do this in legalize
15798 // because the a constant vector is typically transformed to a constant pool
15799 // so we have no knowledge of the shift amount.
15800 if (!Subtarget->hasSSE2())
15803 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
15804 (!Subtarget->hasInt256() ||
15805 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
15808 SDValue ShAmtOp = N->getOperand(1);
15809 EVT EltVT = VT.getVectorElementType();
15810 DebugLoc DL = N->getDebugLoc();
15811 SDValue BaseShAmt = SDValue();
15812 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
15813 unsigned NumElts = VT.getVectorNumElements();
15815 for (; i != NumElts; ++i) {
15816 SDValue Arg = ShAmtOp.getOperand(i);
15817 if (Arg.getOpcode() == ISD::UNDEF) continue;
15821 // Handle the case where the build_vector is all undef
15822 // FIXME: Should DAG allow this?
15826 for (; i != NumElts; ++i) {
15827 SDValue Arg = ShAmtOp.getOperand(i);
15828 if (Arg.getOpcode() == ISD::UNDEF) continue;
15829 if (Arg != BaseShAmt) {
15833 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
15834 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) {
15835 SDValue InVec = ShAmtOp.getOperand(0);
15836 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
15837 unsigned NumElts = InVec.getValueType().getVectorNumElements();
15839 for (; i != NumElts; ++i) {
15840 SDValue Arg = InVec.getOperand(i);
15841 if (Arg.getOpcode() == ISD::UNDEF) continue;
15845 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
15846 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
15847 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex();
15848 if (C->getZExtValue() == SplatIdx)
15849 BaseShAmt = InVec.getOperand(1);
15852 if (BaseShAmt.getNode() == 0) {
15853 // Don't create instructions with illegal types after legalize
15855 if (!DAG.getTargetLoweringInfo().isTypeLegal(EltVT) &&
15856 !DCI.isBeforeLegalize())
15859 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
15860 DAG.getIntPtrConstant(0));
15865 // The shift amount is an i32.
15866 if (EltVT.bitsGT(MVT::i32))
15867 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt);
15868 else if (EltVT.bitsLT(MVT::i32))
15869 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt);
15871 // The shift amount is identical so we can do a vector shift.
15872 SDValue ValOp = N->getOperand(0);
15873 switch (N->getOpcode()) {
15875 llvm_unreachable("Unknown shift opcode!");
15877 switch (VT.getSimpleVT().SimpleTy) {
15878 default: return SDValue();
15885 return getTargetVShiftNode(X86ISD::VSHLI, DL, VT, ValOp, BaseShAmt, DAG);
15888 switch (VT.getSimpleVT().SimpleTy) {
15889 default: return SDValue();
15894 return getTargetVShiftNode(X86ISD::VSRAI, DL, VT, ValOp, BaseShAmt, DAG);
15897 switch (VT.getSimpleVT().SimpleTy) {
15898 default: return SDValue();
15905 return getTargetVShiftNode(X86ISD::VSRLI, DL, VT, ValOp, BaseShAmt, DAG);
15910 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
15911 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
15912 // and friends. Likewise for OR -> CMPNEQSS.
15913 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
15914 TargetLowering::DAGCombinerInfo &DCI,
15915 const X86Subtarget *Subtarget) {
15918 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
15919 // we're requiring SSE2 for both.
15920 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
15921 SDValue N0 = N->getOperand(0);
15922 SDValue N1 = N->getOperand(1);
15923 SDValue CMP0 = N0->getOperand(1);
15924 SDValue CMP1 = N1->getOperand(1);
15925 DebugLoc DL = N->getDebugLoc();
15927 // The SETCCs should both refer to the same CMP.
15928 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
15931 SDValue CMP00 = CMP0->getOperand(0);
15932 SDValue CMP01 = CMP0->getOperand(1);
15933 EVT VT = CMP00.getValueType();
15935 if (VT == MVT::f32 || VT == MVT::f64) {
15936 bool ExpectingFlags = false;
15937 // Check for any users that want flags:
15938 for (SDNode::use_iterator UI = N->use_begin(),
15940 !ExpectingFlags && UI != UE; ++UI)
15941 switch (UI->getOpcode()) {
15946 ExpectingFlags = true;
15948 case ISD::CopyToReg:
15949 case ISD::SIGN_EXTEND:
15950 case ISD::ZERO_EXTEND:
15951 case ISD::ANY_EXTEND:
15955 if (!ExpectingFlags) {
15956 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
15957 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
15959 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
15960 X86::CondCode tmp = cc0;
15965 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
15966 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
15967 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
15968 X86ISD::NodeType NTOperator = is64BitFP ?
15969 X86ISD::FSETCCsd : X86ISD::FSETCCss;
15970 // FIXME: need symbolic constants for these magic numbers.
15971 // See X86ATTInstPrinter.cpp:printSSECC().
15972 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
15973 SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, MVT::f32, CMP00, CMP01,
15974 DAG.getConstant(x86cc, MVT::i8));
15975 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32,
15977 SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI,
15978 DAG.getConstant(1, MVT::i32));
15979 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
15980 return OneBitOfTruth;
15988 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
15989 /// so it can be folded inside ANDNP.
15990 static bool CanFoldXORWithAllOnes(const SDNode *N) {
15991 EVT VT = N->getValueType(0);
15993 // Match direct AllOnes for 128 and 256-bit vectors
15994 if (ISD::isBuildVectorAllOnes(N))
15997 // Look through a bit convert.
15998 if (N->getOpcode() == ISD::BITCAST)
15999 N = N->getOperand(0).getNode();
16001 // Sometimes the operand may come from a insert_subvector building a 256-bit
16003 if (VT.is256BitVector() &&
16004 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
16005 SDValue V1 = N->getOperand(0);
16006 SDValue V2 = N->getOperand(1);
16008 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
16009 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
16010 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
16011 ISD::isBuildVectorAllOnes(V2.getNode()))
16018 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
16019 // register. In most cases we actually compare or select YMM-sized registers
16020 // and mixing the two types creates horrible code. This method optimizes
16021 // some of the transition sequences.
16022 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
16023 TargetLowering::DAGCombinerInfo &DCI,
16024 const X86Subtarget *Subtarget) {
16025 EVT VT = N->getValueType(0);
16026 if (!VT.is256BitVector())
16029 assert((N->getOpcode() == ISD::ANY_EXTEND ||
16030 N->getOpcode() == ISD::ZERO_EXTEND ||
16031 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
16033 SDValue Narrow = N->getOperand(0);
16034 EVT NarrowVT = Narrow->getValueType(0);
16035 if (!NarrowVT.is128BitVector())
16038 if (Narrow->getOpcode() != ISD::XOR &&
16039 Narrow->getOpcode() != ISD::AND &&
16040 Narrow->getOpcode() != ISD::OR)
16043 SDValue N0 = Narrow->getOperand(0);
16044 SDValue N1 = Narrow->getOperand(1);
16045 DebugLoc DL = Narrow->getDebugLoc();
16047 // The Left side has to be a trunc.
16048 if (N0.getOpcode() != ISD::TRUNCATE)
16051 // The type of the truncated inputs.
16052 EVT WideVT = N0->getOperand(0)->getValueType(0);
16056 // The right side has to be a 'trunc' or a constant vector.
16057 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
16058 bool RHSConst = (isSplatVector(N1.getNode()) &&
16059 isa<ConstantSDNode>(N1->getOperand(0)));
16060 if (!RHSTrunc && !RHSConst)
16063 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16065 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
16068 // Set N0 and N1 to hold the inputs to the new wide operation.
16069 N0 = N0->getOperand(0);
16071 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
16072 N1->getOperand(0));
16073 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
16074 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, &C[0], C.size());
16075 } else if (RHSTrunc) {
16076 N1 = N1->getOperand(0);
16079 // Generate the wide operation.
16080 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
16081 unsigned Opcode = N->getOpcode();
16083 case ISD::ANY_EXTEND:
16085 case ISD::ZERO_EXTEND: {
16086 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
16087 APInt Mask = APInt::getAllOnesValue(InBits);
16088 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
16089 return DAG.getNode(ISD::AND, DL, VT,
16090 Op, DAG.getConstant(Mask, VT));
16092 case ISD::SIGN_EXTEND:
16093 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
16094 Op, DAG.getValueType(NarrowVT));
16096 llvm_unreachable("Unexpected opcode");
16100 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
16101 TargetLowering::DAGCombinerInfo &DCI,
16102 const X86Subtarget *Subtarget) {
16103 EVT VT = N->getValueType(0);
16104 if (DCI.isBeforeLegalizeOps())
16107 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
16111 // Create BLSI, and BLSR instructions
16112 // BLSI is X & (-X)
16113 // BLSR is X & (X-1)
16114 if (Subtarget->hasBMI() && (VT == MVT::i32 || VT == MVT::i64)) {
16115 SDValue N0 = N->getOperand(0);
16116 SDValue N1 = N->getOperand(1);
16117 DebugLoc DL = N->getDebugLoc();
16119 // Check LHS for neg
16120 if (N0.getOpcode() == ISD::SUB && N0.getOperand(1) == N1 &&
16121 isZero(N0.getOperand(0)))
16122 return DAG.getNode(X86ISD::BLSI, DL, VT, N1);
16124 // Check RHS for neg
16125 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1) == N0 &&
16126 isZero(N1.getOperand(0)))
16127 return DAG.getNode(X86ISD::BLSI, DL, VT, N0);
16129 // Check LHS for X-1
16130 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
16131 isAllOnes(N0.getOperand(1)))
16132 return DAG.getNode(X86ISD::BLSR, DL, VT, N1);
16134 // Check RHS for X-1
16135 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
16136 isAllOnes(N1.getOperand(1)))
16137 return DAG.getNode(X86ISD::BLSR, DL, VT, N0);
16142 // Want to form ANDNP nodes:
16143 // 1) In the hopes of then easily combining them with OR and AND nodes
16144 // to form PBLEND/PSIGN.
16145 // 2) To match ANDN packed intrinsics
16146 if (VT != MVT::v2i64 && VT != MVT::v4i64)
16149 SDValue N0 = N->getOperand(0);
16150 SDValue N1 = N->getOperand(1);
16151 DebugLoc DL = N->getDebugLoc();
16153 // Check LHS for vnot
16154 if (N0.getOpcode() == ISD::XOR &&
16155 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
16156 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
16157 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
16159 // Check RHS for vnot
16160 if (N1.getOpcode() == ISD::XOR &&
16161 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
16162 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
16163 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
16168 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
16169 TargetLowering::DAGCombinerInfo &DCI,
16170 const X86Subtarget *Subtarget) {
16171 EVT VT = N->getValueType(0);
16172 if (DCI.isBeforeLegalizeOps())
16175 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
16179 SDValue N0 = N->getOperand(0);
16180 SDValue N1 = N->getOperand(1);
16182 // look for psign/blend
16183 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
16184 if (!Subtarget->hasSSSE3() ||
16185 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
16188 // Canonicalize pandn to RHS
16189 if (N0.getOpcode() == X86ISD::ANDNP)
16191 // or (and (m, y), (pandn m, x))
16192 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
16193 SDValue Mask = N1.getOperand(0);
16194 SDValue X = N1.getOperand(1);
16196 if (N0.getOperand(0) == Mask)
16197 Y = N0.getOperand(1);
16198 if (N0.getOperand(1) == Mask)
16199 Y = N0.getOperand(0);
16201 // Check to see if the mask appeared in both the AND and ANDNP and
16205 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
16206 // Look through mask bitcast.
16207 if (Mask.getOpcode() == ISD::BITCAST)
16208 Mask = Mask.getOperand(0);
16209 if (X.getOpcode() == ISD::BITCAST)
16210 X = X.getOperand(0);
16211 if (Y.getOpcode() == ISD::BITCAST)
16212 Y = Y.getOperand(0);
16214 EVT MaskVT = Mask.getValueType();
16216 // Validate that the Mask operand is a vector sra node.
16217 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
16218 // there is no psrai.b
16219 if (Mask.getOpcode() != X86ISD::VSRAI)
16222 // Check that the SRA is all signbits.
16223 SDValue SraC = Mask.getOperand(1);
16224 unsigned SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
16225 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
16226 if ((SraAmt + 1) != EltBits)
16229 DebugLoc DL = N->getDebugLoc();
16231 // We are going to replace the AND, OR, NAND with either BLEND
16232 // or PSIGN, which only look at the MSB. The VSRAI instruction
16233 // does not affect the highest bit, so we can get rid of it.
16234 Mask = Mask.getOperand(0);
16236 // Now we know we at least have a plendvb with the mask val. See if
16237 // we can form a psignb/w/d.
16238 // psign = x.type == y.type == mask.type && y = sub(0, x);
16239 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
16240 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
16241 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
16242 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
16243 "Unsupported VT for PSIGN");
16244 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask);
16245 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
16247 // PBLENDVB only available on SSE 4.1
16248 if (!Subtarget->hasSSE41())
16251 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
16253 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
16254 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
16255 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
16256 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
16257 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
16261 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
16264 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
16265 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
16267 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
16269 if (!N0.hasOneUse() || !N1.hasOneUse())
16272 SDValue ShAmt0 = N0.getOperand(1);
16273 if (ShAmt0.getValueType() != MVT::i8)
16275 SDValue ShAmt1 = N1.getOperand(1);
16276 if (ShAmt1.getValueType() != MVT::i8)
16278 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
16279 ShAmt0 = ShAmt0.getOperand(0);
16280 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
16281 ShAmt1 = ShAmt1.getOperand(0);
16283 DebugLoc DL = N->getDebugLoc();
16284 unsigned Opc = X86ISD::SHLD;
16285 SDValue Op0 = N0.getOperand(0);
16286 SDValue Op1 = N1.getOperand(0);
16287 if (ShAmt0.getOpcode() == ISD::SUB) {
16288 Opc = X86ISD::SHRD;
16289 std::swap(Op0, Op1);
16290 std::swap(ShAmt0, ShAmt1);
16293 unsigned Bits = VT.getSizeInBits();
16294 if (ShAmt1.getOpcode() == ISD::SUB) {
16295 SDValue Sum = ShAmt1.getOperand(0);
16296 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
16297 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
16298 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
16299 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
16300 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
16301 return DAG.getNode(Opc, DL, VT,
16303 DAG.getNode(ISD::TRUNCATE, DL,
16306 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
16307 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
16309 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
16310 return DAG.getNode(Opc, DL, VT,
16311 N0.getOperand(0), N1.getOperand(0),
16312 DAG.getNode(ISD::TRUNCATE, DL,
16319 // Generate NEG and CMOV for integer abs.
16320 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
16321 EVT VT = N->getValueType(0);
16323 // Since X86 does not have CMOV for 8-bit integer, we don't convert
16324 // 8-bit integer abs to NEG and CMOV.
16325 if (VT.isInteger() && VT.getSizeInBits() == 8)
16328 SDValue N0 = N->getOperand(0);
16329 SDValue N1 = N->getOperand(1);
16330 DebugLoc DL = N->getDebugLoc();
16332 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
16333 // and change it to SUB and CMOV.
16334 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
16335 N0.getOpcode() == ISD::ADD &&
16336 N0.getOperand(1) == N1 &&
16337 N1.getOpcode() == ISD::SRA &&
16338 N1.getOperand(0) == N0.getOperand(0))
16339 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
16340 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
16341 // Generate SUB & CMOV.
16342 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
16343 DAG.getConstant(0, VT), N0.getOperand(0));
16345 SDValue Ops[] = { N0.getOperand(0), Neg,
16346 DAG.getConstant(X86::COND_GE, MVT::i8),
16347 SDValue(Neg.getNode(), 1) };
16348 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue),
16349 Ops, array_lengthof(Ops));
16354 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
16355 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
16356 TargetLowering::DAGCombinerInfo &DCI,
16357 const X86Subtarget *Subtarget) {
16358 EVT VT = N->getValueType(0);
16359 if (DCI.isBeforeLegalizeOps())
16362 if (Subtarget->hasCMov()) {
16363 SDValue RV = performIntegerAbsCombine(N, DAG);
16368 // Try forming BMI if it is available.
16369 if (!Subtarget->hasBMI())
16372 if (VT != MVT::i32 && VT != MVT::i64)
16375 assert(Subtarget->hasBMI() && "Creating BLSMSK requires BMI instructions");
16377 // Create BLSMSK instructions by finding X ^ (X-1)
16378 SDValue N0 = N->getOperand(0);
16379 SDValue N1 = N->getOperand(1);
16380 DebugLoc DL = N->getDebugLoc();
16382 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
16383 isAllOnes(N0.getOperand(1)))
16384 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N1);
16386 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
16387 isAllOnes(N1.getOperand(1)))
16388 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N0);
16393 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
16394 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
16395 TargetLowering::DAGCombinerInfo &DCI,
16396 const X86Subtarget *Subtarget) {
16397 LoadSDNode *Ld = cast<LoadSDNode>(N);
16398 EVT RegVT = Ld->getValueType(0);
16399 EVT MemVT = Ld->getMemoryVT();
16400 DebugLoc dl = Ld->getDebugLoc();
16401 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16402 unsigned RegSz = RegVT.getSizeInBits();
16404 ISD::LoadExtType Ext = Ld->getExtensionType();
16405 unsigned Alignment = Ld->getAlignment();
16406 bool IsAligned = Alignment == 0 || Alignment == MemVT.getSizeInBits()/8;
16408 // On Sandybridge unaligned 256bit loads are inefficient.
16409 if (RegVT.is256BitVector() && !Subtarget->hasInt256() &&
16410 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
16411 unsigned NumElems = RegVT.getVectorNumElements();
16415 SDValue Ptr = Ld->getBasePtr();
16416 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
16418 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
16420 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
16421 Ld->getPointerInfo(), Ld->isVolatile(),
16422 Ld->isNonTemporal(), Ld->isInvariant(),
16424 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
16425 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
16426 Ld->getPointerInfo(), Ld->isVolatile(),
16427 Ld->isNonTemporal(), Ld->isInvariant(),
16428 std::max(Alignment/2U, 1U));
16429 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
16431 Load2.getValue(1));
16433 SDValue NewVec = DAG.getUNDEF(RegVT);
16434 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
16435 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
16436 return DCI.CombineTo(N, NewVec, TF, true);
16439 // If this is a vector EXT Load then attempt to optimize it using a
16440 // shuffle. If SSSE3 is not available we may emit an illegal shuffle but the
16441 // expansion is still better than scalar code.
16442 // We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise we'll
16443 // emit a shuffle and a arithmetic shift.
16444 // TODO: It is possible to support ZExt by zeroing the undef values
16445 // during the shuffle phase or after the shuffle.
16446 if (RegVT.isVector() && RegVT.isInteger() && Subtarget->hasSSE2() &&
16447 (Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)) {
16448 assert(MemVT != RegVT && "Cannot extend to the same type");
16449 assert(MemVT.isVector() && "Must load a vector from memory");
16451 unsigned NumElems = RegVT.getVectorNumElements();
16452 unsigned MemSz = MemVT.getSizeInBits();
16453 assert(RegSz > MemSz && "Register size must be greater than the mem size");
16455 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256())
16458 // All sizes must be a power of two.
16459 if (!isPowerOf2_32(RegSz * MemSz * NumElems))
16462 // Attempt to load the original value using scalar loads.
16463 // Find the largest scalar type that divides the total loaded size.
16464 MVT SclrLoadTy = MVT::i8;
16465 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
16466 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
16467 MVT Tp = (MVT::SimpleValueType)tp;
16468 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
16473 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
16474 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
16476 SclrLoadTy = MVT::f64;
16478 // Calculate the number of scalar loads that we need to perform
16479 // in order to load our vector from memory.
16480 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
16481 if (Ext == ISD::SEXTLOAD && NumLoads > 1)
16484 unsigned loadRegZize = RegSz;
16485 if (Ext == ISD::SEXTLOAD && RegSz == 256)
16488 // Represent our vector as a sequence of elements which are the
16489 // largest scalar that we can load.
16490 EVT LoadUnitVecVT = EVT::getVectorVT(*DAG.getContext(), SclrLoadTy,
16491 loadRegZize/SclrLoadTy.getSizeInBits());
16493 // Represent the data using the same element type that is stored in
16494 // memory. In practice, we ''widen'' MemVT.
16496 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
16497 loadRegZize/MemVT.getScalarType().getSizeInBits());
16499 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
16500 "Invalid vector type");
16502 // We can't shuffle using an illegal type.
16503 if (!TLI.isTypeLegal(WideVecVT))
16506 SmallVector<SDValue, 8> Chains;
16507 SDValue Ptr = Ld->getBasePtr();
16508 SDValue Increment = DAG.getConstant(SclrLoadTy.getSizeInBits()/8,
16509 TLI.getPointerTy());
16510 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
16512 for (unsigned i = 0; i < NumLoads; ++i) {
16513 // Perform a single load.
16514 SDValue ScalarLoad = DAG.getLoad(SclrLoadTy, dl, Ld->getChain(),
16515 Ptr, Ld->getPointerInfo(),
16516 Ld->isVolatile(), Ld->isNonTemporal(),
16517 Ld->isInvariant(), Ld->getAlignment());
16518 Chains.push_back(ScalarLoad.getValue(1));
16519 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
16520 // another round of DAGCombining.
16522 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
16524 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
16525 ScalarLoad, DAG.getIntPtrConstant(i));
16527 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
16530 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
16533 // Bitcast the loaded value to a vector of the original element type, in
16534 // the size of the target vector type.
16535 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
16536 unsigned SizeRatio = RegSz/MemSz;
16538 if (Ext == ISD::SEXTLOAD) {
16539 // If we have SSE4.1 we can directly emit a VSEXT node.
16540 if (Subtarget->hasSSE41()) {
16541 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
16542 return DCI.CombineTo(N, Sext, TF, true);
16545 // Otherwise we'll shuffle the small elements in the high bits of the
16546 // larger type and perform an arithmetic shift. If the shift is not legal
16547 // it's better to scalarize.
16548 if (!TLI.isOperationLegalOrCustom(ISD::SRA, RegVT))
16551 // Redistribute the loaded elements into the different locations.
16552 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
16553 for (unsigned i = 0; i != NumElems; ++i)
16554 ShuffleVec[i*SizeRatio + SizeRatio-1] = i;
16556 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
16557 DAG.getUNDEF(WideVecVT),
16560 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
16562 // Build the arithmetic shift.
16563 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
16564 MemVT.getVectorElementType().getSizeInBits();
16565 Shuff = DAG.getNode(ISD::SRA, dl, RegVT, Shuff,
16566 DAG.getConstant(Amt, RegVT));
16568 return DCI.CombineTo(N, Shuff, TF, true);
16571 // Redistribute the loaded elements into the different locations.
16572 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
16573 for (unsigned i = 0; i != NumElems; ++i)
16574 ShuffleVec[i*SizeRatio] = i;
16576 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
16577 DAG.getUNDEF(WideVecVT),
16580 // Bitcast to the requested type.
16581 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
16582 // Replace the original load with the new sequence
16583 // and return the new chain.
16584 return DCI.CombineTo(N, Shuff, TF, true);
16590 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
16591 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
16592 const X86Subtarget *Subtarget) {
16593 StoreSDNode *St = cast<StoreSDNode>(N);
16594 EVT VT = St->getValue().getValueType();
16595 EVT StVT = St->getMemoryVT();
16596 DebugLoc dl = St->getDebugLoc();
16597 SDValue StoredVal = St->getOperand(1);
16598 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16599 unsigned Alignment = St->getAlignment();
16600 bool IsAligned = Alignment == 0 || Alignment == VT.getSizeInBits()/8;
16602 // If we are saving a concatenation of two XMM registers, perform two stores.
16603 // On Sandy Bridge, 256-bit memory operations are executed by two
16604 // 128-bit ports. However, on Haswell it is better to issue a single 256-bit
16605 // memory operation.
16606 if (VT.is256BitVector() && !Subtarget->hasInt256() &&
16607 StVT == VT && !IsAligned) {
16608 unsigned NumElems = VT.getVectorNumElements();
16612 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
16613 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
16615 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
16616 SDValue Ptr0 = St->getBasePtr();
16617 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
16619 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
16620 St->getPointerInfo(), St->isVolatile(),
16621 St->isNonTemporal(), Alignment);
16622 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
16623 St->getPointerInfo(), St->isVolatile(),
16624 St->isNonTemporal(),
16625 std::max(Alignment/2U, 1U));
16626 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
16629 // Optimize trunc store (of multiple scalars) to shuffle and store.
16630 // First, pack all of the elements in one place. Next, store to memory
16631 // in fewer chunks.
16632 if (St->isTruncatingStore() && VT.isVector()) {
16633 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16634 unsigned NumElems = VT.getVectorNumElements();
16635 assert(StVT != VT && "Cannot truncate to the same type");
16636 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
16637 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
16639 // From, To sizes and ElemCount must be pow of two
16640 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
16641 // We are going to use the original vector elt for storing.
16642 // Accumulated smaller vector elements must be a multiple of the store size.
16643 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
16645 unsigned SizeRatio = FromSz / ToSz;
16647 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
16649 // Create a type on which we perform the shuffle
16650 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
16651 StVT.getScalarType(), NumElems*SizeRatio);
16653 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
16655 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
16656 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
16657 for (unsigned i = 0; i != NumElems; ++i)
16658 ShuffleVec[i] = i * SizeRatio;
16660 // Can't shuffle using an illegal type.
16661 if (!TLI.isTypeLegal(WideVecVT))
16664 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
16665 DAG.getUNDEF(WideVecVT),
16667 // At this point all of the data is stored at the bottom of the
16668 // register. We now need to save it to mem.
16670 // Find the largest store unit
16671 MVT StoreType = MVT::i8;
16672 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
16673 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
16674 MVT Tp = (MVT::SimpleValueType)tp;
16675 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
16679 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
16680 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
16681 (64 <= NumElems * ToSz))
16682 StoreType = MVT::f64;
16684 // Bitcast the original vector into a vector of store-size units
16685 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
16686 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
16687 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
16688 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
16689 SmallVector<SDValue, 8> Chains;
16690 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
16691 TLI.getPointerTy());
16692 SDValue Ptr = St->getBasePtr();
16694 // Perform one or more big stores into memory.
16695 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
16696 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
16697 StoreType, ShuffWide,
16698 DAG.getIntPtrConstant(i));
16699 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
16700 St->getPointerInfo(), St->isVolatile(),
16701 St->isNonTemporal(), St->getAlignment());
16702 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
16703 Chains.push_back(Ch);
16706 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
16710 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
16711 // the FP state in cases where an emms may be missing.
16712 // A preferable solution to the general problem is to figure out the right
16713 // places to insert EMMS. This qualifies as a quick hack.
16715 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
16716 if (VT.getSizeInBits() != 64)
16719 const Function *F = DAG.getMachineFunction().getFunction();
16720 bool NoImplicitFloatOps = F->getAttributes().
16721 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
16722 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
16723 && Subtarget->hasSSE2();
16724 if ((VT.isVector() ||
16725 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
16726 isa<LoadSDNode>(St->getValue()) &&
16727 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
16728 St->getChain().hasOneUse() && !St->isVolatile()) {
16729 SDNode* LdVal = St->getValue().getNode();
16730 LoadSDNode *Ld = 0;
16731 int TokenFactorIndex = -1;
16732 SmallVector<SDValue, 8> Ops;
16733 SDNode* ChainVal = St->getChain().getNode();
16734 // Must be a store of a load. We currently handle two cases: the load
16735 // is a direct child, and it's under an intervening TokenFactor. It is
16736 // possible to dig deeper under nested TokenFactors.
16737 if (ChainVal == LdVal)
16738 Ld = cast<LoadSDNode>(St->getChain());
16739 else if (St->getValue().hasOneUse() &&
16740 ChainVal->getOpcode() == ISD::TokenFactor) {
16741 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
16742 if (ChainVal->getOperand(i).getNode() == LdVal) {
16743 TokenFactorIndex = i;
16744 Ld = cast<LoadSDNode>(St->getValue());
16746 Ops.push_back(ChainVal->getOperand(i));
16750 if (!Ld || !ISD::isNormalLoad(Ld))
16753 // If this is not the MMX case, i.e. we are just turning i64 load/store
16754 // into f64 load/store, avoid the transformation if there are multiple
16755 // uses of the loaded value.
16756 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
16759 DebugLoc LdDL = Ld->getDebugLoc();
16760 DebugLoc StDL = N->getDebugLoc();
16761 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
16762 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
16764 if (Subtarget->is64Bit() || F64IsLegal) {
16765 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
16766 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
16767 Ld->getPointerInfo(), Ld->isVolatile(),
16768 Ld->isNonTemporal(), Ld->isInvariant(),
16769 Ld->getAlignment());
16770 SDValue NewChain = NewLd.getValue(1);
16771 if (TokenFactorIndex != -1) {
16772 Ops.push_back(NewChain);
16773 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
16776 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
16777 St->getPointerInfo(),
16778 St->isVolatile(), St->isNonTemporal(),
16779 St->getAlignment());
16782 // Otherwise, lower to two pairs of 32-bit loads / stores.
16783 SDValue LoAddr = Ld->getBasePtr();
16784 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
16785 DAG.getConstant(4, MVT::i32));
16787 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
16788 Ld->getPointerInfo(),
16789 Ld->isVolatile(), Ld->isNonTemporal(),
16790 Ld->isInvariant(), Ld->getAlignment());
16791 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
16792 Ld->getPointerInfo().getWithOffset(4),
16793 Ld->isVolatile(), Ld->isNonTemporal(),
16795 MinAlign(Ld->getAlignment(), 4));
16797 SDValue NewChain = LoLd.getValue(1);
16798 if (TokenFactorIndex != -1) {
16799 Ops.push_back(LoLd);
16800 Ops.push_back(HiLd);
16801 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
16805 LoAddr = St->getBasePtr();
16806 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
16807 DAG.getConstant(4, MVT::i32));
16809 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
16810 St->getPointerInfo(),
16811 St->isVolatile(), St->isNonTemporal(),
16812 St->getAlignment());
16813 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
16814 St->getPointerInfo().getWithOffset(4),
16816 St->isNonTemporal(),
16817 MinAlign(St->getAlignment(), 4));
16818 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
16823 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
16824 /// and return the operands for the horizontal operation in LHS and RHS. A
16825 /// horizontal operation performs the binary operation on successive elements
16826 /// of its first operand, then on successive elements of its second operand,
16827 /// returning the resulting values in a vector. For example, if
16828 /// A = < float a0, float a1, float a2, float a3 >
16830 /// B = < float b0, float b1, float b2, float b3 >
16831 /// then the result of doing a horizontal operation on A and B is
16832 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
16833 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
16834 /// A horizontal-op B, for some already available A and B, and if so then LHS is
16835 /// set to A, RHS to B, and the routine returns 'true'.
16836 /// Note that the binary operation should have the property that if one of the
16837 /// operands is UNDEF then the result is UNDEF.
16838 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
16839 // Look for the following pattern: if
16840 // A = < float a0, float a1, float a2, float a3 >
16841 // B = < float b0, float b1, float b2, float b3 >
16843 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
16844 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
16845 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
16846 // which is A horizontal-op B.
16848 // At least one of the operands should be a vector shuffle.
16849 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
16850 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
16853 EVT VT = LHS.getValueType();
16855 assert((VT.is128BitVector() || VT.is256BitVector()) &&
16856 "Unsupported vector type for horizontal add/sub");
16858 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
16859 // operate independently on 128-bit lanes.
16860 unsigned NumElts = VT.getVectorNumElements();
16861 unsigned NumLanes = VT.getSizeInBits()/128;
16862 unsigned NumLaneElts = NumElts / NumLanes;
16863 assert((NumLaneElts % 2 == 0) &&
16864 "Vector type should have an even number of elements in each lane");
16865 unsigned HalfLaneElts = NumLaneElts/2;
16867 // View LHS in the form
16868 // LHS = VECTOR_SHUFFLE A, B, LMask
16869 // If LHS is not a shuffle then pretend it is the shuffle
16870 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
16871 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
16874 SmallVector<int, 16> LMask(NumElts);
16875 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
16876 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
16877 A = LHS.getOperand(0);
16878 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
16879 B = LHS.getOperand(1);
16880 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
16881 std::copy(Mask.begin(), Mask.end(), LMask.begin());
16883 if (LHS.getOpcode() != ISD::UNDEF)
16885 for (unsigned i = 0; i != NumElts; ++i)
16889 // Likewise, view RHS in the form
16890 // RHS = VECTOR_SHUFFLE C, D, RMask
16892 SmallVector<int, 16> RMask(NumElts);
16893 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
16894 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
16895 C = RHS.getOperand(0);
16896 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
16897 D = RHS.getOperand(1);
16898 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
16899 std::copy(Mask.begin(), Mask.end(), RMask.begin());
16901 if (RHS.getOpcode() != ISD::UNDEF)
16903 for (unsigned i = 0; i != NumElts; ++i)
16907 // Check that the shuffles are both shuffling the same vectors.
16908 if (!(A == C && B == D) && !(A == D && B == C))
16911 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
16912 if (!A.getNode() && !B.getNode())
16915 // If A and B occur in reverse order in RHS, then "swap" them (which means
16916 // rewriting the mask).
16918 CommuteVectorShuffleMask(RMask, NumElts);
16920 // At this point LHS and RHS are equivalent to
16921 // LHS = VECTOR_SHUFFLE A, B, LMask
16922 // RHS = VECTOR_SHUFFLE A, B, RMask
16923 // Check that the masks correspond to performing a horizontal operation.
16924 for (unsigned i = 0; i != NumElts; ++i) {
16925 int LIdx = LMask[i], RIdx = RMask[i];
16927 // Ignore any UNDEF components.
16928 if (LIdx < 0 || RIdx < 0 ||
16929 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
16930 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
16933 // Check that successive elements are being operated on. If not, this is
16934 // not a horizontal operation.
16935 unsigned Src = (i/HalfLaneElts) % 2; // each lane is split between srcs
16936 unsigned LaneStart = (i/NumLaneElts) * NumLaneElts;
16937 int Index = 2*(i%HalfLaneElts) + NumElts*Src + LaneStart;
16938 if (!(LIdx == Index && RIdx == Index + 1) &&
16939 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
16943 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
16944 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
16948 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
16949 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
16950 const X86Subtarget *Subtarget) {
16951 EVT VT = N->getValueType(0);
16952 SDValue LHS = N->getOperand(0);
16953 SDValue RHS = N->getOperand(1);
16955 // Try to synthesize horizontal adds from adds of shuffles.
16956 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
16957 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
16958 isHorizontalBinOp(LHS, RHS, true))
16959 return DAG.getNode(X86ISD::FHADD, N->getDebugLoc(), VT, LHS, RHS);
16963 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
16964 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
16965 const X86Subtarget *Subtarget) {
16966 EVT VT = N->getValueType(0);
16967 SDValue LHS = N->getOperand(0);
16968 SDValue RHS = N->getOperand(1);
16970 // Try to synthesize horizontal subs from subs of shuffles.
16971 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
16972 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
16973 isHorizontalBinOp(LHS, RHS, false))
16974 return DAG.getNode(X86ISD::FHSUB, N->getDebugLoc(), VT, LHS, RHS);
16978 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
16979 /// X86ISD::FXOR nodes.
16980 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
16981 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
16982 // F[X]OR(0.0, x) -> x
16983 // F[X]OR(x, 0.0) -> x
16984 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
16985 if (C->getValueAPF().isPosZero())
16986 return N->getOperand(1);
16987 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
16988 if (C->getValueAPF().isPosZero())
16989 return N->getOperand(0);
16993 /// PerformFMinFMaxCombine - Do target-specific dag combines on X86ISD::FMIN and
16994 /// X86ISD::FMAX nodes.
16995 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
16996 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
16998 // Only perform optimizations if UnsafeMath is used.
16999 if (!DAG.getTarget().Options.UnsafeFPMath)
17002 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
17003 // into FMINC and FMAXC, which are Commutative operations.
17004 unsigned NewOp = 0;
17005 switch (N->getOpcode()) {
17006 default: llvm_unreachable("unknown opcode");
17007 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
17008 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
17011 return DAG.getNode(NewOp, N->getDebugLoc(), N->getValueType(0),
17012 N->getOperand(0), N->getOperand(1));
17015 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
17016 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
17017 // FAND(0.0, x) -> 0.0
17018 // FAND(x, 0.0) -> 0.0
17019 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
17020 if (C->getValueAPF().isPosZero())
17021 return N->getOperand(0);
17022 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
17023 if (C->getValueAPF().isPosZero())
17024 return N->getOperand(1);
17028 static SDValue PerformBTCombine(SDNode *N,
17030 TargetLowering::DAGCombinerInfo &DCI) {
17031 // BT ignores high bits in the bit index operand.
17032 SDValue Op1 = N->getOperand(1);
17033 if (Op1.hasOneUse()) {
17034 unsigned BitWidth = Op1.getValueSizeInBits();
17035 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
17036 APInt KnownZero, KnownOne;
17037 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
17038 !DCI.isBeforeLegalizeOps());
17039 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17040 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
17041 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
17042 DCI.CommitTargetLoweringOpt(TLO);
17047 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
17048 SDValue Op = N->getOperand(0);
17049 if (Op.getOpcode() == ISD::BITCAST)
17050 Op = Op.getOperand(0);
17051 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
17052 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
17053 VT.getVectorElementType().getSizeInBits() ==
17054 OpVT.getVectorElementType().getSizeInBits()) {
17055 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op);
17060 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
17061 TargetLowering::DAGCombinerInfo &DCI,
17062 const X86Subtarget *Subtarget) {
17063 if (!DCI.isBeforeLegalizeOps())
17066 if (!Subtarget->hasFp256())
17069 EVT VT = N->getValueType(0);
17070 if (VT.isVector() && VT.getSizeInBits() == 256) {
17071 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
17079 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
17080 const X86Subtarget* Subtarget) {
17081 DebugLoc dl = N->getDebugLoc();
17082 EVT VT = N->getValueType(0);
17084 // Let legalize expand this if it isn't a legal type yet.
17085 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
17088 EVT ScalarVT = VT.getScalarType();
17089 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
17090 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
17093 SDValue A = N->getOperand(0);
17094 SDValue B = N->getOperand(1);
17095 SDValue C = N->getOperand(2);
17097 bool NegA = (A.getOpcode() == ISD::FNEG);
17098 bool NegB = (B.getOpcode() == ISD::FNEG);
17099 bool NegC = (C.getOpcode() == ISD::FNEG);
17101 // Negative multiplication when NegA xor NegB
17102 bool NegMul = (NegA != NegB);
17104 A = A.getOperand(0);
17106 B = B.getOperand(0);
17108 C = C.getOperand(0);
17112 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
17114 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
17116 return DAG.getNode(Opcode, dl, VT, A, B, C);
17119 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
17120 TargetLowering::DAGCombinerInfo &DCI,
17121 const X86Subtarget *Subtarget) {
17122 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
17123 // (and (i32 x86isd::setcc_carry), 1)
17124 // This eliminates the zext. This transformation is necessary because
17125 // ISD::SETCC is always legalized to i8.
17126 DebugLoc dl = N->getDebugLoc();
17127 SDValue N0 = N->getOperand(0);
17128 EVT VT = N->getValueType(0);
17130 if (N0.getOpcode() == ISD::AND &&
17132 N0.getOperand(0).hasOneUse()) {
17133 SDValue N00 = N0.getOperand(0);
17134 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
17135 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
17136 if (!C || C->getZExtValue() != 1)
17138 return DAG.getNode(ISD::AND, dl, VT,
17139 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
17140 N00.getOperand(0), N00.getOperand(1)),
17141 DAG.getConstant(1, VT));
17145 if (VT.is256BitVector()) {
17146 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
17154 // Optimize x == -y --> x+y == 0
17155 // x != -y --> x+y != 0
17156 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG) {
17157 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
17158 SDValue LHS = N->getOperand(0);
17159 SDValue RHS = N->getOperand(1);
17161 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
17162 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
17163 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
17164 SDValue addV = DAG.getNode(ISD::ADD, N->getDebugLoc(),
17165 LHS.getValueType(), RHS, LHS.getOperand(1));
17166 return DAG.getSetCC(N->getDebugLoc(), N->getValueType(0),
17167 addV, DAG.getConstant(0, addV.getValueType()), CC);
17169 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
17170 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
17171 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
17172 SDValue addV = DAG.getNode(ISD::ADD, N->getDebugLoc(),
17173 RHS.getValueType(), LHS, RHS.getOperand(1));
17174 return DAG.getSetCC(N->getDebugLoc(), N->getValueType(0),
17175 addV, DAG.getConstant(0, addV.getValueType()), CC);
17180 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
17181 // as "sbb reg,reg", since it can be extended without zext and produces
17182 // an all-ones bit which is more useful than 0/1 in some cases.
17183 static SDValue MaterializeSETB(DebugLoc DL, SDValue EFLAGS, SelectionDAG &DAG) {
17184 return DAG.getNode(ISD::AND, DL, MVT::i8,
17185 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
17186 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
17187 DAG.getConstant(1, MVT::i8));
17190 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
17191 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
17192 TargetLowering::DAGCombinerInfo &DCI,
17193 const X86Subtarget *Subtarget) {
17194 DebugLoc DL = N->getDebugLoc();
17195 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
17196 SDValue EFLAGS = N->getOperand(1);
17198 if (CC == X86::COND_A) {
17199 // Try to convert COND_A into COND_B in an attempt to facilitate
17200 // materializing "setb reg".
17202 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
17203 // cannot take an immediate as its first operand.
17205 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
17206 EFLAGS.getValueType().isInteger() &&
17207 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
17208 SDValue NewSub = DAG.getNode(X86ISD::SUB, EFLAGS.getDebugLoc(),
17209 EFLAGS.getNode()->getVTList(),
17210 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
17211 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
17212 return MaterializeSETB(DL, NewEFLAGS, DAG);
17216 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
17217 // a zext and produces an all-ones bit which is more useful than 0/1 in some
17219 if (CC == X86::COND_B)
17220 return MaterializeSETB(DL, EFLAGS, DAG);
17224 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
17225 if (Flags.getNode()) {
17226 SDValue Cond = DAG.getConstant(CC, MVT::i8);
17227 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
17233 // Optimize branch condition evaluation.
17235 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
17236 TargetLowering::DAGCombinerInfo &DCI,
17237 const X86Subtarget *Subtarget) {
17238 DebugLoc DL = N->getDebugLoc();
17239 SDValue Chain = N->getOperand(0);
17240 SDValue Dest = N->getOperand(1);
17241 SDValue EFLAGS = N->getOperand(3);
17242 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
17246 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
17247 if (Flags.getNode()) {
17248 SDValue Cond = DAG.getConstant(CC, MVT::i8);
17249 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
17256 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
17257 const X86TargetLowering *XTLI) {
17258 SDValue Op0 = N->getOperand(0);
17259 EVT InVT = Op0->getValueType(0);
17261 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
17262 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
17263 DebugLoc dl = N->getDebugLoc();
17264 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
17265 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
17266 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
17269 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
17270 // a 32-bit target where SSE doesn't support i64->FP operations.
17271 if (Op0.getOpcode() == ISD::LOAD) {
17272 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
17273 EVT VT = Ld->getValueType(0);
17274 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
17275 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
17276 !XTLI->getSubtarget()->is64Bit() &&
17277 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
17278 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
17279 Ld->getChain(), Op0, DAG);
17280 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
17287 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
17288 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
17289 X86TargetLowering::DAGCombinerInfo &DCI) {
17290 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
17291 // the result is either zero or one (depending on the input carry bit).
17292 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
17293 if (X86::isZeroNode(N->getOperand(0)) &&
17294 X86::isZeroNode(N->getOperand(1)) &&
17295 // We don't have a good way to replace an EFLAGS use, so only do this when
17297 SDValue(N, 1).use_empty()) {
17298 DebugLoc DL = N->getDebugLoc();
17299 EVT VT = N->getValueType(0);
17300 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
17301 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
17302 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
17303 DAG.getConstant(X86::COND_B,MVT::i8),
17305 DAG.getConstant(1, VT));
17306 return DCI.CombineTo(N, Res1, CarryOut);
17312 // fold (add Y, (sete X, 0)) -> adc 0, Y
17313 // (add Y, (setne X, 0)) -> sbb -1, Y
17314 // (sub (sete X, 0), Y) -> sbb 0, Y
17315 // (sub (setne X, 0), Y) -> adc -1, Y
17316 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
17317 DebugLoc DL = N->getDebugLoc();
17319 // Look through ZExts.
17320 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
17321 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
17324 SDValue SetCC = Ext.getOperand(0);
17325 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
17328 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
17329 if (CC != X86::COND_E && CC != X86::COND_NE)
17332 SDValue Cmp = SetCC.getOperand(1);
17333 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
17334 !X86::isZeroNode(Cmp.getOperand(1)) ||
17335 !Cmp.getOperand(0).getValueType().isInteger())
17338 SDValue CmpOp0 = Cmp.getOperand(0);
17339 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
17340 DAG.getConstant(1, CmpOp0.getValueType()));
17342 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
17343 if (CC == X86::COND_NE)
17344 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
17345 DL, OtherVal.getValueType(), OtherVal,
17346 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
17347 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
17348 DL, OtherVal.getValueType(), OtherVal,
17349 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
17352 /// PerformADDCombine - Do target-specific dag combines on integer adds.
17353 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
17354 const X86Subtarget *Subtarget) {
17355 EVT VT = N->getValueType(0);
17356 SDValue Op0 = N->getOperand(0);
17357 SDValue Op1 = N->getOperand(1);
17359 // Try to synthesize horizontal adds from adds of shuffles.
17360 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
17361 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
17362 isHorizontalBinOp(Op0, Op1, true))
17363 return DAG.getNode(X86ISD::HADD, N->getDebugLoc(), VT, Op0, Op1);
17365 return OptimizeConditionalInDecrement(N, DAG);
17368 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
17369 const X86Subtarget *Subtarget) {
17370 SDValue Op0 = N->getOperand(0);
17371 SDValue Op1 = N->getOperand(1);
17373 // X86 can't encode an immediate LHS of a sub. See if we can push the
17374 // negation into a preceding instruction.
17375 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
17376 // If the RHS of the sub is a XOR with one use and a constant, invert the
17377 // immediate. Then add one to the LHS of the sub so we can turn
17378 // X-Y -> X+~Y+1, saving one register.
17379 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
17380 isa<ConstantSDNode>(Op1.getOperand(1))) {
17381 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
17382 EVT VT = Op0.getValueType();
17383 SDValue NewXor = DAG.getNode(ISD::XOR, Op1.getDebugLoc(), VT,
17385 DAG.getConstant(~XorC, VT));
17386 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, NewXor,
17387 DAG.getConstant(C->getAPIntValue()+1, VT));
17391 // Try to synthesize horizontal adds from adds of shuffles.
17392 EVT VT = N->getValueType(0);
17393 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
17394 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
17395 isHorizontalBinOp(Op0, Op1, true))
17396 return DAG.getNode(X86ISD::HSUB, N->getDebugLoc(), VT, Op0, Op1);
17398 return OptimizeConditionalInDecrement(N, DAG);
17401 /// performVZEXTCombine - Performs build vector combines
17402 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
17403 TargetLowering::DAGCombinerInfo &DCI,
17404 const X86Subtarget *Subtarget) {
17405 // (vzext (bitcast (vzext (x)) -> (vzext x)
17406 SDValue In = N->getOperand(0);
17407 while (In.getOpcode() == ISD::BITCAST)
17408 In = In.getOperand(0);
17410 if (In.getOpcode() != X86ISD::VZEXT)
17413 return DAG.getNode(X86ISD::VZEXT, N->getDebugLoc(), N->getValueType(0), In.getOperand(0));
17416 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
17417 DAGCombinerInfo &DCI) const {
17418 SelectionDAG &DAG = DCI.DAG;
17419 switch (N->getOpcode()) {
17421 case ISD::EXTRACT_VECTOR_ELT:
17422 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
17424 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget);
17425 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
17426 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
17427 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
17428 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
17429 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
17432 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
17433 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
17434 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
17435 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
17436 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
17437 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
17438 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
17439 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
17440 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
17442 case X86ISD::FOR: return PerformFORCombine(N, DAG);
17444 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
17445 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
17446 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
17447 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
17448 case ISD::ANY_EXTEND:
17449 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
17450 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
17451 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
17452 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG);
17453 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
17454 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
17455 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
17456 case X86ISD::SHUFP: // Handle all target specific shuffles
17457 case X86ISD::PALIGNR:
17458 case X86ISD::UNPCKH:
17459 case X86ISD::UNPCKL:
17460 case X86ISD::MOVHLPS:
17461 case X86ISD::MOVLHPS:
17462 case X86ISD::PSHUFD:
17463 case X86ISD::PSHUFHW:
17464 case X86ISD::PSHUFLW:
17465 case X86ISD::MOVSS:
17466 case X86ISD::MOVSD:
17467 case X86ISD::VPERMILP:
17468 case X86ISD::VPERM2X128:
17469 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
17470 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
17476 /// isTypeDesirableForOp - Return true if the target has native support for
17477 /// the specified value type and it is 'desirable' to use the type for the
17478 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
17479 /// instruction encodings are longer and some i16 instructions are slow.
17480 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
17481 if (!isTypeLegal(VT))
17483 if (VT != MVT::i16)
17490 case ISD::SIGN_EXTEND:
17491 case ISD::ZERO_EXTEND:
17492 case ISD::ANY_EXTEND:
17505 /// IsDesirableToPromoteOp - This method query the target whether it is
17506 /// beneficial for dag combiner to promote the specified node. If true, it
17507 /// should return the desired promotion type by reference.
17508 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
17509 EVT VT = Op.getValueType();
17510 if (VT != MVT::i16)
17513 bool Promote = false;
17514 bool Commute = false;
17515 switch (Op.getOpcode()) {
17518 LoadSDNode *LD = cast<LoadSDNode>(Op);
17519 // If the non-extending load has a single use and it's not live out, then it
17520 // might be folded.
17521 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
17522 Op.hasOneUse()*/) {
17523 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
17524 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
17525 // The only case where we'd want to promote LOAD (rather then it being
17526 // promoted as an operand is when it's only use is liveout.
17527 if (UI->getOpcode() != ISD::CopyToReg)
17534 case ISD::SIGN_EXTEND:
17535 case ISD::ZERO_EXTEND:
17536 case ISD::ANY_EXTEND:
17541 SDValue N0 = Op.getOperand(0);
17542 // Look out for (store (shl (load), x)).
17543 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
17556 SDValue N0 = Op.getOperand(0);
17557 SDValue N1 = Op.getOperand(1);
17558 if (!Commute && MayFoldLoad(N1))
17560 // Avoid disabling potential load folding opportunities.
17561 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
17563 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
17573 //===----------------------------------------------------------------------===//
17574 // X86 Inline Assembly Support
17575 //===----------------------------------------------------------------------===//
17578 // Helper to match a string separated by whitespace.
17579 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
17580 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
17582 for (unsigned i = 0, e = args.size(); i != e; ++i) {
17583 StringRef piece(*args[i]);
17584 if (!s.startswith(piece)) // Check if the piece matches.
17587 s = s.substr(piece.size());
17588 StringRef::size_type pos = s.find_first_not_of(" \t");
17589 if (pos == 0) // We matched a prefix.
17597 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
17600 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
17601 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
17603 std::string AsmStr = IA->getAsmString();
17605 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
17606 if (!Ty || Ty->getBitWidth() % 16 != 0)
17609 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
17610 SmallVector<StringRef, 4> AsmPieces;
17611 SplitString(AsmStr, AsmPieces, ";\n");
17613 switch (AsmPieces.size()) {
17614 default: return false;
17616 // FIXME: this should verify that we are targeting a 486 or better. If not,
17617 // we will turn this bswap into something that will be lowered to logical
17618 // ops instead of emitting the bswap asm. For now, we don't support 486 or
17619 // lower so don't worry about this.
17621 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
17622 matchAsm(AsmPieces[0], "bswapl", "$0") ||
17623 matchAsm(AsmPieces[0], "bswapq", "$0") ||
17624 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
17625 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
17626 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
17627 // No need to check constraints, nothing other than the equivalent of
17628 // "=r,0" would be valid here.
17629 return IntrinsicLowering::LowerToByteSwap(CI);
17632 // rorw $$8, ${0:w} --> llvm.bswap.i16
17633 if (CI->getType()->isIntegerTy(16) &&
17634 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
17635 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
17636 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
17638 const std::string &ConstraintsStr = IA->getConstraintString();
17639 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
17640 std::sort(AsmPieces.begin(), AsmPieces.end());
17641 if (AsmPieces.size() == 4 &&
17642 AsmPieces[0] == "~{cc}" &&
17643 AsmPieces[1] == "~{dirflag}" &&
17644 AsmPieces[2] == "~{flags}" &&
17645 AsmPieces[3] == "~{fpsr}")
17646 return IntrinsicLowering::LowerToByteSwap(CI);
17650 if (CI->getType()->isIntegerTy(32) &&
17651 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
17652 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
17653 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
17654 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
17656 const std::string &ConstraintsStr = IA->getConstraintString();
17657 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
17658 std::sort(AsmPieces.begin(), AsmPieces.end());
17659 if (AsmPieces.size() == 4 &&
17660 AsmPieces[0] == "~{cc}" &&
17661 AsmPieces[1] == "~{dirflag}" &&
17662 AsmPieces[2] == "~{flags}" &&
17663 AsmPieces[3] == "~{fpsr}")
17664 return IntrinsicLowering::LowerToByteSwap(CI);
17667 if (CI->getType()->isIntegerTy(64)) {
17668 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
17669 if (Constraints.size() >= 2 &&
17670 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
17671 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
17672 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
17673 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
17674 matchAsm(AsmPieces[1], "bswap", "%edx") &&
17675 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
17676 return IntrinsicLowering::LowerToByteSwap(CI);
17684 /// getConstraintType - Given a constraint letter, return the type of
17685 /// constraint it is for this target.
17686 X86TargetLowering::ConstraintType
17687 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
17688 if (Constraint.size() == 1) {
17689 switch (Constraint[0]) {
17700 return C_RegisterClass;
17724 return TargetLowering::getConstraintType(Constraint);
17727 /// Examine constraint type and operand type and determine a weight value.
17728 /// This object must already have been set up with the operand type
17729 /// and the current alternative constraint selected.
17730 TargetLowering::ConstraintWeight
17731 X86TargetLowering::getSingleConstraintMatchWeight(
17732 AsmOperandInfo &info, const char *constraint) const {
17733 ConstraintWeight weight = CW_Invalid;
17734 Value *CallOperandVal = info.CallOperandVal;
17735 // If we don't have a value, we can't do a match,
17736 // but allow it at the lowest weight.
17737 if (CallOperandVal == NULL)
17739 Type *type = CallOperandVal->getType();
17740 // Look at the constraint type.
17741 switch (*constraint) {
17743 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
17754 if (CallOperandVal->getType()->isIntegerTy())
17755 weight = CW_SpecificReg;
17760 if (type->isFloatingPointTy())
17761 weight = CW_SpecificReg;
17764 if (type->isX86_MMXTy() && Subtarget->hasMMX())
17765 weight = CW_SpecificReg;
17769 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
17770 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
17771 weight = CW_Register;
17774 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
17775 if (C->getZExtValue() <= 31)
17776 weight = CW_Constant;
17780 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
17781 if (C->getZExtValue() <= 63)
17782 weight = CW_Constant;
17786 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
17787 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
17788 weight = CW_Constant;
17792 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
17793 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
17794 weight = CW_Constant;
17798 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
17799 if (C->getZExtValue() <= 3)
17800 weight = CW_Constant;
17804 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
17805 if (C->getZExtValue() <= 0xff)
17806 weight = CW_Constant;
17811 if (dyn_cast<ConstantFP>(CallOperandVal)) {
17812 weight = CW_Constant;
17816 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
17817 if ((C->getSExtValue() >= -0x80000000LL) &&
17818 (C->getSExtValue() <= 0x7fffffffLL))
17819 weight = CW_Constant;
17823 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
17824 if (C->getZExtValue() <= 0xffffffff)
17825 weight = CW_Constant;
17832 /// LowerXConstraint - try to replace an X constraint, which matches anything,
17833 /// with another that has more specific requirements based on the type of the
17834 /// corresponding operand.
17835 const char *X86TargetLowering::
17836 LowerXConstraint(EVT ConstraintVT) const {
17837 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
17838 // 'f' like normal targets.
17839 if (ConstraintVT.isFloatingPoint()) {
17840 if (Subtarget->hasSSE2())
17842 if (Subtarget->hasSSE1())
17846 return TargetLowering::LowerXConstraint(ConstraintVT);
17849 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
17850 /// vector. If it is invalid, don't add anything to Ops.
17851 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
17852 std::string &Constraint,
17853 std::vector<SDValue>&Ops,
17854 SelectionDAG &DAG) const {
17855 SDValue Result(0, 0);
17857 // Only support length 1 constraints for now.
17858 if (Constraint.length() > 1) return;
17860 char ConstraintLetter = Constraint[0];
17861 switch (ConstraintLetter) {
17864 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
17865 if (C->getZExtValue() <= 31) {
17866 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
17872 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
17873 if (C->getZExtValue() <= 63) {
17874 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
17880 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
17881 if (isInt<8>(C->getSExtValue())) {
17882 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
17888 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
17889 if (C->getZExtValue() <= 255) {
17890 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
17896 // 32-bit signed value
17897 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
17898 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
17899 C->getSExtValue())) {
17900 // Widen to 64 bits here to get it sign extended.
17901 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
17904 // FIXME gcc accepts some relocatable values here too, but only in certain
17905 // memory models; it's complicated.
17910 // 32-bit unsigned value
17911 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
17912 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
17913 C->getZExtValue())) {
17914 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
17918 // FIXME gcc accepts some relocatable values here too, but only in certain
17919 // memory models; it's complicated.
17923 // Literal immediates are always ok.
17924 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
17925 // Widen to 64 bits here to get it sign extended.
17926 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
17930 // In any sort of PIC mode addresses need to be computed at runtime by
17931 // adding in a register or some sort of table lookup. These can't
17932 // be used as immediates.
17933 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
17936 // If we are in non-pic codegen mode, we allow the address of a global (with
17937 // an optional displacement) to be used with 'i'.
17938 GlobalAddressSDNode *GA = 0;
17939 int64_t Offset = 0;
17941 // Match either (GA), (GA+C), (GA+C1+C2), etc.
17943 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
17944 Offset += GA->getOffset();
17946 } else if (Op.getOpcode() == ISD::ADD) {
17947 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
17948 Offset += C->getZExtValue();
17949 Op = Op.getOperand(0);
17952 } else if (Op.getOpcode() == ISD::SUB) {
17953 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
17954 Offset += -C->getZExtValue();
17955 Op = Op.getOperand(0);
17960 // Otherwise, this isn't something we can handle, reject it.
17964 const GlobalValue *GV = GA->getGlobal();
17965 // If we require an extra load to get this address, as in PIC mode, we
17966 // can't accept it.
17967 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
17968 getTargetMachine())))
17971 Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(),
17972 GA->getValueType(0), Offset);
17977 if (Result.getNode()) {
17978 Ops.push_back(Result);
17981 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
17984 std::pair<unsigned, const TargetRegisterClass*>
17985 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
17987 // First, see if this is a constraint that directly corresponds to an LLVM
17989 if (Constraint.size() == 1) {
17990 // GCC Constraint Letters
17991 switch (Constraint[0]) {
17993 // TODO: Slight differences here in allocation order and leaving
17994 // RIP in the class. Do they matter any more here than they do
17995 // in the normal allocation?
17996 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
17997 if (Subtarget->is64Bit()) {
17998 if (VT == MVT::i32 || VT == MVT::f32)
17999 return std::make_pair(0U, &X86::GR32RegClass);
18000 if (VT == MVT::i16)
18001 return std::make_pair(0U, &X86::GR16RegClass);
18002 if (VT == MVT::i8 || VT == MVT::i1)
18003 return std::make_pair(0U, &X86::GR8RegClass);
18004 if (VT == MVT::i64 || VT == MVT::f64)
18005 return std::make_pair(0U, &X86::GR64RegClass);
18008 // 32-bit fallthrough
18009 case 'Q': // Q_REGS
18010 if (VT == MVT::i32 || VT == MVT::f32)
18011 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
18012 if (VT == MVT::i16)
18013 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
18014 if (VT == MVT::i8 || VT == MVT::i1)
18015 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
18016 if (VT == MVT::i64)
18017 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
18019 case 'r': // GENERAL_REGS
18020 case 'l': // INDEX_REGS
18021 if (VT == MVT::i8 || VT == MVT::i1)
18022 return std::make_pair(0U, &X86::GR8RegClass);
18023 if (VT == MVT::i16)
18024 return std::make_pair(0U, &X86::GR16RegClass);
18025 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
18026 return std::make_pair(0U, &X86::GR32RegClass);
18027 return std::make_pair(0U, &X86::GR64RegClass);
18028 case 'R': // LEGACY_REGS
18029 if (VT == MVT::i8 || VT == MVT::i1)
18030 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
18031 if (VT == MVT::i16)
18032 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
18033 if (VT == MVT::i32 || !Subtarget->is64Bit())
18034 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
18035 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
18036 case 'f': // FP Stack registers.
18037 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
18038 // value to the correct fpstack register class.
18039 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
18040 return std::make_pair(0U, &X86::RFP32RegClass);
18041 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
18042 return std::make_pair(0U, &X86::RFP64RegClass);
18043 return std::make_pair(0U, &X86::RFP80RegClass);
18044 case 'y': // MMX_REGS if MMX allowed.
18045 if (!Subtarget->hasMMX()) break;
18046 return std::make_pair(0U, &X86::VR64RegClass);
18047 case 'Y': // SSE_REGS if SSE2 allowed
18048 if (!Subtarget->hasSSE2()) break;
18050 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
18051 if (!Subtarget->hasSSE1()) break;
18053 switch (VT.getSimpleVT().SimpleTy) {
18055 // Scalar SSE types.
18058 return std::make_pair(0U, &X86::FR32RegClass);
18061 return std::make_pair(0U, &X86::FR64RegClass);
18069 return std::make_pair(0U, &X86::VR128RegClass);
18077 return std::make_pair(0U, &X86::VR256RegClass);
18083 // Use the default implementation in TargetLowering to convert the register
18084 // constraint into a member of a register class.
18085 std::pair<unsigned, const TargetRegisterClass*> Res;
18086 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
18088 // Not found as a standard register?
18089 if (Res.second == 0) {
18090 // Map st(0) -> st(7) -> ST0
18091 if (Constraint.size() == 7 && Constraint[0] == '{' &&
18092 tolower(Constraint[1]) == 's' &&
18093 tolower(Constraint[2]) == 't' &&
18094 Constraint[3] == '(' &&
18095 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
18096 Constraint[5] == ')' &&
18097 Constraint[6] == '}') {
18099 Res.first = X86::ST0+Constraint[4]-'0';
18100 Res.second = &X86::RFP80RegClass;
18104 // GCC allows "st(0)" to be called just plain "st".
18105 if (StringRef("{st}").equals_lower(Constraint)) {
18106 Res.first = X86::ST0;
18107 Res.second = &X86::RFP80RegClass;
18112 if (StringRef("{flags}").equals_lower(Constraint)) {
18113 Res.first = X86::EFLAGS;
18114 Res.second = &X86::CCRRegClass;
18118 // 'A' means EAX + EDX.
18119 if (Constraint == "A") {
18120 Res.first = X86::EAX;
18121 Res.second = &X86::GR32_ADRegClass;
18127 // Otherwise, check to see if this is a register class of the wrong value
18128 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
18129 // turn into {ax},{dx}.
18130 if (Res.second->hasType(VT))
18131 return Res; // Correct type already, nothing to do.
18133 // All of the single-register GCC register classes map their values onto
18134 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
18135 // really want an 8-bit or 32-bit register, map to the appropriate register
18136 // class and return the appropriate register.
18137 if (Res.second == &X86::GR16RegClass) {
18138 if (VT == MVT::i8) {
18139 unsigned DestReg = 0;
18140 switch (Res.first) {
18142 case X86::AX: DestReg = X86::AL; break;
18143 case X86::DX: DestReg = X86::DL; break;
18144 case X86::CX: DestReg = X86::CL; break;
18145 case X86::BX: DestReg = X86::BL; break;
18148 Res.first = DestReg;
18149 Res.second = &X86::GR8RegClass;
18151 } else if (VT == MVT::i32 || VT == MVT::f32) {
18152 unsigned DestReg = 0;
18153 switch (Res.first) {
18155 case X86::AX: DestReg = X86::EAX; break;
18156 case X86::DX: DestReg = X86::EDX; break;
18157 case X86::CX: DestReg = X86::ECX; break;
18158 case X86::BX: DestReg = X86::EBX; break;
18159 case X86::SI: DestReg = X86::ESI; break;
18160 case X86::DI: DestReg = X86::EDI; break;
18161 case X86::BP: DestReg = X86::EBP; break;
18162 case X86::SP: DestReg = X86::ESP; break;
18165 Res.first = DestReg;
18166 Res.second = &X86::GR32RegClass;
18168 } else if (VT == MVT::i64 || VT == MVT::f64) {
18169 unsigned DestReg = 0;
18170 switch (Res.first) {
18172 case X86::AX: DestReg = X86::RAX; break;
18173 case X86::DX: DestReg = X86::RDX; break;
18174 case X86::CX: DestReg = X86::RCX; break;
18175 case X86::BX: DestReg = X86::RBX; break;
18176 case X86::SI: DestReg = X86::RSI; break;
18177 case X86::DI: DestReg = X86::RDI; break;
18178 case X86::BP: DestReg = X86::RBP; break;
18179 case X86::SP: DestReg = X86::RSP; break;
18182 Res.first = DestReg;
18183 Res.second = &X86::GR64RegClass;
18186 } else if (Res.second == &X86::FR32RegClass ||
18187 Res.second == &X86::FR64RegClass ||
18188 Res.second == &X86::VR128RegClass) {
18189 // Handle references to XMM physical registers that got mapped into the
18190 // wrong class. This can happen with constraints like {xmm0} where the
18191 // target independent register mapper will just pick the first match it can
18192 // find, ignoring the required type.
18194 if (VT == MVT::f32 || VT == MVT::i32)
18195 Res.second = &X86::FR32RegClass;
18196 else if (VT == MVT::f64 || VT == MVT::i64)
18197 Res.second = &X86::FR64RegClass;
18198 else if (X86::VR128RegClass.hasType(VT))
18199 Res.second = &X86::VR128RegClass;
18200 else if (X86::VR256RegClass.hasType(VT))
18201 Res.second = &X86::VR256RegClass;