1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
17 #include "X86InstrBuilder.h"
18 #include "X86ISelLowering.h"
19 #include "X86TargetMachine.h"
20 #include "X86TargetObjectFile.h"
21 #include "Utils/X86ShuffleDecode.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/GlobalAlias.h"
26 #include "llvm/GlobalVariable.h"
27 #include "llvm/Function.h"
28 #include "llvm/Instructions.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/LLVMContext.h"
31 #include "llvm/CodeGen/IntrinsicLowering.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/CodeGen/MachineFunction.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineJumpTableInfo.h"
36 #include "llvm/CodeGen/MachineModuleInfo.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/MC/MCAsmInfo.h"
39 #include "llvm/MC/MCContext.h"
40 #include "llvm/MC/MCExpr.h"
41 #include "llvm/MC/MCSymbol.h"
42 #include "llvm/ADT/BitVector.h"
43 #include "llvm/ADT/SmallSet.h"
44 #include "llvm/ADT/Statistic.h"
45 #include "llvm/ADT/StringExtras.h"
46 #include "llvm/ADT/VariadicFunction.h"
47 #include "llvm/ADT/VectorExtras.h"
48 #include "llvm/Support/CallSite.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/Dwarf.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/MathExtras.h"
53 #include "llvm/Support/raw_ostream.h"
54 #include "llvm/Target/TargetOptions.h"
56 using namespace dwarf;
58 STATISTIC(NumTailCalls, "Number of tail calls");
60 // Forward declarations.
61 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
64 static SDValue Insert128BitVector(SDValue Result,
70 static SDValue Extract128BitVector(SDValue Vec,
75 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
76 /// sets things up to match to an AVX VEXTRACTF128 instruction or a
77 /// simple subregister reference. Idx is an index in the 128 bits we
78 /// want. It need not be aligned to a 128-bit bounday. That makes
79 /// lowering EXTRACT_VECTOR_ELT operations easier.
80 static SDValue Extract128BitVector(SDValue Vec,
84 EVT VT = Vec.getValueType();
85 assert(VT.getSizeInBits() == 256 && "Unexpected vector size!");
86 EVT ElVT = VT.getVectorElementType();
87 int Factor = VT.getSizeInBits()/128;
88 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
89 VT.getVectorNumElements()/Factor);
91 // Extract from UNDEF is UNDEF.
92 if (Vec.getOpcode() == ISD::UNDEF)
93 return DAG.getNode(ISD::UNDEF, dl, ResultVT);
95 if (isa<ConstantSDNode>(Idx)) {
96 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
98 // Extract the relevant 128 bits. Generate an EXTRACT_SUBVECTOR
99 // we can match to VEXTRACTF128.
100 unsigned ElemsPerChunk = 128 / ElVT.getSizeInBits();
102 // This is the index of the first element of the 128-bit chunk
104 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / 128)
107 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
108 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
117 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
118 /// sets things up to match to an AVX VINSERTF128 instruction or a
119 /// simple superregister reference. Idx is an index in the 128 bits
120 /// we want. It need not be aligned to a 128-bit bounday. That makes
121 /// lowering INSERT_VECTOR_ELT operations easier.
122 static SDValue Insert128BitVector(SDValue Result,
127 if (isa<ConstantSDNode>(Idx)) {
128 EVT VT = Vec.getValueType();
129 assert(VT.getSizeInBits() == 128 && "Unexpected vector size!");
131 EVT ElVT = VT.getVectorElementType();
132 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
133 EVT ResultVT = Result.getValueType();
135 // Insert the relevant 128 bits.
136 unsigned ElemsPerChunk = 128/ElVT.getSizeInBits();
138 // This is the index of the first element of the 128-bit chunk
140 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/128)
143 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
144 Result = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
152 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
153 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
154 bool is64Bit = Subtarget->is64Bit();
156 if (Subtarget->isTargetEnvMacho()) {
158 return new X8664_MachoTargetObjectFile();
159 return new TargetLoweringObjectFileMachO();
162 if (Subtarget->isTargetELF())
163 return new TargetLoweringObjectFileELF();
164 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
165 return new TargetLoweringObjectFileCOFF();
166 llvm_unreachable("unknown subtarget type");
169 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
170 : TargetLowering(TM, createTLOF(TM)) {
171 Subtarget = &TM.getSubtarget<X86Subtarget>();
172 X86ScalarSSEf64 = Subtarget->hasXMMInt();
173 X86ScalarSSEf32 = Subtarget->hasXMM();
174 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
176 RegInfo = TM.getRegisterInfo();
177 TD = getTargetData();
179 // Set up the TargetLowering object.
180 static MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
182 // X86 is weird, it always uses i8 for shift amounts and setcc results.
183 setBooleanContents(ZeroOrOneBooleanContent);
184 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
185 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
187 // For 64-bit since we have so many registers use the ILP scheduler, for
188 // 32-bit code use the register pressure specific scheduling.
189 if (Subtarget->is64Bit())
190 setSchedulingPreference(Sched::ILP);
192 setSchedulingPreference(Sched::RegPressure);
193 setStackPointerRegisterToSaveRestore(X86StackPtr);
195 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) {
196 // Setup Windows compiler runtime calls.
197 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
198 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
199 setLibcallName(RTLIB::SREM_I64, "_allrem");
200 setLibcallName(RTLIB::UREM_I64, "_aullrem");
201 setLibcallName(RTLIB::MUL_I64, "_allmul");
202 setLibcallName(RTLIB::FPTOUINT_F64_I64, "_ftol2");
203 setLibcallName(RTLIB::FPTOUINT_F32_I64, "_ftol2");
204 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
205 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
206 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
207 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
208 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
209 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I64, CallingConv::C);
210 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I64, CallingConv::C);
213 if (Subtarget->isTargetDarwin()) {
214 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
215 setUseUnderscoreSetJmp(false);
216 setUseUnderscoreLongJmp(false);
217 } else if (Subtarget->isTargetMingw()) {
218 // MS runtime is weird: it exports _setjmp, but longjmp!
219 setUseUnderscoreSetJmp(true);
220 setUseUnderscoreLongJmp(false);
222 setUseUnderscoreSetJmp(true);
223 setUseUnderscoreLongJmp(true);
226 // Set up the register classes.
227 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
228 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
229 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
230 if (Subtarget->is64Bit())
231 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
233 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
235 // We don't accept any truncstore of integer registers.
236 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
237 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
238 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
239 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
240 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
241 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
243 // SETOEQ and SETUNE require checking two conditions.
244 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
245 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
246 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
247 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
248 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
249 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
251 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
253 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
254 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
255 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
257 if (Subtarget->is64Bit()) {
258 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
259 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand);
260 } else if (!TM.Options.UseSoftFloat) {
261 // We have an algorithm for SSE2->double, and we turn this into a
262 // 64-bit FILD followed by conditional FADD for other targets.
263 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
264 // We have an algorithm for SSE2, and we turn this into a 64-bit
265 // FILD for other targets.
266 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
269 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
271 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
272 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
274 if (!TM.Options.UseSoftFloat) {
275 // SSE has no i16 to fp conversion, only i32
276 if (X86ScalarSSEf32) {
277 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
278 // f32 and f64 cases are Legal, f80 case is not
279 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
281 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
282 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
285 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
286 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
289 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
290 // are Legal, f80 is custom lowered.
291 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
292 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
294 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
296 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
297 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
299 if (X86ScalarSSEf32) {
300 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
301 // f32 and f64 cases are Legal, f80 case is not
302 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
304 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
305 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
308 // Handle FP_TO_UINT by promoting the destination to a larger signed
310 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
311 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
312 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
314 if (Subtarget->is64Bit()) {
315 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
316 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
317 } else if (!TM.Options.UseSoftFloat) {
318 // Since AVX is a superset of SSE3, only check for SSE here.
319 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
320 // Expand FP_TO_UINT into a select.
321 // FIXME: We would like to use a Custom expander here eventually to do
322 // the optimal thing for SSE vs. the default expansion in the legalizer.
323 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
325 // With SSE3 we can use fisttpll to convert to a signed i64; without
326 // SSE, we're stuck with a fistpll.
327 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
330 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
331 if (!X86ScalarSSEf64) {
332 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
333 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
334 if (Subtarget->is64Bit()) {
335 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
336 // Without SSE, i64->f64 goes through memory.
337 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
341 // Scalar integer divide and remainder are lowered to use operations that
342 // produce two results, to match the available instructions. This exposes
343 // the two-result form to trivial CSE, which is able to combine x/y and x%y
344 // into a single instruction.
346 // Scalar integer multiply-high is also lowered to use two-result
347 // operations, to match the available instructions. However, plain multiply
348 // (low) operations are left as Legal, as there are single-result
349 // instructions for this in x86. Using the two-result multiply instructions
350 // when both high and low results are needed must be arranged by dagcombine.
351 for (unsigned i = 0, e = 4; i != e; ++i) {
353 setOperationAction(ISD::MULHS, VT, Expand);
354 setOperationAction(ISD::MULHU, VT, Expand);
355 setOperationAction(ISD::SDIV, VT, Expand);
356 setOperationAction(ISD::UDIV, VT, Expand);
357 setOperationAction(ISD::SREM, VT, Expand);
358 setOperationAction(ISD::UREM, VT, Expand);
360 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
361 setOperationAction(ISD::ADDC, VT, Custom);
362 setOperationAction(ISD::ADDE, VT, Custom);
363 setOperationAction(ISD::SUBC, VT, Custom);
364 setOperationAction(ISD::SUBE, VT, Custom);
367 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
368 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
369 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
370 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
371 if (Subtarget->is64Bit())
372 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
373 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
374 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
375 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
376 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
377 setOperationAction(ISD::FREM , MVT::f32 , Expand);
378 setOperationAction(ISD::FREM , MVT::f64 , Expand);
379 setOperationAction(ISD::FREM , MVT::f80 , Expand);
380 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
382 // Promote the i8 variants and force them on up to i32 which has a shorter
384 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
385 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
386 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
387 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
388 if (Subtarget->hasBMI()) {
389 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
390 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
391 if (Subtarget->is64Bit())
392 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
394 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
395 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
396 if (Subtarget->is64Bit())
397 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
400 if (Subtarget->hasLZCNT()) {
401 // When promoting the i8 variants, force them to i32 for a shorter
403 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
404 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
405 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
406 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
407 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
408 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
409 if (Subtarget->is64Bit())
410 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
412 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
413 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
414 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
415 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
416 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
417 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
418 if (Subtarget->is64Bit()) {
419 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
420 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
424 if (Subtarget->hasPOPCNT()) {
425 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
427 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
428 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
429 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
430 if (Subtarget->is64Bit())
431 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
434 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
435 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
437 // These should be promoted to a larger select which is supported.
438 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
439 // X86 wants to expand cmov itself.
440 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
441 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
442 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
443 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
444 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
445 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
446 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
447 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
448 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
449 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
450 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
451 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
452 if (Subtarget->is64Bit()) {
453 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
454 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
456 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
459 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
460 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
461 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
462 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
463 if (Subtarget->is64Bit())
464 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
465 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
466 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
467 if (Subtarget->is64Bit()) {
468 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
469 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
470 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
471 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
472 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
474 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
475 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
476 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
477 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
478 if (Subtarget->is64Bit()) {
479 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
480 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
481 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
484 if (Subtarget->hasXMM())
485 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
487 setOperationAction(ISD::MEMBARRIER , MVT::Other, Custom);
488 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
490 // On X86 and X86-64, atomic operations are lowered to locked instructions.
491 // Locked instructions, in turn, have implicit fence semantics (all memory
492 // operations are flushed before issuing the locked instruction, and they
493 // are not buffered), so we can fold away the common pattern of
494 // fence-atomic-fence.
495 setShouldFoldAtomicFences(true);
497 // Expand certain atomics
498 for (unsigned i = 0, e = 4; i != e; ++i) {
500 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom);
501 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
502 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
505 if (!Subtarget->is64Bit()) {
506 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
507 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
508 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
509 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
510 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
511 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
512 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
513 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
516 if (Subtarget->hasCmpxchg16b()) {
517 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom);
520 // FIXME - use subtarget debug flags
521 if (!Subtarget->isTargetDarwin() &&
522 !Subtarget->isTargetELF() &&
523 !Subtarget->isTargetCygMing()) {
524 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
527 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
528 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
529 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
530 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
531 if (Subtarget->is64Bit()) {
532 setExceptionPointerRegister(X86::RAX);
533 setExceptionSelectorRegister(X86::RDX);
535 setExceptionPointerRegister(X86::EAX);
536 setExceptionSelectorRegister(X86::EDX);
538 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
539 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
541 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
542 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
544 setOperationAction(ISD::TRAP, MVT::Other, Legal);
546 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
547 setOperationAction(ISD::VASTART , MVT::Other, Custom);
548 setOperationAction(ISD::VAEND , MVT::Other, Expand);
549 if (Subtarget->is64Bit()) {
550 setOperationAction(ISD::VAARG , MVT::Other, Custom);
551 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
553 setOperationAction(ISD::VAARG , MVT::Other, Expand);
554 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
557 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
558 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
560 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
561 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
562 MVT::i64 : MVT::i32, Custom);
563 else if (TM.Options.EnableSegmentedStacks)
564 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
565 MVT::i64 : MVT::i32, Custom);
567 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
568 MVT::i64 : MVT::i32, Expand);
570 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
571 // f32 and f64 use SSE.
572 // Set up the FP register classes.
573 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
574 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
576 // Use ANDPD to simulate FABS.
577 setOperationAction(ISD::FABS , MVT::f64, Custom);
578 setOperationAction(ISD::FABS , MVT::f32, Custom);
580 // Use XORP to simulate FNEG.
581 setOperationAction(ISD::FNEG , MVT::f64, Custom);
582 setOperationAction(ISD::FNEG , MVT::f32, Custom);
584 // Use ANDPD and ORPD to simulate FCOPYSIGN.
585 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
586 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
588 // Lower this to FGETSIGNx86 plus an AND.
589 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
590 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
592 // We don't support sin/cos/fmod
593 setOperationAction(ISD::FSIN , MVT::f64, Expand);
594 setOperationAction(ISD::FCOS , MVT::f64, Expand);
595 setOperationAction(ISD::FSIN , MVT::f32, Expand);
596 setOperationAction(ISD::FCOS , MVT::f32, Expand);
598 // Expand FP immediates into loads from the stack, except for the special
600 addLegalFPImmediate(APFloat(+0.0)); // xorpd
601 addLegalFPImmediate(APFloat(+0.0f)); // xorps
602 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
603 // Use SSE for f32, x87 for f64.
604 // Set up the FP register classes.
605 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
606 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
608 // Use ANDPS to simulate FABS.
609 setOperationAction(ISD::FABS , MVT::f32, Custom);
611 // Use XORP to simulate FNEG.
612 setOperationAction(ISD::FNEG , MVT::f32, Custom);
614 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
616 // Use ANDPS and ORPS to simulate FCOPYSIGN.
617 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
618 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
620 // We don't support sin/cos/fmod
621 setOperationAction(ISD::FSIN , MVT::f32, Expand);
622 setOperationAction(ISD::FCOS , MVT::f32, Expand);
624 // Special cases we handle for FP constants.
625 addLegalFPImmediate(APFloat(+0.0f)); // xorps
626 addLegalFPImmediate(APFloat(+0.0)); // FLD0
627 addLegalFPImmediate(APFloat(+1.0)); // FLD1
628 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
629 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
631 if (!TM.Options.UnsafeFPMath) {
632 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
633 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
635 } else if (!TM.Options.UseSoftFloat) {
636 // f32 and f64 in x87.
637 // Set up the FP register classes.
638 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
639 addRegisterClass(MVT::f32, X86::RFP32RegisterClass);
641 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
642 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
643 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
644 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
646 if (!TM.Options.UnsafeFPMath) {
647 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
648 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
650 addLegalFPImmediate(APFloat(+0.0)); // FLD0
651 addLegalFPImmediate(APFloat(+1.0)); // FLD1
652 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
653 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
654 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
655 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
656 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
657 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
660 // We don't support FMA.
661 setOperationAction(ISD::FMA, MVT::f64, Expand);
662 setOperationAction(ISD::FMA, MVT::f32, Expand);
664 // Long double always uses X87.
665 if (!TM.Options.UseSoftFloat) {
666 addRegisterClass(MVT::f80, X86::RFP80RegisterClass);
667 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
668 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
670 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
671 addLegalFPImmediate(TmpFlt); // FLD0
673 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
676 APFloat TmpFlt2(+1.0);
677 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
679 addLegalFPImmediate(TmpFlt2); // FLD1
680 TmpFlt2.changeSign();
681 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
684 if (!TM.Options.UnsafeFPMath) {
685 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
686 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
689 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
690 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
691 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
692 setOperationAction(ISD::FRINT, MVT::f80, Expand);
693 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
694 setOperationAction(ISD::FMA, MVT::f80, Expand);
697 // Always use a library call for pow.
698 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
699 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
700 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
702 setOperationAction(ISD::FLOG, MVT::f80, Expand);
703 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
704 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
705 setOperationAction(ISD::FEXP, MVT::f80, Expand);
706 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
708 // First set operation action for all vector types to either promote
709 // (for widening) or expand (for scalarization). Then we will selectively
710 // turn on ones that can be effectively codegen'd.
711 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
712 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
713 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
714 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
715 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
716 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
717 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
718 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
719 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
720 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
721 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
722 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
723 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
724 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
725 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
726 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
727 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
728 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
729 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
730 setOperationAction(ISD::INSERT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
731 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
732 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
733 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
734 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
735 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
736 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
737 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
738 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
739 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
740 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
741 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
742 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
743 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
744 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
745 setOperationAction(ISD::CTTZ_ZERO_UNDEF, (MVT::SimpleValueType)VT, Expand);
746 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
747 setOperationAction(ISD::CTLZ_ZERO_UNDEF, (MVT::SimpleValueType)VT, Expand);
748 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
749 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
750 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
751 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
752 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
753 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
754 setOperationAction(ISD::SETCC, (MVT::SimpleValueType)VT, Expand);
755 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
756 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
757 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
758 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand);
759 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand);
760 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand);
761 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand);
762 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
763 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
764 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand);
765 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand);
766 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand);
767 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand);
768 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand);
769 setOperationAction(ISD::VSELECT, (MVT::SimpleValueType)VT, Expand);
770 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
771 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
772 setTruncStoreAction((MVT::SimpleValueType)VT,
773 (MVT::SimpleValueType)InnerVT, Expand);
774 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
775 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
776 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
779 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
780 // with -msoft-float, disable use of MMX as well.
781 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
782 addRegisterClass(MVT::x86mmx, X86::VR64RegisterClass);
783 // No operations on x86mmx supported, everything uses intrinsics.
786 // MMX-sized vectors (other than x86mmx) are expected to be expanded
787 // into smaller operations.
788 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
789 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
790 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
791 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
792 setOperationAction(ISD::AND, MVT::v8i8, Expand);
793 setOperationAction(ISD::AND, MVT::v4i16, Expand);
794 setOperationAction(ISD::AND, MVT::v2i32, Expand);
795 setOperationAction(ISD::AND, MVT::v1i64, Expand);
796 setOperationAction(ISD::OR, MVT::v8i8, Expand);
797 setOperationAction(ISD::OR, MVT::v4i16, Expand);
798 setOperationAction(ISD::OR, MVT::v2i32, Expand);
799 setOperationAction(ISD::OR, MVT::v1i64, Expand);
800 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
801 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
802 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
803 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
804 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
805 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
806 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
807 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
808 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
809 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
810 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
811 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
812 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
813 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
814 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
815 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
816 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
818 if (!TM.Options.UseSoftFloat && Subtarget->hasXMM()) {
819 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
821 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
822 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
823 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
824 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
825 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
826 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
827 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
828 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
829 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
830 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
831 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
832 setOperationAction(ISD::SETCC, MVT::v4f32, Custom);
835 if (!TM.Options.UseSoftFloat && Subtarget->hasXMMInt()) {
836 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
838 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
839 // registers cannot be used even for integer operations.
840 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
841 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
842 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
843 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
845 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
846 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
847 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
848 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
849 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
850 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
851 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
852 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
853 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
854 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
855 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
856 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
857 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
858 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
859 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
860 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
862 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
863 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
864 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
865 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
867 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
868 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
869 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
870 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
871 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
873 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Custom);
874 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Custom);
875 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom);
876 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom);
877 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
879 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
880 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) {
881 EVT VT = (MVT::SimpleValueType)i;
882 // Do not attempt to custom lower non-power-of-2 vectors
883 if (!isPowerOf2_32(VT.getVectorNumElements()))
885 // Do not attempt to custom lower non-128-bit vectors
886 if (!VT.is128BitVector())
888 setOperationAction(ISD::BUILD_VECTOR,
889 VT.getSimpleVT().SimpleTy, Custom);
890 setOperationAction(ISD::VECTOR_SHUFFLE,
891 VT.getSimpleVT().SimpleTy, Custom);
892 setOperationAction(ISD::EXTRACT_VECTOR_ELT,
893 VT.getSimpleVT().SimpleTy, Custom);
896 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
897 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
898 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
899 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
900 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
901 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
903 if (Subtarget->is64Bit()) {
904 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
905 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
908 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
909 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) {
910 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
913 // Do not attempt to promote non-128-bit vectors
914 if (!VT.is128BitVector())
917 setOperationAction(ISD::AND, SVT, Promote);
918 AddPromotedToType (ISD::AND, SVT, MVT::v2i64);
919 setOperationAction(ISD::OR, SVT, Promote);
920 AddPromotedToType (ISD::OR, SVT, MVT::v2i64);
921 setOperationAction(ISD::XOR, SVT, Promote);
922 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64);
923 setOperationAction(ISD::LOAD, SVT, Promote);
924 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64);
925 setOperationAction(ISD::SELECT, SVT, Promote);
926 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64);
929 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
931 // Custom lower v2i64 and v2f64 selects.
932 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
933 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
934 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
935 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
937 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
938 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
941 if (Subtarget->hasSSE41orAVX()) {
942 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
943 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
944 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
945 setOperationAction(ISD::FRINT, MVT::f32, Legal);
946 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
947 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
948 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
949 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
950 setOperationAction(ISD::FRINT, MVT::f64, Legal);
951 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
953 // FIXME: Do we need to handle scalar-to-vector here?
954 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
956 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
957 setOperationAction(ISD::VSELECT, MVT::v2i64, Legal);
958 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
959 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
960 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
962 // i8 and i16 vectors are custom , because the source register and source
963 // source memory operand types are not the same width. f32 vectors are
964 // custom since the immediate controlling the insert encodes additional
966 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
967 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
968 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
969 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
971 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
972 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
973 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
974 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
976 // FIXME: these should be Legal but thats only for the case where
977 // the index is constant. For now custom expand to deal with that.
978 if (Subtarget->is64Bit()) {
979 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
980 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
984 if (Subtarget->hasXMMInt()) {
985 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
986 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
988 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
989 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
991 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
992 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
994 if (Subtarget->hasAVX2()) {
995 setOperationAction(ISD::SRL, MVT::v2i64, Legal);
996 setOperationAction(ISD::SRL, MVT::v4i32, Legal);
998 setOperationAction(ISD::SHL, MVT::v2i64, Legal);
999 setOperationAction(ISD::SHL, MVT::v4i32, Legal);
1001 setOperationAction(ISD::SRA, MVT::v4i32, Legal);
1003 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1004 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1006 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1007 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1009 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1013 if (Subtarget->hasSSE42orAVX())
1014 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
1016 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX()) {
1017 addRegisterClass(MVT::v32i8, X86::VR256RegisterClass);
1018 addRegisterClass(MVT::v16i16, X86::VR256RegisterClass);
1019 addRegisterClass(MVT::v8i32, X86::VR256RegisterClass);
1020 addRegisterClass(MVT::v8f32, X86::VR256RegisterClass);
1021 addRegisterClass(MVT::v4i64, X86::VR256RegisterClass);
1022 addRegisterClass(MVT::v4f64, X86::VR256RegisterClass);
1024 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1025 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1026 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1028 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1029 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1030 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1031 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1032 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1033 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1035 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1036 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1037 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1038 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1039 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1040 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1042 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1043 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1044 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1046 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f64, Custom);
1047 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i64, Custom);
1048 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom);
1049 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom);
1050 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i8, Custom);
1051 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i16, Custom);
1053 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1054 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1056 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1057 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1059 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1060 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1062 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1063 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1064 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1065 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1067 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1068 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1069 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1071 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal);
1072 setOperationAction(ISD::VSELECT, MVT::v4i64, Legal);
1073 setOperationAction(ISD::VSELECT, MVT::v8i32, Legal);
1074 setOperationAction(ISD::VSELECT, MVT::v8f32, Legal);
1076 if (Subtarget->hasAVX2()) {
1077 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1078 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1079 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1080 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1082 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1083 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1084 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1085 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1087 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1088 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1089 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1090 // Don't lower v32i8 because there is no 128-bit byte mul
1092 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1094 setOperationAction(ISD::SRL, MVT::v4i64, Legal);
1095 setOperationAction(ISD::SRL, MVT::v8i32, Legal);
1097 setOperationAction(ISD::SHL, MVT::v4i64, Legal);
1098 setOperationAction(ISD::SHL, MVT::v8i32, Legal);
1100 setOperationAction(ISD::SRA, MVT::v8i32, Legal);
1102 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1103 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1104 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1105 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1107 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1108 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1109 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1110 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1112 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1113 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1114 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1115 // Don't lower v32i8 because there is no 128-bit byte mul
1117 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1118 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1120 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1121 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1123 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1126 // Custom lower several nodes for 256-bit types.
1127 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
1128 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
1129 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
1132 // Extract subvector is special because the value type
1133 // (result) is 128-bit but the source is 256-bit wide.
1134 if (VT.is128BitVector())
1135 setOperationAction(ISD::EXTRACT_SUBVECTOR, SVT, Custom);
1137 // Do not attempt to custom lower other non-256-bit vectors
1138 if (!VT.is256BitVector())
1141 setOperationAction(ISD::BUILD_VECTOR, SVT, Custom);
1142 setOperationAction(ISD::VECTOR_SHUFFLE, SVT, Custom);
1143 setOperationAction(ISD::INSERT_VECTOR_ELT, SVT, Custom);
1144 setOperationAction(ISD::EXTRACT_VECTOR_ELT, SVT, Custom);
1145 setOperationAction(ISD::SCALAR_TO_VECTOR, SVT, Custom);
1146 setOperationAction(ISD::INSERT_SUBVECTOR, SVT, Custom);
1149 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1150 for (unsigned i = (unsigned)MVT::v32i8; i != (unsigned)MVT::v4i64; ++i) {
1151 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
1154 // Do not attempt to promote non-256-bit vectors
1155 if (!VT.is256BitVector())
1158 setOperationAction(ISD::AND, SVT, Promote);
1159 AddPromotedToType (ISD::AND, SVT, MVT::v4i64);
1160 setOperationAction(ISD::OR, SVT, Promote);
1161 AddPromotedToType (ISD::OR, SVT, MVT::v4i64);
1162 setOperationAction(ISD::XOR, SVT, Promote);
1163 AddPromotedToType (ISD::XOR, SVT, MVT::v4i64);
1164 setOperationAction(ISD::LOAD, SVT, Promote);
1165 AddPromotedToType (ISD::LOAD, SVT, MVT::v4i64);
1166 setOperationAction(ISD::SELECT, SVT, Promote);
1167 AddPromotedToType (ISD::SELECT, SVT, MVT::v4i64);
1171 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1172 // of this type with custom code.
1173 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
1174 VT != (unsigned)MVT::LAST_VECTOR_VALUETYPE; VT++) {
1175 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1179 // We want to custom lower some of our intrinsics.
1180 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1183 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1184 // handle type legalization for these operations here.
1186 // FIXME: We really should do custom legalization for addition and
1187 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1188 // than generic legalization for 64-bit multiplication-with-overflow, though.
1189 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1190 // Add/Sub/Mul with overflow operations are custom lowered.
1192 setOperationAction(ISD::SADDO, VT, Custom);
1193 setOperationAction(ISD::UADDO, VT, Custom);
1194 setOperationAction(ISD::SSUBO, VT, Custom);
1195 setOperationAction(ISD::USUBO, VT, Custom);
1196 setOperationAction(ISD::SMULO, VT, Custom);
1197 setOperationAction(ISD::UMULO, VT, Custom);
1200 // There are no 8-bit 3-address imul/mul instructions
1201 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1202 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1204 if (!Subtarget->is64Bit()) {
1205 // These libcalls are not available in 32-bit.
1206 setLibcallName(RTLIB::SHL_I128, 0);
1207 setLibcallName(RTLIB::SRL_I128, 0);
1208 setLibcallName(RTLIB::SRA_I128, 0);
1211 // We have target-specific dag combine patterns for the following nodes:
1212 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1213 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1214 setTargetDAGCombine(ISD::VSELECT);
1215 setTargetDAGCombine(ISD::SELECT);
1216 setTargetDAGCombine(ISD::SHL);
1217 setTargetDAGCombine(ISD::SRA);
1218 setTargetDAGCombine(ISD::SRL);
1219 setTargetDAGCombine(ISD::OR);
1220 setTargetDAGCombine(ISD::AND);
1221 setTargetDAGCombine(ISD::ADD);
1222 setTargetDAGCombine(ISD::FADD);
1223 setTargetDAGCombine(ISD::FSUB);
1224 setTargetDAGCombine(ISD::SUB);
1225 setTargetDAGCombine(ISD::LOAD);
1226 setTargetDAGCombine(ISD::STORE);
1227 setTargetDAGCombine(ISD::ZERO_EXTEND);
1228 setTargetDAGCombine(ISD::SINT_TO_FP);
1229 if (Subtarget->is64Bit())
1230 setTargetDAGCombine(ISD::MUL);
1231 if (Subtarget->hasBMI())
1232 setTargetDAGCombine(ISD::XOR);
1234 computeRegisterProperties();
1236 // On Darwin, -Os means optimize for size without hurting performance,
1237 // do not reduce the limit.
1238 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1239 maxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1240 maxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1241 maxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1242 maxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1243 maxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1244 setPrefLoopAlignment(4); // 2^4 bytes.
1245 benefitFromCodePlacementOpt = true;
1247 setPrefFunctionAlignment(4); // 2^4 bytes.
1251 EVT X86TargetLowering::getSetCCResultType(EVT VT) const {
1252 if (!VT.isVector()) return MVT::i8;
1253 return VT.changeVectorElementTypeToInteger();
1257 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1258 /// the desired ByVal argument alignment.
1259 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1262 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1263 if (VTy->getBitWidth() == 128)
1265 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1266 unsigned EltAlign = 0;
1267 getMaxByValAlign(ATy->getElementType(), EltAlign);
1268 if (EltAlign > MaxAlign)
1269 MaxAlign = EltAlign;
1270 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1271 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1272 unsigned EltAlign = 0;
1273 getMaxByValAlign(STy->getElementType(i), EltAlign);
1274 if (EltAlign > MaxAlign)
1275 MaxAlign = EltAlign;
1283 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1284 /// function arguments in the caller parameter area. For X86, aggregates
1285 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1286 /// are at 4-byte boundaries.
1287 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1288 if (Subtarget->is64Bit()) {
1289 // Max of 8 and alignment of type.
1290 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1297 if (Subtarget->hasXMM())
1298 getMaxByValAlign(Ty, Align);
1302 /// getOptimalMemOpType - Returns the target specific optimal type for load
1303 /// and store operations as a result of memset, memcpy, and memmove
1304 /// lowering. If DstAlign is zero that means it's safe to destination
1305 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1306 /// means there isn't a need to check it against alignment requirement,
1307 /// probably because the source does not need to be loaded. If
1308 /// 'IsZeroVal' is true, that means it's safe to return a
1309 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
1310 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
1311 /// constant so it does not need to be loaded.
1312 /// It returns EVT::Other if the type should be determined using generic
1313 /// target-independent logic.
1315 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1316 unsigned DstAlign, unsigned SrcAlign,
1319 MachineFunction &MF) const {
1320 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like
1321 // linux. This is because the stack realignment code can't handle certain
1322 // cases like PR2962. This should be removed when PR2962 is fixed.
1323 const Function *F = MF.getFunction();
1325 !F->hasFnAttr(Attribute::NoImplicitFloat)) {
1327 (Subtarget->isUnalignedMemAccessFast() ||
1328 ((DstAlign == 0 || DstAlign >= 16) &&
1329 (SrcAlign == 0 || SrcAlign >= 16))) &&
1330 Subtarget->getStackAlignment() >= 16) {
1331 if (Subtarget->hasAVX() &&
1332 Subtarget->getStackAlignment() >= 32)
1334 if (Subtarget->hasXMMInt())
1336 if (Subtarget->hasXMM())
1338 } else if (!MemcpyStrSrc && Size >= 8 &&
1339 !Subtarget->is64Bit() &&
1340 Subtarget->getStackAlignment() >= 8 &&
1341 Subtarget->hasXMMInt()) {
1342 // Do not use f64 to lower memcpy if source is string constant. It's
1343 // better to use i32 to avoid the loads.
1347 if (Subtarget->is64Bit() && Size >= 8)
1352 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1353 /// current function. The returned value is a member of the
1354 /// MachineJumpTableInfo::JTEntryKind enum.
1355 unsigned X86TargetLowering::getJumpTableEncoding() const {
1356 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1358 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1359 Subtarget->isPICStyleGOT())
1360 return MachineJumpTableInfo::EK_Custom32;
1362 // Otherwise, use the normal jump table encoding heuristics.
1363 return TargetLowering::getJumpTableEncoding();
1367 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1368 const MachineBasicBlock *MBB,
1369 unsigned uid,MCContext &Ctx) const{
1370 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1371 Subtarget->isPICStyleGOT());
1372 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1374 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1375 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1378 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1380 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1381 SelectionDAG &DAG) const {
1382 if (!Subtarget->is64Bit())
1383 // This doesn't have DebugLoc associated with it, but is not really the
1384 // same as a Register.
1385 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy());
1389 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1390 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1392 const MCExpr *X86TargetLowering::
1393 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1394 MCContext &Ctx) const {
1395 // X86-64 uses RIP relative addressing based on the jump table label.
1396 if (Subtarget->isPICStyleRIPRel())
1397 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1399 // Otherwise, the reference is relative to the PIC base.
1400 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1403 // FIXME: Why this routine is here? Move to RegInfo!
1404 std::pair<const TargetRegisterClass*, uint8_t>
1405 X86TargetLowering::findRepresentativeClass(EVT VT) const{
1406 const TargetRegisterClass *RRC = 0;
1408 switch (VT.getSimpleVT().SimpleTy) {
1410 return TargetLowering::findRepresentativeClass(VT);
1411 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1412 RRC = (Subtarget->is64Bit()
1413 ? X86::GR64RegisterClass : X86::GR32RegisterClass);
1416 RRC = X86::VR64RegisterClass;
1418 case MVT::f32: case MVT::f64:
1419 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1420 case MVT::v4f32: case MVT::v2f64:
1421 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1423 RRC = X86::VR128RegisterClass;
1426 return std::make_pair(RRC, Cost);
1429 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1430 unsigned &Offset) const {
1431 if (!Subtarget->isTargetLinux())
1434 if (Subtarget->is64Bit()) {
1435 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1437 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1450 //===----------------------------------------------------------------------===//
1451 // Return Value Calling Convention Implementation
1452 //===----------------------------------------------------------------------===//
1454 #include "X86GenCallingConv.inc"
1457 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1458 MachineFunction &MF, bool isVarArg,
1459 const SmallVectorImpl<ISD::OutputArg> &Outs,
1460 LLVMContext &Context) const {
1461 SmallVector<CCValAssign, 16> RVLocs;
1462 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1464 return CCInfo.CheckReturn(Outs, RetCC_X86);
1468 X86TargetLowering::LowerReturn(SDValue Chain,
1469 CallingConv::ID CallConv, bool isVarArg,
1470 const SmallVectorImpl<ISD::OutputArg> &Outs,
1471 const SmallVectorImpl<SDValue> &OutVals,
1472 DebugLoc dl, SelectionDAG &DAG) const {
1473 MachineFunction &MF = DAG.getMachineFunction();
1474 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1476 SmallVector<CCValAssign, 16> RVLocs;
1477 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1478 RVLocs, *DAG.getContext());
1479 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1481 // Add the regs to the liveout set for the function.
1482 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
1483 for (unsigned i = 0; i != RVLocs.size(); ++i)
1484 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg()))
1485 MRI.addLiveOut(RVLocs[i].getLocReg());
1489 SmallVector<SDValue, 6> RetOps;
1490 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1491 // Operand #1 = Bytes To Pop
1492 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1495 // Copy the result values into the output registers.
1496 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1497 CCValAssign &VA = RVLocs[i];
1498 assert(VA.isRegLoc() && "Can only return in registers!");
1499 SDValue ValToCopy = OutVals[i];
1500 EVT ValVT = ValToCopy.getValueType();
1502 // If this is x86-64, and we disabled SSE, we can't return FP values,
1503 // or SSE or MMX vectors.
1504 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1505 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1506 (Subtarget->is64Bit() && !Subtarget->hasXMM())) {
1507 report_fatal_error("SSE register return with SSE disabled");
1509 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1510 // llvm-gcc has never done it right and no one has noticed, so this
1511 // should be OK for now.
1512 if (ValVT == MVT::f64 &&
1513 (Subtarget->is64Bit() && !Subtarget->hasXMMInt()))
1514 report_fatal_error("SSE2 register return with SSE2 disabled");
1516 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1517 // the RET instruction and handled by the FP Stackifier.
1518 if (VA.getLocReg() == X86::ST0 ||
1519 VA.getLocReg() == X86::ST1) {
1520 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1521 // change the value to the FP stack register class.
1522 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1523 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1524 RetOps.push_back(ValToCopy);
1525 // Don't emit a copytoreg.
1529 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1530 // which is returned in RAX / RDX.
1531 if (Subtarget->is64Bit()) {
1532 if (ValVT == MVT::x86mmx) {
1533 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1534 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1535 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1537 // If we don't have SSE2 available, convert to v4f32 so the generated
1538 // register is legal.
1539 if (!Subtarget->hasXMMInt())
1540 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1545 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1546 Flag = Chain.getValue(1);
1549 // The x86-64 ABI for returning structs by value requires that we copy
1550 // the sret argument into %rax for the return. We saved the argument into
1551 // a virtual register in the entry block, so now we copy the value out
1553 if (Subtarget->is64Bit() &&
1554 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1555 MachineFunction &MF = DAG.getMachineFunction();
1556 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1557 unsigned Reg = FuncInfo->getSRetReturnReg();
1559 "SRetReturnReg should have been set in LowerFormalArguments().");
1560 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1562 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag);
1563 Flag = Chain.getValue(1);
1565 // RAX now acts like a return value.
1566 MRI.addLiveOut(X86::RAX);
1569 RetOps[0] = Chain; // Update chain.
1571 // Add the flag if we have it.
1573 RetOps.push_back(Flag);
1575 return DAG.getNode(X86ISD::RET_FLAG, dl,
1576 MVT::Other, &RetOps[0], RetOps.size());
1579 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N) const {
1580 if (N->getNumValues() != 1)
1582 if (!N->hasNUsesOfValue(1, 0))
1585 SDNode *Copy = *N->use_begin();
1586 if (Copy->getOpcode() != ISD::CopyToReg &&
1587 Copy->getOpcode() != ISD::FP_EXTEND)
1590 bool HasRet = false;
1591 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1593 if (UI->getOpcode() != X86ISD::RET_FLAG)
1602 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
1603 ISD::NodeType ExtendKind) const {
1605 // TODO: Is this also valid on 32-bit?
1606 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
1607 ReturnMVT = MVT::i8;
1609 ReturnMVT = MVT::i32;
1611 EVT MinVT = getRegisterType(Context, ReturnMVT);
1612 return VT.bitsLT(MinVT) ? MinVT : VT;
1615 /// LowerCallResult - Lower the result values of a call into the
1616 /// appropriate copies out of appropriate physical registers.
1619 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1620 CallingConv::ID CallConv, bool isVarArg,
1621 const SmallVectorImpl<ISD::InputArg> &Ins,
1622 DebugLoc dl, SelectionDAG &DAG,
1623 SmallVectorImpl<SDValue> &InVals) const {
1625 // Assign locations to each value returned by this call.
1626 SmallVector<CCValAssign, 16> RVLocs;
1627 bool Is64Bit = Subtarget->is64Bit();
1628 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1629 getTargetMachine(), RVLocs, *DAG.getContext());
1630 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1632 // Copy all of the result registers out of their specified physreg.
1633 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1634 CCValAssign &VA = RVLocs[i];
1635 EVT CopyVT = VA.getValVT();
1637 // If this is x86-64, and we disabled SSE, we can't return FP values
1638 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1639 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasXMM())) {
1640 report_fatal_error("SSE register return with SSE disabled");
1645 // If this is a call to a function that returns an fp value on the floating
1646 // point stack, we must guarantee the the value is popped from the stack, so
1647 // a CopyFromReg is not good enough - the copy instruction may be eliminated
1648 // if the return value is not used. We use the FpPOP_RETVAL instruction
1650 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {
1651 // If we prefer to use the value in xmm registers, copy it out as f80 and
1652 // use a truncate to move it from fp stack reg to xmm reg.
1653 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
1654 SDValue Ops[] = { Chain, InFlag };
1655 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT,
1656 MVT::Other, MVT::Glue, Ops, 2), 1);
1657 Val = Chain.getValue(0);
1659 // Round the f80 to the right size, which also moves it to the appropriate
1661 if (CopyVT != VA.getValVT())
1662 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1663 // This truncation won't change the value.
1664 DAG.getIntPtrConstant(1));
1666 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1667 CopyVT, InFlag).getValue(1);
1668 Val = Chain.getValue(0);
1670 InFlag = Chain.getValue(2);
1671 InVals.push_back(Val);
1678 //===----------------------------------------------------------------------===//
1679 // C & StdCall & Fast Calling Convention implementation
1680 //===----------------------------------------------------------------------===//
1681 // StdCall calling convention seems to be standard for many Windows' API
1682 // routines and around. It differs from C calling convention just a little:
1683 // callee should clean up the stack, not caller. Symbols should be also
1684 // decorated in some fancy way :) It doesn't support any vector arguments.
1685 // For info on fast calling convention see Fast Calling Convention (tail call)
1686 // implementation LowerX86_32FastCCCallTo.
1688 /// CallIsStructReturn - Determines whether a call uses struct return
1690 static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
1694 return Outs[0].Flags.isSRet();
1697 /// ArgsAreStructReturn - Determines whether a function uses struct
1698 /// return semantics.
1700 ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
1704 return Ins[0].Flags.isSRet();
1707 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1708 /// by "Src" to address "Dst" with size and alignment information specified by
1709 /// the specific parameter attribute. The copy will be passed as a byval
1710 /// function parameter.
1712 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1713 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1715 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1717 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1718 /*isVolatile*/false, /*AlwaysInline=*/true,
1719 MachinePointerInfo(), MachinePointerInfo());
1722 /// IsTailCallConvention - Return true if the calling convention is one that
1723 /// supports tail call optimization.
1724 static bool IsTailCallConvention(CallingConv::ID CC) {
1725 return (CC == CallingConv::Fast || CC == CallingConv::GHC);
1728 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
1729 if (!CI->isTailCall())
1733 CallingConv::ID CalleeCC = CS.getCallingConv();
1734 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C)
1740 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
1741 /// a tailcall target by changing its ABI.
1742 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
1743 bool GuaranteedTailCallOpt) {
1744 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
1748 X86TargetLowering::LowerMemArgument(SDValue Chain,
1749 CallingConv::ID CallConv,
1750 const SmallVectorImpl<ISD::InputArg> &Ins,
1751 DebugLoc dl, SelectionDAG &DAG,
1752 const CCValAssign &VA,
1753 MachineFrameInfo *MFI,
1755 // Create the nodes corresponding to a load from this parameter slot.
1756 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1757 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv,
1758 getTargetMachine().Options.GuaranteedTailCallOpt);
1759 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1762 // If value is passed by pointer we have address passed instead of the value
1764 if (VA.getLocInfo() == CCValAssign::Indirect)
1765 ValVT = VA.getLocVT();
1767 ValVT = VA.getValVT();
1769 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1770 // changed with more analysis.
1771 // In case of tail call optimization mark all arguments mutable. Since they
1772 // could be overwritten by lowering of arguments in case of a tail call.
1773 if (Flags.isByVal()) {
1774 unsigned Bytes = Flags.getByValSize();
1775 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
1776 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
1777 return DAG.getFrameIndex(FI, getPointerTy());
1779 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
1780 VA.getLocMemOffset(), isImmutable);
1781 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1782 return DAG.getLoad(ValVT, dl, Chain, FIN,
1783 MachinePointerInfo::getFixedStack(FI),
1784 false, false, false, 0);
1789 X86TargetLowering::LowerFormalArguments(SDValue Chain,
1790 CallingConv::ID CallConv,
1792 const SmallVectorImpl<ISD::InputArg> &Ins,
1795 SmallVectorImpl<SDValue> &InVals)
1797 MachineFunction &MF = DAG.getMachineFunction();
1798 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1800 const Function* Fn = MF.getFunction();
1801 if (Fn->hasExternalLinkage() &&
1802 Subtarget->isTargetCygMing() &&
1803 Fn->getName() == "main")
1804 FuncInfo->setForceFramePointer(true);
1806 MachineFrameInfo *MFI = MF.getFrameInfo();
1807 bool Is64Bit = Subtarget->is64Bit();
1808 bool IsWin64 = Subtarget->isTargetWin64();
1810 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
1811 "Var args not supported with calling convention fastcc or ghc");
1813 // Assign locations to all of the incoming arguments.
1814 SmallVector<CCValAssign, 16> ArgLocs;
1815 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1816 ArgLocs, *DAG.getContext());
1818 // Allocate shadow area for Win64
1820 CCInfo.AllocateStack(32, 8);
1823 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
1825 unsigned LastVal = ~0U;
1827 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1828 CCValAssign &VA = ArgLocs[i];
1829 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1831 assert(VA.getValNo() != LastVal &&
1832 "Don't support value assigned to multiple locs yet");
1834 LastVal = VA.getValNo();
1836 if (VA.isRegLoc()) {
1837 EVT RegVT = VA.getLocVT();
1838 TargetRegisterClass *RC = NULL;
1839 if (RegVT == MVT::i32)
1840 RC = X86::GR32RegisterClass;
1841 else if (Is64Bit && RegVT == MVT::i64)
1842 RC = X86::GR64RegisterClass;
1843 else if (RegVT == MVT::f32)
1844 RC = X86::FR32RegisterClass;
1845 else if (RegVT == MVT::f64)
1846 RC = X86::FR64RegisterClass;
1847 else if (RegVT.isVector() && RegVT.getSizeInBits() == 256)
1848 RC = X86::VR256RegisterClass;
1849 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128)
1850 RC = X86::VR128RegisterClass;
1851 else if (RegVT == MVT::x86mmx)
1852 RC = X86::VR64RegisterClass;
1854 llvm_unreachable("Unknown argument type!");
1856 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1857 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1859 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1860 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1862 if (VA.getLocInfo() == CCValAssign::SExt)
1863 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1864 DAG.getValueType(VA.getValVT()));
1865 else if (VA.getLocInfo() == CCValAssign::ZExt)
1866 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1867 DAG.getValueType(VA.getValVT()));
1868 else if (VA.getLocInfo() == CCValAssign::BCvt)
1869 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
1871 if (VA.isExtInLoc()) {
1872 // Handle MMX values passed in XMM regs.
1873 if (RegVT.isVector()) {
1874 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(),
1877 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1880 assert(VA.isMemLoc());
1881 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
1884 // If value is passed via pointer - do a load.
1885 if (VA.getLocInfo() == CCValAssign::Indirect)
1886 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
1887 MachinePointerInfo(), false, false, false, 0);
1889 InVals.push_back(ArgValue);
1892 // The x86-64 ABI for returning structs by value requires that we copy
1893 // the sret argument into %rax for the return. Save the argument into
1894 // a virtual register so that we can access it from the return points.
1895 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) {
1896 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1897 unsigned Reg = FuncInfo->getSRetReturnReg();
1899 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1900 FuncInfo->setSRetReturnReg(Reg);
1902 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
1903 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
1906 unsigned StackSize = CCInfo.getNextStackOffset();
1907 // Align stack specially for tail calls.
1908 if (FuncIsMadeTailCallSafe(CallConv,
1909 MF.getTarget().Options.GuaranteedTailCallOpt))
1910 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1912 // If the function takes variable number of arguments, make a frame index for
1913 // the start of the first vararg value... for expansion of llvm.va_start.
1915 if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
1916 CallConv != CallingConv::X86_ThisCall)) {
1917 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
1920 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
1922 // FIXME: We should really autogenerate these arrays
1923 static const unsigned GPR64ArgRegsWin64[] = {
1924 X86::RCX, X86::RDX, X86::R8, X86::R9
1926 static const unsigned GPR64ArgRegs64Bit[] = {
1927 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1929 static const unsigned XMMArgRegs64Bit[] = {
1930 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1931 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1933 const unsigned *GPR64ArgRegs;
1934 unsigned NumXMMRegs = 0;
1937 // The XMM registers which might contain var arg parameters are shadowed
1938 // in their paired GPR. So we only need to save the GPR to their home
1940 TotalNumIntRegs = 4;
1941 GPR64ArgRegs = GPR64ArgRegsWin64;
1943 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
1944 GPR64ArgRegs = GPR64ArgRegs64Bit;
1946 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit,
1949 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
1952 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat);
1953 assert(!(NumXMMRegs && !Subtarget->hasXMM()) &&
1954 "SSE register cannot be used when SSE is disabled!");
1955 assert(!(NumXMMRegs && MF.getTarget().Options.UseSoftFloat &&
1956 NoImplicitFloatOps) &&
1957 "SSE register cannot be used when SSE is disabled!");
1958 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
1959 !Subtarget->hasXMM())
1960 // Kernel mode asks for SSE to be disabled, so don't push them
1962 TotalNumXMMRegs = 0;
1965 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering();
1966 // Get to the caller-allocated home save location. Add 8 to account
1967 // for the return address.
1968 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
1969 FuncInfo->setRegSaveFrameIndex(
1970 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
1971 // Fixup to set vararg frame on shadow area (4 x i64).
1973 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
1975 // For X86-64, if there are vararg parameters that are passed via
1976 // registers, then we must store them to their spots on the stack so
1977 // they may be loaded by deferencing the result of va_next.
1978 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
1979 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
1980 FuncInfo->setRegSaveFrameIndex(
1981 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
1985 // Store the integer parameter registers.
1986 SmallVector<SDValue, 8> MemOps;
1987 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
1989 unsigned Offset = FuncInfo->getVarArgsGPOffset();
1990 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
1991 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
1992 DAG.getIntPtrConstant(Offset));
1993 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
1994 X86::GR64RegisterClass);
1995 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
1997 DAG.getStore(Val.getValue(1), dl, Val, FIN,
1998 MachinePointerInfo::getFixedStack(
1999 FuncInfo->getRegSaveFrameIndex(), Offset),
2001 MemOps.push_back(Store);
2005 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
2006 // Now store the XMM (fp + vector) parameter registers.
2007 SmallVector<SDValue, 11> SaveXMMOps;
2008 SaveXMMOps.push_back(Chain);
2010 unsigned AL = MF.addLiveIn(X86::AL, X86::GR8RegisterClass);
2011 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
2012 SaveXMMOps.push_back(ALVal);
2014 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2015 FuncInfo->getRegSaveFrameIndex()));
2016 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2017 FuncInfo->getVarArgsFPOffset()));
2019 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
2020 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs],
2021 X86::VR128RegisterClass);
2022 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
2023 SaveXMMOps.push_back(Val);
2025 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2027 &SaveXMMOps[0], SaveXMMOps.size()));
2030 if (!MemOps.empty())
2031 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2032 &MemOps[0], MemOps.size());
2036 // Some CCs need callee pop.
2037 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2038 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2039 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2041 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2042 // If this is an sret function, the return should pop the hidden pointer.
2043 if (!Is64Bit && !IsTailCallConvention(CallConv) && ArgsAreStructReturn(Ins))
2044 FuncInfo->setBytesToPopOnReturn(4);
2048 // RegSaveFrameIndex is X86-64 only.
2049 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2050 if (CallConv == CallingConv::X86_FastCall ||
2051 CallConv == CallingConv::X86_ThisCall)
2052 // fastcc functions can't have varargs.
2053 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2056 FuncInfo->setArgumentStackSize(StackSize);
2062 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2063 SDValue StackPtr, SDValue Arg,
2064 DebugLoc dl, SelectionDAG &DAG,
2065 const CCValAssign &VA,
2066 ISD::ArgFlagsTy Flags) const {
2067 unsigned LocMemOffset = VA.getLocMemOffset();
2068 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2069 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2070 if (Flags.isByVal())
2071 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2073 return DAG.getStore(Chain, dl, Arg, PtrOff,
2074 MachinePointerInfo::getStack(LocMemOffset),
2078 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2079 /// optimization is performed and it is required.
2081 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2082 SDValue &OutRetAddr, SDValue Chain,
2083 bool IsTailCall, bool Is64Bit,
2084 int FPDiff, DebugLoc dl) const {
2085 // Adjust the Return address stack slot.
2086 EVT VT = getPointerTy();
2087 OutRetAddr = getReturnAddressFrameIndex(DAG);
2089 // Load the "old" Return address.
2090 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2091 false, false, false, 0);
2092 return SDValue(OutRetAddr.getNode(), 1);
2095 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2096 /// optimization is performed and it is required (FPDiff!=0).
2098 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
2099 SDValue Chain, SDValue RetAddrFrIdx,
2100 bool Is64Bit, int FPDiff, DebugLoc dl) {
2101 // Store the return address to the appropriate stack slot.
2102 if (!FPDiff) return Chain;
2103 // Calculate the new stack slot for the return address.
2104 int SlotSize = Is64Bit ? 8 : 4;
2105 int NewReturnAddrFI =
2106 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false);
2107 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
2108 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
2109 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2110 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2116 X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
2117 CallingConv::ID CallConv, bool isVarArg,
2119 const SmallVectorImpl<ISD::OutputArg> &Outs,
2120 const SmallVectorImpl<SDValue> &OutVals,
2121 const SmallVectorImpl<ISD::InputArg> &Ins,
2122 DebugLoc dl, SelectionDAG &DAG,
2123 SmallVectorImpl<SDValue> &InVals) const {
2124 MachineFunction &MF = DAG.getMachineFunction();
2125 bool Is64Bit = Subtarget->is64Bit();
2126 bool IsWin64 = Subtarget->isTargetWin64();
2127 bool IsStructRet = CallIsStructReturn(Outs);
2128 bool IsSibcall = false;
2131 // Check if it's really possible to do a tail call.
2132 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2133 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
2134 Outs, OutVals, Ins, DAG);
2136 // Sibcalls are automatically detected tailcalls which do not require
2138 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2145 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2146 "Var args not supported with calling convention fastcc or ghc");
2148 // Analyze operands of the call, assigning locations to each operand.
2149 SmallVector<CCValAssign, 16> ArgLocs;
2150 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
2151 ArgLocs, *DAG.getContext());
2153 // Allocate shadow area for Win64
2155 CCInfo.AllocateStack(32, 8);
2158 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2160 // Get a count of how many bytes are to be pushed on the stack.
2161 unsigned NumBytes = CCInfo.getNextStackOffset();
2163 // This is a sibcall. The memory operands are available in caller's
2164 // own caller's stack.
2166 else if (getTargetMachine().Options.GuaranteedTailCallOpt &&
2167 IsTailCallConvention(CallConv))
2168 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2171 if (isTailCall && !IsSibcall) {
2172 // Lower arguments at fp - stackoffset + fpdiff.
2173 unsigned NumBytesCallerPushed =
2174 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
2175 FPDiff = NumBytesCallerPushed - NumBytes;
2177 // Set the delta of movement of the returnaddr stackslot.
2178 // But only set if delta is greater than previous delta.
2179 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
2180 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
2184 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
2186 SDValue RetAddrFrIdx;
2187 // Load return address for tail calls.
2188 if (isTailCall && FPDiff)
2189 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2190 Is64Bit, FPDiff, dl);
2192 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2193 SmallVector<SDValue, 8> MemOpChains;
2196 // Walk the register/memloc assignments, inserting copies/loads. In the case
2197 // of tail call optimization arguments are handle later.
2198 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2199 CCValAssign &VA = ArgLocs[i];
2200 EVT RegVT = VA.getLocVT();
2201 SDValue Arg = OutVals[i];
2202 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2203 bool isByVal = Flags.isByVal();
2205 // Promote the value if needed.
2206 switch (VA.getLocInfo()) {
2207 default: llvm_unreachable("Unknown loc info!");
2208 case CCValAssign::Full: break;
2209 case CCValAssign::SExt:
2210 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2212 case CCValAssign::ZExt:
2213 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2215 case CCValAssign::AExt:
2216 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) {
2217 // Special case: passing MMX values in XMM registers.
2218 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2219 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2220 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2222 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2224 case CCValAssign::BCvt:
2225 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2227 case CCValAssign::Indirect: {
2228 // Store the argument.
2229 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2230 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2231 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2232 MachinePointerInfo::getFixedStack(FI),
2239 if (VA.isRegLoc()) {
2240 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2241 if (isVarArg && IsWin64) {
2242 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2243 // shadow reg if callee is a varargs function.
2244 unsigned ShadowReg = 0;
2245 switch (VA.getLocReg()) {
2246 case X86::XMM0: ShadowReg = X86::RCX; break;
2247 case X86::XMM1: ShadowReg = X86::RDX; break;
2248 case X86::XMM2: ShadowReg = X86::R8; break;
2249 case X86::XMM3: ShadowReg = X86::R9; break;
2252 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2254 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2255 assert(VA.isMemLoc());
2256 if (StackPtr.getNode() == 0)
2257 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy());
2258 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2259 dl, DAG, VA, Flags));
2263 if (!MemOpChains.empty())
2264 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2265 &MemOpChains[0], MemOpChains.size());
2267 // Build a sequence of copy-to-reg nodes chained together with token chain
2268 // and flag operands which copy the outgoing args into registers.
2270 // Tail call byval lowering might overwrite argument registers so in case of
2271 // tail call optimization the copies to registers are lowered later.
2273 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2274 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2275 RegsToPass[i].second, InFlag);
2276 InFlag = Chain.getValue(1);
2279 if (Subtarget->isPICStyleGOT()) {
2280 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2283 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX,
2284 DAG.getNode(X86ISD::GlobalBaseReg,
2285 DebugLoc(), getPointerTy()),
2287 InFlag = Chain.getValue(1);
2289 // If we are tail calling and generating PIC/GOT style code load the
2290 // address of the callee into ECX. The value in ecx is used as target of
2291 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2292 // for tail calls on PIC/GOT architectures. Normally we would just put the
2293 // address of GOT into ebx and then call target@PLT. But for tail calls
2294 // ebx would be restored (since ebx is callee saved) before jumping to the
2297 // Note: The actual moving to ECX is done further down.
2298 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2299 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2300 !G->getGlobal()->hasProtectedVisibility())
2301 Callee = LowerGlobalAddress(Callee, DAG);
2302 else if (isa<ExternalSymbolSDNode>(Callee))
2303 Callee = LowerExternalSymbol(Callee, DAG);
2307 if (Is64Bit && isVarArg && !IsWin64) {
2308 // From AMD64 ABI document:
2309 // For calls that may call functions that use varargs or stdargs
2310 // (prototype-less calls or calls to functions containing ellipsis (...) in
2311 // the declaration) %al is used as hidden argument to specify the number
2312 // of SSE registers used. The contents of %al do not need to match exactly
2313 // the number of registers, but must be an ubound on the number of SSE
2314 // registers used and is in the range 0 - 8 inclusive.
2316 // Count the number of XMM registers allocated.
2317 static const unsigned XMMArgRegs[] = {
2318 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2319 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2321 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2322 assert((Subtarget->hasXMM() || !NumXMMRegs)
2323 && "SSE registers cannot be used when SSE is disabled");
2325 Chain = DAG.getCopyToReg(Chain, dl, X86::AL,
2326 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
2327 InFlag = Chain.getValue(1);
2331 // For tail calls lower the arguments to the 'real' stack slot.
2333 // Force all the incoming stack arguments to be loaded from the stack
2334 // before any new outgoing arguments are stored to the stack, because the
2335 // outgoing stack slots may alias the incoming argument stack slots, and
2336 // the alias isn't otherwise explicit. This is slightly more conservative
2337 // than necessary, because it means that each store effectively depends
2338 // on every argument instead of just those arguments it would clobber.
2339 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2341 SmallVector<SDValue, 8> MemOpChains2;
2344 // Do not flag preceding copytoreg stuff together with the following stuff.
2346 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2347 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2348 CCValAssign &VA = ArgLocs[i];
2351 assert(VA.isMemLoc());
2352 SDValue Arg = OutVals[i];
2353 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2354 // Create frame index.
2355 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2356 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2357 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2358 FIN = DAG.getFrameIndex(FI, getPointerTy());
2360 if (Flags.isByVal()) {
2361 // Copy relative to framepointer.
2362 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2363 if (StackPtr.getNode() == 0)
2364 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr,
2366 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2368 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2372 // Store relative to framepointer.
2373 MemOpChains2.push_back(
2374 DAG.getStore(ArgChain, dl, Arg, FIN,
2375 MachinePointerInfo::getFixedStack(FI),
2381 if (!MemOpChains2.empty())
2382 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2383 &MemOpChains2[0], MemOpChains2.size());
2385 // Copy arguments to their registers.
2386 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2387 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2388 RegsToPass[i].second, InFlag);
2389 InFlag = Chain.getValue(1);
2393 // Store the return address to the appropriate stack slot.
2394 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
2398 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2399 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2400 // In the 64-bit large code model, we have to make all calls
2401 // through a register, since the call instruction's 32-bit
2402 // pc-relative offset may not be large enough to hold the whole
2404 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2405 // If the callee is a GlobalAddress node (quite common, every direct call
2406 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2409 // We should use extra load for direct calls to dllimported functions in
2411 const GlobalValue *GV = G->getGlobal();
2412 if (!GV->hasDLLImportLinkage()) {
2413 unsigned char OpFlags = 0;
2414 bool ExtraLoad = false;
2415 unsigned WrapperKind = ISD::DELETED_NODE;
2417 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2418 // external symbols most go through the PLT in PIC mode. If the symbol
2419 // has hidden or protected visibility, or if it is static or local, then
2420 // we don't need to use the PLT - we can directly call it.
2421 if (Subtarget->isTargetELF() &&
2422 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2423 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2424 OpFlags = X86II::MO_PLT;
2425 } else if (Subtarget->isPICStyleStubAny() &&
2426 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2427 (!Subtarget->getTargetTriple().isMacOSX() ||
2428 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2429 // PC-relative references to external symbols should go through $stub,
2430 // unless we're building with the leopard linker or later, which
2431 // automatically synthesizes these stubs.
2432 OpFlags = X86II::MO_DARWIN_STUB;
2433 } else if (Subtarget->isPICStyleRIPRel() &&
2434 isa<Function>(GV) &&
2435 cast<Function>(GV)->hasFnAttr(Attribute::NonLazyBind)) {
2436 // If the function is marked as non-lazy, generate an indirect call
2437 // which loads from the GOT directly. This avoids runtime overhead
2438 // at the cost of eager binding (and one extra byte of encoding).
2439 OpFlags = X86II::MO_GOTPCREL;
2440 WrapperKind = X86ISD::WrapperRIP;
2444 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2445 G->getOffset(), OpFlags);
2447 // Add a wrapper if needed.
2448 if (WrapperKind != ISD::DELETED_NODE)
2449 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
2450 // Add extra indirection if needed.
2452 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
2453 MachinePointerInfo::getGOT(),
2454 false, false, false, 0);
2456 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2457 unsigned char OpFlags = 0;
2459 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
2460 // external symbols should go through the PLT.
2461 if (Subtarget->isTargetELF() &&
2462 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2463 OpFlags = X86II::MO_PLT;
2464 } else if (Subtarget->isPICStyleStubAny() &&
2465 (!Subtarget->getTargetTriple().isMacOSX() ||
2466 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2467 // PC-relative references to external symbols should go through $stub,
2468 // unless we're building with the leopard linker or later, which
2469 // automatically synthesizes these stubs.
2470 OpFlags = X86II::MO_DARWIN_STUB;
2473 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2477 // Returns a chain & a flag for retval copy to use.
2478 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2479 SmallVector<SDValue, 8> Ops;
2481 if (!IsSibcall && isTailCall) {
2482 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2483 DAG.getIntPtrConstant(0, true), InFlag);
2484 InFlag = Chain.getValue(1);
2487 Ops.push_back(Chain);
2488 Ops.push_back(Callee);
2491 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2493 // Add argument registers to the end of the list so that they are known live
2495 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2496 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2497 RegsToPass[i].second.getValueType()));
2499 // Add an implicit use GOT pointer in EBX.
2500 if (!isTailCall && Subtarget->isPICStyleGOT())
2501 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
2503 // Add an implicit use of AL for non-Windows x86 64-bit vararg functions.
2504 if (Is64Bit && isVarArg && !IsWin64)
2505 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
2507 if (InFlag.getNode())
2508 Ops.push_back(InFlag);
2512 //// If this is the first return lowered for this function, add the regs
2513 //// to the liveout set for the function.
2514 // This isn't right, although it's probably harmless on x86; liveouts
2515 // should be computed from returns not tail calls. Consider a void
2516 // function making a tail call to a function returning int.
2517 return DAG.getNode(X86ISD::TC_RETURN, dl,
2518 NodeTys, &Ops[0], Ops.size());
2521 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2522 InFlag = Chain.getValue(1);
2524 // Create the CALLSEQ_END node.
2525 unsigned NumBytesForCalleeToPush;
2526 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2527 getTargetMachine().Options.GuaranteedTailCallOpt))
2528 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2529 else if (!Is64Bit && !IsTailCallConvention(CallConv) && IsStructRet)
2530 // If this is a call to a struct-return function, the callee
2531 // pops the hidden struct pointer, so we have to push it back.
2532 // This is common for Darwin/X86, Linux & Mingw32 targets.
2533 NumBytesForCalleeToPush = 4;
2535 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2537 // Returns a flag for retval copy to use.
2539 Chain = DAG.getCALLSEQ_END(Chain,
2540 DAG.getIntPtrConstant(NumBytes, true),
2541 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2544 InFlag = Chain.getValue(1);
2547 // Handle result values, copying them out of physregs into vregs that we
2549 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2550 Ins, dl, DAG, InVals);
2554 //===----------------------------------------------------------------------===//
2555 // Fast Calling Convention (tail call) implementation
2556 //===----------------------------------------------------------------------===//
2558 // Like std call, callee cleans arguments, convention except that ECX is
2559 // reserved for storing the tail called function address. Only 2 registers are
2560 // free for argument passing (inreg). Tail call optimization is performed
2562 // * tailcallopt is enabled
2563 // * caller/callee are fastcc
2564 // On X86_64 architecture with GOT-style position independent code only local
2565 // (within module) calls are supported at the moment.
2566 // To keep the stack aligned according to platform abi the function
2567 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2568 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2569 // If a tail called function callee has more arguments than the caller the
2570 // caller needs to make sure that there is room to move the RETADDR to. This is
2571 // achieved by reserving an area the size of the argument delta right after the
2572 // original REtADDR, but before the saved framepointer or the spilled registers
2573 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2585 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2586 /// for a 16 byte align requirement.
2588 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2589 SelectionDAG& DAG) const {
2590 MachineFunction &MF = DAG.getMachineFunction();
2591 const TargetMachine &TM = MF.getTarget();
2592 const TargetFrameLowering &TFI = *TM.getFrameLowering();
2593 unsigned StackAlignment = TFI.getStackAlignment();
2594 uint64_t AlignMask = StackAlignment - 1;
2595 int64_t Offset = StackSize;
2596 uint64_t SlotSize = TD->getPointerSize();
2597 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2598 // Number smaller than 12 so just add the difference.
2599 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2601 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2602 Offset = ((~AlignMask) & Offset) + StackAlignment +
2603 (StackAlignment-SlotSize);
2608 /// MatchingStackOffset - Return true if the given stack call argument is
2609 /// already available in the same position (relatively) of the caller's
2610 /// incoming argument stack.
2612 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2613 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
2614 const X86InstrInfo *TII) {
2615 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
2617 if (Arg.getOpcode() == ISD::CopyFromReg) {
2618 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2619 if (!TargetRegisterInfo::isVirtualRegister(VR))
2621 MachineInstr *Def = MRI->getVRegDef(VR);
2624 if (!Flags.isByVal()) {
2625 if (!TII->isLoadFromStackSlot(Def, FI))
2628 unsigned Opcode = Def->getOpcode();
2629 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
2630 Def->getOperand(1).isFI()) {
2631 FI = Def->getOperand(1).getIndex();
2632 Bytes = Flags.getByValSize();
2636 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2637 if (Flags.isByVal())
2638 // ByVal argument is passed in as a pointer but it's now being
2639 // dereferenced. e.g.
2640 // define @foo(%struct.X* %A) {
2641 // tail call @bar(%struct.X* byval %A)
2644 SDValue Ptr = Ld->getBasePtr();
2645 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2648 FI = FINode->getIndex();
2649 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
2650 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
2651 FI = FINode->getIndex();
2652 Bytes = Flags.getByValSize();
2656 assert(FI != INT_MAX);
2657 if (!MFI->isFixedObjectIndex(FI))
2659 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
2662 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2663 /// for tail call optimization. Targets which want to do tail call
2664 /// optimization should implement this function.
2666 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2667 CallingConv::ID CalleeCC,
2669 bool isCalleeStructRet,
2670 bool isCallerStructRet,
2671 const SmallVectorImpl<ISD::OutputArg> &Outs,
2672 const SmallVectorImpl<SDValue> &OutVals,
2673 const SmallVectorImpl<ISD::InputArg> &Ins,
2674 SelectionDAG& DAG) const {
2675 if (!IsTailCallConvention(CalleeCC) &&
2676 CalleeCC != CallingConv::C)
2679 // If -tailcallopt is specified, make fastcc functions tail-callable.
2680 const MachineFunction &MF = DAG.getMachineFunction();
2681 const Function *CallerF = DAG.getMachineFunction().getFunction();
2682 CallingConv::ID CallerCC = CallerF->getCallingConv();
2683 bool CCMatch = CallerCC == CalleeCC;
2685 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2686 if (IsTailCallConvention(CalleeCC) && CCMatch)
2691 // Look for obvious safe cases to perform tail call optimization that do not
2692 // require ABI changes. This is what gcc calls sibcall.
2694 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
2695 // emit a special epilogue.
2696 if (RegInfo->needsStackRealignment(MF))
2699 // Also avoid sibcall optimization if either caller or callee uses struct
2700 // return semantics.
2701 if (isCalleeStructRet || isCallerStructRet)
2704 // An stdcall caller is expected to clean up its arguments; the callee
2705 // isn't going to do that.
2706 if (!CCMatch && CallerCC==CallingConv::X86_StdCall)
2709 // Do not sibcall optimize vararg calls unless all arguments are passed via
2711 if (isVarArg && !Outs.empty()) {
2713 // Optimizing for varargs on Win64 is unlikely to be safe without
2714 // additional testing.
2715 if (Subtarget->isTargetWin64())
2718 SmallVector<CCValAssign, 16> ArgLocs;
2719 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2720 getTargetMachine(), ArgLocs, *DAG.getContext());
2722 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2723 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
2724 if (!ArgLocs[i].isRegLoc())
2728 // If the call result is in ST0 / ST1, it needs to be popped off the x87
2729 // stack. Therefore, if it's not used by the call it is not safe to optimize
2730 // this into a sibcall.
2731 bool Unused = false;
2732 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
2739 SmallVector<CCValAssign, 16> RVLocs;
2740 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(),
2741 getTargetMachine(), RVLocs, *DAG.getContext());
2742 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2743 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2744 CCValAssign &VA = RVLocs[i];
2745 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
2750 // If the calling conventions do not match, then we'd better make sure the
2751 // results are returned in the same way as what the caller expects.
2753 SmallVector<CCValAssign, 16> RVLocs1;
2754 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
2755 getTargetMachine(), RVLocs1, *DAG.getContext());
2756 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
2758 SmallVector<CCValAssign, 16> RVLocs2;
2759 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
2760 getTargetMachine(), RVLocs2, *DAG.getContext());
2761 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
2763 if (RVLocs1.size() != RVLocs2.size())
2765 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2766 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2768 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2770 if (RVLocs1[i].isRegLoc()) {
2771 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2774 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2780 // If the callee takes no arguments then go on to check the results of the
2782 if (!Outs.empty()) {
2783 // Check if stack adjustment is needed. For now, do not do this if any
2784 // argument is passed on the stack.
2785 SmallVector<CCValAssign, 16> ArgLocs;
2786 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2787 getTargetMachine(), ArgLocs, *DAG.getContext());
2789 // Allocate shadow area for Win64
2790 if (Subtarget->isTargetWin64()) {
2791 CCInfo.AllocateStack(32, 8);
2794 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2795 if (CCInfo.getNextStackOffset()) {
2796 MachineFunction &MF = DAG.getMachineFunction();
2797 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
2800 // Check if the arguments are already laid out in the right way as
2801 // the caller's fixed stack objects.
2802 MachineFrameInfo *MFI = MF.getFrameInfo();
2803 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2804 const X86InstrInfo *TII =
2805 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
2806 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2807 CCValAssign &VA = ArgLocs[i];
2808 SDValue Arg = OutVals[i];
2809 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2810 if (VA.getLocInfo() == CCValAssign::Indirect)
2812 if (!VA.isRegLoc()) {
2813 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2820 // If the tailcall address may be in a register, then make sure it's
2821 // possible to register allocate for it. In 32-bit, the call address can
2822 // only target EAX, EDX, or ECX since the tail call must be scheduled after
2823 // callee-saved registers are restored. These happen to be the same
2824 // registers used to pass 'inreg' arguments so watch out for those.
2825 if (!Subtarget->is64Bit() &&
2826 !isa<GlobalAddressSDNode>(Callee) &&
2827 !isa<ExternalSymbolSDNode>(Callee)) {
2828 unsigned NumInRegs = 0;
2829 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2830 CCValAssign &VA = ArgLocs[i];
2833 unsigned Reg = VA.getLocReg();
2836 case X86::EAX: case X86::EDX: case X86::ECX:
2837 if (++NumInRegs == 3)
2849 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const {
2850 return X86::createFastISel(funcInfo);
2854 //===----------------------------------------------------------------------===//
2855 // Other Lowering Hooks
2856 //===----------------------------------------------------------------------===//
2858 static bool MayFoldLoad(SDValue Op) {
2859 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
2862 static bool MayFoldIntoStore(SDValue Op) {
2863 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
2866 static bool isTargetShuffle(unsigned Opcode) {
2868 default: return false;
2869 case X86ISD::PSHUFD:
2870 case X86ISD::PSHUFHW:
2871 case X86ISD::PSHUFLW:
2873 case X86ISD::PALIGN:
2874 case X86ISD::MOVLHPS:
2875 case X86ISD::MOVLHPD:
2876 case X86ISD::MOVHLPS:
2877 case X86ISD::MOVLPS:
2878 case X86ISD::MOVLPD:
2879 case X86ISD::MOVSHDUP:
2880 case X86ISD::MOVSLDUP:
2881 case X86ISD::MOVDDUP:
2884 case X86ISD::UNPCKL:
2885 case X86ISD::UNPCKH:
2886 case X86ISD::VPERMILP:
2887 case X86ISD::VPERM2X128:
2893 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2894 SDValue V1, SelectionDAG &DAG) {
2896 default: llvm_unreachable("Unknown x86 shuffle node");
2897 case X86ISD::MOVSHDUP:
2898 case X86ISD::MOVSLDUP:
2899 case X86ISD::MOVDDUP:
2900 return DAG.getNode(Opc, dl, VT, V1);
2906 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2907 SDValue V1, unsigned TargetMask, SelectionDAG &DAG) {
2909 default: llvm_unreachable("Unknown x86 shuffle node");
2910 case X86ISD::PSHUFD:
2911 case X86ISD::PSHUFHW:
2912 case X86ISD::PSHUFLW:
2913 case X86ISD::VPERMILP:
2914 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
2920 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2921 SDValue V1, SDValue V2, unsigned TargetMask, SelectionDAG &DAG) {
2923 default: llvm_unreachable("Unknown x86 shuffle node");
2924 case X86ISD::PALIGN:
2926 case X86ISD::VPERM2X128:
2927 return DAG.getNode(Opc, dl, VT, V1, V2,
2928 DAG.getConstant(TargetMask, MVT::i8));
2933 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2934 SDValue V1, SDValue V2, SelectionDAG &DAG) {
2936 default: llvm_unreachable("Unknown x86 shuffle node");
2937 case X86ISD::MOVLHPS:
2938 case X86ISD::MOVLHPD:
2939 case X86ISD::MOVHLPS:
2940 case X86ISD::MOVLPS:
2941 case X86ISD::MOVLPD:
2944 case X86ISD::UNPCKL:
2945 case X86ISD::UNPCKH:
2946 return DAG.getNode(Opc, dl, VT, V1, V2);
2951 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
2952 MachineFunction &MF = DAG.getMachineFunction();
2953 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2954 int ReturnAddrIndex = FuncInfo->getRAIndex();
2956 if (ReturnAddrIndex == 0) {
2957 // Set up a frame object for the return address.
2958 uint64_t SlotSize = TD->getPointerSize();
2959 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
2961 FuncInfo->setRAIndex(ReturnAddrIndex);
2964 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
2968 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
2969 bool hasSymbolicDisplacement) {
2970 // Offset should fit into 32 bit immediate field.
2971 if (!isInt<32>(Offset))
2974 // If we don't have a symbolic displacement - we don't have any extra
2976 if (!hasSymbolicDisplacement)
2979 // FIXME: Some tweaks might be needed for medium code model.
2980 if (M != CodeModel::Small && M != CodeModel::Kernel)
2983 // For small code model we assume that latest object is 16MB before end of 31
2984 // bits boundary. We may also accept pretty large negative constants knowing
2985 // that all objects are in the positive half of address space.
2986 if (M == CodeModel::Small && Offset < 16*1024*1024)
2989 // For kernel code model we know that all object resist in the negative half
2990 // of 32bits address space. We may not accept negative offsets, since they may
2991 // be just off and we may accept pretty large positive ones.
2992 if (M == CodeModel::Kernel && Offset > 0)
2998 /// isCalleePop - Determines whether the callee is required to pop its
2999 /// own arguments. Callee pop is necessary to support tail calls.
3000 bool X86::isCalleePop(CallingConv::ID CallingConv,
3001 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3005 switch (CallingConv) {
3008 case CallingConv::X86_StdCall:
3010 case CallingConv::X86_FastCall:
3012 case CallingConv::X86_ThisCall:
3014 case CallingConv::Fast:
3016 case CallingConv::GHC:
3021 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3022 /// specific condition code, returning the condition code and the LHS/RHS of the
3023 /// comparison to make.
3024 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3025 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3027 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3028 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3029 // X > -1 -> X == 0, jump !sign.
3030 RHS = DAG.getConstant(0, RHS.getValueType());
3031 return X86::COND_NS;
3032 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3033 // X < 0 -> X == 0, jump on sign.
3035 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3037 RHS = DAG.getConstant(0, RHS.getValueType());
3038 return X86::COND_LE;
3042 switch (SetCCOpcode) {
3043 default: llvm_unreachable("Invalid integer condition!");
3044 case ISD::SETEQ: return X86::COND_E;
3045 case ISD::SETGT: return X86::COND_G;
3046 case ISD::SETGE: return X86::COND_GE;
3047 case ISD::SETLT: return X86::COND_L;
3048 case ISD::SETLE: return X86::COND_LE;
3049 case ISD::SETNE: return X86::COND_NE;
3050 case ISD::SETULT: return X86::COND_B;
3051 case ISD::SETUGT: return X86::COND_A;
3052 case ISD::SETULE: return X86::COND_BE;
3053 case ISD::SETUGE: return X86::COND_AE;
3057 // First determine if it is required or is profitable to flip the operands.
3059 // If LHS is a foldable load, but RHS is not, flip the condition.
3060 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3061 !ISD::isNON_EXTLoad(RHS.getNode())) {
3062 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3063 std::swap(LHS, RHS);
3066 switch (SetCCOpcode) {
3072 std::swap(LHS, RHS);
3076 // On a floating point condition, the flags are set as follows:
3078 // 0 | 0 | 0 | X > Y
3079 // 0 | 0 | 1 | X < Y
3080 // 1 | 0 | 0 | X == Y
3081 // 1 | 1 | 1 | unordered
3082 switch (SetCCOpcode) {
3083 default: llvm_unreachable("Condcode should be pre-legalized away");
3085 case ISD::SETEQ: return X86::COND_E;
3086 case ISD::SETOLT: // flipped
3088 case ISD::SETGT: return X86::COND_A;
3089 case ISD::SETOLE: // flipped
3091 case ISD::SETGE: return X86::COND_AE;
3092 case ISD::SETUGT: // flipped
3094 case ISD::SETLT: return X86::COND_B;
3095 case ISD::SETUGE: // flipped
3097 case ISD::SETLE: return X86::COND_BE;
3099 case ISD::SETNE: return X86::COND_NE;
3100 case ISD::SETUO: return X86::COND_P;
3101 case ISD::SETO: return X86::COND_NP;
3103 case ISD::SETUNE: return X86::COND_INVALID;
3107 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3108 /// code. Current x86 isa includes the following FP cmov instructions:
3109 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3110 static bool hasFPCMov(unsigned X86CC) {
3126 /// isFPImmLegal - Returns true if the target can instruction select the
3127 /// specified FP immediate natively. If false, the legalizer will
3128 /// materialize the FP immediate as a load from a constant pool.
3129 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3130 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3131 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3137 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3138 /// the specified range (L, H].
3139 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3140 return (Val < 0) || (Val >= Low && Val < Hi);
3143 /// isUndefOrInRange - Return true if every element in Mask, begining
3144 /// from position Pos and ending in Pos+Size, falls within the specified
3145 /// range (L, L+Pos]. or is undef.
3146 static bool isUndefOrInRange(const SmallVectorImpl<int> &Mask,
3147 int Pos, int Size, int Low, int Hi) {
3148 for (int i = Pos, e = Pos+Size; i != e; ++i)
3149 if (!isUndefOrInRange(Mask[i], Low, Hi))
3154 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3155 /// specified value.
3156 static bool isUndefOrEqual(int Val, int CmpVal) {
3157 if (Val < 0 || Val == CmpVal)
3162 /// isSequentialOrUndefInRange - Return true if every element in Mask, begining
3163 /// from position Pos and ending in Pos+Size, falls within the specified
3164 /// sequential range (L, L+Pos]. or is undef.
3165 static bool isSequentialOrUndefInRange(const SmallVectorImpl<int> &Mask,
3166 int Pos, int Size, int Low) {
3167 for (int i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3168 if (!isUndefOrEqual(Mask[i], Low))
3173 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3174 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3175 /// the second operand.
3176 static bool isPSHUFDMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3177 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3178 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3179 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3180 return (Mask[0] < 2 && Mask[1] < 2);
3184 bool X86::isPSHUFDMask(ShuffleVectorSDNode *N) {
3185 SmallVector<int, 8> M;
3187 return ::isPSHUFDMask(M, N->getValueType(0));
3190 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3191 /// is suitable for input to PSHUFHW.
3192 static bool isPSHUFHWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3193 if (VT != MVT::v8i16)
3196 // Lower quadword copied in order or undef.
3197 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3200 // Upper quadword shuffled.
3201 for (unsigned i = 4; i != 8; ++i)
3202 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7))
3208 bool X86::isPSHUFHWMask(ShuffleVectorSDNode *N) {
3209 SmallVector<int, 8> M;
3211 return ::isPSHUFHWMask(M, N->getValueType(0));
3214 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3215 /// is suitable for input to PSHUFLW.
3216 static bool isPSHUFLWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3217 if (VT != MVT::v8i16)
3220 // Upper quadword copied in order.
3221 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3224 // Lower quadword shuffled.
3225 for (unsigned i = 0; i != 4; ++i)
3232 bool X86::isPSHUFLWMask(ShuffleVectorSDNode *N) {
3233 SmallVector<int, 8> M;
3235 return ::isPSHUFLWMask(M, N->getValueType(0));
3238 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
3239 /// is suitable for input to PALIGNR.
3240 static bool isPALIGNRMask(const SmallVectorImpl<int> &Mask, EVT VT,
3241 bool hasSSSE3OrAVX) {
3242 int i, e = VT.getVectorNumElements();
3243 if (VT.getSizeInBits() != 128)
3246 // Do not handle v2i64 / v2f64 shuffles with palignr.
3247 if (e < 4 || !hasSSSE3OrAVX)
3250 for (i = 0; i != e; ++i)
3254 // All undef, not a palignr.
3258 // Make sure we're shifting in the right direction.
3262 int s = Mask[i] - i;
3264 // Check the rest of the elements to see if they are consecutive.
3265 for (++i; i != e; ++i) {
3267 if (m >= 0 && m != s+i)
3273 /// isVSHUFPYMask - Return true if the specified VECTOR_SHUFFLE operand
3274 /// specifies a shuffle of elements that is suitable for input to 256-bit
3276 static bool isVSHUFPYMask(const SmallVectorImpl<int> &Mask, EVT VT,
3277 bool HasAVX, bool Commuted = false) {
3278 int NumElems = VT.getVectorNumElements();
3280 if (!HasAVX || VT.getSizeInBits() != 256)
3283 if (NumElems != 4 && NumElems != 8)
3286 // VSHUFPSY divides the resulting vector into 4 chunks.
3287 // The sources are also splitted into 4 chunks, and each destination
3288 // chunk must come from a different source chunk.
3290 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
3291 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
3293 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
3294 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
3296 // VSHUFPDY divides the resulting vector into 4 chunks.
3297 // The sources are also splitted into 4 chunks, and each destination
3298 // chunk must come from a different source chunk.
3300 // SRC1 => X3 X2 X1 X0
3301 // SRC2 => Y3 Y2 Y1 Y0
3303 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
3305 unsigned QuarterSize = NumElems/4;
3306 unsigned HalfSize = QuarterSize*2;
3307 for (unsigned l = 0; l != 2; ++l) {
3308 unsigned LaneStart = l*HalfSize;
3309 for (unsigned s = 0; s != 2; ++s) {
3310 unsigned QuarterStart = s*QuarterSize;
3311 unsigned Src = (Commuted) ? (1-s) : s;
3312 unsigned SrcStart = Src*NumElems + LaneStart;
3313 for (unsigned i = 0; i != QuarterSize; ++i) {
3314 int Idx = Mask[i+QuarterStart+LaneStart];
3315 if (!isUndefOrInRange(Idx, SrcStart, SrcStart+HalfSize))
3317 // For VSHUFPSY, the mask of the second half must be the same as the
3318 // first but with the appropriate offsets. This works in the same way as
3319 // VPERMILPS works with masks.
3320 if (NumElems == 4 || l == 0 || Mask[i+QuarterStart] < 0)
3322 if (!isUndefOrEqual(Idx, Mask[i+QuarterStart]+LaneStart))
3331 /// getShuffleVSHUFPYImmediate - Return the appropriate immediate to shuffle
3332 /// the specified VECTOR_MASK mask with VSHUFPSY/VSHUFPDY instructions.
3333 static unsigned getShuffleVSHUFPYImmediate(ShuffleVectorSDNode *SVOp) {
3334 EVT VT = SVOp->getValueType(0);
3335 unsigned NumElems = VT.getVectorNumElements();
3337 assert(VT.getSizeInBits() == 256 && "Only supports 256-bit types");
3338 assert((NumElems == 4 || NumElems == 8) && "Only supports v4 and v8 types");
3340 unsigned HalfSize = NumElems/2;
3341 unsigned Mul = (NumElems == 8) ? 2 : 1;
3343 for (unsigned i = 0; i != NumElems; ++i) {
3344 int Elt = SVOp->getMaskElt(i);
3349 // For VSHUFPSY, the mask of the first half must be equal to the second one.
3350 if (NumElems == 8) Shamt %= HalfSize;
3351 Mask |= Elt << (Shamt*Mul);
3357 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3358 /// the two vector operands have swapped position.
3359 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
3360 unsigned NumElems) {
3361 for (unsigned i = 0; i != NumElems; ++i) {
3365 else if (idx < (int)NumElems)
3366 Mask[i] = idx + NumElems;
3368 Mask[i] = idx - NumElems;
3372 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
3373 /// specifies a shuffle of elements that is suitable for input to 128-bit
3374 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
3375 /// reverse of what x86 shuffles want.
3376 static bool isSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT,
3377 bool Commuted = false) {
3378 unsigned NumElems = VT.getVectorNumElements();
3380 if (VT.getSizeInBits() != 128)
3383 if (NumElems != 2 && NumElems != 4)
3386 unsigned Half = NumElems / 2;
3387 unsigned SrcStart = Commuted ? NumElems : 0;
3388 for (unsigned i = 0; i != Half; ++i)
3389 if (!isUndefOrInRange(Mask[i], SrcStart, SrcStart+NumElems))
3391 SrcStart = Commuted ? 0 : NumElems;
3392 for (unsigned i = Half; i != NumElems; ++i)
3393 if (!isUndefOrInRange(Mask[i], SrcStart, SrcStart+NumElems))
3399 bool X86::isSHUFPMask(ShuffleVectorSDNode *N) {
3400 SmallVector<int, 8> M;
3402 return ::isSHUFPMask(M, N->getValueType(0));
3405 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
3406 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
3407 bool X86::isMOVHLPSMask(ShuffleVectorSDNode *N) {
3408 EVT VT = N->getValueType(0);
3409 unsigned NumElems = VT.getVectorNumElements();
3411 if (VT.getSizeInBits() != 128)
3417 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
3418 return isUndefOrEqual(N->getMaskElt(0), 6) &&
3419 isUndefOrEqual(N->getMaskElt(1), 7) &&
3420 isUndefOrEqual(N->getMaskElt(2), 2) &&
3421 isUndefOrEqual(N->getMaskElt(3), 3);
3424 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
3425 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
3427 bool X86::isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N) {
3428 EVT VT = N->getValueType(0);
3429 unsigned NumElems = VT.getVectorNumElements();
3431 if (VT.getSizeInBits() != 128)
3437 return isUndefOrEqual(N->getMaskElt(0), 2) &&
3438 isUndefOrEqual(N->getMaskElt(1), 3) &&
3439 isUndefOrEqual(N->getMaskElt(2), 2) &&
3440 isUndefOrEqual(N->getMaskElt(3), 3);
3443 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
3444 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
3445 bool X86::isMOVLPMask(ShuffleVectorSDNode *N) {
3446 EVT VT = N->getValueType(0);
3448 if (VT.getSizeInBits() != 128)
3451 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3453 if (NumElems != 2 && NumElems != 4)
3456 for (unsigned i = 0; i < NumElems/2; ++i)
3457 if (!isUndefOrEqual(N->getMaskElt(i), i + NumElems))
3460 for (unsigned i = NumElems/2; i < NumElems; ++i)
3461 if (!isUndefOrEqual(N->getMaskElt(i), i))
3467 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
3468 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
3469 bool X86::isMOVLHPSMask(ShuffleVectorSDNode *N) {
3470 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3472 if ((NumElems != 2 && NumElems != 4)
3473 || N->getValueType(0).getSizeInBits() > 128)
3476 for (unsigned i = 0; i < NumElems/2; ++i)
3477 if (!isUndefOrEqual(N->getMaskElt(i), i))
3480 for (unsigned i = 0; i < NumElems/2; ++i)
3481 if (!isUndefOrEqual(N->getMaskElt(i + NumElems/2), i + NumElems))
3487 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
3488 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
3489 static bool isUNPCKLMask(const SmallVectorImpl<int> &Mask, EVT VT,
3490 bool HasAVX2, bool V2IsSplat = false) {
3491 unsigned NumElts = VT.getVectorNumElements();
3493 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3494 "Unsupported vector type for unpckh");
3496 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3497 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3500 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3501 // independently on 128-bit lanes.
3502 unsigned NumLanes = VT.getSizeInBits()/128;
3503 unsigned NumLaneElts = NumElts/NumLanes;
3505 for (unsigned l = 0; l != NumLanes; ++l) {
3506 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts;
3507 i != (l+1)*NumLaneElts;
3510 int BitI1 = Mask[i+1];
3511 if (!isUndefOrEqual(BitI, j))
3514 if (!isUndefOrEqual(BitI1, NumElts))
3517 if (!isUndefOrEqual(BitI1, j + NumElts))
3526 bool X86::isUNPCKLMask(ShuffleVectorSDNode *N, bool HasAVX2, bool V2IsSplat) {
3527 SmallVector<int, 8> M;
3529 return ::isUNPCKLMask(M, N->getValueType(0), HasAVX2, V2IsSplat);
3532 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
3533 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
3534 static bool isUNPCKHMask(const SmallVectorImpl<int> &Mask, EVT VT,
3535 bool HasAVX2, bool V2IsSplat = false) {
3536 unsigned NumElts = VT.getVectorNumElements();
3538 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3539 "Unsupported vector type for unpckh");
3541 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3542 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3545 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3546 // independently on 128-bit lanes.
3547 unsigned NumLanes = VT.getSizeInBits()/128;
3548 unsigned NumLaneElts = NumElts/NumLanes;
3550 for (unsigned l = 0; l != NumLanes; ++l) {
3551 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2;
3552 i != (l+1)*NumLaneElts; i += 2, ++j) {
3554 int BitI1 = Mask[i+1];
3555 if (!isUndefOrEqual(BitI, j))
3558 if (isUndefOrEqual(BitI1, NumElts))
3561 if (!isUndefOrEqual(BitI1, j+NumElts))
3569 bool X86::isUNPCKHMask(ShuffleVectorSDNode *N, bool HasAVX2, bool V2IsSplat) {
3570 SmallVector<int, 8> M;
3572 return ::isUNPCKHMask(M, N->getValueType(0), HasAVX2, V2IsSplat);
3575 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
3576 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
3578 static bool isUNPCKL_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT,
3580 unsigned NumElts = VT.getVectorNumElements();
3582 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3583 "Unsupported vector type for unpckh");
3585 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3586 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3589 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
3590 // FIXME: Need a better way to get rid of this, there's no latency difference
3591 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
3592 // the former later. We should also remove the "_undef" special mask.
3593 if (NumElts == 4 && VT.getSizeInBits() == 256)
3596 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3597 // independently on 128-bit lanes.
3598 unsigned NumLanes = VT.getSizeInBits()/128;
3599 unsigned NumLaneElts = NumElts/NumLanes;
3601 for (unsigned l = 0; l != NumLanes; ++l) {
3602 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts;
3603 i != (l+1)*NumLaneElts;
3606 int BitI1 = Mask[i+1];
3608 if (!isUndefOrEqual(BitI, j))
3610 if (!isUndefOrEqual(BitI1, j))
3618 bool X86::isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N, bool HasAVX2) {
3619 SmallVector<int, 8> M;
3621 return ::isUNPCKL_v_undef_Mask(M, N->getValueType(0), HasAVX2);
3624 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
3625 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
3627 static bool isUNPCKH_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT,
3629 unsigned NumElts = VT.getVectorNumElements();
3631 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3632 "Unsupported vector type for unpckh");
3634 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3635 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3638 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3639 // independently on 128-bit lanes.
3640 unsigned NumLanes = VT.getSizeInBits()/128;
3641 unsigned NumLaneElts = NumElts/NumLanes;
3643 for (unsigned l = 0; l != NumLanes; ++l) {
3644 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2;
3645 i != (l+1)*NumLaneElts; i += 2, ++j) {
3647 int BitI1 = Mask[i+1];
3648 if (!isUndefOrEqual(BitI, j))
3650 if (!isUndefOrEqual(BitI1, j))
3657 bool X86::isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N, bool HasAVX2) {
3658 SmallVector<int, 8> M;
3660 return ::isUNPCKH_v_undef_Mask(M, N->getValueType(0), HasAVX2);
3663 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
3664 /// specifies a shuffle of elements that is suitable for input to MOVSS,
3665 /// MOVSD, and MOVD, i.e. setting the lowest element.
3666 static bool isMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3667 if (VT.getVectorElementType().getSizeInBits() < 32)
3669 if (VT.getSizeInBits() == 256)
3672 unsigned NumElts = VT.getVectorNumElements();
3674 if (!isUndefOrEqual(Mask[0], NumElts))
3677 for (unsigned i = 1; i != NumElts; ++i)
3678 if (!isUndefOrEqual(Mask[i], i))
3684 bool X86::isMOVLMask(ShuffleVectorSDNode *N) {
3685 SmallVector<int, 8> M;
3687 return ::isMOVLMask(M, N->getValueType(0));
3690 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
3691 /// as permutations between 128-bit chunks or halves. As an example: this
3693 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
3694 /// The first half comes from the second half of V1 and the second half from the
3695 /// the second half of V2.
3696 static bool isVPERM2X128Mask(const SmallVectorImpl<int> &Mask, EVT VT,
3698 if (!HasAVX || VT.getSizeInBits() != 256)
3701 // The shuffle result is divided into half A and half B. In total the two
3702 // sources have 4 halves, namely: C, D, E, F. The final values of A and
3703 // B must come from C, D, E or F.
3704 unsigned HalfSize = VT.getVectorNumElements()/2;
3705 bool MatchA = false, MatchB = false;
3707 // Check if A comes from one of C, D, E, F.
3708 for (unsigned Half = 0; Half != 4; ++Half) {
3709 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
3715 // Check if B comes from one of C, D, E, F.
3716 for (unsigned Half = 0; Half != 4; ++Half) {
3717 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
3723 return MatchA && MatchB;
3726 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
3727 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
3728 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
3729 EVT VT = SVOp->getValueType(0);
3731 unsigned HalfSize = VT.getVectorNumElements()/2;
3733 unsigned FstHalf = 0, SndHalf = 0;
3734 for (unsigned i = 0; i < HalfSize; ++i) {
3735 if (SVOp->getMaskElt(i) > 0) {
3736 FstHalf = SVOp->getMaskElt(i)/HalfSize;
3740 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
3741 if (SVOp->getMaskElt(i) > 0) {
3742 SndHalf = SVOp->getMaskElt(i)/HalfSize;
3747 return (FstHalf | (SndHalf << 4));
3750 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
3751 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
3752 /// Note that VPERMIL mask matching is different depending whether theunderlying
3753 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
3754 /// to the same elements of the low, but to the higher half of the source.
3755 /// In VPERMILPD the two lanes could be shuffled independently of each other
3756 /// with the same restriction that lanes can't be crossed.
3757 static bool isVPERMILPMask(const SmallVectorImpl<int> &Mask, EVT VT,
3762 unsigned NumElts = VT.getVectorNumElements();
3763 // Only match 256-bit with 32/64-bit types
3764 if (VT.getSizeInBits() != 256 || (NumElts != 4 && NumElts != 8))
3767 unsigned NumLanes = VT.getSizeInBits()/128;
3768 unsigned LaneSize = NumElts/NumLanes;
3769 for (unsigned l = 0; l != NumLanes; ++l) {
3770 unsigned LaneStart = l*LaneSize;
3771 for (unsigned i = 0; i != LaneSize; ++i) {
3772 if (!isUndefOrInRange(Mask[i+LaneStart], LaneStart, LaneStart+LaneSize))
3774 if (NumElts == 4 || l == 0)
3776 // VPERMILPS handling
3779 if (!isUndefOrEqual(Mask[i+LaneStart], Mask[i]+LaneStart))
3787 /// getShuffleVPERMILPImmediate - Return the appropriate immediate to shuffle
3788 /// the specified VECTOR_MASK mask with VPERMILPS/D* instructions.
3789 static unsigned getShuffleVPERMILPImmediate(ShuffleVectorSDNode *SVOp) {
3790 EVT VT = SVOp->getValueType(0);
3792 unsigned NumElts = VT.getVectorNumElements();
3793 unsigned NumLanes = VT.getSizeInBits()/128;
3794 unsigned LaneSize = NumElts/NumLanes;
3796 // Although the mask is equal for both lanes do it twice to get the cases
3797 // where a mask will match because the same mask element is undef on the
3798 // first half but valid on the second. This would get pathological cases
3799 // such as: shuffle <u, 0, 1, 2, 4, 4, 5, 6>, which is completely valid.
3800 unsigned Shift = (LaneSize == 4) ? 2 : 1;
3802 for (unsigned i = 0; i != NumElts; ++i) {
3803 int MaskElt = SVOp->getMaskElt(i);
3806 MaskElt %= LaneSize;
3808 // VPERMILPSY, the mask of the first half must be equal to the second one
3809 if (NumElts == 8) Shamt %= LaneSize;
3810 Mask |= MaskElt << (Shamt*Shift);
3816 /// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
3817 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
3818 /// element of vector 2 and the other elements to come from vector 1 in order.
3819 static bool isCommutedMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT,
3820 bool V2IsSplat = false, bool V2IsUndef = false) {
3821 unsigned NumOps = VT.getVectorNumElements();
3822 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
3825 if (!isUndefOrEqual(Mask[0], 0))
3828 for (unsigned i = 1; i != NumOps; ++i)
3829 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
3830 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
3831 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
3837 static bool isCommutedMOVL(ShuffleVectorSDNode *N, bool V2IsSplat = false,
3838 bool V2IsUndef = false) {
3839 SmallVector<int, 8> M;
3841 return isCommutedMOVLMask(M, N->getValueType(0), V2IsSplat, V2IsUndef);
3844 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3845 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
3846 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
3847 bool X86::isMOVSHDUPMask(ShuffleVectorSDNode *N,
3848 const X86Subtarget *Subtarget) {
3849 if (!Subtarget->hasSSE3orAVX())
3852 // The second vector must be undef
3853 if (N->getOperand(1).getOpcode() != ISD::UNDEF)
3856 EVT VT = N->getValueType(0);
3857 unsigned NumElems = VT.getVectorNumElements();
3859 if ((VT.getSizeInBits() == 128 && NumElems != 4) ||
3860 (VT.getSizeInBits() == 256 && NumElems != 8))
3863 // "i+1" is the value the indexed mask element must have
3864 for (unsigned i = 0; i < NumElems; i += 2)
3865 if (!isUndefOrEqual(N->getMaskElt(i), i+1) ||
3866 !isUndefOrEqual(N->getMaskElt(i+1), i+1))
3872 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3873 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
3874 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
3875 bool X86::isMOVSLDUPMask(ShuffleVectorSDNode *N,
3876 const X86Subtarget *Subtarget) {
3877 if (!Subtarget->hasSSE3orAVX())
3880 // The second vector must be undef
3881 if (N->getOperand(1).getOpcode() != ISD::UNDEF)
3884 EVT VT = N->getValueType(0);
3885 unsigned NumElems = VT.getVectorNumElements();
3887 if ((VT.getSizeInBits() == 128 && NumElems != 4) ||
3888 (VT.getSizeInBits() == 256 && NumElems != 8))
3891 // "i" is the value the indexed mask element must have
3892 for (unsigned i = 0; i != NumElems; i += 2)
3893 if (!isUndefOrEqual(N->getMaskElt(i), i) ||
3894 !isUndefOrEqual(N->getMaskElt(i+1), i))
3900 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
3901 /// specifies a shuffle of elements that is suitable for input to 256-bit
3902 /// version of MOVDDUP.
3903 static bool isMOVDDUPYMask(const SmallVectorImpl<int> &Mask, EVT VT,
3905 unsigned NumElts = VT.getVectorNumElements();
3907 if (!HasAVX || VT.getSizeInBits() != 256 || NumElts != 4)
3910 for (unsigned i = 0; i != NumElts/2; ++i)
3911 if (!isUndefOrEqual(Mask[i], 0))
3913 for (unsigned i = NumElts/2; i != NumElts; ++i)
3914 if (!isUndefOrEqual(Mask[i], NumElts/2))
3919 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3920 /// specifies a shuffle of elements that is suitable for input to 128-bit
3921 /// version of MOVDDUP.
3922 bool X86::isMOVDDUPMask(ShuffleVectorSDNode *N) {
3923 EVT VT = N->getValueType(0);
3925 if (VT.getSizeInBits() != 128)
3928 unsigned e = VT.getVectorNumElements() / 2;
3929 for (unsigned i = 0; i != e; ++i)
3930 if (!isUndefOrEqual(N->getMaskElt(i), i))
3932 for (unsigned i = 0; i != e; ++i)
3933 if (!isUndefOrEqual(N->getMaskElt(e+i), i))
3938 /// isVEXTRACTF128Index - Return true if the specified
3939 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
3940 /// suitable for input to VEXTRACTF128.
3941 bool X86::isVEXTRACTF128Index(SDNode *N) {
3942 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3945 // The index should be aligned on a 128-bit boundary.
3947 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
3949 unsigned VL = N->getValueType(0).getVectorNumElements();
3950 unsigned VBits = N->getValueType(0).getSizeInBits();
3951 unsigned ElSize = VBits / VL;
3952 bool Result = (Index * ElSize) % 128 == 0;
3957 /// isVINSERTF128Index - Return true if the specified INSERT_SUBVECTOR
3958 /// operand specifies a subvector insert that is suitable for input to
3960 bool X86::isVINSERTF128Index(SDNode *N) {
3961 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
3964 // The index should be aligned on a 128-bit boundary.
3966 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
3968 unsigned VL = N->getValueType(0).getVectorNumElements();
3969 unsigned VBits = N->getValueType(0).getSizeInBits();
3970 unsigned ElSize = VBits / VL;
3971 bool Result = (Index * ElSize) % 128 == 0;
3976 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
3977 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
3978 unsigned X86::getShuffleSHUFImmediate(SDNode *N) {
3979 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3980 unsigned NumOperands = SVOp->getValueType(0).getVectorNumElements();
3982 unsigned Shift = (NumOperands == 4) ? 2 : 1;
3984 for (unsigned i = 0; i != NumOperands; ++i) {
3985 int Val = SVOp->getMaskElt(NumOperands-i-1);
3986 if (Val < 0) Val = 0;
3987 if (Val >= (int)NumOperands) Val -= NumOperands;
3989 if (i != NumOperands - 1)
3995 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
3996 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
3997 unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
3998 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
4000 // 8 nodes, but we only care about the last 4.
4001 for (unsigned i = 7; i >= 4; --i) {
4002 int Val = SVOp->getMaskElt(i);
4011 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4012 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4013 unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
4014 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
4016 // 8 nodes, but we only care about the first 4.
4017 for (int i = 3; i >= 0; --i) {
4018 int Val = SVOp->getMaskElt(i);
4027 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
4028 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
4029 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4030 EVT VT = SVOp->getValueType(0);
4031 unsigned EltSize = VT.getVectorElementType().getSizeInBits() >> 3;
4035 for (i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
4036 Val = SVOp->getMaskElt(i);
4040 assert(Val - i > 0 && "PALIGNR imm should be positive");
4041 return (Val - i) * EltSize;
4044 /// getExtractVEXTRACTF128Immediate - Return the appropriate immediate
4045 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4047 unsigned X86::getExtractVEXTRACTF128Immediate(SDNode *N) {
4048 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4049 llvm_unreachable("Illegal extract subvector for VEXTRACTF128");
4052 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4054 EVT VecVT = N->getOperand(0).getValueType();
4055 EVT ElVT = VecVT.getVectorElementType();
4057 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
4058 return Index / NumElemsPerChunk;
4061 /// getInsertVINSERTF128Immediate - Return the appropriate immediate
4062 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4064 unsigned X86::getInsertVINSERTF128Immediate(SDNode *N) {
4065 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4066 llvm_unreachable("Illegal insert subvector for VINSERTF128");
4069 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4071 EVT VecVT = N->getValueType(0);
4072 EVT ElVT = VecVT.getVectorElementType();
4074 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
4075 return Index / NumElemsPerChunk;
4078 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4080 bool X86::isZeroNode(SDValue Elt) {
4081 return ((isa<ConstantSDNode>(Elt) &&
4082 cast<ConstantSDNode>(Elt)->isNullValue()) ||
4083 (isa<ConstantFPSDNode>(Elt) &&
4084 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
4087 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
4088 /// their permute mask.
4089 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
4090 SelectionDAG &DAG) {
4091 EVT VT = SVOp->getValueType(0);
4092 unsigned NumElems = VT.getVectorNumElements();
4093 SmallVector<int, 8> MaskVec;
4095 for (unsigned i = 0; i != NumElems; ++i) {
4096 int idx = SVOp->getMaskElt(i);
4098 MaskVec.push_back(idx);
4099 else if (idx < (int)NumElems)
4100 MaskVec.push_back(idx + NumElems);
4102 MaskVec.push_back(idx - NumElems);
4104 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1),
4105 SVOp->getOperand(0), &MaskVec[0]);
4108 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4109 /// match movhlps. The lower half elements should come from upper half of
4110 /// V1 (and in order), and the upper half elements should come from the upper
4111 /// half of V2 (and in order).
4112 static bool ShouldXformToMOVHLPS(ShuffleVectorSDNode *Op) {
4113 EVT VT = Op->getValueType(0);
4114 if (VT.getSizeInBits() != 128)
4116 if (VT.getVectorNumElements() != 4)
4118 for (unsigned i = 0, e = 2; i != e; ++i)
4119 if (!isUndefOrEqual(Op->getMaskElt(i), i+2))
4121 for (unsigned i = 2; i != 4; ++i)
4122 if (!isUndefOrEqual(Op->getMaskElt(i), i+4))
4127 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4128 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4130 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
4131 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4133 N = N->getOperand(0).getNode();
4134 if (!ISD::isNON_EXTLoad(N))
4137 *LD = cast<LoadSDNode>(N);
4141 // Test whether the given value is a vector value which will be legalized
4143 static bool WillBeConstantPoolLoad(SDNode *N) {
4144 if (N->getOpcode() != ISD::BUILD_VECTOR)
4147 // Check for any non-constant elements.
4148 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4149 switch (N->getOperand(i).getNode()->getOpcode()) {
4151 case ISD::ConstantFP:
4158 // Vectors of all-zeros and all-ones are materialized with special
4159 // instructions rather than being loaded.
4160 return !ISD::isBuildVectorAllZeros(N) &&
4161 !ISD::isBuildVectorAllOnes(N);
4164 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
4165 /// match movlp{s|d}. The lower half elements should come from lower half of
4166 /// V1 (and in order), and the upper half elements should come from the upper
4167 /// half of V2 (and in order). And since V1 will become the source of the
4168 /// MOVLP, it must be either a vector load or a scalar load to vector.
4169 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
4170 ShuffleVectorSDNode *Op) {
4171 EVT VT = Op->getValueType(0);
4172 if (VT.getSizeInBits() != 128)
4175 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
4177 // Is V2 is a vector load, don't do this transformation. We will try to use
4178 // load folding shufps op.
4179 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
4182 unsigned NumElems = VT.getVectorNumElements();
4184 if (NumElems != 2 && NumElems != 4)
4186 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4187 if (!isUndefOrEqual(Op->getMaskElt(i), i))
4189 for (unsigned i = NumElems/2; i != NumElems; ++i)
4190 if (!isUndefOrEqual(Op->getMaskElt(i), i+NumElems))
4195 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
4197 static bool isSplatVector(SDNode *N) {
4198 if (N->getOpcode() != ISD::BUILD_VECTOR)
4201 SDValue SplatValue = N->getOperand(0);
4202 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
4203 if (N->getOperand(i) != SplatValue)
4208 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
4209 /// to an zero vector.
4210 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
4211 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
4212 SDValue V1 = N->getOperand(0);
4213 SDValue V2 = N->getOperand(1);
4214 unsigned NumElems = N->getValueType(0).getVectorNumElements();
4215 for (unsigned i = 0; i != NumElems; ++i) {
4216 int Idx = N->getMaskElt(i);
4217 if (Idx >= (int)NumElems) {
4218 unsigned Opc = V2.getOpcode();
4219 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
4221 if (Opc != ISD::BUILD_VECTOR ||
4222 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
4224 } else if (Idx >= 0) {
4225 unsigned Opc = V1.getOpcode();
4226 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
4228 if (Opc != ISD::BUILD_VECTOR ||
4229 !X86::isZeroNode(V1.getOperand(Idx)))
4236 /// getZeroVector - Returns a vector of specified type with all zero elements.
4238 static SDValue getZeroVector(EVT VT, bool HasXMMInt, SelectionDAG &DAG,
4240 assert(VT.isVector() && "Expected a vector type");
4242 // Always build SSE zero vectors as <4 x i32> bitcasted
4243 // to their dest type. This ensures they get CSE'd.
4245 if (VT.getSizeInBits() == 128) { // SSE
4246 if (HasXMMInt) { // SSE2
4247 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4248 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4250 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4251 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4253 } else if (VT.getSizeInBits() == 256) { // AVX
4254 // 256-bit logic and arithmetic instructions in AVX are
4255 // all floating-point, no support for integer ops. Default
4256 // to emitting fp zeroed vectors then.
4257 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4258 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4259 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops, 8);
4261 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4264 /// getOnesVector - Returns a vector of specified type with all bits set.
4265 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4266 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4267 /// Then bitcast to their original type, ensuring they get CSE'd.
4268 static SDValue getOnesVector(EVT VT, bool HasAVX2, SelectionDAG &DAG,
4270 assert(VT.isVector() && "Expected a vector type");
4271 assert((VT.is128BitVector() || VT.is256BitVector())
4272 && "Expected a 128-bit or 256-bit vector type");
4274 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
4276 if (VT.getSizeInBits() == 256) {
4277 if (HasAVX2) { // AVX2
4278 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4279 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8);
4281 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4282 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, MVT::v8i32),
4283 Vec, DAG.getConstant(0, MVT::i32), DAG, dl);
4284 Vec = Insert128BitVector(InsV, Vec,
4285 DAG.getConstant(4 /* NumElems/2 */, MVT::i32), DAG, dl);
4288 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4291 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4294 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
4295 /// that point to V2 points to its first element.
4296 static SDValue NormalizeMask(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
4297 EVT VT = SVOp->getValueType(0);
4298 unsigned NumElems = VT.getVectorNumElements();
4300 bool Changed = false;
4301 SmallVector<int, 8> MaskVec;
4302 SVOp->getMask(MaskVec);
4304 for (unsigned i = 0; i != NumElems; ++i) {
4305 if (MaskVec[i] > (int)NumElems) {
4306 MaskVec[i] = NumElems;
4311 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(0),
4312 SVOp->getOperand(1), &MaskVec[0]);
4313 return SDValue(SVOp, 0);
4316 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4317 /// operation of specified width.
4318 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4320 unsigned NumElems = VT.getVectorNumElements();
4321 SmallVector<int, 8> Mask;
4322 Mask.push_back(NumElems);
4323 for (unsigned i = 1; i != NumElems; ++i)
4325 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4328 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4329 static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4331 unsigned NumElems = VT.getVectorNumElements();
4332 SmallVector<int, 8> Mask;
4333 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4335 Mask.push_back(i + NumElems);
4337 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4340 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4341 static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4343 unsigned NumElems = VT.getVectorNumElements();
4344 unsigned Half = NumElems/2;
4345 SmallVector<int, 8> Mask;
4346 for (unsigned i = 0; i != Half; ++i) {
4347 Mask.push_back(i + Half);
4348 Mask.push_back(i + NumElems + Half);
4350 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4353 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
4354 // a generic shuffle instruction because the target has no such instructions.
4355 // Generate shuffles which repeat i16 and i8 several times until they can be
4356 // represented by v4f32 and then be manipulated by target suported shuffles.
4357 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
4358 EVT VT = V.getValueType();
4359 int NumElems = VT.getVectorNumElements();
4360 DebugLoc dl = V.getDebugLoc();
4362 while (NumElems > 4) {
4363 if (EltNo < NumElems/2) {
4364 V = getUnpackl(DAG, dl, VT, V, V);
4366 V = getUnpackh(DAG, dl, VT, V, V);
4367 EltNo -= NumElems/2;
4374 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
4375 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
4376 EVT VT = V.getValueType();
4377 DebugLoc dl = V.getDebugLoc();
4378 assert((VT.getSizeInBits() == 128 || VT.getSizeInBits() == 256)
4379 && "Vector size not supported");
4381 if (VT.getSizeInBits() == 128) {
4382 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
4383 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
4384 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
4387 // To use VPERMILPS to splat scalars, the second half of indicies must
4388 // refer to the higher part, which is a duplication of the lower one,
4389 // because VPERMILPS can only handle in-lane permutations.
4390 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
4391 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
4393 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
4394 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
4398 return DAG.getNode(ISD::BITCAST, dl, VT, V);
4401 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
4402 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
4403 EVT SrcVT = SV->getValueType(0);
4404 SDValue V1 = SV->getOperand(0);
4405 DebugLoc dl = SV->getDebugLoc();
4407 int EltNo = SV->getSplatIndex();
4408 int NumElems = SrcVT.getVectorNumElements();
4409 unsigned Size = SrcVT.getSizeInBits();
4411 assert(((Size == 128 && NumElems > 4) || Size == 256) &&
4412 "Unknown how to promote splat for type");
4414 // Extract the 128-bit part containing the splat element and update
4415 // the splat element index when it refers to the higher register.
4417 unsigned Idx = (EltNo > NumElems/2) ? NumElems/2 : 0;
4418 V1 = Extract128BitVector(V1, DAG.getConstant(Idx, MVT::i32), DAG, dl);
4420 EltNo -= NumElems/2;
4423 // All i16 and i8 vector types can't be used directly by a generic shuffle
4424 // instruction because the target has no such instruction. Generate shuffles
4425 // which repeat i16 and i8 several times until they fit in i32, and then can
4426 // be manipulated by target suported shuffles.
4427 EVT EltVT = SrcVT.getVectorElementType();
4428 if (EltVT == MVT::i8 || EltVT == MVT::i16)
4429 V1 = PromoteSplati8i16(V1, DAG, EltNo);
4431 // Recreate the 256-bit vector and place the same 128-bit vector
4432 // into the low and high part. This is necessary because we want
4433 // to use VPERM* to shuffle the vectors
4435 SDValue InsV = Insert128BitVector(DAG.getUNDEF(SrcVT), V1,
4436 DAG.getConstant(0, MVT::i32), DAG, dl);
4437 V1 = Insert128BitVector(InsV, V1,
4438 DAG.getConstant(NumElems/2, MVT::i32), DAG, dl);
4441 return getLegalSplat(DAG, V1, EltNo);
4444 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
4445 /// vector of zero or undef vector. This produces a shuffle where the low
4446 /// element of V2 is swizzled into the zero/undef vector, landing at element
4447 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4448 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4449 bool isZero, bool HasXMMInt,
4450 SelectionDAG &DAG) {
4451 EVT VT = V2.getValueType();
4453 ? getZeroVector(VT, HasXMMInt, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT);
4454 unsigned NumElems = VT.getVectorNumElements();
4455 SmallVector<int, 16> MaskVec;
4456 for (unsigned i = 0; i != NumElems; ++i)
4457 // If this is the insertion idx, put the low elt of V2 here.
4458 MaskVec.push_back(i == Idx ? NumElems : i);
4459 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]);
4462 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
4463 /// element of the result of the vector shuffle.
4464 static SDValue getShuffleScalarElt(SDNode *N, int Index, SelectionDAG &DAG,
4467 return SDValue(); // Limit search depth.
4469 SDValue V = SDValue(N, 0);
4470 EVT VT = V.getValueType();
4471 unsigned Opcode = V.getOpcode();
4473 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4474 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4475 Index = SV->getMaskElt(Index);
4478 return DAG.getUNDEF(VT.getVectorElementType());
4480 int NumElems = VT.getVectorNumElements();
4481 SDValue NewV = (Index < NumElems) ? SV->getOperand(0) : SV->getOperand(1);
4482 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG, Depth+1);
4485 // Recurse into target specific vector shuffles to find scalars.
4486 if (isTargetShuffle(Opcode)) {
4487 int NumElems = VT.getVectorNumElements();
4488 SmallVector<unsigned, 16> ShuffleMask;
4493 ImmN = N->getOperand(N->getNumOperands()-1);
4494 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(),
4497 case X86ISD::UNPCKH:
4498 DecodeUNPCKHMask(VT, ShuffleMask);
4500 case X86ISD::UNPCKL:
4501 DecodeUNPCKLMask(VT, ShuffleMask);
4503 case X86ISD::MOVHLPS:
4504 DecodeMOVHLPSMask(NumElems, ShuffleMask);
4506 case X86ISD::MOVLHPS:
4507 DecodeMOVLHPSMask(NumElems, ShuffleMask);
4509 case X86ISD::PSHUFD:
4510 ImmN = N->getOperand(N->getNumOperands()-1);
4511 DecodePSHUFMask(NumElems,
4512 cast<ConstantSDNode>(ImmN)->getZExtValue(),
4515 case X86ISD::PSHUFHW:
4516 ImmN = N->getOperand(N->getNumOperands()-1);
4517 DecodePSHUFHWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(),
4520 case X86ISD::PSHUFLW:
4521 ImmN = N->getOperand(N->getNumOperands()-1);
4522 DecodePSHUFLWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(),
4526 case X86ISD::MOVSD: {
4527 // The index 0 always comes from the first element of the second source,
4528 // this is why MOVSS and MOVSD are used in the first place. The other
4529 // elements come from the other positions of the first source vector.
4530 unsigned OpNum = (Index == 0) ? 1 : 0;
4531 return getShuffleScalarElt(V.getOperand(OpNum).getNode(), Index, DAG,
4534 case X86ISD::VPERMILP:
4535 ImmN = N->getOperand(N->getNumOperands()-1);
4536 DecodeVPERMILPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(),
4539 case X86ISD::VPERM2X128:
4540 ImmN = N->getOperand(N->getNumOperands()-1);
4541 DecodeVPERM2F128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(),
4544 case X86ISD::MOVDDUP:
4545 case X86ISD::MOVLHPD:
4546 case X86ISD::MOVLPD:
4547 case X86ISD::MOVLPS:
4548 case X86ISD::MOVSHDUP:
4549 case X86ISD::MOVSLDUP:
4550 case X86ISD::PALIGN:
4551 return SDValue(); // Not yet implemented.
4553 assert(0 && "unknown target shuffle node");
4557 Index = ShuffleMask[Index];
4559 return DAG.getUNDEF(VT.getVectorElementType());
4561 SDValue NewV = (Index < NumElems) ? N->getOperand(0) : N->getOperand(1);
4562 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG,
4566 // Actual nodes that may contain scalar elements
4567 if (Opcode == ISD::BITCAST) {
4568 V = V.getOperand(0);
4569 EVT SrcVT = V.getValueType();
4570 unsigned NumElems = VT.getVectorNumElements();
4572 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
4576 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
4577 return (Index == 0) ? V.getOperand(0)
4578 : DAG.getUNDEF(VT.getVectorElementType());
4580 if (V.getOpcode() == ISD::BUILD_VECTOR)
4581 return V.getOperand(Index);
4586 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
4587 /// shuffle operation which come from a consecutively from a zero. The
4588 /// search can start in two different directions, from left or right.
4590 unsigned getNumOfConsecutiveZeros(SDNode *N, int NumElems,
4591 bool ZerosFromLeft, SelectionDAG &DAG) {
4594 while (i < NumElems) {
4595 unsigned Index = ZerosFromLeft ? i : NumElems-i-1;
4596 SDValue Elt = getShuffleScalarElt(N, Index, DAG, 0);
4597 if (!(Elt.getNode() &&
4598 (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt))))
4606 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies from MaskI to
4607 /// MaskE correspond consecutively to elements from one of the vector operands,
4608 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
4610 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp, int MaskI, int MaskE,
4611 int OpIdx, int NumElems, unsigned &OpNum) {
4612 bool SeenV1 = false;
4613 bool SeenV2 = false;
4615 for (int i = MaskI; i <= MaskE; ++i, ++OpIdx) {
4616 int Idx = SVOp->getMaskElt(i);
4617 // Ignore undef indicies
4626 // Only accept consecutive elements from the same vector
4627 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
4631 OpNum = SeenV1 ? 0 : 1;
4635 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
4636 /// logical left shift of a vector.
4637 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4638 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4639 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4640 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4641 false /* check zeros from right */, DAG);
4647 // Considering the elements in the mask that are not consecutive zeros,
4648 // check if they consecutively come from only one of the source vectors.
4650 // V1 = {X, A, B, C} 0
4652 // vector_shuffle V1, V2 <1, 2, 3, X>
4654 if (!isShuffleMaskConsecutive(SVOp,
4655 0, // Mask Start Index
4656 NumElems-NumZeros-1, // Mask End Index
4657 NumZeros, // Where to start looking in the src vector
4658 NumElems, // Number of elements in vector
4659 OpSrc)) // Which source operand ?
4664 ShVal = SVOp->getOperand(OpSrc);
4668 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
4669 /// logical left shift of a vector.
4670 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4671 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4672 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4673 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4674 true /* check zeros from left */, DAG);
4680 // Considering the elements in the mask that are not consecutive zeros,
4681 // check if they consecutively come from only one of the source vectors.
4683 // 0 { A, B, X, X } = V2
4685 // vector_shuffle V1, V2 <X, X, 4, 5>
4687 if (!isShuffleMaskConsecutive(SVOp,
4688 NumZeros, // Mask Start Index
4689 NumElems-1, // Mask End Index
4690 0, // Where to start looking in the src vector
4691 NumElems, // Number of elements in vector
4692 OpSrc)) // Which source operand ?
4697 ShVal = SVOp->getOperand(OpSrc);
4701 /// isVectorShift - Returns true if the shuffle can be implemented as a
4702 /// logical left or right shift of a vector.
4703 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4704 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4705 // Although the logic below support any bitwidth size, there are no
4706 // shift instructions which handle more than 128-bit vectors.
4707 if (SVOp->getValueType(0).getSizeInBits() > 128)
4710 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
4711 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
4717 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
4719 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
4720 unsigned NumNonZero, unsigned NumZero,
4722 const TargetLowering &TLI) {
4726 DebugLoc dl = Op.getDebugLoc();
4729 for (unsigned i = 0; i < 16; ++i) {
4730 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
4731 if (ThisIsNonZero && First) {
4733 V = getZeroVector(MVT::v8i16, true, DAG, dl);
4735 V = DAG.getUNDEF(MVT::v8i16);
4740 SDValue ThisElt(0, 0), LastElt(0, 0);
4741 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
4742 if (LastIsNonZero) {
4743 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
4744 MVT::i16, Op.getOperand(i-1));
4746 if (ThisIsNonZero) {
4747 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
4748 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
4749 ThisElt, DAG.getConstant(8, MVT::i8));
4751 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
4755 if (ThisElt.getNode())
4756 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
4757 DAG.getIntPtrConstant(i/2));
4761 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
4764 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
4766 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
4767 unsigned NumNonZero, unsigned NumZero,
4769 const TargetLowering &TLI) {
4773 DebugLoc dl = Op.getDebugLoc();
4776 for (unsigned i = 0; i < 8; ++i) {
4777 bool isNonZero = (NonZeros & (1 << i)) != 0;
4781 V = getZeroVector(MVT::v8i16, true, DAG, dl);
4783 V = DAG.getUNDEF(MVT::v8i16);
4786 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4787 MVT::v8i16, V, Op.getOperand(i),
4788 DAG.getIntPtrConstant(i));
4795 /// getVShift - Return a vector logical shift node.
4797 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
4798 unsigned NumBits, SelectionDAG &DAG,
4799 const TargetLowering &TLI, DebugLoc dl) {
4800 assert(VT.getSizeInBits() == 128 && "Unknown type for VShift");
4801 EVT ShVT = MVT::v2i64;
4802 unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL;
4803 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
4804 return DAG.getNode(ISD::BITCAST, dl, VT,
4805 DAG.getNode(Opc, dl, ShVT, SrcOp,
4806 DAG.getConstant(NumBits,
4807 TLI.getShiftAmountTy(SrcOp.getValueType()))));
4811 X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
4812 SelectionDAG &DAG) const {
4814 // Check if the scalar load can be widened into a vector load. And if
4815 // the address is "base + cst" see if the cst can be "absorbed" into
4816 // the shuffle mask.
4817 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
4818 SDValue Ptr = LD->getBasePtr();
4819 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
4821 EVT PVT = LD->getValueType(0);
4822 if (PVT != MVT::i32 && PVT != MVT::f32)
4827 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
4828 FI = FINode->getIndex();
4830 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
4831 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
4832 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
4833 Offset = Ptr.getConstantOperandVal(1);
4834 Ptr = Ptr.getOperand(0);
4839 // FIXME: 256-bit vector instructions don't require a strict alignment,
4840 // improve this code to support it better.
4841 unsigned RequiredAlign = VT.getSizeInBits()/8;
4842 SDValue Chain = LD->getChain();
4843 // Make sure the stack object alignment is at least 16 or 32.
4844 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4845 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
4846 if (MFI->isFixedObjectIndex(FI)) {
4847 // Can't change the alignment. FIXME: It's possible to compute
4848 // the exact stack offset and reference FI + adjust offset instead.
4849 // If someone *really* cares about this. That's the way to implement it.
4852 MFI->setObjectAlignment(FI, RequiredAlign);
4856 // (Offset % 16 or 32) must be multiple of 4. Then address is then
4857 // Ptr + (Offset & ~15).
4860 if ((Offset % RequiredAlign) & 3)
4862 int64_t StartOffset = Offset & ~(RequiredAlign-1);
4864 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(),
4865 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
4867 int EltNo = (Offset - StartOffset) >> 2;
4868 int NumElems = VT.getVectorNumElements();
4870 EVT CanonVT = VT.getSizeInBits() == 128 ? MVT::v4i32 : MVT::v8i32;
4871 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
4872 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
4873 LD->getPointerInfo().getWithOffset(StartOffset),
4874 false, false, false, 0);
4876 // Canonicalize it to a v4i32 or v8i32 shuffle.
4877 SmallVector<int, 8> Mask;
4878 for (int i = 0; i < NumElems; ++i)
4879 Mask.push_back(EltNo);
4881 V1 = DAG.getNode(ISD::BITCAST, dl, CanonVT, V1);
4882 return DAG.getNode(ISD::BITCAST, dl, NVT,
4883 DAG.getVectorShuffle(CanonVT, dl, V1,
4884 DAG.getUNDEF(CanonVT),&Mask[0]));
4890 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
4891 /// vector of type 'VT', see if the elements can be replaced by a single large
4892 /// load which has the same value as a build_vector whose operands are 'elts'.
4894 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
4896 /// FIXME: we'd also like to handle the case where the last elements are zero
4897 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
4898 /// There's even a handy isZeroNode for that purpose.
4899 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
4900 DebugLoc &DL, SelectionDAG &DAG) {
4901 EVT EltVT = VT.getVectorElementType();
4902 unsigned NumElems = Elts.size();
4904 LoadSDNode *LDBase = NULL;
4905 unsigned LastLoadedElt = -1U;
4907 // For each element in the initializer, see if we've found a load or an undef.
4908 // If we don't find an initial load element, or later load elements are
4909 // non-consecutive, bail out.
4910 for (unsigned i = 0; i < NumElems; ++i) {
4911 SDValue Elt = Elts[i];
4913 if (!Elt.getNode() ||
4914 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
4917 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
4919 LDBase = cast<LoadSDNode>(Elt.getNode());
4923 if (Elt.getOpcode() == ISD::UNDEF)
4926 LoadSDNode *LD = cast<LoadSDNode>(Elt);
4927 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
4932 // If we have found an entire vector of loads and undefs, then return a large
4933 // load of the entire vector width starting at the base pointer. If we found
4934 // consecutive loads for the low half, generate a vzext_load node.
4935 if (LastLoadedElt == NumElems - 1) {
4936 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
4937 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4938 LDBase->getPointerInfo(),
4939 LDBase->isVolatile(), LDBase->isNonTemporal(),
4940 LDBase->isInvariant(), 0);
4941 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4942 LDBase->getPointerInfo(),
4943 LDBase->isVolatile(), LDBase->isNonTemporal(),
4944 LDBase->isInvariant(), LDBase->getAlignment());
4945 } else if (NumElems == 4 && LastLoadedElt == 1 &&
4946 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
4947 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
4948 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
4950 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, 2, MVT::i64,
4951 LDBase->getPointerInfo(),
4952 LDBase->getAlignment(),
4953 false/*isVolatile*/, true/*ReadMem*/,
4955 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
4960 /// isVectorBroadcast - Check if the node chain is suitable to be xformed to
4961 /// a vbroadcast node. We support two patterns:
4962 /// 1. A splat BUILD_VECTOR which uses a single scalar load.
4963 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
4965 /// The scalar load node is returned when a pattern is found,
4966 /// or SDValue() otherwise.
4967 static SDValue isVectorBroadcast(SDValue &Op, bool hasAVX2) {
4968 EVT VT = Op.getValueType();
4971 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
4972 V = V.getOperand(0);
4974 //A suspected load to be broadcasted.
4977 switch (V.getOpcode()) {
4979 // Unknown pattern found.
4982 case ISD::BUILD_VECTOR: {
4983 // The BUILD_VECTOR node must be a splat.
4984 if (!isSplatVector(V.getNode()))
4987 Ld = V.getOperand(0);
4989 // The suspected load node has several users. Make sure that all
4990 // of its users are from the BUILD_VECTOR node.
4991 if (!Ld->hasNUsesOfValue(VT.getVectorNumElements(), 0))
4996 case ISD::VECTOR_SHUFFLE: {
4997 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
4999 // Shuffles must have a splat mask where the first element is
5001 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
5004 SDValue Sc = Op.getOperand(0);
5005 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR)
5008 Ld = Sc.getOperand(0);
5010 // The scalar_to_vector node and the suspected
5011 // load node must have exactly one user.
5012 if (!Sc.hasOneUse() || !Ld.hasOneUse())
5018 // The scalar source must be a normal load.
5019 if (!ISD::isNormalLoad(Ld.getNode()))
5022 bool Is256 = VT.getSizeInBits() == 256;
5023 bool Is128 = VT.getSizeInBits() == 128;
5024 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5027 // VBroadcast to YMM
5028 if (Is256 && (ScalarSize == 8 || ScalarSize == 16 ||
5029 ScalarSize == 32 || ScalarSize == 64 ))
5032 // VBroadcast to XMM
5033 if (Is128 && (ScalarSize == 8 || ScalarSize == 32 ||
5034 ScalarSize == 16 || ScalarSize == 64 ))
5038 // VBroadcast to YMM
5039 if (Is256 && (ScalarSize == 32 || ScalarSize == 64))
5042 // VBroadcast to XMM
5043 if (Is128 && (ScalarSize == 32))
5047 // Unsupported broadcast.
5052 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
5053 DebugLoc dl = Op.getDebugLoc();
5055 EVT VT = Op.getValueType();
5056 EVT ExtVT = VT.getVectorElementType();
5057 unsigned NumElems = Op.getNumOperands();
5059 // Vectors containing all zeros can be matched by pxor and xorps later
5060 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5061 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
5062 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
5063 if (Op.getValueType() == MVT::v4i32 ||
5064 Op.getValueType() == MVT::v8i32)
5067 return getZeroVector(Op.getValueType(), Subtarget->hasXMMInt(), DAG, dl);
5070 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
5071 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
5072 // vpcmpeqd on 256-bit vectors.
5073 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5074 if (Op.getValueType() == MVT::v4i32 ||
5075 (Op.getValueType() == MVT::v8i32 && Subtarget->hasAVX2()))
5078 return getOnesVector(Op.getValueType(), Subtarget->hasAVX2(), DAG, dl);
5081 SDValue LD = isVectorBroadcast(Op, Subtarget->hasAVX2());
5082 if (Subtarget->hasAVX() && LD.getNode())
5083 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, LD);
5085 unsigned EVTBits = ExtVT.getSizeInBits();
5087 unsigned NumZero = 0;
5088 unsigned NumNonZero = 0;
5089 unsigned NonZeros = 0;
5090 bool IsAllConstants = true;
5091 SmallSet<SDValue, 8> Values;
5092 for (unsigned i = 0; i < NumElems; ++i) {
5093 SDValue Elt = Op.getOperand(i);
5094 if (Elt.getOpcode() == ISD::UNDEF)
5097 if (Elt.getOpcode() != ISD::Constant &&
5098 Elt.getOpcode() != ISD::ConstantFP)
5099 IsAllConstants = false;
5100 if (X86::isZeroNode(Elt))
5103 NonZeros |= (1 << i);
5108 // All undef vector. Return an UNDEF. All zero vectors were handled above.
5109 if (NumNonZero == 0)
5110 return DAG.getUNDEF(VT);
5112 // Special case for single non-zero, non-undef, element.
5113 if (NumNonZero == 1) {
5114 unsigned Idx = CountTrailingZeros_32(NonZeros);
5115 SDValue Item = Op.getOperand(Idx);
5117 // If this is an insertion of an i64 value on x86-32, and if the top bits of
5118 // the value are obviously zero, truncate the value to i32 and do the
5119 // insertion that way. Only do this if the value is non-constant or if the
5120 // value is a constant being inserted into element 0. It is cheaper to do
5121 // a constant pool load than it is to do a movd + shuffle.
5122 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
5123 (!IsAllConstants || Idx == 0)) {
5124 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
5126 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
5127 EVT VecVT = MVT::v4i32;
5128 unsigned VecElts = 4;
5130 // Truncate the value (which may itself be a constant) to i32, and
5131 // convert it to a vector with movd (S2V+shuffle to zero extend).
5132 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
5133 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
5134 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
5135 Subtarget->hasXMMInt(), DAG);
5137 // Now we have our 32-bit value zero extended in the low element of
5138 // a vector. If Idx != 0, swizzle it into place.
5140 SmallVector<int, 4> Mask;
5141 Mask.push_back(Idx);
5142 for (unsigned i = 1; i != VecElts; ++i)
5144 Item = DAG.getVectorShuffle(VecVT, dl, Item,
5145 DAG.getUNDEF(Item.getValueType()),
5148 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Item);
5152 // If we have a constant or non-constant insertion into the low element of
5153 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
5154 // the rest of the elements. This will be matched as movd/movq/movss/movsd
5155 // depending on what the source datatype is.
5158 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5160 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
5161 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
5162 if (VT.getSizeInBits() == 256) {
5163 EVT VT128 = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems / 2);
5164 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Item);
5165 SDValue ZeroVec = getZeroVector(VT, true, DAG, dl);
5166 return Insert128BitVector(ZeroVec, Item, DAG.getConstant(0, MVT::i32),
5169 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!");
5170 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5171 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
5172 return getShuffleVectorZeroOrUndef(Item, 0, true,
5173 Subtarget->hasXMMInt(), DAG);
5176 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
5177 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
5178 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5179 if (VT.getSizeInBits() == 256) {
5180 SDValue ZeroVec = getZeroVector(MVT::v8i32, true, DAG, dl);
5181 Item = Insert128BitVector(ZeroVec, Item, DAG.getConstant(0, MVT::i32),
5184 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!");
5185 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
5186 Subtarget->hasXMMInt(), DAG);
5188 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5192 // Is it a vector logical left shift?
5193 if (NumElems == 2 && Idx == 1 &&
5194 X86::isZeroNode(Op.getOperand(0)) &&
5195 !X86::isZeroNode(Op.getOperand(1))) {
5196 unsigned NumBits = VT.getSizeInBits();
5197 return getVShift(true, VT,
5198 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5199 VT, Op.getOperand(1)),
5200 NumBits/2, DAG, *this, dl);
5203 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
5206 // Otherwise, if this is a vector with i32 or f32 elements, and the element
5207 // is a non-constant being inserted into an element other than the low one,
5208 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
5209 // movd/movss) to move this into the low element, then shuffle it into
5211 if (EVTBits == 32) {
5212 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5214 // Turn it into a shuffle of zero and zero-extended scalar to vector.
5215 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0,
5216 Subtarget->hasXMMInt(), DAG);
5217 SmallVector<int, 8> MaskVec;
5218 for (unsigned i = 0; i < NumElems; i++)
5219 MaskVec.push_back(i == Idx ? 0 : 1);
5220 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
5224 // Splat is obviously ok. Let legalizer expand it to a shuffle.
5225 if (Values.size() == 1) {
5226 if (EVTBits == 32) {
5227 // Instead of a shuffle like this:
5228 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
5229 // Check if it's possible to issue this instead.
5230 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
5231 unsigned Idx = CountTrailingZeros_32(NonZeros);
5232 SDValue Item = Op.getOperand(Idx);
5233 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
5234 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
5239 // A vector full of immediates; various special cases are already
5240 // handled, so this is best done with a single constant-pool load.
5244 // For AVX-length vectors, build the individual 128-bit pieces and use
5245 // shuffles to put them in place.
5246 if (VT.getSizeInBits() == 256 && !ISD::isBuildVectorAllZeros(Op.getNode())) {
5247 SmallVector<SDValue, 32> V;
5248 for (unsigned i = 0; i < NumElems; ++i)
5249 V.push_back(Op.getOperand(i));
5251 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
5253 // Build both the lower and upper subvector.
5254 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2);
5255 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2],
5258 // Recreate the wider vector with the lower and upper part.
5259 SDValue Vec = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), Lower,
5260 DAG.getConstant(0, MVT::i32), DAG, dl);
5261 return Insert128BitVector(Vec, Upper, DAG.getConstant(NumElems/2, MVT::i32),
5265 // Let legalizer expand 2-wide build_vectors.
5266 if (EVTBits == 64) {
5267 if (NumNonZero == 1) {
5268 // One half is zero or undef.
5269 unsigned Idx = CountTrailingZeros_32(NonZeros);
5270 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
5271 Op.getOperand(Idx));
5272 return getShuffleVectorZeroOrUndef(V2, Idx, true,
5273 Subtarget->hasXMMInt(), DAG);
5278 // If element VT is < 32 bits, convert it to inserts into a zero vector.
5279 if (EVTBits == 8 && NumElems == 16) {
5280 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
5282 if (V.getNode()) return V;
5285 if (EVTBits == 16 && NumElems == 8) {
5286 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
5288 if (V.getNode()) return V;
5291 // If element VT is == 32 bits, turn it into a number of shuffles.
5292 SmallVector<SDValue, 8> V;
5294 if (NumElems == 4 && NumZero > 0) {
5295 for (unsigned i = 0; i < 4; ++i) {
5296 bool isZero = !(NonZeros & (1 << i));
5298 V[i] = getZeroVector(VT, Subtarget->hasXMMInt(), DAG, dl);
5300 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5303 for (unsigned i = 0; i < 2; ++i) {
5304 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
5307 V[i] = V[i*2]; // Must be a zero vector.
5310 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
5313 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
5316 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
5321 SmallVector<int, 8> MaskVec;
5322 bool Reverse = (NonZeros & 0x3) == 2;
5323 for (unsigned i = 0; i < 2; ++i)
5324 MaskVec.push_back(Reverse ? 1-i : i);
5325 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2;
5326 for (unsigned i = 0; i < 2; ++i)
5327 MaskVec.push_back(Reverse ? 1-i+NumElems : i+NumElems);
5328 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
5331 if (Values.size() > 1 && VT.getSizeInBits() == 128) {
5332 // Check for a build vector of consecutive loads.
5333 for (unsigned i = 0; i < NumElems; ++i)
5334 V[i] = Op.getOperand(i);
5336 // Check for elements which are consecutive loads.
5337 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG);
5341 // For SSE 4.1, use insertps to put the high elements into the low element.
5342 if (getSubtarget()->hasSSE41orAVX()) {
5344 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
5345 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
5347 Result = DAG.getUNDEF(VT);
5349 for (unsigned i = 1; i < NumElems; ++i) {
5350 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
5351 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
5352 Op.getOperand(i), DAG.getIntPtrConstant(i));
5357 // Otherwise, expand into a number of unpckl*, start by extending each of
5358 // our (non-undef) elements to the full vector width with the element in the
5359 // bottom slot of the vector (which generates no code for SSE).
5360 for (unsigned i = 0; i < NumElems; ++i) {
5361 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
5362 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5364 V[i] = DAG.getUNDEF(VT);
5367 // Next, we iteratively mix elements, e.g. for v4f32:
5368 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
5369 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
5370 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
5371 unsigned EltStride = NumElems >> 1;
5372 while (EltStride != 0) {
5373 for (unsigned i = 0; i < EltStride; ++i) {
5374 // If V[i+EltStride] is undef and this is the first round of mixing,
5375 // then it is safe to just drop this shuffle: V[i] is already in the
5376 // right place, the one element (since it's the first round) being
5377 // inserted as undef can be dropped. This isn't safe for successive
5378 // rounds because they will permute elements within both vectors.
5379 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
5380 EltStride == NumElems/2)
5383 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
5392 // LowerMMXCONCAT_VECTORS - We support concatenate two MMX registers and place
5393 // them in a MMX register. This is better than doing a stack convert.
5394 static SDValue LowerMMXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5395 DebugLoc dl = Op.getDebugLoc();
5396 EVT ResVT = Op.getValueType();
5398 assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 ||
5399 ResVT == MVT::v8i16 || ResVT == MVT::v16i8);
5401 SDValue InVec = DAG.getNode(ISD::BITCAST,dl, MVT::v1i64, Op.getOperand(0));
5402 SDValue VecOp = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
5403 InVec = Op.getOperand(1);
5404 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
5405 unsigned NumElts = ResVT.getVectorNumElements();
5406 VecOp = DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp);
5407 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp,
5408 InVec.getOperand(0), DAG.getIntPtrConstant(NumElts/2+1));
5410 InVec = DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, InVec);
5411 SDValue VecOp2 = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
5412 Mask[0] = 0; Mask[1] = 2;
5413 VecOp = DAG.getVectorShuffle(MVT::v2i64, dl, VecOp, VecOp2, Mask);
5415 return DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp);
5418 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
5419 // to create 256-bit vectors from two other 128-bit ones.
5420 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5421 DebugLoc dl = Op.getDebugLoc();
5422 EVT ResVT = Op.getValueType();
5424 assert(ResVT.getSizeInBits() == 256 && "Value type must be 256-bit wide");
5426 SDValue V1 = Op.getOperand(0);
5427 SDValue V2 = Op.getOperand(1);
5428 unsigned NumElems = ResVT.getVectorNumElements();
5430 SDValue V = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, ResVT), V1,
5431 DAG.getConstant(0, MVT::i32), DAG, dl);
5432 return Insert128BitVector(V, V2, DAG.getConstant(NumElems/2, MVT::i32),
5437 X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const {
5438 EVT ResVT = Op.getValueType();
5440 assert(Op.getNumOperands() == 2);
5441 assert((ResVT.getSizeInBits() == 128 || ResVT.getSizeInBits() == 256) &&
5442 "Unsupported CONCAT_VECTORS for value type");
5444 // We support concatenate two MMX registers and place them in a MMX register.
5445 // This is better than doing a stack convert.
5446 if (ResVT.is128BitVector())
5447 return LowerMMXCONCAT_VECTORS(Op, DAG);
5449 // 256-bit AVX can use the vinsertf128 instruction to create 256-bit vectors
5450 // from two other 128-bit ones.
5451 return LowerAVXCONCAT_VECTORS(Op, DAG);
5454 // v8i16 shuffles - Prefer shuffles in the following order:
5455 // 1. [all] pshuflw, pshufhw, optional move
5456 // 2. [ssse3] 1 x pshufb
5457 // 3. [ssse3] 2 x pshufb + 1 x por
5458 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
5460 X86TargetLowering::LowerVECTOR_SHUFFLEv8i16(SDValue Op,
5461 SelectionDAG &DAG) const {
5462 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5463 SDValue V1 = SVOp->getOperand(0);
5464 SDValue V2 = SVOp->getOperand(1);
5465 DebugLoc dl = SVOp->getDebugLoc();
5466 SmallVector<int, 8> MaskVals;
5468 // Determine if more than 1 of the words in each of the low and high quadwords
5469 // of the result come from the same quadword of one of the two inputs. Undef
5470 // mask values count as coming from any quadword, for better codegen.
5471 unsigned LoQuad[] = { 0, 0, 0, 0 };
5472 unsigned HiQuad[] = { 0, 0, 0, 0 };
5473 BitVector InputQuads(4);
5474 for (unsigned i = 0; i < 8; ++i) {
5475 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
5476 int EltIdx = SVOp->getMaskElt(i);
5477 MaskVals.push_back(EltIdx);
5486 InputQuads.set(EltIdx / 4);
5489 int BestLoQuad = -1;
5490 unsigned MaxQuad = 1;
5491 for (unsigned i = 0; i < 4; ++i) {
5492 if (LoQuad[i] > MaxQuad) {
5494 MaxQuad = LoQuad[i];
5498 int BestHiQuad = -1;
5500 for (unsigned i = 0; i < 4; ++i) {
5501 if (HiQuad[i] > MaxQuad) {
5503 MaxQuad = HiQuad[i];
5507 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
5508 // of the two input vectors, shuffle them into one input vector so only a
5509 // single pshufb instruction is necessary. If There are more than 2 input
5510 // quads, disable the next transformation since it does not help SSSE3.
5511 bool V1Used = InputQuads[0] || InputQuads[1];
5512 bool V2Used = InputQuads[2] || InputQuads[3];
5513 if (Subtarget->hasSSSE3orAVX()) {
5514 if (InputQuads.count() == 2 && V1Used && V2Used) {
5515 BestLoQuad = InputQuads.find_first();
5516 BestHiQuad = InputQuads.find_next(BestLoQuad);
5518 if (InputQuads.count() > 2) {
5524 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
5525 // the shuffle mask. If a quad is scored as -1, that means that it contains
5526 // words from all 4 input quadwords.
5528 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
5529 SmallVector<int, 8> MaskV;
5530 MaskV.push_back(BestLoQuad < 0 ? 0 : BestLoQuad);
5531 MaskV.push_back(BestHiQuad < 0 ? 1 : BestHiQuad);
5532 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
5533 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
5534 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
5535 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
5537 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
5538 // source words for the shuffle, to aid later transformations.
5539 bool AllWordsInNewV = true;
5540 bool InOrder[2] = { true, true };
5541 for (unsigned i = 0; i != 8; ++i) {
5542 int idx = MaskVals[i];
5544 InOrder[i/4] = false;
5545 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
5547 AllWordsInNewV = false;
5551 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
5552 if (AllWordsInNewV) {
5553 for (int i = 0; i != 8; ++i) {
5554 int idx = MaskVals[i];
5557 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
5558 if ((idx != i) && idx < 4)
5560 if ((idx != i) && idx > 3)
5569 // If we've eliminated the use of V2, and the new mask is a pshuflw or
5570 // pshufhw, that's as cheap as it gets. Return the new shuffle.
5571 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
5572 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
5573 unsigned TargetMask = 0;
5574 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
5575 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
5576 TargetMask = pshufhw ? X86::getShufflePSHUFHWImmediate(NewV.getNode()):
5577 X86::getShufflePSHUFLWImmediate(NewV.getNode());
5578 V1 = NewV.getOperand(0);
5579 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
5583 // If we have SSSE3, and all words of the result are from 1 input vector,
5584 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
5585 // is present, fall back to case 4.
5586 if (Subtarget->hasSSSE3orAVX()) {
5587 SmallVector<SDValue,16> pshufbMask;
5589 // If we have elements from both input vectors, set the high bit of the
5590 // shuffle mask element to zero out elements that come from V2 in the V1
5591 // mask, and elements that come from V1 in the V2 mask, so that the two
5592 // results can be OR'd together.
5593 bool TwoInputs = V1Used && V2Used;
5594 for (unsigned i = 0; i != 8; ++i) {
5595 int EltIdx = MaskVals[i] * 2;
5596 if (TwoInputs && (EltIdx >= 16)) {
5597 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5598 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5601 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
5602 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8));
5604 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1);
5605 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5606 DAG.getNode(ISD::BUILD_VECTOR, dl,
5607 MVT::v16i8, &pshufbMask[0], 16));
5609 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5611 // Calculate the shuffle mask for the second input, shuffle it, and
5612 // OR it with the first shuffled input.
5614 for (unsigned i = 0; i != 8; ++i) {
5615 int EltIdx = MaskVals[i] * 2;
5617 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5618 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5621 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
5622 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8));
5624 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2);
5625 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
5626 DAG.getNode(ISD::BUILD_VECTOR, dl,
5627 MVT::v16i8, &pshufbMask[0], 16));
5628 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5629 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5632 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
5633 // and update MaskVals with new element order.
5634 BitVector InOrder(8);
5635 if (BestLoQuad >= 0) {
5636 SmallVector<int, 8> MaskV;
5637 for (int i = 0; i != 4; ++i) {
5638 int idx = MaskVals[i];
5640 MaskV.push_back(-1);
5642 } else if ((idx / 4) == BestLoQuad) {
5643 MaskV.push_back(idx & 3);
5646 MaskV.push_back(-1);
5649 for (unsigned i = 4; i != 8; ++i)
5651 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5654 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3orAVX())
5655 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
5657 X86::getShufflePSHUFLWImmediate(NewV.getNode()),
5661 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
5662 // and update MaskVals with the new element order.
5663 if (BestHiQuad >= 0) {
5664 SmallVector<int, 8> MaskV;
5665 for (unsigned i = 0; i != 4; ++i)
5667 for (unsigned i = 4; i != 8; ++i) {
5668 int idx = MaskVals[i];
5670 MaskV.push_back(-1);
5672 } else if ((idx / 4) == BestHiQuad) {
5673 MaskV.push_back((idx & 3) + 4);
5676 MaskV.push_back(-1);
5679 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5682 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3orAVX())
5683 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
5685 X86::getShufflePSHUFHWImmediate(NewV.getNode()),
5689 // In case BestHi & BestLo were both -1, which means each quadword has a word
5690 // from each of the four input quadwords, calculate the InOrder bitvector now
5691 // before falling through to the insert/extract cleanup.
5692 if (BestLoQuad == -1 && BestHiQuad == -1) {
5694 for (int i = 0; i != 8; ++i)
5695 if (MaskVals[i] < 0 || MaskVals[i] == i)
5699 // The other elements are put in the right place using pextrw and pinsrw.
5700 for (unsigned i = 0; i != 8; ++i) {
5703 int EltIdx = MaskVals[i];
5706 SDValue ExtOp = (EltIdx < 8)
5707 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
5708 DAG.getIntPtrConstant(EltIdx))
5709 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
5710 DAG.getIntPtrConstant(EltIdx - 8));
5711 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
5712 DAG.getIntPtrConstant(i));
5717 // v16i8 shuffles - Prefer shuffles in the following order:
5718 // 1. [ssse3] 1 x pshufb
5719 // 2. [ssse3] 2 x pshufb + 1 x por
5720 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
5722 SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
5724 const X86TargetLowering &TLI) {
5725 SDValue V1 = SVOp->getOperand(0);
5726 SDValue V2 = SVOp->getOperand(1);
5727 DebugLoc dl = SVOp->getDebugLoc();
5728 SmallVector<int, 16> MaskVals;
5729 SVOp->getMask(MaskVals);
5731 // If we have SSSE3, case 1 is generated when all result bytes come from
5732 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
5733 // present, fall back to case 3.
5734 // FIXME: kill V2Only once shuffles are canonizalized by getNode.
5737 for (unsigned i = 0; i < 16; ++i) {
5738 int EltIdx = MaskVals[i];
5747 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
5748 if (TLI.getSubtarget()->hasSSSE3orAVX()) {
5749 SmallVector<SDValue,16> pshufbMask;
5751 // If all result elements are from one input vector, then only translate
5752 // undef mask values to 0x80 (zero out result) in the pshufb mask.
5754 // Otherwise, we have elements from both input vectors, and must zero out
5755 // elements that come from V2 in the first mask, and V1 in the second mask
5756 // so that we can OR them together.
5757 bool TwoInputs = !(V1Only || V2Only);
5758 for (unsigned i = 0; i != 16; ++i) {
5759 int EltIdx = MaskVals[i];
5760 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) {
5761 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5764 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
5766 // If all the elements are from V2, assign it to V1 and return after
5767 // building the first pshufb.
5770 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5771 DAG.getNode(ISD::BUILD_VECTOR, dl,
5772 MVT::v16i8, &pshufbMask[0], 16));
5776 // Calculate the shuffle mask for the second input, shuffle it, and
5777 // OR it with the first shuffled input.
5779 for (unsigned i = 0; i != 16; ++i) {
5780 int EltIdx = MaskVals[i];
5782 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5785 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
5787 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
5788 DAG.getNode(ISD::BUILD_VECTOR, dl,
5789 MVT::v16i8, &pshufbMask[0], 16));
5790 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5793 // No SSSE3 - Calculate in place words and then fix all out of place words
5794 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
5795 // the 16 different words that comprise the two doublequadword input vectors.
5796 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5797 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
5798 SDValue NewV = V2Only ? V2 : V1;
5799 for (int i = 0; i != 8; ++i) {
5800 int Elt0 = MaskVals[i*2];
5801 int Elt1 = MaskVals[i*2+1];
5803 // This word of the result is all undef, skip it.
5804 if (Elt0 < 0 && Elt1 < 0)
5807 // This word of the result is already in the correct place, skip it.
5808 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1))
5810 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17))
5813 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
5814 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
5817 // If Elt0 and Elt1 are defined, are consecutive, and can be load
5818 // using a single extract together, load it and store it.
5819 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
5820 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
5821 DAG.getIntPtrConstant(Elt1 / 2));
5822 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
5823 DAG.getIntPtrConstant(i));
5827 // If Elt1 is defined, extract it from the appropriate source. If the
5828 // source byte is not also odd, shift the extracted word left 8 bits
5829 // otherwise clear the bottom 8 bits if we need to do an or.
5831 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
5832 DAG.getIntPtrConstant(Elt1 / 2));
5833 if ((Elt1 & 1) == 0)
5834 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
5836 TLI.getShiftAmountTy(InsElt.getValueType())));
5838 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
5839 DAG.getConstant(0xFF00, MVT::i16));
5841 // If Elt0 is defined, extract it from the appropriate source. If the
5842 // source byte is not also even, shift the extracted word right 8 bits. If
5843 // Elt1 was also defined, OR the extracted values together before
5844 // inserting them in the result.
5846 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
5847 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
5848 if ((Elt0 & 1) != 0)
5849 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
5851 TLI.getShiftAmountTy(InsElt0.getValueType())));
5853 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
5854 DAG.getConstant(0x00FF, MVT::i16));
5855 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
5858 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
5859 DAG.getIntPtrConstant(i));
5861 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
5864 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
5865 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
5866 /// done when every pair / quad of shuffle mask elements point to elements in
5867 /// the right sequence. e.g.
5868 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
5870 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
5871 SelectionDAG &DAG, DebugLoc dl) {
5872 EVT VT = SVOp->getValueType(0);
5873 SDValue V1 = SVOp->getOperand(0);
5874 SDValue V2 = SVOp->getOperand(1);
5875 unsigned NumElems = VT.getVectorNumElements();
5876 unsigned NewWidth = (NumElems == 4) ? 2 : 4;
5878 switch (VT.getSimpleVT().SimpleTy) {
5879 default: assert(false && "Unexpected!");
5880 case MVT::v4f32: NewVT = MVT::v2f64; break;
5881 case MVT::v4i32: NewVT = MVT::v2i64; break;
5882 case MVT::v8i16: NewVT = MVT::v4i32; break;
5883 case MVT::v16i8: NewVT = MVT::v4i32; break;
5886 int Scale = NumElems / NewWidth;
5887 SmallVector<int, 8> MaskVec;
5888 for (unsigned i = 0; i < NumElems; i += Scale) {
5890 for (int j = 0; j < Scale; ++j) {
5891 int EltIdx = SVOp->getMaskElt(i+j);
5895 StartIdx = EltIdx - (EltIdx % Scale);
5896 if (EltIdx != StartIdx + j)
5900 MaskVec.push_back(-1);
5902 MaskVec.push_back(StartIdx / Scale);
5905 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
5906 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
5907 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
5910 /// getVZextMovL - Return a zero-extending vector move low node.
5912 static SDValue getVZextMovL(EVT VT, EVT OpVT,
5913 SDValue SrcOp, SelectionDAG &DAG,
5914 const X86Subtarget *Subtarget, DebugLoc dl) {
5915 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
5916 LoadSDNode *LD = NULL;
5917 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
5918 LD = dyn_cast<LoadSDNode>(SrcOp);
5920 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
5922 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
5923 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
5924 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
5925 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
5926 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
5928 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
5929 return DAG.getNode(ISD::BITCAST, dl, VT,
5930 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
5931 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5939 return DAG.getNode(ISD::BITCAST, dl, VT,
5940 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
5941 DAG.getNode(ISD::BITCAST, dl,
5945 /// areShuffleHalvesWithinDisjointLanes - Check whether each half of a vector
5946 /// shuffle node referes to only one lane in the sources.
5947 static bool areShuffleHalvesWithinDisjointLanes(ShuffleVectorSDNode *SVOp) {
5948 EVT VT = SVOp->getValueType(0);
5949 int NumElems = VT.getVectorNumElements();
5950 int HalfSize = NumElems/2;
5951 SmallVector<int, 16> M;
5953 bool MatchA = false, MatchB = false;
5955 for (int l = 0; l < NumElems*2; l += HalfSize) {
5956 if (isUndefOrInRange(M, 0, HalfSize, l, l+HalfSize)) {
5962 for (int l = 0; l < NumElems*2; l += HalfSize) {
5963 if (isUndefOrInRange(M, HalfSize, HalfSize, l, l+HalfSize)) {
5969 return MatchA && MatchB;
5972 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
5973 /// which could not be matched by any known target speficic shuffle
5975 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
5976 if (areShuffleHalvesWithinDisjointLanes(SVOp)) {
5977 // If each half of a vector shuffle node referes to only one lane in the
5978 // source vectors, extract each used 128-bit lane and shuffle them using
5979 // 128-bit shuffles. Then, concatenate the results. Otherwise leave
5980 // the work to the legalizer.
5981 DebugLoc dl = SVOp->getDebugLoc();
5982 EVT VT = SVOp->getValueType(0);
5983 int NumElems = VT.getVectorNumElements();
5984 int HalfSize = NumElems/2;
5986 // Extract the reference for each half
5987 int FstVecExtractIdx = 0, SndVecExtractIdx = 0;
5988 int FstVecOpNum = 0, SndVecOpNum = 0;
5989 for (int i = 0; i < HalfSize; ++i) {
5990 int Elt = SVOp->getMaskElt(i);
5991 if (SVOp->getMaskElt(i) < 0)
5993 FstVecOpNum = Elt/NumElems;
5994 FstVecExtractIdx = Elt % NumElems < HalfSize ? 0 : HalfSize;
5997 for (int i = HalfSize; i < NumElems; ++i) {
5998 int Elt = SVOp->getMaskElt(i);
5999 if (SVOp->getMaskElt(i) < 0)
6001 SndVecOpNum = Elt/NumElems;
6002 SndVecExtractIdx = Elt % NumElems < HalfSize ? 0 : HalfSize;
6006 // Extract the subvectors
6007 SDValue V1 = Extract128BitVector(SVOp->getOperand(FstVecOpNum),
6008 DAG.getConstant(FstVecExtractIdx, MVT::i32), DAG, dl);
6009 SDValue V2 = Extract128BitVector(SVOp->getOperand(SndVecOpNum),
6010 DAG.getConstant(SndVecExtractIdx, MVT::i32), DAG, dl);
6012 // Generate 128-bit shuffles
6013 SmallVector<int, 16> MaskV1, MaskV2;
6014 for (int i = 0; i < HalfSize; ++i) {
6015 int Elt = SVOp->getMaskElt(i);
6016 MaskV1.push_back(Elt < 0 ? Elt : Elt % HalfSize);
6018 for (int i = HalfSize; i < NumElems; ++i) {
6019 int Elt = SVOp->getMaskElt(i);
6020 MaskV2.push_back(Elt < 0 ? Elt : Elt % HalfSize);
6023 EVT NVT = V1.getValueType();
6024 V1 = DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &MaskV1[0]);
6025 V2 = DAG.getVectorShuffle(NVT, dl, V2, DAG.getUNDEF(NVT), &MaskV2[0]);
6027 // Concatenate the result back
6028 SDValue V = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), V1,
6029 DAG.getConstant(0, MVT::i32), DAG, dl);
6030 return Insert128BitVector(V, V2, DAG.getConstant(NumElems/2, MVT::i32),
6037 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
6038 /// 4 elements, and match them with several different shuffle types.
6040 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
6041 SDValue V1 = SVOp->getOperand(0);
6042 SDValue V2 = SVOp->getOperand(1);
6043 DebugLoc dl = SVOp->getDebugLoc();
6044 EVT VT = SVOp->getValueType(0);
6046 assert(VT.getSizeInBits() == 128 && "Unsupported vector size");
6048 SmallVector<std::pair<int, int>, 8> Locs;
6050 SmallVector<int, 8> Mask1(4U, -1);
6051 SmallVector<int, 8> PermMask;
6052 SVOp->getMask(PermMask);
6056 for (unsigned i = 0; i != 4; ++i) {
6057 int Idx = PermMask[i];
6059 Locs[i] = std::make_pair(-1, -1);
6061 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
6063 Locs[i] = std::make_pair(0, NumLo);
6067 Locs[i] = std::make_pair(1, NumHi);
6069 Mask1[2+NumHi] = Idx;
6075 if (NumLo <= 2 && NumHi <= 2) {
6076 // If no more than two elements come from either vector. This can be
6077 // implemented with two shuffles. First shuffle gather the elements.
6078 // The second shuffle, which takes the first shuffle as both of its
6079 // vector operands, put the elements into the right order.
6080 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6082 SmallVector<int, 8> Mask2(4U, -1);
6084 for (unsigned i = 0; i != 4; ++i) {
6085 if (Locs[i].first == -1)
6088 unsigned Idx = (i < 2) ? 0 : 4;
6089 Idx += Locs[i].first * 2 + Locs[i].second;
6094 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
6095 } else if (NumLo == 3 || NumHi == 3) {
6096 // Otherwise, we must have three elements from one vector, call it X, and
6097 // one element from the other, call it Y. First, use a shufps to build an
6098 // intermediate vector with the one element from Y and the element from X
6099 // that will be in the same half in the final destination (the indexes don't
6100 // matter). Then, use a shufps to build the final vector, taking the half
6101 // containing the element from Y from the intermediate, and the other half
6104 // Normalize it so the 3 elements come from V1.
6105 CommuteVectorShuffleMask(PermMask, 4);
6109 // Find the element from V2.
6111 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
6112 int Val = PermMask[HiIndex];
6119 Mask1[0] = PermMask[HiIndex];
6121 Mask1[2] = PermMask[HiIndex^1];
6123 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6126 Mask1[0] = PermMask[0];
6127 Mask1[1] = PermMask[1];
6128 Mask1[2] = HiIndex & 1 ? 6 : 4;
6129 Mask1[3] = HiIndex & 1 ? 4 : 6;
6130 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6132 Mask1[0] = HiIndex & 1 ? 2 : 0;
6133 Mask1[1] = HiIndex & 1 ? 0 : 2;
6134 Mask1[2] = PermMask[2];
6135 Mask1[3] = PermMask[3];
6140 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
6144 // Break it into (shuffle shuffle_hi, shuffle_lo).
6147 SmallVector<int,8> LoMask(4U, -1);
6148 SmallVector<int,8> HiMask(4U, -1);
6150 SmallVector<int,8> *MaskPtr = &LoMask;
6151 unsigned MaskIdx = 0;
6154 for (unsigned i = 0; i != 4; ++i) {
6161 int Idx = PermMask[i];
6163 Locs[i] = std::make_pair(-1, -1);
6164 } else if (Idx < 4) {
6165 Locs[i] = std::make_pair(MaskIdx, LoIdx);
6166 (*MaskPtr)[LoIdx] = Idx;
6169 Locs[i] = std::make_pair(MaskIdx, HiIdx);
6170 (*MaskPtr)[HiIdx] = Idx;
6175 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
6176 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
6177 SmallVector<int, 8> MaskOps;
6178 for (unsigned i = 0; i != 4; ++i) {
6179 if (Locs[i].first == -1) {
6180 MaskOps.push_back(-1);
6182 unsigned Idx = Locs[i].first * 4 + Locs[i].second;
6183 MaskOps.push_back(Idx);
6186 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
6189 static bool MayFoldVectorLoad(SDValue V) {
6190 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6191 V = V.getOperand(0);
6192 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6193 V = V.getOperand(0);
6194 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
6195 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
6196 // BUILD_VECTOR (load), undef
6197 V = V.getOperand(0);
6203 // FIXME: the version above should always be used. Since there's
6204 // a bug where several vector shuffles can't be folded because the
6205 // DAG is not updated during lowering and a node claims to have two
6206 // uses while it only has one, use this version, and let isel match
6207 // another instruction if the load really happens to have more than
6208 // one use. Remove this version after this bug get fixed.
6209 // rdar://8434668, PR8156
6210 static bool RelaxedMayFoldVectorLoad(SDValue V) {
6211 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6212 V = V.getOperand(0);
6213 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6214 V = V.getOperand(0);
6215 if (ISD::isNormalLoad(V.getNode()))
6220 /// CanFoldShuffleIntoVExtract - Check if the current shuffle is used by
6221 /// a vector extract, and if both can be later optimized into a single load.
6222 /// This is done in visitEXTRACT_VECTOR_ELT and the conditions are checked
6223 /// here because otherwise a target specific shuffle node is going to be
6224 /// emitted for this shuffle, and the optimization not done.
6225 /// FIXME: This is probably not the best approach, but fix the problem
6226 /// until the right path is decided.
6228 bool CanXFormVExtractWithShuffleIntoLoad(SDValue V, SelectionDAG &DAG,
6229 const TargetLowering &TLI) {
6230 EVT VT = V.getValueType();
6231 ShuffleVectorSDNode *SVOp = dyn_cast<ShuffleVectorSDNode>(V);
6233 // Be sure that the vector shuffle is present in a pattern like this:
6234 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), c) -> (f32 load $addr)
6238 SDNode *N = *V.getNode()->use_begin();
6239 if (N->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
6242 SDValue EltNo = N->getOperand(1);
6243 if (!isa<ConstantSDNode>(EltNo))
6246 // If the bit convert changed the number of elements, it is unsafe
6247 // to examine the mask.
6248 bool HasShuffleIntoBitcast = false;
6249 if (V.getOpcode() == ISD::BITCAST) {
6250 EVT SrcVT = V.getOperand(0).getValueType();
6251 if (SrcVT.getVectorNumElements() != VT.getVectorNumElements())
6253 V = V.getOperand(0);
6254 HasShuffleIntoBitcast = true;
6257 // Select the input vector, guarding against out of range extract vector.
6258 unsigned NumElems = VT.getVectorNumElements();
6259 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
6260 int Idx = (Elt > NumElems) ? -1 : SVOp->getMaskElt(Elt);
6261 V = (Idx < (int)NumElems) ? V.getOperand(0) : V.getOperand(1);
6263 // Skip one more bit_convert if necessary
6264 if (V.getOpcode() == ISD::BITCAST)
6265 V = V.getOperand(0);
6267 if (!ISD::isNormalLoad(V.getNode()))
6270 // Is the original load suitable?
6271 LoadSDNode *LN0 = cast<LoadSDNode>(V);
6273 if (!LN0 || !LN0->hasNUsesOfValue(1,0) || LN0->isVolatile())
6276 if (!HasShuffleIntoBitcast)
6279 // If there's a bitcast before the shuffle, check if the load type and
6280 // alignment is valid.
6281 unsigned Align = LN0->getAlignment();
6283 TLI.getTargetData()->getABITypeAlignment(
6284 VT.getTypeForEVT(*DAG.getContext()));
6286 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
6293 SDValue getMOVDDup(SDValue &Op, DebugLoc &dl, SDValue V1, SelectionDAG &DAG) {
6294 EVT VT = Op.getValueType();
6296 // Canonizalize to v2f64.
6297 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
6298 return DAG.getNode(ISD::BITCAST, dl, VT,
6299 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
6304 SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG,
6306 SDValue V1 = Op.getOperand(0);
6307 SDValue V2 = Op.getOperand(1);
6308 EVT VT = Op.getValueType();
6310 assert(VT != MVT::v2i64 && "unsupported shuffle type");
6312 if (HasXMMInt && VT == MVT::v2f64)
6313 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
6315 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
6316 return DAG.getNode(ISD::BITCAST, dl, VT,
6317 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
6318 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
6319 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
6323 SDValue getMOVHighToLow(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG) {
6324 SDValue V1 = Op.getOperand(0);
6325 SDValue V2 = Op.getOperand(1);
6326 EVT VT = Op.getValueType();
6328 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
6329 "unsupported shuffle type");
6331 if (V2.getOpcode() == ISD::UNDEF)
6335 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
6339 SDValue getMOVLP(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasXMMInt) {
6340 SDValue V1 = Op.getOperand(0);
6341 SDValue V2 = Op.getOperand(1);
6342 EVT VT = Op.getValueType();
6343 unsigned NumElems = VT.getVectorNumElements();
6345 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
6346 // operand of these instructions is only memory, so check if there's a
6347 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
6349 bool CanFoldLoad = false;
6351 // Trivial case, when V2 comes from a load.
6352 if (MayFoldVectorLoad(V2))
6355 // When V1 is a load, it can be folded later into a store in isel, example:
6356 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
6358 // (MOVLPSmr addr:$src1, VR128:$src2)
6359 // So, recognize this potential and also use MOVLPS or MOVLPD
6360 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
6363 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6365 if (HasXMMInt && NumElems == 2)
6366 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
6369 // If we don't care about the second element, procede to use movss.
6370 if (SVOp->getMaskElt(1) != -1)
6371 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
6374 // movl and movlp will both match v2i64, but v2i64 is never matched by
6375 // movl earlier because we make it strict to avoid messing with the movlp load
6376 // folding logic (see the code above getMOVLP call). Match it here then,
6377 // this is horrible, but will stay like this until we move all shuffle
6378 // matching to x86 specific nodes. Note that for the 1st condition all
6379 // types are matched with movsd.
6381 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
6382 // as to remove this logic from here, as much as possible
6383 if (NumElems == 2 || !X86::isMOVLMask(SVOp))
6384 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6385 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6388 assert(VT != MVT::v4i32 && "unsupported shuffle type");
6390 // Invert the operand order and use SHUFPS to match it.
6391 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
6392 X86::getShuffleSHUFImmediate(SVOp), DAG);
6396 SDValue NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG,
6397 const TargetLowering &TLI,
6398 const X86Subtarget *Subtarget) {
6399 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6400 EVT VT = Op.getValueType();
6401 DebugLoc dl = Op.getDebugLoc();
6402 SDValue V1 = Op.getOperand(0);
6403 SDValue V2 = Op.getOperand(1);
6405 if (isZeroShuffle(SVOp))
6406 return getZeroVector(VT, Subtarget->hasXMMInt(), DAG, dl);
6408 // Handle splat operations
6409 if (SVOp->isSplat()) {
6410 unsigned NumElem = VT.getVectorNumElements();
6411 int Size = VT.getSizeInBits();
6412 // Special case, this is the only place now where it's allowed to return
6413 // a vector_shuffle operation without using a target specific node, because
6414 // *hopefully* it will be optimized away by the dag combiner. FIXME: should
6415 // this be moved to DAGCombine instead?
6416 if (NumElem <= 4 && CanXFormVExtractWithShuffleIntoLoad(Op, DAG, TLI))
6419 // Use vbroadcast whenever the splat comes from a foldable load
6420 SDValue LD = isVectorBroadcast(Op, Subtarget->hasAVX2());
6421 if (Subtarget->hasAVX() && LD.getNode())
6422 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, LD);
6424 // Handle splats by matching through known shuffle masks
6425 if ((Size == 128 && NumElem <= 4) ||
6426 (Size == 256 && NumElem < 8))
6429 // All remaning splats are promoted to target supported vector shuffles.
6430 return PromoteSplat(SVOp, DAG);
6433 // If the shuffle can be profitably rewritten as a narrower shuffle, then
6435 if (VT == MVT::v8i16 || VT == MVT::v16i8) {
6436 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6437 if (NewOp.getNode())
6438 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
6439 } else if ((VT == MVT::v4i32 ||
6440 (VT == MVT::v4f32 && Subtarget->hasXMMInt()))) {
6441 // FIXME: Figure out a cleaner way to do this.
6442 // Try to make use of movq to zero out the top part.
6443 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
6444 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6445 if (NewOp.getNode()) {
6446 if (isCommutedMOVL(cast<ShuffleVectorSDNode>(NewOp), true, false))
6447 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(0),
6448 DAG, Subtarget, dl);
6450 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
6451 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6452 if (NewOp.getNode() && X86::isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)))
6453 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1),
6454 DAG, Subtarget, dl);
6461 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
6462 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6463 SDValue V1 = Op.getOperand(0);
6464 SDValue V2 = Op.getOperand(1);
6465 EVT VT = Op.getValueType();
6466 DebugLoc dl = Op.getDebugLoc();
6467 unsigned NumElems = VT.getVectorNumElements();
6468 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
6469 bool V1IsSplat = false;
6470 bool V2IsSplat = false;
6471 bool HasXMMInt = Subtarget->hasXMMInt();
6472 bool HasAVX = Subtarget->hasAVX();
6473 bool HasAVX2 = Subtarget->hasAVX2();
6474 MachineFunction &MF = DAG.getMachineFunction();
6475 bool OptForSize = MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize);
6477 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
6479 assert(V1.getOpcode() != ISD::UNDEF && "Op 1 of shuffle should not be undef");
6481 // Vector shuffle lowering takes 3 steps:
6483 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
6484 // narrowing and commutation of operands should be handled.
6485 // 2) Matching of shuffles with known shuffle masks to x86 target specific
6487 // 3) Rewriting of unmatched masks into new generic shuffle operations,
6488 // so the shuffle can be broken into other shuffles and the legalizer can
6489 // try the lowering again.
6491 // The general idea is that no vector_shuffle operation should be left to
6492 // be matched during isel, all of them must be converted to a target specific
6495 // Normalize the input vectors. Here splats, zeroed vectors, profitable
6496 // narrowing and commutation of operands should be handled. The actual code
6497 // doesn't include all of those, work in progress...
6498 SDValue NewOp = NormalizeVectorShuffle(Op, DAG, *this, Subtarget);
6499 if (NewOp.getNode())
6502 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
6503 // unpckh_undef). Only use pshufd if speed is more important than size.
6504 if (OptForSize && X86::isUNPCKL_v_undef_Mask(SVOp, HasAVX2))
6505 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6506 if (OptForSize && X86::isUNPCKH_v_undef_Mask(SVOp, HasAVX2))
6507 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6509 if (X86::isMOVDDUPMask(SVOp) && Subtarget->hasSSE3orAVX() &&
6510 V2IsUndef && RelaxedMayFoldVectorLoad(V1))
6511 return getMOVDDup(Op, dl, V1, DAG);
6513 if (X86::isMOVHLPS_v_undef_Mask(SVOp))
6514 return getMOVHighToLow(Op, dl, DAG);
6516 // Use to match splats
6517 if (HasXMMInt && X86::isUNPCKHMask(SVOp, HasAVX2) && V2IsUndef &&
6518 (VT == MVT::v2f64 || VT == MVT::v2i64))
6519 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6521 if (X86::isPSHUFDMask(SVOp)) {
6522 // The actual implementation will match the mask in the if above and then
6523 // during isel it can match several different instructions, not only pshufd
6524 // as its name says, sad but true, emulate the behavior for now...
6525 if (X86::isMOVDDUPMask(SVOp) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
6526 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
6528 unsigned TargetMask = X86::getShuffleSHUFImmediate(SVOp);
6530 if (HasXMMInt && (VT == MVT::v4f32 || VT == MVT::v4i32))
6531 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
6533 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
6537 // Check if this can be converted into a logical shift.
6538 bool isLeft = false;
6541 bool isShift = HasXMMInt && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
6542 if (isShift && ShVal.hasOneUse()) {
6543 // If the shifted value has multiple uses, it may be cheaper to use
6544 // v_set0 + movlhps or movhlps, etc.
6545 EVT EltVT = VT.getVectorElementType();
6546 ShAmt *= EltVT.getSizeInBits();
6547 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6550 if (X86::isMOVLMask(SVOp)) {
6551 if (ISD::isBuildVectorAllZeros(V1.getNode()))
6552 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
6553 if (!X86::isMOVLPMask(SVOp)) {
6554 if (HasXMMInt && (VT == MVT::v2i64 || VT == MVT::v2f64))
6555 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6557 if (VT == MVT::v4i32 || VT == MVT::v4f32)
6558 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6562 // FIXME: fold these into legal mask.
6563 if (X86::isMOVLHPSMask(SVOp) && !X86::isUNPCKLMask(SVOp, HasAVX2))
6564 return getMOVLowToHigh(Op, dl, DAG, HasXMMInt);
6566 if (X86::isMOVHLPSMask(SVOp))
6567 return getMOVHighToLow(Op, dl, DAG);
6569 if (X86::isMOVSHDUPMask(SVOp, Subtarget))
6570 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
6572 if (X86::isMOVSLDUPMask(SVOp, Subtarget))
6573 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
6575 if (X86::isMOVLPMask(SVOp))
6576 return getMOVLP(Op, dl, DAG, HasXMMInt);
6578 if (ShouldXformToMOVHLPS(SVOp) ||
6579 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), SVOp))
6580 return CommuteVectorShuffle(SVOp, DAG);
6583 // No better options. Use a vshl / vsrl.
6584 EVT EltVT = VT.getVectorElementType();
6585 ShAmt *= EltVT.getSizeInBits();
6586 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6589 bool Commuted = false;
6590 // FIXME: This should also accept a bitcast of a splat? Be careful, not
6591 // 1,1,1,1 -> v8i16 though.
6592 V1IsSplat = isSplatVector(V1.getNode());
6593 V2IsSplat = isSplatVector(V2.getNode());
6595 // Canonicalize the splat or undef, if present, to be on the RHS.
6596 if (V1IsSplat && !V2IsSplat) {
6597 Op = CommuteVectorShuffle(SVOp, DAG);
6598 SVOp = cast<ShuffleVectorSDNode>(Op);
6599 V1 = SVOp->getOperand(0);
6600 V2 = SVOp->getOperand(1);
6601 std::swap(V1IsSplat, V2IsSplat);
6605 SmallVector<int, 32> M;
6608 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
6609 // Shuffling low element of v1 into undef, just return v1.
6612 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
6613 // the instruction selector will not match, so get a canonical MOVL with
6614 // swapped operands to undo the commute.
6615 return getMOVL(DAG, dl, VT, V2, V1);
6618 if (isUNPCKLMask(M, VT, HasAVX2))
6619 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
6621 if (isUNPCKHMask(M, VT, HasAVX2))
6622 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
6625 // Normalize mask so all entries that point to V2 points to its first
6626 // element then try to match unpck{h|l} again. If match, return a
6627 // new vector_shuffle with the corrected mask.
6628 SDValue NewMask = NormalizeMask(SVOp, DAG);
6629 ShuffleVectorSDNode *NSVOp = cast<ShuffleVectorSDNode>(NewMask);
6630 if (NSVOp != SVOp) {
6631 if (X86::isUNPCKLMask(NSVOp, HasAVX2, true)) {
6633 } else if (X86::isUNPCKHMask(NSVOp, HasAVX2, true)) {
6640 // Commute is back and try unpck* again.
6641 // FIXME: this seems wrong.
6642 SDValue NewOp = CommuteVectorShuffle(SVOp, DAG);
6643 ShuffleVectorSDNode *NewSVOp = cast<ShuffleVectorSDNode>(NewOp);
6645 if (X86::isUNPCKLMask(NewSVOp, HasAVX2))
6646 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V2, V1, DAG);
6648 if (X86::isUNPCKHMask(NewSVOp, HasAVX2))
6649 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V2, V1, DAG);
6652 // Normalize the node to match x86 shuffle ops if needed
6653 if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true) ||
6654 isVSHUFPYMask(M, VT, HasAVX, /* Commuted */ true)))
6655 return CommuteVectorShuffle(SVOp, DAG);
6657 // The checks below are all present in isShuffleMaskLegal, but they are
6658 // inlined here right now to enable us to directly emit target specific
6659 // nodes, and remove one by one until they don't return Op anymore.
6661 if (isPALIGNRMask(M, VT, Subtarget->hasSSSE3orAVX()))
6662 return getTargetShuffleNode(X86ISD::PALIGN, dl, VT, V1, V2,
6663 getShufflePALIGNRImmediate(SVOp),
6666 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
6667 SVOp->getSplatIndex() == 0 && V2IsUndef) {
6668 if (VT == MVT::v2f64 || VT == MVT::v2i64)
6669 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6672 if (isPSHUFHWMask(M, VT))
6673 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
6674 X86::getShufflePSHUFHWImmediate(SVOp),
6677 if (isPSHUFLWMask(M, VT))
6678 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
6679 X86::getShufflePSHUFLWImmediate(SVOp),
6682 if (isSHUFPMask(M, VT))
6683 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
6684 X86::getShuffleSHUFImmediate(SVOp), DAG);
6686 if (isUNPCKL_v_undef_Mask(M, VT, HasAVX2))
6687 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6688 if (isUNPCKH_v_undef_Mask(M, VT, HasAVX2))
6689 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6691 //===--------------------------------------------------------------------===//
6692 // Generate target specific nodes for 128 or 256-bit shuffles only
6693 // supported in the AVX instruction set.
6696 // Handle VMOVDDUPY permutations
6697 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasAVX))
6698 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
6700 // Handle VPERMILPS/D* permutations
6701 if (isVPERMILPMask(M, VT, HasAVX))
6702 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1,
6703 getShuffleVPERMILPImmediate(SVOp), DAG);
6705 // Handle VPERM2F128/VPERM2I128 permutations
6706 if (isVPERM2X128Mask(M, VT, HasAVX))
6707 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
6708 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
6710 // Handle VSHUFPS/DY permutations
6711 if (isVSHUFPYMask(M, VT, HasAVX))
6712 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
6713 getShuffleVSHUFPYImmediate(SVOp), DAG);
6715 //===--------------------------------------------------------------------===//
6716 // Since no target specific shuffle was selected for this generic one,
6717 // lower it into other known shuffles. FIXME: this isn't true yet, but
6718 // this is the plan.
6721 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
6722 if (VT == MVT::v8i16) {
6723 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, DAG);
6724 if (NewOp.getNode())
6728 if (VT == MVT::v16i8) {
6729 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this);
6730 if (NewOp.getNode())
6734 // Handle all 128-bit wide vectors with 4 elements, and match them with
6735 // several different shuffle types.
6736 if (NumElems == 4 && VT.getSizeInBits() == 128)
6737 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
6739 // Handle general 256-bit shuffles
6740 if (VT.is256BitVector())
6741 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
6747 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
6748 SelectionDAG &DAG) const {
6749 EVT VT = Op.getValueType();
6750 DebugLoc dl = Op.getDebugLoc();
6752 if (Op.getOperand(0).getValueType().getSizeInBits() != 128)
6755 if (VT.getSizeInBits() == 8) {
6756 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
6757 Op.getOperand(0), Op.getOperand(1));
6758 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
6759 DAG.getValueType(VT));
6760 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6761 } else if (VT.getSizeInBits() == 16) {
6762 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6763 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
6765 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
6766 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6767 DAG.getNode(ISD::BITCAST, dl,
6771 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
6772 Op.getOperand(0), Op.getOperand(1));
6773 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
6774 DAG.getValueType(VT));
6775 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6776 } else if (VT == MVT::f32) {
6777 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
6778 // the result back to FR32 register. It's only worth matching if the
6779 // result has a single use which is a store or a bitcast to i32. And in
6780 // the case of a store, it's not worth it if the index is a constant 0,
6781 // because a MOVSSmr can be used instead, which is smaller and faster.
6782 if (!Op.hasOneUse())
6784 SDNode *User = *Op.getNode()->use_begin();
6785 if ((User->getOpcode() != ISD::STORE ||
6786 (isa<ConstantSDNode>(Op.getOperand(1)) &&
6787 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
6788 (User->getOpcode() != ISD::BITCAST ||
6789 User->getValueType(0) != MVT::i32))
6791 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6792 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
6795 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
6796 } else if (VT == MVT::i32 || VT == MVT::i64) {
6797 // ExtractPS/pextrq works with constant index.
6798 if (isa<ConstantSDNode>(Op.getOperand(1)))
6806 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
6807 SelectionDAG &DAG) const {
6808 if (!isa<ConstantSDNode>(Op.getOperand(1)))
6811 SDValue Vec = Op.getOperand(0);
6812 EVT VecVT = Vec.getValueType();
6814 // If this is a 256-bit vector result, first extract the 128-bit vector and
6815 // then extract the element from the 128-bit vector.
6816 if (VecVT.getSizeInBits() == 256) {
6817 DebugLoc dl = Op.getNode()->getDebugLoc();
6818 unsigned NumElems = VecVT.getVectorNumElements();
6819 SDValue Idx = Op.getOperand(1);
6820 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
6822 // Get the 128-bit vector.
6823 bool Upper = IdxVal >= NumElems/2;
6824 Vec = Extract128BitVector(Vec,
6825 DAG.getConstant(Upper ? NumElems/2 : 0, MVT::i32), DAG, dl);
6827 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
6828 Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : Idx);
6831 assert(Vec.getValueSizeInBits() <= 128 && "Unexpected vector length");
6833 if (Subtarget->hasSSE41orAVX()) {
6834 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
6839 EVT VT = Op.getValueType();
6840 DebugLoc dl = Op.getDebugLoc();
6841 // TODO: handle v16i8.
6842 if (VT.getSizeInBits() == 16) {
6843 SDValue Vec = Op.getOperand(0);
6844 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6846 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
6847 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6848 DAG.getNode(ISD::BITCAST, dl,
6851 // Transform it so it match pextrw which produces a 32-bit result.
6852 EVT EltVT = MVT::i32;
6853 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
6854 Op.getOperand(0), Op.getOperand(1));
6855 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
6856 DAG.getValueType(VT));
6857 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6858 } else if (VT.getSizeInBits() == 32) {
6859 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6863 // SHUFPS the element to the lowest double word, then movss.
6864 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
6865 EVT VVT = Op.getOperand(0).getValueType();
6866 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
6867 DAG.getUNDEF(VVT), Mask);
6868 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
6869 DAG.getIntPtrConstant(0));
6870 } else if (VT.getSizeInBits() == 64) {
6871 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
6872 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
6873 // to match extract_elt for f64.
6874 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6878 // UNPCKHPD the element to the lowest double word, then movsd.
6879 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
6880 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
6881 int Mask[2] = { 1, -1 };
6882 EVT VVT = Op.getOperand(0).getValueType();
6883 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
6884 DAG.getUNDEF(VVT), Mask);
6885 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
6886 DAG.getIntPtrConstant(0));
6893 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op,
6894 SelectionDAG &DAG) const {
6895 EVT VT = Op.getValueType();
6896 EVT EltVT = VT.getVectorElementType();
6897 DebugLoc dl = Op.getDebugLoc();
6899 SDValue N0 = Op.getOperand(0);
6900 SDValue N1 = Op.getOperand(1);
6901 SDValue N2 = Op.getOperand(2);
6903 if (VT.getSizeInBits() == 256)
6906 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
6907 isa<ConstantSDNode>(N2)) {
6909 if (VT == MVT::v8i16)
6910 Opc = X86ISD::PINSRW;
6911 else if (VT == MVT::v16i8)
6912 Opc = X86ISD::PINSRB;
6914 Opc = X86ISD::PINSRB;
6916 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
6918 if (N1.getValueType() != MVT::i32)
6919 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
6920 if (N2.getValueType() != MVT::i32)
6921 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
6922 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
6923 } else if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
6924 // Bits [7:6] of the constant are the source select. This will always be
6925 // zero here. The DAG Combiner may combine an extract_elt index into these
6926 // bits. For example (insert (extract, 3), 2) could be matched by putting
6927 // the '3' into bits [7:6] of X86ISD::INSERTPS.
6928 // Bits [5:4] of the constant are the destination select. This is the
6929 // value of the incoming immediate.
6930 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
6931 // combine either bitwise AND or insert of float 0.0 to set these bits.
6932 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
6933 // Create this as a scalar to vector..
6934 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
6935 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
6936 } else if ((EltVT == MVT::i32 || EltVT == MVT::i64) &&
6937 isa<ConstantSDNode>(N2)) {
6938 // PINSR* works with constant index.
6945 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
6946 EVT VT = Op.getValueType();
6947 EVT EltVT = VT.getVectorElementType();
6949 DebugLoc dl = Op.getDebugLoc();
6950 SDValue N0 = Op.getOperand(0);
6951 SDValue N1 = Op.getOperand(1);
6952 SDValue N2 = Op.getOperand(2);
6954 // If this is a 256-bit vector result, first extract the 128-bit vector,
6955 // insert the element into the extracted half and then place it back.
6956 if (VT.getSizeInBits() == 256) {
6957 if (!isa<ConstantSDNode>(N2))
6960 // Get the desired 128-bit vector half.
6961 unsigned NumElems = VT.getVectorNumElements();
6962 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue();
6963 bool Upper = IdxVal >= NumElems/2;
6964 SDValue Ins128Idx = DAG.getConstant(Upper ? NumElems/2 : 0, MVT::i32);
6965 SDValue V = Extract128BitVector(N0, Ins128Idx, DAG, dl);
6967 // Insert the element into the desired half.
6968 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V,
6969 N1, Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : N2);
6971 // Insert the changed part back to the 256-bit vector
6972 return Insert128BitVector(N0, V, Ins128Idx, DAG, dl);
6975 if (Subtarget->hasSSE41orAVX())
6976 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
6978 if (EltVT == MVT::i8)
6981 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
6982 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
6983 // as its second argument.
6984 if (N1.getValueType() != MVT::i32)
6985 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
6986 if (N2.getValueType() != MVT::i32)
6987 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
6988 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
6994 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6995 LLVMContext *Context = DAG.getContext();
6996 DebugLoc dl = Op.getDebugLoc();
6997 EVT OpVT = Op.getValueType();
6999 // If this is a 256-bit vector result, first insert into a 128-bit
7000 // vector and then insert into the 256-bit vector.
7001 if (OpVT.getSizeInBits() > 128) {
7002 // Insert into a 128-bit vector.
7003 EVT VT128 = EVT::getVectorVT(*Context,
7004 OpVT.getVectorElementType(),
7005 OpVT.getVectorNumElements() / 2);
7007 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
7009 // Insert the 128-bit vector.
7010 return Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, OpVT), Op,
7011 DAG.getConstant(0, MVT::i32),
7015 if (Op.getValueType() == MVT::v1i64 &&
7016 Op.getOperand(0).getValueType() == MVT::i64)
7017 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
7019 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
7020 assert(Op.getValueType().getSimpleVT().getSizeInBits() == 128 &&
7021 "Expected an SSE type!");
7022 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(),
7023 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
7026 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
7027 // a simple subregister reference or explicit instructions to grab
7028 // upper bits of a vector.
7030 X86TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const {
7031 if (Subtarget->hasAVX()) {
7032 DebugLoc dl = Op.getNode()->getDebugLoc();
7033 SDValue Vec = Op.getNode()->getOperand(0);
7034 SDValue Idx = Op.getNode()->getOperand(1);
7036 if (Op.getNode()->getValueType(0).getSizeInBits() == 128
7037 && Vec.getNode()->getValueType(0).getSizeInBits() == 256) {
7038 return Extract128BitVector(Vec, Idx, DAG, dl);
7044 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
7045 // simple superregister reference or explicit instructions to insert
7046 // the upper bits of a vector.
7048 X86TargetLowering::LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const {
7049 if (Subtarget->hasAVX()) {
7050 DebugLoc dl = Op.getNode()->getDebugLoc();
7051 SDValue Vec = Op.getNode()->getOperand(0);
7052 SDValue SubVec = Op.getNode()->getOperand(1);
7053 SDValue Idx = Op.getNode()->getOperand(2);
7055 if (Op.getNode()->getValueType(0).getSizeInBits() == 256
7056 && SubVec.getNode()->getValueType(0).getSizeInBits() == 128) {
7057 return Insert128BitVector(Vec, SubVec, Idx, DAG, dl);
7063 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
7064 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
7065 // one of the above mentioned nodes. It has to be wrapped because otherwise
7066 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
7067 // be used to form addressing mode. These wrapped nodes will be selected
7070 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
7071 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
7073 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7075 unsigned char OpFlag = 0;
7076 unsigned WrapperKind = X86ISD::Wrapper;
7077 CodeModel::Model M = getTargetMachine().getCodeModel();
7079 if (Subtarget->isPICStyleRIPRel() &&
7080 (M == CodeModel::Small || M == CodeModel::Kernel))
7081 WrapperKind = X86ISD::WrapperRIP;
7082 else if (Subtarget->isPICStyleGOT())
7083 OpFlag = X86II::MO_GOTOFF;
7084 else if (Subtarget->isPICStyleStubPIC())
7085 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7087 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
7089 CP->getOffset(), OpFlag);
7090 DebugLoc DL = CP->getDebugLoc();
7091 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7092 // With PIC, the address is actually $g + Offset.
7094 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7095 DAG.getNode(X86ISD::GlobalBaseReg,
7096 DebugLoc(), getPointerTy()),
7103 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
7104 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
7106 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7108 unsigned char OpFlag = 0;
7109 unsigned WrapperKind = X86ISD::Wrapper;
7110 CodeModel::Model M = getTargetMachine().getCodeModel();
7112 if (Subtarget->isPICStyleRIPRel() &&
7113 (M == CodeModel::Small || M == CodeModel::Kernel))
7114 WrapperKind = X86ISD::WrapperRIP;
7115 else if (Subtarget->isPICStyleGOT())
7116 OpFlag = X86II::MO_GOTOFF;
7117 else if (Subtarget->isPICStyleStubPIC())
7118 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7120 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
7122 DebugLoc DL = JT->getDebugLoc();
7123 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7125 // With PIC, the address is actually $g + Offset.
7127 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7128 DAG.getNode(X86ISD::GlobalBaseReg,
7129 DebugLoc(), getPointerTy()),
7136 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
7137 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
7139 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7141 unsigned char OpFlag = 0;
7142 unsigned WrapperKind = X86ISD::Wrapper;
7143 CodeModel::Model M = getTargetMachine().getCodeModel();
7145 if (Subtarget->isPICStyleRIPRel() &&
7146 (M == CodeModel::Small || M == CodeModel::Kernel)) {
7147 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
7148 OpFlag = X86II::MO_GOTPCREL;
7149 WrapperKind = X86ISD::WrapperRIP;
7150 } else if (Subtarget->isPICStyleGOT()) {
7151 OpFlag = X86II::MO_GOT;
7152 } else if (Subtarget->isPICStyleStubPIC()) {
7153 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
7154 } else if (Subtarget->isPICStyleStubNoDynamic()) {
7155 OpFlag = X86II::MO_DARWIN_NONLAZY;
7158 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
7160 DebugLoc DL = Op.getDebugLoc();
7161 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7164 // With PIC, the address is actually $g + Offset.
7165 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
7166 !Subtarget->is64Bit()) {
7167 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7168 DAG.getNode(X86ISD::GlobalBaseReg,
7169 DebugLoc(), getPointerTy()),
7173 // For symbols that require a load from a stub to get the address, emit the
7175 if (isGlobalStubReference(OpFlag))
7176 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
7177 MachinePointerInfo::getGOT(), false, false, false, 0);
7183 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
7184 // Create the TargetBlockAddressAddress node.
7185 unsigned char OpFlags =
7186 Subtarget->ClassifyBlockAddressReference();
7187 CodeModel::Model M = getTargetMachine().getCodeModel();
7188 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
7189 DebugLoc dl = Op.getDebugLoc();
7190 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(),
7191 /*isTarget=*/true, OpFlags);
7193 if (Subtarget->isPICStyleRIPRel() &&
7194 (M == CodeModel::Small || M == CodeModel::Kernel))
7195 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7197 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7199 // With PIC, the address is actually $g + Offset.
7200 if (isGlobalRelativeToPICBase(OpFlags)) {
7201 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7202 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7210 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
7212 SelectionDAG &DAG) const {
7213 // Create the TargetGlobalAddress node, folding in the constant
7214 // offset if it is legal.
7215 unsigned char OpFlags =
7216 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
7217 CodeModel::Model M = getTargetMachine().getCodeModel();
7219 if (OpFlags == X86II::MO_NO_FLAG &&
7220 X86::isOffsetSuitableForCodeModel(Offset, M)) {
7221 // A direct static reference to a global.
7222 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
7225 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
7228 if (Subtarget->isPICStyleRIPRel() &&
7229 (M == CodeModel::Small || M == CodeModel::Kernel))
7230 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7232 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7234 // With PIC, the address is actually $g + Offset.
7235 if (isGlobalRelativeToPICBase(OpFlags)) {
7236 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7237 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7241 // For globals that require a load from a stub to get the address, emit the
7243 if (isGlobalStubReference(OpFlags))
7244 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
7245 MachinePointerInfo::getGOT(), false, false, false, 0);
7247 // If there was a non-zero offset that we didn't fold, create an explicit
7250 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
7251 DAG.getConstant(Offset, getPointerTy()));
7257 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
7258 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
7259 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
7260 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
7264 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
7265 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
7266 unsigned char OperandFlags) {
7267 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7268 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7269 DebugLoc dl = GA->getDebugLoc();
7270 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7271 GA->getValueType(0),
7275 SDValue Ops[] = { Chain, TGA, *InFlag };
7276 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3);
7278 SDValue Ops[] = { Chain, TGA };
7279 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2);
7282 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
7283 MFI->setAdjustsStack(true);
7285 SDValue Flag = Chain.getValue(1);
7286 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
7289 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
7291 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7294 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
7295 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
7296 DAG.getNode(X86ISD::GlobalBaseReg,
7297 DebugLoc(), PtrVT), InFlag);
7298 InFlag = Chain.getValue(1);
7300 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
7303 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
7305 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7307 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
7308 X86::RAX, X86II::MO_TLSGD);
7311 // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
7312 // "local exec" model.
7313 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7314 const EVT PtrVT, TLSModel::Model model,
7316 DebugLoc dl = GA->getDebugLoc();
7318 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
7319 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
7320 is64Bit ? 257 : 256));
7322 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
7323 DAG.getIntPtrConstant(0),
7324 MachinePointerInfo(Ptr),
7325 false, false, false, 0);
7327 unsigned char OperandFlags = 0;
7328 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
7330 unsigned WrapperKind = X86ISD::Wrapper;
7331 if (model == TLSModel::LocalExec) {
7332 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
7333 } else if (is64Bit) {
7334 assert(model == TLSModel::InitialExec);
7335 OperandFlags = X86II::MO_GOTTPOFF;
7336 WrapperKind = X86ISD::WrapperRIP;
7338 assert(model == TLSModel::InitialExec);
7339 OperandFlags = X86II::MO_INDNTPOFF;
7342 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
7344 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7345 GA->getValueType(0),
7346 GA->getOffset(), OperandFlags);
7347 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
7349 if (model == TLSModel::InitialExec)
7350 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
7351 MachinePointerInfo::getGOT(), false, false, false, 0);
7353 // The address of the thread local variable is the add of the thread
7354 // pointer with the offset of the variable.
7355 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
7359 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
7361 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
7362 const GlobalValue *GV = GA->getGlobal();
7364 if (Subtarget->isTargetELF()) {
7365 // TODO: implement the "local dynamic" model
7366 // TODO: implement the "initial exec"model for pic executables
7368 // If GV is an alias then use the aliasee for determining
7369 // thread-localness.
7370 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
7371 GV = GA->resolveAliasedGlobal(false);
7373 TLSModel::Model model
7374 = getTLSModel(GV, getTargetMachine().getRelocationModel());
7377 case TLSModel::GeneralDynamic:
7378 case TLSModel::LocalDynamic: // not implemented
7379 if (Subtarget->is64Bit())
7380 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
7381 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
7383 case TLSModel::InitialExec:
7384 case TLSModel::LocalExec:
7385 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
7386 Subtarget->is64Bit());
7388 } else if (Subtarget->isTargetDarwin()) {
7389 // Darwin only has one model of TLS. Lower to that.
7390 unsigned char OpFlag = 0;
7391 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
7392 X86ISD::WrapperRIP : X86ISD::Wrapper;
7394 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7396 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) &&
7397 !Subtarget->is64Bit();
7399 OpFlag = X86II::MO_TLVP_PIC_BASE;
7401 OpFlag = X86II::MO_TLVP;
7402 DebugLoc DL = Op.getDebugLoc();
7403 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
7404 GA->getValueType(0),
7405 GA->getOffset(), OpFlag);
7406 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7408 // With PIC32, the address is actually $g + Offset.
7410 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7411 DAG.getNode(X86ISD::GlobalBaseReg,
7412 DebugLoc(), getPointerTy()),
7415 // Lowering the machine isd will make sure everything is in the right
7417 SDValue Chain = DAG.getEntryNode();
7418 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7419 SDValue Args[] = { Chain, Offset };
7420 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2);
7422 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
7423 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7424 MFI->setAdjustsStack(true);
7426 // And our return value (tls address) is in the standard call return value
7428 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
7429 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
7434 "TLS not implemented for this target.");
7436 llvm_unreachable("Unreachable");
7441 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
7442 /// and take a 2 x i32 value to shift plus a shift amount.
7443 SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const{
7444 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
7445 EVT VT = Op.getValueType();
7446 unsigned VTBits = VT.getSizeInBits();
7447 DebugLoc dl = Op.getDebugLoc();
7448 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
7449 SDValue ShOpLo = Op.getOperand(0);
7450 SDValue ShOpHi = Op.getOperand(1);
7451 SDValue ShAmt = Op.getOperand(2);
7452 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
7453 DAG.getConstant(VTBits - 1, MVT::i8))
7454 : DAG.getConstant(0, VT);
7457 if (Op.getOpcode() == ISD::SHL_PARTS) {
7458 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
7459 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
7461 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
7462 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
7465 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
7466 DAG.getConstant(VTBits, MVT::i8));
7467 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
7468 AndNode, DAG.getConstant(0, MVT::i8));
7471 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
7472 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
7473 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
7475 if (Op.getOpcode() == ISD::SHL_PARTS) {
7476 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7477 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7479 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7480 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7483 SDValue Ops[2] = { Lo, Hi };
7484 return DAG.getMergeValues(Ops, 2, dl);
7487 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
7488 SelectionDAG &DAG) const {
7489 EVT SrcVT = Op.getOperand(0).getValueType();
7491 if (SrcVT.isVector())
7494 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
7495 "Unknown SINT_TO_FP to lower!");
7497 // These are really Legal; return the operand so the caller accepts it as
7499 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
7501 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
7502 Subtarget->is64Bit()) {
7506 DebugLoc dl = Op.getDebugLoc();
7507 unsigned Size = SrcVT.getSizeInBits()/8;
7508 MachineFunction &MF = DAG.getMachineFunction();
7509 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
7510 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7511 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7513 MachinePointerInfo::getFixedStack(SSFI),
7515 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
7518 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
7520 SelectionDAG &DAG) const {
7522 DebugLoc DL = Op.getDebugLoc();
7524 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
7526 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
7528 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
7530 unsigned ByteSize = SrcVT.getSizeInBits()/8;
7532 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
7533 MachineMemOperand *MMO;
7535 int SSFI = FI->getIndex();
7537 DAG.getMachineFunction()
7538 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7539 MachineMemOperand::MOLoad, ByteSize, ByteSize);
7541 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
7542 StackSlot = StackSlot.getOperand(1);
7544 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
7545 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
7547 Tys, Ops, array_lengthof(Ops),
7551 Chain = Result.getValue(1);
7552 SDValue InFlag = Result.getValue(2);
7554 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
7555 // shouldn't be necessary except that RFP cannot be live across
7556 // multiple blocks. When stackifier is fixed, they can be uncoupled.
7557 MachineFunction &MF = DAG.getMachineFunction();
7558 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
7559 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
7560 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7561 Tys = DAG.getVTList(MVT::Other);
7563 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
7565 MachineMemOperand *MMO =
7566 DAG.getMachineFunction()
7567 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7568 MachineMemOperand::MOStore, SSFISize, SSFISize);
7570 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
7571 Ops, array_lengthof(Ops),
7572 Op.getValueType(), MMO);
7573 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
7574 MachinePointerInfo::getFixedStack(SSFI),
7575 false, false, false, 0);
7581 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
7582 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
7583 SelectionDAG &DAG) const {
7584 // This algorithm is not obvious. Here it is in C code, more or less:
7586 double uint64_to_double( uint32_t hi, uint32_t lo ) {
7587 static const __m128i exp = { 0x4330000045300000ULL, 0 };
7588 static const __m128d bias = { 0x1.0p84, 0x1.0p52 };
7590 // Copy ints to xmm registers.
7591 __m128i xh = _mm_cvtsi32_si128( hi );
7592 __m128i xl = _mm_cvtsi32_si128( lo );
7594 // Combine into low half of a single xmm register.
7595 __m128i x = _mm_unpacklo_epi32( xh, xl );
7599 // Merge in appropriate exponents to give the integer bits the right
7601 x = _mm_unpacklo_epi32( x, exp );
7603 // Subtract away the biases to deal with the IEEE-754 double precision
7605 d = _mm_sub_pd( (__m128d) x, bias );
7607 // All conversions up to here are exact. The correctly rounded result is
7608 // calculated using the current rounding mode using the following
7610 d = _mm_add_sd( d, _mm_unpackhi_pd( d, d ) );
7611 _mm_store_sd( &sd, d ); // Because we are returning doubles in XMM, this
7612 // store doesn't really need to be here (except
7613 // maybe to zero the other double)
7618 DebugLoc dl = Op.getDebugLoc();
7619 LLVMContext *Context = DAG.getContext();
7621 // Build some magic constants.
7622 SmallVector<Constant*,4> CV0;
7623 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x45300000)));
7624 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x43300000)));
7625 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
7626 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
7627 Constant *C0 = ConstantVector::get(CV0);
7628 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
7630 SmallVector<Constant*,2> CV1;
7632 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL))));
7634 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL))));
7635 Constant *C1 = ConstantVector::get(CV1);
7636 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
7638 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
7639 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
7641 DAG.getIntPtrConstant(1)));
7642 SDValue XR2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
7643 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
7645 DAG.getIntPtrConstant(0)));
7646 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, XR1, XR2);
7647 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
7648 MachinePointerInfo::getConstantPool(),
7649 false, false, false, 16);
7650 SDValue Unpck2 = getUnpackl(DAG, dl, MVT::v4i32, Unpck1, CLod0);
7651 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck2);
7652 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
7653 MachinePointerInfo::getConstantPool(),
7654 false, false, false, 16);
7655 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
7657 // Add the halves; easiest way is to swap them into another reg first.
7658 int ShufMask[2] = { 1, -1 };
7659 SDValue Shuf = DAG.getVectorShuffle(MVT::v2f64, dl, Sub,
7660 DAG.getUNDEF(MVT::v2f64), ShufMask);
7661 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::v2f64, Shuf, Sub);
7662 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Add,
7663 DAG.getIntPtrConstant(0));
7666 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
7667 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
7668 SelectionDAG &DAG) const {
7669 DebugLoc dl = Op.getDebugLoc();
7670 // FP constant to bias correct the final result.
7671 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
7674 // Load the 32-bit value into an XMM register.
7675 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
7678 // Zero out the upper parts of the register.
7679 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget->hasXMMInt(),
7682 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
7683 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
7684 DAG.getIntPtrConstant(0));
7686 // Or the load with the bias.
7687 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
7688 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7689 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
7691 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7692 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
7693 MVT::v2f64, Bias)));
7694 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
7695 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
7696 DAG.getIntPtrConstant(0));
7698 // Subtract the bias.
7699 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
7701 // Handle final rounding.
7702 EVT DestVT = Op.getValueType();
7704 if (DestVT.bitsLT(MVT::f64)) {
7705 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
7706 DAG.getIntPtrConstant(0));
7707 } else if (DestVT.bitsGT(MVT::f64)) {
7708 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
7711 // Handle final rounding.
7715 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
7716 SelectionDAG &DAG) const {
7717 SDValue N0 = Op.getOperand(0);
7718 DebugLoc dl = Op.getDebugLoc();
7720 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
7721 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
7722 // the optimization here.
7723 if (DAG.SignBitIsZero(N0))
7724 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
7726 EVT SrcVT = N0.getValueType();
7727 EVT DstVT = Op.getValueType();
7728 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
7729 return LowerUINT_TO_FP_i64(Op, DAG);
7730 else if (SrcVT == MVT::i32 && X86ScalarSSEf64)
7731 return LowerUINT_TO_FP_i32(Op, DAG);
7733 // Make a 64-bit buffer, and use it to build an FILD.
7734 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
7735 if (SrcVT == MVT::i32) {
7736 SDValue WordOff = DAG.getConstant(4, getPointerTy());
7737 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
7738 getPointerTy(), StackSlot, WordOff);
7739 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7740 StackSlot, MachinePointerInfo(),
7742 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
7743 OffsetSlot, MachinePointerInfo(),
7745 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
7749 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
7750 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7751 StackSlot, MachinePointerInfo(),
7753 // For i64 source, we need to add the appropriate power of 2 if the input
7754 // was negative. This is the same as the optimization in
7755 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
7756 // we must be careful to do the computation in x87 extended precision, not
7757 // in SSE. (The generic code can't know it's OK to do this, or how to.)
7758 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
7759 MachineMemOperand *MMO =
7760 DAG.getMachineFunction()
7761 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7762 MachineMemOperand::MOLoad, 8, 8);
7764 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
7765 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
7766 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops, 3,
7769 APInt FF(32, 0x5F800000ULL);
7771 // Check whether the sign bit is set.
7772 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
7773 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
7776 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
7777 SDValue FudgePtr = DAG.getConstantPool(
7778 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
7781 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
7782 SDValue Zero = DAG.getIntPtrConstant(0);
7783 SDValue Four = DAG.getIntPtrConstant(4);
7784 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
7786 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
7788 // Load the value out, extending it from f32 to f80.
7789 // FIXME: Avoid the extend by constructing the right constant pool?
7790 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
7791 FudgePtr, MachinePointerInfo::getConstantPool(),
7792 MVT::f32, false, false, 4);
7793 // Extend everything to 80 bits to force it to be done on x87.
7794 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
7795 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
7798 std::pair<SDValue,SDValue> X86TargetLowering::
7799 FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) const {
7800 DebugLoc DL = Op.getDebugLoc();
7802 EVT DstTy = Op.getValueType();
7805 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
7809 assert(DstTy.getSimpleVT() <= MVT::i64 &&
7810 DstTy.getSimpleVT() >= MVT::i16 &&
7811 "Unknown FP_TO_SINT to lower!");
7813 // These are really Legal.
7814 if (DstTy == MVT::i32 &&
7815 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
7816 return std::make_pair(SDValue(), SDValue());
7817 if (Subtarget->is64Bit() &&
7818 DstTy == MVT::i64 &&
7819 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
7820 return std::make_pair(SDValue(), SDValue());
7822 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
7824 MachineFunction &MF = DAG.getMachineFunction();
7825 unsigned MemSize = DstTy.getSizeInBits()/8;
7826 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
7827 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7832 switch (DstTy.getSimpleVT().SimpleTy) {
7833 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
7834 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
7835 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
7836 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
7839 SDValue Chain = DAG.getEntryNode();
7840 SDValue Value = Op.getOperand(0);
7841 EVT TheVT = Op.getOperand(0).getValueType();
7842 if (isScalarFPTypeInSSEReg(TheVT)) {
7843 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
7844 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
7845 MachinePointerInfo::getFixedStack(SSFI),
7847 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
7849 Chain, StackSlot, DAG.getValueType(TheVT)
7852 MachineMemOperand *MMO =
7853 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7854 MachineMemOperand::MOLoad, MemSize, MemSize);
7855 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, 3,
7857 Chain = Value.getValue(1);
7858 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
7859 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7862 MachineMemOperand *MMO =
7863 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7864 MachineMemOperand::MOStore, MemSize, MemSize);
7866 // Build the FP_TO_INT*_IN_MEM
7867 SDValue Ops[] = { Chain, Value, StackSlot };
7868 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
7869 Ops, 3, DstTy, MMO);
7871 return std::make_pair(FIST, StackSlot);
7874 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
7875 SelectionDAG &DAG) const {
7876 if (Op.getValueType().isVector())
7879 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, true);
7880 SDValue FIST = Vals.first, StackSlot = Vals.second;
7881 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
7882 if (FIST.getNode() == 0) return Op;
7885 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
7886 FIST, StackSlot, MachinePointerInfo(),
7887 false, false, false, 0);
7890 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
7891 SelectionDAG &DAG) const {
7892 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, false);
7893 SDValue FIST = Vals.first, StackSlot = Vals.second;
7894 assert(FIST.getNode() && "Unexpected failure");
7897 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
7898 FIST, StackSlot, MachinePointerInfo(),
7899 false, false, false, 0);
7902 SDValue X86TargetLowering::LowerFABS(SDValue Op,
7903 SelectionDAG &DAG) const {
7904 LLVMContext *Context = DAG.getContext();
7905 DebugLoc dl = Op.getDebugLoc();
7906 EVT VT = Op.getValueType();
7909 EltVT = VT.getVectorElementType();
7910 SmallVector<Constant*,4> CV;
7911 if (EltVT == MVT::f64) {
7912 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))));
7915 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))));
7918 Constant *C = ConstantVector::get(CV);
7919 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7920 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
7921 MachinePointerInfo::getConstantPool(),
7922 false, false, false, 16);
7923 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
7926 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const {
7927 LLVMContext *Context = DAG.getContext();
7928 DebugLoc dl = Op.getDebugLoc();
7929 EVT VT = Op.getValueType();
7931 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
7932 if (VT.isVector()) {
7933 EltVT = VT.getVectorElementType();
7934 NumElts = VT.getVectorNumElements();
7936 SmallVector<Constant*,8> CV;
7937 if (EltVT == MVT::f64) {
7938 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)));
7939 CV.assign(NumElts, C);
7941 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)));
7942 CV.assign(NumElts, C);
7944 Constant *C = ConstantVector::get(CV);
7945 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7946 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
7947 MachinePointerInfo::getConstantPool(),
7948 false, false, false, 16);
7949 if (VT.isVector()) {
7950 MVT XORVT = VT.getSizeInBits() == 128 ? MVT::v2i64 : MVT::v4i64;
7951 return DAG.getNode(ISD::BITCAST, dl, VT,
7952 DAG.getNode(ISD::XOR, dl, XORVT,
7953 DAG.getNode(ISD::BITCAST, dl, XORVT,
7955 DAG.getNode(ISD::BITCAST, dl, XORVT, Mask)));
7957 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
7961 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
7962 LLVMContext *Context = DAG.getContext();
7963 SDValue Op0 = Op.getOperand(0);
7964 SDValue Op1 = Op.getOperand(1);
7965 DebugLoc dl = Op.getDebugLoc();
7966 EVT VT = Op.getValueType();
7967 EVT SrcVT = Op1.getValueType();
7969 // If second operand is smaller, extend it first.
7970 if (SrcVT.bitsLT(VT)) {
7971 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
7974 // And if it is bigger, shrink it first.
7975 if (SrcVT.bitsGT(VT)) {
7976 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
7980 // At this point the operands and the result should have the same
7981 // type, and that won't be f80 since that is not custom lowered.
7983 // First get the sign bit of second operand.
7984 SmallVector<Constant*,4> CV;
7985 if (SrcVT == MVT::f64) {
7986 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))));
7987 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
7989 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))));
7990 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7991 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7992 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7994 Constant *C = ConstantVector::get(CV);
7995 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7996 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
7997 MachinePointerInfo::getConstantPool(),
7998 false, false, false, 16);
7999 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
8001 // Shift sign bit right or left if the two operands have different types.
8002 if (SrcVT.bitsGT(VT)) {
8003 // Op0 is MVT::f32, Op1 is MVT::f64.
8004 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
8005 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
8006 DAG.getConstant(32, MVT::i32));
8007 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
8008 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
8009 DAG.getIntPtrConstant(0));
8012 // Clear first operand sign bit.
8014 if (VT == MVT::f64) {
8015 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
8016 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
8018 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
8019 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8020 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8021 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8023 C = ConstantVector::get(CV);
8024 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8025 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8026 MachinePointerInfo::getConstantPool(),
8027 false, false, false, 16);
8028 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
8030 // Or the value with the sign bit.
8031 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
8034 SDValue X86TargetLowering::LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) const {
8035 SDValue N0 = Op.getOperand(0);
8036 DebugLoc dl = Op.getDebugLoc();
8037 EVT VT = Op.getValueType();
8039 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
8040 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
8041 DAG.getConstant(1, VT));
8042 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
8045 /// Emit nodes that will be selected as "test Op0,Op0", or something
8047 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
8048 SelectionDAG &DAG) const {
8049 DebugLoc dl = Op.getDebugLoc();
8051 // CF and OF aren't always set the way we want. Determine which
8052 // of these we need.
8053 bool NeedCF = false;
8054 bool NeedOF = false;
8057 case X86::COND_A: case X86::COND_AE:
8058 case X86::COND_B: case X86::COND_BE:
8061 case X86::COND_G: case X86::COND_GE:
8062 case X86::COND_L: case X86::COND_LE:
8063 case X86::COND_O: case X86::COND_NO:
8068 // See if we can use the EFLAGS value from the operand instead of
8069 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
8070 // we prove that the arithmetic won't overflow, we can't use OF or CF.
8071 if (Op.getResNo() != 0 || NeedOF || NeedCF)
8072 // Emit a CMP with 0, which is the TEST pattern.
8073 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
8074 DAG.getConstant(0, Op.getValueType()));
8076 unsigned Opcode = 0;
8077 unsigned NumOperands = 0;
8078 switch (Op.getNode()->getOpcode()) {
8080 // Due to an isel shortcoming, be conservative if this add is likely to be
8081 // selected as part of a load-modify-store instruction. When the root node
8082 // in a match is a store, isel doesn't know how to remap non-chain non-flag
8083 // uses of other nodes in the match, such as the ADD in this case. This
8084 // leads to the ADD being left around and reselected, with the result being
8085 // two adds in the output. Alas, even if none our users are stores, that
8086 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
8087 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
8088 // climbing the DAG back to the root, and it doesn't seem to be worth the
8090 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8091 UE = Op.getNode()->use_end(); UI != UE; ++UI)
8092 if (UI->getOpcode() != ISD::CopyToReg &&
8093 UI->getOpcode() != ISD::SETCC &&
8094 UI->getOpcode() != ISD::STORE)
8097 if (ConstantSDNode *C =
8098 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) {
8099 // An add of one will be selected as an INC.
8100 if (C->getAPIntValue() == 1) {
8101 Opcode = X86ISD::INC;
8106 // An add of negative one (subtract of one) will be selected as a DEC.
8107 if (C->getAPIntValue().isAllOnesValue()) {
8108 Opcode = X86ISD::DEC;
8114 // Otherwise use a regular EFLAGS-setting add.
8115 Opcode = X86ISD::ADD;
8119 // If the primary and result isn't used, don't bother using X86ISD::AND,
8120 // because a TEST instruction will be better.
8121 bool NonFlagUse = false;
8122 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8123 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
8125 unsigned UOpNo = UI.getOperandNo();
8126 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
8127 // Look pass truncate.
8128 UOpNo = User->use_begin().getOperandNo();
8129 User = *User->use_begin();
8132 if (User->getOpcode() != ISD::BRCOND &&
8133 User->getOpcode() != ISD::SETCC &&
8134 (User->getOpcode() != ISD::SELECT || UOpNo != 0)) {
8147 // Due to the ISEL shortcoming noted above, be conservative if this op is
8148 // likely to be selected as part of a load-modify-store instruction.
8149 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8150 UE = Op.getNode()->use_end(); UI != UE; ++UI)
8151 if (UI->getOpcode() == ISD::STORE)
8154 // Otherwise use a regular EFLAGS-setting instruction.
8155 switch (Op.getNode()->getOpcode()) {
8156 default: llvm_unreachable("unexpected operator!");
8157 case ISD::SUB: Opcode = X86ISD::SUB; break;
8158 case ISD::OR: Opcode = X86ISD::OR; break;
8159 case ISD::XOR: Opcode = X86ISD::XOR; break;
8160 case ISD::AND: Opcode = X86ISD::AND; break;
8172 return SDValue(Op.getNode(), 1);
8179 // Emit a CMP with 0, which is the TEST pattern.
8180 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
8181 DAG.getConstant(0, Op.getValueType()));
8183 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
8184 SmallVector<SDValue, 4> Ops;
8185 for (unsigned i = 0; i != NumOperands; ++i)
8186 Ops.push_back(Op.getOperand(i));
8188 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
8189 DAG.ReplaceAllUsesWith(Op, New);
8190 return SDValue(New.getNode(), 1);
8193 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
8195 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
8196 SelectionDAG &DAG) const {
8197 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
8198 if (C->getAPIntValue() == 0)
8199 return EmitTest(Op0, X86CC, DAG);
8201 DebugLoc dl = Op0.getDebugLoc();
8202 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
8205 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
8206 /// if it's possible.
8207 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
8208 DebugLoc dl, SelectionDAG &DAG) const {
8209 SDValue Op0 = And.getOperand(0);
8210 SDValue Op1 = And.getOperand(1);
8211 if (Op0.getOpcode() == ISD::TRUNCATE)
8212 Op0 = Op0.getOperand(0);
8213 if (Op1.getOpcode() == ISD::TRUNCATE)
8214 Op1 = Op1.getOperand(0);
8217 if (Op1.getOpcode() == ISD::SHL)
8218 std::swap(Op0, Op1);
8219 if (Op0.getOpcode() == ISD::SHL) {
8220 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
8221 if (And00C->getZExtValue() == 1) {
8222 // If we looked past a truncate, check that it's only truncating away
8224 unsigned BitWidth = Op0.getValueSizeInBits();
8225 unsigned AndBitWidth = And.getValueSizeInBits();
8226 if (BitWidth > AndBitWidth) {
8227 APInt Mask = APInt::getAllOnesValue(BitWidth), Zeros, Ones;
8228 DAG.ComputeMaskedBits(Op0, Mask, Zeros, Ones);
8229 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
8233 RHS = Op0.getOperand(1);
8235 } else if (Op1.getOpcode() == ISD::Constant) {
8236 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
8237 uint64_t AndRHSVal = AndRHS->getZExtValue();
8238 SDValue AndLHS = Op0;
8240 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
8241 LHS = AndLHS.getOperand(0);
8242 RHS = AndLHS.getOperand(1);
8245 // Use BT if the immediate can't be encoded in a TEST instruction.
8246 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
8248 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
8252 if (LHS.getNode()) {
8253 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
8254 // instruction. Since the shift amount is in-range-or-undefined, we know
8255 // that doing a bittest on the i32 value is ok. We extend to i32 because
8256 // the encoding for the i16 version is larger than the i32 version.
8257 // Also promote i16 to i32 for performance / code size reason.
8258 if (LHS.getValueType() == MVT::i8 ||
8259 LHS.getValueType() == MVT::i16)
8260 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
8262 // If the operand types disagree, extend the shift amount to match. Since
8263 // BT ignores high bits (like shifts) we can use anyextend.
8264 if (LHS.getValueType() != RHS.getValueType())
8265 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
8267 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
8268 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
8269 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8270 DAG.getConstant(Cond, MVT::i8), BT);
8276 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
8278 if (Op.getValueType().isVector()) return LowerVSETCC(Op, DAG);
8280 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
8281 SDValue Op0 = Op.getOperand(0);
8282 SDValue Op1 = Op.getOperand(1);
8283 DebugLoc dl = Op.getDebugLoc();
8284 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
8286 // Optimize to BT if possible.
8287 // Lower (X & (1 << N)) == 0 to BT(X, N).
8288 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
8289 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
8290 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
8291 Op1.getOpcode() == ISD::Constant &&
8292 cast<ConstantSDNode>(Op1)->isNullValue() &&
8293 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
8294 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
8295 if (NewSetCC.getNode())
8299 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
8301 if (Op1.getOpcode() == ISD::Constant &&
8302 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
8303 cast<ConstantSDNode>(Op1)->isNullValue()) &&
8304 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
8306 // If the input is a setcc, then reuse the input setcc or use a new one with
8307 // the inverted condition.
8308 if (Op0.getOpcode() == X86ISD::SETCC) {
8309 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
8310 bool Invert = (CC == ISD::SETNE) ^
8311 cast<ConstantSDNode>(Op1)->isNullValue();
8312 if (!Invert) return Op0;
8314 CCode = X86::GetOppositeBranchCondition(CCode);
8315 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8316 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1));
8320 bool isFP = Op1.getValueType().isFloatingPoint();
8321 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
8322 if (X86CC == X86::COND_INVALID)
8325 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG);
8326 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8327 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
8330 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
8331 // ones, and then concatenate the result back.
8332 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
8333 EVT VT = Op.getValueType();
8335 assert(VT.getSizeInBits() == 256 && Op.getOpcode() == ISD::SETCC &&
8336 "Unsupported value type for operation");
8338 int NumElems = VT.getVectorNumElements();
8339 DebugLoc dl = Op.getDebugLoc();
8340 SDValue CC = Op.getOperand(2);
8341 SDValue Idx0 = DAG.getConstant(0, MVT::i32);
8342 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32);
8344 // Extract the LHS vectors
8345 SDValue LHS = Op.getOperand(0);
8346 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl);
8347 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl);
8349 // Extract the RHS vectors
8350 SDValue RHS = Op.getOperand(1);
8351 SDValue RHS1 = Extract128BitVector(RHS, Idx0, DAG, dl);
8352 SDValue RHS2 = Extract128BitVector(RHS, Idx1, DAG, dl);
8354 // Issue the operation on the smaller types and concatenate the result back
8355 MVT EltVT = VT.getVectorElementType().getSimpleVT();
8356 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
8357 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
8358 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
8359 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
8363 SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const {
8365 SDValue Op0 = Op.getOperand(0);
8366 SDValue Op1 = Op.getOperand(1);
8367 SDValue CC = Op.getOperand(2);
8368 EVT VT = Op.getValueType();
8369 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
8370 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
8371 DebugLoc dl = Op.getDebugLoc();
8375 EVT EltVT = Op0.getValueType().getVectorElementType();
8376 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
8378 unsigned Opc = EltVT == MVT::f32 ? X86ISD::CMPPS : X86ISD::CMPPD;
8381 // SSE Condition code mapping:
8390 switch (SetCCOpcode) {
8393 case ISD::SETEQ: SSECC = 0; break;
8395 case ISD::SETGT: Swap = true; // Fallthrough
8397 case ISD::SETOLT: SSECC = 1; break;
8399 case ISD::SETGE: Swap = true; // Fallthrough
8401 case ISD::SETOLE: SSECC = 2; break;
8402 case ISD::SETUO: SSECC = 3; break;
8404 case ISD::SETNE: SSECC = 4; break;
8405 case ISD::SETULE: Swap = true;
8406 case ISD::SETUGE: SSECC = 5; break;
8407 case ISD::SETULT: Swap = true;
8408 case ISD::SETUGT: SSECC = 6; break;
8409 case ISD::SETO: SSECC = 7; break;
8412 std::swap(Op0, Op1);
8414 // In the two special cases we can't handle, emit two comparisons.
8416 if (SetCCOpcode == ISD::SETUEQ) {
8418 UNORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(3, MVT::i8));
8419 EQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(0, MVT::i8));
8420 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ);
8421 } else if (SetCCOpcode == ISD::SETONE) {
8423 ORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(7, MVT::i8));
8424 NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, MVT::i8));
8425 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ);
8427 llvm_unreachable("Illegal FP comparison");
8429 // Handle all other FP comparisons here.
8430 return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8));
8433 // Break 256-bit integer vector compare into smaller ones.
8434 if (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2())
8435 return Lower256IntVSETCC(Op, DAG);
8437 // We are handling one of the integer comparisons here. Since SSE only has
8438 // GT and EQ comparisons for integer, swapping operands and multiple
8439 // operations may be required for some comparisons.
8440 unsigned Opc = 0, EQOpc = 0, GTOpc = 0;
8441 bool Swap = false, Invert = false, FlipSigns = false;
8443 switch (VT.getVectorElementType().getSimpleVT().SimpleTy) {
8445 case MVT::i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break;
8446 case MVT::i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break;
8447 case MVT::i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break;
8448 case MVT::i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break;
8451 switch (SetCCOpcode) {
8453 case ISD::SETNE: Invert = true;
8454 case ISD::SETEQ: Opc = EQOpc; break;
8455 case ISD::SETLT: Swap = true;
8456 case ISD::SETGT: Opc = GTOpc; break;
8457 case ISD::SETGE: Swap = true;
8458 case ISD::SETLE: Opc = GTOpc; Invert = true; break;
8459 case ISD::SETULT: Swap = true;
8460 case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break;
8461 case ISD::SETUGE: Swap = true;
8462 case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break;
8465 std::swap(Op0, Op1);
8467 // Check that the operation in question is available (most are plain SSE2,
8468 // but PCMPGTQ and PCMPEQQ have different requirements).
8469 if (Opc == X86ISD::PCMPGTQ && !Subtarget->hasSSE42orAVX())
8471 if (Opc == X86ISD::PCMPEQQ && !Subtarget->hasSSE41orAVX())
8474 // Since SSE has no unsigned integer comparisons, we need to flip the sign
8475 // bits of the inputs before performing those operations.
8477 EVT EltVT = VT.getVectorElementType();
8478 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
8480 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
8481 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
8483 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
8484 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
8487 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
8489 // If the logical-not of the result is required, perform that now.
8491 Result = DAG.getNOT(dl, Result, VT);
8496 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
8497 static bool isX86LogicalCmp(SDValue Op) {
8498 unsigned Opc = Op.getNode()->getOpcode();
8499 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI)
8501 if (Op.getResNo() == 1 &&
8502 (Opc == X86ISD::ADD ||
8503 Opc == X86ISD::SUB ||
8504 Opc == X86ISD::ADC ||
8505 Opc == X86ISD::SBB ||
8506 Opc == X86ISD::SMUL ||
8507 Opc == X86ISD::UMUL ||
8508 Opc == X86ISD::INC ||
8509 Opc == X86ISD::DEC ||
8510 Opc == X86ISD::OR ||
8511 Opc == X86ISD::XOR ||
8512 Opc == X86ISD::AND))
8515 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
8521 static bool isZero(SDValue V) {
8522 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
8523 return C && C->isNullValue();
8526 static bool isAllOnes(SDValue V) {
8527 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
8528 return C && C->isAllOnesValue();
8531 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
8532 bool addTest = true;
8533 SDValue Cond = Op.getOperand(0);
8534 SDValue Op1 = Op.getOperand(1);
8535 SDValue Op2 = Op.getOperand(2);
8536 DebugLoc DL = Op.getDebugLoc();
8539 if (Cond.getOpcode() == ISD::SETCC) {
8540 SDValue NewCond = LowerSETCC(Cond, DAG);
8541 if (NewCond.getNode())
8545 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
8546 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
8547 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
8548 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
8549 if (Cond.getOpcode() == X86ISD::SETCC &&
8550 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
8551 isZero(Cond.getOperand(1).getOperand(1))) {
8552 SDValue Cmp = Cond.getOperand(1);
8554 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
8556 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
8557 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
8558 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
8560 SDValue CmpOp0 = Cmp.getOperand(0);
8561 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
8562 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
8564 SDValue Res = // Res = 0 or -1.
8565 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
8566 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
8568 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
8569 Res = DAG.getNOT(DL, Res, Res.getValueType());
8571 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
8572 if (N2C == 0 || !N2C->isNullValue())
8573 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
8578 // Look past (and (setcc_carry (cmp ...)), 1).
8579 if (Cond.getOpcode() == ISD::AND &&
8580 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
8581 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
8582 if (C && C->getAPIntValue() == 1)
8583 Cond = Cond.getOperand(0);
8586 // If condition flag is set by a X86ISD::CMP, then use it as the condition
8587 // setting operand in place of the X86ISD::SETCC.
8588 unsigned CondOpcode = Cond.getOpcode();
8589 if (CondOpcode == X86ISD::SETCC ||
8590 CondOpcode == X86ISD::SETCC_CARRY) {
8591 CC = Cond.getOperand(0);
8593 SDValue Cmp = Cond.getOperand(1);
8594 unsigned Opc = Cmp.getOpcode();
8595 EVT VT = Op.getValueType();
8597 bool IllegalFPCMov = false;
8598 if (VT.isFloatingPoint() && !VT.isVector() &&
8599 !isScalarFPTypeInSSEReg(VT)) // FPStack?
8600 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
8602 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
8603 Opc == X86ISD::BT) { // FIXME
8607 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
8608 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
8609 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
8610 Cond.getOperand(0).getValueType() != MVT::i8)) {
8611 SDValue LHS = Cond.getOperand(0);
8612 SDValue RHS = Cond.getOperand(1);
8616 switch (CondOpcode) {
8617 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
8618 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
8619 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
8620 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
8621 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
8622 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
8623 default: llvm_unreachable("unexpected overflowing operator");
8625 if (CondOpcode == ISD::UMULO)
8626 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
8629 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
8631 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
8633 if (CondOpcode == ISD::UMULO)
8634 Cond = X86Op.getValue(2);
8636 Cond = X86Op.getValue(1);
8638 CC = DAG.getConstant(X86Cond, MVT::i8);
8643 // Look pass the truncate.
8644 if (Cond.getOpcode() == ISD::TRUNCATE)
8645 Cond = Cond.getOperand(0);
8647 // We know the result of AND is compared against zero. Try to match
8649 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
8650 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
8651 if (NewSetCC.getNode()) {
8652 CC = NewSetCC.getOperand(0);
8653 Cond = NewSetCC.getOperand(1);
8660 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8661 Cond = EmitTest(Cond, X86::COND_NE, DAG);
8664 // a < b ? -1 : 0 -> RES = ~setcc_carry
8665 // a < b ? 0 : -1 -> RES = setcc_carry
8666 // a >= b ? -1 : 0 -> RES = setcc_carry
8667 // a >= b ? 0 : -1 -> RES = ~setcc_carry
8668 if (Cond.getOpcode() == X86ISD::CMP) {
8669 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
8671 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
8672 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
8673 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
8674 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
8675 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
8676 return DAG.getNOT(DL, Res, Res.getValueType());
8681 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
8682 // condition is true.
8683 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
8684 SDValue Ops[] = { Op2, Op1, CC, Cond };
8685 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops));
8688 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
8689 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
8690 // from the AND / OR.
8691 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
8692 Opc = Op.getOpcode();
8693 if (Opc != ISD::OR && Opc != ISD::AND)
8695 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
8696 Op.getOperand(0).hasOneUse() &&
8697 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
8698 Op.getOperand(1).hasOneUse());
8701 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
8702 // 1 and that the SETCC node has a single use.
8703 static bool isXor1OfSetCC(SDValue Op) {
8704 if (Op.getOpcode() != ISD::XOR)
8706 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
8707 if (N1C && N1C->getAPIntValue() == 1) {
8708 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
8709 Op.getOperand(0).hasOneUse();
8714 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
8715 bool addTest = true;
8716 SDValue Chain = Op.getOperand(0);
8717 SDValue Cond = Op.getOperand(1);
8718 SDValue Dest = Op.getOperand(2);
8719 DebugLoc dl = Op.getDebugLoc();
8721 bool Inverted = false;
8723 if (Cond.getOpcode() == ISD::SETCC) {
8724 // Check for setcc([su]{add,sub,mul}o == 0).
8725 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
8726 isa<ConstantSDNode>(Cond.getOperand(1)) &&
8727 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
8728 Cond.getOperand(0).getResNo() == 1 &&
8729 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
8730 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
8731 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
8732 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
8733 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
8734 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
8736 Cond = Cond.getOperand(0);
8738 SDValue NewCond = LowerSETCC(Cond, DAG);
8739 if (NewCond.getNode())
8744 // FIXME: LowerXALUO doesn't handle these!!
8745 else if (Cond.getOpcode() == X86ISD::ADD ||
8746 Cond.getOpcode() == X86ISD::SUB ||
8747 Cond.getOpcode() == X86ISD::SMUL ||
8748 Cond.getOpcode() == X86ISD::UMUL)
8749 Cond = LowerXALUO(Cond, DAG);
8752 // Look pass (and (setcc_carry (cmp ...)), 1).
8753 if (Cond.getOpcode() == ISD::AND &&
8754 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
8755 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
8756 if (C && C->getAPIntValue() == 1)
8757 Cond = Cond.getOperand(0);
8760 // If condition flag is set by a X86ISD::CMP, then use it as the condition
8761 // setting operand in place of the X86ISD::SETCC.
8762 unsigned CondOpcode = Cond.getOpcode();
8763 if (CondOpcode == X86ISD::SETCC ||
8764 CondOpcode == X86ISD::SETCC_CARRY) {
8765 CC = Cond.getOperand(0);
8767 SDValue Cmp = Cond.getOperand(1);
8768 unsigned Opc = Cmp.getOpcode();
8769 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
8770 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
8774 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
8778 // These can only come from an arithmetic instruction with overflow,
8779 // e.g. SADDO, UADDO.
8780 Cond = Cond.getNode()->getOperand(1);
8786 CondOpcode = Cond.getOpcode();
8787 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
8788 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
8789 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
8790 Cond.getOperand(0).getValueType() != MVT::i8)) {
8791 SDValue LHS = Cond.getOperand(0);
8792 SDValue RHS = Cond.getOperand(1);
8796 switch (CondOpcode) {
8797 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
8798 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
8799 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
8800 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
8801 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
8802 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
8803 default: llvm_unreachable("unexpected overflowing operator");
8806 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
8807 if (CondOpcode == ISD::UMULO)
8808 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
8811 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
8813 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
8815 if (CondOpcode == ISD::UMULO)
8816 Cond = X86Op.getValue(2);
8818 Cond = X86Op.getValue(1);
8820 CC = DAG.getConstant(X86Cond, MVT::i8);
8824 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
8825 SDValue Cmp = Cond.getOperand(0).getOperand(1);
8826 if (CondOpc == ISD::OR) {
8827 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
8828 // two branches instead of an explicit OR instruction with a
8830 if (Cmp == Cond.getOperand(1).getOperand(1) &&
8831 isX86LogicalCmp(Cmp)) {
8832 CC = Cond.getOperand(0).getOperand(0);
8833 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8834 Chain, Dest, CC, Cmp);
8835 CC = Cond.getOperand(1).getOperand(0);
8839 } else { // ISD::AND
8840 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
8841 // two branches instead of an explicit AND instruction with a
8842 // separate test. However, we only do this if this block doesn't
8843 // have a fall-through edge, because this requires an explicit
8844 // jmp when the condition is false.
8845 if (Cmp == Cond.getOperand(1).getOperand(1) &&
8846 isX86LogicalCmp(Cmp) &&
8847 Op.getNode()->hasOneUse()) {
8848 X86::CondCode CCode =
8849 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
8850 CCode = X86::GetOppositeBranchCondition(CCode);
8851 CC = DAG.getConstant(CCode, MVT::i8);
8852 SDNode *User = *Op.getNode()->use_begin();
8853 // Look for an unconditional branch following this conditional branch.
8854 // We need this because we need to reverse the successors in order
8855 // to implement FCMP_OEQ.
8856 if (User->getOpcode() == ISD::BR) {
8857 SDValue FalseBB = User->getOperand(1);
8859 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
8860 assert(NewBR == User);
8864 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8865 Chain, Dest, CC, Cmp);
8866 X86::CondCode CCode =
8867 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
8868 CCode = X86::GetOppositeBranchCondition(CCode);
8869 CC = DAG.getConstant(CCode, MVT::i8);
8875 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
8876 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
8877 // It should be transformed during dag combiner except when the condition
8878 // is set by a arithmetics with overflow node.
8879 X86::CondCode CCode =
8880 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
8881 CCode = X86::GetOppositeBranchCondition(CCode);
8882 CC = DAG.getConstant(CCode, MVT::i8);
8883 Cond = Cond.getOperand(0).getOperand(1);
8885 } else if (Cond.getOpcode() == ISD::SETCC &&
8886 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
8887 // For FCMP_OEQ, we can emit
8888 // two branches instead of an explicit AND instruction with a
8889 // separate test. However, we only do this if this block doesn't
8890 // have a fall-through edge, because this requires an explicit
8891 // jmp when the condition is false.
8892 if (Op.getNode()->hasOneUse()) {
8893 SDNode *User = *Op.getNode()->use_begin();
8894 // Look for an unconditional branch following this conditional branch.
8895 // We need this because we need to reverse the successors in order
8896 // to implement FCMP_OEQ.
8897 if (User->getOpcode() == ISD::BR) {
8898 SDValue FalseBB = User->getOperand(1);
8900 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
8901 assert(NewBR == User);
8905 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
8906 Cond.getOperand(0), Cond.getOperand(1));
8907 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8908 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8909 Chain, Dest, CC, Cmp);
8910 CC = DAG.getConstant(X86::COND_P, MVT::i8);
8915 } else if (Cond.getOpcode() == ISD::SETCC &&
8916 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
8917 // For FCMP_UNE, we can emit
8918 // two branches instead of an explicit AND instruction with a
8919 // separate test. However, we only do this if this block doesn't
8920 // have a fall-through edge, because this requires an explicit
8921 // jmp when the condition is false.
8922 if (Op.getNode()->hasOneUse()) {
8923 SDNode *User = *Op.getNode()->use_begin();
8924 // Look for an unconditional branch following this conditional branch.
8925 // We need this because we need to reverse the successors in order
8926 // to implement FCMP_UNE.
8927 if (User->getOpcode() == ISD::BR) {
8928 SDValue FalseBB = User->getOperand(1);
8930 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
8931 assert(NewBR == User);
8934 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
8935 Cond.getOperand(0), Cond.getOperand(1));
8936 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8937 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8938 Chain, Dest, CC, Cmp);
8939 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
8949 // Look pass the truncate.
8950 if (Cond.getOpcode() == ISD::TRUNCATE)
8951 Cond = Cond.getOperand(0);
8953 // We know the result of AND is compared against zero. Try to match
8955 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
8956 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
8957 if (NewSetCC.getNode()) {
8958 CC = NewSetCC.getOperand(0);
8959 Cond = NewSetCC.getOperand(1);
8966 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8967 Cond = EmitTest(Cond, X86::COND_NE, DAG);
8969 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8970 Chain, Dest, CC, Cond);
8974 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
8975 // Calls to _alloca is needed to probe the stack when allocating more than 4k
8976 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
8977 // that the guard pages used by the OS virtual memory manager are allocated in
8978 // correct sequence.
8980 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
8981 SelectionDAG &DAG) const {
8982 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows() ||
8983 getTargetMachine().Options.EnableSegmentedStacks) &&
8984 "This should be used only on Windows targets or when segmented stacks "
8986 assert(!Subtarget->isTargetEnvMacho() && "Not implemented");
8987 DebugLoc dl = Op.getDebugLoc();
8990 SDValue Chain = Op.getOperand(0);
8991 SDValue Size = Op.getOperand(1);
8992 // FIXME: Ensure alignment here
8994 bool Is64Bit = Subtarget->is64Bit();
8995 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32;
8997 if (getTargetMachine().Options.EnableSegmentedStacks) {
8998 MachineFunction &MF = DAG.getMachineFunction();
8999 MachineRegisterInfo &MRI = MF.getRegInfo();
9002 // The 64 bit implementation of segmented stacks needs to clobber both r10
9003 // r11. This makes it impossible to use it along with nested parameters.
9004 const Function *F = MF.getFunction();
9006 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
9008 if (I->hasNestAttr())
9009 report_fatal_error("Cannot use segmented stacks with functions that "
9010 "have nested arguments.");
9013 const TargetRegisterClass *AddrRegClass =
9014 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32);
9015 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
9016 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
9017 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
9018 DAG.getRegister(Vreg, SPTy));
9019 SDValue Ops1[2] = { Value, Chain };
9020 return DAG.getMergeValues(Ops1, 2, dl);
9023 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
9025 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
9026 Flag = Chain.getValue(1);
9027 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
9029 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
9030 Flag = Chain.getValue(1);
9032 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1);
9034 SDValue Ops1[2] = { Chain.getValue(0), Chain };
9035 return DAG.getMergeValues(Ops1, 2, dl);
9039 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
9040 MachineFunction &MF = DAG.getMachineFunction();
9041 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
9043 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
9044 DebugLoc DL = Op.getDebugLoc();
9046 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
9047 // vastart just stores the address of the VarArgsFrameIndex slot into the
9048 // memory location argument.
9049 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
9051 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
9052 MachinePointerInfo(SV), false, false, 0);
9056 // gp_offset (0 - 6 * 8)
9057 // fp_offset (48 - 48 + 8 * 16)
9058 // overflow_arg_area (point to parameters coming in memory).
9060 SmallVector<SDValue, 8> MemOps;
9061 SDValue FIN = Op.getOperand(1);
9063 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
9064 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
9066 FIN, MachinePointerInfo(SV), false, false, 0);
9067 MemOps.push_back(Store);
9070 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9071 FIN, DAG.getIntPtrConstant(4));
9072 Store = DAG.getStore(Op.getOperand(0), DL,
9073 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
9075 FIN, MachinePointerInfo(SV, 4), false, false, 0);
9076 MemOps.push_back(Store);
9078 // Store ptr to overflow_arg_area
9079 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9080 FIN, DAG.getIntPtrConstant(4));
9081 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
9083 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
9084 MachinePointerInfo(SV, 8),
9086 MemOps.push_back(Store);
9088 // Store ptr to reg_save_area.
9089 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9090 FIN, DAG.getIntPtrConstant(8));
9091 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
9093 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
9094 MachinePointerInfo(SV, 16), false, false, 0);
9095 MemOps.push_back(Store);
9096 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
9097 &MemOps[0], MemOps.size());
9100 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
9101 assert(Subtarget->is64Bit() &&
9102 "LowerVAARG only handles 64-bit va_arg!");
9103 assert((Subtarget->isTargetLinux() ||
9104 Subtarget->isTargetDarwin()) &&
9105 "Unhandled target in LowerVAARG");
9106 assert(Op.getNode()->getNumOperands() == 4);
9107 SDValue Chain = Op.getOperand(0);
9108 SDValue SrcPtr = Op.getOperand(1);
9109 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
9110 unsigned Align = Op.getConstantOperandVal(3);
9111 DebugLoc dl = Op.getDebugLoc();
9113 EVT ArgVT = Op.getNode()->getValueType(0);
9114 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
9115 uint32_t ArgSize = getTargetData()->getTypeAllocSize(ArgTy);
9118 // Decide which area this value should be read from.
9119 // TODO: Implement the AMD64 ABI in its entirety. This simple
9120 // selection mechanism works only for the basic types.
9121 if (ArgVT == MVT::f80) {
9122 llvm_unreachable("va_arg for f80 not yet implemented");
9123 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
9124 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
9125 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
9126 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
9128 llvm_unreachable("Unhandled argument type in LowerVAARG");
9132 // Sanity Check: Make sure using fp_offset makes sense.
9133 assert(!getTargetMachine().Options.UseSoftFloat &&
9134 !(DAG.getMachineFunction()
9135 .getFunction()->hasFnAttr(Attribute::NoImplicitFloat)) &&
9136 Subtarget->hasXMM());
9139 // Insert VAARG_64 node into the DAG
9140 // VAARG_64 returns two values: Variable Argument Address, Chain
9141 SmallVector<SDValue, 11> InstOps;
9142 InstOps.push_back(Chain);
9143 InstOps.push_back(SrcPtr);
9144 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
9145 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
9146 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
9147 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
9148 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
9149 VTs, &InstOps[0], InstOps.size(),
9151 MachinePointerInfo(SV),
9156 Chain = VAARG.getValue(1);
9158 // Load the next argument and return it
9159 return DAG.getLoad(ArgVT, dl,
9162 MachinePointerInfo(),
9163 false, false, false, 0);
9166 SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const {
9167 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
9168 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
9169 SDValue Chain = Op.getOperand(0);
9170 SDValue DstPtr = Op.getOperand(1);
9171 SDValue SrcPtr = Op.getOperand(2);
9172 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
9173 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
9174 DebugLoc DL = Op.getDebugLoc();
9176 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
9177 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
9179 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
9183 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const {
9184 DebugLoc dl = Op.getDebugLoc();
9185 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9187 default: return SDValue(); // Don't custom lower most intrinsics.
9188 // Comparison intrinsics.
9189 case Intrinsic::x86_sse_comieq_ss:
9190 case Intrinsic::x86_sse_comilt_ss:
9191 case Intrinsic::x86_sse_comile_ss:
9192 case Intrinsic::x86_sse_comigt_ss:
9193 case Intrinsic::x86_sse_comige_ss:
9194 case Intrinsic::x86_sse_comineq_ss:
9195 case Intrinsic::x86_sse_ucomieq_ss:
9196 case Intrinsic::x86_sse_ucomilt_ss:
9197 case Intrinsic::x86_sse_ucomile_ss:
9198 case Intrinsic::x86_sse_ucomigt_ss:
9199 case Intrinsic::x86_sse_ucomige_ss:
9200 case Intrinsic::x86_sse_ucomineq_ss:
9201 case Intrinsic::x86_sse2_comieq_sd:
9202 case Intrinsic::x86_sse2_comilt_sd:
9203 case Intrinsic::x86_sse2_comile_sd:
9204 case Intrinsic::x86_sse2_comigt_sd:
9205 case Intrinsic::x86_sse2_comige_sd:
9206 case Intrinsic::x86_sse2_comineq_sd:
9207 case Intrinsic::x86_sse2_ucomieq_sd:
9208 case Intrinsic::x86_sse2_ucomilt_sd:
9209 case Intrinsic::x86_sse2_ucomile_sd:
9210 case Intrinsic::x86_sse2_ucomigt_sd:
9211 case Intrinsic::x86_sse2_ucomige_sd:
9212 case Intrinsic::x86_sse2_ucomineq_sd: {
9214 ISD::CondCode CC = ISD::SETCC_INVALID;
9217 case Intrinsic::x86_sse_comieq_ss:
9218 case Intrinsic::x86_sse2_comieq_sd:
9222 case Intrinsic::x86_sse_comilt_ss:
9223 case Intrinsic::x86_sse2_comilt_sd:
9227 case Intrinsic::x86_sse_comile_ss:
9228 case Intrinsic::x86_sse2_comile_sd:
9232 case Intrinsic::x86_sse_comigt_ss:
9233 case Intrinsic::x86_sse2_comigt_sd:
9237 case Intrinsic::x86_sse_comige_ss:
9238 case Intrinsic::x86_sse2_comige_sd:
9242 case Intrinsic::x86_sse_comineq_ss:
9243 case Intrinsic::x86_sse2_comineq_sd:
9247 case Intrinsic::x86_sse_ucomieq_ss:
9248 case Intrinsic::x86_sse2_ucomieq_sd:
9249 Opc = X86ISD::UCOMI;
9252 case Intrinsic::x86_sse_ucomilt_ss:
9253 case Intrinsic::x86_sse2_ucomilt_sd:
9254 Opc = X86ISD::UCOMI;
9257 case Intrinsic::x86_sse_ucomile_ss:
9258 case Intrinsic::x86_sse2_ucomile_sd:
9259 Opc = X86ISD::UCOMI;
9262 case Intrinsic::x86_sse_ucomigt_ss:
9263 case Intrinsic::x86_sse2_ucomigt_sd:
9264 Opc = X86ISD::UCOMI;
9267 case Intrinsic::x86_sse_ucomige_ss:
9268 case Intrinsic::x86_sse2_ucomige_sd:
9269 Opc = X86ISD::UCOMI;
9272 case Intrinsic::x86_sse_ucomineq_ss:
9273 case Intrinsic::x86_sse2_ucomineq_sd:
9274 Opc = X86ISD::UCOMI;
9279 SDValue LHS = Op.getOperand(1);
9280 SDValue RHS = Op.getOperand(2);
9281 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
9282 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
9283 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
9284 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9285 DAG.getConstant(X86CC, MVT::i8), Cond);
9286 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
9288 // Arithmetic intrinsics.
9289 case Intrinsic::x86_sse3_hadd_ps:
9290 case Intrinsic::x86_sse3_hadd_pd:
9291 case Intrinsic::x86_avx_hadd_ps_256:
9292 case Intrinsic::x86_avx_hadd_pd_256:
9293 return DAG.getNode(X86ISD::FHADD, dl, Op.getValueType(),
9294 Op.getOperand(1), Op.getOperand(2));
9295 case Intrinsic::x86_sse3_hsub_ps:
9296 case Intrinsic::x86_sse3_hsub_pd:
9297 case Intrinsic::x86_avx_hsub_ps_256:
9298 case Intrinsic::x86_avx_hsub_pd_256:
9299 return DAG.getNode(X86ISD::FHSUB, dl, Op.getValueType(),
9300 Op.getOperand(1), Op.getOperand(2));
9301 case Intrinsic::x86_avx2_psllv_d:
9302 case Intrinsic::x86_avx2_psllv_q:
9303 case Intrinsic::x86_avx2_psllv_d_256:
9304 case Intrinsic::x86_avx2_psllv_q_256:
9305 return DAG.getNode(ISD::SHL, dl, Op.getValueType(),
9306 Op.getOperand(1), Op.getOperand(2));
9307 case Intrinsic::x86_avx2_psrlv_d:
9308 case Intrinsic::x86_avx2_psrlv_q:
9309 case Intrinsic::x86_avx2_psrlv_d_256:
9310 case Intrinsic::x86_avx2_psrlv_q_256:
9311 return DAG.getNode(ISD::SRL, dl, Op.getValueType(),
9312 Op.getOperand(1), Op.getOperand(2));
9313 case Intrinsic::x86_avx2_psrav_d:
9314 case Intrinsic::x86_avx2_psrav_d_256:
9315 return DAG.getNode(ISD::SRA, dl, Op.getValueType(),
9316 Op.getOperand(1), Op.getOperand(2));
9318 // ptest and testp intrinsics. The intrinsic these come from are designed to
9319 // return an integer value, not just an instruction so lower it to the ptest
9320 // or testp pattern and a setcc for the result.
9321 case Intrinsic::x86_sse41_ptestz:
9322 case Intrinsic::x86_sse41_ptestc:
9323 case Intrinsic::x86_sse41_ptestnzc:
9324 case Intrinsic::x86_avx_ptestz_256:
9325 case Intrinsic::x86_avx_ptestc_256:
9326 case Intrinsic::x86_avx_ptestnzc_256:
9327 case Intrinsic::x86_avx_vtestz_ps:
9328 case Intrinsic::x86_avx_vtestc_ps:
9329 case Intrinsic::x86_avx_vtestnzc_ps:
9330 case Intrinsic::x86_avx_vtestz_pd:
9331 case Intrinsic::x86_avx_vtestc_pd:
9332 case Intrinsic::x86_avx_vtestnzc_pd:
9333 case Intrinsic::x86_avx_vtestz_ps_256:
9334 case Intrinsic::x86_avx_vtestc_ps_256:
9335 case Intrinsic::x86_avx_vtestnzc_ps_256:
9336 case Intrinsic::x86_avx_vtestz_pd_256:
9337 case Intrinsic::x86_avx_vtestc_pd_256:
9338 case Intrinsic::x86_avx_vtestnzc_pd_256: {
9339 bool IsTestPacked = false;
9342 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
9343 case Intrinsic::x86_avx_vtestz_ps:
9344 case Intrinsic::x86_avx_vtestz_pd:
9345 case Intrinsic::x86_avx_vtestz_ps_256:
9346 case Intrinsic::x86_avx_vtestz_pd_256:
9347 IsTestPacked = true; // Fallthrough
9348 case Intrinsic::x86_sse41_ptestz:
9349 case Intrinsic::x86_avx_ptestz_256:
9351 X86CC = X86::COND_E;
9353 case Intrinsic::x86_avx_vtestc_ps:
9354 case Intrinsic::x86_avx_vtestc_pd:
9355 case Intrinsic::x86_avx_vtestc_ps_256:
9356 case Intrinsic::x86_avx_vtestc_pd_256:
9357 IsTestPacked = true; // Fallthrough
9358 case Intrinsic::x86_sse41_ptestc:
9359 case Intrinsic::x86_avx_ptestc_256:
9361 X86CC = X86::COND_B;
9363 case Intrinsic::x86_avx_vtestnzc_ps:
9364 case Intrinsic::x86_avx_vtestnzc_pd:
9365 case Intrinsic::x86_avx_vtestnzc_ps_256:
9366 case Intrinsic::x86_avx_vtestnzc_pd_256:
9367 IsTestPacked = true; // Fallthrough
9368 case Intrinsic::x86_sse41_ptestnzc:
9369 case Intrinsic::x86_avx_ptestnzc_256:
9371 X86CC = X86::COND_A;
9375 SDValue LHS = Op.getOperand(1);
9376 SDValue RHS = Op.getOperand(2);
9377 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
9378 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
9379 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
9380 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
9381 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
9384 // Fix vector shift instructions where the last operand is a non-immediate
9386 case Intrinsic::x86_avx2_pslli_w:
9387 case Intrinsic::x86_avx2_pslli_d:
9388 case Intrinsic::x86_avx2_pslli_q:
9389 case Intrinsic::x86_avx2_psrli_w:
9390 case Intrinsic::x86_avx2_psrli_d:
9391 case Intrinsic::x86_avx2_psrli_q:
9392 case Intrinsic::x86_avx2_psrai_w:
9393 case Intrinsic::x86_avx2_psrai_d:
9394 case Intrinsic::x86_sse2_pslli_w:
9395 case Intrinsic::x86_sse2_pslli_d:
9396 case Intrinsic::x86_sse2_pslli_q:
9397 case Intrinsic::x86_sse2_psrli_w:
9398 case Intrinsic::x86_sse2_psrli_d:
9399 case Intrinsic::x86_sse2_psrli_q:
9400 case Intrinsic::x86_sse2_psrai_w:
9401 case Intrinsic::x86_sse2_psrai_d:
9402 case Intrinsic::x86_mmx_pslli_w:
9403 case Intrinsic::x86_mmx_pslli_d:
9404 case Intrinsic::x86_mmx_pslli_q:
9405 case Intrinsic::x86_mmx_psrli_w:
9406 case Intrinsic::x86_mmx_psrli_d:
9407 case Intrinsic::x86_mmx_psrli_q:
9408 case Intrinsic::x86_mmx_psrai_w:
9409 case Intrinsic::x86_mmx_psrai_d: {
9410 SDValue ShAmt = Op.getOperand(2);
9411 if (isa<ConstantSDNode>(ShAmt))
9414 unsigned NewIntNo = 0;
9415 EVT ShAmtVT = MVT::v4i32;
9417 case Intrinsic::x86_sse2_pslli_w:
9418 NewIntNo = Intrinsic::x86_sse2_psll_w;
9420 case Intrinsic::x86_sse2_pslli_d:
9421 NewIntNo = Intrinsic::x86_sse2_psll_d;
9423 case Intrinsic::x86_sse2_pslli_q:
9424 NewIntNo = Intrinsic::x86_sse2_psll_q;
9426 case Intrinsic::x86_sse2_psrli_w:
9427 NewIntNo = Intrinsic::x86_sse2_psrl_w;
9429 case Intrinsic::x86_sse2_psrli_d:
9430 NewIntNo = Intrinsic::x86_sse2_psrl_d;
9432 case Intrinsic::x86_sse2_psrli_q:
9433 NewIntNo = Intrinsic::x86_sse2_psrl_q;
9435 case Intrinsic::x86_sse2_psrai_w:
9436 NewIntNo = Intrinsic::x86_sse2_psra_w;
9438 case Intrinsic::x86_sse2_psrai_d:
9439 NewIntNo = Intrinsic::x86_sse2_psra_d;
9441 case Intrinsic::x86_avx2_pslli_w:
9442 NewIntNo = Intrinsic::x86_avx2_psll_w;
9444 case Intrinsic::x86_avx2_pslli_d:
9445 NewIntNo = Intrinsic::x86_avx2_psll_d;
9447 case Intrinsic::x86_avx2_pslli_q:
9448 NewIntNo = Intrinsic::x86_avx2_psll_q;
9450 case Intrinsic::x86_avx2_psrli_w:
9451 NewIntNo = Intrinsic::x86_avx2_psrl_w;
9453 case Intrinsic::x86_avx2_psrli_d:
9454 NewIntNo = Intrinsic::x86_avx2_psrl_d;
9456 case Intrinsic::x86_avx2_psrli_q:
9457 NewIntNo = Intrinsic::x86_avx2_psrl_q;
9459 case Intrinsic::x86_avx2_psrai_w:
9460 NewIntNo = Intrinsic::x86_avx2_psra_w;
9462 case Intrinsic::x86_avx2_psrai_d:
9463 NewIntNo = Intrinsic::x86_avx2_psra_d;
9466 ShAmtVT = MVT::v2i32;
9468 case Intrinsic::x86_mmx_pslli_w:
9469 NewIntNo = Intrinsic::x86_mmx_psll_w;
9471 case Intrinsic::x86_mmx_pslli_d:
9472 NewIntNo = Intrinsic::x86_mmx_psll_d;
9474 case Intrinsic::x86_mmx_pslli_q:
9475 NewIntNo = Intrinsic::x86_mmx_psll_q;
9477 case Intrinsic::x86_mmx_psrli_w:
9478 NewIntNo = Intrinsic::x86_mmx_psrl_w;
9480 case Intrinsic::x86_mmx_psrli_d:
9481 NewIntNo = Intrinsic::x86_mmx_psrl_d;
9483 case Intrinsic::x86_mmx_psrli_q:
9484 NewIntNo = Intrinsic::x86_mmx_psrl_q;
9486 case Intrinsic::x86_mmx_psrai_w:
9487 NewIntNo = Intrinsic::x86_mmx_psra_w;
9489 case Intrinsic::x86_mmx_psrai_d:
9490 NewIntNo = Intrinsic::x86_mmx_psra_d;
9492 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
9498 // The vector shift intrinsics with scalars uses 32b shift amounts but
9499 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
9503 ShOps[1] = DAG.getConstant(0, MVT::i32);
9504 if (ShAmtVT == MVT::v4i32) {
9505 ShOps[2] = DAG.getUNDEF(MVT::i32);
9506 ShOps[3] = DAG.getUNDEF(MVT::i32);
9507 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 4);
9509 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2);
9510 // FIXME this must be lowered to get rid of the invalid type.
9513 EVT VT = Op.getValueType();
9514 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt);
9515 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9516 DAG.getConstant(NewIntNo, MVT::i32),
9517 Op.getOperand(1), ShAmt);
9522 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
9523 SelectionDAG &DAG) const {
9524 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
9525 MFI->setReturnAddressIsTaken(true);
9527 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9528 DebugLoc dl = Op.getDebugLoc();
9531 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
9533 DAG.getConstant(TD->getPointerSize(),
9534 Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
9535 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9536 DAG.getNode(ISD::ADD, dl, getPointerTy(),
9538 MachinePointerInfo(), false, false, false, 0);
9541 // Just load the return address.
9542 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
9543 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9544 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
9547 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
9548 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
9549 MFI->setFrameAddressIsTaken(true);
9551 EVT VT = Op.getValueType();
9552 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
9553 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9554 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
9555 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
9557 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
9558 MachinePointerInfo(),
9559 false, false, false, 0);
9563 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
9564 SelectionDAG &DAG) const {
9565 return DAG.getIntPtrConstant(2*TD->getPointerSize());
9568 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
9569 MachineFunction &MF = DAG.getMachineFunction();
9570 SDValue Chain = Op.getOperand(0);
9571 SDValue Offset = Op.getOperand(1);
9572 SDValue Handler = Op.getOperand(2);
9573 DebugLoc dl = Op.getDebugLoc();
9575 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
9576 Subtarget->is64Bit() ? X86::RBP : X86::EBP,
9578 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
9580 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Frame,
9581 DAG.getIntPtrConstant(TD->getPointerSize()));
9582 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
9583 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
9585 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
9586 MF.getRegInfo().addLiveOut(StoreAddrReg);
9588 return DAG.getNode(X86ISD::EH_RETURN, dl,
9590 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
9593 SDValue X86TargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
9594 SelectionDAG &DAG) const {
9595 return Op.getOperand(0);
9598 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
9599 SelectionDAG &DAG) const {
9600 SDValue Root = Op.getOperand(0);
9601 SDValue Trmp = Op.getOperand(1); // trampoline
9602 SDValue FPtr = Op.getOperand(2); // nested function
9603 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
9604 DebugLoc dl = Op.getDebugLoc();
9606 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
9608 if (Subtarget->is64Bit()) {
9609 SDValue OutChains[6];
9611 // Large code-model.
9612 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
9613 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
9615 const unsigned char N86R10 = X86_MC::getX86RegNum(X86::R10);
9616 const unsigned char N86R11 = X86_MC::getX86RegNum(X86::R11);
9618 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
9620 // Load the pointer to the nested function into R11.
9621 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
9622 SDValue Addr = Trmp;
9623 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9624 Addr, MachinePointerInfo(TrmpAddr),
9627 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9628 DAG.getConstant(2, MVT::i64));
9629 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
9630 MachinePointerInfo(TrmpAddr, 2),
9633 // Load the 'nest' parameter value into R10.
9634 // R10 is specified in X86CallingConv.td
9635 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
9636 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9637 DAG.getConstant(10, MVT::i64));
9638 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9639 Addr, MachinePointerInfo(TrmpAddr, 10),
9642 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9643 DAG.getConstant(12, MVT::i64));
9644 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
9645 MachinePointerInfo(TrmpAddr, 12),
9648 // Jump to the nested function.
9649 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
9650 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9651 DAG.getConstant(20, MVT::i64));
9652 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9653 Addr, MachinePointerInfo(TrmpAddr, 20),
9656 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
9657 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9658 DAG.getConstant(22, MVT::i64));
9659 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
9660 MachinePointerInfo(TrmpAddr, 22),
9663 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6);
9665 const Function *Func =
9666 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
9667 CallingConv::ID CC = Func->getCallingConv();
9672 llvm_unreachable("Unsupported calling convention");
9673 case CallingConv::C:
9674 case CallingConv::X86_StdCall: {
9675 // Pass 'nest' parameter in ECX.
9676 // Must be kept in sync with X86CallingConv.td
9679 // Check that ECX wasn't needed by an 'inreg' parameter.
9680 FunctionType *FTy = Func->getFunctionType();
9681 const AttrListPtr &Attrs = Func->getAttributes();
9683 if (!Attrs.isEmpty() && !Func->isVarArg()) {
9684 unsigned InRegCount = 0;
9687 for (FunctionType::param_iterator I = FTy->param_begin(),
9688 E = FTy->param_end(); I != E; ++I, ++Idx)
9689 if (Attrs.paramHasAttr(Idx, Attribute::InReg))
9690 // FIXME: should only count parameters that are lowered to integers.
9691 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
9693 if (InRegCount > 2) {
9694 report_fatal_error("Nest register in use - reduce number of inreg"
9700 case CallingConv::X86_FastCall:
9701 case CallingConv::X86_ThisCall:
9702 case CallingConv::Fast:
9703 // Pass 'nest' parameter in EAX.
9704 // Must be kept in sync with X86CallingConv.td
9709 SDValue OutChains[4];
9712 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9713 DAG.getConstant(10, MVT::i32));
9714 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
9716 // This is storing the opcode for MOV32ri.
9717 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
9718 const unsigned char N86Reg = X86_MC::getX86RegNum(NestReg);
9719 OutChains[0] = DAG.getStore(Root, dl,
9720 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
9721 Trmp, MachinePointerInfo(TrmpAddr),
9724 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9725 DAG.getConstant(1, MVT::i32));
9726 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
9727 MachinePointerInfo(TrmpAddr, 1),
9730 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
9731 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9732 DAG.getConstant(5, MVT::i32));
9733 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
9734 MachinePointerInfo(TrmpAddr, 5),
9737 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9738 DAG.getConstant(6, MVT::i32));
9739 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
9740 MachinePointerInfo(TrmpAddr, 6),
9743 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4);
9747 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
9748 SelectionDAG &DAG) const {
9750 The rounding mode is in bits 11:10 of FPSR, and has the following
9757 FLT_ROUNDS, on the other hand, expects the following:
9764 To perform the conversion, we do:
9765 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
9768 MachineFunction &MF = DAG.getMachineFunction();
9769 const TargetMachine &TM = MF.getTarget();
9770 const TargetFrameLowering &TFI = *TM.getFrameLowering();
9771 unsigned StackAlignment = TFI.getStackAlignment();
9772 EVT VT = Op.getValueType();
9773 DebugLoc DL = Op.getDebugLoc();
9775 // Save FP Control Word to stack slot
9776 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
9777 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
9780 MachineMemOperand *MMO =
9781 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
9782 MachineMemOperand::MOStore, 2, 2);
9784 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
9785 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
9786 DAG.getVTList(MVT::Other),
9787 Ops, 2, MVT::i16, MMO);
9789 // Load FP Control Word from stack slot
9790 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
9791 MachinePointerInfo(), false, false, false, 0);
9793 // Transform as necessary
9795 DAG.getNode(ISD::SRL, DL, MVT::i16,
9796 DAG.getNode(ISD::AND, DL, MVT::i16,
9797 CWD, DAG.getConstant(0x800, MVT::i16)),
9798 DAG.getConstant(11, MVT::i8));
9800 DAG.getNode(ISD::SRL, DL, MVT::i16,
9801 DAG.getNode(ISD::AND, DL, MVT::i16,
9802 CWD, DAG.getConstant(0x400, MVT::i16)),
9803 DAG.getConstant(9, MVT::i8));
9806 DAG.getNode(ISD::AND, DL, MVT::i16,
9807 DAG.getNode(ISD::ADD, DL, MVT::i16,
9808 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
9809 DAG.getConstant(1, MVT::i16)),
9810 DAG.getConstant(3, MVT::i16));
9813 return DAG.getNode((VT.getSizeInBits() < 16 ?
9814 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
9817 SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const {
9818 EVT VT = Op.getValueType();
9820 unsigned NumBits = VT.getSizeInBits();
9821 DebugLoc dl = Op.getDebugLoc();
9823 Op = Op.getOperand(0);
9824 if (VT == MVT::i8) {
9825 // Zero extend to i32 since there is not an i8 bsr.
9827 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
9830 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
9831 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
9832 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
9834 // If src is zero (i.e. bsr sets ZF), returns NumBits.
9837 DAG.getConstant(NumBits+NumBits-1, OpVT),
9838 DAG.getConstant(X86::COND_E, MVT::i8),
9841 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
9843 // Finally xor with NumBits-1.
9844 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
9847 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
9851 SDValue X86TargetLowering::LowerCTLZ_ZERO_UNDEF(SDValue Op,
9852 SelectionDAG &DAG) const {
9853 EVT VT = Op.getValueType();
9855 unsigned NumBits = VT.getSizeInBits();
9856 DebugLoc dl = Op.getDebugLoc();
9858 Op = Op.getOperand(0);
9859 if (VT == MVT::i8) {
9860 // Zero extend to i32 since there is not an i8 bsr.
9862 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
9865 // Issue a bsr (scan bits in reverse).
9866 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
9867 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
9869 // And xor with NumBits-1.
9870 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
9873 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
9877 SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) const {
9878 EVT VT = Op.getValueType();
9879 unsigned NumBits = VT.getSizeInBits();
9880 DebugLoc dl = Op.getDebugLoc();
9881 Op = Op.getOperand(0);
9883 // Issue a bsf (scan bits forward) which also sets EFLAGS.
9884 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
9885 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
9887 // If src is zero (i.e. bsf sets ZF), returns NumBits.
9890 DAG.getConstant(NumBits, VT),
9891 DAG.getConstant(X86::COND_E, MVT::i8),
9894 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops, array_lengthof(Ops));
9897 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
9898 // ones, and then concatenate the result back.
9899 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
9900 EVT VT = Op.getValueType();
9902 assert(VT.getSizeInBits() == 256 && VT.isInteger() &&
9903 "Unsupported value type for operation");
9905 int NumElems = VT.getVectorNumElements();
9906 DebugLoc dl = Op.getDebugLoc();
9907 SDValue Idx0 = DAG.getConstant(0, MVT::i32);
9908 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32);
9910 // Extract the LHS vectors
9911 SDValue LHS = Op.getOperand(0);
9912 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl);
9913 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl);
9915 // Extract the RHS vectors
9916 SDValue RHS = Op.getOperand(1);
9917 SDValue RHS1 = Extract128BitVector(RHS, Idx0, DAG, dl);
9918 SDValue RHS2 = Extract128BitVector(RHS, Idx1, DAG, dl);
9920 MVT EltVT = VT.getVectorElementType().getSimpleVT();
9921 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
9923 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
9924 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
9925 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
9928 SDValue X86TargetLowering::LowerADD(SDValue Op, SelectionDAG &DAG) const {
9929 assert(Op.getValueType().getSizeInBits() == 256 &&
9930 Op.getValueType().isInteger() &&
9931 "Only handle AVX 256-bit vector integer operation");
9932 return Lower256IntArith(Op, DAG);
9935 SDValue X86TargetLowering::LowerSUB(SDValue Op, SelectionDAG &DAG) const {
9936 assert(Op.getValueType().getSizeInBits() == 256 &&
9937 Op.getValueType().isInteger() &&
9938 "Only handle AVX 256-bit vector integer operation");
9939 return Lower256IntArith(Op, DAG);
9942 SDValue X86TargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
9943 EVT VT = Op.getValueType();
9945 // Decompose 256-bit ops into smaller 128-bit ops.
9946 if (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2())
9947 return Lower256IntArith(Op, DAG);
9949 DebugLoc dl = Op.getDebugLoc();
9951 SDValue A = Op.getOperand(0);
9952 SDValue B = Op.getOperand(1);
9954 if (VT == MVT::v4i64) {
9955 assert(Subtarget->hasAVX2() && "Lowering v4i64 multiply requires AVX2");
9957 // ulong2 Ahi = __builtin_ia32_psrlqi256( a, 32);
9958 // ulong2 Bhi = __builtin_ia32_psrlqi256( b, 32);
9959 // ulong2 AloBlo = __builtin_ia32_pmuludq256( a, b );
9960 // ulong2 AloBhi = __builtin_ia32_pmuludq256( a, Bhi );
9961 // ulong2 AhiBlo = __builtin_ia32_pmuludq256( Ahi, b );
9963 // AloBhi = __builtin_ia32_psllqi256( AloBhi, 32 );
9964 // AhiBlo = __builtin_ia32_psllqi256( AhiBlo, 32 );
9965 // return AloBlo + AloBhi + AhiBlo;
9967 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9968 DAG.getConstant(Intrinsic::x86_avx2_psrli_q, MVT::i32),
9969 A, DAG.getConstant(32, MVT::i32));
9970 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9971 DAG.getConstant(Intrinsic::x86_avx2_psrli_q, MVT::i32),
9972 B, DAG.getConstant(32, MVT::i32));
9973 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9974 DAG.getConstant(Intrinsic::x86_avx2_pmulu_dq, MVT::i32),
9976 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9977 DAG.getConstant(Intrinsic::x86_avx2_pmulu_dq, MVT::i32),
9979 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9980 DAG.getConstant(Intrinsic::x86_avx2_pmulu_dq, MVT::i32),
9982 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9983 DAG.getConstant(Intrinsic::x86_avx2_pslli_q, MVT::i32),
9984 AloBhi, DAG.getConstant(32, MVT::i32));
9985 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9986 DAG.getConstant(Intrinsic::x86_avx2_pslli_q, MVT::i32),
9987 AhiBlo, DAG.getConstant(32, MVT::i32));
9988 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
9989 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
9993 assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply");
9995 // ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32);
9996 // ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32);
9997 // ulong2 AloBlo = __builtin_ia32_pmuludq128( a, b );
9998 // ulong2 AloBhi = __builtin_ia32_pmuludq128( a, Bhi );
9999 // ulong2 AhiBlo = __builtin_ia32_pmuludq128( Ahi, b );
10001 // AloBhi = __builtin_ia32_psllqi128( AloBhi, 32 );
10002 // AhiBlo = __builtin_ia32_psllqi128( AhiBlo, 32 );
10003 // return AloBlo + AloBhi + AhiBlo;
10005 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10006 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
10007 A, DAG.getConstant(32, MVT::i32));
10008 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10009 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
10010 B, DAG.getConstant(32, MVT::i32));
10011 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10012 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
10014 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10015 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
10017 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10018 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
10020 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10021 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
10022 AloBhi, DAG.getConstant(32, MVT::i32));
10023 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10024 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
10025 AhiBlo, DAG.getConstant(32, MVT::i32));
10026 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
10027 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
10031 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const {
10033 EVT VT = Op.getValueType();
10034 DebugLoc dl = Op.getDebugLoc();
10035 SDValue R = Op.getOperand(0);
10036 SDValue Amt = Op.getOperand(1);
10037 LLVMContext *Context = DAG.getContext();
10039 if (!Subtarget->hasXMMInt())
10042 // Optimize shl/srl/sra with constant shift amount.
10043 if (isSplatVector(Amt.getNode())) {
10044 SDValue SclrAmt = Amt->getOperand(0);
10045 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
10046 uint64_t ShiftAmt = C->getZExtValue();
10048 if (VT == MVT::v16i8 && Op.getOpcode() == ISD::SHL) {
10049 // Make a large shift.
10051 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10052 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
10053 R, DAG.getConstant(ShiftAmt, MVT::i32));
10054 // Zero out the rightmost bits.
10055 SmallVector<SDValue, 16> V(16, DAG.getConstant(uint8_t(-1U << ShiftAmt),
10057 return DAG.getNode(ISD::AND, dl, VT, SHL,
10058 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
10061 if (VT == MVT::v2i64 && Op.getOpcode() == ISD::SHL)
10062 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10063 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
10064 R, DAG.getConstant(ShiftAmt, MVT::i32));
10066 if (VT == MVT::v4i32 && Op.getOpcode() == ISD::SHL)
10067 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10068 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
10069 R, DAG.getConstant(ShiftAmt, MVT::i32));
10071 if (VT == MVT::v8i16 && Op.getOpcode() == ISD::SHL)
10072 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10073 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
10074 R, DAG.getConstant(ShiftAmt, MVT::i32));
10076 if (VT == MVT::v16i8 && Op.getOpcode() == ISD::SRL) {
10077 // Make a large shift.
10079 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10080 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32),
10081 R, DAG.getConstant(ShiftAmt, MVT::i32));
10082 // Zero out the leftmost bits.
10083 SmallVector<SDValue, 16> V(16, DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
10085 return DAG.getNode(ISD::AND, dl, VT, SRL,
10086 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
10089 if (VT == MVT::v2i64 && Op.getOpcode() == ISD::SRL)
10090 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10091 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
10092 R, DAG.getConstant(ShiftAmt, MVT::i32));
10094 if (VT == MVT::v4i32 && Op.getOpcode() == ISD::SRL)
10095 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10096 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32),
10097 R, DAG.getConstant(ShiftAmt, MVT::i32));
10099 if (VT == MVT::v8i16 && Op.getOpcode() == ISD::SRL)
10100 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10101 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32),
10102 R, DAG.getConstant(ShiftAmt, MVT::i32));
10104 if (VT == MVT::v4i32 && Op.getOpcode() == ISD::SRA)
10105 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10106 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32),
10107 R, DAG.getConstant(ShiftAmt, MVT::i32));
10109 if (VT == MVT::v8i16 && Op.getOpcode() == ISD::SRA)
10110 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10111 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32),
10112 R, DAG.getConstant(ShiftAmt, MVT::i32));
10114 if (VT == MVT::v16i8 && Op.getOpcode() == ISD::SRA) {
10115 if (ShiftAmt == 7) {
10116 // R s>> 7 === R s< 0
10117 SDValue Zeros = getZeroVector(VT, true /* HasXMMInt */, DAG, dl);
10118 return DAG.getNode(X86ISD::PCMPGTB, dl, VT, Zeros, R);
10121 // R s>> a === ((R u>> a) ^ m) - m
10122 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
10123 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
10125 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16);
10126 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
10127 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
10131 if (Subtarget->hasAVX2() && VT == MVT::v32i8) {
10132 if (Op.getOpcode() == ISD::SHL) {
10133 // Make a large shift.
10135 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10136 DAG.getConstant(Intrinsic::x86_avx2_pslli_w, MVT::i32),
10137 R, DAG.getConstant(ShiftAmt, MVT::i32));
10138 // Zero out the rightmost bits.
10139 SmallVector<SDValue, 32> V(32, DAG.getConstant(uint8_t(-1U << ShiftAmt),
10141 return DAG.getNode(ISD::AND, dl, VT, SHL,
10142 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
10144 if (Op.getOpcode() == ISD::SRL) {
10145 // Make a large shift.
10147 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10148 DAG.getConstant(Intrinsic::x86_avx2_psrli_w, MVT::i32),
10149 R, DAG.getConstant(ShiftAmt, MVT::i32));
10150 // Zero out the leftmost bits.
10151 SmallVector<SDValue, 32> V(32, DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
10153 return DAG.getNode(ISD::AND, dl, VT, SRL,
10154 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
10156 if (Op.getOpcode() == ISD::SRA) {
10157 if (ShiftAmt == 7) {
10158 // R s>> 7 === R s< 0
10159 SDValue Zeros = getZeroVector(VT, true /* HasXMMInt */, DAG, dl);
10160 return DAG.getNode(X86ISD::PCMPGTB, dl, VT, Zeros, R);
10163 // R s>> a === ((R u>> a) ^ m) - m
10164 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
10165 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
10167 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32);
10168 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
10169 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
10176 // Lower SHL with variable shift amount.
10177 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
10178 Op = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10179 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
10180 Op.getOperand(1), DAG.getConstant(23, MVT::i32));
10182 ConstantInt *CI = ConstantInt::get(*Context, APInt(32, 0x3f800000U));
10184 std::vector<Constant*> CV(4, CI);
10185 Constant *C = ConstantVector::get(CV);
10186 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
10187 SDValue Addend = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
10188 MachinePointerInfo::getConstantPool(),
10189 false, false, false, 16);
10191 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Addend);
10192 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
10193 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
10194 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
10196 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
10197 assert((Subtarget->hasSSE2() || Subtarget->hasAVX()) &&
10198 "Need SSE2 for pslli/pcmpeq.");
10201 Op = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10202 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
10203 Op.getOperand(1), DAG.getConstant(5, MVT::i32));
10205 // Turn 'a' into a mask suitable for VSELECT
10206 SDValue VSelM = DAG.getConstant(0x80, VT);
10207 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
10208 OpVSel = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10209 DAG.getConstant(Intrinsic::x86_sse2_pcmpeq_b, MVT::i32),
10212 SDValue CM1 = DAG.getConstant(0x0f, VT);
10213 SDValue CM2 = DAG.getConstant(0x3f, VT);
10215 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
10216 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
10217 M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10218 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M,
10219 DAG.getConstant(4, MVT::i32));
10220 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
10223 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
10224 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
10225 OpVSel = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10226 DAG.getConstant(Intrinsic::x86_sse2_pcmpeq_b, MVT::i32),
10229 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
10230 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
10231 M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10232 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M,
10233 DAG.getConstant(2, MVT::i32));
10234 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
10237 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
10238 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
10239 OpVSel = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10240 DAG.getConstant(Intrinsic::x86_sse2_pcmpeq_b, MVT::i32),
10243 // return VSELECT(r, r+r, a);
10244 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
10245 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
10249 // Decompose 256-bit shifts into smaller 128-bit shifts.
10250 if (VT.getSizeInBits() == 256) {
10251 int NumElems = VT.getVectorNumElements();
10252 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10253 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
10255 // Extract the two vectors
10256 SDValue V1 = Extract128BitVector(R, DAG.getConstant(0, MVT::i32), DAG, dl);
10257 SDValue V2 = Extract128BitVector(R, DAG.getConstant(NumElems/2, MVT::i32),
10260 // Recreate the shift amount vectors
10261 SDValue Amt1, Amt2;
10262 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
10263 // Constant shift amount
10264 SmallVector<SDValue, 4> Amt1Csts;
10265 SmallVector<SDValue, 4> Amt2Csts;
10266 for (int i = 0; i < NumElems/2; ++i)
10267 Amt1Csts.push_back(Amt->getOperand(i));
10268 for (int i = NumElems/2; i < NumElems; ++i)
10269 Amt2Csts.push_back(Amt->getOperand(i));
10271 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
10272 &Amt1Csts[0], NumElems/2);
10273 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
10274 &Amt2Csts[0], NumElems/2);
10276 // Variable shift amount
10277 Amt1 = Extract128BitVector(Amt, DAG.getConstant(0, MVT::i32), DAG, dl);
10278 Amt2 = Extract128BitVector(Amt, DAG.getConstant(NumElems/2, MVT::i32),
10282 // Issue new vector shifts for the smaller types
10283 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
10284 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
10286 // Concatenate the result back
10287 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
10293 SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const {
10294 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
10295 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
10296 // looks for this combo and may remove the "setcc" instruction if the "setcc"
10297 // has only one use.
10298 SDNode *N = Op.getNode();
10299 SDValue LHS = N->getOperand(0);
10300 SDValue RHS = N->getOperand(1);
10301 unsigned BaseOp = 0;
10303 DebugLoc DL = Op.getDebugLoc();
10304 switch (Op.getOpcode()) {
10305 default: llvm_unreachable("Unknown ovf instruction!");
10307 // A subtract of one will be selected as a INC. Note that INC doesn't
10308 // set CF, so we can't do this for UADDO.
10309 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
10311 BaseOp = X86ISD::INC;
10312 Cond = X86::COND_O;
10315 BaseOp = X86ISD::ADD;
10316 Cond = X86::COND_O;
10319 BaseOp = X86ISD::ADD;
10320 Cond = X86::COND_B;
10323 // A subtract of one will be selected as a DEC. Note that DEC doesn't
10324 // set CF, so we can't do this for USUBO.
10325 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
10327 BaseOp = X86ISD::DEC;
10328 Cond = X86::COND_O;
10331 BaseOp = X86ISD::SUB;
10332 Cond = X86::COND_O;
10335 BaseOp = X86ISD::SUB;
10336 Cond = X86::COND_B;
10339 BaseOp = X86ISD::SMUL;
10340 Cond = X86::COND_O;
10342 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
10343 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
10345 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
10348 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
10349 DAG.getConstant(X86::COND_O, MVT::i32),
10350 SDValue(Sum.getNode(), 2));
10352 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
10356 // Also sets EFLAGS.
10357 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
10358 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
10361 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
10362 DAG.getConstant(Cond, MVT::i32),
10363 SDValue(Sum.getNode(), 1));
10365 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
10368 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
10369 SelectionDAG &DAG) const {
10370 DebugLoc dl = Op.getDebugLoc();
10371 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
10372 EVT VT = Op.getValueType();
10374 if (Subtarget->hasXMMInt() && VT.isVector()) {
10375 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
10376 ExtraVT.getScalarType().getSizeInBits();
10377 SDValue ShAmt = DAG.getConstant(BitsDiff, MVT::i32);
10379 unsigned SHLIntrinsicsID = 0;
10380 unsigned SRAIntrinsicsID = 0;
10381 switch (VT.getSimpleVT().SimpleTy) {
10385 SHLIntrinsicsID = Intrinsic::x86_sse2_pslli_d;
10386 SRAIntrinsicsID = Intrinsic::x86_sse2_psrai_d;
10389 SHLIntrinsicsID = Intrinsic::x86_sse2_pslli_w;
10390 SRAIntrinsicsID = Intrinsic::x86_sse2_psrai_w;
10394 if (!Subtarget->hasAVX())
10396 if (!Subtarget->hasAVX2()) {
10397 // needs to be split
10398 int NumElems = VT.getVectorNumElements();
10399 SDValue Idx0 = DAG.getConstant(0, MVT::i32);
10400 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32);
10402 // Extract the LHS vectors
10403 SDValue LHS = Op.getOperand(0);
10404 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl);
10405 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl);
10407 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10408 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
10410 EVT ExtraEltVT = ExtraVT.getVectorElementType();
10411 int ExtraNumElems = ExtraVT.getVectorNumElements();
10412 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
10414 SDValue Extra = DAG.getValueType(ExtraVT);
10416 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
10417 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
10419 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);;
10421 if (VT == MVT::v8i32) {
10422 SHLIntrinsicsID = Intrinsic::x86_avx2_pslli_d;
10423 SRAIntrinsicsID = Intrinsic::x86_avx2_psrai_d;
10425 SHLIntrinsicsID = Intrinsic::x86_avx2_pslli_w;
10426 SRAIntrinsicsID = Intrinsic::x86_avx2_psrai_w;
10430 SDValue Tmp1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10431 DAG.getConstant(SHLIntrinsicsID, MVT::i32),
10432 Op.getOperand(0), ShAmt);
10434 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10435 DAG.getConstant(SRAIntrinsicsID, MVT::i32),
10443 SDValue X86TargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const{
10444 DebugLoc dl = Op.getDebugLoc();
10446 // Go ahead and emit the fence on x86-64 even if we asked for no-sse2.
10447 // There isn't any reason to disable it if the target processor supports it.
10448 if (!Subtarget->hasXMMInt() && !Subtarget->is64Bit()) {
10449 SDValue Chain = Op.getOperand(0);
10450 SDValue Zero = DAG.getConstant(0, MVT::i32);
10452 DAG.getRegister(X86::ESP, MVT::i32), // Base
10453 DAG.getTargetConstant(1, MVT::i8), // Scale
10454 DAG.getRegister(0, MVT::i32), // Index
10455 DAG.getTargetConstant(0, MVT::i32), // Disp
10456 DAG.getRegister(0, MVT::i32), // Segment.
10461 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
10462 array_lengthof(Ops));
10463 return SDValue(Res, 0);
10466 unsigned isDev = cast<ConstantSDNode>(Op.getOperand(5))->getZExtValue();
10468 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
10470 unsigned Op1 = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10471 unsigned Op2 = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
10472 unsigned Op3 = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
10473 unsigned Op4 = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
10475 // def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
10476 if (!Op1 && !Op2 && !Op3 && Op4)
10477 return DAG.getNode(X86ISD::SFENCE, dl, MVT::Other, Op.getOperand(0));
10479 // def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
10480 if (Op1 && !Op2 && !Op3 && !Op4)
10481 return DAG.getNode(X86ISD::LFENCE, dl, MVT::Other, Op.getOperand(0));
10483 // def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm), (i8 1)),
10485 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
10488 SDValue X86TargetLowering::LowerATOMIC_FENCE(SDValue Op,
10489 SelectionDAG &DAG) const {
10490 DebugLoc dl = Op.getDebugLoc();
10491 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
10492 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
10493 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
10494 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
10496 // The only fence that needs an instruction is a sequentially-consistent
10497 // cross-thread fence.
10498 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
10499 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
10500 // no-sse2). There isn't any reason to disable it if the target processor
10502 if (Subtarget->hasXMMInt() || Subtarget->is64Bit())
10503 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
10505 SDValue Chain = Op.getOperand(0);
10506 SDValue Zero = DAG.getConstant(0, MVT::i32);
10508 DAG.getRegister(X86::ESP, MVT::i32), // Base
10509 DAG.getTargetConstant(1, MVT::i8), // Scale
10510 DAG.getRegister(0, MVT::i32), // Index
10511 DAG.getTargetConstant(0, MVT::i32), // Disp
10512 DAG.getRegister(0, MVT::i32), // Segment.
10517 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
10518 array_lengthof(Ops));
10519 return SDValue(Res, 0);
10522 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
10523 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
10527 SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const {
10528 EVT T = Op.getValueType();
10529 DebugLoc DL = Op.getDebugLoc();
10532 switch(T.getSimpleVT().SimpleTy) {
10534 assert(false && "Invalid value type!");
10535 case MVT::i8: Reg = X86::AL; size = 1; break;
10536 case MVT::i16: Reg = X86::AX; size = 2; break;
10537 case MVT::i32: Reg = X86::EAX; size = 4; break;
10539 assert(Subtarget->is64Bit() && "Node not type legal!");
10540 Reg = X86::RAX; size = 8;
10543 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
10544 Op.getOperand(2), SDValue());
10545 SDValue Ops[] = { cpIn.getValue(0),
10548 DAG.getTargetConstant(size, MVT::i8),
10549 cpIn.getValue(1) };
10550 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10551 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
10552 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
10555 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
10559 SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
10560 SelectionDAG &DAG) const {
10561 assert(Subtarget->is64Bit() && "Result not type legalized?");
10562 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10563 SDValue TheChain = Op.getOperand(0);
10564 DebugLoc dl = Op.getDebugLoc();
10565 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
10566 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
10567 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
10569 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
10570 DAG.getConstant(32, MVT::i8));
10572 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
10575 return DAG.getMergeValues(Ops, 2, dl);
10578 SDValue X86TargetLowering::LowerBITCAST(SDValue Op,
10579 SelectionDAG &DAG) const {
10580 EVT SrcVT = Op.getOperand(0).getValueType();
10581 EVT DstVT = Op.getValueType();
10582 assert(Subtarget->is64Bit() && !Subtarget->hasXMMInt() &&
10583 Subtarget->hasMMX() && "Unexpected custom BITCAST");
10584 assert((DstVT == MVT::i64 ||
10585 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
10586 "Unexpected custom BITCAST");
10587 // i64 <=> MMX conversions are Legal.
10588 if (SrcVT==MVT::i64 && DstVT.isVector())
10590 if (DstVT==MVT::i64 && SrcVT.isVector())
10592 // MMX <=> MMX conversions are Legal.
10593 if (SrcVT.isVector() && DstVT.isVector())
10595 // All other conversions need to be expanded.
10599 SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const {
10600 SDNode *Node = Op.getNode();
10601 DebugLoc dl = Node->getDebugLoc();
10602 EVT T = Node->getValueType(0);
10603 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
10604 DAG.getConstant(0, T), Node->getOperand(2));
10605 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
10606 cast<AtomicSDNode>(Node)->getMemoryVT(),
10607 Node->getOperand(0),
10608 Node->getOperand(1), negOp,
10609 cast<AtomicSDNode>(Node)->getSrcValue(),
10610 cast<AtomicSDNode>(Node)->getAlignment(),
10611 cast<AtomicSDNode>(Node)->getOrdering(),
10612 cast<AtomicSDNode>(Node)->getSynchScope());
10615 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
10616 SDNode *Node = Op.getNode();
10617 DebugLoc dl = Node->getDebugLoc();
10618 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
10620 // Convert seq_cst store -> xchg
10621 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
10622 // FIXME: On 32-bit, store -> fist or movq would be more efficient
10623 // (The only way to get a 16-byte store is cmpxchg16b)
10624 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
10625 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
10626 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
10627 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
10628 cast<AtomicSDNode>(Node)->getMemoryVT(),
10629 Node->getOperand(0),
10630 Node->getOperand(1), Node->getOperand(2),
10631 cast<AtomicSDNode>(Node)->getMemOperand(),
10632 cast<AtomicSDNode>(Node)->getOrdering(),
10633 cast<AtomicSDNode>(Node)->getSynchScope());
10634 return Swap.getValue(1);
10636 // Other atomic stores have a simple pattern.
10640 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
10641 EVT VT = Op.getNode()->getValueType(0);
10643 // Let legalize expand this if it isn't a legal type yet.
10644 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
10647 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
10650 bool ExtraOp = false;
10651 switch (Op.getOpcode()) {
10652 default: assert(0 && "Invalid code");
10653 case ISD::ADDC: Opc = X86ISD::ADD; break;
10654 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
10655 case ISD::SUBC: Opc = X86ISD::SUB; break;
10656 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
10660 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
10662 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
10663 Op.getOperand(1), Op.getOperand(2));
10666 /// LowerOperation - Provide custom lowering hooks for some operations.
10668 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
10669 switch (Op.getOpcode()) {
10670 default: llvm_unreachable("Should not custom lower this!");
10671 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
10672 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op,DAG);
10673 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op,DAG);
10674 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG);
10675 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
10676 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
10677 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
10678 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
10679 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
10680 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
10681 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
10682 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
10683 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, DAG);
10684 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
10685 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
10686 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
10687 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
10688 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
10689 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
10690 case ISD::SHL_PARTS:
10691 case ISD::SRA_PARTS:
10692 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
10693 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
10694 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
10695 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
10696 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
10697 case ISD::FABS: return LowerFABS(Op, DAG);
10698 case ISD::FNEG: return LowerFNEG(Op, DAG);
10699 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
10700 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
10701 case ISD::SETCC: return LowerSETCC(Op, DAG);
10702 case ISD::SELECT: return LowerSELECT(Op, DAG);
10703 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
10704 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
10705 case ISD::VASTART: return LowerVASTART(Op, DAG);
10706 case ISD::VAARG: return LowerVAARG(Op, DAG);
10707 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
10708 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
10709 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
10710 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
10711 case ISD::FRAME_TO_ARGS_OFFSET:
10712 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
10713 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
10714 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
10715 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
10716 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
10717 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
10718 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
10719 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
10720 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
10721 case ISD::MUL: return LowerMUL(Op, DAG);
10724 case ISD::SHL: return LowerShift(Op, DAG);
10730 case ISD::UMULO: return LowerXALUO(Op, DAG);
10731 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
10732 case ISD::BITCAST: return LowerBITCAST(Op, DAG);
10736 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
10737 case ISD::ADD: return LowerADD(Op, DAG);
10738 case ISD::SUB: return LowerSUB(Op, DAG);
10742 static void ReplaceATOMIC_LOAD(SDNode *Node,
10743 SmallVectorImpl<SDValue> &Results,
10744 SelectionDAG &DAG) {
10745 DebugLoc dl = Node->getDebugLoc();
10746 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
10748 // Convert wide load -> cmpxchg8b/cmpxchg16b
10749 // FIXME: On 32-bit, load -> fild or movq would be more efficient
10750 // (The only way to get a 16-byte load is cmpxchg16b)
10751 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment.
10752 SDValue Zero = DAG.getConstant(0, VT);
10753 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT,
10754 Node->getOperand(0),
10755 Node->getOperand(1), Zero, Zero,
10756 cast<AtomicSDNode>(Node)->getMemOperand(),
10757 cast<AtomicSDNode>(Node)->getOrdering(),
10758 cast<AtomicSDNode>(Node)->getSynchScope());
10759 Results.push_back(Swap.getValue(0));
10760 Results.push_back(Swap.getValue(1));
10763 void X86TargetLowering::
10764 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
10765 SelectionDAG &DAG, unsigned NewOp) const {
10766 DebugLoc dl = Node->getDebugLoc();
10767 assert (Node->getValueType(0) == MVT::i64 &&
10768 "Only know how to expand i64 atomics");
10770 SDValue Chain = Node->getOperand(0);
10771 SDValue In1 = Node->getOperand(1);
10772 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
10773 Node->getOperand(2), DAG.getIntPtrConstant(0));
10774 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
10775 Node->getOperand(2), DAG.getIntPtrConstant(1));
10776 SDValue Ops[] = { Chain, In1, In2L, In2H };
10777 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
10779 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64,
10780 cast<MemSDNode>(Node)->getMemOperand());
10781 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
10782 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
10783 Results.push_back(Result.getValue(2));
10786 /// ReplaceNodeResults - Replace a node with an illegal result type
10787 /// with a new node built out of custom code.
10788 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
10789 SmallVectorImpl<SDValue>&Results,
10790 SelectionDAG &DAG) const {
10791 DebugLoc dl = N->getDebugLoc();
10792 switch (N->getOpcode()) {
10794 assert(false && "Do not know how to custom type legalize this operation!");
10796 case ISD::SIGN_EXTEND_INREG:
10801 // We don't want to expand or promote these.
10803 case ISD::FP_TO_SINT: {
10804 std::pair<SDValue,SDValue> Vals =
10805 FP_TO_INTHelper(SDValue(N, 0), DAG, true);
10806 SDValue FIST = Vals.first, StackSlot = Vals.second;
10807 if (FIST.getNode() != 0) {
10808 EVT VT = N->getValueType(0);
10809 // Return a load from the stack slot.
10810 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
10811 MachinePointerInfo(),
10812 false, false, false, 0));
10816 case ISD::READCYCLECOUNTER: {
10817 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10818 SDValue TheChain = N->getOperand(0);
10819 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
10820 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
10822 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
10824 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
10825 SDValue Ops[] = { eax, edx };
10826 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
10827 Results.push_back(edx.getValue(1));
10830 case ISD::ATOMIC_CMP_SWAP: {
10831 EVT T = N->getValueType(0);
10832 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
10833 bool Regs64bit = T == MVT::i128;
10834 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
10835 SDValue cpInL, cpInH;
10836 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
10837 DAG.getConstant(0, HalfT));
10838 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
10839 DAG.getConstant(1, HalfT));
10840 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
10841 Regs64bit ? X86::RAX : X86::EAX,
10843 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
10844 Regs64bit ? X86::RDX : X86::EDX,
10845 cpInH, cpInL.getValue(1));
10846 SDValue swapInL, swapInH;
10847 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
10848 DAG.getConstant(0, HalfT));
10849 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
10850 DAG.getConstant(1, HalfT));
10851 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
10852 Regs64bit ? X86::RBX : X86::EBX,
10853 swapInL, cpInH.getValue(1));
10854 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
10855 Regs64bit ? X86::RCX : X86::ECX,
10856 swapInH, swapInL.getValue(1));
10857 SDValue Ops[] = { swapInH.getValue(0),
10859 swapInH.getValue(1) };
10860 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10861 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
10862 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
10863 X86ISD::LCMPXCHG8_DAG;
10864 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys,
10866 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
10867 Regs64bit ? X86::RAX : X86::EAX,
10868 HalfT, Result.getValue(1));
10869 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
10870 Regs64bit ? X86::RDX : X86::EDX,
10871 HalfT, cpOutL.getValue(2));
10872 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
10873 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF, 2));
10874 Results.push_back(cpOutH.getValue(1));
10877 case ISD::ATOMIC_LOAD_ADD:
10878 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG);
10880 case ISD::ATOMIC_LOAD_AND:
10881 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG);
10883 case ISD::ATOMIC_LOAD_NAND:
10884 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG);
10886 case ISD::ATOMIC_LOAD_OR:
10887 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG);
10889 case ISD::ATOMIC_LOAD_SUB:
10890 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG);
10892 case ISD::ATOMIC_LOAD_XOR:
10893 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG);
10895 case ISD::ATOMIC_SWAP:
10896 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG);
10898 case ISD::ATOMIC_LOAD:
10899 ReplaceATOMIC_LOAD(N, Results, DAG);
10903 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
10905 default: return NULL;
10906 case X86ISD::BSF: return "X86ISD::BSF";
10907 case X86ISD::BSR: return "X86ISD::BSR";
10908 case X86ISD::SHLD: return "X86ISD::SHLD";
10909 case X86ISD::SHRD: return "X86ISD::SHRD";
10910 case X86ISD::FAND: return "X86ISD::FAND";
10911 case X86ISD::FOR: return "X86ISD::FOR";
10912 case X86ISD::FXOR: return "X86ISD::FXOR";
10913 case X86ISD::FSRL: return "X86ISD::FSRL";
10914 case X86ISD::FILD: return "X86ISD::FILD";
10915 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
10916 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
10917 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
10918 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
10919 case X86ISD::FLD: return "X86ISD::FLD";
10920 case X86ISD::FST: return "X86ISD::FST";
10921 case X86ISD::CALL: return "X86ISD::CALL";
10922 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
10923 case X86ISD::BT: return "X86ISD::BT";
10924 case X86ISD::CMP: return "X86ISD::CMP";
10925 case X86ISD::COMI: return "X86ISD::COMI";
10926 case X86ISD::UCOMI: return "X86ISD::UCOMI";
10927 case X86ISD::SETCC: return "X86ISD::SETCC";
10928 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
10929 case X86ISD::FSETCCsd: return "X86ISD::FSETCCsd";
10930 case X86ISD::FSETCCss: return "X86ISD::FSETCCss";
10931 case X86ISD::CMOV: return "X86ISD::CMOV";
10932 case X86ISD::BRCOND: return "X86ISD::BRCOND";
10933 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
10934 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
10935 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
10936 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
10937 case X86ISD::Wrapper: return "X86ISD::Wrapper";
10938 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
10939 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
10940 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
10941 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
10942 case X86ISD::PINSRB: return "X86ISD::PINSRB";
10943 case X86ISD::PINSRW: return "X86ISD::PINSRW";
10944 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
10945 case X86ISD::ANDNP: return "X86ISD::ANDNP";
10946 case X86ISD::PSIGN: return "X86ISD::PSIGN";
10947 case X86ISD::BLENDV: return "X86ISD::BLENDV";
10948 case X86ISD::HADD: return "X86ISD::HADD";
10949 case X86ISD::HSUB: return "X86ISD::HSUB";
10950 case X86ISD::FHADD: return "X86ISD::FHADD";
10951 case X86ISD::FHSUB: return "X86ISD::FHSUB";
10952 case X86ISD::FMAX: return "X86ISD::FMAX";
10953 case X86ISD::FMIN: return "X86ISD::FMIN";
10954 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
10955 case X86ISD::FRCP: return "X86ISD::FRCP";
10956 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
10957 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
10958 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
10959 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
10960 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
10961 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
10962 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
10963 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
10964 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
10965 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
10966 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
10967 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
10968 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
10969 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
10970 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
10971 case X86ISD::VSHL: return "X86ISD::VSHL";
10972 case X86ISD::VSRL: return "X86ISD::VSRL";
10973 case X86ISD::CMPPD: return "X86ISD::CMPPD";
10974 case X86ISD::CMPPS: return "X86ISD::CMPPS";
10975 case X86ISD::PCMPEQB: return "X86ISD::PCMPEQB";
10976 case X86ISD::PCMPEQW: return "X86ISD::PCMPEQW";
10977 case X86ISD::PCMPEQD: return "X86ISD::PCMPEQD";
10978 case X86ISD::PCMPEQQ: return "X86ISD::PCMPEQQ";
10979 case X86ISD::PCMPGTB: return "X86ISD::PCMPGTB";
10980 case X86ISD::PCMPGTW: return "X86ISD::PCMPGTW";
10981 case X86ISD::PCMPGTD: return "X86ISD::PCMPGTD";
10982 case X86ISD::PCMPGTQ: return "X86ISD::PCMPGTQ";
10983 case X86ISD::ADD: return "X86ISD::ADD";
10984 case X86ISD::SUB: return "X86ISD::SUB";
10985 case X86ISD::ADC: return "X86ISD::ADC";
10986 case X86ISD::SBB: return "X86ISD::SBB";
10987 case X86ISD::SMUL: return "X86ISD::SMUL";
10988 case X86ISD::UMUL: return "X86ISD::UMUL";
10989 case X86ISD::INC: return "X86ISD::INC";
10990 case X86ISD::DEC: return "X86ISD::DEC";
10991 case X86ISD::OR: return "X86ISD::OR";
10992 case X86ISD::XOR: return "X86ISD::XOR";
10993 case X86ISD::AND: return "X86ISD::AND";
10994 case X86ISD::ANDN: return "X86ISD::ANDN";
10995 case X86ISD::BLSI: return "X86ISD::BLSI";
10996 case X86ISD::BLSMSK: return "X86ISD::BLSMSK";
10997 case X86ISD::BLSR: return "X86ISD::BLSR";
10998 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
10999 case X86ISD::PTEST: return "X86ISD::PTEST";
11000 case X86ISD::TESTP: return "X86ISD::TESTP";
11001 case X86ISD::PALIGN: return "X86ISD::PALIGN";
11002 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
11003 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
11004 case X86ISD::PSHUFHW_LD: return "X86ISD::PSHUFHW_LD";
11005 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
11006 case X86ISD::PSHUFLW_LD: return "X86ISD::PSHUFLW_LD";
11007 case X86ISD::SHUFP: return "X86ISD::SHUFP";
11008 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
11009 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
11010 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
11011 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
11012 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
11013 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
11014 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
11015 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
11016 case X86ISD::MOVSHDUP_LD: return "X86ISD::MOVSHDUP_LD";
11017 case X86ISD::MOVSLDUP_LD: return "X86ISD::MOVSLDUP_LD";
11018 case X86ISD::MOVSD: return "X86ISD::MOVSD";
11019 case X86ISD::MOVSS: return "X86ISD::MOVSS";
11020 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
11021 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
11022 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
11023 case X86ISD::VPERMILP: return "X86ISD::VPERMILP";
11024 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
11025 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
11026 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
11027 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
11028 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
11029 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
11033 // isLegalAddressingMode - Return true if the addressing mode represented
11034 // by AM is legal for this target, for a load/store of the specified type.
11035 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
11037 // X86 supports extremely general addressing modes.
11038 CodeModel::Model M = getTargetMachine().getCodeModel();
11039 Reloc::Model R = getTargetMachine().getRelocationModel();
11041 // X86 allows a sign-extended 32-bit immediate field as a displacement.
11042 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
11047 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
11049 // If a reference to this global requires an extra load, we can't fold it.
11050 if (isGlobalStubReference(GVFlags))
11053 // If BaseGV requires a register for the PIC base, we cannot also have a
11054 // BaseReg specified.
11055 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
11058 // If lower 4G is not available, then we must use rip-relative addressing.
11059 if ((M != CodeModel::Small || R != Reloc::Static) &&
11060 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
11064 switch (AM.Scale) {
11070 // These scales always work.
11075 // These scales are formed with basereg+scalereg. Only accept if there is
11080 default: // Other stuff never works.
11088 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
11089 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
11091 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
11092 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
11093 if (NumBits1 <= NumBits2)
11098 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
11099 if (!VT1.isInteger() || !VT2.isInteger())
11101 unsigned NumBits1 = VT1.getSizeInBits();
11102 unsigned NumBits2 = VT2.getSizeInBits();
11103 if (NumBits1 <= NumBits2)
11108 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
11109 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
11110 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
11113 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
11114 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
11115 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
11118 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
11119 // i16 instructions are longer (0x66 prefix) and potentially slower.
11120 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
11123 /// isShuffleMaskLegal - Targets can use this to indicate that they only
11124 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
11125 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
11126 /// are assumed to be legal.
11128 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
11130 // Very little shuffling can be done for 64-bit vectors right now.
11131 if (VT.getSizeInBits() == 64)
11134 // FIXME: pshufb, blends, shifts.
11135 return (VT.getVectorNumElements() == 2 ||
11136 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
11137 isMOVLMask(M, VT) ||
11138 isSHUFPMask(M, VT) ||
11139 isPSHUFDMask(M, VT) ||
11140 isPSHUFHWMask(M, VT) ||
11141 isPSHUFLWMask(M, VT) ||
11142 isPALIGNRMask(M, VT, Subtarget->hasSSSE3orAVX()) ||
11143 isUNPCKLMask(M, VT, Subtarget->hasAVX2()) ||
11144 isUNPCKHMask(M, VT, Subtarget->hasAVX2()) ||
11145 isUNPCKL_v_undef_Mask(M, VT, Subtarget->hasAVX2()) ||
11146 isUNPCKH_v_undef_Mask(M, VT, Subtarget->hasAVX2()));
11150 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
11152 unsigned NumElts = VT.getVectorNumElements();
11153 // FIXME: This collection of masks seems suspect.
11156 if (NumElts == 4 && VT.getSizeInBits() == 128) {
11157 return (isMOVLMask(Mask, VT) ||
11158 isCommutedMOVLMask(Mask, VT, true) ||
11159 isSHUFPMask(Mask, VT) ||
11160 isSHUFPMask(Mask, VT, /* Commuted */ true));
11165 //===----------------------------------------------------------------------===//
11166 // X86 Scheduler Hooks
11167 //===----------------------------------------------------------------------===//
11169 // private utility function
11170 MachineBasicBlock *
11171 X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
11172 MachineBasicBlock *MBB,
11179 TargetRegisterClass *RC,
11180 bool invSrc) const {
11181 // For the atomic bitwise operator, we generate
11184 // ld t1 = [bitinstr.addr]
11185 // op t2 = t1, [bitinstr.val]
11187 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
11189 // fallthrough -->nextMBB
11190 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11191 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11192 MachineFunction::iterator MBBIter = MBB;
11195 /// First build the CFG
11196 MachineFunction *F = MBB->getParent();
11197 MachineBasicBlock *thisMBB = MBB;
11198 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11199 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11200 F->insert(MBBIter, newMBB);
11201 F->insert(MBBIter, nextMBB);
11203 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11204 nextMBB->splice(nextMBB->begin(), thisMBB,
11205 llvm::next(MachineBasicBlock::iterator(bInstr)),
11207 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11209 // Update thisMBB to fall through to newMBB
11210 thisMBB->addSuccessor(newMBB);
11212 // newMBB jumps to itself and fall through to nextMBB
11213 newMBB->addSuccessor(nextMBB);
11214 newMBB->addSuccessor(newMBB);
11216 // Insert instructions into newMBB based on incoming instruction
11217 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
11218 "unexpected number of operands");
11219 DebugLoc dl = bInstr->getDebugLoc();
11220 MachineOperand& destOper = bInstr->getOperand(0);
11221 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11222 int numArgs = bInstr->getNumOperands() - 1;
11223 for (int i=0; i < numArgs; ++i)
11224 argOpers[i] = &bInstr->getOperand(i+1);
11226 // x86 address has 4 operands: base, index, scale, and displacement
11227 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11228 int valArgIndx = lastAddrIndx + 1;
11230 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
11231 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1);
11232 for (int i=0; i <= lastAddrIndx; ++i)
11233 (*MIB).addOperand(*argOpers[i]);
11235 unsigned tt = F->getRegInfo().createVirtualRegister(RC);
11237 MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1);
11242 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
11243 assert((argOpers[valArgIndx]->isReg() ||
11244 argOpers[valArgIndx]->isImm()) &&
11245 "invalid operand");
11246 if (argOpers[valArgIndx]->isReg())
11247 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2);
11249 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2);
11251 (*MIB).addOperand(*argOpers[valArgIndx]);
11253 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), EAXreg);
11256 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc));
11257 for (int i=0; i <= lastAddrIndx; ++i)
11258 (*MIB).addOperand(*argOpers[i]);
11260 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11261 (*MIB).setMemRefs(bInstr->memoperands_begin(),
11262 bInstr->memoperands_end());
11264 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
11265 MIB.addReg(EAXreg);
11268 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11270 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
11274 // private utility function: 64 bit atomics on 32 bit host.
11275 MachineBasicBlock *
11276 X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
11277 MachineBasicBlock *MBB,
11282 bool invSrc) const {
11283 // For the atomic bitwise operator, we generate
11284 // thisMBB (instructions are in pairs, except cmpxchg8b)
11285 // ld t1,t2 = [bitinstr.addr]
11287 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4)
11288 // op t5, t6 <- out1, out2, [bitinstr.val]
11289 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val])
11290 // mov ECX, EBX <- t5, t6
11291 // mov EAX, EDX <- t1, t2
11292 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit]
11293 // mov t3, t4 <- EAX, EDX
11295 // result in out1, out2
11296 // fallthrough -->nextMBB
11298 const TargetRegisterClass *RC = X86::GR32RegisterClass;
11299 const unsigned LoadOpc = X86::MOV32rm;
11300 const unsigned NotOpc = X86::NOT32r;
11301 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11302 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11303 MachineFunction::iterator MBBIter = MBB;
11306 /// First build the CFG
11307 MachineFunction *F = MBB->getParent();
11308 MachineBasicBlock *thisMBB = MBB;
11309 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11310 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11311 F->insert(MBBIter, newMBB);
11312 F->insert(MBBIter, nextMBB);
11314 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11315 nextMBB->splice(nextMBB->begin(), thisMBB,
11316 llvm::next(MachineBasicBlock::iterator(bInstr)),
11318 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11320 // Update thisMBB to fall through to newMBB
11321 thisMBB->addSuccessor(newMBB);
11323 // newMBB jumps to itself and fall through to nextMBB
11324 newMBB->addSuccessor(nextMBB);
11325 newMBB->addSuccessor(newMBB);
11327 DebugLoc dl = bInstr->getDebugLoc();
11328 // Insert instructions into newMBB based on incoming instruction
11329 // There are 8 "real" operands plus 9 implicit def/uses, ignored here.
11330 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 14 &&
11331 "unexpected number of operands");
11332 MachineOperand& dest1Oper = bInstr->getOperand(0);
11333 MachineOperand& dest2Oper = bInstr->getOperand(1);
11334 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11335 for (int i=0; i < 2 + X86::AddrNumOperands; ++i) {
11336 argOpers[i] = &bInstr->getOperand(i+2);
11338 // We use some of the operands multiple times, so conservatively just
11339 // clear any kill flags that might be present.
11340 if (argOpers[i]->isReg() && argOpers[i]->isUse())
11341 argOpers[i]->setIsKill(false);
11344 // x86 address has 5 operands: base, index, scale, displacement, and segment.
11345 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11347 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
11348 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1);
11349 for (int i=0; i <= lastAddrIndx; ++i)
11350 (*MIB).addOperand(*argOpers[i]);
11351 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
11352 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2);
11353 // add 4 to displacement.
11354 for (int i=0; i <= lastAddrIndx-2; ++i)
11355 (*MIB).addOperand(*argOpers[i]);
11356 MachineOperand newOp3 = *(argOpers[3]);
11357 if (newOp3.isImm())
11358 newOp3.setImm(newOp3.getImm()+4);
11360 newOp3.setOffset(newOp3.getOffset()+4);
11361 (*MIB).addOperand(newOp3);
11362 (*MIB).addOperand(*argOpers[lastAddrIndx]);
11364 // t3/4 are defined later, at the bottom of the loop
11365 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
11366 unsigned t4 = F->getRegInfo().createVirtualRegister(RC);
11367 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg())
11368 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB);
11369 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg())
11370 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB);
11372 // The subsequent operations should be using the destination registers of
11373 //the PHI instructions.
11375 t1 = F->getRegInfo().createVirtualRegister(RC);
11376 t2 = F->getRegInfo().createVirtualRegister(RC);
11377 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t1).addReg(dest1Oper.getReg());
11378 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t2).addReg(dest2Oper.getReg());
11380 t1 = dest1Oper.getReg();
11381 t2 = dest2Oper.getReg();
11384 int valArgIndx = lastAddrIndx + 1;
11385 assert((argOpers[valArgIndx]->isReg() ||
11386 argOpers[valArgIndx]->isImm()) &&
11387 "invalid operand");
11388 unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
11389 unsigned t6 = F->getRegInfo().createVirtualRegister(RC);
11390 if (argOpers[valArgIndx]->isReg())
11391 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5);
11393 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5);
11394 if (regOpcL != X86::MOV32rr)
11396 (*MIB).addOperand(*argOpers[valArgIndx]);
11397 assert(argOpers[valArgIndx + 1]->isReg() ==
11398 argOpers[valArgIndx]->isReg());
11399 assert(argOpers[valArgIndx + 1]->isImm() ==
11400 argOpers[valArgIndx]->isImm());
11401 if (argOpers[valArgIndx + 1]->isReg())
11402 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6);
11404 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6);
11405 if (regOpcH != X86::MOV32rr)
11407 (*MIB).addOperand(*argOpers[valArgIndx + 1]);
11409 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
11411 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EDX);
11414 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EBX);
11416 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::ECX);
11419 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B));
11420 for (int i=0; i <= lastAddrIndx; ++i)
11421 (*MIB).addOperand(*argOpers[i]);
11423 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11424 (*MIB).setMemRefs(bInstr->memoperands_begin(),
11425 bInstr->memoperands_end());
11427 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t3);
11428 MIB.addReg(X86::EAX);
11429 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t4);
11430 MIB.addReg(X86::EDX);
11433 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11435 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
11439 // private utility function
11440 MachineBasicBlock *
11441 X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
11442 MachineBasicBlock *MBB,
11443 unsigned cmovOpc) const {
11444 // For the atomic min/max operator, we generate
11447 // ld t1 = [min/max.addr]
11448 // mov t2 = [min/max.val]
11450 // cmov[cond] t2 = t1
11452 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
11454 // fallthrough -->nextMBB
11456 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11457 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11458 MachineFunction::iterator MBBIter = MBB;
11461 /// First build the CFG
11462 MachineFunction *F = MBB->getParent();
11463 MachineBasicBlock *thisMBB = MBB;
11464 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11465 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11466 F->insert(MBBIter, newMBB);
11467 F->insert(MBBIter, nextMBB);
11469 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11470 nextMBB->splice(nextMBB->begin(), thisMBB,
11471 llvm::next(MachineBasicBlock::iterator(mInstr)),
11473 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11475 // Update thisMBB to fall through to newMBB
11476 thisMBB->addSuccessor(newMBB);
11478 // newMBB jumps to newMBB and fall through to nextMBB
11479 newMBB->addSuccessor(nextMBB);
11480 newMBB->addSuccessor(newMBB);
11482 DebugLoc dl = mInstr->getDebugLoc();
11483 // Insert instructions into newMBB based on incoming instruction
11484 assert(mInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
11485 "unexpected number of operands");
11486 MachineOperand& destOper = mInstr->getOperand(0);
11487 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11488 int numArgs = mInstr->getNumOperands() - 1;
11489 for (int i=0; i < numArgs; ++i)
11490 argOpers[i] = &mInstr->getOperand(i+1);
11492 // x86 address has 4 operands: base, index, scale, and displacement
11493 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11494 int valArgIndx = lastAddrIndx + 1;
11496 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
11497 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1);
11498 for (int i=0; i <= lastAddrIndx; ++i)
11499 (*MIB).addOperand(*argOpers[i]);
11501 // We only support register and immediate values
11502 assert((argOpers[valArgIndx]->isReg() ||
11503 argOpers[valArgIndx]->isImm()) &&
11504 "invalid operand");
11506 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
11507 if (argOpers[valArgIndx]->isReg())
11508 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t2);
11510 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
11511 (*MIB).addOperand(*argOpers[valArgIndx]);
11513 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
11516 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr));
11521 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
11522 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3);
11526 // Cmp and exchange if none has modified the memory location
11527 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32));
11528 for (int i=0; i <= lastAddrIndx; ++i)
11529 (*MIB).addOperand(*argOpers[i]);
11531 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11532 (*MIB).setMemRefs(mInstr->memoperands_begin(),
11533 mInstr->memoperands_end());
11535 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
11536 MIB.addReg(X86::EAX);
11539 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11541 mInstr->eraseFromParent(); // The pseudo instruction is gone now.
11545 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
11546 // or XMM0_V32I8 in AVX all of this code can be replaced with that
11547 // in the .td file.
11548 MachineBasicBlock *
11549 X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB,
11550 unsigned numArgs, bool memArg) const {
11551 assert(Subtarget->hasSSE42orAVX() &&
11552 "Target must have SSE4.2 or AVX features enabled");
11554 DebugLoc dl = MI->getDebugLoc();
11555 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11557 if (!Subtarget->hasAVX()) {
11559 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm;
11561 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr;
11564 Opc = numArgs == 3 ? X86::VPCMPISTRM128rm : X86::VPCMPESTRM128rm;
11566 Opc = numArgs == 3 ? X86::VPCMPISTRM128rr : X86::VPCMPESTRM128rr;
11569 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
11570 for (unsigned i = 0; i < numArgs; ++i) {
11571 MachineOperand &Op = MI->getOperand(i+1);
11572 if (!(Op.isReg() && Op.isImplicit()))
11573 MIB.addOperand(Op);
11575 BuildMI(*BB, MI, dl,
11576 TII->get(Subtarget->hasAVX() ? X86::VMOVAPSrr : X86::MOVAPSrr),
11577 MI->getOperand(0).getReg())
11578 .addReg(X86::XMM0);
11580 MI->eraseFromParent();
11584 MachineBasicBlock *
11585 X86TargetLowering::EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB) const {
11586 DebugLoc dl = MI->getDebugLoc();
11587 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11589 // Address into RAX/EAX, other two args into ECX, EDX.
11590 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
11591 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
11592 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
11593 for (int i = 0; i < X86::AddrNumOperands; ++i)
11594 MIB.addOperand(MI->getOperand(i));
11596 unsigned ValOps = X86::AddrNumOperands;
11597 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
11598 .addReg(MI->getOperand(ValOps).getReg());
11599 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
11600 .addReg(MI->getOperand(ValOps+1).getReg());
11602 // The instruction doesn't actually take any operands though.
11603 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
11605 MI->eraseFromParent(); // The pseudo is gone now.
11609 MachineBasicBlock *
11610 X86TargetLowering::EmitMwait(MachineInstr *MI, MachineBasicBlock *BB) const {
11611 DebugLoc dl = MI->getDebugLoc();
11612 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11614 // First arg in ECX, the second in EAX.
11615 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
11616 .addReg(MI->getOperand(0).getReg());
11617 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EAX)
11618 .addReg(MI->getOperand(1).getReg());
11620 // The instruction doesn't actually take any operands though.
11621 BuildMI(*BB, MI, dl, TII->get(X86::MWAITrr));
11623 MI->eraseFromParent(); // The pseudo is gone now.
11627 MachineBasicBlock *
11628 X86TargetLowering::EmitVAARG64WithCustomInserter(
11630 MachineBasicBlock *MBB) const {
11631 // Emit va_arg instruction on X86-64.
11633 // Operands to this pseudo-instruction:
11634 // 0 ) Output : destination address (reg)
11635 // 1-5) Input : va_list address (addr, i64mem)
11636 // 6 ) ArgSize : Size (in bytes) of vararg type
11637 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
11638 // 8 ) Align : Alignment of type
11639 // 9 ) EFLAGS (implicit-def)
11641 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
11642 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
11644 unsigned DestReg = MI->getOperand(0).getReg();
11645 MachineOperand &Base = MI->getOperand(1);
11646 MachineOperand &Scale = MI->getOperand(2);
11647 MachineOperand &Index = MI->getOperand(3);
11648 MachineOperand &Disp = MI->getOperand(4);
11649 MachineOperand &Segment = MI->getOperand(5);
11650 unsigned ArgSize = MI->getOperand(6).getImm();
11651 unsigned ArgMode = MI->getOperand(7).getImm();
11652 unsigned Align = MI->getOperand(8).getImm();
11654 // Memory Reference
11655 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
11656 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
11657 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
11659 // Machine Information
11660 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11661 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
11662 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
11663 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
11664 DebugLoc DL = MI->getDebugLoc();
11666 // struct va_list {
11669 // i64 overflow_area (address)
11670 // i64 reg_save_area (address)
11672 // sizeof(va_list) = 24
11673 // alignment(va_list) = 8
11675 unsigned TotalNumIntRegs = 6;
11676 unsigned TotalNumXMMRegs = 8;
11677 bool UseGPOffset = (ArgMode == 1);
11678 bool UseFPOffset = (ArgMode == 2);
11679 unsigned MaxOffset = TotalNumIntRegs * 8 +
11680 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
11682 /* Align ArgSize to a multiple of 8 */
11683 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
11684 bool NeedsAlign = (Align > 8);
11686 MachineBasicBlock *thisMBB = MBB;
11687 MachineBasicBlock *overflowMBB;
11688 MachineBasicBlock *offsetMBB;
11689 MachineBasicBlock *endMBB;
11691 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
11692 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
11693 unsigned OffsetReg = 0;
11695 if (!UseGPOffset && !UseFPOffset) {
11696 // If we only pull from the overflow region, we don't create a branch.
11697 // We don't need to alter control flow.
11698 OffsetDestReg = 0; // unused
11699 OverflowDestReg = DestReg;
11702 overflowMBB = thisMBB;
11705 // First emit code to check if gp_offset (or fp_offset) is below the bound.
11706 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
11707 // If not, pull from overflow_area. (branch to overflowMBB)
11712 // offsetMBB overflowMBB
11717 // Registers for the PHI in endMBB
11718 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
11719 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
11721 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11722 MachineFunction *MF = MBB->getParent();
11723 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11724 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11725 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11727 MachineFunction::iterator MBBIter = MBB;
11730 // Insert the new basic blocks
11731 MF->insert(MBBIter, offsetMBB);
11732 MF->insert(MBBIter, overflowMBB);
11733 MF->insert(MBBIter, endMBB);
11735 // Transfer the remainder of MBB and its successor edges to endMBB.
11736 endMBB->splice(endMBB->begin(), thisMBB,
11737 llvm::next(MachineBasicBlock::iterator(MI)),
11739 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11741 // Make offsetMBB and overflowMBB successors of thisMBB
11742 thisMBB->addSuccessor(offsetMBB);
11743 thisMBB->addSuccessor(overflowMBB);
11745 // endMBB is a successor of both offsetMBB and overflowMBB
11746 offsetMBB->addSuccessor(endMBB);
11747 overflowMBB->addSuccessor(endMBB);
11749 // Load the offset value into a register
11750 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
11751 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
11755 .addDisp(Disp, UseFPOffset ? 4 : 0)
11756 .addOperand(Segment)
11757 .setMemRefs(MMOBegin, MMOEnd);
11759 // Check if there is enough room left to pull this argument.
11760 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
11762 .addImm(MaxOffset + 8 - ArgSizeA8);
11764 // Branch to "overflowMBB" if offset >= max
11765 // Fall through to "offsetMBB" otherwise
11766 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
11767 .addMBB(overflowMBB);
11770 // In offsetMBB, emit code to use the reg_save_area.
11772 assert(OffsetReg != 0);
11774 // Read the reg_save_area address.
11775 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
11776 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
11781 .addOperand(Segment)
11782 .setMemRefs(MMOBegin, MMOEnd);
11784 // Zero-extend the offset
11785 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
11786 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
11789 .addImm(X86::sub_32bit);
11791 // Add the offset to the reg_save_area to get the final address.
11792 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
11793 .addReg(OffsetReg64)
11794 .addReg(RegSaveReg);
11796 // Compute the offset for the next argument
11797 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
11798 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
11800 .addImm(UseFPOffset ? 16 : 8);
11802 // Store it back into the va_list.
11803 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
11807 .addDisp(Disp, UseFPOffset ? 4 : 0)
11808 .addOperand(Segment)
11809 .addReg(NextOffsetReg)
11810 .setMemRefs(MMOBegin, MMOEnd);
11813 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
11818 // Emit code to use overflow area
11821 // Load the overflow_area address into a register.
11822 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
11823 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
11828 .addOperand(Segment)
11829 .setMemRefs(MMOBegin, MMOEnd);
11831 // If we need to align it, do so. Otherwise, just copy the address
11832 // to OverflowDestReg.
11834 // Align the overflow address
11835 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
11836 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
11838 // aligned_addr = (addr + (align-1)) & ~(align-1)
11839 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
11840 .addReg(OverflowAddrReg)
11843 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
11845 .addImm(~(uint64_t)(Align-1));
11847 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
11848 .addReg(OverflowAddrReg);
11851 // Compute the next overflow address after this argument.
11852 // (the overflow address should be kept 8-byte aligned)
11853 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
11854 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
11855 .addReg(OverflowDestReg)
11856 .addImm(ArgSizeA8);
11858 // Store the new overflow address.
11859 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
11864 .addOperand(Segment)
11865 .addReg(NextAddrReg)
11866 .setMemRefs(MMOBegin, MMOEnd);
11868 // If we branched, emit the PHI to the front of endMBB.
11870 BuildMI(*endMBB, endMBB->begin(), DL,
11871 TII->get(X86::PHI), DestReg)
11872 .addReg(OffsetDestReg).addMBB(offsetMBB)
11873 .addReg(OverflowDestReg).addMBB(overflowMBB);
11876 // Erase the pseudo instruction
11877 MI->eraseFromParent();
11882 MachineBasicBlock *
11883 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
11885 MachineBasicBlock *MBB) const {
11886 // Emit code to save XMM registers to the stack. The ABI says that the
11887 // number of registers to save is given in %al, so it's theoretically
11888 // possible to do an indirect jump trick to avoid saving all of them,
11889 // however this code takes a simpler approach and just executes all
11890 // of the stores if %al is non-zero. It's less code, and it's probably
11891 // easier on the hardware branch predictor, and stores aren't all that
11892 // expensive anyway.
11894 // Create the new basic blocks. One block contains all the XMM stores,
11895 // and one block is the final destination regardless of whether any
11896 // stores were performed.
11897 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11898 MachineFunction *F = MBB->getParent();
11899 MachineFunction::iterator MBBIter = MBB;
11901 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
11902 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
11903 F->insert(MBBIter, XMMSaveMBB);
11904 F->insert(MBBIter, EndMBB);
11906 // Transfer the remainder of MBB and its successor edges to EndMBB.
11907 EndMBB->splice(EndMBB->begin(), MBB,
11908 llvm::next(MachineBasicBlock::iterator(MI)),
11910 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
11912 // The original block will now fall through to the XMM save block.
11913 MBB->addSuccessor(XMMSaveMBB);
11914 // The XMMSaveMBB will fall through to the end block.
11915 XMMSaveMBB->addSuccessor(EndMBB);
11917 // Now add the instructions.
11918 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11919 DebugLoc DL = MI->getDebugLoc();
11921 unsigned CountReg = MI->getOperand(0).getReg();
11922 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
11923 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
11925 if (!Subtarget->isTargetWin64()) {
11926 // If %al is 0, branch around the XMM save block.
11927 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
11928 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
11929 MBB->addSuccessor(EndMBB);
11932 unsigned MOVOpc = Subtarget->hasAVX() ? X86::VMOVAPSmr : X86::MOVAPSmr;
11933 // In the XMM save block, save all the XMM argument registers.
11934 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
11935 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
11936 MachineMemOperand *MMO =
11937 F->getMachineMemOperand(
11938 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
11939 MachineMemOperand::MOStore,
11940 /*Size=*/16, /*Align=*/16);
11941 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
11942 .addFrameIndex(RegSaveFrameIndex)
11943 .addImm(/*Scale=*/1)
11944 .addReg(/*IndexReg=*/0)
11945 .addImm(/*Disp=*/Offset)
11946 .addReg(/*Segment=*/0)
11947 .addReg(MI->getOperand(i).getReg())
11948 .addMemOperand(MMO);
11951 MI->eraseFromParent(); // The pseudo instruction is gone now.
11956 MachineBasicBlock *
11957 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
11958 MachineBasicBlock *BB) const {
11959 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11960 DebugLoc DL = MI->getDebugLoc();
11962 // To "insert" a SELECT_CC instruction, we actually have to insert the
11963 // diamond control-flow pattern. The incoming instruction knows the
11964 // destination vreg to set, the condition code register to branch on, the
11965 // true/false values to select between, and a branch opcode to use.
11966 const BasicBlock *LLVM_BB = BB->getBasicBlock();
11967 MachineFunction::iterator It = BB;
11973 // cmpTY ccX, r1, r2
11975 // fallthrough --> copy0MBB
11976 MachineBasicBlock *thisMBB = BB;
11977 MachineFunction *F = BB->getParent();
11978 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
11979 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
11980 F->insert(It, copy0MBB);
11981 F->insert(It, sinkMBB);
11983 // If the EFLAGS register isn't dead in the terminator, then claim that it's
11984 // live into the sink and copy blocks.
11985 if (!MI->killsRegister(X86::EFLAGS)) {
11986 copy0MBB->addLiveIn(X86::EFLAGS);
11987 sinkMBB->addLiveIn(X86::EFLAGS);
11990 // Transfer the remainder of BB and its successor edges to sinkMBB.
11991 sinkMBB->splice(sinkMBB->begin(), BB,
11992 llvm::next(MachineBasicBlock::iterator(MI)),
11994 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
11996 // Add the true and fallthrough blocks as its successors.
11997 BB->addSuccessor(copy0MBB);
11998 BB->addSuccessor(sinkMBB);
12000 // Create the conditional branch instruction.
12002 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
12003 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
12006 // %FalseValue = ...
12007 // # fallthrough to sinkMBB
12008 copy0MBB->addSuccessor(sinkMBB);
12011 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
12013 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
12014 TII->get(X86::PHI), MI->getOperand(0).getReg())
12015 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
12016 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
12018 MI->eraseFromParent(); // The pseudo instruction is gone now.
12022 MachineBasicBlock *
12023 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB,
12024 bool Is64Bit) const {
12025 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12026 DebugLoc DL = MI->getDebugLoc();
12027 MachineFunction *MF = BB->getParent();
12028 const BasicBlock *LLVM_BB = BB->getBasicBlock();
12030 assert(getTargetMachine().Options.EnableSegmentedStacks);
12032 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
12033 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30;
12036 // ... [Till the alloca]
12037 // If stacklet is not large enough, jump to mallocMBB
12040 // Allocate by subtracting from RSP
12041 // Jump to continueMBB
12044 // Allocate by call to runtime
12048 // [rest of original BB]
12051 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12052 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12053 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12055 MachineRegisterInfo &MRI = MF->getRegInfo();
12056 const TargetRegisterClass *AddrRegClass =
12057 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32);
12059 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
12060 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
12061 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
12062 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
12063 sizeVReg = MI->getOperand(1).getReg(),
12064 physSPReg = Is64Bit ? X86::RSP : X86::ESP;
12066 MachineFunction::iterator MBBIter = BB;
12069 MF->insert(MBBIter, bumpMBB);
12070 MF->insert(MBBIter, mallocMBB);
12071 MF->insert(MBBIter, continueMBB);
12073 continueMBB->splice(continueMBB->begin(), BB, llvm::next
12074 (MachineBasicBlock::iterator(MI)), BB->end());
12075 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
12077 // Add code to the main basic block to check if the stack limit has been hit,
12078 // and if so, jump to mallocMBB otherwise to bumpMBB.
12079 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
12080 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
12081 .addReg(tmpSPVReg).addReg(sizeVReg);
12082 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr))
12083 .addReg(0).addImm(0).addReg(0).addImm(TlsOffset).addReg(TlsReg)
12084 .addReg(SPLimitVReg);
12085 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
12087 // bumpMBB simply decreases the stack pointer, since we know the current
12088 // stacklet has enough space.
12089 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
12090 .addReg(SPLimitVReg);
12091 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
12092 .addReg(SPLimitVReg);
12093 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
12095 // Calls into a routine in libgcc to allocate more space from the heap.
12097 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
12099 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
12100 .addExternalSymbol("__morestack_allocate_stack_space").addReg(X86::RDI);
12102 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
12104 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
12105 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
12106 .addExternalSymbol("__morestack_allocate_stack_space");
12110 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
12113 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
12114 .addReg(Is64Bit ? X86::RAX : X86::EAX);
12115 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
12117 // Set up the CFG correctly.
12118 BB->addSuccessor(bumpMBB);
12119 BB->addSuccessor(mallocMBB);
12120 mallocMBB->addSuccessor(continueMBB);
12121 bumpMBB->addSuccessor(continueMBB);
12123 // Take care of the PHI nodes.
12124 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
12125 MI->getOperand(0).getReg())
12126 .addReg(mallocPtrVReg).addMBB(mallocMBB)
12127 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
12129 // Delete the original pseudo instruction.
12130 MI->eraseFromParent();
12133 return continueMBB;
12136 MachineBasicBlock *
12137 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
12138 MachineBasicBlock *BB) const {
12139 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12140 DebugLoc DL = MI->getDebugLoc();
12142 assert(!Subtarget->isTargetEnvMacho());
12144 // The lowering is pretty easy: we're just emitting the call to _alloca. The
12145 // non-trivial part is impdef of ESP.
12147 if (Subtarget->isTargetWin64()) {
12148 if (Subtarget->isTargetCygMing()) {
12149 // ___chkstk(Mingw64):
12150 // Clobbers R10, R11, RAX and EFLAGS.
12152 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
12153 .addExternalSymbol("___chkstk")
12154 .addReg(X86::RAX, RegState::Implicit)
12155 .addReg(X86::RSP, RegState::Implicit)
12156 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
12157 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
12158 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
12160 // __chkstk(MSVCRT): does not update stack pointer.
12161 // Clobbers R10, R11 and EFLAGS.
12162 // FIXME: RAX(allocated size) might be reused and not killed.
12163 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
12164 .addExternalSymbol("__chkstk")
12165 .addReg(X86::RAX, RegState::Implicit)
12166 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
12167 // RAX has the offset to subtracted from RSP.
12168 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
12173 const char *StackProbeSymbol =
12174 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca";
12176 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
12177 .addExternalSymbol(StackProbeSymbol)
12178 .addReg(X86::EAX, RegState::Implicit)
12179 .addReg(X86::ESP, RegState::Implicit)
12180 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
12181 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
12182 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
12185 MI->eraseFromParent(); // The pseudo instruction is gone now.
12189 MachineBasicBlock *
12190 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
12191 MachineBasicBlock *BB) const {
12192 // This is pretty easy. We're taking the value that we received from
12193 // our load from the relocation, sticking it in either RDI (x86-64)
12194 // or EAX and doing an indirect call. The return value will then
12195 // be in the normal return register.
12196 const X86InstrInfo *TII
12197 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo());
12198 DebugLoc DL = MI->getDebugLoc();
12199 MachineFunction *F = BB->getParent();
12201 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
12202 assert(MI->getOperand(3).isGlobal() && "This should be a global");
12204 if (Subtarget->is64Bit()) {
12205 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
12206 TII->get(X86::MOV64rm), X86::RDI)
12208 .addImm(0).addReg(0)
12209 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
12210 MI->getOperand(3).getTargetFlags())
12212 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
12213 addDirectMem(MIB, X86::RDI);
12214 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
12215 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
12216 TII->get(X86::MOV32rm), X86::EAX)
12218 .addImm(0).addReg(0)
12219 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
12220 MI->getOperand(3).getTargetFlags())
12222 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
12223 addDirectMem(MIB, X86::EAX);
12225 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
12226 TII->get(X86::MOV32rm), X86::EAX)
12227 .addReg(TII->getGlobalBaseReg(F))
12228 .addImm(0).addReg(0)
12229 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
12230 MI->getOperand(3).getTargetFlags())
12232 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
12233 addDirectMem(MIB, X86::EAX);
12236 MI->eraseFromParent(); // The pseudo instruction is gone now.
12240 MachineBasicBlock *
12241 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
12242 MachineBasicBlock *BB) const {
12243 switch (MI->getOpcode()) {
12244 default: assert(0 && "Unexpected instr type to insert");
12245 case X86::TAILJMPd64:
12246 case X86::TAILJMPr64:
12247 case X86::TAILJMPm64:
12248 assert(0 && "TAILJMP64 would not be touched here.");
12249 case X86::TCRETURNdi64:
12250 case X86::TCRETURNri64:
12251 case X86::TCRETURNmi64:
12252 // Defs of TCRETURNxx64 has Win64's callee-saved registers, as subset.
12253 // On AMD64, additional defs should be added before register allocation.
12254 if (!Subtarget->isTargetWin64()) {
12255 MI->addRegisterDefined(X86::RSI);
12256 MI->addRegisterDefined(X86::RDI);
12257 MI->addRegisterDefined(X86::XMM6);
12258 MI->addRegisterDefined(X86::XMM7);
12259 MI->addRegisterDefined(X86::XMM8);
12260 MI->addRegisterDefined(X86::XMM9);
12261 MI->addRegisterDefined(X86::XMM10);
12262 MI->addRegisterDefined(X86::XMM11);
12263 MI->addRegisterDefined(X86::XMM12);
12264 MI->addRegisterDefined(X86::XMM13);
12265 MI->addRegisterDefined(X86::XMM14);
12266 MI->addRegisterDefined(X86::XMM15);
12269 case X86::WIN_ALLOCA:
12270 return EmitLoweredWinAlloca(MI, BB);
12271 case X86::SEG_ALLOCA_32:
12272 return EmitLoweredSegAlloca(MI, BB, false);
12273 case X86::SEG_ALLOCA_64:
12274 return EmitLoweredSegAlloca(MI, BB, true);
12275 case X86::TLSCall_32:
12276 case X86::TLSCall_64:
12277 return EmitLoweredTLSCall(MI, BB);
12278 case X86::CMOV_GR8:
12279 case X86::CMOV_FR32:
12280 case X86::CMOV_FR64:
12281 case X86::CMOV_V4F32:
12282 case X86::CMOV_V2F64:
12283 case X86::CMOV_V2I64:
12284 case X86::CMOV_V8F32:
12285 case X86::CMOV_V4F64:
12286 case X86::CMOV_V4I64:
12287 case X86::CMOV_GR16:
12288 case X86::CMOV_GR32:
12289 case X86::CMOV_RFP32:
12290 case X86::CMOV_RFP64:
12291 case X86::CMOV_RFP80:
12292 return EmitLoweredSelect(MI, BB);
12294 case X86::FP32_TO_INT16_IN_MEM:
12295 case X86::FP32_TO_INT32_IN_MEM:
12296 case X86::FP32_TO_INT64_IN_MEM:
12297 case X86::FP64_TO_INT16_IN_MEM:
12298 case X86::FP64_TO_INT32_IN_MEM:
12299 case X86::FP64_TO_INT64_IN_MEM:
12300 case X86::FP80_TO_INT16_IN_MEM:
12301 case X86::FP80_TO_INT32_IN_MEM:
12302 case X86::FP80_TO_INT64_IN_MEM: {
12303 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12304 DebugLoc DL = MI->getDebugLoc();
12306 // Change the floating point control register to use "round towards zero"
12307 // mode when truncating to an integer value.
12308 MachineFunction *F = BB->getParent();
12309 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
12310 addFrameReference(BuildMI(*BB, MI, DL,
12311 TII->get(X86::FNSTCW16m)), CWFrameIdx);
12313 // Load the old value of the high byte of the control word...
12315 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass);
12316 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
12319 // Set the high part to be round to zero...
12320 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
12323 // Reload the modified control word now...
12324 addFrameReference(BuildMI(*BB, MI, DL,
12325 TII->get(X86::FLDCW16m)), CWFrameIdx);
12327 // Restore the memory image of control word to original value
12328 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
12331 // Get the X86 opcode to use.
12333 switch (MI->getOpcode()) {
12334 default: llvm_unreachable("illegal opcode!");
12335 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
12336 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
12337 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
12338 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
12339 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
12340 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
12341 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
12342 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
12343 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
12347 MachineOperand &Op = MI->getOperand(0);
12349 AM.BaseType = X86AddressMode::RegBase;
12350 AM.Base.Reg = Op.getReg();
12352 AM.BaseType = X86AddressMode::FrameIndexBase;
12353 AM.Base.FrameIndex = Op.getIndex();
12355 Op = MI->getOperand(1);
12357 AM.Scale = Op.getImm();
12358 Op = MI->getOperand(2);
12360 AM.IndexReg = Op.getImm();
12361 Op = MI->getOperand(3);
12362 if (Op.isGlobal()) {
12363 AM.GV = Op.getGlobal();
12365 AM.Disp = Op.getImm();
12367 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
12368 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
12370 // Reload the original control word now.
12371 addFrameReference(BuildMI(*BB, MI, DL,
12372 TII->get(X86::FLDCW16m)), CWFrameIdx);
12374 MI->eraseFromParent(); // The pseudo instruction is gone now.
12377 // String/text processing lowering.
12378 case X86::PCMPISTRM128REG:
12379 case X86::VPCMPISTRM128REG:
12380 return EmitPCMP(MI, BB, 3, false /* in-mem */);
12381 case X86::PCMPISTRM128MEM:
12382 case X86::VPCMPISTRM128MEM:
12383 return EmitPCMP(MI, BB, 3, true /* in-mem */);
12384 case X86::PCMPESTRM128REG:
12385 case X86::VPCMPESTRM128REG:
12386 return EmitPCMP(MI, BB, 5, false /* in mem */);
12387 case X86::PCMPESTRM128MEM:
12388 case X86::VPCMPESTRM128MEM:
12389 return EmitPCMP(MI, BB, 5, true /* in mem */);
12391 // Thread synchronization.
12393 return EmitMonitor(MI, BB);
12395 return EmitMwait(MI, BB);
12397 // Atomic Lowering.
12398 case X86::ATOMAND32:
12399 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
12400 X86::AND32ri, X86::MOV32rm,
12402 X86::NOT32r, X86::EAX,
12403 X86::GR32RegisterClass);
12404 case X86::ATOMOR32:
12405 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
12406 X86::OR32ri, X86::MOV32rm,
12408 X86::NOT32r, X86::EAX,
12409 X86::GR32RegisterClass);
12410 case X86::ATOMXOR32:
12411 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
12412 X86::XOR32ri, X86::MOV32rm,
12414 X86::NOT32r, X86::EAX,
12415 X86::GR32RegisterClass);
12416 case X86::ATOMNAND32:
12417 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
12418 X86::AND32ri, X86::MOV32rm,
12420 X86::NOT32r, X86::EAX,
12421 X86::GR32RegisterClass, true);
12422 case X86::ATOMMIN32:
12423 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
12424 case X86::ATOMMAX32:
12425 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
12426 case X86::ATOMUMIN32:
12427 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
12428 case X86::ATOMUMAX32:
12429 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
12431 case X86::ATOMAND16:
12432 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
12433 X86::AND16ri, X86::MOV16rm,
12435 X86::NOT16r, X86::AX,
12436 X86::GR16RegisterClass);
12437 case X86::ATOMOR16:
12438 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
12439 X86::OR16ri, X86::MOV16rm,
12441 X86::NOT16r, X86::AX,
12442 X86::GR16RegisterClass);
12443 case X86::ATOMXOR16:
12444 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr,
12445 X86::XOR16ri, X86::MOV16rm,
12447 X86::NOT16r, X86::AX,
12448 X86::GR16RegisterClass);
12449 case X86::ATOMNAND16:
12450 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
12451 X86::AND16ri, X86::MOV16rm,
12453 X86::NOT16r, X86::AX,
12454 X86::GR16RegisterClass, true);
12455 case X86::ATOMMIN16:
12456 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr);
12457 case X86::ATOMMAX16:
12458 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr);
12459 case X86::ATOMUMIN16:
12460 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr);
12461 case X86::ATOMUMAX16:
12462 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr);
12464 case X86::ATOMAND8:
12465 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
12466 X86::AND8ri, X86::MOV8rm,
12468 X86::NOT8r, X86::AL,
12469 X86::GR8RegisterClass);
12471 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
12472 X86::OR8ri, X86::MOV8rm,
12474 X86::NOT8r, X86::AL,
12475 X86::GR8RegisterClass);
12476 case X86::ATOMXOR8:
12477 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr,
12478 X86::XOR8ri, X86::MOV8rm,
12480 X86::NOT8r, X86::AL,
12481 X86::GR8RegisterClass);
12482 case X86::ATOMNAND8:
12483 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
12484 X86::AND8ri, X86::MOV8rm,
12486 X86::NOT8r, X86::AL,
12487 X86::GR8RegisterClass, true);
12488 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
12489 // This group is for 64-bit host.
12490 case X86::ATOMAND64:
12491 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
12492 X86::AND64ri32, X86::MOV64rm,
12494 X86::NOT64r, X86::RAX,
12495 X86::GR64RegisterClass);
12496 case X86::ATOMOR64:
12497 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
12498 X86::OR64ri32, X86::MOV64rm,
12500 X86::NOT64r, X86::RAX,
12501 X86::GR64RegisterClass);
12502 case X86::ATOMXOR64:
12503 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr,
12504 X86::XOR64ri32, X86::MOV64rm,
12506 X86::NOT64r, X86::RAX,
12507 X86::GR64RegisterClass);
12508 case X86::ATOMNAND64:
12509 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
12510 X86::AND64ri32, X86::MOV64rm,
12512 X86::NOT64r, X86::RAX,
12513 X86::GR64RegisterClass, true);
12514 case X86::ATOMMIN64:
12515 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr);
12516 case X86::ATOMMAX64:
12517 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr);
12518 case X86::ATOMUMIN64:
12519 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr);
12520 case X86::ATOMUMAX64:
12521 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr);
12523 // This group does 64-bit operations on a 32-bit host.
12524 case X86::ATOMAND6432:
12525 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12526 X86::AND32rr, X86::AND32rr,
12527 X86::AND32ri, X86::AND32ri,
12529 case X86::ATOMOR6432:
12530 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12531 X86::OR32rr, X86::OR32rr,
12532 X86::OR32ri, X86::OR32ri,
12534 case X86::ATOMXOR6432:
12535 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12536 X86::XOR32rr, X86::XOR32rr,
12537 X86::XOR32ri, X86::XOR32ri,
12539 case X86::ATOMNAND6432:
12540 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12541 X86::AND32rr, X86::AND32rr,
12542 X86::AND32ri, X86::AND32ri,
12544 case X86::ATOMADD6432:
12545 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12546 X86::ADD32rr, X86::ADC32rr,
12547 X86::ADD32ri, X86::ADC32ri,
12549 case X86::ATOMSUB6432:
12550 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12551 X86::SUB32rr, X86::SBB32rr,
12552 X86::SUB32ri, X86::SBB32ri,
12554 case X86::ATOMSWAP6432:
12555 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12556 X86::MOV32rr, X86::MOV32rr,
12557 X86::MOV32ri, X86::MOV32ri,
12559 case X86::VASTART_SAVE_XMM_REGS:
12560 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
12562 case X86::VAARG_64:
12563 return EmitVAARG64WithCustomInserter(MI, BB);
12567 //===----------------------------------------------------------------------===//
12568 // X86 Optimization Hooks
12569 //===----------------------------------------------------------------------===//
12571 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
12575 const SelectionDAG &DAG,
12576 unsigned Depth) const {
12577 unsigned Opc = Op.getOpcode();
12578 assert((Opc >= ISD::BUILTIN_OP_END ||
12579 Opc == ISD::INTRINSIC_WO_CHAIN ||
12580 Opc == ISD::INTRINSIC_W_CHAIN ||
12581 Opc == ISD::INTRINSIC_VOID) &&
12582 "Should use MaskedValueIsZero if you don't know whether Op"
12583 " is a target node!");
12585 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything.
12599 // These nodes' second result is a boolean.
12600 if (Op.getResNo() == 0)
12603 case X86ISD::SETCC:
12604 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(),
12605 Mask.getBitWidth() - 1);
12607 case ISD::INTRINSIC_WO_CHAIN: {
12608 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
12609 unsigned NumLoBits = 0;
12612 case Intrinsic::x86_sse_movmsk_ps:
12613 case Intrinsic::x86_avx_movmsk_ps_256:
12614 case Intrinsic::x86_sse2_movmsk_pd:
12615 case Intrinsic::x86_avx_movmsk_pd_256:
12616 case Intrinsic::x86_mmx_pmovmskb:
12617 case Intrinsic::x86_sse2_pmovmskb_128:
12618 case Intrinsic::x86_avx2_pmovmskb: {
12619 // High bits of movmskp{s|d}, pmovmskb are known zero.
12621 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
12622 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
12623 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
12624 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
12625 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
12626 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
12627 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
12629 KnownZero = APInt::getHighBitsSet(Mask.getBitWidth(),
12630 Mask.getBitWidth() - NumLoBits);
12639 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
12640 unsigned Depth) const {
12641 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
12642 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
12643 return Op.getValueType().getScalarType().getSizeInBits();
12649 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
12650 /// node is a GlobalAddress + offset.
12651 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
12652 const GlobalValue* &GA,
12653 int64_t &Offset) const {
12654 if (N->getOpcode() == X86ISD::Wrapper) {
12655 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
12656 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
12657 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
12661 return TargetLowering::isGAPlusOffset(N, GA, Offset);
12664 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
12665 /// same as extracting the high 128-bit part of 256-bit vector and then
12666 /// inserting the result into the low part of a new 256-bit vector
12667 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
12668 EVT VT = SVOp->getValueType(0);
12669 int NumElems = VT.getVectorNumElements();
12671 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
12672 for (int i = 0, j = NumElems/2; i < NumElems/2; ++i, ++j)
12673 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
12674 SVOp->getMaskElt(j) >= 0)
12680 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
12681 /// same as extracting the low 128-bit part of 256-bit vector and then
12682 /// inserting the result into the high part of a new 256-bit vector
12683 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
12684 EVT VT = SVOp->getValueType(0);
12685 int NumElems = VT.getVectorNumElements();
12687 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
12688 for (int i = NumElems/2, j = 0; i < NumElems; ++i, ++j)
12689 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
12690 SVOp->getMaskElt(j) >= 0)
12696 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
12697 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
12698 TargetLowering::DAGCombinerInfo &DCI) {
12699 DebugLoc dl = N->getDebugLoc();
12700 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
12701 SDValue V1 = SVOp->getOperand(0);
12702 SDValue V2 = SVOp->getOperand(1);
12703 EVT VT = SVOp->getValueType(0);
12704 int NumElems = VT.getVectorNumElements();
12706 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
12707 V2.getOpcode() == ISD::CONCAT_VECTORS) {
12711 // V UNDEF BUILD_VECTOR UNDEF
12713 // CONCAT_VECTOR CONCAT_VECTOR
12716 // RESULT: V + zero extended
12718 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
12719 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
12720 V1.getOperand(1).getOpcode() != ISD::UNDEF)
12723 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
12726 // To match the shuffle mask, the first half of the mask should
12727 // be exactly the first vector, and all the rest a splat with the
12728 // first element of the second one.
12729 for (int i = 0; i < NumElems/2; ++i)
12730 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
12731 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
12734 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
12735 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
12736 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
12737 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
12739 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2,
12741 Ld->getPointerInfo(),
12742 Ld->getAlignment(),
12743 false/*isVolatile*/, true/*ReadMem*/,
12744 false/*WriteMem*/);
12745 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
12748 // Emit a zeroed vector and insert the desired subvector on its
12750 SDValue Zeros = getZeroVector(VT, true /* HasXMMInt */, DAG, dl);
12751 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0),
12752 DAG.getConstant(0, MVT::i32), DAG, dl);
12753 return DCI.CombineTo(N, InsV);
12756 //===--------------------------------------------------------------------===//
12757 // Combine some shuffles into subvector extracts and inserts:
12760 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
12761 if (isShuffleHigh128VectorInsertLow(SVOp)) {
12762 SDValue V = Extract128BitVector(V1, DAG.getConstant(NumElems/2, MVT::i32),
12764 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT),
12765 V, DAG.getConstant(0, MVT::i32), DAG, dl);
12766 return DCI.CombineTo(N, InsV);
12769 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
12770 if (isShuffleLow128VectorInsertHigh(SVOp)) {
12771 SDValue V = Extract128BitVector(V1, DAG.getConstant(0, MVT::i32), DAG, dl);
12772 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT),
12773 V, DAG.getConstant(NumElems/2, MVT::i32), DAG, dl);
12774 return DCI.CombineTo(N, InsV);
12780 /// PerformShuffleCombine - Performs several different shuffle combines.
12781 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
12782 TargetLowering::DAGCombinerInfo &DCI,
12783 const X86Subtarget *Subtarget) {
12784 DebugLoc dl = N->getDebugLoc();
12785 EVT VT = N->getValueType(0);
12787 // Don't create instructions with illegal types after legalize types has run.
12788 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12789 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
12792 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
12793 if (Subtarget->hasAVX() && VT.getSizeInBits() == 256 &&
12794 N->getOpcode() == ISD::VECTOR_SHUFFLE)
12795 return PerformShuffleCombine256(N, DAG, DCI);
12797 // Only handle 128 wide vector from here on.
12798 if (VT.getSizeInBits() != 128)
12801 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
12802 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
12803 // consecutive, non-overlapping, and in the right order.
12804 SmallVector<SDValue, 16> Elts;
12805 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
12806 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
12808 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG);
12811 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
12812 /// generation and convert it from being a bunch of shuffles and extracts
12813 /// to a simple store and scalar loads to extract the elements.
12814 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
12815 const TargetLowering &TLI) {
12816 SDValue InputVector = N->getOperand(0);
12818 // Only operate on vectors of 4 elements, where the alternative shuffling
12819 // gets to be more expensive.
12820 if (InputVector.getValueType() != MVT::v4i32)
12823 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
12824 // single use which is a sign-extend or zero-extend, and all elements are
12826 SmallVector<SDNode *, 4> Uses;
12827 unsigned ExtractedElements = 0;
12828 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
12829 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
12830 if (UI.getUse().getResNo() != InputVector.getResNo())
12833 SDNode *Extract = *UI;
12834 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
12837 if (Extract->getValueType(0) != MVT::i32)
12839 if (!Extract->hasOneUse())
12841 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
12842 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
12844 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
12847 // Record which element was extracted.
12848 ExtractedElements |=
12849 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
12851 Uses.push_back(Extract);
12854 // If not all the elements were used, this may not be worthwhile.
12855 if (ExtractedElements != 15)
12858 // Ok, we've now decided to do the transformation.
12859 DebugLoc dl = InputVector.getDebugLoc();
12861 // Store the value to a temporary stack slot.
12862 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
12863 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
12864 MachinePointerInfo(), false, false, 0);
12866 // Replace each use (extract) with a load of the appropriate element.
12867 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
12868 UE = Uses.end(); UI != UE; ++UI) {
12869 SDNode *Extract = *UI;
12871 // cOMpute the element's address.
12872 SDValue Idx = Extract->getOperand(1);
12874 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
12875 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
12876 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
12878 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
12879 StackPtr, OffsetVal);
12881 // Load the scalar.
12882 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
12883 ScalarAddr, MachinePointerInfo(),
12884 false, false, false, 0);
12886 // Replace the exact with the load.
12887 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
12890 // The replacement was made in place; don't return anything.
12894 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
12896 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
12897 const X86Subtarget *Subtarget) {
12898 DebugLoc DL = N->getDebugLoc();
12899 SDValue Cond = N->getOperand(0);
12900 // Get the LHS/RHS of the select.
12901 SDValue LHS = N->getOperand(1);
12902 SDValue RHS = N->getOperand(2);
12903 EVT VT = LHS.getValueType();
12905 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
12906 // instructions match the semantics of the common C idiom x<y?x:y but not
12907 // x<=y?x:y, because of how they handle negative zero (which can be
12908 // ignored in unsafe-math mode).
12909 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
12910 VT != MVT::f80 && DAG.getTargetLoweringInfo().isTypeLegal(VT) &&
12911 (Subtarget->hasXMMInt() ||
12912 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
12913 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
12915 unsigned Opcode = 0;
12916 // Check for x CC y ? x : y.
12917 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
12918 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
12922 // Converting this to a min would handle NaNs incorrectly, and swapping
12923 // the operands would cause it to handle comparisons between positive
12924 // and negative zero incorrectly.
12925 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
12926 if (!DAG.getTarget().Options.UnsafeFPMath &&
12927 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
12929 std::swap(LHS, RHS);
12931 Opcode = X86ISD::FMIN;
12934 // Converting this to a min would handle comparisons between positive
12935 // and negative zero incorrectly.
12936 if (!DAG.getTarget().Options.UnsafeFPMath &&
12937 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
12939 Opcode = X86ISD::FMIN;
12942 // Converting this to a min would handle both negative zeros and NaNs
12943 // incorrectly, but we can swap the operands to fix both.
12944 std::swap(LHS, RHS);
12948 Opcode = X86ISD::FMIN;
12952 // Converting this to a max would handle comparisons between positive
12953 // and negative zero incorrectly.
12954 if (!DAG.getTarget().Options.UnsafeFPMath &&
12955 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
12957 Opcode = X86ISD::FMAX;
12960 // Converting this to a max would handle NaNs incorrectly, and swapping
12961 // the operands would cause it to handle comparisons between positive
12962 // and negative zero incorrectly.
12963 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
12964 if (!DAG.getTarget().Options.UnsafeFPMath &&
12965 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
12967 std::swap(LHS, RHS);
12969 Opcode = X86ISD::FMAX;
12972 // Converting this to a max would handle both negative zeros and NaNs
12973 // incorrectly, but we can swap the operands to fix both.
12974 std::swap(LHS, RHS);
12978 Opcode = X86ISD::FMAX;
12981 // Check for x CC y ? y : x -- a min/max with reversed arms.
12982 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
12983 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
12987 // Converting this to a min would handle comparisons between positive
12988 // and negative zero incorrectly, and swapping the operands would
12989 // cause it to handle NaNs incorrectly.
12990 if (!DAG.getTarget().Options.UnsafeFPMath &&
12991 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
12992 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
12994 std::swap(LHS, RHS);
12996 Opcode = X86ISD::FMIN;
12999 // Converting this to a min would handle NaNs incorrectly.
13000 if (!DAG.getTarget().Options.UnsafeFPMath &&
13001 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
13003 Opcode = X86ISD::FMIN;
13006 // Converting this to a min would handle both negative zeros and NaNs
13007 // incorrectly, but we can swap the operands to fix both.
13008 std::swap(LHS, RHS);
13012 Opcode = X86ISD::FMIN;
13016 // Converting this to a max would handle NaNs incorrectly.
13017 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
13019 Opcode = X86ISD::FMAX;
13022 // Converting this to a max would handle comparisons between positive
13023 // and negative zero incorrectly, and swapping the operands would
13024 // cause it to handle NaNs incorrectly.
13025 if (!DAG.getTarget().Options.UnsafeFPMath &&
13026 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
13027 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
13029 std::swap(LHS, RHS);
13031 Opcode = X86ISD::FMAX;
13034 // Converting this to a max would handle both negative zeros and NaNs
13035 // incorrectly, but we can swap the operands to fix both.
13036 std::swap(LHS, RHS);
13040 Opcode = X86ISD::FMAX;
13046 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
13049 // If this is a select between two integer constants, try to do some
13051 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
13052 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
13053 // Don't do this for crazy integer types.
13054 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
13055 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
13056 // so that TrueC (the true value) is larger than FalseC.
13057 bool NeedsCondInvert = false;
13059 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
13060 // Efficiently invertible.
13061 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
13062 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
13063 isa<ConstantSDNode>(Cond.getOperand(1))))) {
13064 NeedsCondInvert = true;
13065 std::swap(TrueC, FalseC);
13068 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
13069 if (FalseC->getAPIntValue() == 0 &&
13070 TrueC->getAPIntValue().isPowerOf2()) {
13071 if (NeedsCondInvert) // Invert the condition if needed.
13072 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
13073 DAG.getConstant(1, Cond.getValueType()));
13075 // Zero extend the condition if needed.
13076 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
13078 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
13079 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
13080 DAG.getConstant(ShAmt, MVT::i8));
13083 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
13084 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
13085 if (NeedsCondInvert) // Invert the condition if needed.
13086 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
13087 DAG.getConstant(1, Cond.getValueType()));
13089 // Zero extend the condition if needed.
13090 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
13091 FalseC->getValueType(0), Cond);
13092 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13093 SDValue(FalseC, 0));
13096 // Optimize cases that will turn into an LEA instruction. This requires
13097 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
13098 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
13099 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
13100 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
13102 bool isFastMultiplier = false;
13104 switch ((unsigned char)Diff) {
13106 case 1: // result = add base, cond
13107 case 2: // result = lea base( , cond*2)
13108 case 3: // result = lea base(cond, cond*2)
13109 case 4: // result = lea base( , cond*4)
13110 case 5: // result = lea base(cond, cond*4)
13111 case 8: // result = lea base( , cond*8)
13112 case 9: // result = lea base(cond, cond*8)
13113 isFastMultiplier = true;
13118 if (isFastMultiplier) {
13119 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
13120 if (NeedsCondInvert) // Invert the condition if needed.
13121 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
13122 DAG.getConstant(1, Cond.getValueType()));
13124 // Zero extend the condition if needed.
13125 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
13127 // Scale the condition by the difference.
13129 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
13130 DAG.getConstant(Diff, Cond.getValueType()));
13132 // Add the base if non-zero.
13133 if (FalseC->getAPIntValue() != 0)
13134 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13135 SDValue(FalseC, 0));
13145 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
13146 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
13147 TargetLowering::DAGCombinerInfo &DCI) {
13148 DebugLoc DL = N->getDebugLoc();
13150 // If the flag operand isn't dead, don't touch this CMOV.
13151 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
13154 SDValue FalseOp = N->getOperand(0);
13155 SDValue TrueOp = N->getOperand(1);
13156 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
13157 SDValue Cond = N->getOperand(3);
13158 if (CC == X86::COND_E || CC == X86::COND_NE) {
13159 switch (Cond.getOpcode()) {
13163 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
13164 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
13165 return (CC == X86::COND_E) ? FalseOp : TrueOp;
13169 // If this is a select between two integer constants, try to do some
13170 // optimizations. Note that the operands are ordered the opposite of SELECT
13172 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
13173 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
13174 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
13175 // larger than FalseC (the false value).
13176 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
13177 CC = X86::GetOppositeBranchCondition(CC);
13178 std::swap(TrueC, FalseC);
13181 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
13182 // This is efficient for any integer data type (including i8/i16) and
13184 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
13185 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13186 DAG.getConstant(CC, MVT::i8), Cond);
13188 // Zero extend the condition if needed.
13189 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
13191 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
13192 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
13193 DAG.getConstant(ShAmt, MVT::i8));
13194 if (N->getNumValues() == 2) // Dead flag value?
13195 return DCI.CombineTo(N, Cond, SDValue());
13199 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
13200 // for any integer data type, including i8/i16.
13201 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
13202 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13203 DAG.getConstant(CC, MVT::i8), Cond);
13205 // Zero extend the condition if needed.
13206 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
13207 FalseC->getValueType(0), Cond);
13208 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13209 SDValue(FalseC, 0));
13211 if (N->getNumValues() == 2) // Dead flag value?
13212 return DCI.CombineTo(N, Cond, SDValue());
13216 // Optimize cases that will turn into an LEA instruction. This requires
13217 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
13218 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
13219 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
13220 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
13222 bool isFastMultiplier = false;
13224 switch ((unsigned char)Diff) {
13226 case 1: // result = add base, cond
13227 case 2: // result = lea base( , cond*2)
13228 case 3: // result = lea base(cond, cond*2)
13229 case 4: // result = lea base( , cond*4)
13230 case 5: // result = lea base(cond, cond*4)
13231 case 8: // result = lea base( , cond*8)
13232 case 9: // result = lea base(cond, cond*8)
13233 isFastMultiplier = true;
13238 if (isFastMultiplier) {
13239 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
13240 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13241 DAG.getConstant(CC, MVT::i8), Cond);
13242 // Zero extend the condition if needed.
13243 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
13245 // Scale the condition by the difference.
13247 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
13248 DAG.getConstant(Diff, Cond.getValueType()));
13250 // Add the base if non-zero.
13251 if (FalseC->getAPIntValue() != 0)
13252 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13253 SDValue(FalseC, 0));
13254 if (N->getNumValues() == 2) // Dead flag value?
13255 return DCI.CombineTo(N, Cond, SDValue());
13265 /// PerformMulCombine - Optimize a single multiply with constant into two
13266 /// in order to implement it with two cheaper instructions, e.g.
13267 /// LEA + SHL, LEA + LEA.
13268 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
13269 TargetLowering::DAGCombinerInfo &DCI) {
13270 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
13273 EVT VT = N->getValueType(0);
13274 if (VT != MVT::i64)
13277 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
13280 uint64_t MulAmt = C->getZExtValue();
13281 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
13284 uint64_t MulAmt1 = 0;
13285 uint64_t MulAmt2 = 0;
13286 if ((MulAmt % 9) == 0) {
13288 MulAmt2 = MulAmt / 9;
13289 } else if ((MulAmt % 5) == 0) {
13291 MulAmt2 = MulAmt / 5;
13292 } else if ((MulAmt % 3) == 0) {
13294 MulAmt2 = MulAmt / 3;
13297 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
13298 DebugLoc DL = N->getDebugLoc();
13300 if (isPowerOf2_64(MulAmt2) &&
13301 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
13302 // If second multiplifer is pow2, issue it first. We want the multiply by
13303 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
13305 std::swap(MulAmt1, MulAmt2);
13308 if (isPowerOf2_64(MulAmt1))
13309 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
13310 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
13312 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
13313 DAG.getConstant(MulAmt1, VT));
13315 if (isPowerOf2_64(MulAmt2))
13316 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
13317 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
13319 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
13320 DAG.getConstant(MulAmt2, VT));
13322 // Do not add new nodes to DAG combiner worklist.
13323 DCI.CombineTo(N, NewMul, false);
13328 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
13329 SDValue N0 = N->getOperand(0);
13330 SDValue N1 = N->getOperand(1);
13331 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
13332 EVT VT = N0.getValueType();
13334 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
13335 // since the result of setcc_c is all zero's or all ones.
13336 if (VT.isInteger() && !VT.isVector() &&
13337 N1C && N0.getOpcode() == ISD::AND &&
13338 N0.getOperand(1).getOpcode() == ISD::Constant) {
13339 SDValue N00 = N0.getOperand(0);
13340 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
13341 ((N00.getOpcode() == ISD::ANY_EXTEND ||
13342 N00.getOpcode() == ISD::ZERO_EXTEND) &&
13343 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
13344 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
13345 APInt ShAmt = N1C->getAPIntValue();
13346 Mask = Mask.shl(ShAmt);
13348 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
13349 N00, DAG.getConstant(Mask, VT));
13354 // Hardware support for vector shifts is sparse which makes us scalarize the
13355 // vector operations in many cases. Also, on sandybridge ADD is faster than
13357 // (shl V, 1) -> add V,V
13358 if (isSplatVector(N1.getNode())) {
13359 assert(N0.getValueType().isVector() && "Invalid vector shift type");
13360 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1->getOperand(0));
13361 // We shift all of the values by one. In many cases we do not have
13362 // hardware support for this operation. This is better expressed as an ADD
13364 if (N1C && (1 == N1C->getZExtValue())) {
13365 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, N0);
13372 /// PerformShiftCombine - Transforms vector shift nodes to use vector shifts
13374 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
13375 const X86Subtarget *Subtarget) {
13376 EVT VT = N->getValueType(0);
13377 if (N->getOpcode() == ISD::SHL) {
13378 SDValue V = PerformSHLCombine(N, DAG);
13379 if (V.getNode()) return V;
13382 // On X86 with SSE2 support, we can transform this to a vector shift if
13383 // all elements are shifted by the same amount. We can't do this in legalize
13384 // because the a constant vector is typically transformed to a constant pool
13385 // so we have no knowledge of the shift amount.
13386 if (!Subtarget->hasXMMInt())
13389 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
13390 (!Subtarget->hasAVX2() ||
13391 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
13394 SDValue ShAmtOp = N->getOperand(1);
13395 EVT EltVT = VT.getVectorElementType();
13396 DebugLoc DL = N->getDebugLoc();
13397 SDValue BaseShAmt = SDValue();
13398 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
13399 unsigned NumElts = VT.getVectorNumElements();
13401 for (; i != NumElts; ++i) {
13402 SDValue Arg = ShAmtOp.getOperand(i);
13403 if (Arg.getOpcode() == ISD::UNDEF) continue;
13407 for (; i != NumElts; ++i) {
13408 SDValue Arg = ShAmtOp.getOperand(i);
13409 if (Arg.getOpcode() == ISD::UNDEF) continue;
13410 if (Arg != BaseShAmt) {
13414 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
13415 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) {
13416 SDValue InVec = ShAmtOp.getOperand(0);
13417 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
13418 unsigned NumElts = InVec.getValueType().getVectorNumElements();
13420 for (; i != NumElts; ++i) {
13421 SDValue Arg = InVec.getOperand(i);
13422 if (Arg.getOpcode() == ISD::UNDEF) continue;
13426 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
13427 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
13428 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex();
13429 if (C->getZExtValue() == SplatIdx)
13430 BaseShAmt = InVec.getOperand(1);
13433 if (BaseShAmt.getNode() == 0)
13434 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
13435 DAG.getIntPtrConstant(0));
13439 // The shift amount is an i32.
13440 if (EltVT.bitsGT(MVT::i32))
13441 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt);
13442 else if (EltVT.bitsLT(MVT::i32))
13443 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt);
13445 // The shift amount is identical so we can do a vector shift.
13446 SDValue ValOp = N->getOperand(0);
13447 switch (N->getOpcode()) {
13449 llvm_unreachable("Unknown shift opcode!");
13452 if (VT == MVT::v2i64)
13453 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13454 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
13456 if (VT == MVT::v4i32)
13457 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13458 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
13460 if (VT == MVT::v8i16)
13461 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13462 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
13464 if (VT == MVT::v4i64)
13465 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13466 DAG.getConstant(Intrinsic::x86_avx2_pslli_q, MVT::i32),
13468 if (VT == MVT::v8i32)
13469 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13470 DAG.getConstant(Intrinsic::x86_avx2_pslli_d, MVT::i32),
13472 if (VT == MVT::v16i16)
13473 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13474 DAG.getConstant(Intrinsic::x86_avx2_pslli_w, MVT::i32),
13478 if (VT == MVT::v4i32)
13479 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13480 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32),
13482 if (VT == MVT::v8i16)
13483 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13484 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32),
13486 if (VT == MVT::v8i32)
13487 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13488 DAG.getConstant(Intrinsic::x86_avx2_psrai_d, MVT::i32),
13490 if (VT == MVT::v16i16)
13491 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13492 DAG.getConstant(Intrinsic::x86_avx2_psrai_w, MVT::i32),
13496 if (VT == MVT::v2i64)
13497 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13498 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
13500 if (VT == MVT::v4i32)
13501 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13502 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32),
13504 if (VT == MVT::v8i16)
13505 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13506 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32),
13508 if (VT == MVT::v4i64)
13509 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13510 DAG.getConstant(Intrinsic::x86_avx2_psrli_q, MVT::i32),
13512 if (VT == MVT::v8i32)
13513 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13514 DAG.getConstant(Intrinsic::x86_avx2_psrli_d, MVT::i32),
13516 if (VT == MVT::v16i16)
13517 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13518 DAG.getConstant(Intrinsic::x86_avx2_psrli_w, MVT::i32),
13526 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
13527 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
13528 // and friends. Likewise for OR -> CMPNEQSS.
13529 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
13530 TargetLowering::DAGCombinerInfo &DCI,
13531 const X86Subtarget *Subtarget) {
13534 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
13535 // we're requiring SSE2 for both.
13536 if (Subtarget->hasXMMInt() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
13537 SDValue N0 = N->getOperand(0);
13538 SDValue N1 = N->getOperand(1);
13539 SDValue CMP0 = N0->getOperand(1);
13540 SDValue CMP1 = N1->getOperand(1);
13541 DebugLoc DL = N->getDebugLoc();
13543 // The SETCCs should both refer to the same CMP.
13544 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
13547 SDValue CMP00 = CMP0->getOperand(0);
13548 SDValue CMP01 = CMP0->getOperand(1);
13549 EVT VT = CMP00.getValueType();
13551 if (VT == MVT::f32 || VT == MVT::f64) {
13552 bool ExpectingFlags = false;
13553 // Check for any users that want flags:
13554 for (SDNode::use_iterator UI = N->use_begin(),
13556 !ExpectingFlags && UI != UE; ++UI)
13557 switch (UI->getOpcode()) {
13562 ExpectingFlags = true;
13564 case ISD::CopyToReg:
13565 case ISD::SIGN_EXTEND:
13566 case ISD::ZERO_EXTEND:
13567 case ISD::ANY_EXTEND:
13571 if (!ExpectingFlags) {
13572 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
13573 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
13575 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
13576 X86::CondCode tmp = cc0;
13581 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
13582 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
13583 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
13584 X86ISD::NodeType NTOperator = is64BitFP ?
13585 X86ISD::FSETCCsd : X86ISD::FSETCCss;
13586 // FIXME: need symbolic constants for these magic numbers.
13587 // See X86ATTInstPrinter.cpp:printSSECC().
13588 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
13589 SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, MVT::f32, CMP00, CMP01,
13590 DAG.getConstant(x86cc, MVT::i8));
13591 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32,
13593 SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI,
13594 DAG.getConstant(1, MVT::i32));
13595 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
13596 return OneBitOfTruth;
13604 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
13605 /// so it can be folded inside ANDNP.
13606 static bool CanFoldXORWithAllOnes(const SDNode *N) {
13607 EVT VT = N->getValueType(0);
13609 // Match direct AllOnes for 128 and 256-bit vectors
13610 if (ISD::isBuildVectorAllOnes(N))
13613 // Look through a bit convert.
13614 if (N->getOpcode() == ISD::BITCAST)
13615 N = N->getOperand(0).getNode();
13617 // Sometimes the operand may come from a insert_subvector building a 256-bit
13619 if (VT.getSizeInBits() == 256 &&
13620 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
13621 SDValue V1 = N->getOperand(0);
13622 SDValue V2 = N->getOperand(1);
13624 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
13625 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
13626 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
13627 ISD::isBuildVectorAllOnes(V2.getNode()))
13634 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
13635 TargetLowering::DAGCombinerInfo &DCI,
13636 const X86Subtarget *Subtarget) {
13637 if (DCI.isBeforeLegalizeOps())
13640 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
13644 EVT VT = N->getValueType(0);
13646 // Create ANDN, BLSI, and BLSR instructions
13647 // BLSI is X & (-X)
13648 // BLSR is X & (X-1)
13649 if (Subtarget->hasBMI() && (VT == MVT::i32 || VT == MVT::i64)) {
13650 SDValue N0 = N->getOperand(0);
13651 SDValue N1 = N->getOperand(1);
13652 DebugLoc DL = N->getDebugLoc();
13654 // Check LHS for not
13655 if (N0.getOpcode() == ISD::XOR && isAllOnes(N0.getOperand(1)))
13656 return DAG.getNode(X86ISD::ANDN, DL, VT, N0.getOperand(0), N1);
13657 // Check RHS for not
13658 if (N1.getOpcode() == ISD::XOR && isAllOnes(N1.getOperand(1)))
13659 return DAG.getNode(X86ISD::ANDN, DL, VT, N1.getOperand(0), N0);
13661 // Check LHS for neg
13662 if (N0.getOpcode() == ISD::SUB && N0.getOperand(1) == N1 &&
13663 isZero(N0.getOperand(0)))
13664 return DAG.getNode(X86ISD::BLSI, DL, VT, N1);
13666 // Check RHS for neg
13667 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1) == N0 &&
13668 isZero(N1.getOperand(0)))
13669 return DAG.getNode(X86ISD::BLSI, DL, VT, N0);
13671 // Check LHS for X-1
13672 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
13673 isAllOnes(N0.getOperand(1)))
13674 return DAG.getNode(X86ISD::BLSR, DL, VT, N1);
13676 // Check RHS for X-1
13677 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
13678 isAllOnes(N1.getOperand(1)))
13679 return DAG.getNode(X86ISD::BLSR, DL, VT, N0);
13684 // Want to form ANDNP nodes:
13685 // 1) In the hopes of then easily combining them with OR and AND nodes
13686 // to form PBLEND/PSIGN.
13687 // 2) To match ANDN packed intrinsics
13688 if (VT != MVT::v2i64 && VT != MVT::v4i64)
13691 SDValue N0 = N->getOperand(0);
13692 SDValue N1 = N->getOperand(1);
13693 DebugLoc DL = N->getDebugLoc();
13695 // Check LHS for vnot
13696 if (N0.getOpcode() == ISD::XOR &&
13697 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
13698 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
13699 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
13701 // Check RHS for vnot
13702 if (N1.getOpcode() == ISD::XOR &&
13703 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
13704 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
13705 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
13710 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
13711 TargetLowering::DAGCombinerInfo &DCI,
13712 const X86Subtarget *Subtarget) {
13713 if (DCI.isBeforeLegalizeOps())
13716 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
13720 EVT VT = N->getValueType(0);
13722 SDValue N0 = N->getOperand(0);
13723 SDValue N1 = N->getOperand(1);
13725 // look for psign/blend
13726 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
13727 if (!Subtarget->hasSSSE3orAVX() ||
13728 (VT == MVT::v4i64 && !Subtarget->hasAVX2()))
13731 // Canonicalize pandn to RHS
13732 if (N0.getOpcode() == X86ISD::ANDNP)
13734 // or (and (m, x), (pandn m, y))
13735 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
13736 SDValue Mask = N1.getOperand(0);
13737 SDValue X = N1.getOperand(1);
13739 if (N0.getOperand(0) == Mask)
13740 Y = N0.getOperand(1);
13741 if (N0.getOperand(1) == Mask)
13742 Y = N0.getOperand(0);
13744 // Check to see if the mask appeared in both the AND and ANDNP and
13748 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
13749 if (Mask.getOpcode() != ISD::BITCAST ||
13750 X.getOpcode() != ISD::BITCAST ||
13751 Y.getOpcode() != ISD::BITCAST)
13754 // Look through mask bitcast.
13755 Mask = Mask.getOperand(0);
13756 EVT MaskVT = Mask.getValueType();
13758 // Validate that the Mask operand is a vector sra node. The sra node
13759 // will be an intrinsic.
13760 if (Mask.getOpcode() != ISD::INTRINSIC_WO_CHAIN)
13763 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
13764 // there is no psrai.b
13765 switch (cast<ConstantSDNode>(Mask.getOperand(0))->getZExtValue()) {
13766 case Intrinsic::x86_sse2_psrai_w:
13767 case Intrinsic::x86_sse2_psrai_d:
13768 case Intrinsic::x86_avx2_psrai_w:
13769 case Intrinsic::x86_avx2_psrai_d:
13771 default: return SDValue();
13774 // Check that the SRA is all signbits.
13775 SDValue SraC = Mask.getOperand(2);
13776 unsigned SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
13777 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
13778 if ((SraAmt + 1) != EltBits)
13781 DebugLoc DL = N->getDebugLoc();
13783 // Now we know we at least have a plendvb with the mask val. See if
13784 // we can form a psignb/w/d.
13785 // psign = x.type == y.type == mask.type && y = sub(0, x);
13786 X = X.getOperand(0);
13787 Y = Y.getOperand(0);
13788 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
13789 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
13790 X.getValueType() == MaskVT && X.getValueType() == Y.getValueType() &&
13791 (EltBits == 8 || EltBits == 16 || EltBits == 32)) {
13792 SDValue Sign = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X,
13793 Mask.getOperand(1));
13794 return DAG.getNode(ISD::BITCAST, DL, VT, Sign);
13796 // PBLENDVB only available on SSE 4.1
13797 if (!Subtarget->hasSSE41orAVX())
13800 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
13802 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
13803 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
13804 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
13805 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
13806 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
13810 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
13813 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
13814 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
13816 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
13818 if (!N0.hasOneUse() || !N1.hasOneUse())
13821 SDValue ShAmt0 = N0.getOperand(1);
13822 if (ShAmt0.getValueType() != MVT::i8)
13824 SDValue ShAmt1 = N1.getOperand(1);
13825 if (ShAmt1.getValueType() != MVT::i8)
13827 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
13828 ShAmt0 = ShAmt0.getOperand(0);
13829 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
13830 ShAmt1 = ShAmt1.getOperand(0);
13832 DebugLoc DL = N->getDebugLoc();
13833 unsigned Opc = X86ISD::SHLD;
13834 SDValue Op0 = N0.getOperand(0);
13835 SDValue Op1 = N1.getOperand(0);
13836 if (ShAmt0.getOpcode() == ISD::SUB) {
13837 Opc = X86ISD::SHRD;
13838 std::swap(Op0, Op1);
13839 std::swap(ShAmt0, ShAmt1);
13842 unsigned Bits = VT.getSizeInBits();
13843 if (ShAmt1.getOpcode() == ISD::SUB) {
13844 SDValue Sum = ShAmt1.getOperand(0);
13845 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
13846 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
13847 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
13848 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
13849 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
13850 return DAG.getNode(Opc, DL, VT,
13852 DAG.getNode(ISD::TRUNCATE, DL,
13855 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
13856 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
13858 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
13859 return DAG.getNode(Opc, DL, VT,
13860 N0.getOperand(0), N1.getOperand(0),
13861 DAG.getNode(ISD::TRUNCATE, DL,
13868 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
13869 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
13870 TargetLowering::DAGCombinerInfo &DCI,
13871 const X86Subtarget *Subtarget) {
13872 if (DCI.isBeforeLegalizeOps())
13875 EVT VT = N->getValueType(0);
13877 if (VT != MVT::i32 && VT != MVT::i64)
13880 assert(Subtarget->hasBMI() && "Creating BLSMSK requires BMI instructions");
13882 // Create BLSMSK instructions by finding X ^ (X-1)
13883 SDValue N0 = N->getOperand(0);
13884 SDValue N1 = N->getOperand(1);
13885 DebugLoc DL = N->getDebugLoc();
13887 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
13888 isAllOnes(N0.getOperand(1)))
13889 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N1);
13891 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
13892 isAllOnes(N1.getOperand(1)))
13893 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N0);
13898 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
13899 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
13900 const X86Subtarget *Subtarget) {
13901 LoadSDNode *Ld = cast<LoadSDNode>(N);
13902 EVT RegVT = Ld->getValueType(0);
13903 EVT MemVT = Ld->getMemoryVT();
13904 DebugLoc dl = Ld->getDebugLoc();
13905 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13907 ISD::LoadExtType Ext = Ld->getExtensionType();
13909 // If this is a vector EXT Load then attempt to optimize it using a
13910 // shuffle. We need SSE4 for the shuffles.
13911 // TODO: It is possible to support ZExt by zeroing the undef values
13912 // during the shuffle phase or after the shuffle.
13913 if (RegVT.isVector() && RegVT.isInteger() &&
13914 Ext == ISD::EXTLOAD && Subtarget->hasSSE41()) {
13915 assert(MemVT != RegVT && "Cannot extend to the same type");
13916 assert(MemVT.isVector() && "Must load a vector from memory");
13918 unsigned NumElems = RegVT.getVectorNumElements();
13919 unsigned RegSz = RegVT.getSizeInBits();
13920 unsigned MemSz = MemVT.getSizeInBits();
13921 assert(RegSz > MemSz && "Register size must be greater than the mem size");
13922 // All sizes must be a power of two
13923 if (!isPowerOf2_32(RegSz * MemSz * NumElems)) return SDValue();
13925 // Attempt to load the original value using a single load op.
13926 // Find a scalar type which is equal to the loaded word size.
13927 MVT SclrLoadTy = MVT::i8;
13928 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
13929 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
13930 MVT Tp = (MVT::SimpleValueType)tp;
13931 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() == MemSz) {
13937 // Proceed if a load word is found.
13938 if (SclrLoadTy.getSizeInBits() != MemSz) return SDValue();
13940 EVT LoadUnitVecVT = EVT::getVectorVT(*DAG.getContext(), SclrLoadTy,
13941 RegSz/SclrLoadTy.getSizeInBits());
13943 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
13944 RegSz/MemVT.getScalarType().getSizeInBits());
13945 // Can't shuffle using an illegal type.
13946 if (!TLI.isTypeLegal(WideVecVT)) return SDValue();
13948 // Perform a single load.
13949 SDValue ScalarLoad = DAG.getLoad(SclrLoadTy, dl, Ld->getChain(),
13951 Ld->getPointerInfo(), Ld->isVolatile(),
13952 Ld->isNonTemporal(), Ld->isInvariant(),
13953 Ld->getAlignment());
13955 // Insert the word loaded into a vector.
13956 SDValue ScalarInVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
13957 LoadUnitVecVT, ScalarLoad);
13959 // Bitcast the loaded value to a vector of the original element type, in
13960 // the size of the target vector type.
13961 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT,
13963 unsigned SizeRatio = RegSz/MemSz;
13965 // Redistribute the loaded elements into the different locations.
13966 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
13967 for (unsigned i = 0; i < NumElems; i++) ShuffleVec[i*SizeRatio] = i;
13969 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
13970 DAG.getUNDEF(SlicedVec.getValueType()),
13971 ShuffleVec.data());
13973 // Bitcast to the requested type.
13974 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
13975 // Replace the original load with the new sequence
13976 // and return the new chain.
13977 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Shuff);
13978 return SDValue(ScalarLoad.getNode(), 1);
13984 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
13985 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
13986 const X86Subtarget *Subtarget) {
13987 StoreSDNode *St = cast<StoreSDNode>(N);
13988 EVT VT = St->getValue().getValueType();
13989 EVT StVT = St->getMemoryVT();
13990 DebugLoc dl = St->getDebugLoc();
13991 SDValue StoredVal = St->getOperand(1);
13992 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13994 // If we are saving a concatenation of two XMM registers, perform two stores.
13995 // This is better in Sandy Bridge cause one 256-bit mem op is done via two
13996 // 128-bit ones. If in the future the cost becomes only one memory access the
13997 // first version would be better.
13998 if (VT.getSizeInBits() == 256 &&
13999 StoredVal.getNode()->getOpcode() == ISD::CONCAT_VECTORS &&
14000 StoredVal.getNumOperands() == 2) {
14002 SDValue Value0 = StoredVal.getOperand(0);
14003 SDValue Value1 = StoredVal.getOperand(1);
14005 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
14006 SDValue Ptr0 = St->getBasePtr();
14007 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
14009 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
14010 St->getPointerInfo(), St->isVolatile(),
14011 St->isNonTemporal(), St->getAlignment());
14012 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
14013 St->getPointerInfo(), St->isVolatile(),
14014 St->isNonTemporal(), St->getAlignment());
14015 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
14018 // Optimize trunc store (of multiple scalars) to shuffle and store.
14019 // First, pack all of the elements in one place. Next, store to memory
14020 // in fewer chunks.
14021 if (St->isTruncatingStore() && VT.isVector()) {
14022 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14023 unsigned NumElems = VT.getVectorNumElements();
14024 assert(StVT != VT && "Cannot truncate to the same type");
14025 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
14026 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
14028 // From, To sizes and ElemCount must be pow of two
14029 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
14030 // We are going to use the original vector elt for storing.
14031 // Accumulated smaller vector elements must be a multiple of the store size.
14032 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
14034 unsigned SizeRatio = FromSz / ToSz;
14036 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
14038 // Create a type on which we perform the shuffle
14039 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
14040 StVT.getScalarType(), NumElems*SizeRatio);
14042 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
14044 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
14045 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
14046 for (unsigned i = 0; i < NumElems; i++ ) ShuffleVec[i] = i * SizeRatio;
14048 // Can't shuffle using an illegal type
14049 if (!TLI.isTypeLegal(WideVecVT)) return SDValue();
14051 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
14052 DAG.getUNDEF(WideVec.getValueType()),
14053 ShuffleVec.data());
14054 // At this point all of the data is stored at the bottom of the
14055 // register. We now need to save it to mem.
14057 // Find the largest store unit
14058 MVT StoreType = MVT::i8;
14059 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
14060 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
14061 MVT Tp = (MVT::SimpleValueType)tp;
14062 if (TLI.isTypeLegal(Tp) && StoreType.getSizeInBits() < NumElems * ToSz)
14066 // Bitcast the original vector into a vector of store-size units
14067 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
14068 StoreType, VT.getSizeInBits()/EVT(StoreType).getSizeInBits());
14069 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
14070 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
14071 SmallVector<SDValue, 8> Chains;
14072 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
14073 TLI.getPointerTy());
14074 SDValue Ptr = St->getBasePtr();
14076 // Perform one or more big stores into memory.
14077 for (unsigned i = 0; i < (ToSz*NumElems)/StoreType.getSizeInBits() ; i++) {
14078 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
14079 StoreType, ShuffWide,
14080 DAG.getIntPtrConstant(i));
14081 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
14082 St->getPointerInfo(), St->isVolatile(),
14083 St->isNonTemporal(), St->getAlignment());
14084 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
14085 Chains.push_back(Ch);
14088 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
14093 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
14094 // the FP state in cases where an emms may be missing.
14095 // A preferable solution to the general problem is to figure out the right
14096 // places to insert EMMS. This qualifies as a quick hack.
14098 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
14099 if (VT.getSizeInBits() != 64)
14102 const Function *F = DAG.getMachineFunction().getFunction();
14103 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
14104 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
14105 && Subtarget->hasXMMInt();
14106 if ((VT.isVector() ||
14107 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
14108 isa<LoadSDNode>(St->getValue()) &&
14109 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
14110 St->getChain().hasOneUse() && !St->isVolatile()) {
14111 SDNode* LdVal = St->getValue().getNode();
14112 LoadSDNode *Ld = 0;
14113 int TokenFactorIndex = -1;
14114 SmallVector<SDValue, 8> Ops;
14115 SDNode* ChainVal = St->getChain().getNode();
14116 // Must be a store of a load. We currently handle two cases: the load
14117 // is a direct child, and it's under an intervening TokenFactor. It is
14118 // possible to dig deeper under nested TokenFactors.
14119 if (ChainVal == LdVal)
14120 Ld = cast<LoadSDNode>(St->getChain());
14121 else if (St->getValue().hasOneUse() &&
14122 ChainVal->getOpcode() == ISD::TokenFactor) {
14123 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) {
14124 if (ChainVal->getOperand(i).getNode() == LdVal) {
14125 TokenFactorIndex = i;
14126 Ld = cast<LoadSDNode>(St->getValue());
14128 Ops.push_back(ChainVal->getOperand(i));
14132 if (!Ld || !ISD::isNormalLoad(Ld))
14135 // If this is not the MMX case, i.e. we are just turning i64 load/store
14136 // into f64 load/store, avoid the transformation if there are multiple
14137 // uses of the loaded value.
14138 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
14141 DebugLoc LdDL = Ld->getDebugLoc();
14142 DebugLoc StDL = N->getDebugLoc();
14143 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
14144 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
14146 if (Subtarget->is64Bit() || F64IsLegal) {
14147 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
14148 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
14149 Ld->getPointerInfo(), Ld->isVolatile(),
14150 Ld->isNonTemporal(), Ld->isInvariant(),
14151 Ld->getAlignment());
14152 SDValue NewChain = NewLd.getValue(1);
14153 if (TokenFactorIndex != -1) {
14154 Ops.push_back(NewChain);
14155 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
14158 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
14159 St->getPointerInfo(),
14160 St->isVolatile(), St->isNonTemporal(),
14161 St->getAlignment());
14164 // Otherwise, lower to two pairs of 32-bit loads / stores.
14165 SDValue LoAddr = Ld->getBasePtr();
14166 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
14167 DAG.getConstant(4, MVT::i32));
14169 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
14170 Ld->getPointerInfo(),
14171 Ld->isVolatile(), Ld->isNonTemporal(),
14172 Ld->isInvariant(), Ld->getAlignment());
14173 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
14174 Ld->getPointerInfo().getWithOffset(4),
14175 Ld->isVolatile(), Ld->isNonTemporal(),
14177 MinAlign(Ld->getAlignment(), 4));
14179 SDValue NewChain = LoLd.getValue(1);
14180 if (TokenFactorIndex != -1) {
14181 Ops.push_back(LoLd);
14182 Ops.push_back(HiLd);
14183 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
14187 LoAddr = St->getBasePtr();
14188 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
14189 DAG.getConstant(4, MVT::i32));
14191 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
14192 St->getPointerInfo(),
14193 St->isVolatile(), St->isNonTemporal(),
14194 St->getAlignment());
14195 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
14196 St->getPointerInfo().getWithOffset(4),
14198 St->isNonTemporal(),
14199 MinAlign(St->getAlignment(), 4));
14200 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
14205 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
14206 /// and return the operands for the horizontal operation in LHS and RHS. A
14207 /// horizontal operation performs the binary operation on successive elements
14208 /// of its first operand, then on successive elements of its second operand,
14209 /// returning the resulting values in a vector. For example, if
14210 /// A = < float a0, float a1, float a2, float a3 >
14212 /// B = < float b0, float b1, float b2, float b3 >
14213 /// then the result of doing a horizontal operation on A and B is
14214 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
14215 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
14216 /// A horizontal-op B, for some already available A and B, and if so then LHS is
14217 /// set to A, RHS to B, and the routine returns 'true'.
14218 /// Note that the binary operation should have the property that if one of the
14219 /// operands is UNDEF then the result is UNDEF.
14220 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
14221 // Look for the following pattern: if
14222 // A = < float a0, float a1, float a2, float a3 >
14223 // B = < float b0, float b1, float b2, float b3 >
14225 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
14226 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
14227 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
14228 // which is A horizontal-op B.
14230 // At least one of the operands should be a vector shuffle.
14231 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
14232 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
14235 EVT VT = LHS.getValueType();
14237 assert((VT.is128BitVector() || VT.is256BitVector()) &&
14238 "Unsupported vector type for horizontal add/sub");
14240 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
14241 // operate independently on 128-bit lanes.
14242 unsigned NumElts = VT.getVectorNumElements();
14243 unsigned NumLanes = VT.getSizeInBits()/128;
14244 unsigned NumLaneElts = NumElts / NumLanes;
14245 assert((NumLaneElts % 2 == 0) &&
14246 "Vector type should have an even number of elements in each lane");
14247 unsigned HalfLaneElts = NumLaneElts/2;
14249 // View LHS in the form
14250 // LHS = VECTOR_SHUFFLE A, B, LMask
14251 // If LHS is not a shuffle then pretend it is the shuffle
14252 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
14253 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
14256 SmallVector<int, 16> LMask(NumElts);
14257 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
14258 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
14259 A = LHS.getOperand(0);
14260 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
14261 B = LHS.getOperand(1);
14262 cast<ShuffleVectorSDNode>(LHS.getNode())->getMask(LMask);
14264 if (LHS.getOpcode() != ISD::UNDEF)
14266 for (unsigned i = 0; i != NumElts; ++i)
14270 // Likewise, view RHS in the form
14271 // RHS = VECTOR_SHUFFLE C, D, RMask
14273 SmallVector<int, 16> RMask(NumElts);
14274 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
14275 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
14276 C = RHS.getOperand(0);
14277 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
14278 D = RHS.getOperand(1);
14279 cast<ShuffleVectorSDNode>(RHS.getNode())->getMask(RMask);
14281 if (RHS.getOpcode() != ISD::UNDEF)
14283 for (unsigned i = 0; i != NumElts; ++i)
14287 // Check that the shuffles are both shuffling the same vectors.
14288 if (!(A == C && B == D) && !(A == D && B == C))
14291 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
14292 if (!A.getNode() && !B.getNode())
14295 // If A and B occur in reverse order in RHS, then "swap" them (which means
14296 // rewriting the mask).
14298 CommuteVectorShuffleMask(RMask, NumElts);
14300 // At this point LHS and RHS are equivalent to
14301 // LHS = VECTOR_SHUFFLE A, B, LMask
14302 // RHS = VECTOR_SHUFFLE A, B, RMask
14303 // Check that the masks correspond to performing a horizontal operation.
14304 for (unsigned i = 0; i != NumElts; ++i) {
14305 int LIdx = LMask[i], RIdx = RMask[i];
14307 // Ignore any UNDEF components.
14308 if (LIdx < 0 || RIdx < 0 ||
14309 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
14310 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
14313 // Check that successive elements are being operated on. If not, this is
14314 // not a horizontal operation.
14315 unsigned Src = (i/HalfLaneElts) % 2; // each lane is split between srcs
14316 unsigned LaneStart = (i/NumLaneElts) * NumLaneElts;
14317 int Index = 2*(i%HalfLaneElts) + NumElts*Src + LaneStart;
14318 if (!(LIdx == Index && RIdx == Index + 1) &&
14319 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
14323 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
14324 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
14328 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
14329 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
14330 const X86Subtarget *Subtarget) {
14331 EVT VT = N->getValueType(0);
14332 SDValue LHS = N->getOperand(0);
14333 SDValue RHS = N->getOperand(1);
14335 // Try to synthesize horizontal adds from adds of shuffles.
14336 if (((Subtarget->hasSSE3orAVX() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
14337 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
14338 isHorizontalBinOp(LHS, RHS, true))
14339 return DAG.getNode(X86ISD::FHADD, N->getDebugLoc(), VT, LHS, RHS);
14343 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
14344 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
14345 const X86Subtarget *Subtarget) {
14346 EVT VT = N->getValueType(0);
14347 SDValue LHS = N->getOperand(0);
14348 SDValue RHS = N->getOperand(1);
14350 // Try to synthesize horizontal subs from subs of shuffles.
14351 if (((Subtarget->hasSSE3orAVX() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
14352 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
14353 isHorizontalBinOp(LHS, RHS, false))
14354 return DAG.getNode(X86ISD::FHSUB, N->getDebugLoc(), VT, LHS, RHS);
14358 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
14359 /// X86ISD::FXOR nodes.
14360 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
14361 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
14362 // F[X]OR(0.0, x) -> x
14363 // F[X]OR(x, 0.0) -> x
14364 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
14365 if (C->getValueAPF().isPosZero())
14366 return N->getOperand(1);
14367 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
14368 if (C->getValueAPF().isPosZero())
14369 return N->getOperand(0);
14373 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
14374 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
14375 // FAND(0.0, x) -> 0.0
14376 // FAND(x, 0.0) -> 0.0
14377 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
14378 if (C->getValueAPF().isPosZero())
14379 return N->getOperand(0);
14380 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
14381 if (C->getValueAPF().isPosZero())
14382 return N->getOperand(1);
14386 static SDValue PerformBTCombine(SDNode *N,
14388 TargetLowering::DAGCombinerInfo &DCI) {
14389 // BT ignores high bits in the bit index operand.
14390 SDValue Op1 = N->getOperand(1);
14391 if (Op1.hasOneUse()) {
14392 unsigned BitWidth = Op1.getValueSizeInBits();
14393 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
14394 APInt KnownZero, KnownOne;
14395 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
14396 !DCI.isBeforeLegalizeOps());
14397 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14398 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
14399 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
14400 DCI.CommitTargetLoweringOpt(TLO);
14405 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
14406 SDValue Op = N->getOperand(0);
14407 if (Op.getOpcode() == ISD::BITCAST)
14408 Op = Op.getOperand(0);
14409 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
14410 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
14411 VT.getVectorElementType().getSizeInBits() ==
14412 OpVT.getVectorElementType().getSizeInBits()) {
14413 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op);
14418 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG) {
14419 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
14420 // (and (i32 x86isd::setcc_carry), 1)
14421 // This eliminates the zext. This transformation is necessary because
14422 // ISD::SETCC is always legalized to i8.
14423 DebugLoc dl = N->getDebugLoc();
14424 SDValue N0 = N->getOperand(0);
14425 EVT VT = N->getValueType(0);
14426 if (N0.getOpcode() == ISD::AND &&
14428 N0.getOperand(0).hasOneUse()) {
14429 SDValue N00 = N0.getOperand(0);
14430 if (N00.getOpcode() != X86ISD::SETCC_CARRY)
14432 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
14433 if (!C || C->getZExtValue() != 1)
14435 return DAG.getNode(ISD::AND, dl, VT,
14436 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
14437 N00.getOperand(0), N00.getOperand(1)),
14438 DAG.getConstant(1, VT));
14444 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
14445 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG) {
14446 unsigned X86CC = N->getConstantOperandVal(0);
14447 SDValue EFLAG = N->getOperand(1);
14448 DebugLoc DL = N->getDebugLoc();
14450 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
14451 // a zext and produces an all-ones bit which is more useful than 0/1 in some
14453 if (X86CC == X86::COND_B)
14454 return DAG.getNode(ISD::AND, DL, MVT::i8,
14455 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
14456 DAG.getConstant(X86CC, MVT::i8), EFLAG),
14457 DAG.getConstant(1, MVT::i8));
14462 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
14463 const X86TargetLowering *XTLI) {
14464 SDValue Op0 = N->getOperand(0);
14465 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
14466 // a 32-bit target where SSE doesn't support i64->FP operations.
14467 if (Op0.getOpcode() == ISD::LOAD) {
14468 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
14469 EVT VT = Ld->getValueType(0);
14470 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
14471 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
14472 !XTLI->getSubtarget()->is64Bit() &&
14473 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
14474 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
14475 Ld->getChain(), Op0, DAG);
14476 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
14483 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
14484 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
14485 X86TargetLowering::DAGCombinerInfo &DCI) {
14486 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
14487 // the result is either zero or one (depending on the input carry bit).
14488 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
14489 if (X86::isZeroNode(N->getOperand(0)) &&
14490 X86::isZeroNode(N->getOperand(1)) &&
14491 // We don't have a good way to replace an EFLAGS use, so only do this when
14493 SDValue(N, 1).use_empty()) {
14494 DebugLoc DL = N->getDebugLoc();
14495 EVT VT = N->getValueType(0);
14496 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
14497 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
14498 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
14499 DAG.getConstant(X86::COND_B,MVT::i8),
14501 DAG.getConstant(1, VT));
14502 return DCI.CombineTo(N, Res1, CarryOut);
14508 // fold (add Y, (sete X, 0)) -> adc 0, Y
14509 // (add Y, (setne X, 0)) -> sbb -1, Y
14510 // (sub (sete X, 0), Y) -> sbb 0, Y
14511 // (sub (setne X, 0), Y) -> adc -1, Y
14512 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
14513 DebugLoc DL = N->getDebugLoc();
14515 // Look through ZExts.
14516 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
14517 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
14520 SDValue SetCC = Ext.getOperand(0);
14521 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
14524 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
14525 if (CC != X86::COND_E && CC != X86::COND_NE)
14528 SDValue Cmp = SetCC.getOperand(1);
14529 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
14530 !X86::isZeroNode(Cmp.getOperand(1)) ||
14531 !Cmp.getOperand(0).getValueType().isInteger())
14534 SDValue CmpOp0 = Cmp.getOperand(0);
14535 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
14536 DAG.getConstant(1, CmpOp0.getValueType()));
14538 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
14539 if (CC == X86::COND_NE)
14540 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
14541 DL, OtherVal.getValueType(), OtherVal,
14542 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
14543 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
14544 DL, OtherVal.getValueType(), OtherVal,
14545 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
14548 /// PerformADDCombine - Do target-specific dag combines on integer adds.
14549 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
14550 const X86Subtarget *Subtarget) {
14551 EVT VT = N->getValueType(0);
14552 SDValue Op0 = N->getOperand(0);
14553 SDValue Op1 = N->getOperand(1);
14555 // Try to synthesize horizontal adds from adds of shuffles.
14556 if (((Subtarget->hasSSSE3orAVX() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
14557 (Subtarget->hasAVX2() && (VT == MVT::v16i16 || MVT::v8i32))) &&
14558 isHorizontalBinOp(Op0, Op1, true))
14559 return DAG.getNode(X86ISD::HADD, N->getDebugLoc(), VT, Op0, Op1);
14561 return OptimizeConditionalInDecrement(N, DAG);
14564 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
14565 const X86Subtarget *Subtarget) {
14566 SDValue Op0 = N->getOperand(0);
14567 SDValue Op1 = N->getOperand(1);
14569 // X86 can't encode an immediate LHS of a sub. See if we can push the
14570 // negation into a preceding instruction.
14571 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
14572 // If the RHS of the sub is a XOR with one use and a constant, invert the
14573 // immediate. Then add one to the LHS of the sub so we can turn
14574 // X-Y -> X+~Y+1, saving one register.
14575 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
14576 isa<ConstantSDNode>(Op1.getOperand(1))) {
14577 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
14578 EVT VT = Op0.getValueType();
14579 SDValue NewXor = DAG.getNode(ISD::XOR, Op1.getDebugLoc(), VT,
14581 DAG.getConstant(~XorC, VT));
14582 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, NewXor,
14583 DAG.getConstant(C->getAPIntValue()+1, VT));
14587 // Try to synthesize horizontal adds from adds of shuffles.
14588 EVT VT = N->getValueType(0);
14589 if (((Subtarget->hasSSSE3orAVX() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
14590 (Subtarget->hasAVX2() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
14591 isHorizontalBinOp(Op0, Op1, true))
14592 return DAG.getNode(X86ISD::HSUB, N->getDebugLoc(), VT, Op0, Op1);
14594 return OptimizeConditionalInDecrement(N, DAG);
14597 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
14598 DAGCombinerInfo &DCI) const {
14599 SelectionDAG &DAG = DCI.DAG;
14600 switch (N->getOpcode()) {
14602 case ISD::EXTRACT_VECTOR_ELT:
14603 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, *this);
14605 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget);
14606 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI);
14607 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
14608 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
14609 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
14610 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
14613 case ISD::SRL: return PerformShiftCombine(N, DAG, Subtarget);
14614 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
14615 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
14616 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
14617 case ISD::LOAD: return PerformLOADCombine(N, DAG, Subtarget);
14618 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
14619 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
14620 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
14621 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
14623 case X86ISD::FOR: return PerformFORCombine(N, DAG);
14624 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
14625 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
14626 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
14627 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG);
14628 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG);
14629 case X86ISD::SHUFP: // Handle all target specific shuffles
14630 case X86ISD::PALIGN:
14631 case X86ISD::UNPCKH:
14632 case X86ISD::UNPCKL:
14633 case X86ISD::MOVHLPS:
14634 case X86ISD::MOVLHPS:
14635 case X86ISD::PSHUFD:
14636 case X86ISD::PSHUFHW:
14637 case X86ISD::PSHUFLW:
14638 case X86ISD::MOVSS:
14639 case X86ISD::MOVSD:
14640 case X86ISD::VPERMILP:
14641 case X86ISD::VPERM2X128:
14642 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
14648 /// isTypeDesirableForOp - Return true if the target has native support for
14649 /// the specified value type and it is 'desirable' to use the type for the
14650 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
14651 /// instruction encodings are longer and some i16 instructions are slow.
14652 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
14653 if (!isTypeLegal(VT))
14655 if (VT != MVT::i16)
14662 case ISD::SIGN_EXTEND:
14663 case ISD::ZERO_EXTEND:
14664 case ISD::ANY_EXTEND:
14677 /// IsDesirableToPromoteOp - This method query the target whether it is
14678 /// beneficial for dag combiner to promote the specified node. If true, it
14679 /// should return the desired promotion type by reference.
14680 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
14681 EVT VT = Op.getValueType();
14682 if (VT != MVT::i16)
14685 bool Promote = false;
14686 bool Commute = false;
14687 switch (Op.getOpcode()) {
14690 LoadSDNode *LD = cast<LoadSDNode>(Op);
14691 // If the non-extending load has a single use and it's not live out, then it
14692 // might be folded.
14693 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
14694 Op.hasOneUse()*/) {
14695 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
14696 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
14697 // The only case where we'd want to promote LOAD (rather then it being
14698 // promoted as an operand is when it's only use is liveout.
14699 if (UI->getOpcode() != ISD::CopyToReg)
14706 case ISD::SIGN_EXTEND:
14707 case ISD::ZERO_EXTEND:
14708 case ISD::ANY_EXTEND:
14713 SDValue N0 = Op.getOperand(0);
14714 // Look out for (store (shl (load), x)).
14715 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
14728 SDValue N0 = Op.getOperand(0);
14729 SDValue N1 = Op.getOperand(1);
14730 if (!Commute && MayFoldLoad(N1))
14732 // Avoid disabling potential load folding opportunities.
14733 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
14735 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
14745 //===----------------------------------------------------------------------===//
14746 // X86 Inline Assembly Support
14747 //===----------------------------------------------------------------------===//
14750 // Helper to match a string separated by whitespace.
14751 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
14752 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
14754 for (unsigned i = 0, e = args.size(); i != e; ++i) {
14755 StringRef piece(*args[i]);
14756 if (!s.startswith(piece)) // Check if the piece matches.
14759 s = s.substr(piece.size());
14760 StringRef::size_type pos = s.find_first_not_of(" \t");
14761 if (pos == 0) // We matched a prefix.
14769 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
14772 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
14773 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
14775 std::string AsmStr = IA->getAsmString();
14777 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
14778 if (!Ty || Ty->getBitWidth() % 16 != 0)
14781 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
14782 SmallVector<StringRef, 4> AsmPieces;
14783 SplitString(AsmStr, AsmPieces, ";\n");
14785 switch (AsmPieces.size()) {
14786 default: return false;
14788 // FIXME: this should verify that we are targeting a 486 or better. If not,
14789 // we will turn this bswap into something that will be lowered to logical
14790 // ops instead of emitting the bswap asm. For now, we don't support 486 or
14791 // lower so don't worry about this.
14793 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
14794 matchAsm(AsmPieces[0], "bswapl", "$0") ||
14795 matchAsm(AsmPieces[0], "bswapq", "$0") ||
14796 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
14797 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
14798 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
14799 // No need to check constraints, nothing other than the equivalent of
14800 // "=r,0" would be valid here.
14801 return IntrinsicLowering::LowerToByteSwap(CI);
14804 // rorw $$8, ${0:w} --> llvm.bswap.i16
14805 if (CI->getType()->isIntegerTy(16) &&
14806 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
14807 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
14808 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
14810 const std::string &ConstraintsStr = IA->getConstraintString();
14811 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
14812 std::sort(AsmPieces.begin(), AsmPieces.end());
14813 if (AsmPieces.size() == 4 &&
14814 AsmPieces[0] == "~{cc}" &&
14815 AsmPieces[1] == "~{dirflag}" &&
14816 AsmPieces[2] == "~{flags}" &&
14817 AsmPieces[3] == "~{fpsr}")
14818 return IntrinsicLowering::LowerToByteSwap(CI);
14822 if (CI->getType()->isIntegerTy(32) &&
14823 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
14824 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
14825 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
14826 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
14828 const std::string &ConstraintsStr = IA->getConstraintString();
14829 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
14830 std::sort(AsmPieces.begin(), AsmPieces.end());
14831 if (AsmPieces.size() == 4 &&
14832 AsmPieces[0] == "~{cc}" &&
14833 AsmPieces[1] == "~{dirflag}" &&
14834 AsmPieces[2] == "~{flags}" &&
14835 AsmPieces[3] == "~{fpsr}")
14836 return IntrinsicLowering::LowerToByteSwap(CI);
14839 if (CI->getType()->isIntegerTy(64)) {
14840 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
14841 if (Constraints.size() >= 2 &&
14842 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
14843 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
14844 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
14845 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
14846 matchAsm(AsmPieces[1], "bswap", "%edx") &&
14847 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
14848 return IntrinsicLowering::LowerToByteSwap(CI);
14858 /// getConstraintType - Given a constraint letter, return the type of
14859 /// constraint it is for this target.
14860 X86TargetLowering::ConstraintType
14861 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
14862 if (Constraint.size() == 1) {
14863 switch (Constraint[0]) {
14874 return C_RegisterClass;
14898 return TargetLowering::getConstraintType(Constraint);
14901 /// Examine constraint type and operand type and determine a weight value.
14902 /// This object must already have been set up with the operand type
14903 /// and the current alternative constraint selected.
14904 TargetLowering::ConstraintWeight
14905 X86TargetLowering::getSingleConstraintMatchWeight(
14906 AsmOperandInfo &info, const char *constraint) const {
14907 ConstraintWeight weight = CW_Invalid;
14908 Value *CallOperandVal = info.CallOperandVal;
14909 // If we don't have a value, we can't do a match,
14910 // but allow it at the lowest weight.
14911 if (CallOperandVal == NULL)
14913 Type *type = CallOperandVal->getType();
14914 // Look at the constraint type.
14915 switch (*constraint) {
14917 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
14928 if (CallOperandVal->getType()->isIntegerTy())
14929 weight = CW_SpecificReg;
14934 if (type->isFloatingPointTy())
14935 weight = CW_SpecificReg;
14938 if (type->isX86_MMXTy() && Subtarget->hasMMX())
14939 weight = CW_SpecificReg;
14943 if ((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasXMM())
14944 weight = CW_Register;
14947 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
14948 if (C->getZExtValue() <= 31)
14949 weight = CW_Constant;
14953 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
14954 if (C->getZExtValue() <= 63)
14955 weight = CW_Constant;
14959 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
14960 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
14961 weight = CW_Constant;
14965 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
14966 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
14967 weight = CW_Constant;
14971 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
14972 if (C->getZExtValue() <= 3)
14973 weight = CW_Constant;
14977 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
14978 if (C->getZExtValue() <= 0xff)
14979 weight = CW_Constant;
14984 if (dyn_cast<ConstantFP>(CallOperandVal)) {
14985 weight = CW_Constant;
14989 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
14990 if ((C->getSExtValue() >= -0x80000000LL) &&
14991 (C->getSExtValue() <= 0x7fffffffLL))
14992 weight = CW_Constant;
14996 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
14997 if (C->getZExtValue() <= 0xffffffff)
14998 weight = CW_Constant;
15005 /// LowerXConstraint - try to replace an X constraint, which matches anything,
15006 /// with another that has more specific requirements based on the type of the
15007 /// corresponding operand.
15008 const char *X86TargetLowering::
15009 LowerXConstraint(EVT ConstraintVT) const {
15010 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
15011 // 'f' like normal targets.
15012 if (ConstraintVT.isFloatingPoint()) {
15013 if (Subtarget->hasXMMInt())
15015 if (Subtarget->hasXMM())
15019 return TargetLowering::LowerXConstraint(ConstraintVT);
15022 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
15023 /// vector. If it is invalid, don't add anything to Ops.
15024 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
15025 std::string &Constraint,
15026 std::vector<SDValue>&Ops,
15027 SelectionDAG &DAG) const {
15028 SDValue Result(0, 0);
15030 // Only support length 1 constraints for now.
15031 if (Constraint.length() > 1) return;
15033 char ConstraintLetter = Constraint[0];
15034 switch (ConstraintLetter) {
15037 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15038 if (C->getZExtValue() <= 31) {
15039 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15045 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15046 if (C->getZExtValue() <= 63) {
15047 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15053 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15054 if ((int8_t)C->getSExtValue() == C->getSExtValue()) {
15055 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15061 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15062 if (C->getZExtValue() <= 255) {
15063 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15069 // 32-bit signed value
15070 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15071 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
15072 C->getSExtValue())) {
15073 // Widen to 64 bits here to get it sign extended.
15074 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
15077 // FIXME gcc accepts some relocatable values here too, but only in certain
15078 // memory models; it's complicated.
15083 // 32-bit unsigned value
15084 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15085 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
15086 C->getZExtValue())) {
15087 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15091 // FIXME gcc accepts some relocatable values here too, but only in certain
15092 // memory models; it's complicated.
15096 // Literal immediates are always ok.
15097 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
15098 // Widen to 64 bits here to get it sign extended.
15099 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
15103 // In any sort of PIC mode addresses need to be computed at runtime by
15104 // adding in a register or some sort of table lookup. These can't
15105 // be used as immediates.
15106 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
15109 // If we are in non-pic codegen mode, we allow the address of a global (with
15110 // an optional displacement) to be used with 'i'.
15111 GlobalAddressSDNode *GA = 0;
15112 int64_t Offset = 0;
15114 // Match either (GA), (GA+C), (GA+C1+C2), etc.
15116 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
15117 Offset += GA->getOffset();
15119 } else if (Op.getOpcode() == ISD::ADD) {
15120 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
15121 Offset += C->getZExtValue();
15122 Op = Op.getOperand(0);
15125 } else if (Op.getOpcode() == ISD::SUB) {
15126 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
15127 Offset += -C->getZExtValue();
15128 Op = Op.getOperand(0);
15133 // Otherwise, this isn't something we can handle, reject it.
15137 const GlobalValue *GV = GA->getGlobal();
15138 // If we require an extra load to get this address, as in PIC mode, we
15139 // can't accept it.
15140 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
15141 getTargetMachine())))
15144 Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(),
15145 GA->getValueType(0), Offset);
15150 if (Result.getNode()) {
15151 Ops.push_back(Result);
15154 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
15157 std::pair<unsigned, const TargetRegisterClass*>
15158 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
15160 // First, see if this is a constraint that directly corresponds to an LLVM
15162 if (Constraint.size() == 1) {
15163 // GCC Constraint Letters
15164 switch (Constraint[0]) {
15166 // TODO: Slight differences here in allocation order and leaving
15167 // RIP in the class. Do they matter any more here than they do
15168 // in the normal allocation?
15169 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
15170 if (Subtarget->is64Bit()) {
15171 if (VT == MVT::i32 || VT == MVT::f32)
15172 return std::make_pair(0U, X86::GR32RegisterClass);
15173 else if (VT == MVT::i16)
15174 return std::make_pair(0U, X86::GR16RegisterClass);
15175 else if (VT == MVT::i8 || VT == MVT::i1)
15176 return std::make_pair(0U, X86::GR8RegisterClass);
15177 else if (VT == MVT::i64 || VT == MVT::f64)
15178 return std::make_pair(0U, X86::GR64RegisterClass);
15181 // 32-bit fallthrough
15182 case 'Q': // Q_REGS
15183 if (VT == MVT::i32 || VT == MVT::f32)
15184 return std::make_pair(0U, X86::GR32_ABCDRegisterClass);
15185 else if (VT == MVT::i16)
15186 return std::make_pair(0U, X86::GR16_ABCDRegisterClass);
15187 else if (VT == MVT::i8 || VT == MVT::i1)
15188 return std::make_pair(0U, X86::GR8_ABCD_LRegisterClass);
15189 else if (VT == MVT::i64)
15190 return std::make_pair(0U, X86::GR64_ABCDRegisterClass);
15192 case 'r': // GENERAL_REGS
15193 case 'l': // INDEX_REGS
15194 if (VT == MVT::i8 || VT == MVT::i1)
15195 return std::make_pair(0U, X86::GR8RegisterClass);
15196 if (VT == MVT::i16)
15197 return std::make_pair(0U, X86::GR16RegisterClass);
15198 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
15199 return std::make_pair(0U, X86::GR32RegisterClass);
15200 return std::make_pair(0U, X86::GR64RegisterClass);
15201 case 'R': // LEGACY_REGS
15202 if (VT == MVT::i8 || VT == MVT::i1)
15203 return std::make_pair(0U, X86::GR8_NOREXRegisterClass);
15204 if (VT == MVT::i16)
15205 return std::make_pair(0U, X86::GR16_NOREXRegisterClass);
15206 if (VT == MVT::i32 || !Subtarget->is64Bit())
15207 return std::make_pair(0U, X86::GR32_NOREXRegisterClass);
15208 return std::make_pair(0U, X86::GR64_NOREXRegisterClass);
15209 case 'f': // FP Stack registers.
15210 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
15211 // value to the correct fpstack register class.
15212 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
15213 return std::make_pair(0U, X86::RFP32RegisterClass);
15214 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
15215 return std::make_pair(0U, X86::RFP64RegisterClass);
15216 return std::make_pair(0U, X86::RFP80RegisterClass);
15217 case 'y': // MMX_REGS if MMX allowed.
15218 if (!Subtarget->hasMMX()) break;
15219 return std::make_pair(0U, X86::VR64RegisterClass);
15220 case 'Y': // SSE_REGS if SSE2 allowed
15221 if (!Subtarget->hasXMMInt()) break;
15223 case 'x': // SSE_REGS if SSE1 allowed
15224 if (!Subtarget->hasXMM()) break;
15226 switch (VT.getSimpleVT().SimpleTy) {
15228 // Scalar SSE types.
15231 return std::make_pair(0U, X86::FR32RegisterClass);
15234 return std::make_pair(0U, X86::FR64RegisterClass);
15242 return std::make_pair(0U, X86::VR128RegisterClass);
15248 // Use the default implementation in TargetLowering to convert the register
15249 // constraint into a member of a register class.
15250 std::pair<unsigned, const TargetRegisterClass*> Res;
15251 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
15253 // Not found as a standard register?
15254 if (Res.second == 0) {
15255 // Map st(0) -> st(7) -> ST0
15256 if (Constraint.size() == 7 && Constraint[0] == '{' &&
15257 tolower(Constraint[1]) == 's' &&
15258 tolower(Constraint[2]) == 't' &&
15259 Constraint[3] == '(' &&
15260 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
15261 Constraint[5] == ')' &&
15262 Constraint[6] == '}') {
15264 Res.first = X86::ST0+Constraint[4]-'0';
15265 Res.second = X86::RFP80RegisterClass;
15269 // GCC allows "st(0)" to be called just plain "st".
15270 if (StringRef("{st}").equals_lower(Constraint)) {
15271 Res.first = X86::ST0;
15272 Res.second = X86::RFP80RegisterClass;
15277 if (StringRef("{flags}").equals_lower(Constraint)) {
15278 Res.first = X86::EFLAGS;
15279 Res.second = X86::CCRRegisterClass;
15283 // 'A' means EAX + EDX.
15284 if (Constraint == "A") {
15285 Res.first = X86::EAX;
15286 Res.second = X86::GR32_ADRegisterClass;
15292 // Otherwise, check to see if this is a register class of the wrong value
15293 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
15294 // turn into {ax},{dx}.
15295 if (Res.second->hasType(VT))
15296 return Res; // Correct type already, nothing to do.
15298 // All of the single-register GCC register classes map their values onto
15299 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
15300 // really want an 8-bit or 32-bit register, map to the appropriate register
15301 // class and return the appropriate register.
15302 if (Res.second == X86::GR16RegisterClass) {
15303 if (VT == MVT::i8) {
15304 unsigned DestReg = 0;
15305 switch (Res.first) {
15307 case X86::AX: DestReg = X86::AL; break;
15308 case X86::DX: DestReg = X86::DL; break;
15309 case X86::CX: DestReg = X86::CL; break;
15310 case X86::BX: DestReg = X86::BL; break;
15313 Res.first = DestReg;
15314 Res.second = X86::GR8RegisterClass;
15316 } else if (VT == MVT::i32) {
15317 unsigned DestReg = 0;
15318 switch (Res.first) {
15320 case X86::AX: DestReg = X86::EAX; break;
15321 case X86::DX: DestReg = X86::EDX; break;
15322 case X86::CX: DestReg = X86::ECX; break;
15323 case X86::BX: DestReg = X86::EBX; break;
15324 case X86::SI: DestReg = X86::ESI; break;
15325 case X86::DI: DestReg = X86::EDI; break;
15326 case X86::BP: DestReg = X86::EBP; break;
15327 case X86::SP: DestReg = X86::ESP; break;
15330 Res.first = DestReg;
15331 Res.second = X86::GR32RegisterClass;
15333 } else if (VT == MVT::i64) {
15334 unsigned DestReg = 0;
15335 switch (Res.first) {
15337 case X86::AX: DestReg = X86::RAX; break;
15338 case X86::DX: DestReg = X86::RDX; break;
15339 case X86::CX: DestReg = X86::RCX; break;
15340 case X86::BX: DestReg = X86::RBX; break;
15341 case X86::SI: DestReg = X86::RSI; break;
15342 case X86::DI: DestReg = X86::RDI; break;
15343 case X86::BP: DestReg = X86::RBP; break;
15344 case X86::SP: DestReg = X86::RSP; break;
15347 Res.first = DestReg;
15348 Res.second = X86::GR64RegisterClass;
15351 } else if (Res.second == X86::FR32RegisterClass ||
15352 Res.second == X86::FR64RegisterClass ||
15353 Res.second == X86::VR128RegisterClass) {
15354 // Handle references to XMM physical registers that got mapped into the
15355 // wrong class. This can happen with constraints like {xmm0} where the
15356 // target independent register mapper will just pick the first match it can
15357 // find, ignoring the required type.
15358 if (VT == MVT::f32)
15359 Res.second = X86::FR32RegisterClass;
15360 else if (VT == MVT::f64)
15361 Res.second = X86::FR64RegisterClass;
15362 else if (X86::VR128RegisterClass->hasType(VT))
15363 Res.second = X86::VR128RegisterClass;