1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
16 #include "X86ISelLowering.h"
17 #include "Utils/X86ShuffleDecode.h"
18 #include "X86CallingConv.h"
19 #include "X86InstrBuilder.h"
20 #include "X86MachineFunctionInfo.h"
21 #include "X86TargetMachine.h"
22 #include "X86TargetObjectFile.h"
23 #include "llvm/ADT/SmallSet.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/ADT/VariadicFunction.h"
27 #include "llvm/CodeGen/IntrinsicLowering.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineJumpTableInfo.h"
32 #include "llvm/CodeGen/MachineModuleInfo.h"
33 #include "llvm/CodeGen/MachineRegisterInfo.h"
34 #include "llvm/IR/CallSite.h"
35 #include "llvm/IR/CallingConv.h"
36 #include "llvm/IR/Constants.h"
37 #include "llvm/IR/DerivedTypes.h"
38 #include "llvm/IR/Function.h"
39 #include "llvm/IR/GlobalAlias.h"
40 #include "llvm/IR/GlobalVariable.h"
41 #include "llvm/IR/Instructions.h"
42 #include "llvm/IR/Intrinsics.h"
43 #include "llvm/MC/MCAsmInfo.h"
44 #include "llvm/MC/MCContext.h"
45 #include "llvm/MC/MCExpr.h"
46 #include "llvm/MC/MCSymbol.h"
47 #include "llvm/Support/Debug.h"
48 #include "llvm/Support/ErrorHandling.h"
49 #include "llvm/Support/MathExtras.h"
50 #include "llvm/Target/TargetOptions.h"
55 STATISTIC(NumTailCalls, "Number of tail calls");
57 // Forward declarations.
58 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
61 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
62 SelectionDAG &DAG, SDLoc dl,
63 unsigned vectorWidth) {
64 assert((vectorWidth == 128 || vectorWidth == 256) &&
65 "Unsupported vector width");
66 EVT VT = Vec.getValueType();
67 EVT ElVT = VT.getVectorElementType();
68 unsigned Factor = VT.getSizeInBits()/vectorWidth;
69 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
70 VT.getVectorNumElements()/Factor);
72 // Extract from UNDEF is UNDEF.
73 if (Vec.getOpcode() == ISD::UNDEF)
74 return DAG.getUNDEF(ResultVT);
76 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
77 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
79 // This is the index of the first element of the vectorWidth-bit chunk
81 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
84 // If the input is a buildvector just emit a smaller one.
85 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
86 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
87 Vec->op_begin()+NormalizedIdxVal, ElemsPerChunk);
89 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
90 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
96 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
97 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
98 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
99 /// instructions or a simple subregister reference. Idx is an index in the
100 /// 128 bits we want. It need not be aligned to a 128-bit bounday. That makes
101 /// lowering EXTRACT_VECTOR_ELT operations easier.
102 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
103 SelectionDAG &DAG, SDLoc dl) {
104 assert((Vec.getValueType().is256BitVector() ||
105 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
106 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
109 /// Generate a DAG to grab 256-bits from a 512-bit vector.
110 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
111 SelectionDAG &DAG, SDLoc dl) {
112 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
113 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
116 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
117 unsigned IdxVal, SelectionDAG &DAG,
118 SDLoc dl, unsigned vectorWidth) {
119 assert((vectorWidth == 128 || vectorWidth == 256) &&
120 "Unsupported vector width");
121 // Inserting UNDEF is Result
122 if (Vec.getOpcode() == ISD::UNDEF)
124 EVT VT = Vec.getValueType();
125 EVT ElVT = VT.getVectorElementType();
126 EVT ResultVT = Result.getValueType();
128 // Insert the relevant vectorWidth bits.
129 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
131 // This is the index of the first element of the vectorWidth-bit chunk
133 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
136 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
137 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
140 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
141 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
142 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
143 /// simple superregister reference. Idx is an index in the 128 bits
144 /// we want. It need not be aligned to a 128-bit bounday. That makes
145 /// lowering INSERT_VECTOR_ELT operations easier.
146 static SDValue Insert128BitVector(SDValue Result, SDValue Vec,
147 unsigned IdxVal, SelectionDAG &DAG,
149 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
150 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
153 static SDValue Insert256BitVector(SDValue Result, SDValue Vec,
154 unsigned IdxVal, SelectionDAG &DAG,
156 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
157 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
160 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
161 /// instructions. This is used because creating CONCAT_VECTOR nodes of
162 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
163 /// large BUILD_VECTORS.
164 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
165 unsigned NumElems, SelectionDAG &DAG,
167 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
168 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
171 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
172 unsigned NumElems, SelectionDAG &DAG,
174 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
175 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
178 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
179 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
180 bool is64Bit = Subtarget->is64Bit();
182 if (Subtarget->isTargetMacho()) {
184 return new X86_64MachoTargetObjectFile();
185 return new TargetLoweringObjectFileMachO();
188 if (Subtarget->isTargetLinux())
189 return new X86LinuxTargetObjectFile();
190 if (Subtarget->isTargetELF())
191 return new TargetLoweringObjectFileELF();
192 if (Subtarget->isTargetKnownWindowsMSVC())
193 return new X86WindowsTargetObjectFile();
194 if (Subtarget->isTargetCOFF())
195 return new TargetLoweringObjectFileCOFF();
196 llvm_unreachable("unknown subtarget type");
199 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
200 : TargetLowering(TM, createTLOF(TM)) {
201 Subtarget = &TM.getSubtarget<X86Subtarget>();
202 X86ScalarSSEf64 = Subtarget->hasSSE2();
203 X86ScalarSSEf32 = Subtarget->hasSSE1();
204 TD = getDataLayout();
206 resetOperationActions();
209 void X86TargetLowering::resetOperationActions() {
210 const TargetMachine &TM = getTargetMachine();
211 static bool FirstTimeThrough = true;
213 // If none of the target options have changed, then we don't need to reset the
214 // operation actions.
215 if (!FirstTimeThrough && TO == TM.Options) return;
217 if (!FirstTimeThrough) {
218 // Reinitialize the actions.
220 FirstTimeThrough = false;
225 // Set up the TargetLowering object.
226 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
228 // X86 is weird, it always uses i8 for shift amounts and setcc results.
229 setBooleanContents(ZeroOrOneBooleanContent);
230 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
231 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
233 // For 64-bit since we have so many registers use the ILP scheduler, for
234 // 32-bit code use the register pressure specific scheduling.
235 // For Atom, always use ILP scheduling.
236 if (Subtarget->isAtom())
237 setSchedulingPreference(Sched::ILP);
238 else if (Subtarget->is64Bit())
239 setSchedulingPreference(Sched::ILP);
241 setSchedulingPreference(Sched::RegPressure);
242 const X86RegisterInfo *RegInfo =
243 static_cast<const X86RegisterInfo*>(TM.getRegisterInfo());
244 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
246 // Bypass expensive divides on Atom when compiling with O2
247 if (Subtarget->hasSlowDivide() && TM.getOptLevel() >= CodeGenOpt::Default) {
248 addBypassSlowDiv(32, 8);
249 if (Subtarget->is64Bit())
250 addBypassSlowDiv(64, 16);
253 if (Subtarget->isTargetKnownWindowsMSVC()) {
254 // Setup Windows compiler runtime calls.
255 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
256 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
257 setLibcallName(RTLIB::SREM_I64, "_allrem");
258 setLibcallName(RTLIB::UREM_I64, "_aullrem");
259 setLibcallName(RTLIB::MUL_I64, "_allmul");
260 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
261 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
262 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
263 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
264 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
266 // The _ftol2 runtime function has an unusual calling conv, which
267 // is modeled by a special pseudo-instruction.
268 setLibcallName(RTLIB::FPTOUINT_F64_I64, 0);
269 setLibcallName(RTLIB::FPTOUINT_F32_I64, 0);
270 setLibcallName(RTLIB::FPTOUINT_F64_I32, 0);
271 setLibcallName(RTLIB::FPTOUINT_F32_I32, 0);
274 if (Subtarget->isTargetDarwin()) {
275 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
276 setUseUnderscoreSetJmp(false);
277 setUseUnderscoreLongJmp(false);
278 } else if (Subtarget->isTargetWindowsGNU()) {
279 // MS runtime is weird: it exports _setjmp, but longjmp!
280 setUseUnderscoreSetJmp(true);
281 setUseUnderscoreLongJmp(false);
283 setUseUnderscoreSetJmp(true);
284 setUseUnderscoreLongJmp(true);
287 // Set up the register classes.
288 addRegisterClass(MVT::i8, &X86::GR8RegClass);
289 addRegisterClass(MVT::i16, &X86::GR16RegClass);
290 addRegisterClass(MVT::i32, &X86::GR32RegClass);
291 if (Subtarget->is64Bit())
292 addRegisterClass(MVT::i64, &X86::GR64RegClass);
294 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
296 // We don't accept any truncstore of integer registers.
297 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
298 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
299 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
300 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
301 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
302 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
304 // SETOEQ and SETUNE require checking two conditions.
305 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
306 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
307 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
308 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
309 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
310 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
312 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
314 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
315 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
316 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
318 if (Subtarget->is64Bit()) {
319 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
320 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
321 } else if (!TM.Options.UseSoftFloat) {
322 // We have an algorithm for SSE2->double, and we turn this into a
323 // 64-bit FILD followed by conditional FADD for other targets.
324 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
325 // We have an algorithm for SSE2, and we turn this into a 64-bit
326 // FILD for other targets.
327 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
330 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
332 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
333 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
335 if (!TM.Options.UseSoftFloat) {
336 // SSE has no i16 to fp conversion, only i32
337 if (X86ScalarSSEf32) {
338 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
339 // f32 and f64 cases are Legal, f80 case is not
340 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
342 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
343 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
346 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
347 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
350 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
351 // are Legal, f80 is custom lowered.
352 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
353 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
355 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
357 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
358 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
360 if (X86ScalarSSEf32) {
361 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
362 // f32 and f64 cases are Legal, f80 case is not
363 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
365 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
366 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
369 // Handle FP_TO_UINT by promoting the destination to a larger signed
371 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
372 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
373 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
375 if (Subtarget->is64Bit()) {
376 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
377 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
378 } else if (!TM.Options.UseSoftFloat) {
379 // Since AVX is a superset of SSE3, only check for SSE here.
380 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
381 // Expand FP_TO_UINT into a select.
382 // FIXME: We would like to use a Custom expander here eventually to do
383 // the optimal thing for SSE vs. the default expansion in the legalizer.
384 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
386 // With SSE3 we can use fisttpll to convert to a signed i64; without
387 // SSE, we're stuck with a fistpll.
388 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
391 if (isTargetFTOL()) {
392 // Use the _ftol2 runtime function, which has a pseudo-instruction
393 // to handle its weird calling convention.
394 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
397 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
398 if (!X86ScalarSSEf64) {
399 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
400 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
401 if (Subtarget->is64Bit()) {
402 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
403 // Without SSE, i64->f64 goes through memory.
404 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
408 // Scalar integer divide and remainder are lowered to use operations that
409 // produce two results, to match the available instructions. This exposes
410 // the two-result form to trivial CSE, which is able to combine x/y and x%y
411 // into a single instruction.
413 // Scalar integer multiply-high is also lowered to use two-result
414 // operations, to match the available instructions. However, plain multiply
415 // (low) operations are left as Legal, as there are single-result
416 // instructions for this in x86. Using the two-result multiply instructions
417 // when both high and low results are needed must be arranged by dagcombine.
418 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
420 setOperationAction(ISD::MULHS, VT, Expand);
421 setOperationAction(ISD::MULHU, VT, Expand);
422 setOperationAction(ISD::SDIV, VT, Expand);
423 setOperationAction(ISD::UDIV, VT, Expand);
424 setOperationAction(ISD::SREM, VT, Expand);
425 setOperationAction(ISD::UREM, VT, Expand);
427 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
428 setOperationAction(ISD::ADDC, VT, Custom);
429 setOperationAction(ISD::ADDE, VT, Custom);
430 setOperationAction(ISD::SUBC, VT, Custom);
431 setOperationAction(ISD::SUBE, VT, Custom);
434 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
435 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
436 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
437 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
438 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
439 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
440 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
441 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
442 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
443 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
444 if (Subtarget->is64Bit())
445 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
446 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
447 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
448 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
449 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
450 setOperationAction(ISD::FREM , MVT::f32 , Expand);
451 setOperationAction(ISD::FREM , MVT::f64 , Expand);
452 setOperationAction(ISD::FREM , MVT::f80 , Expand);
453 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
455 // Promote the i8 variants and force them on up to i32 which has a shorter
457 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
458 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
459 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
460 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
461 if (Subtarget->hasBMI()) {
462 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
463 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
464 if (Subtarget->is64Bit())
465 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
467 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
468 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
469 if (Subtarget->is64Bit())
470 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
473 if (Subtarget->hasLZCNT()) {
474 // When promoting the i8 variants, force them to i32 for a shorter
476 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
477 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
478 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
479 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
480 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
481 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
482 if (Subtarget->is64Bit())
483 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
485 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
486 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
487 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
488 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
489 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
490 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
491 if (Subtarget->is64Bit()) {
492 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
493 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
497 if (Subtarget->hasPOPCNT()) {
498 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
500 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
501 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
502 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
503 if (Subtarget->is64Bit())
504 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
507 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
509 if (!Subtarget->hasMOVBE())
510 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
512 // These should be promoted to a larger select which is supported.
513 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
514 // X86 wants to expand cmov itself.
515 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
516 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
517 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
518 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
519 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
520 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
521 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
522 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
523 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
524 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
525 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
526 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
527 if (Subtarget->is64Bit()) {
528 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
529 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
531 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
532 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
533 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
534 // support continuation, user-level threading, and etc.. As a result, no
535 // other SjLj exception interfaces are implemented and please don't build
536 // your own exception handling based on them.
537 // LLVM/Clang supports zero-cost DWARF exception handling.
538 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
539 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
542 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
543 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
544 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
545 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
546 if (Subtarget->is64Bit())
547 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
548 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
549 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
550 if (Subtarget->is64Bit()) {
551 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
552 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
553 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
554 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
555 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
557 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
558 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
559 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
560 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
561 if (Subtarget->is64Bit()) {
562 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
563 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
564 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
567 if (Subtarget->hasSSE1())
568 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
570 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
572 // Expand certain atomics
573 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
575 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom);
576 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
577 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
580 if (!Subtarget->is64Bit()) {
581 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
582 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
583 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
584 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
585 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
586 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
587 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
588 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
589 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i64, Custom);
590 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i64, Custom);
591 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i64, Custom);
592 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i64, Custom);
595 if (Subtarget->hasCmpxchg16b()) {
596 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom);
599 // FIXME - use subtarget debug flags
600 if (!Subtarget->isTargetDarwin() &&
601 !Subtarget->isTargetELF() &&
602 !Subtarget->isTargetCygMing()) {
603 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
606 if (Subtarget->is64Bit()) {
607 setExceptionPointerRegister(X86::RAX);
608 setExceptionSelectorRegister(X86::RDX);
610 setExceptionPointerRegister(X86::EAX);
611 setExceptionSelectorRegister(X86::EDX);
613 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
614 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
616 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
617 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
619 setOperationAction(ISD::TRAP, MVT::Other, Legal);
620 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
622 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
623 setOperationAction(ISD::VASTART , MVT::Other, Custom);
624 setOperationAction(ISD::VAEND , MVT::Other, Expand);
625 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
626 // TargetInfo::X86_64ABIBuiltinVaList
627 setOperationAction(ISD::VAARG , MVT::Other, Custom);
628 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
630 // TargetInfo::CharPtrBuiltinVaList
631 setOperationAction(ISD::VAARG , MVT::Other, Expand);
632 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
635 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
636 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
638 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
639 MVT::i64 : MVT::i32, Custom);
641 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
642 // f32 and f64 use SSE.
643 // Set up the FP register classes.
644 addRegisterClass(MVT::f32, &X86::FR32RegClass);
645 addRegisterClass(MVT::f64, &X86::FR64RegClass);
647 // Use ANDPD to simulate FABS.
648 setOperationAction(ISD::FABS , MVT::f64, Custom);
649 setOperationAction(ISD::FABS , MVT::f32, Custom);
651 // Use XORP to simulate FNEG.
652 setOperationAction(ISD::FNEG , MVT::f64, Custom);
653 setOperationAction(ISD::FNEG , MVT::f32, Custom);
655 // Use ANDPD and ORPD to simulate FCOPYSIGN.
656 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
657 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
659 // Lower this to FGETSIGNx86 plus an AND.
660 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
661 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
663 // We don't support sin/cos/fmod
664 setOperationAction(ISD::FSIN , MVT::f64, Expand);
665 setOperationAction(ISD::FCOS , MVT::f64, Expand);
666 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
667 setOperationAction(ISD::FSIN , MVT::f32, Expand);
668 setOperationAction(ISD::FCOS , MVT::f32, Expand);
669 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
671 // Expand FP immediates into loads from the stack, except for the special
673 addLegalFPImmediate(APFloat(+0.0)); // xorpd
674 addLegalFPImmediate(APFloat(+0.0f)); // xorps
675 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
676 // Use SSE for f32, x87 for f64.
677 // Set up the FP register classes.
678 addRegisterClass(MVT::f32, &X86::FR32RegClass);
679 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
681 // Use ANDPS to simulate FABS.
682 setOperationAction(ISD::FABS , MVT::f32, Custom);
684 // Use XORP to simulate FNEG.
685 setOperationAction(ISD::FNEG , MVT::f32, Custom);
687 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
689 // Use ANDPS and ORPS to simulate FCOPYSIGN.
690 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
691 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
693 // We don't support sin/cos/fmod
694 setOperationAction(ISD::FSIN , MVT::f32, Expand);
695 setOperationAction(ISD::FCOS , MVT::f32, Expand);
696 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
698 // Special cases we handle for FP constants.
699 addLegalFPImmediate(APFloat(+0.0f)); // xorps
700 addLegalFPImmediate(APFloat(+0.0)); // FLD0
701 addLegalFPImmediate(APFloat(+1.0)); // FLD1
702 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
703 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
705 if (!TM.Options.UnsafeFPMath) {
706 setOperationAction(ISD::FSIN , MVT::f64, Expand);
707 setOperationAction(ISD::FCOS , MVT::f64, Expand);
708 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
710 } else if (!TM.Options.UseSoftFloat) {
711 // f32 and f64 in x87.
712 // Set up the FP register classes.
713 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
714 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
716 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
717 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
718 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
719 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
721 if (!TM.Options.UnsafeFPMath) {
722 setOperationAction(ISD::FSIN , MVT::f64, Expand);
723 setOperationAction(ISD::FSIN , MVT::f32, Expand);
724 setOperationAction(ISD::FCOS , MVT::f64, Expand);
725 setOperationAction(ISD::FCOS , MVT::f32, Expand);
726 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
727 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
729 addLegalFPImmediate(APFloat(+0.0)); // FLD0
730 addLegalFPImmediate(APFloat(+1.0)); // FLD1
731 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
732 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
733 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
734 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
735 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
736 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
739 // We don't support FMA.
740 setOperationAction(ISD::FMA, MVT::f64, Expand);
741 setOperationAction(ISD::FMA, MVT::f32, Expand);
743 // Long double always uses X87.
744 if (!TM.Options.UseSoftFloat) {
745 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
746 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
747 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
749 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
750 addLegalFPImmediate(TmpFlt); // FLD0
752 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
755 APFloat TmpFlt2(+1.0);
756 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
758 addLegalFPImmediate(TmpFlt2); // FLD1
759 TmpFlt2.changeSign();
760 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
763 if (!TM.Options.UnsafeFPMath) {
764 setOperationAction(ISD::FSIN , MVT::f80, Expand);
765 setOperationAction(ISD::FCOS , MVT::f80, Expand);
766 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
769 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
770 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
771 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
772 setOperationAction(ISD::FRINT, MVT::f80, Expand);
773 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
774 setOperationAction(ISD::FMA, MVT::f80, Expand);
777 // Always use a library call for pow.
778 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
779 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
780 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
782 setOperationAction(ISD::FLOG, MVT::f80, Expand);
783 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
784 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
785 setOperationAction(ISD::FEXP, MVT::f80, Expand);
786 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
788 // First set operation action for all vector types to either promote
789 // (for widening) or expand (for scalarization). Then we will selectively
790 // turn on ones that can be effectively codegen'd.
791 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
792 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
793 MVT VT = (MVT::SimpleValueType)i;
794 setOperationAction(ISD::ADD , VT, Expand);
795 setOperationAction(ISD::SUB , VT, Expand);
796 setOperationAction(ISD::FADD, VT, Expand);
797 setOperationAction(ISD::FNEG, VT, Expand);
798 setOperationAction(ISD::FSUB, VT, Expand);
799 setOperationAction(ISD::MUL , VT, Expand);
800 setOperationAction(ISD::FMUL, VT, Expand);
801 setOperationAction(ISD::SDIV, VT, Expand);
802 setOperationAction(ISD::UDIV, VT, Expand);
803 setOperationAction(ISD::FDIV, VT, Expand);
804 setOperationAction(ISD::SREM, VT, Expand);
805 setOperationAction(ISD::UREM, VT, Expand);
806 setOperationAction(ISD::LOAD, VT, Expand);
807 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
808 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
809 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
810 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
811 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
812 setOperationAction(ISD::FABS, VT, Expand);
813 setOperationAction(ISD::FSIN, VT, Expand);
814 setOperationAction(ISD::FSINCOS, VT, Expand);
815 setOperationAction(ISD::FCOS, VT, Expand);
816 setOperationAction(ISD::FSINCOS, VT, Expand);
817 setOperationAction(ISD::FREM, VT, Expand);
818 setOperationAction(ISD::FMA, VT, Expand);
819 setOperationAction(ISD::FPOWI, VT, Expand);
820 setOperationAction(ISD::FSQRT, VT, Expand);
821 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
822 setOperationAction(ISD::FFLOOR, VT, Expand);
823 setOperationAction(ISD::FCEIL, VT, Expand);
824 setOperationAction(ISD::FTRUNC, VT, Expand);
825 setOperationAction(ISD::FRINT, VT, Expand);
826 setOperationAction(ISD::FNEARBYINT, VT, Expand);
827 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
828 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
829 setOperationAction(ISD::SDIVREM, VT, Expand);
830 setOperationAction(ISD::UDIVREM, VT, Expand);
831 setOperationAction(ISD::FPOW, VT, Expand);
832 setOperationAction(ISD::CTPOP, VT, Expand);
833 setOperationAction(ISD::CTTZ, VT, Expand);
834 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
835 setOperationAction(ISD::CTLZ, VT, Expand);
836 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
837 setOperationAction(ISD::SHL, VT, Expand);
838 setOperationAction(ISD::SRA, VT, Expand);
839 setOperationAction(ISD::SRL, VT, Expand);
840 setOperationAction(ISD::ROTL, VT, Expand);
841 setOperationAction(ISD::ROTR, VT, Expand);
842 setOperationAction(ISD::BSWAP, VT, Expand);
843 setOperationAction(ISD::SETCC, VT, Expand);
844 setOperationAction(ISD::FLOG, VT, Expand);
845 setOperationAction(ISD::FLOG2, VT, Expand);
846 setOperationAction(ISD::FLOG10, VT, Expand);
847 setOperationAction(ISD::FEXP, VT, Expand);
848 setOperationAction(ISD::FEXP2, VT, Expand);
849 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
850 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
851 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
852 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
853 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
854 setOperationAction(ISD::TRUNCATE, VT, Expand);
855 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
856 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
857 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
858 setOperationAction(ISD::VSELECT, VT, Expand);
859 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
860 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
861 setTruncStoreAction(VT,
862 (MVT::SimpleValueType)InnerVT, Expand);
863 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
864 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
865 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
868 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
869 // with -msoft-float, disable use of MMX as well.
870 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
871 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
872 // No operations on x86mmx supported, everything uses intrinsics.
875 // MMX-sized vectors (other than x86mmx) are expected to be expanded
876 // into smaller operations.
877 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
878 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
879 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
880 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
881 setOperationAction(ISD::AND, MVT::v8i8, Expand);
882 setOperationAction(ISD::AND, MVT::v4i16, Expand);
883 setOperationAction(ISD::AND, MVT::v2i32, Expand);
884 setOperationAction(ISD::AND, MVT::v1i64, Expand);
885 setOperationAction(ISD::OR, MVT::v8i8, Expand);
886 setOperationAction(ISD::OR, MVT::v4i16, Expand);
887 setOperationAction(ISD::OR, MVT::v2i32, Expand);
888 setOperationAction(ISD::OR, MVT::v1i64, Expand);
889 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
890 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
891 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
892 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
893 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
894 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
895 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
896 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
897 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
898 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
899 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
900 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
901 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
902 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
903 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
904 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
905 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
907 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
908 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
910 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
911 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
912 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
913 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
914 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
915 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
916 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
917 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
918 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
919 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
920 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
921 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
924 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
925 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
927 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
928 // registers cannot be used even for integer operations.
929 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
930 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
931 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
932 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
934 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
935 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
936 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
937 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
938 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
939 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
940 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
941 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
942 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
943 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
944 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
945 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
946 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
947 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
948 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
949 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
950 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
951 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
953 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
954 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
955 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
956 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
958 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
959 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
960 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
961 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
962 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
964 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
965 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
966 MVT VT = (MVT::SimpleValueType)i;
967 // Do not attempt to custom lower non-power-of-2 vectors
968 if (!isPowerOf2_32(VT.getVectorNumElements()))
970 // Do not attempt to custom lower non-128-bit vectors
971 if (!VT.is128BitVector())
973 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
974 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
975 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
978 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
979 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
980 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
981 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
982 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
983 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
985 if (Subtarget->is64Bit()) {
986 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
987 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
990 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
991 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
992 MVT VT = (MVT::SimpleValueType)i;
994 // Do not attempt to promote non-128-bit vectors
995 if (!VT.is128BitVector())
998 setOperationAction(ISD::AND, VT, Promote);
999 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
1000 setOperationAction(ISD::OR, VT, Promote);
1001 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
1002 setOperationAction(ISD::XOR, VT, Promote);
1003 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
1004 setOperationAction(ISD::LOAD, VT, Promote);
1005 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
1006 setOperationAction(ISD::SELECT, VT, Promote);
1007 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
1010 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
1012 // Custom lower v2i64 and v2f64 selects.
1013 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1014 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
1015 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
1016 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1018 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1019 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1021 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1022 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1023 // As there is no 64-bit GPR available, we need build a special custom
1024 // sequence to convert from v2i32 to v2f32.
1025 if (!Subtarget->is64Bit())
1026 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
1028 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1029 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1031 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal);
1034 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
1035 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1036 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1037 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1038 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1039 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1040 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1041 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1042 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1043 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1044 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1046 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1047 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1048 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1049 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1050 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1051 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1052 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1053 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1054 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1055 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1057 // FIXME: Do we need to handle scalar-to-vector here?
1058 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1060 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
1061 setOperationAction(ISD::VSELECT, MVT::v2i64, Legal);
1062 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1063 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
1064 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
1066 // i8 and i16 vectors are custom , because the source register and source
1067 // source memory operand types are not the same width. f32 vectors are
1068 // custom since the immediate controlling the insert encodes additional
1070 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1071 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1072 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1073 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1075 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1076 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1077 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1078 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1080 // FIXME: these should be Legal but thats only for the case where
1081 // the index is constant. For now custom expand to deal with that.
1082 if (Subtarget->is64Bit()) {
1083 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1084 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1088 if (Subtarget->hasSSE2()) {
1089 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1090 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1092 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1093 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1095 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1096 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1098 // In the customized shift lowering, the legal cases in AVX2 will be
1100 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1101 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1103 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1104 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1106 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1108 setOperationAction(ISD::SDIV, MVT::v8i16, Custom);
1109 setOperationAction(ISD::SDIV, MVT::v4i32, Custom);
1112 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1113 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1114 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1115 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1116 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1117 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1118 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1120 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1121 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1122 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1124 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1125 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1126 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1127 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1128 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1129 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1130 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1131 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1132 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1133 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1134 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1135 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1137 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1138 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1139 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1140 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1141 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1142 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1143 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1144 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1145 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1146 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1147 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1148 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1150 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1151 // even though v8i16 is a legal type.
1152 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1153 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1154 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1156 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1157 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1158 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1160 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1161 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1163 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal);
1165 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1166 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1168 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1169 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1171 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1172 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1174 setOperationAction(ISD::SDIV, MVT::v16i16, Custom);
1176 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1177 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1178 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1179 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1181 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1182 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1183 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1185 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal);
1186 setOperationAction(ISD::VSELECT, MVT::v4i64, Legal);
1187 setOperationAction(ISD::VSELECT, MVT::v8i32, Legal);
1188 setOperationAction(ISD::VSELECT, MVT::v8f32, Legal);
1190 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1191 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1192 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1193 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1194 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1195 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1196 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1197 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1198 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1199 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1200 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1201 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1203 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1204 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1205 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1206 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1207 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1208 setOperationAction(ISD::FMA, MVT::f32, Legal);
1209 setOperationAction(ISD::FMA, MVT::f64, Legal);
1212 if (Subtarget->hasInt256()) {
1213 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1214 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1215 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1216 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1218 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1219 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1220 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1221 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1223 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1224 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1225 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1226 // Don't lower v32i8 because there is no 128-bit byte mul
1228 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1230 setOperationAction(ISD::SDIV, MVT::v8i32, Custom);
1232 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1233 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1234 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1235 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1237 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1238 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1239 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1240 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1242 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1243 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1244 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1245 // Don't lower v32i8 because there is no 128-bit byte mul
1248 // In the customized shift lowering, the legal cases in AVX2 will be
1250 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1251 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1253 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1254 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1256 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1258 // Custom lower several nodes for 256-bit types.
1259 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1260 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1261 MVT VT = (MVT::SimpleValueType)i;
1263 // Extract subvector is special because the value type
1264 // (result) is 128-bit but the source is 256-bit wide.
1265 if (VT.is128BitVector())
1266 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1268 // Do not attempt to custom lower other non-256-bit vectors
1269 if (!VT.is256BitVector())
1272 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1273 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1274 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1275 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1276 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1277 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1278 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1281 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1282 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1283 MVT VT = (MVT::SimpleValueType)i;
1285 // Do not attempt to promote non-256-bit vectors
1286 if (!VT.is256BitVector())
1289 setOperationAction(ISD::AND, VT, Promote);
1290 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1291 setOperationAction(ISD::OR, VT, Promote);
1292 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1293 setOperationAction(ISD::XOR, VT, Promote);
1294 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1295 setOperationAction(ISD::LOAD, VT, Promote);
1296 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1297 setOperationAction(ISD::SELECT, VT, Promote);
1298 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1302 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) {
1303 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1304 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1305 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1306 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1308 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1309 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1310 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1312 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1313 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1314 setOperationAction(ISD::XOR, MVT::i1, Legal);
1315 setOperationAction(ISD::OR, MVT::i1, Legal);
1316 setOperationAction(ISD::AND, MVT::i1, Legal);
1317 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, Legal);
1318 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1319 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1320 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1321 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1322 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1324 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1325 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1326 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1327 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1328 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1329 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1331 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1332 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1333 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1334 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1335 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1336 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1337 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1338 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1339 setOperationAction(ISD::SDIV, MVT::v16i32, Custom);
1341 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1342 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1343 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1344 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1345 if (Subtarget->is64Bit()) {
1346 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1347 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1348 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1349 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1351 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1352 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1353 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1354 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1355 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1356 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1357 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1358 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1359 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1360 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1362 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1363 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1364 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1365 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1366 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1367 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1368 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1369 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1370 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1371 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1372 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1373 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1374 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1376 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1377 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1378 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1379 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1380 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1381 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1383 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1384 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1386 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1388 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1389 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1390 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1391 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1392 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1393 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1394 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1395 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1396 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1398 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1399 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1401 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1402 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1404 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1406 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1407 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1409 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1410 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1412 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1413 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1415 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1416 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1417 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1418 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1419 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1420 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1422 // Custom lower several nodes.
1423 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1424 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1425 MVT VT = (MVT::SimpleValueType)i;
1427 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1428 // Extract subvector is special because the value type
1429 // (result) is 256/128-bit but the source is 512-bit wide.
1430 if (VT.is128BitVector() || VT.is256BitVector())
1431 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1433 if (VT.getVectorElementType() == MVT::i1)
1434 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1436 // Do not attempt to custom lower other non-512-bit vectors
1437 if (!VT.is512BitVector())
1440 if ( EltSize >= 32) {
1441 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1442 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1443 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1444 setOperationAction(ISD::VSELECT, VT, Legal);
1445 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1446 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1447 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1450 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1451 MVT VT = (MVT::SimpleValueType)i;
1453 // Do not attempt to promote non-256-bit vectors
1454 if (!VT.is512BitVector())
1457 setOperationAction(ISD::SELECT, VT, Promote);
1458 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1462 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1463 // of this type with custom code.
1464 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1465 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1466 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1470 // We want to custom lower some of our intrinsics.
1471 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1472 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1473 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1475 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1476 // handle type legalization for these operations here.
1478 // FIXME: We really should do custom legalization for addition and
1479 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1480 // than generic legalization for 64-bit multiplication-with-overflow, though.
1481 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1482 // Add/Sub/Mul with overflow operations are custom lowered.
1484 setOperationAction(ISD::SADDO, VT, Custom);
1485 setOperationAction(ISD::UADDO, VT, Custom);
1486 setOperationAction(ISD::SSUBO, VT, Custom);
1487 setOperationAction(ISD::USUBO, VT, Custom);
1488 setOperationAction(ISD::SMULO, VT, Custom);
1489 setOperationAction(ISD::UMULO, VT, Custom);
1492 // There are no 8-bit 3-address imul/mul instructions
1493 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1494 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1496 if (!Subtarget->is64Bit()) {
1497 // These libcalls are not available in 32-bit.
1498 setLibcallName(RTLIB::SHL_I128, 0);
1499 setLibcallName(RTLIB::SRL_I128, 0);
1500 setLibcallName(RTLIB::SRA_I128, 0);
1503 // Combine sin / cos into one node or libcall if possible.
1504 if (Subtarget->hasSinCos()) {
1505 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1506 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1507 if (Subtarget->isTargetDarwin()) {
1508 // For MacOSX, we don't want to the normal expansion of a libcall to
1509 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
1511 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1512 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1516 // We have target-specific dag combine patterns for the following nodes:
1517 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1518 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1519 setTargetDAGCombine(ISD::VSELECT);
1520 setTargetDAGCombine(ISD::SELECT);
1521 setTargetDAGCombine(ISD::SHL);
1522 setTargetDAGCombine(ISD::SRA);
1523 setTargetDAGCombine(ISD::SRL);
1524 setTargetDAGCombine(ISD::OR);
1525 setTargetDAGCombine(ISD::AND);
1526 setTargetDAGCombine(ISD::ADD);
1527 setTargetDAGCombine(ISD::FADD);
1528 setTargetDAGCombine(ISD::FSUB);
1529 setTargetDAGCombine(ISD::FMA);
1530 setTargetDAGCombine(ISD::SUB);
1531 setTargetDAGCombine(ISD::LOAD);
1532 setTargetDAGCombine(ISD::STORE);
1533 setTargetDAGCombine(ISD::ZERO_EXTEND);
1534 setTargetDAGCombine(ISD::ANY_EXTEND);
1535 setTargetDAGCombine(ISD::SIGN_EXTEND);
1536 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1537 setTargetDAGCombine(ISD::TRUNCATE);
1538 setTargetDAGCombine(ISD::SINT_TO_FP);
1539 setTargetDAGCombine(ISD::SETCC);
1540 if (Subtarget->is64Bit())
1541 setTargetDAGCombine(ISD::MUL);
1542 setTargetDAGCombine(ISD::XOR);
1544 computeRegisterProperties();
1546 // On Darwin, -Os means optimize for size without hurting performance,
1547 // do not reduce the limit.
1548 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1549 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1550 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1551 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1552 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1553 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1554 setPrefLoopAlignment(4); // 2^4 bytes.
1556 // Predictable cmov don't hurt on atom because it's in-order.
1557 PredictableSelectIsExpensive = !Subtarget->isAtom();
1559 setPrefFunctionAlignment(4); // 2^4 bytes.
1562 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1564 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1566 if (Subtarget->hasAVX512())
1567 switch(VT.getVectorNumElements()) {
1568 case 8: return MVT::v8i1;
1569 case 16: return MVT::v16i1;
1572 return VT.changeVectorElementTypeToInteger();
1575 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1576 /// the desired ByVal argument alignment.
1577 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1580 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1581 if (VTy->getBitWidth() == 128)
1583 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1584 unsigned EltAlign = 0;
1585 getMaxByValAlign(ATy->getElementType(), EltAlign);
1586 if (EltAlign > MaxAlign)
1587 MaxAlign = EltAlign;
1588 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1589 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1590 unsigned EltAlign = 0;
1591 getMaxByValAlign(STy->getElementType(i), EltAlign);
1592 if (EltAlign > MaxAlign)
1593 MaxAlign = EltAlign;
1600 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1601 /// function arguments in the caller parameter area. For X86, aggregates
1602 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1603 /// are at 4-byte boundaries.
1604 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1605 if (Subtarget->is64Bit()) {
1606 // Max of 8 and alignment of type.
1607 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1614 if (Subtarget->hasSSE1())
1615 getMaxByValAlign(Ty, Align);
1619 /// getOptimalMemOpType - Returns the target specific optimal type for load
1620 /// and store operations as a result of memset, memcpy, and memmove
1621 /// lowering. If DstAlign is zero that means it's safe to destination
1622 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1623 /// means there isn't a need to check it against alignment requirement,
1624 /// probably because the source does not need to be loaded. If 'IsMemset' is
1625 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1626 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1627 /// source is constant so it does not need to be loaded.
1628 /// It returns EVT::Other if the type should be determined using generic
1629 /// target-independent logic.
1631 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1632 unsigned DstAlign, unsigned SrcAlign,
1633 bool IsMemset, bool ZeroMemset,
1635 MachineFunction &MF) const {
1636 const Function *F = MF.getFunction();
1637 if ((!IsMemset || ZeroMemset) &&
1638 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1639 Attribute::NoImplicitFloat)) {
1641 (Subtarget->isUnalignedMemAccessFast() ||
1642 ((DstAlign == 0 || DstAlign >= 16) &&
1643 (SrcAlign == 0 || SrcAlign >= 16)))) {
1645 if (Subtarget->hasInt256())
1647 if (Subtarget->hasFp256())
1650 if (Subtarget->hasSSE2())
1652 if (Subtarget->hasSSE1())
1654 } else if (!MemcpyStrSrc && Size >= 8 &&
1655 !Subtarget->is64Bit() &&
1656 Subtarget->hasSSE2()) {
1657 // Do not use f64 to lower memcpy if source is string constant. It's
1658 // better to use i32 to avoid the loads.
1662 if (Subtarget->is64Bit() && Size >= 8)
1667 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1669 return X86ScalarSSEf32;
1670 else if (VT == MVT::f64)
1671 return X86ScalarSSEf64;
1676 X86TargetLowering::allowsUnalignedMemoryAccesses(EVT VT,
1680 *Fast = Subtarget->isUnalignedMemAccessFast();
1684 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1685 /// current function. The returned value is a member of the
1686 /// MachineJumpTableInfo::JTEntryKind enum.
1687 unsigned X86TargetLowering::getJumpTableEncoding() const {
1688 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1690 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1691 Subtarget->isPICStyleGOT())
1692 return MachineJumpTableInfo::EK_Custom32;
1694 // Otherwise, use the normal jump table encoding heuristics.
1695 return TargetLowering::getJumpTableEncoding();
1699 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1700 const MachineBasicBlock *MBB,
1701 unsigned uid,MCContext &Ctx) const{
1702 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1703 Subtarget->isPICStyleGOT());
1704 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1706 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1707 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1710 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1712 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1713 SelectionDAG &DAG) const {
1714 if (!Subtarget->is64Bit())
1715 // This doesn't have SDLoc associated with it, but is not really the
1716 // same as a Register.
1717 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1721 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1722 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1724 const MCExpr *X86TargetLowering::
1725 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1726 MCContext &Ctx) const {
1727 // X86-64 uses RIP relative addressing based on the jump table label.
1728 if (Subtarget->isPICStyleRIPRel())
1729 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1731 // Otherwise, the reference is relative to the PIC base.
1732 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1735 // FIXME: Why this routine is here? Move to RegInfo!
1736 std::pair<const TargetRegisterClass*, uint8_t>
1737 X86TargetLowering::findRepresentativeClass(MVT VT) const{
1738 const TargetRegisterClass *RRC = 0;
1740 switch (VT.SimpleTy) {
1742 return TargetLowering::findRepresentativeClass(VT);
1743 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1744 RRC = Subtarget->is64Bit() ?
1745 (const TargetRegisterClass*)&X86::GR64RegClass :
1746 (const TargetRegisterClass*)&X86::GR32RegClass;
1749 RRC = &X86::VR64RegClass;
1751 case MVT::f32: case MVT::f64:
1752 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1753 case MVT::v4f32: case MVT::v2f64:
1754 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1756 RRC = &X86::VR128RegClass;
1759 return std::make_pair(RRC, Cost);
1762 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1763 unsigned &Offset) const {
1764 if (!Subtarget->isTargetLinux())
1767 if (Subtarget->is64Bit()) {
1768 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1770 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1782 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1783 unsigned DestAS) const {
1784 assert(SrcAS != DestAS && "Expected different address spaces!");
1786 return SrcAS < 256 && DestAS < 256;
1789 //===----------------------------------------------------------------------===//
1790 // Return Value Calling Convention Implementation
1791 //===----------------------------------------------------------------------===//
1793 #include "X86GenCallingConv.inc"
1796 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1797 MachineFunction &MF, bool isVarArg,
1798 const SmallVectorImpl<ISD::OutputArg> &Outs,
1799 LLVMContext &Context) const {
1800 SmallVector<CCValAssign, 16> RVLocs;
1801 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1803 return CCInfo.CheckReturn(Outs, RetCC_X86);
1806 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
1807 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
1812 X86TargetLowering::LowerReturn(SDValue Chain,
1813 CallingConv::ID CallConv, bool isVarArg,
1814 const SmallVectorImpl<ISD::OutputArg> &Outs,
1815 const SmallVectorImpl<SDValue> &OutVals,
1816 SDLoc dl, SelectionDAG &DAG) const {
1817 MachineFunction &MF = DAG.getMachineFunction();
1818 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1820 SmallVector<CCValAssign, 16> RVLocs;
1821 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1822 RVLocs, *DAG.getContext());
1823 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1826 SmallVector<SDValue, 6> RetOps;
1827 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1828 // Operand #1 = Bytes To Pop
1829 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1832 // Copy the result values into the output registers.
1833 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1834 CCValAssign &VA = RVLocs[i];
1835 assert(VA.isRegLoc() && "Can only return in registers!");
1836 SDValue ValToCopy = OutVals[i];
1837 EVT ValVT = ValToCopy.getValueType();
1839 // Promote values to the appropriate types
1840 if (VA.getLocInfo() == CCValAssign::SExt)
1841 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
1842 else if (VA.getLocInfo() == CCValAssign::ZExt)
1843 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
1844 else if (VA.getLocInfo() == CCValAssign::AExt)
1845 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
1846 else if (VA.getLocInfo() == CCValAssign::BCvt)
1847 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
1849 assert(VA.getLocInfo() != CCValAssign::FPExt &&
1850 "Unexpected FP-extend for return value.");
1852 // If this is x86-64, and we disabled SSE, we can't return FP values,
1853 // or SSE or MMX vectors.
1854 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1855 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1856 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
1857 report_fatal_error("SSE register return with SSE disabled");
1859 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1860 // llvm-gcc has never done it right and no one has noticed, so this
1861 // should be OK for now.
1862 if (ValVT == MVT::f64 &&
1863 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
1864 report_fatal_error("SSE2 register return with SSE2 disabled");
1866 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1867 // the RET instruction and handled by the FP Stackifier.
1868 if (VA.getLocReg() == X86::ST0 ||
1869 VA.getLocReg() == X86::ST1) {
1870 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1871 // change the value to the FP stack register class.
1872 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1873 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1874 RetOps.push_back(ValToCopy);
1875 // Don't emit a copytoreg.
1879 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1880 // which is returned in RAX / RDX.
1881 if (Subtarget->is64Bit()) {
1882 if (ValVT == MVT::x86mmx) {
1883 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1884 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1885 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1887 // If we don't have SSE2 available, convert to v4f32 so the generated
1888 // register is legal.
1889 if (!Subtarget->hasSSE2())
1890 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1895 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1896 Flag = Chain.getValue(1);
1897 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
1900 // The x86-64 ABIs require that for returning structs by value we copy
1901 // the sret argument into %rax/%eax (depending on ABI) for the return.
1902 // Win32 requires us to put the sret argument to %eax as well.
1903 // We saved the argument into a virtual register in the entry block,
1904 // so now we copy the value out and into %rax/%eax.
1905 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr() &&
1906 (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC())) {
1907 MachineFunction &MF = DAG.getMachineFunction();
1908 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1909 unsigned Reg = FuncInfo->getSRetReturnReg();
1911 "SRetReturnReg should have been set in LowerFormalArguments().");
1912 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1915 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
1916 X86::RAX : X86::EAX;
1917 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
1918 Flag = Chain.getValue(1);
1920 // RAX/EAX now acts like a return value.
1921 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
1924 RetOps[0] = Chain; // Update chain.
1926 // Add the flag if we have it.
1928 RetOps.push_back(Flag);
1930 return DAG.getNode(X86ISD::RET_FLAG, dl,
1931 MVT::Other, &RetOps[0], RetOps.size());
1934 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
1935 if (N->getNumValues() != 1)
1937 if (!N->hasNUsesOfValue(1, 0))
1940 SDValue TCChain = Chain;
1941 SDNode *Copy = *N->use_begin();
1942 if (Copy->getOpcode() == ISD::CopyToReg) {
1943 // If the copy has a glue operand, we conservatively assume it isn't safe to
1944 // perform a tail call.
1945 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
1947 TCChain = Copy->getOperand(0);
1948 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
1951 bool HasRet = false;
1952 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1954 if (UI->getOpcode() != X86ISD::RET_FLAG)
1967 X86TargetLowering::getTypeForExtArgOrReturn(MVT VT,
1968 ISD::NodeType ExtendKind) const {
1970 // TODO: Is this also valid on 32-bit?
1971 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
1972 ReturnMVT = MVT::i8;
1974 ReturnMVT = MVT::i32;
1976 MVT MinVT = getRegisterType(ReturnMVT);
1977 return VT.bitsLT(MinVT) ? MinVT : VT;
1980 /// LowerCallResult - Lower the result values of a call into the
1981 /// appropriate copies out of appropriate physical registers.
1984 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1985 CallingConv::ID CallConv, bool isVarArg,
1986 const SmallVectorImpl<ISD::InputArg> &Ins,
1987 SDLoc dl, SelectionDAG &DAG,
1988 SmallVectorImpl<SDValue> &InVals) const {
1990 // Assign locations to each value returned by this call.
1991 SmallVector<CCValAssign, 16> RVLocs;
1992 bool Is64Bit = Subtarget->is64Bit();
1993 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1994 getTargetMachine(), RVLocs, *DAG.getContext());
1995 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1997 // Copy all of the result registers out of their specified physreg.
1998 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
1999 CCValAssign &VA = RVLocs[i];
2000 EVT CopyVT = VA.getValVT();
2002 // If this is x86-64, and we disabled SSE, we can't return FP values
2003 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2004 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2005 report_fatal_error("SSE register return with SSE disabled");
2010 // If this is a call to a function that returns an fp value on the floating
2011 // point stack, we must guarantee the value is popped from the stack, so
2012 // a CopyFromReg is not good enough - the copy instruction may be eliminated
2013 // if the return value is not used. We use the FpPOP_RETVAL instruction
2015 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {
2016 // If we prefer to use the value in xmm registers, copy it out as f80 and
2017 // use a truncate to move it from fp stack reg to xmm reg.
2018 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
2019 SDValue Ops[] = { Chain, InFlag };
2020 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT,
2021 MVT::Other, MVT::Glue, Ops), 1);
2022 Val = Chain.getValue(0);
2024 // Round the f80 to the right size, which also moves it to the appropriate
2026 if (CopyVT != VA.getValVT())
2027 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2028 // This truncation won't change the value.
2029 DAG.getIntPtrConstant(1));
2031 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2032 CopyVT, InFlag).getValue(1);
2033 Val = Chain.getValue(0);
2035 InFlag = Chain.getValue(2);
2036 InVals.push_back(Val);
2042 //===----------------------------------------------------------------------===//
2043 // C & StdCall & Fast Calling Convention implementation
2044 //===----------------------------------------------------------------------===//
2045 // StdCall calling convention seems to be standard for many Windows' API
2046 // routines and around. It differs from C calling convention just a little:
2047 // callee should clean up the stack, not caller. Symbols should be also
2048 // decorated in some fancy way :) It doesn't support any vector arguments.
2049 // For info on fast calling convention see Fast Calling Convention (tail call)
2050 // implementation LowerX86_32FastCCCallTo.
2052 /// CallIsStructReturn - Determines whether a call uses struct return
2054 enum StructReturnType {
2059 static StructReturnType
2060 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2062 return NotStructReturn;
2064 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2065 if (!Flags.isSRet())
2066 return NotStructReturn;
2067 if (Flags.isInReg())
2068 return RegStructReturn;
2069 return StackStructReturn;
2072 /// ArgsAreStructReturn - Determines whether a function uses struct
2073 /// return semantics.
2074 static StructReturnType
2075 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2077 return NotStructReturn;
2079 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2080 if (!Flags.isSRet())
2081 return NotStructReturn;
2082 if (Flags.isInReg())
2083 return RegStructReturn;
2084 return StackStructReturn;
2087 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2088 /// by "Src" to address "Dst" with size and alignment information specified by
2089 /// the specific parameter attribute. The copy will be passed as a byval
2090 /// function parameter.
2092 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2093 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2095 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2097 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2098 /*isVolatile*/false, /*AlwaysInline=*/true,
2099 MachinePointerInfo(), MachinePointerInfo());
2102 /// IsTailCallConvention - Return true if the calling convention is one that
2103 /// supports tail call optimization.
2104 static bool IsTailCallConvention(CallingConv::ID CC) {
2105 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2106 CC == CallingConv::HiPE);
2109 /// \brief Return true if the calling convention is a C calling convention.
2110 static bool IsCCallConvention(CallingConv::ID CC) {
2111 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2112 CC == CallingConv::X86_64_SysV);
2115 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2116 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2120 CallingConv::ID CalleeCC = CS.getCallingConv();
2121 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2127 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
2128 /// a tailcall target by changing its ABI.
2129 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2130 bool GuaranteedTailCallOpt) {
2131 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2135 X86TargetLowering::LowerMemArgument(SDValue Chain,
2136 CallingConv::ID CallConv,
2137 const SmallVectorImpl<ISD::InputArg> &Ins,
2138 SDLoc dl, SelectionDAG &DAG,
2139 const CCValAssign &VA,
2140 MachineFrameInfo *MFI,
2142 // Create the nodes corresponding to a load from this parameter slot.
2143 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2144 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv,
2145 getTargetMachine().Options.GuaranteedTailCallOpt);
2146 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2149 // If value is passed by pointer we have address passed instead of the value
2151 if (VA.getLocInfo() == CCValAssign::Indirect)
2152 ValVT = VA.getLocVT();
2154 ValVT = VA.getValVT();
2156 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2157 // changed with more analysis.
2158 // In case of tail call optimization mark all arguments mutable. Since they
2159 // could be overwritten by lowering of arguments in case of a tail call.
2160 if (Flags.isByVal()) {
2161 unsigned Bytes = Flags.getByValSize();
2162 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2163 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2164 return DAG.getFrameIndex(FI, getPointerTy());
2166 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2167 VA.getLocMemOffset(), isImmutable);
2168 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2169 return DAG.getLoad(ValVT, dl, Chain, FIN,
2170 MachinePointerInfo::getFixedStack(FI),
2171 false, false, false, 0);
2176 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2177 CallingConv::ID CallConv,
2179 const SmallVectorImpl<ISD::InputArg> &Ins,
2182 SmallVectorImpl<SDValue> &InVals)
2184 MachineFunction &MF = DAG.getMachineFunction();
2185 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2187 const Function* Fn = MF.getFunction();
2188 if (Fn->hasExternalLinkage() &&
2189 Subtarget->isTargetCygMing() &&
2190 Fn->getName() == "main")
2191 FuncInfo->setForceFramePointer(true);
2193 MachineFrameInfo *MFI = MF.getFrameInfo();
2194 bool Is64Bit = Subtarget->is64Bit();
2195 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2197 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2198 "Var args not supported with calling convention fastcc, ghc or hipe");
2200 // Assign locations to all of the incoming arguments.
2201 SmallVector<CCValAssign, 16> ArgLocs;
2202 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
2203 ArgLocs, *DAG.getContext());
2205 // Allocate shadow area for Win64
2207 CCInfo.AllocateStack(32, 8);
2209 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2211 unsigned LastVal = ~0U;
2213 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2214 CCValAssign &VA = ArgLocs[i];
2215 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2217 assert(VA.getValNo() != LastVal &&
2218 "Don't support value assigned to multiple locs yet");
2220 LastVal = VA.getValNo();
2222 if (VA.isRegLoc()) {
2223 EVT RegVT = VA.getLocVT();
2224 const TargetRegisterClass *RC;
2225 if (RegVT == MVT::i32)
2226 RC = &X86::GR32RegClass;
2227 else if (Is64Bit && RegVT == MVT::i64)
2228 RC = &X86::GR64RegClass;
2229 else if (RegVT == MVT::f32)
2230 RC = &X86::FR32RegClass;
2231 else if (RegVT == MVT::f64)
2232 RC = &X86::FR64RegClass;
2233 else if (RegVT.is512BitVector())
2234 RC = &X86::VR512RegClass;
2235 else if (RegVT.is256BitVector())
2236 RC = &X86::VR256RegClass;
2237 else if (RegVT.is128BitVector())
2238 RC = &X86::VR128RegClass;
2239 else if (RegVT == MVT::x86mmx)
2240 RC = &X86::VR64RegClass;
2241 else if (RegVT == MVT::i1)
2242 RC = &X86::VK1RegClass;
2243 else if (RegVT == MVT::v8i1)
2244 RC = &X86::VK8RegClass;
2245 else if (RegVT == MVT::v16i1)
2246 RC = &X86::VK16RegClass;
2248 llvm_unreachable("Unknown argument type!");
2250 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2251 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2253 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2254 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2256 if (VA.getLocInfo() == CCValAssign::SExt)
2257 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2258 DAG.getValueType(VA.getValVT()));
2259 else if (VA.getLocInfo() == CCValAssign::ZExt)
2260 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2261 DAG.getValueType(VA.getValVT()));
2262 else if (VA.getLocInfo() == CCValAssign::BCvt)
2263 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2265 if (VA.isExtInLoc()) {
2266 // Handle MMX values passed in XMM regs.
2267 if (RegVT.isVector())
2268 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2270 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2273 assert(VA.isMemLoc());
2274 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2277 // If value is passed via pointer - do a load.
2278 if (VA.getLocInfo() == CCValAssign::Indirect)
2279 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2280 MachinePointerInfo(), false, false, false, 0);
2282 InVals.push_back(ArgValue);
2285 // The x86-64 ABIs require that for returning structs by value we copy
2286 // the sret argument into %rax/%eax (depending on ABI) for the return.
2287 // Win32 requires us to put the sret argument to %eax as well.
2288 // Save the argument into a virtual register so that we can access it
2289 // from the return points.
2290 if (MF.getFunction()->hasStructRetAttr() &&
2291 (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC())) {
2292 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2293 unsigned Reg = FuncInfo->getSRetReturnReg();
2295 MVT PtrTy = getPointerTy();
2296 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2297 FuncInfo->setSRetReturnReg(Reg);
2299 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
2300 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2303 unsigned StackSize = CCInfo.getNextStackOffset();
2304 // Align stack specially for tail calls.
2305 if (FuncIsMadeTailCallSafe(CallConv,
2306 MF.getTarget().Options.GuaranteedTailCallOpt))
2307 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2309 // If the function takes variable number of arguments, make a frame index for
2310 // the start of the first vararg value... for expansion of llvm.va_start.
2312 if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2313 CallConv != CallingConv::X86_ThisCall)) {
2314 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
2317 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
2319 // FIXME: We should really autogenerate these arrays
2320 static const MCPhysReg GPR64ArgRegsWin64[] = {
2321 X86::RCX, X86::RDX, X86::R8, X86::R9
2323 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2324 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2326 static const MCPhysReg XMMArgRegs64Bit[] = {
2327 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2328 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2330 const MCPhysReg *GPR64ArgRegs;
2331 unsigned NumXMMRegs = 0;
2334 // The XMM registers which might contain var arg parameters are shadowed
2335 // in their paired GPR. So we only need to save the GPR to their home
2337 TotalNumIntRegs = 4;
2338 GPR64ArgRegs = GPR64ArgRegsWin64;
2340 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
2341 GPR64ArgRegs = GPR64ArgRegs64Bit;
2343 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit,
2346 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
2349 bool NoImplicitFloatOps = Fn->getAttributes().
2350 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2351 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2352 "SSE register cannot be used when SSE is disabled!");
2353 assert(!(NumXMMRegs && MF.getTarget().Options.UseSoftFloat &&
2354 NoImplicitFloatOps) &&
2355 "SSE register cannot be used when SSE is disabled!");
2356 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2357 !Subtarget->hasSSE1())
2358 // Kernel mode asks for SSE to be disabled, so don't push them
2360 TotalNumXMMRegs = 0;
2363 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering();
2364 // Get to the caller-allocated home save location. Add 8 to account
2365 // for the return address.
2366 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2367 FuncInfo->setRegSaveFrameIndex(
2368 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2369 // Fixup to set vararg frame on shadow area (4 x i64).
2371 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2373 // For X86-64, if there are vararg parameters that are passed via
2374 // registers, then we must store them to their spots on the stack so
2375 // they may be loaded by deferencing the result of va_next.
2376 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2377 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
2378 FuncInfo->setRegSaveFrameIndex(
2379 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
2383 // Store the integer parameter registers.
2384 SmallVector<SDValue, 8> MemOps;
2385 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2387 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2388 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
2389 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2390 DAG.getIntPtrConstant(Offset));
2391 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
2392 &X86::GR64RegClass);
2393 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2395 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2396 MachinePointerInfo::getFixedStack(
2397 FuncInfo->getRegSaveFrameIndex(), Offset),
2399 MemOps.push_back(Store);
2403 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
2404 // Now store the XMM (fp + vector) parameter registers.
2405 SmallVector<SDValue, 11> SaveXMMOps;
2406 SaveXMMOps.push_back(Chain);
2408 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2409 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
2410 SaveXMMOps.push_back(ALVal);
2412 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2413 FuncInfo->getRegSaveFrameIndex()));
2414 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2415 FuncInfo->getVarArgsFPOffset()));
2417 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
2418 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs],
2419 &X86::VR128RegClass);
2420 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
2421 SaveXMMOps.push_back(Val);
2423 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2425 &SaveXMMOps[0], SaveXMMOps.size()));
2428 if (!MemOps.empty())
2429 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2430 &MemOps[0], MemOps.size());
2434 // Some CCs need callee pop.
2435 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2436 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2437 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2439 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2440 // If this is an sret function, the return should pop the hidden pointer.
2441 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2442 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2443 argsAreStructReturn(Ins) == StackStructReturn)
2444 FuncInfo->setBytesToPopOnReturn(4);
2448 // RegSaveFrameIndex is X86-64 only.
2449 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2450 if (CallConv == CallingConv::X86_FastCall ||
2451 CallConv == CallingConv::X86_ThisCall)
2452 // fastcc functions can't have varargs.
2453 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2456 FuncInfo->setArgumentStackSize(StackSize);
2462 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2463 SDValue StackPtr, SDValue Arg,
2464 SDLoc dl, SelectionDAG &DAG,
2465 const CCValAssign &VA,
2466 ISD::ArgFlagsTy Flags) const {
2467 unsigned LocMemOffset = VA.getLocMemOffset();
2468 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2469 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2470 if (Flags.isByVal())
2471 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2473 return DAG.getStore(Chain, dl, Arg, PtrOff,
2474 MachinePointerInfo::getStack(LocMemOffset),
2478 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2479 /// optimization is performed and it is required.
2481 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2482 SDValue &OutRetAddr, SDValue Chain,
2483 bool IsTailCall, bool Is64Bit,
2484 int FPDiff, SDLoc dl) const {
2485 // Adjust the Return address stack slot.
2486 EVT VT = getPointerTy();
2487 OutRetAddr = getReturnAddressFrameIndex(DAG);
2489 // Load the "old" Return address.
2490 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2491 false, false, false, 0);
2492 return SDValue(OutRetAddr.getNode(), 1);
2495 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2496 /// optimization is performed and it is required (FPDiff!=0).
2498 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
2499 SDValue Chain, SDValue RetAddrFrIdx, EVT PtrVT,
2500 unsigned SlotSize, int FPDiff, SDLoc dl) {
2501 // Store the return address to the appropriate stack slot.
2502 if (!FPDiff) return Chain;
2503 // Calculate the new stack slot for the return address.
2504 int NewReturnAddrFI =
2505 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2507 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2508 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2509 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2515 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2516 SmallVectorImpl<SDValue> &InVals) const {
2517 SelectionDAG &DAG = CLI.DAG;
2519 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2520 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2521 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2522 SDValue Chain = CLI.Chain;
2523 SDValue Callee = CLI.Callee;
2524 CallingConv::ID CallConv = CLI.CallConv;
2525 bool &isTailCall = CLI.IsTailCall;
2526 bool isVarArg = CLI.IsVarArg;
2528 MachineFunction &MF = DAG.getMachineFunction();
2529 bool Is64Bit = Subtarget->is64Bit();
2530 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2531 StructReturnType SR = callIsStructReturn(Outs);
2532 bool IsSibcall = false;
2534 if (MF.getTarget().Options.DisableTailCalls)
2538 // Check if it's really possible to do a tail call.
2539 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2540 isVarArg, SR != NotStructReturn,
2541 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2542 Outs, OutVals, Ins, DAG);
2544 // Sibcalls are automatically detected tailcalls which do not require
2546 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2553 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2554 "Var args not supported with calling convention fastcc, ghc or hipe");
2556 // Analyze operands of the call, assigning locations to each operand.
2557 SmallVector<CCValAssign, 16> ArgLocs;
2558 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
2559 ArgLocs, *DAG.getContext());
2561 // Allocate shadow area for Win64
2563 CCInfo.AllocateStack(32, 8);
2565 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2567 // Get a count of how many bytes are to be pushed on the stack.
2568 unsigned NumBytes = CCInfo.getNextStackOffset();
2570 // This is a sibcall. The memory operands are available in caller's
2571 // own caller's stack.
2573 else if (getTargetMachine().Options.GuaranteedTailCallOpt &&
2574 IsTailCallConvention(CallConv))
2575 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2578 if (isTailCall && !IsSibcall) {
2579 // Lower arguments at fp - stackoffset + fpdiff.
2580 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2581 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2583 FPDiff = NumBytesCallerPushed - NumBytes;
2585 // Set the delta of movement of the returnaddr stackslot.
2586 // But only set if delta is greater than previous delta.
2587 if (FPDiff < X86Info->getTCReturnAddrDelta())
2588 X86Info->setTCReturnAddrDelta(FPDiff);
2591 unsigned NumBytesToPush = NumBytes;
2592 unsigned NumBytesToPop = NumBytes;
2594 // If we have an inalloca argument, all stack space has already been allocated
2595 // for us and be right at the top of the stack. We don't support multiple
2596 // arguments passed in memory when using inalloca.
2597 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
2599 assert(ArgLocs.back().getLocMemOffset() == 0 &&
2600 "an inalloca argument must be the only memory argument");
2604 Chain = DAG.getCALLSEQ_START(
2605 Chain, DAG.getIntPtrConstant(NumBytesToPush, true), dl);
2607 SDValue RetAddrFrIdx;
2608 // Load return address for tail calls.
2609 if (isTailCall && FPDiff)
2610 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2611 Is64Bit, FPDiff, dl);
2613 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2614 SmallVector<SDValue, 8> MemOpChains;
2617 // Walk the register/memloc assignments, inserting copies/loads. In the case
2618 // of tail call optimization arguments are handle later.
2619 const X86RegisterInfo *RegInfo =
2620 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
2621 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2622 // Skip inalloca arguments, they have already been written.
2623 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2624 if (Flags.isInAlloca())
2627 CCValAssign &VA = ArgLocs[i];
2628 EVT RegVT = VA.getLocVT();
2629 SDValue Arg = OutVals[i];
2630 bool isByVal = Flags.isByVal();
2632 // Promote the value if needed.
2633 switch (VA.getLocInfo()) {
2634 default: llvm_unreachable("Unknown loc info!");
2635 case CCValAssign::Full: break;
2636 case CCValAssign::SExt:
2637 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2639 case CCValAssign::ZExt:
2640 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2642 case CCValAssign::AExt:
2643 if (RegVT.is128BitVector()) {
2644 // Special case: passing MMX values in XMM registers.
2645 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2646 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2647 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2649 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2651 case CCValAssign::BCvt:
2652 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2654 case CCValAssign::Indirect: {
2655 // Store the argument.
2656 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2657 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2658 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2659 MachinePointerInfo::getFixedStack(FI),
2666 if (VA.isRegLoc()) {
2667 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2668 if (isVarArg && IsWin64) {
2669 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2670 // shadow reg if callee is a varargs function.
2671 unsigned ShadowReg = 0;
2672 switch (VA.getLocReg()) {
2673 case X86::XMM0: ShadowReg = X86::RCX; break;
2674 case X86::XMM1: ShadowReg = X86::RDX; break;
2675 case X86::XMM2: ShadowReg = X86::R8; break;
2676 case X86::XMM3: ShadowReg = X86::R9; break;
2679 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2681 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2682 assert(VA.isMemLoc());
2683 if (StackPtr.getNode() == 0)
2684 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2686 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2687 dl, DAG, VA, Flags));
2691 if (!MemOpChains.empty())
2692 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2693 &MemOpChains[0], MemOpChains.size());
2695 if (Subtarget->isPICStyleGOT()) {
2696 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2699 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2700 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2702 // If we are tail calling and generating PIC/GOT style code load the
2703 // address of the callee into ECX. The value in ecx is used as target of
2704 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2705 // for tail calls on PIC/GOT architectures. Normally we would just put the
2706 // address of GOT into ebx and then call target@PLT. But for tail calls
2707 // ebx would be restored (since ebx is callee saved) before jumping to the
2710 // Note: The actual moving to ECX is done further down.
2711 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2712 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2713 !G->getGlobal()->hasProtectedVisibility())
2714 Callee = LowerGlobalAddress(Callee, DAG);
2715 else if (isa<ExternalSymbolSDNode>(Callee))
2716 Callee = LowerExternalSymbol(Callee, DAG);
2720 if (Is64Bit && isVarArg && !IsWin64) {
2721 // From AMD64 ABI document:
2722 // For calls that may call functions that use varargs or stdargs
2723 // (prototype-less calls or calls to functions containing ellipsis (...) in
2724 // the declaration) %al is used as hidden argument to specify the number
2725 // of SSE registers used. The contents of %al do not need to match exactly
2726 // the number of registers, but must be an ubound on the number of SSE
2727 // registers used and is in the range 0 - 8 inclusive.
2729 // Count the number of XMM registers allocated.
2730 static const MCPhysReg XMMArgRegs[] = {
2731 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2732 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2734 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2735 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2736 && "SSE registers cannot be used when SSE is disabled");
2738 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2739 DAG.getConstant(NumXMMRegs, MVT::i8)));
2742 // For tail calls lower the arguments to the 'real' stack slot.
2744 // Force all the incoming stack arguments to be loaded from the stack
2745 // before any new outgoing arguments are stored to the stack, because the
2746 // outgoing stack slots may alias the incoming argument stack slots, and
2747 // the alias isn't otherwise explicit. This is slightly more conservative
2748 // than necessary, because it means that each store effectively depends
2749 // on every argument instead of just those arguments it would clobber.
2750 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2752 SmallVector<SDValue, 8> MemOpChains2;
2755 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2756 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2757 CCValAssign &VA = ArgLocs[i];
2760 assert(VA.isMemLoc());
2761 SDValue Arg = OutVals[i];
2762 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2763 // Create frame index.
2764 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2765 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2766 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2767 FIN = DAG.getFrameIndex(FI, getPointerTy());
2769 if (Flags.isByVal()) {
2770 // Copy relative to framepointer.
2771 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2772 if (StackPtr.getNode() == 0)
2773 StackPtr = DAG.getCopyFromReg(Chain, dl,
2774 RegInfo->getStackRegister(),
2776 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2778 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2782 // Store relative to framepointer.
2783 MemOpChains2.push_back(
2784 DAG.getStore(ArgChain, dl, Arg, FIN,
2785 MachinePointerInfo::getFixedStack(FI),
2791 if (!MemOpChains2.empty())
2792 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2793 &MemOpChains2[0], MemOpChains2.size());
2795 // Store the return address to the appropriate stack slot.
2796 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
2797 getPointerTy(), RegInfo->getSlotSize(),
2801 // Build a sequence of copy-to-reg nodes chained together with token chain
2802 // and flag operands which copy the outgoing args into registers.
2804 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2805 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2806 RegsToPass[i].second, InFlag);
2807 InFlag = Chain.getValue(1);
2810 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2811 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2812 // In the 64-bit large code model, we have to make all calls
2813 // through a register, since the call instruction's 32-bit
2814 // pc-relative offset may not be large enough to hold the whole
2816 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2817 // If the callee is a GlobalAddress node (quite common, every direct call
2818 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2821 // We should use extra load for direct calls to dllimported functions in
2823 const GlobalValue *GV = G->getGlobal();
2824 if (!GV->hasDLLImportStorageClass()) {
2825 unsigned char OpFlags = 0;
2826 bool ExtraLoad = false;
2827 unsigned WrapperKind = ISD::DELETED_NODE;
2829 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2830 // external symbols most go through the PLT in PIC mode. If the symbol
2831 // has hidden or protected visibility, or if it is static or local, then
2832 // we don't need to use the PLT - we can directly call it.
2833 if (Subtarget->isTargetELF() &&
2834 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2835 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2836 OpFlags = X86II::MO_PLT;
2837 } else if (Subtarget->isPICStyleStubAny() &&
2838 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2839 (!Subtarget->getTargetTriple().isMacOSX() ||
2840 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2841 // PC-relative references to external symbols should go through $stub,
2842 // unless we're building with the leopard linker or later, which
2843 // automatically synthesizes these stubs.
2844 OpFlags = X86II::MO_DARWIN_STUB;
2845 } else if (Subtarget->isPICStyleRIPRel() &&
2846 isa<Function>(GV) &&
2847 cast<Function>(GV)->getAttributes().
2848 hasAttribute(AttributeSet::FunctionIndex,
2849 Attribute::NonLazyBind)) {
2850 // If the function is marked as non-lazy, generate an indirect call
2851 // which loads from the GOT directly. This avoids runtime overhead
2852 // at the cost of eager binding (and one extra byte of encoding).
2853 OpFlags = X86II::MO_GOTPCREL;
2854 WrapperKind = X86ISD::WrapperRIP;
2858 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2859 G->getOffset(), OpFlags);
2861 // Add a wrapper if needed.
2862 if (WrapperKind != ISD::DELETED_NODE)
2863 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
2864 // Add extra indirection if needed.
2866 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
2867 MachinePointerInfo::getGOT(),
2868 false, false, false, 0);
2870 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2871 unsigned char OpFlags = 0;
2873 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
2874 // external symbols should go through the PLT.
2875 if (Subtarget->isTargetELF() &&
2876 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2877 OpFlags = X86II::MO_PLT;
2878 } else if (Subtarget->isPICStyleStubAny() &&
2879 (!Subtarget->getTargetTriple().isMacOSX() ||
2880 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2881 // PC-relative references to external symbols should go through $stub,
2882 // unless we're building with the leopard linker or later, which
2883 // automatically synthesizes these stubs.
2884 OpFlags = X86II::MO_DARWIN_STUB;
2887 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2891 // Returns a chain & a flag for retval copy to use.
2892 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2893 SmallVector<SDValue, 8> Ops;
2895 if (!IsSibcall && isTailCall) {
2896 Chain = DAG.getCALLSEQ_END(Chain,
2897 DAG.getIntPtrConstant(NumBytesToPop, true),
2898 DAG.getIntPtrConstant(0, true), InFlag, dl);
2899 InFlag = Chain.getValue(1);
2902 Ops.push_back(Chain);
2903 Ops.push_back(Callee);
2906 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2908 // Add argument registers to the end of the list so that they are known live
2910 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2911 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2912 RegsToPass[i].second.getValueType()));
2914 // Add a register mask operand representing the call-preserved registers.
2915 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2916 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
2917 assert(Mask && "Missing call preserved mask for calling convention");
2918 Ops.push_back(DAG.getRegisterMask(Mask));
2920 if (InFlag.getNode())
2921 Ops.push_back(InFlag);
2925 //// If this is the first return lowered for this function, add the regs
2926 //// to the liveout set for the function.
2927 // This isn't right, although it's probably harmless on x86; liveouts
2928 // should be computed from returns not tail calls. Consider a void
2929 // function making a tail call to a function returning int.
2930 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size());
2933 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2934 InFlag = Chain.getValue(1);
2936 // Create the CALLSEQ_END node.
2937 unsigned NumBytesForCalleeToPop;
2938 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2939 getTargetMachine().Options.GuaranteedTailCallOpt))
2940 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
2941 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2942 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2943 SR == StackStructReturn)
2944 // If this is a call to a struct-return function, the callee
2945 // pops the hidden struct pointer, so we have to push it back.
2946 // This is common for Darwin/X86, Linux & Mingw32 targets.
2947 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
2948 NumBytesForCalleeToPop = 4;
2950 NumBytesForCalleeToPop = 0; // Callee pops nothing.
2952 // Returns a flag for retval copy to use.
2954 Chain = DAG.getCALLSEQ_END(Chain,
2955 DAG.getIntPtrConstant(NumBytesToPop, true),
2956 DAG.getIntPtrConstant(NumBytesForCalleeToPop,
2959 InFlag = Chain.getValue(1);
2962 // Handle result values, copying them out of physregs into vregs that we
2964 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2965 Ins, dl, DAG, InVals);
2968 //===----------------------------------------------------------------------===//
2969 // Fast Calling Convention (tail call) implementation
2970 //===----------------------------------------------------------------------===//
2972 // Like std call, callee cleans arguments, convention except that ECX is
2973 // reserved for storing the tail called function address. Only 2 registers are
2974 // free for argument passing (inreg). Tail call optimization is performed
2976 // * tailcallopt is enabled
2977 // * caller/callee are fastcc
2978 // On X86_64 architecture with GOT-style position independent code only local
2979 // (within module) calls are supported at the moment.
2980 // To keep the stack aligned according to platform abi the function
2981 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2982 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2983 // If a tail called function callee has more arguments than the caller the
2984 // caller needs to make sure that there is room to move the RETADDR to. This is
2985 // achieved by reserving an area the size of the argument delta right after the
2986 // original REtADDR, but before the saved framepointer or the spilled registers
2987 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2999 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
3000 /// for a 16 byte align requirement.
3002 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3003 SelectionDAG& DAG) const {
3004 MachineFunction &MF = DAG.getMachineFunction();
3005 const TargetMachine &TM = MF.getTarget();
3006 const X86RegisterInfo *RegInfo =
3007 static_cast<const X86RegisterInfo*>(TM.getRegisterInfo());
3008 const TargetFrameLowering &TFI = *TM.getFrameLowering();
3009 unsigned StackAlignment = TFI.getStackAlignment();
3010 uint64_t AlignMask = StackAlignment - 1;
3011 int64_t Offset = StackSize;
3012 unsigned SlotSize = RegInfo->getSlotSize();
3013 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3014 // Number smaller than 12 so just add the difference.
3015 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3017 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3018 Offset = ((~AlignMask) & Offset) + StackAlignment +
3019 (StackAlignment-SlotSize);
3024 /// MatchingStackOffset - Return true if the given stack call argument is
3025 /// already available in the same position (relatively) of the caller's
3026 /// incoming argument stack.
3028 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3029 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3030 const X86InstrInfo *TII) {
3031 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3033 if (Arg.getOpcode() == ISD::CopyFromReg) {
3034 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3035 if (!TargetRegisterInfo::isVirtualRegister(VR))
3037 MachineInstr *Def = MRI->getVRegDef(VR);
3040 if (!Flags.isByVal()) {
3041 if (!TII->isLoadFromStackSlot(Def, FI))
3044 unsigned Opcode = Def->getOpcode();
3045 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
3046 Def->getOperand(1).isFI()) {
3047 FI = Def->getOperand(1).getIndex();
3048 Bytes = Flags.getByValSize();
3052 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3053 if (Flags.isByVal())
3054 // ByVal argument is passed in as a pointer but it's now being
3055 // dereferenced. e.g.
3056 // define @foo(%struct.X* %A) {
3057 // tail call @bar(%struct.X* byval %A)
3060 SDValue Ptr = Ld->getBasePtr();
3061 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3064 FI = FINode->getIndex();
3065 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3066 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3067 FI = FINode->getIndex();
3068 Bytes = Flags.getByValSize();
3072 assert(FI != INT_MAX);
3073 if (!MFI->isFixedObjectIndex(FI))
3075 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3078 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3079 /// for tail call optimization. Targets which want to do tail call
3080 /// optimization should implement this function.
3082 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3083 CallingConv::ID CalleeCC,
3085 bool isCalleeStructRet,
3086 bool isCallerStructRet,
3088 const SmallVectorImpl<ISD::OutputArg> &Outs,
3089 const SmallVectorImpl<SDValue> &OutVals,
3090 const SmallVectorImpl<ISD::InputArg> &Ins,
3091 SelectionDAG &DAG) const {
3092 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3095 // If -tailcallopt is specified, make fastcc functions tail-callable.
3096 const MachineFunction &MF = DAG.getMachineFunction();
3097 const Function *CallerF = MF.getFunction();
3099 // If the function return type is x86_fp80 and the callee return type is not,
3100 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3101 // perform a tailcall optimization here.
3102 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3105 CallingConv::ID CallerCC = CallerF->getCallingConv();
3106 bool CCMatch = CallerCC == CalleeCC;
3107 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3108 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3110 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
3111 if (IsTailCallConvention(CalleeCC) && CCMatch)
3116 // Look for obvious safe cases to perform tail call optimization that do not
3117 // require ABI changes. This is what gcc calls sibcall.
3119 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3120 // emit a special epilogue.
3121 const X86RegisterInfo *RegInfo =
3122 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
3123 if (RegInfo->needsStackRealignment(MF))
3126 // Also avoid sibcall optimization if either caller or callee uses struct
3127 // return semantics.
3128 if (isCalleeStructRet || isCallerStructRet)
3131 // An stdcall/thiscall caller is expected to clean up its arguments; the
3132 // callee isn't going to do that.
3133 // FIXME: this is more restrictive than needed. We could produce a tailcall
3134 // when the stack adjustment matches. For example, with a thiscall that takes
3135 // only one argument.
3136 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3137 CallerCC == CallingConv::X86_ThisCall))
3140 // Do not sibcall optimize vararg calls unless all arguments are passed via
3142 if (isVarArg && !Outs.empty()) {
3144 // Optimizing for varargs on Win64 is unlikely to be safe without
3145 // additional testing.
3146 if (IsCalleeWin64 || IsCallerWin64)
3149 SmallVector<CCValAssign, 16> ArgLocs;
3150 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
3151 getTargetMachine(), ArgLocs, *DAG.getContext());
3153 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3154 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3155 if (!ArgLocs[i].isRegLoc())
3159 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3160 // stack. Therefore, if it's not used by the call it is not safe to optimize
3161 // this into a sibcall.
3162 bool Unused = false;
3163 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3170 SmallVector<CCValAssign, 16> RVLocs;
3171 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(),
3172 getTargetMachine(), RVLocs, *DAG.getContext());
3173 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3174 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3175 CCValAssign &VA = RVLocs[i];
3176 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
3181 // If the calling conventions do not match, then we'd better make sure the
3182 // results are returned in the same way as what the caller expects.
3184 SmallVector<CCValAssign, 16> RVLocs1;
3185 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
3186 getTargetMachine(), RVLocs1, *DAG.getContext());
3187 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3189 SmallVector<CCValAssign, 16> RVLocs2;
3190 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
3191 getTargetMachine(), RVLocs2, *DAG.getContext());
3192 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3194 if (RVLocs1.size() != RVLocs2.size())
3196 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3197 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3199 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3201 if (RVLocs1[i].isRegLoc()) {
3202 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3205 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3211 // If the callee takes no arguments then go on to check the results of the
3213 if (!Outs.empty()) {
3214 // Check if stack adjustment is needed. For now, do not do this if any
3215 // argument is passed on the stack.
3216 SmallVector<CCValAssign, 16> ArgLocs;
3217 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
3218 getTargetMachine(), ArgLocs, *DAG.getContext());
3220 // Allocate shadow area for Win64
3222 CCInfo.AllocateStack(32, 8);
3224 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3225 if (CCInfo.getNextStackOffset()) {
3226 MachineFunction &MF = DAG.getMachineFunction();
3227 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3230 // Check if the arguments are already laid out in the right way as
3231 // the caller's fixed stack objects.
3232 MachineFrameInfo *MFI = MF.getFrameInfo();
3233 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3234 const X86InstrInfo *TII =
3235 ((const X86TargetMachine&)getTargetMachine()).getInstrInfo();
3236 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3237 CCValAssign &VA = ArgLocs[i];
3238 SDValue Arg = OutVals[i];
3239 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3240 if (VA.getLocInfo() == CCValAssign::Indirect)
3242 if (!VA.isRegLoc()) {
3243 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3250 // If the tailcall address may be in a register, then make sure it's
3251 // possible to register allocate for it. In 32-bit, the call address can
3252 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3253 // callee-saved registers are restored. These happen to be the same
3254 // registers used to pass 'inreg' arguments so watch out for those.
3255 if (!Subtarget->is64Bit() &&
3256 ((!isa<GlobalAddressSDNode>(Callee) &&
3257 !isa<ExternalSymbolSDNode>(Callee)) ||
3258 getTargetMachine().getRelocationModel() == Reloc::PIC_)) {
3259 unsigned NumInRegs = 0;
3260 // In PIC we need an extra register to formulate the address computation
3262 unsigned MaxInRegs =
3263 (getTargetMachine().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3265 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3266 CCValAssign &VA = ArgLocs[i];
3269 unsigned Reg = VA.getLocReg();
3272 case X86::EAX: case X86::EDX: case X86::ECX:
3273 if (++NumInRegs == MaxInRegs)
3285 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3286 const TargetLibraryInfo *libInfo) const {
3287 return X86::createFastISel(funcInfo, libInfo);
3290 //===----------------------------------------------------------------------===//
3291 // Other Lowering Hooks
3292 //===----------------------------------------------------------------------===//
3294 static bool MayFoldLoad(SDValue Op) {
3295 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3298 static bool MayFoldIntoStore(SDValue Op) {
3299 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3302 static bool isTargetShuffle(unsigned Opcode) {
3304 default: return false;
3305 case X86ISD::PSHUFD:
3306 case X86ISD::PSHUFHW:
3307 case X86ISD::PSHUFLW:
3309 case X86ISD::PALIGNR:
3310 case X86ISD::MOVLHPS:
3311 case X86ISD::MOVLHPD:
3312 case X86ISD::MOVHLPS:
3313 case X86ISD::MOVLPS:
3314 case X86ISD::MOVLPD:
3315 case X86ISD::MOVSHDUP:
3316 case X86ISD::MOVSLDUP:
3317 case X86ISD::MOVDDUP:
3320 case X86ISD::UNPCKL:
3321 case X86ISD::UNPCKH:
3322 case X86ISD::VPERMILP:
3323 case X86ISD::VPERM2X128:
3324 case X86ISD::VPERMI:
3329 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3330 SDValue V1, SelectionDAG &DAG) {
3332 default: llvm_unreachable("Unknown x86 shuffle node");
3333 case X86ISD::MOVSHDUP:
3334 case X86ISD::MOVSLDUP:
3335 case X86ISD::MOVDDUP:
3336 return DAG.getNode(Opc, dl, VT, V1);
3340 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3341 SDValue V1, unsigned TargetMask,
3342 SelectionDAG &DAG) {
3344 default: llvm_unreachable("Unknown x86 shuffle node");
3345 case X86ISD::PSHUFD:
3346 case X86ISD::PSHUFHW:
3347 case X86ISD::PSHUFLW:
3348 case X86ISD::VPERMILP:
3349 case X86ISD::VPERMI:
3350 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3354 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3355 SDValue V1, SDValue V2, unsigned TargetMask,
3356 SelectionDAG &DAG) {
3358 default: llvm_unreachable("Unknown x86 shuffle node");
3359 case X86ISD::PALIGNR:
3361 case X86ISD::VPERM2X128:
3362 return DAG.getNode(Opc, dl, VT, V1, V2,
3363 DAG.getConstant(TargetMask, MVT::i8));
3367 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3368 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3370 default: llvm_unreachable("Unknown x86 shuffle node");
3371 case X86ISD::MOVLHPS:
3372 case X86ISD::MOVLHPD:
3373 case X86ISD::MOVHLPS:
3374 case X86ISD::MOVLPS:
3375 case X86ISD::MOVLPD:
3378 case X86ISD::UNPCKL:
3379 case X86ISD::UNPCKH:
3380 return DAG.getNode(Opc, dl, VT, V1, V2);
3384 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3385 MachineFunction &MF = DAG.getMachineFunction();
3386 const X86RegisterInfo *RegInfo =
3387 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
3388 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3389 int ReturnAddrIndex = FuncInfo->getRAIndex();
3391 if (ReturnAddrIndex == 0) {
3392 // Set up a frame object for the return address.
3393 unsigned SlotSize = RegInfo->getSlotSize();
3394 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3397 FuncInfo->setRAIndex(ReturnAddrIndex);
3400 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3403 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3404 bool hasSymbolicDisplacement) {
3405 // Offset should fit into 32 bit immediate field.
3406 if (!isInt<32>(Offset))
3409 // If we don't have a symbolic displacement - we don't have any extra
3411 if (!hasSymbolicDisplacement)
3414 // FIXME: Some tweaks might be needed for medium code model.
3415 if (M != CodeModel::Small && M != CodeModel::Kernel)
3418 // For small code model we assume that latest object is 16MB before end of 31
3419 // bits boundary. We may also accept pretty large negative constants knowing
3420 // that all objects are in the positive half of address space.
3421 if (M == CodeModel::Small && Offset < 16*1024*1024)
3424 // For kernel code model we know that all object resist in the negative half
3425 // of 32bits address space. We may not accept negative offsets, since they may
3426 // be just off and we may accept pretty large positive ones.
3427 if (M == CodeModel::Kernel && Offset > 0)
3433 /// isCalleePop - Determines whether the callee is required to pop its
3434 /// own arguments. Callee pop is necessary to support tail calls.
3435 bool X86::isCalleePop(CallingConv::ID CallingConv,
3436 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3440 switch (CallingConv) {
3443 case CallingConv::X86_StdCall:
3445 case CallingConv::X86_FastCall:
3447 case CallingConv::X86_ThisCall:
3449 case CallingConv::Fast:
3451 case CallingConv::GHC:
3453 case CallingConv::HiPE:
3458 /// \brief Return true if the condition is an unsigned comparison operation.
3459 static bool isX86CCUnsigned(unsigned X86CC) {
3461 default: llvm_unreachable("Invalid integer condition!");
3462 case X86::COND_E: return true;
3463 case X86::COND_G: return false;
3464 case X86::COND_GE: return false;
3465 case X86::COND_L: return false;
3466 case X86::COND_LE: return false;
3467 case X86::COND_NE: return true;
3468 case X86::COND_B: return true;
3469 case X86::COND_A: return true;
3470 case X86::COND_BE: return true;
3471 case X86::COND_AE: return true;
3473 llvm_unreachable("covered switch fell through?!");
3476 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3477 /// specific condition code, returning the condition code and the LHS/RHS of the
3478 /// comparison to make.
3479 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3480 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3482 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3483 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3484 // X > -1 -> X == 0, jump !sign.
3485 RHS = DAG.getConstant(0, RHS.getValueType());
3486 return X86::COND_NS;
3488 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3489 // X < 0 -> X == 0, jump on sign.
3492 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3494 RHS = DAG.getConstant(0, RHS.getValueType());
3495 return X86::COND_LE;
3499 switch (SetCCOpcode) {
3500 default: llvm_unreachable("Invalid integer condition!");
3501 case ISD::SETEQ: return X86::COND_E;
3502 case ISD::SETGT: return X86::COND_G;
3503 case ISD::SETGE: return X86::COND_GE;
3504 case ISD::SETLT: return X86::COND_L;
3505 case ISD::SETLE: return X86::COND_LE;
3506 case ISD::SETNE: return X86::COND_NE;
3507 case ISD::SETULT: return X86::COND_B;
3508 case ISD::SETUGT: return X86::COND_A;
3509 case ISD::SETULE: return X86::COND_BE;
3510 case ISD::SETUGE: return X86::COND_AE;
3514 // First determine if it is required or is profitable to flip the operands.
3516 // If LHS is a foldable load, but RHS is not, flip the condition.
3517 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3518 !ISD::isNON_EXTLoad(RHS.getNode())) {
3519 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3520 std::swap(LHS, RHS);
3523 switch (SetCCOpcode) {
3529 std::swap(LHS, RHS);
3533 // On a floating point condition, the flags are set as follows:
3535 // 0 | 0 | 0 | X > Y
3536 // 0 | 0 | 1 | X < Y
3537 // 1 | 0 | 0 | X == Y
3538 // 1 | 1 | 1 | unordered
3539 switch (SetCCOpcode) {
3540 default: llvm_unreachable("Condcode should be pre-legalized away");
3542 case ISD::SETEQ: return X86::COND_E;
3543 case ISD::SETOLT: // flipped
3545 case ISD::SETGT: return X86::COND_A;
3546 case ISD::SETOLE: // flipped
3548 case ISD::SETGE: return X86::COND_AE;
3549 case ISD::SETUGT: // flipped
3551 case ISD::SETLT: return X86::COND_B;
3552 case ISD::SETUGE: // flipped
3554 case ISD::SETLE: return X86::COND_BE;
3556 case ISD::SETNE: return X86::COND_NE;
3557 case ISD::SETUO: return X86::COND_P;
3558 case ISD::SETO: return X86::COND_NP;
3560 case ISD::SETUNE: return X86::COND_INVALID;
3564 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3565 /// code. Current x86 isa includes the following FP cmov instructions:
3566 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3567 static bool hasFPCMov(unsigned X86CC) {
3583 /// isFPImmLegal - Returns true if the target can instruction select the
3584 /// specified FP immediate natively. If false, the legalizer will
3585 /// materialize the FP immediate as a load from a constant pool.
3586 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3587 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3588 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3594 /// \brief Returns true if it is beneficial to convert a load of a constant
3595 /// to just the constant itself.
3596 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
3598 assert(Ty->isIntegerTy());
3600 unsigned BitSize = Ty->getPrimitiveSizeInBits();
3601 if (BitSize == 0 || BitSize > 64)
3606 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3607 /// the specified range (L, H].
3608 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3609 return (Val < 0) || (Val >= Low && Val < Hi);
3612 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3613 /// specified value.
3614 static bool isUndefOrEqual(int Val, int CmpVal) {
3615 return (Val < 0 || Val == CmpVal);
3618 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3619 /// from position Pos and ending in Pos+Size, falls within the specified
3620 /// sequential range (L, L+Pos]. or is undef.
3621 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3622 unsigned Pos, unsigned Size, int Low) {
3623 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3624 if (!isUndefOrEqual(Mask[i], Low))
3629 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3630 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3631 /// the second operand.
3632 static bool isPSHUFDMask(ArrayRef<int> Mask, MVT VT) {
3633 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3634 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3635 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3636 return (Mask[0] < 2 && Mask[1] < 2);
3640 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3641 /// is suitable for input to PSHUFHW.
3642 static bool isPSHUFHWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3643 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3646 // Lower quadword copied in order or undef.
3647 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3650 // Upper quadword shuffled.
3651 for (unsigned i = 4; i != 8; ++i)
3652 if (!isUndefOrInRange(Mask[i], 4, 8))
3655 if (VT == MVT::v16i16) {
3656 // Lower quadword copied in order or undef.
3657 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3660 // Upper quadword shuffled.
3661 for (unsigned i = 12; i != 16; ++i)
3662 if (!isUndefOrInRange(Mask[i], 12, 16))
3669 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3670 /// is suitable for input to PSHUFLW.
3671 static bool isPSHUFLWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3672 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3675 // Upper quadword copied in order.
3676 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3679 // Lower quadword shuffled.
3680 for (unsigned i = 0; i != 4; ++i)
3681 if (!isUndefOrInRange(Mask[i], 0, 4))
3684 if (VT == MVT::v16i16) {
3685 // Upper quadword copied in order.
3686 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3689 // Lower quadword shuffled.
3690 for (unsigned i = 8; i != 12; ++i)
3691 if (!isUndefOrInRange(Mask[i], 8, 12))
3698 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
3699 /// is suitable for input to PALIGNR.
3700 static bool isPALIGNRMask(ArrayRef<int> Mask, MVT VT,
3701 const X86Subtarget *Subtarget) {
3702 if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
3703 (VT.is256BitVector() && !Subtarget->hasInt256()))
3706 unsigned NumElts = VT.getVectorNumElements();
3707 unsigned NumLanes = VT.is512BitVector() ? 1: VT.getSizeInBits()/128;
3708 unsigned NumLaneElts = NumElts/NumLanes;
3710 // Do not handle 64-bit element shuffles with palignr.
3711 if (NumLaneElts == 2)
3714 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3716 for (i = 0; i != NumLaneElts; ++i) {
3721 // Lane is all undef, go to next lane
3722 if (i == NumLaneElts)
3725 int Start = Mask[i+l];
3727 // Make sure its in this lane in one of the sources
3728 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3729 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3732 // If not lane 0, then we must match lane 0
3733 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3736 // Correct second source to be contiguous with first source
3737 if (Start >= (int)NumElts)
3738 Start -= NumElts - NumLaneElts;
3740 // Make sure we're shifting in the right direction.
3741 if (Start <= (int)(i+l))
3746 // Check the rest of the elements to see if they are consecutive.
3747 for (++i; i != NumLaneElts; ++i) {
3748 int Idx = Mask[i+l];
3750 // Make sure its in this lane
3751 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3752 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3755 // If not lane 0, then we must match lane 0
3756 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3759 if (Idx >= (int)NumElts)
3760 Idx -= NumElts - NumLaneElts;
3762 if (!isUndefOrEqual(Idx, Start+i))
3771 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3772 /// the two vector operands have swapped position.
3773 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
3774 unsigned NumElems) {
3775 for (unsigned i = 0; i != NumElems; ++i) {
3779 else if (idx < (int)NumElems)
3780 Mask[i] = idx + NumElems;
3782 Mask[i] = idx - NumElems;
3786 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
3787 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
3788 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
3789 /// reverse of what x86 shuffles want.
3790 static bool isSHUFPMask(ArrayRef<int> Mask, MVT VT, bool Commuted = false) {
3792 unsigned NumElems = VT.getVectorNumElements();
3793 unsigned NumLanes = VT.getSizeInBits()/128;
3794 unsigned NumLaneElems = NumElems/NumLanes;
3796 if (NumLaneElems != 2 && NumLaneElems != 4)
3799 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3800 bool symetricMaskRequired =
3801 (VT.getSizeInBits() >= 256) && (EltSize == 32);
3803 // VSHUFPSY divides the resulting vector into 4 chunks.
3804 // The sources are also splitted into 4 chunks, and each destination
3805 // chunk must come from a different source chunk.
3807 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
3808 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
3810 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
3811 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
3813 // VSHUFPDY divides the resulting vector into 4 chunks.
3814 // The sources are also splitted into 4 chunks, and each destination
3815 // chunk must come from a different source chunk.
3817 // SRC1 => X3 X2 X1 X0
3818 // SRC2 => Y3 Y2 Y1 Y0
3820 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
3822 SmallVector<int, 4> MaskVal(NumLaneElems, -1);
3823 unsigned HalfLaneElems = NumLaneElems/2;
3824 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
3825 for (unsigned i = 0; i != NumLaneElems; ++i) {
3826 int Idx = Mask[i+l];
3827 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
3828 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
3830 // For VSHUFPSY, the mask of the second half must be the same as the
3831 // first but with the appropriate offsets. This works in the same way as
3832 // VPERMILPS works with masks.
3833 if (!symetricMaskRequired || Idx < 0)
3835 if (MaskVal[i] < 0) {
3836 MaskVal[i] = Idx - l;
3839 if ((signed)(Idx - l) != MaskVal[i])
3847 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
3848 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
3849 static bool isMOVHLPSMask(ArrayRef<int> Mask, MVT VT) {
3850 if (!VT.is128BitVector())
3853 unsigned NumElems = VT.getVectorNumElements();
3858 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
3859 return isUndefOrEqual(Mask[0], 6) &&
3860 isUndefOrEqual(Mask[1], 7) &&
3861 isUndefOrEqual(Mask[2], 2) &&
3862 isUndefOrEqual(Mask[3], 3);
3865 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
3866 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
3868 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, MVT VT) {
3869 if (!VT.is128BitVector())
3872 unsigned NumElems = VT.getVectorNumElements();
3877 return isUndefOrEqual(Mask[0], 2) &&
3878 isUndefOrEqual(Mask[1], 3) &&
3879 isUndefOrEqual(Mask[2], 2) &&
3880 isUndefOrEqual(Mask[3], 3);
3883 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
3884 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
3885 static bool isMOVLPMask(ArrayRef<int> Mask, MVT VT) {
3886 if (!VT.is128BitVector())
3889 unsigned NumElems = VT.getVectorNumElements();
3891 if (NumElems != 2 && NumElems != 4)
3894 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3895 if (!isUndefOrEqual(Mask[i], i + NumElems))
3898 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
3899 if (!isUndefOrEqual(Mask[i], i))
3905 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
3906 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
3907 static bool isMOVLHPSMask(ArrayRef<int> Mask, MVT VT) {
3908 if (!VT.is128BitVector())
3911 unsigned NumElems = VT.getVectorNumElements();
3913 if (NumElems != 2 && NumElems != 4)
3916 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3917 if (!isUndefOrEqual(Mask[i], i))
3920 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3921 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
3928 // Some special combinations that can be optimized.
3931 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
3932 SelectionDAG &DAG) {
3933 MVT VT = SVOp->getSimpleValueType(0);
3936 if (VT != MVT::v8i32 && VT != MVT::v8f32)
3939 ArrayRef<int> Mask = SVOp->getMask();
3941 // These are the special masks that may be optimized.
3942 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
3943 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
3944 bool MatchEvenMask = true;
3945 bool MatchOddMask = true;
3946 for (int i=0; i<8; ++i) {
3947 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
3948 MatchEvenMask = false;
3949 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
3950 MatchOddMask = false;
3953 if (!MatchEvenMask && !MatchOddMask)
3956 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
3958 SDValue Op0 = SVOp->getOperand(0);
3959 SDValue Op1 = SVOp->getOperand(1);
3961 if (MatchEvenMask) {
3962 // Shift the second operand right to 32 bits.
3963 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 };
3964 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
3966 // Shift the first operand left to 32 bits.
3967 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 };
3968 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
3970 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15};
3971 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
3974 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
3975 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
3976 static bool isUNPCKLMask(ArrayRef<int> Mask, MVT VT,
3977 bool HasInt256, bool V2IsSplat = false) {
3979 assert(VT.getSizeInBits() >= 128 &&
3980 "Unsupported vector type for unpckl");
3982 // AVX defines UNPCK* to operate independently on 128-bit lanes.
3984 unsigned NumOf256BitLanes;
3985 unsigned NumElts = VT.getVectorNumElements();
3986 if (VT.is256BitVector()) {
3987 if (NumElts != 4 && NumElts != 8 &&
3988 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
3991 NumOf256BitLanes = 1;
3992 } else if (VT.is512BitVector()) {
3993 assert(VT.getScalarType().getSizeInBits() >= 32 &&
3994 "Unsupported vector type for unpckh");
3996 NumOf256BitLanes = 2;
3999 NumOf256BitLanes = 1;
4002 unsigned NumEltsInStride = NumElts/NumOf256BitLanes;
4003 unsigned NumLaneElts = NumEltsInStride/NumLanes;
4005 for (unsigned l256 = 0; l256 < NumOf256BitLanes; l256 += 1) {
4006 for (unsigned l = 0; l != NumEltsInStride; l += NumLaneElts) {
4007 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4008 int BitI = Mask[l256*NumEltsInStride+l+i];
4009 int BitI1 = Mask[l256*NumEltsInStride+l+i+1];
4010 if (!isUndefOrEqual(BitI, j+l256*NumElts))
4012 if (V2IsSplat && !isUndefOrEqual(BitI1, NumElts))
4014 if (!isUndefOrEqual(BitI1, j+l256*NumElts+NumEltsInStride))
4022 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
4023 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
4024 static bool isUNPCKHMask(ArrayRef<int> Mask, MVT VT,
4025 bool HasInt256, bool V2IsSplat = false) {
4026 assert(VT.getSizeInBits() >= 128 &&
4027 "Unsupported vector type for unpckh");
4029 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4031 unsigned NumOf256BitLanes;
4032 unsigned NumElts = VT.getVectorNumElements();
4033 if (VT.is256BitVector()) {
4034 if (NumElts != 4 && NumElts != 8 &&
4035 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4038 NumOf256BitLanes = 1;
4039 } else if (VT.is512BitVector()) {
4040 assert(VT.getScalarType().getSizeInBits() >= 32 &&
4041 "Unsupported vector type for unpckh");
4043 NumOf256BitLanes = 2;
4046 NumOf256BitLanes = 1;
4049 unsigned NumEltsInStride = NumElts/NumOf256BitLanes;
4050 unsigned NumLaneElts = NumEltsInStride/NumLanes;
4052 for (unsigned l256 = 0; l256 < NumOf256BitLanes; l256 += 1) {
4053 for (unsigned l = 0; l != NumEltsInStride; l += NumLaneElts) {
4054 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4055 int BitI = Mask[l256*NumEltsInStride+l+i];
4056 int BitI1 = Mask[l256*NumEltsInStride+l+i+1];
4057 if (!isUndefOrEqual(BitI, j+l256*NumElts))
4059 if (V2IsSplat && !isUndefOrEqual(BitI1, NumElts))
4061 if (!isUndefOrEqual(BitI1, j+l256*NumElts+NumEltsInStride))
4069 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
4070 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
4072 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4073 unsigned NumElts = VT.getVectorNumElements();
4074 bool Is256BitVec = VT.is256BitVector();
4076 if (VT.is512BitVector())
4078 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4079 "Unsupported vector type for unpckh");
4081 if (Is256BitVec && NumElts != 4 && NumElts != 8 &&
4082 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4085 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
4086 // FIXME: Need a better way to get rid of this, there's no latency difference
4087 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
4088 // the former later. We should also remove the "_undef" special mask.
4089 if (NumElts == 4 && Is256BitVec)
4092 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4093 // independently on 128-bit lanes.
4094 unsigned NumLanes = VT.getSizeInBits()/128;
4095 unsigned NumLaneElts = NumElts/NumLanes;
4097 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4098 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4099 int BitI = Mask[l+i];
4100 int BitI1 = Mask[l+i+1];
4102 if (!isUndefOrEqual(BitI, j))
4104 if (!isUndefOrEqual(BitI1, j))
4112 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
4113 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
4115 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4116 unsigned NumElts = VT.getVectorNumElements();
4118 if (VT.is512BitVector())
4121 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4122 "Unsupported vector type for unpckh");
4124 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4125 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4128 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4129 // independently on 128-bit lanes.
4130 unsigned NumLanes = VT.getSizeInBits()/128;
4131 unsigned NumLaneElts = NumElts/NumLanes;
4133 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4134 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4135 int BitI = Mask[l+i];
4136 int BitI1 = Mask[l+i+1];
4137 if (!isUndefOrEqual(BitI, j))
4139 if (!isUndefOrEqual(BitI1, j))
4146 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
4147 /// specifies a shuffle of elements that is suitable for input to MOVSS,
4148 /// MOVSD, and MOVD, i.e. setting the lowest element.
4149 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
4150 if (VT.getVectorElementType().getSizeInBits() < 32)
4152 if (!VT.is128BitVector())
4155 unsigned NumElts = VT.getVectorNumElements();
4157 if (!isUndefOrEqual(Mask[0], NumElts))
4160 for (unsigned i = 1; i != NumElts; ++i)
4161 if (!isUndefOrEqual(Mask[i], i))
4167 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
4168 /// as permutations between 128-bit chunks or halves. As an example: this
4170 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
4171 /// The first half comes from the second half of V1 and the second half from the
4172 /// the second half of V2.
4173 static bool isVPERM2X128Mask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4174 if (!HasFp256 || !VT.is256BitVector())
4177 // The shuffle result is divided into half A and half B. In total the two
4178 // sources have 4 halves, namely: C, D, E, F. The final values of A and
4179 // B must come from C, D, E or F.
4180 unsigned HalfSize = VT.getVectorNumElements()/2;
4181 bool MatchA = false, MatchB = false;
4183 // Check if A comes from one of C, D, E, F.
4184 for (unsigned Half = 0; Half != 4; ++Half) {
4185 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
4191 // Check if B comes from one of C, D, E, F.
4192 for (unsigned Half = 0; Half != 4; ++Half) {
4193 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
4199 return MatchA && MatchB;
4202 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
4203 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
4204 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
4205 MVT VT = SVOp->getSimpleValueType(0);
4207 unsigned HalfSize = VT.getVectorNumElements()/2;
4209 unsigned FstHalf = 0, SndHalf = 0;
4210 for (unsigned i = 0; i < HalfSize; ++i) {
4211 if (SVOp->getMaskElt(i) > 0) {
4212 FstHalf = SVOp->getMaskElt(i)/HalfSize;
4216 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
4217 if (SVOp->getMaskElt(i) > 0) {
4218 SndHalf = SVOp->getMaskElt(i)/HalfSize;
4223 return (FstHalf | (SndHalf << 4));
4226 // Symetric in-lane mask. Each lane has 4 elements (for imm8)
4227 static bool isPermImmMask(ArrayRef<int> Mask, MVT VT, unsigned& Imm8) {
4228 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4232 unsigned NumElts = VT.getVectorNumElements();
4234 if (VT.is128BitVector() || (VT.is256BitVector() && EltSize == 64)) {
4235 for (unsigned i = 0; i != NumElts; ++i) {
4238 Imm8 |= Mask[i] << (i*2);
4243 unsigned LaneSize = 4;
4244 SmallVector<int, 4> MaskVal(LaneSize, -1);
4246 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4247 for (unsigned i = 0; i != LaneSize; ++i) {
4248 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4252 if (MaskVal[i] < 0) {
4253 MaskVal[i] = Mask[i+l] - l;
4254 Imm8 |= MaskVal[i] << (i*2);
4257 if (Mask[i+l] != (signed)(MaskVal[i]+l))
4264 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
4265 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
4266 /// Note that VPERMIL mask matching is different depending whether theunderlying
4267 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
4268 /// to the same elements of the low, but to the higher half of the source.
4269 /// In VPERMILPD the two lanes could be shuffled independently of each other
4270 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
4271 static bool isVPERMILPMask(ArrayRef<int> Mask, MVT VT) {
4272 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4273 if (VT.getSizeInBits() < 256 || EltSize < 32)
4275 bool symetricMaskRequired = (EltSize == 32);
4276 unsigned NumElts = VT.getVectorNumElements();
4278 unsigned NumLanes = VT.getSizeInBits()/128;
4279 unsigned LaneSize = NumElts/NumLanes;
4280 // 2 or 4 elements in one lane
4282 SmallVector<int, 4> ExpectedMaskVal(LaneSize, -1);
4283 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4284 for (unsigned i = 0; i != LaneSize; ++i) {
4285 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4287 if (symetricMaskRequired) {
4288 if (ExpectedMaskVal[i] < 0 && Mask[i+l] >= 0) {
4289 ExpectedMaskVal[i] = Mask[i+l] - l;
4292 if (!isUndefOrEqual(Mask[i+l], ExpectedMaskVal[i]+l))
4300 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
4301 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
4302 /// element of vector 2 and the other elements to come from vector 1 in order.
4303 static bool isCommutedMOVLMask(ArrayRef<int> Mask, MVT VT,
4304 bool V2IsSplat = false, bool V2IsUndef = false) {
4305 if (!VT.is128BitVector())
4308 unsigned NumOps = VT.getVectorNumElements();
4309 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
4312 if (!isUndefOrEqual(Mask[0], 0))
4315 for (unsigned i = 1; i != NumOps; ++i)
4316 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
4317 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
4318 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
4324 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4325 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
4326 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
4327 static bool isMOVSHDUPMask(ArrayRef<int> Mask, MVT VT,
4328 const X86Subtarget *Subtarget) {
4329 if (!Subtarget->hasSSE3())
4332 unsigned NumElems = VT.getVectorNumElements();
4334 if ((VT.is128BitVector() && NumElems != 4) ||
4335 (VT.is256BitVector() && NumElems != 8) ||
4336 (VT.is512BitVector() && NumElems != 16))
4339 // "i+1" is the value the indexed mask element must have
4340 for (unsigned i = 0; i != NumElems; i += 2)
4341 if (!isUndefOrEqual(Mask[i], i+1) ||
4342 !isUndefOrEqual(Mask[i+1], i+1))
4348 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4349 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
4350 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
4351 static bool isMOVSLDUPMask(ArrayRef<int> Mask, MVT VT,
4352 const X86Subtarget *Subtarget) {
4353 if (!Subtarget->hasSSE3())
4356 unsigned NumElems = VT.getVectorNumElements();
4358 if ((VT.is128BitVector() && NumElems != 4) ||
4359 (VT.is256BitVector() && NumElems != 8) ||
4360 (VT.is512BitVector() && NumElems != 16))
4363 // "i" is the value the indexed mask element must have
4364 for (unsigned i = 0; i != NumElems; i += 2)
4365 if (!isUndefOrEqual(Mask[i], i) ||
4366 !isUndefOrEqual(Mask[i+1], i))
4372 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
4373 /// specifies a shuffle of elements that is suitable for input to 256-bit
4374 /// version of MOVDDUP.
4375 static bool isMOVDDUPYMask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4376 if (!HasFp256 || !VT.is256BitVector())
4379 unsigned NumElts = VT.getVectorNumElements();
4383 for (unsigned i = 0; i != NumElts/2; ++i)
4384 if (!isUndefOrEqual(Mask[i], 0))
4386 for (unsigned i = NumElts/2; i != NumElts; ++i)
4387 if (!isUndefOrEqual(Mask[i], NumElts/2))
4392 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4393 /// specifies a shuffle of elements that is suitable for input to 128-bit
4394 /// version of MOVDDUP.
4395 static bool isMOVDDUPMask(ArrayRef<int> Mask, MVT VT) {
4396 if (!VT.is128BitVector())
4399 unsigned e = VT.getVectorNumElements() / 2;
4400 for (unsigned i = 0; i != e; ++i)
4401 if (!isUndefOrEqual(Mask[i], i))
4403 for (unsigned i = 0; i != e; ++i)
4404 if (!isUndefOrEqual(Mask[e+i], i))
4409 /// isVEXTRACTIndex - Return true if the specified
4410 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
4411 /// suitable for instruction that extract 128 or 256 bit vectors
4412 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4413 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4414 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4417 // The index should be aligned on a vecWidth-bit boundary.
4419 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4421 MVT VT = N->getSimpleValueType(0);
4422 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4423 bool Result = (Index * ElSize) % vecWidth == 0;
4428 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
4429 /// operand specifies a subvector insert that is suitable for input to
4430 /// insertion of 128 or 256-bit subvectors
4431 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4432 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4433 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4435 // The index should be aligned on a vecWidth-bit boundary.
4437 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4439 MVT VT = N->getSimpleValueType(0);
4440 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4441 bool Result = (Index * ElSize) % vecWidth == 0;
4446 bool X86::isVINSERT128Index(SDNode *N) {
4447 return isVINSERTIndex(N, 128);
4450 bool X86::isVINSERT256Index(SDNode *N) {
4451 return isVINSERTIndex(N, 256);
4454 bool X86::isVEXTRACT128Index(SDNode *N) {
4455 return isVEXTRACTIndex(N, 128);
4458 bool X86::isVEXTRACT256Index(SDNode *N) {
4459 return isVEXTRACTIndex(N, 256);
4462 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4463 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4464 /// Handles 128-bit and 256-bit.
4465 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
4466 MVT VT = N->getSimpleValueType(0);
4468 assert((VT.getSizeInBits() >= 128) &&
4469 "Unsupported vector type for PSHUF/SHUFP");
4471 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
4472 // independently on 128-bit lanes.
4473 unsigned NumElts = VT.getVectorNumElements();
4474 unsigned NumLanes = VT.getSizeInBits()/128;
4475 unsigned NumLaneElts = NumElts/NumLanes;
4477 assert((NumLaneElts == 2 || NumLaneElts == 4 || NumLaneElts == 8) &&
4478 "Only supports 2, 4 or 8 elements per lane");
4480 unsigned Shift = (NumLaneElts >= 4) ? 1 : 0;
4482 for (unsigned i = 0; i != NumElts; ++i) {
4483 int Elt = N->getMaskElt(i);
4484 if (Elt < 0) continue;
4485 Elt &= NumLaneElts - 1;
4486 unsigned ShAmt = (i << Shift) % 8;
4487 Mask |= Elt << ShAmt;
4493 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4494 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4495 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4496 MVT VT = N->getSimpleValueType(0);
4498 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4499 "Unsupported vector type for PSHUFHW");
4501 unsigned NumElts = VT.getVectorNumElements();
4504 for (unsigned l = 0; l != NumElts; l += 8) {
4505 // 8 nodes per lane, but we only care about the last 4.
4506 for (unsigned i = 0; i < 4; ++i) {
4507 int Elt = N->getMaskElt(l+i+4);
4508 if (Elt < 0) continue;
4509 Elt &= 0x3; // only 2-bits.
4510 Mask |= Elt << (i * 2);
4517 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4518 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4519 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4520 MVT VT = N->getSimpleValueType(0);
4522 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4523 "Unsupported vector type for PSHUFHW");
4525 unsigned NumElts = VT.getVectorNumElements();
4528 for (unsigned l = 0; l != NumElts; l += 8) {
4529 // 8 nodes per lane, but we only care about the first 4.
4530 for (unsigned i = 0; i < 4; ++i) {
4531 int Elt = N->getMaskElt(l+i);
4532 if (Elt < 0) continue;
4533 Elt &= 0x3; // only 2-bits
4534 Mask |= Elt << (i * 2);
4541 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
4542 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
4543 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4544 MVT VT = SVOp->getSimpleValueType(0);
4545 unsigned EltSize = VT.is512BitVector() ? 1 :
4546 VT.getVectorElementType().getSizeInBits() >> 3;
4548 unsigned NumElts = VT.getVectorNumElements();
4549 unsigned NumLanes = VT.is512BitVector() ? 1 : VT.getSizeInBits()/128;
4550 unsigned NumLaneElts = NumElts/NumLanes;
4554 for (i = 0; i != NumElts; ++i) {
4555 Val = SVOp->getMaskElt(i);
4559 if (Val >= (int)NumElts)
4560 Val -= NumElts - NumLaneElts;
4562 assert(Val - i > 0 && "PALIGNR imm should be positive");
4563 return (Val - i) * EltSize;
4566 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4567 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4568 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4569 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4572 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4574 MVT VecVT = N->getOperand(0).getSimpleValueType();
4575 MVT ElVT = VecVT.getVectorElementType();
4577 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4578 return Index / NumElemsPerChunk;
4581 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4582 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4583 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4584 llvm_unreachable("Illegal insert subvector for VINSERT");
4587 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4589 MVT VecVT = N->getSimpleValueType(0);
4590 MVT ElVT = VecVT.getVectorElementType();
4592 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4593 return Index / NumElemsPerChunk;
4596 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
4597 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4598 /// and VINSERTI128 instructions.
4599 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4600 return getExtractVEXTRACTImmediate(N, 128);
4603 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
4604 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4605 /// and VINSERTI64x4 instructions.
4606 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4607 return getExtractVEXTRACTImmediate(N, 256);
4610 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4611 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4612 /// and VINSERTI128 instructions.
4613 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4614 return getInsertVINSERTImmediate(N, 128);
4617 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4618 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4619 /// and VINSERTI64x4 instructions.
4620 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4621 return getInsertVINSERTImmediate(N, 256);
4624 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4626 bool X86::isZeroNode(SDValue Elt) {
4627 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Elt))
4628 return CN->isNullValue();
4629 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4630 return CFP->getValueAPF().isPosZero();
4634 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
4635 /// their permute mask.
4636 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
4637 SelectionDAG &DAG) {
4638 MVT VT = SVOp->getSimpleValueType(0);
4639 unsigned NumElems = VT.getVectorNumElements();
4640 SmallVector<int, 8> MaskVec;
4642 for (unsigned i = 0; i != NumElems; ++i) {
4643 int Idx = SVOp->getMaskElt(i);
4645 if (Idx < (int)NumElems)
4650 MaskVec.push_back(Idx);
4652 return DAG.getVectorShuffle(VT, SDLoc(SVOp), SVOp->getOperand(1),
4653 SVOp->getOperand(0), &MaskVec[0]);
4656 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4657 /// match movhlps. The lower half elements should come from upper half of
4658 /// V1 (and in order), and the upper half elements should come from the upper
4659 /// half of V2 (and in order).
4660 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, MVT VT) {
4661 if (!VT.is128BitVector())
4663 if (VT.getVectorNumElements() != 4)
4665 for (unsigned i = 0, e = 2; i != e; ++i)
4666 if (!isUndefOrEqual(Mask[i], i+2))
4668 for (unsigned i = 2; i != 4; ++i)
4669 if (!isUndefOrEqual(Mask[i], i+4))
4674 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4675 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4677 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
4678 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4680 N = N->getOperand(0).getNode();
4681 if (!ISD::isNON_EXTLoad(N))
4684 *LD = cast<LoadSDNode>(N);
4688 // Test whether the given value is a vector value which will be legalized
4690 static bool WillBeConstantPoolLoad(SDNode *N) {
4691 if (N->getOpcode() != ISD::BUILD_VECTOR)
4694 // Check for any non-constant elements.
4695 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4696 switch (N->getOperand(i).getNode()->getOpcode()) {
4698 case ISD::ConstantFP:
4705 // Vectors of all-zeros and all-ones are materialized with special
4706 // instructions rather than being loaded.
4707 return !ISD::isBuildVectorAllZeros(N) &&
4708 !ISD::isBuildVectorAllOnes(N);
4711 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
4712 /// match movlp{s|d}. The lower half elements should come from lower half of
4713 /// V1 (and in order), and the upper half elements should come from the upper
4714 /// half of V2 (and in order). And since V1 will become the source of the
4715 /// MOVLP, it must be either a vector load or a scalar load to vector.
4716 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
4717 ArrayRef<int> Mask, MVT VT) {
4718 if (!VT.is128BitVector())
4721 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
4723 // Is V2 is a vector load, don't do this transformation. We will try to use
4724 // load folding shufps op.
4725 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
4728 unsigned NumElems = VT.getVectorNumElements();
4730 if (NumElems != 2 && NumElems != 4)
4732 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4733 if (!isUndefOrEqual(Mask[i], i))
4735 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4736 if (!isUndefOrEqual(Mask[i], i+NumElems))
4741 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
4743 static bool isSplatVector(SDNode *N) {
4744 if (N->getOpcode() != ISD::BUILD_VECTOR)
4747 SDValue SplatValue = N->getOperand(0);
4748 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
4749 if (N->getOperand(i) != SplatValue)
4754 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
4755 /// to an zero vector.
4756 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
4757 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
4758 SDValue V1 = N->getOperand(0);
4759 SDValue V2 = N->getOperand(1);
4760 unsigned NumElems = N->getValueType(0).getVectorNumElements();
4761 for (unsigned i = 0; i != NumElems; ++i) {
4762 int Idx = N->getMaskElt(i);
4763 if (Idx >= (int)NumElems) {
4764 unsigned Opc = V2.getOpcode();
4765 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
4767 if (Opc != ISD::BUILD_VECTOR ||
4768 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
4770 } else if (Idx >= 0) {
4771 unsigned Opc = V1.getOpcode();
4772 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
4774 if (Opc != ISD::BUILD_VECTOR ||
4775 !X86::isZeroNode(V1.getOperand(Idx)))
4782 /// getZeroVector - Returns a vector of specified type with all zero elements.
4784 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4785 SelectionDAG &DAG, SDLoc dl) {
4786 assert(VT.isVector() && "Expected a vector type");
4788 // Always build SSE zero vectors as <4 x i32> bitcasted
4789 // to their dest type. This ensures they get CSE'd.
4791 if (VT.is128BitVector()) { // SSE
4792 if (Subtarget->hasSSE2()) { // SSE2
4793 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4794 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4796 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4797 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4799 } else if (VT.is256BitVector()) { // AVX
4800 if (Subtarget->hasInt256()) { // AVX2
4801 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4802 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4803 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops,
4804 array_lengthof(Ops));
4806 // 256-bit logic and arithmetic instructions in AVX are all
4807 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4808 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4809 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4810 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops,
4811 array_lengthof(Ops));
4813 } else if (VT.is512BitVector()) { // AVX-512
4814 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4815 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4816 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4817 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops, 16);
4818 } else if (VT.getScalarType() == MVT::i1) {
4819 assert(VT.getVectorNumElements() <= 16 && "Unexpected vector type");
4820 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
4821 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4822 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4823 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
4824 Ops, VT.getVectorNumElements());
4826 llvm_unreachable("Unexpected vector type");
4828 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4831 /// getOnesVector - Returns a vector of specified type with all bits set.
4832 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4833 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4834 /// Then bitcast to their original type, ensuring they get CSE'd.
4835 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
4837 assert(VT.isVector() && "Expected a vector type");
4839 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
4841 if (VT.is256BitVector()) {
4842 if (HasInt256) { // AVX2
4843 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4844 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops,
4845 array_lengthof(Ops));
4847 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4848 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4850 } else if (VT.is128BitVector()) {
4851 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4853 llvm_unreachable("Unexpected vector type");
4855 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4858 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
4859 /// that point to V2 points to its first element.
4860 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
4861 for (unsigned i = 0; i != NumElems; ++i) {
4862 if (Mask[i] > (int)NumElems) {
4868 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4869 /// operation of specified width.
4870 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
4872 unsigned NumElems = VT.getVectorNumElements();
4873 SmallVector<int, 8> Mask;
4874 Mask.push_back(NumElems);
4875 for (unsigned i = 1; i != NumElems; ++i)
4877 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4880 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4881 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4883 unsigned NumElems = VT.getVectorNumElements();
4884 SmallVector<int, 8> Mask;
4885 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4887 Mask.push_back(i + NumElems);
4889 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4892 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4893 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4895 unsigned NumElems = VT.getVectorNumElements();
4896 SmallVector<int, 8> Mask;
4897 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
4898 Mask.push_back(i + Half);
4899 Mask.push_back(i + NumElems + Half);
4901 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4904 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
4905 // a generic shuffle instruction because the target has no such instructions.
4906 // Generate shuffles which repeat i16 and i8 several times until they can be
4907 // represented by v4f32 and then be manipulated by target suported shuffles.
4908 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
4909 MVT VT = V.getSimpleValueType();
4910 int NumElems = VT.getVectorNumElements();
4913 while (NumElems > 4) {
4914 if (EltNo < NumElems/2) {
4915 V = getUnpackl(DAG, dl, VT, V, V);
4917 V = getUnpackh(DAG, dl, VT, V, V);
4918 EltNo -= NumElems/2;
4925 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
4926 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
4927 MVT VT = V.getSimpleValueType();
4930 if (VT.is128BitVector()) {
4931 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
4932 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
4933 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
4935 } else if (VT.is256BitVector()) {
4936 // To use VPERMILPS to splat scalars, the second half of indicies must
4937 // refer to the higher part, which is a duplication of the lower one,
4938 // because VPERMILPS can only handle in-lane permutations.
4939 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
4940 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
4942 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
4943 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
4946 llvm_unreachable("Vector size not supported");
4948 return DAG.getNode(ISD::BITCAST, dl, VT, V);
4951 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
4952 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
4953 MVT SrcVT = SV->getSimpleValueType(0);
4954 SDValue V1 = SV->getOperand(0);
4957 int EltNo = SV->getSplatIndex();
4958 int NumElems = SrcVT.getVectorNumElements();
4959 bool Is256BitVec = SrcVT.is256BitVector();
4961 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) &&
4962 "Unknown how to promote splat for type");
4964 // Extract the 128-bit part containing the splat element and update
4965 // the splat element index when it refers to the higher register.
4967 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
4968 if (EltNo >= NumElems/2)
4969 EltNo -= NumElems/2;
4972 // All i16 and i8 vector types can't be used directly by a generic shuffle
4973 // instruction because the target has no such instruction. Generate shuffles
4974 // which repeat i16 and i8 several times until they fit in i32, and then can
4975 // be manipulated by target suported shuffles.
4976 MVT EltVT = SrcVT.getVectorElementType();
4977 if (EltVT == MVT::i8 || EltVT == MVT::i16)
4978 V1 = PromoteSplati8i16(V1, DAG, EltNo);
4980 // Recreate the 256-bit vector and place the same 128-bit vector
4981 // into the low and high part. This is necessary because we want
4982 // to use VPERM* to shuffle the vectors
4984 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
4987 return getLegalSplat(DAG, V1, EltNo);
4990 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
4991 /// vector of zero or undef vector. This produces a shuffle where the low
4992 /// element of V2 is swizzled into the zero/undef vector, landing at element
4993 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4994 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4996 const X86Subtarget *Subtarget,
4997 SelectionDAG &DAG) {
4998 MVT VT = V2.getSimpleValueType();
5000 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
5001 unsigned NumElems = VT.getVectorNumElements();
5002 SmallVector<int, 16> MaskVec;
5003 for (unsigned i = 0; i != NumElems; ++i)
5004 // If this is the insertion idx, put the low elt of V2 here.
5005 MaskVec.push_back(i == Idx ? NumElems : i);
5006 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
5009 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
5010 /// target specific opcode. Returns true if the Mask could be calculated.
5011 /// Sets IsUnary to true if only uses one source.
5012 static bool getTargetShuffleMask(SDNode *N, MVT VT,
5013 SmallVectorImpl<int> &Mask, bool &IsUnary) {
5014 unsigned NumElems = VT.getVectorNumElements();
5018 switch(N->getOpcode()) {
5020 ImmN = N->getOperand(N->getNumOperands()-1);
5021 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5023 case X86ISD::UNPCKH:
5024 DecodeUNPCKHMask(VT, Mask);
5026 case X86ISD::UNPCKL:
5027 DecodeUNPCKLMask(VT, Mask);
5029 case X86ISD::MOVHLPS:
5030 DecodeMOVHLPSMask(NumElems, Mask);
5032 case X86ISD::MOVLHPS:
5033 DecodeMOVLHPSMask(NumElems, Mask);
5035 case X86ISD::PALIGNR:
5036 ImmN = N->getOperand(N->getNumOperands()-1);
5037 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5039 case X86ISD::PSHUFD:
5040 case X86ISD::VPERMILP:
5041 ImmN = N->getOperand(N->getNumOperands()-1);
5042 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5045 case X86ISD::PSHUFHW:
5046 ImmN = N->getOperand(N->getNumOperands()-1);
5047 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5050 case X86ISD::PSHUFLW:
5051 ImmN = N->getOperand(N->getNumOperands()-1);
5052 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5055 case X86ISD::VPERMI:
5056 ImmN = N->getOperand(N->getNumOperands()-1);
5057 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5061 case X86ISD::MOVSD: {
5062 // The index 0 always comes from the first element of the second source,
5063 // this is why MOVSS and MOVSD are used in the first place. The other
5064 // elements come from the other positions of the first source vector
5065 Mask.push_back(NumElems);
5066 for (unsigned i = 1; i != NumElems; ++i) {
5071 case X86ISD::VPERM2X128:
5072 ImmN = N->getOperand(N->getNumOperands()-1);
5073 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5074 if (Mask.empty()) return false;
5076 case X86ISD::MOVDDUP:
5077 case X86ISD::MOVLHPD:
5078 case X86ISD::MOVLPD:
5079 case X86ISD::MOVLPS:
5080 case X86ISD::MOVSHDUP:
5081 case X86ISD::MOVSLDUP:
5082 // Not yet implemented
5084 default: llvm_unreachable("unknown target shuffle node");
5090 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
5091 /// element of the result of the vector shuffle.
5092 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
5095 return SDValue(); // Limit search depth.
5097 SDValue V = SDValue(N, 0);
5098 EVT VT = V.getValueType();
5099 unsigned Opcode = V.getOpcode();
5101 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
5102 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
5103 int Elt = SV->getMaskElt(Index);
5106 return DAG.getUNDEF(VT.getVectorElementType());
5108 unsigned NumElems = VT.getVectorNumElements();
5109 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
5110 : SV->getOperand(1);
5111 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
5114 // Recurse into target specific vector shuffles to find scalars.
5115 if (isTargetShuffle(Opcode)) {
5116 MVT ShufVT = V.getSimpleValueType();
5117 unsigned NumElems = ShufVT.getVectorNumElements();
5118 SmallVector<int, 16> ShuffleMask;
5121 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
5124 int Elt = ShuffleMask[Index];
5126 return DAG.getUNDEF(ShufVT.getVectorElementType());
5128 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
5130 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
5134 // Actual nodes that may contain scalar elements
5135 if (Opcode == ISD::BITCAST) {
5136 V = V.getOperand(0);
5137 EVT SrcVT = V.getValueType();
5138 unsigned NumElems = VT.getVectorNumElements();
5140 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5144 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5145 return (Index == 0) ? V.getOperand(0)
5146 : DAG.getUNDEF(VT.getVectorElementType());
5148 if (V.getOpcode() == ISD::BUILD_VECTOR)
5149 return V.getOperand(Index);
5154 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
5155 /// shuffle operation which come from a consecutively from a zero. The
5156 /// search can start in two different directions, from left or right.
5157 /// We count undefs as zeros until PreferredNum is reached.
5158 static unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp,
5159 unsigned NumElems, bool ZerosFromLeft,
5161 unsigned PreferredNum = -1U) {
5162 unsigned NumZeros = 0;
5163 for (unsigned i = 0; i != NumElems; ++i) {
5164 unsigned Index = ZerosFromLeft ? i : NumElems - i - 1;
5165 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
5169 if (X86::isZeroNode(Elt))
5171 else if (Elt.getOpcode() == ISD::UNDEF) // Undef as zero up to PreferredNum.
5172 NumZeros = std::min(NumZeros + 1, PreferredNum);
5180 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
5181 /// correspond consecutively to elements from one of the vector operands,
5182 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
5184 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
5185 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
5186 unsigned NumElems, unsigned &OpNum) {
5187 bool SeenV1 = false;
5188 bool SeenV2 = false;
5190 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
5191 int Idx = SVOp->getMaskElt(i);
5192 // Ignore undef indicies
5196 if (Idx < (int)NumElems)
5201 // Only accept consecutive elements from the same vector
5202 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
5206 OpNum = SeenV1 ? 0 : 1;
5210 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
5211 /// logical left shift of a vector.
5212 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5213 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5215 SVOp->getSimpleValueType(0).getVectorNumElements();
5216 unsigned NumZeros = getNumOfConsecutiveZeros(
5217 SVOp, NumElems, false /* check zeros from right */, DAG,
5218 SVOp->getMaskElt(0));
5224 // Considering the elements in the mask that are not consecutive zeros,
5225 // check if they consecutively come from only one of the source vectors.
5227 // V1 = {X, A, B, C} 0
5229 // vector_shuffle V1, V2 <1, 2, 3, X>
5231 if (!isShuffleMaskConsecutive(SVOp,
5232 0, // Mask Start Index
5233 NumElems-NumZeros, // Mask End Index(exclusive)
5234 NumZeros, // Where to start looking in the src vector
5235 NumElems, // Number of elements in vector
5236 OpSrc)) // Which source operand ?
5241 ShVal = SVOp->getOperand(OpSrc);
5245 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
5246 /// logical left shift of a vector.
5247 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5248 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5250 SVOp->getSimpleValueType(0).getVectorNumElements();
5251 unsigned NumZeros = getNumOfConsecutiveZeros(
5252 SVOp, NumElems, true /* check zeros from left */, DAG,
5253 NumElems - SVOp->getMaskElt(NumElems - 1) - 1);
5259 // Considering the elements in the mask that are not consecutive zeros,
5260 // check if they consecutively come from only one of the source vectors.
5262 // 0 { A, B, X, X } = V2
5264 // vector_shuffle V1, V2 <X, X, 4, 5>
5266 if (!isShuffleMaskConsecutive(SVOp,
5267 NumZeros, // Mask Start Index
5268 NumElems, // Mask End Index(exclusive)
5269 0, // Where to start looking in the src vector
5270 NumElems, // Number of elements in vector
5271 OpSrc)) // Which source operand ?
5276 ShVal = SVOp->getOperand(OpSrc);
5280 /// isVectorShift - Returns true if the shuffle can be implemented as a
5281 /// logical left or right shift of a vector.
5282 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5283 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5284 // Although the logic below support any bitwidth size, there are no
5285 // shift instructions which handle more than 128-bit vectors.
5286 if (!SVOp->getSimpleValueType(0).is128BitVector())
5289 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
5290 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
5296 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
5298 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5299 unsigned NumNonZero, unsigned NumZero,
5301 const X86Subtarget* Subtarget,
5302 const TargetLowering &TLI) {
5309 for (unsigned i = 0; i < 16; ++i) {
5310 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5311 if (ThisIsNonZero && First) {
5313 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5315 V = DAG.getUNDEF(MVT::v8i16);
5320 SDValue ThisElt(0, 0), LastElt(0, 0);
5321 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5322 if (LastIsNonZero) {
5323 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5324 MVT::i16, Op.getOperand(i-1));
5326 if (ThisIsNonZero) {
5327 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5328 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5329 ThisElt, DAG.getConstant(8, MVT::i8));
5331 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5335 if (ThisElt.getNode())
5336 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5337 DAG.getIntPtrConstant(i/2));
5341 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
5344 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
5346 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5347 unsigned NumNonZero, unsigned NumZero,
5349 const X86Subtarget* Subtarget,
5350 const TargetLowering &TLI) {
5357 for (unsigned i = 0; i < 8; ++i) {
5358 bool isNonZero = (NonZeros & (1 << i)) != 0;
5362 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5364 V = DAG.getUNDEF(MVT::v8i16);
5367 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5368 MVT::v8i16, V, Op.getOperand(i),
5369 DAG.getIntPtrConstant(i));
5376 /// getVShift - Return a vector logical shift node.
5378 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5379 unsigned NumBits, SelectionDAG &DAG,
5380 const TargetLowering &TLI, SDLoc dl) {
5381 assert(VT.is128BitVector() && "Unknown type for VShift");
5382 EVT ShVT = MVT::v2i64;
5383 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5384 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
5385 return DAG.getNode(ISD::BITCAST, dl, VT,
5386 DAG.getNode(Opc, dl, ShVT, SrcOp,
5387 DAG.getConstant(NumBits,
5388 TLI.getScalarShiftAmountTy(SrcOp.getValueType()))));
5392 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5394 // Check if the scalar load can be widened into a vector load. And if
5395 // the address is "base + cst" see if the cst can be "absorbed" into
5396 // the shuffle mask.
5397 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5398 SDValue Ptr = LD->getBasePtr();
5399 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5401 EVT PVT = LD->getValueType(0);
5402 if (PVT != MVT::i32 && PVT != MVT::f32)
5407 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5408 FI = FINode->getIndex();
5410 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5411 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5412 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5413 Offset = Ptr.getConstantOperandVal(1);
5414 Ptr = Ptr.getOperand(0);
5419 // FIXME: 256-bit vector instructions don't require a strict alignment,
5420 // improve this code to support it better.
5421 unsigned RequiredAlign = VT.getSizeInBits()/8;
5422 SDValue Chain = LD->getChain();
5423 // Make sure the stack object alignment is at least 16 or 32.
5424 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5425 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5426 if (MFI->isFixedObjectIndex(FI)) {
5427 // Can't change the alignment. FIXME: It's possible to compute
5428 // the exact stack offset and reference FI + adjust offset instead.
5429 // If someone *really* cares about this. That's the way to implement it.
5432 MFI->setObjectAlignment(FI, RequiredAlign);
5436 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5437 // Ptr + (Offset & ~15).
5440 if ((Offset % RequiredAlign) & 3)
5442 int64_t StartOffset = Offset & ~(RequiredAlign-1);
5444 Ptr = DAG.getNode(ISD::ADD, SDLoc(Ptr), Ptr.getValueType(),
5445 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
5447 int EltNo = (Offset - StartOffset) >> 2;
5448 unsigned NumElems = VT.getVectorNumElements();
5450 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5451 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5452 LD->getPointerInfo().getWithOffset(StartOffset),
5453 false, false, false, 0);
5455 SmallVector<int, 8> Mask;
5456 for (unsigned i = 0; i != NumElems; ++i)
5457 Mask.push_back(EltNo);
5459 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5465 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
5466 /// vector of type 'VT', see if the elements can be replaced by a single large
5467 /// load which has the same value as a build_vector whose operands are 'elts'.
5469 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5471 /// FIXME: we'd also like to handle the case where the last elements are zero
5472 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5473 /// There's even a handy isZeroNode for that purpose.
5474 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
5475 SDLoc &DL, SelectionDAG &DAG,
5476 bool isAfterLegalize) {
5477 EVT EltVT = VT.getVectorElementType();
5478 unsigned NumElems = Elts.size();
5480 LoadSDNode *LDBase = NULL;
5481 unsigned LastLoadedElt = -1U;
5483 // For each element in the initializer, see if we've found a load or an undef.
5484 // If we don't find an initial load element, or later load elements are
5485 // non-consecutive, bail out.
5486 for (unsigned i = 0; i < NumElems; ++i) {
5487 SDValue Elt = Elts[i];
5489 if (!Elt.getNode() ||
5490 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5493 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5495 LDBase = cast<LoadSDNode>(Elt.getNode());
5499 if (Elt.getOpcode() == ISD::UNDEF)
5502 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5503 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
5508 // If we have found an entire vector of loads and undefs, then return a large
5509 // load of the entire vector width starting at the base pointer. If we found
5510 // consecutive loads for the low half, generate a vzext_load node.
5511 if (LastLoadedElt == NumElems - 1) {
5513 if (isAfterLegalize &&
5514 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
5517 SDValue NewLd = SDValue();
5519 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
5520 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5521 LDBase->getPointerInfo(),
5522 LDBase->isVolatile(), LDBase->isNonTemporal(),
5523 LDBase->isInvariant(), 0);
5524 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5525 LDBase->getPointerInfo(),
5526 LDBase->isVolatile(), LDBase->isNonTemporal(),
5527 LDBase->isInvariant(), LDBase->getAlignment());
5529 if (LDBase->hasAnyUseOfValue(1)) {
5530 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5532 SDValue(NewLd.getNode(), 1));
5533 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5534 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5535 SDValue(NewLd.getNode(), 1));
5540 if (NumElems == 4 && LastLoadedElt == 1 &&
5541 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5542 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5543 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5545 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops,
5546 array_lengthof(Ops), MVT::i64,
5547 LDBase->getPointerInfo(),
5548 LDBase->getAlignment(),
5549 false/*isVolatile*/, true/*ReadMem*/,
5552 // Make sure the newly-created LOAD is in the same position as LDBase in
5553 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5554 // update uses of LDBase's output chain to use the TokenFactor.
5555 if (LDBase->hasAnyUseOfValue(1)) {
5556 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5557 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5558 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5559 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5560 SDValue(ResNode.getNode(), 1));
5563 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
5568 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
5569 /// to generate a splat value for the following cases:
5570 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
5571 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
5572 /// a scalar load, or a constant.
5573 /// The VBROADCAST node is returned when a pattern is found,
5574 /// or SDValue() otherwise.
5575 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
5576 SelectionDAG &DAG) {
5577 if (!Subtarget->hasFp256())
5580 MVT VT = Op.getSimpleValueType();
5583 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
5584 "Unsupported vector type for broadcast.");
5589 switch (Op.getOpcode()) {
5591 // Unknown pattern found.
5594 case ISD::BUILD_VECTOR: {
5595 // The BUILD_VECTOR node must be a splat.
5596 if (!isSplatVector(Op.getNode()))
5599 Ld = Op.getOperand(0);
5600 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5601 Ld.getOpcode() == ISD::ConstantFP);
5603 // The suspected load node has several users. Make sure that all
5604 // of its users are from the BUILD_VECTOR node.
5605 // Constants may have multiple users.
5606 if (!ConstSplatVal && !Ld->hasNUsesOfValue(VT.getVectorNumElements(), 0))
5611 case ISD::VECTOR_SHUFFLE: {
5612 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5614 // Shuffles must have a splat mask where the first element is
5616 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
5619 SDValue Sc = Op.getOperand(0);
5620 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
5621 Sc.getOpcode() != ISD::BUILD_VECTOR) {
5623 if (!Subtarget->hasInt256())
5626 // Use the register form of the broadcast instruction available on AVX2.
5627 if (VT.getSizeInBits() >= 256)
5628 Sc = Extract128BitVector(Sc, 0, DAG, dl);
5629 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
5632 Ld = Sc.getOperand(0);
5633 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5634 Ld.getOpcode() == ISD::ConstantFP);
5636 // The scalar_to_vector node and the suspected
5637 // load node must have exactly one user.
5638 // Constants may have multiple users.
5640 // AVX-512 has register version of the broadcast
5641 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
5642 Ld.getValueType().getSizeInBits() >= 32;
5643 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
5650 bool IsGE256 = (VT.getSizeInBits() >= 256);
5652 // Handle the broadcasting a single constant scalar from the constant pool
5653 // into a vector. On Sandybridge it is still better to load a constant vector
5654 // from the constant pool and not to broadcast it from a scalar.
5655 if (ConstSplatVal && Subtarget->hasInt256()) {
5656 EVT CVT = Ld.getValueType();
5657 assert(!CVT.isVector() && "Must not broadcast a vector type");
5658 unsigned ScalarSize = CVT.getSizeInBits();
5660 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)) {
5661 const Constant *C = 0;
5662 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
5663 C = CI->getConstantIntValue();
5664 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
5665 C = CF->getConstantFPValue();
5667 assert(C && "Invalid constant type");
5669 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5670 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
5671 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
5672 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
5673 MachinePointerInfo::getConstantPool(),
5674 false, false, false, Alignment);
5676 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5680 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
5681 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5683 // Handle AVX2 in-register broadcasts.
5684 if (!IsLoad && Subtarget->hasInt256() &&
5685 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
5686 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5688 // The scalar source must be a normal load.
5692 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64))
5693 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5695 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5696 // double since there is no vbroadcastsd xmm
5697 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
5698 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
5699 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5702 // Unsupported broadcast.
5706 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
5707 MVT VT = Op.getSimpleValueType();
5709 // Skip if insert_vec_elt is not supported.
5710 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5711 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
5715 unsigned NumElems = Op.getNumOperands();
5719 SmallVector<unsigned, 4> InsertIndices;
5720 SmallVector<int, 8> Mask(NumElems, -1);
5722 for (unsigned i = 0; i != NumElems; ++i) {
5723 unsigned Opc = Op.getOperand(i).getOpcode();
5725 if (Opc == ISD::UNDEF)
5728 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
5729 // Quit if more than 1 elements need inserting.
5730 if (InsertIndices.size() > 1)
5733 InsertIndices.push_back(i);
5737 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
5738 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
5740 // Quit if extracted from vector of different type.
5741 if (ExtractedFromVec.getValueType() != VT)
5744 // Quit if non-constant index.
5745 if (!isa<ConstantSDNode>(ExtIdx))
5748 if (VecIn1.getNode() == 0)
5749 VecIn1 = ExtractedFromVec;
5750 else if (VecIn1 != ExtractedFromVec) {
5751 if (VecIn2.getNode() == 0)
5752 VecIn2 = ExtractedFromVec;
5753 else if (VecIn2 != ExtractedFromVec)
5754 // Quit if more than 2 vectors to shuffle
5758 unsigned Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
5760 if (ExtractedFromVec == VecIn1)
5762 else if (ExtractedFromVec == VecIn2)
5763 Mask[i] = Idx + NumElems;
5766 if (VecIn1.getNode() == 0)
5769 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
5770 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
5771 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
5772 unsigned Idx = InsertIndices[i];
5773 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
5774 DAG.getIntPtrConstant(Idx));
5780 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
5782 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
5784 MVT VT = Op.getSimpleValueType();
5785 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
5786 "Unexpected type in LowerBUILD_VECTORvXi1!");
5789 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5790 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
5791 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
5792 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5793 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
5794 Ops, VT.getVectorNumElements());
5797 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5798 SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
5799 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
5800 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5801 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
5802 Ops, VT.getVectorNumElements());
5805 bool AllContants = true;
5806 uint64_t Immediate = 0;
5807 int NonConstIdx = -1;
5808 bool IsSplat = true;
5809 unsigned NumNonConsts = 0;
5810 unsigned NumConsts = 0;
5811 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5812 SDValue In = Op.getOperand(idx);
5813 if (In.getOpcode() == ISD::UNDEF)
5815 if (!isa<ConstantSDNode>(In)) {
5816 AllContants = false;
5822 if (cast<ConstantSDNode>(In)->getZExtValue())
5823 Immediate |= (1ULL << idx);
5825 if (In != Op.getOperand(0))
5830 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
5831 DAG.getConstant(Immediate, MVT::i16));
5832 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
5833 DAG.getIntPtrConstant(0));
5836 if (NumNonConsts == 1 && NonConstIdx != 0) {
5839 SDValue VecAsImm = DAG.getConstant(Immediate,
5840 MVT::getIntegerVT(VT.getSizeInBits()));
5841 DstVec = DAG.getNode(ISD::BITCAST, dl, VT, VecAsImm);
5844 DstVec = DAG.getUNDEF(VT);
5845 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
5846 Op.getOperand(NonConstIdx),
5847 DAG.getIntPtrConstant(NonConstIdx));
5849 if (!IsSplat && (NonConstIdx != 0))
5850 llvm_unreachable("Unsupported BUILD_VECTOR operation");
5851 MVT SelectVT = (VT == MVT::v16i1)? MVT::i16 : MVT::i8;
5854 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
5855 DAG.getConstant(-1, SelectVT),
5856 DAG.getConstant(0, SelectVT));
5858 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
5859 DAG.getConstant((Immediate | 1), SelectVT),
5860 DAG.getConstant(Immediate, SelectVT));
5861 return DAG.getNode(ISD::BITCAST, dl, VT, Select);
5865 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
5868 MVT VT = Op.getSimpleValueType();
5869 MVT ExtVT = VT.getVectorElementType();
5870 unsigned NumElems = Op.getNumOperands();
5872 // Generate vectors for predicate vectors.
5873 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
5874 return LowerBUILD_VECTORvXi1(Op, DAG);
5876 // Vectors containing all zeros can be matched by pxor and xorps later
5877 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5878 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
5879 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
5880 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
5883 return getZeroVector(VT, Subtarget, DAG, dl);
5886 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
5887 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
5888 // vpcmpeqd on 256-bit vectors.
5889 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
5890 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
5893 if (!VT.is512BitVector())
5894 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
5897 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
5898 if (Broadcast.getNode())
5901 unsigned EVTBits = ExtVT.getSizeInBits();
5903 unsigned NumZero = 0;
5904 unsigned NumNonZero = 0;
5905 unsigned NonZeros = 0;
5906 bool IsAllConstants = true;
5907 SmallSet<SDValue, 8> Values;
5908 for (unsigned i = 0; i < NumElems; ++i) {
5909 SDValue Elt = Op.getOperand(i);
5910 if (Elt.getOpcode() == ISD::UNDEF)
5913 if (Elt.getOpcode() != ISD::Constant &&
5914 Elt.getOpcode() != ISD::ConstantFP)
5915 IsAllConstants = false;
5916 if (X86::isZeroNode(Elt))
5919 NonZeros |= (1 << i);
5924 // All undef vector. Return an UNDEF. All zero vectors were handled above.
5925 if (NumNonZero == 0)
5926 return DAG.getUNDEF(VT);
5928 // Special case for single non-zero, non-undef, element.
5929 if (NumNonZero == 1) {
5930 unsigned Idx = countTrailingZeros(NonZeros);
5931 SDValue Item = Op.getOperand(Idx);
5933 // If this is an insertion of an i64 value on x86-32, and if the top bits of
5934 // the value are obviously zero, truncate the value to i32 and do the
5935 // insertion that way. Only do this if the value is non-constant or if the
5936 // value is a constant being inserted into element 0. It is cheaper to do
5937 // a constant pool load than it is to do a movd + shuffle.
5938 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
5939 (!IsAllConstants || Idx == 0)) {
5940 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
5942 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
5943 EVT VecVT = MVT::v4i32;
5944 unsigned VecElts = 4;
5946 // Truncate the value (which may itself be a constant) to i32, and
5947 // convert it to a vector with movd (S2V+shuffle to zero extend).
5948 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
5949 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
5950 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5952 // Now we have our 32-bit value zero extended in the low element of
5953 // a vector. If Idx != 0, swizzle it into place.
5955 SmallVector<int, 4> Mask;
5956 Mask.push_back(Idx);
5957 for (unsigned i = 1; i != VecElts; ++i)
5959 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
5962 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5966 // If we have a constant or non-constant insertion into the low element of
5967 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
5968 // the rest of the elements. This will be matched as movd/movq/movss/movsd
5969 // depending on what the source datatype is.
5972 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5974 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
5975 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
5976 if (VT.is256BitVector() || VT.is512BitVector()) {
5977 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
5978 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
5979 Item, DAG.getIntPtrConstant(0));
5981 assert(VT.is128BitVector() && "Expected an SSE value type!");
5982 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5983 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
5984 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5987 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
5988 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
5989 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5990 if (VT.is256BitVector()) {
5991 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
5992 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
5994 assert(VT.is128BitVector() && "Expected an SSE value type!");
5995 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5997 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6001 // Is it a vector logical left shift?
6002 if (NumElems == 2 && Idx == 1 &&
6003 X86::isZeroNode(Op.getOperand(0)) &&
6004 !X86::isZeroNode(Op.getOperand(1))) {
6005 unsigned NumBits = VT.getSizeInBits();
6006 return getVShift(true, VT,
6007 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6008 VT, Op.getOperand(1)),
6009 NumBits/2, DAG, *this, dl);
6012 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
6015 // Otherwise, if this is a vector with i32 or f32 elements, and the element
6016 // is a non-constant being inserted into an element other than the low one,
6017 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
6018 // movd/movss) to move this into the low element, then shuffle it into
6020 if (EVTBits == 32) {
6021 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6023 // Turn it into a shuffle of zero and zero-extended scalar to vector.
6024 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
6025 SmallVector<int, 8> MaskVec;
6026 for (unsigned i = 0; i != NumElems; ++i)
6027 MaskVec.push_back(i == Idx ? 0 : 1);
6028 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
6032 // Splat is obviously ok. Let legalizer expand it to a shuffle.
6033 if (Values.size() == 1) {
6034 if (EVTBits == 32) {
6035 // Instead of a shuffle like this:
6036 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
6037 // Check if it's possible to issue this instead.
6038 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
6039 unsigned Idx = countTrailingZeros(NonZeros);
6040 SDValue Item = Op.getOperand(Idx);
6041 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
6042 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6047 // A vector full of immediates; various special cases are already
6048 // handled, so this is best done with a single constant-pool load.
6052 // For AVX-length vectors, build the individual 128-bit pieces and use
6053 // shuffles to put them in place.
6054 if (VT.is256BitVector() || VT.is512BitVector()) {
6055 SmallVector<SDValue, 64> V;
6056 for (unsigned i = 0; i != NumElems; ++i)
6057 V.push_back(Op.getOperand(i));
6059 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
6061 // Build both the lower and upper subvector.
6062 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2);
6063 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2],
6066 // Recreate the wider vector with the lower and upper part.
6067 if (VT.is256BitVector())
6068 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6069 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6072 // Let legalizer expand 2-wide build_vectors.
6073 if (EVTBits == 64) {
6074 if (NumNonZero == 1) {
6075 // One half is zero or undef.
6076 unsigned Idx = countTrailingZeros(NonZeros);
6077 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
6078 Op.getOperand(Idx));
6079 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
6084 // If element VT is < 32 bits, convert it to inserts into a zero vector.
6085 if (EVTBits == 8 && NumElems == 16) {
6086 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
6088 if (V.getNode()) return V;
6091 if (EVTBits == 16 && NumElems == 8) {
6092 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
6094 if (V.getNode()) return V;
6097 // If element VT is == 32 bits, turn it into a number of shuffles.
6098 SmallVector<SDValue, 8> V(NumElems);
6099 if (NumElems == 4 && NumZero > 0) {
6100 for (unsigned i = 0; i < 4; ++i) {
6101 bool isZero = !(NonZeros & (1 << i));
6103 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
6105 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6108 for (unsigned i = 0; i < 2; ++i) {
6109 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
6112 V[i] = V[i*2]; // Must be a zero vector.
6115 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
6118 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
6121 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
6126 bool Reverse1 = (NonZeros & 0x3) == 2;
6127 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
6131 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
6132 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
6134 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
6137 if (Values.size() > 1 && VT.is128BitVector()) {
6138 // Check for a build vector of consecutive loads.
6139 for (unsigned i = 0; i < NumElems; ++i)
6140 V[i] = Op.getOperand(i);
6142 // Check for elements which are consecutive loads.
6143 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false);
6147 // Check for a build vector from mostly shuffle plus few inserting.
6148 SDValue Sh = buildFromShuffleMostly(Op, DAG);
6152 // For SSE 4.1, use insertps to put the high elements into the low element.
6153 if (getSubtarget()->hasSSE41()) {
6155 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
6156 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
6158 Result = DAG.getUNDEF(VT);
6160 for (unsigned i = 1; i < NumElems; ++i) {
6161 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
6162 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
6163 Op.getOperand(i), DAG.getIntPtrConstant(i));
6168 // Otherwise, expand into a number of unpckl*, start by extending each of
6169 // our (non-undef) elements to the full vector width with the element in the
6170 // bottom slot of the vector (which generates no code for SSE).
6171 for (unsigned i = 0; i < NumElems; ++i) {
6172 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
6173 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6175 V[i] = DAG.getUNDEF(VT);
6178 // Next, we iteratively mix elements, e.g. for v4f32:
6179 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
6180 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
6181 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
6182 unsigned EltStride = NumElems >> 1;
6183 while (EltStride != 0) {
6184 for (unsigned i = 0; i < EltStride; ++i) {
6185 // If V[i+EltStride] is undef and this is the first round of mixing,
6186 // then it is safe to just drop this shuffle: V[i] is already in the
6187 // right place, the one element (since it's the first round) being
6188 // inserted as undef can be dropped. This isn't safe for successive
6189 // rounds because they will permute elements within both vectors.
6190 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
6191 EltStride == NumElems/2)
6194 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
6203 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
6204 // to create 256-bit vectors from two other 128-bit ones.
6205 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6207 MVT ResVT = Op.getSimpleValueType();
6209 assert((ResVT.is256BitVector() ||
6210 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
6212 SDValue V1 = Op.getOperand(0);
6213 SDValue V2 = Op.getOperand(1);
6214 unsigned NumElems = ResVT.getVectorNumElements();
6215 if(ResVT.is256BitVector())
6216 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6218 if (Op.getNumOperands() == 4) {
6219 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
6220 ResVT.getVectorNumElements()/2);
6221 SDValue V3 = Op.getOperand(2);
6222 SDValue V4 = Op.getOperand(3);
6223 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
6224 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
6226 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6229 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6230 MVT LLVM_ATTRIBUTE_UNUSED VT = Op.getSimpleValueType();
6231 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
6232 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
6233 Op.getNumOperands() == 4)));
6235 // AVX can use the vinsertf128 instruction to create 256-bit vectors
6236 // from two other 128-bit ones.
6238 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
6239 return LowerAVXCONCAT_VECTORS(Op, DAG);
6242 // Try to lower a shuffle node into a simple blend instruction.
6244 LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
6245 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
6246 SDValue V1 = SVOp->getOperand(0);
6247 SDValue V2 = SVOp->getOperand(1);
6249 MVT VT = SVOp->getSimpleValueType(0);
6250 MVT EltVT = VT.getVectorElementType();
6251 unsigned NumElems = VT.getVectorNumElements();
6253 // There is no blend with immediate in AVX-512.
6254 if (VT.is512BitVector())
6257 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
6259 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
6262 // Check the mask for BLEND and build the value.
6263 unsigned MaskValue = 0;
6264 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
6265 unsigned NumLanes = (NumElems-1)/8 + 1;
6266 unsigned NumElemsInLane = NumElems / NumLanes;
6268 // Blend for v16i16 should be symetric for the both lanes.
6269 for (unsigned i = 0; i < NumElemsInLane; ++i) {
6271 int SndLaneEltIdx = (NumLanes == 2) ?
6272 SVOp->getMaskElt(i + NumElemsInLane) : -1;
6273 int EltIdx = SVOp->getMaskElt(i);
6275 if ((EltIdx < 0 || EltIdx == (int)i) &&
6276 (SndLaneEltIdx < 0 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
6279 if (((unsigned)EltIdx == (i + NumElems)) &&
6280 (SndLaneEltIdx < 0 ||
6281 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
6282 MaskValue |= (1<<i);
6287 // Convert i32 vectors to floating point if it is not AVX2.
6288 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
6290 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
6291 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
6293 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
6294 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
6297 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
6298 DAG.getConstant(MaskValue, MVT::i32));
6299 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
6302 /// In vector type \p VT, return true if the element at index \p InputIdx
6303 /// falls on a different 128-bit lane than \p OutputIdx.
6304 static bool ShuffleCrosses128bitLane(MVT VT, unsigned InputIdx,
6305 unsigned OutputIdx) {
6306 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
6307 return InputIdx * EltSize / 128 != OutputIdx * EltSize / 128;
6310 /// Generate a PSHUFB if possible. Selects elements from \p V1 according to
6311 /// \p MaskVals. MaskVals[OutputIdx] = InputIdx specifies that we want to
6312 /// shuffle the element at InputIdx in V1 to OutputIdx in the result. If \p
6313 /// MaskVals refers to elements outside of \p V1 or is undef (-1), insert a
6315 static SDValue getPSHUFB(ArrayRef<int> MaskVals, SDValue V1, SDLoc &dl,
6316 SelectionDAG &DAG) {
6317 MVT VT = V1.getSimpleValueType();
6318 assert(VT.is128BitVector() || VT.is256BitVector());
6320 MVT EltVT = VT.getVectorElementType();
6321 unsigned EltSizeInBytes = EltVT.getSizeInBits() / 8;
6322 unsigned NumElts = VT.getVectorNumElements();
6324 SmallVector<SDValue, 32> PshufbMask;
6325 for (unsigned OutputIdx = 0; OutputIdx < NumElts; ++OutputIdx) {
6326 int InputIdx = MaskVals[OutputIdx];
6327 unsigned InputByteIdx;
6329 if (InputIdx < 0 || NumElts <= (unsigned)InputIdx)
6330 InputByteIdx = 0x80;
6332 // Cross lane is not allowed.
6333 if (ShuffleCrosses128bitLane(VT, InputIdx, OutputIdx))
6335 InputByteIdx = InputIdx * EltSizeInBytes;
6336 // Index is an byte offset within the 128-bit lane.
6337 InputByteIdx &= 0xf;
6340 for (unsigned j = 0; j < EltSizeInBytes; ++j) {
6341 PshufbMask.push_back(DAG.getConstant(InputByteIdx, MVT::i8));
6342 if (InputByteIdx != 0x80)
6347 MVT ShufVT = MVT::getVectorVT(MVT::i8, PshufbMask.size());
6349 V1 = DAG.getNode(ISD::BITCAST, dl, ShufVT, V1);
6350 return DAG.getNode(X86ISD::PSHUFB, dl, ShufVT, V1,
6351 DAG.getNode(ISD::BUILD_VECTOR, dl, ShufVT,
6352 PshufbMask.data(), PshufbMask.size()));
6355 // v8i16 shuffles - Prefer shuffles in the following order:
6356 // 1. [all] pshuflw, pshufhw, optional move
6357 // 2. [ssse3] 1 x pshufb
6358 // 3. [ssse3] 2 x pshufb + 1 x por
6359 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
6361 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
6362 SelectionDAG &DAG) {
6363 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6364 SDValue V1 = SVOp->getOperand(0);
6365 SDValue V2 = SVOp->getOperand(1);
6367 SmallVector<int, 8> MaskVals;
6369 // Determine if more than 1 of the words in each of the low and high quadwords
6370 // of the result come from the same quadword of one of the two inputs. Undef
6371 // mask values count as coming from any quadword, for better codegen.
6373 // Lo/HiQuad[i] = j indicates how many words from the ith quad of the input
6374 // feeds this quad. For i, 0 and 1 refer to V1, 2 and 3 refer to V2.
6375 unsigned LoQuad[] = { 0, 0, 0, 0 };
6376 unsigned HiQuad[] = { 0, 0, 0, 0 };
6377 // Indices of quads used.
6378 std::bitset<4> InputQuads;
6379 for (unsigned i = 0; i < 8; ++i) {
6380 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
6381 int EltIdx = SVOp->getMaskElt(i);
6382 MaskVals.push_back(EltIdx);
6391 InputQuads.set(EltIdx / 4);
6394 int BestLoQuad = -1;
6395 unsigned MaxQuad = 1;
6396 for (unsigned i = 0; i < 4; ++i) {
6397 if (LoQuad[i] > MaxQuad) {
6399 MaxQuad = LoQuad[i];
6403 int BestHiQuad = -1;
6405 for (unsigned i = 0; i < 4; ++i) {
6406 if (HiQuad[i] > MaxQuad) {
6408 MaxQuad = HiQuad[i];
6412 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
6413 // of the two input vectors, shuffle them into one input vector so only a
6414 // single pshufb instruction is necessary. If there are more than 2 input
6415 // quads, disable the next transformation since it does not help SSSE3.
6416 bool V1Used = InputQuads[0] || InputQuads[1];
6417 bool V2Used = InputQuads[2] || InputQuads[3];
6418 if (Subtarget->hasSSSE3()) {
6419 if (InputQuads.count() == 2 && V1Used && V2Used) {
6420 BestLoQuad = InputQuads[0] ? 0 : 1;
6421 BestHiQuad = InputQuads[2] ? 2 : 3;
6423 if (InputQuads.count() > 2) {
6429 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
6430 // the shuffle mask. If a quad is scored as -1, that means that it contains
6431 // words from all 4 input quadwords.
6433 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
6435 BestLoQuad < 0 ? 0 : BestLoQuad,
6436 BestHiQuad < 0 ? 1 : BestHiQuad
6438 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
6439 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
6440 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
6441 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
6443 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
6444 // source words for the shuffle, to aid later transformations.
6445 bool AllWordsInNewV = true;
6446 bool InOrder[2] = { true, true };
6447 for (unsigned i = 0; i != 8; ++i) {
6448 int idx = MaskVals[i];
6450 InOrder[i/4] = false;
6451 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
6453 AllWordsInNewV = false;
6457 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
6458 if (AllWordsInNewV) {
6459 for (int i = 0; i != 8; ++i) {
6460 int idx = MaskVals[i];
6463 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
6464 if ((idx != i) && idx < 4)
6466 if ((idx != i) && idx > 3)
6475 // If we've eliminated the use of V2, and the new mask is a pshuflw or
6476 // pshufhw, that's as cheap as it gets. Return the new shuffle.
6477 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
6478 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
6479 unsigned TargetMask = 0;
6480 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
6481 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
6482 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
6483 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
6484 getShufflePSHUFLWImmediate(SVOp);
6485 V1 = NewV.getOperand(0);
6486 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
6490 // Promote splats to a larger type which usually leads to more efficient code.
6491 // FIXME: Is this true if pshufb is available?
6492 if (SVOp->isSplat())
6493 return PromoteSplat(SVOp, DAG);
6495 // If we have SSSE3, and all words of the result are from 1 input vector,
6496 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
6497 // is present, fall back to case 4.
6498 if (Subtarget->hasSSSE3()) {
6499 SmallVector<SDValue,16> pshufbMask;
6501 // If we have elements from both input vectors, set the high bit of the
6502 // shuffle mask element to zero out elements that come from V2 in the V1
6503 // mask, and elements that come from V1 in the V2 mask, so that the two
6504 // results can be OR'd together.
6505 bool TwoInputs = V1Used && V2Used;
6506 V1 = getPSHUFB(MaskVals, V1, dl, DAG);
6508 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
6510 // Calculate the shuffle mask for the second input, shuffle it, and
6511 // OR it with the first shuffled input.
6512 CommuteVectorShuffleMask(MaskVals, 8);
6513 V2 = getPSHUFB(MaskVals, V2, dl, DAG);
6514 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
6515 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
6518 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
6519 // and update MaskVals with new element order.
6520 std::bitset<8> InOrder;
6521 if (BestLoQuad >= 0) {
6522 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
6523 for (int i = 0; i != 4; ++i) {
6524 int idx = MaskVals[i];
6527 } else if ((idx / 4) == BestLoQuad) {
6532 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
6535 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
6536 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
6537 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
6539 getShufflePSHUFLWImmediate(SVOp), DAG);
6543 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
6544 // and update MaskVals with the new element order.
6545 if (BestHiQuad >= 0) {
6546 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
6547 for (unsigned i = 4; i != 8; ++i) {
6548 int idx = MaskVals[i];
6551 } else if ((idx / 4) == BestHiQuad) {
6552 MaskV[i] = (idx & 3) + 4;
6556 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
6559 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
6560 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
6561 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
6563 getShufflePSHUFHWImmediate(SVOp), DAG);
6567 // In case BestHi & BestLo were both -1, which means each quadword has a word
6568 // from each of the four input quadwords, calculate the InOrder bitvector now
6569 // before falling through to the insert/extract cleanup.
6570 if (BestLoQuad == -1 && BestHiQuad == -1) {
6572 for (int i = 0; i != 8; ++i)
6573 if (MaskVals[i] < 0 || MaskVals[i] == i)
6577 // The other elements are put in the right place using pextrw and pinsrw.
6578 for (unsigned i = 0; i != 8; ++i) {
6581 int EltIdx = MaskVals[i];
6584 SDValue ExtOp = (EltIdx < 8) ?
6585 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
6586 DAG.getIntPtrConstant(EltIdx)) :
6587 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
6588 DAG.getIntPtrConstant(EltIdx - 8));
6589 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
6590 DAG.getIntPtrConstant(i));
6595 /// \brief v16i16 shuffles
6597 /// FIXME: We only support generation of a single pshufb currently. We can
6598 /// generalize the other applicable cases from LowerVECTOR_SHUFFLEv8i16 as
6599 /// well (e.g 2 x pshufb + 1 x por).
6601 LowerVECTOR_SHUFFLEv16i16(SDValue Op, SelectionDAG &DAG) {
6602 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6603 SDValue V1 = SVOp->getOperand(0);
6604 SDValue V2 = SVOp->getOperand(1);
6607 if (V2.getOpcode() != ISD::UNDEF)
6610 SmallVector<int, 16> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
6611 return getPSHUFB(MaskVals, V1, dl, DAG);
6614 // v16i8 shuffles - Prefer shuffles in the following order:
6615 // 1. [ssse3] 1 x pshufb
6616 // 2. [ssse3] 2 x pshufb + 1 x por
6617 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
6618 static SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
6619 const X86Subtarget* Subtarget,
6620 SelectionDAG &DAG) {
6621 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6622 SDValue V1 = SVOp->getOperand(0);
6623 SDValue V2 = SVOp->getOperand(1);
6625 ArrayRef<int> MaskVals = SVOp->getMask();
6627 // Promote splats to a larger type which usually leads to more efficient code.
6628 // FIXME: Is this true if pshufb is available?
6629 if (SVOp->isSplat())
6630 return PromoteSplat(SVOp, DAG);
6632 // If we have SSSE3, case 1 is generated when all result bytes come from
6633 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
6634 // present, fall back to case 3.
6636 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
6637 if (Subtarget->hasSSSE3()) {
6638 SmallVector<SDValue,16> pshufbMask;
6640 // If all result elements are from one input vector, then only translate
6641 // undef mask values to 0x80 (zero out result) in the pshufb mask.
6643 // Otherwise, we have elements from both input vectors, and must zero out
6644 // elements that come from V2 in the first mask, and V1 in the second mask
6645 // so that we can OR them together.
6646 for (unsigned i = 0; i != 16; ++i) {
6647 int EltIdx = MaskVals[i];
6648 if (EltIdx < 0 || EltIdx >= 16)
6650 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
6652 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
6653 DAG.getNode(ISD::BUILD_VECTOR, dl,
6654 MVT::v16i8, &pshufbMask[0], 16));
6656 // As PSHUFB will zero elements with negative indices, it's safe to ignore
6657 // the 2nd operand if it's undefined or zero.
6658 if (V2.getOpcode() == ISD::UNDEF ||
6659 ISD::isBuildVectorAllZeros(V2.getNode()))
6662 // Calculate the shuffle mask for the second input, shuffle it, and
6663 // OR it with the first shuffled input.
6665 for (unsigned i = 0; i != 16; ++i) {
6666 int EltIdx = MaskVals[i];
6667 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
6668 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
6670 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
6671 DAG.getNode(ISD::BUILD_VECTOR, dl,
6672 MVT::v16i8, &pshufbMask[0], 16));
6673 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
6676 // No SSSE3 - Calculate in place words and then fix all out of place words
6677 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
6678 // the 16 different words that comprise the two doublequadword input vectors.
6679 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
6680 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
6682 for (int i = 0; i != 8; ++i) {
6683 int Elt0 = MaskVals[i*2];
6684 int Elt1 = MaskVals[i*2+1];
6686 // This word of the result is all undef, skip it.
6687 if (Elt0 < 0 && Elt1 < 0)
6690 // This word of the result is already in the correct place, skip it.
6691 if ((Elt0 == i*2) && (Elt1 == i*2+1))
6694 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
6695 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
6698 // If Elt0 and Elt1 are defined, are consecutive, and can be load
6699 // using a single extract together, load it and store it.
6700 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
6701 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
6702 DAG.getIntPtrConstant(Elt1 / 2));
6703 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
6704 DAG.getIntPtrConstant(i));
6708 // If Elt1 is defined, extract it from the appropriate source. If the
6709 // source byte is not also odd, shift the extracted word left 8 bits
6710 // otherwise clear the bottom 8 bits if we need to do an or.
6712 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
6713 DAG.getIntPtrConstant(Elt1 / 2));
6714 if ((Elt1 & 1) == 0)
6715 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
6717 TLI.getShiftAmountTy(InsElt.getValueType())));
6719 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
6720 DAG.getConstant(0xFF00, MVT::i16));
6722 // If Elt0 is defined, extract it from the appropriate source. If the
6723 // source byte is not also even, shift the extracted word right 8 bits. If
6724 // Elt1 was also defined, OR the extracted values together before
6725 // inserting them in the result.
6727 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
6728 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
6729 if ((Elt0 & 1) != 0)
6730 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
6732 TLI.getShiftAmountTy(InsElt0.getValueType())));
6734 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
6735 DAG.getConstant(0x00FF, MVT::i16));
6736 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
6739 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
6740 DAG.getIntPtrConstant(i));
6742 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
6745 // v32i8 shuffles - Translate to VPSHUFB if possible.
6747 SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
6748 const X86Subtarget *Subtarget,
6749 SelectionDAG &DAG) {
6750 MVT VT = SVOp->getSimpleValueType(0);
6751 SDValue V1 = SVOp->getOperand(0);
6752 SDValue V2 = SVOp->getOperand(1);
6754 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
6756 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
6757 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
6758 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
6760 // VPSHUFB may be generated if
6761 // (1) one of input vector is undefined or zeroinitializer.
6762 // The mask value 0x80 puts 0 in the corresponding slot of the vector.
6763 // And (2) the mask indexes don't cross the 128-bit lane.
6764 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
6765 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
6768 if (V1IsAllZero && !V2IsAllZero) {
6769 CommuteVectorShuffleMask(MaskVals, 32);
6772 return getPSHUFB(MaskVals, V1, dl, DAG);
6775 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
6776 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
6777 /// done when every pair / quad of shuffle mask elements point to elements in
6778 /// the right sequence. e.g.
6779 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
6781 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
6782 SelectionDAG &DAG) {
6783 MVT VT = SVOp->getSimpleValueType(0);
6785 unsigned NumElems = VT.getVectorNumElements();
6788 switch (VT.SimpleTy) {
6789 default: llvm_unreachable("Unexpected!");
6790 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
6791 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
6792 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
6793 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
6794 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
6795 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
6798 SmallVector<int, 8> MaskVec;
6799 for (unsigned i = 0; i != NumElems; i += Scale) {
6801 for (unsigned j = 0; j != Scale; ++j) {
6802 int EltIdx = SVOp->getMaskElt(i+j);
6806 StartIdx = (EltIdx / Scale);
6807 if (EltIdx != (int)(StartIdx*Scale + j))
6810 MaskVec.push_back(StartIdx);
6813 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
6814 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
6815 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
6818 /// getVZextMovL - Return a zero-extending vector move low node.
6820 static SDValue getVZextMovL(MVT VT, MVT OpVT,
6821 SDValue SrcOp, SelectionDAG &DAG,
6822 const X86Subtarget *Subtarget, SDLoc dl) {
6823 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
6824 LoadSDNode *LD = NULL;
6825 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
6826 LD = dyn_cast<LoadSDNode>(SrcOp);
6828 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
6830 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
6831 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
6832 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
6833 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
6834 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
6836 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
6837 return DAG.getNode(ISD::BITCAST, dl, VT,
6838 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
6839 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6847 return DAG.getNode(ISD::BITCAST, dl, VT,
6848 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
6849 DAG.getNode(ISD::BITCAST, dl,
6853 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
6854 /// which could not be matched by any known target speficic shuffle
6856 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
6858 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
6859 if (NewOp.getNode())
6862 MVT VT = SVOp->getSimpleValueType(0);
6864 unsigned NumElems = VT.getVectorNumElements();
6865 unsigned NumLaneElems = NumElems / 2;
6868 MVT EltVT = VT.getVectorElementType();
6869 MVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
6872 SmallVector<int, 16> Mask;
6873 for (unsigned l = 0; l < 2; ++l) {
6874 // Build a shuffle mask for the output, discovering on the fly which
6875 // input vectors to use as shuffle operands (recorded in InputUsed).
6876 // If building a suitable shuffle vector proves too hard, then bail
6877 // out with UseBuildVector set.
6878 bool UseBuildVector = false;
6879 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
6880 unsigned LaneStart = l * NumLaneElems;
6881 for (unsigned i = 0; i != NumLaneElems; ++i) {
6882 // The mask element. This indexes into the input.
6883 int Idx = SVOp->getMaskElt(i+LaneStart);
6885 // the mask element does not index into any input vector.
6890 // The input vector this mask element indexes into.
6891 int Input = Idx / NumLaneElems;
6893 // Turn the index into an offset from the start of the input vector.
6894 Idx -= Input * NumLaneElems;
6896 // Find or create a shuffle vector operand to hold this input.
6898 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
6899 if (InputUsed[OpNo] == Input)
6900 // This input vector is already an operand.
6902 if (InputUsed[OpNo] < 0) {
6903 // Create a new operand for this input vector.
6904 InputUsed[OpNo] = Input;
6909 if (OpNo >= array_lengthof(InputUsed)) {
6910 // More than two input vectors used! Give up on trying to create a
6911 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
6912 UseBuildVector = true;
6916 // Add the mask index for the new shuffle vector.
6917 Mask.push_back(Idx + OpNo * NumLaneElems);
6920 if (UseBuildVector) {
6921 SmallVector<SDValue, 16> SVOps;
6922 for (unsigned i = 0; i != NumLaneElems; ++i) {
6923 // The mask element. This indexes into the input.
6924 int Idx = SVOp->getMaskElt(i+LaneStart);
6926 SVOps.push_back(DAG.getUNDEF(EltVT));
6930 // The input vector this mask element indexes into.
6931 int Input = Idx / NumElems;
6933 // Turn the index into an offset from the start of the input vector.
6934 Idx -= Input * NumElems;
6936 // Extract the vector element by hand.
6937 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
6938 SVOp->getOperand(Input),
6939 DAG.getIntPtrConstant(Idx)));
6942 // Construct the output using a BUILD_VECTOR.
6943 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, &SVOps[0],
6945 } else if (InputUsed[0] < 0) {
6946 // No input vectors were used! The result is undefined.
6947 Output[l] = DAG.getUNDEF(NVT);
6949 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
6950 (InputUsed[0] % 2) * NumLaneElems,
6952 // If only one input was used, use an undefined vector for the other.
6953 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
6954 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
6955 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
6956 // At least one input vector was used. Create a new shuffle vector.
6957 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
6963 // Concatenate the result back
6964 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
6967 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
6968 /// 4 elements, and match them with several different shuffle types.
6970 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
6971 SDValue V1 = SVOp->getOperand(0);
6972 SDValue V2 = SVOp->getOperand(1);
6974 MVT VT = SVOp->getSimpleValueType(0);
6976 assert(VT.is128BitVector() && "Unsupported vector size");
6978 std::pair<int, int> Locs[4];
6979 int Mask1[] = { -1, -1, -1, -1 };
6980 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
6984 for (unsigned i = 0; i != 4; ++i) {
6985 int Idx = PermMask[i];
6987 Locs[i] = std::make_pair(-1, -1);
6989 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
6991 Locs[i] = std::make_pair(0, NumLo);
6995 Locs[i] = std::make_pair(1, NumHi);
6997 Mask1[2+NumHi] = Idx;
7003 if (NumLo <= 2 && NumHi <= 2) {
7004 // If no more than two elements come from either vector. This can be
7005 // implemented with two shuffles. First shuffle gather the elements.
7006 // The second shuffle, which takes the first shuffle as both of its
7007 // vector operands, put the elements into the right order.
7008 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
7010 int Mask2[] = { -1, -1, -1, -1 };
7012 for (unsigned i = 0; i != 4; ++i)
7013 if (Locs[i].first != -1) {
7014 unsigned Idx = (i < 2) ? 0 : 4;
7015 Idx += Locs[i].first * 2 + Locs[i].second;
7019 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
7022 if (NumLo == 3 || NumHi == 3) {
7023 // Otherwise, we must have three elements from one vector, call it X, and
7024 // one element from the other, call it Y. First, use a shufps to build an
7025 // intermediate vector with the one element from Y and the element from X
7026 // that will be in the same half in the final destination (the indexes don't
7027 // matter). Then, use a shufps to build the final vector, taking the half
7028 // containing the element from Y from the intermediate, and the other half
7031 // Normalize it so the 3 elements come from V1.
7032 CommuteVectorShuffleMask(PermMask, 4);
7036 // Find the element from V2.
7038 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
7039 int Val = PermMask[HiIndex];
7046 Mask1[0] = PermMask[HiIndex];
7048 Mask1[2] = PermMask[HiIndex^1];
7050 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
7053 Mask1[0] = PermMask[0];
7054 Mask1[1] = PermMask[1];
7055 Mask1[2] = HiIndex & 1 ? 6 : 4;
7056 Mask1[3] = HiIndex & 1 ? 4 : 6;
7057 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
7060 Mask1[0] = HiIndex & 1 ? 2 : 0;
7061 Mask1[1] = HiIndex & 1 ? 0 : 2;
7062 Mask1[2] = PermMask[2];
7063 Mask1[3] = PermMask[3];
7068 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
7071 // Break it into (shuffle shuffle_hi, shuffle_lo).
7072 int LoMask[] = { -1, -1, -1, -1 };
7073 int HiMask[] = { -1, -1, -1, -1 };
7075 int *MaskPtr = LoMask;
7076 unsigned MaskIdx = 0;
7079 for (unsigned i = 0; i != 4; ++i) {
7086 int Idx = PermMask[i];
7088 Locs[i] = std::make_pair(-1, -1);
7089 } else if (Idx < 4) {
7090 Locs[i] = std::make_pair(MaskIdx, LoIdx);
7091 MaskPtr[LoIdx] = Idx;
7094 Locs[i] = std::make_pair(MaskIdx, HiIdx);
7095 MaskPtr[HiIdx] = Idx;
7100 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
7101 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
7102 int MaskOps[] = { -1, -1, -1, -1 };
7103 for (unsigned i = 0; i != 4; ++i)
7104 if (Locs[i].first != -1)
7105 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
7106 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
7109 static bool MayFoldVectorLoad(SDValue V) {
7110 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
7111 V = V.getOperand(0);
7113 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
7114 V = V.getOperand(0);
7115 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
7116 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
7117 // BUILD_VECTOR (load), undef
7118 V = V.getOperand(0);
7120 return MayFoldLoad(V);
7124 SDValue getMOVDDup(SDValue &Op, SDLoc &dl, SDValue V1, SelectionDAG &DAG) {
7125 MVT VT = Op.getSimpleValueType();
7127 // Canonizalize to v2f64.
7128 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
7129 return DAG.getNode(ISD::BITCAST, dl, VT,
7130 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
7135 SDValue getMOVLowToHigh(SDValue &Op, SDLoc &dl, SelectionDAG &DAG,
7137 SDValue V1 = Op.getOperand(0);
7138 SDValue V2 = Op.getOperand(1);
7139 MVT VT = Op.getSimpleValueType();
7141 assert(VT != MVT::v2i64 && "unsupported shuffle type");
7143 if (HasSSE2 && VT == MVT::v2f64)
7144 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
7146 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
7147 return DAG.getNode(ISD::BITCAST, dl, VT,
7148 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
7149 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
7150 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
7154 SDValue getMOVHighToLow(SDValue &Op, SDLoc &dl, SelectionDAG &DAG) {
7155 SDValue V1 = Op.getOperand(0);
7156 SDValue V2 = Op.getOperand(1);
7157 MVT VT = Op.getSimpleValueType();
7159 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
7160 "unsupported shuffle type");
7162 if (V2.getOpcode() == ISD::UNDEF)
7166 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
7170 SDValue getMOVLP(SDValue &Op, SDLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
7171 SDValue V1 = Op.getOperand(0);
7172 SDValue V2 = Op.getOperand(1);
7173 MVT VT = Op.getSimpleValueType();
7174 unsigned NumElems = VT.getVectorNumElements();
7176 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
7177 // operand of these instructions is only memory, so check if there's a
7178 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
7180 bool CanFoldLoad = false;
7182 // Trivial case, when V2 comes from a load.
7183 if (MayFoldVectorLoad(V2))
7186 // When V1 is a load, it can be folded later into a store in isel, example:
7187 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
7189 // (MOVLPSmr addr:$src1, VR128:$src2)
7190 // So, recognize this potential and also use MOVLPS or MOVLPD
7191 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
7194 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7196 if (HasSSE2 && NumElems == 2)
7197 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
7200 // If we don't care about the second element, proceed to use movss.
7201 if (SVOp->getMaskElt(1) != -1)
7202 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
7205 // movl and movlp will both match v2i64, but v2i64 is never matched by
7206 // movl earlier because we make it strict to avoid messing with the movlp load
7207 // folding logic (see the code above getMOVLP call). Match it here then,
7208 // this is horrible, but will stay like this until we move all shuffle
7209 // matching to x86 specific nodes. Note that for the 1st condition all
7210 // types are matched with movsd.
7212 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
7213 // as to remove this logic from here, as much as possible
7214 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
7215 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
7216 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
7219 assert(VT != MVT::v4i32 && "unsupported shuffle type");
7221 // Invert the operand order and use SHUFPS to match it.
7222 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
7223 getShuffleSHUFImmediate(SVOp), DAG);
7226 // Reduce a vector shuffle to zext.
7227 static SDValue LowerVectorIntExtend(SDValue Op, const X86Subtarget *Subtarget,
7228 SelectionDAG &DAG) {
7229 // PMOVZX is only available from SSE41.
7230 if (!Subtarget->hasSSE41())
7233 MVT VT = Op.getSimpleValueType();
7235 // Only AVX2 support 256-bit vector integer extending.
7236 if (!Subtarget->hasInt256() && VT.is256BitVector())
7239 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7241 SDValue V1 = Op.getOperand(0);
7242 SDValue V2 = Op.getOperand(1);
7243 unsigned NumElems = VT.getVectorNumElements();
7245 // Extending is an unary operation and the element type of the source vector
7246 // won't be equal to or larger than i64.
7247 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
7248 VT.getVectorElementType() == MVT::i64)
7251 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
7252 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
7253 while ((1U << Shift) < NumElems) {
7254 if (SVOp->getMaskElt(1U << Shift) == 1)
7257 // The maximal ratio is 8, i.e. from i8 to i64.
7262 // Check the shuffle mask.
7263 unsigned Mask = (1U << Shift) - 1;
7264 for (unsigned i = 0; i != NumElems; ++i) {
7265 int EltIdx = SVOp->getMaskElt(i);
7266 if ((i & Mask) != 0 && EltIdx != -1)
7268 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift))
7272 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
7273 MVT NeVT = MVT::getIntegerVT(NBits);
7274 MVT NVT = MVT::getVectorVT(NeVT, NumElems >> Shift);
7276 if (!DAG.getTargetLoweringInfo().isTypeLegal(NVT))
7279 // Simplify the operand as it's prepared to be fed into shuffle.
7280 unsigned SignificantBits = NVT.getSizeInBits() >> Shift;
7281 if (V1.getOpcode() == ISD::BITCAST &&
7282 V1.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
7283 V1.getOperand(0).getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
7284 V1.getOperand(0).getOperand(0)
7285 .getSimpleValueType().getSizeInBits() == SignificantBits) {
7286 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
7287 SDValue V = V1.getOperand(0).getOperand(0).getOperand(0);
7288 ConstantSDNode *CIdx =
7289 dyn_cast<ConstantSDNode>(V1.getOperand(0).getOperand(0).getOperand(1));
7290 // If it's foldable, i.e. normal load with single use, we will let code
7291 // selection to fold it. Otherwise, we will short the conversion sequence.
7292 if (CIdx && CIdx->getZExtValue() == 0 &&
7293 (!ISD::isNormalLoad(V.getNode()) || !V.hasOneUse())) {
7294 MVT FullVT = V.getSimpleValueType();
7295 MVT V1VT = V1.getSimpleValueType();
7296 if (FullVT.getSizeInBits() > V1VT.getSizeInBits()) {
7297 // The "ext_vec_elt" node is wider than the result node.
7298 // In this case we should extract subvector from V.
7299 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast (extract_subvector x)).
7300 unsigned Ratio = FullVT.getSizeInBits() / V1VT.getSizeInBits();
7301 MVT SubVecVT = MVT::getVectorVT(FullVT.getVectorElementType(),
7302 FullVT.getVectorNumElements()/Ratio);
7303 V = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVecVT, V,
7304 DAG.getIntPtrConstant(0));
7306 V1 = DAG.getNode(ISD::BITCAST, DL, V1VT, V);
7310 return DAG.getNode(ISD::BITCAST, DL, VT,
7311 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
7315 NormalizeVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
7316 SelectionDAG &DAG) {
7317 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7318 MVT VT = Op.getSimpleValueType();
7320 SDValue V1 = Op.getOperand(0);
7321 SDValue V2 = Op.getOperand(1);
7323 if (isZeroShuffle(SVOp))
7324 return getZeroVector(VT, Subtarget, DAG, dl);
7326 // Handle splat operations
7327 if (SVOp->isSplat()) {
7328 // Use vbroadcast whenever the splat comes from a foldable load
7329 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
7330 if (Broadcast.getNode())
7334 // Check integer expanding shuffles.
7335 SDValue NewOp = LowerVectorIntExtend(Op, Subtarget, DAG);
7336 if (NewOp.getNode())
7339 // If the shuffle can be profitably rewritten as a narrower shuffle, then
7341 if (VT == MVT::v8i16 || VT == MVT::v16i8 ||
7342 VT == MVT::v16i16 || VT == MVT::v32i8) {
7343 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
7344 if (NewOp.getNode())
7345 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
7346 } else if ((VT == MVT::v4i32 ||
7347 (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
7348 // FIXME: Figure out a cleaner way to do this.
7349 // Try to make use of movq to zero out the top part.
7350 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
7351 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
7352 if (NewOp.getNode()) {
7353 MVT NewVT = NewOp.getSimpleValueType();
7354 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
7355 NewVT, true, false))
7356 return getVZextMovL(VT, NewVT, NewOp.getOperand(0),
7357 DAG, Subtarget, dl);
7359 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
7360 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
7361 if (NewOp.getNode()) {
7362 MVT NewVT = NewOp.getSimpleValueType();
7363 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
7364 return getVZextMovL(VT, NewVT, NewOp.getOperand(1),
7365 DAG, Subtarget, dl);
7373 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
7374 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7375 SDValue V1 = Op.getOperand(0);
7376 SDValue V2 = Op.getOperand(1);
7377 MVT VT = Op.getSimpleValueType();
7379 unsigned NumElems = VT.getVectorNumElements();
7380 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
7381 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
7382 bool V1IsSplat = false;
7383 bool V2IsSplat = false;
7384 bool HasSSE2 = Subtarget->hasSSE2();
7385 bool HasFp256 = Subtarget->hasFp256();
7386 bool HasInt256 = Subtarget->hasInt256();
7387 MachineFunction &MF = DAG.getMachineFunction();
7388 bool OptForSize = MF.getFunction()->getAttributes().
7389 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
7391 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
7393 if (V1IsUndef && V2IsUndef)
7394 return DAG.getUNDEF(VT);
7396 // When we create a shuffle node we put the UNDEF node to second operand,
7397 // but in some cases the first operand may be transformed to UNDEF.
7398 // In this case we should just commute the node.
7400 return CommuteVectorShuffle(SVOp, DAG);
7402 // Vector shuffle lowering takes 3 steps:
7404 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
7405 // narrowing and commutation of operands should be handled.
7406 // 2) Matching of shuffles with known shuffle masks to x86 target specific
7408 // 3) Rewriting of unmatched masks into new generic shuffle operations,
7409 // so the shuffle can be broken into other shuffles and the legalizer can
7410 // try the lowering again.
7412 // The general idea is that no vector_shuffle operation should be left to
7413 // be matched during isel, all of them must be converted to a target specific
7416 // Normalize the input vectors. Here splats, zeroed vectors, profitable
7417 // narrowing and commutation of operands should be handled. The actual code
7418 // doesn't include all of those, work in progress...
7419 SDValue NewOp = NormalizeVectorShuffle(Op, Subtarget, DAG);
7420 if (NewOp.getNode())
7423 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
7425 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
7426 // unpckh_undef). Only use pshufd if speed is more important than size.
7427 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
7428 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
7429 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
7430 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
7432 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
7433 V2IsUndef && MayFoldVectorLoad(V1))
7434 return getMOVDDup(Op, dl, V1, DAG);
7436 if (isMOVHLPS_v_undef_Mask(M, VT))
7437 return getMOVHighToLow(Op, dl, DAG);
7439 // Use to match splats
7440 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
7441 (VT == MVT::v2f64 || VT == MVT::v2i64))
7442 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
7444 if (isPSHUFDMask(M, VT)) {
7445 // The actual implementation will match the mask in the if above and then
7446 // during isel it can match several different instructions, not only pshufd
7447 // as its name says, sad but true, emulate the behavior for now...
7448 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
7449 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
7451 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
7453 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
7454 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
7456 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
7457 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, TargetMask,
7460 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
7464 if (isPALIGNRMask(M, VT, Subtarget))
7465 return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
7466 getShufflePALIGNRImmediate(SVOp),
7469 // Check if this can be converted into a logical shift.
7470 bool isLeft = false;
7473 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
7474 if (isShift && ShVal.hasOneUse()) {
7475 // If the shifted value has multiple uses, it may be cheaper to use
7476 // v_set0 + movlhps or movhlps, etc.
7477 MVT EltVT = VT.getVectorElementType();
7478 ShAmt *= EltVT.getSizeInBits();
7479 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
7482 if (isMOVLMask(M, VT)) {
7483 if (ISD::isBuildVectorAllZeros(V1.getNode()))
7484 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
7485 if (!isMOVLPMask(M, VT)) {
7486 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
7487 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
7489 if (VT == MVT::v4i32 || VT == MVT::v4f32)
7490 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
7494 // FIXME: fold these into legal mask.
7495 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
7496 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
7498 if (isMOVHLPSMask(M, VT))
7499 return getMOVHighToLow(Op, dl, DAG);
7501 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
7502 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
7504 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
7505 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
7507 if (isMOVLPMask(M, VT))
7508 return getMOVLP(Op, dl, DAG, HasSSE2);
7510 if (ShouldXformToMOVHLPS(M, VT) ||
7511 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
7512 return CommuteVectorShuffle(SVOp, DAG);
7515 // No better options. Use a vshldq / vsrldq.
7516 MVT EltVT = VT.getVectorElementType();
7517 ShAmt *= EltVT.getSizeInBits();
7518 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
7521 bool Commuted = false;
7522 // FIXME: This should also accept a bitcast of a splat? Be careful, not
7523 // 1,1,1,1 -> v8i16 though.
7524 V1IsSplat = isSplatVector(V1.getNode());
7525 V2IsSplat = isSplatVector(V2.getNode());
7527 // Canonicalize the splat or undef, if present, to be on the RHS.
7528 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
7529 CommuteVectorShuffleMask(M, NumElems);
7531 std::swap(V1IsSplat, V2IsSplat);
7535 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
7536 // Shuffling low element of v1 into undef, just return v1.
7539 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
7540 // the instruction selector will not match, so get a canonical MOVL with
7541 // swapped operands to undo the commute.
7542 return getMOVL(DAG, dl, VT, V2, V1);
7545 if (isUNPCKLMask(M, VT, HasInt256))
7546 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
7548 if (isUNPCKHMask(M, VT, HasInt256))
7549 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
7552 // Normalize mask so all entries that point to V2 points to its first
7553 // element then try to match unpck{h|l} again. If match, return a
7554 // new vector_shuffle with the corrected mask.p
7555 SmallVector<int, 8> NewMask(M.begin(), M.end());
7556 NormalizeMask(NewMask, NumElems);
7557 if (isUNPCKLMask(NewMask, VT, HasInt256, true))
7558 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
7559 if (isUNPCKHMask(NewMask, VT, HasInt256, true))
7560 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
7564 // Commute is back and try unpck* again.
7565 // FIXME: this seems wrong.
7566 CommuteVectorShuffleMask(M, NumElems);
7568 std::swap(V1IsSplat, V2IsSplat);
7570 if (isUNPCKLMask(M, VT, HasInt256))
7571 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
7573 if (isUNPCKHMask(M, VT, HasInt256))
7574 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
7577 // Normalize the node to match x86 shuffle ops if needed
7578 if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true)))
7579 return CommuteVectorShuffle(SVOp, DAG);
7581 // The checks below are all present in isShuffleMaskLegal, but they are
7582 // inlined here right now to enable us to directly emit target specific
7583 // nodes, and remove one by one until they don't return Op anymore.
7585 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
7586 SVOp->getSplatIndex() == 0 && V2IsUndef) {
7587 if (VT == MVT::v2f64 || VT == MVT::v2i64)
7588 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
7591 if (isPSHUFHWMask(M, VT, HasInt256))
7592 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
7593 getShufflePSHUFHWImmediate(SVOp),
7596 if (isPSHUFLWMask(M, VT, HasInt256))
7597 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
7598 getShufflePSHUFLWImmediate(SVOp),
7601 if (isSHUFPMask(M, VT))
7602 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
7603 getShuffleSHUFImmediate(SVOp), DAG);
7605 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
7606 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
7607 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
7608 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
7610 //===--------------------------------------------------------------------===//
7611 // Generate target specific nodes for 128 or 256-bit shuffles only
7612 // supported in the AVX instruction set.
7615 // Handle VMOVDDUPY permutations
7616 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
7617 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
7619 // Handle VPERMILPS/D* permutations
7620 if (isVPERMILPMask(M, VT)) {
7621 if ((HasInt256 && VT == MVT::v8i32) || VT == MVT::v16i32)
7622 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
7623 getShuffleSHUFImmediate(SVOp), DAG);
7624 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1,
7625 getShuffleSHUFImmediate(SVOp), DAG);
7628 // Handle VPERM2F128/VPERM2I128 permutations
7629 if (isVPERM2X128Mask(M, VT, HasFp256))
7630 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
7631 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
7633 SDValue BlendOp = LowerVECTOR_SHUFFLEtoBlend(SVOp, Subtarget, DAG);
7634 if (BlendOp.getNode())
7638 if (V2IsUndef && HasInt256 && isPermImmMask(M, VT, Imm8))
7639 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, Imm8, DAG);
7641 if ((V2IsUndef && HasInt256 && VT.is256BitVector() && NumElems == 8) ||
7642 VT.is512BitVector()) {
7643 MVT MaskEltVT = MVT::getIntegerVT(VT.getVectorElementType().getSizeInBits());
7644 MVT MaskVectorVT = MVT::getVectorVT(MaskEltVT, NumElems);
7645 SmallVector<SDValue, 16> permclMask;
7646 for (unsigned i = 0; i != NumElems; ++i) {
7647 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MaskEltVT));
7650 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVectorVT,
7651 &permclMask[0], NumElems);
7653 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
7654 return DAG.getNode(X86ISD::VPERMV, dl, VT,
7655 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
7656 return DAG.getNode(X86ISD::VPERMV3, dl, VT, V1,
7657 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V2);
7660 //===--------------------------------------------------------------------===//
7661 // Since no target specific shuffle was selected for this generic one,
7662 // lower it into other known shuffles. FIXME: this isn't true yet, but
7663 // this is the plan.
7666 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
7667 if (VT == MVT::v8i16) {
7668 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
7669 if (NewOp.getNode())
7673 if (VT == MVT::v16i16 && Subtarget->hasInt256()) {
7674 SDValue NewOp = LowerVECTOR_SHUFFLEv16i16(Op, DAG);
7675 if (NewOp.getNode())
7679 if (VT == MVT::v16i8) {
7680 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, Subtarget, DAG);
7681 if (NewOp.getNode())
7685 if (VT == MVT::v32i8) {
7686 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
7687 if (NewOp.getNode())
7691 // Handle all 128-bit wide vectors with 4 elements, and match them with
7692 // several different shuffle types.
7693 if (NumElems == 4 && VT.is128BitVector())
7694 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
7696 // Handle general 256-bit shuffles
7697 if (VT.is256BitVector())
7698 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
7703 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
7704 MVT VT = Op.getSimpleValueType();
7707 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
7710 if (VT.getSizeInBits() == 8) {
7711 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
7712 Op.getOperand(0), Op.getOperand(1));
7713 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
7714 DAG.getValueType(VT));
7715 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
7718 if (VT.getSizeInBits() == 16) {
7719 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7720 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
7722 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
7723 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
7724 DAG.getNode(ISD::BITCAST, dl,
7728 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
7729 Op.getOperand(0), Op.getOperand(1));
7730 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
7731 DAG.getValueType(VT));
7732 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
7735 if (VT == MVT::f32) {
7736 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
7737 // the result back to FR32 register. It's only worth matching if the
7738 // result has a single use which is a store or a bitcast to i32. And in
7739 // the case of a store, it's not worth it if the index is a constant 0,
7740 // because a MOVSSmr can be used instead, which is smaller and faster.
7741 if (!Op.hasOneUse())
7743 SDNode *User = *Op.getNode()->use_begin();
7744 if ((User->getOpcode() != ISD::STORE ||
7745 (isa<ConstantSDNode>(Op.getOperand(1)) &&
7746 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
7747 (User->getOpcode() != ISD::BITCAST ||
7748 User->getValueType(0) != MVT::i32))
7750 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
7751 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
7754 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
7757 if (VT == MVT::i32 || VT == MVT::i64) {
7758 // ExtractPS/pextrq works with constant index.
7759 if (isa<ConstantSDNode>(Op.getOperand(1)))
7765 /// Extract one bit from mask vector, like v16i1 or v8i1.
7766 /// AVX-512 feature.
7768 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
7769 SDValue Vec = Op.getOperand(0);
7771 MVT VecVT = Vec.getSimpleValueType();
7772 SDValue Idx = Op.getOperand(1);
7773 MVT EltVT = Op.getSimpleValueType();
7775 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
7777 // variable index can't be handled in mask registers,
7778 // extend vector to VR512
7779 if (!isa<ConstantSDNode>(Idx)) {
7780 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
7781 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
7782 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
7783 ExtVT.getVectorElementType(), Ext, Idx);
7784 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
7787 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7788 const TargetRegisterClass* rc = getRegClassFor(VecVT);
7789 unsigned MaxSift = rc->getSize()*8 - 1;
7790 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
7791 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
7792 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
7793 DAG.getConstant(MaxSift, MVT::i8));
7794 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
7795 DAG.getIntPtrConstant(0));
7799 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
7800 SelectionDAG &DAG) const {
7802 SDValue Vec = Op.getOperand(0);
7803 MVT VecVT = Vec.getSimpleValueType();
7804 SDValue Idx = Op.getOperand(1);
7806 if (Op.getSimpleValueType() == MVT::i1)
7807 return ExtractBitFromMaskVector(Op, DAG);
7809 if (!isa<ConstantSDNode>(Idx)) {
7810 if (VecVT.is512BitVector() ||
7811 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
7812 VecVT.getVectorElementType().getSizeInBits() == 32)) {
7815 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
7816 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
7817 MaskEltVT.getSizeInBits());
7819 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
7820 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
7821 getZeroVector(MaskVT, Subtarget, DAG, dl),
7822 Idx, DAG.getConstant(0, getPointerTy()));
7823 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
7824 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
7825 Perm, DAG.getConstant(0, getPointerTy()));
7830 // If this is a 256-bit vector result, first extract the 128-bit vector and
7831 // then extract the element from the 128-bit vector.
7832 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
7834 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7835 // Get the 128-bit vector.
7836 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
7837 MVT EltVT = VecVT.getVectorElementType();
7839 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
7841 //if (IdxVal >= NumElems/2)
7842 // IdxVal -= NumElems/2;
7843 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
7844 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
7845 DAG.getConstant(IdxVal, MVT::i32));
7848 assert(VecVT.is128BitVector() && "Unexpected vector length");
7850 if (Subtarget->hasSSE41()) {
7851 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
7856 MVT VT = Op.getSimpleValueType();
7857 // TODO: handle v16i8.
7858 if (VT.getSizeInBits() == 16) {
7859 SDValue Vec = Op.getOperand(0);
7860 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7862 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
7863 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
7864 DAG.getNode(ISD::BITCAST, dl,
7867 // Transform it so it match pextrw which produces a 32-bit result.
7868 MVT EltVT = MVT::i32;
7869 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
7870 Op.getOperand(0), Op.getOperand(1));
7871 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
7872 DAG.getValueType(VT));
7873 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
7876 if (VT.getSizeInBits() == 32) {
7877 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7881 // SHUFPS the element to the lowest double word, then movss.
7882 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
7883 MVT VVT = Op.getOperand(0).getSimpleValueType();
7884 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
7885 DAG.getUNDEF(VVT), Mask);
7886 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
7887 DAG.getIntPtrConstant(0));
7890 if (VT.getSizeInBits() == 64) {
7891 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
7892 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
7893 // to match extract_elt for f64.
7894 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7898 // UNPCKHPD the element to the lowest double word, then movsd.
7899 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
7900 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
7901 int Mask[2] = { 1, -1 };
7902 MVT VVT = Op.getOperand(0).getSimpleValueType();
7903 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
7904 DAG.getUNDEF(VVT), Mask);
7905 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
7906 DAG.getIntPtrConstant(0));
7912 static SDValue LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
7913 MVT VT = Op.getSimpleValueType();
7914 MVT EltVT = VT.getVectorElementType();
7917 SDValue N0 = Op.getOperand(0);
7918 SDValue N1 = Op.getOperand(1);
7919 SDValue N2 = Op.getOperand(2);
7921 if (!VT.is128BitVector())
7924 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
7925 isa<ConstantSDNode>(N2)) {
7927 if (VT == MVT::v8i16)
7928 Opc = X86ISD::PINSRW;
7929 else if (VT == MVT::v16i8)
7930 Opc = X86ISD::PINSRB;
7932 Opc = X86ISD::PINSRB;
7934 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
7936 if (N1.getValueType() != MVT::i32)
7937 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
7938 if (N2.getValueType() != MVT::i32)
7939 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
7940 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
7943 if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
7944 // Bits [7:6] of the constant are the source select. This will always be
7945 // zero here. The DAG Combiner may combine an extract_elt index into these
7946 // bits. For example (insert (extract, 3), 2) could be matched by putting
7947 // the '3' into bits [7:6] of X86ISD::INSERTPS.
7948 // Bits [5:4] of the constant are the destination select. This is the
7949 // value of the incoming immediate.
7950 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
7951 // combine either bitwise AND or insert of float 0.0 to set these bits.
7952 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
7953 // Create this as a scalar to vector..
7954 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
7955 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
7958 if ((EltVT == MVT::i32 || EltVT == MVT::i64) && isa<ConstantSDNode>(N2)) {
7959 // PINSR* works with constant index.
7965 /// Insert one bit to mask vector, like v16i1 or v8i1.
7966 /// AVX-512 feature.
7968 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
7970 SDValue Vec = Op.getOperand(0);
7971 SDValue Elt = Op.getOperand(1);
7972 SDValue Idx = Op.getOperand(2);
7973 MVT VecVT = Vec.getSimpleValueType();
7975 if (!isa<ConstantSDNode>(Idx)) {
7976 // Non constant index. Extend source and destination,
7977 // insert element and then truncate the result.
7978 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
7979 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
7980 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
7981 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
7982 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
7983 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
7986 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7987 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
7988 if (Vec.getOpcode() == ISD::UNDEF)
7989 return DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
7990 DAG.getConstant(IdxVal, MVT::i8));
7991 const TargetRegisterClass* rc = getRegClassFor(VecVT);
7992 unsigned MaxSift = rc->getSize()*8 - 1;
7993 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
7994 DAG.getConstant(MaxSift, MVT::i8));
7995 EltInVec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, EltInVec,
7996 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
7997 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
8000 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
8001 MVT VT = Op.getSimpleValueType();
8002 MVT EltVT = VT.getVectorElementType();
8004 if (EltVT == MVT::i1)
8005 return InsertBitToMaskVector(Op, DAG);
8008 SDValue N0 = Op.getOperand(0);
8009 SDValue N1 = Op.getOperand(1);
8010 SDValue N2 = Op.getOperand(2);
8012 // If this is a 256-bit vector result, first extract the 128-bit vector,
8013 // insert the element into the extracted half and then place it back.
8014 if (VT.is256BitVector() || VT.is512BitVector()) {
8015 if (!isa<ConstantSDNode>(N2))
8018 // Get the desired 128-bit vector half.
8019 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue();
8020 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
8022 // Insert the element into the desired half.
8023 unsigned NumEltsIn128 = 128/EltVT.getSizeInBits();
8024 unsigned IdxIn128 = IdxVal - (IdxVal/NumEltsIn128) * NumEltsIn128;
8026 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
8027 DAG.getConstant(IdxIn128, MVT::i32));
8029 // Insert the changed part back to the 256-bit vector
8030 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
8033 if (Subtarget->hasSSE41())
8034 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
8036 if (EltVT == MVT::i8)
8039 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
8040 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
8041 // as its second argument.
8042 if (N1.getValueType() != MVT::i32)
8043 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
8044 if (N2.getValueType() != MVT::i32)
8045 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
8046 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
8051 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
8053 MVT OpVT = Op.getSimpleValueType();
8055 // If this is a 256-bit vector result, first insert into a 128-bit
8056 // vector and then insert into the 256-bit vector.
8057 if (!OpVT.is128BitVector()) {
8058 // Insert into a 128-bit vector.
8059 unsigned SizeFactor = OpVT.getSizeInBits()/128;
8060 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
8061 OpVT.getVectorNumElements() / SizeFactor);
8063 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
8065 // Insert the 128-bit vector.
8066 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
8069 if (OpVT == MVT::v1i64 &&
8070 Op.getOperand(0).getValueType() == MVT::i64)
8071 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
8073 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
8074 assert(OpVT.is128BitVector() && "Expected an SSE type!");
8075 return DAG.getNode(ISD::BITCAST, dl, OpVT,
8076 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
8079 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
8080 // a simple subregister reference or explicit instructions to grab
8081 // upper bits of a vector.
8082 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
8083 SelectionDAG &DAG) {
8085 SDValue In = Op.getOperand(0);
8086 SDValue Idx = Op.getOperand(1);
8087 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
8088 MVT ResVT = Op.getSimpleValueType();
8089 MVT InVT = In.getSimpleValueType();
8091 if (Subtarget->hasFp256()) {
8092 if (ResVT.is128BitVector() &&
8093 (InVT.is256BitVector() || InVT.is512BitVector()) &&
8094 isa<ConstantSDNode>(Idx)) {
8095 return Extract128BitVector(In, IdxVal, DAG, dl);
8097 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
8098 isa<ConstantSDNode>(Idx)) {
8099 return Extract256BitVector(In, IdxVal, DAG, dl);
8105 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
8106 // simple superregister reference or explicit instructions to insert
8107 // the upper bits of a vector.
8108 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
8109 SelectionDAG &DAG) {
8110 if (Subtarget->hasFp256()) {
8111 SDLoc dl(Op.getNode());
8112 SDValue Vec = Op.getNode()->getOperand(0);
8113 SDValue SubVec = Op.getNode()->getOperand(1);
8114 SDValue Idx = Op.getNode()->getOperand(2);
8116 if ((Op.getNode()->getSimpleValueType(0).is256BitVector() ||
8117 Op.getNode()->getSimpleValueType(0).is512BitVector()) &&
8118 SubVec.getNode()->getSimpleValueType(0).is128BitVector() &&
8119 isa<ConstantSDNode>(Idx)) {
8120 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
8121 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
8124 if (Op.getNode()->getSimpleValueType(0).is512BitVector() &&
8125 SubVec.getNode()->getSimpleValueType(0).is256BitVector() &&
8126 isa<ConstantSDNode>(Idx)) {
8127 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
8128 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
8134 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
8135 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
8136 // one of the above mentioned nodes. It has to be wrapped because otherwise
8137 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
8138 // be used to form addressing mode. These wrapped nodes will be selected
8141 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
8142 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
8144 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
8146 unsigned char OpFlag = 0;
8147 unsigned WrapperKind = X86ISD::Wrapper;
8148 CodeModel::Model M = getTargetMachine().getCodeModel();
8150 if (Subtarget->isPICStyleRIPRel() &&
8151 (M == CodeModel::Small || M == CodeModel::Kernel))
8152 WrapperKind = X86ISD::WrapperRIP;
8153 else if (Subtarget->isPICStyleGOT())
8154 OpFlag = X86II::MO_GOTOFF;
8155 else if (Subtarget->isPICStyleStubPIC())
8156 OpFlag = X86II::MO_PIC_BASE_OFFSET;
8158 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
8160 CP->getOffset(), OpFlag);
8162 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
8163 // With PIC, the address is actually $g + Offset.
8165 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8166 DAG.getNode(X86ISD::GlobalBaseReg,
8167 SDLoc(), getPointerTy()),
8174 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
8175 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
8177 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
8179 unsigned char OpFlag = 0;
8180 unsigned WrapperKind = X86ISD::Wrapper;
8181 CodeModel::Model M = getTargetMachine().getCodeModel();
8183 if (Subtarget->isPICStyleRIPRel() &&
8184 (M == CodeModel::Small || M == CodeModel::Kernel))
8185 WrapperKind = X86ISD::WrapperRIP;
8186 else if (Subtarget->isPICStyleGOT())
8187 OpFlag = X86II::MO_GOTOFF;
8188 else if (Subtarget->isPICStyleStubPIC())
8189 OpFlag = X86II::MO_PIC_BASE_OFFSET;
8191 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
8194 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
8196 // With PIC, the address is actually $g + Offset.
8198 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8199 DAG.getNode(X86ISD::GlobalBaseReg,
8200 SDLoc(), getPointerTy()),
8207 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
8208 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
8210 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
8212 unsigned char OpFlag = 0;
8213 unsigned WrapperKind = X86ISD::Wrapper;
8214 CodeModel::Model M = getTargetMachine().getCodeModel();
8216 if (Subtarget->isPICStyleRIPRel() &&
8217 (M == CodeModel::Small || M == CodeModel::Kernel)) {
8218 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
8219 OpFlag = X86II::MO_GOTPCREL;
8220 WrapperKind = X86ISD::WrapperRIP;
8221 } else if (Subtarget->isPICStyleGOT()) {
8222 OpFlag = X86II::MO_GOT;
8223 } else if (Subtarget->isPICStyleStubPIC()) {
8224 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
8225 } else if (Subtarget->isPICStyleStubNoDynamic()) {
8226 OpFlag = X86II::MO_DARWIN_NONLAZY;
8229 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
8232 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
8234 // With PIC, the address is actually $g + Offset.
8235 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
8236 !Subtarget->is64Bit()) {
8237 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8238 DAG.getNode(X86ISD::GlobalBaseReg,
8239 SDLoc(), getPointerTy()),
8243 // For symbols that require a load from a stub to get the address, emit the
8245 if (isGlobalStubReference(OpFlag))
8246 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
8247 MachinePointerInfo::getGOT(), false, false, false, 0);
8253 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
8254 // Create the TargetBlockAddressAddress node.
8255 unsigned char OpFlags =
8256 Subtarget->ClassifyBlockAddressReference();
8257 CodeModel::Model M = getTargetMachine().getCodeModel();
8258 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
8259 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
8261 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
8264 if (Subtarget->isPICStyleRIPRel() &&
8265 (M == CodeModel::Small || M == CodeModel::Kernel))
8266 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
8268 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
8270 // With PIC, the address is actually $g + Offset.
8271 if (isGlobalRelativeToPICBase(OpFlags)) {
8272 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
8273 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
8281 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
8282 int64_t Offset, SelectionDAG &DAG) const {
8283 // Create the TargetGlobalAddress node, folding in the constant
8284 // offset if it is legal.
8285 unsigned char OpFlags =
8286 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
8287 CodeModel::Model M = getTargetMachine().getCodeModel();
8289 if (OpFlags == X86II::MO_NO_FLAG &&
8290 X86::isOffsetSuitableForCodeModel(Offset, M)) {
8291 // A direct static reference to a global.
8292 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
8295 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
8298 if (Subtarget->isPICStyleRIPRel() &&
8299 (M == CodeModel::Small || M == CodeModel::Kernel))
8300 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
8302 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
8304 // With PIC, the address is actually $g + Offset.
8305 if (isGlobalRelativeToPICBase(OpFlags)) {
8306 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
8307 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
8311 // For globals that require a load from a stub to get the address, emit the
8313 if (isGlobalStubReference(OpFlags))
8314 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
8315 MachinePointerInfo::getGOT(), false, false, false, 0);
8317 // If there was a non-zero offset that we didn't fold, create an explicit
8320 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
8321 DAG.getConstant(Offset, getPointerTy()));
8327 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
8328 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
8329 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
8330 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
8334 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
8335 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
8336 unsigned char OperandFlags, bool LocalDynamic = false) {
8337 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
8338 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
8340 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
8341 GA->getValueType(0),
8345 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
8349 SDValue Ops[] = { Chain, TGA, *InFlag };
8350 Chain = DAG.getNode(CallType, dl, NodeTys, Ops, array_lengthof(Ops));
8352 SDValue Ops[] = { Chain, TGA };
8353 Chain = DAG.getNode(CallType, dl, NodeTys, Ops, array_lengthof(Ops));
8356 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
8357 MFI->setAdjustsStack(true);
8359 SDValue Flag = Chain.getValue(1);
8360 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
8363 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
8365 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
8368 SDLoc dl(GA); // ? function entry point might be better
8369 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
8370 DAG.getNode(X86ISD::GlobalBaseReg,
8371 SDLoc(), PtrVT), InFlag);
8372 InFlag = Chain.getValue(1);
8374 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
8377 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
8379 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
8381 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
8382 X86::RAX, X86II::MO_TLSGD);
8385 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
8391 // Get the start address of the TLS block for this module.
8392 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
8393 .getInfo<X86MachineFunctionInfo>();
8394 MFI->incNumLocalDynamicTLSAccesses();
8398 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT, X86::RAX,
8399 X86II::MO_TLSLD, /*LocalDynamic=*/true);
8402 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
8403 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
8404 InFlag = Chain.getValue(1);
8405 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
8406 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
8409 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
8413 unsigned char OperandFlags = X86II::MO_DTPOFF;
8414 unsigned WrapperKind = X86ISD::Wrapper;
8415 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
8416 GA->getValueType(0),
8417 GA->getOffset(), OperandFlags);
8418 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
8420 // Add x@dtpoff with the base.
8421 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
8424 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
8425 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
8426 const EVT PtrVT, TLSModel::Model model,
8427 bool is64Bit, bool isPIC) {
8430 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
8431 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
8432 is64Bit ? 257 : 256));
8434 SDValue ThreadPointer =
8435 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0),
8436 MachinePointerInfo(Ptr), false, false, false, 0);
8438 unsigned char OperandFlags = 0;
8439 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
8441 unsigned WrapperKind = X86ISD::Wrapper;
8442 if (model == TLSModel::LocalExec) {
8443 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
8444 } else if (model == TLSModel::InitialExec) {
8446 OperandFlags = X86II::MO_GOTTPOFF;
8447 WrapperKind = X86ISD::WrapperRIP;
8449 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
8452 llvm_unreachable("Unexpected model");
8455 // emit "addl x@ntpoff,%eax" (local exec)
8456 // or "addl x@indntpoff,%eax" (initial exec)
8457 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
8459 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
8460 GA->getOffset(), OperandFlags);
8461 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
8463 if (model == TLSModel::InitialExec) {
8464 if (isPIC && !is64Bit) {
8465 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
8466 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
8470 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
8471 MachinePointerInfo::getGOT(), false, false, false, 0);
8474 // The address of the thread local variable is the add of the thread
8475 // pointer with the offset of the variable.
8476 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
8480 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
8482 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
8483 const GlobalValue *GV = GA->getGlobal();
8485 if (Subtarget->isTargetELF()) {
8486 TLSModel::Model model = getTargetMachine().getTLSModel(GV);
8489 case TLSModel::GeneralDynamic:
8490 if (Subtarget->is64Bit())
8491 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
8492 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
8493 case TLSModel::LocalDynamic:
8494 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
8495 Subtarget->is64Bit());
8496 case TLSModel::InitialExec:
8497 case TLSModel::LocalExec:
8498 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
8499 Subtarget->is64Bit(),
8500 getTargetMachine().getRelocationModel() == Reloc::PIC_);
8502 llvm_unreachable("Unknown TLS model.");
8505 if (Subtarget->isTargetDarwin()) {
8506 // Darwin only has one model of TLS. Lower to that.
8507 unsigned char OpFlag = 0;
8508 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
8509 X86ISD::WrapperRIP : X86ISD::Wrapper;
8511 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
8513 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) &&
8514 !Subtarget->is64Bit();
8516 OpFlag = X86II::MO_TLVP_PIC_BASE;
8518 OpFlag = X86II::MO_TLVP;
8520 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
8521 GA->getValueType(0),
8522 GA->getOffset(), OpFlag);
8523 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
8525 // With PIC32, the address is actually $g + Offset.
8527 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8528 DAG.getNode(X86ISD::GlobalBaseReg,
8529 SDLoc(), getPointerTy()),
8532 // Lowering the machine isd will make sure everything is in the right
8534 SDValue Chain = DAG.getEntryNode();
8535 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
8536 SDValue Args[] = { Chain, Offset };
8537 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2);
8539 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
8540 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
8541 MFI->setAdjustsStack(true);
8543 // And our return value (tls address) is in the standard call return value
8545 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
8546 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
8550 if (Subtarget->isTargetKnownWindowsMSVC() ||
8551 Subtarget->isTargetWindowsGNU()) {
8552 // Just use the implicit TLS architecture
8553 // Need to generate someting similar to:
8554 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
8556 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
8557 // mov rcx, qword [rdx+rcx*8]
8558 // mov eax, .tls$:tlsvar
8559 // [rax+rcx] contains the address
8560 // Windows 64bit: gs:0x58
8561 // Windows 32bit: fs:__tls_array
8563 // If GV is an alias then use the aliasee for determining
8564 // thread-localness.
8565 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
8566 GV = GA->getAliasedGlobal();
8568 SDValue Chain = DAG.getEntryNode();
8570 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
8571 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
8572 // use its literal value of 0x2C.
8573 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
8574 ? Type::getInt8PtrTy(*DAG.getContext(),
8576 : Type::getInt32PtrTy(*DAG.getContext(),
8580 Subtarget->is64Bit()
8581 ? DAG.getIntPtrConstant(0x58)
8582 : (Subtarget->isTargetWindowsGNU()
8583 ? DAG.getIntPtrConstant(0x2C)
8584 : DAG.getExternalSymbol("_tls_array", getPointerTy()));
8586 SDValue ThreadPointer =
8587 DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
8588 MachinePointerInfo(Ptr), false, false, false, 0);
8590 // Load the _tls_index variable
8591 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
8592 if (Subtarget->is64Bit())
8593 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
8594 IDX, MachinePointerInfo(), MVT::i32,
8597 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
8598 false, false, false, 0);
8600 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
8602 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
8604 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
8605 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
8606 false, false, false, 0);
8608 // Get the offset of start of .tls section
8609 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
8610 GA->getValueType(0),
8611 GA->getOffset(), X86II::MO_SECREL);
8612 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
8614 // The address of the thread local variable is the add of the thread
8615 // pointer with the offset of the variable.
8616 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
8619 llvm_unreachable("TLS not implemented for this target.");
8622 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
8623 /// and take a 2 x i32 value to shift plus a shift amount.
8624 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
8625 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
8626 MVT VT = Op.getSimpleValueType();
8627 unsigned VTBits = VT.getSizeInBits();
8629 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
8630 SDValue ShOpLo = Op.getOperand(0);
8631 SDValue ShOpHi = Op.getOperand(1);
8632 SDValue ShAmt = Op.getOperand(2);
8633 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
8634 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
8636 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
8637 DAG.getConstant(VTBits - 1, MVT::i8));
8638 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
8639 DAG.getConstant(VTBits - 1, MVT::i8))
8640 : DAG.getConstant(0, VT);
8643 if (Op.getOpcode() == ISD::SHL_PARTS) {
8644 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
8645 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
8647 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
8648 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
8651 // If the shift amount is larger or equal than the width of a part we can't
8652 // rely on the results of shld/shrd. Insert a test and select the appropriate
8653 // values for large shift amounts.
8654 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
8655 DAG.getConstant(VTBits, MVT::i8));
8656 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
8657 AndNode, DAG.getConstant(0, MVT::i8));
8660 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8661 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
8662 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
8664 if (Op.getOpcode() == ISD::SHL_PARTS) {
8665 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
8666 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
8668 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
8669 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
8672 SDValue Ops[2] = { Lo, Hi };
8673 return DAG.getMergeValues(Ops, array_lengthof(Ops), dl);
8676 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
8677 SelectionDAG &DAG) const {
8678 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
8680 if (SrcVT.isVector())
8683 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
8684 "Unknown SINT_TO_FP to lower!");
8686 // These are really Legal; return the operand so the caller accepts it as
8688 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
8690 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
8691 Subtarget->is64Bit()) {
8696 unsigned Size = SrcVT.getSizeInBits()/8;
8697 MachineFunction &MF = DAG.getMachineFunction();
8698 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
8699 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8700 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
8702 MachinePointerInfo::getFixedStack(SSFI),
8704 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
8707 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
8709 SelectionDAG &DAG) const {
8713 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
8715 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
8717 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
8719 unsigned ByteSize = SrcVT.getSizeInBits()/8;
8721 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
8722 MachineMemOperand *MMO;
8724 int SSFI = FI->getIndex();
8726 DAG.getMachineFunction()
8727 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8728 MachineMemOperand::MOLoad, ByteSize, ByteSize);
8730 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
8731 StackSlot = StackSlot.getOperand(1);
8733 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
8734 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
8736 Tys, Ops, array_lengthof(Ops),
8740 Chain = Result.getValue(1);
8741 SDValue InFlag = Result.getValue(2);
8743 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
8744 // shouldn't be necessary except that RFP cannot be live across
8745 // multiple blocks. When stackifier is fixed, they can be uncoupled.
8746 MachineFunction &MF = DAG.getMachineFunction();
8747 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
8748 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
8749 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8750 Tys = DAG.getVTList(MVT::Other);
8752 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
8754 MachineMemOperand *MMO =
8755 DAG.getMachineFunction()
8756 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8757 MachineMemOperand::MOStore, SSFISize, SSFISize);
8759 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
8760 Ops, array_lengthof(Ops),
8761 Op.getValueType(), MMO);
8762 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
8763 MachinePointerInfo::getFixedStack(SSFI),
8764 false, false, false, 0);
8770 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
8771 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
8772 SelectionDAG &DAG) const {
8773 // This algorithm is not obvious. Here it is what we're trying to output:
8776 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
8777 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
8781 pshufd $0x4e, %xmm0, %xmm1
8787 LLVMContext *Context = DAG.getContext();
8789 // Build some magic constants.
8790 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
8791 Constant *C0 = ConstantDataVector::get(*Context, CV0);
8792 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
8794 SmallVector<Constant*,2> CV1;
8796 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
8797 APInt(64, 0x4330000000000000ULL))));
8799 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
8800 APInt(64, 0x4530000000000000ULL))));
8801 Constant *C1 = ConstantVector::get(CV1);
8802 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
8804 // Load the 64-bit value into an XMM register.
8805 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
8807 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
8808 MachinePointerInfo::getConstantPool(),
8809 false, false, false, 16);
8810 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
8811 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
8814 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
8815 MachinePointerInfo::getConstantPool(),
8816 false, false, false, 16);
8817 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
8818 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
8821 if (Subtarget->hasSSE3()) {
8822 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
8823 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
8825 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
8826 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
8828 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
8829 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
8833 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
8834 DAG.getIntPtrConstant(0));
8837 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
8838 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
8839 SelectionDAG &DAG) const {
8841 // FP constant to bias correct the final result.
8842 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
8845 // Load the 32-bit value into an XMM register.
8846 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
8849 // Zero out the upper parts of the register.
8850 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
8852 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
8853 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
8854 DAG.getIntPtrConstant(0));
8856 // Or the load with the bias.
8857 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
8858 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
8859 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
8861 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
8862 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
8863 MVT::v2f64, Bias)));
8864 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
8865 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
8866 DAG.getIntPtrConstant(0));
8868 // Subtract the bias.
8869 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
8871 // Handle final rounding.
8872 EVT DestVT = Op.getValueType();
8874 if (DestVT.bitsLT(MVT::f64))
8875 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
8876 DAG.getIntPtrConstant(0));
8877 if (DestVT.bitsGT(MVT::f64))
8878 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
8880 // Handle final rounding.
8884 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
8885 SelectionDAG &DAG) const {
8886 SDValue N0 = Op.getOperand(0);
8887 MVT SVT = N0.getSimpleValueType();
8890 assert((SVT == MVT::v4i8 || SVT == MVT::v4i16 ||
8891 SVT == MVT::v8i8 || SVT == MVT::v8i16) &&
8892 "Custom UINT_TO_FP is not supported!");
8894 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
8895 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
8896 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
8899 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
8900 SelectionDAG &DAG) const {
8901 SDValue N0 = Op.getOperand(0);
8904 if (Op.getValueType().isVector())
8905 return lowerUINT_TO_FP_vec(Op, DAG);
8907 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
8908 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
8909 // the optimization here.
8910 if (DAG.SignBitIsZero(N0))
8911 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
8913 MVT SrcVT = N0.getSimpleValueType();
8914 MVT DstVT = Op.getSimpleValueType();
8915 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
8916 return LowerUINT_TO_FP_i64(Op, DAG);
8917 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
8918 return LowerUINT_TO_FP_i32(Op, DAG);
8919 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
8922 // Make a 64-bit buffer, and use it to build an FILD.
8923 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
8924 if (SrcVT == MVT::i32) {
8925 SDValue WordOff = DAG.getConstant(4, getPointerTy());
8926 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
8927 getPointerTy(), StackSlot, WordOff);
8928 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
8929 StackSlot, MachinePointerInfo(),
8931 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
8932 OffsetSlot, MachinePointerInfo(),
8934 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
8938 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
8939 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
8940 StackSlot, MachinePointerInfo(),
8942 // For i64 source, we need to add the appropriate power of 2 if the input
8943 // was negative. This is the same as the optimization in
8944 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
8945 // we must be careful to do the computation in x87 extended precision, not
8946 // in SSE. (The generic code can't know it's OK to do this, or how to.)
8947 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
8948 MachineMemOperand *MMO =
8949 DAG.getMachineFunction()
8950 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8951 MachineMemOperand::MOLoad, 8, 8);
8953 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
8954 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
8955 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
8956 array_lengthof(Ops), MVT::i64, MMO);
8958 APInt FF(32, 0x5F800000ULL);
8960 // Check whether the sign bit is set.
8961 SDValue SignSet = DAG.getSetCC(dl,
8962 getSetCCResultType(*DAG.getContext(), MVT::i64),
8963 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
8966 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
8967 SDValue FudgePtr = DAG.getConstantPool(
8968 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
8971 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
8972 SDValue Zero = DAG.getIntPtrConstant(0);
8973 SDValue Four = DAG.getIntPtrConstant(4);
8974 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
8976 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
8978 // Load the value out, extending it from f32 to f80.
8979 // FIXME: Avoid the extend by constructing the right constant pool?
8980 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
8981 FudgePtr, MachinePointerInfo::getConstantPool(),
8982 MVT::f32, false, false, 4);
8983 // Extend everything to 80 bits to force it to be done on x87.
8984 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
8985 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
8988 std::pair<SDValue,SDValue>
8989 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
8990 bool IsSigned, bool IsReplace) const {
8993 EVT DstTy = Op.getValueType();
8995 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
8996 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
9000 assert(DstTy.getSimpleVT() <= MVT::i64 &&
9001 DstTy.getSimpleVT() >= MVT::i16 &&
9002 "Unknown FP_TO_INT to lower!");
9004 // These are really Legal.
9005 if (DstTy == MVT::i32 &&
9006 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
9007 return std::make_pair(SDValue(), SDValue());
9008 if (Subtarget->is64Bit() &&
9009 DstTy == MVT::i64 &&
9010 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
9011 return std::make_pair(SDValue(), SDValue());
9013 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
9014 // stack slot, or into the FTOL runtime function.
9015 MachineFunction &MF = DAG.getMachineFunction();
9016 unsigned MemSize = DstTy.getSizeInBits()/8;
9017 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
9018 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
9021 if (!IsSigned && isIntegerTypeFTOL(DstTy))
9022 Opc = X86ISD::WIN_FTOL;
9024 switch (DstTy.getSimpleVT().SimpleTy) {
9025 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
9026 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
9027 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
9028 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
9031 SDValue Chain = DAG.getEntryNode();
9032 SDValue Value = Op.getOperand(0);
9033 EVT TheVT = Op.getOperand(0).getValueType();
9034 // FIXME This causes a redundant load/store if the SSE-class value is already
9035 // in memory, such as if it is on the callstack.
9036 if (isScalarFPTypeInSSEReg(TheVT)) {
9037 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
9038 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
9039 MachinePointerInfo::getFixedStack(SSFI),
9041 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
9043 Chain, StackSlot, DAG.getValueType(TheVT)
9046 MachineMemOperand *MMO =
9047 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
9048 MachineMemOperand::MOLoad, MemSize, MemSize);
9049 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops,
9050 array_lengthof(Ops), DstTy, MMO);
9051 Chain = Value.getValue(1);
9052 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
9053 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
9056 MachineMemOperand *MMO =
9057 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
9058 MachineMemOperand::MOStore, MemSize, MemSize);
9060 if (Opc != X86ISD::WIN_FTOL) {
9061 // Build the FP_TO_INT*_IN_MEM
9062 SDValue Ops[] = { Chain, Value, StackSlot };
9063 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
9064 Ops, array_lengthof(Ops), DstTy,
9066 return std::make_pair(FIST, StackSlot);
9068 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
9069 DAG.getVTList(MVT::Other, MVT::Glue),
9071 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
9072 MVT::i32, ftol.getValue(1));
9073 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
9074 MVT::i32, eax.getValue(2));
9075 SDValue Ops[] = { eax, edx };
9076 SDValue pair = IsReplace
9077 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops, array_lengthof(Ops))
9078 : DAG.getMergeValues(Ops, array_lengthof(Ops), DL);
9079 return std::make_pair(pair, SDValue());
9083 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
9084 const X86Subtarget *Subtarget) {
9085 MVT VT = Op->getSimpleValueType(0);
9086 SDValue In = Op->getOperand(0);
9087 MVT InVT = In.getSimpleValueType();
9090 // Optimize vectors in AVX mode:
9093 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
9094 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
9095 // Concat upper and lower parts.
9098 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
9099 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
9100 // Concat upper and lower parts.
9103 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
9104 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
9105 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
9108 if (Subtarget->hasInt256())
9109 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
9111 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
9112 SDValue Undef = DAG.getUNDEF(InVT);
9113 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
9114 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
9115 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
9117 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
9118 VT.getVectorNumElements()/2);
9120 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
9121 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
9123 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
9126 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
9127 SelectionDAG &DAG) {
9128 MVT VT = Op->getSimpleValueType(0);
9129 SDValue In = Op->getOperand(0);
9130 MVT InVT = In.getSimpleValueType();
9132 unsigned int NumElts = VT.getVectorNumElements();
9133 if (NumElts != 8 && NumElts != 16)
9136 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
9137 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
9139 EVT ExtVT = (NumElts == 8)? MVT::v8i64 : MVT::v16i32;
9140 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9141 // Now we have only mask extension
9142 assert(InVT.getVectorElementType() == MVT::i1);
9143 SDValue Cst = DAG.getTargetConstant(1, ExtVT.getScalarType());
9144 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
9145 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
9146 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
9147 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
9148 MachinePointerInfo::getConstantPool(),
9149 false, false, false, Alignment);
9151 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, DL, ExtVT, In, Ld);
9152 if (VT.is512BitVector())
9154 return DAG.getNode(X86ISD::VTRUNC, DL, VT, Brcst);
9157 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
9158 SelectionDAG &DAG) {
9159 if (Subtarget->hasFp256()) {
9160 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
9168 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
9169 SelectionDAG &DAG) {
9171 MVT VT = Op.getSimpleValueType();
9172 SDValue In = Op.getOperand(0);
9173 MVT SVT = In.getSimpleValueType();
9175 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
9176 return LowerZERO_EXTEND_AVX512(Op, DAG);
9178 if (Subtarget->hasFp256()) {
9179 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
9184 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
9185 VT.getVectorNumElements() != SVT.getVectorNumElements());
9189 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
9191 MVT VT = Op.getSimpleValueType();
9192 SDValue In = Op.getOperand(0);
9193 MVT InVT = In.getSimpleValueType();
9195 if (VT == MVT::i1) {
9196 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
9197 "Invalid scalar TRUNCATE operation");
9198 if (InVT == MVT::i32)
9200 if (InVT.getSizeInBits() == 64)
9201 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::i32, In);
9202 else if (InVT.getSizeInBits() < 32)
9203 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
9204 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
9206 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
9207 "Invalid TRUNCATE operation");
9209 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
9210 if (VT.getVectorElementType().getSizeInBits() >=8)
9211 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
9213 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
9214 unsigned NumElts = InVT.getVectorNumElements();
9215 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
9216 if (InVT.getSizeInBits() < 512) {
9217 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
9218 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
9222 SDValue Cst = DAG.getTargetConstant(1, InVT.getVectorElementType());
9223 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
9224 SDValue CP = DAG.getConstantPool(C, getPointerTy());
9225 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
9226 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
9227 MachinePointerInfo::getConstantPool(),
9228 false, false, false, Alignment);
9229 SDValue OneV = DAG.getNode(X86ISD::VBROADCAST, DL, InVT, Ld);
9230 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
9231 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
9234 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
9235 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
9236 if (Subtarget->hasInt256()) {
9237 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
9238 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
9239 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
9241 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
9242 DAG.getIntPtrConstant(0));
9245 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
9246 DAG.getIntPtrConstant(0));
9247 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
9248 DAG.getIntPtrConstant(2));
9249 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
9250 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
9251 static const int ShufMask[] = {0, 2, 4, 6};
9252 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
9255 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
9256 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
9257 if (Subtarget->hasInt256()) {
9258 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
9260 SmallVector<SDValue,32> pshufbMask;
9261 for (unsigned i = 0; i < 2; ++i) {
9262 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
9263 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
9264 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
9265 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
9266 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
9267 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
9268 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
9269 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
9270 for (unsigned j = 0; j < 8; ++j)
9271 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
9273 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8,
9274 &pshufbMask[0], 32);
9275 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
9276 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
9278 static const int ShufMask[] = {0, 2, -1, -1};
9279 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
9281 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
9282 DAG.getIntPtrConstant(0));
9283 return DAG.getNode(ISD::BITCAST, DL, VT, In);
9286 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
9287 DAG.getIntPtrConstant(0));
9289 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
9290 DAG.getIntPtrConstant(4));
9292 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
9293 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
9296 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
9297 -1, -1, -1, -1, -1, -1, -1, -1};
9299 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
9300 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
9301 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
9303 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
9304 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
9306 // The MOVLHPS Mask:
9307 static const int ShufMask2[] = {0, 1, 4, 5};
9308 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
9309 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
9312 // Handle truncation of V256 to V128 using shuffles.
9313 if (!VT.is128BitVector() || !InVT.is256BitVector())
9316 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
9318 unsigned NumElems = VT.getVectorNumElements();
9319 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
9321 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
9322 // Prepare truncation shuffle mask
9323 for (unsigned i = 0; i != NumElems; ++i)
9325 SDValue V = DAG.getVectorShuffle(NVT, DL,
9326 DAG.getNode(ISD::BITCAST, DL, NVT, In),
9327 DAG.getUNDEF(NVT), &MaskVec[0]);
9328 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
9329 DAG.getIntPtrConstant(0));
9332 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
9333 SelectionDAG &DAG) const {
9334 assert(!Op.getSimpleValueType().isVector());
9336 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
9337 /*IsSigned=*/ true, /*IsReplace=*/ false);
9338 SDValue FIST = Vals.first, StackSlot = Vals.second;
9339 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
9340 if (FIST.getNode() == 0) return Op;
9342 if (StackSlot.getNode())
9344 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
9345 FIST, StackSlot, MachinePointerInfo(),
9346 false, false, false, 0);
9348 // The node is the result.
9352 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
9353 SelectionDAG &DAG) const {
9354 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
9355 /*IsSigned=*/ false, /*IsReplace=*/ false);
9356 SDValue FIST = Vals.first, StackSlot = Vals.second;
9357 assert(FIST.getNode() && "Unexpected failure");
9359 if (StackSlot.getNode())
9361 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
9362 FIST, StackSlot, MachinePointerInfo(),
9363 false, false, false, 0);
9365 // The node is the result.
9369 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
9371 MVT VT = Op.getSimpleValueType();
9372 SDValue In = Op.getOperand(0);
9373 MVT SVT = In.getSimpleValueType();
9375 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
9377 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
9378 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
9379 In, DAG.getUNDEF(SVT)));
9382 static SDValue LowerFABS(SDValue Op, SelectionDAG &DAG) {
9383 LLVMContext *Context = DAG.getContext();
9385 MVT VT = Op.getSimpleValueType();
9387 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
9388 if (VT.isVector()) {
9389 EltVT = VT.getVectorElementType();
9390 NumElts = VT.getVectorNumElements();
9393 if (EltVT == MVT::f64)
9394 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
9395 APInt(64, ~(1ULL << 63))));
9397 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEsingle,
9398 APInt(32, ~(1U << 31))));
9399 C = ConstantVector::getSplat(NumElts, C);
9400 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9401 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
9402 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
9403 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9404 MachinePointerInfo::getConstantPool(),
9405 false, false, false, Alignment);
9406 if (VT.isVector()) {
9407 MVT ANDVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
9408 return DAG.getNode(ISD::BITCAST, dl, VT,
9409 DAG.getNode(ISD::AND, dl, ANDVT,
9410 DAG.getNode(ISD::BITCAST, dl, ANDVT,
9412 DAG.getNode(ISD::BITCAST, dl, ANDVT, Mask)));
9414 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
9417 static SDValue LowerFNEG(SDValue Op, SelectionDAG &DAG) {
9418 LLVMContext *Context = DAG.getContext();
9420 MVT VT = Op.getSimpleValueType();
9422 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
9423 if (VT.isVector()) {
9424 EltVT = VT.getVectorElementType();
9425 NumElts = VT.getVectorNumElements();
9428 if (EltVT == MVT::f64)
9429 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
9430 APInt(64, 1ULL << 63)));
9432 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEsingle,
9433 APInt(32, 1U << 31)));
9434 C = ConstantVector::getSplat(NumElts, C);
9435 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9436 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
9437 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
9438 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9439 MachinePointerInfo::getConstantPool(),
9440 false, false, false, Alignment);
9441 if (VT.isVector()) {
9442 MVT XORVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits()/64);
9443 return DAG.getNode(ISD::BITCAST, dl, VT,
9444 DAG.getNode(ISD::XOR, dl, XORVT,
9445 DAG.getNode(ISD::BITCAST, dl, XORVT,
9447 DAG.getNode(ISD::BITCAST, dl, XORVT, Mask)));
9450 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
9453 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
9454 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9455 LLVMContext *Context = DAG.getContext();
9456 SDValue Op0 = Op.getOperand(0);
9457 SDValue Op1 = Op.getOperand(1);
9459 MVT VT = Op.getSimpleValueType();
9460 MVT SrcVT = Op1.getSimpleValueType();
9462 // If second operand is smaller, extend it first.
9463 if (SrcVT.bitsLT(VT)) {
9464 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
9467 // And if it is bigger, shrink it first.
9468 if (SrcVT.bitsGT(VT)) {
9469 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
9473 // At this point the operands and the result should have the same
9474 // type, and that won't be f80 since that is not custom lowered.
9476 // First get the sign bit of second operand.
9477 SmallVector<Constant*,4> CV;
9478 if (SrcVT == MVT::f64) {
9479 const fltSemantics &Sem = APFloat::IEEEdouble;
9480 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 1ULL << 63))));
9481 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
9483 const fltSemantics &Sem = APFloat::IEEEsingle;
9484 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 1U << 31))));
9485 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9486 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9487 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9489 Constant *C = ConstantVector::get(CV);
9490 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
9491 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
9492 MachinePointerInfo::getConstantPool(),
9493 false, false, false, 16);
9494 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
9496 // Shift sign bit right or left if the two operands have different types.
9497 if (SrcVT.bitsGT(VT)) {
9498 // Op0 is MVT::f32, Op1 is MVT::f64.
9499 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
9500 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
9501 DAG.getConstant(32, MVT::i32));
9502 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
9503 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
9504 DAG.getIntPtrConstant(0));
9507 // Clear first operand sign bit.
9509 if (VT == MVT::f64) {
9510 const fltSemantics &Sem = APFloat::IEEEdouble;
9511 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
9512 APInt(64, ~(1ULL << 63)))));
9513 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
9515 const fltSemantics &Sem = APFloat::IEEEsingle;
9516 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
9517 APInt(32, ~(1U << 31)))));
9518 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9519 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9520 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9522 C = ConstantVector::get(CV);
9523 CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
9524 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9525 MachinePointerInfo::getConstantPool(),
9526 false, false, false, 16);
9527 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
9529 // Or the value with the sign bit.
9530 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
9533 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
9534 SDValue N0 = Op.getOperand(0);
9536 MVT VT = Op.getSimpleValueType();
9538 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
9539 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
9540 DAG.getConstant(1, VT));
9541 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
9544 // LowerVectorAllZeroTest - Check whether an OR'd tree is PTEST-able.
9546 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
9547 SelectionDAG &DAG) {
9548 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
9550 if (!Subtarget->hasSSE41())
9553 if (!Op->hasOneUse())
9556 SDNode *N = Op.getNode();
9559 SmallVector<SDValue, 8> Opnds;
9560 DenseMap<SDValue, unsigned> VecInMap;
9561 SmallVector<SDValue, 8> VecIns;
9562 EVT VT = MVT::Other;
9564 // Recognize a special case where a vector is casted into wide integer to
9566 Opnds.push_back(N->getOperand(0));
9567 Opnds.push_back(N->getOperand(1));
9569 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
9570 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
9571 // BFS traverse all OR'd operands.
9572 if (I->getOpcode() == ISD::OR) {
9573 Opnds.push_back(I->getOperand(0));
9574 Opnds.push_back(I->getOperand(1));
9575 // Re-evaluate the number of nodes to be traversed.
9576 e += 2; // 2 more nodes (LHS and RHS) are pushed.
9580 // Quit if a non-EXTRACT_VECTOR_ELT
9581 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
9584 // Quit if without a constant index.
9585 SDValue Idx = I->getOperand(1);
9586 if (!isa<ConstantSDNode>(Idx))
9589 SDValue ExtractedFromVec = I->getOperand(0);
9590 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
9591 if (M == VecInMap.end()) {
9592 VT = ExtractedFromVec.getValueType();
9593 // Quit if not 128/256-bit vector.
9594 if (!VT.is128BitVector() && !VT.is256BitVector())
9596 // Quit if not the same type.
9597 if (VecInMap.begin() != VecInMap.end() &&
9598 VT != VecInMap.begin()->first.getValueType())
9600 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
9601 VecIns.push_back(ExtractedFromVec);
9603 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
9606 assert((VT.is128BitVector() || VT.is256BitVector()) &&
9607 "Not extracted from 128-/256-bit vector.");
9609 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
9611 for (DenseMap<SDValue, unsigned>::const_iterator
9612 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
9613 // Quit if not all elements are used.
9614 if (I->second != FullMask)
9618 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
9620 // Cast all vectors into TestVT for PTEST.
9621 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
9622 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
9624 // If more than one full vectors are evaluated, OR them first before PTEST.
9625 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
9626 // Each iteration will OR 2 nodes and append the result until there is only
9627 // 1 node left, i.e. the final OR'd value of all vectors.
9628 SDValue LHS = VecIns[Slot];
9629 SDValue RHS = VecIns[Slot + 1];
9630 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
9633 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
9634 VecIns.back(), VecIns.back());
9637 /// Emit nodes that will be selected as "test Op0,Op0", or something
9639 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
9640 SelectionDAG &DAG) const {
9641 if (Op.getValueType() == MVT::i1)
9642 // KORTEST instruction should be selected
9643 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
9644 DAG.getConstant(0, Op.getValueType()));
9646 // CF and OF aren't always set the way we want. Determine which
9647 // of these we need.
9648 bool NeedCF = false;
9649 bool NeedOF = false;
9652 case X86::COND_A: case X86::COND_AE:
9653 case X86::COND_B: case X86::COND_BE:
9656 case X86::COND_G: case X86::COND_GE:
9657 case X86::COND_L: case X86::COND_LE:
9658 case X86::COND_O: case X86::COND_NO:
9662 // See if we can use the EFLAGS value from the operand instead of
9663 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
9664 // we prove that the arithmetic won't overflow, we can't use OF or CF.
9665 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
9666 // Emit a CMP with 0, which is the TEST pattern.
9667 //if (Op.getValueType() == MVT::i1)
9668 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
9669 // DAG.getConstant(0, MVT::i1));
9670 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
9671 DAG.getConstant(0, Op.getValueType()));
9673 unsigned Opcode = 0;
9674 unsigned NumOperands = 0;
9676 // Truncate operations may prevent the merge of the SETCC instruction
9677 // and the arithmetic instruction before it. Attempt to truncate the operands
9678 // of the arithmetic instruction and use a reduced bit-width instruction.
9679 bool NeedTruncation = false;
9680 SDValue ArithOp = Op;
9681 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
9682 SDValue Arith = Op->getOperand(0);
9683 // Both the trunc and the arithmetic op need to have one user each.
9684 if (Arith->hasOneUse())
9685 switch (Arith.getOpcode()) {
9692 NeedTruncation = true;
9698 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
9699 // which may be the result of a CAST. We use the variable 'Op', which is the
9700 // non-casted variable when we check for possible users.
9701 switch (ArithOp.getOpcode()) {
9703 // Due to an isel shortcoming, be conservative if this add is likely to be
9704 // selected as part of a load-modify-store instruction. When the root node
9705 // in a match is a store, isel doesn't know how to remap non-chain non-flag
9706 // uses of other nodes in the match, such as the ADD in this case. This
9707 // leads to the ADD being left around and reselected, with the result being
9708 // two adds in the output. Alas, even if none our users are stores, that
9709 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
9710 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
9711 // climbing the DAG back to the root, and it doesn't seem to be worth the
9713 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
9714 UE = Op.getNode()->use_end(); UI != UE; ++UI)
9715 if (UI->getOpcode() != ISD::CopyToReg &&
9716 UI->getOpcode() != ISD::SETCC &&
9717 UI->getOpcode() != ISD::STORE)
9720 if (ConstantSDNode *C =
9721 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
9722 // An add of one will be selected as an INC.
9723 if (C->getAPIntValue() == 1) {
9724 Opcode = X86ISD::INC;
9729 // An add of negative one (subtract of one) will be selected as a DEC.
9730 if (C->getAPIntValue().isAllOnesValue()) {
9731 Opcode = X86ISD::DEC;
9737 // Otherwise use a regular EFLAGS-setting add.
9738 Opcode = X86ISD::ADD;
9742 // If the primary and result isn't used, don't bother using X86ISD::AND,
9743 // because a TEST instruction will be better.
9744 bool NonFlagUse = false;
9745 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
9746 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
9748 unsigned UOpNo = UI.getOperandNo();
9749 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
9750 // Look pass truncate.
9751 UOpNo = User->use_begin().getOperandNo();
9752 User = *User->use_begin();
9755 if (User->getOpcode() != ISD::BRCOND &&
9756 User->getOpcode() != ISD::SETCC &&
9757 !(User->getOpcode() == ISD::SELECT && UOpNo == 0)) {
9770 // Due to the ISEL shortcoming noted above, be conservative if this op is
9771 // likely to be selected as part of a load-modify-store instruction.
9772 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
9773 UE = Op.getNode()->use_end(); UI != UE; ++UI)
9774 if (UI->getOpcode() == ISD::STORE)
9777 // Otherwise use a regular EFLAGS-setting instruction.
9778 switch (ArithOp.getOpcode()) {
9779 default: llvm_unreachable("unexpected operator!");
9780 case ISD::SUB: Opcode = X86ISD::SUB; break;
9781 case ISD::XOR: Opcode = X86ISD::XOR; break;
9782 case ISD::AND: Opcode = X86ISD::AND; break;
9784 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
9785 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
9786 if (EFLAGS.getNode())
9789 Opcode = X86ISD::OR;
9803 return SDValue(Op.getNode(), 1);
9809 // If we found that truncation is beneficial, perform the truncation and
9811 if (NeedTruncation) {
9812 EVT VT = Op.getValueType();
9813 SDValue WideVal = Op->getOperand(0);
9814 EVT WideVT = WideVal.getValueType();
9815 unsigned ConvertedOp = 0;
9816 // Use a target machine opcode to prevent further DAGCombine
9817 // optimizations that may separate the arithmetic operations
9818 // from the setcc node.
9819 switch (WideVal.getOpcode()) {
9821 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
9822 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
9823 case ISD::AND: ConvertedOp = X86ISD::AND; break;
9824 case ISD::OR: ConvertedOp = X86ISD::OR; break;
9825 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
9829 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9830 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
9831 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
9832 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
9833 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
9839 // Emit a CMP with 0, which is the TEST pattern.
9840 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
9841 DAG.getConstant(0, Op.getValueType()));
9843 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
9844 SmallVector<SDValue, 4> Ops;
9845 for (unsigned i = 0; i != NumOperands; ++i)
9846 Ops.push_back(Op.getOperand(i));
9848 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
9849 DAG.ReplaceAllUsesWith(Op, New);
9850 return SDValue(New.getNode(), 1);
9853 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
9855 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
9856 SDLoc dl, SelectionDAG &DAG) const {
9857 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
9858 if (C->getAPIntValue() == 0)
9859 return EmitTest(Op0, X86CC, dl, DAG);
9861 if (Op0.getValueType() == MVT::i1)
9862 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
9865 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
9866 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
9867 // Do the comparison at i32 if it's smaller, besides the Atom case.
9868 // This avoids subregister aliasing issues. Keep the smaller reference
9869 // if we're optimizing for size, however, as that'll allow better folding
9870 // of memory operations.
9871 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
9872 !DAG.getMachineFunction().getFunction()->getAttributes().hasAttribute(
9873 AttributeSet::FunctionIndex, Attribute::MinSize) &&
9874 !Subtarget->isAtom()) {
9876 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
9877 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
9878 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
9880 // Use SUB instead of CMP to enable CSE between SUB and CMP.
9881 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
9882 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
9884 return SDValue(Sub.getNode(), 1);
9886 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
9889 /// Convert a comparison if required by the subtarget.
9890 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
9891 SelectionDAG &DAG) const {
9892 // If the subtarget does not support the FUCOMI instruction, floating-point
9893 // comparisons have to be converted.
9894 if (Subtarget->hasCMov() ||
9895 Cmp.getOpcode() != X86ISD::CMP ||
9896 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
9897 !Cmp.getOperand(1).getValueType().isFloatingPoint())
9900 // The instruction selector will select an FUCOM instruction instead of
9901 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
9902 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
9903 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
9905 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
9906 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
9907 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
9908 DAG.getConstant(8, MVT::i8));
9909 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
9910 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
9913 static bool isAllOnes(SDValue V) {
9914 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
9915 return C && C->isAllOnesValue();
9918 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
9919 /// if it's possible.
9920 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
9921 SDLoc dl, SelectionDAG &DAG) const {
9922 SDValue Op0 = And.getOperand(0);
9923 SDValue Op1 = And.getOperand(1);
9924 if (Op0.getOpcode() == ISD::TRUNCATE)
9925 Op0 = Op0.getOperand(0);
9926 if (Op1.getOpcode() == ISD::TRUNCATE)
9927 Op1 = Op1.getOperand(0);
9930 if (Op1.getOpcode() == ISD::SHL)
9931 std::swap(Op0, Op1);
9932 if (Op0.getOpcode() == ISD::SHL) {
9933 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
9934 if (And00C->getZExtValue() == 1) {
9935 // If we looked past a truncate, check that it's only truncating away
9937 unsigned BitWidth = Op0.getValueSizeInBits();
9938 unsigned AndBitWidth = And.getValueSizeInBits();
9939 if (BitWidth > AndBitWidth) {
9941 DAG.ComputeMaskedBits(Op0, Zeros, Ones);
9942 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
9946 RHS = Op0.getOperand(1);
9948 } else if (Op1.getOpcode() == ISD::Constant) {
9949 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
9950 uint64_t AndRHSVal = AndRHS->getZExtValue();
9951 SDValue AndLHS = Op0;
9953 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
9954 LHS = AndLHS.getOperand(0);
9955 RHS = AndLHS.getOperand(1);
9958 // Use BT if the immediate can't be encoded in a TEST instruction.
9959 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
9961 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
9965 if (LHS.getNode()) {
9966 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
9967 // instruction. Since the shift amount is in-range-or-undefined, we know
9968 // that doing a bittest on the i32 value is ok. We extend to i32 because
9969 // the encoding for the i16 version is larger than the i32 version.
9970 // Also promote i16 to i32 for performance / code size reason.
9971 if (LHS.getValueType() == MVT::i8 ||
9972 LHS.getValueType() == MVT::i16)
9973 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
9975 // If the operand types disagree, extend the shift amount to match. Since
9976 // BT ignores high bits (like shifts) we can use anyextend.
9977 if (LHS.getValueType() != RHS.getValueType())
9978 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
9980 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
9981 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
9982 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9983 DAG.getConstant(Cond, MVT::i8), BT);
9989 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
9991 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
9996 // SSE Condition code mapping:
10005 switch (SetCCOpcode) {
10006 default: llvm_unreachable("Unexpected SETCC condition");
10008 case ISD::SETEQ: SSECC = 0; break;
10010 case ISD::SETGT: Swap = true; // Fallthrough
10012 case ISD::SETOLT: SSECC = 1; break;
10014 case ISD::SETGE: Swap = true; // Fallthrough
10016 case ISD::SETOLE: SSECC = 2; break;
10017 case ISD::SETUO: SSECC = 3; break;
10019 case ISD::SETNE: SSECC = 4; break;
10020 case ISD::SETULE: Swap = true; // Fallthrough
10021 case ISD::SETUGE: SSECC = 5; break;
10022 case ISD::SETULT: Swap = true; // Fallthrough
10023 case ISD::SETUGT: SSECC = 6; break;
10024 case ISD::SETO: SSECC = 7; break;
10026 case ISD::SETONE: SSECC = 8; break;
10029 std::swap(Op0, Op1);
10034 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
10035 // ones, and then concatenate the result back.
10036 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
10037 MVT VT = Op.getSimpleValueType();
10039 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
10040 "Unsupported value type for operation");
10042 unsigned NumElems = VT.getVectorNumElements();
10044 SDValue CC = Op.getOperand(2);
10046 // Extract the LHS vectors
10047 SDValue LHS = Op.getOperand(0);
10048 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
10049 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
10051 // Extract the RHS vectors
10052 SDValue RHS = Op.getOperand(1);
10053 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
10054 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
10056 // Issue the operation on the smaller types and concatenate the result back
10057 MVT EltVT = VT.getVectorElementType();
10058 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
10059 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
10060 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
10061 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
10064 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
10065 const X86Subtarget *Subtarget) {
10066 SDValue Op0 = Op.getOperand(0);
10067 SDValue Op1 = Op.getOperand(1);
10068 SDValue CC = Op.getOperand(2);
10069 MVT VT = Op.getSimpleValueType();
10072 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 32 &&
10073 Op.getValueType().getScalarType() == MVT::i1 &&
10074 "Cannot set masked compare for this operation");
10076 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
10078 bool Unsigned = false;
10081 switch (SetCCOpcode) {
10082 default: llvm_unreachable("Unexpected SETCC condition");
10083 case ISD::SETNE: SSECC = 4; break;
10084 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
10085 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
10086 case ISD::SETLT: Swap = true; //fall-through
10087 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
10088 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
10089 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
10090 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
10091 case ISD::SETULE: Unsigned = true; //fall-through
10092 case ISD::SETLE: SSECC = 2; break;
10096 std::swap(Op0, Op1);
10098 return DAG.getNode(Opc, dl, VT, Op0, Op1);
10099 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
10100 return DAG.getNode(Opc, dl, VT, Op0, Op1,
10101 DAG.getConstant(SSECC, MVT::i8));
10104 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
10105 /// operand \p Op1. If non-trivial (for example because it's not constant)
10106 /// return an empty value.
10107 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
10109 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
10113 MVT VT = Op1.getSimpleValueType();
10114 MVT EVT = VT.getVectorElementType();
10115 unsigned n = VT.getVectorNumElements();
10116 SmallVector<SDValue, 8> ULTOp1;
10118 for (unsigned i = 0; i < n; ++i) {
10119 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
10120 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
10123 // Avoid underflow.
10124 APInt Val = Elt->getAPIntValue();
10128 ULTOp1.push_back(DAG.getConstant(Val - 1, EVT));
10131 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1.data(), ULTOp1.size());
10134 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
10135 SelectionDAG &DAG) {
10136 SDValue Op0 = Op.getOperand(0);
10137 SDValue Op1 = Op.getOperand(1);
10138 SDValue CC = Op.getOperand(2);
10139 MVT VT = Op.getSimpleValueType();
10140 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
10141 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
10146 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
10147 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
10150 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
10151 unsigned Opc = X86ISD::CMPP;
10152 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
10153 assert(VT.getVectorNumElements() <= 16);
10154 Opc = X86ISD::CMPM;
10156 // In the two special cases we can't handle, emit two comparisons.
10159 unsigned CombineOpc;
10160 if (SetCCOpcode == ISD::SETUEQ) {
10161 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
10163 assert(SetCCOpcode == ISD::SETONE);
10164 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
10167 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
10168 DAG.getConstant(CC0, MVT::i8));
10169 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
10170 DAG.getConstant(CC1, MVT::i8));
10171 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
10173 // Handle all other FP comparisons here.
10174 return DAG.getNode(Opc, dl, VT, Op0, Op1,
10175 DAG.getConstant(SSECC, MVT::i8));
10178 // Break 256-bit integer vector compare into smaller ones.
10179 if (VT.is256BitVector() && !Subtarget->hasInt256())
10180 return Lower256IntVSETCC(Op, DAG);
10182 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
10183 EVT OpVT = Op1.getValueType();
10184 if (Subtarget->hasAVX512()) {
10185 if (Op1.getValueType().is512BitVector() ||
10186 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
10187 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
10189 // In AVX-512 architecture setcc returns mask with i1 elements,
10190 // But there is no compare instruction for i8 and i16 elements.
10191 // We are not talking about 512-bit operands in this case, these
10192 // types are illegal.
10194 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
10195 OpVT.getVectorElementType().getSizeInBits() >= 8))
10196 return DAG.getNode(ISD::TRUNCATE, dl, VT,
10197 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
10200 // We are handling one of the integer comparisons here. Since SSE only has
10201 // GT and EQ comparisons for integer, swapping operands and multiple
10202 // operations may be required for some comparisons.
10204 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
10205 bool Subus = false;
10207 switch (SetCCOpcode) {
10208 default: llvm_unreachable("Unexpected SETCC condition");
10209 case ISD::SETNE: Invert = true;
10210 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
10211 case ISD::SETLT: Swap = true;
10212 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
10213 case ISD::SETGE: Swap = true;
10214 case ISD::SETLE: Opc = X86ISD::PCMPGT;
10215 Invert = true; break;
10216 case ISD::SETULT: Swap = true;
10217 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
10218 FlipSigns = true; break;
10219 case ISD::SETUGE: Swap = true;
10220 case ISD::SETULE: Opc = X86ISD::PCMPGT;
10221 FlipSigns = true; Invert = true; break;
10224 // Special case: Use min/max operations for SETULE/SETUGE
10225 MVT VET = VT.getVectorElementType();
10227 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
10228 || (Subtarget->hasSSE2() && (VET == MVT::i8));
10231 switch (SetCCOpcode) {
10233 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
10234 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
10237 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
10240 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
10241 if (!MinMax && hasSubus) {
10242 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
10244 // t = psubus Op0, Op1
10245 // pcmpeq t, <0..0>
10246 switch (SetCCOpcode) {
10248 case ISD::SETULT: {
10249 // If the comparison is against a constant we can turn this into a
10250 // setule. With psubus, setule does not require a swap. This is
10251 // beneficial because the constant in the register is no longer
10252 // destructed as the destination so it can be hoisted out of a loop.
10253 // Only do this pre-AVX since vpcmp* is no longer destructive.
10254 if (Subtarget->hasAVX())
10256 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
10257 if (ULEOp1.getNode()) {
10259 Subus = true; Invert = false; Swap = false;
10263 // Psubus is better than flip-sign because it requires no inversion.
10264 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
10265 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
10269 Opc = X86ISD::SUBUS;
10275 std::swap(Op0, Op1);
10277 // Check that the operation in question is available (most are plain SSE2,
10278 // but PCMPGTQ and PCMPEQQ have different requirements).
10279 if (VT == MVT::v2i64) {
10280 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
10281 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
10283 // First cast everything to the right type.
10284 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
10285 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
10287 // Since SSE has no unsigned integer comparisons, we need to flip the sign
10288 // bits of the inputs before performing those operations. The lower
10289 // compare is always unsigned.
10292 SB = DAG.getConstant(0x80000000U, MVT::v4i32);
10294 SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
10295 SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
10296 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
10297 Sign, Zero, Sign, Zero);
10299 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
10300 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
10302 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
10303 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
10304 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
10306 // Create masks for only the low parts/high parts of the 64 bit integers.
10307 static const int MaskHi[] = { 1, 1, 3, 3 };
10308 static const int MaskLo[] = { 0, 0, 2, 2 };
10309 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
10310 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
10311 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
10313 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
10314 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
10317 Result = DAG.getNOT(dl, Result, MVT::v4i32);
10319 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
10322 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
10323 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
10324 // pcmpeqd + pshufd + pand.
10325 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
10327 // First cast everything to the right type.
10328 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
10329 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
10332 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
10334 // Make sure the lower and upper halves are both all-ones.
10335 static const int Mask[] = { 1, 0, 3, 2 };
10336 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
10337 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
10340 Result = DAG.getNOT(dl, Result, MVT::v4i32);
10342 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
10346 // Since SSE has no unsigned integer comparisons, we need to flip the sign
10347 // bits of the inputs before performing those operations.
10349 EVT EltVT = VT.getVectorElementType();
10350 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
10351 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
10352 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
10355 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
10357 // If the logical-not of the result is required, perform that now.
10359 Result = DAG.getNOT(dl, Result, VT);
10362 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
10365 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
10366 getZeroVector(VT, Subtarget, DAG, dl));
10371 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
10373 MVT VT = Op.getSimpleValueType();
10375 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
10377 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
10378 && "SetCC type must be 8-bit or 1-bit integer");
10379 SDValue Op0 = Op.getOperand(0);
10380 SDValue Op1 = Op.getOperand(1);
10382 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
10384 // Optimize to BT if possible.
10385 // Lower (X & (1 << N)) == 0 to BT(X, N).
10386 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
10387 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
10388 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
10389 Op1.getOpcode() == ISD::Constant &&
10390 cast<ConstantSDNode>(Op1)->isNullValue() &&
10391 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
10392 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
10393 if (NewSetCC.getNode())
10397 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
10399 if (Op1.getOpcode() == ISD::Constant &&
10400 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
10401 cast<ConstantSDNode>(Op1)->isNullValue()) &&
10402 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
10404 // If the input is a setcc, then reuse the input setcc or use a new one with
10405 // the inverted condition.
10406 if (Op0.getOpcode() == X86ISD::SETCC) {
10407 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
10408 bool Invert = (CC == ISD::SETNE) ^
10409 cast<ConstantSDNode>(Op1)->isNullValue();
10413 CCode = X86::GetOppositeBranchCondition(CCode);
10414 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
10415 DAG.getConstant(CCode, MVT::i8),
10416 Op0.getOperand(1));
10418 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
10422 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
10423 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
10424 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
10426 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
10427 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, MVT::i1), NewCC);
10430 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
10431 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
10432 if (X86CC == X86::COND_INVALID)
10435 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
10436 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
10437 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
10438 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
10440 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
10444 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
10445 static bool isX86LogicalCmp(SDValue Op) {
10446 unsigned Opc = Op.getNode()->getOpcode();
10447 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
10448 Opc == X86ISD::SAHF)
10450 if (Op.getResNo() == 1 &&
10451 (Opc == X86ISD::ADD ||
10452 Opc == X86ISD::SUB ||
10453 Opc == X86ISD::ADC ||
10454 Opc == X86ISD::SBB ||
10455 Opc == X86ISD::SMUL ||
10456 Opc == X86ISD::UMUL ||
10457 Opc == X86ISD::INC ||
10458 Opc == X86ISD::DEC ||
10459 Opc == X86ISD::OR ||
10460 Opc == X86ISD::XOR ||
10461 Opc == X86ISD::AND))
10464 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
10470 static bool isZero(SDValue V) {
10471 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
10472 return C && C->isNullValue();
10475 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
10476 if (V.getOpcode() != ISD::TRUNCATE)
10479 SDValue VOp0 = V.getOperand(0);
10480 unsigned InBits = VOp0.getValueSizeInBits();
10481 unsigned Bits = V.getValueSizeInBits();
10482 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
10485 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
10486 bool addTest = true;
10487 SDValue Cond = Op.getOperand(0);
10488 SDValue Op1 = Op.getOperand(1);
10489 SDValue Op2 = Op.getOperand(2);
10491 EVT VT = Op1.getValueType();
10494 // Lower fp selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
10495 // are available. Otherwise fp cmovs get lowered into a less efficient branch
10496 // sequence later on.
10497 if (Cond.getOpcode() == ISD::SETCC &&
10498 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
10499 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
10500 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
10501 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
10502 int SSECC = translateX86FSETCC(
10503 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
10506 if (Subtarget->hasAVX512()) {
10507 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
10508 DAG.getConstant(SSECC, MVT::i8));
10509 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
10511 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
10512 DAG.getConstant(SSECC, MVT::i8));
10513 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
10514 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
10515 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
10519 if (Cond.getOpcode() == ISD::SETCC) {
10520 SDValue NewCond = LowerSETCC(Cond, DAG);
10521 if (NewCond.getNode())
10525 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
10526 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
10527 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
10528 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
10529 if (Cond.getOpcode() == X86ISD::SETCC &&
10530 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
10531 isZero(Cond.getOperand(1).getOperand(1))) {
10532 SDValue Cmp = Cond.getOperand(1);
10534 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
10536 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
10537 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
10538 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
10540 SDValue CmpOp0 = Cmp.getOperand(0);
10541 // Apply further optimizations for special cases
10542 // (select (x != 0), -1, 0) -> neg & sbb
10543 // (select (x == 0), 0, -1) -> neg & sbb
10544 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
10545 if (YC->isNullValue() &&
10546 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
10547 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
10548 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
10549 DAG.getConstant(0, CmpOp0.getValueType()),
10551 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
10552 DAG.getConstant(X86::COND_B, MVT::i8),
10553 SDValue(Neg.getNode(), 1));
10557 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
10558 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
10559 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
10561 SDValue Res = // Res = 0 or -1.
10562 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
10563 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
10565 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
10566 Res = DAG.getNOT(DL, Res, Res.getValueType());
10568 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
10569 if (N2C == 0 || !N2C->isNullValue())
10570 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
10575 // Look past (and (setcc_carry (cmp ...)), 1).
10576 if (Cond.getOpcode() == ISD::AND &&
10577 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
10578 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
10579 if (C && C->getAPIntValue() == 1)
10580 Cond = Cond.getOperand(0);
10583 // If condition flag is set by a X86ISD::CMP, then use it as the condition
10584 // setting operand in place of the X86ISD::SETCC.
10585 unsigned CondOpcode = Cond.getOpcode();
10586 if (CondOpcode == X86ISD::SETCC ||
10587 CondOpcode == X86ISD::SETCC_CARRY) {
10588 CC = Cond.getOperand(0);
10590 SDValue Cmp = Cond.getOperand(1);
10591 unsigned Opc = Cmp.getOpcode();
10592 MVT VT = Op.getSimpleValueType();
10594 bool IllegalFPCMov = false;
10595 if (VT.isFloatingPoint() && !VT.isVector() &&
10596 !isScalarFPTypeInSSEReg(VT)) // FPStack?
10597 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
10599 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
10600 Opc == X86ISD::BT) { // FIXME
10604 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
10605 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
10606 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
10607 Cond.getOperand(0).getValueType() != MVT::i8)) {
10608 SDValue LHS = Cond.getOperand(0);
10609 SDValue RHS = Cond.getOperand(1);
10610 unsigned X86Opcode;
10613 switch (CondOpcode) {
10614 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
10615 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
10616 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
10617 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
10618 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
10619 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
10620 default: llvm_unreachable("unexpected overflowing operator");
10622 if (CondOpcode == ISD::UMULO)
10623 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
10626 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
10628 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
10630 if (CondOpcode == ISD::UMULO)
10631 Cond = X86Op.getValue(2);
10633 Cond = X86Op.getValue(1);
10635 CC = DAG.getConstant(X86Cond, MVT::i8);
10640 // Look pass the truncate if the high bits are known zero.
10641 if (isTruncWithZeroHighBitsInput(Cond, DAG))
10642 Cond = Cond.getOperand(0);
10644 // We know the result of AND is compared against zero. Try to match
10646 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
10647 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
10648 if (NewSetCC.getNode()) {
10649 CC = NewSetCC.getOperand(0);
10650 Cond = NewSetCC.getOperand(1);
10657 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
10658 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
10661 // a < b ? -1 : 0 -> RES = ~setcc_carry
10662 // a < b ? 0 : -1 -> RES = setcc_carry
10663 // a >= b ? -1 : 0 -> RES = setcc_carry
10664 // a >= b ? 0 : -1 -> RES = ~setcc_carry
10665 if (Cond.getOpcode() == X86ISD::SUB) {
10666 Cond = ConvertCmpIfNecessary(Cond, DAG);
10667 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
10669 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
10670 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
10671 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
10672 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
10673 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
10674 return DAG.getNOT(DL, Res, Res.getValueType());
10679 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
10680 // widen the cmov and push the truncate through. This avoids introducing a new
10681 // branch during isel and doesn't add any extensions.
10682 if (Op.getValueType() == MVT::i8 &&
10683 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
10684 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
10685 if (T1.getValueType() == T2.getValueType() &&
10686 // Blacklist CopyFromReg to avoid partial register stalls.
10687 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
10688 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
10689 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
10690 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
10694 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
10695 // condition is true.
10696 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
10697 SDValue Ops[] = { Op2, Op1, CC, Cond };
10698 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops));
10701 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, SelectionDAG &DAG) {
10702 MVT VT = Op->getSimpleValueType(0);
10703 SDValue In = Op->getOperand(0);
10704 MVT InVT = In.getSimpleValueType();
10707 unsigned int NumElts = VT.getVectorNumElements();
10708 if (NumElts != 8 && NumElts != 16)
10711 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
10712 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
10714 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
10715 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
10717 MVT ExtVT = (NumElts == 8) ? MVT::v8i64 : MVT::v16i32;
10718 Constant *C = ConstantInt::get(*DAG.getContext(),
10719 APInt::getAllOnesValue(ExtVT.getScalarType().getSizeInBits()));
10721 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
10722 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
10723 SDValue Ld = DAG.getLoad(ExtVT.getScalarType(), dl, DAG.getEntryNode(), CP,
10724 MachinePointerInfo::getConstantPool(),
10725 false, false, false, Alignment);
10726 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, dl, ExtVT, In, Ld);
10727 if (VT.is512BitVector())
10729 return DAG.getNode(X86ISD::VTRUNC, dl, VT, Brcst);
10732 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
10733 SelectionDAG &DAG) {
10734 MVT VT = Op->getSimpleValueType(0);
10735 SDValue In = Op->getOperand(0);
10736 MVT InVT = In.getSimpleValueType();
10739 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
10740 return LowerSIGN_EXTEND_AVX512(Op, DAG);
10742 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
10743 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
10744 (VT != MVT::v16i16 || InVT != MVT::v16i8))
10747 if (Subtarget->hasInt256())
10748 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
10750 // Optimize vectors in AVX mode
10751 // Sign extend v8i16 to v8i32 and
10754 // Divide input vector into two parts
10755 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
10756 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
10757 // concat the vectors to original VT
10759 unsigned NumElems = InVT.getVectorNumElements();
10760 SDValue Undef = DAG.getUNDEF(InVT);
10762 SmallVector<int,8> ShufMask1(NumElems, -1);
10763 for (unsigned i = 0; i != NumElems/2; ++i)
10766 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
10768 SmallVector<int,8> ShufMask2(NumElems, -1);
10769 for (unsigned i = 0; i != NumElems/2; ++i)
10770 ShufMask2[i] = i + NumElems/2;
10772 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
10774 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
10775 VT.getVectorNumElements()/2);
10777 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
10778 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
10780 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
10783 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
10784 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
10785 // from the AND / OR.
10786 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
10787 Opc = Op.getOpcode();
10788 if (Opc != ISD::OR && Opc != ISD::AND)
10790 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
10791 Op.getOperand(0).hasOneUse() &&
10792 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
10793 Op.getOperand(1).hasOneUse());
10796 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
10797 // 1 and that the SETCC node has a single use.
10798 static bool isXor1OfSetCC(SDValue Op) {
10799 if (Op.getOpcode() != ISD::XOR)
10801 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
10802 if (N1C && N1C->getAPIntValue() == 1) {
10803 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
10804 Op.getOperand(0).hasOneUse();
10809 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
10810 bool addTest = true;
10811 SDValue Chain = Op.getOperand(0);
10812 SDValue Cond = Op.getOperand(1);
10813 SDValue Dest = Op.getOperand(2);
10816 bool Inverted = false;
10818 if (Cond.getOpcode() == ISD::SETCC) {
10819 // Check for setcc([su]{add,sub,mul}o == 0).
10820 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
10821 isa<ConstantSDNode>(Cond.getOperand(1)) &&
10822 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
10823 Cond.getOperand(0).getResNo() == 1 &&
10824 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
10825 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
10826 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
10827 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
10828 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
10829 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
10831 Cond = Cond.getOperand(0);
10833 SDValue NewCond = LowerSETCC(Cond, DAG);
10834 if (NewCond.getNode())
10839 // FIXME: LowerXALUO doesn't handle these!!
10840 else if (Cond.getOpcode() == X86ISD::ADD ||
10841 Cond.getOpcode() == X86ISD::SUB ||
10842 Cond.getOpcode() == X86ISD::SMUL ||
10843 Cond.getOpcode() == X86ISD::UMUL)
10844 Cond = LowerXALUO(Cond, DAG);
10847 // Look pass (and (setcc_carry (cmp ...)), 1).
10848 if (Cond.getOpcode() == ISD::AND &&
10849 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
10850 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
10851 if (C && C->getAPIntValue() == 1)
10852 Cond = Cond.getOperand(0);
10855 // If condition flag is set by a X86ISD::CMP, then use it as the condition
10856 // setting operand in place of the X86ISD::SETCC.
10857 unsigned CondOpcode = Cond.getOpcode();
10858 if (CondOpcode == X86ISD::SETCC ||
10859 CondOpcode == X86ISD::SETCC_CARRY) {
10860 CC = Cond.getOperand(0);
10862 SDValue Cmp = Cond.getOperand(1);
10863 unsigned Opc = Cmp.getOpcode();
10864 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
10865 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
10869 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
10873 // These can only come from an arithmetic instruction with overflow,
10874 // e.g. SADDO, UADDO.
10875 Cond = Cond.getNode()->getOperand(1);
10881 CondOpcode = Cond.getOpcode();
10882 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
10883 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
10884 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
10885 Cond.getOperand(0).getValueType() != MVT::i8)) {
10886 SDValue LHS = Cond.getOperand(0);
10887 SDValue RHS = Cond.getOperand(1);
10888 unsigned X86Opcode;
10891 // Keep this in sync with LowerXALUO, otherwise we might create redundant
10892 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
10894 switch (CondOpcode) {
10895 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
10897 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
10899 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
10902 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
10903 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
10905 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
10907 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
10910 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
10911 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
10912 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
10913 default: llvm_unreachable("unexpected overflowing operator");
10916 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
10917 if (CondOpcode == ISD::UMULO)
10918 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
10921 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
10923 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
10925 if (CondOpcode == ISD::UMULO)
10926 Cond = X86Op.getValue(2);
10928 Cond = X86Op.getValue(1);
10930 CC = DAG.getConstant(X86Cond, MVT::i8);
10934 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
10935 SDValue Cmp = Cond.getOperand(0).getOperand(1);
10936 if (CondOpc == ISD::OR) {
10937 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
10938 // two branches instead of an explicit OR instruction with a
10940 if (Cmp == Cond.getOperand(1).getOperand(1) &&
10941 isX86LogicalCmp(Cmp)) {
10942 CC = Cond.getOperand(0).getOperand(0);
10943 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10944 Chain, Dest, CC, Cmp);
10945 CC = Cond.getOperand(1).getOperand(0);
10949 } else { // ISD::AND
10950 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
10951 // two branches instead of an explicit AND instruction with a
10952 // separate test. However, we only do this if this block doesn't
10953 // have a fall-through edge, because this requires an explicit
10954 // jmp when the condition is false.
10955 if (Cmp == Cond.getOperand(1).getOperand(1) &&
10956 isX86LogicalCmp(Cmp) &&
10957 Op.getNode()->hasOneUse()) {
10958 X86::CondCode CCode =
10959 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
10960 CCode = X86::GetOppositeBranchCondition(CCode);
10961 CC = DAG.getConstant(CCode, MVT::i8);
10962 SDNode *User = *Op.getNode()->use_begin();
10963 // Look for an unconditional branch following this conditional branch.
10964 // We need this because we need to reverse the successors in order
10965 // to implement FCMP_OEQ.
10966 if (User->getOpcode() == ISD::BR) {
10967 SDValue FalseBB = User->getOperand(1);
10969 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
10970 assert(NewBR == User);
10974 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10975 Chain, Dest, CC, Cmp);
10976 X86::CondCode CCode =
10977 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
10978 CCode = X86::GetOppositeBranchCondition(CCode);
10979 CC = DAG.getConstant(CCode, MVT::i8);
10985 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
10986 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
10987 // It should be transformed during dag combiner except when the condition
10988 // is set by a arithmetics with overflow node.
10989 X86::CondCode CCode =
10990 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
10991 CCode = X86::GetOppositeBranchCondition(CCode);
10992 CC = DAG.getConstant(CCode, MVT::i8);
10993 Cond = Cond.getOperand(0).getOperand(1);
10995 } else if (Cond.getOpcode() == ISD::SETCC &&
10996 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
10997 // For FCMP_OEQ, we can emit
10998 // two branches instead of an explicit AND instruction with a
10999 // separate test. However, we only do this if this block doesn't
11000 // have a fall-through edge, because this requires an explicit
11001 // jmp when the condition is false.
11002 if (Op.getNode()->hasOneUse()) {
11003 SDNode *User = *Op.getNode()->use_begin();
11004 // Look for an unconditional branch following this conditional branch.
11005 // We need this because we need to reverse the successors in order
11006 // to implement FCMP_OEQ.
11007 if (User->getOpcode() == ISD::BR) {
11008 SDValue FalseBB = User->getOperand(1);
11010 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
11011 assert(NewBR == User);
11015 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
11016 Cond.getOperand(0), Cond.getOperand(1));
11017 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
11018 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
11019 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
11020 Chain, Dest, CC, Cmp);
11021 CC = DAG.getConstant(X86::COND_P, MVT::i8);
11026 } else if (Cond.getOpcode() == ISD::SETCC &&
11027 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
11028 // For FCMP_UNE, we can emit
11029 // two branches instead of an explicit AND instruction with a
11030 // separate test. However, we only do this if this block doesn't
11031 // have a fall-through edge, because this requires an explicit
11032 // jmp when the condition is false.
11033 if (Op.getNode()->hasOneUse()) {
11034 SDNode *User = *Op.getNode()->use_begin();
11035 // Look for an unconditional branch following this conditional branch.
11036 // We need this because we need to reverse the successors in order
11037 // to implement FCMP_UNE.
11038 if (User->getOpcode() == ISD::BR) {
11039 SDValue FalseBB = User->getOperand(1);
11041 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
11042 assert(NewBR == User);
11045 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
11046 Cond.getOperand(0), Cond.getOperand(1));
11047 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
11048 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
11049 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
11050 Chain, Dest, CC, Cmp);
11051 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
11061 // Look pass the truncate if the high bits are known zero.
11062 if (isTruncWithZeroHighBitsInput(Cond, DAG))
11063 Cond = Cond.getOperand(0);
11065 // We know the result of AND is compared against zero. Try to match
11067 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
11068 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
11069 if (NewSetCC.getNode()) {
11070 CC = NewSetCC.getOperand(0);
11071 Cond = NewSetCC.getOperand(1);
11078 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
11079 Cond = EmitTest(Cond, X86::COND_NE, dl, DAG);
11081 Cond = ConvertCmpIfNecessary(Cond, DAG);
11082 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
11083 Chain, Dest, CC, Cond);
11086 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
11087 // Calls to _alloca is needed to probe the stack when allocating more than 4k
11088 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
11089 // that the guard pages used by the OS virtual memory manager are allocated in
11090 // correct sequence.
11092 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
11093 SelectionDAG &DAG) const {
11094 MachineFunction &MF = DAG.getMachineFunction();
11095 bool SplitStack = MF.shouldSplitStack();
11096 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMacho()) ||
11101 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11102 SDNode* Node = Op.getNode();
11104 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
11105 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
11106 " not tell us which reg is the stack pointer!");
11107 EVT VT = Node->getValueType(0);
11108 SDValue Tmp1 = SDValue(Node, 0);
11109 SDValue Tmp2 = SDValue(Node, 1);
11110 SDValue Tmp3 = Node->getOperand(2);
11111 SDValue Chain = Tmp1.getOperand(0);
11113 // Chain the dynamic stack allocation so that it doesn't modify the stack
11114 // pointer when other instructions are using the stack.
11115 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true),
11118 SDValue Size = Tmp2.getOperand(1);
11119 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
11120 Chain = SP.getValue(1);
11121 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
11122 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering();
11123 unsigned StackAlign = TFI.getStackAlignment();
11124 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
11125 if (Align > StackAlign)
11126 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
11127 DAG.getConstant(-(uint64_t)Align, VT));
11128 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
11130 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
11131 DAG.getIntPtrConstant(0, true), SDValue(),
11134 SDValue Ops[2] = { Tmp1, Tmp2 };
11135 return DAG.getMergeValues(Ops, 2, dl);
11139 SDValue Chain = Op.getOperand(0);
11140 SDValue Size = Op.getOperand(1);
11141 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
11142 EVT VT = Op.getNode()->getValueType(0);
11144 bool Is64Bit = Subtarget->is64Bit();
11145 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32;
11148 MachineRegisterInfo &MRI = MF.getRegInfo();
11151 // The 64 bit implementation of segmented stacks needs to clobber both r10
11152 // r11. This makes it impossible to use it along with nested parameters.
11153 const Function *F = MF.getFunction();
11155 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
11157 if (I->hasNestAttr())
11158 report_fatal_error("Cannot use segmented stacks with functions that "
11159 "have nested arguments.");
11162 const TargetRegisterClass *AddrRegClass =
11163 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32);
11164 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
11165 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
11166 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
11167 DAG.getRegister(Vreg, SPTy));
11168 SDValue Ops1[2] = { Value, Chain };
11169 return DAG.getMergeValues(Ops1, 2, dl);
11172 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
11174 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
11175 Flag = Chain.getValue(1);
11176 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
11178 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
11180 const X86RegisterInfo *RegInfo =
11181 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
11182 unsigned SPReg = RegInfo->getStackRegister();
11183 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
11184 Chain = SP.getValue(1);
11187 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
11188 DAG.getConstant(-(uint64_t)Align, VT));
11189 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
11192 SDValue Ops1[2] = { SP, Chain };
11193 return DAG.getMergeValues(Ops1, 2, dl);
11197 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
11198 MachineFunction &MF = DAG.getMachineFunction();
11199 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
11201 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
11204 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
11205 // vastart just stores the address of the VarArgsFrameIndex slot into the
11206 // memory location argument.
11207 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
11209 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
11210 MachinePointerInfo(SV), false, false, 0);
11214 // gp_offset (0 - 6 * 8)
11215 // fp_offset (48 - 48 + 8 * 16)
11216 // overflow_arg_area (point to parameters coming in memory).
11218 SmallVector<SDValue, 8> MemOps;
11219 SDValue FIN = Op.getOperand(1);
11221 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
11222 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
11224 FIN, MachinePointerInfo(SV), false, false, 0);
11225 MemOps.push_back(Store);
11228 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11229 FIN, DAG.getIntPtrConstant(4));
11230 Store = DAG.getStore(Op.getOperand(0), DL,
11231 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
11233 FIN, MachinePointerInfo(SV, 4), false, false, 0);
11234 MemOps.push_back(Store);
11236 // Store ptr to overflow_arg_area
11237 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11238 FIN, DAG.getIntPtrConstant(4));
11239 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
11241 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
11242 MachinePointerInfo(SV, 8),
11244 MemOps.push_back(Store);
11246 // Store ptr to reg_save_area.
11247 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11248 FIN, DAG.getIntPtrConstant(8));
11249 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
11251 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
11252 MachinePointerInfo(SV, 16), false, false, 0);
11253 MemOps.push_back(Store);
11254 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
11255 &MemOps[0], MemOps.size());
11258 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
11259 assert(Subtarget->is64Bit() &&
11260 "LowerVAARG only handles 64-bit va_arg!");
11261 assert((Subtarget->isTargetLinux() ||
11262 Subtarget->isTargetDarwin()) &&
11263 "Unhandled target in LowerVAARG");
11264 assert(Op.getNode()->getNumOperands() == 4);
11265 SDValue Chain = Op.getOperand(0);
11266 SDValue SrcPtr = Op.getOperand(1);
11267 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
11268 unsigned Align = Op.getConstantOperandVal(3);
11271 EVT ArgVT = Op.getNode()->getValueType(0);
11272 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
11273 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
11276 // Decide which area this value should be read from.
11277 // TODO: Implement the AMD64 ABI in its entirety. This simple
11278 // selection mechanism works only for the basic types.
11279 if (ArgVT == MVT::f80) {
11280 llvm_unreachable("va_arg for f80 not yet implemented");
11281 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
11282 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
11283 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
11284 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
11286 llvm_unreachable("Unhandled argument type in LowerVAARG");
11289 if (ArgMode == 2) {
11290 // Sanity Check: Make sure using fp_offset makes sense.
11291 assert(!getTargetMachine().Options.UseSoftFloat &&
11292 !(DAG.getMachineFunction()
11293 .getFunction()->getAttributes()
11294 .hasAttribute(AttributeSet::FunctionIndex,
11295 Attribute::NoImplicitFloat)) &&
11296 Subtarget->hasSSE1());
11299 // Insert VAARG_64 node into the DAG
11300 // VAARG_64 returns two values: Variable Argument Address, Chain
11301 SmallVector<SDValue, 11> InstOps;
11302 InstOps.push_back(Chain);
11303 InstOps.push_back(SrcPtr);
11304 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
11305 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
11306 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
11307 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
11308 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
11309 VTs, &InstOps[0], InstOps.size(),
11311 MachinePointerInfo(SV),
11313 /*Volatile=*/false,
11315 /*WriteMem=*/true);
11316 Chain = VAARG.getValue(1);
11318 // Load the next argument and return it
11319 return DAG.getLoad(ArgVT, dl,
11322 MachinePointerInfo(),
11323 false, false, false, 0);
11326 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
11327 SelectionDAG &DAG) {
11328 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
11329 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
11330 SDValue Chain = Op.getOperand(0);
11331 SDValue DstPtr = Op.getOperand(1);
11332 SDValue SrcPtr = Op.getOperand(2);
11333 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
11334 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
11337 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
11338 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
11340 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
11343 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
11344 // amount is a constant. Takes immediate version of shift as input.
11345 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
11346 SDValue SrcOp, uint64_t ShiftAmt,
11347 SelectionDAG &DAG) {
11348 MVT ElementType = VT.getVectorElementType();
11350 // Check for ShiftAmt >= element width
11351 if (ShiftAmt >= ElementType.getSizeInBits()) {
11352 if (Opc == X86ISD::VSRAI)
11353 ShiftAmt = ElementType.getSizeInBits() - 1;
11355 return DAG.getConstant(0, VT);
11358 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
11359 && "Unknown target vector shift-by-constant node");
11361 // Fold this packed vector shift into a build vector if SrcOp is a
11362 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
11363 if (VT == SrcOp.getSimpleValueType() &&
11364 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
11365 SmallVector<SDValue, 8> Elts;
11366 unsigned NumElts = SrcOp->getNumOperands();
11367 ConstantSDNode *ND;
11370 default: llvm_unreachable(0);
11371 case X86ISD::VSHLI:
11372 for (unsigned i=0; i!=NumElts; ++i) {
11373 SDValue CurrentOp = SrcOp->getOperand(i);
11374 if (CurrentOp->getOpcode() == ISD::UNDEF) {
11375 Elts.push_back(CurrentOp);
11378 ND = cast<ConstantSDNode>(CurrentOp);
11379 const APInt &C = ND->getAPIntValue();
11380 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), ElementType));
11383 case X86ISD::VSRLI:
11384 for (unsigned i=0; i!=NumElts; ++i) {
11385 SDValue CurrentOp = SrcOp->getOperand(i);
11386 if (CurrentOp->getOpcode() == ISD::UNDEF) {
11387 Elts.push_back(CurrentOp);
11390 ND = cast<ConstantSDNode>(CurrentOp);
11391 const APInt &C = ND->getAPIntValue();
11392 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), ElementType));
11395 case X86ISD::VSRAI:
11396 for (unsigned i=0; i!=NumElts; ++i) {
11397 SDValue CurrentOp = SrcOp->getOperand(i);
11398 if (CurrentOp->getOpcode() == ISD::UNDEF) {
11399 Elts.push_back(CurrentOp);
11402 ND = cast<ConstantSDNode>(CurrentOp);
11403 const APInt &C = ND->getAPIntValue();
11404 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), ElementType));
11409 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Elts[0], NumElts);
11412 return DAG.getNode(Opc, dl, VT, SrcOp, DAG.getConstant(ShiftAmt, MVT::i8));
11415 // getTargetVShiftNode - Handle vector element shifts where the shift amount
11416 // may or may not be a constant. Takes immediate version of shift as input.
11417 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
11418 SDValue SrcOp, SDValue ShAmt,
11419 SelectionDAG &DAG) {
11420 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
11422 // Catch shift-by-constant.
11423 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
11424 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
11425 CShAmt->getZExtValue(), DAG);
11427 // Change opcode to non-immediate version
11429 default: llvm_unreachable("Unknown target vector shift node");
11430 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
11431 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
11432 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
11435 // Need to build a vector containing shift amount
11436 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
11439 ShOps[1] = DAG.getConstant(0, MVT::i32);
11440 ShOps[2] = ShOps[3] = DAG.getUNDEF(MVT::i32);
11441 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, &ShOps[0], 4);
11443 // The return type has to be a 128-bit type with the same element
11444 // type as the input type.
11445 MVT EltVT = VT.getVectorElementType();
11446 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
11448 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
11449 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
11452 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
11454 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
11456 default: return SDValue(); // Don't custom lower most intrinsics.
11457 // Comparison intrinsics.
11458 case Intrinsic::x86_sse_comieq_ss:
11459 case Intrinsic::x86_sse_comilt_ss:
11460 case Intrinsic::x86_sse_comile_ss:
11461 case Intrinsic::x86_sse_comigt_ss:
11462 case Intrinsic::x86_sse_comige_ss:
11463 case Intrinsic::x86_sse_comineq_ss:
11464 case Intrinsic::x86_sse_ucomieq_ss:
11465 case Intrinsic::x86_sse_ucomilt_ss:
11466 case Intrinsic::x86_sse_ucomile_ss:
11467 case Intrinsic::x86_sse_ucomigt_ss:
11468 case Intrinsic::x86_sse_ucomige_ss:
11469 case Intrinsic::x86_sse_ucomineq_ss:
11470 case Intrinsic::x86_sse2_comieq_sd:
11471 case Intrinsic::x86_sse2_comilt_sd:
11472 case Intrinsic::x86_sse2_comile_sd:
11473 case Intrinsic::x86_sse2_comigt_sd:
11474 case Intrinsic::x86_sse2_comige_sd:
11475 case Intrinsic::x86_sse2_comineq_sd:
11476 case Intrinsic::x86_sse2_ucomieq_sd:
11477 case Intrinsic::x86_sse2_ucomilt_sd:
11478 case Intrinsic::x86_sse2_ucomile_sd:
11479 case Intrinsic::x86_sse2_ucomigt_sd:
11480 case Intrinsic::x86_sse2_ucomige_sd:
11481 case Intrinsic::x86_sse2_ucomineq_sd: {
11485 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11486 case Intrinsic::x86_sse_comieq_ss:
11487 case Intrinsic::x86_sse2_comieq_sd:
11488 Opc = X86ISD::COMI;
11491 case Intrinsic::x86_sse_comilt_ss:
11492 case Intrinsic::x86_sse2_comilt_sd:
11493 Opc = X86ISD::COMI;
11496 case Intrinsic::x86_sse_comile_ss:
11497 case Intrinsic::x86_sse2_comile_sd:
11498 Opc = X86ISD::COMI;
11501 case Intrinsic::x86_sse_comigt_ss:
11502 case Intrinsic::x86_sse2_comigt_sd:
11503 Opc = X86ISD::COMI;
11506 case Intrinsic::x86_sse_comige_ss:
11507 case Intrinsic::x86_sse2_comige_sd:
11508 Opc = X86ISD::COMI;
11511 case Intrinsic::x86_sse_comineq_ss:
11512 case Intrinsic::x86_sse2_comineq_sd:
11513 Opc = X86ISD::COMI;
11516 case Intrinsic::x86_sse_ucomieq_ss:
11517 case Intrinsic::x86_sse2_ucomieq_sd:
11518 Opc = X86ISD::UCOMI;
11521 case Intrinsic::x86_sse_ucomilt_ss:
11522 case Intrinsic::x86_sse2_ucomilt_sd:
11523 Opc = X86ISD::UCOMI;
11526 case Intrinsic::x86_sse_ucomile_ss:
11527 case Intrinsic::x86_sse2_ucomile_sd:
11528 Opc = X86ISD::UCOMI;
11531 case Intrinsic::x86_sse_ucomigt_ss:
11532 case Intrinsic::x86_sse2_ucomigt_sd:
11533 Opc = X86ISD::UCOMI;
11536 case Intrinsic::x86_sse_ucomige_ss:
11537 case Intrinsic::x86_sse2_ucomige_sd:
11538 Opc = X86ISD::UCOMI;
11541 case Intrinsic::x86_sse_ucomineq_ss:
11542 case Intrinsic::x86_sse2_ucomineq_sd:
11543 Opc = X86ISD::UCOMI;
11548 SDValue LHS = Op.getOperand(1);
11549 SDValue RHS = Op.getOperand(2);
11550 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
11551 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
11552 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
11553 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
11554 DAG.getConstant(X86CC, MVT::i8), Cond);
11555 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
11558 // Arithmetic intrinsics.
11559 case Intrinsic::x86_sse2_pmulu_dq:
11560 case Intrinsic::x86_avx2_pmulu_dq:
11561 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
11562 Op.getOperand(1), Op.getOperand(2));
11564 // SSE2/AVX2 sub with unsigned saturation intrinsics
11565 case Intrinsic::x86_sse2_psubus_b:
11566 case Intrinsic::x86_sse2_psubus_w:
11567 case Intrinsic::x86_avx2_psubus_b:
11568 case Intrinsic::x86_avx2_psubus_w:
11569 return DAG.getNode(X86ISD::SUBUS, dl, Op.getValueType(),
11570 Op.getOperand(1), Op.getOperand(2));
11572 // SSE3/AVX horizontal add/sub intrinsics
11573 case Intrinsic::x86_sse3_hadd_ps:
11574 case Intrinsic::x86_sse3_hadd_pd:
11575 case Intrinsic::x86_avx_hadd_ps_256:
11576 case Intrinsic::x86_avx_hadd_pd_256:
11577 case Intrinsic::x86_sse3_hsub_ps:
11578 case Intrinsic::x86_sse3_hsub_pd:
11579 case Intrinsic::x86_avx_hsub_ps_256:
11580 case Intrinsic::x86_avx_hsub_pd_256:
11581 case Intrinsic::x86_ssse3_phadd_w_128:
11582 case Intrinsic::x86_ssse3_phadd_d_128:
11583 case Intrinsic::x86_avx2_phadd_w:
11584 case Intrinsic::x86_avx2_phadd_d:
11585 case Intrinsic::x86_ssse3_phsub_w_128:
11586 case Intrinsic::x86_ssse3_phsub_d_128:
11587 case Intrinsic::x86_avx2_phsub_w:
11588 case Intrinsic::x86_avx2_phsub_d: {
11591 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11592 case Intrinsic::x86_sse3_hadd_ps:
11593 case Intrinsic::x86_sse3_hadd_pd:
11594 case Intrinsic::x86_avx_hadd_ps_256:
11595 case Intrinsic::x86_avx_hadd_pd_256:
11596 Opcode = X86ISD::FHADD;
11598 case Intrinsic::x86_sse3_hsub_ps:
11599 case Intrinsic::x86_sse3_hsub_pd:
11600 case Intrinsic::x86_avx_hsub_ps_256:
11601 case Intrinsic::x86_avx_hsub_pd_256:
11602 Opcode = X86ISD::FHSUB;
11604 case Intrinsic::x86_ssse3_phadd_w_128:
11605 case Intrinsic::x86_ssse3_phadd_d_128:
11606 case Intrinsic::x86_avx2_phadd_w:
11607 case Intrinsic::x86_avx2_phadd_d:
11608 Opcode = X86ISD::HADD;
11610 case Intrinsic::x86_ssse3_phsub_w_128:
11611 case Intrinsic::x86_ssse3_phsub_d_128:
11612 case Intrinsic::x86_avx2_phsub_w:
11613 case Intrinsic::x86_avx2_phsub_d:
11614 Opcode = X86ISD::HSUB;
11617 return DAG.getNode(Opcode, dl, Op.getValueType(),
11618 Op.getOperand(1), Op.getOperand(2));
11621 // SSE2/SSE41/AVX2 integer max/min intrinsics.
11622 case Intrinsic::x86_sse2_pmaxu_b:
11623 case Intrinsic::x86_sse41_pmaxuw:
11624 case Intrinsic::x86_sse41_pmaxud:
11625 case Intrinsic::x86_avx2_pmaxu_b:
11626 case Intrinsic::x86_avx2_pmaxu_w:
11627 case Intrinsic::x86_avx2_pmaxu_d:
11628 case Intrinsic::x86_sse2_pminu_b:
11629 case Intrinsic::x86_sse41_pminuw:
11630 case Intrinsic::x86_sse41_pminud:
11631 case Intrinsic::x86_avx2_pminu_b:
11632 case Intrinsic::x86_avx2_pminu_w:
11633 case Intrinsic::x86_avx2_pminu_d:
11634 case Intrinsic::x86_sse41_pmaxsb:
11635 case Intrinsic::x86_sse2_pmaxs_w:
11636 case Intrinsic::x86_sse41_pmaxsd:
11637 case Intrinsic::x86_avx2_pmaxs_b:
11638 case Intrinsic::x86_avx2_pmaxs_w:
11639 case Intrinsic::x86_avx2_pmaxs_d:
11640 case Intrinsic::x86_sse41_pminsb:
11641 case Intrinsic::x86_sse2_pmins_w:
11642 case Intrinsic::x86_sse41_pminsd:
11643 case Intrinsic::x86_avx2_pmins_b:
11644 case Intrinsic::x86_avx2_pmins_w:
11645 case Intrinsic::x86_avx2_pmins_d: {
11648 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11649 case Intrinsic::x86_sse2_pmaxu_b:
11650 case Intrinsic::x86_sse41_pmaxuw:
11651 case Intrinsic::x86_sse41_pmaxud:
11652 case Intrinsic::x86_avx2_pmaxu_b:
11653 case Intrinsic::x86_avx2_pmaxu_w:
11654 case Intrinsic::x86_avx2_pmaxu_d:
11655 Opcode = X86ISD::UMAX;
11657 case Intrinsic::x86_sse2_pminu_b:
11658 case Intrinsic::x86_sse41_pminuw:
11659 case Intrinsic::x86_sse41_pminud:
11660 case Intrinsic::x86_avx2_pminu_b:
11661 case Intrinsic::x86_avx2_pminu_w:
11662 case Intrinsic::x86_avx2_pminu_d:
11663 Opcode = X86ISD::UMIN;
11665 case Intrinsic::x86_sse41_pmaxsb:
11666 case Intrinsic::x86_sse2_pmaxs_w:
11667 case Intrinsic::x86_sse41_pmaxsd:
11668 case Intrinsic::x86_avx2_pmaxs_b:
11669 case Intrinsic::x86_avx2_pmaxs_w:
11670 case Intrinsic::x86_avx2_pmaxs_d:
11671 Opcode = X86ISD::SMAX;
11673 case Intrinsic::x86_sse41_pminsb:
11674 case Intrinsic::x86_sse2_pmins_w:
11675 case Intrinsic::x86_sse41_pminsd:
11676 case Intrinsic::x86_avx2_pmins_b:
11677 case Intrinsic::x86_avx2_pmins_w:
11678 case Intrinsic::x86_avx2_pmins_d:
11679 Opcode = X86ISD::SMIN;
11682 return DAG.getNode(Opcode, dl, Op.getValueType(),
11683 Op.getOperand(1), Op.getOperand(2));
11686 // SSE/SSE2/AVX floating point max/min intrinsics.
11687 case Intrinsic::x86_sse_max_ps:
11688 case Intrinsic::x86_sse2_max_pd:
11689 case Intrinsic::x86_avx_max_ps_256:
11690 case Intrinsic::x86_avx_max_pd_256:
11691 case Intrinsic::x86_sse_min_ps:
11692 case Intrinsic::x86_sse2_min_pd:
11693 case Intrinsic::x86_avx_min_ps_256:
11694 case Intrinsic::x86_avx_min_pd_256: {
11697 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11698 case Intrinsic::x86_sse_max_ps:
11699 case Intrinsic::x86_sse2_max_pd:
11700 case Intrinsic::x86_avx_max_ps_256:
11701 case Intrinsic::x86_avx_max_pd_256:
11702 Opcode = X86ISD::FMAX;
11704 case Intrinsic::x86_sse_min_ps:
11705 case Intrinsic::x86_sse2_min_pd:
11706 case Intrinsic::x86_avx_min_ps_256:
11707 case Intrinsic::x86_avx_min_pd_256:
11708 Opcode = X86ISD::FMIN;
11711 return DAG.getNode(Opcode, dl, Op.getValueType(),
11712 Op.getOperand(1), Op.getOperand(2));
11715 // AVX2 variable shift intrinsics
11716 case Intrinsic::x86_avx2_psllv_d:
11717 case Intrinsic::x86_avx2_psllv_q:
11718 case Intrinsic::x86_avx2_psllv_d_256:
11719 case Intrinsic::x86_avx2_psllv_q_256:
11720 case Intrinsic::x86_avx2_psrlv_d:
11721 case Intrinsic::x86_avx2_psrlv_q:
11722 case Intrinsic::x86_avx2_psrlv_d_256:
11723 case Intrinsic::x86_avx2_psrlv_q_256:
11724 case Intrinsic::x86_avx2_psrav_d:
11725 case Intrinsic::x86_avx2_psrav_d_256: {
11728 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11729 case Intrinsic::x86_avx2_psllv_d:
11730 case Intrinsic::x86_avx2_psllv_q:
11731 case Intrinsic::x86_avx2_psllv_d_256:
11732 case Intrinsic::x86_avx2_psllv_q_256:
11735 case Intrinsic::x86_avx2_psrlv_d:
11736 case Intrinsic::x86_avx2_psrlv_q:
11737 case Intrinsic::x86_avx2_psrlv_d_256:
11738 case Intrinsic::x86_avx2_psrlv_q_256:
11741 case Intrinsic::x86_avx2_psrav_d:
11742 case Intrinsic::x86_avx2_psrav_d_256:
11746 return DAG.getNode(Opcode, dl, Op.getValueType(),
11747 Op.getOperand(1), Op.getOperand(2));
11750 case Intrinsic::x86_ssse3_pshuf_b_128:
11751 case Intrinsic::x86_avx2_pshuf_b:
11752 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
11753 Op.getOperand(1), Op.getOperand(2));
11755 case Intrinsic::x86_ssse3_psign_b_128:
11756 case Intrinsic::x86_ssse3_psign_w_128:
11757 case Intrinsic::x86_ssse3_psign_d_128:
11758 case Intrinsic::x86_avx2_psign_b:
11759 case Intrinsic::x86_avx2_psign_w:
11760 case Intrinsic::x86_avx2_psign_d:
11761 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
11762 Op.getOperand(1), Op.getOperand(2));
11764 case Intrinsic::x86_sse41_insertps:
11765 return DAG.getNode(X86ISD::INSERTPS, dl, Op.getValueType(),
11766 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
11768 case Intrinsic::x86_avx_vperm2f128_ps_256:
11769 case Intrinsic::x86_avx_vperm2f128_pd_256:
11770 case Intrinsic::x86_avx_vperm2f128_si_256:
11771 case Intrinsic::x86_avx2_vperm2i128:
11772 return DAG.getNode(X86ISD::VPERM2X128, dl, Op.getValueType(),
11773 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
11775 case Intrinsic::x86_avx2_permd:
11776 case Intrinsic::x86_avx2_permps:
11777 // Operands intentionally swapped. Mask is last operand to intrinsic,
11778 // but second operand for node/instruction.
11779 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
11780 Op.getOperand(2), Op.getOperand(1));
11782 case Intrinsic::x86_sse_sqrt_ps:
11783 case Intrinsic::x86_sse2_sqrt_pd:
11784 case Intrinsic::x86_avx_sqrt_ps_256:
11785 case Intrinsic::x86_avx_sqrt_pd_256:
11786 return DAG.getNode(ISD::FSQRT, dl, Op.getValueType(), Op.getOperand(1));
11788 // ptest and testp intrinsics. The intrinsic these come from are designed to
11789 // return an integer value, not just an instruction so lower it to the ptest
11790 // or testp pattern and a setcc for the result.
11791 case Intrinsic::x86_sse41_ptestz:
11792 case Intrinsic::x86_sse41_ptestc:
11793 case Intrinsic::x86_sse41_ptestnzc:
11794 case Intrinsic::x86_avx_ptestz_256:
11795 case Intrinsic::x86_avx_ptestc_256:
11796 case Intrinsic::x86_avx_ptestnzc_256:
11797 case Intrinsic::x86_avx_vtestz_ps:
11798 case Intrinsic::x86_avx_vtestc_ps:
11799 case Intrinsic::x86_avx_vtestnzc_ps:
11800 case Intrinsic::x86_avx_vtestz_pd:
11801 case Intrinsic::x86_avx_vtestc_pd:
11802 case Intrinsic::x86_avx_vtestnzc_pd:
11803 case Intrinsic::x86_avx_vtestz_ps_256:
11804 case Intrinsic::x86_avx_vtestc_ps_256:
11805 case Intrinsic::x86_avx_vtestnzc_ps_256:
11806 case Intrinsic::x86_avx_vtestz_pd_256:
11807 case Intrinsic::x86_avx_vtestc_pd_256:
11808 case Intrinsic::x86_avx_vtestnzc_pd_256: {
11809 bool IsTestPacked = false;
11812 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
11813 case Intrinsic::x86_avx_vtestz_ps:
11814 case Intrinsic::x86_avx_vtestz_pd:
11815 case Intrinsic::x86_avx_vtestz_ps_256:
11816 case Intrinsic::x86_avx_vtestz_pd_256:
11817 IsTestPacked = true; // Fallthrough
11818 case Intrinsic::x86_sse41_ptestz:
11819 case Intrinsic::x86_avx_ptestz_256:
11821 X86CC = X86::COND_E;
11823 case Intrinsic::x86_avx_vtestc_ps:
11824 case Intrinsic::x86_avx_vtestc_pd:
11825 case Intrinsic::x86_avx_vtestc_ps_256:
11826 case Intrinsic::x86_avx_vtestc_pd_256:
11827 IsTestPacked = true; // Fallthrough
11828 case Intrinsic::x86_sse41_ptestc:
11829 case Intrinsic::x86_avx_ptestc_256:
11831 X86CC = X86::COND_B;
11833 case Intrinsic::x86_avx_vtestnzc_ps:
11834 case Intrinsic::x86_avx_vtestnzc_pd:
11835 case Intrinsic::x86_avx_vtestnzc_ps_256:
11836 case Intrinsic::x86_avx_vtestnzc_pd_256:
11837 IsTestPacked = true; // Fallthrough
11838 case Intrinsic::x86_sse41_ptestnzc:
11839 case Intrinsic::x86_avx_ptestnzc_256:
11841 X86CC = X86::COND_A;
11845 SDValue LHS = Op.getOperand(1);
11846 SDValue RHS = Op.getOperand(2);
11847 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
11848 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
11849 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
11850 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
11851 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
11853 case Intrinsic::x86_avx512_kortestz_w:
11854 case Intrinsic::x86_avx512_kortestc_w: {
11855 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
11856 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
11857 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
11858 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
11859 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
11860 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
11861 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
11864 // SSE/AVX shift intrinsics
11865 case Intrinsic::x86_sse2_psll_w:
11866 case Intrinsic::x86_sse2_psll_d:
11867 case Intrinsic::x86_sse2_psll_q:
11868 case Intrinsic::x86_avx2_psll_w:
11869 case Intrinsic::x86_avx2_psll_d:
11870 case Intrinsic::x86_avx2_psll_q:
11871 case Intrinsic::x86_sse2_psrl_w:
11872 case Intrinsic::x86_sse2_psrl_d:
11873 case Intrinsic::x86_sse2_psrl_q:
11874 case Intrinsic::x86_avx2_psrl_w:
11875 case Intrinsic::x86_avx2_psrl_d:
11876 case Intrinsic::x86_avx2_psrl_q:
11877 case Intrinsic::x86_sse2_psra_w:
11878 case Intrinsic::x86_sse2_psra_d:
11879 case Intrinsic::x86_avx2_psra_w:
11880 case Intrinsic::x86_avx2_psra_d: {
11883 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11884 case Intrinsic::x86_sse2_psll_w:
11885 case Intrinsic::x86_sse2_psll_d:
11886 case Intrinsic::x86_sse2_psll_q:
11887 case Intrinsic::x86_avx2_psll_w:
11888 case Intrinsic::x86_avx2_psll_d:
11889 case Intrinsic::x86_avx2_psll_q:
11890 Opcode = X86ISD::VSHL;
11892 case Intrinsic::x86_sse2_psrl_w:
11893 case Intrinsic::x86_sse2_psrl_d:
11894 case Intrinsic::x86_sse2_psrl_q:
11895 case Intrinsic::x86_avx2_psrl_w:
11896 case Intrinsic::x86_avx2_psrl_d:
11897 case Intrinsic::x86_avx2_psrl_q:
11898 Opcode = X86ISD::VSRL;
11900 case Intrinsic::x86_sse2_psra_w:
11901 case Intrinsic::x86_sse2_psra_d:
11902 case Intrinsic::x86_avx2_psra_w:
11903 case Intrinsic::x86_avx2_psra_d:
11904 Opcode = X86ISD::VSRA;
11907 return DAG.getNode(Opcode, dl, Op.getValueType(),
11908 Op.getOperand(1), Op.getOperand(2));
11911 // SSE/AVX immediate shift intrinsics
11912 case Intrinsic::x86_sse2_pslli_w:
11913 case Intrinsic::x86_sse2_pslli_d:
11914 case Intrinsic::x86_sse2_pslli_q:
11915 case Intrinsic::x86_avx2_pslli_w:
11916 case Intrinsic::x86_avx2_pslli_d:
11917 case Intrinsic::x86_avx2_pslli_q:
11918 case Intrinsic::x86_sse2_psrli_w:
11919 case Intrinsic::x86_sse2_psrli_d:
11920 case Intrinsic::x86_sse2_psrli_q:
11921 case Intrinsic::x86_avx2_psrli_w:
11922 case Intrinsic::x86_avx2_psrli_d:
11923 case Intrinsic::x86_avx2_psrli_q:
11924 case Intrinsic::x86_sse2_psrai_w:
11925 case Intrinsic::x86_sse2_psrai_d:
11926 case Intrinsic::x86_avx2_psrai_w:
11927 case Intrinsic::x86_avx2_psrai_d: {
11930 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11931 case Intrinsic::x86_sse2_pslli_w:
11932 case Intrinsic::x86_sse2_pslli_d:
11933 case Intrinsic::x86_sse2_pslli_q:
11934 case Intrinsic::x86_avx2_pslli_w:
11935 case Intrinsic::x86_avx2_pslli_d:
11936 case Intrinsic::x86_avx2_pslli_q:
11937 Opcode = X86ISD::VSHLI;
11939 case Intrinsic::x86_sse2_psrli_w:
11940 case Intrinsic::x86_sse2_psrli_d:
11941 case Intrinsic::x86_sse2_psrli_q:
11942 case Intrinsic::x86_avx2_psrli_w:
11943 case Intrinsic::x86_avx2_psrli_d:
11944 case Intrinsic::x86_avx2_psrli_q:
11945 Opcode = X86ISD::VSRLI;
11947 case Intrinsic::x86_sse2_psrai_w:
11948 case Intrinsic::x86_sse2_psrai_d:
11949 case Intrinsic::x86_avx2_psrai_w:
11950 case Intrinsic::x86_avx2_psrai_d:
11951 Opcode = X86ISD::VSRAI;
11954 return getTargetVShiftNode(Opcode, dl, Op.getSimpleValueType(),
11955 Op.getOperand(1), Op.getOperand(2), DAG);
11958 case Intrinsic::x86_sse42_pcmpistria128:
11959 case Intrinsic::x86_sse42_pcmpestria128:
11960 case Intrinsic::x86_sse42_pcmpistric128:
11961 case Intrinsic::x86_sse42_pcmpestric128:
11962 case Intrinsic::x86_sse42_pcmpistrio128:
11963 case Intrinsic::x86_sse42_pcmpestrio128:
11964 case Intrinsic::x86_sse42_pcmpistris128:
11965 case Intrinsic::x86_sse42_pcmpestris128:
11966 case Intrinsic::x86_sse42_pcmpistriz128:
11967 case Intrinsic::x86_sse42_pcmpestriz128: {
11971 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11972 case Intrinsic::x86_sse42_pcmpistria128:
11973 Opcode = X86ISD::PCMPISTRI;
11974 X86CC = X86::COND_A;
11976 case Intrinsic::x86_sse42_pcmpestria128:
11977 Opcode = X86ISD::PCMPESTRI;
11978 X86CC = X86::COND_A;
11980 case Intrinsic::x86_sse42_pcmpistric128:
11981 Opcode = X86ISD::PCMPISTRI;
11982 X86CC = X86::COND_B;
11984 case Intrinsic::x86_sse42_pcmpestric128:
11985 Opcode = X86ISD::PCMPESTRI;
11986 X86CC = X86::COND_B;
11988 case Intrinsic::x86_sse42_pcmpistrio128:
11989 Opcode = X86ISD::PCMPISTRI;
11990 X86CC = X86::COND_O;
11992 case Intrinsic::x86_sse42_pcmpestrio128:
11993 Opcode = X86ISD::PCMPESTRI;
11994 X86CC = X86::COND_O;
11996 case Intrinsic::x86_sse42_pcmpistris128:
11997 Opcode = X86ISD::PCMPISTRI;
11998 X86CC = X86::COND_S;
12000 case Intrinsic::x86_sse42_pcmpestris128:
12001 Opcode = X86ISD::PCMPESTRI;
12002 X86CC = X86::COND_S;
12004 case Intrinsic::x86_sse42_pcmpistriz128:
12005 Opcode = X86ISD::PCMPISTRI;
12006 X86CC = X86::COND_E;
12008 case Intrinsic::x86_sse42_pcmpestriz128:
12009 Opcode = X86ISD::PCMPESTRI;
12010 X86CC = X86::COND_E;
12013 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
12014 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
12015 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps.data(), NewOps.size());
12016 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
12017 DAG.getConstant(X86CC, MVT::i8),
12018 SDValue(PCMP.getNode(), 1));
12019 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
12022 case Intrinsic::x86_sse42_pcmpistri128:
12023 case Intrinsic::x86_sse42_pcmpestri128: {
12025 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
12026 Opcode = X86ISD::PCMPISTRI;
12028 Opcode = X86ISD::PCMPESTRI;
12030 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
12031 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
12032 return DAG.getNode(Opcode, dl, VTs, NewOps.data(), NewOps.size());
12034 case Intrinsic::x86_fma_vfmadd_ps:
12035 case Intrinsic::x86_fma_vfmadd_pd:
12036 case Intrinsic::x86_fma_vfmsub_ps:
12037 case Intrinsic::x86_fma_vfmsub_pd:
12038 case Intrinsic::x86_fma_vfnmadd_ps:
12039 case Intrinsic::x86_fma_vfnmadd_pd:
12040 case Intrinsic::x86_fma_vfnmsub_ps:
12041 case Intrinsic::x86_fma_vfnmsub_pd:
12042 case Intrinsic::x86_fma_vfmaddsub_ps:
12043 case Intrinsic::x86_fma_vfmaddsub_pd:
12044 case Intrinsic::x86_fma_vfmsubadd_ps:
12045 case Intrinsic::x86_fma_vfmsubadd_pd:
12046 case Intrinsic::x86_fma_vfmadd_ps_256:
12047 case Intrinsic::x86_fma_vfmadd_pd_256:
12048 case Intrinsic::x86_fma_vfmsub_ps_256:
12049 case Intrinsic::x86_fma_vfmsub_pd_256:
12050 case Intrinsic::x86_fma_vfnmadd_ps_256:
12051 case Intrinsic::x86_fma_vfnmadd_pd_256:
12052 case Intrinsic::x86_fma_vfnmsub_ps_256:
12053 case Intrinsic::x86_fma_vfnmsub_pd_256:
12054 case Intrinsic::x86_fma_vfmaddsub_ps_256:
12055 case Intrinsic::x86_fma_vfmaddsub_pd_256:
12056 case Intrinsic::x86_fma_vfmsubadd_ps_256:
12057 case Intrinsic::x86_fma_vfmsubadd_pd_256:
12058 case Intrinsic::x86_fma_vfmadd_ps_512:
12059 case Intrinsic::x86_fma_vfmadd_pd_512:
12060 case Intrinsic::x86_fma_vfmsub_ps_512:
12061 case Intrinsic::x86_fma_vfmsub_pd_512:
12062 case Intrinsic::x86_fma_vfnmadd_ps_512:
12063 case Intrinsic::x86_fma_vfnmadd_pd_512:
12064 case Intrinsic::x86_fma_vfnmsub_ps_512:
12065 case Intrinsic::x86_fma_vfnmsub_pd_512:
12066 case Intrinsic::x86_fma_vfmaddsub_ps_512:
12067 case Intrinsic::x86_fma_vfmaddsub_pd_512:
12068 case Intrinsic::x86_fma_vfmsubadd_ps_512:
12069 case Intrinsic::x86_fma_vfmsubadd_pd_512: {
12072 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
12073 case Intrinsic::x86_fma_vfmadd_ps:
12074 case Intrinsic::x86_fma_vfmadd_pd:
12075 case Intrinsic::x86_fma_vfmadd_ps_256:
12076 case Intrinsic::x86_fma_vfmadd_pd_256:
12077 case Intrinsic::x86_fma_vfmadd_ps_512:
12078 case Intrinsic::x86_fma_vfmadd_pd_512:
12079 Opc = X86ISD::FMADD;
12081 case Intrinsic::x86_fma_vfmsub_ps:
12082 case Intrinsic::x86_fma_vfmsub_pd:
12083 case Intrinsic::x86_fma_vfmsub_ps_256:
12084 case Intrinsic::x86_fma_vfmsub_pd_256:
12085 case Intrinsic::x86_fma_vfmsub_ps_512:
12086 case Intrinsic::x86_fma_vfmsub_pd_512:
12087 Opc = X86ISD::FMSUB;
12089 case Intrinsic::x86_fma_vfnmadd_ps:
12090 case Intrinsic::x86_fma_vfnmadd_pd:
12091 case Intrinsic::x86_fma_vfnmadd_ps_256:
12092 case Intrinsic::x86_fma_vfnmadd_pd_256:
12093 case Intrinsic::x86_fma_vfnmadd_ps_512:
12094 case Intrinsic::x86_fma_vfnmadd_pd_512:
12095 Opc = X86ISD::FNMADD;
12097 case Intrinsic::x86_fma_vfnmsub_ps:
12098 case Intrinsic::x86_fma_vfnmsub_pd:
12099 case Intrinsic::x86_fma_vfnmsub_ps_256:
12100 case Intrinsic::x86_fma_vfnmsub_pd_256:
12101 case Intrinsic::x86_fma_vfnmsub_ps_512:
12102 case Intrinsic::x86_fma_vfnmsub_pd_512:
12103 Opc = X86ISD::FNMSUB;
12105 case Intrinsic::x86_fma_vfmaddsub_ps:
12106 case Intrinsic::x86_fma_vfmaddsub_pd:
12107 case Intrinsic::x86_fma_vfmaddsub_ps_256:
12108 case Intrinsic::x86_fma_vfmaddsub_pd_256:
12109 case Intrinsic::x86_fma_vfmaddsub_ps_512:
12110 case Intrinsic::x86_fma_vfmaddsub_pd_512:
12111 Opc = X86ISD::FMADDSUB;
12113 case Intrinsic::x86_fma_vfmsubadd_ps:
12114 case Intrinsic::x86_fma_vfmsubadd_pd:
12115 case Intrinsic::x86_fma_vfmsubadd_ps_256:
12116 case Intrinsic::x86_fma_vfmsubadd_pd_256:
12117 case Intrinsic::x86_fma_vfmsubadd_ps_512:
12118 case Intrinsic::x86_fma_vfmsubadd_pd_512:
12119 Opc = X86ISD::FMSUBADD;
12123 return DAG.getNode(Opc, dl, Op.getValueType(), Op.getOperand(1),
12124 Op.getOperand(2), Op.getOperand(3));
12129 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
12130 SDValue Base, SDValue Index,
12131 SDValue ScaleOp, SDValue Chain,
12132 const X86Subtarget * Subtarget) {
12134 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
12135 assert(C && "Invalid scale type");
12136 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
12137 SDValue Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
12138 EVT MaskVT = MVT::getVectorVT(MVT::i1,
12139 Index.getSimpleValueType().getVectorNumElements());
12140 SDValue MaskInReg = DAG.getConstant(~0, MaskVT);
12141 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
12142 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
12143 SDValue Segment = DAG.getRegister(0, MVT::i32);
12144 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
12145 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
12146 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
12147 return DAG.getMergeValues(RetOps, array_lengthof(RetOps), dl);
12150 static SDValue getMGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
12151 SDValue Src, SDValue Mask, SDValue Base,
12152 SDValue Index, SDValue ScaleOp, SDValue Chain,
12153 const X86Subtarget * Subtarget) {
12155 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
12156 assert(C && "Invalid scale type");
12157 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
12158 EVT MaskVT = MVT::getVectorVT(MVT::i1,
12159 Index.getSimpleValueType().getVectorNumElements());
12160 SDValue MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
12161 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
12162 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
12163 SDValue Segment = DAG.getRegister(0, MVT::i32);
12164 if (Src.getOpcode() == ISD::UNDEF)
12165 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
12166 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
12167 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
12168 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
12169 return DAG.getMergeValues(RetOps, array_lengthof(RetOps), dl);
12172 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
12173 SDValue Src, SDValue Base, SDValue Index,
12174 SDValue ScaleOp, SDValue Chain) {
12176 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
12177 assert(C && "Invalid scale type");
12178 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
12179 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
12180 SDValue Segment = DAG.getRegister(0, MVT::i32);
12181 EVT MaskVT = MVT::getVectorVT(MVT::i1,
12182 Index.getSimpleValueType().getVectorNumElements());
12183 SDValue MaskInReg = DAG.getConstant(~0, MaskVT);
12184 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
12185 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
12186 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
12187 return SDValue(Res, 1);
12190 static SDValue getMScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
12191 SDValue Src, SDValue Mask, SDValue Base,
12192 SDValue Index, SDValue ScaleOp, SDValue Chain) {
12194 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
12195 assert(C && "Invalid scale type");
12196 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
12197 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
12198 SDValue Segment = DAG.getRegister(0, MVT::i32);
12199 EVT MaskVT = MVT::getVectorVT(MVT::i1,
12200 Index.getSimpleValueType().getVectorNumElements());
12201 SDValue MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
12202 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
12203 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
12204 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
12205 return SDValue(Res, 1);
12208 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
12209 SelectionDAG &DAG) {
12211 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12213 default: return SDValue(); // Don't custom lower most intrinsics.
12215 // RDRAND/RDSEED intrinsics.
12216 case Intrinsic::x86_rdrand_16:
12217 case Intrinsic::x86_rdrand_32:
12218 case Intrinsic::x86_rdrand_64:
12219 case Intrinsic::x86_rdseed_16:
12220 case Intrinsic::x86_rdseed_32:
12221 case Intrinsic::x86_rdseed_64: {
12222 unsigned Opcode = (IntNo == Intrinsic::x86_rdseed_16 ||
12223 IntNo == Intrinsic::x86_rdseed_32 ||
12224 IntNo == Intrinsic::x86_rdseed_64) ? X86ISD::RDSEED :
12226 // Emit the node with the right value type.
12227 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
12228 SDValue Result = DAG.getNode(Opcode, dl, VTs, Op.getOperand(0));
12230 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
12231 // Otherwise return the value from Rand, which is always 0, casted to i32.
12232 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
12233 DAG.getConstant(1, Op->getValueType(1)),
12234 DAG.getConstant(X86::COND_B, MVT::i32),
12235 SDValue(Result.getNode(), 1) };
12236 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
12237 DAG.getVTList(Op->getValueType(1), MVT::Glue),
12238 Ops, array_lengthof(Ops));
12240 // Return { result, isValid, chain }.
12241 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
12242 SDValue(Result.getNode(), 2));
12244 //int_gather(index, base, scale);
12245 case Intrinsic::x86_avx512_gather_qpd_512:
12246 case Intrinsic::x86_avx512_gather_qps_512:
12247 case Intrinsic::x86_avx512_gather_dpd_512:
12248 case Intrinsic::x86_avx512_gather_qpi_512:
12249 case Intrinsic::x86_avx512_gather_qpq_512:
12250 case Intrinsic::x86_avx512_gather_dpq_512:
12251 case Intrinsic::x86_avx512_gather_dps_512:
12252 case Intrinsic::x86_avx512_gather_dpi_512: {
12255 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
12256 case Intrinsic::x86_avx512_gather_qps_512: Opc = X86::VGATHERQPSZrm; break;
12257 case Intrinsic::x86_avx512_gather_qpd_512: Opc = X86::VGATHERQPDZrm; break;
12258 case Intrinsic::x86_avx512_gather_dpd_512: Opc = X86::VGATHERDPDZrm; break;
12259 case Intrinsic::x86_avx512_gather_dps_512: Opc = X86::VGATHERDPSZrm; break;
12260 case Intrinsic::x86_avx512_gather_qpi_512: Opc = X86::VPGATHERQDZrm; break;
12261 case Intrinsic::x86_avx512_gather_qpq_512: Opc = X86::VPGATHERQQZrm; break;
12262 case Intrinsic::x86_avx512_gather_dpi_512: Opc = X86::VPGATHERDDZrm; break;
12263 case Intrinsic::x86_avx512_gather_dpq_512: Opc = X86::VPGATHERDQZrm; break;
12265 SDValue Chain = Op.getOperand(0);
12266 SDValue Index = Op.getOperand(2);
12267 SDValue Base = Op.getOperand(3);
12268 SDValue Scale = Op.getOperand(4);
12269 return getGatherNode(Opc, Op, DAG, Base, Index, Scale, Chain, Subtarget);
12271 //int_gather_mask(v1, mask, index, base, scale);
12272 case Intrinsic::x86_avx512_gather_qps_mask_512:
12273 case Intrinsic::x86_avx512_gather_qpd_mask_512:
12274 case Intrinsic::x86_avx512_gather_dpd_mask_512:
12275 case Intrinsic::x86_avx512_gather_dps_mask_512:
12276 case Intrinsic::x86_avx512_gather_qpi_mask_512:
12277 case Intrinsic::x86_avx512_gather_qpq_mask_512:
12278 case Intrinsic::x86_avx512_gather_dpi_mask_512:
12279 case Intrinsic::x86_avx512_gather_dpq_mask_512: {
12282 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
12283 case Intrinsic::x86_avx512_gather_qps_mask_512:
12284 Opc = X86::VGATHERQPSZrm; break;
12285 case Intrinsic::x86_avx512_gather_qpd_mask_512:
12286 Opc = X86::VGATHERQPDZrm; break;
12287 case Intrinsic::x86_avx512_gather_dpd_mask_512:
12288 Opc = X86::VGATHERDPDZrm; break;
12289 case Intrinsic::x86_avx512_gather_dps_mask_512:
12290 Opc = X86::VGATHERDPSZrm; break;
12291 case Intrinsic::x86_avx512_gather_qpi_mask_512:
12292 Opc = X86::VPGATHERQDZrm; break;
12293 case Intrinsic::x86_avx512_gather_qpq_mask_512:
12294 Opc = X86::VPGATHERQQZrm; break;
12295 case Intrinsic::x86_avx512_gather_dpi_mask_512:
12296 Opc = X86::VPGATHERDDZrm; break;
12297 case Intrinsic::x86_avx512_gather_dpq_mask_512:
12298 Opc = X86::VPGATHERDQZrm; break;
12300 SDValue Chain = Op.getOperand(0);
12301 SDValue Src = Op.getOperand(2);
12302 SDValue Mask = Op.getOperand(3);
12303 SDValue Index = Op.getOperand(4);
12304 SDValue Base = Op.getOperand(5);
12305 SDValue Scale = Op.getOperand(6);
12306 return getMGatherNode(Opc, Op, DAG, Src, Mask, Base, Index, Scale, Chain,
12309 //int_scatter(base, index, v1, scale);
12310 case Intrinsic::x86_avx512_scatter_qpd_512:
12311 case Intrinsic::x86_avx512_scatter_qps_512:
12312 case Intrinsic::x86_avx512_scatter_dpd_512:
12313 case Intrinsic::x86_avx512_scatter_qpi_512:
12314 case Intrinsic::x86_avx512_scatter_qpq_512:
12315 case Intrinsic::x86_avx512_scatter_dpq_512:
12316 case Intrinsic::x86_avx512_scatter_dps_512:
12317 case Intrinsic::x86_avx512_scatter_dpi_512: {
12320 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
12321 case Intrinsic::x86_avx512_scatter_qpd_512:
12322 Opc = X86::VSCATTERQPDZmr; break;
12323 case Intrinsic::x86_avx512_scatter_qps_512:
12324 Opc = X86::VSCATTERQPSZmr; break;
12325 case Intrinsic::x86_avx512_scatter_dpd_512:
12326 Opc = X86::VSCATTERDPDZmr; break;
12327 case Intrinsic::x86_avx512_scatter_dps_512:
12328 Opc = X86::VSCATTERDPSZmr; break;
12329 case Intrinsic::x86_avx512_scatter_qpi_512:
12330 Opc = X86::VPSCATTERQDZmr; break;
12331 case Intrinsic::x86_avx512_scatter_qpq_512:
12332 Opc = X86::VPSCATTERQQZmr; break;
12333 case Intrinsic::x86_avx512_scatter_dpq_512:
12334 Opc = X86::VPSCATTERDQZmr; break;
12335 case Intrinsic::x86_avx512_scatter_dpi_512:
12336 Opc = X86::VPSCATTERDDZmr; break;
12338 SDValue Chain = Op.getOperand(0);
12339 SDValue Base = Op.getOperand(2);
12340 SDValue Index = Op.getOperand(3);
12341 SDValue Src = Op.getOperand(4);
12342 SDValue Scale = Op.getOperand(5);
12343 return getScatterNode(Opc, Op, DAG, Src, Base, Index, Scale, Chain);
12345 //int_scatter_mask(base, mask, index, v1, scale);
12346 case Intrinsic::x86_avx512_scatter_qps_mask_512:
12347 case Intrinsic::x86_avx512_scatter_qpd_mask_512:
12348 case Intrinsic::x86_avx512_scatter_dpd_mask_512:
12349 case Intrinsic::x86_avx512_scatter_dps_mask_512:
12350 case Intrinsic::x86_avx512_scatter_qpi_mask_512:
12351 case Intrinsic::x86_avx512_scatter_qpq_mask_512:
12352 case Intrinsic::x86_avx512_scatter_dpi_mask_512:
12353 case Intrinsic::x86_avx512_scatter_dpq_mask_512: {
12356 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
12357 case Intrinsic::x86_avx512_scatter_qpd_mask_512:
12358 Opc = X86::VSCATTERQPDZmr; break;
12359 case Intrinsic::x86_avx512_scatter_qps_mask_512:
12360 Opc = X86::VSCATTERQPSZmr; break;
12361 case Intrinsic::x86_avx512_scatter_dpd_mask_512:
12362 Opc = X86::VSCATTERDPDZmr; break;
12363 case Intrinsic::x86_avx512_scatter_dps_mask_512:
12364 Opc = X86::VSCATTERDPSZmr; break;
12365 case Intrinsic::x86_avx512_scatter_qpi_mask_512:
12366 Opc = X86::VPSCATTERQDZmr; break;
12367 case Intrinsic::x86_avx512_scatter_qpq_mask_512:
12368 Opc = X86::VPSCATTERQQZmr; break;
12369 case Intrinsic::x86_avx512_scatter_dpq_mask_512:
12370 Opc = X86::VPSCATTERDQZmr; break;
12371 case Intrinsic::x86_avx512_scatter_dpi_mask_512:
12372 Opc = X86::VPSCATTERDDZmr; break;
12374 SDValue Chain = Op.getOperand(0);
12375 SDValue Base = Op.getOperand(2);
12376 SDValue Mask = Op.getOperand(3);
12377 SDValue Index = Op.getOperand(4);
12378 SDValue Src = Op.getOperand(5);
12379 SDValue Scale = Op.getOperand(6);
12380 return getMScatterNode(Opc, Op, DAG, Src, Mask, Base, Index, Scale, Chain);
12382 // XTEST intrinsics.
12383 case Intrinsic::x86_xtest: {
12384 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
12385 SDValue InTrans = DAG.getNode(X86ISD::XTEST, dl, VTs, Op.getOperand(0));
12386 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
12387 DAG.getConstant(X86::COND_NE, MVT::i8),
12389 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
12390 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
12391 Ret, SDValue(InTrans.getNode(), 1));
12396 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
12397 SelectionDAG &DAG) const {
12398 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12399 MFI->setReturnAddressIsTaken(true);
12401 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
12404 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
12406 EVT PtrVT = getPointerTy();
12409 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
12410 const X86RegisterInfo *RegInfo =
12411 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
12412 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
12413 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
12414 DAG.getNode(ISD::ADD, dl, PtrVT,
12415 FrameAddr, Offset),
12416 MachinePointerInfo(), false, false, false, 0);
12419 // Just load the return address.
12420 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
12421 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
12422 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
12425 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
12426 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12427 MFI->setFrameAddressIsTaken(true);
12429 EVT VT = Op.getValueType();
12430 SDLoc dl(Op); // FIXME probably not meaningful
12431 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
12432 const X86RegisterInfo *RegInfo =
12433 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
12434 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
12435 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
12436 (FrameReg == X86::EBP && VT == MVT::i32)) &&
12437 "Invalid Frame Register!");
12438 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
12440 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
12441 MachinePointerInfo(),
12442 false, false, false, 0);
12446 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
12447 SelectionDAG &DAG) const {
12448 const X86RegisterInfo *RegInfo =
12449 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
12450 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
12453 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
12454 SDValue Chain = Op.getOperand(0);
12455 SDValue Offset = Op.getOperand(1);
12456 SDValue Handler = Op.getOperand(2);
12459 EVT PtrVT = getPointerTy();
12460 const X86RegisterInfo *RegInfo =
12461 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
12462 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
12463 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
12464 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
12465 "Invalid Frame Register!");
12466 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
12467 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
12469 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
12470 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
12471 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
12472 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
12474 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
12476 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
12477 DAG.getRegister(StoreAddrReg, PtrVT));
12480 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
12481 SelectionDAG &DAG) const {
12483 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
12484 DAG.getVTList(MVT::i32, MVT::Other),
12485 Op.getOperand(0), Op.getOperand(1));
12488 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
12489 SelectionDAG &DAG) const {
12491 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
12492 Op.getOperand(0), Op.getOperand(1));
12495 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
12496 return Op.getOperand(0);
12499 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
12500 SelectionDAG &DAG) const {
12501 SDValue Root = Op.getOperand(0);
12502 SDValue Trmp = Op.getOperand(1); // trampoline
12503 SDValue FPtr = Op.getOperand(2); // nested function
12504 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
12507 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
12508 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
12510 if (Subtarget->is64Bit()) {
12511 SDValue OutChains[6];
12513 // Large code-model.
12514 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
12515 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
12517 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
12518 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
12520 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
12522 // Load the pointer to the nested function into R11.
12523 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
12524 SDValue Addr = Trmp;
12525 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
12526 Addr, MachinePointerInfo(TrmpAddr),
12529 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
12530 DAG.getConstant(2, MVT::i64));
12531 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
12532 MachinePointerInfo(TrmpAddr, 2),
12535 // Load the 'nest' parameter value into R10.
12536 // R10 is specified in X86CallingConv.td
12537 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
12538 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
12539 DAG.getConstant(10, MVT::i64));
12540 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
12541 Addr, MachinePointerInfo(TrmpAddr, 10),
12544 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
12545 DAG.getConstant(12, MVT::i64));
12546 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
12547 MachinePointerInfo(TrmpAddr, 12),
12550 // Jump to the nested function.
12551 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
12552 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
12553 DAG.getConstant(20, MVT::i64));
12554 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
12555 Addr, MachinePointerInfo(TrmpAddr, 20),
12558 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
12559 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
12560 DAG.getConstant(22, MVT::i64));
12561 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
12562 MachinePointerInfo(TrmpAddr, 22),
12565 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6);
12567 const Function *Func =
12568 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
12569 CallingConv::ID CC = Func->getCallingConv();
12574 llvm_unreachable("Unsupported calling convention");
12575 case CallingConv::C:
12576 case CallingConv::X86_StdCall: {
12577 // Pass 'nest' parameter in ECX.
12578 // Must be kept in sync with X86CallingConv.td
12579 NestReg = X86::ECX;
12581 // Check that ECX wasn't needed by an 'inreg' parameter.
12582 FunctionType *FTy = Func->getFunctionType();
12583 const AttributeSet &Attrs = Func->getAttributes();
12585 if (!Attrs.isEmpty() && !Func->isVarArg()) {
12586 unsigned InRegCount = 0;
12589 for (FunctionType::param_iterator I = FTy->param_begin(),
12590 E = FTy->param_end(); I != E; ++I, ++Idx)
12591 if (Attrs.hasAttribute(Idx, Attribute::InReg))
12592 // FIXME: should only count parameters that are lowered to integers.
12593 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
12595 if (InRegCount > 2) {
12596 report_fatal_error("Nest register in use - reduce number of inreg"
12602 case CallingConv::X86_FastCall:
12603 case CallingConv::X86_ThisCall:
12604 case CallingConv::Fast:
12605 // Pass 'nest' parameter in EAX.
12606 // Must be kept in sync with X86CallingConv.td
12607 NestReg = X86::EAX;
12611 SDValue OutChains[4];
12612 SDValue Addr, Disp;
12614 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
12615 DAG.getConstant(10, MVT::i32));
12616 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
12618 // This is storing the opcode for MOV32ri.
12619 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
12620 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
12621 OutChains[0] = DAG.getStore(Root, dl,
12622 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
12623 Trmp, MachinePointerInfo(TrmpAddr),
12626 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
12627 DAG.getConstant(1, MVT::i32));
12628 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
12629 MachinePointerInfo(TrmpAddr, 1),
12632 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
12633 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
12634 DAG.getConstant(5, MVT::i32));
12635 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
12636 MachinePointerInfo(TrmpAddr, 5),
12639 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
12640 DAG.getConstant(6, MVT::i32));
12641 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
12642 MachinePointerInfo(TrmpAddr, 6),
12645 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4);
12649 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
12650 SelectionDAG &DAG) const {
12652 The rounding mode is in bits 11:10 of FPSR, and has the following
12654 00 Round to nearest
12659 FLT_ROUNDS, on the other hand, expects the following:
12666 To perform the conversion, we do:
12667 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
12670 MachineFunction &MF = DAG.getMachineFunction();
12671 const TargetMachine &TM = MF.getTarget();
12672 const TargetFrameLowering &TFI = *TM.getFrameLowering();
12673 unsigned StackAlignment = TFI.getStackAlignment();
12674 MVT VT = Op.getSimpleValueType();
12677 // Save FP Control Word to stack slot
12678 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
12679 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
12681 MachineMemOperand *MMO =
12682 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12683 MachineMemOperand::MOStore, 2, 2);
12685 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
12686 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
12687 DAG.getVTList(MVT::Other),
12688 Ops, array_lengthof(Ops), MVT::i16,
12691 // Load FP Control Word from stack slot
12692 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
12693 MachinePointerInfo(), false, false, false, 0);
12695 // Transform as necessary
12697 DAG.getNode(ISD::SRL, DL, MVT::i16,
12698 DAG.getNode(ISD::AND, DL, MVT::i16,
12699 CWD, DAG.getConstant(0x800, MVT::i16)),
12700 DAG.getConstant(11, MVT::i8));
12702 DAG.getNode(ISD::SRL, DL, MVT::i16,
12703 DAG.getNode(ISD::AND, DL, MVT::i16,
12704 CWD, DAG.getConstant(0x400, MVT::i16)),
12705 DAG.getConstant(9, MVT::i8));
12708 DAG.getNode(ISD::AND, DL, MVT::i16,
12709 DAG.getNode(ISD::ADD, DL, MVT::i16,
12710 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
12711 DAG.getConstant(1, MVT::i16)),
12712 DAG.getConstant(3, MVT::i16));
12714 return DAG.getNode((VT.getSizeInBits() < 16 ?
12715 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
12718 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
12719 MVT VT = Op.getSimpleValueType();
12721 unsigned NumBits = VT.getSizeInBits();
12724 Op = Op.getOperand(0);
12725 if (VT == MVT::i8) {
12726 // Zero extend to i32 since there is not an i8 bsr.
12728 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
12731 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
12732 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
12733 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
12735 // If src is zero (i.e. bsr sets ZF), returns NumBits.
12738 DAG.getConstant(NumBits+NumBits-1, OpVT),
12739 DAG.getConstant(X86::COND_E, MVT::i8),
12742 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
12744 // Finally xor with NumBits-1.
12745 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
12748 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
12752 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
12753 MVT VT = Op.getSimpleValueType();
12755 unsigned NumBits = VT.getSizeInBits();
12758 Op = Op.getOperand(0);
12759 if (VT == MVT::i8) {
12760 // Zero extend to i32 since there is not an i8 bsr.
12762 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
12765 // Issue a bsr (scan bits in reverse).
12766 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
12767 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
12769 // And xor with NumBits-1.
12770 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
12773 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
12777 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
12778 MVT VT = Op.getSimpleValueType();
12779 unsigned NumBits = VT.getSizeInBits();
12781 Op = Op.getOperand(0);
12783 // Issue a bsf (scan bits forward) which also sets EFLAGS.
12784 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
12785 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
12787 // If src is zero (i.e. bsf sets ZF), returns NumBits.
12790 DAG.getConstant(NumBits, VT),
12791 DAG.getConstant(X86::COND_E, MVT::i8),
12794 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops, array_lengthof(Ops));
12797 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
12798 // ones, and then concatenate the result back.
12799 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
12800 MVT VT = Op.getSimpleValueType();
12802 assert(VT.is256BitVector() && VT.isInteger() &&
12803 "Unsupported value type for operation");
12805 unsigned NumElems = VT.getVectorNumElements();
12808 // Extract the LHS vectors
12809 SDValue LHS = Op.getOperand(0);
12810 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
12811 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
12813 // Extract the RHS vectors
12814 SDValue RHS = Op.getOperand(1);
12815 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
12816 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
12818 MVT EltVT = VT.getVectorElementType();
12819 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
12821 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
12822 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
12823 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
12826 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
12827 assert(Op.getSimpleValueType().is256BitVector() &&
12828 Op.getSimpleValueType().isInteger() &&
12829 "Only handle AVX 256-bit vector integer operation");
12830 return Lower256IntArith(Op, DAG);
12833 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
12834 assert(Op.getSimpleValueType().is256BitVector() &&
12835 Op.getSimpleValueType().isInteger() &&
12836 "Only handle AVX 256-bit vector integer operation");
12837 return Lower256IntArith(Op, DAG);
12840 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
12841 SelectionDAG &DAG) {
12843 MVT VT = Op.getSimpleValueType();
12845 // Decompose 256-bit ops into smaller 128-bit ops.
12846 if (VT.is256BitVector() && !Subtarget->hasInt256())
12847 return Lower256IntArith(Op, DAG);
12849 SDValue A = Op.getOperand(0);
12850 SDValue B = Op.getOperand(1);
12852 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
12853 if (VT == MVT::v4i32) {
12854 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
12855 "Should not custom lower when pmuldq is available!");
12857 // Extract the odd parts.
12858 static const int UnpackMask[] = { 1, -1, 3, -1 };
12859 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
12860 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
12862 // Multiply the even parts.
12863 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
12864 // Now multiply odd parts.
12865 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
12867 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
12868 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
12870 // Merge the two vectors back together with a shuffle. This expands into 2
12872 static const int ShufMask[] = { 0, 4, 2, 6 };
12873 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
12876 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
12877 "Only know how to lower V2I64/V4I64/V8I64 multiply");
12879 // Ahi = psrlqi(a, 32);
12880 // Bhi = psrlqi(b, 32);
12882 // AloBlo = pmuludq(a, b);
12883 // AloBhi = pmuludq(a, Bhi);
12884 // AhiBlo = pmuludq(Ahi, b);
12886 // AloBhi = psllqi(AloBhi, 32);
12887 // AhiBlo = psllqi(AhiBlo, 32);
12888 // return AloBlo + AloBhi + AhiBlo;
12890 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
12891 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
12893 // Bit cast to 32-bit vectors for MULUDQ
12894 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
12895 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
12896 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
12897 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
12898 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
12899 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
12901 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
12902 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
12903 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
12905 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
12906 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
12908 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
12909 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
12912 static SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG) {
12913 MVT VT = Op.getSimpleValueType();
12914 MVT EltTy = VT.getVectorElementType();
12915 unsigned NumElts = VT.getVectorNumElements();
12916 SDValue N0 = Op.getOperand(0);
12919 // Lower sdiv X, pow2-const.
12920 BuildVectorSDNode *C = dyn_cast<BuildVectorSDNode>(Op.getOperand(1));
12924 APInt SplatValue, SplatUndef;
12925 unsigned SplatBitSize;
12927 if (!C->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
12929 EltTy.getSizeInBits() < SplatBitSize)
12932 if ((SplatValue != 0) &&
12933 (SplatValue.isPowerOf2() || (-SplatValue).isPowerOf2())) {
12934 unsigned Lg2 = SplatValue.countTrailingZeros();
12935 // Splat the sign bit.
12936 SmallVector<SDValue, 16> Sz(NumElts,
12937 DAG.getConstant(EltTy.getSizeInBits() - 1,
12939 SDValue SGN = DAG.getNode(ISD::SRA, dl, VT, N0,
12940 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Sz[0],
12942 // Add (N0 < 0) ? abs2 - 1 : 0;
12943 SmallVector<SDValue, 16> Amt(NumElts,
12944 DAG.getConstant(EltTy.getSizeInBits() - Lg2,
12946 SDValue SRL = DAG.getNode(ISD::SRL, dl, VT, SGN,
12947 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Amt[0],
12949 SDValue ADD = DAG.getNode(ISD::ADD, dl, VT, N0, SRL);
12950 SmallVector<SDValue, 16> Lg2Amt(NumElts, DAG.getConstant(Lg2, EltTy));
12951 SDValue SRA = DAG.getNode(ISD::SRA, dl, VT, ADD,
12952 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Lg2Amt[0],
12955 // If we're dividing by a positive value, we're done. Otherwise, we must
12956 // negate the result.
12957 if (SplatValue.isNonNegative())
12960 SmallVector<SDValue, 16> V(NumElts, DAG.getConstant(0, EltTy));
12961 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], NumElts);
12962 return DAG.getNode(ISD::SUB, dl, VT, Zero, SRA);
12967 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
12968 const X86Subtarget *Subtarget) {
12969 MVT VT = Op.getSimpleValueType();
12971 SDValue R = Op.getOperand(0);
12972 SDValue Amt = Op.getOperand(1);
12974 // Optimize shl/srl/sra with constant shift amount.
12975 if (isSplatVector(Amt.getNode())) {
12976 SDValue SclrAmt = Amt->getOperand(0);
12977 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
12978 uint64_t ShiftAmt = C->getZExtValue();
12980 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
12981 (Subtarget->hasInt256() &&
12982 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16)) ||
12983 (Subtarget->hasAVX512() &&
12984 (VT == MVT::v8i64 || VT == MVT::v16i32))) {
12985 if (Op.getOpcode() == ISD::SHL)
12986 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
12988 if (Op.getOpcode() == ISD::SRL)
12989 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
12991 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
12992 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
12996 if (VT == MVT::v16i8) {
12997 if (Op.getOpcode() == ISD::SHL) {
12998 // Make a large shift.
12999 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
13000 MVT::v8i16, R, ShiftAmt,
13002 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
13003 // Zero out the rightmost bits.
13004 SmallVector<SDValue, 16> V(16,
13005 DAG.getConstant(uint8_t(-1U << ShiftAmt),
13007 return DAG.getNode(ISD::AND, dl, VT, SHL,
13008 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
13010 if (Op.getOpcode() == ISD::SRL) {
13011 // Make a large shift.
13012 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
13013 MVT::v8i16, R, ShiftAmt,
13015 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
13016 // Zero out the leftmost bits.
13017 SmallVector<SDValue, 16> V(16,
13018 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
13020 return DAG.getNode(ISD::AND, dl, VT, SRL,
13021 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
13023 if (Op.getOpcode() == ISD::SRA) {
13024 if (ShiftAmt == 7) {
13025 // R s>> 7 === R s< 0
13026 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
13027 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
13030 // R s>> a === ((R u>> a) ^ m) - m
13031 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
13032 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
13034 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16);
13035 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
13036 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
13039 llvm_unreachable("Unknown shift opcode.");
13042 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
13043 if (Op.getOpcode() == ISD::SHL) {
13044 // Make a large shift.
13045 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
13046 MVT::v16i16, R, ShiftAmt,
13048 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
13049 // Zero out the rightmost bits.
13050 SmallVector<SDValue, 32> V(32,
13051 DAG.getConstant(uint8_t(-1U << ShiftAmt),
13053 return DAG.getNode(ISD::AND, dl, VT, SHL,
13054 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
13056 if (Op.getOpcode() == ISD::SRL) {
13057 // Make a large shift.
13058 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
13059 MVT::v16i16, R, ShiftAmt,
13061 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
13062 // Zero out the leftmost bits.
13063 SmallVector<SDValue, 32> V(32,
13064 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
13066 return DAG.getNode(ISD::AND, dl, VT, SRL,
13067 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
13069 if (Op.getOpcode() == ISD::SRA) {
13070 if (ShiftAmt == 7) {
13071 // R s>> 7 === R s< 0
13072 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
13073 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
13076 // R s>> a === ((R u>> a) ^ m) - m
13077 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
13078 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
13080 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32);
13081 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
13082 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
13085 llvm_unreachable("Unknown shift opcode.");
13090 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
13091 if (!Subtarget->is64Bit() &&
13092 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
13093 Amt.getOpcode() == ISD::BITCAST &&
13094 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
13095 Amt = Amt.getOperand(0);
13096 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
13097 VT.getVectorNumElements();
13098 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
13099 uint64_t ShiftAmt = 0;
13100 for (unsigned i = 0; i != Ratio; ++i) {
13101 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
13105 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
13107 // Check remaining shift amounts.
13108 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
13109 uint64_t ShAmt = 0;
13110 for (unsigned j = 0; j != Ratio; ++j) {
13111 ConstantSDNode *C =
13112 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
13116 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
13118 if (ShAmt != ShiftAmt)
13121 switch (Op.getOpcode()) {
13123 llvm_unreachable("Unknown shift opcode!");
13125 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
13128 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
13131 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
13139 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
13140 const X86Subtarget* Subtarget) {
13141 MVT VT = Op.getSimpleValueType();
13143 SDValue R = Op.getOperand(0);
13144 SDValue Amt = Op.getOperand(1);
13146 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
13147 VT == MVT::v4i32 || VT == MVT::v8i16 ||
13148 (Subtarget->hasInt256() &&
13149 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
13150 VT == MVT::v8i32 || VT == MVT::v16i16)) ||
13151 (Subtarget->hasAVX512() && (VT == MVT::v8i64 || VT == MVT::v16i32))) {
13153 EVT EltVT = VT.getVectorElementType();
13155 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
13156 unsigned NumElts = VT.getVectorNumElements();
13158 for (i = 0; i != NumElts; ++i) {
13159 if (Amt.getOperand(i).getOpcode() == ISD::UNDEF)
13163 for (j = i; j != NumElts; ++j) {
13164 SDValue Arg = Amt.getOperand(j);
13165 if (Arg.getOpcode() == ISD::UNDEF) continue;
13166 if (Arg != Amt.getOperand(i))
13169 if (i != NumElts && j == NumElts)
13170 BaseShAmt = Amt.getOperand(i);
13172 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
13173 Amt = Amt.getOperand(0);
13174 if (Amt.getOpcode() == ISD::VECTOR_SHUFFLE &&
13175 cast<ShuffleVectorSDNode>(Amt)->isSplat()) {
13176 SDValue InVec = Amt.getOperand(0);
13177 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
13178 unsigned NumElts = InVec.getValueType().getVectorNumElements();
13180 for (; i != NumElts; ++i) {
13181 SDValue Arg = InVec.getOperand(i);
13182 if (Arg.getOpcode() == ISD::UNDEF) continue;
13186 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
13187 if (ConstantSDNode *C =
13188 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
13189 unsigned SplatIdx =
13190 cast<ShuffleVectorSDNode>(Amt)->getSplatIndex();
13191 if (C->getZExtValue() == SplatIdx)
13192 BaseShAmt = InVec.getOperand(1);
13195 if (BaseShAmt.getNode() == 0)
13196 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Amt,
13197 DAG.getIntPtrConstant(0));
13201 if (BaseShAmt.getNode()) {
13202 if (EltVT.bitsGT(MVT::i32))
13203 BaseShAmt = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BaseShAmt);
13204 else if (EltVT.bitsLT(MVT::i32))
13205 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
13207 switch (Op.getOpcode()) {
13209 llvm_unreachable("Unknown shift opcode!");
13211 switch (VT.SimpleTy) {
13212 default: return SDValue();
13221 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
13224 switch (VT.SimpleTy) {
13225 default: return SDValue();
13232 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
13235 switch (VT.SimpleTy) {
13236 default: return SDValue();
13245 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);
13251 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
13252 if (!Subtarget->is64Bit() &&
13253 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64) ||
13254 (Subtarget->hasAVX512() && VT == MVT::v8i64)) &&
13255 Amt.getOpcode() == ISD::BITCAST &&
13256 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
13257 Amt = Amt.getOperand(0);
13258 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
13259 VT.getVectorNumElements();
13260 std::vector<SDValue> Vals(Ratio);
13261 for (unsigned i = 0; i != Ratio; ++i)
13262 Vals[i] = Amt.getOperand(i);
13263 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
13264 for (unsigned j = 0; j != Ratio; ++j)
13265 if (Vals[j] != Amt.getOperand(i + j))
13268 switch (Op.getOpcode()) {
13270 llvm_unreachable("Unknown shift opcode!");
13272 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1));
13274 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1));
13276 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1));
13283 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
13284 SelectionDAG &DAG) {
13286 MVT VT = Op.getSimpleValueType();
13288 SDValue R = Op.getOperand(0);
13289 SDValue Amt = Op.getOperand(1);
13292 if (!Subtarget->hasSSE2())
13295 V = LowerScalarImmediateShift(Op, DAG, Subtarget);
13299 V = LowerScalarVariableShift(Op, DAG, Subtarget);
13303 if (Subtarget->hasAVX512() && (VT == MVT::v16i32 || VT == MVT::v8i64))
13305 // AVX2 has VPSLLV/VPSRAV/VPSRLV.
13306 if (Subtarget->hasInt256()) {
13307 if (Op.getOpcode() == ISD::SRL &&
13308 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
13309 VT == MVT::v4i64 || VT == MVT::v8i32))
13311 if (Op.getOpcode() == ISD::SHL &&
13312 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
13313 VT == MVT::v4i64 || VT == MVT::v8i32))
13315 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
13319 // If possible, lower this packed shift into a vector multiply instead of
13320 // expanding it into a sequence of scalar shifts.
13321 // Do this only if the vector shift count is a constant build_vector.
13322 if (Op.getOpcode() == ISD::SHL &&
13323 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
13324 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
13325 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
13326 SmallVector<SDValue, 8> Elts;
13327 EVT SVT = VT.getScalarType();
13328 unsigned SVTBits = SVT.getSizeInBits();
13329 const APInt &One = APInt(SVTBits, 1);
13330 unsigned NumElems = VT.getVectorNumElements();
13332 for (unsigned i=0; i !=NumElems; ++i) {
13333 SDValue Op = Amt->getOperand(i);
13334 if (Op->getOpcode() == ISD::UNDEF) {
13335 Elts.push_back(Op);
13339 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
13340 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
13341 uint64_t ShAmt = C.getZExtValue();
13342 if (ShAmt >= SVTBits) {
13343 Elts.push_back(DAG.getUNDEF(SVT));
13346 Elts.push_back(DAG.getConstant(One.shl(ShAmt), SVT));
13348 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Elts[0], NumElems);
13349 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
13352 // Lower SHL with variable shift amount.
13353 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
13354 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
13356 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
13357 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
13358 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
13359 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
13362 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
13363 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
13366 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
13367 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
13369 // Turn 'a' into a mask suitable for VSELECT
13370 SDValue VSelM = DAG.getConstant(0x80, VT);
13371 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
13372 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
13374 SDValue CM1 = DAG.getConstant(0x0f, VT);
13375 SDValue CM2 = DAG.getConstant(0x3f, VT);
13377 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
13378 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
13379 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 4, DAG);
13380 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
13381 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
13384 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
13385 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
13386 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
13388 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
13389 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
13390 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 2, DAG);
13391 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
13392 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
13395 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
13396 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
13397 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
13399 // return VSELECT(r, r+r, a);
13400 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
13401 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
13405 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
13406 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
13407 // solution better.
13408 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
13409 MVT NewVT = VT == MVT::v8i16 ? MVT::v8i32 : MVT::v16i16;
13411 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
13412 R = DAG.getNode(ExtOpc, dl, NewVT, R);
13413 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, NewVT, Amt);
13414 return DAG.getNode(ISD::TRUNCATE, dl, VT,
13415 DAG.getNode(Op.getOpcode(), dl, NewVT, R, Amt));
13418 // Decompose 256-bit shifts into smaller 128-bit shifts.
13419 if (VT.is256BitVector()) {
13420 unsigned NumElems = VT.getVectorNumElements();
13421 MVT EltVT = VT.getVectorElementType();
13422 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
13424 // Extract the two vectors
13425 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
13426 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
13428 // Recreate the shift amount vectors
13429 SDValue Amt1, Amt2;
13430 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
13431 // Constant shift amount
13432 SmallVector<SDValue, 4> Amt1Csts;
13433 SmallVector<SDValue, 4> Amt2Csts;
13434 for (unsigned i = 0; i != NumElems/2; ++i)
13435 Amt1Csts.push_back(Amt->getOperand(i));
13436 for (unsigned i = NumElems/2; i != NumElems; ++i)
13437 Amt2Csts.push_back(Amt->getOperand(i));
13439 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
13440 &Amt1Csts[0], NumElems/2);
13441 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
13442 &Amt2Csts[0], NumElems/2);
13444 // Variable shift amount
13445 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
13446 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
13449 // Issue new vector shifts for the smaller types
13450 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
13451 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
13453 // Concatenate the result back
13454 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
13460 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
13461 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
13462 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
13463 // looks for this combo and may remove the "setcc" instruction if the "setcc"
13464 // has only one use.
13465 SDNode *N = Op.getNode();
13466 SDValue LHS = N->getOperand(0);
13467 SDValue RHS = N->getOperand(1);
13468 unsigned BaseOp = 0;
13471 switch (Op.getOpcode()) {
13472 default: llvm_unreachable("Unknown ovf instruction!");
13474 // A subtract of one will be selected as a INC. Note that INC doesn't
13475 // set CF, so we can't do this for UADDO.
13476 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
13478 BaseOp = X86ISD::INC;
13479 Cond = X86::COND_O;
13482 BaseOp = X86ISD::ADD;
13483 Cond = X86::COND_O;
13486 BaseOp = X86ISD::ADD;
13487 Cond = X86::COND_B;
13490 // A subtract of one will be selected as a DEC. Note that DEC doesn't
13491 // set CF, so we can't do this for USUBO.
13492 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
13494 BaseOp = X86ISD::DEC;
13495 Cond = X86::COND_O;
13498 BaseOp = X86ISD::SUB;
13499 Cond = X86::COND_O;
13502 BaseOp = X86ISD::SUB;
13503 Cond = X86::COND_B;
13506 BaseOp = X86ISD::SMUL;
13507 Cond = X86::COND_O;
13509 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
13510 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
13512 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
13515 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13516 DAG.getConstant(X86::COND_O, MVT::i32),
13517 SDValue(Sum.getNode(), 2));
13519 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
13523 // Also sets EFLAGS.
13524 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
13525 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
13528 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
13529 DAG.getConstant(Cond, MVT::i32),
13530 SDValue(Sum.getNode(), 1));
13532 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
13535 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
13536 SelectionDAG &DAG) const {
13538 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
13539 MVT VT = Op.getSimpleValueType();
13541 if (!Subtarget->hasSSE2() || !VT.isVector())
13544 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
13545 ExtraVT.getScalarType().getSizeInBits();
13547 switch (VT.SimpleTy) {
13548 default: return SDValue();
13551 if (!Subtarget->hasFp256())
13553 if (!Subtarget->hasInt256()) {
13554 // needs to be split
13555 unsigned NumElems = VT.getVectorNumElements();
13557 // Extract the LHS vectors
13558 SDValue LHS = Op.getOperand(0);
13559 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
13560 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
13562 MVT EltVT = VT.getVectorElementType();
13563 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
13565 EVT ExtraEltVT = ExtraVT.getVectorElementType();
13566 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
13567 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
13569 SDValue Extra = DAG.getValueType(ExtraVT);
13571 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
13572 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
13574 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
13579 SDValue Op0 = Op.getOperand(0);
13580 SDValue Op00 = Op0.getOperand(0);
13582 // Hopefully, this VECTOR_SHUFFLE is just a VZEXT.
13583 if (Op0.getOpcode() == ISD::BITCAST &&
13584 Op00.getOpcode() == ISD::VECTOR_SHUFFLE) {
13585 // (sext (vzext x)) -> (vsext x)
13586 Tmp1 = LowerVectorIntExtend(Op00, Subtarget, DAG);
13587 if (Tmp1.getNode()) {
13588 EVT ExtraEltVT = ExtraVT.getVectorElementType();
13589 // This folding is only valid when the in-reg type is a vector of i8,
13591 if (ExtraEltVT == MVT::i8 || ExtraEltVT == MVT::i16 ||
13592 ExtraEltVT == MVT::i32) {
13593 SDValue Tmp1Op0 = Tmp1.getOperand(0);
13594 assert(Tmp1Op0.getOpcode() == X86ISD::VZEXT &&
13595 "This optimization is invalid without a VZEXT.");
13596 return DAG.getNode(X86ISD::VSEXT, dl, VT, Tmp1Op0.getOperand(0));
13602 // If the above didn't work, then just use Shift-Left + Shift-Right.
13603 Tmp1 = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, Op0, BitsDiff,
13605 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, Tmp1, BitsDiff,
13611 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
13612 SelectionDAG &DAG) {
13614 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
13615 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
13616 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
13617 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
13619 // The only fence that needs an instruction is a sequentially-consistent
13620 // cross-thread fence.
13621 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
13622 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
13623 // no-sse2). There isn't any reason to disable it if the target processor
13625 if (Subtarget->hasSSE2() || Subtarget->is64Bit())
13626 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
13628 SDValue Chain = Op.getOperand(0);
13629 SDValue Zero = DAG.getConstant(0, MVT::i32);
13631 DAG.getRegister(X86::ESP, MVT::i32), // Base
13632 DAG.getTargetConstant(1, MVT::i8), // Scale
13633 DAG.getRegister(0, MVT::i32), // Index
13634 DAG.getTargetConstant(0, MVT::i32), // Disp
13635 DAG.getRegister(0, MVT::i32), // Segment.
13639 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
13640 return SDValue(Res, 0);
13643 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
13644 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
13647 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
13648 SelectionDAG &DAG) {
13649 MVT T = Op.getSimpleValueType();
13653 switch(T.SimpleTy) {
13654 default: llvm_unreachable("Invalid value type!");
13655 case MVT::i8: Reg = X86::AL; size = 1; break;
13656 case MVT::i16: Reg = X86::AX; size = 2; break;
13657 case MVT::i32: Reg = X86::EAX; size = 4; break;
13659 assert(Subtarget->is64Bit() && "Node not type legal!");
13660 Reg = X86::RAX; size = 8;
13663 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
13664 Op.getOperand(2), SDValue());
13665 SDValue Ops[] = { cpIn.getValue(0),
13668 DAG.getTargetConstant(size, MVT::i8),
13669 cpIn.getValue(1) };
13670 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
13671 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
13672 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
13673 Ops, array_lengthof(Ops), T, MMO);
13675 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
13679 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
13680 SelectionDAG &DAG) {
13681 assert(Subtarget->is64Bit() && "Result not type legalized?");
13682 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
13683 SDValue TheChain = Op.getOperand(0);
13685 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
13686 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
13687 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
13689 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
13690 DAG.getConstant(32, MVT::i8));
13692 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
13695 return DAG.getMergeValues(Ops, array_lengthof(Ops), dl);
13698 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
13699 SelectionDAG &DAG) {
13700 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
13701 MVT DstVT = Op.getSimpleValueType();
13702 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
13703 Subtarget->hasMMX() && "Unexpected custom BITCAST");
13704 assert((DstVT == MVT::i64 ||
13705 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
13706 "Unexpected custom BITCAST");
13707 // i64 <=> MMX conversions are Legal.
13708 if (SrcVT==MVT::i64 && DstVT.isVector())
13710 if (DstVT==MVT::i64 && SrcVT.isVector())
13712 // MMX <=> MMX conversions are Legal.
13713 if (SrcVT.isVector() && DstVT.isVector())
13715 // All other conversions need to be expanded.
13719 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
13720 SDNode *Node = Op.getNode();
13722 EVT T = Node->getValueType(0);
13723 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
13724 DAG.getConstant(0, T), Node->getOperand(2));
13725 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
13726 cast<AtomicSDNode>(Node)->getMemoryVT(),
13727 Node->getOperand(0),
13728 Node->getOperand(1), negOp,
13729 cast<AtomicSDNode>(Node)->getSrcValue(),
13730 cast<AtomicSDNode>(Node)->getAlignment(),
13731 cast<AtomicSDNode>(Node)->getOrdering(),
13732 cast<AtomicSDNode>(Node)->getSynchScope());
13735 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
13736 SDNode *Node = Op.getNode();
13738 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
13740 // Convert seq_cst store -> xchg
13741 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
13742 // FIXME: On 32-bit, store -> fist or movq would be more efficient
13743 // (The only way to get a 16-byte store is cmpxchg16b)
13744 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
13745 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
13746 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
13747 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
13748 cast<AtomicSDNode>(Node)->getMemoryVT(),
13749 Node->getOperand(0),
13750 Node->getOperand(1), Node->getOperand(2),
13751 cast<AtomicSDNode>(Node)->getMemOperand(),
13752 cast<AtomicSDNode>(Node)->getOrdering(),
13753 cast<AtomicSDNode>(Node)->getSynchScope());
13754 return Swap.getValue(1);
13756 // Other atomic stores have a simple pattern.
13760 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
13761 EVT VT = Op.getNode()->getSimpleValueType(0);
13763 // Let legalize expand this if it isn't a legal type yet.
13764 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
13767 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
13770 bool ExtraOp = false;
13771 switch (Op.getOpcode()) {
13772 default: llvm_unreachable("Invalid code");
13773 case ISD::ADDC: Opc = X86ISD::ADD; break;
13774 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
13775 case ISD::SUBC: Opc = X86ISD::SUB; break;
13776 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
13780 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
13782 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
13783 Op.getOperand(1), Op.getOperand(2));
13786 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
13787 SelectionDAG &DAG) {
13788 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
13790 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
13791 // which returns the values as { float, float } (in XMM0) or
13792 // { double, double } (which is returned in XMM0, XMM1).
13794 SDValue Arg = Op.getOperand(0);
13795 EVT ArgVT = Arg.getValueType();
13796 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
13798 TargetLowering::ArgListTy Args;
13799 TargetLowering::ArgListEntry Entry;
13803 Entry.isSExt = false;
13804 Entry.isZExt = false;
13805 Args.push_back(Entry);
13807 bool isF64 = ArgVT == MVT::f64;
13808 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
13809 // the small struct {f32, f32} is returned in (eax, edx). For f64,
13810 // the results are returned via SRet in memory.
13811 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
13812 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13813 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
13815 Type *RetTy = isF64
13816 ? (Type*)StructType::get(ArgTy, ArgTy, NULL)
13817 : (Type*)VectorType::get(ArgTy, 4);
13819 CallLoweringInfo CLI(DAG.getEntryNode(), RetTy,
13820 false, false, false, false, 0,
13821 CallingConv::C, /*isTaillCall=*/false,
13822 /*doesNotRet=*/false, /*isReturnValueUsed*/true,
13823 Callee, Args, DAG, dl);
13824 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
13827 // Returned in xmm0 and xmm1.
13828 return CallResult.first;
13830 // Returned in bits 0:31 and 32:64 xmm0.
13831 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
13832 CallResult.first, DAG.getIntPtrConstant(0));
13833 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
13834 CallResult.first, DAG.getIntPtrConstant(1));
13835 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
13836 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
13839 /// LowerOperation - Provide custom lowering hooks for some operations.
13841 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
13842 switch (Op.getOpcode()) {
13843 default: llvm_unreachable("Should not custom lower this!");
13844 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
13845 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
13846 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op, Subtarget, DAG);
13847 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
13848 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
13849 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
13850 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
13851 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
13852 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
13853 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
13854 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
13855 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
13856 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
13857 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
13858 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
13859 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
13860 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
13861 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
13862 case ISD::SHL_PARTS:
13863 case ISD::SRA_PARTS:
13864 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
13865 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
13866 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
13867 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
13868 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
13869 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
13870 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
13871 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
13872 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
13873 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
13874 case ISD::FABS: return LowerFABS(Op, DAG);
13875 case ISD::FNEG: return LowerFNEG(Op, DAG);
13876 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
13877 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
13878 case ISD::SETCC: return LowerSETCC(Op, DAG);
13879 case ISD::SELECT: return LowerSELECT(Op, DAG);
13880 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
13881 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
13882 case ISD::VASTART: return LowerVASTART(Op, DAG);
13883 case ISD::VAARG: return LowerVAARG(Op, DAG);
13884 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
13885 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
13886 case ISD::INTRINSIC_VOID:
13887 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
13888 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
13889 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
13890 case ISD::FRAME_TO_ARGS_OFFSET:
13891 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
13892 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
13893 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
13894 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
13895 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
13896 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
13897 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
13898 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
13899 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
13900 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
13901 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
13902 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
13905 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
13911 case ISD::UMULO: return LowerXALUO(Op, DAG);
13912 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
13913 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
13917 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
13918 case ISD::ADD: return LowerADD(Op, DAG);
13919 case ISD::SUB: return LowerSUB(Op, DAG);
13920 case ISD::SDIV: return LowerSDIV(Op, DAG);
13921 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
13925 static void ReplaceATOMIC_LOAD(SDNode *Node,
13926 SmallVectorImpl<SDValue> &Results,
13927 SelectionDAG &DAG) {
13929 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
13931 // Convert wide load -> cmpxchg8b/cmpxchg16b
13932 // FIXME: On 32-bit, load -> fild or movq would be more efficient
13933 // (The only way to get a 16-byte load is cmpxchg16b)
13934 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment.
13935 SDValue Zero = DAG.getConstant(0, VT);
13936 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT,
13937 Node->getOperand(0),
13938 Node->getOperand(1), Zero, Zero,
13939 cast<AtomicSDNode>(Node)->getMemOperand(),
13940 cast<AtomicSDNode>(Node)->getOrdering(),
13941 cast<AtomicSDNode>(Node)->getOrdering(),
13942 cast<AtomicSDNode>(Node)->getSynchScope());
13943 Results.push_back(Swap.getValue(0));
13944 Results.push_back(Swap.getValue(1));
13948 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
13949 SelectionDAG &DAG, unsigned NewOp) {
13951 assert (Node->getValueType(0) == MVT::i64 &&
13952 "Only know how to expand i64 atomics");
13954 SDValue Chain = Node->getOperand(0);
13955 SDValue In1 = Node->getOperand(1);
13956 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
13957 Node->getOperand(2), DAG.getIntPtrConstant(0));
13958 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
13959 Node->getOperand(2), DAG.getIntPtrConstant(1));
13960 SDValue Ops[] = { Chain, In1, In2L, In2H };
13961 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
13963 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, array_lengthof(Ops), MVT::i64,
13964 cast<MemSDNode>(Node)->getMemOperand());
13965 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
13966 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
13967 Results.push_back(Result.getValue(2));
13970 /// ReplaceNodeResults - Replace a node with an illegal result type
13971 /// with a new node built out of custom code.
13972 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
13973 SmallVectorImpl<SDValue>&Results,
13974 SelectionDAG &DAG) const {
13976 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13977 switch (N->getOpcode()) {
13979 llvm_unreachable("Do not know how to custom type legalize this operation!");
13980 case ISD::SIGN_EXTEND_INREG:
13985 // We don't want to expand or promote these.
13987 case ISD::FP_TO_SINT:
13988 case ISD::FP_TO_UINT: {
13989 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
13991 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
13994 std::pair<SDValue,SDValue> Vals =
13995 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
13996 SDValue FIST = Vals.first, StackSlot = Vals.second;
13997 if (FIST.getNode() != 0) {
13998 EVT VT = N->getValueType(0);
13999 // Return a load from the stack slot.
14000 if (StackSlot.getNode() != 0)
14001 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
14002 MachinePointerInfo(),
14003 false, false, false, 0));
14005 Results.push_back(FIST);
14009 case ISD::UINT_TO_FP: {
14010 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
14011 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
14012 N->getValueType(0) != MVT::v2f32)
14014 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
14016 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
14018 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
14019 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
14020 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
14021 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
14022 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
14023 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
14026 case ISD::FP_ROUND: {
14027 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
14029 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
14030 Results.push_back(V);
14033 case ISD::READCYCLECOUNTER: {
14034 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
14035 SDValue TheChain = N->getOperand(0);
14036 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
14037 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
14039 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
14041 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
14042 SDValue Ops[] = { eax, edx };
14043 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops,
14044 array_lengthof(Ops)));
14045 Results.push_back(edx.getValue(1));
14048 case ISD::ATOMIC_CMP_SWAP: {
14049 EVT T = N->getValueType(0);
14050 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
14051 bool Regs64bit = T == MVT::i128;
14052 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
14053 SDValue cpInL, cpInH;
14054 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
14055 DAG.getConstant(0, HalfT));
14056 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
14057 DAG.getConstant(1, HalfT));
14058 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
14059 Regs64bit ? X86::RAX : X86::EAX,
14061 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
14062 Regs64bit ? X86::RDX : X86::EDX,
14063 cpInH, cpInL.getValue(1));
14064 SDValue swapInL, swapInH;
14065 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
14066 DAG.getConstant(0, HalfT));
14067 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
14068 DAG.getConstant(1, HalfT));
14069 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
14070 Regs64bit ? X86::RBX : X86::EBX,
14071 swapInL, cpInH.getValue(1));
14072 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
14073 Regs64bit ? X86::RCX : X86::ECX,
14074 swapInH, swapInL.getValue(1));
14075 SDValue Ops[] = { swapInH.getValue(0),
14077 swapInH.getValue(1) };
14078 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
14079 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
14080 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
14081 X86ISD::LCMPXCHG8_DAG;
14082 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys,
14083 Ops, array_lengthof(Ops), T, MMO);
14084 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
14085 Regs64bit ? X86::RAX : X86::EAX,
14086 HalfT, Result.getValue(1));
14087 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
14088 Regs64bit ? X86::RDX : X86::EDX,
14089 HalfT, cpOutL.getValue(2));
14090 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
14091 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF, 2));
14092 Results.push_back(cpOutH.getValue(1));
14095 case ISD::ATOMIC_LOAD_ADD:
14096 case ISD::ATOMIC_LOAD_AND:
14097 case ISD::ATOMIC_LOAD_NAND:
14098 case ISD::ATOMIC_LOAD_OR:
14099 case ISD::ATOMIC_LOAD_SUB:
14100 case ISD::ATOMIC_LOAD_XOR:
14101 case ISD::ATOMIC_LOAD_MAX:
14102 case ISD::ATOMIC_LOAD_MIN:
14103 case ISD::ATOMIC_LOAD_UMAX:
14104 case ISD::ATOMIC_LOAD_UMIN:
14105 case ISD::ATOMIC_SWAP: {
14107 switch (N->getOpcode()) {
14108 default: llvm_unreachable("Unexpected opcode");
14109 case ISD::ATOMIC_LOAD_ADD:
14110 Opc = X86ISD::ATOMADD64_DAG;
14112 case ISD::ATOMIC_LOAD_AND:
14113 Opc = X86ISD::ATOMAND64_DAG;
14115 case ISD::ATOMIC_LOAD_NAND:
14116 Opc = X86ISD::ATOMNAND64_DAG;
14118 case ISD::ATOMIC_LOAD_OR:
14119 Opc = X86ISD::ATOMOR64_DAG;
14121 case ISD::ATOMIC_LOAD_SUB:
14122 Opc = X86ISD::ATOMSUB64_DAG;
14124 case ISD::ATOMIC_LOAD_XOR:
14125 Opc = X86ISD::ATOMXOR64_DAG;
14127 case ISD::ATOMIC_LOAD_MAX:
14128 Opc = X86ISD::ATOMMAX64_DAG;
14130 case ISD::ATOMIC_LOAD_MIN:
14131 Opc = X86ISD::ATOMMIN64_DAG;
14133 case ISD::ATOMIC_LOAD_UMAX:
14134 Opc = X86ISD::ATOMUMAX64_DAG;
14136 case ISD::ATOMIC_LOAD_UMIN:
14137 Opc = X86ISD::ATOMUMIN64_DAG;
14139 case ISD::ATOMIC_SWAP:
14140 Opc = X86ISD::ATOMSWAP64_DAG;
14143 ReplaceATOMIC_BINARY_64(N, Results, DAG, Opc);
14146 case ISD::ATOMIC_LOAD:
14147 ReplaceATOMIC_LOAD(N, Results, DAG);
14151 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
14153 default: return NULL;
14154 case X86ISD::BSF: return "X86ISD::BSF";
14155 case X86ISD::BSR: return "X86ISD::BSR";
14156 case X86ISD::SHLD: return "X86ISD::SHLD";
14157 case X86ISD::SHRD: return "X86ISD::SHRD";
14158 case X86ISD::FAND: return "X86ISD::FAND";
14159 case X86ISD::FANDN: return "X86ISD::FANDN";
14160 case X86ISD::FOR: return "X86ISD::FOR";
14161 case X86ISD::FXOR: return "X86ISD::FXOR";
14162 case X86ISD::FSRL: return "X86ISD::FSRL";
14163 case X86ISD::FILD: return "X86ISD::FILD";
14164 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
14165 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
14166 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
14167 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
14168 case X86ISD::FLD: return "X86ISD::FLD";
14169 case X86ISD::FST: return "X86ISD::FST";
14170 case X86ISD::CALL: return "X86ISD::CALL";
14171 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
14172 case X86ISD::BT: return "X86ISD::BT";
14173 case X86ISD::CMP: return "X86ISD::CMP";
14174 case X86ISD::COMI: return "X86ISD::COMI";
14175 case X86ISD::UCOMI: return "X86ISD::UCOMI";
14176 case X86ISD::CMPM: return "X86ISD::CMPM";
14177 case X86ISD::CMPMU: return "X86ISD::CMPMU";
14178 case X86ISD::SETCC: return "X86ISD::SETCC";
14179 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
14180 case X86ISD::FSETCC: return "X86ISD::FSETCC";
14181 case X86ISD::CMOV: return "X86ISD::CMOV";
14182 case X86ISD::BRCOND: return "X86ISD::BRCOND";
14183 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
14184 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
14185 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
14186 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
14187 case X86ISD::Wrapper: return "X86ISD::Wrapper";
14188 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
14189 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
14190 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
14191 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
14192 case X86ISD::PINSRB: return "X86ISD::PINSRB";
14193 case X86ISD::PINSRW: return "X86ISD::PINSRW";
14194 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
14195 case X86ISD::ANDNP: return "X86ISD::ANDNP";
14196 case X86ISD::PSIGN: return "X86ISD::PSIGN";
14197 case X86ISD::BLENDV: return "X86ISD::BLENDV";
14198 case X86ISD::BLENDI: return "X86ISD::BLENDI";
14199 case X86ISD::SUBUS: return "X86ISD::SUBUS";
14200 case X86ISD::HADD: return "X86ISD::HADD";
14201 case X86ISD::HSUB: return "X86ISD::HSUB";
14202 case X86ISD::FHADD: return "X86ISD::FHADD";
14203 case X86ISD::FHSUB: return "X86ISD::FHSUB";
14204 case X86ISD::UMAX: return "X86ISD::UMAX";
14205 case X86ISD::UMIN: return "X86ISD::UMIN";
14206 case X86ISD::SMAX: return "X86ISD::SMAX";
14207 case X86ISD::SMIN: return "X86ISD::SMIN";
14208 case X86ISD::FMAX: return "X86ISD::FMAX";
14209 case X86ISD::FMIN: return "X86ISD::FMIN";
14210 case X86ISD::FMAXC: return "X86ISD::FMAXC";
14211 case X86ISD::FMINC: return "X86ISD::FMINC";
14212 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
14213 case X86ISD::FRCP: return "X86ISD::FRCP";
14214 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
14215 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
14216 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
14217 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
14218 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
14219 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
14220 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
14221 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
14222 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
14223 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
14224 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
14225 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
14226 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
14227 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
14228 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
14229 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
14230 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
14231 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
14232 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
14233 case X86ISD::VZEXT: return "X86ISD::VZEXT";
14234 case X86ISD::VSEXT: return "X86ISD::VSEXT";
14235 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
14236 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
14237 case X86ISD::VINSERT: return "X86ISD::VINSERT";
14238 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
14239 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
14240 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
14241 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
14242 case X86ISD::VSHL: return "X86ISD::VSHL";
14243 case X86ISD::VSRL: return "X86ISD::VSRL";
14244 case X86ISD::VSRA: return "X86ISD::VSRA";
14245 case X86ISD::VSHLI: return "X86ISD::VSHLI";
14246 case X86ISD::VSRLI: return "X86ISD::VSRLI";
14247 case X86ISD::VSRAI: return "X86ISD::VSRAI";
14248 case X86ISD::CMPP: return "X86ISD::CMPP";
14249 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
14250 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
14251 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
14252 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
14253 case X86ISD::ADD: return "X86ISD::ADD";
14254 case X86ISD::SUB: return "X86ISD::SUB";
14255 case X86ISD::ADC: return "X86ISD::ADC";
14256 case X86ISD::SBB: return "X86ISD::SBB";
14257 case X86ISD::SMUL: return "X86ISD::SMUL";
14258 case X86ISD::UMUL: return "X86ISD::UMUL";
14259 case X86ISD::INC: return "X86ISD::INC";
14260 case X86ISD::DEC: return "X86ISD::DEC";
14261 case X86ISD::OR: return "X86ISD::OR";
14262 case X86ISD::XOR: return "X86ISD::XOR";
14263 case X86ISD::AND: return "X86ISD::AND";
14264 case X86ISD::BZHI: return "X86ISD::BZHI";
14265 case X86ISD::BEXTR: return "X86ISD::BEXTR";
14266 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
14267 case X86ISD::PTEST: return "X86ISD::PTEST";
14268 case X86ISD::TESTP: return "X86ISD::TESTP";
14269 case X86ISD::TESTM: return "X86ISD::TESTM";
14270 case X86ISD::TESTNM: return "X86ISD::TESTNM";
14271 case X86ISD::KORTEST: return "X86ISD::KORTEST";
14272 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
14273 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
14274 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
14275 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
14276 case X86ISD::SHUFP: return "X86ISD::SHUFP";
14277 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
14278 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
14279 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
14280 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
14281 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
14282 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
14283 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
14284 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
14285 case X86ISD::MOVSD: return "X86ISD::MOVSD";
14286 case X86ISD::MOVSS: return "X86ISD::MOVSS";
14287 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
14288 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
14289 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
14290 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
14291 case X86ISD::VPERMILP: return "X86ISD::VPERMILP";
14292 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
14293 case X86ISD::VPERMV: return "X86ISD::VPERMV";
14294 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
14295 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
14296 case X86ISD::VPERMI: return "X86ISD::VPERMI";
14297 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
14298 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
14299 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
14300 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
14301 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
14302 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
14303 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
14304 case X86ISD::SAHF: return "X86ISD::SAHF";
14305 case X86ISD::RDRAND: return "X86ISD::RDRAND";
14306 case X86ISD::RDSEED: return "X86ISD::RDSEED";
14307 case X86ISD::FMADD: return "X86ISD::FMADD";
14308 case X86ISD::FMSUB: return "X86ISD::FMSUB";
14309 case X86ISD::FNMADD: return "X86ISD::FNMADD";
14310 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
14311 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
14312 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
14313 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
14314 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
14315 case X86ISD::XTEST: return "X86ISD::XTEST";
14319 // isLegalAddressingMode - Return true if the addressing mode represented
14320 // by AM is legal for this target, for a load/store of the specified type.
14321 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
14323 // X86 supports extremely general addressing modes.
14324 CodeModel::Model M = getTargetMachine().getCodeModel();
14325 Reloc::Model R = getTargetMachine().getRelocationModel();
14327 // X86 allows a sign-extended 32-bit immediate field as a displacement.
14328 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
14333 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
14335 // If a reference to this global requires an extra load, we can't fold it.
14336 if (isGlobalStubReference(GVFlags))
14339 // If BaseGV requires a register for the PIC base, we cannot also have a
14340 // BaseReg specified.
14341 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
14344 // If lower 4G is not available, then we must use rip-relative addressing.
14345 if ((M != CodeModel::Small || R != Reloc::Static) &&
14346 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
14350 switch (AM.Scale) {
14356 // These scales always work.
14361 // These scales are formed with basereg+scalereg. Only accept if there is
14366 default: // Other stuff never works.
14373 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
14374 unsigned Bits = Ty->getScalarSizeInBits();
14376 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
14377 // particularly cheaper than those without.
14381 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
14382 // variable shifts just as cheap as scalar ones.
14383 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
14386 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
14387 // fully general vector.
14391 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
14392 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
14394 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
14395 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
14396 return NumBits1 > NumBits2;
14399 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
14400 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
14403 if (!isTypeLegal(EVT::getEVT(Ty1)))
14406 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
14408 // Assuming the caller doesn't have a zeroext or signext return parameter,
14409 // truncation all the way down to i1 is valid.
14413 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
14414 return isInt<32>(Imm);
14417 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
14418 // Can also use sub to handle negated immediates.
14419 return isInt<32>(Imm);
14422 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
14423 if (!VT1.isInteger() || !VT2.isInteger())
14425 unsigned NumBits1 = VT1.getSizeInBits();
14426 unsigned NumBits2 = VT2.getSizeInBits();
14427 return NumBits1 > NumBits2;
14430 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
14431 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
14432 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
14435 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
14436 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
14437 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
14440 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
14441 EVT VT1 = Val.getValueType();
14442 if (isZExtFree(VT1, VT2))
14445 if (Val.getOpcode() != ISD::LOAD)
14448 if (!VT1.isSimple() || !VT1.isInteger() ||
14449 !VT2.isSimple() || !VT2.isInteger())
14452 switch (VT1.getSimpleVT().SimpleTy) {
14457 // X86 has 8, 16, and 32-bit zero-extending loads.
14465 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
14466 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
14469 VT = VT.getScalarType();
14471 if (!VT.isSimple())
14474 switch (VT.getSimpleVT().SimpleTy) {
14485 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
14486 // i16 instructions are longer (0x66 prefix) and potentially slower.
14487 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
14490 /// isShuffleMaskLegal - Targets can use this to indicate that they only
14491 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
14492 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
14493 /// are assumed to be legal.
14495 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
14497 if (!VT.isSimple())
14500 MVT SVT = VT.getSimpleVT();
14502 // Very little shuffling can be done for 64-bit vectors right now.
14503 if (VT.getSizeInBits() == 64)
14506 // FIXME: pshufb, blends, shifts.
14507 return (SVT.getVectorNumElements() == 2 ||
14508 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
14509 isMOVLMask(M, SVT) ||
14510 isSHUFPMask(M, SVT) ||
14511 isPSHUFDMask(M, SVT) ||
14512 isPSHUFHWMask(M, SVT, Subtarget->hasInt256()) ||
14513 isPSHUFLWMask(M, SVT, Subtarget->hasInt256()) ||
14514 isPALIGNRMask(M, SVT, Subtarget) ||
14515 isUNPCKLMask(M, SVT, Subtarget->hasInt256()) ||
14516 isUNPCKHMask(M, SVT, Subtarget->hasInt256()) ||
14517 isUNPCKL_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
14518 isUNPCKH_v_undef_Mask(M, SVT, Subtarget->hasInt256()));
14522 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
14524 if (!VT.isSimple())
14527 MVT SVT = VT.getSimpleVT();
14528 unsigned NumElts = SVT.getVectorNumElements();
14529 // FIXME: This collection of masks seems suspect.
14532 if (NumElts == 4 && SVT.is128BitVector()) {
14533 return (isMOVLMask(Mask, SVT) ||
14534 isCommutedMOVLMask(Mask, SVT, true) ||
14535 isSHUFPMask(Mask, SVT) ||
14536 isSHUFPMask(Mask, SVT, /* Commuted */ true));
14541 //===----------------------------------------------------------------------===//
14542 // X86 Scheduler Hooks
14543 //===----------------------------------------------------------------------===//
14545 /// Utility function to emit xbegin specifying the start of an RTM region.
14546 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
14547 const TargetInstrInfo *TII) {
14548 DebugLoc DL = MI->getDebugLoc();
14550 const BasicBlock *BB = MBB->getBasicBlock();
14551 MachineFunction::iterator I = MBB;
14554 // For the v = xbegin(), we generate
14565 MachineBasicBlock *thisMBB = MBB;
14566 MachineFunction *MF = MBB->getParent();
14567 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
14568 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
14569 MF->insert(I, mainMBB);
14570 MF->insert(I, sinkMBB);
14572 // Transfer the remainder of BB and its successor edges to sinkMBB.
14573 sinkMBB->splice(sinkMBB->begin(), MBB,
14574 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
14575 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
14579 // # fallthrough to mainMBB
14580 // # abortion to sinkMBB
14581 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
14582 thisMBB->addSuccessor(mainMBB);
14583 thisMBB->addSuccessor(sinkMBB);
14587 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
14588 mainMBB->addSuccessor(sinkMBB);
14591 // EAX is live into the sinkMBB
14592 sinkMBB->addLiveIn(X86::EAX);
14593 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
14594 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
14597 MI->eraseFromParent();
14601 // Get CMPXCHG opcode for the specified data type.
14602 static unsigned getCmpXChgOpcode(EVT VT) {
14603 switch (VT.getSimpleVT().SimpleTy) {
14604 case MVT::i8: return X86::LCMPXCHG8;
14605 case MVT::i16: return X86::LCMPXCHG16;
14606 case MVT::i32: return X86::LCMPXCHG32;
14607 case MVT::i64: return X86::LCMPXCHG64;
14611 llvm_unreachable("Invalid operand size!");
14614 // Get LOAD opcode for the specified data type.
14615 static unsigned getLoadOpcode(EVT VT) {
14616 switch (VT.getSimpleVT().SimpleTy) {
14617 case MVT::i8: return X86::MOV8rm;
14618 case MVT::i16: return X86::MOV16rm;
14619 case MVT::i32: return X86::MOV32rm;
14620 case MVT::i64: return X86::MOV64rm;
14624 llvm_unreachable("Invalid operand size!");
14627 // Get opcode of the non-atomic one from the specified atomic instruction.
14628 static unsigned getNonAtomicOpcode(unsigned Opc) {
14630 case X86::ATOMAND8: return X86::AND8rr;
14631 case X86::ATOMAND16: return X86::AND16rr;
14632 case X86::ATOMAND32: return X86::AND32rr;
14633 case X86::ATOMAND64: return X86::AND64rr;
14634 case X86::ATOMOR8: return X86::OR8rr;
14635 case X86::ATOMOR16: return X86::OR16rr;
14636 case X86::ATOMOR32: return X86::OR32rr;
14637 case X86::ATOMOR64: return X86::OR64rr;
14638 case X86::ATOMXOR8: return X86::XOR8rr;
14639 case X86::ATOMXOR16: return X86::XOR16rr;
14640 case X86::ATOMXOR32: return X86::XOR32rr;
14641 case X86::ATOMXOR64: return X86::XOR64rr;
14643 llvm_unreachable("Unhandled atomic-load-op opcode!");
14646 // Get opcode of the non-atomic one from the specified atomic instruction with
14648 static unsigned getNonAtomicOpcodeWithExtraOpc(unsigned Opc,
14649 unsigned &ExtraOpc) {
14651 case X86::ATOMNAND8: ExtraOpc = X86::NOT8r; return X86::AND8rr;
14652 case X86::ATOMNAND16: ExtraOpc = X86::NOT16r; return X86::AND16rr;
14653 case X86::ATOMNAND32: ExtraOpc = X86::NOT32r; return X86::AND32rr;
14654 case X86::ATOMNAND64: ExtraOpc = X86::NOT64r; return X86::AND64rr;
14655 case X86::ATOMMAX8: ExtraOpc = X86::CMP8rr; return X86::CMOVL32rr;
14656 case X86::ATOMMAX16: ExtraOpc = X86::CMP16rr; return X86::CMOVL16rr;
14657 case X86::ATOMMAX32: ExtraOpc = X86::CMP32rr; return X86::CMOVL32rr;
14658 case X86::ATOMMAX64: ExtraOpc = X86::CMP64rr; return X86::CMOVL64rr;
14659 case X86::ATOMMIN8: ExtraOpc = X86::CMP8rr; return X86::CMOVG32rr;
14660 case X86::ATOMMIN16: ExtraOpc = X86::CMP16rr; return X86::CMOVG16rr;
14661 case X86::ATOMMIN32: ExtraOpc = X86::CMP32rr; return X86::CMOVG32rr;
14662 case X86::ATOMMIN64: ExtraOpc = X86::CMP64rr; return X86::CMOVG64rr;
14663 case X86::ATOMUMAX8: ExtraOpc = X86::CMP8rr; return X86::CMOVB32rr;
14664 case X86::ATOMUMAX16: ExtraOpc = X86::CMP16rr; return X86::CMOVB16rr;
14665 case X86::ATOMUMAX32: ExtraOpc = X86::CMP32rr; return X86::CMOVB32rr;
14666 case X86::ATOMUMAX64: ExtraOpc = X86::CMP64rr; return X86::CMOVB64rr;
14667 case X86::ATOMUMIN8: ExtraOpc = X86::CMP8rr; return X86::CMOVA32rr;
14668 case X86::ATOMUMIN16: ExtraOpc = X86::CMP16rr; return X86::CMOVA16rr;
14669 case X86::ATOMUMIN32: ExtraOpc = X86::CMP32rr; return X86::CMOVA32rr;
14670 case X86::ATOMUMIN64: ExtraOpc = X86::CMP64rr; return X86::CMOVA64rr;
14672 llvm_unreachable("Unhandled atomic-load-op opcode!");
14675 // Get opcode of the non-atomic one from the specified atomic instruction for
14676 // 64-bit data type on 32-bit target.
14677 static unsigned getNonAtomic6432Opcode(unsigned Opc, unsigned &HiOpc) {
14679 case X86::ATOMAND6432: HiOpc = X86::AND32rr; return X86::AND32rr;
14680 case X86::ATOMOR6432: HiOpc = X86::OR32rr; return X86::OR32rr;
14681 case X86::ATOMXOR6432: HiOpc = X86::XOR32rr; return X86::XOR32rr;
14682 case X86::ATOMADD6432: HiOpc = X86::ADC32rr; return X86::ADD32rr;
14683 case X86::ATOMSUB6432: HiOpc = X86::SBB32rr; return X86::SUB32rr;
14684 case X86::ATOMSWAP6432: HiOpc = X86::MOV32rr; return X86::MOV32rr;
14685 case X86::ATOMMAX6432: HiOpc = X86::SETLr; return X86::SETLr;
14686 case X86::ATOMMIN6432: HiOpc = X86::SETGr; return X86::SETGr;
14687 case X86::ATOMUMAX6432: HiOpc = X86::SETBr; return X86::SETBr;
14688 case X86::ATOMUMIN6432: HiOpc = X86::SETAr; return X86::SETAr;
14690 llvm_unreachable("Unhandled atomic-load-op opcode!");
14693 // Get opcode of the non-atomic one from the specified atomic instruction for
14694 // 64-bit data type on 32-bit target with extra opcode.
14695 static unsigned getNonAtomic6432OpcodeWithExtraOpc(unsigned Opc,
14697 unsigned &ExtraOpc) {
14699 case X86::ATOMNAND6432:
14700 ExtraOpc = X86::NOT32r;
14701 HiOpc = X86::AND32rr;
14702 return X86::AND32rr;
14704 llvm_unreachable("Unhandled atomic-load-op opcode!");
14707 // Get pseudo CMOV opcode from the specified data type.
14708 static unsigned getPseudoCMOVOpc(EVT VT) {
14709 switch (VT.getSimpleVT().SimpleTy) {
14710 case MVT::i8: return X86::CMOV_GR8;
14711 case MVT::i16: return X86::CMOV_GR16;
14712 case MVT::i32: return X86::CMOV_GR32;
14716 llvm_unreachable("Unknown CMOV opcode!");
14719 // EmitAtomicLoadArith - emit the code sequence for pseudo atomic instructions.
14720 // They will be translated into a spin-loop or compare-exchange loop from
14723 // dst = atomic-fetch-op MI.addr, MI.val
14729 // t1 = LOAD MI.addr
14731 // t4 = phi(t1, t3 / loop)
14732 // t2 = OP MI.val, t4
14734 // LCMPXCHG [MI.addr], t2, [EAX is implicitly used & defined]
14740 MachineBasicBlock *
14741 X86TargetLowering::EmitAtomicLoadArith(MachineInstr *MI,
14742 MachineBasicBlock *MBB) const {
14743 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
14744 DebugLoc DL = MI->getDebugLoc();
14746 MachineFunction *MF = MBB->getParent();
14747 MachineRegisterInfo &MRI = MF->getRegInfo();
14749 const BasicBlock *BB = MBB->getBasicBlock();
14750 MachineFunction::iterator I = MBB;
14753 assert(MI->getNumOperands() <= X86::AddrNumOperands + 4 &&
14754 "Unexpected number of operands");
14756 assert(MI->hasOneMemOperand() &&
14757 "Expected atomic-load-op to have one memoperand");
14759 // Memory Reference
14760 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
14761 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
14763 unsigned DstReg, SrcReg;
14764 unsigned MemOpndSlot;
14766 unsigned CurOp = 0;
14768 DstReg = MI->getOperand(CurOp++).getReg();
14769 MemOpndSlot = CurOp;
14770 CurOp += X86::AddrNumOperands;
14771 SrcReg = MI->getOperand(CurOp++).getReg();
14773 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
14774 MVT::SimpleValueType VT = *RC->vt_begin();
14775 unsigned t1 = MRI.createVirtualRegister(RC);
14776 unsigned t2 = MRI.createVirtualRegister(RC);
14777 unsigned t3 = MRI.createVirtualRegister(RC);
14778 unsigned t4 = MRI.createVirtualRegister(RC);
14779 unsigned PhyReg = getX86SubSuperRegister(X86::EAX, VT);
14781 unsigned LCMPXCHGOpc = getCmpXChgOpcode(VT);
14782 unsigned LOADOpc = getLoadOpcode(VT);
14784 // For the atomic load-arith operator, we generate
14787 // t1 = LOAD [MI.addr]
14789 // t4 = phi(t1 / thisMBB, t3 / mainMBB)
14790 // t1 = OP MI.val, EAX
14792 // LCMPXCHG [MI.addr], t1, [EAX is implicitly used & defined]
14798 MachineBasicBlock *thisMBB = MBB;
14799 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
14800 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
14801 MF->insert(I, mainMBB);
14802 MF->insert(I, sinkMBB);
14804 MachineInstrBuilder MIB;
14806 // Transfer the remainder of BB and its successor edges to sinkMBB.
14807 sinkMBB->splice(sinkMBB->begin(), MBB,
14808 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
14809 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
14812 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), t1);
14813 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14814 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
14816 NewMO.setIsKill(false);
14817 MIB.addOperand(NewMO);
14819 for (MachineInstr::mmo_iterator MMOI = MMOBegin; MMOI != MMOEnd; ++MMOI) {
14820 unsigned flags = (*MMOI)->getFlags();
14821 flags = (flags & ~MachineMemOperand::MOStore) | MachineMemOperand::MOLoad;
14822 MachineMemOperand *MMO =
14823 MF->getMachineMemOperand((*MMOI)->getPointerInfo(), flags,
14824 (*MMOI)->getSize(),
14825 (*MMOI)->getBaseAlignment(),
14826 (*MMOI)->getTBAAInfo(),
14827 (*MMOI)->getRanges());
14828 MIB.addMemOperand(MMO);
14831 thisMBB->addSuccessor(mainMBB);
14834 MachineBasicBlock *origMainMBB = mainMBB;
14837 MachineInstr *Phi = BuildMI(mainMBB, DL, TII->get(X86::PHI), t4)
14838 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(mainMBB);
14840 unsigned Opc = MI->getOpcode();
14843 llvm_unreachable("Unhandled atomic-load-op opcode!");
14844 case X86::ATOMAND8:
14845 case X86::ATOMAND16:
14846 case X86::ATOMAND32:
14847 case X86::ATOMAND64:
14849 case X86::ATOMOR16:
14850 case X86::ATOMOR32:
14851 case X86::ATOMOR64:
14852 case X86::ATOMXOR8:
14853 case X86::ATOMXOR16:
14854 case X86::ATOMXOR32:
14855 case X86::ATOMXOR64: {
14856 unsigned ARITHOpc = getNonAtomicOpcode(Opc);
14857 BuildMI(mainMBB, DL, TII->get(ARITHOpc), t2).addReg(SrcReg)
14861 case X86::ATOMNAND8:
14862 case X86::ATOMNAND16:
14863 case X86::ATOMNAND32:
14864 case X86::ATOMNAND64: {
14865 unsigned Tmp = MRI.createVirtualRegister(RC);
14867 unsigned ANDOpc = getNonAtomicOpcodeWithExtraOpc(Opc, NOTOpc);
14868 BuildMI(mainMBB, DL, TII->get(ANDOpc), Tmp).addReg(SrcReg)
14870 BuildMI(mainMBB, DL, TII->get(NOTOpc), t2).addReg(Tmp);
14873 case X86::ATOMMAX8:
14874 case X86::ATOMMAX16:
14875 case X86::ATOMMAX32:
14876 case X86::ATOMMAX64:
14877 case X86::ATOMMIN8:
14878 case X86::ATOMMIN16:
14879 case X86::ATOMMIN32:
14880 case X86::ATOMMIN64:
14881 case X86::ATOMUMAX8:
14882 case X86::ATOMUMAX16:
14883 case X86::ATOMUMAX32:
14884 case X86::ATOMUMAX64:
14885 case X86::ATOMUMIN8:
14886 case X86::ATOMUMIN16:
14887 case X86::ATOMUMIN32:
14888 case X86::ATOMUMIN64: {
14890 unsigned CMOVOpc = getNonAtomicOpcodeWithExtraOpc(Opc, CMPOpc);
14892 BuildMI(mainMBB, DL, TII->get(CMPOpc))
14896 if (Subtarget->hasCMov()) {
14897 if (VT != MVT::i8) {
14899 BuildMI(mainMBB, DL, TII->get(CMOVOpc), t2)
14903 // Promote i8 to i32 to use CMOV32
14904 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
14905 const TargetRegisterClass *RC32 =
14906 TRI->getSubClassWithSubReg(getRegClassFor(MVT::i32), X86::sub_8bit);
14907 unsigned SrcReg32 = MRI.createVirtualRegister(RC32);
14908 unsigned AccReg32 = MRI.createVirtualRegister(RC32);
14909 unsigned Tmp = MRI.createVirtualRegister(RC32);
14911 unsigned Undef = MRI.createVirtualRegister(RC32);
14912 BuildMI(mainMBB, DL, TII->get(TargetOpcode::IMPLICIT_DEF), Undef);
14914 BuildMI(mainMBB, DL, TII->get(TargetOpcode::INSERT_SUBREG), SrcReg32)
14917 .addImm(X86::sub_8bit);
14918 BuildMI(mainMBB, DL, TII->get(TargetOpcode::INSERT_SUBREG), AccReg32)
14921 .addImm(X86::sub_8bit);
14923 BuildMI(mainMBB, DL, TII->get(CMOVOpc), Tmp)
14927 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t2)
14928 .addReg(Tmp, 0, X86::sub_8bit);
14931 // Use pseudo select and lower them.
14932 assert((VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32) &&
14933 "Invalid atomic-load-op transformation!");
14934 unsigned SelOpc = getPseudoCMOVOpc(VT);
14935 X86::CondCode CC = X86::getCondFromCMovOpc(CMOVOpc);
14936 assert(CC != X86::COND_INVALID && "Invalid atomic-load-op transformation!");
14937 MIB = BuildMI(mainMBB, DL, TII->get(SelOpc), t2)
14938 .addReg(SrcReg).addReg(t4)
14940 mainMBB = EmitLoweredSelect(MIB, mainMBB);
14941 // Replace the original PHI node as mainMBB is changed after CMOV
14943 BuildMI(*origMainMBB, Phi, DL, TII->get(X86::PHI), t4)
14944 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(mainMBB);
14945 Phi->eraseFromParent();
14951 // Copy PhyReg back from virtual register.
14952 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), PhyReg)
14955 MIB = BuildMI(mainMBB, DL, TII->get(LCMPXCHGOpc));
14956 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14957 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
14959 NewMO.setIsKill(false);
14960 MIB.addOperand(NewMO);
14963 MIB.setMemRefs(MMOBegin, MMOEnd);
14965 // Copy PhyReg back to virtual register.
14966 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t3)
14969 BuildMI(mainMBB, DL, TII->get(X86::JNE_4)).addMBB(origMainMBB);
14971 mainMBB->addSuccessor(origMainMBB);
14972 mainMBB->addSuccessor(sinkMBB);
14975 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
14976 TII->get(TargetOpcode::COPY), DstReg)
14979 MI->eraseFromParent();
14983 // EmitAtomicLoadArith6432 - emit the code sequence for pseudo atomic
14984 // instructions. They will be translated into a spin-loop or compare-exchange
14988 // dst = atomic-fetch-op MI.addr, MI.val
14994 // t1L = LOAD [MI.addr + 0]
14995 // t1H = LOAD [MI.addr + 4]
14997 // t4L = phi(t1L, t3L / loop)
14998 // t4H = phi(t1H, t3H / loop)
14999 // t2L = OP MI.val.lo, t4L
15000 // t2H = OP MI.val.hi, t4H
15005 // LCMPXCHG8B [MI.addr], [ECX:EBX & EDX:EAX are implicitly used and EDX:EAX is implicitly defined]
15013 MachineBasicBlock *
15014 X86TargetLowering::EmitAtomicLoadArith6432(MachineInstr *MI,
15015 MachineBasicBlock *MBB) const {
15016 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15017 DebugLoc DL = MI->getDebugLoc();
15019 MachineFunction *MF = MBB->getParent();
15020 MachineRegisterInfo &MRI = MF->getRegInfo();
15022 const BasicBlock *BB = MBB->getBasicBlock();
15023 MachineFunction::iterator I = MBB;
15026 assert(MI->getNumOperands() <= X86::AddrNumOperands + 7 &&
15027 "Unexpected number of operands");
15029 assert(MI->hasOneMemOperand() &&
15030 "Expected atomic-load-op32 to have one memoperand");
15032 // Memory Reference
15033 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
15034 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
15036 unsigned DstLoReg, DstHiReg;
15037 unsigned SrcLoReg, SrcHiReg;
15038 unsigned MemOpndSlot;
15040 unsigned CurOp = 0;
15042 DstLoReg = MI->getOperand(CurOp++).getReg();
15043 DstHiReg = MI->getOperand(CurOp++).getReg();
15044 MemOpndSlot = CurOp;
15045 CurOp += X86::AddrNumOperands;
15046 SrcLoReg = MI->getOperand(CurOp++).getReg();
15047 SrcHiReg = MI->getOperand(CurOp++).getReg();
15049 const TargetRegisterClass *RC = &X86::GR32RegClass;
15050 const TargetRegisterClass *RC8 = &X86::GR8RegClass;
15052 unsigned t1L = MRI.createVirtualRegister(RC);
15053 unsigned t1H = MRI.createVirtualRegister(RC);
15054 unsigned t2L = MRI.createVirtualRegister(RC);
15055 unsigned t2H = MRI.createVirtualRegister(RC);
15056 unsigned t3L = MRI.createVirtualRegister(RC);
15057 unsigned t3H = MRI.createVirtualRegister(RC);
15058 unsigned t4L = MRI.createVirtualRegister(RC);
15059 unsigned t4H = MRI.createVirtualRegister(RC);
15061 unsigned LCMPXCHGOpc = X86::LCMPXCHG8B;
15062 unsigned LOADOpc = X86::MOV32rm;
15064 // For the atomic load-arith operator, we generate
15067 // t1L = LOAD [MI.addr + 0]
15068 // t1H = LOAD [MI.addr + 4]
15070 // t4L = phi(t1L / thisMBB, t3L / mainMBB)
15071 // t4H = phi(t1H / thisMBB, t3H / mainMBB)
15072 // t2L = OP MI.val.lo, t4L
15073 // t2H = OP MI.val.hi, t4H
15076 // LCMPXCHG8B [MI.addr], [ECX:EBX & EDX:EAX are implicitly used and EDX:EAX is implicitly defined]
15084 MachineBasicBlock *thisMBB = MBB;
15085 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
15086 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
15087 MF->insert(I, mainMBB);
15088 MF->insert(I, sinkMBB);
15090 MachineInstrBuilder MIB;
15092 // Transfer the remainder of BB and its successor edges to sinkMBB.
15093 sinkMBB->splice(sinkMBB->begin(), MBB,
15094 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
15095 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
15099 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), t1L);
15100 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
15101 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
15103 NewMO.setIsKill(false);
15104 MIB.addOperand(NewMO);
15106 for (MachineInstr::mmo_iterator MMOI = MMOBegin; MMOI != MMOEnd; ++MMOI) {
15107 unsigned flags = (*MMOI)->getFlags();
15108 flags = (flags & ~MachineMemOperand::MOStore) | MachineMemOperand::MOLoad;
15109 MachineMemOperand *MMO =
15110 MF->getMachineMemOperand((*MMOI)->getPointerInfo(), flags,
15111 (*MMOI)->getSize(),
15112 (*MMOI)->getBaseAlignment(),
15113 (*MMOI)->getTBAAInfo(),
15114 (*MMOI)->getRanges());
15115 MIB.addMemOperand(MMO);
15117 MachineInstr *LowMI = MIB;
15120 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), t1H);
15121 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
15122 if (i == X86::AddrDisp) {
15123 MIB.addDisp(MI->getOperand(MemOpndSlot + i), 4); // 4 == sizeof(i32)
15125 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
15127 NewMO.setIsKill(false);
15128 MIB.addOperand(NewMO);
15131 MIB.setMemRefs(LowMI->memoperands_begin(), LowMI->memoperands_end());
15133 thisMBB->addSuccessor(mainMBB);
15136 MachineBasicBlock *origMainMBB = mainMBB;
15139 MachineInstr *PhiL = BuildMI(mainMBB, DL, TII->get(X86::PHI), t4L)
15140 .addReg(t1L).addMBB(thisMBB).addReg(t3L).addMBB(mainMBB);
15141 MachineInstr *PhiH = BuildMI(mainMBB, DL, TII->get(X86::PHI), t4H)
15142 .addReg(t1H).addMBB(thisMBB).addReg(t3H).addMBB(mainMBB);
15144 unsigned Opc = MI->getOpcode();
15147 llvm_unreachable("Unhandled atomic-load-op6432 opcode!");
15148 case X86::ATOMAND6432:
15149 case X86::ATOMOR6432:
15150 case X86::ATOMXOR6432:
15151 case X86::ATOMADD6432:
15152 case X86::ATOMSUB6432: {
15154 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc);
15155 BuildMI(mainMBB, DL, TII->get(LoOpc), t2L).addReg(t4L)
15157 BuildMI(mainMBB, DL, TII->get(HiOpc), t2H).addReg(t4H)
15161 case X86::ATOMNAND6432: {
15162 unsigned HiOpc, NOTOpc;
15163 unsigned LoOpc = getNonAtomic6432OpcodeWithExtraOpc(Opc, HiOpc, NOTOpc);
15164 unsigned TmpL = MRI.createVirtualRegister(RC);
15165 unsigned TmpH = MRI.createVirtualRegister(RC);
15166 BuildMI(mainMBB, DL, TII->get(LoOpc), TmpL).addReg(SrcLoReg)
15168 BuildMI(mainMBB, DL, TII->get(HiOpc), TmpH).addReg(SrcHiReg)
15170 BuildMI(mainMBB, DL, TII->get(NOTOpc), t2L).addReg(TmpL);
15171 BuildMI(mainMBB, DL, TII->get(NOTOpc), t2H).addReg(TmpH);
15174 case X86::ATOMMAX6432:
15175 case X86::ATOMMIN6432:
15176 case X86::ATOMUMAX6432:
15177 case X86::ATOMUMIN6432: {
15179 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc);
15180 unsigned cL = MRI.createVirtualRegister(RC8);
15181 unsigned cH = MRI.createVirtualRegister(RC8);
15182 unsigned cL32 = MRI.createVirtualRegister(RC);
15183 unsigned cH32 = MRI.createVirtualRegister(RC);
15184 unsigned cc = MRI.createVirtualRegister(RC);
15185 // cl := cmp src_lo, lo
15186 BuildMI(mainMBB, DL, TII->get(X86::CMP32rr))
15187 .addReg(SrcLoReg).addReg(t4L);
15188 BuildMI(mainMBB, DL, TII->get(LoOpc), cL);
15189 BuildMI(mainMBB, DL, TII->get(X86::MOVZX32rr8), cL32).addReg(cL);
15190 // ch := cmp src_hi, hi
15191 BuildMI(mainMBB, DL, TII->get(X86::CMP32rr))
15192 .addReg(SrcHiReg).addReg(t4H);
15193 BuildMI(mainMBB, DL, TII->get(HiOpc), cH);
15194 BuildMI(mainMBB, DL, TII->get(X86::MOVZX32rr8), cH32).addReg(cH);
15195 // cc := if (src_hi == hi) ? cl : ch;
15196 if (Subtarget->hasCMov()) {
15197 BuildMI(mainMBB, DL, TII->get(X86::CMOVE32rr), cc)
15198 .addReg(cH32).addReg(cL32);
15200 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), cc)
15201 .addReg(cH32).addReg(cL32)
15202 .addImm(X86::COND_E);
15203 mainMBB = EmitLoweredSelect(MIB, mainMBB);
15205 BuildMI(mainMBB, DL, TII->get(X86::TEST32rr)).addReg(cc).addReg(cc);
15206 if (Subtarget->hasCMov()) {
15207 BuildMI(mainMBB, DL, TII->get(X86::CMOVNE32rr), t2L)
15208 .addReg(SrcLoReg).addReg(t4L);
15209 BuildMI(mainMBB, DL, TII->get(X86::CMOVNE32rr), t2H)
15210 .addReg(SrcHiReg).addReg(t4H);
15212 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), t2L)
15213 .addReg(SrcLoReg).addReg(t4L)
15214 .addImm(X86::COND_NE);
15215 mainMBB = EmitLoweredSelect(MIB, mainMBB);
15216 // As the lowered CMOV won't clobber EFLAGS, we could reuse it for the
15217 // 2nd CMOV lowering.
15218 mainMBB->addLiveIn(X86::EFLAGS);
15219 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), t2H)
15220 .addReg(SrcHiReg).addReg(t4H)
15221 .addImm(X86::COND_NE);
15222 mainMBB = EmitLoweredSelect(MIB, mainMBB);
15223 // Replace the original PHI node as mainMBB is changed after CMOV
15225 BuildMI(*origMainMBB, PhiL, DL, TII->get(X86::PHI), t4L)
15226 .addReg(t1L).addMBB(thisMBB).addReg(t3L).addMBB(mainMBB);
15227 BuildMI(*origMainMBB, PhiH, DL, TII->get(X86::PHI), t4H)
15228 .addReg(t1H).addMBB(thisMBB).addReg(t3H).addMBB(mainMBB);
15229 PhiL->eraseFromParent();
15230 PhiH->eraseFromParent();
15234 case X86::ATOMSWAP6432: {
15236 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc);
15237 BuildMI(mainMBB, DL, TII->get(LoOpc), t2L).addReg(SrcLoReg);
15238 BuildMI(mainMBB, DL, TII->get(HiOpc), t2H).addReg(SrcHiReg);
15243 // Copy EDX:EAX back from HiReg:LoReg
15244 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EAX).addReg(t4L);
15245 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EDX).addReg(t4H);
15246 // Copy ECX:EBX from t1H:t1L
15247 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EBX).addReg(t2L);
15248 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::ECX).addReg(t2H);
15250 MIB = BuildMI(mainMBB, DL, TII->get(LCMPXCHGOpc));
15251 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
15252 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
15254 NewMO.setIsKill(false);
15255 MIB.addOperand(NewMO);
15257 MIB.setMemRefs(MMOBegin, MMOEnd);
15259 // Copy EDX:EAX back to t3H:t3L
15260 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t3L).addReg(X86::EAX);
15261 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t3H).addReg(X86::EDX);
15263 BuildMI(mainMBB, DL, TII->get(X86::JNE_4)).addMBB(origMainMBB);
15265 mainMBB->addSuccessor(origMainMBB);
15266 mainMBB->addSuccessor(sinkMBB);
15269 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
15270 TII->get(TargetOpcode::COPY), DstLoReg)
15272 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
15273 TII->get(TargetOpcode::COPY), DstHiReg)
15276 MI->eraseFromParent();
15280 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
15281 // or XMM0_V32I8 in AVX all of this code can be replaced with that
15282 // in the .td file.
15283 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
15284 const TargetInstrInfo *TII) {
15286 switch (MI->getOpcode()) {
15287 default: llvm_unreachable("illegal opcode!");
15288 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
15289 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
15290 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
15291 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
15292 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
15293 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
15294 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
15295 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
15298 DebugLoc dl = MI->getDebugLoc();
15299 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
15301 unsigned NumArgs = MI->getNumOperands();
15302 for (unsigned i = 1; i < NumArgs; ++i) {
15303 MachineOperand &Op = MI->getOperand(i);
15304 if (!(Op.isReg() && Op.isImplicit()))
15305 MIB.addOperand(Op);
15307 if (MI->hasOneMemOperand())
15308 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
15310 BuildMI(*BB, MI, dl,
15311 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
15312 .addReg(X86::XMM0);
15314 MI->eraseFromParent();
15318 // FIXME: Custom handling because TableGen doesn't support multiple implicit
15319 // defs in an instruction pattern
15320 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
15321 const TargetInstrInfo *TII) {
15323 switch (MI->getOpcode()) {
15324 default: llvm_unreachable("illegal opcode!");
15325 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
15326 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
15327 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
15328 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
15329 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
15330 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
15331 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
15332 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
15335 DebugLoc dl = MI->getDebugLoc();
15336 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
15338 unsigned NumArgs = MI->getNumOperands(); // remove the results
15339 for (unsigned i = 1; i < NumArgs; ++i) {
15340 MachineOperand &Op = MI->getOperand(i);
15341 if (!(Op.isReg() && Op.isImplicit()))
15342 MIB.addOperand(Op);
15344 if (MI->hasOneMemOperand())
15345 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
15347 BuildMI(*BB, MI, dl,
15348 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
15351 MI->eraseFromParent();
15355 static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
15356 const TargetInstrInfo *TII,
15357 const X86Subtarget* Subtarget) {
15358 DebugLoc dl = MI->getDebugLoc();
15360 // Address into RAX/EAX, other two args into ECX, EDX.
15361 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
15362 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
15363 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
15364 for (int i = 0; i < X86::AddrNumOperands; ++i)
15365 MIB.addOperand(MI->getOperand(i));
15367 unsigned ValOps = X86::AddrNumOperands;
15368 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
15369 .addReg(MI->getOperand(ValOps).getReg());
15370 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
15371 .addReg(MI->getOperand(ValOps+1).getReg());
15373 // The instruction doesn't actually take any operands though.
15374 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
15376 MI->eraseFromParent(); // The pseudo is gone now.
15380 MachineBasicBlock *
15381 X86TargetLowering::EmitVAARG64WithCustomInserter(
15383 MachineBasicBlock *MBB) const {
15384 // Emit va_arg instruction on X86-64.
15386 // Operands to this pseudo-instruction:
15387 // 0 ) Output : destination address (reg)
15388 // 1-5) Input : va_list address (addr, i64mem)
15389 // 6 ) ArgSize : Size (in bytes) of vararg type
15390 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
15391 // 8 ) Align : Alignment of type
15392 // 9 ) EFLAGS (implicit-def)
15394 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
15395 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
15397 unsigned DestReg = MI->getOperand(0).getReg();
15398 MachineOperand &Base = MI->getOperand(1);
15399 MachineOperand &Scale = MI->getOperand(2);
15400 MachineOperand &Index = MI->getOperand(3);
15401 MachineOperand &Disp = MI->getOperand(4);
15402 MachineOperand &Segment = MI->getOperand(5);
15403 unsigned ArgSize = MI->getOperand(6).getImm();
15404 unsigned ArgMode = MI->getOperand(7).getImm();
15405 unsigned Align = MI->getOperand(8).getImm();
15407 // Memory Reference
15408 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
15409 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
15410 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
15412 // Machine Information
15413 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15414 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
15415 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
15416 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
15417 DebugLoc DL = MI->getDebugLoc();
15419 // struct va_list {
15422 // i64 overflow_area (address)
15423 // i64 reg_save_area (address)
15425 // sizeof(va_list) = 24
15426 // alignment(va_list) = 8
15428 unsigned TotalNumIntRegs = 6;
15429 unsigned TotalNumXMMRegs = 8;
15430 bool UseGPOffset = (ArgMode == 1);
15431 bool UseFPOffset = (ArgMode == 2);
15432 unsigned MaxOffset = TotalNumIntRegs * 8 +
15433 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
15435 /* Align ArgSize to a multiple of 8 */
15436 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
15437 bool NeedsAlign = (Align > 8);
15439 MachineBasicBlock *thisMBB = MBB;
15440 MachineBasicBlock *overflowMBB;
15441 MachineBasicBlock *offsetMBB;
15442 MachineBasicBlock *endMBB;
15444 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
15445 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
15446 unsigned OffsetReg = 0;
15448 if (!UseGPOffset && !UseFPOffset) {
15449 // If we only pull from the overflow region, we don't create a branch.
15450 // We don't need to alter control flow.
15451 OffsetDestReg = 0; // unused
15452 OverflowDestReg = DestReg;
15455 overflowMBB = thisMBB;
15458 // First emit code to check if gp_offset (or fp_offset) is below the bound.
15459 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
15460 // If not, pull from overflow_area. (branch to overflowMBB)
15465 // offsetMBB overflowMBB
15470 // Registers for the PHI in endMBB
15471 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
15472 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
15474 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
15475 MachineFunction *MF = MBB->getParent();
15476 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
15477 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
15478 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
15480 MachineFunction::iterator MBBIter = MBB;
15483 // Insert the new basic blocks
15484 MF->insert(MBBIter, offsetMBB);
15485 MF->insert(MBBIter, overflowMBB);
15486 MF->insert(MBBIter, endMBB);
15488 // Transfer the remainder of MBB and its successor edges to endMBB.
15489 endMBB->splice(endMBB->begin(), thisMBB,
15490 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
15491 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
15493 // Make offsetMBB and overflowMBB successors of thisMBB
15494 thisMBB->addSuccessor(offsetMBB);
15495 thisMBB->addSuccessor(overflowMBB);
15497 // endMBB is a successor of both offsetMBB and overflowMBB
15498 offsetMBB->addSuccessor(endMBB);
15499 overflowMBB->addSuccessor(endMBB);
15501 // Load the offset value into a register
15502 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
15503 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
15507 .addDisp(Disp, UseFPOffset ? 4 : 0)
15508 .addOperand(Segment)
15509 .setMemRefs(MMOBegin, MMOEnd);
15511 // Check if there is enough room left to pull this argument.
15512 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
15514 .addImm(MaxOffset + 8 - ArgSizeA8);
15516 // Branch to "overflowMBB" if offset >= max
15517 // Fall through to "offsetMBB" otherwise
15518 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
15519 .addMBB(overflowMBB);
15522 // In offsetMBB, emit code to use the reg_save_area.
15524 assert(OffsetReg != 0);
15526 // Read the reg_save_area address.
15527 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
15528 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
15533 .addOperand(Segment)
15534 .setMemRefs(MMOBegin, MMOEnd);
15536 // Zero-extend the offset
15537 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
15538 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
15541 .addImm(X86::sub_32bit);
15543 // Add the offset to the reg_save_area to get the final address.
15544 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
15545 .addReg(OffsetReg64)
15546 .addReg(RegSaveReg);
15548 // Compute the offset for the next argument
15549 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
15550 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
15552 .addImm(UseFPOffset ? 16 : 8);
15554 // Store it back into the va_list.
15555 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
15559 .addDisp(Disp, UseFPOffset ? 4 : 0)
15560 .addOperand(Segment)
15561 .addReg(NextOffsetReg)
15562 .setMemRefs(MMOBegin, MMOEnd);
15565 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
15570 // Emit code to use overflow area
15573 // Load the overflow_area address into a register.
15574 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
15575 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
15580 .addOperand(Segment)
15581 .setMemRefs(MMOBegin, MMOEnd);
15583 // If we need to align it, do so. Otherwise, just copy the address
15584 // to OverflowDestReg.
15586 // Align the overflow address
15587 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
15588 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
15590 // aligned_addr = (addr + (align-1)) & ~(align-1)
15591 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
15592 .addReg(OverflowAddrReg)
15595 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
15597 .addImm(~(uint64_t)(Align-1));
15599 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
15600 .addReg(OverflowAddrReg);
15603 // Compute the next overflow address after this argument.
15604 // (the overflow address should be kept 8-byte aligned)
15605 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
15606 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
15607 .addReg(OverflowDestReg)
15608 .addImm(ArgSizeA8);
15610 // Store the new overflow address.
15611 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
15616 .addOperand(Segment)
15617 .addReg(NextAddrReg)
15618 .setMemRefs(MMOBegin, MMOEnd);
15620 // If we branched, emit the PHI to the front of endMBB.
15622 BuildMI(*endMBB, endMBB->begin(), DL,
15623 TII->get(X86::PHI), DestReg)
15624 .addReg(OffsetDestReg).addMBB(offsetMBB)
15625 .addReg(OverflowDestReg).addMBB(overflowMBB);
15628 // Erase the pseudo instruction
15629 MI->eraseFromParent();
15634 MachineBasicBlock *
15635 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
15637 MachineBasicBlock *MBB) const {
15638 // Emit code to save XMM registers to the stack. The ABI says that the
15639 // number of registers to save is given in %al, so it's theoretically
15640 // possible to do an indirect jump trick to avoid saving all of them,
15641 // however this code takes a simpler approach and just executes all
15642 // of the stores if %al is non-zero. It's less code, and it's probably
15643 // easier on the hardware branch predictor, and stores aren't all that
15644 // expensive anyway.
15646 // Create the new basic blocks. One block contains all the XMM stores,
15647 // and one block is the final destination regardless of whether any
15648 // stores were performed.
15649 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
15650 MachineFunction *F = MBB->getParent();
15651 MachineFunction::iterator MBBIter = MBB;
15653 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
15654 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
15655 F->insert(MBBIter, XMMSaveMBB);
15656 F->insert(MBBIter, EndMBB);
15658 // Transfer the remainder of MBB and its successor edges to EndMBB.
15659 EndMBB->splice(EndMBB->begin(), MBB,
15660 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
15661 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
15663 // The original block will now fall through to the XMM save block.
15664 MBB->addSuccessor(XMMSaveMBB);
15665 // The XMMSaveMBB will fall through to the end block.
15666 XMMSaveMBB->addSuccessor(EndMBB);
15668 // Now add the instructions.
15669 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15670 DebugLoc DL = MI->getDebugLoc();
15672 unsigned CountReg = MI->getOperand(0).getReg();
15673 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
15674 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
15676 if (!Subtarget->isTargetWin64()) {
15677 // If %al is 0, branch around the XMM save block.
15678 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
15679 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
15680 MBB->addSuccessor(EndMBB);
15683 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
15684 // that was just emitted, but clearly shouldn't be "saved".
15685 assert((MI->getNumOperands() <= 3 ||
15686 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
15687 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
15688 && "Expected last argument to be EFLAGS");
15689 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
15690 // In the XMM save block, save all the XMM argument registers.
15691 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
15692 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
15693 MachineMemOperand *MMO =
15694 F->getMachineMemOperand(
15695 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
15696 MachineMemOperand::MOStore,
15697 /*Size=*/16, /*Align=*/16);
15698 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
15699 .addFrameIndex(RegSaveFrameIndex)
15700 .addImm(/*Scale=*/1)
15701 .addReg(/*IndexReg=*/0)
15702 .addImm(/*Disp=*/Offset)
15703 .addReg(/*Segment=*/0)
15704 .addReg(MI->getOperand(i).getReg())
15705 .addMemOperand(MMO);
15708 MI->eraseFromParent(); // The pseudo instruction is gone now.
15713 // The EFLAGS operand of SelectItr might be missing a kill marker
15714 // because there were multiple uses of EFLAGS, and ISel didn't know
15715 // which to mark. Figure out whether SelectItr should have had a
15716 // kill marker, and set it if it should. Returns the correct kill
15718 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
15719 MachineBasicBlock* BB,
15720 const TargetRegisterInfo* TRI) {
15721 // Scan forward through BB for a use/def of EFLAGS.
15722 MachineBasicBlock::iterator miI(std::next(SelectItr));
15723 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
15724 const MachineInstr& mi = *miI;
15725 if (mi.readsRegister(X86::EFLAGS))
15727 if (mi.definesRegister(X86::EFLAGS))
15728 break; // Should have kill-flag - update below.
15731 // If we hit the end of the block, check whether EFLAGS is live into a
15733 if (miI == BB->end()) {
15734 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
15735 sEnd = BB->succ_end();
15736 sItr != sEnd; ++sItr) {
15737 MachineBasicBlock* succ = *sItr;
15738 if (succ->isLiveIn(X86::EFLAGS))
15743 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
15744 // out. SelectMI should have a kill flag on EFLAGS.
15745 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
15749 MachineBasicBlock *
15750 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
15751 MachineBasicBlock *BB) const {
15752 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15753 DebugLoc DL = MI->getDebugLoc();
15755 // To "insert" a SELECT_CC instruction, we actually have to insert the
15756 // diamond control-flow pattern. The incoming instruction knows the
15757 // destination vreg to set, the condition code register to branch on, the
15758 // true/false values to select between, and a branch opcode to use.
15759 const BasicBlock *LLVM_BB = BB->getBasicBlock();
15760 MachineFunction::iterator It = BB;
15766 // cmpTY ccX, r1, r2
15768 // fallthrough --> copy0MBB
15769 MachineBasicBlock *thisMBB = BB;
15770 MachineFunction *F = BB->getParent();
15771 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
15772 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
15773 F->insert(It, copy0MBB);
15774 F->insert(It, sinkMBB);
15776 // If the EFLAGS register isn't dead in the terminator, then claim that it's
15777 // live into the sink and copy blocks.
15778 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
15779 if (!MI->killsRegister(X86::EFLAGS) &&
15780 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
15781 copy0MBB->addLiveIn(X86::EFLAGS);
15782 sinkMBB->addLiveIn(X86::EFLAGS);
15785 // Transfer the remainder of BB and its successor edges to sinkMBB.
15786 sinkMBB->splice(sinkMBB->begin(), BB,
15787 std::next(MachineBasicBlock::iterator(MI)), BB->end());
15788 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
15790 // Add the true and fallthrough blocks as its successors.
15791 BB->addSuccessor(copy0MBB);
15792 BB->addSuccessor(sinkMBB);
15794 // Create the conditional branch instruction.
15796 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
15797 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
15800 // %FalseValue = ...
15801 // # fallthrough to sinkMBB
15802 copy0MBB->addSuccessor(sinkMBB);
15805 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
15807 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
15808 TII->get(X86::PHI), MI->getOperand(0).getReg())
15809 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
15810 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
15812 MI->eraseFromParent(); // The pseudo instruction is gone now.
15816 MachineBasicBlock *
15817 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB,
15818 bool Is64Bit) const {
15819 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15820 DebugLoc DL = MI->getDebugLoc();
15821 MachineFunction *MF = BB->getParent();
15822 const BasicBlock *LLVM_BB = BB->getBasicBlock();
15824 assert(MF->shouldSplitStack());
15826 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
15827 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30;
15830 // ... [Till the alloca]
15831 // If stacklet is not large enough, jump to mallocMBB
15834 // Allocate by subtracting from RSP
15835 // Jump to continueMBB
15838 // Allocate by call to runtime
15842 // [rest of original BB]
15845 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
15846 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
15847 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
15849 MachineRegisterInfo &MRI = MF->getRegInfo();
15850 const TargetRegisterClass *AddrRegClass =
15851 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32);
15853 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
15854 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
15855 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
15856 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
15857 sizeVReg = MI->getOperand(1).getReg(),
15858 physSPReg = Is64Bit ? X86::RSP : X86::ESP;
15860 MachineFunction::iterator MBBIter = BB;
15863 MF->insert(MBBIter, bumpMBB);
15864 MF->insert(MBBIter, mallocMBB);
15865 MF->insert(MBBIter, continueMBB);
15867 continueMBB->splice(continueMBB->begin(), BB,
15868 std::next(MachineBasicBlock::iterator(MI)), BB->end());
15869 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
15871 // Add code to the main basic block to check if the stack limit has been hit,
15872 // and if so, jump to mallocMBB otherwise to bumpMBB.
15873 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
15874 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
15875 .addReg(tmpSPVReg).addReg(sizeVReg);
15876 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr))
15877 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
15878 .addReg(SPLimitVReg);
15879 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
15881 // bumpMBB simply decreases the stack pointer, since we know the current
15882 // stacklet has enough space.
15883 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
15884 .addReg(SPLimitVReg);
15885 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
15886 .addReg(SPLimitVReg);
15887 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
15889 // Calls into a routine in libgcc to allocate more space from the heap.
15890 const uint32_t *RegMask =
15891 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
15893 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
15895 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
15896 .addExternalSymbol("__morestack_allocate_stack_space")
15897 .addRegMask(RegMask)
15898 .addReg(X86::RDI, RegState::Implicit)
15899 .addReg(X86::RAX, RegState::ImplicitDefine);
15901 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
15903 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
15904 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
15905 .addExternalSymbol("__morestack_allocate_stack_space")
15906 .addRegMask(RegMask)
15907 .addReg(X86::EAX, RegState::ImplicitDefine);
15911 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
15914 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
15915 .addReg(Is64Bit ? X86::RAX : X86::EAX);
15916 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
15918 // Set up the CFG correctly.
15919 BB->addSuccessor(bumpMBB);
15920 BB->addSuccessor(mallocMBB);
15921 mallocMBB->addSuccessor(continueMBB);
15922 bumpMBB->addSuccessor(continueMBB);
15924 // Take care of the PHI nodes.
15925 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
15926 MI->getOperand(0).getReg())
15927 .addReg(mallocPtrVReg).addMBB(mallocMBB)
15928 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
15930 // Delete the original pseudo instruction.
15931 MI->eraseFromParent();
15934 return continueMBB;
15937 MachineBasicBlock *
15938 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
15939 MachineBasicBlock *BB) const {
15940 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15941 DebugLoc DL = MI->getDebugLoc();
15943 assert(!Subtarget->isTargetMacho());
15945 // The lowering is pretty easy: we're just emitting the call to _alloca. The
15946 // non-trivial part is impdef of ESP.
15948 if (Subtarget->isTargetWin64()) {
15949 if (Subtarget->isTargetCygMing()) {
15950 // ___chkstk(Mingw64):
15951 // Clobbers R10, R11, RAX and EFLAGS.
15953 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
15954 .addExternalSymbol("___chkstk")
15955 .addReg(X86::RAX, RegState::Implicit)
15956 .addReg(X86::RSP, RegState::Implicit)
15957 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
15958 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
15959 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
15961 // __chkstk(MSVCRT): does not update stack pointer.
15962 // Clobbers R10, R11 and EFLAGS.
15963 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
15964 .addExternalSymbol("__chkstk")
15965 .addReg(X86::RAX, RegState::Implicit)
15966 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
15967 // RAX has the offset to be subtracted from RSP.
15968 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
15973 const char *StackProbeSymbol =
15974 Subtarget->isTargetKnownWindowsMSVC() ? "_chkstk" : "_alloca";
15976 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
15977 .addExternalSymbol(StackProbeSymbol)
15978 .addReg(X86::EAX, RegState::Implicit)
15979 .addReg(X86::ESP, RegState::Implicit)
15980 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
15981 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
15982 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
15985 MI->eraseFromParent(); // The pseudo instruction is gone now.
15989 MachineBasicBlock *
15990 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
15991 MachineBasicBlock *BB) const {
15992 // This is pretty easy. We're taking the value that we received from
15993 // our load from the relocation, sticking it in either RDI (x86-64)
15994 // or EAX and doing an indirect call. The return value will then
15995 // be in the normal return register.
15996 const X86InstrInfo *TII
15997 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo());
15998 DebugLoc DL = MI->getDebugLoc();
15999 MachineFunction *F = BB->getParent();
16001 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
16002 assert(MI->getOperand(3).isGlobal() && "This should be a global");
16004 // Get a register mask for the lowered call.
16005 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
16006 // proper register mask.
16007 const uint32_t *RegMask =
16008 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
16009 if (Subtarget->is64Bit()) {
16010 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
16011 TII->get(X86::MOV64rm), X86::RDI)
16013 .addImm(0).addReg(0)
16014 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
16015 MI->getOperand(3).getTargetFlags())
16017 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
16018 addDirectMem(MIB, X86::RDI);
16019 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
16020 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
16021 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
16022 TII->get(X86::MOV32rm), X86::EAX)
16024 .addImm(0).addReg(0)
16025 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
16026 MI->getOperand(3).getTargetFlags())
16028 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
16029 addDirectMem(MIB, X86::EAX);
16030 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
16032 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
16033 TII->get(X86::MOV32rm), X86::EAX)
16034 .addReg(TII->getGlobalBaseReg(F))
16035 .addImm(0).addReg(0)
16036 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
16037 MI->getOperand(3).getTargetFlags())
16039 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
16040 addDirectMem(MIB, X86::EAX);
16041 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
16044 MI->eraseFromParent(); // The pseudo instruction is gone now.
16048 MachineBasicBlock *
16049 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
16050 MachineBasicBlock *MBB) const {
16051 DebugLoc DL = MI->getDebugLoc();
16052 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
16054 MachineFunction *MF = MBB->getParent();
16055 MachineRegisterInfo &MRI = MF->getRegInfo();
16057 const BasicBlock *BB = MBB->getBasicBlock();
16058 MachineFunction::iterator I = MBB;
16061 // Memory Reference
16062 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
16063 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
16066 unsigned MemOpndSlot = 0;
16068 unsigned CurOp = 0;
16070 DstReg = MI->getOperand(CurOp++).getReg();
16071 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
16072 assert(RC->hasType(MVT::i32) && "Invalid destination!");
16073 unsigned mainDstReg = MRI.createVirtualRegister(RC);
16074 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
16076 MemOpndSlot = CurOp;
16078 MVT PVT = getPointerTy();
16079 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
16080 "Invalid Pointer Size!");
16082 // For v = setjmp(buf), we generate
16085 // buf[LabelOffset] = restoreMBB
16086 // SjLjSetup restoreMBB
16092 // v = phi(main, restore)
16097 MachineBasicBlock *thisMBB = MBB;
16098 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
16099 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
16100 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
16101 MF->insert(I, mainMBB);
16102 MF->insert(I, sinkMBB);
16103 MF->push_back(restoreMBB);
16105 MachineInstrBuilder MIB;
16107 // Transfer the remainder of BB and its successor edges to sinkMBB.
16108 sinkMBB->splice(sinkMBB->begin(), MBB,
16109 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
16110 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
16113 unsigned PtrStoreOpc = 0;
16114 unsigned LabelReg = 0;
16115 const int64_t LabelOffset = 1 * PVT.getStoreSize();
16116 Reloc::Model RM = getTargetMachine().getRelocationModel();
16117 bool UseImmLabel = (getTargetMachine().getCodeModel() == CodeModel::Small) &&
16118 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
16120 // Prepare IP either in reg or imm.
16121 if (!UseImmLabel) {
16122 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
16123 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
16124 LabelReg = MRI.createVirtualRegister(PtrRC);
16125 if (Subtarget->is64Bit()) {
16126 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
16130 .addMBB(restoreMBB)
16133 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
16134 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
16135 .addReg(XII->getGlobalBaseReg(MF))
16138 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
16142 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
16144 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
16145 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
16146 if (i == X86::AddrDisp)
16147 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
16149 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
16152 MIB.addReg(LabelReg);
16154 MIB.addMBB(restoreMBB);
16155 MIB.setMemRefs(MMOBegin, MMOEnd);
16157 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
16158 .addMBB(restoreMBB);
16160 const X86RegisterInfo *RegInfo =
16161 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
16162 MIB.addRegMask(RegInfo->getNoPreservedMask());
16163 thisMBB->addSuccessor(mainMBB);
16164 thisMBB->addSuccessor(restoreMBB);
16168 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
16169 mainMBB->addSuccessor(sinkMBB);
16172 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
16173 TII->get(X86::PHI), DstReg)
16174 .addReg(mainDstReg).addMBB(mainMBB)
16175 .addReg(restoreDstReg).addMBB(restoreMBB);
16178 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
16179 BuildMI(restoreMBB, DL, TII->get(X86::JMP_4)).addMBB(sinkMBB);
16180 restoreMBB->addSuccessor(sinkMBB);
16182 MI->eraseFromParent();
16186 MachineBasicBlock *
16187 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
16188 MachineBasicBlock *MBB) const {
16189 DebugLoc DL = MI->getDebugLoc();
16190 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
16192 MachineFunction *MF = MBB->getParent();
16193 MachineRegisterInfo &MRI = MF->getRegInfo();
16195 // Memory Reference
16196 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
16197 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
16199 MVT PVT = getPointerTy();
16200 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
16201 "Invalid Pointer Size!");
16203 const TargetRegisterClass *RC =
16204 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
16205 unsigned Tmp = MRI.createVirtualRegister(RC);
16206 // Since FP is only updated here but NOT referenced, it's treated as GPR.
16207 const X86RegisterInfo *RegInfo =
16208 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
16209 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
16210 unsigned SP = RegInfo->getStackRegister();
16212 MachineInstrBuilder MIB;
16214 const int64_t LabelOffset = 1 * PVT.getStoreSize();
16215 const int64_t SPOffset = 2 * PVT.getStoreSize();
16217 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
16218 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
16221 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
16222 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
16223 MIB.addOperand(MI->getOperand(i));
16224 MIB.setMemRefs(MMOBegin, MMOEnd);
16226 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
16227 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
16228 if (i == X86::AddrDisp)
16229 MIB.addDisp(MI->getOperand(i), LabelOffset);
16231 MIB.addOperand(MI->getOperand(i));
16233 MIB.setMemRefs(MMOBegin, MMOEnd);
16235 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
16236 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
16237 if (i == X86::AddrDisp)
16238 MIB.addDisp(MI->getOperand(i), SPOffset);
16240 MIB.addOperand(MI->getOperand(i));
16242 MIB.setMemRefs(MMOBegin, MMOEnd);
16244 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
16246 MI->eraseFromParent();
16250 // Replace 213-type (isel default) FMA3 instructions with 231-type for
16251 // accumulator loops. Writing back to the accumulator allows the coalescer
16252 // to remove extra copies in the loop.
16253 MachineBasicBlock *
16254 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
16255 MachineBasicBlock *MBB) const {
16256 MachineOperand &AddendOp = MI->getOperand(3);
16258 // Bail out early if the addend isn't a register - we can't switch these.
16259 if (!AddendOp.isReg())
16262 MachineFunction &MF = *MBB->getParent();
16263 MachineRegisterInfo &MRI = MF.getRegInfo();
16265 // Check whether the addend is defined by a PHI:
16266 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
16267 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
16268 if (!AddendDef.isPHI())
16271 // Look for the following pattern:
16273 // %addend = phi [%entry, 0], [%loop, %result]
16275 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
16279 // %addend = phi [%entry, 0], [%loop, %result]
16281 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
16283 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
16284 assert(AddendDef.getOperand(i).isReg());
16285 MachineOperand PHISrcOp = AddendDef.getOperand(i);
16286 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
16287 if (&PHISrcInst == MI) {
16288 // Found a matching instruction.
16289 unsigned NewFMAOpc = 0;
16290 switch (MI->getOpcode()) {
16291 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
16292 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
16293 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
16294 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
16295 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
16296 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
16297 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
16298 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
16299 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
16300 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
16301 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
16302 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
16303 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
16304 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
16305 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
16306 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
16307 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
16308 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
16309 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
16310 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
16311 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
16312 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
16313 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
16314 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
16315 default: llvm_unreachable("Unrecognized FMA variant.");
16318 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
16319 MachineInstrBuilder MIB =
16320 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
16321 .addOperand(MI->getOperand(0))
16322 .addOperand(MI->getOperand(3))
16323 .addOperand(MI->getOperand(2))
16324 .addOperand(MI->getOperand(1));
16325 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
16326 MI->eraseFromParent();
16333 MachineBasicBlock *
16334 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
16335 MachineBasicBlock *BB) const {
16336 switch (MI->getOpcode()) {
16337 default: llvm_unreachable("Unexpected instr type to insert");
16338 case X86::TAILJMPd64:
16339 case X86::TAILJMPr64:
16340 case X86::TAILJMPm64:
16341 llvm_unreachable("TAILJMP64 would not be touched here.");
16342 case X86::TCRETURNdi64:
16343 case X86::TCRETURNri64:
16344 case X86::TCRETURNmi64:
16346 case X86::WIN_ALLOCA:
16347 return EmitLoweredWinAlloca(MI, BB);
16348 case X86::SEG_ALLOCA_32:
16349 return EmitLoweredSegAlloca(MI, BB, false);
16350 case X86::SEG_ALLOCA_64:
16351 return EmitLoweredSegAlloca(MI, BB, true);
16352 case X86::TLSCall_32:
16353 case X86::TLSCall_64:
16354 return EmitLoweredTLSCall(MI, BB);
16355 case X86::CMOV_GR8:
16356 case X86::CMOV_FR32:
16357 case X86::CMOV_FR64:
16358 case X86::CMOV_V4F32:
16359 case X86::CMOV_V2F64:
16360 case X86::CMOV_V2I64:
16361 case X86::CMOV_V8F32:
16362 case X86::CMOV_V4F64:
16363 case X86::CMOV_V4I64:
16364 case X86::CMOV_V16F32:
16365 case X86::CMOV_V8F64:
16366 case X86::CMOV_V8I64:
16367 case X86::CMOV_GR16:
16368 case X86::CMOV_GR32:
16369 case X86::CMOV_RFP32:
16370 case X86::CMOV_RFP64:
16371 case X86::CMOV_RFP80:
16372 return EmitLoweredSelect(MI, BB);
16374 case X86::FP32_TO_INT16_IN_MEM:
16375 case X86::FP32_TO_INT32_IN_MEM:
16376 case X86::FP32_TO_INT64_IN_MEM:
16377 case X86::FP64_TO_INT16_IN_MEM:
16378 case X86::FP64_TO_INT32_IN_MEM:
16379 case X86::FP64_TO_INT64_IN_MEM:
16380 case X86::FP80_TO_INT16_IN_MEM:
16381 case X86::FP80_TO_INT32_IN_MEM:
16382 case X86::FP80_TO_INT64_IN_MEM: {
16383 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
16384 DebugLoc DL = MI->getDebugLoc();
16386 // Change the floating point control register to use "round towards zero"
16387 // mode when truncating to an integer value.
16388 MachineFunction *F = BB->getParent();
16389 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
16390 addFrameReference(BuildMI(*BB, MI, DL,
16391 TII->get(X86::FNSTCW16m)), CWFrameIdx);
16393 // Load the old value of the high byte of the control word...
16395 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
16396 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
16399 // Set the high part to be round to zero...
16400 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
16403 // Reload the modified control word now...
16404 addFrameReference(BuildMI(*BB, MI, DL,
16405 TII->get(X86::FLDCW16m)), CWFrameIdx);
16407 // Restore the memory image of control word to original value
16408 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
16411 // Get the X86 opcode to use.
16413 switch (MI->getOpcode()) {
16414 default: llvm_unreachable("illegal opcode!");
16415 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
16416 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
16417 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
16418 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
16419 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
16420 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
16421 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
16422 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
16423 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
16427 MachineOperand &Op = MI->getOperand(0);
16429 AM.BaseType = X86AddressMode::RegBase;
16430 AM.Base.Reg = Op.getReg();
16432 AM.BaseType = X86AddressMode::FrameIndexBase;
16433 AM.Base.FrameIndex = Op.getIndex();
16435 Op = MI->getOperand(1);
16437 AM.Scale = Op.getImm();
16438 Op = MI->getOperand(2);
16440 AM.IndexReg = Op.getImm();
16441 Op = MI->getOperand(3);
16442 if (Op.isGlobal()) {
16443 AM.GV = Op.getGlobal();
16445 AM.Disp = Op.getImm();
16447 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
16448 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
16450 // Reload the original control word now.
16451 addFrameReference(BuildMI(*BB, MI, DL,
16452 TII->get(X86::FLDCW16m)), CWFrameIdx);
16454 MI->eraseFromParent(); // The pseudo instruction is gone now.
16457 // String/text processing lowering.
16458 case X86::PCMPISTRM128REG:
16459 case X86::VPCMPISTRM128REG:
16460 case X86::PCMPISTRM128MEM:
16461 case X86::VPCMPISTRM128MEM:
16462 case X86::PCMPESTRM128REG:
16463 case X86::VPCMPESTRM128REG:
16464 case X86::PCMPESTRM128MEM:
16465 case X86::VPCMPESTRM128MEM:
16466 assert(Subtarget->hasSSE42() &&
16467 "Target must have SSE4.2 or AVX features enabled");
16468 return EmitPCMPSTRM(MI, BB, getTargetMachine().getInstrInfo());
16470 // String/text processing lowering.
16471 case X86::PCMPISTRIREG:
16472 case X86::VPCMPISTRIREG:
16473 case X86::PCMPISTRIMEM:
16474 case X86::VPCMPISTRIMEM:
16475 case X86::PCMPESTRIREG:
16476 case X86::VPCMPESTRIREG:
16477 case X86::PCMPESTRIMEM:
16478 case X86::VPCMPESTRIMEM:
16479 assert(Subtarget->hasSSE42() &&
16480 "Target must have SSE4.2 or AVX features enabled");
16481 return EmitPCMPSTRI(MI, BB, getTargetMachine().getInstrInfo());
16483 // Thread synchronization.
16485 return EmitMonitor(MI, BB, getTargetMachine().getInstrInfo(), Subtarget);
16489 return EmitXBegin(MI, BB, getTargetMachine().getInstrInfo());
16491 // Atomic Lowering.
16492 case X86::ATOMAND8:
16493 case X86::ATOMAND16:
16494 case X86::ATOMAND32:
16495 case X86::ATOMAND64:
16498 case X86::ATOMOR16:
16499 case X86::ATOMOR32:
16500 case X86::ATOMOR64:
16502 case X86::ATOMXOR16:
16503 case X86::ATOMXOR8:
16504 case X86::ATOMXOR32:
16505 case X86::ATOMXOR64:
16507 case X86::ATOMNAND8:
16508 case X86::ATOMNAND16:
16509 case X86::ATOMNAND32:
16510 case X86::ATOMNAND64:
16512 case X86::ATOMMAX8:
16513 case X86::ATOMMAX16:
16514 case X86::ATOMMAX32:
16515 case X86::ATOMMAX64:
16517 case X86::ATOMMIN8:
16518 case X86::ATOMMIN16:
16519 case X86::ATOMMIN32:
16520 case X86::ATOMMIN64:
16522 case X86::ATOMUMAX8:
16523 case X86::ATOMUMAX16:
16524 case X86::ATOMUMAX32:
16525 case X86::ATOMUMAX64:
16527 case X86::ATOMUMIN8:
16528 case X86::ATOMUMIN16:
16529 case X86::ATOMUMIN32:
16530 case X86::ATOMUMIN64:
16531 return EmitAtomicLoadArith(MI, BB);
16533 // This group does 64-bit operations on a 32-bit host.
16534 case X86::ATOMAND6432:
16535 case X86::ATOMOR6432:
16536 case X86::ATOMXOR6432:
16537 case X86::ATOMNAND6432:
16538 case X86::ATOMADD6432:
16539 case X86::ATOMSUB6432:
16540 case X86::ATOMMAX6432:
16541 case X86::ATOMMIN6432:
16542 case X86::ATOMUMAX6432:
16543 case X86::ATOMUMIN6432:
16544 case X86::ATOMSWAP6432:
16545 return EmitAtomicLoadArith6432(MI, BB);
16547 case X86::VASTART_SAVE_XMM_REGS:
16548 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
16550 case X86::VAARG_64:
16551 return EmitVAARG64WithCustomInserter(MI, BB);
16553 case X86::EH_SjLj_SetJmp32:
16554 case X86::EH_SjLj_SetJmp64:
16555 return emitEHSjLjSetJmp(MI, BB);
16557 case X86::EH_SjLj_LongJmp32:
16558 case X86::EH_SjLj_LongJmp64:
16559 return emitEHSjLjLongJmp(MI, BB);
16561 case TargetOpcode::STACKMAP:
16562 case TargetOpcode::PATCHPOINT:
16563 return emitPatchPoint(MI, BB);
16565 case X86::VFMADDPDr213r:
16566 case X86::VFMADDPSr213r:
16567 case X86::VFMADDSDr213r:
16568 case X86::VFMADDSSr213r:
16569 case X86::VFMSUBPDr213r:
16570 case X86::VFMSUBPSr213r:
16571 case X86::VFMSUBSDr213r:
16572 case X86::VFMSUBSSr213r:
16573 case X86::VFNMADDPDr213r:
16574 case X86::VFNMADDPSr213r:
16575 case X86::VFNMADDSDr213r:
16576 case X86::VFNMADDSSr213r:
16577 case X86::VFNMSUBPDr213r:
16578 case X86::VFNMSUBPSr213r:
16579 case X86::VFNMSUBSDr213r:
16580 case X86::VFNMSUBSSr213r:
16581 case X86::VFMADDPDr213rY:
16582 case X86::VFMADDPSr213rY:
16583 case X86::VFMSUBPDr213rY:
16584 case X86::VFMSUBPSr213rY:
16585 case X86::VFNMADDPDr213rY:
16586 case X86::VFNMADDPSr213rY:
16587 case X86::VFNMSUBPDr213rY:
16588 case X86::VFNMSUBPSr213rY:
16589 return emitFMA3Instr(MI, BB);
16593 //===----------------------------------------------------------------------===//
16594 // X86 Optimization Hooks
16595 //===----------------------------------------------------------------------===//
16597 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
16600 const SelectionDAG &DAG,
16601 unsigned Depth) const {
16602 unsigned BitWidth = KnownZero.getBitWidth();
16603 unsigned Opc = Op.getOpcode();
16604 assert((Opc >= ISD::BUILTIN_OP_END ||
16605 Opc == ISD::INTRINSIC_WO_CHAIN ||
16606 Opc == ISD::INTRINSIC_W_CHAIN ||
16607 Opc == ISD::INTRINSIC_VOID) &&
16608 "Should use MaskedValueIsZero if you don't know whether Op"
16609 " is a target node!");
16611 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
16625 // These nodes' second result is a boolean.
16626 if (Op.getResNo() == 0)
16629 case X86ISD::SETCC:
16630 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
16632 case ISD::INTRINSIC_WO_CHAIN: {
16633 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16634 unsigned NumLoBits = 0;
16637 case Intrinsic::x86_sse_movmsk_ps:
16638 case Intrinsic::x86_avx_movmsk_ps_256:
16639 case Intrinsic::x86_sse2_movmsk_pd:
16640 case Intrinsic::x86_avx_movmsk_pd_256:
16641 case Intrinsic::x86_mmx_pmovmskb:
16642 case Intrinsic::x86_sse2_pmovmskb_128:
16643 case Intrinsic::x86_avx2_pmovmskb: {
16644 // High bits of movmskp{s|d}, pmovmskb are known zero.
16646 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16647 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
16648 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
16649 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
16650 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
16651 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
16652 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
16653 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
16655 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
16664 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
16666 const SelectionDAG &,
16667 unsigned Depth) const {
16668 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
16669 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
16670 return Op.getValueType().getScalarType().getSizeInBits();
16676 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
16677 /// node is a GlobalAddress + offset.
16678 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
16679 const GlobalValue* &GA,
16680 int64_t &Offset) const {
16681 if (N->getOpcode() == X86ISD::Wrapper) {
16682 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
16683 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
16684 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
16688 return TargetLowering::isGAPlusOffset(N, GA, Offset);
16691 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
16692 /// same as extracting the high 128-bit part of 256-bit vector and then
16693 /// inserting the result into the low part of a new 256-bit vector
16694 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
16695 EVT VT = SVOp->getValueType(0);
16696 unsigned NumElems = VT.getVectorNumElements();
16698 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
16699 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
16700 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
16701 SVOp->getMaskElt(j) >= 0)
16707 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
16708 /// same as extracting the low 128-bit part of 256-bit vector and then
16709 /// inserting the result into the high part of a new 256-bit vector
16710 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
16711 EVT VT = SVOp->getValueType(0);
16712 unsigned NumElems = VT.getVectorNumElements();
16714 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
16715 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
16716 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
16717 SVOp->getMaskElt(j) >= 0)
16723 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
16724 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
16725 TargetLowering::DAGCombinerInfo &DCI,
16726 const X86Subtarget* Subtarget) {
16728 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
16729 SDValue V1 = SVOp->getOperand(0);
16730 SDValue V2 = SVOp->getOperand(1);
16731 EVT VT = SVOp->getValueType(0);
16732 unsigned NumElems = VT.getVectorNumElements();
16734 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
16735 V2.getOpcode() == ISD::CONCAT_VECTORS) {
16739 // V UNDEF BUILD_VECTOR UNDEF
16741 // CONCAT_VECTOR CONCAT_VECTOR
16744 // RESULT: V + zero extended
16746 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
16747 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
16748 V1.getOperand(1).getOpcode() != ISD::UNDEF)
16751 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
16754 // To match the shuffle mask, the first half of the mask should
16755 // be exactly the first vector, and all the rest a splat with the
16756 // first element of the second one.
16757 for (unsigned i = 0; i != NumElems/2; ++i)
16758 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
16759 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
16762 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
16763 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
16764 if (Ld->hasNUsesOfValue(1, 0)) {
16765 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
16766 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
16768 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
16769 array_lengthof(Ops),
16771 Ld->getPointerInfo(),
16772 Ld->getAlignment(),
16773 false/*isVolatile*/, true/*ReadMem*/,
16774 false/*WriteMem*/);
16776 // Make sure the newly-created LOAD is in the same position as Ld in
16777 // terms of dependency. We create a TokenFactor for Ld and ResNode,
16778 // and update uses of Ld's output chain to use the TokenFactor.
16779 if (Ld->hasAnyUseOfValue(1)) {
16780 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
16781 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
16782 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
16783 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
16784 SDValue(ResNode.getNode(), 1));
16787 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
16791 // Emit a zeroed vector and insert the desired subvector on its
16793 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
16794 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
16795 return DCI.CombineTo(N, InsV);
16798 //===--------------------------------------------------------------------===//
16799 // Combine some shuffles into subvector extracts and inserts:
16802 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
16803 if (isShuffleHigh128VectorInsertLow(SVOp)) {
16804 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
16805 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
16806 return DCI.CombineTo(N, InsV);
16809 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
16810 if (isShuffleLow128VectorInsertHigh(SVOp)) {
16811 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
16812 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
16813 return DCI.CombineTo(N, InsV);
16819 /// PerformShuffleCombine - Performs several different shuffle combines.
16820 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
16821 TargetLowering::DAGCombinerInfo &DCI,
16822 const X86Subtarget *Subtarget) {
16824 EVT VT = N->getValueType(0);
16826 // Don't create instructions with illegal types after legalize types has run.
16827 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16828 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
16831 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
16832 if (Subtarget->hasFp256() && VT.is256BitVector() &&
16833 N->getOpcode() == ISD::VECTOR_SHUFFLE)
16834 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
16836 // Only handle 128 wide vector from here on.
16837 if (!VT.is128BitVector())
16840 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
16841 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
16842 // consecutive, non-overlapping, and in the right order.
16843 SmallVector<SDValue, 16> Elts;
16844 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
16845 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
16847 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true);
16850 /// PerformTruncateCombine - Converts truncate operation to
16851 /// a sequence of vector shuffle operations.
16852 /// It is possible when we truncate 256-bit vector to 128-bit vector
16853 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
16854 TargetLowering::DAGCombinerInfo &DCI,
16855 const X86Subtarget *Subtarget) {
16859 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
16860 /// specific shuffle of a load can be folded into a single element load.
16861 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
16862 /// shuffles have been customed lowered so we need to handle those here.
16863 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
16864 TargetLowering::DAGCombinerInfo &DCI) {
16865 if (DCI.isBeforeLegalizeOps())
16868 SDValue InVec = N->getOperand(0);
16869 SDValue EltNo = N->getOperand(1);
16871 if (!isa<ConstantSDNode>(EltNo))
16874 EVT VT = InVec.getValueType();
16876 bool HasShuffleIntoBitcast = false;
16877 if (InVec.getOpcode() == ISD::BITCAST) {
16878 // Don't duplicate a load with other uses.
16879 if (!InVec.hasOneUse())
16881 EVT BCVT = InVec.getOperand(0).getValueType();
16882 if (BCVT.getVectorNumElements() != VT.getVectorNumElements())
16884 InVec = InVec.getOperand(0);
16885 HasShuffleIntoBitcast = true;
16888 if (!isTargetShuffle(InVec.getOpcode()))
16891 // Don't duplicate a load with other uses.
16892 if (!InVec.hasOneUse())
16895 SmallVector<int, 16> ShuffleMask;
16897 if (!getTargetShuffleMask(InVec.getNode(), VT.getSimpleVT(), ShuffleMask,
16901 // Select the input vector, guarding against out of range extract vector.
16902 unsigned NumElems = VT.getVectorNumElements();
16903 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
16904 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
16905 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
16906 : InVec.getOperand(1);
16908 // If inputs to shuffle are the same for both ops, then allow 2 uses
16909 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
16911 if (LdNode.getOpcode() == ISD::BITCAST) {
16912 // Don't duplicate a load with other uses.
16913 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
16916 AllowedUses = 1; // only allow 1 load use if we have a bitcast
16917 LdNode = LdNode.getOperand(0);
16920 if (!ISD::isNormalLoad(LdNode.getNode()))
16923 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
16925 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
16928 if (HasShuffleIntoBitcast) {
16929 // If there's a bitcast before the shuffle, check if the load type and
16930 // alignment is valid.
16931 unsigned Align = LN0->getAlignment();
16932 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16933 unsigned NewAlign = TLI.getDataLayout()->
16934 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
16936 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
16940 // All checks match so transform back to vector_shuffle so that DAG combiner
16941 // can finish the job
16944 // Create shuffle node taking into account the case that its a unary shuffle
16945 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1);
16946 Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl,
16947 InVec.getOperand(0), Shuffle,
16949 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
16950 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
16954 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
16955 /// generation and convert it from being a bunch of shuffles and extracts
16956 /// to a simple store and scalar loads to extract the elements.
16957 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
16958 TargetLowering::DAGCombinerInfo &DCI) {
16959 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
16960 if (NewOp.getNode())
16963 SDValue InputVector = N->getOperand(0);
16965 // Detect whether we are trying to convert from mmx to i32 and the bitcast
16966 // from mmx to v2i32 has a single usage.
16967 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
16968 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
16969 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
16970 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
16971 N->getValueType(0),
16972 InputVector.getNode()->getOperand(0));
16974 // Only operate on vectors of 4 elements, where the alternative shuffling
16975 // gets to be more expensive.
16976 if (InputVector.getValueType() != MVT::v4i32)
16979 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
16980 // single use which is a sign-extend or zero-extend, and all elements are
16982 SmallVector<SDNode *, 4> Uses;
16983 unsigned ExtractedElements = 0;
16984 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
16985 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
16986 if (UI.getUse().getResNo() != InputVector.getResNo())
16989 SDNode *Extract = *UI;
16990 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
16993 if (Extract->getValueType(0) != MVT::i32)
16995 if (!Extract->hasOneUse())
16997 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
16998 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
17000 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
17003 // Record which element was extracted.
17004 ExtractedElements |=
17005 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
17007 Uses.push_back(Extract);
17010 // If not all the elements were used, this may not be worthwhile.
17011 if (ExtractedElements != 15)
17014 // Ok, we've now decided to do the transformation.
17015 SDLoc dl(InputVector);
17017 // Store the value to a temporary stack slot.
17018 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
17019 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
17020 MachinePointerInfo(), false, false, 0);
17022 // Replace each use (extract) with a load of the appropriate element.
17023 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
17024 UE = Uses.end(); UI != UE; ++UI) {
17025 SDNode *Extract = *UI;
17027 // cOMpute the element's address.
17028 SDValue Idx = Extract->getOperand(1);
17030 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
17031 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
17032 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17033 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
17035 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
17036 StackPtr, OffsetVal);
17038 // Load the scalar.
17039 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
17040 ScalarAddr, MachinePointerInfo(),
17041 false, false, false, 0);
17043 // Replace the exact with the load.
17044 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
17047 // The replacement was made in place; don't return anything.
17051 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
17052 static std::pair<unsigned, bool>
17053 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
17054 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
17055 if (!VT.isVector())
17056 return std::make_pair(0, false);
17058 bool NeedSplit = false;
17059 switch (VT.getSimpleVT().SimpleTy) {
17060 default: return std::make_pair(0, false);
17064 if (!Subtarget->hasAVX2())
17066 if (!Subtarget->hasAVX())
17067 return std::make_pair(0, false);
17072 if (!Subtarget->hasSSE2())
17073 return std::make_pair(0, false);
17076 // SSE2 has only a small subset of the operations.
17077 bool hasUnsigned = Subtarget->hasSSE41() ||
17078 (Subtarget->hasSSE2() && VT == MVT::v16i8);
17079 bool hasSigned = Subtarget->hasSSE41() ||
17080 (Subtarget->hasSSE2() && VT == MVT::v8i16);
17082 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
17085 // Check for x CC y ? x : y.
17086 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
17087 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
17092 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
17095 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
17098 Opc = hasSigned ? X86ISD::SMIN : 0; break;
17101 Opc = hasSigned ? X86ISD::SMAX : 0; break;
17103 // Check for x CC y ? y : x -- a min/max with reversed arms.
17104 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
17105 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
17110 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
17113 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
17116 Opc = hasSigned ? X86ISD::SMAX : 0; break;
17119 Opc = hasSigned ? X86ISD::SMIN : 0; break;
17123 return std::make_pair(Opc, NeedSplit);
17126 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
17128 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
17129 TargetLowering::DAGCombinerInfo &DCI,
17130 const X86Subtarget *Subtarget) {
17132 SDValue Cond = N->getOperand(0);
17133 // Get the LHS/RHS of the select.
17134 SDValue LHS = N->getOperand(1);
17135 SDValue RHS = N->getOperand(2);
17136 EVT VT = LHS.getValueType();
17137 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17139 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
17140 // instructions match the semantics of the common C idiom x<y?x:y but not
17141 // x<=y?x:y, because of how they handle negative zero (which can be
17142 // ignored in unsafe-math mode).
17143 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
17144 VT != MVT::f80 && TLI.isTypeLegal(VT) &&
17145 (Subtarget->hasSSE2() ||
17146 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
17147 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
17149 unsigned Opcode = 0;
17150 // Check for x CC y ? x : y.
17151 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
17152 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
17156 // Converting this to a min would handle NaNs incorrectly, and swapping
17157 // the operands would cause it to handle comparisons between positive
17158 // and negative zero incorrectly.
17159 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
17160 if (!DAG.getTarget().Options.UnsafeFPMath &&
17161 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
17163 std::swap(LHS, RHS);
17165 Opcode = X86ISD::FMIN;
17168 // Converting this to a min would handle comparisons between positive
17169 // and negative zero incorrectly.
17170 if (!DAG.getTarget().Options.UnsafeFPMath &&
17171 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
17173 Opcode = X86ISD::FMIN;
17176 // Converting this to a min would handle both negative zeros and NaNs
17177 // incorrectly, but we can swap the operands to fix both.
17178 std::swap(LHS, RHS);
17182 Opcode = X86ISD::FMIN;
17186 // Converting this to a max would handle comparisons between positive
17187 // and negative zero incorrectly.
17188 if (!DAG.getTarget().Options.UnsafeFPMath &&
17189 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
17191 Opcode = X86ISD::FMAX;
17194 // Converting this to a max would handle NaNs incorrectly, and swapping
17195 // the operands would cause it to handle comparisons between positive
17196 // and negative zero incorrectly.
17197 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
17198 if (!DAG.getTarget().Options.UnsafeFPMath &&
17199 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
17201 std::swap(LHS, RHS);
17203 Opcode = X86ISD::FMAX;
17206 // Converting this to a max would handle both negative zeros and NaNs
17207 // incorrectly, but we can swap the operands to fix both.
17208 std::swap(LHS, RHS);
17212 Opcode = X86ISD::FMAX;
17215 // Check for x CC y ? y : x -- a min/max with reversed arms.
17216 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
17217 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
17221 // Converting this to a min would handle comparisons between positive
17222 // and negative zero incorrectly, and swapping the operands would
17223 // cause it to handle NaNs incorrectly.
17224 if (!DAG.getTarget().Options.UnsafeFPMath &&
17225 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
17226 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
17228 std::swap(LHS, RHS);
17230 Opcode = X86ISD::FMIN;
17233 // Converting this to a min would handle NaNs incorrectly.
17234 if (!DAG.getTarget().Options.UnsafeFPMath &&
17235 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
17237 Opcode = X86ISD::FMIN;
17240 // Converting this to a min would handle both negative zeros and NaNs
17241 // incorrectly, but we can swap the operands to fix both.
17242 std::swap(LHS, RHS);
17246 Opcode = X86ISD::FMIN;
17250 // Converting this to a max would handle NaNs incorrectly.
17251 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
17253 Opcode = X86ISD::FMAX;
17256 // Converting this to a max would handle comparisons between positive
17257 // and negative zero incorrectly, and swapping the operands would
17258 // cause it to handle NaNs incorrectly.
17259 if (!DAG.getTarget().Options.UnsafeFPMath &&
17260 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
17261 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
17263 std::swap(LHS, RHS);
17265 Opcode = X86ISD::FMAX;
17268 // Converting this to a max would handle both negative zeros and NaNs
17269 // incorrectly, but we can swap the operands to fix both.
17270 std::swap(LHS, RHS);
17274 Opcode = X86ISD::FMAX;
17280 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
17283 EVT CondVT = Cond.getValueType();
17284 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
17285 CondVT.getVectorElementType() == MVT::i1) {
17286 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
17287 // lowering on AVX-512. In this case we convert it to
17288 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
17289 // The same situation for all 128 and 256-bit vectors of i8 and i16
17290 EVT OpVT = LHS.getValueType();
17291 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
17292 (OpVT.getVectorElementType() == MVT::i8 ||
17293 OpVT.getVectorElementType() == MVT::i16)) {
17294 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
17295 DCI.AddToWorklist(Cond.getNode());
17296 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
17299 // If this is a select between two integer constants, try to do some
17301 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
17302 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
17303 // Don't do this for crazy integer types.
17304 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
17305 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
17306 // so that TrueC (the true value) is larger than FalseC.
17307 bool NeedsCondInvert = false;
17309 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
17310 // Efficiently invertible.
17311 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
17312 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
17313 isa<ConstantSDNode>(Cond.getOperand(1))))) {
17314 NeedsCondInvert = true;
17315 std::swap(TrueC, FalseC);
17318 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
17319 if (FalseC->getAPIntValue() == 0 &&
17320 TrueC->getAPIntValue().isPowerOf2()) {
17321 if (NeedsCondInvert) // Invert the condition if needed.
17322 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
17323 DAG.getConstant(1, Cond.getValueType()));
17325 // Zero extend the condition if needed.
17326 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
17328 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
17329 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
17330 DAG.getConstant(ShAmt, MVT::i8));
17333 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
17334 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
17335 if (NeedsCondInvert) // Invert the condition if needed.
17336 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
17337 DAG.getConstant(1, Cond.getValueType()));
17339 // Zero extend the condition if needed.
17340 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
17341 FalseC->getValueType(0), Cond);
17342 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
17343 SDValue(FalseC, 0));
17346 // Optimize cases that will turn into an LEA instruction. This requires
17347 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
17348 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
17349 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
17350 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
17352 bool isFastMultiplier = false;
17354 switch ((unsigned char)Diff) {
17356 case 1: // result = add base, cond
17357 case 2: // result = lea base( , cond*2)
17358 case 3: // result = lea base(cond, cond*2)
17359 case 4: // result = lea base( , cond*4)
17360 case 5: // result = lea base(cond, cond*4)
17361 case 8: // result = lea base( , cond*8)
17362 case 9: // result = lea base(cond, cond*8)
17363 isFastMultiplier = true;
17368 if (isFastMultiplier) {
17369 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
17370 if (NeedsCondInvert) // Invert the condition if needed.
17371 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
17372 DAG.getConstant(1, Cond.getValueType()));
17374 // Zero extend the condition if needed.
17375 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
17377 // Scale the condition by the difference.
17379 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
17380 DAG.getConstant(Diff, Cond.getValueType()));
17382 // Add the base if non-zero.
17383 if (FalseC->getAPIntValue() != 0)
17384 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
17385 SDValue(FalseC, 0));
17392 // Canonicalize max and min:
17393 // (x > y) ? x : y -> (x >= y) ? x : y
17394 // (x < y) ? x : y -> (x <= y) ? x : y
17395 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
17396 // the need for an extra compare
17397 // against zero. e.g.
17398 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
17400 // testl %edi, %edi
17402 // cmovgl %edi, %eax
17406 // cmovsl %eax, %edi
17407 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
17408 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
17409 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
17410 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
17415 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
17416 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
17417 Cond.getOperand(0), Cond.getOperand(1), NewCC);
17418 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
17423 // Early exit check
17424 if (!TLI.isTypeLegal(VT))
17427 // Match VSELECTs into subs with unsigned saturation.
17428 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
17429 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
17430 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
17431 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
17432 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
17434 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
17435 // left side invert the predicate to simplify logic below.
17437 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
17439 CC = ISD::getSetCCInverse(CC, true);
17440 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
17444 if (Other.getNode() && Other->getNumOperands() == 2 &&
17445 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
17446 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
17447 SDValue CondRHS = Cond->getOperand(1);
17449 // Look for a general sub with unsigned saturation first.
17450 // x >= y ? x-y : 0 --> subus x, y
17451 // x > y ? x-y : 0 --> subus x, y
17452 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
17453 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
17454 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
17456 // If the RHS is a constant we have to reverse the const canonicalization.
17457 // x > C-1 ? x+-C : 0 --> subus x, C
17458 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
17459 isSplatVector(CondRHS.getNode()) && isSplatVector(OpRHS.getNode())) {
17460 APInt A = cast<ConstantSDNode>(OpRHS.getOperand(0))->getAPIntValue();
17461 if (CondRHS.getConstantOperandVal(0) == -A-1)
17462 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS,
17463 DAG.getConstant(-A, VT));
17466 // Another special case: If C was a sign bit, the sub has been
17467 // canonicalized into a xor.
17468 // FIXME: Would it be better to use ComputeMaskedBits to determine whether
17469 // it's safe to decanonicalize the xor?
17470 // x s< 0 ? x^C : 0 --> subus x, C
17471 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
17472 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
17473 isSplatVector(OpRHS.getNode())) {
17474 APInt A = cast<ConstantSDNode>(OpRHS.getOperand(0))->getAPIntValue();
17476 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
17481 // Try to match a min/max vector operation.
17482 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
17483 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
17484 unsigned Opc = ret.first;
17485 bool NeedSplit = ret.second;
17487 if (Opc && NeedSplit) {
17488 unsigned NumElems = VT.getVectorNumElements();
17489 // Extract the LHS vectors
17490 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
17491 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
17493 // Extract the RHS vectors
17494 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
17495 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
17497 // Create min/max for each subvector
17498 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
17499 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
17501 // Merge the result
17502 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
17504 return DAG.getNode(Opc, DL, VT, LHS, RHS);
17507 // Simplify vector selection if the selector will be produced by CMPP*/PCMP*.
17508 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
17509 // Check if SETCC has already been promoted
17510 TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT &&
17511 // Check that condition value type matches vselect operand type
17514 assert(Cond.getValueType().isVector() &&
17515 "vector select expects a vector selector!");
17517 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
17518 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
17520 if (!TValIsAllOnes && !FValIsAllZeros) {
17521 // Try invert the condition if true value is not all 1s and false value
17523 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
17524 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
17526 if (TValIsAllZeros || FValIsAllOnes) {
17527 SDValue CC = Cond.getOperand(2);
17528 ISD::CondCode NewCC =
17529 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
17530 Cond.getOperand(0).getValueType().isInteger());
17531 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
17532 std::swap(LHS, RHS);
17533 TValIsAllOnes = FValIsAllOnes;
17534 FValIsAllZeros = TValIsAllZeros;
17538 if (TValIsAllOnes || FValIsAllZeros) {
17541 if (TValIsAllOnes && FValIsAllZeros)
17543 else if (TValIsAllOnes)
17544 Ret = DAG.getNode(ISD::OR, DL, CondVT, Cond,
17545 DAG.getNode(ISD::BITCAST, DL, CondVT, RHS));
17546 else if (FValIsAllZeros)
17547 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
17548 DAG.getNode(ISD::BITCAST, DL, CondVT, LHS));
17550 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
17554 // Try to fold this VSELECT into a MOVSS/MOVSD
17555 if (N->getOpcode() == ISD::VSELECT &&
17556 Cond.getOpcode() == ISD::BUILD_VECTOR && !DCI.isBeforeLegalize()) {
17557 if (VT == MVT::v4i32 || VT == MVT::v4f32 ||
17558 (Subtarget->hasSSE2() && (VT == MVT::v2i64 || VT == MVT::v2f64))) {
17559 bool CanFold = false;
17560 unsigned NumElems = Cond.getNumOperands();
17564 if (isZero(Cond.getOperand(0))) {
17567 // fold (vselect <0,-1,-1,-1>, A, B) -> (movss A, B)
17568 // fold (vselect <0,-1> -> (movsd A, B)
17569 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
17570 CanFold = isAllOnes(Cond.getOperand(i));
17571 } else if (isAllOnes(Cond.getOperand(0))) {
17575 // fold (vselect <-1,0,0,0>, A, B) -> (movss B, A)
17576 // fold (vselect <-1,0> -> (movsd B, A)
17577 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
17578 CanFold = isZero(Cond.getOperand(i));
17582 if (VT == MVT::v4i32 || VT == MVT::v4f32)
17583 return getTargetShuffleNode(X86ISD::MOVSS, DL, VT, A, B, DAG);
17584 return getTargetShuffleNode(X86ISD::MOVSD, DL, VT, A, B, DAG);
17587 if (Subtarget->hasSSE2() && (VT == MVT::v4i32 || VT == MVT::v4f32)) {
17588 // fold (v4i32: vselect <0,0,-1,-1>, A, B) ->
17589 // (v4i32 (bitcast (movsd (v2i64 (bitcast A)),
17590 // (v2i64 (bitcast B)))))
17592 // fold (v4f32: vselect <0,0,-1,-1>, A, B) ->
17593 // (v4f32 (bitcast (movsd (v2f64 (bitcast A)),
17594 // (v2f64 (bitcast B)))))
17596 // fold (v4i32: vselect <-1,-1,0,0>, A, B) ->
17597 // (v4i32 (bitcast (movsd (v2i64 (bitcast B)),
17598 // (v2i64 (bitcast A)))))
17600 // fold (v4f32: vselect <-1,-1,0,0>, A, B) ->
17601 // (v4f32 (bitcast (movsd (v2f64 (bitcast B)),
17602 // (v2f64 (bitcast A)))))
17604 CanFold = (isZero(Cond.getOperand(0)) &&
17605 isZero(Cond.getOperand(1)) &&
17606 isAllOnes(Cond.getOperand(2)) &&
17607 isAllOnes(Cond.getOperand(3)));
17609 if (!CanFold && isAllOnes(Cond.getOperand(0)) &&
17610 isAllOnes(Cond.getOperand(1)) &&
17611 isZero(Cond.getOperand(2)) &&
17612 isZero(Cond.getOperand(3))) {
17614 std::swap(LHS, RHS);
17618 EVT NVT = (VT == MVT::v4i32) ? MVT::v2i64 : MVT::v2f64;
17619 SDValue NewA = DAG.getNode(ISD::BITCAST, DL, NVT, LHS);
17620 SDValue NewB = DAG.getNode(ISD::BITCAST, DL, NVT, RHS);
17621 SDValue Select = getTargetShuffleNode(X86ISD::MOVSD, DL, NVT, NewA,
17623 return DAG.getNode(ISD::BITCAST, DL, VT, Select);
17629 // If we know that this node is legal then we know that it is going to be
17630 // matched by one of the SSE/AVX BLEND instructions. These instructions only
17631 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
17632 // to simplify previous instructions.
17633 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
17634 !DCI.isBeforeLegalize() && TLI.isOperationLegal(ISD::VSELECT, VT)) {
17635 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
17637 // Don't optimize vector selects that map to mask-registers.
17641 // Check all uses of that condition operand to check whether it will be
17642 // consumed by non-BLEND instructions, which may depend on all bits are set
17644 for (SDNode::use_iterator I = Cond->use_begin(),
17645 E = Cond->use_end(); I != E; ++I)
17646 if (I->getOpcode() != ISD::VSELECT)
17647 // TODO: Add other opcodes eventually lowered into BLEND.
17650 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
17651 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
17653 APInt KnownZero, KnownOne;
17654 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
17655 DCI.isBeforeLegalizeOps());
17656 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
17657 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO))
17658 DCI.CommitTargetLoweringOpt(TLO);
17664 // Check whether a boolean test is testing a boolean value generated by
17665 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
17668 // Simplify the following patterns:
17669 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
17670 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
17671 // to (Op EFLAGS Cond)
17673 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
17674 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
17675 // to (Op EFLAGS !Cond)
17677 // where Op could be BRCOND or CMOV.
17679 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
17680 // Quit if not CMP and SUB with its value result used.
17681 if (Cmp.getOpcode() != X86ISD::CMP &&
17682 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
17685 // Quit if not used as a boolean value.
17686 if (CC != X86::COND_E && CC != X86::COND_NE)
17689 // Check CMP operands. One of them should be 0 or 1 and the other should be
17690 // an SetCC or extended from it.
17691 SDValue Op1 = Cmp.getOperand(0);
17692 SDValue Op2 = Cmp.getOperand(1);
17695 const ConstantSDNode* C = 0;
17696 bool needOppositeCond = (CC == X86::COND_E);
17697 bool checkAgainstTrue = false; // Is it a comparison against 1?
17699 if ((C = dyn_cast<ConstantSDNode>(Op1)))
17701 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
17703 else // Quit if all operands are not constants.
17706 if (C->getZExtValue() == 1) {
17707 needOppositeCond = !needOppositeCond;
17708 checkAgainstTrue = true;
17709 } else if (C->getZExtValue() != 0)
17710 // Quit if the constant is neither 0 or 1.
17713 bool truncatedToBoolWithAnd = false;
17714 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
17715 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
17716 SetCC.getOpcode() == ISD::TRUNCATE ||
17717 SetCC.getOpcode() == ISD::AND) {
17718 if (SetCC.getOpcode() == ISD::AND) {
17720 ConstantSDNode *CS;
17721 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
17722 CS->getZExtValue() == 1)
17724 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
17725 CS->getZExtValue() == 1)
17729 SetCC = SetCC.getOperand(OpIdx);
17730 truncatedToBoolWithAnd = true;
17732 SetCC = SetCC.getOperand(0);
17735 switch (SetCC.getOpcode()) {
17736 case X86ISD::SETCC_CARRY:
17737 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
17738 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
17739 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
17740 // truncated to i1 using 'and'.
17741 if (checkAgainstTrue && !truncatedToBoolWithAnd)
17743 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
17744 "Invalid use of SETCC_CARRY!");
17746 case X86ISD::SETCC:
17747 // Set the condition code or opposite one if necessary.
17748 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
17749 if (needOppositeCond)
17750 CC = X86::GetOppositeBranchCondition(CC);
17751 return SetCC.getOperand(1);
17752 case X86ISD::CMOV: {
17753 // Check whether false/true value has canonical one, i.e. 0 or 1.
17754 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
17755 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
17756 // Quit if true value is not a constant.
17759 // Quit if false value is not a constant.
17761 SDValue Op = SetCC.getOperand(0);
17762 // Skip 'zext' or 'trunc' node.
17763 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
17764 Op.getOpcode() == ISD::TRUNCATE)
17765 Op = Op.getOperand(0);
17766 // A special case for rdrand/rdseed, where 0 is set if false cond is
17768 if ((Op.getOpcode() != X86ISD::RDRAND &&
17769 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
17772 // Quit if false value is not the constant 0 or 1.
17773 bool FValIsFalse = true;
17774 if (FVal && FVal->getZExtValue() != 0) {
17775 if (FVal->getZExtValue() != 1)
17777 // If FVal is 1, opposite cond is needed.
17778 needOppositeCond = !needOppositeCond;
17779 FValIsFalse = false;
17781 // Quit if TVal is not the constant opposite of FVal.
17782 if (FValIsFalse && TVal->getZExtValue() != 1)
17784 if (!FValIsFalse && TVal->getZExtValue() != 0)
17786 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
17787 if (needOppositeCond)
17788 CC = X86::GetOppositeBranchCondition(CC);
17789 return SetCC.getOperand(3);
17796 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
17797 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
17798 TargetLowering::DAGCombinerInfo &DCI,
17799 const X86Subtarget *Subtarget) {
17802 // If the flag operand isn't dead, don't touch this CMOV.
17803 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
17806 SDValue FalseOp = N->getOperand(0);
17807 SDValue TrueOp = N->getOperand(1);
17808 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
17809 SDValue Cond = N->getOperand(3);
17811 if (CC == X86::COND_E || CC == X86::COND_NE) {
17812 switch (Cond.getOpcode()) {
17816 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
17817 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
17818 return (CC == X86::COND_E) ? FalseOp : TrueOp;
17824 Flags = checkBoolTestSetCCCombine(Cond, CC);
17825 if (Flags.getNode() &&
17826 // Extra check as FCMOV only supports a subset of X86 cond.
17827 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
17828 SDValue Ops[] = { FalseOp, TrueOp,
17829 DAG.getConstant(CC, MVT::i8), Flags };
17830 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(),
17831 Ops, array_lengthof(Ops));
17834 // If this is a select between two integer constants, try to do some
17835 // optimizations. Note that the operands are ordered the opposite of SELECT
17837 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
17838 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
17839 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
17840 // larger than FalseC (the false value).
17841 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
17842 CC = X86::GetOppositeBranchCondition(CC);
17843 std::swap(TrueC, FalseC);
17844 std::swap(TrueOp, FalseOp);
17847 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
17848 // This is efficient for any integer data type (including i8/i16) and
17850 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
17851 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
17852 DAG.getConstant(CC, MVT::i8), Cond);
17854 // Zero extend the condition if needed.
17855 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
17857 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
17858 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
17859 DAG.getConstant(ShAmt, MVT::i8));
17860 if (N->getNumValues() == 2) // Dead flag value?
17861 return DCI.CombineTo(N, Cond, SDValue());
17865 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
17866 // for any integer data type, including i8/i16.
17867 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
17868 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
17869 DAG.getConstant(CC, MVT::i8), Cond);
17871 // Zero extend the condition if needed.
17872 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
17873 FalseC->getValueType(0), Cond);
17874 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
17875 SDValue(FalseC, 0));
17877 if (N->getNumValues() == 2) // Dead flag value?
17878 return DCI.CombineTo(N, Cond, SDValue());
17882 // Optimize cases that will turn into an LEA instruction. This requires
17883 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
17884 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
17885 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
17886 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
17888 bool isFastMultiplier = false;
17890 switch ((unsigned char)Diff) {
17892 case 1: // result = add base, cond
17893 case 2: // result = lea base( , cond*2)
17894 case 3: // result = lea base(cond, cond*2)
17895 case 4: // result = lea base( , cond*4)
17896 case 5: // result = lea base(cond, cond*4)
17897 case 8: // result = lea base( , cond*8)
17898 case 9: // result = lea base(cond, cond*8)
17899 isFastMultiplier = true;
17904 if (isFastMultiplier) {
17905 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
17906 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
17907 DAG.getConstant(CC, MVT::i8), Cond);
17908 // Zero extend the condition if needed.
17909 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
17911 // Scale the condition by the difference.
17913 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
17914 DAG.getConstant(Diff, Cond.getValueType()));
17916 // Add the base if non-zero.
17917 if (FalseC->getAPIntValue() != 0)
17918 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
17919 SDValue(FalseC, 0));
17920 if (N->getNumValues() == 2) // Dead flag value?
17921 return DCI.CombineTo(N, Cond, SDValue());
17928 // Handle these cases:
17929 // (select (x != c), e, c) -> select (x != c), e, x),
17930 // (select (x == c), c, e) -> select (x == c), x, e)
17931 // where the c is an integer constant, and the "select" is the combination
17932 // of CMOV and CMP.
17934 // The rationale for this change is that the conditional-move from a constant
17935 // needs two instructions, however, conditional-move from a register needs
17936 // only one instruction.
17938 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
17939 // some instruction-combining opportunities. This opt needs to be
17940 // postponed as late as possible.
17942 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
17943 // the DCI.xxxx conditions are provided to postpone the optimization as
17944 // late as possible.
17946 ConstantSDNode *CmpAgainst = 0;
17947 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
17948 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
17949 !isa<ConstantSDNode>(Cond.getOperand(0))) {
17951 if (CC == X86::COND_NE &&
17952 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
17953 CC = X86::GetOppositeBranchCondition(CC);
17954 std::swap(TrueOp, FalseOp);
17957 if (CC == X86::COND_E &&
17958 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
17959 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
17960 DAG.getConstant(CC, MVT::i8), Cond };
17961 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops,
17962 array_lengthof(Ops));
17970 /// PerformMulCombine - Optimize a single multiply with constant into two
17971 /// in order to implement it with two cheaper instructions, e.g.
17972 /// LEA + SHL, LEA + LEA.
17973 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
17974 TargetLowering::DAGCombinerInfo &DCI) {
17975 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
17978 EVT VT = N->getValueType(0);
17979 if (VT != MVT::i64)
17982 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
17985 uint64_t MulAmt = C->getZExtValue();
17986 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
17989 uint64_t MulAmt1 = 0;
17990 uint64_t MulAmt2 = 0;
17991 if ((MulAmt % 9) == 0) {
17993 MulAmt2 = MulAmt / 9;
17994 } else if ((MulAmt % 5) == 0) {
17996 MulAmt2 = MulAmt / 5;
17997 } else if ((MulAmt % 3) == 0) {
17999 MulAmt2 = MulAmt / 3;
18002 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
18005 if (isPowerOf2_64(MulAmt2) &&
18006 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
18007 // If second multiplifer is pow2, issue it first. We want the multiply by
18008 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
18010 std::swap(MulAmt1, MulAmt2);
18013 if (isPowerOf2_64(MulAmt1))
18014 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
18015 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
18017 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
18018 DAG.getConstant(MulAmt1, VT));
18020 if (isPowerOf2_64(MulAmt2))
18021 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
18022 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
18024 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
18025 DAG.getConstant(MulAmt2, VT));
18027 // Do not add new nodes to DAG combiner worklist.
18028 DCI.CombineTo(N, NewMul, false);
18033 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
18034 SDValue N0 = N->getOperand(0);
18035 SDValue N1 = N->getOperand(1);
18036 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
18037 EVT VT = N0.getValueType();
18039 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
18040 // since the result of setcc_c is all zero's or all ones.
18041 if (VT.isInteger() && !VT.isVector() &&
18042 N1C && N0.getOpcode() == ISD::AND &&
18043 N0.getOperand(1).getOpcode() == ISD::Constant) {
18044 SDValue N00 = N0.getOperand(0);
18045 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
18046 ((N00.getOpcode() == ISD::ANY_EXTEND ||
18047 N00.getOpcode() == ISD::ZERO_EXTEND) &&
18048 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
18049 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
18050 APInt ShAmt = N1C->getAPIntValue();
18051 Mask = Mask.shl(ShAmt);
18053 return DAG.getNode(ISD::AND, SDLoc(N), VT,
18054 N00, DAG.getConstant(Mask, VT));
18058 // Hardware support for vector shifts is sparse which makes us scalarize the
18059 // vector operations in many cases. Also, on sandybridge ADD is faster than
18061 // (shl V, 1) -> add V,V
18062 if (isSplatVector(N1.getNode())) {
18063 assert(N0.getValueType().isVector() && "Invalid vector shift type");
18064 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1->getOperand(0));
18065 // We shift all of the values by one. In many cases we do not have
18066 // hardware support for this operation. This is better expressed as an ADD
18068 if (N1C && (1 == N1C->getZExtValue())) {
18069 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
18076 /// \brief Returns a vector of 0s if the node in input is a vector logical
18077 /// shift by a constant amount which is known to be bigger than or equal
18078 /// to the vector element size in bits.
18079 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
18080 const X86Subtarget *Subtarget) {
18081 EVT VT = N->getValueType(0);
18083 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
18084 (!Subtarget->hasInt256() ||
18085 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
18088 SDValue Amt = N->getOperand(1);
18090 if (isSplatVector(Amt.getNode())) {
18091 SDValue SclrAmt = Amt->getOperand(0);
18092 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
18093 APInt ShiftAmt = C->getAPIntValue();
18094 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
18096 // SSE2/AVX2 logical shifts always return a vector of 0s
18097 // if the shift amount is bigger than or equal to
18098 // the element size. The constant shift amount will be
18099 // encoded as a 8-bit immediate.
18100 if (ShiftAmt.trunc(8).uge(MaxAmount))
18101 return getZeroVector(VT, Subtarget, DAG, DL);
18108 /// PerformShiftCombine - Combine shifts.
18109 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
18110 TargetLowering::DAGCombinerInfo &DCI,
18111 const X86Subtarget *Subtarget) {
18112 if (N->getOpcode() == ISD::SHL) {
18113 SDValue V = PerformSHLCombine(N, DAG);
18114 if (V.getNode()) return V;
18117 if (N->getOpcode() != ISD::SRA) {
18118 // Try to fold this logical shift into a zero vector.
18119 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
18120 if (V.getNode()) return V;
18126 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
18127 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
18128 // and friends. Likewise for OR -> CMPNEQSS.
18129 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
18130 TargetLowering::DAGCombinerInfo &DCI,
18131 const X86Subtarget *Subtarget) {
18134 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
18135 // we're requiring SSE2 for both.
18136 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
18137 SDValue N0 = N->getOperand(0);
18138 SDValue N1 = N->getOperand(1);
18139 SDValue CMP0 = N0->getOperand(1);
18140 SDValue CMP1 = N1->getOperand(1);
18143 // The SETCCs should both refer to the same CMP.
18144 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
18147 SDValue CMP00 = CMP0->getOperand(0);
18148 SDValue CMP01 = CMP0->getOperand(1);
18149 EVT VT = CMP00.getValueType();
18151 if (VT == MVT::f32 || VT == MVT::f64) {
18152 bool ExpectingFlags = false;
18153 // Check for any users that want flags:
18154 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
18155 !ExpectingFlags && UI != UE; ++UI)
18156 switch (UI->getOpcode()) {
18161 ExpectingFlags = true;
18163 case ISD::CopyToReg:
18164 case ISD::SIGN_EXTEND:
18165 case ISD::ZERO_EXTEND:
18166 case ISD::ANY_EXTEND:
18170 if (!ExpectingFlags) {
18171 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
18172 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
18174 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
18175 X86::CondCode tmp = cc0;
18180 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
18181 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
18182 // FIXME: need symbolic constants for these magic numbers.
18183 // See X86ATTInstPrinter.cpp:printSSECC().
18184 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
18185 if (Subtarget->hasAVX512()) {
18186 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
18187 CMP01, DAG.getConstant(x86cc, MVT::i8));
18188 if (N->getValueType(0) != MVT::i1)
18189 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
18193 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
18194 CMP00.getValueType(), CMP00, CMP01,
18195 DAG.getConstant(x86cc, MVT::i8));
18197 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
18198 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
18200 if (is64BitFP && !Subtarget->is64Bit()) {
18201 // On a 32-bit target, we cannot bitcast the 64-bit float to a
18202 // 64-bit integer, since that's not a legal type. Since
18203 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
18204 // bits, but can do this little dance to extract the lowest 32 bits
18205 // and work with those going forward.
18206 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
18208 SDValue Vector32 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f32,
18210 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
18211 Vector32, DAG.getIntPtrConstant(0));
18215 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT, OnesOrZeroesF);
18216 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
18217 DAG.getConstant(1, IntVT));
18218 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
18219 return OneBitOfTruth;
18227 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
18228 /// so it can be folded inside ANDNP.
18229 static bool CanFoldXORWithAllOnes(const SDNode *N) {
18230 EVT VT = N->getValueType(0);
18232 // Match direct AllOnes for 128 and 256-bit vectors
18233 if (ISD::isBuildVectorAllOnes(N))
18236 // Look through a bit convert.
18237 if (N->getOpcode() == ISD::BITCAST)
18238 N = N->getOperand(0).getNode();
18240 // Sometimes the operand may come from a insert_subvector building a 256-bit
18242 if (VT.is256BitVector() &&
18243 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
18244 SDValue V1 = N->getOperand(0);
18245 SDValue V2 = N->getOperand(1);
18247 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
18248 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
18249 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
18250 ISD::isBuildVectorAllOnes(V2.getNode()))
18257 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
18258 // register. In most cases we actually compare or select YMM-sized registers
18259 // and mixing the two types creates horrible code. This method optimizes
18260 // some of the transition sequences.
18261 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
18262 TargetLowering::DAGCombinerInfo &DCI,
18263 const X86Subtarget *Subtarget) {
18264 EVT VT = N->getValueType(0);
18265 if (!VT.is256BitVector())
18268 assert((N->getOpcode() == ISD::ANY_EXTEND ||
18269 N->getOpcode() == ISD::ZERO_EXTEND ||
18270 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
18272 SDValue Narrow = N->getOperand(0);
18273 EVT NarrowVT = Narrow->getValueType(0);
18274 if (!NarrowVT.is128BitVector())
18277 if (Narrow->getOpcode() != ISD::XOR &&
18278 Narrow->getOpcode() != ISD::AND &&
18279 Narrow->getOpcode() != ISD::OR)
18282 SDValue N0 = Narrow->getOperand(0);
18283 SDValue N1 = Narrow->getOperand(1);
18286 // The Left side has to be a trunc.
18287 if (N0.getOpcode() != ISD::TRUNCATE)
18290 // The type of the truncated inputs.
18291 EVT WideVT = N0->getOperand(0)->getValueType(0);
18295 // The right side has to be a 'trunc' or a constant vector.
18296 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
18297 bool RHSConst = (isSplatVector(N1.getNode()) &&
18298 isa<ConstantSDNode>(N1->getOperand(0)));
18299 if (!RHSTrunc && !RHSConst)
18302 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18304 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
18307 // Set N0 and N1 to hold the inputs to the new wide operation.
18308 N0 = N0->getOperand(0);
18310 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
18311 N1->getOperand(0));
18312 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
18313 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, &C[0], C.size());
18314 } else if (RHSTrunc) {
18315 N1 = N1->getOperand(0);
18318 // Generate the wide operation.
18319 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
18320 unsigned Opcode = N->getOpcode();
18322 case ISD::ANY_EXTEND:
18324 case ISD::ZERO_EXTEND: {
18325 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
18326 APInt Mask = APInt::getAllOnesValue(InBits);
18327 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
18328 return DAG.getNode(ISD::AND, DL, VT,
18329 Op, DAG.getConstant(Mask, VT));
18331 case ISD::SIGN_EXTEND:
18332 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
18333 Op, DAG.getValueType(NarrowVT));
18335 llvm_unreachable("Unexpected opcode");
18339 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
18340 TargetLowering::DAGCombinerInfo &DCI,
18341 const X86Subtarget *Subtarget) {
18342 EVT VT = N->getValueType(0);
18343 if (DCI.isBeforeLegalizeOps())
18346 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
18350 // Create BEXTR and BZHI instructions
18351 // BZHI is X & ((1 << Y) - 1)
18352 // BEXTR is ((X >> imm) & (2**size-1))
18353 if (VT == MVT::i32 || VT == MVT::i64) {
18354 SDValue N0 = N->getOperand(0);
18355 SDValue N1 = N->getOperand(1);
18358 if (Subtarget->hasBMI2()) {
18359 // Check for (and (add (shl 1, Y), -1), X)
18360 if (N0.getOpcode() == ISD::ADD && isAllOnes(N0.getOperand(1))) {
18361 SDValue N00 = N0.getOperand(0);
18362 if (N00.getOpcode() == ISD::SHL) {
18363 SDValue N001 = N00.getOperand(1);
18364 assert(N001.getValueType() == MVT::i8 && "unexpected type");
18365 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N00.getOperand(0));
18366 if (C && C->getZExtValue() == 1)
18367 return DAG.getNode(X86ISD::BZHI, DL, VT, N1, N001);
18371 // Check for (and X, (add (shl 1, Y), -1))
18372 if (N1.getOpcode() == ISD::ADD && isAllOnes(N1.getOperand(1))) {
18373 SDValue N10 = N1.getOperand(0);
18374 if (N10.getOpcode() == ISD::SHL) {
18375 SDValue N101 = N10.getOperand(1);
18376 assert(N101.getValueType() == MVT::i8 && "unexpected type");
18377 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N10.getOperand(0));
18378 if (C && C->getZExtValue() == 1)
18379 return DAG.getNode(X86ISD::BZHI, DL, VT, N0, N101);
18384 // Check for BEXTR.
18385 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
18386 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
18387 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
18388 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
18389 if (MaskNode && ShiftNode) {
18390 uint64_t Mask = MaskNode->getZExtValue();
18391 uint64_t Shift = ShiftNode->getZExtValue();
18392 if (isMask_64(Mask)) {
18393 uint64_t MaskSize = CountPopulation_64(Mask);
18394 if (Shift + MaskSize <= VT.getSizeInBits())
18395 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
18396 DAG.getConstant(Shift | (MaskSize << 8), VT));
18404 // Want to form ANDNP nodes:
18405 // 1) In the hopes of then easily combining them with OR and AND nodes
18406 // to form PBLEND/PSIGN.
18407 // 2) To match ANDN packed intrinsics
18408 if (VT != MVT::v2i64 && VT != MVT::v4i64)
18411 SDValue N0 = N->getOperand(0);
18412 SDValue N1 = N->getOperand(1);
18415 // Check LHS for vnot
18416 if (N0.getOpcode() == ISD::XOR &&
18417 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
18418 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
18419 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
18421 // Check RHS for vnot
18422 if (N1.getOpcode() == ISD::XOR &&
18423 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
18424 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
18425 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
18430 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
18431 TargetLowering::DAGCombinerInfo &DCI,
18432 const X86Subtarget *Subtarget) {
18433 if (DCI.isBeforeLegalizeOps())
18436 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
18440 SDValue N0 = N->getOperand(0);
18441 SDValue N1 = N->getOperand(1);
18442 EVT VT = N->getValueType(0);
18444 // look for psign/blend
18445 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
18446 if (!Subtarget->hasSSSE3() ||
18447 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
18450 // Canonicalize pandn to RHS
18451 if (N0.getOpcode() == X86ISD::ANDNP)
18453 // or (and (m, y), (pandn m, x))
18454 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
18455 SDValue Mask = N1.getOperand(0);
18456 SDValue X = N1.getOperand(1);
18458 if (N0.getOperand(0) == Mask)
18459 Y = N0.getOperand(1);
18460 if (N0.getOperand(1) == Mask)
18461 Y = N0.getOperand(0);
18463 // Check to see if the mask appeared in both the AND and ANDNP and
18467 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
18468 // Look through mask bitcast.
18469 if (Mask.getOpcode() == ISD::BITCAST)
18470 Mask = Mask.getOperand(0);
18471 if (X.getOpcode() == ISD::BITCAST)
18472 X = X.getOperand(0);
18473 if (Y.getOpcode() == ISD::BITCAST)
18474 Y = Y.getOperand(0);
18476 EVT MaskVT = Mask.getValueType();
18478 // Validate that the Mask operand is a vector sra node.
18479 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
18480 // there is no psrai.b
18481 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
18482 unsigned SraAmt = ~0;
18483 if (Mask.getOpcode() == ISD::SRA) {
18484 SDValue Amt = Mask.getOperand(1);
18485 if (isSplatVector(Amt.getNode())) {
18486 SDValue SclrAmt = Amt->getOperand(0);
18487 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt))
18488 SraAmt = C->getZExtValue();
18490 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
18491 SDValue SraC = Mask.getOperand(1);
18492 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
18494 if ((SraAmt + 1) != EltBits)
18499 // Now we know we at least have a plendvb with the mask val. See if
18500 // we can form a psignb/w/d.
18501 // psign = x.type == y.type == mask.type && y = sub(0, x);
18502 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
18503 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
18504 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
18505 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
18506 "Unsupported VT for PSIGN");
18507 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
18508 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
18510 // PBLENDVB only available on SSE 4.1
18511 if (!Subtarget->hasSSE41())
18514 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
18516 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
18517 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
18518 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
18519 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
18520 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
18524 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
18527 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
18528 MachineFunction &MF = DAG.getMachineFunction();
18529 bool OptForSize = MF.getFunction()->getAttributes().
18530 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
18532 // SHLD/SHRD instructions have lower register pressure, but on some
18533 // platforms they have higher latency than the equivalent
18534 // series of shifts/or that would otherwise be generated.
18535 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
18536 // have higher latencies and we are not optimizing for size.
18537 if (!OptForSize && Subtarget->isSHLDSlow())
18540 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
18542 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
18544 if (!N0.hasOneUse() || !N1.hasOneUse())
18547 SDValue ShAmt0 = N0.getOperand(1);
18548 if (ShAmt0.getValueType() != MVT::i8)
18550 SDValue ShAmt1 = N1.getOperand(1);
18551 if (ShAmt1.getValueType() != MVT::i8)
18553 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
18554 ShAmt0 = ShAmt0.getOperand(0);
18555 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
18556 ShAmt1 = ShAmt1.getOperand(0);
18559 unsigned Opc = X86ISD::SHLD;
18560 SDValue Op0 = N0.getOperand(0);
18561 SDValue Op1 = N1.getOperand(0);
18562 if (ShAmt0.getOpcode() == ISD::SUB) {
18563 Opc = X86ISD::SHRD;
18564 std::swap(Op0, Op1);
18565 std::swap(ShAmt0, ShAmt1);
18568 unsigned Bits = VT.getSizeInBits();
18569 if (ShAmt1.getOpcode() == ISD::SUB) {
18570 SDValue Sum = ShAmt1.getOperand(0);
18571 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
18572 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
18573 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
18574 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
18575 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
18576 return DAG.getNode(Opc, DL, VT,
18578 DAG.getNode(ISD::TRUNCATE, DL,
18581 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
18582 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
18584 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
18585 return DAG.getNode(Opc, DL, VT,
18586 N0.getOperand(0), N1.getOperand(0),
18587 DAG.getNode(ISD::TRUNCATE, DL,
18594 // Generate NEG and CMOV for integer abs.
18595 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
18596 EVT VT = N->getValueType(0);
18598 // Since X86 does not have CMOV for 8-bit integer, we don't convert
18599 // 8-bit integer abs to NEG and CMOV.
18600 if (VT.isInteger() && VT.getSizeInBits() == 8)
18603 SDValue N0 = N->getOperand(0);
18604 SDValue N1 = N->getOperand(1);
18607 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
18608 // and change it to SUB and CMOV.
18609 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
18610 N0.getOpcode() == ISD::ADD &&
18611 N0.getOperand(1) == N1 &&
18612 N1.getOpcode() == ISD::SRA &&
18613 N1.getOperand(0) == N0.getOperand(0))
18614 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
18615 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
18616 // Generate SUB & CMOV.
18617 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
18618 DAG.getConstant(0, VT), N0.getOperand(0));
18620 SDValue Ops[] = { N0.getOperand(0), Neg,
18621 DAG.getConstant(X86::COND_GE, MVT::i8),
18622 SDValue(Neg.getNode(), 1) };
18623 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue),
18624 Ops, array_lengthof(Ops));
18629 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
18630 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
18631 TargetLowering::DAGCombinerInfo &DCI,
18632 const X86Subtarget *Subtarget) {
18633 if (DCI.isBeforeLegalizeOps())
18636 if (Subtarget->hasCMov()) {
18637 SDValue RV = performIntegerAbsCombine(N, DAG);
18645 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
18646 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
18647 TargetLowering::DAGCombinerInfo &DCI,
18648 const X86Subtarget *Subtarget) {
18649 LoadSDNode *Ld = cast<LoadSDNode>(N);
18650 EVT RegVT = Ld->getValueType(0);
18651 EVT MemVT = Ld->getMemoryVT();
18653 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18654 unsigned RegSz = RegVT.getSizeInBits();
18656 // On Sandybridge unaligned 256bit loads are inefficient.
18657 ISD::LoadExtType Ext = Ld->getExtensionType();
18658 unsigned Alignment = Ld->getAlignment();
18659 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
18660 if (RegVT.is256BitVector() && !Subtarget->hasInt256() &&
18661 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
18662 unsigned NumElems = RegVT.getVectorNumElements();
18666 SDValue Ptr = Ld->getBasePtr();
18667 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
18669 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
18671 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
18672 Ld->getPointerInfo(), Ld->isVolatile(),
18673 Ld->isNonTemporal(), Ld->isInvariant(),
18675 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
18676 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
18677 Ld->getPointerInfo(), Ld->isVolatile(),
18678 Ld->isNonTemporal(), Ld->isInvariant(),
18679 std::min(16U, Alignment));
18680 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
18682 Load2.getValue(1));
18684 SDValue NewVec = DAG.getUNDEF(RegVT);
18685 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
18686 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
18687 return DCI.CombineTo(N, NewVec, TF, true);
18690 // If this is a vector EXT Load then attempt to optimize it using a
18691 // shuffle. If SSSE3 is not available we may emit an illegal shuffle but the
18692 // expansion is still better than scalar code.
18693 // We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise we'll
18694 // emit a shuffle and a arithmetic shift.
18695 // TODO: It is possible to support ZExt by zeroing the undef values
18696 // during the shuffle phase or after the shuffle.
18697 if (RegVT.isVector() && RegVT.isInteger() && Subtarget->hasSSE2() &&
18698 (Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)) {
18699 assert(MemVT != RegVT && "Cannot extend to the same type");
18700 assert(MemVT.isVector() && "Must load a vector from memory");
18702 unsigned NumElems = RegVT.getVectorNumElements();
18703 unsigned MemSz = MemVT.getSizeInBits();
18704 assert(RegSz > MemSz && "Register size must be greater than the mem size");
18706 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256())
18709 // All sizes must be a power of two.
18710 if (!isPowerOf2_32(RegSz * MemSz * NumElems))
18713 // Attempt to load the original value using scalar loads.
18714 // Find the largest scalar type that divides the total loaded size.
18715 MVT SclrLoadTy = MVT::i8;
18716 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
18717 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
18718 MVT Tp = (MVT::SimpleValueType)tp;
18719 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
18724 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
18725 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
18727 SclrLoadTy = MVT::f64;
18729 // Calculate the number of scalar loads that we need to perform
18730 // in order to load our vector from memory.
18731 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
18732 if (Ext == ISD::SEXTLOAD && NumLoads > 1)
18735 unsigned loadRegZize = RegSz;
18736 if (Ext == ISD::SEXTLOAD && RegSz == 256)
18739 // Represent our vector as a sequence of elements which are the
18740 // largest scalar that we can load.
18741 EVT LoadUnitVecVT = EVT::getVectorVT(*DAG.getContext(), SclrLoadTy,
18742 loadRegZize/SclrLoadTy.getSizeInBits());
18744 // Represent the data using the same element type that is stored in
18745 // memory. In practice, we ''widen'' MemVT.
18747 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
18748 loadRegZize/MemVT.getScalarType().getSizeInBits());
18750 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
18751 "Invalid vector type");
18753 // We can't shuffle using an illegal type.
18754 if (!TLI.isTypeLegal(WideVecVT))
18757 SmallVector<SDValue, 8> Chains;
18758 SDValue Ptr = Ld->getBasePtr();
18759 SDValue Increment = DAG.getConstant(SclrLoadTy.getSizeInBits()/8,
18760 TLI.getPointerTy());
18761 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
18763 for (unsigned i = 0; i < NumLoads; ++i) {
18764 // Perform a single load.
18765 SDValue ScalarLoad = DAG.getLoad(SclrLoadTy, dl, Ld->getChain(),
18766 Ptr, Ld->getPointerInfo(),
18767 Ld->isVolatile(), Ld->isNonTemporal(),
18768 Ld->isInvariant(), Ld->getAlignment());
18769 Chains.push_back(ScalarLoad.getValue(1));
18770 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
18771 // another round of DAGCombining.
18773 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
18775 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
18776 ScalarLoad, DAG.getIntPtrConstant(i));
18778 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
18781 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
18784 // Bitcast the loaded value to a vector of the original element type, in
18785 // the size of the target vector type.
18786 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
18787 unsigned SizeRatio = RegSz/MemSz;
18789 if (Ext == ISD::SEXTLOAD) {
18790 // If we have SSE4.1 we can directly emit a VSEXT node.
18791 if (Subtarget->hasSSE41()) {
18792 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
18793 return DCI.CombineTo(N, Sext, TF, true);
18796 // Otherwise we'll shuffle the small elements in the high bits of the
18797 // larger type and perform an arithmetic shift. If the shift is not legal
18798 // it's better to scalarize.
18799 if (!TLI.isOperationLegalOrCustom(ISD::SRA, RegVT))
18802 // Redistribute the loaded elements into the different locations.
18803 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
18804 for (unsigned i = 0; i != NumElems; ++i)
18805 ShuffleVec[i*SizeRatio + SizeRatio-1] = i;
18807 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
18808 DAG.getUNDEF(WideVecVT),
18811 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
18813 // Build the arithmetic shift.
18814 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
18815 MemVT.getVectorElementType().getSizeInBits();
18816 Shuff = DAG.getNode(ISD::SRA, dl, RegVT, Shuff,
18817 DAG.getConstant(Amt, RegVT));
18819 return DCI.CombineTo(N, Shuff, TF, true);
18822 // Redistribute the loaded elements into the different locations.
18823 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
18824 for (unsigned i = 0; i != NumElems; ++i)
18825 ShuffleVec[i*SizeRatio] = i;
18827 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
18828 DAG.getUNDEF(WideVecVT),
18831 // Bitcast to the requested type.
18832 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
18833 // Replace the original load with the new sequence
18834 // and return the new chain.
18835 return DCI.CombineTo(N, Shuff, TF, true);
18841 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
18842 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
18843 const X86Subtarget *Subtarget) {
18844 StoreSDNode *St = cast<StoreSDNode>(N);
18845 EVT VT = St->getValue().getValueType();
18846 EVT StVT = St->getMemoryVT();
18848 SDValue StoredVal = St->getOperand(1);
18849 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18851 // If we are saving a concatenation of two XMM registers, perform two stores.
18852 // On Sandy Bridge, 256-bit memory operations are executed by two
18853 // 128-bit ports. However, on Haswell it is better to issue a single 256-bit
18854 // memory operation.
18855 unsigned Alignment = St->getAlignment();
18856 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
18857 if (VT.is256BitVector() && !Subtarget->hasInt256() &&
18858 StVT == VT && !IsAligned) {
18859 unsigned NumElems = VT.getVectorNumElements();
18863 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
18864 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
18866 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
18867 SDValue Ptr0 = St->getBasePtr();
18868 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
18870 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
18871 St->getPointerInfo(), St->isVolatile(),
18872 St->isNonTemporal(), Alignment);
18873 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
18874 St->getPointerInfo(), St->isVolatile(),
18875 St->isNonTemporal(),
18876 std::min(16U, Alignment));
18877 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
18880 // Optimize trunc store (of multiple scalars) to shuffle and store.
18881 // First, pack all of the elements in one place. Next, store to memory
18882 // in fewer chunks.
18883 if (St->isTruncatingStore() && VT.isVector()) {
18884 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18885 unsigned NumElems = VT.getVectorNumElements();
18886 assert(StVT != VT && "Cannot truncate to the same type");
18887 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
18888 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
18890 // From, To sizes and ElemCount must be pow of two
18891 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
18892 // We are going to use the original vector elt for storing.
18893 // Accumulated smaller vector elements must be a multiple of the store size.
18894 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
18896 unsigned SizeRatio = FromSz / ToSz;
18898 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
18900 // Create a type on which we perform the shuffle
18901 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
18902 StVT.getScalarType(), NumElems*SizeRatio);
18904 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
18906 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
18907 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
18908 for (unsigned i = 0; i != NumElems; ++i)
18909 ShuffleVec[i] = i * SizeRatio;
18911 // Can't shuffle using an illegal type.
18912 if (!TLI.isTypeLegal(WideVecVT))
18915 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
18916 DAG.getUNDEF(WideVecVT),
18918 // At this point all of the data is stored at the bottom of the
18919 // register. We now need to save it to mem.
18921 // Find the largest store unit
18922 MVT StoreType = MVT::i8;
18923 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
18924 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
18925 MVT Tp = (MVT::SimpleValueType)tp;
18926 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
18930 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
18931 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
18932 (64 <= NumElems * ToSz))
18933 StoreType = MVT::f64;
18935 // Bitcast the original vector into a vector of store-size units
18936 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
18937 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
18938 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
18939 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
18940 SmallVector<SDValue, 8> Chains;
18941 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
18942 TLI.getPointerTy());
18943 SDValue Ptr = St->getBasePtr();
18945 // Perform one or more big stores into memory.
18946 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
18947 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
18948 StoreType, ShuffWide,
18949 DAG.getIntPtrConstant(i));
18950 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
18951 St->getPointerInfo(), St->isVolatile(),
18952 St->isNonTemporal(), St->getAlignment());
18953 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
18954 Chains.push_back(Ch);
18957 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
18961 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
18962 // the FP state in cases where an emms may be missing.
18963 // A preferable solution to the general problem is to figure out the right
18964 // places to insert EMMS. This qualifies as a quick hack.
18966 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
18967 if (VT.getSizeInBits() != 64)
18970 const Function *F = DAG.getMachineFunction().getFunction();
18971 bool NoImplicitFloatOps = F->getAttributes().
18972 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
18973 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
18974 && Subtarget->hasSSE2();
18975 if ((VT.isVector() ||
18976 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
18977 isa<LoadSDNode>(St->getValue()) &&
18978 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
18979 St->getChain().hasOneUse() && !St->isVolatile()) {
18980 SDNode* LdVal = St->getValue().getNode();
18981 LoadSDNode *Ld = 0;
18982 int TokenFactorIndex = -1;
18983 SmallVector<SDValue, 8> Ops;
18984 SDNode* ChainVal = St->getChain().getNode();
18985 // Must be a store of a load. We currently handle two cases: the load
18986 // is a direct child, and it's under an intervening TokenFactor. It is
18987 // possible to dig deeper under nested TokenFactors.
18988 if (ChainVal == LdVal)
18989 Ld = cast<LoadSDNode>(St->getChain());
18990 else if (St->getValue().hasOneUse() &&
18991 ChainVal->getOpcode() == ISD::TokenFactor) {
18992 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
18993 if (ChainVal->getOperand(i).getNode() == LdVal) {
18994 TokenFactorIndex = i;
18995 Ld = cast<LoadSDNode>(St->getValue());
18997 Ops.push_back(ChainVal->getOperand(i));
19001 if (!Ld || !ISD::isNormalLoad(Ld))
19004 // If this is not the MMX case, i.e. we are just turning i64 load/store
19005 // into f64 load/store, avoid the transformation if there are multiple
19006 // uses of the loaded value.
19007 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
19012 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
19013 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
19015 if (Subtarget->is64Bit() || F64IsLegal) {
19016 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
19017 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
19018 Ld->getPointerInfo(), Ld->isVolatile(),
19019 Ld->isNonTemporal(), Ld->isInvariant(),
19020 Ld->getAlignment());
19021 SDValue NewChain = NewLd.getValue(1);
19022 if (TokenFactorIndex != -1) {
19023 Ops.push_back(NewChain);
19024 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
19027 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
19028 St->getPointerInfo(),
19029 St->isVolatile(), St->isNonTemporal(),
19030 St->getAlignment());
19033 // Otherwise, lower to two pairs of 32-bit loads / stores.
19034 SDValue LoAddr = Ld->getBasePtr();
19035 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
19036 DAG.getConstant(4, MVT::i32));
19038 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
19039 Ld->getPointerInfo(),
19040 Ld->isVolatile(), Ld->isNonTemporal(),
19041 Ld->isInvariant(), Ld->getAlignment());
19042 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
19043 Ld->getPointerInfo().getWithOffset(4),
19044 Ld->isVolatile(), Ld->isNonTemporal(),
19046 MinAlign(Ld->getAlignment(), 4));
19048 SDValue NewChain = LoLd.getValue(1);
19049 if (TokenFactorIndex != -1) {
19050 Ops.push_back(LoLd);
19051 Ops.push_back(HiLd);
19052 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
19056 LoAddr = St->getBasePtr();
19057 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
19058 DAG.getConstant(4, MVT::i32));
19060 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
19061 St->getPointerInfo(),
19062 St->isVolatile(), St->isNonTemporal(),
19063 St->getAlignment());
19064 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
19065 St->getPointerInfo().getWithOffset(4),
19067 St->isNonTemporal(),
19068 MinAlign(St->getAlignment(), 4));
19069 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
19074 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
19075 /// and return the operands for the horizontal operation in LHS and RHS. A
19076 /// horizontal operation performs the binary operation on successive elements
19077 /// of its first operand, then on successive elements of its second operand,
19078 /// returning the resulting values in a vector. For example, if
19079 /// A = < float a0, float a1, float a2, float a3 >
19081 /// B = < float b0, float b1, float b2, float b3 >
19082 /// then the result of doing a horizontal operation on A and B is
19083 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
19084 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
19085 /// A horizontal-op B, for some already available A and B, and if so then LHS is
19086 /// set to A, RHS to B, and the routine returns 'true'.
19087 /// Note that the binary operation should have the property that if one of the
19088 /// operands is UNDEF then the result is UNDEF.
19089 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
19090 // Look for the following pattern: if
19091 // A = < float a0, float a1, float a2, float a3 >
19092 // B = < float b0, float b1, float b2, float b3 >
19094 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
19095 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
19096 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
19097 // which is A horizontal-op B.
19099 // At least one of the operands should be a vector shuffle.
19100 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
19101 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
19104 MVT VT = LHS.getSimpleValueType();
19106 assert((VT.is128BitVector() || VT.is256BitVector()) &&
19107 "Unsupported vector type for horizontal add/sub");
19109 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
19110 // operate independently on 128-bit lanes.
19111 unsigned NumElts = VT.getVectorNumElements();
19112 unsigned NumLanes = VT.getSizeInBits()/128;
19113 unsigned NumLaneElts = NumElts / NumLanes;
19114 assert((NumLaneElts % 2 == 0) &&
19115 "Vector type should have an even number of elements in each lane");
19116 unsigned HalfLaneElts = NumLaneElts/2;
19118 // View LHS in the form
19119 // LHS = VECTOR_SHUFFLE A, B, LMask
19120 // If LHS is not a shuffle then pretend it is the shuffle
19121 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
19122 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
19125 SmallVector<int, 16> LMask(NumElts);
19126 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
19127 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
19128 A = LHS.getOperand(0);
19129 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
19130 B = LHS.getOperand(1);
19131 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
19132 std::copy(Mask.begin(), Mask.end(), LMask.begin());
19134 if (LHS.getOpcode() != ISD::UNDEF)
19136 for (unsigned i = 0; i != NumElts; ++i)
19140 // Likewise, view RHS in the form
19141 // RHS = VECTOR_SHUFFLE C, D, RMask
19143 SmallVector<int, 16> RMask(NumElts);
19144 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
19145 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
19146 C = RHS.getOperand(0);
19147 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
19148 D = RHS.getOperand(1);
19149 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
19150 std::copy(Mask.begin(), Mask.end(), RMask.begin());
19152 if (RHS.getOpcode() != ISD::UNDEF)
19154 for (unsigned i = 0; i != NumElts; ++i)
19158 // Check that the shuffles are both shuffling the same vectors.
19159 if (!(A == C && B == D) && !(A == D && B == C))
19162 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
19163 if (!A.getNode() && !B.getNode())
19166 // If A and B occur in reverse order in RHS, then "swap" them (which means
19167 // rewriting the mask).
19169 CommuteVectorShuffleMask(RMask, NumElts);
19171 // At this point LHS and RHS are equivalent to
19172 // LHS = VECTOR_SHUFFLE A, B, LMask
19173 // RHS = VECTOR_SHUFFLE A, B, RMask
19174 // Check that the masks correspond to performing a horizontal operation.
19175 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
19176 for (unsigned i = 0; i != NumLaneElts; ++i) {
19177 int LIdx = LMask[i+l], RIdx = RMask[i+l];
19179 // Ignore any UNDEF components.
19180 if (LIdx < 0 || RIdx < 0 ||
19181 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
19182 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
19185 // Check that successive elements are being operated on. If not, this is
19186 // not a horizontal operation.
19187 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
19188 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
19189 if (!(LIdx == Index && RIdx == Index + 1) &&
19190 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
19195 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
19196 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
19200 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
19201 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
19202 const X86Subtarget *Subtarget) {
19203 EVT VT = N->getValueType(0);
19204 SDValue LHS = N->getOperand(0);
19205 SDValue RHS = N->getOperand(1);
19207 // Try to synthesize horizontal adds from adds of shuffles.
19208 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
19209 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
19210 isHorizontalBinOp(LHS, RHS, true))
19211 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
19215 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
19216 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
19217 const X86Subtarget *Subtarget) {
19218 EVT VT = N->getValueType(0);
19219 SDValue LHS = N->getOperand(0);
19220 SDValue RHS = N->getOperand(1);
19222 // Try to synthesize horizontal subs from subs of shuffles.
19223 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
19224 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
19225 isHorizontalBinOp(LHS, RHS, false))
19226 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
19230 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
19231 /// X86ISD::FXOR nodes.
19232 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
19233 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
19234 // F[X]OR(0.0, x) -> x
19235 // F[X]OR(x, 0.0) -> x
19236 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
19237 if (C->getValueAPF().isPosZero())
19238 return N->getOperand(1);
19239 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
19240 if (C->getValueAPF().isPosZero())
19241 return N->getOperand(0);
19245 /// PerformFMinFMaxCombine - Do target-specific dag combines on X86ISD::FMIN and
19246 /// X86ISD::FMAX nodes.
19247 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
19248 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
19250 // Only perform optimizations if UnsafeMath is used.
19251 if (!DAG.getTarget().Options.UnsafeFPMath)
19254 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
19255 // into FMINC and FMAXC, which are Commutative operations.
19256 unsigned NewOp = 0;
19257 switch (N->getOpcode()) {
19258 default: llvm_unreachable("unknown opcode");
19259 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
19260 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
19263 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
19264 N->getOperand(0), N->getOperand(1));
19267 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
19268 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
19269 // FAND(0.0, x) -> 0.0
19270 // FAND(x, 0.0) -> 0.0
19271 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
19272 if (C->getValueAPF().isPosZero())
19273 return N->getOperand(0);
19274 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
19275 if (C->getValueAPF().isPosZero())
19276 return N->getOperand(1);
19280 /// PerformFANDNCombine - Do target-specific dag combines on X86ISD::FANDN nodes
19281 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
19282 // FANDN(x, 0.0) -> 0.0
19283 // FANDN(0.0, x) -> x
19284 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
19285 if (C->getValueAPF().isPosZero())
19286 return N->getOperand(1);
19287 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
19288 if (C->getValueAPF().isPosZero())
19289 return N->getOperand(1);
19293 static SDValue PerformBTCombine(SDNode *N,
19295 TargetLowering::DAGCombinerInfo &DCI) {
19296 // BT ignores high bits in the bit index operand.
19297 SDValue Op1 = N->getOperand(1);
19298 if (Op1.hasOneUse()) {
19299 unsigned BitWidth = Op1.getValueSizeInBits();
19300 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
19301 APInt KnownZero, KnownOne;
19302 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
19303 !DCI.isBeforeLegalizeOps());
19304 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19305 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
19306 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
19307 DCI.CommitTargetLoweringOpt(TLO);
19312 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
19313 SDValue Op = N->getOperand(0);
19314 if (Op.getOpcode() == ISD::BITCAST)
19315 Op = Op.getOperand(0);
19316 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
19317 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
19318 VT.getVectorElementType().getSizeInBits() ==
19319 OpVT.getVectorElementType().getSizeInBits()) {
19320 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
19325 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
19326 const X86Subtarget *Subtarget) {
19327 EVT VT = N->getValueType(0);
19328 if (!VT.isVector())
19331 SDValue N0 = N->getOperand(0);
19332 SDValue N1 = N->getOperand(1);
19333 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
19336 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
19337 // both SSE and AVX2 since there is no sign-extended shift right
19338 // operation on a vector with 64-bit elements.
19339 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
19340 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
19341 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
19342 N0.getOpcode() == ISD::SIGN_EXTEND)) {
19343 SDValue N00 = N0.getOperand(0);
19345 // EXTLOAD has a better solution on AVX2,
19346 // it may be replaced with X86ISD::VSEXT node.
19347 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
19348 if (!ISD::isNormalLoad(N00.getNode()))
19351 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
19352 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
19354 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
19360 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
19361 TargetLowering::DAGCombinerInfo &DCI,
19362 const X86Subtarget *Subtarget) {
19363 if (!DCI.isBeforeLegalizeOps())
19366 if (!Subtarget->hasFp256())
19369 EVT VT = N->getValueType(0);
19370 if (VT.isVector() && VT.getSizeInBits() == 256) {
19371 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
19379 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
19380 const X86Subtarget* Subtarget) {
19382 EVT VT = N->getValueType(0);
19384 // Let legalize expand this if it isn't a legal type yet.
19385 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
19388 EVT ScalarVT = VT.getScalarType();
19389 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
19390 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
19393 SDValue A = N->getOperand(0);
19394 SDValue B = N->getOperand(1);
19395 SDValue C = N->getOperand(2);
19397 bool NegA = (A.getOpcode() == ISD::FNEG);
19398 bool NegB = (B.getOpcode() == ISD::FNEG);
19399 bool NegC = (C.getOpcode() == ISD::FNEG);
19401 // Negative multiplication when NegA xor NegB
19402 bool NegMul = (NegA != NegB);
19404 A = A.getOperand(0);
19406 B = B.getOperand(0);
19408 C = C.getOperand(0);
19412 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
19414 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
19416 return DAG.getNode(Opcode, dl, VT, A, B, C);
19419 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
19420 TargetLowering::DAGCombinerInfo &DCI,
19421 const X86Subtarget *Subtarget) {
19422 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
19423 // (and (i32 x86isd::setcc_carry), 1)
19424 // This eliminates the zext. This transformation is necessary because
19425 // ISD::SETCC is always legalized to i8.
19427 SDValue N0 = N->getOperand(0);
19428 EVT VT = N->getValueType(0);
19430 if (N0.getOpcode() == ISD::AND &&
19432 N0.getOperand(0).hasOneUse()) {
19433 SDValue N00 = N0.getOperand(0);
19434 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
19435 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
19436 if (!C || C->getZExtValue() != 1)
19438 return DAG.getNode(ISD::AND, dl, VT,
19439 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
19440 N00.getOperand(0), N00.getOperand(1)),
19441 DAG.getConstant(1, VT));
19445 if (N0.getOpcode() == ISD::TRUNCATE &&
19447 N0.getOperand(0).hasOneUse()) {
19448 SDValue N00 = N0.getOperand(0);
19449 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
19450 return DAG.getNode(ISD::AND, dl, VT,
19451 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
19452 N00.getOperand(0), N00.getOperand(1)),
19453 DAG.getConstant(1, VT));
19456 if (VT.is256BitVector()) {
19457 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
19465 // Optimize x == -y --> x+y == 0
19466 // x != -y --> x+y != 0
19467 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
19468 const X86Subtarget* Subtarget) {
19469 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
19470 SDValue LHS = N->getOperand(0);
19471 SDValue RHS = N->getOperand(1);
19472 EVT VT = N->getValueType(0);
19475 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
19476 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
19477 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
19478 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
19479 LHS.getValueType(), RHS, LHS.getOperand(1));
19480 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
19481 addV, DAG.getConstant(0, addV.getValueType()), CC);
19483 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
19484 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
19485 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
19486 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
19487 RHS.getValueType(), LHS, RHS.getOperand(1));
19488 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
19489 addV, DAG.getConstant(0, addV.getValueType()), CC);
19492 if (VT.getScalarType() == MVT::i1) {
19493 bool IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
19494 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
19495 bool IsVZero0 = ISD::isBuildVectorAllZeros(LHS.getNode());
19496 if (!IsSEXT0 && !IsVZero0)
19498 bool IsSEXT1 = (RHS.getOpcode() == ISD::SIGN_EXTEND) &&
19499 (RHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
19500 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
19502 if (!IsSEXT1 && !IsVZero1)
19505 if (IsSEXT0 && IsVZero1) {
19506 assert(VT == LHS.getOperand(0).getValueType() && "Uexpected operand type");
19507 if (CC == ISD::SETEQ)
19508 return DAG.getNOT(DL, LHS.getOperand(0), VT);
19509 return LHS.getOperand(0);
19511 if (IsSEXT1 && IsVZero0) {
19512 assert(VT == RHS.getOperand(0).getValueType() && "Uexpected operand type");
19513 if (CC == ISD::SETEQ)
19514 return DAG.getNOT(DL, RHS.getOperand(0), VT);
19515 return RHS.getOperand(0);
19522 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
19523 // as "sbb reg,reg", since it can be extended without zext and produces
19524 // an all-ones bit which is more useful than 0/1 in some cases.
19525 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
19528 return DAG.getNode(ISD::AND, DL, VT,
19529 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
19530 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
19531 DAG.getConstant(1, VT));
19532 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
19533 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
19534 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
19535 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS));
19538 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
19539 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
19540 TargetLowering::DAGCombinerInfo &DCI,
19541 const X86Subtarget *Subtarget) {
19543 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
19544 SDValue EFLAGS = N->getOperand(1);
19546 if (CC == X86::COND_A) {
19547 // Try to convert COND_A into COND_B in an attempt to facilitate
19548 // materializing "setb reg".
19550 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
19551 // cannot take an immediate as its first operand.
19553 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
19554 EFLAGS.getValueType().isInteger() &&
19555 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
19556 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
19557 EFLAGS.getNode()->getVTList(),
19558 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
19559 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
19560 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
19564 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
19565 // a zext and produces an all-ones bit which is more useful than 0/1 in some
19567 if (CC == X86::COND_B)
19568 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
19572 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
19573 if (Flags.getNode()) {
19574 SDValue Cond = DAG.getConstant(CC, MVT::i8);
19575 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
19581 // Optimize branch condition evaluation.
19583 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
19584 TargetLowering::DAGCombinerInfo &DCI,
19585 const X86Subtarget *Subtarget) {
19587 SDValue Chain = N->getOperand(0);
19588 SDValue Dest = N->getOperand(1);
19589 SDValue EFLAGS = N->getOperand(3);
19590 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
19594 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
19595 if (Flags.getNode()) {
19596 SDValue Cond = DAG.getConstant(CC, MVT::i8);
19597 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
19604 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
19605 const X86TargetLowering *XTLI) {
19606 SDValue Op0 = N->getOperand(0);
19607 EVT InVT = Op0->getValueType(0);
19609 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
19610 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
19612 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
19613 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
19614 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
19617 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
19618 // a 32-bit target where SSE doesn't support i64->FP operations.
19619 if (Op0.getOpcode() == ISD::LOAD) {
19620 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
19621 EVT VT = Ld->getValueType(0);
19622 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
19623 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
19624 !XTLI->getSubtarget()->is64Bit() &&
19626 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
19627 Ld->getChain(), Op0, DAG);
19628 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
19635 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
19636 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
19637 X86TargetLowering::DAGCombinerInfo &DCI) {
19638 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
19639 // the result is either zero or one (depending on the input carry bit).
19640 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
19641 if (X86::isZeroNode(N->getOperand(0)) &&
19642 X86::isZeroNode(N->getOperand(1)) &&
19643 // We don't have a good way to replace an EFLAGS use, so only do this when
19645 SDValue(N, 1).use_empty()) {
19647 EVT VT = N->getValueType(0);
19648 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
19649 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
19650 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
19651 DAG.getConstant(X86::COND_B,MVT::i8),
19653 DAG.getConstant(1, VT));
19654 return DCI.CombineTo(N, Res1, CarryOut);
19660 // fold (add Y, (sete X, 0)) -> adc 0, Y
19661 // (add Y, (setne X, 0)) -> sbb -1, Y
19662 // (sub (sete X, 0), Y) -> sbb 0, Y
19663 // (sub (setne X, 0), Y) -> adc -1, Y
19664 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
19667 // Look through ZExts.
19668 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
19669 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
19672 SDValue SetCC = Ext.getOperand(0);
19673 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
19676 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
19677 if (CC != X86::COND_E && CC != X86::COND_NE)
19680 SDValue Cmp = SetCC.getOperand(1);
19681 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
19682 !X86::isZeroNode(Cmp.getOperand(1)) ||
19683 !Cmp.getOperand(0).getValueType().isInteger())
19686 SDValue CmpOp0 = Cmp.getOperand(0);
19687 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
19688 DAG.getConstant(1, CmpOp0.getValueType()));
19690 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
19691 if (CC == X86::COND_NE)
19692 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
19693 DL, OtherVal.getValueType(), OtherVal,
19694 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
19695 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
19696 DL, OtherVal.getValueType(), OtherVal,
19697 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
19700 /// PerformADDCombine - Do target-specific dag combines on integer adds.
19701 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
19702 const X86Subtarget *Subtarget) {
19703 EVT VT = N->getValueType(0);
19704 SDValue Op0 = N->getOperand(0);
19705 SDValue Op1 = N->getOperand(1);
19707 // Try to synthesize horizontal adds from adds of shuffles.
19708 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
19709 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
19710 isHorizontalBinOp(Op0, Op1, true))
19711 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
19713 return OptimizeConditionalInDecrement(N, DAG);
19716 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
19717 const X86Subtarget *Subtarget) {
19718 SDValue Op0 = N->getOperand(0);
19719 SDValue Op1 = N->getOperand(1);
19721 // X86 can't encode an immediate LHS of a sub. See if we can push the
19722 // negation into a preceding instruction.
19723 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
19724 // If the RHS of the sub is a XOR with one use and a constant, invert the
19725 // immediate. Then add one to the LHS of the sub so we can turn
19726 // X-Y -> X+~Y+1, saving one register.
19727 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
19728 isa<ConstantSDNode>(Op1.getOperand(1))) {
19729 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
19730 EVT VT = Op0.getValueType();
19731 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
19733 DAG.getConstant(~XorC, VT));
19734 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
19735 DAG.getConstant(C->getAPIntValue()+1, VT));
19739 // Try to synthesize horizontal adds from adds of shuffles.
19740 EVT VT = N->getValueType(0);
19741 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
19742 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
19743 isHorizontalBinOp(Op0, Op1, true))
19744 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
19746 return OptimizeConditionalInDecrement(N, DAG);
19749 /// performVZEXTCombine - Performs build vector combines
19750 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
19751 TargetLowering::DAGCombinerInfo &DCI,
19752 const X86Subtarget *Subtarget) {
19753 // (vzext (bitcast (vzext (x)) -> (vzext x)
19754 SDValue In = N->getOperand(0);
19755 while (In.getOpcode() == ISD::BITCAST)
19756 In = In.getOperand(0);
19758 if (In.getOpcode() != X86ISD::VZEXT)
19761 return DAG.getNode(X86ISD::VZEXT, SDLoc(N), N->getValueType(0),
19765 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
19766 DAGCombinerInfo &DCI) const {
19767 SelectionDAG &DAG = DCI.DAG;
19768 switch (N->getOpcode()) {
19770 case ISD::EXTRACT_VECTOR_ELT:
19771 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
19773 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget);
19774 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
19775 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
19776 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
19777 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
19778 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
19781 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
19782 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
19783 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
19784 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
19785 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
19786 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
19787 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
19788 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
19789 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
19791 case X86ISD::FOR: return PerformFORCombine(N, DAG);
19793 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
19794 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
19795 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
19796 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
19797 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
19798 case ISD::ANY_EXTEND:
19799 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
19800 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
19801 case ISD::SIGN_EXTEND_INREG: return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
19802 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
19803 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
19804 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
19805 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
19806 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
19807 case X86ISD::SHUFP: // Handle all target specific shuffles
19808 case X86ISD::PALIGNR:
19809 case X86ISD::UNPCKH:
19810 case X86ISD::UNPCKL:
19811 case X86ISD::MOVHLPS:
19812 case X86ISD::MOVLHPS:
19813 case X86ISD::PSHUFD:
19814 case X86ISD::PSHUFHW:
19815 case X86ISD::PSHUFLW:
19816 case X86ISD::MOVSS:
19817 case X86ISD::MOVSD:
19818 case X86ISD::VPERMILP:
19819 case X86ISD::VPERM2X128:
19820 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
19821 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
19827 /// isTypeDesirableForOp - Return true if the target has native support for
19828 /// the specified value type and it is 'desirable' to use the type for the
19829 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
19830 /// instruction encodings are longer and some i16 instructions are slow.
19831 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
19832 if (!isTypeLegal(VT))
19834 if (VT != MVT::i16)
19841 case ISD::SIGN_EXTEND:
19842 case ISD::ZERO_EXTEND:
19843 case ISD::ANY_EXTEND:
19856 /// IsDesirableToPromoteOp - This method query the target whether it is
19857 /// beneficial for dag combiner to promote the specified node. If true, it
19858 /// should return the desired promotion type by reference.
19859 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
19860 EVT VT = Op.getValueType();
19861 if (VT != MVT::i16)
19864 bool Promote = false;
19865 bool Commute = false;
19866 switch (Op.getOpcode()) {
19869 LoadSDNode *LD = cast<LoadSDNode>(Op);
19870 // If the non-extending load has a single use and it's not live out, then it
19871 // might be folded.
19872 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
19873 Op.hasOneUse()*/) {
19874 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
19875 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
19876 // The only case where we'd want to promote LOAD (rather then it being
19877 // promoted as an operand is when it's only use is liveout.
19878 if (UI->getOpcode() != ISD::CopyToReg)
19885 case ISD::SIGN_EXTEND:
19886 case ISD::ZERO_EXTEND:
19887 case ISD::ANY_EXTEND:
19892 SDValue N0 = Op.getOperand(0);
19893 // Look out for (store (shl (load), x)).
19894 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
19907 SDValue N0 = Op.getOperand(0);
19908 SDValue N1 = Op.getOperand(1);
19909 if (!Commute && MayFoldLoad(N1))
19911 // Avoid disabling potential load folding opportunities.
19912 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
19914 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
19924 //===----------------------------------------------------------------------===//
19925 // X86 Inline Assembly Support
19926 //===----------------------------------------------------------------------===//
19929 // Helper to match a string separated by whitespace.
19930 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
19931 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
19933 for (unsigned i = 0, e = args.size(); i != e; ++i) {
19934 StringRef piece(*args[i]);
19935 if (!s.startswith(piece)) // Check if the piece matches.
19938 s = s.substr(piece.size());
19939 StringRef::size_type pos = s.find_first_not_of(" \t");
19940 if (pos == 0) // We matched a prefix.
19948 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
19951 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
19953 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
19954 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
19955 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
19956 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
19958 if (AsmPieces.size() == 3)
19960 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
19967 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
19968 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
19970 std::string AsmStr = IA->getAsmString();
19972 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
19973 if (!Ty || Ty->getBitWidth() % 16 != 0)
19976 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
19977 SmallVector<StringRef, 4> AsmPieces;
19978 SplitString(AsmStr, AsmPieces, ";\n");
19980 switch (AsmPieces.size()) {
19981 default: return false;
19983 // FIXME: this should verify that we are targeting a 486 or better. If not,
19984 // we will turn this bswap into something that will be lowered to logical
19985 // ops instead of emitting the bswap asm. For now, we don't support 486 or
19986 // lower so don't worry about this.
19988 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
19989 matchAsm(AsmPieces[0], "bswapl", "$0") ||
19990 matchAsm(AsmPieces[0], "bswapq", "$0") ||
19991 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
19992 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
19993 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
19994 // No need to check constraints, nothing other than the equivalent of
19995 // "=r,0" would be valid here.
19996 return IntrinsicLowering::LowerToByteSwap(CI);
19999 // rorw $$8, ${0:w} --> llvm.bswap.i16
20000 if (CI->getType()->isIntegerTy(16) &&
20001 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
20002 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
20003 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
20005 const std::string &ConstraintsStr = IA->getConstraintString();
20006 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
20007 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
20008 if (clobbersFlagRegisters(AsmPieces))
20009 return IntrinsicLowering::LowerToByteSwap(CI);
20013 if (CI->getType()->isIntegerTy(32) &&
20014 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
20015 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
20016 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
20017 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
20019 const std::string &ConstraintsStr = IA->getConstraintString();
20020 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
20021 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
20022 if (clobbersFlagRegisters(AsmPieces))
20023 return IntrinsicLowering::LowerToByteSwap(CI);
20026 if (CI->getType()->isIntegerTy(64)) {
20027 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
20028 if (Constraints.size() >= 2 &&
20029 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
20030 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
20031 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
20032 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
20033 matchAsm(AsmPieces[1], "bswap", "%edx") &&
20034 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
20035 return IntrinsicLowering::LowerToByteSwap(CI);
20043 /// getConstraintType - Given a constraint letter, return the type of
20044 /// constraint it is for this target.
20045 X86TargetLowering::ConstraintType
20046 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
20047 if (Constraint.size() == 1) {
20048 switch (Constraint[0]) {
20059 return C_RegisterClass;
20083 return TargetLowering::getConstraintType(Constraint);
20086 /// Examine constraint type and operand type and determine a weight value.
20087 /// This object must already have been set up with the operand type
20088 /// and the current alternative constraint selected.
20089 TargetLowering::ConstraintWeight
20090 X86TargetLowering::getSingleConstraintMatchWeight(
20091 AsmOperandInfo &info, const char *constraint) const {
20092 ConstraintWeight weight = CW_Invalid;
20093 Value *CallOperandVal = info.CallOperandVal;
20094 // If we don't have a value, we can't do a match,
20095 // but allow it at the lowest weight.
20096 if (CallOperandVal == NULL)
20098 Type *type = CallOperandVal->getType();
20099 // Look at the constraint type.
20100 switch (*constraint) {
20102 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
20113 if (CallOperandVal->getType()->isIntegerTy())
20114 weight = CW_SpecificReg;
20119 if (type->isFloatingPointTy())
20120 weight = CW_SpecificReg;
20123 if (type->isX86_MMXTy() && Subtarget->hasMMX())
20124 weight = CW_SpecificReg;
20128 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
20129 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
20130 weight = CW_Register;
20133 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
20134 if (C->getZExtValue() <= 31)
20135 weight = CW_Constant;
20139 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
20140 if (C->getZExtValue() <= 63)
20141 weight = CW_Constant;
20145 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
20146 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
20147 weight = CW_Constant;
20151 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
20152 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
20153 weight = CW_Constant;
20157 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
20158 if (C->getZExtValue() <= 3)
20159 weight = CW_Constant;
20163 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
20164 if (C->getZExtValue() <= 0xff)
20165 weight = CW_Constant;
20170 if (dyn_cast<ConstantFP>(CallOperandVal)) {
20171 weight = CW_Constant;
20175 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
20176 if ((C->getSExtValue() >= -0x80000000LL) &&
20177 (C->getSExtValue() <= 0x7fffffffLL))
20178 weight = CW_Constant;
20182 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
20183 if (C->getZExtValue() <= 0xffffffff)
20184 weight = CW_Constant;
20191 /// LowerXConstraint - try to replace an X constraint, which matches anything,
20192 /// with another that has more specific requirements based on the type of the
20193 /// corresponding operand.
20194 const char *X86TargetLowering::
20195 LowerXConstraint(EVT ConstraintVT) const {
20196 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
20197 // 'f' like normal targets.
20198 if (ConstraintVT.isFloatingPoint()) {
20199 if (Subtarget->hasSSE2())
20201 if (Subtarget->hasSSE1())
20205 return TargetLowering::LowerXConstraint(ConstraintVT);
20208 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
20209 /// vector. If it is invalid, don't add anything to Ops.
20210 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
20211 std::string &Constraint,
20212 std::vector<SDValue>&Ops,
20213 SelectionDAG &DAG) const {
20214 SDValue Result(0, 0);
20216 // Only support length 1 constraints for now.
20217 if (Constraint.length() > 1) return;
20219 char ConstraintLetter = Constraint[0];
20220 switch (ConstraintLetter) {
20223 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
20224 if (C->getZExtValue() <= 31) {
20225 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
20231 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
20232 if (C->getZExtValue() <= 63) {
20233 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
20239 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
20240 if (isInt<8>(C->getSExtValue())) {
20241 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
20247 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
20248 if (C->getZExtValue() <= 255) {
20249 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
20255 // 32-bit signed value
20256 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
20257 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
20258 C->getSExtValue())) {
20259 // Widen to 64 bits here to get it sign extended.
20260 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
20263 // FIXME gcc accepts some relocatable values here too, but only in certain
20264 // memory models; it's complicated.
20269 // 32-bit unsigned value
20270 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
20271 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
20272 C->getZExtValue())) {
20273 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
20277 // FIXME gcc accepts some relocatable values here too, but only in certain
20278 // memory models; it's complicated.
20282 // Literal immediates are always ok.
20283 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
20284 // Widen to 64 bits here to get it sign extended.
20285 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
20289 // In any sort of PIC mode addresses need to be computed at runtime by
20290 // adding in a register or some sort of table lookup. These can't
20291 // be used as immediates.
20292 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
20295 // If we are in non-pic codegen mode, we allow the address of a global (with
20296 // an optional displacement) to be used with 'i'.
20297 GlobalAddressSDNode *GA = 0;
20298 int64_t Offset = 0;
20300 // Match either (GA), (GA+C), (GA+C1+C2), etc.
20302 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
20303 Offset += GA->getOffset();
20305 } else if (Op.getOpcode() == ISD::ADD) {
20306 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
20307 Offset += C->getZExtValue();
20308 Op = Op.getOperand(0);
20311 } else if (Op.getOpcode() == ISD::SUB) {
20312 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
20313 Offset += -C->getZExtValue();
20314 Op = Op.getOperand(0);
20319 // Otherwise, this isn't something we can handle, reject it.
20323 const GlobalValue *GV = GA->getGlobal();
20324 // If we require an extra load to get this address, as in PIC mode, we
20325 // can't accept it.
20326 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
20327 getTargetMachine())))
20330 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
20331 GA->getValueType(0), Offset);
20336 if (Result.getNode()) {
20337 Ops.push_back(Result);
20340 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
20343 std::pair<unsigned, const TargetRegisterClass*>
20344 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
20346 // First, see if this is a constraint that directly corresponds to an LLVM
20348 if (Constraint.size() == 1) {
20349 // GCC Constraint Letters
20350 switch (Constraint[0]) {
20352 // TODO: Slight differences here in allocation order and leaving
20353 // RIP in the class. Do they matter any more here than they do
20354 // in the normal allocation?
20355 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
20356 if (Subtarget->is64Bit()) {
20357 if (VT == MVT::i32 || VT == MVT::f32)
20358 return std::make_pair(0U, &X86::GR32RegClass);
20359 if (VT == MVT::i16)
20360 return std::make_pair(0U, &X86::GR16RegClass);
20361 if (VT == MVT::i8 || VT == MVT::i1)
20362 return std::make_pair(0U, &X86::GR8RegClass);
20363 if (VT == MVT::i64 || VT == MVT::f64)
20364 return std::make_pair(0U, &X86::GR64RegClass);
20367 // 32-bit fallthrough
20368 case 'Q': // Q_REGS
20369 if (VT == MVT::i32 || VT == MVT::f32)
20370 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
20371 if (VT == MVT::i16)
20372 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
20373 if (VT == MVT::i8 || VT == MVT::i1)
20374 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
20375 if (VT == MVT::i64)
20376 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
20378 case 'r': // GENERAL_REGS
20379 case 'l': // INDEX_REGS
20380 if (VT == MVT::i8 || VT == MVT::i1)
20381 return std::make_pair(0U, &X86::GR8RegClass);
20382 if (VT == MVT::i16)
20383 return std::make_pair(0U, &X86::GR16RegClass);
20384 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
20385 return std::make_pair(0U, &X86::GR32RegClass);
20386 return std::make_pair(0U, &X86::GR64RegClass);
20387 case 'R': // LEGACY_REGS
20388 if (VT == MVT::i8 || VT == MVT::i1)
20389 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
20390 if (VT == MVT::i16)
20391 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
20392 if (VT == MVT::i32 || !Subtarget->is64Bit())
20393 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
20394 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
20395 case 'f': // FP Stack registers.
20396 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
20397 // value to the correct fpstack register class.
20398 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
20399 return std::make_pair(0U, &X86::RFP32RegClass);
20400 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
20401 return std::make_pair(0U, &X86::RFP64RegClass);
20402 return std::make_pair(0U, &X86::RFP80RegClass);
20403 case 'y': // MMX_REGS if MMX allowed.
20404 if (!Subtarget->hasMMX()) break;
20405 return std::make_pair(0U, &X86::VR64RegClass);
20406 case 'Y': // SSE_REGS if SSE2 allowed
20407 if (!Subtarget->hasSSE2()) break;
20409 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
20410 if (!Subtarget->hasSSE1()) break;
20412 switch (VT.SimpleTy) {
20414 // Scalar SSE types.
20417 return std::make_pair(0U, &X86::FR32RegClass);
20420 return std::make_pair(0U, &X86::FR64RegClass);
20428 return std::make_pair(0U, &X86::VR128RegClass);
20436 return std::make_pair(0U, &X86::VR256RegClass);
20441 return std::make_pair(0U, &X86::VR512RegClass);
20447 // Use the default implementation in TargetLowering to convert the register
20448 // constraint into a member of a register class.
20449 std::pair<unsigned, const TargetRegisterClass*> Res;
20450 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
20452 // Not found as a standard register?
20453 if (Res.second == 0) {
20454 // Map st(0) -> st(7) -> ST0
20455 if (Constraint.size() == 7 && Constraint[0] == '{' &&
20456 tolower(Constraint[1]) == 's' &&
20457 tolower(Constraint[2]) == 't' &&
20458 Constraint[3] == '(' &&
20459 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
20460 Constraint[5] == ')' &&
20461 Constraint[6] == '}') {
20463 Res.first = X86::ST0+Constraint[4]-'0';
20464 Res.second = &X86::RFP80RegClass;
20468 // GCC allows "st(0)" to be called just plain "st".
20469 if (StringRef("{st}").equals_lower(Constraint)) {
20470 Res.first = X86::ST0;
20471 Res.second = &X86::RFP80RegClass;
20476 if (StringRef("{flags}").equals_lower(Constraint)) {
20477 Res.first = X86::EFLAGS;
20478 Res.second = &X86::CCRRegClass;
20482 // 'A' means EAX + EDX.
20483 if (Constraint == "A") {
20484 Res.first = X86::EAX;
20485 Res.second = &X86::GR32_ADRegClass;
20491 // Otherwise, check to see if this is a register class of the wrong value
20492 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
20493 // turn into {ax},{dx}.
20494 if (Res.second->hasType(VT))
20495 return Res; // Correct type already, nothing to do.
20497 // All of the single-register GCC register classes map their values onto
20498 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
20499 // really want an 8-bit or 32-bit register, map to the appropriate register
20500 // class and return the appropriate register.
20501 if (Res.second == &X86::GR16RegClass) {
20502 if (VT == MVT::i8 || VT == MVT::i1) {
20503 unsigned DestReg = 0;
20504 switch (Res.first) {
20506 case X86::AX: DestReg = X86::AL; break;
20507 case X86::DX: DestReg = X86::DL; break;
20508 case X86::CX: DestReg = X86::CL; break;
20509 case X86::BX: DestReg = X86::BL; break;
20512 Res.first = DestReg;
20513 Res.second = &X86::GR8RegClass;
20515 } else if (VT == MVT::i32 || VT == MVT::f32) {
20516 unsigned DestReg = 0;
20517 switch (Res.first) {
20519 case X86::AX: DestReg = X86::EAX; break;
20520 case X86::DX: DestReg = X86::EDX; break;
20521 case X86::CX: DestReg = X86::ECX; break;
20522 case X86::BX: DestReg = X86::EBX; break;
20523 case X86::SI: DestReg = X86::ESI; break;
20524 case X86::DI: DestReg = X86::EDI; break;
20525 case X86::BP: DestReg = X86::EBP; break;
20526 case X86::SP: DestReg = X86::ESP; break;
20529 Res.first = DestReg;
20530 Res.second = &X86::GR32RegClass;
20532 } else if (VT == MVT::i64 || VT == MVT::f64) {
20533 unsigned DestReg = 0;
20534 switch (Res.first) {
20536 case X86::AX: DestReg = X86::RAX; break;
20537 case X86::DX: DestReg = X86::RDX; break;
20538 case X86::CX: DestReg = X86::RCX; break;
20539 case X86::BX: DestReg = X86::RBX; break;
20540 case X86::SI: DestReg = X86::RSI; break;
20541 case X86::DI: DestReg = X86::RDI; break;
20542 case X86::BP: DestReg = X86::RBP; break;
20543 case X86::SP: DestReg = X86::RSP; break;
20546 Res.first = DestReg;
20547 Res.second = &X86::GR64RegClass;
20550 } else if (Res.second == &X86::FR32RegClass ||
20551 Res.second == &X86::FR64RegClass ||
20552 Res.second == &X86::VR128RegClass ||
20553 Res.second == &X86::VR256RegClass ||
20554 Res.second == &X86::FR32XRegClass ||
20555 Res.second == &X86::FR64XRegClass ||
20556 Res.second == &X86::VR128XRegClass ||
20557 Res.second == &X86::VR256XRegClass ||
20558 Res.second == &X86::VR512RegClass) {
20559 // Handle references to XMM physical registers that got mapped into the
20560 // wrong class. This can happen with constraints like {xmm0} where the
20561 // target independent register mapper will just pick the first match it can
20562 // find, ignoring the required type.
20564 if (VT == MVT::f32 || VT == MVT::i32)
20565 Res.second = &X86::FR32RegClass;
20566 else if (VT == MVT::f64 || VT == MVT::i64)
20567 Res.second = &X86::FR64RegClass;
20568 else if (X86::VR128RegClass.hasType(VT))
20569 Res.second = &X86::VR128RegClass;
20570 else if (X86::VR256RegClass.hasType(VT))
20571 Res.second = &X86::VR256RegClass;
20572 else if (X86::VR512RegClass.hasType(VT))
20573 Res.second = &X86::VR512RegClass;