1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/ADT/SmallBitVector.h"
23 #include "llvm/ADT/SmallSet.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/ADT/StringSwitch.h"
27 #include "llvm/ADT/VariadicFunction.h"
28 #include "llvm/CodeGen/IntrinsicLowering.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/IR/CallSite.h"
36 #include "llvm/IR/CallingConv.h"
37 #include "llvm/IR/Constants.h"
38 #include "llvm/IR/DerivedTypes.h"
39 #include "llvm/IR/Function.h"
40 #include "llvm/IR/GlobalAlias.h"
41 #include "llvm/IR/GlobalVariable.h"
42 #include "llvm/IR/Instructions.h"
43 #include "llvm/IR/Intrinsics.h"
44 #include "llvm/MC/MCAsmInfo.h"
45 #include "llvm/MC/MCContext.h"
46 #include "llvm/MC/MCExpr.h"
47 #include "llvm/MC/MCSymbol.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/MathExtras.h"
52 #include "llvm/Target/TargetOptions.h"
53 #include "X86IntrinsicsInfo.h"
59 #define DEBUG_TYPE "x86-isel"
61 STATISTIC(NumTailCalls, "Number of tail calls");
63 static cl::opt<bool> ExperimentalVectorWideningLegalization(
64 "x86-experimental-vector-widening-legalization", cl::init(false),
65 cl::desc("Enable an experimental vector type legalization through widening "
66 "rather than promotion."),
69 static cl::opt<bool> ExperimentalVectorShuffleLowering(
70 "x86-experimental-vector-shuffle-lowering", cl::init(false),
71 cl::desc("Enable an experimental vector shuffle lowering code path."),
74 // Forward declarations.
75 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
78 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
79 SelectionDAG &DAG, SDLoc dl,
80 unsigned vectorWidth) {
81 assert((vectorWidth == 128 || vectorWidth == 256) &&
82 "Unsupported vector width");
83 EVT VT = Vec.getValueType();
84 EVT ElVT = VT.getVectorElementType();
85 unsigned Factor = VT.getSizeInBits()/vectorWidth;
86 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
87 VT.getVectorNumElements()/Factor);
89 // Extract from UNDEF is UNDEF.
90 if (Vec.getOpcode() == ISD::UNDEF)
91 return DAG.getUNDEF(ResultVT);
93 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
94 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
96 // This is the index of the first element of the vectorWidth-bit chunk
98 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
101 // If the input is a buildvector just emit a smaller one.
102 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
103 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
104 makeArrayRef(Vec->op_begin()+NormalizedIdxVal,
107 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
108 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
114 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
115 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
116 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
117 /// instructions or a simple subregister reference. Idx is an index in the
118 /// 128 bits we want. It need not be aligned to a 128-bit bounday. That makes
119 /// lowering EXTRACT_VECTOR_ELT operations easier.
120 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
121 SelectionDAG &DAG, SDLoc dl) {
122 assert((Vec.getValueType().is256BitVector() ||
123 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
124 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
127 /// Generate a DAG to grab 256-bits from a 512-bit vector.
128 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
129 SelectionDAG &DAG, SDLoc dl) {
130 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
131 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
134 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
135 unsigned IdxVal, SelectionDAG &DAG,
136 SDLoc dl, unsigned vectorWidth) {
137 assert((vectorWidth == 128 || vectorWidth == 256) &&
138 "Unsupported vector width");
139 // Inserting UNDEF is Result
140 if (Vec.getOpcode() == ISD::UNDEF)
142 EVT VT = Vec.getValueType();
143 EVT ElVT = VT.getVectorElementType();
144 EVT ResultVT = Result.getValueType();
146 // Insert the relevant vectorWidth bits.
147 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
149 // This is the index of the first element of the vectorWidth-bit chunk
151 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
154 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
155 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
158 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
159 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
160 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
161 /// simple superregister reference. Idx is an index in the 128 bits
162 /// we want. It need not be aligned to a 128-bit bounday. That makes
163 /// lowering INSERT_VECTOR_ELT operations easier.
164 static SDValue Insert128BitVector(SDValue Result, SDValue Vec,
165 unsigned IdxVal, SelectionDAG &DAG,
167 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
168 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
171 static SDValue Insert256BitVector(SDValue Result, SDValue Vec,
172 unsigned IdxVal, SelectionDAG &DAG,
174 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
175 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
178 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
179 /// instructions. This is used because creating CONCAT_VECTOR nodes of
180 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
181 /// large BUILD_VECTORS.
182 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
183 unsigned NumElems, SelectionDAG &DAG,
185 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
186 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
189 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
190 unsigned NumElems, SelectionDAG &DAG,
192 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
193 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
196 static TargetLoweringObjectFile *createTLOF(const Triple &TT) {
197 if (TT.isOSBinFormatMachO()) {
198 if (TT.getArch() == Triple::x86_64)
199 return new X86_64MachoTargetObjectFile();
200 return new TargetLoweringObjectFileMachO();
204 return new X86LinuxTargetObjectFile();
205 if (TT.isOSBinFormatELF())
206 return new TargetLoweringObjectFileELF();
207 if (TT.isKnownWindowsMSVCEnvironment())
208 return new X86WindowsTargetObjectFile();
209 if (TT.isOSBinFormatCOFF())
210 return new TargetLoweringObjectFileCOFF();
211 llvm_unreachable("unknown subtarget type");
214 // FIXME: This should stop caching the target machine as soon as
215 // we can remove resetOperationActions et al.
216 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
217 : TargetLowering(TM, createTLOF(Triple(TM.getTargetTriple()))) {
218 Subtarget = &TM.getSubtarget<X86Subtarget>();
219 X86ScalarSSEf64 = Subtarget->hasSSE2();
220 X86ScalarSSEf32 = Subtarget->hasSSE1();
221 TD = getDataLayout();
223 resetOperationActions();
226 void X86TargetLowering::resetOperationActions() {
227 const TargetMachine &TM = getTargetMachine();
228 static bool FirstTimeThrough = true;
230 // If none of the target options have changed, then we don't need to reset the
231 // operation actions.
232 if (!FirstTimeThrough && TO == TM.Options) return;
234 if (!FirstTimeThrough) {
235 // Reinitialize the actions.
237 FirstTimeThrough = false;
242 // Set up the TargetLowering object.
243 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
245 // X86 is weird, it always uses i8 for shift amounts and setcc results.
246 setBooleanContents(ZeroOrOneBooleanContent);
247 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
248 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
250 // For 64-bit since we have so many registers use the ILP scheduler, for
251 // 32-bit code use the register pressure specific scheduling.
252 // For Atom, always use ILP scheduling.
253 if (Subtarget->isAtom())
254 setSchedulingPreference(Sched::ILP);
255 else if (Subtarget->is64Bit())
256 setSchedulingPreference(Sched::ILP);
258 setSchedulingPreference(Sched::RegPressure);
259 const X86RegisterInfo *RegInfo =
260 TM.getSubtarget<X86Subtarget>().getRegisterInfo();
261 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
263 // Bypass expensive divides on Atom when compiling with O2
264 if (Subtarget->hasSlowDivide() && TM.getOptLevel() >= CodeGenOpt::Default) {
265 addBypassSlowDiv(32, 8);
266 if (Subtarget->is64Bit())
267 addBypassSlowDiv(64, 16);
270 if (Subtarget->isTargetKnownWindowsMSVC()) {
271 // Setup Windows compiler runtime calls.
272 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
273 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
274 setLibcallName(RTLIB::SREM_I64, "_allrem");
275 setLibcallName(RTLIB::UREM_I64, "_aullrem");
276 setLibcallName(RTLIB::MUL_I64, "_allmul");
277 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
278 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
279 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
280 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
281 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
283 // The _ftol2 runtime function has an unusual calling conv, which
284 // is modeled by a special pseudo-instruction.
285 setLibcallName(RTLIB::FPTOUINT_F64_I64, nullptr);
286 setLibcallName(RTLIB::FPTOUINT_F32_I64, nullptr);
287 setLibcallName(RTLIB::FPTOUINT_F64_I32, nullptr);
288 setLibcallName(RTLIB::FPTOUINT_F32_I32, nullptr);
291 if (Subtarget->isTargetDarwin()) {
292 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
293 setUseUnderscoreSetJmp(false);
294 setUseUnderscoreLongJmp(false);
295 } else if (Subtarget->isTargetWindowsGNU()) {
296 // MS runtime is weird: it exports _setjmp, but longjmp!
297 setUseUnderscoreSetJmp(true);
298 setUseUnderscoreLongJmp(false);
300 setUseUnderscoreSetJmp(true);
301 setUseUnderscoreLongJmp(true);
304 // Set up the register classes.
305 addRegisterClass(MVT::i8, &X86::GR8RegClass);
306 addRegisterClass(MVT::i16, &X86::GR16RegClass);
307 addRegisterClass(MVT::i32, &X86::GR32RegClass);
308 if (Subtarget->is64Bit())
309 addRegisterClass(MVT::i64, &X86::GR64RegClass);
311 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
313 // We don't accept any truncstore of integer registers.
314 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
315 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
316 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
317 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
318 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
319 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
321 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
323 // SETOEQ and SETUNE require checking two conditions.
324 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
325 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
326 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
327 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
328 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
329 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
331 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
333 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
334 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
335 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
337 if (Subtarget->is64Bit()) {
338 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
339 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
340 } else if (!TM.Options.UseSoftFloat) {
341 // We have an algorithm for SSE2->double, and we turn this into a
342 // 64-bit FILD followed by conditional FADD for other targets.
343 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
344 // We have an algorithm for SSE2, and we turn this into a 64-bit
345 // FILD for other targets.
346 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
349 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
351 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
352 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
354 if (!TM.Options.UseSoftFloat) {
355 // SSE has no i16 to fp conversion, only i32
356 if (X86ScalarSSEf32) {
357 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
358 // f32 and f64 cases are Legal, f80 case is not
359 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
361 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
362 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
365 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
366 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
369 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
370 // are Legal, f80 is custom lowered.
371 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
372 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
374 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
376 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
377 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
379 if (X86ScalarSSEf32) {
380 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
381 // f32 and f64 cases are Legal, f80 case is not
382 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
384 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
385 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
388 // Handle FP_TO_UINT by promoting the destination to a larger signed
390 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
391 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
392 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
394 if (Subtarget->is64Bit()) {
395 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
396 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
397 } else if (!TM.Options.UseSoftFloat) {
398 // Since AVX is a superset of SSE3, only check for SSE here.
399 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
400 // Expand FP_TO_UINT into a select.
401 // FIXME: We would like to use a Custom expander here eventually to do
402 // the optimal thing for SSE vs. the default expansion in the legalizer.
403 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
405 // With SSE3 we can use fisttpll to convert to a signed i64; without
406 // SSE, we're stuck with a fistpll.
407 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
410 if (isTargetFTOL()) {
411 // Use the _ftol2 runtime function, which has a pseudo-instruction
412 // to handle its weird calling convention.
413 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
416 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
417 if (!X86ScalarSSEf64) {
418 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
419 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
420 if (Subtarget->is64Bit()) {
421 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
422 // Without SSE, i64->f64 goes through memory.
423 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
427 // Scalar integer divide and remainder are lowered to use operations that
428 // produce two results, to match the available instructions. This exposes
429 // the two-result form to trivial CSE, which is able to combine x/y and x%y
430 // into a single instruction.
432 // Scalar integer multiply-high is also lowered to use two-result
433 // operations, to match the available instructions. However, plain multiply
434 // (low) operations are left as Legal, as there are single-result
435 // instructions for this in x86. Using the two-result multiply instructions
436 // when both high and low results are needed must be arranged by dagcombine.
437 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
439 setOperationAction(ISD::MULHS, VT, Expand);
440 setOperationAction(ISD::MULHU, VT, Expand);
441 setOperationAction(ISD::SDIV, VT, Expand);
442 setOperationAction(ISD::UDIV, VT, Expand);
443 setOperationAction(ISD::SREM, VT, Expand);
444 setOperationAction(ISD::UREM, VT, Expand);
446 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
447 setOperationAction(ISD::ADDC, VT, Custom);
448 setOperationAction(ISD::ADDE, VT, Custom);
449 setOperationAction(ISD::SUBC, VT, Custom);
450 setOperationAction(ISD::SUBE, VT, Custom);
453 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
454 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
455 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
456 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
457 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
458 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
459 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
460 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
461 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
462 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
463 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
464 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
465 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
466 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
467 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
468 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
469 if (Subtarget->is64Bit())
470 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
471 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
472 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
473 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
474 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
475 setOperationAction(ISD::FREM , MVT::f32 , Expand);
476 setOperationAction(ISD::FREM , MVT::f64 , Expand);
477 setOperationAction(ISD::FREM , MVT::f80 , Expand);
478 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
480 // Promote the i8 variants and force them on up to i32 which has a shorter
482 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
483 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
484 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
485 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
486 if (Subtarget->hasBMI()) {
487 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
488 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
489 if (Subtarget->is64Bit())
490 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
492 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
493 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
494 if (Subtarget->is64Bit())
495 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
498 if (Subtarget->hasLZCNT()) {
499 // When promoting the i8 variants, force them to i32 for a shorter
501 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
502 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
503 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
504 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
505 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
506 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
507 if (Subtarget->is64Bit())
508 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
510 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
511 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
512 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
513 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
514 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
515 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
516 if (Subtarget->is64Bit()) {
517 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
518 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
522 // Special handling for half-precision floating point conversions.
523 // If we don't have F16C support, then lower half float conversions
524 // into library calls.
525 if (TM.Options.UseSoftFloat || !Subtarget->hasF16C()) {
526 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
527 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
530 // There's never any support for operations beyond MVT::f32.
531 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
532 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
533 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
534 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
536 setLoadExtAction(ISD::EXTLOAD, MVT::f16, Expand);
537 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
538 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
539 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
541 if (Subtarget->hasPOPCNT()) {
542 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
544 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
545 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
546 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
547 if (Subtarget->is64Bit())
548 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
551 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
553 if (!Subtarget->hasMOVBE())
554 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
556 // These should be promoted to a larger select which is supported.
557 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
558 // X86 wants to expand cmov itself.
559 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
560 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
561 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
562 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
563 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
564 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
565 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
566 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
567 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
568 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
569 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
570 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
571 if (Subtarget->is64Bit()) {
572 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
573 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
575 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
576 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
577 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
578 // support continuation, user-level threading, and etc.. As a result, no
579 // other SjLj exception interfaces are implemented and please don't build
580 // your own exception handling based on them.
581 // LLVM/Clang supports zero-cost DWARF exception handling.
582 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
583 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
586 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
587 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
588 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
589 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
590 if (Subtarget->is64Bit())
591 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
592 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
593 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
594 if (Subtarget->is64Bit()) {
595 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
596 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
597 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
598 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
599 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
601 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
602 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
603 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
604 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
605 if (Subtarget->is64Bit()) {
606 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
607 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
608 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
611 if (Subtarget->hasSSE1())
612 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
614 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
616 // Expand certain atomics
617 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
619 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
620 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
621 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
624 if (Subtarget->hasCmpxchg16b()) {
625 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
628 // FIXME - use subtarget debug flags
629 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
630 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
631 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
634 if (Subtarget->is64Bit()) {
635 setExceptionPointerRegister(X86::RAX);
636 setExceptionSelectorRegister(X86::RDX);
638 setExceptionPointerRegister(X86::EAX);
639 setExceptionSelectorRegister(X86::EDX);
641 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
642 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
644 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
645 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
647 setOperationAction(ISD::TRAP, MVT::Other, Legal);
648 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
650 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
651 setOperationAction(ISD::VASTART , MVT::Other, Custom);
652 setOperationAction(ISD::VAEND , MVT::Other, Expand);
653 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
654 // TargetInfo::X86_64ABIBuiltinVaList
655 setOperationAction(ISD::VAARG , MVT::Other, Custom);
656 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
658 // TargetInfo::CharPtrBuiltinVaList
659 setOperationAction(ISD::VAARG , MVT::Other, Expand);
660 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
663 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
664 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
666 setOperationAction(ISD::DYNAMIC_STACKALLOC, getPointerTy(), Custom);
668 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
669 // f32 and f64 use SSE.
670 // Set up the FP register classes.
671 addRegisterClass(MVT::f32, &X86::FR32RegClass);
672 addRegisterClass(MVT::f64, &X86::FR64RegClass);
674 // Use ANDPD to simulate FABS.
675 setOperationAction(ISD::FABS , MVT::f64, Custom);
676 setOperationAction(ISD::FABS , MVT::f32, Custom);
678 // Use XORP to simulate FNEG.
679 setOperationAction(ISD::FNEG , MVT::f64, Custom);
680 setOperationAction(ISD::FNEG , MVT::f32, Custom);
682 // Use ANDPD and ORPD to simulate FCOPYSIGN.
683 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
684 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
686 // Lower this to FGETSIGNx86 plus an AND.
687 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
688 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
690 // We don't support sin/cos/fmod
691 setOperationAction(ISD::FSIN , MVT::f64, Expand);
692 setOperationAction(ISD::FCOS , MVT::f64, Expand);
693 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
694 setOperationAction(ISD::FSIN , MVT::f32, Expand);
695 setOperationAction(ISD::FCOS , MVT::f32, Expand);
696 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
698 // Expand FP immediates into loads from the stack, except for the special
700 addLegalFPImmediate(APFloat(+0.0)); // xorpd
701 addLegalFPImmediate(APFloat(+0.0f)); // xorps
702 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
703 // Use SSE for f32, x87 for f64.
704 // Set up the FP register classes.
705 addRegisterClass(MVT::f32, &X86::FR32RegClass);
706 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
708 // Use ANDPS to simulate FABS.
709 setOperationAction(ISD::FABS , MVT::f32, Custom);
711 // Use XORP to simulate FNEG.
712 setOperationAction(ISD::FNEG , MVT::f32, Custom);
714 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
716 // Use ANDPS and ORPS to simulate FCOPYSIGN.
717 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
718 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
720 // We don't support sin/cos/fmod
721 setOperationAction(ISD::FSIN , MVT::f32, Expand);
722 setOperationAction(ISD::FCOS , MVT::f32, Expand);
723 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
725 // Special cases we handle for FP constants.
726 addLegalFPImmediate(APFloat(+0.0f)); // xorps
727 addLegalFPImmediate(APFloat(+0.0)); // FLD0
728 addLegalFPImmediate(APFloat(+1.0)); // FLD1
729 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
730 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
732 if (!TM.Options.UnsafeFPMath) {
733 setOperationAction(ISD::FSIN , MVT::f64, Expand);
734 setOperationAction(ISD::FCOS , MVT::f64, Expand);
735 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
737 } else if (!TM.Options.UseSoftFloat) {
738 // f32 and f64 in x87.
739 // Set up the FP register classes.
740 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
741 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
743 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
744 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
745 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
746 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
748 if (!TM.Options.UnsafeFPMath) {
749 setOperationAction(ISD::FSIN , MVT::f64, Expand);
750 setOperationAction(ISD::FSIN , MVT::f32, Expand);
751 setOperationAction(ISD::FCOS , MVT::f64, Expand);
752 setOperationAction(ISD::FCOS , MVT::f32, Expand);
753 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
754 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
756 addLegalFPImmediate(APFloat(+0.0)); // FLD0
757 addLegalFPImmediate(APFloat(+1.0)); // FLD1
758 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
759 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
760 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
761 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
762 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
763 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
766 // We don't support FMA.
767 setOperationAction(ISD::FMA, MVT::f64, Expand);
768 setOperationAction(ISD::FMA, MVT::f32, Expand);
770 // Long double always uses X87.
771 if (!TM.Options.UseSoftFloat) {
772 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
773 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
774 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
776 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
777 addLegalFPImmediate(TmpFlt); // FLD0
779 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
782 APFloat TmpFlt2(+1.0);
783 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
785 addLegalFPImmediate(TmpFlt2); // FLD1
786 TmpFlt2.changeSign();
787 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
790 if (!TM.Options.UnsafeFPMath) {
791 setOperationAction(ISD::FSIN , MVT::f80, Expand);
792 setOperationAction(ISD::FCOS , MVT::f80, Expand);
793 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
796 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
797 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
798 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
799 setOperationAction(ISD::FRINT, MVT::f80, Expand);
800 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
801 setOperationAction(ISD::FMA, MVT::f80, Expand);
804 // Always use a library call for pow.
805 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
806 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
807 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
809 setOperationAction(ISD::FLOG, MVT::f80, Expand);
810 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
811 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
812 setOperationAction(ISD::FEXP, MVT::f80, Expand);
813 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
815 // First set operation action for all vector types to either promote
816 // (for widening) or expand (for scalarization). Then we will selectively
817 // turn on ones that can be effectively codegen'd.
818 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
819 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
820 MVT VT = (MVT::SimpleValueType)i;
821 setOperationAction(ISD::ADD , VT, Expand);
822 setOperationAction(ISD::SUB , VT, Expand);
823 setOperationAction(ISD::FADD, VT, Expand);
824 setOperationAction(ISD::FNEG, VT, Expand);
825 setOperationAction(ISD::FSUB, VT, Expand);
826 setOperationAction(ISD::MUL , VT, Expand);
827 setOperationAction(ISD::FMUL, VT, Expand);
828 setOperationAction(ISD::SDIV, VT, Expand);
829 setOperationAction(ISD::UDIV, VT, Expand);
830 setOperationAction(ISD::FDIV, VT, Expand);
831 setOperationAction(ISD::SREM, VT, Expand);
832 setOperationAction(ISD::UREM, VT, Expand);
833 setOperationAction(ISD::LOAD, VT, Expand);
834 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
835 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
836 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
837 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
838 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
839 setOperationAction(ISD::FABS, VT, Expand);
840 setOperationAction(ISD::FSIN, VT, Expand);
841 setOperationAction(ISD::FSINCOS, VT, Expand);
842 setOperationAction(ISD::FCOS, VT, Expand);
843 setOperationAction(ISD::FSINCOS, VT, Expand);
844 setOperationAction(ISD::FREM, VT, Expand);
845 setOperationAction(ISD::FMA, VT, Expand);
846 setOperationAction(ISD::FPOWI, VT, Expand);
847 setOperationAction(ISD::FSQRT, VT, Expand);
848 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
849 setOperationAction(ISD::FFLOOR, VT, Expand);
850 setOperationAction(ISD::FCEIL, VT, Expand);
851 setOperationAction(ISD::FTRUNC, VT, Expand);
852 setOperationAction(ISD::FRINT, VT, Expand);
853 setOperationAction(ISD::FNEARBYINT, VT, Expand);
854 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
855 setOperationAction(ISD::MULHS, VT, Expand);
856 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
857 setOperationAction(ISD::MULHU, VT, Expand);
858 setOperationAction(ISD::SDIVREM, VT, Expand);
859 setOperationAction(ISD::UDIVREM, VT, Expand);
860 setOperationAction(ISD::FPOW, VT, Expand);
861 setOperationAction(ISD::CTPOP, VT, Expand);
862 setOperationAction(ISD::CTTZ, VT, Expand);
863 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
864 setOperationAction(ISD::CTLZ, VT, Expand);
865 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
866 setOperationAction(ISD::SHL, VT, Expand);
867 setOperationAction(ISD::SRA, VT, Expand);
868 setOperationAction(ISD::SRL, VT, Expand);
869 setOperationAction(ISD::ROTL, VT, Expand);
870 setOperationAction(ISD::ROTR, VT, Expand);
871 setOperationAction(ISD::BSWAP, VT, Expand);
872 setOperationAction(ISD::SETCC, VT, Expand);
873 setOperationAction(ISD::FLOG, VT, Expand);
874 setOperationAction(ISD::FLOG2, VT, Expand);
875 setOperationAction(ISD::FLOG10, VT, Expand);
876 setOperationAction(ISD::FEXP, VT, Expand);
877 setOperationAction(ISD::FEXP2, VT, Expand);
878 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
879 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
880 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
881 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
882 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
883 setOperationAction(ISD::TRUNCATE, VT, Expand);
884 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
885 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
886 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
887 setOperationAction(ISD::VSELECT, VT, Expand);
888 setOperationAction(ISD::SELECT_CC, VT, Expand);
889 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
890 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
891 setTruncStoreAction(VT,
892 (MVT::SimpleValueType)InnerVT, Expand);
893 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
894 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
896 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like types,
897 // we have to deal with them whether we ask for Expansion or not. Setting
898 // Expand causes its own optimisation problems though, so leave them legal.
899 if (VT.getVectorElementType() == MVT::i1)
900 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
903 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
904 // with -msoft-float, disable use of MMX as well.
905 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
906 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
907 // No operations on x86mmx supported, everything uses intrinsics.
910 // MMX-sized vectors (other than x86mmx) are expected to be expanded
911 // into smaller operations.
912 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
913 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
914 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
915 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
916 setOperationAction(ISD::AND, MVT::v8i8, Expand);
917 setOperationAction(ISD::AND, MVT::v4i16, Expand);
918 setOperationAction(ISD::AND, MVT::v2i32, Expand);
919 setOperationAction(ISD::AND, MVT::v1i64, Expand);
920 setOperationAction(ISD::OR, MVT::v8i8, Expand);
921 setOperationAction(ISD::OR, MVT::v4i16, Expand);
922 setOperationAction(ISD::OR, MVT::v2i32, Expand);
923 setOperationAction(ISD::OR, MVT::v1i64, Expand);
924 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
925 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
926 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
927 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
928 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
929 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
930 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
931 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
932 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
933 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
934 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
935 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
936 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
937 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
938 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
939 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
940 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
942 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
943 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
945 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
946 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
947 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
948 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
949 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
950 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
951 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
952 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
953 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
954 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
955 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
956 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
959 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
960 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
962 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
963 // registers cannot be used even for integer operations.
964 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
965 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
966 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
967 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
969 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
970 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
971 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
972 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
973 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
974 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
975 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
976 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
977 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
978 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
979 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
980 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
981 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
982 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
983 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
984 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
985 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
986 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
987 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
988 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
989 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
990 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
992 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
993 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
994 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
995 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
997 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
998 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
999 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1000 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1001 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1003 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
1004 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1005 MVT VT = (MVT::SimpleValueType)i;
1006 // Do not attempt to custom lower non-power-of-2 vectors
1007 if (!isPowerOf2_32(VT.getVectorNumElements()))
1009 // Do not attempt to custom lower non-128-bit vectors
1010 if (!VT.is128BitVector())
1012 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1013 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1014 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1017 // We support custom legalizing of sext and anyext loads for specific
1018 // memory vector types which we can load as a scalar (or sequence of
1019 // scalars) and extend in-register to a legal 128-bit vector type. For sext
1020 // loads these must work with a single scalar load.
1021 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i8, Custom);
1022 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, Custom);
1023 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i8, Custom);
1024 setLoadExtAction(ISD::EXTLOAD, MVT::v2i8, Custom);
1025 setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, Custom);
1026 setLoadExtAction(ISD::EXTLOAD, MVT::v2i32, Custom);
1027 setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Custom);
1028 setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, Custom);
1029 setLoadExtAction(ISD::EXTLOAD, MVT::v8i8, Custom);
1031 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
1032 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
1033 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
1034 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
1035 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
1036 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
1038 if (Subtarget->is64Bit()) {
1039 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1040 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1043 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
1044 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1045 MVT VT = (MVT::SimpleValueType)i;
1047 // Do not attempt to promote non-128-bit vectors
1048 if (!VT.is128BitVector())
1051 setOperationAction(ISD::AND, VT, Promote);
1052 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
1053 setOperationAction(ISD::OR, VT, Promote);
1054 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
1055 setOperationAction(ISD::XOR, VT, Promote);
1056 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
1057 setOperationAction(ISD::LOAD, VT, Promote);
1058 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
1059 setOperationAction(ISD::SELECT, VT, Promote);
1060 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
1063 // Custom lower v2i64 and v2f64 selects.
1064 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1065 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
1066 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
1067 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1069 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1070 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1072 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1073 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1074 // As there is no 64-bit GPR available, we need build a special custom
1075 // sequence to convert from v2i32 to v2f32.
1076 if (!Subtarget->is64Bit())
1077 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
1079 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1080 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1082 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal);
1084 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
1085 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
1086 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
1089 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
1090 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1091 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1092 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1093 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1094 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1095 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1096 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1097 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1098 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1099 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1101 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1102 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1103 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1104 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1105 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1106 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1107 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1108 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1109 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1110 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1112 // FIXME: Do we need to handle scalar-to-vector here?
1113 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1115 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
1116 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
1117 setOperationAction(ISD::VSELECT, MVT::v4i32, Custom);
1118 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
1119 setOperationAction(ISD::VSELECT, MVT::v8i16, Custom);
1120 // There is no BLENDI for byte vectors. We don't need to custom lower
1121 // some vselects for now.
1122 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1124 // SSE41 brings specific instructions for doing vector sign extend even in
1125 // cases where we don't have SRA.
1126 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i8, Custom);
1127 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, Custom);
1128 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i32, Custom);
1130 // i8 and i16 vectors are custom because the source register and source
1131 // source memory operand types are not the same width. f32 vectors are
1132 // custom since the immediate controlling the insert encodes additional
1134 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1135 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1136 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1137 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1139 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1140 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1141 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1142 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1144 // FIXME: these should be Legal, but that's only for the case where
1145 // the index is constant. For now custom expand to deal with that.
1146 if (Subtarget->is64Bit()) {
1147 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1148 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1152 if (Subtarget->hasSSE2()) {
1153 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1154 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1156 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1157 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1159 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1160 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1162 // In the customized shift lowering, the legal cases in AVX2 will be
1164 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1165 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1167 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1168 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1170 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1173 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1174 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1175 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1176 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1177 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1178 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1179 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1181 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1182 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1183 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1185 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1186 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1187 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1188 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1189 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1190 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1191 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1192 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1193 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1194 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1195 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1196 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1198 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1199 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1200 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1201 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1202 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1203 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1204 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1205 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1206 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1207 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1208 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1209 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1211 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1212 // even though v8i16 is a legal type.
1213 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1214 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1215 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1217 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1218 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1219 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1221 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1222 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1224 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal);
1226 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1227 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1229 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1230 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1232 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1233 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1235 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1236 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1237 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1238 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1240 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1241 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1242 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1244 setOperationAction(ISD::VSELECT, MVT::v4f64, Custom);
1245 setOperationAction(ISD::VSELECT, MVT::v4i64, Custom);
1246 setOperationAction(ISD::VSELECT, MVT::v8i32, Custom);
1247 setOperationAction(ISD::VSELECT, MVT::v8f32, Custom);
1249 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1250 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1251 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1252 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1253 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1254 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1255 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1256 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1257 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1258 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1259 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1260 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1262 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1263 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1264 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1265 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1266 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1267 setOperationAction(ISD::FMA, MVT::f32, Legal);
1268 setOperationAction(ISD::FMA, MVT::f64, Legal);
1271 if (Subtarget->hasInt256()) {
1272 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1273 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1274 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1275 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1277 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1278 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1279 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1280 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1282 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1283 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1284 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1285 // Don't lower v32i8 because there is no 128-bit byte mul
1287 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1288 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1289 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1290 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1292 setOperationAction(ISD::VSELECT, MVT::v16i16, Custom);
1293 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1295 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1296 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1297 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1298 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1300 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1301 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1302 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1303 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1305 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1306 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1307 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1308 // Don't lower v32i8 because there is no 128-bit byte mul
1311 // In the customized shift lowering, the legal cases in AVX2 will be
1313 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1314 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1316 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1317 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1319 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1321 // Custom lower several nodes for 256-bit types.
1322 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1323 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1324 MVT VT = (MVT::SimpleValueType)i;
1326 // Extract subvector is special because the value type
1327 // (result) is 128-bit but the source is 256-bit wide.
1328 if (VT.is128BitVector())
1329 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1331 // Do not attempt to custom lower other non-256-bit vectors
1332 if (!VT.is256BitVector())
1335 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1336 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1337 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1338 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1339 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1340 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1341 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1344 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1345 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1346 MVT VT = (MVT::SimpleValueType)i;
1348 // Do not attempt to promote non-256-bit vectors
1349 if (!VT.is256BitVector())
1352 setOperationAction(ISD::AND, VT, Promote);
1353 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1354 setOperationAction(ISD::OR, VT, Promote);
1355 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1356 setOperationAction(ISD::XOR, VT, Promote);
1357 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1358 setOperationAction(ISD::LOAD, VT, Promote);
1359 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1360 setOperationAction(ISD::SELECT, VT, Promote);
1361 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1365 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) {
1366 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1367 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1368 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1369 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1371 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1372 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1373 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1375 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1376 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1377 setOperationAction(ISD::XOR, MVT::i1, Legal);
1378 setOperationAction(ISD::OR, MVT::i1, Legal);
1379 setOperationAction(ISD::AND, MVT::i1, Legal);
1380 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, Legal);
1381 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1382 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1383 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1384 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1385 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1387 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1388 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1389 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1390 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1391 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1392 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1394 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1395 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1396 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1397 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1398 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1399 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1400 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1401 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1403 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1404 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1405 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1406 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1407 if (Subtarget->is64Bit()) {
1408 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1409 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1410 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1411 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1413 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1414 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1415 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1416 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1417 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1418 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1419 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1420 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1421 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1422 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1424 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1425 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1426 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1427 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1428 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1429 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1430 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1431 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1432 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1433 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1434 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1435 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1436 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1438 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1439 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1440 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1441 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1442 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1443 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1445 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1446 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1448 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1450 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1451 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1452 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1453 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1454 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1455 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1456 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1457 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1458 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1460 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1461 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1463 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1464 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1466 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1468 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1469 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1471 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1472 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1474 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1475 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1477 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1478 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1479 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1480 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1481 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1482 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1484 if (Subtarget->hasCDI()) {
1485 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1486 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1489 // Custom lower several nodes.
1490 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1491 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1492 MVT VT = (MVT::SimpleValueType)i;
1494 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1495 // Extract subvector is special because the value type
1496 // (result) is 256/128-bit but the source is 512-bit wide.
1497 if (VT.is128BitVector() || VT.is256BitVector())
1498 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1500 if (VT.getVectorElementType() == MVT::i1)
1501 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1503 // Do not attempt to custom lower other non-512-bit vectors
1504 if (!VT.is512BitVector())
1507 if ( EltSize >= 32) {
1508 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1509 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1510 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1511 setOperationAction(ISD::VSELECT, VT, Legal);
1512 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1513 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1514 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1517 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1518 MVT VT = (MVT::SimpleValueType)i;
1520 // Do not attempt to promote non-256-bit vectors
1521 if (!VT.is512BitVector())
1524 setOperationAction(ISD::SELECT, VT, Promote);
1525 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1529 if (!TM.Options.UseSoftFloat && Subtarget->hasBWI()) {
1530 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1531 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1533 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1534 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1536 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1537 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1538 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1539 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1541 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1542 const MVT VT = (MVT::SimpleValueType)i;
1544 const unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1546 // Do not attempt to promote non-256-bit vectors
1547 if (!VT.is512BitVector())
1550 if ( EltSize < 32) {
1551 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1552 setOperationAction(ISD::VSELECT, VT, Legal);
1557 if (!TM.Options.UseSoftFloat && Subtarget->hasVLX()) {
1558 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1559 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1561 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1562 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1565 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1566 // of this type with custom code.
1567 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1568 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1569 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1573 // We want to custom lower some of our intrinsics.
1574 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1575 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1576 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1577 if (!Subtarget->is64Bit())
1578 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1580 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1581 // handle type legalization for these operations here.
1583 // FIXME: We really should do custom legalization for addition and
1584 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1585 // than generic legalization for 64-bit multiplication-with-overflow, though.
1586 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1587 // Add/Sub/Mul with overflow operations are custom lowered.
1589 setOperationAction(ISD::SADDO, VT, Custom);
1590 setOperationAction(ISD::UADDO, VT, Custom);
1591 setOperationAction(ISD::SSUBO, VT, Custom);
1592 setOperationAction(ISD::USUBO, VT, Custom);
1593 setOperationAction(ISD::SMULO, VT, Custom);
1594 setOperationAction(ISD::UMULO, VT, Custom);
1597 // There are no 8-bit 3-address imul/mul instructions
1598 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1599 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1601 if (!Subtarget->is64Bit()) {
1602 // These libcalls are not available in 32-bit.
1603 setLibcallName(RTLIB::SHL_I128, nullptr);
1604 setLibcallName(RTLIB::SRL_I128, nullptr);
1605 setLibcallName(RTLIB::SRA_I128, nullptr);
1608 // Combine sin / cos into one node or libcall if possible.
1609 if (Subtarget->hasSinCos()) {
1610 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1611 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1612 if (Subtarget->isTargetDarwin()) {
1613 // For MacOSX, we don't want to the normal expansion of a libcall to
1614 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
1616 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1617 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1621 if (Subtarget->isTargetWin64()) {
1622 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1623 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1624 setOperationAction(ISD::SREM, MVT::i128, Custom);
1625 setOperationAction(ISD::UREM, MVT::i128, Custom);
1626 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1627 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1630 // We have target-specific dag combine patterns for the following nodes:
1631 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1632 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1633 setTargetDAGCombine(ISD::VSELECT);
1634 setTargetDAGCombine(ISD::SELECT);
1635 setTargetDAGCombine(ISD::SHL);
1636 setTargetDAGCombine(ISD::SRA);
1637 setTargetDAGCombine(ISD::SRL);
1638 setTargetDAGCombine(ISD::OR);
1639 setTargetDAGCombine(ISD::AND);
1640 setTargetDAGCombine(ISD::ADD);
1641 setTargetDAGCombine(ISD::FADD);
1642 setTargetDAGCombine(ISD::FSUB);
1643 setTargetDAGCombine(ISD::FMA);
1644 setTargetDAGCombine(ISD::SUB);
1645 setTargetDAGCombine(ISD::LOAD);
1646 setTargetDAGCombine(ISD::STORE);
1647 setTargetDAGCombine(ISD::ZERO_EXTEND);
1648 setTargetDAGCombine(ISD::ANY_EXTEND);
1649 setTargetDAGCombine(ISD::SIGN_EXTEND);
1650 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1651 setTargetDAGCombine(ISD::TRUNCATE);
1652 setTargetDAGCombine(ISD::SINT_TO_FP);
1653 setTargetDAGCombine(ISD::SETCC);
1654 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1655 setTargetDAGCombine(ISD::BUILD_VECTOR);
1656 if (Subtarget->is64Bit())
1657 setTargetDAGCombine(ISD::MUL);
1658 setTargetDAGCombine(ISD::XOR);
1660 computeRegisterProperties();
1662 // On Darwin, -Os means optimize for size without hurting performance,
1663 // do not reduce the limit.
1664 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1665 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1666 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1667 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1668 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1669 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1670 setPrefLoopAlignment(4); // 2^4 bytes.
1672 // Predictable cmov don't hurt on atom because it's in-order.
1673 PredictableSelectIsExpensive = !Subtarget->isAtom();
1675 setPrefFunctionAlignment(4); // 2^4 bytes.
1677 verifyIntrinsicTables();
1680 // This has so far only been implemented for 64-bit MachO.
1681 bool X86TargetLowering::useLoadStackGuardNode() const {
1682 return Subtarget->getTargetTriple().getObjectFormat() == Triple::MachO &&
1683 Subtarget->is64Bit();
1686 TargetLoweringBase::LegalizeTypeAction
1687 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1688 if (ExperimentalVectorWideningLegalization &&
1689 VT.getVectorNumElements() != 1 &&
1690 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1691 return TypeWidenVector;
1693 return TargetLoweringBase::getPreferredVectorAction(VT);
1696 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1698 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1700 const unsigned NumElts = VT.getVectorNumElements();
1701 const EVT EltVT = VT.getVectorElementType();
1702 if (VT.is512BitVector()) {
1703 if (Subtarget->hasAVX512())
1704 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1705 EltVT == MVT::f32 || EltVT == MVT::f64)
1707 case 8: return MVT::v8i1;
1708 case 16: return MVT::v16i1;
1710 if (Subtarget->hasBWI())
1711 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1713 case 32: return MVT::v32i1;
1714 case 64: return MVT::v64i1;
1718 if (VT.is256BitVector() || VT.is128BitVector()) {
1719 if (Subtarget->hasVLX())
1720 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1721 EltVT == MVT::f32 || EltVT == MVT::f64)
1723 case 2: return MVT::v2i1;
1724 case 4: return MVT::v4i1;
1725 case 8: return MVT::v8i1;
1727 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1728 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1730 case 8: return MVT::v8i1;
1731 case 16: return MVT::v16i1;
1732 case 32: return MVT::v32i1;
1736 return VT.changeVectorElementTypeToInteger();
1739 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1740 /// the desired ByVal argument alignment.
1741 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1744 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1745 if (VTy->getBitWidth() == 128)
1747 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1748 unsigned EltAlign = 0;
1749 getMaxByValAlign(ATy->getElementType(), EltAlign);
1750 if (EltAlign > MaxAlign)
1751 MaxAlign = EltAlign;
1752 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1753 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1754 unsigned EltAlign = 0;
1755 getMaxByValAlign(STy->getElementType(i), EltAlign);
1756 if (EltAlign > MaxAlign)
1757 MaxAlign = EltAlign;
1764 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1765 /// function arguments in the caller parameter area. For X86, aggregates
1766 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1767 /// are at 4-byte boundaries.
1768 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1769 if (Subtarget->is64Bit()) {
1770 // Max of 8 and alignment of type.
1771 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1778 if (Subtarget->hasSSE1())
1779 getMaxByValAlign(Ty, Align);
1783 /// getOptimalMemOpType - Returns the target specific optimal type for load
1784 /// and store operations as a result of memset, memcpy, and memmove
1785 /// lowering. If DstAlign is zero that means it's safe to destination
1786 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1787 /// means there isn't a need to check it against alignment requirement,
1788 /// probably because the source does not need to be loaded. If 'IsMemset' is
1789 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1790 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1791 /// source is constant so it does not need to be loaded.
1792 /// It returns EVT::Other if the type should be determined using generic
1793 /// target-independent logic.
1795 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1796 unsigned DstAlign, unsigned SrcAlign,
1797 bool IsMemset, bool ZeroMemset,
1799 MachineFunction &MF) const {
1800 const Function *F = MF.getFunction();
1801 if ((!IsMemset || ZeroMemset) &&
1802 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1803 Attribute::NoImplicitFloat)) {
1805 (Subtarget->isUnalignedMemAccessFast() ||
1806 ((DstAlign == 0 || DstAlign >= 16) &&
1807 (SrcAlign == 0 || SrcAlign >= 16)))) {
1809 if (Subtarget->hasInt256())
1811 if (Subtarget->hasFp256())
1814 if (Subtarget->hasSSE2())
1816 if (Subtarget->hasSSE1())
1818 } else if (!MemcpyStrSrc && Size >= 8 &&
1819 !Subtarget->is64Bit() &&
1820 Subtarget->hasSSE2()) {
1821 // Do not use f64 to lower memcpy if source is string constant. It's
1822 // better to use i32 to avoid the loads.
1826 if (Subtarget->is64Bit() && Size >= 8)
1831 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1833 return X86ScalarSSEf32;
1834 else if (VT == MVT::f64)
1835 return X86ScalarSSEf64;
1840 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1845 *Fast = Subtarget->isUnalignedMemAccessFast();
1849 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1850 /// current function. The returned value is a member of the
1851 /// MachineJumpTableInfo::JTEntryKind enum.
1852 unsigned X86TargetLowering::getJumpTableEncoding() const {
1853 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1855 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1856 Subtarget->isPICStyleGOT())
1857 return MachineJumpTableInfo::EK_Custom32;
1859 // Otherwise, use the normal jump table encoding heuristics.
1860 return TargetLowering::getJumpTableEncoding();
1864 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1865 const MachineBasicBlock *MBB,
1866 unsigned uid,MCContext &Ctx) const{
1867 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
1868 Subtarget->isPICStyleGOT());
1869 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1871 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1872 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1875 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1877 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1878 SelectionDAG &DAG) const {
1879 if (!Subtarget->is64Bit())
1880 // This doesn't have SDLoc associated with it, but is not really the
1881 // same as a Register.
1882 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1886 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1887 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1889 const MCExpr *X86TargetLowering::
1890 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1891 MCContext &Ctx) const {
1892 // X86-64 uses RIP relative addressing based on the jump table label.
1893 if (Subtarget->isPICStyleRIPRel())
1894 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1896 // Otherwise, the reference is relative to the PIC base.
1897 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1900 // FIXME: Why this routine is here? Move to RegInfo!
1901 std::pair<const TargetRegisterClass*, uint8_t>
1902 X86TargetLowering::findRepresentativeClass(MVT VT) const{
1903 const TargetRegisterClass *RRC = nullptr;
1905 switch (VT.SimpleTy) {
1907 return TargetLowering::findRepresentativeClass(VT);
1908 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1909 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
1912 RRC = &X86::VR64RegClass;
1914 case MVT::f32: case MVT::f64:
1915 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1916 case MVT::v4f32: case MVT::v2f64:
1917 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1919 RRC = &X86::VR128RegClass;
1922 return std::make_pair(RRC, Cost);
1925 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1926 unsigned &Offset) const {
1927 if (!Subtarget->isTargetLinux())
1930 if (Subtarget->is64Bit()) {
1931 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1933 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1945 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1946 unsigned DestAS) const {
1947 assert(SrcAS != DestAS && "Expected different address spaces!");
1949 return SrcAS < 256 && DestAS < 256;
1952 //===----------------------------------------------------------------------===//
1953 // Return Value Calling Convention Implementation
1954 //===----------------------------------------------------------------------===//
1956 #include "X86GenCallingConv.inc"
1959 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1960 MachineFunction &MF, bool isVarArg,
1961 const SmallVectorImpl<ISD::OutputArg> &Outs,
1962 LLVMContext &Context) const {
1963 SmallVector<CCValAssign, 16> RVLocs;
1964 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1965 return CCInfo.CheckReturn(Outs, RetCC_X86);
1968 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
1969 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
1974 X86TargetLowering::LowerReturn(SDValue Chain,
1975 CallingConv::ID CallConv, bool isVarArg,
1976 const SmallVectorImpl<ISD::OutputArg> &Outs,
1977 const SmallVectorImpl<SDValue> &OutVals,
1978 SDLoc dl, SelectionDAG &DAG) const {
1979 MachineFunction &MF = DAG.getMachineFunction();
1980 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1982 SmallVector<CCValAssign, 16> RVLocs;
1983 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
1984 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1987 SmallVector<SDValue, 6> RetOps;
1988 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1989 // Operand #1 = Bytes To Pop
1990 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1993 // Copy the result values into the output registers.
1994 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1995 CCValAssign &VA = RVLocs[i];
1996 assert(VA.isRegLoc() && "Can only return in registers!");
1997 SDValue ValToCopy = OutVals[i];
1998 EVT ValVT = ValToCopy.getValueType();
2000 // Promote values to the appropriate types
2001 if (VA.getLocInfo() == CCValAssign::SExt)
2002 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2003 else if (VA.getLocInfo() == CCValAssign::ZExt)
2004 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2005 else if (VA.getLocInfo() == CCValAssign::AExt)
2006 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2007 else if (VA.getLocInfo() == CCValAssign::BCvt)
2008 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
2010 assert(VA.getLocInfo() != CCValAssign::FPExt &&
2011 "Unexpected FP-extend for return value.");
2013 // If this is x86-64, and we disabled SSE, we can't return FP values,
2014 // or SSE or MMX vectors.
2015 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
2016 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2017 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
2018 report_fatal_error("SSE register return with SSE disabled");
2020 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
2021 // llvm-gcc has never done it right and no one has noticed, so this
2022 // should be OK for now.
2023 if (ValVT == MVT::f64 &&
2024 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
2025 report_fatal_error("SSE2 register return with SSE2 disabled");
2027 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2028 // the RET instruction and handled by the FP Stackifier.
2029 if (VA.getLocReg() == X86::FP0 ||
2030 VA.getLocReg() == X86::FP1) {
2031 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2032 // change the value to the FP stack register class.
2033 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2034 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2035 RetOps.push_back(ValToCopy);
2036 // Don't emit a copytoreg.
2040 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2041 // which is returned in RAX / RDX.
2042 if (Subtarget->is64Bit()) {
2043 if (ValVT == MVT::x86mmx) {
2044 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2045 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
2046 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2048 // If we don't have SSE2 available, convert to v4f32 so the generated
2049 // register is legal.
2050 if (!Subtarget->hasSSE2())
2051 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
2056 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2057 Flag = Chain.getValue(1);
2058 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2061 // The x86-64 ABIs require that for returning structs by value we copy
2062 // the sret argument into %rax/%eax (depending on ABI) for the return.
2063 // Win32 requires us to put the sret argument to %eax as well.
2064 // We saved the argument into a virtual register in the entry block,
2065 // so now we copy the value out and into %rax/%eax.
2066 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr() &&
2067 (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC())) {
2068 MachineFunction &MF = DAG.getMachineFunction();
2069 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2070 unsigned Reg = FuncInfo->getSRetReturnReg();
2072 "SRetReturnReg should have been set in LowerFormalArguments().");
2073 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
2076 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2077 X86::RAX : X86::EAX;
2078 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2079 Flag = Chain.getValue(1);
2081 // RAX/EAX now acts like a return value.
2082 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
2085 RetOps[0] = Chain; // Update chain.
2087 // Add the flag if we have it.
2089 RetOps.push_back(Flag);
2091 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2094 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2095 if (N->getNumValues() != 1)
2097 if (!N->hasNUsesOfValue(1, 0))
2100 SDValue TCChain = Chain;
2101 SDNode *Copy = *N->use_begin();
2102 if (Copy->getOpcode() == ISD::CopyToReg) {
2103 // If the copy has a glue operand, we conservatively assume it isn't safe to
2104 // perform a tail call.
2105 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2107 TCChain = Copy->getOperand(0);
2108 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2111 bool HasRet = false;
2112 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2114 if (UI->getOpcode() != X86ISD::RET_FLAG)
2116 // If we are returning more than one value, we can definitely
2117 // not make a tail call see PR19530
2118 if (UI->getNumOperands() > 4)
2120 if (UI->getNumOperands() == 4 &&
2121 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2134 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2135 ISD::NodeType ExtendKind) const {
2137 // TODO: Is this also valid on 32-bit?
2138 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2139 ReturnMVT = MVT::i8;
2141 ReturnMVT = MVT::i32;
2143 EVT MinVT = getRegisterType(Context, ReturnMVT);
2144 return VT.bitsLT(MinVT) ? MinVT : VT;
2147 /// LowerCallResult - Lower the result values of a call into the
2148 /// appropriate copies out of appropriate physical registers.
2151 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2152 CallingConv::ID CallConv, bool isVarArg,
2153 const SmallVectorImpl<ISD::InputArg> &Ins,
2154 SDLoc dl, SelectionDAG &DAG,
2155 SmallVectorImpl<SDValue> &InVals) const {
2157 // Assign locations to each value returned by this call.
2158 SmallVector<CCValAssign, 16> RVLocs;
2159 bool Is64Bit = Subtarget->is64Bit();
2160 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2162 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2164 // Copy all of the result registers out of their specified physreg.
2165 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2166 CCValAssign &VA = RVLocs[i];
2167 EVT CopyVT = VA.getValVT();
2169 // If this is x86-64, and we disabled SSE, we can't return FP values
2170 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2171 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2172 report_fatal_error("SSE register return with SSE disabled");
2175 // If we prefer to use the value in xmm registers, copy it out as f80 and
2176 // use a truncate to move it from fp stack reg to xmm reg.
2177 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2178 isScalarFPTypeInSSEReg(VA.getValVT()))
2181 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2182 CopyVT, InFlag).getValue(1);
2183 SDValue Val = Chain.getValue(0);
2185 if (CopyVT != VA.getValVT())
2186 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2187 // This truncation won't change the value.
2188 DAG.getIntPtrConstant(1));
2190 InFlag = Chain.getValue(2);
2191 InVals.push_back(Val);
2197 //===----------------------------------------------------------------------===//
2198 // C & StdCall & Fast Calling Convention implementation
2199 //===----------------------------------------------------------------------===//
2200 // StdCall calling convention seems to be standard for many Windows' API
2201 // routines and around. It differs from C calling convention just a little:
2202 // callee should clean up the stack, not caller. Symbols should be also
2203 // decorated in some fancy way :) It doesn't support any vector arguments.
2204 // For info on fast calling convention see Fast Calling Convention (tail call)
2205 // implementation LowerX86_32FastCCCallTo.
2207 /// CallIsStructReturn - Determines whether a call uses struct return
2209 enum StructReturnType {
2214 static StructReturnType
2215 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2217 return NotStructReturn;
2219 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2220 if (!Flags.isSRet())
2221 return NotStructReturn;
2222 if (Flags.isInReg())
2223 return RegStructReturn;
2224 return StackStructReturn;
2227 /// ArgsAreStructReturn - Determines whether a function uses struct
2228 /// return semantics.
2229 static StructReturnType
2230 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2232 return NotStructReturn;
2234 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2235 if (!Flags.isSRet())
2236 return NotStructReturn;
2237 if (Flags.isInReg())
2238 return RegStructReturn;
2239 return StackStructReturn;
2242 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2243 /// by "Src" to address "Dst" with size and alignment information specified by
2244 /// the specific parameter attribute. The copy will be passed as a byval
2245 /// function parameter.
2247 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2248 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2250 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2252 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2253 /*isVolatile*/false, /*AlwaysInline=*/true,
2254 MachinePointerInfo(), MachinePointerInfo());
2257 /// IsTailCallConvention - Return true if the calling convention is one that
2258 /// supports tail call optimization.
2259 static bool IsTailCallConvention(CallingConv::ID CC) {
2260 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2261 CC == CallingConv::HiPE);
2264 /// \brief Return true if the calling convention is a C calling convention.
2265 static bool IsCCallConvention(CallingConv::ID CC) {
2266 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2267 CC == CallingConv::X86_64_SysV);
2270 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2271 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2275 CallingConv::ID CalleeCC = CS.getCallingConv();
2276 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2282 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
2283 /// a tailcall target by changing its ABI.
2284 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2285 bool GuaranteedTailCallOpt) {
2286 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2290 X86TargetLowering::LowerMemArgument(SDValue Chain,
2291 CallingConv::ID CallConv,
2292 const SmallVectorImpl<ISD::InputArg> &Ins,
2293 SDLoc dl, SelectionDAG &DAG,
2294 const CCValAssign &VA,
2295 MachineFrameInfo *MFI,
2297 // Create the nodes corresponding to a load from this parameter slot.
2298 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2299 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2300 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2301 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2304 // If value is passed by pointer we have address passed instead of the value
2306 if (VA.getLocInfo() == CCValAssign::Indirect)
2307 ValVT = VA.getLocVT();
2309 ValVT = VA.getValVT();
2311 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2312 // changed with more analysis.
2313 // In case of tail call optimization mark all arguments mutable. Since they
2314 // could be overwritten by lowering of arguments in case of a tail call.
2315 if (Flags.isByVal()) {
2316 unsigned Bytes = Flags.getByValSize();
2317 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2318 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2319 return DAG.getFrameIndex(FI, getPointerTy());
2321 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2322 VA.getLocMemOffset(), isImmutable);
2323 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2324 return DAG.getLoad(ValVT, dl, Chain, FIN,
2325 MachinePointerInfo::getFixedStack(FI),
2326 false, false, false, 0);
2330 // FIXME: Get this from tablegen.
2331 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2332 const X86Subtarget *Subtarget) {
2333 assert(Subtarget->is64Bit());
2335 if (Subtarget->isCallingConvWin64(CallConv)) {
2336 static const MCPhysReg GPR64ArgRegsWin64[] = {
2337 X86::RCX, X86::RDX, X86::R8, X86::R9
2339 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2342 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2343 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2345 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2348 // FIXME: Get this from tablegen.
2349 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2350 CallingConv::ID CallConv,
2351 const X86Subtarget *Subtarget) {
2352 assert(Subtarget->is64Bit());
2353 if (Subtarget->isCallingConvWin64(CallConv)) {
2354 // The XMM registers which might contain var arg parameters are shadowed
2355 // in their paired GPR. So we only need to save the GPR to their home
2357 // TODO: __vectorcall will change this.
2361 const Function *Fn = MF.getFunction();
2362 bool NoImplicitFloatOps = Fn->getAttributes().
2363 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2364 assert(!(MF.getTarget().Options.UseSoftFloat && NoImplicitFloatOps) &&
2365 "SSE register cannot be used when SSE is disabled!");
2366 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2367 !Subtarget->hasSSE1())
2368 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2372 static const MCPhysReg XMMArgRegs64Bit[] = {
2373 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2374 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2376 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2380 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2381 CallingConv::ID CallConv,
2383 const SmallVectorImpl<ISD::InputArg> &Ins,
2386 SmallVectorImpl<SDValue> &InVals)
2388 MachineFunction &MF = DAG.getMachineFunction();
2389 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2391 const Function* Fn = MF.getFunction();
2392 if (Fn->hasExternalLinkage() &&
2393 Subtarget->isTargetCygMing() &&
2394 Fn->getName() == "main")
2395 FuncInfo->setForceFramePointer(true);
2397 MachineFrameInfo *MFI = MF.getFrameInfo();
2398 bool Is64Bit = Subtarget->is64Bit();
2399 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2401 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2402 "Var args not supported with calling convention fastcc, ghc or hipe");
2404 // Assign locations to all of the incoming arguments.
2405 SmallVector<CCValAssign, 16> ArgLocs;
2406 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2408 // Allocate shadow area for Win64
2410 CCInfo.AllocateStack(32, 8);
2412 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2414 unsigned LastVal = ~0U;
2416 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2417 CCValAssign &VA = ArgLocs[i];
2418 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2420 assert(VA.getValNo() != LastVal &&
2421 "Don't support value assigned to multiple locs yet");
2423 LastVal = VA.getValNo();
2425 if (VA.isRegLoc()) {
2426 EVT RegVT = VA.getLocVT();
2427 const TargetRegisterClass *RC;
2428 if (RegVT == MVT::i32)
2429 RC = &X86::GR32RegClass;
2430 else if (Is64Bit && RegVT == MVT::i64)
2431 RC = &X86::GR64RegClass;
2432 else if (RegVT == MVT::f32)
2433 RC = &X86::FR32RegClass;
2434 else if (RegVT == MVT::f64)
2435 RC = &X86::FR64RegClass;
2436 else if (RegVT.is512BitVector())
2437 RC = &X86::VR512RegClass;
2438 else if (RegVT.is256BitVector())
2439 RC = &X86::VR256RegClass;
2440 else if (RegVT.is128BitVector())
2441 RC = &X86::VR128RegClass;
2442 else if (RegVT == MVT::x86mmx)
2443 RC = &X86::VR64RegClass;
2444 else if (RegVT == MVT::i1)
2445 RC = &X86::VK1RegClass;
2446 else if (RegVT == MVT::v8i1)
2447 RC = &X86::VK8RegClass;
2448 else if (RegVT == MVT::v16i1)
2449 RC = &X86::VK16RegClass;
2450 else if (RegVT == MVT::v32i1)
2451 RC = &X86::VK32RegClass;
2452 else if (RegVT == MVT::v64i1)
2453 RC = &X86::VK64RegClass;
2455 llvm_unreachable("Unknown argument type!");
2457 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2458 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2460 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2461 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2463 if (VA.getLocInfo() == CCValAssign::SExt)
2464 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2465 DAG.getValueType(VA.getValVT()));
2466 else if (VA.getLocInfo() == CCValAssign::ZExt)
2467 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2468 DAG.getValueType(VA.getValVT()));
2469 else if (VA.getLocInfo() == CCValAssign::BCvt)
2470 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2472 if (VA.isExtInLoc()) {
2473 // Handle MMX values passed in XMM regs.
2474 if (RegVT.isVector())
2475 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2477 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2480 assert(VA.isMemLoc());
2481 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2484 // If value is passed via pointer - do a load.
2485 if (VA.getLocInfo() == CCValAssign::Indirect)
2486 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2487 MachinePointerInfo(), false, false, false, 0);
2489 InVals.push_back(ArgValue);
2492 if (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC()) {
2493 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2494 // The x86-64 ABIs require that for returning structs by value we copy
2495 // the sret argument into %rax/%eax (depending on ABI) for the return.
2496 // Win32 requires us to put the sret argument to %eax as well.
2497 // Save the argument into a virtual register so that we can access it
2498 // from the return points.
2499 if (Ins[i].Flags.isSRet()) {
2500 unsigned Reg = FuncInfo->getSRetReturnReg();
2502 MVT PtrTy = getPointerTy();
2503 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2504 FuncInfo->setSRetReturnReg(Reg);
2506 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2507 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2513 unsigned StackSize = CCInfo.getNextStackOffset();
2514 // Align stack specially for tail calls.
2515 if (FuncIsMadeTailCallSafe(CallConv,
2516 MF.getTarget().Options.GuaranteedTailCallOpt))
2517 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2519 // If the function takes variable number of arguments, make a frame index for
2520 // the start of the first vararg value... for expansion of llvm.va_start. We
2521 // can skip this if there are no va_start calls.
2522 if (MFI->hasVAStart() &&
2523 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2524 CallConv != CallingConv::X86_ThisCall))) {
2525 FuncInfo->setVarArgsFrameIndex(
2526 MFI->CreateFixedObject(1, StackSize, true));
2529 // 64-bit calling conventions support varargs and register parameters, so we
2530 // have to do extra work to spill them in the prologue or forward them to
2532 if (Is64Bit && isVarArg &&
2533 (MFI->hasVAStart() || MFI->hasMustTailInVarArgFunc())) {
2534 // Find the first unallocated argument registers.
2535 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2536 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2537 unsigned NumIntRegs =
2538 CCInfo.getFirstUnallocated(ArgGPRs.data(), ArgGPRs.size());
2539 unsigned NumXMMRegs =
2540 CCInfo.getFirstUnallocated(ArgXMMs.data(), ArgXMMs.size());
2541 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2542 "SSE register cannot be used when SSE is disabled!");
2544 // Gather all the live in physical registers.
2545 SmallVector<SDValue, 6> LiveGPRs;
2546 SmallVector<SDValue, 8> LiveXMMRegs;
2548 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2549 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2551 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2553 if (!ArgXMMs.empty()) {
2554 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2555 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2556 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2557 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2558 LiveXMMRegs.push_back(
2559 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2563 // Store them to the va_list returned by va_start.
2564 if (MFI->hasVAStart()) {
2566 const TargetFrameLowering &TFI = *MF.getSubtarget().getFrameLowering();
2567 // Get to the caller-allocated home save location. Add 8 to account
2568 // for the return address.
2569 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2570 FuncInfo->setRegSaveFrameIndex(
2571 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2572 // Fixup to set vararg frame on shadow area (4 x i64).
2574 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2576 // For X86-64, if there are vararg parameters that are passed via
2577 // registers, then we must store them to their spots on the stack so
2578 // they may be loaded by deferencing the result of va_next.
2579 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2580 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2581 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2582 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2585 // Store the integer parameter registers.
2586 SmallVector<SDValue, 8> MemOps;
2587 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2589 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2590 for (SDValue Val : LiveGPRs) {
2591 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2592 DAG.getIntPtrConstant(Offset));
2594 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2595 MachinePointerInfo::getFixedStack(
2596 FuncInfo->getRegSaveFrameIndex(), Offset),
2598 MemOps.push_back(Store);
2602 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2603 // Now store the XMM (fp + vector) parameter registers.
2604 SmallVector<SDValue, 12> SaveXMMOps;
2605 SaveXMMOps.push_back(Chain);
2606 SaveXMMOps.push_back(ALVal);
2607 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2608 FuncInfo->getRegSaveFrameIndex()));
2609 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2610 FuncInfo->getVarArgsFPOffset()));
2611 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2613 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2614 MVT::Other, SaveXMMOps));
2617 if (!MemOps.empty())
2618 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2620 // Add all GPRs, al, and XMMs to the list of forwards. We will add then
2621 // to the liveout set on a musttail call.
2622 assert(MFI->hasMustTailInVarArgFunc());
2623 auto &Forwards = FuncInfo->getForwardedMustTailRegParms();
2624 typedef X86MachineFunctionInfo::Forward Forward;
2626 for (unsigned I = 0, E = LiveGPRs.size(); I != E; ++I) {
2628 MF.getRegInfo().createVirtualRegister(&X86::GR64RegClass);
2629 Chain = DAG.getCopyToReg(Chain, dl, VReg, LiveGPRs[I]);
2630 Forwards.push_back(Forward(VReg, ArgGPRs[NumIntRegs + I], MVT::i64));
2633 if (!ArgXMMs.empty()) {
2635 MF.getRegInfo().createVirtualRegister(&X86::GR8RegClass);
2636 Chain = DAG.getCopyToReg(Chain, dl, ALVReg, ALVal);
2637 Forwards.push_back(Forward(ALVReg, X86::AL, MVT::i8));
2639 for (unsigned I = 0, E = LiveXMMRegs.size(); I != E; ++I) {
2641 MF.getRegInfo().createVirtualRegister(&X86::VR128RegClass);
2642 Chain = DAG.getCopyToReg(Chain, dl, VReg, LiveXMMRegs[I]);
2644 Forward(VReg, ArgXMMs[NumXMMRegs + I], MVT::v4f32));
2650 // Some CCs need callee pop.
2651 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2652 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2653 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2655 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2656 // If this is an sret function, the return should pop the hidden pointer.
2657 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2658 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2659 argsAreStructReturn(Ins) == StackStructReturn)
2660 FuncInfo->setBytesToPopOnReturn(4);
2664 // RegSaveFrameIndex is X86-64 only.
2665 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2666 if (CallConv == CallingConv::X86_FastCall ||
2667 CallConv == CallingConv::X86_ThisCall)
2668 // fastcc functions can't have varargs.
2669 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2672 FuncInfo->setArgumentStackSize(StackSize);
2678 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2679 SDValue StackPtr, SDValue Arg,
2680 SDLoc dl, SelectionDAG &DAG,
2681 const CCValAssign &VA,
2682 ISD::ArgFlagsTy Flags) const {
2683 unsigned LocMemOffset = VA.getLocMemOffset();
2684 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2685 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2686 if (Flags.isByVal())
2687 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2689 return DAG.getStore(Chain, dl, Arg, PtrOff,
2690 MachinePointerInfo::getStack(LocMemOffset),
2694 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2695 /// optimization is performed and it is required.
2697 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2698 SDValue &OutRetAddr, SDValue Chain,
2699 bool IsTailCall, bool Is64Bit,
2700 int FPDiff, SDLoc dl) const {
2701 // Adjust the Return address stack slot.
2702 EVT VT = getPointerTy();
2703 OutRetAddr = getReturnAddressFrameIndex(DAG);
2705 // Load the "old" Return address.
2706 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2707 false, false, false, 0);
2708 return SDValue(OutRetAddr.getNode(), 1);
2711 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2712 /// optimization is performed and it is required (FPDiff!=0).
2713 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2714 SDValue Chain, SDValue RetAddrFrIdx,
2715 EVT PtrVT, unsigned SlotSize,
2716 int FPDiff, SDLoc dl) {
2717 // Store the return address to the appropriate stack slot.
2718 if (!FPDiff) return Chain;
2719 // Calculate the new stack slot for the return address.
2720 int NewReturnAddrFI =
2721 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2723 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2724 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2725 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2731 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2732 SmallVectorImpl<SDValue> &InVals) const {
2733 SelectionDAG &DAG = CLI.DAG;
2735 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2736 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2737 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2738 SDValue Chain = CLI.Chain;
2739 SDValue Callee = CLI.Callee;
2740 CallingConv::ID CallConv = CLI.CallConv;
2741 bool &isTailCall = CLI.IsTailCall;
2742 bool isVarArg = CLI.IsVarArg;
2744 MachineFunction &MF = DAG.getMachineFunction();
2745 bool Is64Bit = Subtarget->is64Bit();
2746 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2747 StructReturnType SR = callIsStructReturn(Outs);
2748 bool IsSibcall = false;
2749 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2751 if (MF.getTarget().Options.DisableTailCalls)
2754 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2756 // Force this to be a tail call. The verifier rules are enough to ensure
2757 // that we can lower this successfully without moving the return address
2760 } else if (isTailCall) {
2761 // Check if it's really possible to do a tail call.
2762 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2763 isVarArg, SR != NotStructReturn,
2764 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2765 Outs, OutVals, Ins, DAG);
2767 // Sibcalls are automatically detected tailcalls which do not require
2769 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2776 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2777 "Var args not supported with calling convention fastcc, ghc or hipe");
2779 // Analyze operands of the call, assigning locations to each operand.
2780 SmallVector<CCValAssign, 16> ArgLocs;
2781 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2783 // Allocate shadow area for Win64
2785 CCInfo.AllocateStack(32, 8);
2787 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2789 // Get a count of how many bytes are to be pushed on the stack.
2790 unsigned NumBytes = CCInfo.getNextStackOffset();
2792 // This is a sibcall. The memory operands are available in caller's
2793 // own caller's stack.
2795 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
2796 IsTailCallConvention(CallConv))
2797 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2800 if (isTailCall && !IsSibcall && !IsMustTail) {
2801 // Lower arguments at fp - stackoffset + fpdiff.
2802 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2804 FPDiff = NumBytesCallerPushed - NumBytes;
2806 // Set the delta of movement of the returnaddr stackslot.
2807 // But only set if delta is greater than previous delta.
2808 if (FPDiff < X86Info->getTCReturnAddrDelta())
2809 X86Info->setTCReturnAddrDelta(FPDiff);
2812 unsigned NumBytesToPush = NumBytes;
2813 unsigned NumBytesToPop = NumBytes;
2815 // If we have an inalloca argument, all stack space has already been allocated
2816 // for us and be right at the top of the stack. We don't support multiple
2817 // arguments passed in memory when using inalloca.
2818 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
2820 if (!ArgLocs.back().isMemLoc())
2821 report_fatal_error("cannot use inalloca attribute on a register "
2823 if (ArgLocs.back().getLocMemOffset() != 0)
2824 report_fatal_error("any parameter with the inalloca attribute must be "
2825 "the only memory argument");
2829 Chain = DAG.getCALLSEQ_START(
2830 Chain, DAG.getIntPtrConstant(NumBytesToPush, true), dl);
2832 SDValue RetAddrFrIdx;
2833 // Load return address for tail calls.
2834 if (isTailCall && FPDiff)
2835 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2836 Is64Bit, FPDiff, dl);
2838 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2839 SmallVector<SDValue, 8> MemOpChains;
2842 // Walk the register/memloc assignments, inserting copies/loads. In the case
2843 // of tail call optimization arguments are handle later.
2844 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
2845 DAG.getSubtarget().getRegisterInfo());
2846 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2847 // Skip inalloca arguments, they have already been written.
2848 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2849 if (Flags.isInAlloca())
2852 CCValAssign &VA = ArgLocs[i];
2853 EVT RegVT = VA.getLocVT();
2854 SDValue Arg = OutVals[i];
2855 bool isByVal = Flags.isByVal();
2857 // Promote the value if needed.
2858 switch (VA.getLocInfo()) {
2859 default: llvm_unreachable("Unknown loc info!");
2860 case CCValAssign::Full: break;
2861 case CCValAssign::SExt:
2862 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2864 case CCValAssign::ZExt:
2865 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2867 case CCValAssign::AExt:
2868 if (RegVT.is128BitVector()) {
2869 // Special case: passing MMX values in XMM registers.
2870 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2871 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2872 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2874 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2876 case CCValAssign::BCvt:
2877 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2879 case CCValAssign::Indirect: {
2880 // Store the argument.
2881 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2882 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2883 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2884 MachinePointerInfo::getFixedStack(FI),
2891 if (VA.isRegLoc()) {
2892 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2893 if (isVarArg && IsWin64) {
2894 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2895 // shadow reg if callee is a varargs function.
2896 unsigned ShadowReg = 0;
2897 switch (VA.getLocReg()) {
2898 case X86::XMM0: ShadowReg = X86::RCX; break;
2899 case X86::XMM1: ShadowReg = X86::RDX; break;
2900 case X86::XMM2: ShadowReg = X86::R8; break;
2901 case X86::XMM3: ShadowReg = X86::R9; break;
2904 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2906 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2907 assert(VA.isMemLoc());
2908 if (!StackPtr.getNode())
2909 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2911 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2912 dl, DAG, VA, Flags));
2916 if (!MemOpChains.empty())
2917 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2919 if (Subtarget->isPICStyleGOT()) {
2920 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2923 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2924 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2926 // If we are tail calling and generating PIC/GOT style code load the
2927 // address of the callee into ECX. The value in ecx is used as target of
2928 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2929 // for tail calls on PIC/GOT architectures. Normally we would just put the
2930 // address of GOT into ebx and then call target@PLT. But for tail calls
2931 // ebx would be restored (since ebx is callee saved) before jumping to the
2934 // Note: The actual moving to ECX is done further down.
2935 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2936 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2937 !G->getGlobal()->hasProtectedVisibility())
2938 Callee = LowerGlobalAddress(Callee, DAG);
2939 else if (isa<ExternalSymbolSDNode>(Callee))
2940 Callee = LowerExternalSymbol(Callee, DAG);
2944 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
2945 // From AMD64 ABI document:
2946 // For calls that may call functions that use varargs or stdargs
2947 // (prototype-less calls or calls to functions containing ellipsis (...) in
2948 // the declaration) %al is used as hidden argument to specify the number
2949 // of SSE registers used. The contents of %al do not need to match exactly
2950 // the number of registers, but must be an ubound on the number of SSE
2951 // registers used and is in the range 0 - 8 inclusive.
2953 // Count the number of XMM registers allocated.
2954 static const MCPhysReg XMMArgRegs[] = {
2955 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2956 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2958 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2959 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2960 && "SSE registers cannot be used when SSE is disabled");
2962 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2963 DAG.getConstant(NumXMMRegs, MVT::i8)));
2966 if (Is64Bit && isVarArg && IsMustTail) {
2967 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
2968 for (const auto &F : Forwards) {
2969 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2970 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
2974 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
2975 // don't need this because the eligibility check rejects calls that require
2976 // shuffling arguments passed in memory.
2977 if (!IsSibcall && isTailCall) {
2978 // Force all the incoming stack arguments to be loaded from the stack
2979 // before any new outgoing arguments are stored to the stack, because the
2980 // outgoing stack slots may alias the incoming argument stack slots, and
2981 // the alias isn't otherwise explicit. This is slightly more conservative
2982 // than necessary, because it means that each store effectively depends
2983 // on every argument instead of just those arguments it would clobber.
2984 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2986 SmallVector<SDValue, 8> MemOpChains2;
2989 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2990 CCValAssign &VA = ArgLocs[i];
2993 assert(VA.isMemLoc());
2994 SDValue Arg = OutVals[i];
2995 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2996 // Skip inalloca arguments. They don't require any work.
2997 if (Flags.isInAlloca())
2999 // Create frame index.
3000 int32_t Offset = VA.getLocMemOffset()+FPDiff;
3001 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
3002 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3003 FIN = DAG.getFrameIndex(FI, getPointerTy());
3005 if (Flags.isByVal()) {
3006 // Copy relative to framepointer.
3007 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
3008 if (!StackPtr.getNode())
3009 StackPtr = DAG.getCopyFromReg(Chain, dl,
3010 RegInfo->getStackRegister(),
3012 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
3014 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3018 // Store relative to framepointer.
3019 MemOpChains2.push_back(
3020 DAG.getStore(ArgChain, dl, Arg, FIN,
3021 MachinePointerInfo::getFixedStack(FI),
3026 if (!MemOpChains2.empty())
3027 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3029 // Store the return address to the appropriate stack slot.
3030 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3031 getPointerTy(), RegInfo->getSlotSize(),
3035 // Build a sequence of copy-to-reg nodes chained together with token chain
3036 // and flag operands which copy the outgoing args into registers.
3038 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3039 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3040 RegsToPass[i].second, InFlag);
3041 InFlag = Chain.getValue(1);
3044 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3045 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3046 // In the 64-bit large code model, we have to make all calls
3047 // through a register, since the call instruction's 32-bit
3048 // pc-relative offset may not be large enough to hold the whole
3050 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3051 // If the callee is a GlobalAddress node (quite common, every direct call
3052 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3055 // We should use extra load for direct calls to dllimported functions in
3057 const GlobalValue *GV = G->getGlobal();
3058 if (!GV->hasDLLImportStorageClass()) {
3059 unsigned char OpFlags = 0;
3060 bool ExtraLoad = false;
3061 unsigned WrapperKind = ISD::DELETED_NODE;
3063 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3064 // external symbols most go through the PLT in PIC mode. If the symbol
3065 // has hidden or protected visibility, or if it is static or local, then
3066 // we don't need to use the PLT - we can directly call it.
3067 if (Subtarget->isTargetELF() &&
3068 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3069 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3070 OpFlags = X86II::MO_PLT;
3071 } else if (Subtarget->isPICStyleStubAny() &&
3072 (GV->isDeclaration() || GV->isWeakForLinker()) &&
3073 (!Subtarget->getTargetTriple().isMacOSX() ||
3074 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3075 // PC-relative references to external symbols should go through $stub,
3076 // unless we're building with the leopard linker or later, which
3077 // automatically synthesizes these stubs.
3078 OpFlags = X86II::MO_DARWIN_STUB;
3079 } else if (Subtarget->isPICStyleRIPRel() &&
3080 isa<Function>(GV) &&
3081 cast<Function>(GV)->getAttributes().
3082 hasAttribute(AttributeSet::FunctionIndex,
3083 Attribute::NonLazyBind)) {
3084 // If the function is marked as non-lazy, generate an indirect call
3085 // which loads from the GOT directly. This avoids runtime overhead
3086 // at the cost of eager binding (and one extra byte of encoding).
3087 OpFlags = X86II::MO_GOTPCREL;
3088 WrapperKind = X86ISD::WrapperRIP;
3092 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
3093 G->getOffset(), OpFlags);
3095 // Add a wrapper if needed.
3096 if (WrapperKind != ISD::DELETED_NODE)
3097 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
3098 // Add extra indirection if needed.
3100 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
3101 MachinePointerInfo::getGOT(),
3102 false, false, false, 0);
3104 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3105 unsigned char OpFlags = 0;
3107 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3108 // external symbols should go through the PLT.
3109 if (Subtarget->isTargetELF() &&
3110 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3111 OpFlags = X86II::MO_PLT;
3112 } else if (Subtarget->isPICStyleStubAny() &&
3113 (!Subtarget->getTargetTriple().isMacOSX() ||
3114 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3115 // PC-relative references to external symbols should go through $stub,
3116 // unless we're building with the leopard linker or later, which
3117 // automatically synthesizes these stubs.
3118 OpFlags = X86II::MO_DARWIN_STUB;
3121 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
3123 } else if (Subtarget->isTarget64BitILP32() && Callee->getValueType(0) == MVT::i32) {
3124 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3125 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3128 // Returns a chain & a flag for retval copy to use.
3129 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3130 SmallVector<SDValue, 8> Ops;
3132 if (!IsSibcall && isTailCall) {
3133 Chain = DAG.getCALLSEQ_END(Chain,
3134 DAG.getIntPtrConstant(NumBytesToPop, true),
3135 DAG.getIntPtrConstant(0, true), InFlag, dl);
3136 InFlag = Chain.getValue(1);
3139 Ops.push_back(Chain);
3140 Ops.push_back(Callee);
3143 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
3145 // Add argument registers to the end of the list so that they are known live
3147 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3148 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3149 RegsToPass[i].second.getValueType()));
3151 // Add a register mask operand representing the call-preserved registers.
3152 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
3153 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3154 assert(Mask && "Missing call preserved mask for calling convention");
3155 Ops.push_back(DAG.getRegisterMask(Mask));
3157 if (InFlag.getNode())
3158 Ops.push_back(InFlag);
3162 //// If this is the first return lowered for this function, add the regs
3163 //// to the liveout set for the function.
3164 // This isn't right, although it's probably harmless on x86; liveouts
3165 // should be computed from returns not tail calls. Consider a void
3166 // function making a tail call to a function returning int.
3167 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3170 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3171 InFlag = Chain.getValue(1);
3173 // Create the CALLSEQ_END node.
3174 unsigned NumBytesForCalleeToPop;
3175 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3176 DAG.getTarget().Options.GuaranteedTailCallOpt))
3177 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3178 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3179 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3180 SR == StackStructReturn)
3181 // If this is a call to a struct-return function, the callee
3182 // pops the hidden struct pointer, so we have to push it back.
3183 // This is common for Darwin/X86, Linux & Mingw32 targets.
3184 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3185 NumBytesForCalleeToPop = 4;
3187 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3189 // Returns a flag for retval copy to use.
3191 Chain = DAG.getCALLSEQ_END(Chain,
3192 DAG.getIntPtrConstant(NumBytesToPop, true),
3193 DAG.getIntPtrConstant(NumBytesForCalleeToPop,
3196 InFlag = Chain.getValue(1);
3199 // Handle result values, copying them out of physregs into vregs that we
3201 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3202 Ins, dl, DAG, InVals);
3205 //===----------------------------------------------------------------------===//
3206 // Fast Calling Convention (tail call) implementation
3207 //===----------------------------------------------------------------------===//
3209 // Like std call, callee cleans arguments, convention except that ECX is
3210 // reserved for storing the tail called function address. Only 2 registers are
3211 // free for argument passing (inreg). Tail call optimization is performed
3213 // * tailcallopt is enabled
3214 // * caller/callee are fastcc
3215 // On X86_64 architecture with GOT-style position independent code only local
3216 // (within module) calls are supported at the moment.
3217 // To keep the stack aligned according to platform abi the function
3218 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3219 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3220 // If a tail called function callee has more arguments than the caller the
3221 // caller needs to make sure that there is room to move the RETADDR to. This is
3222 // achieved by reserving an area the size of the argument delta right after the
3223 // original RETADDR, but before the saved framepointer or the spilled registers
3224 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3236 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
3237 /// for a 16 byte align requirement.
3239 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3240 SelectionDAG& DAG) const {
3241 MachineFunction &MF = DAG.getMachineFunction();
3242 const TargetMachine &TM = MF.getTarget();
3243 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3244 TM.getSubtargetImpl()->getRegisterInfo());
3245 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
3246 unsigned StackAlignment = TFI.getStackAlignment();
3247 uint64_t AlignMask = StackAlignment - 1;
3248 int64_t Offset = StackSize;
3249 unsigned SlotSize = RegInfo->getSlotSize();
3250 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3251 // Number smaller than 12 so just add the difference.
3252 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3254 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3255 Offset = ((~AlignMask) & Offset) + StackAlignment +
3256 (StackAlignment-SlotSize);
3261 /// MatchingStackOffset - Return true if the given stack call argument is
3262 /// already available in the same position (relatively) of the caller's
3263 /// incoming argument stack.
3265 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3266 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3267 const X86InstrInfo *TII) {
3268 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3270 if (Arg.getOpcode() == ISD::CopyFromReg) {
3271 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3272 if (!TargetRegisterInfo::isVirtualRegister(VR))
3274 MachineInstr *Def = MRI->getVRegDef(VR);
3277 if (!Flags.isByVal()) {
3278 if (!TII->isLoadFromStackSlot(Def, FI))
3281 unsigned Opcode = Def->getOpcode();
3282 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
3283 Def->getOperand(1).isFI()) {
3284 FI = Def->getOperand(1).getIndex();
3285 Bytes = Flags.getByValSize();
3289 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3290 if (Flags.isByVal())
3291 // ByVal argument is passed in as a pointer but it's now being
3292 // dereferenced. e.g.
3293 // define @foo(%struct.X* %A) {
3294 // tail call @bar(%struct.X* byval %A)
3297 SDValue Ptr = Ld->getBasePtr();
3298 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3301 FI = FINode->getIndex();
3302 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3303 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3304 FI = FINode->getIndex();
3305 Bytes = Flags.getByValSize();
3309 assert(FI != INT_MAX);
3310 if (!MFI->isFixedObjectIndex(FI))
3312 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3315 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3316 /// for tail call optimization. Targets which want to do tail call
3317 /// optimization should implement this function.
3319 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3320 CallingConv::ID CalleeCC,
3322 bool isCalleeStructRet,
3323 bool isCallerStructRet,
3325 const SmallVectorImpl<ISD::OutputArg> &Outs,
3326 const SmallVectorImpl<SDValue> &OutVals,
3327 const SmallVectorImpl<ISD::InputArg> &Ins,
3328 SelectionDAG &DAG) const {
3329 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3332 // If -tailcallopt is specified, make fastcc functions tail-callable.
3333 const MachineFunction &MF = DAG.getMachineFunction();
3334 const Function *CallerF = MF.getFunction();
3336 // If the function return type is x86_fp80 and the callee return type is not,
3337 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3338 // perform a tailcall optimization here.
3339 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3342 CallingConv::ID CallerCC = CallerF->getCallingConv();
3343 bool CCMatch = CallerCC == CalleeCC;
3344 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3345 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3347 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3348 if (IsTailCallConvention(CalleeCC) && CCMatch)
3353 // Look for obvious safe cases to perform tail call optimization that do not
3354 // require ABI changes. This is what gcc calls sibcall.
3356 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3357 // emit a special epilogue.
3358 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3359 DAG.getSubtarget().getRegisterInfo());
3360 if (RegInfo->needsStackRealignment(MF))
3363 // Also avoid sibcall optimization if either caller or callee uses struct
3364 // return semantics.
3365 if (isCalleeStructRet || isCallerStructRet)
3368 // An stdcall/thiscall caller is expected to clean up its arguments; the
3369 // callee isn't going to do that.
3370 // FIXME: this is more restrictive than needed. We could produce a tailcall
3371 // when the stack adjustment matches. For example, with a thiscall that takes
3372 // only one argument.
3373 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3374 CallerCC == CallingConv::X86_ThisCall))
3377 // Do not sibcall optimize vararg calls unless all arguments are passed via
3379 if (isVarArg && !Outs.empty()) {
3381 // Optimizing for varargs on Win64 is unlikely to be safe without
3382 // additional testing.
3383 if (IsCalleeWin64 || IsCallerWin64)
3386 SmallVector<CCValAssign, 16> ArgLocs;
3387 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3390 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3391 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3392 if (!ArgLocs[i].isRegLoc())
3396 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3397 // stack. Therefore, if it's not used by the call it is not safe to optimize
3398 // this into a sibcall.
3399 bool Unused = false;
3400 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3407 SmallVector<CCValAssign, 16> RVLocs;
3408 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3410 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3411 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3412 CCValAssign &VA = RVLocs[i];
3413 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3418 // If the calling conventions do not match, then we'd better make sure the
3419 // results are returned in the same way as what the caller expects.
3421 SmallVector<CCValAssign, 16> RVLocs1;
3422 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3424 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3426 SmallVector<CCValAssign, 16> RVLocs2;
3427 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3429 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3431 if (RVLocs1.size() != RVLocs2.size())
3433 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3434 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3436 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3438 if (RVLocs1[i].isRegLoc()) {
3439 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3442 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3448 // If the callee takes no arguments then go on to check the results of the
3450 if (!Outs.empty()) {
3451 // Check if stack adjustment is needed. For now, do not do this if any
3452 // argument is passed on the stack.
3453 SmallVector<CCValAssign, 16> ArgLocs;
3454 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3457 // Allocate shadow area for Win64
3459 CCInfo.AllocateStack(32, 8);
3461 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3462 if (CCInfo.getNextStackOffset()) {
3463 MachineFunction &MF = DAG.getMachineFunction();
3464 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3467 // Check if the arguments are already laid out in the right way as
3468 // the caller's fixed stack objects.
3469 MachineFrameInfo *MFI = MF.getFrameInfo();
3470 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3471 const X86InstrInfo *TII =
3472 static_cast<const X86InstrInfo *>(DAG.getSubtarget().getInstrInfo());
3473 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3474 CCValAssign &VA = ArgLocs[i];
3475 SDValue Arg = OutVals[i];
3476 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3477 if (VA.getLocInfo() == CCValAssign::Indirect)
3479 if (!VA.isRegLoc()) {
3480 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3487 // If the tailcall address may be in a register, then make sure it's
3488 // possible to register allocate for it. In 32-bit, the call address can
3489 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3490 // callee-saved registers are restored. These happen to be the same
3491 // registers used to pass 'inreg' arguments so watch out for those.
3492 if (!Subtarget->is64Bit() &&
3493 ((!isa<GlobalAddressSDNode>(Callee) &&
3494 !isa<ExternalSymbolSDNode>(Callee)) ||
3495 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3496 unsigned NumInRegs = 0;
3497 // In PIC we need an extra register to formulate the address computation
3499 unsigned MaxInRegs =
3500 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3502 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3503 CCValAssign &VA = ArgLocs[i];
3506 unsigned Reg = VA.getLocReg();
3509 case X86::EAX: case X86::EDX: case X86::ECX:
3510 if (++NumInRegs == MaxInRegs)
3522 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3523 const TargetLibraryInfo *libInfo) const {
3524 return X86::createFastISel(funcInfo, libInfo);
3527 //===----------------------------------------------------------------------===//
3528 // Other Lowering Hooks
3529 //===----------------------------------------------------------------------===//
3531 static bool MayFoldLoad(SDValue Op) {
3532 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3535 static bool MayFoldIntoStore(SDValue Op) {
3536 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3539 static bool isTargetShuffle(unsigned Opcode) {
3541 default: return false;
3542 case X86ISD::PSHUFB:
3543 case X86ISD::PSHUFD:
3544 case X86ISD::PSHUFHW:
3545 case X86ISD::PSHUFLW:
3547 case X86ISD::PALIGNR:
3548 case X86ISD::MOVLHPS:
3549 case X86ISD::MOVLHPD:
3550 case X86ISD::MOVHLPS:
3551 case X86ISD::MOVLPS:
3552 case X86ISD::MOVLPD:
3553 case X86ISD::MOVSHDUP:
3554 case X86ISD::MOVSLDUP:
3555 case X86ISD::MOVDDUP:
3558 case X86ISD::UNPCKL:
3559 case X86ISD::UNPCKH:
3560 case X86ISD::VPERMILP:
3561 case X86ISD::VPERM2X128:
3562 case X86ISD::VPERMI:
3567 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3568 SDValue V1, SelectionDAG &DAG) {
3570 default: llvm_unreachable("Unknown x86 shuffle node");
3571 case X86ISD::MOVSHDUP:
3572 case X86ISD::MOVSLDUP:
3573 case X86ISD::MOVDDUP:
3574 return DAG.getNode(Opc, dl, VT, V1);
3578 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3579 SDValue V1, unsigned TargetMask,
3580 SelectionDAG &DAG) {
3582 default: llvm_unreachable("Unknown x86 shuffle node");
3583 case X86ISD::PSHUFD:
3584 case X86ISD::PSHUFHW:
3585 case X86ISD::PSHUFLW:
3586 case X86ISD::VPERMILP:
3587 case X86ISD::VPERMI:
3588 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3592 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3593 SDValue V1, SDValue V2, unsigned TargetMask,
3594 SelectionDAG &DAG) {
3596 default: llvm_unreachable("Unknown x86 shuffle node");
3597 case X86ISD::PALIGNR:
3598 case X86ISD::VALIGN:
3600 case X86ISD::VPERM2X128:
3601 return DAG.getNode(Opc, dl, VT, V1, V2,
3602 DAG.getConstant(TargetMask, MVT::i8));
3606 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3607 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3609 default: llvm_unreachable("Unknown x86 shuffle node");
3610 case X86ISD::MOVLHPS:
3611 case X86ISD::MOVLHPD:
3612 case X86ISD::MOVHLPS:
3613 case X86ISD::MOVLPS:
3614 case X86ISD::MOVLPD:
3617 case X86ISD::UNPCKL:
3618 case X86ISD::UNPCKH:
3619 return DAG.getNode(Opc, dl, VT, V1, V2);
3623 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3624 MachineFunction &MF = DAG.getMachineFunction();
3625 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3626 DAG.getSubtarget().getRegisterInfo());
3627 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3628 int ReturnAddrIndex = FuncInfo->getRAIndex();
3630 if (ReturnAddrIndex == 0) {
3631 // Set up a frame object for the return address.
3632 unsigned SlotSize = RegInfo->getSlotSize();
3633 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3636 FuncInfo->setRAIndex(ReturnAddrIndex);
3639 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3642 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3643 bool hasSymbolicDisplacement) {
3644 // Offset should fit into 32 bit immediate field.
3645 if (!isInt<32>(Offset))
3648 // If we don't have a symbolic displacement - we don't have any extra
3650 if (!hasSymbolicDisplacement)
3653 // FIXME: Some tweaks might be needed for medium code model.
3654 if (M != CodeModel::Small && M != CodeModel::Kernel)
3657 // For small code model we assume that latest object is 16MB before end of 31
3658 // bits boundary. We may also accept pretty large negative constants knowing
3659 // that all objects are in the positive half of address space.
3660 if (M == CodeModel::Small && Offset < 16*1024*1024)
3663 // For kernel code model we know that all object resist in the negative half
3664 // of 32bits address space. We may not accept negative offsets, since they may
3665 // be just off and we may accept pretty large positive ones.
3666 if (M == CodeModel::Kernel && Offset > 0)
3672 /// isCalleePop - Determines whether the callee is required to pop its
3673 /// own arguments. Callee pop is necessary to support tail calls.
3674 bool X86::isCalleePop(CallingConv::ID CallingConv,
3675 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3676 switch (CallingConv) {
3679 case CallingConv::X86_StdCall:
3680 case CallingConv::X86_FastCall:
3681 case CallingConv::X86_ThisCall:
3683 case CallingConv::Fast:
3684 case CallingConv::GHC:
3685 case CallingConv::HiPE:
3692 /// \brief Return true if the condition is an unsigned comparison operation.
3693 static bool isX86CCUnsigned(unsigned X86CC) {
3695 default: llvm_unreachable("Invalid integer condition!");
3696 case X86::COND_E: return true;
3697 case X86::COND_G: return false;
3698 case X86::COND_GE: return false;
3699 case X86::COND_L: return false;
3700 case X86::COND_LE: return false;
3701 case X86::COND_NE: return true;
3702 case X86::COND_B: return true;
3703 case X86::COND_A: return true;
3704 case X86::COND_BE: return true;
3705 case X86::COND_AE: return true;
3707 llvm_unreachable("covered switch fell through?!");
3710 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3711 /// specific condition code, returning the condition code and the LHS/RHS of the
3712 /// comparison to make.
3713 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3714 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3716 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3717 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3718 // X > -1 -> X == 0, jump !sign.
3719 RHS = DAG.getConstant(0, RHS.getValueType());
3720 return X86::COND_NS;
3722 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3723 // X < 0 -> X == 0, jump on sign.
3726 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3728 RHS = DAG.getConstant(0, RHS.getValueType());
3729 return X86::COND_LE;
3733 switch (SetCCOpcode) {
3734 default: llvm_unreachable("Invalid integer condition!");
3735 case ISD::SETEQ: return X86::COND_E;
3736 case ISD::SETGT: return X86::COND_G;
3737 case ISD::SETGE: return X86::COND_GE;
3738 case ISD::SETLT: return X86::COND_L;
3739 case ISD::SETLE: return X86::COND_LE;
3740 case ISD::SETNE: return X86::COND_NE;
3741 case ISD::SETULT: return X86::COND_B;
3742 case ISD::SETUGT: return X86::COND_A;
3743 case ISD::SETULE: return X86::COND_BE;
3744 case ISD::SETUGE: return X86::COND_AE;
3748 // First determine if it is required or is profitable to flip the operands.
3750 // If LHS is a foldable load, but RHS is not, flip the condition.
3751 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3752 !ISD::isNON_EXTLoad(RHS.getNode())) {
3753 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3754 std::swap(LHS, RHS);
3757 switch (SetCCOpcode) {
3763 std::swap(LHS, RHS);
3767 // On a floating point condition, the flags are set as follows:
3769 // 0 | 0 | 0 | X > Y
3770 // 0 | 0 | 1 | X < Y
3771 // 1 | 0 | 0 | X == Y
3772 // 1 | 1 | 1 | unordered
3773 switch (SetCCOpcode) {
3774 default: llvm_unreachable("Condcode should be pre-legalized away");
3776 case ISD::SETEQ: return X86::COND_E;
3777 case ISD::SETOLT: // flipped
3779 case ISD::SETGT: return X86::COND_A;
3780 case ISD::SETOLE: // flipped
3782 case ISD::SETGE: return X86::COND_AE;
3783 case ISD::SETUGT: // flipped
3785 case ISD::SETLT: return X86::COND_B;
3786 case ISD::SETUGE: // flipped
3788 case ISD::SETLE: return X86::COND_BE;
3790 case ISD::SETNE: return X86::COND_NE;
3791 case ISD::SETUO: return X86::COND_P;
3792 case ISD::SETO: return X86::COND_NP;
3794 case ISD::SETUNE: return X86::COND_INVALID;
3798 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3799 /// code. Current x86 isa includes the following FP cmov instructions:
3800 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3801 static bool hasFPCMov(unsigned X86CC) {
3817 /// isFPImmLegal - Returns true if the target can instruction select the
3818 /// specified FP immediate natively. If false, the legalizer will
3819 /// materialize the FP immediate as a load from a constant pool.
3820 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3821 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3822 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3828 /// \brief Returns true if it is beneficial to convert a load of a constant
3829 /// to just the constant itself.
3830 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
3832 assert(Ty->isIntegerTy());
3834 unsigned BitSize = Ty->getPrimitiveSizeInBits();
3835 if (BitSize == 0 || BitSize > 64)
3840 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3841 /// the specified range (L, H].
3842 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3843 return (Val < 0) || (Val >= Low && Val < Hi);
3846 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3847 /// specified value.
3848 static bool isUndefOrEqual(int Val, int CmpVal) {
3849 return (Val < 0 || Val == CmpVal);
3852 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3853 /// from position Pos and ending in Pos+Size, falls within the specified
3854 /// sequential range (L, L+Pos]. or is undef.
3855 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3856 unsigned Pos, unsigned Size, int Low) {
3857 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3858 if (!isUndefOrEqual(Mask[i], Low))
3863 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3864 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3865 /// the second operand.
3866 static bool isPSHUFDMask(ArrayRef<int> Mask, MVT VT) {
3867 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3868 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3869 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3870 return (Mask[0] < 2 && Mask[1] < 2);
3874 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3875 /// is suitable for input to PSHUFHW.
3876 static bool isPSHUFHWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3877 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3880 // Lower quadword copied in order or undef.
3881 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3884 // Upper quadword shuffled.
3885 for (unsigned i = 4; i != 8; ++i)
3886 if (!isUndefOrInRange(Mask[i], 4, 8))
3889 if (VT == MVT::v16i16) {
3890 // Lower quadword copied in order or undef.
3891 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3894 // Upper quadword shuffled.
3895 for (unsigned i = 12; i != 16; ++i)
3896 if (!isUndefOrInRange(Mask[i], 12, 16))
3903 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3904 /// is suitable for input to PSHUFLW.
3905 static bool isPSHUFLWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3906 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3909 // Upper quadword copied in order.
3910 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3913 // Lower quadword shuffled.
3914 for (unsigned i = 0; i != 4; ++i)
3915 if (!isUndefOrInRange(Mask[i], 0, 4))
3918 if (VT == MVT::v16i16) {
3919 // Upper quadword copied in order.
3920 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3923 // Lower quadword shuffled.
3924 for (unsigned i = 8; i != 12; ++i)
3925 if (!isUndefOrInRange(Mask[i], 8, 12))
3932 /// \brief Return true if the mask specifies a shuffle of elements that is
3933 /// suitable for input to intralane (palignr) or interlane (valign) vector
3935 static bool isAlignrMask(ArrayRef<int> Mask, MVT VT, bool InterLane) {
3936 unsigned NumElts = VT.getVectorNumElements();
3937 unsigned NumLanes = InterLane ? 1: VT.getSizeInBits()/128;
3938 unsigned NumLaneElts = NumElts/NumLanes;
3940 // Do not handle 64-bit element shuffles with palignr.
3941 if (NumLaneElts == 2)
3944 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3946 for (i = 0; i != NumLaneElts; ++i) {
3951 // Lane is all undef, go to next lane
3952 if (i == NumLaneElts)
3955 int Start = Mask[i+l];
3957 // Make sure its in this lane in one of the sources
3958 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3959 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3962 // If not lane 0, then we must match lane 0
3963 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3966 // Correct second source to be contiguous with first source
3967 if (Start >= (int)NumElts)
3968 Start -= NumElts - NumLaneElts;
3970 // Make sure we're shifting in the right direction.
3971 if (Start <= (int)(i+l))
3976 // Check the rest of the elements to see if they are consecutive.
3977 for (++i; i != NumLaneElts; ++i) {
3978 int Idx = Mask[i+l];
3980 // Make sure its in this lane
3981 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3982 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3985 // If not lane 0, then we must match lane 0
3986 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3989 if (Idx >= (int)NumElts)
3990 Idx -= NumElts - NumLaneElts;
3992 if (!isUndefOrEqual(Idx, Start+i))
4001 /// \brief Return true if the node specifies a shuffle of elements that is
4002 /// suitable for input to PALIGNR.
4003 static bool isPALIGNRMask(ArrayRef<int> Mask, MVT VT,
4004 const X86Subtarget *Subtarget) {
4005 if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
4006 (VT.is256BitVector() && !Subtarget->hasInt256()) ||
4007 VT.is512BitVector())
4008 // FIXME: Add AVX512BW.
4011 return isAlignrMask(Mask, VT, false);
4014 /// \brief Return true if the node specifies a shuffle of elements that is
4015 /// suitable for input to VALIGN.
4016 static bool isVALIGNMask(ArrayRef<int> Mask, MVT VT,
4017 const X86Subtarget *Subtarget) {
4018 // FIXME: Add AVX512VL.
4019 if (!VT.is512BitVector() || !Subtarget->hasAVX512())
4021 return isAlignrMask(Mask, VT, true);
4024 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
4025 /// the two vector operands have swapped position.
4026 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
4027 unsigned NumElems) {
4028 for (unsigned i = 0; i != NumElems; ++i) {
4032 else if (idx < (int)NumElems)
4033 Mask[i] = idx + NumElems;
4035 Mask[i] = idx - NumElems;
4039 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
4040 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
4041 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
4042 /// reverse of what x86 shuffles want.
4043 static bool isSHUFPMask(ArrayRef<int> Mask, MVT VT, bool Commuted = false) {
4045 unsigned NumElems = VT.getVectorNumElements();
4046 unsigned NumLanes = VT.getSizeInBits()/128;
4047 unsigned NumLaneElems = NumElems/NumLanes;
4049 if (NumLaneElems != 2 && NumLaneElems != 4)
4052 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4053 bool symetricMaskRequired =
4054 (VT.getSizeInBits() >= 256) && (EltSize == 32);
4056 // VSHUFPSY divides the resulting vector into 4 chunks.
4057 // The sources are also splitted into 4 chunks, and each destination
4058 // chunk must come from a different source chunk.
4060 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
4061 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
4063 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
4064 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
4066 // VSHUFPDY divides the resulting vector into 4 chunks.
4067 // The sources are also splitted into 4 chunks, and each destination
4068 // chunk must come from a different source chunk.
4070 // SRC1 => X3 X2 X1 X0
4071 // SRC2 => Y3 Y2 Y1 Y0
4073 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
4075 SmallVector<int, 4> MaskVal(NumLaneElems, -1);
4076 unsigned HalfLaneElems = NumLaneElems/2;
4077 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
4078 for (unsigned i = 0; i != NumLaneElems; ++i) {
4079 int Idx = Mask[i+l];
4080 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
4081 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
4083 // For VSHUFPSY, the mask of the second half must be the same as the
4084 // first but with the appropriate offsets. This works in the same way as
4085 // VPERMILPS works with masks.
4086 if (!symetricMaskRequired || Idx < 0)
4088 if (MaskVal[i] < 0) {
4089 MaskVal[i] = Idx - l;
4092 if ((signed)(Idx - l) != MaskVal[i])
4100 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
4101 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
4102 static bool isMOVHLPSMask(ArrayRef<int> Mask, MVT VT) {
4103 if (!VT.is128BitVector())
4106 unsigned NumElems = VT.getVectorNumElements();
4111 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
4112 return isUndefOrEqual(Mask[0], 6) &&
4113 isUndefOrEqual(Mask[1], 7) &&
4114 isUndefOrEqual(Mask[2], 2) &&
4115 isUndefOrEqual(Mask[3], 3);
4118 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
4119 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
4121 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, MVT VT) {
4122 if (!VT.is128BitVector())
4125 unsigned NumElems = VT.getVectorNumElements();
4130 return isUndefOrEqual(Mask[0], 2) &&
4131 isUndefOrEqual(Mask[1], 3) &&
4132 isUndefOrEqual(Mask[2], 2) &&
4133 isUndefOrEqual(Mask[3], 3);
4136 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
4137 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
4138 static bool isMOVLPMask(ArrayRef<int> Mask, MVT VT) {
4139 if (!VT.is128BitVector())
4142 unsigned NumElems = VT.getVectorNumElements();
4144 if (NumElems != 2 && NumElems != 4)
4147 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4148 if (!isUndefOrEqual(Mask[i], i + NumElems))
4151 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4152 if (!isUndefOrEqual(Mask[i], i))
4158 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
4159 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
4160 static bool isMOVLHPSMask(ArrayRef<int> Mask, MVT VT) {
4161 if (!VT.is128BitVector())
4164 unsigned NumElems = VT.getVectorNumElements();
4166 if (NumElems != 2 && NumElems != 4)
4169 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4170 if (!isUndefOrEqual(Mask[i], i))
4173 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4174 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
4180 /// isINSERTPSMask - Return true if the specified VECTOR_SHUFFLE operand
4181 /// specifies a shuffle of elements that is suitable for input to INSERTPS.
4182 /// i. e: If all but one element come from the same vector.
4183 static bool isINSERTPSMask(ArrayRef<int> Mask, MVT VT) {
4184 // TODO: Deal with AVX's VINSERTPS
4185 if (!VT.is128BitVector() || (VT != MVT::v4f32 && VT != MVT::v4i32))
4188 unsigned CorrectPosV1 = 0;
4189 unsigned CorrectPosV2 = 0;
4190 for (int i = 0, e = (int)VT.getVectorNumElements(); i != e; ++i) {
4191 if (Mask[i] == -1) {
4199 else if (Mask[i] == i + 4)
4203 if (CorrectPosV1 == 3 || CorrectPosV2 == 3)
4204 // We have 3 elements (undefs count as elements from any vector) from one
4205 // vector, and one from another.
4212 // Some special combinations that can be optimized.
4215 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
4216 SelectionDAG &DAG) {
4217 MVT VT = SVOp->getSimpleValueType(0);
4220 if (VT != MVT::v8i32 && VT != MVT::v8f32)
4223 ArrayRef<int> Mask = SVOp->getMask();
4225 // These are the special masks that may be optimized.
4226 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
4227 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
4228 bool MatchEvenMask = true;
4229 bool MatchOddMask = true;
4230 for (int i=0; i<8; ++i) {
4231 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
4232 MatchEvenMask = false;
4233 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
4234 MatchOddMask = false;
4237 if (!MatchEvenMask && !MatchOddMask)
4240 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
4242 SDValue Op0 = SVOp->getOperand(0);
4243 SDValue Op1 = SVOp->getOperand(1);
4245 if (MatchEvenMask) {
4246 // Shift the second operand right to 32 bits.
4247 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 };
4248 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
4250 // Shift the first operand left to 32 bits.
4251 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 };
4252 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
4254 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15};
4255 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
4258 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
4259 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
4260 static bool isUNPCKLMask(ArrayRef<int> Mask, MVT VT,
4261 bool HasInt256, bool V2IsSplat = false) {
4263 assert(VT.getSizeInBits() >= 128 &&
4264 "Unsupported vector type for unpckl");
4266 unsigned NumElts = VT.getVectorNumElements();
4267 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4268 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4271 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4272 "Unsupported vector type for unpckh");
4274 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4275 unsigned NumLanes = VT.getSizeInBits()/128;
4276 unsigned NumLaneElts = NumElts/NumLanes;
4278 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4279 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4280 int BitI = Mask[l+i];
4281 int BitI1 = Mask[l+i+1];
4282 if (!isUndefOrEqual(BitI, j))
4285 if (!isUndefOrEqual(BitI1, NumElts))
4288 if (!isUndefOrEqual(BitI1, j + NumElts))
4297 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
4298 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
4299 static bool isUNPCKHMask(ArrayRef<int> Mask, MVT VT,
4300 bool HasInt256, bool V2IsSplat = false) {
4301 assert(VT.getSizeInBits() >= 128 &&
4302 "Unsupported vector type for unpckh");
4304 unsigned NumElts = VT.getVectorNumElements();
4305 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4306 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4309 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4310 "Unsupported vector type for unpckh");
4312 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4313 unsigned NumLanes = VT.getSizeInBits()/128;
4314 unsigned NumLaneElts = NumElts/NumLanes;
4316 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4317 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4318 int BitI = Mask[l+i];
4319 int BitI1 = Mask[l+i+1];
4320 if (!isUndefOrEqual(BitI, j))
4323 if (isUndefOrEqual(BitI1, NumElts))
4326 if (!isUndefOrEqual(BitI1, j+NumElts))
4334 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
4335 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
4337 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4338 unsigned NumElts = VT.getVectorNumElements();
4339 bool Is256BitVec = VT.is256BitVector();
4341 if (VT.is512BitVector())
4343 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4344 "Unsupported vector type for unpckh");
4346 if (Is256BitVec && NumElts != 4 && NumElts != 8 &&
4347 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4350 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
4351 // FIXME: Need a better way to get rid of this, there's no latency difference
4352 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
4353 // the former later. We should also remove the "_undef" special mask.
4354 if (NumElts == 4 && Is256BitVec)
4357 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4358 // independently on 128-bit lanes.
4359 unsigned NumLanes = VT.getSizeInBits()/128;
4360 unsigned NumLaneElts = NumElts/NumLanes;
4362 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4363 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4364 int BitI = Mask[l+i];
4365 int BitI1 = Mask[l+i+1];
4367 if (!isUndefOrEqual(BitI, j))
4369 if (!isUndefOrEqual(BitI1, j))
4377 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
4378 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
4380 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4381 unsigned NumElts = VT.getVectorNumElements();
4383 if (VT.is512BitVector())
4386 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4387 "Unsupported vector type for unpckh");
4389 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4390 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4393 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4394 // independently on 128-bit lanes.
4395 unsigned NumLanes = VT.getSizeInBits()/128;
4396 unsigned NumLaneElts = NumElts/NumLanes;
4398 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4399 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4400 int BitI = Mask[l+i];
4401 int BitI1 = Mask[l+i+1];
4402 if (!isUndefOrEqual(BitI, j))
4404 if (!isUndefOrEqual(BitI1, j))
4411 // Match for INSERTI64x4 INSERTF64x4 instructions (src0[0], src1[0]) or
4412 // (src1[0], src0[1]), manipulation with 256-bit sub-vectors
4413 static bool isINSERT64x4Mask(ArrayRef<int> Mask, MVT VT, unsigned int *Imm) {
4414 if (!VT.is512BitVector())
4417 unsigned NumElts = VT.getVectorNumElements();
4418 unsigned HalfSize = NumElts/2;
4419 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, 0)) {
4420 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, NumElts)) {
4425 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, NumElts)) {
4426 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, HalfSize)) {
4434 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
4435 /// specifies a shuffle of elements that is suitable for input to MOVSS,
4436 /// MOVSD, and MOVD, i.e. setting the lowest element.
4437 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
4438 if (VT.getVectorElementType().getSizeInBits() < 32)
4440 if (!VT.is128BitVector())
4443 unsigned NumElts = VT.getVectorNumElements();
4445 if (!isUndefOrEqual(Mask[0], NumElts))
4448 for (unsigned i = 1; i != NumElts; ++i)
4449 if (!isUndefOrEqual(Mask[i], i))
4455 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
4456 /// as permutations between 128-bit chunks or halves. As an example: this
4458 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
4459 /// The first half comes from the second half of V1 and the second half from the
4460 /// the second half of V2.
4461 static bool isVPERM2X128Mask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4462 if (!HasFp256 || !VT.is256BitVector())
4465 // The shuffle result is divided into half A and half B. In total the two
4466 // sources have 4 halves, namely: C, D, E, F. The final values of A and
4467 // B must come from C, D, E or F.
4468 unsigned HalfSize = VT.getVectorNumElements()/2;
4469 bool MatchA = false, MatchB = false;
4471 // Check if A comes from one of C, D, E, F.
4472 for (unsigned Half = 0; Half != 4; ++Half) {
4473 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
4479 // Check if B comes from one of C, D, E, F.
4480 for (unsigned Half = 0; Half != 4; ++Half) {
4481 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
4487 return MatchA && MatchB;
4490 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
4491 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
4492 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
4493 MVT VT = SVOp->getSimpleValueType(0);
4495 unsigned HalfSize = VT.getVectorNumElements()/2;
4497 unsigned FstHalf = 0, SndHalf = 0;
4498 for (unsigned i = 0; i < HalfSize; ++i) {
4499 if (SVOp->getMaskElt(i) > 0) {
4500 FstHalf = SVOp->getMaskElt(i)/HalfSize;
4504 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
4505 if (SVOp->getMaskElt(i) > 0) {
4506 SndHalf = SVOp->getMaskElt(i)/HalfSize;
4511 return (FstHalf | (SndHalf << 4));
4514 // Symetric in-lane mask. Each lane has 4 elements (for imm8)
4515 static bool isPermImmMask(ArrayRef<int> Mask, MVT VT, unsigned& Imm8) {
4516 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4520 unsigned NumElts = VT.getVectorNumElements();
4522 if (VT.is128BitVector() || (VT.is256BitVector() && EltSize == 64)) {
4523 for (unsigned i = 0; i != NumElts; ++i) {
4526 Imm8 |= Mask[i] << (i*2);
4531 unsigned LaneSize = 4;
4532 SmallVector<int, 4> MaskVal(LaneSize, -1);
4534 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4535 for (unsigned i = 0; i != LaneSize; ++i) {
4536 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4540 if (MaskVal[i] < 0) {
4541 MaskVal[i] = Mask[i+l] - l;
4542 Imm8 |= MaskVal[i] << (i*2);
4545 if (Mask[i+l] != (signed)(MaskVal[i]+l))
4552 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
4553 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
4554 /// Note that VPERMIL mask matching is different depending whether theunderlying
4555 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
4556 /// to the same elements of the low, but to the higher half of the source.
4557 /// In VPERMILPD the two lanes could be shuffled independently of each other
4558 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
4559 static bool isVPERMILPMask(ArrayRef<int> Mask, MVT VT) {
4560 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4561 if (VT.getSizeInBits() < 256 || EltSize < 32)
4563 bool symetricMaskRequired = (EltSize == 32);
4564 unsigned NumElts = VT.getVectorNumElements();
4566 unsigned NumLanes = VT.getSizeInBits()/128;
4567 unsigned LaneSize = NumElts/NumLanes;
4568 // 2 or 4 elements in one lane
4570 SmallVector<int, 4> ExpectedMaskVal(LaneSize, -1);
4571 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4572 for (unsigned i = 0; i != LaneSize; ++i) {
4573 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4575 if (symetricMaskRequired) {
4576 if (ExpectedMaskVal[i] < 0 && Mask[i+l] >= 0) {
4577 ExpectedMaskVal[i] = Mask[i+l] - l;
4580 if (!isUndefOrEqual(Mask[i+l], ExpectedMaskVal[i]+l))
4588 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
4589 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
4590 /// element of vector 2 and the other elements to come from vector 1 in order.
4591 static bool isCommutedMOVLMask(ArrayRef<int> Mask, MVT VT,
4592 bool V2IsSplat = false, bool V2IsUndef = false) {
4593 if (!VT.is128BitVector())
4596 unsigned NumOps = VT.getVectorNumElements();
4597 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
4600 if (!isUndefOrEqual(Mask[0], 0))
4603 for (unsigned i = 1; i != NumOps; ++i)
4604 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
4605 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
4606 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
4612 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4613 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
4614 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
4615 static bool isMOVSHDUPMask(ArrayRef<int> Mask, MVT VT,
4616 const X86Subtarget *Subtarget) {
4617 if (!Subtarget->hasSSE3())
4620 unsigned NumElems = VT.getVectorNumElements();
4622 if ((VT.is128BitVector() && NumElems != 4) ||
4623 (VT.is256BitVector() && NumElems != 8) ||
4624 (VT.is512BitVector() && NumElems != 16))
4627 // "i+1" is the value the indexed mask element must have
4628 for (unsigned i = 0; i != NumElems; i += 2)
4629 if (!isUndefOrEqual(Mask[i], i+1) ||
4630 !isUndefOrEqual(Mask[i+1], i+1))
4636 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4637 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
4638 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
4639 static bool isMOVSLDUPMask(ArrayRef<int> Mask, MVT VT,
4640 const X86Subtarget *Subtarget) {
4641 if (!Subtarget->hasSSE3())
4644 unsigned NumElems = VT.getVectorNumElements();
4646 if ((VT.is128BitVector() && NumElems != 4) ||
4647 (VT.is256BitVector() && NumElems != 8) ||
4648 (VT.is512BitVector() && NumElems != 16))
4651 // "i" is the value the indexed mask element must have
4652 for (unsigned i = 0; i != NumElems; i += 2)
4653 if (!isUndefOrEqual(Mask[i], i) ||
4654 !isUndefOrEqual(Mask[i+1], i))
4660 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
4661 /// specifies a shuffle of elements that is suitable for input to 256-bit
4662 /// version of MOVDDUP.
4663 static bool isMOVDDUPYMask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4664 if (!HasFp256 || !VT.is256BitVector())
4667 unsigned NumElts = VT.getVectorNumElements();
4671 for (unsigned i = 0; i != NumElts/2; ++i)
4672 if (!isUndefOrEqual(Mask[i], 0))
4674 for (unsigned i = NumElts/2; i != NumElts; ++i)
4675 if (!isUndefOrEqual(Mask[i], NumElts/2))
4680 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4681 /// specifies a shuffle of elements that is suitable for input to 128-bit
4682 /// version of MOVDDUP.
4683 static bool isMOVDDUPMask(ArrayRef<int> Mask, MVT VT) {
4684 if (!VT.is128BitVector())
4687 unsigned e = VT.getVectorNumElements() / 2;
4688 for (unsigned i = 0; i != e; ++i)
4689 if (!isUndefOrEqual(Mask[i], i))
4691 for (unsigned i = 0; i != e; ++i)
4692 if (!isUndefOrEqual(Mask[e+i], i))
4697 /// isVEXTRACTIndex - Return true if the specified
4698 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
4699 /// suitable for instruction that extract 128 or 256 bit vectors
4700 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4701 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4702 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4705 // The index should be aligned on a vecWidth-bit boundary.
4707 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4709 MVT VT = N->getSimpleValueType(0);
4710 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4711 bool Result = (Index * ElSize) % vecWidth == 0;
4716 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
4717 /// operand specifies a subvector insert that is suitable for input to
4718 /// insertion of 128 or 256-bit subvectors
4719 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4720 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4721 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4723 // The index should be aligned on a vecWidth-bit boundary.
4725 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4727 MVT VT = N->getSimpleValueType(0);
4728 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4729 bool Result = (Index * ElSize) % vecWidth == 0;
4734 bool X86::isVINSERT128Index(SDNode *N) {
4735 return isVINSERTIndex(N, 128);
4738 bool X86::isVINSERT256Index(SDNode *N) {
4739 return isVINSERTIndex(N, 256);
4742 bool X86::isVEXTRACT128Index(SDNode *N) {
4743 return isVEXTRACTIndex(N, 128);
4746 bool X86::isVEXTRACT256Index(SDNode *N) {
4747 return isVEXTRACTIndex(N, 256);
4750 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4751 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4752 /// Handles 128-bit and 256-bit.
4753 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
4754 MVT VT = N->getSimpleValueType(0);
4756 assert((VT.getSizeInBits() >= 128) &&
4757 "Unsupported vector type for PSHUF/SHUFP");
4759 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
4760 // independently on 128-bit lanes.
4761 unsigned NumElts = VT.getVectorNumElements();
4762 unsigned NumLanes = VT.getSizeInBits()/128;
4763 unsigned NumLaneElts = NumElts/NumLanes;
4765 assert((NumLaneElts == 2 || NumLaneElts == 4 || NumLaneElts == 8) &&
4766 "Only supports 2, 4 or 8 elements per lane");
4768 unsigned Shift = (NumLaneElts >= 4) ? 1 : 0;
4770 for (unsigned i = 0; i != NumElts; ++i) {
4771 int Elt = N->getMaskElt(i);
4772 if (Elt < 0) continue;
4773 Elt &= NumLaneElts - 1;
4774 unsigned ShAmt = (i << Shift) % 8;
4775 Mask |= Elt << ShAmt;
4781 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4782 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4783 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4784 MVT VT = N->getSimpleValueType(0);
4786 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4787 "Unsupported vector type for PSHUFHW");
4789 unsigned NumElts = VT.getVectorNumElements();
4792 for (unsigned l = 0; l != NumElts; l += 8) {
4793 // 8 nodes per lane, but we only care about the last 4.
4794 for (unsigned i = 0; i < 4; ++i) {
4795 int Elt = N->getMaskElt(l+i+4);
4796 if (Elt < 0) continue;
4797 Elt &= 0x3; // only 2-bits.
4798 Mask |= Elt << (i * 2);
4805 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4806 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4807 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4808 MVT VT = N->getSimpleValueType(0);
4810 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4811 "Unsupported vector type for PSHUFHW");
4813 unsigned NumElts = VT.getVectorNumElements();
4816 for (unsigned l = 0; l != NumElts; l += 8) {
4817 // 8 nodes per lane, but we only care about the first 4.
4818 for (unsigned i = 0; i < 4; ++i) {
4819 int Elt = N->getMaskElt(l+i);
4820 if (Elt < 0) continue;
4821 Elt &= 0x3; // only 2-bits
4822 Mask |= Elt << (i * 2);
4829 /// \brief Return the appropriate immediate to shuffle the specified
4830 /// VECTOR_SHUFFLE mask with the PALIGNR (if InterLane is false) or with
4831 /// VALIGN (if Interlane is true) instructions.
4832 static unsigned getShuffleAlignrImmediate(ShuffleVectorSDNode *SVOp,
4834 MVT VT = SVOp->getSimpleValueType(0);
4835 unsigned EltSize = InterLane ? 1 :
4836 VT.getVectorElementType().getSizeInBits() >> 3;
4838 unsigned NumElts = VT.getVectorNumElements();
4839 unsigned NumLanes = VT.is512BitVector() ? 1 : VT.getSizeInBits()/128;
4840 unsigned NumLaneElts = NumElts/NumLanes;
4844 for (i = 0; i != NumElts; ++i) {
4845 Val = SVOp->getMaskElt(i);
4849 if (Val >= (int)NumElts)
4850 Val -= NumElts - NumLaneElts;
4852 assert(Val - i > 0 && "PALIGNR imm should be positive");
4853 return (Val - i) * EltSize;
4856 /// \brief Return the appropriate immediate to shuffle the specified
4857 /// VECTOR_SHUFFLE mask with the PALIGNR instruction.
4858 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4859 return getShuffleAlignrImmediate(SVOp, false);
4862 /// \brief Return the appropriate immediate to shuffle the specified
4863 /// VECTOR_SHUFFLE mask with the VALIGN instruction.
4864 static unsigned getShuffleVALIGNImmediate(ShuffleVectorSDNode *SVOp) {
4865 return getShuffleAlignrImmediate(SVOp, true);
4869 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4870 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4871 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4872 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4875 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4877 MVT VecVT = N->getOperand(0).getSimpleValueType();
4878 MVT ElVT = VecVT.getVectorElementType();
4880 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4881 return Index / NumElemsPerChunk;
4884 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4885 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4886 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4887 llvm_unreachable("Illegal insert subvector for VINSERT");
4890 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4892 MVT VecVT = N->getSimpleValueType(0);
4893 MVT ElVT = VecVT.getVectorElementType();
4895 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4896 return Index / NumElemsPerChunk;
4899 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
4900 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4901 /// and VINSERTI128 instructions.
4902 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4903 return getExtractVEXTRACTImmediate(N, 128);
4906 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
4907 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4908 /// and VINSERTI64x4 instructions.
4909 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4910 return getExtractVEXTRACTImmediate(N, 256);
4913 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4914 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4915 /// and VINSERTI128 instructions.
4916 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4917 return getInsertVINSERTImmediate(N, 128);
4920 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4921 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4922 /// and VINSERTI64x4 instructions.
4923 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4924 return getInsertVINSERTImmediate(N, 256);
4927 /// isZero - Returns true if Elt is a constant integer zero
4928 static bool isZero(SDValue V) {
4929 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
4930 return C && C->isNullValue();
4933 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4935 bool X86::isZeroNode(SDValue Elt) {
4938 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4939 return CFP->getValueAPF().isPosZero();
4943 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4944 /// match movhlps. The lower half elements should come from upper half of
4945 /// V1 (and in order), and the upper half elements should come from the upper
4946 /// half of V2 (and in order).
4947 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, MVT VT) {
4948 if (!VT.is128BitVector())
4950 if (VT.getVectorNumElements() != 4)
4952 for (unsigned i = 0, e = 2; i != e; ++i)
4953 if (!isUndefOrEqual(Mask[i], i+2))
4955 for (unsigned i = 2; i != 4; ++i)
4956 if (!isUndefOrEqual(Mask[i], i+4))
4961 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4962 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4964 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = nullptr) {
4965 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4967 N = N->getOperand(0).getNode();
4968 if (!ISD::isNON_EXTLoad(N))
4971 *LD = cast<LoadSDNode>(N);
4975 // Test whether the given value is a vector value which will be legalized
4977 static bool WillBeConstantPoolLoad(SDNode *N) {
4978 if (N->getOpcode() != ISD::BUILD_VECTOR)
4981 // Check for any non-constant elements.
4982 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4983 switch (N->getOperand(i).getNode()->getOpcode()) {
4985 case ISD::ConstantFP:
4992 // Vectors of all-zeros and all-ones are materialized with special
4993 // instructions rather than being loaded.
4994 return !ISD::isBuildVectorAllZeros(N) &&
4995 !ISD::isBuildVectorAllOnes(N);
4998 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
4999 /// match movlp{s|d}. The lower half elements should come from lower half of
5000 /// V1 (and in order), and the upper half elements should come from the upper
5001 /// half of V2 (and in order). And since V1 will become the source of the
5002 /// MOVLP, it must be either a vector load or a scalar load to vector.
5003 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
5004 ArrayRef<int> Mask, MVT VT) {
5005 if (!VT.is128BitVector())
5008 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
5010 // Is V2 is a vector load, don't do this transformation. We will try to use
5011 // load folding shufps op.
5012 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
5015 unsigned NumElems = VT.getVectorNumElements();
5017 if (NumElems != 2 && NumElems != 4)
5019 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
5020 if (!isUndefOrEqual(Mask[i], i))
5022 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
5023 if (!isUndefOrEqual(Mask[i], i+NumElems))
5028 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
5029 /// to an zero vector.
5030 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
5031 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
5032 SDValue V1 = N->getOperand(0);
5033 SDValue V2 = N->getOperand(1);
5034 unsigned NumElems = N->getValueType(0).getVectorNumElements();
5035 for (unsigned i = 0; i != NumElems; ++i) {
5036 int Idx = N->getMaskElt(i);
5037 if (Idx >= (int)NumElems) {
5038 unsigned Opc = V2.getOpcode();
5039 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
5041 if (Opc != ISD::BUILD_VECTOR ||
5042 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
5044 } else if (Idx >= 0) {
5045 unsigned Opc = V1.getOpcode();
5046 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
5048 if (Opc != ISD::BUILD_VECTOR ||
5049 !X86::isZeroNode(V1.getOperand(Idx)))
5056 /// getZeroVector - Returns a vector of specified type with all zero elements.
5058 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
5059 SelectionDAG &DAG, SDLoc dl) {
5060 assert(VT.isVector() && "Expected a vector type");
5062 // Always build SSE zero vectors as <4 x i32> bitcasted
5063 // to their dest type. This ensures they get CSE'd.
5065 if (VT.is128BitVector()) { // SSE
5066 if (Subtarget->hasSSE2()) { // SSE2
5067 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
5068 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5070 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
5071 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
5073 } else if (VT.is256BitVector()) { // AVX
5074 if (Subtarget->hasInt256()) { // AVX2
5075 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
5076 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5077 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5079 // 256-bit logic and arithmetic instructions in AVX are all
5080 // floating-point, no support for integer ops. Emit fp zeroed vectors.
5081 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
5082 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5083 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
5085 } else if (VT.is512BitVector()) { // AVX-512
5086 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
5087 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
5088 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5089 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
5090 } else if (VT.getScalarType() == MVT::i1) {
5091 assert(VT.getVectorNumElements() <= 16 && "Unexpected vector type");
5092 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
5093 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5094 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5096 llvm_unreachable("Unexpected vector type");
5098 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5101 /// getOnesVector - Returns a vector of specified type with all bits set.
5102 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
5103 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
5104 /// Then bitcast to their original type, ensuring they get CSE'd.
5105 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
5107 assert(VT.isVector() && "Expected a vector type");
5109 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
5111 if (VT.is256BitVector()) {
5112 if (HasInt256) { // AVX2
5113 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5114 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5116 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5117 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
5119 } else if (VT.is128BitVector()) {
5120 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5122 llvm_unreachable("Unexpected vector type");
5124 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5127 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
5128 /// that point to V2 points to its first element.
5129 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
5130 for (unsigned i = 0; i != NumElems; ++i) {
5131 if (Mask[i] > (int)NumElems) {
5137 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
5138 /// operation of specified width.
5139 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
5141 unsigned NumElems = VT.getVectorNumElements();
5142 SmallVector<int, 8> Mask;
5143 Mask.push_back(NumElems);
5144 for (unsigned i = 1; i != NumElems; ++i)
5146 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5149 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
5150 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5152 unsigned NumElems = VT.getVectorNumElements();
5153 SmallVector<int, 8> Mask;
5154 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
5156 Mask.push_back(i + NumElems);
5158 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5161 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
5162 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5164 unsigned NumElems = VT.getVectorNumElements();
5165 SmallVector<int, 8> Mask;
5166 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
5167 Mask.push_back(i + Half);
5168 Mask.push_back(i + NumElems + Half);
5170 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5173 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
5174 // a generic shuffle instruction because the target has no such instructions.
5175 // Generate shuffles which repeat i16 and i8 several times until they can be
5176 // represented by v4f32 and then be manipulated by target suported shuffles.
5177 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
5178 MVT VT = V.getSimpleValueType();
5179 int NumElems = VT.getVectorNumElements();
5182 while (NumElems > 4) {
5183 if (EltNo < NumElems/2) {
5184 V = getUnpackl(DAG, dl, VT, V, V);
5186 V = getUnpackh(DAG, dl, VT, V, V);
5187 EltNo -= NumElems/2;
5194 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
5195 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
5196 MVT VT = V.getSimpleValueType();
5199 if (VT.is128BitVector()) {
5200 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
5201 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
5202 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
5204 } else if (VT.is256BitVector()) {
5205 // To use VPERMILPS to splat scalars, the second half of indicies must
5206 // refer to the higher part, which is a duplication of the lower one,
5207 // because VPERMILPS can only handle in-lane permutations.
5208 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
5209 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
5211 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
5212 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
5215 llvm_unreachable("Vector size not supported");
5217 return DAG.getNode(ISD::BITCAST, dl, VT, V);
5220 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
5221 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
5222 MVT SrcVT = SV->getSimpleValueType(0);
5223 SDValue V1 = SV->getOperand(0);
5226 int EltNo = SV->getSplatIndex();
5227 int NumElems = SrcVT.getVectorNumElements();
5228 bool Is256BitVec = SrcVT.is256BitVector();
5230 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) &&
5231 "Unknown how to promote splat for type");
5233 // Extract the 128-bit part containing the splat element and update
5234 // the splat element index when it refers to the higher register.
5236 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
5237 if (EltNo >= NumElems/2)
5238 EltNo -= NumElems/2;
5241 // All i16 and i8 vector types can't be used directly by a generic shuffle
5242 // instruction because the target has no such instruction. Generate shuffles
5243 // which repeat i16 and i8 several times until they fit in i32, and then can
5244 // be manipulated by target suported shuffles.
5245 MVT EltVT = SrcVT.getVectorElementType();
5246 if (EltVT == MVT::i8 || EltVT == MVT::i16)
5247 V1 = PromoteSplati8i16(V1, DAG, EltNo);
5249 // Recreate the 256-bit vector and place the same 128-bit vector
5250 // into the low and high part. This is necessary because we want
5251 // to use VPERM* to shuffle the vectors
5253 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
5256 return getLegalSplat(DAG, V1, EltNo);
5259 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
5260 /// vector of zero or undef vector. This produces a shuffle where the low
5261 /// element of V2 is swizzled into the zero/undef vector, landing at element
5262 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
5263 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
5265 const X86Subtarget *Subtarget,
5266 SelectionDAG &DAG) {
5267 MVT VT = V2.getSimpleValueType();
5269 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
5270 unsigned NumElems = VT.getVectorNumElements();
5271 SmallVector<int, 16> MaskVec;
5272 for (unsigned i = 0; i != NumElems; ++i)
5273 // If this is the insertion idx, put the low elt of V2 here.
5274 MaskVec.push_back(i == Idx ? NumElems : i);
5275 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
5278 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
5279 /// target specific opcode. Returns true if the Mask could be calculated. Sets
5280 /// IsUnary to true if only uses one source. Note that this will set IsUnary for
5281 /// shuffles which use a single input multiple times, and in those cases it will
5282 /// adjust the mask to only have indices within that single input.
5283 static bool getTargetShuffleMask(SDNode *N, MVT VT,
5284 SmallVectorImpl<int> &Mask, bool &IsUnary) {
5285 unsigned NumElems = VT.getVectorNumElements();
5289 bool IsFakeUnary = false;
5290 switch(N->getOpcode()) {
5292 ImmN = N->getOperand(N->getNumOperands()-1);
5293 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5294 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5296 case X86ISD::UNPCKH:
5297 DecodeUNPCKHMask(VT, Mask);
5298 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5300 case X86ISD::UNPCKL:
5301 DecodeUNPCKLMask(VT, Mask);
5302 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5304 case X86ISD::MOVHLPS:
5305 DecodeMOVHLPSMask(NumElems, Mask);
5306 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5308 case X86ISD::MOVLHPS:
5309 DecodeMOVLHPSMask(NumElems, Mask);
5310 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5312 case X86ISD::PALIGNR:
5313 ImmN = N->getOperand(N->getNumOperands()-1);
5314 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5316 case X86ISD::PSHUFD:
5317 case X86ISD::VPERMILP:
5318 ImmN = N->getOperand(N->getNumOperands()-1);
5319 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5322 case X86ISD::PSHUFHW:
5323 ImmN = N->getOperand(N->getNumOperands()-1);
5324 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5327 case X86ISD::PSHUFLW:
5328 ImmN = N->getOperand(N->getNumOperands()-1);
5329 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5332 case X86ISD::PSHUFB: {
5334 SDValue MaskNode = N->getOperand(1);
5335 while (MaskNode->getOpcode() == ISD::BITCAST)
5336 MaskNode = MaskNode->getOperand(0);
5338 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
5339 // If we have a build-vector, then things are easy.
5340 EVT VT = MaskNode.getValueType();
5341 assert(VT.isVector() &&
5342 "Can't produce a non-vector with a build_vector!");
5343 if (!VT.isInteger())
5346 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
5348 SmallVector<uint64_t, 32> RawMask;
5349 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
5350 auto *CN = dyn_cast<ConstantSDNode>(MaskNode->getOperand(i));
5353 APInt MaskElement = CN->getAPIntValue();
5355 // We now have to decode the element which could be any integer size and
5356 // extract each byte of it.
5357 for (int j = 0; j < NumBytesPerElement; ++j) {
5358 // Note that this is x86 and so always little endian: the low byte is
5359 // the first byte of the mask.
5360 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
5361 MaskElement = MaskElement.lshr(8);
5364 DecodePSHUFBMask(RawMask, Mask);
5368 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
5372 SDValue Ptr = MaskLoad->getBasePtr();
5373 if (Ptr->getOpcode() == X86ISD::Wrapper)
5374 Ptr = Ptr->getOperand(0);
5376 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
5377 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
5380 if (auto *C = dyn_cast<ConstantDataSequential>(MaskCP->getConstVal())) {
5381 // FIXME: Support AVX-512 here.
5382 if (!C->getType()->isVectorTy() ||
5383 (C->getNumElements() != 16 && C->getNumElements() != 32))
5386 assert(C->getType()->isVectorTy() && "Expected a vector constant.");
5387 DecodePSHUFBMask(C, Mask);
5393 case X86ISD::VPERMI:
5394 ImmN = N->getOperand(N->getNumOperands()-1);
5395 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5399 case X86ISD::MOVSD: {
5400 // The index 0 always comes from the first element of the second source,
5401 // this is why MOVSS and MOVSD are used in the first place. The other
5402 // elements come from the other positions of the first source vector
5403 Mask.push_back(NumElems);
5404 for (unsigned i = 1; i != NumElems; ++i) {
5409 case X86ISD::VPERM2X128:
5410 ImmN = N->getOperand(N->getNumOperands()-1);
5411 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5412 if (Mask.empty()) return false;
5414 case X86ISD::MOVSLDUP:
5415 DecodeMOVSLDUPMask(VT, Mask);
5417 case X86ISD::MOVSHDUP:
5418 DecodeMOVSHDUPMask(VT, Mask);
5420 case X86ISD::MOVDDUP:
5421 case X86ISD::MOVLHPD:
5422 case X86ISD::MOVLPD:
5423 case X86ISD::MOVLPS:
5424 // Not yet implemented
5426 default: llvm_unreachable("unknown target shuffle node");
5429 // If we have a fake unary shuffle, the shuffle mask is spread across two
5430 // inputs that are actually the same node. Re-map the mask to always point
5431 // into the first input.
5434 if (M >= (int)Mask.size())
5440 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
5441 /// element of the result of the vector shuffle.
5442 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
5445 return SDValue(); // Limit search depth.
5447 SDValue V = SDValue(N, 0);
5448 EVT VT = V.getValueType();
5449 unsigned Opcode = V.getOpcode();
5451 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
5452 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
5453 int Elt = SV->getMaskElt(Index);
5456 return DAG.getUNDEF(VT.getVectorElementType());
5458 unsigned NumElems = VT.getVectorNumElements();
5459 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
5460 : SV->getOperand(1);
5461 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
5464 // Recurse into target specific vector shuffles to find scalars.
5465 if (isTargetShuffle(Opcode)) {
5466 MVT ShufVT = V.getSimpleValueType();
5467 unsigned NumElems = ShufVT.getVectorNumElements();
5468 SmallVector<int, 16> ShuffleMask;
5471 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
5474 int Elt = ShuffleMask[Index];
5476 return DAG.getUNDEF(ShufVT.getVectorElementType());
5478 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
5480 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
5484 // Actual nodes that may contain scalar elements
5485 if (Opcode == ISD::BITCAST) {
5486 V = V.getOperand(0);
5487 EVT SrcVT = V.getValueType();
5488 unsigned NumElems = VT.getVectorNumElements();
5490 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5494 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5495 return (Index == 0) ? V.getOperand(0)
5496 : DAG.getUNDEF(VT.getVectorElementType());
5498 if (V.getOpcode() == ISD::BUILD_VECTOR)
5499 return V.getOperand(Index);
5504 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
5505 /// shuffle operation which come from a consecutively from a zero. The
5506 /// search can start in two different directions, from left or right.
5507 /// We count undefs as zeros until PreferredNum is reached.
5508 static unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp,
5509 unsigned NumElems, bool ZerosFromLeft,
5511 unsigned PreferredNum = -1U) {
5512 unsigned NumZeros = 0;
5513 for (unsigned i = 0; i != NumElems; ++i) {
5514 unsigned Index = ZerosFromLeft ? i : NumElems - i - 1;
5515 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
5519 if (X86::isZeroNode(Elt))
5521 else if (Elt.getOpcode() == ISD::UNDEF) // Undef as zero up to PreferredNum.
5522 NumZeros = std::min(NumZeros + 1, PreferredNum);
5530 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
5531 /// correspond consecutively to elements from one of the vector operands,
5532 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
5534 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
5535 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
5536 unsigned NumElems, unsigned &OpNum) {
5537 bool SeenV1 = false;
5538 bool SeenV2 = false;
5540 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
5541 int Idx = SVOp->getMaskElt(i);
5542 // Ignore undef indicies
5546 if (Idx < (int)NumElems)
5551 // Only accept consecutive elements from the same vector
5552 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
5556 OpNum = SeenV1 ? 0 : 1;
5560 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
5561 /// logical left shift of a vector.
5562 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5563 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5565 SVOp->getSimpleValueType(0).getVectorNumElements();
5566 unsigned NumZeros = getNumOfConsecutiveZeros(
5567 SVOp, NumElems, false /* check zeros from right */, DAG,
5568 SVOp->getMaskElt(0));
5574 // Considering the elements in the mask that are not consecutive zeros,
5575 // check if they consecutively come from only one of the source vectors.
5577 // V1 = {X, A, B, C} 0
5579 // vector_shuffle V1, V2 <1, 2, 3, X>
5581 if (!isShuffleMaskConsecutive(SVOp,
5582 0, // Mask Start Index
5583 NumElems-NumZeros, // Mask End Index(exclusive)
5584 NumZeros, // Where to start looking in the src vector
5585 NumElems, // Number of elements in vector
5586 OpSrc)) // Which source operand ?
5591 ShVal = SVOp->getOperand(OpSrc);
5595 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
5596 /// logical left shift of a vector.
5597 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5598 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5600 SVOp->getSimpleValueType(0).getVectorNumElements();
5601 unsigned NumZeros = getNumOfConsecutiveZeros(
5602 SVOp, NumElems, true /* check zeros from left */, DAG,
5603 NumElems - SVOp->getMaskElt(NumElems - 1) - 1);
5609 // Considering the elements in the mask that are not consecutive zeros,
5610 // check if they consecutively come from only one of the source vectors.
5612 // 0 { A, B, X, X } = V2
5614 // vector_shuffle V1, V2 <X, X, 4, 5>
5616 if (!isShuffleMaskConsecutive(SVOp,
5617 NumZeros, // Mask Start Index
5618 NumElems, // Mask End Index(exclusive)
5619 0, // Where to start looking in the src vector
5620 NumElems, // Number of elements in vector
5621 OpSrc)) // Which source operand ?
5626 ShVal = SVOp->getOperand(OpSrc);
5630 /// isVectorShift - Returns true if the shuffle can be implemented as a
5631 /// logical left or right shift of a vector.
5632 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5633 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5634 // Although the logic below support any bitwidth size, there are no
5635 // shift instructions which handle more than 128-bit vectors.
5636 if (!SVOp->getSimpleValueType(0).is128BitVector())
5639 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
5640 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
5646 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
5648 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5649 unsigned NumNonZero, unsigned NumZero,
5651 const X86Subtarget* Subtarget,
5652 const TargetLowering &TLI) {
5659 for (unsigned i = 0; i < 16; ++i) {
5660 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5661 if (ThisIsNonZero && First) {
5663 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5665 V = DAG.getUNDEF(MVT::v8i16);
5670 SDValue ThisElt, LastElt;
5671 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5672 if (LastIsNonZero) {
5673 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5674 MVT::i16, Op.getOperand(i-1));
5676 if (ThisIsNonZero) {
5677 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5678 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5679 ThisElt, DAG.getConstant(8, MVT::i8));
5681 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5685 if (ThisElt.getNode())
5686 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5687 DAG.getIntPtrConstant(i/2));
5691 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
5694 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
5696 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5697 unsigned NumNonZero, unsigned NumZero,
5699 const X86Subtarget* Subtarget,
5700 const TargetLowering &TLI) {
5707 for (unsigned i = 0; i < 8; ++i) {
5708 bool isNonZero = (NonZeros & (1 << i)) != 0;
5712 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5714 V = DAG.getUNDEF(MVT::v8i16);
5717 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5718 MVT::v8i16, V, Op.getOperand(i),
5719 DAG.getIntPtrConstant(i));
5726 /// LowerBuildVectorv4x32 - Custom lower build_vector of v4i32 or v4f32.
5727 static SDValue LowerBuildVectorv4x32(SDValue Op, unsigned NumElems,
5728 unsigned NonZeros, unsigned NumNonZero,
5729 unsigned NumZero, SelectionDAG &DAG,
5730 const X86Subtarget *Subtarget,
5731 const TargetLowering &TLI) {
5732 // We know there's at least one non-zero element
5733 unsigned FirstNonZeroIdx = 0;
5734 SDValue FirstNonZero = Op->getOperand(FirstNonZeroIdx);
5735 while (FirstNonZero.getOpcode() == ISD::UNDEF ||
5736 X86::isZeroNode(FirstNonZero)) {
5738 FirstNonZero = Op->getOperand(FirstNonZeroIdx);
5741 if (FirstNonZero.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5742 !isa<ConstantSDNode>(FirstNonZero.getOperand(1)))
5745 SDValue V = FirstNonZero.getOperand(0);
5746 MVT VVT = V.getSimpleValueType();
5747 if (!Subtarget->hasSSE41() || (VVT != MVT::v4f32 && VVT != MVT::v4i32))
5750 unsigned FirstNonZeroDst =
5751 cast<ConstantSDNode>(FirstNonZero.getOperand(1))->getZExtValue();
5752 unsigned CorrectIdx = FirstNonZeroDst == FirstNonZeroIdx;
5753 unsigned IncorrectIdx = CorrectIdx ? -1U : FirstNonZeroIdx;
5754 unsigned IncorrectDst = CorrectIdx ? -1U : FirstNonZeroDst;
5756 for (unsigned Idx = FirstNonZeroIdx + 1; Idx < NumElems; ++Idx) {
5757 SDValue Elem = Op.getOperand(Idx);
5758 if (Elem.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elem))
5761 // TODO: What else can be here? Deal with it.
5762 if (Elem.getOpcode() != ISD::EXTRACT_VECTOR_ELT)
5765 // TODO: Some optimizations are still possible here
5766 // ex: Getting one element from a vector, and the rest from another.
5767 if (Elem.getOperand(0) != V)
5770 unsigned Dst = cast<ConstantSDNode>(Elem.getOperand(1))->getZExtValue();
5773 else if (IncorrectIdx == -1U) {
5777 // There was already one element with an incorrect index.
5778 // We can't optimize this case to an insertps.
5782 if (NumNonZero == CorrectIdx || NumNonZero == CorrectIdx + 1) {
5784 EVT VT = Op.getSimpleValueType();
5785 unsigned ElementMoveMask = 0;
5786 if (IncorrectIdx == -1U)
5787 ElementMoveMask = FirstNonZeroIdx << 6 | FirstNonZeroIdx << 4;
5789 ElementMoveMask = IncorrectDst << 6 | IncorrectIdx << 4;
5791 SDValue InsertpsMask =
5792 DAG.getIntPtrConstant(ElementMoveMask | (~NonZeros & 0xf));
5793 return DAG.getNode(X86ISD::INSERTPS, dl, VT, V, V, InsertpsMask);
5799 /// getVShift - Return a vector logical shift node.
5801 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5802 unsigned NumBits, SelectionDAG &DAG,
5803 const TargetLowering &TLI, SDLoc dl) {
5804 assert(VT.is128BitVector() && "Unknown type for VShift");
5805 EVT ShVT = MVT::v2i64;
5806 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5807 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
5808 return DAG.getNode(ISD::BITCAST, dl, VT,
5809 DAG.getNode(Opc, dl, ShVT, SrcOp,
5810 DAG.getConstant(NumBits,
5811 TLI.getScalarShiftAmountTy(SrcOp.getValueType()))));
5815 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5817 // Check if the scalar load can be widened into a vector load. And if
5818 // the address is "base + cst" see if the cst can be "absorbed" into
5819 // the shuffle mask.
5820 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5821 SDValue Ptr = LD->getBasePtr();
5822 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5824 EVT PVT = LD->getValueType(0);
5825 if (PVT != MVT::i32 && PVT != MVT::f32)
5830 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5831 FI = FINode->getIndex();
5833 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5834 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5835 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5836 Offset = Ptr.getConstantOperandVal(1);
5837 Ptr = Ptr.getOperand(0);
5842 // FIXME: 256-bit vector instructions don't require a strict alignment,
5843 // improve this code to support it better.
5844 unsigned RequiredAlign = VT.getSizeInBits()/8;
5845 SDValue Chain = LD->getChain();
5846 // Make sure the stack object alignment is at least 16 or 32.
5847 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5848 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5849 if (MFI->isFixedObjectIndex(FI)) {
5850 // Can't change the alignment. FIXME: It's possible to compute
5851 // the exact stack offset and reference FI + adjust offset instead.
5852 // If someone *really* cares about this. That's the way to implement it.
5855 MFI->setObjectAlignment(FI, RequiredAlign);
5859 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5860 // Ptr + (Offset & ~15).
5863 if ((Offset % RequiredAlign) & 3)
5865 int64_t StartOffset = Offset & ~(RequiredAlign-1);
5867 Ptr = DAG.getNode(ISD::ADD, SDLoc(Ptr), Ptr.getValueType(),
5868 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
5870 int EltNo = (Offset - StartOffset) >> 2;
5871 unsigned NumElems = VT.getVectorNumElements();
5873 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5874 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5875 LD->getPointerInfo().getWithOffset(StartOffset),
5876 false, false, false, 0);
5878 SmallVector<int, 8> Mask;
5879 for (unsigned i = 0; i != NumElems; ++i)
5880 Mask.push_back(EltNo);
5882 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5888 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
5889 /// vector of type 'VT', see if the elements can be replaced by a single large
5890 /// load which has the same value as a build_vector whose operands are 'elts'.
5892 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5894 /// FIXME: we'd also like to handle the case where the last elements are zero
5895 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5896 /// There's even a handy isZeroNode for that purpose.
5897 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
5898 SDLoc &DL, SelectionDAG &DAG,
5899 bool isAfterLegalize) {
5900 EVT EltVT = VT.getVectorElementType();
5901 unsigned NumElems = Elts.size();
5903 LoadSDNode *LDBase = nullptr;
5904 unsigned LastLoadedElt = -1U;
5906 // For each element in the initializer, see if we've found a load or an undef.
5907 // If we don't find an initial load element, or later load elements are
5908 // non-consecutive, bail out.
5909 for (unsigned i = 0; i < NumElems; ++i) {
5910 SDValue Elt = Elts[i];
5912 if (!Elt.getNode() ||
5913 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5916 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5918 LDBase = cast<LoadSDNode>(Elt.getNode());
5922 if (Elt.getOpcode() == ISD::UNDEF)
5925 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5926 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
5931 // If we have found an entire vector of loads and undefs, then return a large
5932 // load of the entire vector width starting at the base pointer. If we found
5933 // consecutive loads for the low half, generate a vzext_load node.
5934 if (LastLoadedElt == NumElems - 1) {
5936 if (isAfterLegalize &&
5937 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
5940 SDValue NewLd = SDValue();
5942 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
5943 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5944 LDBase->getPointerInfo(),
5945 LDBase->isVolatile(), LDBase->isNonTemporal(),
5946 LDBase->isInvariant(), 0);
5947 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5948 LDBase->getPointerInfo(),
5949 LDBase->isVolatile(), LDBase->isNonTemporal(),
5950 LDBase->isInvariant(), LDBase->getAlignment());
5952 if (LDBase->hasAnyUseOfValue(1)) {
5953 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5955 SDValue(NewLd.getNode(), 1));
5956 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5957 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5958 SDValue(NewLd.getNode(), 1));
5963 if (NumElems == 4 && LastLoadedElt == 1 &&
5964 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5965 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5966 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5968 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
5969 LDBase->getPointerInfo(),
5970 LDBase->getAlignment(),
5971 false/*isVolatile*/, true/*ReadMem*/,
5974 // Make sure the newly-created LOAD is in the same position as LDBase in
5975 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5976 // update uses of LDBase's output chain to use the TokenFactor.
5977 if (LDBase->hasAnyUseOfValue(1)) {
5978 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5979 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5980 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5981 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5982 SDValue(ResNode.getNode(), 1));
5985 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
5990 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
5991 /// to generate a splat value for the following cases:
5992 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
5993 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
5994 /// a scalar load, or a constant.
5995 /// The VBROADCAST node is returned when a pattern is found,
5996 /// or SDValue() otherwise.
5997 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
5998 SelectionDAG &DAG) {
5999 if (!Subtarget->hasFp256())
6002 MVT VT = Op.getSimpleValueType();
6005 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
6006 "Unsupported vector type for broadcast.");
6011 switch (Op.getOpcode()) {
6013 // Unknown pattern found.
6016 case ISD::BUILD_VECTOR: {
6017 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
6018 BitVector UndefElements;
6019 SDValue Splat = BVOp->getSplatValue(&UndefElements);
6021 // We need a splat of a single value to use broadcast, and it doesn't
6022 // make any sense if the value is only in one element of the vector.
6023 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
6027 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6028 Ld.getOpcode() == ISD::ConstantFP);
6030 // Make sure that all of the users of a non-constant load are from the
6031 // BUILD_VECTOR node.
6032 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
6037 case ISD::VECTOR_SHUFFLE: {
6038 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6040 // Shuffles must have a splat mask where the first element is
6042 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
6045 SDValue Sc = Op.getOperand(0);
6046 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
6047 Sc.getOpcode() != ISD::BUILD_VECTOR) {
6049 if (!Subtarget->hasInt256())
6052 // Use the register form of the broadcast instruction available on AVX2.
6053 if (VT.getSizeInBits() >= 256)
6054 Sc = Extract128BitVector(Sc, 0, DAG, dl);
6055 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
6058 Ld = Sc.getOperand(0);
6059 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6060 Ld.getOpcode() == ISD::ConstantFP);
6062 // The scalar_to_vector node and the suspected
6063 // load node must have exactly one user.
6064 // Constants may have multiple users.
6066 // AVX-512 has register version of the broadcast
6067 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
6068 Ld.getValueType().getSizeInBits() >= 32;
6069 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
6076 bool IsGE256 = (VT.getSizeInBits() >= 256);
6078 // Handle the broadcasting a single constant scalar from the constant pool
6079 // into a vector. On Sandybridge it is still better to load a constant vector
6080 // from the constant pool and not to broadcast it from a scalar.
6081 if (ConstSplatVal && Subtarget->hasInt256()) {
6082 EVT CVT = Ld.getValueType();
6083 assert(!CVT.isVector() && "Must not broadcast a vector type");
6084 unsigned ScalarSize = CVT.getSizeInBits();
6086 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)) {
6087 const Constant *C = nullptr;
6088 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
6089 C = CI->getConstantIntValue();
6090 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
6091 C = CF->getConstantFPValue();
6093 assert(C && "Invalid constant type");
6095 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6096 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
6097 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
6098 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
6099 MachinePointerInfo::getConstantPool(),
6100 false, false, false, Alignment);
6102 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6106 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
6107 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
6109 // Handle AVX2 in-register broadcasts.
6110 if (!IsLoad && Subtarget->hasInt256() &&
6111 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
6112 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6114 // The scalar source must be a normal load.
6118 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64))
6119 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6121 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
6122 // double since there is no vbroadcastsd xmm
6123 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
6124 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
6125 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6128 // Unsupported broadcast.
6132 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
6133 /// underlying vector and index.
6135 /// Modifies \p ExtractedFromVec to the real vector and returns the real
6137 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
6139 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
6140 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
6143 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
6145 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
6147 // (extract_vector_elt (vector_shuffle<2,u,u,u>
6148 // (extract_subvector (v8f32 %vreg0), Constant<4>),
6151 // In this case the vector is the extract_subvector expression and the index
6152 // is 2, as specified by the shuffle.
6153 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
6154 SDValue ShuffleVec = SVOp->getOperand(0);
6155 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
6156 assert(ShuffleVecVT.getVectorElementType() ==
6157 ExtractedFromVec.getSimpleValueType().getVectorElementType());
6159 int ShuffleIdx = SVOp->getMaskElt(Idx);
6160 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
6161 ExtractedFromVec = ShuffleVec;
6167 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
6168 MVT VT = Op.getSimpleValueType();
6170 // Skip if insert_vec_elt is not supported.
6171 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6172 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
6176 unsigned NumElems = Op.getNumOperands();
6180 SmallVector<unsigned, 4> InsertIndices;
6181 SmallVector<int, 8> Mask(NumElems, -1);
6183 for (unsigned i = 0; i != NumElems; ++i) {
6184 unsigned Opc = Op.getOperand(i).getOpcode();
6186 if (Opc == ISD::UNDEF)
6189 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
6190 // Quit if more than 1 elements need inserting.
6191 if (InsertIndices.size() > 1)
6194 InsertIndices.push_back(i);
6198 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
6199 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
6200 // Quit if non-constant index.
6201 if (!isa<ConstantSDNode>(ExtIdx))
6203 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
6205 // Quit if extracted from vector of different type.
6206 if (ExtractedFromVec.getValueType() != VT)
6209 if (!VecIn1.getNode())
6210 VecIn1 = ExtractedFromVec;
6211 else if (VecIn1 != ExtractedFromVec) {
6212 if (!VecIn2.getNode())
6213 VecIn2 = ExtractedFromVec;
6214 else if (VecIn2 != ExtractedFromVec)
6215 // Quit if more than 2 vectors to shuffle
6219 if (ExtractedFromVec == VecIn1)
6221 else if (ExtractedFromVec == VecIn2)
6222 Mask[i] = Idx + NumElems;
6225 if (!VecIn1.getNode())
6228 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
6229 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
6230 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
6231 unsigned Idx = InsertIndices[i];
6232 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
6233 DAG.getIntPtrConstant(Idx));
6239 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
6241 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
6243 MVT VT = Op.getSimpleValueType();
6244 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
6245 "Unexpected type in LowerBUILD_VECTORvXi1!");
6248 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6249 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
6250 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6251 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6254 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
6255 SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
6256 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6257 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6260 bool AllContants = true;
6261 uint64_t Immediate = 0;
6262 int NonConstIdx = -1;
6263 bool IsSplat = true;
6264 unsigned NumNonConsts = 0;
6265 unsigned NumConsts = 0;
6266 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
6267 SDValue In = Op.getOperand(idx);
6268 if (In.getOpcode() == ISD::UNDEF)
6270 if (!isa<ConstantSDNode>(In)) {
6271 AllContants = false;
6277 if (cast<ConstantSDNode>(In)->getZExtValue())
6278 Immediate |= (1ULL << idx);
6280 if (In != Op.getOperand(0))
6285 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
6286 DAG.getConstant(Immediate, MVT::i16));
6287 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
6288 DAG.getIntPtrConstant(0));
6291 if (NumNonConsts == 1 && NonConstIdx != 0) {
6294 SDValue VecAsImm = DAG.getConstant(Immediate,
6295 MVT::getIntegerVT(VT.getSizeInBits()));
6296 DstVec = DAG.getNode(ISD::BITCAST, dl, VT, VecAsImm);
6299 DstVec = DAG.getUNDEF(VT);
6300 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
6301 Op.getOperand(NonConstIdx),
6302 DAG.getIntPtrConstant(NonConstIdx));
6304 if (!IsSplat && (NonConstIdx != 0))
6305 llvm_unreachable("Unsupported BUILD_VECTOR operation");
6306 MVT SelectVT = (VT == MVT::v16i1)? MVT::i16 : MVT::i8;
6309 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6310 DAG.getConstant(-1, SelectVT),
6311 DAG.getConstant(0, SelectVT));
6313 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6314 DAG.getConstant((Immediate | 1), SelectVT),
6315 DAG.getConstant(Immediate, SelectVT));
6316 return DAG.getNode(ISD::BITCAST, dl, VT, Select);
6319 /// \brief Return true if \p N implements a horizontal binop and return the
6320 /// operands for the horizontal binop into V0 and V1.
6322 /// This is a helper function of PerformBUILD_VECTORCombine.
6323 /// This function checks that the build_vector \p N in input implements a
6324 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
6325 /// operation to match.
6326 /// For example, if \p Opcode is equal to ISD::ADD, then this function
6327 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
6328 /// is equal to ISD::SUB, then this function checks if this is a horizontal
6331 /// This function only analyzes elements of \p N whose indices are
6332 /// in range [BaseIdx, LastIdx).
6333 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
6335 unsigned BaseIdx, unsigned LastIdx,
6336 SDValue &V0, SDValue &V1) {
6337 EVT VT = N->getValueType(0);
6339 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
6340 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
6341 "Invalid Vector in input!");
6343 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
6344 bool CanFold = true;
6345 unsigned ExpectedVExtractIdx = BaseIdx;
6346 unsigned NumElts = LastIdx - BaseIdx;
6347 V0 = DAG.getUNDEF(VT);
6348 V1 = DAG.getUNDEF(VT);
6350 // Check if N implements a horizontal binop.
6351 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
6352 SDValue Op = N->getOperand(i + BaseIdx);
6355 if (Op->getOpcode() == ISD::UNDEF) {
6356 // Update the expected vector extract index.
6357 if (i * 2 == NumElts)
6358 ExpectedVExtractIdx = BaseIdx;
6359 ExpectedVExtractIdx += 2;
6363 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
6368 SDValue Op0 = Op.getOperand(0);
6369 SDValue Op1 = Op.getOperand(1);
6371 // Try to match the following pattern:
6372 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
6373 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6374 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6375 Op0.getOperand(0) == Op1.getOperand(0) &&
6376 isa<ConstantSDNode>(Op0.getOperand(1)) &&
6377 isa<ConstantSDNode>(Op1.getOperand(1)));
6381 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6382 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
6384 if (i * 2 < NumElts) {
6385 if (V0.getOpcode() == ISD::UNDEF)
6386 V0 = Op0.getOperand(0);
6388 if (V1.getOpcode() == ISD::UNDEF)
6389 V1 = Op0.getOperand(0);
6390 if (i * 2 == NumElts)
6391 ExpectedVExtractIdx = BaseIdx;
6394 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
6395 if (I0 == ExpectedVExtractIdx)
6396 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
6397 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
6398 // Try to match the following dag sequence:
6399 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
6400 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
6404 ExpectedVExtractIdx += 2;
6410 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
6411 /// a concat_vector.
6413 /// This is a helper function of PerformBUILD_VECTORCombine.
6414 /// This function expects two 256-bit vectors called V0 and V1.
6415 /// At first, each vector is split into two separate 128-bit vectors.
6416 /// Then, the resulting 128-bit vectors are used to implement two
6417 /// horizontal binary operations.
6419 /// The kind of horizontal binary operation is defined by \p X86Opcode.
6421 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
6422 /// the two new horizontal binop.
6423 /// When Mode is set, the first horizontal binop dag node would take as input
6424 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
6425 /// horizontal binop dag node would take as input the lower 128-bit of V1
6426 /// and the upper 128-bit of V1.
6428 /// HADD V0_LO, V0_HI
6429 /// HADD V1_LO, V1_HI
6431 /// Otherwise, the first horizontal binop dag node takes as input the lower
6432 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
6433 /// dag node takes the the upper 128-bit of V0 and the upper 128-bit of V1.
6435 /// HADD V0_LO, V1_LO
6436 /// HADD V0_HI, V1_HI
6438 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
6439 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
6440 /// the upper 128-bits of the result.
6441 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
6442 SDLoc DL, SelectionDAG &DAG,
6443 unsigned X86Opcode, bool Mode,
6444 bool isUndefLO, bool isUndefHI) {
6445 EVT VT = V0.getValueType();
6446 assert(VT.is256BitVector() && VT == V1.getValueType() &&
6447 "Invalid nodes in input!");
6449 unsigned NumElts = VT.getVectorNumElements();
6450 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
6451 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
6452 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
6453 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
6454 EVT NewVT = V0_LO.getValueType();
6456 SDValue LO = DAG.getUNDEF(NewVT);
6457 SDValue HI = DAG.getUNDEF(NewVT);
6460 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6461 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
6462 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
6463 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
6464 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
6466 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6467 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
6468 V1_LO->getOpcode() != ISD::UNDEF))
6469 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
6471 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
6472 V1_HI->getOpcode() != ISD::UNDEF))
6473 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
6476 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
6479 /// \brief Try to fold a build_vector that performs an 'addsub' into the
6480 /// sequence of 'vadd + vsub + blendi'.
6481 static SDValue matchAddSub(const BuildVectorSDNode *BV, SelectionDAG &DAG,
6482 const X86Subtarget *Subtarget) {
6484 EVT VT = BV->getValueType(0);
6485 unsigned NumElts = VT.getVectorNumElements();
6486 SDValue InVec0 = DAG.getUNDEF(VT);
6487 SDValue InVec1 = DAG.getUNDEF(VT);
6489 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
6490 VT == MVT::v2f64) && "build_vector with an invalid type found!");
6492 // Odd-numbered elements in the input build vector are obtained from
6493 // adding two integer/float elements.
6494 // Even-numbered elements in the input build vector are obtained from
6495 // subtracting two integer/float elements.
6496 unsigned ExpectedOpcode = ISD::FSUB;
6497 unsigned NextExpectedOpcode = ISD::FADD;
6498 bool AddFound = false;
6499 bool SubFound = false;
6501 for (unsigned i = 0, e = NumElts; i != e; i++) {
6502 SDValue Op = BV->getOperand(i);
6504 // Skip 'undef' values.
6505 unsigned Opcode = Op.getOpcode();
6506 if (Opcode == ISD::UNDEF) {
6507 std::swap(ExpectedOpcode, NextExpectedOpcode);
6511 // Early exit if we found an unexpected opcode.
6512 if (Opcode != ExpectedOpcode)
6515 SDValue Op0 = Op.getOperand(0);
6516 SDValue Op1 = Op.getOperand(1);
6518 // Try to match the following pattern:
6519 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
6520 // Early exit if we cannot match that sequence.
6521 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6522 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6523 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
6524 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
6525 Op0.getOperand(1) != Op1.getOperand(1))
6528 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6532 // We found a valid add/sub node. Update the information accordingly.
6538 // Update InVec0 and InVec1.
6539 if (InVec0.getOpcode() == ISD::UNDEF)
6540 InVec0 = Op0.getOperand(0);
6541 if (InVec1.getOpcode() == ISD::UNDEF)
6542 InVec1 = Op1.getOperand(0);
6544 // Make sure that operands in input to each add/sub node always
6545 // come from a same pair of vectors.
6546 if (InVec0 != Op0.getOperand(0)) {
6547 if (ExpectedOpcode == ISD::FSUB)
6550 // FADD is commutable. Try to commute the operands
6551 // and then test again.
6552 std::swap(Op0, Op1);
6553 if (InVec0 != Op0.getOperand(0))
6557 if (InVec1 != Op1.getOperand(0))
6560 // Update the pair of expected opcodes.
6561 std::swap(ExpectedOpcode, NextExpectedOpcode);
6564 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
6565 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
6566 InVec1.getOpcode() != ISD::UNDEF)
6567 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
6572 static SDValue PerformBUILD_VECTORCombine(SDNode *N, SelectionDAG &DAG,
6573 const X86Subtarget *Subtarget) {
6575 EVT VT = N->getValueType(0);
6576 unsigned NumElts = VT.getVectorNumElements();
6577 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
6578 SDValue InVec0, InVec1;
6580 // Try to match an ADDSUB.
6581 if ((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
6582 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) {
6583 SDValue Value = matchAddSub(BV, DAG, Subtarget);
6584 if (Value.getNode())
6588 // Try to match horizontal ADD/SUB.
6589 unsigned NumUndefsLO = 0;
6590 unsigned NumUndefsHI = 0;
6591 unsigned Half = NumElts/2;
6593 // Count the number of UNDEF operands in the build_vector in input.
6594 for (unsigned i = 0, e = Half; i != e; ++i)
6595 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6598 for (unsigned i = Half, e = NumElts; i != e; ++i)
6599 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6602 // Early exit if this is either a build_vector of all UNDEFs or all the
6603 // operands but one are UNDEF.
6604 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
6607 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
6608 // Try to match an SSE3 float HADD/HSUB.
6609 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6610 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6612 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6613 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6614 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
6615 // Try to match an SSSE3 integer HADD/HSUB.
6616 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6617 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
6619 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6620 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
6623 if (!Subtarget->hasAVX())
6626 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
6627 // Try to match an AVX horizontal add/sub of packed single/double
6628 // precision floating point values from 256-bit vectors.
6629 SDValue InVec2, InVec3;
6630 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
6631 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
6632 ((InVec0.getOpcode() == ISD::UNDEF ||
6633 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6634 ((InVec1.getOpcode() == ISD::UNDEF ||
6635 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6636 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6638 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
6639 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
6640 ((InVec0.getOpcode() == ISD::UNDEF ||
6641 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6642 ((InVec1.getOpcode() == ISD::UNDEF ||
6643 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6644 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6645 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
6646 // Try to match an AVX2 horizontal add/sub of signed integers.
6647 SDValue InVec2, InVec3;
6649 bool CanFold = true;
6651 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
6652 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
6653 ((InVec0.getOpcode() == ISD::UNDEF ||
6654 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6655 ((InVec1.getOpcode() == ISD::UNDEF ||
6656 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6657 X86Opcode = X86ISD::HADD;
6658 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
6659 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
6660 ((InVec0.getOpcode() == ISD::UNDEF ||
6661 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6662 ((InVec1.getOpcode() == ISD::UNDEF ||
6663 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6664 X86Opcode = X86ISD::HSUB;
6669 // Fold this build_vector into a single horizontal add/sub.
6670 // Do this only if the target has AVX2.
6671 if (Subtarget->hasAVX2())
6672 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
6674 // Do not try to expand this build_vector into a pair of horizontal
6675 // add/sub if we can emit a pair of scalar add/sub.
6676 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6679 // Convert this build_vector into a pair of horizontal binop followed by
6681 bool isUndefLO = NumUndefsLO == Half;
6682 bool isUndefHI = NumUndefsHI == Half;
6683 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
6684 isUndefLO, isUndefHI);
6688 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
6689 VT == MVT::v16i16) && Subtarget->hasAVX()) {
6691 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6692 X86Opcode = X86ISD::HADD;
6693 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6694 X86Opcode = X86ISD::HSUB;
6695 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6696 X86Opcode = X86ISD::FHADD;
6697 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6698 X86Opcode = X86ISD::FHSUB;
6702 // Don't try to expand this build_vector into a pair of horizontal add/sub
6703 // if we can simply emit a pair of scalar add/sub.
6704 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6707 // Convert this build_vector into two horizontal add/sub followed by
6709 bool isUndefLO = NumUndefsLO == Half;
6710 bool isUndefHI = NumUndefsHI == Half;
6711 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
6712 isUndefLO, isUndefHI);
6719 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6722 MVT VT = Op.getSimpleValueType();
6723 MVT ExtVT = VT.getVectorElementType();
6724 unsigned NumElems = Op.getNumOperands();
6726 // Generate vectors for predicate vectors.
6727 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
6728 return LowerBUILD_VECTORvXi1(Op, DAG);
6730 // Vectors containing all zeros can be matched by pxor and xorps later
6731 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6732 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6733 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6734 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6737 return getZeroVector(VT, Subtarget, DAG, dl);
6740 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6741 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6742 // vpcmpeqd on 256-bit vectors.
6743 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6744 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6747 if (!VT.is512BitVector())
6748 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
6751 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
6752 if (Broadcast.getNode())
6755 unsigned EVTBits = ExtVT.getSizeInBits();
6757 unsigned NumZero = 0;
6758 unsigned NumNonZero = 0;
6759 unsigned NonZeros = 0;
6760 bool IsAllConstants = true;
6761 SmallSet<SDValue, 8> Values;
6762 for (unsigned i = 0; i < NumElems; ++i) {
6763 SDValue Elt = Op.getOperand(i);
6764 if (Elt.getOpcode() == ISD::UNDEF)
6767 if (Elt.getOpcode() != ISD::Constant &&
6768 Elt.getOpcode() != ISD::ConstantFP)
6769 IsAllConstants = false;
6770 if (X86::isZeroNode(Elt))
6773 NonZeros |= (1 << i);
6778 // All undef vector. Return an UNDEF. All zero vectors were handled above.
6779 if (NumNonZero == 0)
6780 return DAG.getUNDEF(VT);
6782 // Special case for single non-zero, non-undef, element.
6783 if (NumNonZero == 1) {
6784 unsigned Idx = countTrailingZeros(NonZeros);
6785 SDValue Item = Op.getOperand(Idx);
6787 // If this is an insertion of an i64 value on x86-32, and if the top bits of
6788 // the value are obviously zero, truncate the value to i32 and do the
6789 // insertion that way. Only do this if the value is non-constant or if the
6790 // value is a constant being inserted into element 0. It is cheaper to do
6791 // a constant pool load than it is to do a movd + shuffle.
6792 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6793 (!IsAllConstants || Idx == 0)) {
6794 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6796 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6797 EVT VecVT = MVT::v4i32;
6798 unsigned VecElts = 4;
6800 // Truncate the value (which may itself be a constant) to i32, and
6801 // convert it to a vector with movd (S2V+shuffle to zero extend).
6802 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6803 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6805 // If using the new shuffle lowering, just directly insert this.
6806 if (ExperimentalVectorShuffleLowering)
6808 ISD::BITCAST, dl, VT,
6809 getShuffleVectorZeroOrUndef(Item, Idx * 2, true, Subtarget, DAG));
6811 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6813 // Now we have our 32-bit value zero extended in the low element of
6814 // a vector. If Idx != 0, swizzle it into place.
6816 SmallVector<int, 4> Mask;
6817 Mask.push_back(Idx);
6818 for (unsigned i = 1; i != VecElts; ++i)
6820 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
6823 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6827 // If we have a constant or non-constant insertion into the low element of
6828 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
6829 // the rest of the elements. This will be matched as movd/movq/movss/movsd
6830 // depending on what the source datatype is.
6833 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6835 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
6836 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6837 if (VT.is256BitVector() || VT.is512BitVector()) {
6838 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6839 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6840 Item, DAG.getIntPtrConstant(0));
6842 assert(VT.is128BitVector() && "Expected an SSE value type!");
6843 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6844 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6845 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6848 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6849 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6850 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6851 if (VT.is256BitVector()) {
6852 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6853 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6855 assert(VT.is128BitVector() && "Expected an SSE value type!");
6856 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6858 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6862 // Is it a vector logical left shift?
6863 if (NumElems == 2 && Idx == 1 &&
6864 X86::isZeroNode(Op.getOperand(0)) &&
6865 !X86::isZeroNode(Op.getOperand(1))) {
6866 unsigned NumBits = VT.getSizeInBits();
6867 return getVShift(true, VT,
6868 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6869 VT, Op.getOperand(1)),
6870 NumBits/2, DAG, *this, dl);
6873 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
6876 // Otherwise, if this is a vector with i32 or f32 elements, and the element
6877 // is a non-constant being inserted into an element other than the low one,
6878 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
6879 // movd/movss) to move this into the low element, then shuffle it into
6881 if (EVTBits == 32) {
6882 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6884 // If using the new shuffle lowering, just directly insert this.
6885 if (ExperimentalVectorShuffleLowering)
6886 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
6888 // Turn it into a shuffle of zero and zero-extended scalar to vector.
6889 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
6890 SmallVector<int, 8> MaskVec;
6891 for (unsigned i = 0; i != NumElems; ++i)
6892 MaskVec.push_back(i == Idx ? 0 : 1);
6893 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
6897 // Splat is obviously ok. Let legalizer expand it to a shuffle.
6898 if (Values.size() == 1) {
6899 if (EVTBits == 32) {
6900 // Instead of a shuffle like this:
6901 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
6902 // Check if it's possible to issue this instead.
6903 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
6904 unsigned Idx = countTrailingZeros(NonZeros);
6905 SDValue Item = Op.getOperand(Idx);
6906 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
6907 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6912 // A vector full of immediates; various special cases are already
6913 // handled, so this is best done with a single constant-pool load.
6917 // For AVX-length vectors, build the individual 128-bit pieces and use
6918 // shuffles to put them in place.
6919 if (VT.is256BitVector() || VT.is512BitVector()) {
6920 SmallVector<SDValue, 64> V;
6921 for (unsigned i = 0; i != NumElems; ++i)
6922 V.push_back(Op.getOperand(i));
6924 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
6926 // Build both the lower and upper subvector.
6927 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6928 makeArrayRef(&V[0], NumElems/2));
6929 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6930 makeArrayRef(&V[NumElems / 2], NumElems/2));
6932 // Recreate the wider vector with the lower and upper part.
6933 if (VT.is256BitVector())
6934 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6935 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6938 // Let legalizer expand 2-wide build_vectors.
6939 if (EVTBits == 64) {
6940 if (NumNonZero == 1) {
6941 // One half is zero or undef.
6942 unsigned Idx = countTrailingZeros(NonZeros);
6943 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
6944 Op.getOperand(Idx));
6945 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
6950 // If element VT is < 32 bits, convert it to inserts into a zero vector.
6951 if (EVTBits == 8 && NumElems == 16) {
6952 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
6954 if (V.getNode()) return V;
6957 if (EVTBits == 16 && NumElems == 8) {
6958 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
6960 if (V.getNode()) return V;
6963 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
6964 if (EVTBits == 32 && NumElems == 4) {
6965 SDValue V = LowerBuildVectorv4x32(Op, NumElems, NonZeros, NumNonZero,
6966 NumZero, DAG, Subtarget, *this);
6971 // If element VT is == 32 bits, turn it into a number of shuffles.
6972 SmallVector<SDValue, 8> V(NumElems);
6973 if (NumElems == 4 && NumZero > 0) {
6974 for (unsigned i = 0; i < 4; ++i) {
6975 bool isZero = !(NonZeros & (1 << i));
6977 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
6979 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6982 for (unsigned i = 0; i < 2; ++i) {
6983 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
6986 V[i] = V[i*2]; // Must be a zero vector.
6989 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
6992 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
6995 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
7000 bool Reverse1 = (NonZeros & 0x3) == 2;
7001 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
7005 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
7006 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
7008 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
7011 if (Values.size() > 1 && VT.is128BitVector()) {
7012 // Check for a build vector of consecutive loads.
7013 for (unsigned i = 0; i < NumElems; ++i)
7014 V[i] = Op.getOperand(i);
7016 // Check for elements which are consecutive loads.
7017 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false);
7021 // Check for a build vector from mostly shuffle plus few inserting.
7022 SDValue Sh = buildFromShuffleMostly(Op, DAG);
7026 // For SSE 4.1, use insertps to put the high elements into the low element.
7027 if (getSubtarget()->hasSSE41()) {
7029 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
7030 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
7032 Result = DAG.getUNDEF(VT);
7034 for (unsigned i = 1; i < NumElems; ++i) {
7035 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
7036 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
7037 Op.getOperand(i), DAG.getIntPtrConstant(i));
7042 // Otherwise, expand into a number of unpckl*, start by extending each of
7043 // our (non-undef) elements to the full vector width with the element in the
7044 // bottom slot of the vector (which generates no code for SSE).
7045 for (unsigned i = 0; i < NumElems; ++i) {
7046 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
7047 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7049 V[i] = DAG.getUNDEF(VT);
7052 // Next, we iteratively mix elements, e.g. for v4f32:
7053 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
7054 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
7055 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
7056 unsigned EltStride = NumElems >> 1;
7057 while (EltStride != 0) {
7058 for (unsigned i = 0; i < EltStride; ++i) {
7059 // If V[i+EltStride] is undef and this is the first round of mixing,
7060 // then it is safe to just drop this shuffle: V[i] is already in the
7061 // right place, the one element (since it's the first round) being
7062 // inserted as undef can be dropped. This isn't safe for successive
7063 // rounds because they will permute elements within both vectors.
7064 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
7065 EltStride == NumElems/2)
7068 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
7077 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
7078 // to create 256-bit vectors from two other 128-bit ones.
7079 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7081 MVT ResVT = Op.getSimpleValueType();
7083 assert((ResVT.is256BitVector() ||
7084 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
7086 SDValue V1 = Op.getOperand(0);
7087 SDValue V2 = Op.getOperand(1);
7088 unsigned NumElems = ResVT.getVectorNumElements();
7089 if(ResVT.is256BitVector())
7090 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7092 if (Op.getNumOperands() == 4) {
7093 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
7094 ResVT.getVectorNumElements()/2);
7095 SDValue V3 = Op.getOperand(2);
7096 SDValue V4 = Op.getOperand(3);
7097 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
7098 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
7100 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7103 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7104 MVT LLVM_ATTRIBUTE_UNUSED VT = Op.getSimpleValueType();
7105 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
7106 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
7107 Op.getNumOperands() == 4)));
7109 // AVX can use the vinsertf128 instruction to create 256-bit vectors
7110 // from two other 128-bit ones.
7112 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
7113 return LowerAVXCONCAT_VECTORS(Op, DAG);
7117 //===----------------------------------------------------------------------===//
7118 // Vector shuffle lowering
7120 // This is an experimental code path for lowering vector shuffles on x86. It is
7121 // designed to handle arbitrary vector shuffles and blends, gracefully
7122 // degrading performance as necessary. It works hard to recognize idiomatic
7123 // shuffles and lower them to optimal instruction patterns without leaving
7124 // a framework that allows reasonably efficient handling of all vector shuffle
7126 //===----------------------------------------------------------------------===//
7128 /// \brief Tiny helper function to identify a no-op mask.
7130 /// This is a somewhat boring predicate function. It checks whether the mask
7131 /// array input, which is assumed to be a single-input shuffle mask of the kind
7132 /// used by the X86 shuffle instructions (not a fully general
7133 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
7134 /// in-place shuffle are 'no-op's.
7135 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
7136 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7137 if (Mask[i] != -1 && Mask[i] != i)
7142 /// \brief Helper function to classify a mask as a single-input mask.
7144 /// This isn't a generic single-input test because in the vector shuffle
7145 /// lowering we canonicalize single inputs to be the first input operand. This
7146 /// means we can more quickly test for a single input by only checking whether
7147 /// an input from the second operand exists. We also assume that the size of
7148 /// mask corresponds to the size of the input vectors which isn't true in the
7149 /// fully general case.
7150 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
7152 if (M >= (int)Mask.size())
7157 // Hide this symbol with an anonymous namespace instead of 'static' so that MSVC
7158 // 2013 will allow us to use it as a non-type template parameter.
7161 /// \brief Implementation of the \c isShuffleEquivalent variadic functor.
7163 /// See its documentation for details.
7164 bool isShuffleEquivalentImpl(ArrayRef<int> Mask, ArrayRef<const int *> Args) {
7165 if (Mask.size() != Args.size())
7167 for (int i = 0, e = Mask.size(); i < e; ++i) {
7168 assert(*Args[i] >= 0 && "Arguments must be positive integers!");
7169 assert(*Args[i] < (int)Args.size() * 2 &&
7170 "Argument outside the range of possible shuffle inputs!");
7171 if (Mask[i] != -1 && Mask[i] != *Args[i])
7179 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
7182 /// This is a fast way to test a shuffle mask against a fixed pattern:
7184 /// if (isShuffleEquivalent(Mask, 3, 2, 1, 0)) { ... }
7186 /// It returns true if the mask is exactly as wide as the argument list, and
7187 /// each element of the mask is either -1 (signifying undef) or the value given
7188 /// in the argument.
7189 static const VariadicFunction1<
7190 bool, ArrayRef<int>, int, isShuffleEquivalentImpl> isShuffleEquivalent = {};
7192 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
7194 /// This helper function produces an 8-bit shuffle immediate corresponding to
7195 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
7196 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
7199 /// NB: We rely heavily on "undef" masks preserving the input lane.
7200 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask,
7201 SelectionDAG &DAG) {
7202 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
7203 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
7204 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
7205 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
7206 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
7209 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
7210 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
7211 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
7212 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
7213 return DAG.getConstant(Imm, MVT::i8);
7216 /// \brief Try to emit a blend instruction for a shuffle.
7218 /// This doesn't do any checks for the availability of instructions for blending
7219 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
7220 /// be matched in the backend with the type given. What it does check for is
7221 /// that the shuffle mask is in fact a blend.
7222 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
7223 SDValue V2, ArrayRef<int> Mask,
7224 SelectionDAG &DAG) {
7226 unsigned BlendMask = 0;
7227 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7228 if (Mask[i] >= Size) {
7229 if (Mask[i] != i + Size)
7230 return SDValue(); // Shuffled V2 input!
7231 BlendMask |= 1u << i;
7234 if (Mask[i] >= 0 && Mask[i] != i)
7235 return SDValue(); // Shuffled V1 input!
7237 if (VT == MVT::v4f32 || VT == MVT::v2f64)
7238 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
7239 DAG.getConstant(BlendMask, MVT::i8));
7240 assert(!VT.isFloatingPoint() && "Only v4f32 and v2f64 are supported!");
7242 // For integer shuffles we need to expand the mask and cast the inputs to
7243 // v8i16s prior to blending.
7244 assert((VT == MVT::v8i16 || VT == MVT::v4i32 || VT == MVT::v2i64) &&
7245 "Not a supported integer vector type!");
7246 int Scale = 8 / VT.getVectorNumElements();
7248 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7249 if (Mask[i] >= Size)
7250 for (int j = 0; j < Scale; ++j)
7251 BlendMask |= 1u << (i * Scale + j);
7253 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
7254 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
7255 return DAG.getNode(ISD::BITCAST, DL, VT,
7256 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
7257 DAG.getConstant(BlendMask, MVT::i8)));
7260 /// \brief Try to lower a vector shuffle as a byte rotation.
7262 /// We have a generic PALIGNR instruction in x86 that will do an arbitrary
7263 /// byte-rotation of a the concatentation of two vectors. This routine will
7264 /// try to generically lower a vector shuffle through such an instruction. It
7265 /// does not check for the availability of PALIGNR-based lowerings, only the
7266 /// applicability of this strategy to the given mask. This matches shuffle
7267 /// vectors that look like:
7269 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
7271 /// Essentially it concatenates V1 and V2, shifts right by some number of
7272 /// elements, and takes the low elements as the result. Note that while this is
7273 /// specified as a *right shift* because x86 is little-endian, it is a *left
7274 /// rotate* of the vector lanes.
7276 /// Note that this only handles 128-bit vector widths currently.
7277 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
7280 SelectionDAG &DAG) {
7281 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7283 // We need to detect various ways of spelling a rotation:
7284 // [11, 12, 13, 14, 15, 0, 1, 2]
7285 // [-1, 12, 13, 14, -1, -1, 1, -1]
7286 // [-1, -1, -1, -1, -1, -1, 1, 2]
7287 // [ 3, 4, 5, 6, 7, 8, 9, 10]
7288 // [-1, 4, 5, 6, -1, -1, 9, -1]
7289 // [-1, 4, 5, 6, -1, -1, -1, -1]
7292 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7295 assert(Mask[i] >= 0 && "Only -1 is a valid negative mask element!");
7297 // Based on the mod-Size value of this mask element determine where
7298 // a rotated vector would have started.
7299 int StartIdx = i - (Mask[i] % Size);
7301 // The identity rotation isn't interesting, stop.
7304 // If we found the tail of a vector the rotation must be the missing
7305 // front. If we found the head of a vector, it must be how much of the head.
7306 int CandidateRotation = StartIdx < 0 ? -StartIdx : Size - StartIdx;
7309 Rotation = CandidateRotation;
7310 else if (Rotation != CandidateRotation)
7311 // The rotations don't match, so we can't match this mask.
7314 // Compute which value this mask is pointing at.
7315 SDValue MaskV = Mask[i] < Size ? V1 : V2;
7317 // Compute which of the two target values this index should be assigned to.
7318 // This reflects whether the high elements are remaining or the low elements
7320 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
7322 // Either set up this value if we've not encountered it before, or check
7323 // that it remains consistent.
7326 else if (TargetV != MaskV)
7327 // This may be a rotation, but it pulls from the inputs in some
7328 // unsupported interleaving.
7332 // Check that we successfully analyzed the mask, and normalize the results.
7333 assert(Rotation != 0 && "Failed to locate a viable rotation!");
7334 assert((Lo || Hi) && "Failed to find a rotated input vector!");
7340 // Cast the inputs to v16i8 to match PALIGNR.
7341 Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Lo);
7342 Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Hi);
7344 assert(VT.getSizeInBits() == 128 &&
7345 "Rotate-based lowering only supports 128-bit lowering!");
7346 assert(Mask.size() <= 16 &&
7347 "Can shuffle at most 16 bytes in a 128-bit vector!");
7348 // The actual rotate instruction rotates bytes, so we need to scale the
7349 // rotation based on how many bytes are in the vector.
7350 int Scale = 16 / Mask.size();
7352 return DAG.getNode(ISD::BITCAST, DL, VT,
7353 DAG.getNode(X86ISD::PALIGNR, DL, MVT::v16i8, Hi, Lo,
7354 DAG.getConstant(Rotation * Scale, MVT::i8)));
7357 /// \brief Compute whether each element of a shuffle is zeroable.
7359 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
7360 /// Either it is an undef element in the shuffle mask, the element of the input
7361 /// referenced is undef, or the element of the input referenced is known to be
7362 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
7363 /// as many lanes with this technique as possible to simplify the remaining
7365 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
7366 SDValue V1, SDValue V2) {
7367 SmallBitVector Zeroable(Mask.size(), false);
7369 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
7370 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
7372 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7374 // Handle the easy cases.
7375 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
7380 // If this is an index into a build_vector node, dig out the input value and
7382 SDValue V = M < Size ? V1 : V2;
7383 if (V.getOpcode() != ISD::BUILD_VECTOR)
7386 SDValue Input = V.getOperand(M % Size);
7387 // The UNDEF opcode check really should be dead code here, but not quite
7388 // worth asserting on (it isn't invalid, just unexpected).
7389 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
7396 /// \brief Lower a vector shuffle as a zero or any extension.
7398 /// Given a specific number of elements, element bit width, and extension
7399 /// stride, produce either a zero or any extension based on the available
7400 /// features of the subtarget.
7401 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7402 SDLoc DL, MVT VT, int NumElements, int Scale, bool AnyExt, SDValue InputV,
7403 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7404 assert(Scale > 1 && "Need a scale to extend.");
7405 int EltBits = VT.getSizeInBits() / NumElements;
7406 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
7407 "Only 8, 16, and 32 bit elements can be extended.");
7408 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
7410 // Found a valid zext mask! Try various lowering strategies based on the
7411 // input type and available ISA extensions.
7412 if (Subtarget->hasSSE41()) {
7413 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7414 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
7415 NumElements / Scale);
7416 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7417 return DAG.getNode(ISD::BITCAST, DL, VT,
7418 DAG.getNode(X86ISD::VZEXT, DL, ExtVT, InputV));
7421 // For any extends we can cheat for larger element sizes and use shuffle
7422 // instructions that can fold with a load and/or copy.
7423 if (AnyExt && EltBits == 32) {
7424 int PSHUFDMask[4] = {0, -1, 1, -1};
7426 ISD::BITCAST, DL, VT,
7427 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7428 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7429 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
7431 if (AnyExt && EltBits == 16 && Scale > 2) {
7432 int PSHUFDMask[4] = {0, -1, 0, -1};
7433 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7434 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7435 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG));
7436 int PSHUFHWMask[4] = {1, -1, -1, -1};
7438 ISD::BITCAST, DL, VT,
7439 DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16,
7440 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, InputV),
7441 getV4X86ShuffleImm8ForMask(PSHUFHWMask, DAG)));
7444 // If this would require more than 2 unpack instructions to expand, use
7445 // pshufb when available. We can only use more than 2 unpack instructions
7446 // when zero extending i8 elements which also makes it easier to use pshufb.
7447 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
7448 assert(NumElements == 16 && "Unexpected byte vector width!");
7449 SDValue PSHUFBMask[16];
7450 for (int i = 0; i < 16; ++i)
7452 DAG.getConstant((i % Scale == 0) ? i / Scale : 0x80, MVT::i8);
7453 InputV = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, InputV);
7454 return DAG.getNode(ISD::BITCAST, DL, VT,
7455 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
7456 DAG.getNode(ISD::BUILD_VECTOR, DL,
7457 MVT::v16i8, PSHUFBMask)));
7460 // Otherwise emit a sequence of unpacks.
7462 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7463 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
7464 : getZeroVector(InputVT, Subtarget, DAG, DL);
7465 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7466 InputV = DAG.getNode(X86ISD::UNPCKL, DL, InputVT, InputV, Ext);
7470 } while (Scale > 1);
7471 return DAG.getNode(ISD::BITCAST, DL, VT, InputV);
7474 /// \brief Try to lower a vector shuffle as a zero extension on any micrarch.
7476 /// This routine will try to do everything in its power to cleverly lower
7477 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
7478 /// check for the profitability of this lowering, it tries to aggressively
7479 /// match this pattern. It will use all of the micro-architectural details it
7480 /// can to emit an efficient lowering. It handles both blends with all-zero
7481 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
7482 /// masking out later).
7484 /// The reason we have dedicated lowering for zext-style shuffles is that they
7485 /// are both incredibly common and often quite performance sensitive.
7486 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
7487 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7488 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7489 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7491 int Bits = VT.getSizeInBits();
7492 int NumElements = Mask.size();
7494 // Define a helper function to check a particular ext-scale and lower to it if
7496 auto Lower = [&](int Scale) -> SDValue {
7499 for (int i = 0; i < NumElements; ++i) {
7501 continue; // Valid anywhere but doesn't tell us anything.
7502 if (i % Scale != 0) {
7503 // Each of the extend elements needs to be zeroable.
7507 // We no lorger are in the anyext case.
7512 // Each of the base elements needs to be consecutive indices into the
7513 // same input vector.
7514 SDValue V = Mask[i] < NumElements ? V1 : V2;
7517 else if (InputV != V)
7518 return SDValue(); // Flip-flopping inputs.
7520 if (Mask[i] % NumElements != i / Scale)
7521 return SDValue(); // Non-consecutive strided elemenst.
7524 // If we fail to find an input, we have a zero-shuffle which should always
7525 // have already been handled.
7526 // FIXME: Maybe handle this here in case during blending we end up with one?
7530 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7531 DL, VT, NumElements, Scale, AnyExt, InputV, Subtarget, DAG);
7534 // The widest scale possible for extending is to a 64-bit integer.
7535 assert(Bits % 64 == 0 &&
7536 "The number of bits in a vector must be divisible by 64 on x86!");
7537 int NumExtElements = Bits / 64;
7539 // Each iteration, try extending the elements half as much, but into twice as
7541 for (; NumExtElements < NumElements; NumExtElements *= 2) {
7542 assert(NumElements % NumExtElements == 0 &&
7543 "The input vector size must be divisble by the extended size.");
7544 if (SDValue V = Lower(NumElements / NumExtElements))
7548 // No viable ext lowering found.
7552 /// \brief Try to lower insertion of a single element into a zero vector.
7554 /// This is a common pattern that we have especially efficient patterns to lower
7555 /// across all subtarget feature sets.
7556 static SDValue lowerVectorShuffleAsElementInsertion(
7557 MVT VT, SDLoc DL, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7558 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7559 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7561 int V2Index = std::find_if(Mask.begin(), Mask.end(),
7562 [&Mask](int M) { return M >= (int)Mask.size(); }) -
7564 if (Mask.size() == 2) {
7565 if (!Zeroable[V2Index ^ 1]) {
7566 // For 2-wide masks we may be able to just invert the inputs. We use an xor
7567 // with 2 to flip from {2,3} to {0,1} and vice versa.
7568 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
7569 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
7570 if (Zeroable[V2Index])
7571 return lowerVectorShuffleAsElementInsertion(VT, DL, V2, V1, InverseMask,
7577 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7578 if (i != V2Index && !Zeroable[i])
7579 return SDValue(); // Not inserting into a zero vector.
7582 // Step over any bitcasts on either input so we can scan the actual
7583 // BUILD_VECTOR nodes.
7584 while (V1.getOpcode() == ISD::BITCAST)
7585 V1 = V1.getOperand(0);
7586 while (V2.getOpcode() == ISD::BITCAST)
7587 V2 = V2.getOperand(0);
7589 // Check for a single input from a SCALAR_TO_VECTOR node.
7590 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
7591 // all the smarts here sunk into that routine. However, the current
7592 // lowering of BUILD_VECTOR makes that nearly impossible until the old
7593 // vector shuffle lowering is dead.
7594 if (!((V2.getOpcode() == ISD::SCALAR_TO_VECTOR &&
7595 Mask[V2Index] == (int)Mask.size()) ||
7596 V2.getOpcode() == ISD::BUILD_VECTOR))
7599 SDValue V2S = V2.getOperand(Mask[V2Index] - Mask.size());
7601 // First, we need to zext the scalar if it is smaller than an i32.
7603 MVT EltVT = VT.getVectorElementType();
7604 V2S = DAG.getNode(ISD::BITCAST, DL, EltVT, V2S);
7605 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
7606 // Zero-extend directly to i32.
7608 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
7611 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT,
7612 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S));
7614 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
7617 // If we have 4 or fewer lanes we can cheaply shuffle the element into
7618 // the desired position. Otherwise it is more efficient to do a vector
7619 // shift left. We know that we can do a vector shift left because all
7620 // the inputs are zero.
7621 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
7622 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
7623 V2Shuffle[V2Index] = 0;
7624 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
7626 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, V2);
7628 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
7630 V2Index * EltVT.getSizeInBits(),
7631 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(MVT::v2i64)));
7632 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
7638 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
7640 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
7641 /// support for floating point shuffles but not integer shuffles. These
7642 /// instructions will incur a domain crossing penalty on some chips though so
7643 /// it is better to avoid lowering through this for integer vectors where
7645 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7646 const X86Subtarget *Subtarget,
7647 SelectionDAG &DAG) {
7649 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
7650 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7651 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7652 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7653 ArrayRef<int> Mask = SVOp->getMask();
7654 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7656 if (isSingleInputShuffleMask(Mask)) {
7657 // Straight shuffle of a single input vector. Simulate this by using the
7658 // single input as both of the "inputs" to this instruction..
7659 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
7661 if (Subtarget->hasAVX()) {
7662 // If we have AVX, we can use VPERMILPS which will allow folding a load
7663 // into the shuffle.
7664 return DAG.getNode(X86ISD::VPERMILP, DL, MVT::v2f64, V1,
7665 DAG.getConstant(SHUFPDMask, MVT::i8));
7668 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V1,
7669 DAG.getConstant(SHUFPDMask, MVT::i8));
7671 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
7672 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
7674 // Use dedicated unpack instructions for masks that match their pattern.
7675 if (isShuffleEquivalent(Mask, 0, 2))
7676 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2f64, V1, V2);
7677 if (isShuffleEquivalent(Mask, 1, 3))
7678 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2f64, V1, V2);
7680 // If we have a single input, insert that into V1 if we can do so cheaply.
7681 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1)
7682 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7683 MVT::v2f64, DL, V1, V2, Mask, Subtarget, DAG))
7686 if (Subtarget->hasSSE41())
7688 lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask, DAG))
7691 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
7692 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V2,
7693 DAG.getConstant(SHUFPDMask, MVT::i8));
7696 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
7698 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
7699 /// the integer unit to minimize domain crossing penalties. However, for blends
7700 /// it falls back to the floating point shuffle operation with appropriate bit
7702 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7703 const X86Subtarget *Subtarget,
7704 SelectionDAG &DAG) {
7706 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
7707 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7708 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7709 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7710 ArrayRef<int> Mask = SVOp->getMask();
7711 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7713 if (isSingleInputShuffleMask(Mask)) {
7714 // Straight shuffle of a single input vector. For everything from SSE2
7715 // onward this has a single fast instruction with no scary immediates.
7716 // We have to map the mask as it is actually a v4i32 shuffle instruction.
7717 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V1);
7718 int WidenedMask[4] = {
7719 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
7720 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
7722 ISD::BITCAST, DL, MVT::v2i64,
7723 DAG.getNode(X86ISD::PSHUFD, SDLoc(Op), MVT::v4i32, V1,
7724 getV4X86ShuffleImm8ForMask(WidenedMask, DAG)));
7727 // Use dedicated unpack instructions for masks that match their pattern.
7728 if (isShuffleEquivalent(Mask, 0, 2))
7729 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, V1, V2);
7730 if (isShuffleEquivalent(Mask, 1, 3))
7731 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2i64, V1, V2);
7733 // If we have a single input from V2 insert that into V1 if we can do so
7735 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1)
7736 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7737 MVT::v2i64, DL, V1, V2, Mask, Subtarget, DAG))
7740 if (Subtarget->hasSSE41())
7742 lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask, DAG))
7745 // Try to use rotation instructions if available.
7746 if (Subtarget->hasSSSE3())
7747 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
7748 DL, MVT::v2i64, V1, V2, Mask, DAG))
7751 // We implement this with SHUFPD which is pretty lame because it will likely
7752 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
7753 // However, all the alternatives are still more cycles and newer chips don't
7754 // have this problem. It would be really nice if x86 had better shuffles here.
7755 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V1);
7756 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V2);
7757 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7758 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
7761 /// \brief Lower 4-lane 32-bit floating point shuffles.
7763 /// Uses instructions exclusively from the floating point unit to minimize
7764 /// domain crossing penalties, as these are sufficient to implement all v4f32
7766 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7767 const X86Subtarget *Subtarget,
7768 SelectionDAG &DAG) {
7770 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
7771 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7772 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7773 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7774 ArrayRef<int> Mask = SVOp->getMask();
7775 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7777 SDValue LowV = V1, HighV = V2;
7778 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
7781 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
7783 if (NumV2Elements == 0) {
7784 if (Subtarget->hasAVX()) {
7785 // If we have AVX, we can use VPERMILPS which will allow folding a load
7786 // into the shuffle.
7787 return DAG.getNode(X86ISD::VPERMILP, DL, MVT::v4f32, V1,
7788 getV4X86ShuffleImm8ForMask(Mask, DAG));
7791 // Otherwise, use a straight shuffle of a single input vector. We pass the
7792 // input vector to both operands to simulate this with a SHUFPS.
7793 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
7794 getV4X86ShuffleImm8ForMask(Mask, DAG));
7797 // Use dedicated unpack instructions for masks that match their pattern.
7798 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
7799 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V1, V2);
7800 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
7801 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V1, V2);
7803 // There are special ways we can lower some single-element blends. However, we
7804 // have custom ways we can lower more complex single-element blends below that
7805 // we defer to if both this and BLENDPS fail to match, so restrict this to
7806 // when the V2 input is targeting element 0 of the mask -- that is the fast
7808 if (NumV2Elements == 1 && Mask[0] >= 4)
7809 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4f32, DL, V1, V2,
7810 Mask, Subtarget, DAG))
7813 if (Subtarget->hasSSE41())
7815 lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask, DAG))
7818 if (NumV2Elements == 1) {
7820 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
7823 // Check for whether we can use INSERTPS to perform the blend. We only use
7824 // INSERTPS when the V1 elements are already in the correct locations
7825 // because otherwise we can just always use two SHUFPS instructions which
7826 // are much smaller to encode than a SHUFPS and an INSERTPS.
7827 if (Subtarget->hasSSE41()) {
7828 // When using INSERTPS we can zero any lane of the destination. Collect
7829 // the zero inputs into a mask and drop them from the lanes of V1 which
7830 // actually need to be present as inputs to the INSERTPS.
7831 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7833 // Synthesize a shuffle mask for the non-zero and non-v2 inputs.
7834 bool InsertNeedsShuffle = false;
7836 for (int i = 0; i < 4; ++i)
7840 } else if (Mask[i] != i) {
7841 InsertNeedsShuffle = true;
7846 // We don't want to use INSERTPS or other insertion techniques if it will
7847 // require shuffling anyways.
7848 if (!InsertNeedsShuffle) {
7849 // If all of V1 is zeroable, replace it with undef.
7850 if ((ZMask | 1 << V2Index) == 0xF)
7851 V1 = DAG.getUNDEF(MVT::v4f32);
7853 unsigned InsertPSMask = (Mask[V2Index] - 4) << 6 | V2Index << 4 | ZMask;
7854 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
7856 // Insert the V2 element into the desired position.
7857 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
7858 DAG.getConstant(InsertPSMask, MVT::i8));
7862 // Compute the index adjacent to V2Index and in the same half by toggling
7864 int V2AdjIndex = V2Index ^ 1;
7866 if (Mask[V2AdjIndex] == -1) {
7867 // Handles all the cases where we have a single V2 element and an undef.
7868 // This will only ever happen in the high lanes because we commute the
7869 // vector otherwise.
7871 std::swap(LowV, HighV);
7872 NewMask[V2Index] -= 4;
7874 // Handle the case where the V2 element ends up adjacent to a V1 element.
7875 // To make this work, blend them together as the first step.
7876 int V1Index = V2AdjIndex;
7877 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
7878 V2 = DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V2, V1,
7879 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
7881 // Now proceed to reconstruct the final blend as we have the necessary
7882 // high or low half formed.
7889 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
7890 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
7892 } else if (NumV2Elements == 2) {
7893 if (Mask[0] < 4 && Mask[1] < 4) {
7894 // Handle the easy case where we have V1 in the low lanes and V2 in the
7895 // high lanes. We never see this reversed because we sort the shuffle.
7899 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
7900 // trying to place elements directly, just blend them and set up the final
7901 // shuffle to place them.
7903 // The first two blend mask elements are for V1, the second two are for
7905 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
7906 Mask[2] < 4 ? Mask[2] : Mask[3],
7907 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
7908 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
7909 V1 = DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V2,
7910 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
7912 // Now we do a normal shuffle of V1 by giving V1 as both operands to
7915 NewMask[0] = Mask[0] < 4 ? 0 : 2;
7916 NewMask[1] = Mask[0] < 4 ? 2 : 0;
7917 NewMask[2] = Mask[2] < 4 ? 1 : 3;
7918 NewMask[3] = Mask[2] < 4 ? 3 : 1;
7921 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, LowV, HighV,
7922 getV4X86ShuffleImm8ForMask(NewMask, DAG));
7925 /// \brief Lower 4-lane i32 vector shuffles.
7927 /// We try to handle these with integer-domain shuffles where we can, but for
7928 /// blends we use the floating point domain blend instructions.
7929 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7930 const X86Subtarget *Subtarget,
7931 SelectionDAG &DAG) {
7933 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
7934 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
7935 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
7936 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7937 ArrayRef<int> Mask = SVOp->getMask();
7938 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7941 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
7943 if (NumV2Elements == 0) {
7944 // Straight shuffle of a single input vector. For everything from SSE2
7945 // onward this has a single fast instruction with no scary immediates.
7946 // We coerce the shuffle pattern to be compatible with UNPCK instructions
7947 // but we aren't actually going to use the UNPCK instruction because doing
7948 // so prevents folding a load into this instruction or making a copy.
7949 const int UnpackLoMask[] = {0, 0, 1, 1};
7950 const int UnpackHiMask[] = {2, 2, 3, 3};
7951 if (isShuffleEquivalent(Mask, 0, 0, 1, 1))
7952 Mask = UnpackLoMask;
7953 else if (isShuffleEquivalent(Mask, 2, 2, 3, 3))
7954 Mask = UnpackHiMask;
7956 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
7957 getV4X86ShuffleImm8ForMask(Mask, DAG));
7960 // Whenever we can lower this as a zext, that instruction is strictly faster
7961 // than any alternative.
7962 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
7963 Mask, Subtarget, DAG))
7966 // Use dedicated unpack instructions for masks that match their pattern.
7967 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
7968 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V1, V2);
7969 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
7970 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V1, V2);
7972 // There are special ways we can lower some single-element blends.
7973 if (NumV2Elements == 1)
7974 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4i32, DL, V1, V2,
7975 Mask, Subtarget, DAG))
7978 if (Subtarget->hasSSE41())
7980 lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask, DAG))
7983 // Try to use rotation instructions if available.
7984 if (Subtarget->hasSSSE3())
7985 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
7986 DL, MVT::v4i32, V1, V2, Mask, DAG))
7989 // We implement this with SHUFPS because it can blend from two vectors.
7990 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
7991 // up the inputs, bypassing domain shift penalties that we would encur if we
7992 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
7994 return DAG.getNode(ISD::BITCAST, DL, MVT::v4i32,
7995 DAG.getVectorShuffle(
7997 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V1),
7998 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V2), Mask));
8001 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
8002 /// shuffle lowering, and the most complex part.
8004 /// The lowering strategy is to try to form pairs of input lanes which are
8005 /// targeted at the same half of the final vector, and then use a dword shuffle
8006 /// to place them onto the right half, and finally unpack the paired lanes into
8007 /// their final position.
8009 /// The exact breakdown of how to form these dword pairs and align them on the
8010 /// correct sides is really tricky. See the comments within the function for
8011 /// more of the details.
8012 static SDValue lowerV8I16SingleInputVectorShuffle(
8013 SDLoc DL, SDValue V, MutableArrayRef<int> Mask,
8014 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
8015 assert(V.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8016 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
8017 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
8019 SmallVector<int, 4> LoInputs;
8020 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
8021 [](int M) { return M >= 0; });
8022 std::sort(LoInputs.begin(), LoInputs.end());
8023 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
8024 SmallVector<int, 4> HiInputs;
8025 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
8026 [](int M) { return M >= 0; });
8027 std::sort(HiInputs.begin(), HiInputs.end());
8028 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
8030 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
8031 int NumHToL = LoInputs.size() - NumLToL;
8033 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
8034 int NumHToH = HiInputs.size() - NumLToH;
8035 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
8036 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
8037 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
8038 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
8040 // Use dedicated unpack instructions for masks that match their pattern.
8041 if (isShuffleEquivalent(Mask, 0, 0, 1, 1, 2, 2, 3, 3))
8042 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V, V);
8043 if (isShuffleEquivalent(Mask, 4, 4, 5, 5, 6, 6, 7, 7))
8044 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V, V);
8046 // Try to use rotation instructions if available.
8047 if (Subtarget->hasSSSE3())
8048 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8049 DL, MVT::v8i16, V, V, Mask, DAG))
8052 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
8053 // such inputs we can swap two of the dwords across the half mark and end up
8054 // with <=2 inputs to each half in each half. Once there, we can fall through
8055 // to the generic code below. For example:
8057 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8058 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
8060 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
8061 // and an existing 2-into-2 on the other half. In this case we may have to
8062 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
8063 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
8064 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
8065 // because any other situation (including a 3-into-1 or 1-into-3 in the other
8066 // half than the one we target for fixing) will be fixed when we re-enter this
8067 // path. We will also combine away any sequence of PSHUFD instructions that
8068 // result into a single instruction. Here is an example of the tricky case:
8070 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8071 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
8073 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
8075 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
8076 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
8078 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
8079 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
8081 // The result is fine to be handled by the generic logic.
8082 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
8083 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
8084 int AOffset, int BOffset) {
8085 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
8086 "Must call this with A having 3 or 1 inputs from the A half.");
8087 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
8088 "Must call this with B having 1 or 3 inputs from the B half.");
8089 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
8090 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
8092 // Compute the index of dword with only one word among the three inputs in
8093 // a half by taking the sum of the half with three inputs and subtracting
8094 // the sum of the actual three inputs. The difference is the remaining
8097 int &TripleDWord = AToAInputs.size() == 3 ? ADWord : BDWord;
8098 int &OneInputDWord = AToAInputs.size() == 3 ? BDWord : ADWord;
8099 int TripleInputOffset = AToAInputs.size() == 3 ? AOffset : BOffset;
8100 ArrayRef<int> TripleInputs = AToAInputs.size() == 3 ? AToAInputs : BToAInputs;
8101 int OneInput = AToAInputs.size() == 3 ? BToAInputs[0] : AToAInputs[0];
8102 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
8103 int TripleNonInputIdx =
8104 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
8105 TripleDWord = TripleNonInputIdx / 2;
8107 // We use xor with one to compute the adjacent DWord to whichever one the
8109 OneInputDWord = (OneInput / 2) ^ 1;
8111 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
8112 // and BToA inputs. If there is also such a problem with the BToB and AToB
8113 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
8114 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
8115 // is essential that we don't *create* a 3<-1 as then we might oscillate.
8116 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
8117 // Compute how many inputs will be flipped by swapping these DWords. We
8119 // to balance this to ensure we don't form a 3-1 shuffle in the other
8121 int NumFlippedAToBInputs =
8122 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
8123 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
8124 int NumFlippedBToBInputs =
8125 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
8126 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
8127 if ((NumFlippedAToBInputs == 1 &&
8128 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
8129 (NumFlippedBToBInputs == 1 &&
8130 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
8131 // We choose whether to fix the A half or B half based on whether that
8132 // half has zero flipped inputs. At zero, we may not be able to fix it
8133 // with that half. We also bias towards fixing the B half because that
8134 // will more commonly be the high half, and we have to bias one way.
8135 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
8136 ArrayRef<int> Inputs) {
8137 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
8138 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
8139 PinnedIdx ^ 1) != Inputs.end();
8140 // Determine whether the free index is in the flipped dword or the
8141 // unflipped dword based on where the pinned index is. We use this bit
8142 // in an xor to conditionally select the adjacent dword.
8143 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
8144 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8145 FixFreeIdx) != Inputs.end();
8146 if (IsFixIdxInput == IsFixFreeIdxInput)
8148 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8149 FixFreeIdx) != Inputs.end();
8150 assert(IsFixIdxInput != IsFixFreeIdxInput &&
8151 "We need to be changing the number of flipped inputs!");
8152 int PSHUFHalfMask[] = {0, 1, 2, 3};
8153 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
8154 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
8156 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DAG));
8159 if (M != -1 && M == FixIdx)
8161 else if (M != -1 && M == FixFreeIdx)
8164 if (NumFlippedBToBInputs != 0) {
8166 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8167 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
8169 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
8171 AToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8172 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
8177 int PSHUFDMask[] = {0, 1, 2, 3};
8178 PSHUFDMask[ADWord] = BDWord;
8179 PSHUFDMask[BDWord] = ADWord;
8180 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8181 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8182 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8183 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8185 // Adjust the mask to match the new locations of A and B.
8187 if (M != -1 && M/2 == ADWord)
8188 M = 2 * BDWord + M % 2;
8189 else if (M != -1 && M/2 == BDWord)
8190 M = 2 * ADWord + M % 2;
8192 // Recurse back into this routine to re-compute state now that this isn't
8193 // a 3 and 1 problem.
8194 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
8197 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
8198 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
8199 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
8200 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
8202 // At this point there are at most two inputs to the low and high halves from
8203 // each half. That means the inputs can always be grouped into dwords and
8204 // those dwords can then be moved to the correct half with a dword shuffle.
8205 // We use at most one low and one high word shuffle to collect these paired
8206 // inputs into dwords, and finally a dword shuffle to place them.
8207 int PSHUFLMask[4] = {-1, -1, -1, -1};
8208 int PSHUFHMask[4] = {-1, -1, -1, -1};
8209 int PSHUFDMask[4] = {-1, -1, -1, -1};
8211 // First fix the masks for all the inputs that are staying in their
8212 // original halves. This will then dictate the targets of the cross-half
8214 auto fixInPlaceInputs =
8215 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
8216 MutableArrayRef<int> SourceHalfMask,
8217 MutableArrayRef<int> HalfMask, int HalfOffset) {
8218 if (InPlaceInputs.empty())
8220 if (InPlaceInputs.size() == 1) {
8221 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8222 InPlaceInputs[0] - HalfOffset;
8223 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
8226 if (IncomingInputs.empty()) {
8227 // Just fix all of the in place inputs.
8228 for (int Input : InPlaceInputs) {
8229 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
8230 PSHUFDMask[Input / 2] = Input / 2;
8235 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
8236 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8237 InPlaceInputs[0] - HalfOffset;
8238 // Put the second input next to the first so that they are packed into
8239 // a dword. We find the adjacent index by toggling the low bit.
8240 int AdjIndex = InPlaceInputs[0] ^ 1;
8241 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
8242 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
8243 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
8245 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
8246 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
8248 // Now gather the cross-half inputs and place them into a free dword of
8249 // their target half.
8250 // FIXME: This operation could almost certainly be simplified dramatically to
8251 // look more like the 3-1 fixing operation.
8252 auto moveInputsToRightHalf = [&PSHUFDMask](
8253 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
8254 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
8255 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
8257 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
8258 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
8260 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
8262 int LowWord = Word & ~1;
8263 int HighWord = Word | 1;
8264 return isWordClobbered(SourceHalfMask, LowWord) ||
8265 isWordClobbered(SourceHalfMask, HighWord);
8268 if (IncomingInputs.empty())
8271 if (ExistingInputs.empty()) {
8272 // Map any dwords with inputs from them into the right half.
8273 for (int Input : IncomingInputs) {
8274 // If the source half mask maps over the inputs, turn those into
8275 // swaps and use the swapped lane.
8276 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
8277 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
8278 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
8279 Input - SourceOffset;
8280 // We have to swap the uses in our half mask in one sweep.
8281 for (int &M : HalfMask)
8282 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
8284 else if (M == Input)
8285 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8287 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
8288 Input - SourceOffset &&
8289 "Previous placement doesn't match!");
8291 // Note that this correctly re-maps both when we do a swap and when
8292 // we observe the other side of the swap above. We rely on that to
8293 // avoid swapping the members of the input list directly.
8294 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8297 // Map the input's dword into the correct half.
8298 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
8299 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
8301 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
8303 "Previous placement doesn't match!");
8306 // And just directly shift any other-half mask elements to be same-half
8307 // as we will have mirrored the dword containing the element into the
8308 // same position within that half.
8309 for (int &M : HalfMask)
8310 if (M >= SourceOffset && M < SourceOffset + 4) {
8311 M = M - SourceOffset + DestOffset;
8312 assert(M >= 0 && "This should never wrap below zero!");
8317 // Ensure we have the input in a viable dword of its current half. This
8318 // is particularly tricky because the original position may be clobbered
8319 // by inputs being moved and *staying* in that half.
8320 if (IncomingInputs.size() == 1) {
8321 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8322 int InputFixed = std::find(std::begin(SourceHalfMask),
8323 std::end(SourceHalfMask), -1) -
8324 std::begin(SourceHalfMask) + SourceOffset;
8325 SourceHalfMask[InputFixed - SourceOffset] =
8326 IncomingInputs[0] - SourceOffset;
8327 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
8329 IncomingInputs[0] = InputFixed;
8331 } else if (IncomingInputs.size() == 2) {
8332 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
8333 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8334 // We have two non-adjacent or clobbered inputs we need to extract from
8335 // the source half. To do this, we need to map them into some adjacent
8336 // dword slot in the source mask.
8337 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
8338 IncomingInputs[1] - SourceOffset};
8340 // If there is a free slot in the source half mask adjacent to one of
8341 // the inputs, place the other input in it. We use (Index XOR 1) to
8342 // compute an adjacent index.
8343 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
8344 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
8345 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
8346 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8347 InputsFixed[1] = InputsFixed[0] ^ 1;
8348 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
8349 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
8350 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
8351 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
8352 InputsFixed[0] = InputsFixed[1] ^ 1;
8353 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
8354 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
8355 // The two inputs are in the same DWord but it is clobbered and the
8356 // adjacent DWord isn't used at all. Move both inputs to the free
8358 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
8359 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
8360 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
8361 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
8363 // The only way we hit this point is if there is no clobbering
8364 // (because there are no off-half inputs to this half) and there is no
8365 // free slot adjacent to one of the inputs. In this case, we have to
8366 // swap an input with a non-input.
8367 for (int i = 0; i < 4; ++i)
8368 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
8369 "We can't handle any clobbers here!");
8370 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
8371 "Cannot have adjacent inputs here!");
8373 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8374 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
8376 // We also have to update the final source mask in this case because
8377 // it may need to undo the above swap.
8378 for (int &M : FinalSourceHalfMask)
8379 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
8380 M = InputsFixed[1] + SourceOffset;
8381 else if (M == InputsFixed[1] + SourceOffset)
8382 M = (InputsFixed[0] ^ 1) + SourceOffset;
8384 InputsFixed[1] = InputsFixed[0] ^ 1;
8387 // Point everything at the fixed inputs.
8388 for (int &M : HalfMask)
8389 if (M == IncomingInputs[0])
8390 M = InputsFixed[0] + SourceOffset;
8391 else if (M == IncomingInputs[1])
8392 M = InputsFixed[1] + SourceOffset;
8394 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
8395 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
8398 llvm_unreachable("Unhandled input size!");
8401 // Now hoist the DWord down to the right half.
8402 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
8403 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
8404 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
8405 for (int &M : HalfMask)
8406 for (int Input : IncomingInputs)
8408 M = FreeDWord * 2 + Input % 2;
8410 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
8411 /*SourceOffset*/ 4, /*DestOffset*/ 0);
8412 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
8413 /*SourceOffset*/ 0, /*DestOffset*/ 4);
8415 // Now enact all the shuffles we've computed to move the inputs into their
8417 if (!isNoopShuffleMask(PSHUFLMask))
8418 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
8419 getV4X86ShuffleImm8ForMask(PSHUFLMask, DAG));
8420 if (!isNoopShuffleMask(PSHUFHMask))
8421 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
8422 getV4X86ShuffleImm8ForMask(PSHUFHMask, DAG));
8423 if (!isNoopShuffleMask(PSHUFDMask))
8424 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8425 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8426 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8427 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8429 // At this point, each half should contain all its inputs, and we can then
8430 // just shuffle them into their final position.
8431 assert(std::count_if(LoMask.begin(), LoMask.end(),
8432 [](int M) { return M >= 4; }) == 0 &&
8433 "Failed to lift all the high half inputs to the low mask!");
8434 assert(std::count_if(HiMask.begin(), HiMask.end(),
8435 [](int M) { return M >= 0 && M < 4; }) == 0 &&
8436 "Failed to lift all the low half inputs to the high mask!");
8438 // Do a half shuffle for the low mask.
8439 if (!isNoopShuffleMask(LoMask))
8440 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
8441 getV4X86ShuffleImm8ForMask(LoMask, DAG));
8443 // Do a half shuffle with the high mask after shifting its values down.
8444 for (int &M : HiMask)
8447 if (!isNoopShuffleMask(HiMask))
8448 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
8449 getV4X86ShuffleImm8ForMask(HiMask, DAG));
8454 /// \brief Detect whether the mask pattern should be lowered through
8457 /// This essentially tests whether viewing the mask as an interleaving of two
8458 /// sub-sequences reduces the cross-input traffic of a blend operation. If so,
8459 /// lowering it through interleaving is a significantly better strategy.
8460 static bool shouldLowerAsInterleaving(ArrayRef<int> Mask) {
8461 int NumEvenInputs[2] = {0, 0};
8462 int NumOddInputs[2] = {0, 0};
8463 int NumLoInputs[2] = {0, 0};
8464 int NumHiInputs[2] = {0, 0};
8465 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
8469 int InputIdx = Mask[i] >= Size;
8472 ++NumLoInputs[InputIdx];
8474 ++NumHiInputs[InputIdx];
8477 ++NumEvenInputs[InputIdx];
8479 ++NumOddInputs[InputIdx];
8482 // The minimum number of cross-input results for both the interleaved and
8483 // split cases. If interleaving results in fewer cross-input results, return
8485 int InterleavedCrosses = std::min(NumEvenInputs[1] + NumOddInputs[0],
8486 NumEvenInputs[0] + NumOddInputs[1]);
8487 int SplitCrosses = std::min(NumLoInputs[1] + NumHiInputs[0],
8488 NumLoInputs[0] + NumHiInputs[1]);
8489 return InterleavedCrosses < SplitCrosses;
8492 /// \brief Blend two v8i16 vectors using a naive unpack strategy.
8494 /// This strategy only works when the inputs from each vector fit into a single
8495 /// half of that vector, and generally there are not so many inputs as to leave
8496 /// the in-place shuffles required highly constrained (and thus expensive). It
8497 /// shifts all the inputs into a single side of both input vectors and then
8498 /// uses an unpack to interleave these inputs in a single vector. At that
8499 /// point, we will fall back on the generic single input shuffle lowering.
8500 static SDValue lowerV8I16BasicBlendVectorShuffle(SDLoc DL, SDValue V1,
8502 MutableArrayRef<int> Mask,
8503 const X86Subtarget *Subtarget,
8504 SelectionDAG &DAG) {
8505 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8506 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8507 SmallVector<int, 3> LoV1Inputs, HiV1Inputs, LoV2Inputs, HiV2Inputs;
8508 for (int i = 0; i < 8; ++i)
8509 if (Mask[i] >= 0 && Mask[i] < 4)
8510 LoV1Inputs.push_back(i);
8511 else if (Mask[i] >= 4 && Mask[i] < 8)
8512 HiV1Inputs.push_back(i);
8513 else if (Mask[i] >= 8 && Mask[i] < 12)
8514 LoV2Inputs.push_back(i);
8515 else if (Mask[i] >= 12)
8516 HiV2Inputs.push_back(i);
8518 int NumV1Inputs = LoV1Inputs.size() + HiV1Inputs.size();
8519 int NumV2Inputs = LoV2Inputs.size() + HiV2Inputs.size();
8522 assert(NumV1Inputs > 0 && NumV1Inputs <= 3 && "At most 3 inputs supported");
8523 assert(NumV2Inputs > 0 && NumV2Inputs <= 3 && "At most 3 inputs supported");
8524 assert(NumV1Inputs + NumV2Inputs <= 4 && "At most 4 combined inputs");
8526 bool MergeFromLo = LoV1Inputs.size() + LoV2Inputs.size() >=
8527 HiV1Inputs.size() + HiV2Inputs.size();
8529 auto moveInputsToHalf = [&](SDValue V, ArrayRef<int> LoInputs,
8530 ArrayRef<int> HiInputs, bool MoveToLo,
8532 ArrayRef<int> GoodInputs = MoveToLo ? LoInputs : HiInputs;
8533 ArrayRef<int> BadInputs = MoveToLo ? HiInputs : LoInputs;
8534 if (BadInputs.empty())
8537 int MoveMask[] = {-1, -1, -1, -1, -1, -1, -1, -1};
8538 int MoveOffset = MoveToLo ? 0 : 4;
8540 if (GoodInputs.empty()) {
8541 for (int BadInput : BadInputs) {
8542 MoveMask[Mask[BadInput] % 4 + MoveOffset] = Mask[BadInput] - MaskOffset;
8543 Mask[BadInput] = Mask[BadInput] % 4 + MoveOffset + MaskOffset;
8546 if (GoodInputs.size() == 2) {
8547 // If the low inputs are spread across two dwords, pack them into
8549 MoveMask[MoveOffset] = Mask[GoodInputs[0]] - MaskOffset;
8550 MoveMask[MoveOffset + 1] = Mask[GoodInputs[1]] - MaskOffset;
8551 Mask[GoodInputs[0]] = MoveOffset + MaskOffset;
8552 Mask[GoodInputs[1]] = MoveOffset + 1 + MaskOffset;
8554 // Otherwise pin the good inputs.
8555 for (int GoodInput : GoodInputs)
8556 MoveMask[Mask[GoodInput] - MaskOffset] = Mask[GoodInput] - MaskOffset;
8559 if (BadInputs.size() == 2) {
8560 // If we have two bad inputs then there may be either one or two good
8561 // inputs fixed in place. Find a fixed input, and then find the *other*
8562 // two adjacent indices by using modular arithmetic.
8564 std::find_if(std::begin(MoveMask) + MoveOffset, std::end(MoveMask),
8565 [](int M) { return M >= 0; }) -
8566 std::begin(MoveMask);
8568 ((((GoodMaskIdx - MoveOffset) & ~1) + 2) % 4) + MoveOffset;
8569 assert(MoveMask[MoveMaskIdx] == -1 && "Expected empty slot");
8570 assert(MoveMask[MoveMaskIdx + 1] == -1 && "Expected empty slot");
8571 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
8572 MoveMask[MoveMaskIdx + 1] = Mask[BadInputs[1]] - MaskOffset;
8573 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
8574 Mask[BadInputs[1]] = MoveMaskIdx + 1 + MaskOffset;
8576 assert(BadInputs.size() == 1 && "All sizes handled");
8577 int MoveMaskIdx = std::find(std::begin(MoveMask) + MoveOffset,
8578 std::end(MoveMask), -1) -
8579 std::begin(MoveMask);
8580 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
8581 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
8585 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
8588 V1 = moveInputsToHalf(V1, LoV1Inputs, HiV1Inputs, MergeFromLo,
8590 V2 = moveInputsToHalf(V2, LoV2Inputs, HiV2Inputs, MergeFromLo,
8593 // FIXME: Select an interleaving of the merge of V1 and V2 that minimizes
8594 // cross-half traffic in the final shuffle.
8596 // Munge the mask to be a single-input mask after the unpack merges the
8600 M = 2 * (M % 4) + (M / 8);
8602 return DAG.getVectorShuffle(
8603 MVT::v8i16, DL, DAG.getNode(MergeFromLo ? X86ISD::UNPCKL : X86ISD::UNPCKH,
8604 DL, MVT::v8i16, V1, V2),
8605 DAG.getUNDEF(MVT::v8i16), Mask);
8608 /// \brief Generic lowering of 8-lane i16 shuffles.
8610 /// This handles both single-input shuffles and combined shuffle/blends with
8611 /// two inputs. The single input shuffles are immediately delegated to
8612 /// a dedicated lowering routine.
8614 /// The blends are lowered in one of three fundamental ways. If there are few
8615 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
8616 /// of the input is significantly cheaper when lowered as an interleaving of
8617 /// the two inputs, try to interleave them. Otherwise, blend the low and high
8618 /// halves of the inputs separately (making them have relatively few inputs)
8619 /// and then concatenate them.
8620 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8621 const X86Subtarget *Subtarget,
8622 SelectionDAG &DAG) {
8624 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
8625 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
8626 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
8627 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8628 ArrayRef<int> OrigMask = SVOp->getMask();
8629 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
8630 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
8631 MutableArrayRef<int> Mask(MaskStorage);
8633 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
8635 // Whenever we can lower this as a zext, that instruction is strictly faster
8636 // than any alternative.
8637 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
8638 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
8641 auto isV1 = [](int M) { return M >= 0 && M < 8; };
8642 auto isV2 = [](int M) { return M >= 8; };
8644 int NumV1Inputs = std::count_if(Mask.begin(), Mask.end(), isV1);
8645 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
8647 if (NumV2Inputs == 0)
8648 return lowerV8I16SingleInputVectorShuffle(DL, V1, Mask, Subtarget, DAG);
8650 assert(NumV1Inputs > 0 && "All single-input shuffles should be canonicalized "
8651 "to be V1-input shuffles.");
8653 // There are special ways we can lower some single-element blends.
8654 if (NumV2Inputs == 1)
8655 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v8i16, DL, V1, V2,
8656 Mask, Subtarget, DAG))
8659 if (Subtarget->hasSSE41())
8661 lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask, DAG))
8664 // Try to use rotation instructions if available.
8665 if (Subtarget->hasSSSE3())
8666 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(DL, MVT::v8i16, V1, V2, Mask, DAG))
8669 if (NumV1Inputs + NumV2Inputs <= 4)
8670 return lowerV8I16BasicBlendVectorShuffle(DL, V1, V2, Mask, Subtarget, DAG);
8672 // Check whether an interleaving lowering is likely to be more efficient.
8673 // This isn't perfect but it is a strong heuristic that tends to work well on
8674 // the kinds of shuffles that show up in practice.
8676 // FIXME: Handle 1x, 2x, and 4x interleaving.
8677 if (shouldLowerAsInterleaving(Mask)) {
8678 // FIXME: Figure out whether we should pack these into the low or high
8681 int EMask[8], OMask[8];
8682 for (int i = 0; i < 4; ++i) {
8683 EMask[i] = Mask[2*i];
8684 OMask[i] = Mask[2*i + 1];
8689 SDValue Evens = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, EMask);
8690 SDValue Odds = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, OMask);
8692 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, Evens, Odds);
8695 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8696 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8698 for (int i = 0; i < 4; ++i) {
8699 LoBlendMask[i] = Mask[i];
8700 HiBlendMask[i] = Mask[i + 4];
8703 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
8704 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
8705 LoV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, LoV);
8706 HiV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, HiV);
8708 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8709 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, LoV, HiV));
8712 /// \brief Check whether a compaction lowering can be done by dropping even
8713 /// elements and compute how many times even elements must be dropped.
8715 /// This handles shuffles which take every Nth element where N is a power of
8716 /// two. Example shuffle masks:
8718 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
8719 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
8720 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
8721 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
8722 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
8723 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
8725 /// Any of these lanes can of course be undef.
8727 /// This routine only supports N <= 3.
8728 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
8731 /// \returns N above, or the number of times even elements must be dropped if
8732 /// there is such a number. Otherwise returns zero.
8733 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
8734 // Figure out whether we're looping over two inputs or just one.
8735 bool IsSingleInput = isSingleInputShuffleMask(Mask);
8737 // The modulus for the shuffle vector entries is based on whether this is
8738 // a single input or not.
8739 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
8740 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
8741 "We should only be called with masks with a power-of-2 size!");
8743 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
8745 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
8746 // and 2^3 simultaneously. This is because we may have ambiguity with
8747 // partially undef inputs.
8748 bool ViableForN[3] = {true, true, true};
8750 for (int i = 0, e = Mask.size(); i < e; ++i) {
8751 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
8756 bool IsAnyViable = false;
8757 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
8758 if (ViableForN[j]) {
8761 // The shuffle mask must be equal to (i * 2^N) % M.
8762 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
8765 ViableForN[j] = false;
8767 // Early exit if we exhaust the possible powers of two.
8772 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
8776 // Return 0 as there is no viable power of two.
8780 /// \brief Generic lowering of v16i8 shuffles.
8782 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
8783 /// detect any complexity reducing interleaving. If that doesn't help, it uses
8784 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
8785 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
8787 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8788 const X86Subtarget *Subtarget,
8789 SelectionDAG &DAG) {
8791 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
8792 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
8793 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
8794 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8795 ArrayRef<int> OrigMask = SVOp->getMask();
8796 assert(OrigMask.size() == 16 && "Unexpected mask size for v16 shuffle!");
8798 // Try to use rotation instructions if available.
8799 if (Subtarget->hasSSSE3())
8800 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(DL, MVT::v16i8, V1, V2,
8804 // Try to use a zext lowering.
8805 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
8806 DL, MVT::v16i8, V1, V2, OrigMask, Subtarget, DAG))
8809 int MaskStorage[16] = {
8810 OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
8811 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7],
8812 OrigMask[8], OrigMask[9], OrigMask[10], OrigMask[11],
8813 OrigMask[12], OrigMask[13], OrigMask[14], OrigMask[15]};
8814 MutableArrayRef<int> Mask(MaskStorage);
8815 MutableArrayRef<int> LoMask = Mask.slice(0, 8);
8816 MutableArrayRef<int> HiMask = Mask.slice(8, 8);
8819 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
8821 // For single-input shuffles, there are some nicer lowering tricks we can use.
8822 if (NumV2Elements == 0) {
8823 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
8824 // Notably, this handles splat and partial-splat shuffles more efficiently.
8825 // However, it only makes sense if the pre-duplication shuffle simplifies
8826 // things significantly. Currently, this means we need to be able to
8827 // express the pre-duplication shuffle as an i16 shuffle.
8829 // FIXME: We should check for other patterns which can be widened into an
8830 // i16 shuffle as well.
8831 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
8832 for (int i = 0; i < 16; i += 2)
8833 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
8838 auto tryToWidenViaDuplication = [&]() -> SDValue {
8839 if (!canWidenViaDuplication(Mask))
8841 SmallVector<int, 4> LoInputs;
8842 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
8843 [](int M) { return M >= 0 && M < 8; });
8844 std::sort(LoInputs.begin(), LoInputs.end());
8845 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
8847 SmallVector<int, 4> HiInputs;
8848 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
8849 [](int M) { return M >= 8; });
8850 std::sort(HiInputs.begin(), HiInputs.end());
8851 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
8854 bool TargetLo = LoInputs.size() >= HiInputs.size();
8855 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
8856 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
8858 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
8859 SmallDenseMap<int, int, 8> LaneMap;
8860 for (int I : InPlaceInputs) {
8861 PreDupI16Shuffle[I/2] = I/2;
8864 int j = TargetLo ? 0 : 4, je = j + 4;
8865 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
8866 // Check if j is already a shuffle of this input. This happens when
8867 // there are two adjacent bytes after we move the low one.
8868 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
8869 // If we haven't yet mapped the input, search for a slot into which
8871 while (j < je && PreDupI16Shuffle[j] != -1)
8875 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
8878 // Map this input with the i16 shuffle.
8879 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
8882 // Update the lane map based on the mapping we ended up with.
8883 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
8886 ISD::BITCAST, DL, MVT::v16i8,
8887 DAG.getVectorShuffle(MVT::v8i16, DL,
8888 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
8889 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
8891 // Unpack the bytes to form the i16s that will be shuffled into place.
8892 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
8893 MVT::v16i8, V1, V1);
8895 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8896 for (int i = 0; i < 16; i += 2) {
8898 PostDupI16Shuffle[i / 2] = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
8899 assert(PostDupI16Shuffle[i / 2] < 8 && "Invalid v8 shuffle mask!");
8902 ISD::BITCAST, DL, MVT::v16i8,
8903 DAG.getVectorShuffle(MVT::v8i16, DL,
8904 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
8905 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
8907 if (SDValue V = tryToWidenViaDuplication())
8911 // Check whether an interleaving lowering is likely to be more efficient.
8912 // This isn't perfect but it is a strong heuristic that tends to work well on
8913 // the kinds of shuffles that show up in practice.
8915 // FIXME: We need to handle other interleaving widths (i16, i32, ...).
8916 if (shouldLowerAsInterleaving(Mask)) {
8917 // FIXME: Figure out whether we should pack these into the low or high
8920 int EMask[16], OMask[16];
8921 for (int i = 0; i < 8; ++i) {
8922 EMask[i] = Mask[2*i];
8923 OMask[i] = Mask[2*i + 1];
8928 SDValue Evens = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, EMask);
8929 SDValue Odds = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, OMask);
8931 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, Evens, Odds);
8934 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
8935 // with PSHUFB. It is important to do this before we attempt to generate any
8936 // blends but after all of the single-input lowerings. If the single input
8937 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
8938 // want to preserve that and we can DAG combine any longer sequences into
8939 // a PSHUFB in the end. But once we start blending from multiple inputs,
8940 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
8941 // and there are *very* few patterns that would actually be faster than the
8942 // PSHUFB approach because of its ability to zero lanes.
8944 // FIXME: The only exceptions to the above are blends which are exact
8945 // interleavings with direct instructions supporting them. We currently don't
8946 // handle those well here.
8947 if (Subtarget->hasSSSE3()) {
8950 for (int i = 0; i < 16; ++i)
8951 if (Mask[i] == -1) {
8952 V1Mask[i] = V2Mask[i] = DAG.getConstant(0x80, MVT::i8);
8954 V1Mask[i] = DAG.getConstant(Mask[i] < 16 ? Mask[i] : 0x80, MVT::i8);
8956 DAG.getConstant(Mask[i] < 16 ? 0x80 : Mask[i] - 16, MVT::i8);
8958 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V1,
8959 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
8960 if (isSingleInputShuffleMask(Mask))
8961 return V1; // Single inputs are easy.
8963 // Otherwise, blend the two.
8964 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V2,
8965 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
8966 return DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
8969 // There are special ways we can lower some single-element blends.
8970 if (NumV2Elements == 1)
8971 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v16i8, DL, V1, V2,
8972 Mask, Subtarget, DAG))
8975 // Check whether a compaction lowering can be done. This handles shuffles
8976 // which take every Nth element for some even N. See the helper function for
8979 // We special case these as they can be particularly efficiently handled with
8980 // the PACKUSB instruction on x86 and they show up in common patterns of
8981 // rearranging bytes to truncate wide elements.
8982 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
8983 // NumEvenDrops is the power of two stride of the elements. Another way of
8984 // thinking about it is that we need to drop the even elements this many
8985 // times to get the original input.
8986 bool IsSingleInput = isSingleInputShuffleMask(Mask);
8988 // First we need to zero all the dropped bytes.
8989 assert(NumEvenDrops <= 3 &&
8990 "No support for dropping even elements more than 3 times.");
8991 // We use the mask type to pick which bytes are preserved based on how many
8992 // elements are dropped.
8993 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
8994 SDValue ByteClearMask =
8995 DAG.getNode(ISD::BITCAST, DL, MVT::v16i8,
8996 DAG.getConstant(0xFF, MaskVTs[NumEvenDrops - 1]));
8997 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
8999 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
9001 // Now pack things back together.
9002 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
9003 V2 = IsSingleInput ? V1 : DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
9004 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
9005 for (int i = 1; i < NumEvenDrops; ++i) {
9006 Result = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, Result);
9007 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
9013 int V1LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9014 int V1HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9015 int V2LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9016 int V2HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9018 auto buildBlendMasks = [](MutableArrayRef<int> HalfMask,
9019 MutableArrayRef<int> V1HalfBlendMask,
9020 MutableArrayRef<int> V2HalfBlendMask) {
9021 for (int i = 0; i < 8; ++i)
9022 if (HalfMask[i] >= 0 && HalfMask[i] < 16) {
9023 V1HalfBlendMask[i] = HalfMask[i];
9025 } else if (HalfMask[i] >= 16) {
9026 V2HalfBlendMask[i] = HalfMask[i] - 16;
9027 HalfMask[i] = i + 8;
9030 buildBlendMasks(LoMask, V1LoBlendMask, V2LoBlendMask);
9031 buildBlendMasks(HiMask, V1HiBlendMask, V2HiBlendMask);
9033 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
9035 auto buildLoAndHiV8s = [&](SDValue V, MutableArrayRef<int> LoBlendMask,
9036 MutableArrayRef<int> HiBlendMask) {
9038 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
9039 // them out and avoid using UNPCK{L,H} to extract the elements of V as
9041 if (std::none_of(LoBlendMask.begin(), LoBlendMask.end(),
9042 [](int M) { return M >= 0 && M % 2 == 1; }) &&
9043 std::none_of(HiBlendMask.begin(), HiBlendMask.end(),
9044 [](int M) { return M >= 0 && M % 2 == 1; })) {
9045 // Use a mask to drop the high bytes.
9046 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
9047 V1 = DAG.getNode(ISD::AND, DL, MVT::v8i16, V1,
9048 DAG.getConstant(0x00FF, MVT::v8i16));
9050 // This will be a single vector shuffle instead of a blend so nuke V2.
9051 V2 = DAG.getUNDEF(MVT::v8i16);
9053 // Squash the masks to point directly into V1.
9054 for (int &M : LoBlendMask)
9057 for (int &M : HiBlendMask)
9061 // Otherwise just unpack the low half of V into V1 and the high half into
9062 // V2 so that we can blend them as i16s.
9063 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9064 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
9065 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9066 DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
9069 SDValue BlendedLo = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
9070 SDValue BlendedHi = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
9071 return std::make_pair(BlendedLo, BlendedHi);
9073 SDValue V1Lo, V1Hi, V2Lo, V2Hi;
9074 std::tie(V1Lo, V1Hi) = buildLoAndHiV8s(V1, V1LoBlendMask, V1HiBlendMask);
9075 std::tie(V2Lo, V2Hi) = buildLoAndHiV8s(V2, V2LoBlendMask, V2HiBlendMask);
9077 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Lo, V2Lo, LoMask);
9078 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Hi, V2Hi, HiMask);
9080 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
9083 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
9085 /// This routine breaks down the specific type of 128-bit shuffle and
9086 /// dispatches to the lowering routines accordingly.
9087 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9088 MVT VT, const X86Subtarget *Subtarget,
9089 SelectionDAG &DAG) {
9090 switch (VT.SimpleTy) {
9092 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9094 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9096 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9098 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9100 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9102 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9105 llvm_unreachable("Unimplemented!");
9109 static bool isHalfCrossingShuffleMask(ArrayRef<int> Mask) {
9110 int Size = Mask.size();
9111 for (int M : Mask.slice(0, Size / 2))
9112 if (M >= 0 && (M % Size) >= Size / 2)
9114 for (int M : Mask.slice(Size / 2, Size / 2))
9115 if (M >= 0 && (M % Size) < Size / 2)
9120 /// \brief Generic routine to split a 256-bit vector shuffle into 128-bit
9123 /// There is a severely limited set of shuffles available in AVX1 for 256-bit
9124 /// vectors resulting in routinely needing to split the shuffle into two 128-bit
9125 /// shuffles. This can be done generically for any 256-bit vector shuffle and so
9126 /// we encode the logic here for specific shuffle lowering routines to bail to
9127 /// when they exhaust the features avaible to more directly handle the shuffle.
9128 static SDValue splitAndLower256BitVectorShuffle(SDValue Op, SDValue V1,
9130 const X86Subtarget *Subtarget,
9131 SelectionDAG &DAG) {
9133 MVT VT = Op.getSimpleValueType();
9134 assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!");
9135 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
9136 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
9137 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9138 ArrayRef<int> Mask = SVOp->getMask();
9140 ArrayRef<int> LoMask = Mask.slice(0, Mask.size()/2);
9141 ArrayRef<int> HiMask = Mask.slice(Mask.size()/2);
9143 int NumElements = VT.getVectorNumElements();
9144 int SplitNumElements = NumElements / 2;
9145 MVT ScalarVT = VT.getScalarType();
9146 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
9148 SDValue LoV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9149 DAG.getIntPtrConstant(0));
9150 SDValue HiV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9151 DAG.getIntPtrConstant(SplitNumElements));
9152 SDValue LoV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9153 DAG.getIntPtrConstant(0));
9154 SDValue HiV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9155 DAG.getIntPtrConstant(SplitNumElements));
9157 // Now create two 4-way blends of these half-width vectors.
9158 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
9159 SmallVector<int, 16> V1BlendMask, V2BlendMask, BlendMask;
9160 for (int i = 0; i < SplitNumElements; ++i) {
9161 int M = HalfMask[i];
9162 if (M >= NumElements) {
9163 V2BlendMask.push_back(M - NumElements);
9164 V1BlendMask.push_back(-1);
9165 BlendMask.push_back(SplitNumElements + i);
9166 } else if (M >= 0) {
9167 V2BlendMask.push_back(-1);
9168 V1BlendMask.push_back(M);
9169 BlendMask.push_back(i);
9171 V2BlendMask.push_back(-1);
9172 V1BlendMask.push_back(-1);
9173 BlendMask.push_back(-1);
9176 SDValue V1Blend = DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9177 SDValue V2Blend = DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9178 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
9180 SDValue Lo = HalfBlend(LoMask);
9181 SDValue Hi = HalfBlend(HiMask);
9182 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
9185 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
9187 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
9188 /// isn't available.
9189 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9190 const X86Subtarget *Subtarget,
9191 SelectionDAG &DAG) {
9193 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9194 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9195 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9196 ArrayRef<int> Mask = SVOp->getMask();
9197 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9199 // FIXME: If we have AVX2, we should delegate to generic code as crossing
9200 // shuffles aren't a problem and FP and int have the same patterns.
9202 // FIXME: We can handle these more cleverly than splitting for v4f64.
9203 if (isHalfCrossingShuffleMask(Mask))
9204 return splitAndLower256BitVectorShuffle(Op, V1, V2, Subtarget, DAG);
9206 if (isSingleInputShuffleMask(Mask)) {
9207 // Non-half-crossing single input shuffles can be lowerid with an
9208 // interleaved permutation.
9209 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
9210 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
9211 return DAG.getNode(X86ISD::VPERMILP, DL, MVT::v4f64, V1,
9212 DAG.getConstant(VPERMILPMask, MVT::i8));
9215 // X86 has dedicated unpack instructions that can handle specific blend
9216 // operations: UNPCKH and UNPCKL.
9217 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
9218 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V1, V2);
9219 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
9220 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V1, V2);
9221 // FIXME: It would be nice to find a way to get canonicalization to commute
9223 if (isShuffleEquivalent(Mask, 4, 0, 6, 2))
9224 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V2, V1);
9225 if (isShuffleEquivalent(Mask, 5, 1, 7, 3))
9226 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V2, V1);
9228 // Check if the blend happens to exactly fit that of SHUFPD.
9229 if (Mask[0] < 4 && (Mask[1] == -1 || Mask[1] >= 4) &&
9230 Mask[2] < 4 && (Mask[3] == -1 || Mask[3] >= 4)) {
9231 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 5) << 1) |
9232 ((Mask[2] == 3) << 2) | ((Mask[3] == 7) << 3);
9233 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V1, V2,
9234 DAG.getConstant(SHUFPDMask, MVT::i8));
9236 if ((Mask[0] == -1 || Mask[0] >= 4) && Mask[1] < 4 &&
9237 (Mask[2] == -1 || Mask[2] >= 4) && Mask[3] < 4) {
9238 unsigned SHUFPDMask = (Mask[0] == 5) | ((Mask[1] == 1) << 1) |
9239 ((Mask[2] == 7) << 2) | ((Mask[3] == 3) << 3);
9240 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V2, V1,
9241 DAG.getConstant(SHUFPDMask, MVT::i8));
9244 // Shuffle the input elements into the desired positions in V1 and V2 and
9245 // blend them together.
9246 int V1Mask[] = {-1, -1, -1, -1};
9247 int V2Mask[] = {-1, -1, -1, -1};
9248 for (int i = 0; i < 4; ++i)
9249 if (Mask[i] >= 0 && Mask[i] < 4)
9250 V1Mask[i] = Mask[i];
9251 else if (Mask[i] >= 4)
9252 V2Mask[i] = Mask[i] - 4;
9254 V1 = DAG.getVectorShuffle(MVT::v4f64, DL, V1, DAG.getUNDEF(MVT::v4f64), V1Mask);
9255 V2 = DAG.getVectorShuffle(MVT::v4f64, DL, V2, DAG.getUNDEF(MVT::v4f64), V2Mask);
9257 unsigned BlendMask = 0;
9258 for (int i = 0; i < 4; ++i)
9260 BlendMask |= 1 << i;
9262 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v4f64, V1, V2,
9263 DAG.getConstant(BlendMask, MVT::i8));
9266 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
9268 /// Largely delegates to common code when we have AVX2 and to the floating-point
9269 /// code when we only have AVX.
9270 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9271 const X86Subtarget *Subtarget,
9272 SelectionDAG &DAG) {
9274 assert(Op.getSimpleValueType() == MVT::v4i64 && "Bad shuffle type!");
9275 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
9276 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
9277 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9278 ArrayRef<int> Mask = SVOp->getMask();
9279 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9281 // FIXME: If we have AVX2, we should delegate to generic code as crossing
9282 // shuffles aren't a problem and FP and int have the same patterns.
9284 if (isHalfCrossingShuffleMask(Mask))
9285 return splitAndLower256BitVectorShuffle(Op, V1, V2, Subtarget, DAG);
9287 // AVX1 doesn't provide any facilities for v4i64 shuffles, bitcast and
9288 // delegate to floating point code.
9289 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f64, V1);
9290 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f64, V2);
9291 return DAG.getNode(ISD::BITCAST, DL, MVT::v4i64,
9292 lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG));
9295 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
9297 /// This routine either breaks down the specific type of a 256-bit x86 vector
9298 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
9299 /// together based on the available instructions.
9300 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9301 MVT VT, const X86Subtarget *Subtarget,
9302 SelectionDAG &DAG) {
9303 switch (VT.SimpleTy) {
9305 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9307 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9312 // Fall back to the basic pattern of extracting the high half and forming
9314 // FIXME: Add targeted lowering for each type that can document rationale
9315 // for delegating to this when necessary.
9316 return splitAndLower256BitVectorShuffle(Op, V1, V2, Subtarget, DAG);
9319 llvm_unreachable("Not a valid 256-bit x86 vector type!");
9323 /// \brief Tiny helper function to test whether a shuffle mask could be
9324 /// simplified by widening the elements being shuffled.
9325 static bool canWidenShuffleElements(ArrayRef<int> Mask) {
9326 for (int i = 0, Size = Mask.size(); i < Size; i += 2)
9327 if ((Mask[i] != -1 && Mask[i] % 2 != 0) ||
9328 (Mask[i + 1] != -1 && (Mask[i + 1] % 2 != 1 ||
9329 (Mask[i] != -1 && Mask[i] + 1 != Mask[i + 1]))))
9335 /// \brief Top-level lowering for x86 vector shuffles.
9337 /// This handles decomposition, canonicalization, and lowering of all x86
9338 /// vector shuffles. Most of the specific lowering strategies are encapsulated
9339 /// above in helper routines. The canonicalization attempts to widen shuffles
9340 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
9341 /// s.t. only one of the two inputs needs to be tested, etc.
9342 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
9343 SelectionDAG &DAG) {
9344 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9345 ArrayRef<int> Mask = SVOp->getMask();
9346 SDValue V1 = Op.getOperand(0);
9347 SDValue V2 = Op.getOperand(1);
9348 MVT VT = Op.getSimpleValueType();
9349 int NumElements = VT.getVectorNumElements();
9352 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
9354 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
9355 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
9356 if (V1IsUndef && V2IsUndef)
9357 return DAG.getUNDEF(VT);
9359 // When we create a shuffle node we put the UNDEF node to second operand,
9360 // but in some cases the first operand may be transformed to UNDEF.
9361 // In this case we should just commute the node.
9363 return DAG.getCommutedVectorShuffle(*SVOp);
9365 // Check for non-undef masks pointing at an undef vector and make the masks
9366 // undef as well. This makes it easier to match the shuffle based solely on
9370 if (M >= NumElements) {
9371 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
9372 for (int &M : NewMask)
9373 if (M >= NumElements)
9375 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
9378 // For integer vector shuffles, try to collapse them into a shuffle of fewer
9379 // lanes but wider integers. We cap this to not form integers larger than i64
9380 // but it might be interesting to form i128 integers to handle flipping the
9381 // low and high halves of AVX 256-bit vectors.
9382 if (VT.isInteger() && VT.getScalarSizeInBits() < 64 &&
9383 canWidenShuffleElements(Mask)) {
9384 SmallVector<int, 8> NewMask;
9385 for (int i = 0, Size = Mask.size(); i < Size; i += 2)
9386 NewMask.push_back(Mask[i] != -1
9388 : (Mask[i + 1] != -1 ? Mask[i + 1] / 2 : -1));
9390 MVT::getVectorVT(MVT::getIntegerVT(VT.getScalarSizeInBits() * 2),
9391 VT.getVectorNumElements() / 2);
9392 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
9393 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
9394 return DAG.getNode(ISD::BITCAST, dl, VT,
9395 DAG.getVectorShuffle(NewVT, dl, V1, V2, NewMask));
9398 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
9399 for (int M : SVOp->getMask())
9402 else if (M < NumElements)
9407 // Commute the shuffle as needed such that more elements come from V1 than
9408 // V2. This allows us to match the shuffle pattern strictly on how many
9409 // elements come from V1 without handling the symmetric cases.
9410 if (NumV2Elements > NumV1Elements)
9411 return DAG.getCommutedVectorShuffle(*SVOp);
9413 // When the number of V1 and V2 elements are the same, try to minimize the
9414 // number of uses of V2 in the low half of the vector.
9415 if (NumV1Elements == NumV2Elements) {
9416 int LowV1Elements = 0, LowV2Elements = 0;
9417 for (int M : SVOp->getMask().slice(0, NumElements / 2))
9418 if (M >= NumElements)
9422 if (LowV2Elements > LowV1Elements)
9423 return DAG.getCommutedVectorShuffle(*SVOp);
9426 // For each vector width, delegate to a specialized lowering routine.
9427 if (VT.getSizeInBits() == 128)
9428 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
9430 if (VT.getSizeInBits() == 256)
9431 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
9433 llvm_unreachable("Unimplemented!");
9437 //===----------------------------------------------------------------------===//
9438 // Legacy vector shuffle lowering
9440 // This code is the legacy code handling vector shuffles until the above
9441 // replaces its functionality and performance.
9442 //===----------------------------------------------------------------------===//
9444 static bool isBlendMask(ArrayRef<int> MaskVals, MVT VT, bool hasSSE41,
9445 bool hasInt256, unsigned *MaskOut = nullptr) {
9446 MVT EltVT = VT.getVectorElementType();
9448 // There is no blend with immediate in AVX-512.
9449 if (VT.is512BitVector())
9452 if (!hasSSE41 || EltVT == MVT::i8)
9454 if (!hasInt256 && VT == MVT::v16i16)
9457 unsigned MaskValue = 0;
9458 unsigned NumElems = VT.getVectorNumElements();
9459 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
9460 unsigned NumLanes = (NumElems - 1) / 8 + 1;
9461 unsigned NumElemsInLane = NumElems / NumLanes;
9463 // Blend for v16i16 should be symetric for the both lanes.
9464 for (unsigned i = 0; i < NumElemsInLane; ++i) {
9466 int SndLaneEltIdx = (NumLanes == 2) ? MaskVals[i + NumElemsInLane] : -1;
9467 int EltIdx = MaskVals[i];
9469 if ((EltIdx < 0 || EltIdx == (int)i) &&
9470 (SndLaneEltIdx < 0 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
9473 if (((unsigned)EltIdx == (i + NumElems)) &&
9474 (SndLaneEltIdx < 0 ||
9475 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
9476 MaskValue |= (1 << i);
9482 *MaskOut = MaskValue;
9486 // Try to lower a shuffle node into a simple blend instruction.
9487 // This function assumes isBlendMask returns true for this
9488 // SuffleVectorSDNode
9489 static SDValue LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
9491 const X86Subtarget *Subtarget,
9492 SelectionDAG &DAG) {
9493 MVT VT = SVOp->getSimpleValueType(0);
9494 MVT EltVT = VT.getVectorElementType();
9495 assert(isBlendMask(SVOp->getMask(), VT, Subtarget->hasSSE41(),
9496 Subtarget->hasInt256() && "Trying to lower a "
9497 "VECTOR_SHUFFLE to a Blend but "
9498 "with the wrong mask"));
9499 SDValue V1 = SVOp->getOperand(0);
9500 SDValue V2 = SVOp->getOperand(1);
9502 unsigned NumElems = VT.getVectorNumElements();
9504 // Convert i32 vectors to floating point if it is not AVX2.
9505 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
9507 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
9508 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
9510 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
9511 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
9514 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
9515 DAG.getConstant(MaskValue, MVT::i32));
9516 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
9519 /// In vector type \p VT, return true if the element at index \p InputIdx
9520 /// falls on a different 128-bit lane than \p OutputIdx.
9521 static bool ShuffleCrosses128bitLane(MVT VT, unsigned InputIdx,
9522 unsigned OutputIdx) {
9523 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
9524 return InputIdx * EltSize / 128 != OutputIdx * EltSize / 128;
9527 /// Generate a PSHUFB if possible. Selects elements from \p V1 according to
9528 /// \p MaskVals. MaskVals[OutputIdx] = InputIdx specifies that we want to
9529 /// shuffle the element at InputIdx in V1 to OutputIdx in the result. If \p
9530 /// MaskVals refers to elements outside of \p V1 or is undef (-1), insert a
9532 static SDValue getPSHUFB(ArrayRef<int> MaskVals, SDValue V1, SDLoc &dl,
9533 SelectionDAG &DAG) {
9534 MVT VT = V1.getSimpleValueType();
9535 assert(VT.is128BitVector() || VT.is256BitVector());
9537 MVT EltVT = VT.getVectorElementType();
9538 unsigned EltSizeInBytes = EltVT.getSizeInBits() / 8;
9539 unsigned NumElts = VT.getVectorNumElements();
9541 SmallVector<SDValue, 32> PshufbMask;
9542 for (unsigned OutputIdx = 0; OutputIdx < NumElts; ++OutputIdx) {
9543 int InputIdx = MaskVals[OutputIdx];
9544 unsigned InputByteIdx;
9546 if (InputIdx < 0 || NumElts <= (unsigned)InputIdx)
9547 InputByteIdx = 0x80;
9549 // Cross lane is not allowed.
9550 if (ShuffleCrosses128bitLane(VT, InputIdx, OutputIdx))
9552 InputByteIdx = InputIdx * EltSizeInBytes;
9553 // Index is an byte offset within the 128-bit lane.
9554 InputByteIdx &= 0xf;
9557 for (unsigned j = 0; j < EltSizeInBytes; ++j) {
9558 PshufbMask.push_back(DAG.getConstant(InputByteIdx, MVT::i8));
9559 if (InputByteIdx != 0x80)
9564 MVT ShufVT = MVT::getVectorVT(MVT::i8, PshufbMask.size());
9566 V1 = DAG.getNode(ISD::BITCAST, dl, ShufVT, V1);
9567 return DAG.getNode(X86ISD::PSHUFB, dl, ShufVT, V1,
9568 DAG.getNode(ISD::BUILD_VECTOR, dl, ShufVT, PshufbMask));
9571 // v8i16 shuffles - Prefer shuffles in the following order:
9572 // 1. [all] pshuflw, pshufhw, optional move
9573 // 2. [ssse3] 1 x pshufb
9574 // 3. [ssse3] 2 x pshufb + 1 x por
9575 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
9577 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
9578 SelectionDAG &DAG) {
9579 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9580 SDValue V1 = SVOp->getOperand(0);
9581 SDValue V2 = SVOp->getOperand(1);
9583 SmallVector<int, 8> MaskVals;
9585 // Determine if more than 1 of the words in each of the low and high quadwords
9586 // of the result come from the same quadword of one of the two inputs. Undef
9587 // mask values count as coming from any quadword, for better codegen.
9589 // Lo/HiQuad[i] = j indicates how many words from the ith quad of the input
9590 // feeds this quad. For i, 0 and 1 refer to V1, 2 and 3 refer to V2.
9591 unsigned LoQuad[] = { 0, 0, 0, 0 };
9592 unsigned HiQuad[] = { 0, 0, 0, 0 };
9593 // Indices of quads used.
9594 std::bitset<4> InputQuads;
9595 for (unsigned i = 0; i < 8; ++i) {
9596 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
9597 int EltIdx = SVOp->getMaskElt(i);
9598 MaskVals.push_back(EltIdx);
9607 InputQuads.set(EltIdx / 4);
9610 int BestLoQuad = -1;
9611 unsigned MaxQuad = 1;
9612 for (unsigned i = 0; i < 4; ++i) {
9613 if (LoQuad[i] > MaxQuad) {
9615 MaxQuad = LoQuad[i];
9619 int BestHiQuad = -1;
9621 for (unsigned i = 0; i < 4; ++i) {
9622 if (HiQuad[i] > MaxQuad) {
9624 MaxQuad = HiQuad[i];
9628 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
9629 // of the two input vectors, shuffle them into one input vector so only a
9630 // single pshufb instruction is necessary. If there are more than 2 input
9631 // quads, disable the next transformation since it does not help SSSE3.
9632 bool V1Used = InputQuads[0] || InputQuads[1];
9633 bool V2Used = InputQuads[2] || InputQuads[3];
9634 if (Subtarget->hasSSSE3()) {
9635 if (InputQuads.count() == 2 && V1Used && V2Used) {
9636 BestLoQuad = InputQuads[0] ? 0 : 1;
9637 BestHiQuad = InputQuads[2] ? 2 : 3;
9639 if (InputQuads.count() > 2) {
9645 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
9646 // the shuffle mask. If a quad is scored as -1, that means that it contains
9647 // words from all 4 input quadwords.
9649 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
9651 BestLoQuad < 0 ? 0 : BestLoQuad,
9652 BestHiQuad < 0 ? 1 : BestHiQuad
9654 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
9655 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
9656 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
9657 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
9659 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
9660 // source words for the shuffle, to aid later transformations.
9661 bool AllWordsInNewV = true;
9662 bool InOrder[2] = { true, true };
9663 for (unsigned i = 0; i != 8; ++i) {
9664 int idx = MaskVals[i];
9666 InOrder[i/4] = false;
9667 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
9669 AllWordsInNewV = false;
9673 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
9674 if (AllWordsInNewV) {
9675 for (int i = 0; i != 8; ++i) {
9676 int idx = MaskVals[i];
9679 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
9680 if ((idx != i) && idx < 4)
9682 if ((idx != i) && idx > 3)
9691 // If we've eliminated the use of V2, and the new mask is a pshuflw or
9692 // pshufhw, that's as cheap as it gets. Return the new shuffle.
9693 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
9694 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
9695 unsigned TargetMask = 0;
9696 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
9697 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
9698 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
9699 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
9700 getShufflePSHUFLWImmediate(SVOp);
9701 V1 = NewV.getOperand(0);
9702 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
9706 // Promote splats to a larger type which usually leads to more efficient code.
9707 // FIXME: Is this true if pshufb is available?
9708 if (SVOp->isSplat())
9709 return PromoteSplat(SVOp, DAG);
9711 // If we have SSSE3, and all words of the result are from 1 input vector,
9712 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
9713 // is present, fall back to case 4.
9714 if (Subtarget->hasSSSE3()) {
9715 SmallVector<SDValue,16> pshufbMask;
9717 // If we have elements from both input vectors, set the high bit of the
9718 // shuffle mask element to zero out elements that come from V2 in the V1
9719 // mask, and elements that come from V1 in the V2 mask, so that the two
9720 // results can be OR'd together.
9721 bool TwoInputs = V1Used && V2Used;
9722 V1 = getPSHUFB(MaskVals, V1, dl, DAG);
9724 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
9726 // Calculate the shuffle mask for the second input, shuffle it, and
9727 // OR it with the first shuffled input.
9728 CommuteVectorShuffleMask(MaskVals, 8);
9729 V2 = getPSHUFB(MaskVals, V2, dl, DAG);
9730 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
9731 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
9734 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
9735 // and update MaskVals with new element order.
9736 std::bitset<8> InOrder;
9737 if (BestLoQuad >= 0) {
9738 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
9739 for (int i = 0; i != 4; ++i) {
9740 int idx = MaskVals[i];
9743 } else if ((idx / 4) == BestLoQuad) {
9748 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
9751 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
9752 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
9753 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
9755 getShufflePSHUFLWImmediate(SVOp), DAG);
9759 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
9760 // and update MaskVals with the new element order.
9761 if (BestHiQuad >= 0) {
9762 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
9763 for (unsigned i = 4; i != 8; ++i) {
9764 int idx = MaskVals[i];
9767 } else if ((idx / 4) == BestHiQuad) {
9768 MaskV[i] = (idx & 3) + 4;
9772 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
9775 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
9776 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
9777 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
9779 getShufflePSHUFHWImmediate(SVOp), DAG);
9783 // In case BestHi & BestLo were both -1, which means each quadword has a word
9784 // from each of the four input quadwords, calculate the InOrder bitvector now
9785 // before falling through to the insert/extract cleanup.
9786 if (BestLoQuad == -1 && BestHiQuad == -1) {
9788 for (int i = 0; i != 8; ++i)
9789 if (MaskVals[i] < 0 || MaskVals[i] == i)
9793 // The other elements are put in the right place using pextrw and pinsrw.
9794 for (unsigned i = 0; i != 8; ++i) {
9797 int EltIdx = MaskVals[i];
9800 SDValue ExtOp = (EltIdx < 8) ?
9801 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
9802 DAG.getIntPtrConstant(EltIdx)) :
9803 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
9804 DAG.getIntPtrConstant(EltIdx - 8));
9805 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
9806 DAG.getIntPtrConstant(i));
9811 /// \brief v16i16 shuffles
9813 /// FIXME: We only support generation of a single pshufb currently. We can
9814 /// generalize the other applicable cases from LowerVECTOR_SHUFFLEv8i16 as
9815 /// well (e.g 2 x pshufb + 1 x por).
9817 LowerVECTOR_SHUFFLEv16i16(SDValue Op, SelectionDAG &DAG) {
9818 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9819 SDValue V1 = SVOp->getOperand(0);
9820 SDValue V2 = SVOp->getOperand(1);
9823 if (V2.getOpcode() != ISD::UNDEF)
9826 SmallVector<int, 16> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
9827 return getPSHUFB(MaskVals, V1, dl, DAG);
9830 // v16i8 shuffles - Prefer shuffles in the following order:
9831 // 1. [ssse3] 1 x pshufb
9832 // 2. [ssse3] 2 x pshufb + 1 x por
9833 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
9834 static SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
9835 const X86Subtarget* Subtarget,
9836 SelectionDAG &DAG) {
9837 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9838 SDValue V1 = SVOp->getOperand(0);
9839 SDValue V2 = SVOp->getOperand(1);
9841 ArrayRef<int> MaskVals = SVOp->getMask();
9843 // Promote splats to a larger type which usually leads to more efficient code.
9844 // FIXME: Is this true if pshufb is available?
9845 if (SVOp->isSplat())
9846 return PromoteSplat(SVOp, DAG);
9848 // If we have SSSE3, case 1 is generated when all result bytes come from
9849 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
9850 // present, fall back to case 3.
9852 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
9853 if (Subtarget->hasSSSE3()) {
9854 SmallVector<SDValue,16> pshufbMask;
9856 // If all result elements are from one input vector, then only translate
9857 // undef mask values to 0x80 (zero out result) in the pshufb mask.
9859 // Otherwise, we have elements from both input vectors, and must zero out
9860 // elements that come from V2 in the first mask, and V1 in the second mask
9861 // so that we can OR them together.
9862 for (unsigned i = 0; i != 16; ++i) {
9863 int EltIdx = MaskVals[i];
9864 if (EltIdx < 0 || EltIdx >= 16)
9866 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
9868 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
9869 DAG.getNode(ISD::BUILD_VECTOR, dl,
9870 MVT::v16i8, pshufbMask));
9872 // As PSHUFB will zero elements with negative indices, it's safe to ignore
9873 // the 2nd operand if it's undefined or zero.
9874 if (V2.getOpcode() == ISD::UNDEF ||
9875 ISD::isBuildVectorAllZeros(V2.getNode()))
9878 // Calculate the shuffle mask for the second input, shuffle it, and
9879 // OR it with the first shuffled input.
9881 for (unsigned i = 0; i != 16; ++i) {
9882 int EltIdx = MaskVals[i];
9883 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
9884 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
9886 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
9887 DAG.getNode(ISD::BUILD_VECTOR, dl,
9888 MVT::v16i8, pshufbMask));
9889 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
9892 // No SSSE3 - Calculate in place words and then fix all out of place words
9893 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
9894 // the 16 different words that comprise the two doublequadword input vectors.
9895 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
9896 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
9898 for (int i = 0; i != 8; ++i) {
9899 int Elt0 = MaskVals[i*2];
9900 int Elt1 = MaskVals[i*2+1];
9902 // This word of the result is all undef, skip it.
9903 if (Elt0 < 0 && Elt1 < 0)
9906 // This word of the result is already in the correct place, skip it.
9907 if ((Elt0 == i*2) && (Elt1 == i*2+1))
9910 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
9911 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
9914 // If Elt0 and Elt1 are defined, are consecutive, and can be load
9915 // using a single extract together, load it and store it.
9916 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
9917 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
9918 DAG.getIntPtrConstant(Elt1 / 2));
9919 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
9920 DAG.getIntPtrConstant(i));
9924 // If Elt1 is defined, extract it from the appropriate source. If the
9925 // source byte is not also odd, shift the extracted word left 8 bits
9926 // otherwise clear the bottom 8 bits if we need to do an or.
9928 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
9929 DAG.getIntPtrConstant(Elt1 / 2));
9930 if ((Elt1 & 1) == 0)
9931 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
9933 TLI.getShiftAmountTy(InsElt.getValueType())));
9935 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
9936 DAG.getConstant(0xFF00, MVT::i16));
9938 // If Elt0 is defined, extract it from the appropriate source. If the
9939 // source byte is not also even, shift the extracted word right 8 bits. If
9940 // Elt1 was also defined, OR the extracted values together before
9941 // inserting them in the result.
9943 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
9944 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
9945 if ((Elt0 & 1) != 0)
9946 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
9948 TLI.getShiftAmountTy(InsElt0.getValueType())));
9950 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
9951 DAG.getConstant(0x00FF, MVT::i16));
9952 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
9955 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
9956 DAG.getIntPtrConstant(i));
9958 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
9961 // v32i8 shuffles - Translate to VPSHUFB if possible.
9963 SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
9964 const X86Subtarget *Subtarget,
9965 SelectionDAG &DAG) {
9966 MVT VT = SVOp->getSimpleValueType(0);
9967 SDValue V1 = SVOp->getOperand(0);
9968 SDValue V2 = SVOp->getOperand(1);
9970 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
9972 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
9973 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
9974 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
9976 // VPSHUFB may be generated if
9977 // (1) one of input vector is undefined or zeroinitializer.
9978 // The mask value 0x80 puts 0 in the corresponding slot of the vector.
9979 // And (2) the mask indexes don't cross the 128-bit lane.
9980 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
9981 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
9984 if (V1IsAllZero && !V2IsAllZero) {
9985 CommuteVectorShuffleMask(MaskVals, 32);
9988 return getPSHUFB(MaskVals, V1, dl, DAG);
9991 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
9992 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
9993 /// done when every pair / quad of shuffle mask elements point to elements in
9994 /// the right sequence. e.g.
9995 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
9997 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
9998 SelectionDAG &DAG) {
9999 MVT VT = SVOp->getSimpleValueType(0);
10001 unsigned NumElems = VT.getVectorNumElements();
10004 switch (VT.SimpleTy) {
10005 default: llvm_unreachable("Unexpected!");
10008 return SDValue(SVOp, 0);
10009 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
10010 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
10011 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
10012 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
10013 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
10014 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
10017 SmallVector<int, 8> MaskVec;
10018 for (unsigned i = 0; i != NumElems; i += Scale) {
10020 for (unsigned j = 0; j != Scale; ++j) {
10021 int EltIdx = SVOp->getMaskElt(i+j);
10025 StartIdx = (EltIdx / Scale);
10026 if (EltIdx != (int)(StartIdx*Scale + j))
10029 MaskVec.push_back(StartIdx);
10032 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
10033 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
10034 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
10037 /// getVZextMovL - Return a zero-extending vector move low node.
10039 static SDValue getVZextMovL(MVT VT, MVT OpVT,
10040 SDValue SrcOp, SelectionDAG &DAG,
10041 const X86Subtarget *Subtarget, SDLoc dl) {
10042 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
10043 LoadSDNode *LD = nullptr;
10044 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
10045 LD = dyn_cast<LoadSDNode>(SrcOp);
10047 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
10049 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
10050 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
10051 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
10052 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
10053 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
10055 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
10056 return DAG.getNode(ISD::BITCAST, dl, VT,
10057 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
10058 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
10060 SrcOp.getOperand(0)
10066 return DAG.getNode(ISD::BITCAST, dl, VT,
10067 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
10068 DAG.getNode(ISD::BITCAST, dl,
10072 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
10073 /// which could not be matched by any known target speficic shuffle
10075 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
10077 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
10078 if (NewOp.getNode())
10081 MVT VT = SVOp->getSimpleValueType(0);
10083 unsigned NumElems = VT.getVectorNumElements();
10084 unsigned NumLaneElems = NumElems / 2;
10087 MVT EltVT = VT.getVectorElementType();
10088 MVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
10091 SmallVector<int, 16> Mask;
10092 for (unsigned l = 0; l < 2; ++l) {
10093 // Build a shuffle mask for the output, discovering on the fly which
10094 // input vectors to use as shuffle operands (recorded in InputUsed).
10095 // If building a suitable shuffle vector proves too hard, then bail
10096 // out with UseBuildVector set.
10097 bool UseBuildVector = false;
10098 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
10099 unsigned LaneStart = l * NumLaneElems;
10100 for (unsigned i = 0; i != NumLaneElems; ++i) {
10101 // The mask element. This indexes into the input.
10102 int Idx = SVOp->getMaskElt(i+LaneStart);
10104 // the mask element does not index into any input vector.
10105 Mask.push_back(-1);
10109 // The input vector this mask element indexes into.
10110 int Input = Idx / NumLaneElems;
10112 // Turn the index into an offset from the start of the input vector.
10113 Idx -= Input * NumLaneElems;
10115 // Find or create a shuffle vector operand to hold this input.
10117 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
10118 if (InputUsed[OpNo] == Input)
10119 // This input vector is already an operand.
10121 if (InputUsed[OpNo] < 0) {
10122 // Create a new operand for this input vector.
10123 InputUsed[OpNo] = Input;
10128 if (OpNo >= array_lengthof(InputUsed)) {
10129 // More than two input vectors used! Give up on trying to create a
10130 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
10131 UseBuildVector = true;
10135 // Add the mask index for the new shuffle vector.
10136 Mask.push_back(Idx + OpNo * NumLaneElems);
10139 if (UseBuildVector) {
10140 SmallVector<SDValue, 16> SVOps;
10141 for (unsigned i = 0; i != NumLaneElems; ++i) {
10142 // The mask element. This indexes into the input.
10143 int Idx = SVOp->getMaskElt(i+LaneStart);
10145 SVOps.push_back(DAG.getUNDEF(EltVT));
10149 // The input vector this mask element indexes into.
10150 int Input = Idx / NumElems;
10152 // Turn the index into an offset from the start of the input vector.
10153 Idx -= Input * NumElems;
10155 // Extract the vector element by hand.
10156 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
10157 SVOp->getOperand(Input),
10158 DAG.getIntPtrConstant(Idx)));
10161 // Construct the output using a BUILD_VECTOR.
10162 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, SVOps);
10163 } else if (InputUsed[0] < 0) {
10164 // No input vectors were used! The result is undefined.
10165 Output[l] = DAG.getUNDEF(NVT);
10167 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
10168 (InputUsed[0] % 2) * NumLaneElems,
10170 // If only one input was used, use an undefined vector for the other.
10171 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
10172 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
10173 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
10174 // At least one input vector was used. Create a new shuffle vector.
10175 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
10181 // Concatenate the result back
10182 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
10185 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
10186 /// 4 elements, and match them with several different shuffle types.
10188 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
10189 SDValue V1 = SVOp->getOperand(0);
10190 SDValue V2 = SVOp->getOperand(1);
10192 MVT VT = SVOp->getSimpleValueType(0);
10194 assert(VT.is128BitVector() && "Unsupported vector size");
10196 std::pair<int, int> Locs[4];
10197 int Mask1[] = { -1, -1, -1, -1 };
10198 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
10200 unsigned NumHi = 0;
10201 unsigned NumLo = 0;
10202 for (unsigned i = 0; i != 4; ++i) {
10203 int Idx = PermMask[i];
10205 Locs[i] = std::make_pair(-1, -1);
10207 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
10209 Locs[i] = std::make_pair(0, NumLo);
10210 Mask1[NumLo] = Idx;
10213 Locs[i] = std::make_pair(1, NumHi);
10215 Mask1[2+NumHi] = Idx;
10221 if (NumLo <= 2 && NumHi <= 2) {
10222 // If no more than two elements come from either vector. This can be
10223 // implemented with two shuffles. First shuffle gather the elements.
10224 // The second shuffle, which takes the first shuffle as both of its
10225 // vector operands, put the elements into the right order.
10226 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
10228 int Mask2[] = { -1, -1, -1, -1 };
10230 for (unsigned i = 0; i != 4; ++i)
10231 if (Locs[i].first != -1) {
10232 unsigned Idx = (i < 2) ? 0 : 4;
10233 Idx += Locs[i].first * 2 + Locs[i].second;
10237 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
10240 if (NumLo == 3 || NumHi == 3) {
10241 // Otherwise, we must have three elements from one vector, call it X, and
10242 // one element from the other, call it Y. First, use a shufps to build an
10243 // intermediate vector with the one element from Y and the element from X
10244 // that will be in the same half in the final destination (the indexes don't
10245 // matter). Then, use a shufps to build the final vector, taking the half
10246 // containing the element from Y from the intermediate, and the other half
10249 // Normalize it so the 3 elements come from V1.
10250 CommuteVectorShuffleMask(PermMask, 4);
10254 // Find the element from V2.
10256 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
10257 int Val = PermMask[HiIndex];
10264 Mask1[0] = PermMask[HiIndex];
10266 Mask1[2] = PermMask[HiIndex^1];
10268 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
10270 if (HiIndex >= 2) {
10271 Mask1[0] = PermMask[0];
10272 Mask1[1] = PermMask[1];
10273 Mask1[2] = HiIndex & 1 ? 6 : 4;
10274 Mask1[3] = HiIndex & 1 ? 4 : 6;
10275 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
10278 Mask1[0] = HiIndex & 1 ? 2 : 0;
10279 Mask1[1] = HiIndex & 1 ? 0 : 2;
10280 Mask1[2] = PermMask[2];
10281 Mask1[3] = PermMask[3];
10286 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
10289 // Break it into (shuffle shuffle_hi, shuffle_lo).
10290 int LoMask[] = { -1, -1, -1, -1 };
10291 int HiMask[] = { -1, -1, -1, -1 };
10293 int *MaskPtr = LoMask;
10294 unsigned MaskIdx = 0;
10295 unsigned LoIdx = 0;
10296 unsigned HiIdx = 2;
10297 for (unsigned i = 0; i != 4; ++i) {
10304 int Idx = PermMask[i];
10306 Locs[i] = std::make_pair(-1, -1);
10307 } else if (Idx < 4) {
10308 Locs[i] = std::make_pair(MaskIdx, LoIdx);
10309 MaskPtr[LoIdx] = Idx;
10312 Locs[i] = std::make_pair(MaskIdx, HiIdx);
10313 MaskPtr[HiIdx] = Idx;
10318 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
10319 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
10320 int MaskOps[] = { -1, -1, -1, -1 };
10321 for (unsigned i = 0; i != 4; ++i)
10322 if (Locs[i].first != -1)
10323 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
10324 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
10327 static bool MayFoldVectorLoad(SDValue V) {
10328 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
10329 V = V.getOperand(0);
10331 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
10332 V = V.getOperand(0);
10333 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
10334 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
10335 // BUILD_VECTOR (load), undef
10336 V = V.getOperand(0);
10338 return MayFoldLoad(V);
10342 SDValue getMOVDDup(SDValue &Op, SDLoc &dl, SDValue V1, SelectionDAG &DAG) {
10343 MVT VT = Op.getSimpleValueType();
10345 // Canonizalize to v2f64.
10346 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
10347 return DAG.getNode(ISD::BITCAST, dl, VT,
10348 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
10353 SDValue getMOVLowToHigh(SDValue &Op, SDLoc &dl, SelectionDAG &DAG,
10355 SDValue V1 = Op.getOperand(0);
10356 SDValue V2 = Op.getOperand(1);
10357 MVT VT = Op.getSimpleValueType();
10359 assert(VT != MVT::v2i64 && "unsupported shuffle type");
10361 if (HasSSE2 && VT == MVT::v2f64)
10362 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
10364 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
10365 return DAG.getNode(ISD::BITCAST, dl, VT,
10366 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
10367 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
10368 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
10372 SDValue getMOVHighToLow(SDValue &Op, SDLoc &dl, SelectionDAG &DAG) {
10373 SDValue V1 = Op.getOperand(0);
10374 SDValue V2 = Op.getOperand(1);
10375 MVT VT = Op.getSimpleValueType();
10377 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
10378 "unsupported shuffle type");
10380 if (V2.getOpcode() == ISD::UNDEF)
10384 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
10388 SDValue getMOVLP(SDValue &Op, SDLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
10389 SDValue V1 = Op.getOperand(0);
10390 SDValue V2 = Op.getOperand(1);
10391 MVT VT = Op.getSimpleValueType();
10392 unsigned NumElems = VT.getVectorNumElements();
10394 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
10395 // operand of these instructions is only memory, so check if there's a
10396 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
10398 bool CanFoldLoad = false;
10400 // Trivial case, when V2 comes from a load.
10401 if (MayFoldVectorLoad(V2))
10402 CanFoldLoad = true;
10404 // When V1 is a load, it can be folded later into a store in isel, example:
10405 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
10407 // (MOVLPSmr addr:$src1, VR128:$src2)
10408 // So, recognize this potential and also use MOVLPS or MOVLPD
10409 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
10410 CanFoldLoad = true;
10412 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10414 if (HasSSE2 && NumElems == 2)
10415 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
10418 // If we don't care about the second element, proceed to use movss.
10419 if (SVOp->getMaskElt(1) != -1)
10420 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
10423 // movl and movlp will both match v2i64, but v2i64 is never matched by
10424 // movl earlier because we make it strict to avoid messing with the movlp load
10425 // folding logic (see the code above getMOVLP call). Match it here then,
10426 // this is horrible, but will stay like this until we move all shuffle
10427 // matching to x86 specific nodes. Note that for the 1st condition all
10428 // types are matched with movsd.
10430 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
10431 // as to remove this logic from here, as much as possible
10432 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
10433 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
10434 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
10437 assert(VT != MVT::v4i32 && "unsupported shuffle type");
10439 // Invert the operand order and use SHUFPS to match it.
10440 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
10441 getShuffleSHUFImmediate(SVOp), DAG);
10444 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
10445 SelectionDAG &DAG) {
10447 MVT VT = Load->getSimpleValueType(0);
10448 MVT EVT = VT.getVectorElementType();
10449 SDValue Addr = Load->getOperand(1);
10450 SDValue NewAddr = DAG.getNode(
10451 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
10452 DAG.getConstant(Index * EVT.getStoreSize(), Addr.getSimpleValueType()));
10455 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
10456 DAG.getMachineFunction().getMachineMemOperand(
10457 Load->getMemOperand(), 0, EVT.getStoreSize()));
10461 // It is only safe to call this function if isINSERTPSMask is true for
10462 // this shufflevector mask.
10463 static SDValue getINSERTPS(ShuffleVectorSDNode *SVOp, SDLoc &dl,
10464 SelectionDAG &DAG) {
10465 // Generate an insertps instruction when inserting an f32 from memory onto a
10466 // v4f32 or when copying a member from one v4f32 to another.
10467 // We also use it for transferring i32 from one register to another,
10468 // since it simply copies the same bits.
10469 // If we're transferring an i32 from memory to a specific element in a
10470 // register, we output a generic DAG that will match the PINSRD
10472 MVT VT = SVOp->getSimpleValueType(0);
10473 MVT EVT = VT.getVectorElementType();
10474 SDValue V1 = SVOp->getOperand(0);
10475 SDValue V2 = SVOp->getOperand(1);
10476 auto Mask = SVOp->getMask();
10477 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
10478 "unsupported vector type for insertps/pinsrd");
10480 auto FromV1Predicate = [](const int &i) { return i < 4 && i > -1; };
10481 auto FromV2Predicate = [](const int &i) { return i >= 4; };
10482 int FromV1 = std::count_if(Mask.begin(), Mask.end(), FromV1Predicate);
10486 unsigned DestIndex;
10490 DestIndex = std::find_if(Mask.begin(), Mask.end(), FromV1Predicate) -
10493 // If we have 1 element from each vector, we have to check if we're
10494 // changing V1's element's place. If so, we're done. Otherwise, we
10495 // should assume we're changing V2's element's place and behave
10497 int FromV2 = std::count_if(Mask.begin(), Mask.end(), FromV2Predicate);
10498 assert(DestIndex <= INT32_MAX && "truncated destination index");
10499 if (FromV1 == FromV2 &&
10500 static_cast<int>(DestIndex) == Mask[DestIndex] % 4) {
10504 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
10507 assert(std::count_if(Mask.begin(), Mask.end(), FromV2Predicate) == 1 &&
10508 "More than one element from V1 and from V2, or no elements from one "
10509 "of the vectors. This case should not have returned true from "
10514 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
10517 // Get an index into the source vector in the range [0,4) (the mask is
10518 // in the range [0,8) because it can address V1 and V2)
10519 unsigned SrcIndex = Mask[DestIndex] % 4;
10520 if (MayFoldLoad(From)) {
10521 // Trivial case, when From comes from a load and is only used by the
10522 // shuffle. Make it use insertps from the vector that we need from that
10525 NarrowVectorLoadToElement(cast<LoadSDNode>(From), SrcIndex, DAG);
10526 if (!NewLoad.getNode())
10529 if (EVT == MVT::f32) {
10530 // Create this as a scalar to vector to match the instruction pattern.
10531 SDValue LoadScalarToVector =
10532 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, NewLoad);
10533 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4);
10534 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, LoadScalarToVector,
10536 } else { // EVT == MVT::i32
10537 // If we're getting an i32 from memory, use an INSERT_VECTOR_ELT
10538 // instruction, to match the PINSRD instruction, which loads an i32 to a
10539 // certain vector element.
10540 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, To, NewLoad,
10541 DAG.getConstant(DestIndex, MVT::i32));
10545 // Vector-element-to-vector
10546 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4 | SrcIndex << 6);
10547 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, From, InsertpsMask);
10550 // Reduce a vector shuffle to zext.
10551 static SDValue LowerVectorIntExtend(SDValue Op, const X86Subtarget *Subtarget,
10552 SelectionDAG &DAG) {
10553 // PMOVZX is only available from SSE41.
10554 if (!Subtarget->hasSSE41())
10557 MVT VT = Op.getSimpleValueType();
10559 // Only AVX2 support 256-bit vector integer extending.
10560 if (!Subtarget->hasInt256() && VT.is256BitVector())
10563 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10565 SDValue V1 = Op.getOperand(0);
10566 SDValue V2 = Op.getOperand(1);
10567 unsigned NumElems = VT.getVectorNumElements();
10569 // Extending is an unary operation and the element type of the source vector
10570 // won't be equal to or larger than i64.
10571 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
10572 VT.getVectorElementType() == MVT::i64)
10575 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
10576 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
10577 while ((1U << Shift) < NumElems) {
10578 if (SVOp->getMaskElt(1U << Shift) == 1)
10581 // The maximal ratio is 8, i.e. from i8 to i64.
10586 // Check the shuffle mask.
10587 unsigned Mask = (1U << Shift) - 1;
10588 for (unsigned i = 0; i != NumElems; ++i) {
10589 int EltIdx = SVOp->getMaskElt(i);
10590 if ((i & Mask) != 0 && EltIdx != -1)
10592 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift))
10596 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
10597 MVT NeVT = MVT::getIntegerVT(NBits);
10598 MVT NVT = MVT::getVectorVT(NeVT, NumElems >> Shift);
10600 if (!DAG.getTargetLoweringInfo().isTypeLegal(NVT))
10603 // Simplify the operand as it's prepared to be fed into shuffle.
10604 unsigned SignificantBits = NVT.getSizeInBits() >> Shift;
10605 if (V1.getOpcode() == ISD::BITCAST &&
10606 V1.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
10607 V1.getOperand(0).getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
10608 V1.getOperand(0).getOperand(0)
10609 .getSimpleValueType().getSizeInBits() == SignificantBits) {
10610 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
10611 SDValue V = V1.getOperand(0).getOperand(0).getOperand(0);
10612 ConstantSDNode *CIdx =
10613 dyn_cast<ConstantSDNode>(V1.getOperand(0).getOperand(0).getOperand(1));
10614 // If it's foldable, i.e. normal load with single use, we will let code
10615 // selection to fold it. Otherwise, we will short the conversion sequence.
10616 if (CIdx && CIdx->getZExtValue() == 0 &&
10617 (!ISD::isNormalLoad(V.getNode()) || !V.hasOneUse())) {
10618 MVT FullVT = V.getSimpleValueType();
10619 MVT V1VT = V1.getSimpleValueType();
10620 if (FullVT.getSizeInBits() > V1VT.getSizeInBits()) {
10621 // The "ext_vec_elt" node is wider than the result node.
10622 // In this case we should extract subvector from V.
10623 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast (extract_subvector x)).
10624 unsigned Ratio = FullVT.getSizeInBits() / V1VT.getSizeInBits();
10625 MVT SubVecVT = MVT::getVectorVT(FullVT.getVectorElementType(),
10626 FullVT.getVectorNumElements()/Ratio);
10627 V = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVecVT, V,
10628 DAG.getIntPtrConstant(0));
10630 V1 = DAG.getNode(ISD::BITCAST, DL, V1VT, V);
10634 return DAG.getNode(ISD::BITCAST, DL, VT,
10635 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
10638 static SDValue NormalizeVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
10639 SelectionDAG &DAG) {
10640 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10641 MVT VT = Op.getSimpleValueType();
10643 SDValue V1 = Op.getOperand(0);
10644 SDValue V2 = Op.getOperand(1);
10646 if (isZeroShuffle(SVOp))
10647 return getZeroVector(VT, Subtarget, DAG, dl);
10649 // Handle splat operations
10650 if (SVOp->isSplat()) {
10651 // Use vbroadcast whenever the splat comes from a foldable load
10652 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
10653 if (Broadcast.getNode())
10657 // Check integer expanding shuffles.
10658 SDValue NewOp = LowerVectorIntExtend(Op, Subtarget, DAG);
10659 if (NewOp.getNode())
10662 // If the shuffle can be profitably rewritten as a narrower shuffle, then
10664 if (VT == MVT::v8i16 || VT == MVT::v16i8 || VT == MVT::v16i16 ||
10665 VT == MVT::v32i8) {
10666 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
10667 if (NewOp.getNode())
10668 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
10669 } else if (VT.is128BitVector() && Subtarget->hasSSE2()) {
10670 // FIXME: Figure out a cleaner way to do this.
10671 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
10672 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
10673 if (NewOp.getNode()) {
10674 MVT NewVT = NewOp.getSimpleValueType();
10675 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
10676 NewVT, true, false))
10677 return getVZextMovL(VT, NewVT, NewOp.getOperand(0), DAG, Subtarget,
10680 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
10681 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
10682 if (NewOp.getNode()) {
10683 MVT NewVT = NewOp.getSimpleValueType();
10684 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
10685 return getVZextMovL(VT, NewVT, NewOp.getOperand(1), DAG, Subtarget,
10694 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
10695 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10696 SDValue V1 = Op.getOperand(0);
10697 SDValue V2 = Op.getOperand(1);
10698 MVT VT = Op.getSimpleValueType();
10700 unsigned NumElems = VT.getVectorNumElements();
10701 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
10702 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10703 bool V1IsSplat = false;
10704 bool V2IsSplat = false;
10705 bool HasSSE2 = Subtarget->hasSSE2();
10706 bool HasFp256 = Subtarget->hasFp256();
10707 bool HasInt256 = Subtarget->hasInt256();
10708 MachineFunction &MF = DAG.getMachineFunction();
10709 bool OptForSize = MF.getFunction()->getAttributes().
10710 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
10712 // Check if we should use the experimental vector shuffle lowering. If so,
10713 // delegate completely to that code path.
10714 if (ExperimentalVectorShuffleLowering)
10715 return lowerVectorShuffle(Op, Subtarget, DAG);
10717 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
10719 if (V1IsUndef && V2IsUndef)
10720 return DAG.getUNDEF(VT);
10722 // When we create a shuffle node we put the UNDEF node to second operand,
10723 // but in some cases the first operand may be transformed to UNDEF.
10724 // In this case we should just commute the node.
10726 return DAG.getCommutedVectorShuffle(*SVOp);
10728 // Vector shuffle lowering takes 3 steps:
10730 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
10731 // narrowing and commutation of operands should be handled.
10732 // 2) Matching of shuffles with known shuffle masks to x86 target specific
10734 // 3) Rewriting of unmatched masks into new generic shuffle operations,
10735 // so the shuffle can be broken into other shuffles and the legalizer can
10736 // try the lowering again.
10738 // The general idea is that no vector_shuffle operation should be left to
10739 // be matched during isel, all of them must be converted to a target specific
10742 // Normalize the input vectors. Here splats, zeroed vectors, profitable
10743 // narrowing and commutation of operands should be handled. The actual code
10744 // doesn't include all of those, work in progress...
10745 SDValue NewOp = NormalizeVectorShuffle(Op, Subtarget, DAG);
10746 if (NewOp.getNode())
10749 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
10751 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
10752 // unpckh_undef). Only use pshufd if speed is more important than size.
10753 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
10754 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
10755 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
10756 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
10758 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
10759 V2IsUndef && MayFoldVectorLoad(V1))
10760 return getMOVDDup(Op, dl, V1, DAG);
10762 if (isMOVHLPS_v_undef_Mask(M, VT))
10763 return getMOVHighToLow(Op, dl, DAG);
10765 // Use to match splats
10766 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
10767 (VT == MVT::v2f64 || VT == MVT::v2i64))
10768 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
10770 if (isPSHUFDMask(M, VT)) {
10771 // The actual implementation will match the mask in the if above and then
10772 // during isel it can match several different instructions, not only pshufd
10773 // as its name says, sad but true, emulate the behavior for now...
10774 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
10775 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
10777 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
10779 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
10780 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
10782 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
10783 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, TargetMask,
10786 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
10790 if (isPALIGNRMask(M, VT, Subtarget))
10791 return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
10792 getShufflePALIGNRImmediate(SVOp),
10795 if (isVALIGNMask(M, VT, Subtarget))
10796 return getTargetShuffleNode(X86ISD::VALIGN, dl, VT, V1, V2,
10797 getShuffleVALIGNImmediate(SVOp),
10800 // Check if this can be converted into a logical shift.
10801 bool isLeft = false;
10802 unsigned ShAmt = 0;
10804 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
10805 if (isShift && ShVal.hasOneUse()) {
10806 // If the shifted value has multiple uses, it may be cheaper to use
10807 // v_set0 + movlhps or movhlps, etc.
10808 MVT EltVT = VT.getVectorElementType();
10809 ShAmt *= EltVT.getSizeInBits();
10810 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
10813 if (isMOVLMask(M, VT)) {
10814 if (ISD::isBuildVectorAllZeros(V1.getNode()))
10815 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
10816 if (!isMOVLPMask(M, VT)) {
10817 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
10818 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
10820 if (VT == MVT::v4i32 || VT == MVT::v4f32)
10821 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
10825 // FIXME: fold these into legal mask.
10826 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
10827 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
10829 if (isMOVHLPSMask(M, VT))
10830 return getMOVHighToLow(Op, dl, DAG);
10832 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
10833 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
10835 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
10836 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
10838 if (isMOVLPMask(M, VT))
10839 return getMOVLP(Op, dl, DAG, HasSSE2);
10841 if (ShouldXformToMOVHLPS(M, VT) ||
10842 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
10843 return DAG.getCommutedVectorShuffle(*SVOp);
10846 // No better options. Use a vshldq / vsrldq.
10847 MVT EltVT = VT.getVectorElementType();
10848 ShAmt *= EltVT.getSizeInBits();
10849 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
10852 bool Commuted = false;
10853 // FIXME: This should also accept a bitcast of a splat? Be careful, not
10854 // 1,1,1,1 -> v8i16 though.
10855 BitVector UndefElements;
10856 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V1.getNode()))
10857 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
10859 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V2.getNode()))
10860 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
10863 // Canonicalize the splat or undef, if present, to be on the RHS.
10864 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
10865 CommuteVectorShuffleMask(M, NumElems);
10867 std::swap(V1IsSplat, V2IsSplat);
10871 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
10872 // Shuffling low element of v1 into undef, just return v1.
10875 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
10876 // the instruction selector will not match, so get a canonical MOVL with
10877 // swapped operands to undo the commute.
10878 return getMOVL(DAG, dl, VT, V2, V1);
10881 if (isUNPCKLMask(M, VT, HasInt256))
10882 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
10884 if (isUNPCKHMask(M, VT, HasInt256))
10885 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
10888 // Normalize mask so all entries that point to V2 points to its first
10889 // element then try to match unpck{h|l} again. If match, return a
10890 // new vector_shuffle with the corrected mask.p
10891 SmallVector<int, 8> NewMask(M.begin(), M.end());
10892 NormalizeMask(NewMask, NumElems);
10893 if (isUNPCKLMask(NewMask, VT, HasInt256, true))
10894 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
10895 if (isUNPCKHMask(NewMask, VT, HasInt256, true))
10896 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
10900 // Commute is back and try unpck* again.
10901 // FIXME: this seems wrong.
10902 CommuteVectorShuffleMask(M, NumElems);
10904 std::swap(V1IsSplat, V2IsSplat);
10906 if (isUNPCKLMask(M, VT, HasInt256))
10907 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
10909 if (isUNPCKHMask(M, VT, HasInt256))
10910 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
10913 // Normalize the node to match x86 shuffle ops if needed
10914 if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true)))
10915 return DAG.getCommutedVectorShuffle(*SVOp);
10917 // The checks below are all present in isShuffleMaskLegal, but they are
10918 // inlined here right now to enable us to directly emit target specific
10919 // nodes, and remove one by one until they don't return Op anymore.
10921 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
10922 SVOp->getSplatIndex() == 0 && V2IsUndef) {
10923 if (VT == MVT::v2f64 || VT == MVT::v2i64)
10924 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
10927 if (isPSHUFHWMask(M, VT, HasInt256))
10928 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
10929 getShufflePSHUFHWImmediate(SVOp),
10932 if (isPSHUFLWMask(M, VT, HasInt256))
10933 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
10934 getShufflePSHUFLWImmediate(SVOp),
10937 unsigned MaskValue;
10938 if (isBlendMask(M, VT, Subtarget->hasSSE41(), Subtarget->hasInt256(),
10940 return LowerVECTOR_SHUFFLEtoBlend(SVOp, MaskValue, Subtarget, DAG);
10942 if (isSHUFPMask(M, VT))
10943 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
10944 getShuffleSHUFImmediate(SVOp), DAG);
10946 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
10947 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
10948 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
10949 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
10951 //===--------------------------------------------------------------------===//
10952 // Generate target specific nodes for 128 or 256-bit shuffles only
10953 // supported in the AVX instruction set.
10956 // Handle VMOVDDUPY permutations
10957 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
10958 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
10960 // Handle VPERMILPS/D* permutations
10961 if (isVPERMILPMask(M, VT)) {
10962 if ((HasInt256 && VT == MVT::v8i32) || VT == MVT::v16i32)
10963 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
10964 getShuffleSHUFImmediate(SVOp), DAG);
10965 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1,
10966 getShuffleSHUFImmediate(SVOp), DAG);
10970 if (VT.is512BitVector() && isINSERT64x4Mask(M, VT, &Idx))
10971 return Insert256BitVector(V1, Extract256BitVector(V2, 0, DAG, dl),
10972 Idx*(NumElems/2), DAG, dl);
10974 // Handle VPERM2F128/VPERM2I128 permutations
10975 if (isVPERM2X128Mask(M, VT, HasFp256))
10976 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
10977 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
10979 if (Subtarget->hasSSE41() && isINSERTPSMask(M, VT))
10980 return getINSERTPS(SVOp, dl, DAG);
10983 if (V2IsUndef && HasInt256 && isPermImmMask(M, VT, Imm8))
10984 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, Imm8, DAG);
10986 if ((V2IsUndef && HasInt256 && VT.is256BitVector() && NumElems == 8) ||
10987 VT.is512BitVector()) {
10988 MVT MaskEltVT = MVT::getIntegerVT(VT.getVectorElementType().getSizeInBits());
10989 MVT MaskVectorVT = MVT::getVectorVT(MaskEltVT, NumElems);
10990 SmallVector<SDValue, 16> permclMask;
10991 for (unsigned i = 0; i != NumElems; ++i) {
10992 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MaskEltVT));
10995 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVectorVT, permclMask);
10997 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
10998 return DAG.getNode(X86ISD::VPERMV, dl, VT,
10999 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
11000 return DAG.getNode(X86ISD::VPERMV3, dl, VT, V1,
11001 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V2);
11004 //===--------------------------------------------------------------------===//
11005 // Since no target specific shuffle was selected for this generic one,
11006 // lower it into other known shuffles. FIXME: this isn't true yet, but
11007 // this is the plan.
11010 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
11011 if (VT == MVT::v8i16) {
11012 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
11013 if (NewOp.getNode())
11017 if (VT == MVT::v16i16 && Subtarget->hasInt256()) {
11018 SDValue NewOp = LowerVECTOR_SHUFFLEv16i16(Op, DAG);
11019 if (NewOp.getNode())
11023 if (VT == MVT::v16i8) {
11024 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, Subtarget, DAG);
11025 if (NewOp.getNode())
11029 if (VT == MVT::v32i8) {
11030 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
11031 if (NewOp.getNode())
11035 // Handle all 128-bit wide vectors with 4 elements, and match them with
11036 // several different shuffle types.
11037 if (NumElems == 4 && VT.is128BitVector())
11038 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
11040 // Handle general 256-bit shuffles
11041 if (VT.is256BitVector())
11042 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
11047 // This function assumes its argument is a BUILD_VECTOR of constants or
11048 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
11050 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
11051 unsigned &MaskValue) {
11053 unsigned NumElems = BuildVector->getNumOperands();
11054 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
11055 unsigned NumLanes = (NumElems - 1) / 8 + 1;
11056 unsigned NumElemsInLane = NumElems / NumLanes;
11058 // Blend for v16i16 should be symetric for the both lanes.
11059 for (unsigned i = 0; i < NumElemsInLane; ++i) {
11060 SDValue EltCond = BuildVector->getOperand(i);
11061 SDValue SndLaneEltCond =
11062 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
11064 int Lane1Cond = -1, Lane2Cond = -1;
11065 if (isa<ConstantSDNode>(EltCond))
11066 Lane1Cond = !isZero(EltCond);
11067 if (isa<ConstantSDNode>(SndLaneEltCond))
11068 Lane2Cond = !isZero(SndLaneEltCond);
11070 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
11071 // Lane1Cond != 0, means we want the first argument.
11072 // Lane1Cond == 0, means we want the second argument.
11073 // The encoding of this argument is 0 for the first argument, 1
11074 // for the second. Therefore, invert the condition.
11075 MaskValue |= !Lane1Cond << i;
11076 else if (Lane1Cond < 0)
11077 MaskValue |= !Lane2Cond << i;
11084 // Try to lower a vselect node into a simple blend instruction.
11085 static SDValue LowerVSELECTtoBlend(SDValue Op, const X86Subtarget *Subtarget,
11086 SelectionDAG &DAG) {
11087 SDValue Cond = Op.getOperand(0);
11088 SDValue LHS = Op.getOperand(1);
11089 SDValue RHS = Op.getOperand(2);
11091 MVT VT = Op.getSimpleValueType();
11092 MVT EltVT = VT.getVectorElementType();
11093 unsigned NumElems = VT.getVectorNumElements();
11095 // There is no blend with immediate in AVX-512.
11096 if (VT.is512BitVector())
11099 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
11101 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
11104 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
11107 // Check the mask for BLEND and build the value.
11108 unsigned MaskValue = 0;
11109 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
11112 // Convert i32 vectors to floating point if it is not AVX2.
11113 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
11115 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
11116 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
11118 LHS = DAG.getNode(ISD::BITCAST, dl, VT, LHS);
11119 RHS = DAG.getNode(ISD::BITCAST, dl, VT, RHS);
11122 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, LHS, RHS,
11123 DAG.getConstant(MaskValue, MVT::i32));
11124 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
11127 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
11128 // A vselect where all conditions and data are constants can be optimized into
11129 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
11130 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
11131 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
11132 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
11135 SDValue BlendOp = LowerVSELECTtoBlend(Op, Subtarget, DAG);
11136 if (BlendOp.getNode())
11139 // Some types for vselect were previously set to Expand, not Legal or
11140 // Custom. Return an empty SDValue so we fall-through to Expand, after
11141 // the Custom lowering phase.
11142 MVT VT = Op.getSimpleValueType();
11143 switch (VT.SimpleTy) {
11148 if (Subtarget->hasBWI() && Subtarget->hasVLX())
11153 // We couldn't create a "Blend with immediate" node.
11154 // This node should still be legal, but we'll have to emit a blendv*
11159 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
11160 MVT VT = Op.getSimpleValueType();
11163 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
11166 if (VT.getSizeInBits() == 8) {
11167 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
11168 Op.getOperand(0), Op.getOperand(1));
11169 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
11170 DAG.getValueType(VT));
11171 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11174 if (VT.getSizeInBits() == 16) {
11175 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11176 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
11178 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
11179 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11180 DAG.getNode(ISD::BITCAST, dl,
11183 Op.getOperand(1)));
11184 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
11185 Op.getOperand(0), Op.getOperand(1));
11186 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
11187 DAG.getValueType(VT));
11188 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11191 if (VT == MVT::f32) {
11192 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
11193 // the result back to FR32 register. It's only worth matching if the
11194 // result has a single use which is a store or a bitcast to i32. And in
11195 // the case of a store, it's not worth it if the index is a constant 0,
11196 // because a MOVSSmr can be used instead, which is smaller and faster.
11197 if (!Op.hasOneUse())
11199 SDNode *User = *Op.getNode()->use_begin();
11200 if ((User->getOpcode() != ISD::STORE ||
11201 (isa<ConstantSDNode>(Op.getOperand(1)) &&
11202 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
11203 (User->getOpcode() != ISD::BITCAST ||
11204 User->getValueType(0) != MVT::i32))
11206 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11207 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
11210 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
11213 if (VT == MVT::i32 || VT == MVT::i64) {
11214 // ExtractPS/pextrq works with constant index.
11215 if (isa<ConstantSDNode>(Op.getOperand(1)))
11221 /// Extract one bit from mask vector, like v16i1 or v8i1.
11222 /// AVX-512 feature.
11224 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
11225 SDValue Vec = Op.getOperand(0);
11227 MVT VecVT = Vec.getSimpleValueType();
11228 SDValue Idx = Op.getOperand(1);
11229 MVT EltVT = Op.getSimpleValueType();
11231 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
11233 // variable index can't be handled in mask registers,
11234 // extend vector to VR512
11235 if (!isa<ConstantSDNode>(Idx)) {
11236 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
11237 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
11238 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
11239 ExtVT.getVectorElementType(), Ext, Idx);
11240 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
11243 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11244 const TargetRegisterClass* rc = getRegClassFor(VecVT);
11245 unsigned MaxSift = rc->getSize()*8 - 1;
11246 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
11247 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
11248 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
11249 DAG.getConstant(MaxSift, MVT::i8));
11250 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
11251 DAG.getIntPtrConstant(0));
11255 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
11256 SelectionDAG &DAG) const {
11258 SDValue Vec = Op.getOperand(0);
11259 MVT VecVT = Vec.getSimpleValueType();
11260 SDValue Idx = Op.getOperand(1);
11262 if (Op.getSimpleValueType() == MVT::i1)
11263 return ExtractBitFromMaskVector(Op, DAG);
11265 if (!isa<ConstantSDNode>(Idx)) {
11266 if (VecVT.is512BitVector() ||
11267 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
11268 VecVT.getVectorElementType().getSizeInBits() == 32)) {
11271 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
11272 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
11273 MaskEltVT.getSizeInBits());
11275 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
11276 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
11277 getZeroVector(MaskVT, Subtarget, DAG, dl),
11278 Idx, DAG.getConstant(0, getPointerTy()));
11279 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
11280 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
11281 Perm, DAG.getConstant(0, getPointerTy()));
11286 // If this is a 256-bit vector result, first extract the 128-bit vector and
11287 // then extract the element from the 128-bit vector.
11288 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
11290 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11291 // Get the 128-bit vector.
11292 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
11293 MVT EltVT = VecVT.getVectorElementType();
11295 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
11297 //if (IdxVal >= NumElems/2)
11298 // IdxVal -= NumElems/2;
11299 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
11300 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
11301 DAG.getConstant(IdxVal, MVT::i32));
11304 assert(VecVT.is128BitVector() && "Unexpected vector length");
11306 if (Subtarget->hasSSE41()) {
11307 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
11312 MVT VT = Op.getSimpleValueType();
11313 // TODO: handle v16i8.
11314 if (VT.getSizeInBits() == 16) {
11315 SDValue Vec = Op.getOperand(0);
11316 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11318 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
11319 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11320 DAG.getNode(ISD::BITCAST, dl,
11322 Op.getOperand(1)));
11323 // Transform it so it match pextrw which produces a 32-bit result.
11324 MVT EltVT = MVT::i32;
11325 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
11326 Op.getOperand(0), Op.getOperand(1));
11327 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
11328 DAG.getValueType(VT));
11329 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11332 if (VT.getSizeInBits() == 32) {
11333 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11337 // SHUFPS the element to the lowest double word, then movss.
11338 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
11339 MVT VVT = Op.getOperand(0).getSimpleValueType();
11340 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
11341 DAG.getUNDEF(VVT), Mask);
11342 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
11343 DAG.getIntPtrConstant(0));
11346 if (VT.getSizeInBits() == 64) {
11347 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
11348 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
11349 // to match extract_elt for f64.
11350 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11354 // UNPCKHPD the element to the lowest double word, then movsd.
11355 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
11356 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
11357 int Mask[2] = { 1, -1 };
11358 MVT VVT = Op.getOperand(0).getSimpleValueType();
11359 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
11360 DAG.getUNDEF(VVT), Mask);
11361 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
11362 DAG.getIntPtrConstant(0));
11368 /// Insert one bit to mask vector, like v16i1 or v8i1.
11369 /// AVX-512 feature.
11371 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
11373 SDValue Vec = Op.getOperand(0);
11374 SDValue Elt = Op.getOperand(1);
11375 SDValue Idx = Op.getOperand(2);
11376 MVT VecVT = Vec.getSimpleValueType();
11378 if (!isa<ConstantSDNode>(Idx)) {
11379 // Non constant index. Extend source and destination,
11380 // insert element and then truncate the result.
11381 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
11382 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
11383 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
11384 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
11385 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
11386 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
11389 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11390 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
11391 if (Vec.getOpcode() == ISD::UNDEF)
11392 return DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
11393 DAG.getConstant(IdxVal, MVT::i8));
11394 const TargetRegisterClass* rc = getRegClassFor(VecVT);
11395 unsigned MaxSift = rc->getSize()*8 - 1;
11396 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
11397 DAG.getConstant(MaxSift, MVT::i8));
11398 EltInVec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, EltInVec,
11399 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
11400 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
11403 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
11404 SelectionDAG &DAG) const {
11405 MVT VT = Op.getSimpleValueType();
11406 MVT EltVT = VT.getVectorElementType();
11408 if (EltVT == MVT::i1)
11409 return InsertBitToMaskVector(Op, DAG);
11412 SDValue N0 = Op.getOperand(0);
11413 SDValue N1 = Op.getOperand(1);
11414 SDValue N2 = Op.getOperand(2);
11415 if (!isa<ConstantSDNode>(N2))
11417 auto *N2C = cast<ConstantSDNode>(N2);
11418 unsigned IdxVal = N2C->getZExtValue();
11420 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
11421 // into that, and then insert the subvector back into the result.
11422 if (VT.is256BitVector() || VT.is512BitVector()) {
11423 // Get the desired 128-bit vector half.
11424 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
11426 // Insert the element into the desired half.
11427 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
11428 unsigned IdxIn128 = IdxVal - (IdxVal / NumEltsIn128) * NumEltsIn128;
11430 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
11431 DAG.getConstant(IdxIn128, MVT::i32));
11433 // Insert the changed part back to the 256-bit vector
11434 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
11436 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
11438 if (Subtarget->hasSSE41()) {
11439 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
11441 if (VT == MVT::v8i16) {
11442 Opc = X86ISD::PINSRW;
11444 assert(VT == MVT::v16i8);
11445 Opc = X86ISD::PINSRB;
11448 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
11450 if (N1.getValueType() != MVT::i32)
11451 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
11452 if (N2.getValueType() != MVT::i32)
11453 N2 = DAG.getIntPtrConstant(IdxVal);
11454 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
11457 if (EltVT == MVT::f32) {
11458 // Bits [7:6] of the constant are the source select. This will always be
11459 // zero here. The DAG Combiner may combine an extract_elt index into
11461 // bits. For example (insert (extract, 3), 2) could be matched by
11463 // the '3' into bits [7:6] of X86ISD::INSERTPS.
11464 // Bits [5:4] of the constant are the destination select. This is the
11465 // value of the incoming immediate.
11466 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
11467 // combine either bitwise AND or insert of float 0.0 to set these bits.
11468 N2 = DAG.getIntPtrConstant(IdxVal << 4);
11469 // Create this as a scalar to vector..
11470 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
11471 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
11474 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
11475 // PINSR* works with constant index.
11480 if (EltVT == MVT::i8)
11483 if (EltVT.getSizeInBits() == 16) {
11484 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
11485 // as its second argument.
11486 if (N1.getValueType() != MVT::i32)
11487 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
11488 if (N2.getValueType() != MVT::i32)
11489 N2 = DAG.getIntPtrConstant(IdxVal);
11490 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
11495 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
11497 MVT OpVT = Op.getSimpleValueType();
11499 // If this is a 256-bit vector result, first insert into a 128-bit
11500 // vector and then insert into the 256-bit vector.
11501 if (!OpVT.is128BitVector()) {
11502 // Insert into a 128-bit vector.
11503 unsigned SizeFactor = OpVT.getSizeInBits()/128;
11504 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
11505 OpVT.getVectorNumElements() / SizeFactor);
11507 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
11509 // Insert the 128-bit vector.
11510 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
11513 if (OpVT == MVT::v1i64 &&
11514 Op.getOperand(0).getValueType() == MVT::i64)
11515 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
11517 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
11518 assert(OpVT.is128BitVector() && "Expected an SSE type!");
11519 return DAG.getNode(ISD::BITCAST, dl, OpVT,
11520 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
11523 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
11524 // a simple subregister reference or explicit instructions to grab
11525 // upper bits of a vector.
11526 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
11527 SelectionDAG &DAG) {
11529 SDValue In = Op.getOperand(0);
11530 SDValue Idx = Op.getOperand(1);
11531 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11532 MVT ResVT = Op.getSimpleValueType();
11533 MVT InVT = In.getSimpleValueType();
11535 if (Subtarget->hasFp256()) {
11536 if (ResVT.is128BitVector() &&
11537 (InVT.is256BitVector() || InVT.is512BitVector()) &&
11538 isa<ConstantSDNode>(Idx)) {
11539 return Extract128BitVector(In, IdxVal, DAG, dl);
11541 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
11542 isa<ConstantSDNode>(Idx)) {
11543 return Extract256BitVector(In, IdxVal, DAG, dl);
11549 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
11550 // simple superregister reference or explicit instructions to insert
11551 // the upper bits of a vector.
11552 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
11553 SelectionDAG &DAG) {
11554 if (Subtarget->hasFp256()) {
11555 SDLoc dl(Op.getNode());
11556 SDValue Vec = Op.getNode()->getOperand(0);
11557 SDValue SubVec = Op.getNode()->getOperand(1);
11558 SDValue Idx = Op.getNode()->getOperand(2);
11560 if ((Op.getNode()->getSimpleValueType(0).is256BitVector() ||
11561 Op.getNode()->getSimpleValueType(0).is512BitVector()) &&
11562 SubVec.getNode()->getSimpleValueType(0).is128BitVector() &&
11563 isa<ConstantSDNode>(Idx)) {
11564 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11565 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
11568 if (Op.getNode()->getSimpleValueType(0).is512BitVector() &&
11569 SubVec.getNode()->getSimpleValueType(0).is256BitVector() &&
11570 isa<ConstantSDNode>(Idx)) {
11571 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11572 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
11578 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
11579 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
11580 // one of the above mentioned nodes. It has to be wrapped because otherwise
11581 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
11582 // be used to form addressing mode. These wrapped nodes will be selected
11585 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
11586 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
11588 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11589 // global base reg.
11590 unsigned char OpFlag = 0;
11591 unsigned WrapperKind = X86ISD::Wrapper;
11592 CodeModel::Model M = DAG.getTarget().getCodeModel();
11594 if (Subtarget->isPICStyleRIPRel() &&
11595 (M == CodeModel::Small || M == CodeModel::Kernel))
11596 WrapperKind = X86ISD::WrapperRIP;
11597 else if (Subtarget->isPICStyleGOT())
11598 OpFlag = X86II::MO_GOTOFF;
11599 else if (Subtarget->isPICStyleStubPIC())
11600 OpFlag = X86II::MO_PIC_BASE_OFFSET;
11602 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
11603 CP->getAlignment(),
11604 CP->getOffset(), OpFlag);
11606 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
11607 // With PIC, the address is actually $g + Offset.
11609 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11610 DAG.getNode(X86ISD::GlobalBaseReg,
11611 SDLoc(), getPointerTy()),
11618 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
11619 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
11621 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11622 // global base reg.
11623 unsigned char OpFlag = 0;
11624 unsigned WrapperKind = X86ISD::Wrapper;
11625 CodeModel::Model M = DAG.getTarget().getCodeModel();
11627 if (Subtarget->isPICStyleRIPRel() &&
11628 (M == CodeModel::Small || M == CodeModel::Kernel))
11629 WrapperKind = X86ISD::WrapperRIP;
11630 else if (Subtarget->isPICStyleGOT())
11631 OpFlag = X86II::MO_GOTOFF;
11632 else if (Subtarget->isPICStyleStubPIC())
11633 OpFlag = X86II::MO_PIC_BASE_OFFSET;
11635 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
11638 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
11640 // With PIC, the address is actually $g + Offset.
11642 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11643 DAG.getNode(X86ISD::GlobalBaseReg,
11644 SDLoc(), getPointerTy()),
11651 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
11652 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
11654 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11655 // global base reg.
11656 unsigned char OpFlag = 0;
11657 unsigned WrapperKind = X86ISD::Wrapper;
11658 CodeModel::Model M = DAG.getTarget().getCodeModel();
11660 if (Subtarget->isPICStyleRIPRel() &&
11661 (M == CodeModel::Small || M == CodeModel::Kernel)) {
11662 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
11663 OpFlag = X86II::MO_GOTPCREL;
11664 WrapperKind = X86ISD::WrapperRIP;
11665 } else if (Subtarget->isPICStyleGOT()) {
11666 OpFlag = X86II::MO_GOT;
11667 } else if (Subtarget->isPICStyleStubPIC()) {
11668 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
11669 } else if (Subtarget->isPICStyleStubNoDynamic()) {
11670 OpFlag = X86II::MO_DARWIN_NONLAZY;
11673 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
11676 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
11678 // With PIC, the address is actually $g + Offset.
11679 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
11680 !Subtarget->is64Bit()) {
11681 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11682 DAG.getNode(X86ISD::GlobalBaseReg,
11683 SDLoc(), getPointerTy()),
11687 // For symbols that require a load from a stub to get the address, emit the
11689 if (isGlobalStubReference(OpFlag))
11690 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
11691 MachinePointerInfo::getGOT(), false, false, false, 0);
11697 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
11698 // Create the TargetBlockAddressAddress node.
11699 unsigned char OpFlags =
11700 Subtarget->ClassifyBlockAddressReference();
11701 CodeModel::Model M = DAG.getTarget().getCodeModel();
11702 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
11703 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
11705 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
11708 if (Subtarget->isPICStyleRIPRel() &&
11709 (M == CodeModel::Small || M == CodeModel::Kernel))
11710 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
11712 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
11714 // With PIC, the address is actually $g + Offset.
11715 if (isGlobalRelativeToPICBase(OpFlags)) {
11716 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
11717 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
11725 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
11726 int64_t Offset, SelectionDAG &DAG) const {
11727 // Create the TargetGlobalAddress node, folding in the constant
11728 // offset if it is legal.
11729 unsigned char OpFlags =
11730 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
11731 CodeModel::Model M = DAG.getTarget().getCodeModel();
11733 if (OpFlags == X86II::MO_NO_FLAG &&
11734 X86::isOffsetSuitableForCodeModel(Offset, M)) {
11735 // A direct static reference to a global.
11736 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
11739 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
11742 if (Subtarget->isPICStyleRIPRel() &&
11743 (M == CodeModel::Small || M == CodeModel::Kernel))
11744 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
11746 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
11748 // With PIC, the address is actually $g + Offset.
11749 if (isGlobalRelativeToPICBase(OpFlags)) {
11750 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
11751 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
11755 // For globals that require a load from a stub to get the address, emit the
11757 if (isGlobalStubReference(OpFlags))
11758 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
11759 MachinePointerInfo::getGOT(), false, false, false, 0);
11761 // If there was a non-zero offset that we didn't fold, create an explicit
11762 // addition for it.
11764 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
11765 DAG.getConstant(Offset, getPointerTy()));
11771 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
11772 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
11773 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
11774 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
11778 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
11779 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
11780 unsigned char OperandFlags, bool LocalDynamic = false) {
11781 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
11782 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
11784 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11785 GA->getValueType(0),
11789 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
11793 SDValue Ops[] = { Chain, TGA, *InFlag };
11794 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
11796 SDValue Ops[] = { Chain, TGA };
11797 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
11800 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
11801 MFI->setAdjustsStack(true);
11803 SDValue Flag = Chain.getValue(1);
11804 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
11807 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
11809 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11812 SDLoc dl(GA); // ? function entry point might be better
11813 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
11814 DAG.getNode(X86ISD::GlobalBaseReg,
11815 SDLoc(), PtrVT), InFlag);
11816 InFlag = Chain.getValue(1);
11818 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
11821 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
11823 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11825 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
11826 X86::RAX, X86II::MO_TLSGD);
11829 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
11835 // Get the start address of the TLS block for this module.
11836 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
11837 .getInfo<X86MachineFunctionInfo>();
11838 MFI->incNumLocalDynamicTLSAccesses();
11842 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
11843 X86II::MO_TLSLD, /*LocalDynamic=*/true);
11846 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
11847 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
11848 InFlag = Chain.getValue(1);
11849 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
11850 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
11853 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
11857 unsigned char OperandFlags = X86II::MO_DTPOFF;
11858 unsigned WrapperKind = X86ISD::Wrapper;
11859 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11860 GA->getValueType(0),
11861 GA->getOffset(), OperandFlags);
11862 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
11864 // Add x@dtpoff with the base.
11865 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
11868 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
11869 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11870 const EVT PtrVT, TLSModel::Model model,
11871 bool is64Bit, bool isPIC) {
11874 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
11875 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
11876 is64Bit ? 257 : 256));
11878 SDValue ThreadPointer =
11879 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0),
11880 MachinePointerInfo(Ptr), false, false, false, 0);
11882 unsigned char OperandFlags = 0;
11883 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
11885 unsigned WrapperKind = X86ISD::Wrapper;
11886 if (model == TLSModel::LocalExec) {
11887 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
11888 } else if (model == TLSModel::InitialExec) {
11890 OperandFlags = X86II::MO_GOTTPOFF;
11891 WrapperKind = X86ISD::WrapperRIP;
11893 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
11896 llvm_unreachable("Unexpected model");
11899 // emit "addl x@ntpoff,%eax" (local exec)
11900 // or "addl x@indntpoff,%eax" (initial exec)
11901 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
11903 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
11904 GA->getOffset(), OperandFlags);
11905 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
11907 if (model == TLSModel::InitialExec) {
11908 if (isPIC && !is64Bit) {
11909 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
11910 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
11914 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
11915 MachinePointerInfo::getGOT(), false, false, false, 0);
11918 // The address of the thread local variable is the add of the thread
11919 // pointer with the offset of the variable.
11920 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
11924 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
11926 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
11927 const GlobalValue *GV = GA->getGlobal();
11929 if (Subtarget->isTargetELF()) {
11930 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
11933 case TLSModel::GeneralDynamic:
11934 if (Subtarget->is64Bit())
11935 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
11936 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
11937 case TLSModel::LocalDynamic:
11938 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
11939 Subtarget->is64Bit());
11940 case TLSModel::InitialExec:
11941 case TLSModel::LocalExec:
11942 return LowerToTLSExecModel(
11943 GA, DAG, getPointerTy(), model, Subtarget->is64Bit(),
11944 DAG.getTarget().getRelocationModel() == Reloc::PIC_);
11946 llvm_unreachable("Unknown TLS model.");
11949 if (Subtarget->isTargetDarwin()) {
11950 // Darwin only has one model of TLS. Lower to that.
11951 unsigned char OpFlag = 0;
11952 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
11953 X86ISD::WrapperRIP : X86ISD::Wrapper;
11955 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11956 // global base reg.
11957 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
11958 !Subtarget->is64Bit();
11960 OpFlag = X86II::MO_TLVP_PIC_BASE;
11962 OpFlag = X86II::MO_TLVP;
11964 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
11965 GA->getValueType(0),
11966 GA->getOffset(), OpFlag);
11967 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
11969 // With PIC32, the address is actually $g + Offset.
11971 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11972 DAG.getNode(X86ISD::GlobalBaseReg,
11973 SDLoc(), getPointerTy()),
11976 // Lowering the machine isd will make sure everything is in the right
11978 SDValue Chain = DAG.getEntryNode();
11979 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
11980 SDValue Args[] = { Chain, Offset };
11981 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
11983 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
11984 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
11985 MFI->setAdjustsStack(true);
11987 // And our return value (tls address) is in the standard call return value
11989 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
11990 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
11991 Chain.getValue(1));
11994 if (Subtarget->isTargetKnownWindowsMSVC() ||
11995 Subtarget->isTargetWindowsGNU()) {
11996 // Just use the implicit TLS architecture
11997 // Need to generate someting similar to:
11998 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
12000 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
12001 // mov rcx, qword [rdx+rcx*8]
12002 // mov eax, .tls$:tlsvar
12003 // [rax+rcx] contains the address
12004 // Windows 64bit: gs:0x58
12005 // Windows 32bit: fs:__tls_array
12008 SDValue Chain = DAG.getEntryNode();
12010 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
12011 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
12012 // use its literal value of 0x2C.
12013 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
12014 ? Type::getInt8PtrTy(*DAG.getContext(),
12016 : Type::getInt32PtrTy(*DAG.getContext(),
12020 Subtarget->is64Bit()
12021 ? DAG.getIntPtrConstant(0x58)
12022 : (Subtarget->isTargetWindowsGNU()
12023 ? DAG.getIntPtrConstant(0x2C)
12024 : DAG.getExternalSymbol("_tls_array", getPointerTy()));
12026 SDValue ThreadPointer =
12027 DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
12028 MachinePointerInfo(Ptr), false, false, false, 0);
12030 // Load the _tls_index variable
12031 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
12032 if (Subtarget->is64Bit())
12033 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
12034 IDX, MachinePointerInfo(), MVT::i32,
12035 false, false, false, 0);
12037 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
12038 false, false, false, 0);
12040 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
12042 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
12044 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
12045 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
12046 false, false, false, 0);
12048 // Get the offset of start of .tls section
12049 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12050 GA->getValueType(0),
12051 GA->getOffset(), X86II::MO_SECREL);
12052 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
12054 // The address of the thread local variable is the add of the thread
12055 // pointer with the offset of the variable.
12056 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
12059 llvm_unreachable("TLS not implemented for this target.");
12062 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
12063 /// and take a 2 x i32 value to shift plus a shift amount.
12064 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
12065 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
12066 MVT VT = Op.getSimpleValueType();
12067 unsigned VTBits = VT.getSizeInBits();
12069 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
12070 SDValue ShOpLo = Op.getOperand(0);
12071 SDValue ShOpHi = Op.getOperand(1);
12072 SDValue ShAmt = Op.getOperand(2);
12073 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
12074 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
12076 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
12077 DAG.getConstant(VTBits - 1, MVT::i8));
12078 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
12079 DAG.getConstant(VTBits - 1, MVT::i8))
12080 : DAG.getConstant(0, VT);
12082 SDValue Tmp2, Tmp3;
12083 if (Op.getOpcode() == ISD::SHL_PARTS) {
12084 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
12085 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
12087 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
12088 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
12091 // If the shift amount is larger or equal than the width of a part we can't
12092 // rely on the results of shld/shrd. Insert a test and select the appropriate
12093 // values for large shift amounts.
12094 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
12095 DAG.getConstant(VTBits, MVT::i8));
12096 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
12097 AndNode, DAG.getConstant(0, MVT::i8));
12100 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
12101 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
12102 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
12104 if (Op.getOpcode() == ISD::SHL_PARTS) {
12105 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
12106 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
12108 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
12109 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
12112 SDValue Ops[2] = { Lo, Hi };
12113 return DAG.getMergeValues(Ops, dl);
12116 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
12117 SelectionDAG &DAG) const {
12118 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
12120 if (SrcVT.isVector())
12123 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
12124 "Unknown SINT_TO_FP to lower!");
12126 // These are really Legal; return the operand so the caller accepts it as
12128 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
12130 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
12131 Subtarget->is64Bit()) {
12136 unsigned Size = SrcVT.getSizeInBits()/8;
12137 MachineFunction &MF = DAG.getMachineFunction();
12138 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
12139 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
12140 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12142 MachinePointerInfo::getFixedStack(SSFI),
12144 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
12147 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
12149 SelectionDAG &DAG) const {
12153 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
12155 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
12157 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
12159 unsigned ByteSize = SrcVT.getSizeInBits()/8;
12161 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
12162 MachineMemOperand *MMO;
12164 int SSFI = FI->getIndex();
12166 DAG.getMachineFunction()
12167 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12168 MachineMemOperand::MOLoad, ByteSize, ByteSize);
12170 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
12171 StackSlot = StackSlot.getOperand(1);
12173 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
12174 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
12176 Tys, Ops, SrcVT, MMO);
12179 Chain = Result.getValue(1);
12180 SDValue InFlag = Result.getValue(2);
12182 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
12183 // shouldn't be necessary except that RFP cannot be live across
12184 // multiple blocks. When stackifier is fixed, they can be uncoupled.
12185 MachineFunction &MF = DAG.getMachineFunction();
12186 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
12187 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
12188 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
12189 Tys = DAG.getVTList(MVT::Other);
12191 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
12193 MachineMemOperand *MMO =
12194 DAG.getMachineFunction()
12195 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12196 MachineMemOperand::MOStore, SSFISize, SSFISize);
12198 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
12199 Ops, Op.getValueType(), MMO);
12200 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
12201 MachinePointerInfo::getFixedStack(SSFI),
12202 false, false, false, 0);
12208 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
12209 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
12210 SelectionDAG &DAG) const {
12211 // This algorithm is not obvious. Here it is what we're trying to output:
12214 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
12215 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
12217 haddpd %xmm0, %xmm0
12219 pshufd $0x4e, %xmm0, %xmm1
12225 LLVMContext *Context = DAG.getContext();
12227 // Build some magic constants.
12228 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
12229 Constant *C0 = ConstantDataVector::get(*Context, CV0);
12230 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
12232 SmallVector<Constant*,2> CV1;
12234 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
12235 APInt(64, 0x4330000000000000ULL))));
12237 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
12238 APInt(64, 0x4530000000000000ULL))));
12239 Constant *C1 = ConstantVector::get(CV1);
12240 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
12242 // Load the 64-bit value into an XMM register.
12243 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
12245 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
12246 MachinePointerInfo::getConstantPool(),
12247 false, false, false, 16);
12248 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
12249 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
12252 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
12253 MachinePointerInfo::getConstantPool(),
12254 false, false, false, 16);
12255 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
12256 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
12259 if (Subtarget->hasSSE3()) {
12260 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
12261 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
12263 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
12264 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
12266 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
12267 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
12271 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
12272 DAG.getIntPtrConstant(0));
12275 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
12276 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
12277 SelectionDAG &DAG) const {
12279 // FP constant to bias correct the final result.
12280 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
12283 // Load the 32-bit value into an XMM register.
12284 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
12287 // Zero out the upper parts of the register.
12288 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
12290 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
12291 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
12292 DAG.getIntPtrConstant(0));
12294 // Or the load with the bias.
12295 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
12296 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
12297 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
12298 MVT::v2f64, Load)),
12299 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
12300 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
12301 MVT::v2f64, Bias)));
12302 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
12303 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
12304 DAG.getIntPtrConstant(0));
12306 // Subtract the bias.
12307 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
12309 // Handle final rounding.
12310 EVT DestVT = Op.getValueType();
12312 if (DestVT.bitsLT(MVT::f64))
12313 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
12314 DAG.getIntPtrConstant(0));
12315 if (DestVT.bitsGT(MVT::f64))
12316 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
12318 // Handle final rounding.
12322 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
12323 SelectionDAG &DAG) const {
12324 SDValue N0 = Op.getOperand(0);
12325 MVT SVT = N0.getSimpleValueType();
12328 assert((SVT == MVT::v4i8 || SVT == MVT::v4i16 ||
12329 SVT == MVT::v8i8 || SVT == MVT::v8i16) &&
12330 "Custom UINT_TO_FP is not supported!");
12332 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
12333 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
12334 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
12337 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
12338 SelectionDAG &DAG) const {
12339 SDValue N0 = Op.getOperand(0);
12342 if (Op.getValueType().isVector())
12343 return lowerUINT_TO_FP_vec(Op, DAG);
12345 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
12346 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
12347 // the optimization here.
12348 if (DAG.SignBitIsZero(N0))
12349 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
12351 MVT SrcVT = N0.getSimpleValueType();
12352 MVT DstVT = Op.getSimpleValueType();
12353 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
12354 return LowerUINT_TO_FP_i64(Op, DAG);
12355 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
12356 return LowerUINT_TO_FP_i32(Op, DAG);
12357 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
12360 // Make a 64-bit buffer, and use it to build an FILD.
12361 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
12362 if (SrcVT == MVT::i32) {
12363 SDValue WordOff = DAG.getConstant(4, getPointerTy());
12364 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
12365 getPointerTy(), StackSlot, WordOff);
12366 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12367 StackSlot, MachinePointerInfo(),
12369 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
12370 OffsetSlot, MachinePointerInfo(),
12372 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
12376 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
12377 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12378 StackSlot, MachinePointerInfo(),
12380 // For i64 source, we need to add the appropriate power of 2 if the input
12381 // was negative. This is the same as the optimization in
12382 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
12383 // we must be careful to do the computation in x87 extended precision, not
12384 // in SSE. (The generic code can't know it's OK to do this, or how to.)
12385 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
12386 MachineMemOperand *MMO =
12387 DAG.getMachineFunction()
12388 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12389 MachineMemOperand::MOLoad, 8, 8);
12391 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
12392 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
12393 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
12396 APInt FF(32, 0x5F800000ULL);
12398 // Check whether the sign bit is set.
12399 SDValue SignSet = DAG.getSetCC(dl,
12400 getSetCCResultType(*DAG.getContext(), MVT::i64),
12401 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
12404 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
12405 SDValue FudgePtr = DAG.getConstantPool(
12406 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
12409 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
12410 SDValue Zero = DAG.getIntPtrConstant(0);
12411 SDValue Four = DAG.getIntPtrConstant(4);
12412 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
12414 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
12416 // Load the value out, extending it from f32 to f80.
12417 // FIXME: Avoid the extend by constructing the right constant pool?
12418 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
12419 FudgePtr, MachinePointerInfo::getConstantPool(),
12420 MVT::f32, false, false, false, 4);
12421 // Extend everything to 80 bits to force it to be done on x87.
12422 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
12423 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
12426 std::pair<SDValue,SDValue>
12427 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
12428 bool IsSigned, bool IsReplace) const {
12431 EVT DstTy = Op.getValueType();
12433 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
12434 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
12438 assert(DstTy.getSimpleVT() <= MVT::i64 &&
12439 DstTy.getSimpleVT() >= MVT::i16 &&
12440 "Unknown FP_TO_INT to lower!");
12442 // These are really Legal.
12443 if (DstTy == MVT::i32 &&
12444 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
12445 return std::make_pair(SDValue(), SDValue());
12446 if (Subtarget->is64Bit() &&
12447 DstTy == MVT::i64 &&
12448 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
12449 return std::make_pair(SDValue(), SDValue());
12451 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
12452 // stack slot, or into the FTOL runtime function.
12453 MachineFunction &MF = DAG.getMachineFunction();
12454 unsigned MemSize = DstTy.getSizeInBits()/8;
12455 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
12456 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
12459 if (!IsSigned && isIntegerTypeFTOL(DstTy))
12460 Opc = X86ISD::WIN_FTOL;
12462 switch (DstTy.getSimpleVT().SimpleTy) {
12463 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
12464 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
12465 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
12466 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
12469 SDValue Chain = DAG.getEntryNode();
12470 SDValue Value = Op.getOperand(0);
12471 EVT TheVT = Op.getOperand(0).getValueType();
12472 // FIXME This causes a redundant load/store if the SSE-class value is already
12473 // in memory, such as if it is on the callstack.
12474 if (isScalarFPTypeInSSEReg(TheVT)) {
12475 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
12476 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
12477 MachinePointerInfo::getFixedStack(SSFI),
12479 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
12481 Chain, StackSlot, DAG.getValueType(TheVT)
12484 MachineMemOperand *MMO =
12485 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12486 MachineMemOperand::MOLoad, MemSize, MemSize);
12487 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
12488 Chain = Value.getValue(1);
12489 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
12490 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
12493 MachineMemOperand *MMO =
12494 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12495 MachineMemOperand::MOStore, MemSize, MemSize);
12497 if (Opc != X86ISD::WIN_FTOL) {
12498 // Build the FP_TO_INT*_IN_MEM
12499 SDValue Ops[] = { Chain, Value, StackSlot };
12500 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
12502 return std::make_pair(FIST, StackSlot);
12504 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
12505 DAG.getVTList(MVT::Other, MVT::Glue),
12507 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
12508 MVT::i32, ftol.getValue(1));
12509 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
12510 MVT::i32, eax.getValue(2));
12511 SDValue Ops[] = { eax, edx };
12512 SDValue pair = IsReplace
12513 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops)
12514 : DAG.getMergeValues(Ops, DL);
12515 return std::make_pair(pair, SDValue());
12519 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
12520 const X86Subtarget *Subtarget) {
12521 MVT VT = Op->getSimpleValueType(0);
12522 SDValue In = Op->getOperand(0);
12523 MVT InVT = In.getSimpleValueType();
12526 // Optimize vectors in AVX mode:
12529 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
12530 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
12531 // Concat upper and lower parts.
12534 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
12535 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
12536 // Concat upper and lower parts.
12539 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
12540 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
12541 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
12544 if (Subtarget->hasInt256())
12545 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
12547 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
12548 SDValue Undef = DAG.getUNDEF(InVT);
12549 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
12550 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
12551 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
12553 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
12554 VT.getVectorNumElements()/2);
12556 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
12557 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
12559 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
12562 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
12563 SelectionDAG &DAG) {
12564 MVT VT = Op->getSimpleValueType(0);
12565 SDValue In = Op->getOperand(0);
12566 MVT InVT = In.getSimpleValueType();
12568 unsigned int NumElts = VT.getVectorNumElements();
12569 if (NumElts != 8 && NumElts != 16)
12572 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
12573 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
12575 EVT ExtVT = (NumElts == 8)? MVT::v8i64 : MVT::v16i32;
12576 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12577 // Now we have only mask extension
12578 assert(InVT.getVectorElementType() == MVT::i1);
12579 SDValue Cst = DAG.getTargetConstant(1, ExtVT.getScalarType());
12580 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
12581 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
12582 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
12583 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
12584 MachinePointerInfo::getConstantPool(),
12585 false, false, false, Alignment);
12587 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, DL, ExtVT, In, Ld);
12588 if (VT.is512BitVector())
12590 return DAG.getNode(X86ISD::VTRUNC, DL, VT, Brcst);
12593 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
12594 SelectionDAG &DAG) {
12595 if (Subtarget->hasFp256()) {
12596 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
12604 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
12605 SelectionDAG &DAG) {
12607 MVT VT = Op.getSimpleValueType();
12608 SDValue In = Op.getOperand(0);
12609 MVT SVT = In.getSimpleValueType();
12611 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
12612 return LowerZERO_EXTEND_AVX512(Op, DAG);
12614 if (Subtarget->hasFp256()) {
12615 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
12620 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
12621 VT.getVectorNumElements() != SVT.getVectorNumElements());
12625 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
12627 MVT VT = Op.getSimpleValueType();
12628 SDValue In = Op.getOperand(0);
12629 MVT InVT = In.getSimpleValueType();
12631 if (VT == MVT::i1) {
12632 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
12633 "Invalid scalar TRUNCATE operation");
12634 if (InVT.getSizeInBits() >= 32)
12636 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
12637 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
12639 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
12640 "Invalid TRUNCATE operation");
12642 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
12643 if (VT.getVectorElementType().getSizeInBits() >=8)
12644 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
12646 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
12647 unsigned NumElts = InVT.getVectorNumElements();
12648 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
12649 if (InVT.getSizeInBits() < 512) {
12650 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
12651 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
12655 SDValue Cst = DAG.getTargetConstant(1, InVT.getVectorElementType());
12656 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
12657 SDValue CP = DAG.getConstantPool(C, getPointerTy());
12658 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
12659 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
12660 MachinePointerInfo::getConstantPool(),
12661 false, false, false, Alignment);
12662 SDValue OneV = DAG.getNode(X86ISD::VBROADCAST, DL, InVT, Ld);
12663 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
12664 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
12667 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
12668 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
12669 if (Subtarget->hasInt256()) {
12670 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
12671 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
12672 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
12674 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
12675 DAG.getIntPtrConstant(0));
12678 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
12679 DAG.getIntPtrConstant(0));
12680 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
12681 DAG.getIntPtrConstant(2));
12682 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
12683 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
12684 static const int ShufMask[] = {0, 2, 4, 6};
12685 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
12688 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
12689 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
12690 if (Subtarget->hasInt256()) {
12691 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
12693 SmallVector<SDValue,32> pshufbMask;
12694 for (unsigned i = 0; i < 2; ++i) {
12695 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
12696 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
12697 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
12698 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
12699 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
12700 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
12701 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
12702 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
12703 for (unsigned j = 0; j < 8; ++j)
12704 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
12706 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
12707 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
12708 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
12710 static const int ShufMask[] = {0, 2, -1, -1};
12711 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
12713 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
12714 DAG.getIntPtrConstant(0));
12715 return DAG.getNode(ISD::BITCAST, DL, VT, In);
12718 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
12719 DAG.getIntPtrConstant(0));
12721 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
12722 DAG.getIntPtrConstant(4));
12724 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
12725 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
12727 // The PSHUFB mask:
12728 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
12729 -1, -1, -1, -1, -1, -1, -1, -1};
12731 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
12732 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
12733 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
12735 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
12736 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
12738 // The MOVLHPS Mask:
12739 static const int ShufMask2[] = {0, 1, 4, 5};
12740 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
12741 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
12744 // Handle truncation of V256 to V128 using shuffles.
12745 if (!VT.is128BitVector() || !InVT.is256BitVector())
12748 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
12750 unsigned NumElems = VT.getVectorNumElements();
12751 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
12753 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
12754 // Prepare truncation shuffle mask
12755 for (unsigned i = 0; i != NumElems; ++i)
12756 MaskVec[i] = i * 2;
12757 SDValue V = DAG.getVectorShuffle(NVT, DL,
12758 DAG.getNode(ISD::BITCAST, DL, NVT, In),
12759 DAG.getUNDEF(NVT), &MaskVec[0]);
12760 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
12761 DAG.getIntPtrConstant(0));
12764 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
12765 SelectionDAG &DAG) const {
12766 assert(!Op.getSimpleValueType().isVector());
12768 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
12769 /*IsSigned=*/ true, /*IsReplace=*/ false);
12770 SDValue FIST = Vals.first, StackSlot = Vals.second;
12771 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
12772 if (!FIST.getNode()) return Op;
12774 if (StackSlot.getNode())
12775 // Load the result.
12776 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
12777 FIST, StackSlot, MachinePointerInfo(),
12778 false, false, false, 0);
12780 // The node is the result.
12784 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
12785 SelectionDAG &DAG) const {
12786 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
12787 /*IsSigned=*/ false, /*IsReplace=*/ false);
12788 SDValue FIST = Vals.first, StackSlot = Vals.second;
12789 assert(FIST.getNode() && "Unexpected failure");
12791 if (StackSlot.getNode())
12792 // Load the result.
12793 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
12794 FIST, StackSlot, MachinePointerInfo(),
12795 false, false, false, 0);
12797 // The node is the result.
12801 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
12803 MVT VT = Op.getSimpleValueType();
12804 SDValue In = Op.getOperand(0);
12805 MVT SVT = In.getSimpleValueType();
12807 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
12809 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
12810 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
12811 In, DAG.getUNDEF(SVT)));
12814 // The only differences between FABS and FNEG are the mask and the logic op.
12815 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
12816 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
12817 "Wrong opcode for lowering FABS or FNEG.");
12819 bool IsFABS = (Op.getOpcode() == ISD::FABS);
12821 MVT VT = Op.getSimpleValueType();
12822 // Assume scalar op for initialization; update for vector if needed.
12823 // Note that there are no scalar bitwise logical SSE/AVX instructions, so we
12824 // generate a 16-byte vector constant and logic op even for the scalar case.
12825 // Using a 16-byte mask allows folding the load of the mask with
12826 // the logic op, so it can save (~4 bytes) on code size.
12828 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
12829 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
12830 // decide if we should generate a 16-byte constant mask when we only need 4 or
12831 // 8 bytes for the scalar case.
12832 if (VT.isVector()) {
12833 EltVT = VT.getVectorElementType();
12834 NumElts = VT.getVectorNumElements();
12837 unsigned EltBits = EltVT.getSizeInBits();
12838 LLVMContext *Context = DAG.getContext();
12839 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
12841 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
12842 Constant *C = ConstantInt::get(*Context, MaskElt);
12843 C = ConstantVector::getSplat(NumElts, C);
12844 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12845 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
12846 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
12847 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
12848 MachinePointerInfo::getConstantPool(),
12849 false, false, false, Alignment);
12851 if (VT.isVector()) {
12852 // For a vector, cast operands to a vector type, perform the logic op,
12853 // and cast the result back to the original value type.
12854 MVT VecVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
12855 SDValue Op0Casted = DAG.getNode(ISD::BITCAST, dl, VecVT, Op.getOperand(0));
12856 SDValue MaskCasted = DAG.getNode(ISD::BITCAST, dl, VecVT, Mask);
12857 unsigned LogicOp = IsFABS ? ISD::AND : ISD::XOR;
12858 return DAG.getNode(ISD::BITCAST, dl, VT,
12859 DAG.getNode(LogicOp, dl, VecVT, Op0Casted, MaskCasted));
12861 // If not vector, then scalar.
12862 unsigned LogicOp = IsFABS ? X86ISD::FAND : X86ISD::FXOR;
12863 return DAG.getNode(LogicOp, dl, VT, Op.getOperand(0), Mask);
12866 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
12867 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12868 LLVMContext *Context = DAG.getContext();
12869 SDValue Op0 = Op.getOperand(0);
12870 SDValue Op1 = Op.getOperand(1);
12872 MVT VT = Op.getSimpleValueType();
12873 MVT SrcVT = Op1.getSimpleValueType();
12875 // If second operand is smaller, extend it first.
12876 if (SrcVT.bitsLT(VT)) {
12877 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
12880 // And if it is bigger, shrink it first.
12881 if (SrcVT.bitsGT(VT)) {
12882 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
12886 // At this point the operands and the result should have the same
12887 // type, and that won't be f80 since that is not custom lowered.
12889 // First get the sign bit of second operand.
12890 SmallVector<Constant*,4> CV;
12891 if (SrcVT == MVT::f64) {
12892 const fltSemantics &Sem = APFloat::IEEEdouble;
12893 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 1ULL << 63))));
12894 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
12896 const fltSemantics &Sem = APFloat::IEEEsingle;
12897 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 1U << 31))));
12898 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
12899 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
12900 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
12902 Constant *C = ConstantVector::get(CV);
12903 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
12904 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
12905 MachinePointerInfo::getConstantPool(),
12906 false, false, false, 16);
12907 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
12909 // Shift sign bit right or left if the two operands have different types.
12910 if (SrcVT.bitsGT(VT)) {
12911 // Op0 is MVT::f32, Op1 is MVT::f64.
12912 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
12913 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
12914 DAG.getConstant(32, MVT::i32));
12915 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
12916 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
12917 DAG.getIntPtrConstant(0));
12920 // Clear first operand sign bit.
12922 if (VT == MVT::f64) {
12923 const fltSemantics &Sem = APFloat::IEEEdouble;
12924 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
12925 APInt(64, ~(1ULL << 63)))));
12926 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
12928 const fltSemantics &Sem = APFloat::IEEEsingle;
12929 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
12930 APInt(32, ~(1U << 31)))));
12931 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
12932 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
12933 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
12935 C = ConstantVector::get(CV);
12936 CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
12937 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
12938 MachinePointerInfo::getConstantPool(),
12939 false, false, false, 16);
12940 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
12942 // Or the value with the sign bit.
12943 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
12946 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
12947 SDValue N0 = Op.getOperand(0);
12949 MVT VT = Op.getSimpleValueType();
12951 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
12952 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
12953 DAG.getConstant(1, VT));
12954 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
12957 // LowerVectorAllZeroTest - Check whether an OR'd tree is PTEST-able.
12959 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
12960 SelectionDAG &DAG) {
12961 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
12963 if (!Subtarget->hasSSE41())
12966 if (!Op->hasOneUse())
12969 SDNode *N = Op.getNode();
12972 SmallVector<SDValue, 8> Opnds;
12973 DenseMap<SDValue, unsigned> VecInMap;
12974 SmallVector<SDValue, 8> VecIns;
12975 EVT VT = MVT::Other;
12977 // Recognize a special case where a vector is casted into wide integer to
12979 Opnds.push_back(N->getOperand(0));
12980 Opnds.push_back(N->getOperand(1));
12982 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
12983 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
12984 // BFS traverse all OR'd operands.
12985 if (I->getOpcode() == ISD::OR) {
12986 Opnds.push_back(I->getOperand(0));
12987 Opnds.push_back(I->getOperand(1));
12988 // Re-evaluate the number of nodes to be traversed.
12989 e += 2; // 2 more nodes (LHS and RHS) are pushed.
12993 // Quit if a non-EXTRACT_VECTOR_ELT
12994 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
12997 // Quit if without a constant index.
12998 SDValue Idx = I->getOperand(1);
12999 if (!isa<ConstantSDNode>(Idx))
13002 SDValue ExtractedFromVec = I->getOperand(0);
13003 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
13004 if (M == VecInMap.end()) {
13005 VT = ExtractedFromVec.getValueType();
13006 // Quit if not 128/256-bit vector.
13007 if (!VT.is128BitVector() && !VT.is256BitVector())
13009 // Quit if not the same type.
13010 if (VecInMap.begin() != VecInMap.end() &&
13011 VT != VecInMap.begin()->first.getValueType())
13013 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
13014 VecIns.push_back(ExtractedFromVec);
13016 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
13019 assert((VT.is128BitVector() || VT.is256BitVector()) &&
13020 "Not extracted from 128-/256-bit vector.");
13022 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
13024 for (DenseMap<SDValue, unsigned>::const_iterator
13025 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
13026 // Quit if not all elements are used.
13027 if (I->second != FullMask)
13031 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
13033 // Cast all vectors into TestVT for PTEST.
13034 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
13035 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
13037 // If more than one full vectors are evaluated, OR them first before PTEST.
13038 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
13039 // Each iteration will OR 2 nodes and append the result until there is only
13040 // 1 node left, i.e. the final OR'd value of all vectors.
13041 SDValue LHS = VecIns[Slot];
13042 SDValue RHS = VecIns[Slot + 1];
13043 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
13046 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
13047 VecIns.back(), VecIns.back());
13050 /// \brief return true if \c Op has a use that doesn't just read flags.
13051 static bool hasNonFlagsUse(SDValue Op) {
13052 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
13054 SDNode *User = *UI;
13055 unsigned UOpNo = UI.getOperandNo();
13056 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
13057 // Look pass truncate.
13058 UOpNo = User->use_begin().getOperandNo();
13059 User = *User->use_begin();
13062 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
13063 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
13069 /// Emit nodes that will be selected as "test Op0,Op0", or something
13071 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
13072 SelectionDAG &DAG) const {
13073 if (Op.getValueType() == MVT::i1)
13074 // KORTEST instruction should be selected
13075 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13076 DAG.getConstant(0, Op.getValueType()));
13078 // CF and OF aren't always set the way we want. Determine which
13079 // of these we need.
13080 bool NeedCF = false;
13081 bool NeedOF = false;
13084 case X86::COND_A: case X86::COND_AE:
13085 case X86::COND_B: case X86::COND_BE:
13088 case X86::COND_G: case X86::COND_GE:
13089 case X86::COND_L: case X86::COND_LE:
13090 case X86::COND_O: case X86::COND_NO: {
13091 // Check if we really need to set the
13092 // Overflow flag. If NoSignedWrap is present
13093 // that is not actually needed.
13094 switch (Op->getOpcode()) {
13099 const BinaryWithFlagsSDNode *BinNode =
13100 cast<BinaryWithFlagsSDNode>(Op.getNode());
13101 if (BinNode->hasNoSignedWrap())
13111 // See if we can use the EFLAGS value from the operand instead of
13112 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
13113 // we prove that the arithmetic won't overflow, we can't use OF or CF.
13114 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
13115 // Emit a CMP with 0, which is the TEST pattern.
13116 //if (Op.getValueType() == MVT::i1)
13117 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
13118 // DAG.getConstant(0, MVT::i1));
13119 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13120 DAG.getConstant(0, Op.getValueType()));
13122 unsigned Opcode = 0;
13123 unsigned NumOperands = 0;
13125 // Truncate operations may prevent the merge of the SETCC instruction
13126 // and the arithmetic instruction before it. Attempt to truncate the operands
13127 // of the arithmetic instruction and use a reduced bit-width instruction.
13128 bool NeedTruncation = false;
13129 SDValue ArithOp = Op;
13130 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
13131 SDValue Arith = Op->getOperand(0);
13132 // Both the trunc and the arithmetic op need to have one user each.
13133 if (Arith->hasOneUse())
13134 switch (Arith.getOpcode()) {
13141 NeedTruncation = true;
13147 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
13148 // which may be the result of a CAST. We use the variable 'Op', which is the
13149 // non-casted variable when we check for possible users.
13150 switch (ArithOp.getOpcode()) {
13152 // Due to an isel shortcoming, be conservative if this add is likely to be
13153 // selected as part of a load-modify-store instruction. When the root node
13154 // in a match is a store, isel doesn't know how to remap non-chain non-flag
13155 // uses of other nodes in the match, such as the ADD in this case. This
13156 // leads to the ADD being left around and reselected, with the result being
13157 // two adds in the output. Alas, even if none our users are stores, that
13158 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
13159 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
13160 // climbing the DAG back to the root, and it doesn't seem to be worth the
13162 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13163 UE = Op.getNode()->use_end(); UI != UE; ++UI)
13164 if (UI->getOpcode() != ISD::CopyToReg &&
13165 UI->getOpcode() != ISD::SETCC &&
13166 UI->getOpcode() != ISD::STORE)
13169 if (ConstantSDNode *C =
13170 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
13171 // An add of one will be selected as an INC.
13172 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
13173 Opcode = X86ISD::INC;
13178 // An add of negative one (subtract of one) will be selected as a DEC.
13179 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
13180 Opcode = X86ISD::DEC;
13186 // Otherwise use a regular EFLAGS-setting add.
13187 Opcode = X86ISD::ADD;
13192 // If we have a constant logical shift that's only used in a comparison
13193 // against zero turn it into an equivalent AND. This allows turning it into
13194 // a TEST instruction later.
13195 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
13196 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
13197 EVT VT = Op.getValueType();
13198 unsigned BitWidth = VT.getSizeInBits();
13199 unsigned ShAmt = Op->getConstantOperandVal(1);
13200 if (ShAmt >= BitWidth) // Avoid undefined shifts.
13202 APInt Mask = ArithOp.getOpcode() == ISD::SRL
13203 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
13204 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
13205 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
13207 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
13208 DAG.getConstant(Mask, VT));
13209 DAG.ReplaceAllUsesWith(Op, New);
13215 // If the primary and result isn't used, don't bother using X86ISD::AND,
13216 // because a TEST instruction will be better.
13217 if (!hasNonFlagsUse(Op))
13223 // Due to the ISEL shortcoming noted above, be conservative if this op is
13224 // likely to be selected as part of a load-modify-store instruction.
13225 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13226 UE = Op.getNode()->use_end(); UI != UE; ++UI)
13227 if (UI->getOpcode() == ISD::STORE)
13230 // Otherwise use a regular EFLAGS-setting instruction.
13231 switch (ArithOp.getOpcode()) {
13232 default: llvm_unreachable("unexpected operator!");
13233 case ISD::SUB: Opcode = X86ISD::SUB; break;
13234 case ISD::XOR: Opcode = X86ISD::XOR; break;
13235 case ISD::AND: Opcode = X86ISD::AND; break;
13237 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
13238 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
13239 if (EFLAGS.getNode())
13242 Opcode = X86ISD::OR;
13256 return SDValue(Op.getNode(), 1);
13262 // If we found that truncation is beneficial, perform the truncation and
13264 if (NeedTruncation) {
13265 EVT VT = Op.getValueType();
13266 SDValue WideVal = Op->getOperand(0);
13267 EVT WideVT = WideVal.getValueType();
13268 unsigned ConvertedOp = 0;
13269 // Use a target machine opcode to prevent further DAGCombine
13270 // optimizations that may separate the arithmetic operations
13271 // from the setcc node.
13272 switch (WideVal.getOpcode()) {
13274 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
13275 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
13276 case ISD::AND: ConvertedOp = X86ISD::AND; break;
13277 case ISD::OR: ConvertedOp = X86ISD::OR; break;
13278 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
13282 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13283 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
13284 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
13285 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
13286 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
13292 // Emit a CMP with 0, which is the TEST pattern.
13293 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13294 DAG.getConstant(0, Op.getValueType()));
13296 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
13297 SmallVector<SDValue, 4> Ops;
13298 for (unsigned i = 0; i != NumOperands; ++i)
13299 Ops.push_back(Op.getOperand(i));
13301 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
13302 DAG.ReplaceAllUsesWith(Op, New);
13303 return SDValue(New.getNode(), 1);
13306 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
13308 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
13309 SDLoc dl, SelectionDAG &DAG) const {
13310 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
13311 if (C->getAPIntValue() == 0)
13312 return EmitTest(Op0, X86CC, dl, DAG);
13314 if (Op0.getValueType() == MVT::i1)
13315 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
13318 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
13319 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
13320 // Do the comparison at i32 if it's smaller, besides the Atom case.
13321 // This avoids subregister aliasing issues. Keep the smaller reference
13322 // if we're optimizing for size, however, as that'll allow better folding
13323 // of memory operations.
13324 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
13325 !DAG.getMachineFunction().getFunction()->getAttributes().hasAttribute(
13326 AttributeSet::FunctionIndex, Attribute::MinSize) &&
13327 !Subtarget->isAtom()) {
13328 unsigned ExtendOp =
13329 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
13330 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
13331 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
13333 // Use SUB instead of CMP to enable CSE between SUB and CMP.
13334 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
13335 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
13337 return SDValue(Sub.getNode(), 1);
13339 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
13342 /// Convert a comparison if required by the subtarget.
13343 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
13344 SelectionDAG &DAG) const {
13345 // If the subtarget does not support the FUCOMI instruction, floating-point
13346 // comparisons have to be converted.
13347 if (Subtarget->hasCMov() ||
13348 Cmp.getOpcode() != X86ISD::CMP ||
13349 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
13350 !Cmp.getOperand(1).getValueType().isFloatingPoint())
13353 // The instruction selector will select an FUCOM instruction instead of
13354 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
13355 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
13356 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
13358 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
13359 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
13360 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
13361 DAG.getConstant(8, MVT::i8));
13362 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
13363 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
13366 static bool isAllOnes(SDValue V) {
13367 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
13368 return C && C->isAllOnesValue();
13371 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
13372 /// if it's possible.
13373 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
13374 SDLoc dl, SelectionDAG &DAG) const {
13375 SDValue Op0 = And.getOperand(0);
13376 SDValue Op1 = And.getOperand(1);
13377 if (Op0.getOpcode() == ISD::TRUNCATE)
13378 Op0 = Op0.getOperand(0);
13379 if (Op1.getOpcode() == ISD::TRUNCATE)
13380 Op1 = Op1.getOperand(0);
13383 if (Op1.getOpcode() == ISD::SHL)
13384 std::swap(Op0, Op1);
13385 if (Op0.getOpcode() == ISD::SHL) {
13386 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
13387 if (And00C->getZExtValue() == 1) {
13388 // If we looked past a truncate, check that it's only truncating away
13390 unsigned BitWidth = Op0.getValueSizeInBits();
13391 unsigned AndBitWidth = And.getValueSizeInBits();
13392 if (BitWidth > AndBitWidth) {
13394 DAG.computeKnownBits(Op0, Zeros, Ones);
13395 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
13399 RHS = Op0.getOperand(1);
13401 } else if (Op1.getOpcode() == ISD::Constant) {
13402 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
13403 uint64_t AndRHSVal = AndRHS->getZExtValue();
13404 SDValue AndLHS = Op0;
13406 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
13407 LHS = AndLHS.getOperand(0);
13408 RHS = AndLHS.getOperand(1);
13411 // Use BT if the immediate can't be encoded in a TEST instruction.
13412 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
13414 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
13418 if (LHS.getNode()) {
13419 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
13420 // instruction. Since the shift amount is in-range-or-undefined, we know
13421 // that doing a bittest on the i32 value is ok. We extend to i32 because
13422 // the encoding for the i16 version is larger than the i32 version.
13423 // Also promote i16 to i32 for performance / code size reason.
13424 if (LHS.getValueType() == MVT::i8 ||
13425 LHS.getValueType() == MVT::i16)
13426 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
13428 // If the operand types disagree, extend the shift amount to match. Since
13429 // BT ignores high bits (like shifts) we can use anyextend.
13430 if (LHS.getValueType() != RHS.getValueType())
13431 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
13433 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
13434 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
13435 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13436 DAG.getConstant(Cond, MVT::i8), BT);
13442 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
13444 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
13449 // SSE Condition code mapping:
13458 switch (SetCCOpcode) {
13459 default: llvm_unreachable("Unexpected SETCC condition");
13461 case ISD::SETEQ: SSECC = 0; break;
13463 case ISD::SETGT: Swap = true; // Fallthrough
13465 case ISD::SETOLT: SSECC = 1; break;
13467 case ISD::SETGE: Swap = true; // Fallthrough
13469 case ISD::SETOLE: SSECC = 2; break;
13470 case ISD::SETUO: SSECC = 3; break;
13472 case ISD::SETNE: SSECC = 4; break;
13473 case ISD::SETULE: Swap = true; // Fallthrough
13474 case ISD::SETUGE: SSECC = 5; break;
13475 case ISD::SETULT: Swap = true; // Fallthrough
13476 case ISD::SETUGT: SSECC = 6; break;
13477 case ISD::SETO: SSECC = 7; break;
13479 case ISD::SETONE: SSECC = 8; break;
13482 std::swap(Op0, Op1);
13487 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
13488 // ones, and then concatenate the result back.
13489 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
13490 MVT VT = Op.getSimpleValueType();
13492 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
13493 "Unsupported value type for operation");
13495 unsigned NumElems = VT.getVectorNumElements();
13497 SDValue CC = Op.getOperand(2);
13499 // Extract the LHS vectors
13500 SDValue LHS = Op.getOperand(0);
13501 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
13502 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
13504 // Extract the RHS vectors
13505 SDValue RHS = Op.getOperand(1);
13506 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
13507 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
13509 // Issue the operation on the smaller types and concatenate the result back
13510 MVT EltVT = VT.getVectorElementType();
13511 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
13512 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
13513 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
13514 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
13517 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
13518 const X86Subtarget *Subtarget) {
13519 SDValue Op0 = Op.getOperand(0);
13520 SDValue Op1 = Op.getOperand(1);
13521 SDValue CC = Op.getOperand(2);
13522 MVT VT = Op.getSimpleValueType();
13525 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 8 &&
13526 Op.getValueType().getScalarType() == MVT::i1 &&
13527 "Cannot set masked compare for this operation");
13529 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
13531 bool Unsigned = false;
13534 switch (SetCCOpcode) {
13535 default: llvm_unreachable("Unexpected SETCC condition");
13536 case ISD::SETNE: SSECC = 4; break;
13537 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
13538 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
13539 case ISD::SETLT: Swap = true; //fall-through
13540 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
13541 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
13542 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
13543 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
13544 case ISD::SETULE: Unsigned = true; //fall-through
13545 case ISD::SETLE: SSECC = 2; break;
13549 std::swap(Op0, Op1);
13551 return DAG.getNode(Opc, dl, VT, Op0, Op1);
13552 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
13553 return DAG.getNode(Opc, dl, VT, Op0, Op1,
13554 DAG.getConstant(SSECC, MVT::i8));
13557 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
13558 /// operand \p Op1. If non-trivial (for example because it's not constant)
13559 /// return an empty value.
13560 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
13562 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
13566 MVT VT = Op1.getSimpleValueType();
13567 MVT EVT = VT.getVectorElementType();
13568 unsigned n = VT.getVectorNumElements();
13569 SmallVector<SDValue, 8> ULTOp1;
13571 for (unsigned i = 0; i < n; ++i) {
13572 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
13573 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
13576 // Avoid underflow.
13577 APInt Val = Elt->getAPIntValue();
13581 ULTOp1.push_back(DAG.getConstant(Val - 1, EVT));
13584 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
13587 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
13588 SelectionDAG &DAG) {
13589 SDValue Op0 = Op.getOperand(0);
13590 SDValue Op1 = Op.getOperand(1);
13591 SDValue CC = Op.getOperand(2);
13592 MVT VT = Op.getSimpleValueType();
13593 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
13594 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
13599 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
13600 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
13603 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
13604 unsigned Opc = X86ISD::CMPP;
13605 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
13606 assert(VT.getVectorNumElements() <= 16);
13607 Opc = X86ISD::CMPM;
13609 // In the two special cases we can't handle, emit two comparisons.
13612 unsigned CombineOpc;
13613 if (SetCCOpcode == ISD::SETUEQ) {
13614 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
13616 assert(SetCCOpcode == ISD::SETONE);
13617 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
13620 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
13621 DAG.getConstant(CC0, MVT::i8));
13622 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
13623 DAG.getConstant(CC1, MVT::i8));
13624 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
13626 // Handle all other FP comparisons here.
13627 return DAG.getNode(Opc, dl, VT, Op0, Op1,
13628 DAG.getConstant(SSECC, MVT::i8));
13631 // Break 256-bit integer vector compare into smaller ones.
13632 if (VT.is256BitVector() && !Subtarget->hasInt256())
13633 return Lower256IntVSETCC(Op, DAG);
13635 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
13636 EVT OpVT = Op1.getValueType();
13637 if (Subtarget->hasAVX512()) {
13638 if (Op1.getValueType().is512BitVector() ||
13639 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
13640 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
13641 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
13643 // In AVX-512 architecture setcc returns mask with i1 elements,
13644 // But there is no compare instruction for i8 and i16 elements in KNL.
13645 // We are not talking about 512-bit operands in this case, these
13646 // types are illegal.
13648 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
13649 OpVT.getVectorElementType().getSizeInBits() >= 8))
13650 return DAG.getNode(ISD::TRUNCATE, dl, VT,
13651 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
13654 // We are handling one of the integer comparisons here. Since SSE only has
13655 // GT and EQ comparisons for integer, swapping operands and multiple
13656 // operations may be required for some comparisons.
13658 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
13659 bool Subus = false;
13661 switch (SetCCOpcode) {
13662 default: llvm_unreachable("Unexpected SETCC condition");
13663 case ISD::SETNE: Invert = true;
13664 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
13665 case ISD::SETLT: Swap = true;
13666 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
13667 case ISD::SETGE: Swap = true;
13668 case ISD::SETLE: Opc = X86ISD::PCMPGT;
13669 Invert = true; break;
13670 case ISD::SETULT: Swap = true;
13671 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
13672 FlipSigns = true; break;
13673 case ISD::SETUGE: Swap = true;
13674 case ISD::SETULE: Opc = X86ISD::PCMPGT;
13675 FlipSigns = true; Invert = true; break;
13678 // Special case: Use min/max operations for SETULE/SETUGE
13679 MVT VET = VT.getVectorElementType();
13681 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
13682 || (Subtarget->hasSSE2() && (VET == MVT::i8));
13685 switch (SetCCOpcode) {
13687 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
13688 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
13691 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
13694 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
13695 if (!MinMax && hasSubus) {
13696 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
13698 // t = psubus Op0, Op1
13699 // pcmpeq t, <0..0>
13700 switch (SetCCOpcode) {
13702 case ISD::SETULT: {
13703 // If the comparison is against a constant we can turn this into a
13704 // setule. With psubus, setule does not require a swap. This is
13705 // beneficial because the constant in the register is no longer
13706 // destructed as the destination so it can be hoisted out of a loop.
13707 // Only do this pre-AVX since vpcmp* is no longer destructive.
13708 if (Subtarget->hasAVX())
13710 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
13711 if (ULEOp1.getNode()) {
13713 Subus = true; Invert = false; Swap = false;
13717 // Psubus is better than flip-sign because it requires no inversion.
13718 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
13719 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
13723 Opc = X86ISD::SUBUS;
13729 std::swap(Op0, Op1);
13731 // Check that the operation in question is available (most are plain SSE2,
13732 // but PCMPGTQ and PCMPEQQ have different requirements).
13733 if (VT == MVT::v2i64) {
13734 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
13735 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
13737 // First cast everything to the right type.
13738 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
13739 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
13741 // Since SSE has no unsigned integer comparisons, we need to flip the sign
13742 // bits of the inputs before performing those operations. The lower
13743 // compare is always unsigned.
13746 SB = DAG.getConstant(0x80000000U, MVT::v4i32);
13748 SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
13749 SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
13750 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
13751 Sign, Zero, Sign, Zero);
13753 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
13754 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
13756 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
13757 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
13758 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
13760 // Create masks for only the low parts/high parts of the 64 bit integers.
13761 static const int MaskHi[] = { 1, 1, 3, 3 };
13762 static const int MaskLo[] = { 0, 0, 2, 2 };
13763 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
13764 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
13765 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
13767 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
13768 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
13771 Result = DAG.getNOT(dl, Result, MVT::v4i32);
13773 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
13776 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
13777 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
13778 // pcmpeqd + pshufd + pand.
13779 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
13781 // First cast everything to the right type.
13782 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
13783 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
13786 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
13788 // Make sure the lower and upper halves are both all-ones.
13789 static const int Mask[] = { 1, 0, 3, 2 };
13790 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
13791 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
13794 Result = DAG.getNOT(dl, Result, MVT::v4i32);
13796 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
13800 // Since SSE has no unsigned integer comparisons, we need to flip the sign
13801 // bits of the inputs before performing those operations.
13803 EVT EltVT = VT.getVectorElementType();
13804 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
13805 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
13806 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
13809 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
13811 // If the logical-not of the result is required, perform that now.
13813 Result = DAG.getNOT(dl, Result, VT);
13816 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
13819 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
13820 getZeroVector(VT, Subtarget, DAG, dl));
13825 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
13827 MVT VT = Op.getSimpleValueType();
13829 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
13831 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
13832 && "SetCC type must be 8-bit or 1-bit integer");
13833 SDValue Op0 = Op.getOperand(0);
13834 SDValue Op1 = Op.getOperand(1);
13836 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
13838 // Optimize to BT if possible.
13839 // Lower (X & (1 << N)) == 0 to BT(X, N).
13840 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
13841 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
13842 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
13843 Op1.getOpcode() == ISD::Constant &&
13844 cast<ConstantSDNode>(Op1)->isNullValue() &&
13845 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
13846 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
13847 if (NewSetCC.getNode())
13851 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
13853 if (Op1.getOpcode() == ISD::Constant &&
13854 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
13855 cast<ConstantSDNode>(Op1)->isNullValue()) &&
13856 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
13858 // If the input is a setcc, then reuse the input setcc or use a new one with
13859 // the inverted condition.
13860 if (Op0.getOpcode() == X86ISD::SETCC) {
13861 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
13862 bool Invert = (CC == ISD::SETNE) ^
13863 cast<ConstantSDNode>(Op1)->isNullValue();
13867 CCode = X86::GetOppositeBranchCondition(CCode);
13868 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13869 DAG.getConstant(CCode, MVT::i8),
13870 Op0.getOperand(1));
13872 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
13876 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
13877 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
13878 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
13880 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
13881 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, MVT::i1), NewCC);
13884 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
13885 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
13886 if (X86CC == X86::COND_INVALID)
13889 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
13890 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
13891 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13892 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
13894 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
13898 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
13899 static bool isX86LogicalCmp(SDValue Op) {
13900 unsigned Opc = Op.getNode()->getOpcode();
13901 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
13902 Opc == X86ISD::SAHF)
13904 if (Op.getResNo() == 1 &&
13905 (Opc == X86ISD::ADD ||
13906 Opc == X86ISD::SUB ||
13907 Opc == X86ISD::ADC ||
13908 Opc == X86ISD::SBB ||
13909 Opc == X86ISD::SMUL ||
13910 Opc == X86ISD::UMUL ||
13911 Opc == X86ISD::INC ||
13912 Opc == X86ISD::DEC ||
13913 Opc == X86ISD::OR ||
13914 Opc == X86ISD::XOR ||
13915 Opc == X86ISD::AND))
13918 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
13924 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
13925 if (V.getOpcode() != ISD::TRUNCATE)
13928 SDValue VOp0 = V.getOperand(0);
13929 unsigned InBits = VOp0.getValueSizeInBits();
13930 unsigned Bits = V.getValueSizeInBits();
13931 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
13934 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
13935 bool addTest = true;
13936 SDValue Cond = Op.getOperand(0);
13937 SDValue Op1 = Op.getOperand(1);
13938 SDValue Op2 = Op.getOperand(2);
13940 EVT VT = Op1.getValueType();
13943 // Lower fp selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
13944 // are available. Otherwise fp cmovs get lowered into a less efficient branch
13945 // sequence later on.
13946 if (Cond.getOpcode() == ISD::SETCC &&
13947 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
13948 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
13949 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
13950 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
13951 int SSECC = translateX86FSETCC(
13952 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
13955 if (Subtarget->hasAVX512()) {
13956 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
13957 DAG.getConstant(SSECC, MVT::i8));
13958 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
13960 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
13961 DAG.getConstant(SSECC, MVT::i8));
13962 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
13963 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
13964 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
13968 if (Cond.getOpcode() == ISD::SETCC) {
13969 SDValue NewCond = LowerSETCC(Cond, DAG);
13970 if (NewCond.getNode())
13974 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
13975 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
13976 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
13977 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
13978 if (Cond.getOpcode() == X86ISD::SETCC &&
13979 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
13980 isZero(Cond.getOperand(1).getOperand(1))) {
13981 SDValue Cmp = Cond.getOperand(1);
13983 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
13985 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
13986 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
13987 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
13989 SDValue CmpOp0 = Cmp.getOperand(0);
13990 // Apply further optimizations for special cases
13991 // (select (x != 0), -1, 0) -> neg & sbb
13992 // (select (x == 0), 0, -1) -> neg & sbb
13993 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
13994 if (YC->isNullValue() &&
13995 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
13996 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
13997 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
13998 DAG.getConstant(0, CmpOp0.getValueType()),
14000 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14001 DAG.getConstant(X86::COND_B, MVT::i8),
14002 SDValue(Neg.getNode(), 1));
14006 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
14007 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
14008 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14010 SDValue Res = // Res = 0 or -1.
14011 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14012 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
14014 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
14015 Res = DAG.getNOT(DL, Res, Res.getValueType());
14017 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
14018 if (!N2C || !N2C->isNullValue())
14019 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
14024 // Look past (and (setcc_carry (cmp ...)), 1).
14025 if (Cond.getOpcode() == ISD::AND &&
14026 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
14027 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
14028 if (C && C->getAPIntValue() == 1)
14029 Cond = Cond.getOperand(0);
14032 // If condition flag is set by a X86ISD::CMP, then use it as the condition
14033 // setting operand in place of the X86ISD::SETCC.
14034 unsigned CondOpcode = Cond.getOpcode();
14035 if (CondOpcode == X86ISD::SETCC ||
14036 CondOpcode == X86ISD::SETCC_CARRY) {
14037 CC = Cond.getOperand(0);
14039 SDValue Cmp = Cond.getOperand(1);
14040 unsigned Opc = Cmp.getOpcode();
14041 MVT VT = Op.getSimpleValueType();
14043 bool IllegalFPCMov = false;
14044 if (VT.isFloatingPoint() && !VT.isVector() &&
14045 !isScalarFPTypeInSSEReg(VT)) // FPStack?
14046 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
14048 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
14049 Opc == X86ISD::BT) { // FIXME
14053 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
14054 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
14055 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
14056 Cond.getOperand(0).getValueType() != MVT::i8)) {
14057 SDValue LHS = Cond.getOperand(0);
14058 SDValue RHS = Cond.getOperand(1);
14059 unsigned X86Opcode;
14062 switch (CondOpcode) {
14063 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
14064 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
14065 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
14066 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
14067 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
14068 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
14069 default: llvm_unreachable("unexpected overflowing operator");
14071 if (CondOpcode == ISD::UMULO)
14072 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
14075 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
14077 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
14079 if (CondOpcode == ISD::UMULO)
14080 Cond = X86Op.getValue(2);
14082 Cond = X86Op.getValue(1);
14084 CC = DAG.getConstant(X86Cond, MVT::i8);
14089 // Look pass the truncate if the high bits are known zero.
14090 if (isTruncWithZeroHighBitsInput(Cond, DAG))
14091 Cond = Cond.getOperand(0);
14093 // We know the result of AND is compared against zero. Try to match
14095 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
14096 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
14097 if (NewSetCC.getNode()) {
14098 CC = NewSetCC.getOperand(0);
14099 Cond = NewSetCC.getOperand(1);
14106 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
14107 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
14110 // a < b ? -1 : 0 -> RES = ~setcc_carry
14111 // a < b ? 0 : -1 -> RES = setcc_carry
14112 // a >= b ? -1 : 0 -> RES = setcc_carry
14113 // a >= b ? 0 : -1 -> RES = ~setcc_carry
14114 if (Cond.getOpcode() == X86ISD::SUB) {
14115 Cond = ConvertCmpIfNecessary(Cond, DAG);
14116 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
14118 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
14119 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
14120 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14121 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
14122 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
14123 return DAG.getNOT(DL, Res, Res.getValueType());
14128 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
14129 // widen the cmov and push the truncate through. This avoids introducing a new
14130 // branch during isel and doesn't add any extensions.
14131 if (Op.getValueType() == MVT::i8 &&
14132 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
14133 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
14134 if (T1.getValueType() == T2.getValueType() &&
14135 // Blacklist CopyFromReg to avoid partial register stalls.
14136 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
14137 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
14138 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
14139 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
14143 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
14144 // condition is true.
14145 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
14146 SDValue Ops[] = { Op2, Op1, CC, Cond };
14147 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
14150 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, SelectionDAG &DAG) {
14151 MVT VT = Op->getSimpleValueType(0);
14152 SDValue In = Op->getOperand(0);
14153 MVT InVT = In.getSimpleValueType();
14156 unsigned int NumElts = VT.getVectorNumElements();
14157 if (NumElts != 8 && NumElts != 16)
14160 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
14161 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14163 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14164 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
14166 MVT ExtVT = (NumElts == 8) ? MVT::v8i64 : MVT::v16i32;
14167 Constant *C = ConstantInt::get(*DAG.getContext(),
14168 APInt::getAllOnesValue(ExtVT.getScalarType().getSizeInBits()));
14170 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
14171 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
14172 SDValue Ld = DAG.getLoad(ExtVT.getScalarType(), dl, DAG.getEntryNode(), CP,
14173 MachinePointerInfo::getConstantPool(),
14174 false, false, false, Alignment);
14175 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, dl, ExtVT, In, Ld);
14176 if (VT.is512BitVector())
14178 return DAG.getNode(X86ISD::VTRUNC, dl, VT, Brcst);
14181 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
14182 SelectionDAG &DAG) {
14183 MVT VT = Op->getSimpleValueType(0);
14184 SDValue In = Op->getOperand(0);
14185 MVT InVT = In.getSimpleValueType();
14188 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
14189 return LowerSIGN_EXTEND_AVX512(Op, DAG);
14191 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
14192 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
14193 (VT != MVT::v16i16 || InVT != MVT::v16i8))
14196 if (Subtarget->hasInt256())
14197 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14199 // Optimize vectors in AVX mode
14200 // Sign extend v8i16 to v8i32 and
14203 // Divide input vector into two parts
14204 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
14205 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
14206 // concat the vectors to original VT
14208 unsigned NumElems = InVT.getVectorNumElements();
14209 SDValue Undef = DAG.getUNDEF(InVT);
14211 SmallVector<int,8> ShufMask1(NumElems, -1);
14212 for (unsigned i = 0; i != NumElems/2; ++i)
14215 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
14217 SmallVector<int,8> ShufMask2(NumElems, -1);
14218 for (unsigned i = 0; i != NumElems/2; ++i)
14219 ShufMask2[i] = i + NumElems/2;
14221 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
14223 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
14224 VT.getVectorNumElements()/2);
14226 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
14227 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
14229 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
14232 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
14233 // may emit an illegal shuffle but the expansion is still better than scalar
14234 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
14235 // we'll emit a shuffle and a arithmetic shift.
14236 // TODO: It is possible to support ZExt by zeroing the undef values during
14237 // the shuffle phase or after the shuffle.
14238 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
14239 SelectionDAG &DAG) {
14240 MVT RegVT = Op.getSimpleValueType();
14241 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
14242 assert(RegVT.isInteger() &&
14243 "We only custom lower integer vector sext loads.");
14245 // Nothing useful we can do without SSE2 shuffles.
14246 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
14248 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
14250 EVT MemVT = Ld->getMemoryVT();
14251 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14252 unsigned RegSz = RegVT.getSizeInBits();
14254 ISD::LoadExtType Ext = Ld->getExtensionType();
14256 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
14257 && "Only anyext and sext are currently implemented.");
14258 assert(MemVT != RegVT && "Cannot extend to the same type");
14259 assert(MemVT.isVector() && "Must load a vector from memory");
14261 unsigned NumElems = RegVT.getVectorNumElements();
14262 unsigned MemSz = MemVT.getSizeInBits();
14263 assert(RegSz > MemSz && "Register size must be greater than the mem size");
14265 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
14266 // The only way in which we have a legal 256-bit vector result but not the
14267 // integer 256-bit operations needed to directly lower a sextload is if we
14268 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
14269 // a 128-bit vector and a normal sign_extend to 256-bits that should get
14270 // correctly legalized. We do this late to allow the canonical form of
14271 // sextload to persist throughout the rest of the DAG combiner -- it wants
14272 // to fold together any extensions it can, and so will fuse a sign_extend
14273 // of an sextload into a sextload targeting a wider value.
14275 if (MemSz == 128) {
14276 // Just switch this to a normal load.
14277 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
14278 "it must be a legal 128-bit vector "
14280 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
14281 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
14282 Ld->isInvariant(), Ld->getAlignment());
14284 assert(MemSz < 128 &&
14285 "Can't extend a type wider than 128 bits to a 256 bit vector!");
14286 // Do an sext load to a 128-bit vector type. We want to use the same
14287 // number of elements, but elements half as wide. This will end up being
14288 // recursively lowered by this routine, but will succeed as we definitely
14289 // have all the necessary features if we're using AVX1.
14291 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
14292 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
14294 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
14295 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
14296 Ld->isNonTemporal(), Ld->isInvariant(),
14297 Ld->getAlignment());
14300 // Replace chain users with the new chain.
14301 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
14302 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
14304 // Finally, do a normal sign-extend to the desired register.
14305 return DAG.getSExtOrTrunc(Load, dl, RegVT);
14308 // All sizes must be a power of two.
14309 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
14310 "Non-power-of-two elements are not custom lowered!");
14312 // Attempt to load the original value using scalar loads.
14313 // Find the largest scalar type that divides the total loaded size.
14314 MVT SclrLoadTy = MVT::i8;
14315 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
14316 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
14317 MVT Tp = (MVT::SimpleValueType)tp;
14318 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
14323 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
14324 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
14326 SclrLoadTy = MVT::f64;
14328 // Calculate the number of scalar loads that we need to perform
14329 // in order to load our vector from memory.
14330 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
14332 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
14333 "Can only lower sext loads with a single scalar load!");
14335 unsigned loadRegZize = RegSz;
14336 if (Ext == ISD::SEXTLOAD && RegSz == 256)
14339 // Represent our vector as a sequence of elements which are the
14340 // largest scalar that we can load.
14341 EVT LoadUnitVecVT = EVT::getVectorVT(
14342 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
14344 // Represent the data using the same element type that is stored in
14345 // memory. In practice, we ''widen'' MemVT.
14347 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
14348 loadRegZize / MemVT.getScalarType().getSizeInBits());
14350 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
14351 "Invalid vector type");
14353 // We can't shuffle using an illegal type.
14354 assert(TLI.isTypeLegal(WideVecVT) &&
14355 "We only lower types that form legal widened vector types");
14357 SmallVector<SDValue, 8> Chains;
14358 SDValue Ptr = Ld->getBasePtr();
14359 SDValue Increment =
14360 DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, TLI.getPointerTy());
14361 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
14363 for (unsigned i = 0; i < NumLoads; ++i) {
14364 // Perform a single load.
14365 SDValue ScalarLoad =
14366 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
14367 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
14368 Ld->getAlignment());
14369 Chains.push_back(ScalarLoad.getValue(1));
14370 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
14371 // another round of DAGCombining.
14373 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
14375 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
14376 ScalarLoad, DAG.getIntPtrConstant(i));
14378 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
14381 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
14383 // Bitcast the loaded value to a vector of the original element type, in
14384 // the size of the target vector type.
14385 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
14386 unsigned SizeRatio = RegSz / MemSz;
14388 if (Ext == ISD::SEXTLOAD) {
14389 // If we have SSE4.1, we can directly emit a VSEXT node.
14390 if (Subtarget->hasSSE41()) {
14391 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
14392 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
14396 // Otherwise we'll shuffle the small elements in the high bits of the
14397 // larger type and perform an arithmetic shift. If the shift is not legal
14398 // it's better to scalarize.
14399 assert(TLI.isOperationLegalOrCustom(ISD::SRA, RegVT) &&
14400 "We can't implement a sext load without an arithmetic right shift!");
14402 // Redistribute the loaded elements into the different locations.
14403 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
14404 for (unsigned i = 0; i != NumElems; ++i)
14405 ShuffleVec[i * SizeRatio + SizeRatio - 1] = i;
14407 SDValue Shuff = DAG.getVectorShuffle(
14408 WideVecVT, dl, SlicedVec, DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
14410 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
14412 // Build the arithmetic shift.
14413 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
14414 MemVT.getVectorElementType().getSizeInBits();
14416 DAG.getNode(ISD::SRA, dl, RegVT, Shuff, DAG.getConstant(Amt, RegVT));
14418 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
14422 // Redistribute the loaded elements into the different locations.
14423 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
14424 for (unsigned i = 0; i != NumElems; ++i)
14425 ShuffleVec[i * SizeRatio] = i;
14427 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
14428 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
14430 // Bitcast to the requested type.
14431 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
14432 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
14436 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
14437 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
14438 // from the AND / OR.
14439 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
14440 Opc = Op.getOpcode();
14441 if (Opc != ISD::OR && Opc != ISD::AND)
14443 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
14444 Op.getOperand(0).hasOneUse() &&
14445 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
14446 Op.getOperand(1).hasOneUse());
14449 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
14450 // 1 and that the SETCC node has a single use.
14451 static bool isXor1OfSetCC(SDValue Op) {
14452 if (Op.getOpcode() != ISD::XOR)
14454 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
14455 if (N1C && N1C->getAPIntValue() == 1) {
14456 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
14457 Op.getOperand(0).hasOneUse();
14462 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
14463 bool addTest = true;
14464 SDValue Chain = Op.getOperand(0);
14465 SDValue Cond = Op.getOperand(1);
14466 SDValue Dest = Op.getOperand(2);
14469 bool Inverted = false;
14471 if (Cond.getOpcode() == ISD::SETCC) {
14472 // Check for setcc([su]{add,sub,mul}o == 0).
14473 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
14474 isa<ConstantSDNode>(Cond.getOperand(1)) &&
14475 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
14476 Cond.getOperand(0).getResNo() == 1 &&
14477 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
14478 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
14479 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
14480 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
14481 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
14482 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
14484 Cond = Cond.getOperand(0);
14486 SDValue NewCond = LowerSETCC(Cond, DAG);
14487 if (NewCond.getNode())
14492 // FIXME: LowerXALUO doesn't handle these!!
14493 else if (Cond.getOpcode() == X86ISD::ADD ||
14494 Cond.getOpcode() == X86ISD::SUB ||
14495 Cond.getOpcode() == X86ISD::SMUL ||
14496 Cond.getOpcode() == X86ISD::UMUL)
14497 Cond = LowerXALUO(Cond, DAG);
14500 // Look pass (and (setcc_carry (cmp ...)), 1).
14501 if (Cond.getOpcode() == ISD::AND &&
14502 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
14503 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
14504 if (C && C->getAPIntValue() == 1)
14505 Cond = Cond.getOperand(0);
14508 // If condition flag is set by a X86ISD::CMP, then use it as the condition
14509 // setting operand in place of the X86ISD::SETCC.
14510 unsigned CondOpcode = Cond.getOpcode();
14511 if (CondOpcode == X86ISD::SETCC ||
14512 CondOpcode == X86ISD::SETCC_CARRY) {
14513 CC = Cond.getOperand(0);
14515 SDValue Cmp = Cond.getOperand(1);
14516 unsigned Opc = Cmp.getOpcode();
14517 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
14518 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
14522 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
14526 // These can only come from an arithmetic instruction with overflow,
14527 // e.g. SADDO, UADDO.
14528 Cond = Cond.getNode()->getOperand(1);
14534 CondOpcode = Cond.getOpcode();
14535 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
14536 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
14537 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
14538 Cond.getOperand(0).getValueType() != MVT::i8)) {
14539 SDValue LHS = Cond.getOperand(0);
14540 SDValue RHS = Cond.getOperand(1);
14541 unsigned X86Opcode;
14544 // Keep this in sync with LowerXALUO, otherwise we might create redundant
14545 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
14547 switch (CondOpcode) {
14548 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
14550 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
14552 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
14555 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
14556 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
14558 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
14560 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
14563 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
14564 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
14565 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
14566 default: llvm_unreachable("unexpected overflowing operator");
14569 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
14570 if (CondOpcode == ISD::UMULO)
14571 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
14574 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
14576 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
14578 if (CondOpcode == ISD::UMULO)
14579 Cond = X86Op.getValue(2);
14581 Cond = X86Op.getValue(1);
14583 CC = DAG.getConstant(X86Cond, MVT::i8);
14587 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
14588 SDValue Cmp = Cond.getOperand(0).getOperand(1);
14589 if (CondOpc == ISD::OR) {
14590 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
14591 // two branches instead of an explicit OR instruction with a
14593 if (Cmp == Cond.getOperand(1).getOperand(1) &&
14594 isX86LogicalCmp(Cmp)) {
14595 CC = Cond.getOperand(0).getOperand(0);
14596 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14597 Chain, Dest, CC, Cmp);
14598 CC = Cond.getOperand(1).getOperand(0);
14602 } else { // ISD::AND
14603 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
14604 // two branches instead of an explicit AND instruction with a
14605 // separate test. However, we only do this if this block doesn't
14606 // have a fall-through edge, because this requires an explicit
14607 // jmp when the condition is false.
14608 if (Cmp == Cond.getOperand(1).getOperand(1) &&
14609 isX86LogicalCmp(Cmp) &&
14610 Op.getNode()->hasOneUse()) {
14611 X86::CondCode CCode =
14612 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
14613 CCode = X86::GetOppositeBranchCondition(CCode);
14614 CC = DAG.getConstant(CCode, MVT::i8);
14615 SDNode *User = *Op.getNode()->use_begin();
14616 // Look for an unconditional branch following this conditional branch.
14617 // We need this because we need to reverse the successors in order
14618 // to implement FCMP_OEQ.
14619 if (User->getOpcode() == ISD::BR) {
14620 SDValue FalseBB = User->getOperand(1);
14622 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
14623 assert(NewBR == User);
14627 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14628 Chain, Dest, CC, Cmp);
14629 X86::CondCode CCode =
14630 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
14631 CCode = X86::GetOppositeBranchCondition(CCode);
14632 CC = DAG.getConstant(CCode, MVT::i8);
14638 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
14639 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
14640 // It should be transformed during dag combiner except when the condition
14641 // is set by a arithmetics with overflow node.
14642 X86::CondCode CCode =
14643 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
14644 CCode = X86::GetOppositeBranchCondition(CCode);
14645 CC = DAG.getConstant(CCode, MVT::i8);
14646 Cond = Cond.getOperand(0).getOperand(1);
14648 } else if (Cond.getOpcode() == ISD::SETCC &&
14649 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
14650 // For FCMP_OEQ, we can emit
14651 // two branches instead of an explicit AND instruction with a
14652 // separate test. However, we only do this if this block doesn't
14653 // have a fall-through edge, because this requires an explicit
14654 // jmp when the condition is false.
14655 if (Op.getNode()->hasOneUse()) {
14656 SDNode *User = *Op.getNode()->use_begin();
14657 // Look for an unconditional branch following this conditional branch.
14658 // We need this because we need to reverse the successors in order
14659 // to implement FCMP_OEQ.
14660 if (User->getOpcode() == ISD::BR) {
14661 SDValue FalseBB = User->getOperand(1);
14663 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
14664 assert(NewBR == User);
14668 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
14669 Cond.getOperand(0), Cond.getOperand(1));
14670 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14671 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
14672 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14673 Chain, Dest, CC, Cmp);
14674 CC = DAG.getConstant(X86::COND_P, MVT::i8);
14679 } else if (Cond.getOpcode() == ISD::SETCC &&
14680 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
14681 // For FCMP_UNE, we can emit
14682 // two branches instead of an explicit AND instruction with a
14683 // separate test. However, we only do this if this block doesn't
14684 // have a fall-through edge, because this requires an explicit
14685 // jmp when the condition is false.
14686 if (Op.getNode()->hasOneUse()) {
14687 SDNode *User = *Op.getNode()->use_begin();
14688 // Look for an unconditional branch following this conditional branch.
14689 // We need this because we need to reverse the successors in order
14690 // to implement FCMP_UNE.
14691 if (User->getOpcode() == ISD::BR) {
14692 SDValue FalseBB = User->getOperand(1);
14694 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
14695 assert(NewBR == User);
14698 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
14699 Cond.getOperand(0), Cond.getOperand(1));
14700 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14701 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
14702 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14703 Chain, Dest, CC, Cmp);
14704 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
14714 // Look pass the truncate if the high bits are known zero.
14715 if (isTruncWithZeroHighBitsInput(Cond, DAG))
14716 Cond = Cond.getOperand(0);
14718 // We know the result of AND is compared against zero. Try to match
14720 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
14721 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
14722 if (NewSetCC.getNode()) {
14723 CC = NewSetCC.getOperand(0);
14724 Cond = NewSetCC.getOperand(1);
14731 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
14732 CC = DAG.getConstant(X86Cond, MVT::i8);
14733 Cond = EmitTest(Cond, X86Cond, dl, DAG);
14735 Cond = ConvertCmpIfNecessary(Cond, DAG);
14736 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14737 Chain, Dest, CC, Cond);
14740 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
14741 // Calls to _alloca are needed to probe the stack when allocating more than 4k
14742 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
14743 // that the guard pages used by the OS virtual memory manager are allocated in
14744 // correct sequence.
14746 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
14747 SelectionDAG &DAG) const {
14748 MachineFunction &MF = DAG.getMachineFunction();
14749 bool SplitStack = MF.shouldSplitStack();
14750 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMacho()) ||
14755 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14756 SDNode* Node = Op.getNode();
14758 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
14759 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
14760 " not tell us which reg is the stack pointer!");
14761 EVT VT = Node->getValueType(0);
14762 SDValue Tmp1 = SDValue(Node, 0);
14763 SDValue Tmp2 = SDValue(Node, 1);
14764 SDValue Tmp3 = Node->getOperand(2);
14765 SDValue Chain = Tmp1.getOperand(0);
14767 // Chain the dynamic stack allocation so that it doesn't modify the stack
14768 // pointer when other instructions are using the stack.
14769 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true),
14772 SDValue Size = Tmp2.getOperand(1);
14773 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
14774 Chain = SP.getValue(1);
14775 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
14776 const TargetFrameLowering &TFI = *DAG.getSubtarget().getFrameLowering();
14777 unsigned StackAlign = TFI.getStackAlignment();
14778 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
14779 if (Align > StackAlign)
14780 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
14781 DAG.getConstant(-(uint64_t)Align, VT));
14782 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
14784 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
14785 DAG.getIntPtrConstant(0, true), SDValue(),
14788 SDValue Ops[2] = { Tmp1, Tmp2 };
14789 return DAG.getMergeValues(Ops, dl);
14793 SDValue Chain = Op.getOperand(0);
14794 SDValue Size = Op.getOperand(1);
14795 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
14796 EVT VT = Op.getNode()->getValueType(0);
14798 bool Is64Bit = Subtarget->is64Bit();
14799 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32;
14802 MachineRegisterInfo &MRI = MF.getRegInfo();
14805 // The 64 bit implementation of segmented stacks needs to clobber both r10
14806 // r11. This makes it impossible to use it along with nested parameters.
14807 const Function *F = MF.getFunction();
14809 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
14811 if (I->hasNestAttr())
14812 report_fatal_error("Cannot use segmented stacks with functions that "
14813 "have nested arguments.");
14816 const TargetRegisterClass *AddrRegClass =
14817 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32);
14818 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
14819 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
14820 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
14821 DAG.getRegister(Vreg, SPTy));
14822 SDValue Ops1[2] = { Value, Chain };
14823 return DAG.getMergeValues(Ops1, dl);
14826 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
14828 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
14829 Flag = Chain.getValue(1);
14830 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
14832 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
14834 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
14835 DAG.getSubtarget().getRegisterInfo());
14836 unsigned SPReg = RegInfo->getStackRegister();
14837 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
14838 Chain = SP.getValue(1);
14841 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
14842 DAG.getConstant(-(uint64_t)Align, VT));
14843 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
14846 SDValue Ops1[2] = { SP, Chain };
14847 return DAG.getMergeValues(Ops1, dl);
14851 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
14852 MachineFunction &MF = DAG.getMachineFunction();
14853 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
14855 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
14858 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
14859 // vastart just stores the address of the VarArgsFrameIndex slot into the
14860 // memory location argument.
14861 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
14863 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
14864 MachinePointerInfo(SV), false, false, 0);
14868 // gp_offset (0 - 6 * 8)
14869 // fp_offset (48 - 48 + 8 * 16)
14870 // overflow_arg_area (point to parameters coming in memory).
14872 SmallVector<SDValue, 8> MemOps;
14873 SDValue FIN = Op.getOperand(1);
14875 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
14876 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
14878 FIN, MachinePointerInfo(SV), false, false, 0);
14879 MemOps.push_back(Store);
14882 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
14883 FIN, DAG.getIntPtrConstant(4));
14884 Store = DAG.getStore(Op.getOperand(0), DL,
14885 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
14887 FIN, MachinePointerInfo(SV, 4), false, false, 0);
14888 MemOps.push_back(Store);
14890 // Store ptr to overflow_arg_area
14891 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
14892 FIN, DAG.getIntPtrConstant(4));
14893 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
14895 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
14896 MachinePointerInfo(SV, 8),
14898 MemOps.push_back(Store);
14900 // Store ptr to reg_save_area.
14901 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
14902 FIN, DAG.getIntPtrConstant(8));
14903 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
14905 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
14906 MachinePointerInfo(SV, 16), false, false, 0);
14907 MemOps.push_back(Store);
14908 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
14911 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
14912 assert(Subtarget->is64Bit() &&
14913 "LowerVAARG only handles 64-bit va_arg!");
14914 assert((Subtarget->isTargetLinux() ||
14915 Subtarget->isTargetDarwin()) &&
14916 "Unhandled target in LowerVAARG");
14917 assert(Op.getNode()->getNumOperands() == 4);
14918 SDValue Chain = Op.getOperand(0);
14919 SDValue SrcPtr = Op.getOperand(1);
14920 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
14921 unsigned Align = Op.getConstantOperandVal(3);
14924 EVT ArgVT = Op.getNode()->getValueType(0);
14925 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
14926 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
14929 // Decide which area this value should be read from.
14930 // TODO: Implement the AMD64 ABI in its entirety. This simple
14931 // selection mechanism works only for the basic types.
14932 if (ArgVT == MVT::f80) {
14933 llvm_unreachable("va_arg for f80 not yet implemented");
14934 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
14935 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
14936 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
14937 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
14939 llvm_unreachable("Unhandled argument type in LowerVAARG");
14942 if (ArgMode == 2) {
14943 // Sanity Check: Make sure using fp_offset makes sense.
14944 assert(!DAG.getTarget().Options.UseSoftFloat &&
14945 !(DAG.getMachineFunction()
14946 .getFunction()->getAttributes()
14947 .hasAttribute(AttributeSet::FunctionIndex,
14948 Attribute::NoImplicitFloat)) &&
14949 Subtarget->hasSSE1());
14952 // Insert VAARG_64 node into the DAG
14953 // VAARG_64 returns two values: Variable Argument Address, Chain
14954 SmallVector<SDValue, 11> InstOps;
14955 InstOps.push_back(Chain);
14956 InstOps.push_back(SrcPtr);
14957 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
14958 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
14959 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
14960 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
14961 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
14962 VTs, InstOps, MVT::i64,
14963 MachinePointerInfo(SV),
14965 /*Volatile=*/false,
14967 /*WriteMem=*/true);
14968 Chain = VAARG.getValue(1);
14970 // Load the next argument and return it
14971 return DAG.getLoad(ArgVT, dl,
14974 MachinePointerInfo(),
14975 false, false, false, 0);
14978 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
14979 SelectionDAG &DAG) {
14980 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
14981 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
14982 SDValue Chain = Op.getOperand(0);
14983 SDValue DstPtr = Op.getOperand(1);
14984 SDValue SrcPtr = Op.getOperand(2);
14985 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
14986 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
14989 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
14990 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
14992 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
14995 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
14996 // amount is a constant. Takes immediate version of shift as input.
14997 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
14998 SDValue SrcOp, uint64_t ShiftAmt,
14999 SelectionDAG &DAG) {
15000 MVT ElementType = VT.getVectorElementType();
15002 // Fold this packed shift into its first operand if ShiftAmt is 0.
15006 // Check for ShiftAmt >= element width
15007 if (ShiftAmt >= ElementType.getSizeInBits()) {
15008 if (Opc == X86ISD::VSRAI)
15009 ShiftAmt = ElementType.getSizeInBits() - 1;
15011 return DAG.getConstant(0, VT);
15014 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
15015 && "Unknown target vector shift-by-constant node");
15017 // Fold this packed vector shift into a build vector if SrcOp is a
15018 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
15019 if (VT == SrcOp.getSimpleValueType() &&
15020 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
15021 SmallVector<SDValue, 8> Elts;
15022 unsigned NumElts = SrcOp->getNumOperands();
15023 ConstantSDNode *ND;
15026 default: llvm_unreachable(nullptr);
15027 case X86ISD::VSHLI:
15028 for (unsigned i=0; i!=NumElts; ++i) {
15029 SDValue CurrentOp = SrcOp->getOperand(i);
15030 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15031 Elts.push_back(CurrentOp);
15034 ND = cast<ConstantSDNode>(CurrentOp);
15035 const APInt &C = ND->getAPIntValue();
15036 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), ElementType));
15039 case X86ISD::VSRLI:
15040 for (unsigned i=0; i!=NumElts; ++i) {
15041 SDValue CurrentOp = SrcOp->getOperand(i);
15042 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15043 Elts.push_back(CurrentOp);
15046 ND = cast<ConstantSDNode>(CurrentOp);
15047 const APInt &C = ND->getAPIntValue();
15048 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), ElementType));
15051 case X86ISD::VSRAI:
15052 for (unsigned i=0; i!=NumElts; ++i) {
15053 SDValue CurrentOp = SrcOp->getOperand(i);
15054 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15055 Elts.push_back(CurrentOp);
15058 ND = cast<ConstantSDNode>(CurrentOp);
15059 const APInt &C = ND->getAPIntValue();
15060 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), ElementType));
15065 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
15068 return DAG.getNode(Opc, dl, VT, SrcOp, DAG.getConstant(ShiftAmt, MVT::i8));
15071 // getTargetVShiftNode - Handle vector element shifts where the shift amount
15072 // may or may not be a constant. Takes immediate version of shift as input.
15073 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
15074 SDValue SrcOp, SDValue ShAmt,
15075 SelectionDAG &DAG) {
15076 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
15078 // Catch shift-by-constant.
15079 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
15080 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
15081 CShAmt->getZExtValue(), DAG);
15083 // Change opcode to non-immediate version
15085 default: llvm_unreachable("Unknown target vector shift node");
15086 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
15087 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
15088 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
15091 // Need to build a vector containing shift amount
15092 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
15095 ShOps[1] = DAG.getConstant(0, MVT::i32);
15096 ShOps[2] = ShOps[3] = DAG.getUNDEF(MVT::i32);
15097 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, ShOps);
15099 // The return type has to be a 128-bit type with the same element
15100 // type as the input type.
15101 MVT EltVT = VT.getVectorElementType();
15102 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
15104 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
15105 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
15108 /// \brief Return (vselect \p Mask, \p Op, \p PreservedSrc) along with the
15109 /// necessary casting for \p Mask when lowering masking intrinsics.
15110 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
15111 SDValue PreservedSrc, SelectionDAG &DAG) {
15112 EVT VT = Op.getValueType();
15113 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
15114 MVT::i1, VT.getVectorNumElements());
15117 assert(MaskVT.isSimple() && "invalid mask type");
15118 return DAG.getNode(ISD::VSELECT, dl, VT,
15119 DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask),
15123 static unsigned getOpcodeForFMAIntrinsic(unsigned IntNo) {
15125 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
15126 case Intrinsic::x86_fma_vfmadd_ps:
15127 case Intrinsic::x86_fma_vfmadd_pd:
15128 case Intrinsic::x86_fma_vfmadd_ps_256:
15129 case Intrinsic::x86_fma_vfmadd_pd_256:
15130 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
15131 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
15132 return X86ISD::FMADD;
15133 case Intrinsic::x86_fma_vfmsub_ps:
15134 case Intrinsic::x86_fma_vfmsub_pd:
15135 case Intrinsic::x86_fma_vfmsub_ps_256:
15136 case Intrinsic::x86_fma_vfmsub_pd_256:
15137 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
15138 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
15139 return X86ISD::FMSUB;
15140 case Intrinsic::x86_fma_vfnmadd_ps:
15141 case Intrinsic::x86_fma_vfnmadd_pd:
15142 case Intrinsic::x86_fma_vfnmadd_ps_256:
15143 case Intrinsic::x86_fma_vfnmadd_pd_256:
15144 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
15145 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
15146 return X86ISD::FNMADD;
15147 case Intrinsic::x86_fma_vfnmsub_ps:
15148 case Intrinsic::x86_fma_vfnmsub_pd:
15149 case Intrinsic::x86_fma_vfnmsub_ps_256:
15150 case Intrinsic::x86_fma_vfnmsub_pd_256:
15151 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
15152 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
15153 return X86ISD::FNMSUB;
15154 case Intrinsic::x86_fma_vfmaddsub_ps:
15155 case Intrinsic::x86_fma_vfmaddsub_pd:
15156 case Intrinsic::x86_fma_vfmaddsub_ps_256:
15157 case Intrinsic::x86_fma_vfmaddsub_pd_256:
15158 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
15159 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
15160 return X86ISD::FMADDSUB;
15161 case Intrinsic::x86_fma_vfmsubadd_ps:
15162 case Intrinsic::x86_fma_vfmsubadd_pd:
15163 case Intrinsic::x86_fma_vfmsubadd_ps_256:
15164 case Intrinsic::x86_fma_vfmsubadd_pd_256:
15165 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
15166 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512:
15167 return X86ISD::FMSUBADD;
15171 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
15173 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15175 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
15177 switch(IntrData->Type) {
15178 case INTR_TYPE_1OP:
15179 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
15180 case INTR_TYPE_2OP:
15181 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
15183 case INTR_TYPE_3OP:
15184 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
15185 Op.getOperand(2), Op.getOperand(3));
15186 case COMI: { // Comparison intrinsics
15187 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
15188 SDValue LHS = Op.getOperand(1);
15189 SDValue RHS = Op.getOperand(2);
15190 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
15191 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
15192 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
15193 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15194 DAG.getConstant(X86CC, MVT::i8), Cond);
15195 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15198 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
15199 Op.getOperand(1), Op.getOperand(2), DAG);
15206 default: return SDValue(); // Don't custom lower most intrinsics.
15208 // Arithmetic intrinsics.
15209 case Intrinsic::x86_sse2_pmulu_dq:
15210 case Intrinsic::x86_avx2_pmulu_dq:
15211 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
15212 Op.getOperand(1), Op.getOperand(2));
15214 case Intrinsic::x86_sse41_pmuldq:
15215 case Intrinsic::x86_avx2_pmul_dq:
15216 return DAG.getNode(X86ISD::PMULDQ, dl, Op.getValueType(),
15217 Op.getOperand(1), Op.getOperand(2));
15219 case Intrinsic::x86_sse2_pmulhu_w:
15220 case Intrinsic::x86_avx2_pmulhu_w:
15221 return DAG.getNode(ISD::MULHU, dl, Op.getValueType(),
15222 Op.getOperand(1), Op.getOperand(2));
15224 case Intrinsic::x86_sse2_pmulh_w:
15225 case Intrinsic::x86_avx2_pmulh_w:
15226 return DAG.getNode(ISD::MULHS, dl, Op.getValueType(),
15227 Op.getOperand(1), Op.getOperand(2));
15229 // SSE/SSE2/AVX floating point max/min intrinsics.
15230 case Intrinsic::x86_sse_max_ps:
15231 case Intrinsic::x86_sse2_max_pd:
15232 case Intrinsic::x86_avx_max_ps_256:
15233 case Intrinsic::x86_avx_max_pd_256:
15234 case Intrinsic::x86_sse_min_ps:
15235 case Intrinsic::x86_sse2_min_pd:
15236 case Intrinsic::x86_avx_min_ps_256:
15237 case Intrinsic::x86_avx_min_pd_256: {
15240 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
15241 case Intrinsic::x86_sse_max_ps:
15242 case Intrinsic::x86_sse2_max_pd:
15243 case Intrinsic::x86_avx_max_ps_256:
15244 case Intrinsic::x86_avx_max_pd_256:
15245 Opcode = X86ISD::FMAX;
15247 case Intrinsic::x86_sse_min_ps:
15248 case Intrinsic::x86_sse2_min_pd:
15249 case Intrinsic::x86_avx_min_ps_256:
15250 case Intrinsic::x86_avx_min_pd_256:
15251 Opcode = X86ISD::FMIN;
15254 return DAG.getNode(Opcode, dl, Op.getValueType(),
15255 Op.getOperand(1), Op.getOperand(2));
15258 // AVX2 variable shift intrinsics
15259 case Intrinsic::x86_avx2_psllv_d:
15260 case Intrinsic::x86_avx2_psllv_q:
15261 case Intrinsic::x86_avx2_psllv_d_256:
15262 case Intrinsic::x86_avx2_psllv_q_256:
15263 case Intrinsic::x86_avx2_psrlv_d:
15264 case Intrinsic::x86_avx2_psrlv_q:
15265 case Intrinsic::x86_avx2_psrlv_d_256:
15266 case Intrinsic::x86_avx2_psrlv_q_256:
15267 case Intrinsic::x86_avx2_psrav_d:
15268 case Intrinsic::x86_avx2_psrav_d_256: {
15271 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
15272 case Intrinsic::x86_avx2_psllv_d:
15273 case Intrinsic::x86_avx2_psllv_q:
15274 case Intrinsic::x86_avx2_psllv_d_256:
15275 case Intrinsic::x86_avx2_psllv_q_256:
15278 case Intrinsic::x86_avx2_psrlv_d:
15279 case Intrinsic::x86_avx2_psrlv_q:
15280 case Intrinsic::x86_avx2_psrlv_d_256:
15281 case Intrinsic::x86_avx2_psrlv_q_256:
15284 case Intrinsic::x86_avx2_psrav_d:
15285 case Intrinsic::x86_avx2_psrav_d_256:
15289 return DAG.getNode(Opcode, dl, Op.getValueType(),
15290 Op.getOperand(1), Op.getOperand(2));
15293 case Intrinsic::x86_sse2_packssdw_128:
15294 case Intrinsic::x86_sse2_packsswb_128:
15295 case Intrinsic::x86_avx2_packssdw:
15296 case Intrinsic::x86_avx2_packsswb:
15297 return DAG.getNode(X86ISD::PACKSS, dl, Op.getValueType(),
15298 Op.getOperand(1), Op.getOperand(2));
15300 case Intrinsic::x86_sse2_packuswb_128:
15301 case Intrinsic::x86_sse41_packusdw:
15302 case Intrinsic::x86_avx2_packuswb:
15303 case Intrinsic::x86_avx2_packusdw:
15304 return DAG.getNode(X86ISD::PACKUS, dl, Op.getValueType(),
15305 Op.getOperand(1), Op.getOperand(2));
15307 case Intrinsic::x86_ssse3_pshuf_b_128:
15308 case Intrinsic::x86_avx2_pshuf_b:
15309 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
15310 Op.getOperand(1), Op.getOperand(2));
15312 case Intrinsic::x86_sse2_pshuf_d:
15313 return DAG.getNode(X86ISD::PSHUFD, dl, Op.getValueType(),
15314 Op.getOperand(1), Op.getOperand(2));
15316 case Intrinsic::x86_sse2_pshufl_w:
15317 return DAG.getNode(X86ISD::PSHUFLW, dl, Op.getValueType(),
15318 Op.getOperand(1), Op.getOperand(2));
15320 case Intrinsic::x86_sse2_pshufh_w:
15321 return DAG.getNode(X86ISD::PSHUFHW, dl, Op.getValueType(),
15322 Op.getOperand(1), Op.getOperand(2));
15324 case Intrinsic::x86_ssse3_psign_b_128:
15325 case Intrinsic::x86_ssse3_psign_w_128:
15326 case Intrinsic::x86_ssse3_psign_d_128:
15327 case Intrinsic::x86_avx2_psign_b:
15328 case Intrinsic::x86_avx2_psign_w:
15329 case Intrinsic::x86_avx2_psign_d:
15330 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
15331 Op.getOperand(1), Op.getOperand(2));
15333 case Intrinsic::x86_avx2_permd:
15334 case Intrinsic::x86_avx2_permps:
15335 // Operands intentionally swapped. Mask is last operand to intrinsic,
15336 // but second operand for node/instruction.
15337 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
15338 Op.getOperand(2), Op.getOperand(1));
15340 case Intrinsic::x86_avx512_mask_valign_q_512:
15341 case Intrinsic::x86_avx512_mask_valign_d_512:
15342 // Vector source operands are swapped.
15343 return getVectorMaskingNode(DAG.getNode(X86ISD::VALIGN, dl,
15344 Op.getValueType(), Op.getOperand(2),
15347 Op.getOperand(5), Op.getOperand(4), DAG);
15349 // ptest and testp intrinsics. The intrinsic these come from are designed to
15350 // return an integer value, not just an instruction so lower it to the ptest
15351 // or testp pattern and a setcc for the result.
15352 case Intrinsic::x86_sse41_ptestz:
15353 case Intrinsic::x86_sse41_ptestc:
15354 case Intrinsic::x86_sse41_ptestnzc:
15355 case Intrinsic::x86_avx_ptestz_256:
15356 case Intrinsic::x86_avx_ptestc_256:
15357 case Intrinsic::x86_avx_ptestnzc_256:
15358 case Intrinsic::x86_avx_vtestz_ps:
15359 case Intrinsic::x86_avx_vtestc_ps:
15360 case Intrinsic::x86_avx_vtestnzc_ps:
15361 case Intrinsic::x86_avx_vtestz_pd:
15362 case Intrinsic::x86_avx_vtestc_pd:
15363 case Intrinsic::x86_avx_vtestnzc_pd:
15364 case Intrinsic::x86_avx_vtestz_ps_256:
15365 case Intrinsic::x86_avx_vtestc_ps_256:
15366 case Intrinsic::x86_avx_vtestnzc_ps_256:
15367 case Intrinsic::x86_avx_vtestz_pd_256:
15368 case Intrinsic::x86_avx_vtestc_pd_256:
15369 case Intrinsic::x86_avx_vtestnzc_pd_256: {
15370 bool IsTestPacked = false;
15373 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
15374 case Intrinsic::x86_avx_vtestz_ps:
15375 case Intrinsic::x86_avx_vtestz_pd:
15376 case Intrinsic::x86_avx_vtestz_ps_256:
15377 case Intrinsic::x86_avx_vtestz_pd_256:
15378 IsTestPacked = true; // Fallthrough
15379 case Intrinsic::x86_sse41_ptestz:
15380 case Intrinsic::x86_avx_ptestz_256:
15382 X86CC = X86::COND_E;
15384 case Intrinsic::x86_avx_vtestc_ps:
15385 case Intrinsic::x86_avx_vtestc_pd:
15386 case Intrinsic::x86_avx_vtestc_ps_256:
15387 case Intrinsic::x86_avx_vtestc_pd_256:
15388 IsTestPacked = true; // Fallthrough
15389 case Intrinsic::x86_sse41_ptestc:
15390 case Intrinsic::x86_avx_ptestc_256:
15392 X86CC = X86::COND_B;
15394 case Intrinsic::x86_avx_vtestnzc_ps:
15395 case Intrinsic::x86_avx_vtestnzc_pd:
15396 case Intrinsic::x86_avx_vtestnzc_ps_256:
15397 case Intrinsic::x86_avx_vtestnzc_pd_256:
15398 IsTestPacked = true; // Fallthrough
15399 case Intrinsic::x86_sse41_ptestnzc:
15400 case Intrinsic::x86_avx_ptestnzc_256:
15402 X86CC = X86::COND_A;
15406 SDValue LHS = Op.getOperand(1);
15407 SDValue RHS = Op.getOperand(2);
15408 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
15409 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
15410 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
15411 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
15412 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15414 case Intrinsic::x86_avx512_kortestz_w:
15415 case Intrinsic::x86_avx512_kortestc_w: {
15416 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
15417 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
15418 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
15419 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
15420 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
15421 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
15422 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15425 case Intrinsic::x86_sse42_pcmpistria128:
15426 case Intrinsic::x86_sse42_pcmpestria128:
15427 case Intrinsic::x86_sse42_pcmpistric128:
15428 case Intrinsic::x86_sse42_pcmpestric128:
15429 case Intrinsic::x86_sse42_pcmpistrio128:
15430 case Intrinsic::x86_sse42_pcmpestrio128:
15431 case Intrinsic::x86_sse42_pcmpistris128:
15432 case Intrinsic::x86_sse42_pcmpestris128:
15433 case Intrinsic::x86_sse42_pcmpistriz128:
15434 case Intrinsic::x86_sse42_pcmpestriz128: {
15438 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
15439 case Intrinsic::x86_sse42_pcmpistria128:
15440 Opcode = X86ISD::PCMPISTRI;
15441 X86CC = X86::COND_A;
15443 case Intrinsic::x86_sse42_pcmpestria128:
15444 Opcode = X86ISD::PCMPESTRI;
15445 X86CC = X86::COND_A;
15447 case Intrinsic::x86_sse42_pcmpistric128:
15448 Opcode = X86ISD::PCMPISTRI;
15449 X86CC = X86::COND_B;
15451 case Intrinsic::x86_sse42_pcmpestric128:
15452 Opcode = X86ISD::PCMPESTRI;
15453 X86CC = X86::COND_B;
15455 case Intrinsic::x86_sse42_pcmpistrio128:
15456 Opcode = X86ISD::PCMPISTRI;
15457 X86CC = X86::COND_O;
15459 case Intrinsic::x86_sse42_pcmpestrio128:
15460 Opcode = X86ISD::PCMPESTRI;
15461 X86CC = X86::COND_O;
15463 case Intrinsic::x86_sse42_pcmpistris128:
15464 Opcode = X86ISD::PCMPISTRI;
15465 X86CC = X86::COND_S;
15467 case Intrinsic::x86_sse42_pcmpestris128:
15468 Opcode = X86ISD::PCMPESTRI;
15469 X86CC = X86::COND_S;
15471 case Intrinsic::x86_sse42_pcmpistriz128:
15472 Opcode = X86ISD::PCMPISTRI;
15473 X86CC = X86::COND_E;
15475 case Intrinsic::x86_sse42_pcmpestriz128:
15476 Opcode = X86ISD::PCMPESTRI;
15477 X86CC = X86::COND_E;
15480 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
15481 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
15482 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
15483 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15484 DAG.getConstant(X86CC, MVT::i8),
15485 SDValue(PCMP.getNode(), 1));
15486 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15489 case Intrinsic::x86_sse42_pcmpistri128:
15490 case Intrinsic::x86_sse42_pcmpestri128: {
15492 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
15493 Opcode = X86ISD::PCMPISTRI;
15495 Opcode = X86ISD::PCMPESTRI;
15497 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
15498 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
15499 return DAG.getNode(Opcode, dl, VTs, NewOps);
15502 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
15503 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
15504 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
15505 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
15506 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
15507 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
15508 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
15509 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
15510 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
15511 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
15512 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
15513 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512: {
15514 auto *SAE = cast<ConstantSDNode>(Op.getOperand(5));
15515 if (SAE->getZExtValue() == X86::STATIC_ROUNDING::CUR_DIRECTION)
15516 return getVectorMaskingNode(DAG.getNode(getOpcodeForFMAIntrinsic(IntNo),
15517 dl, Op.getValueType(),
15521 Op.getOperand(4), Op.getOperand(1), DAG);
15526 case Intrinsic::x86_fma_vfmadd_ps:
15527 case Intrinsic::x86_fma_vfmadd_pd:
15528 case Intrinsic::x86_fma_vfmsub_ps:
15529 case Intrinsic::x86_fma_vfmsub_pd:
15530 case Intrinsic::x86_fma_vfnmadd_ps:
15531 case Intrinsic::x86_fma_vfnmadd_pd:
15532 case Intrinsic::x86_fma_vfnmsub_ps:
15533 case Intrinsic::x86_fma_vfnmsub_pd:
15534 case Intrinsic::x86_fma_vfmaddsub_ps:
15535 case Intrinsic::x86_fma_vfmaddsub_pd:
15536 case Intrinsic::x86_fma_vfmsubadd_ps:
15537 case Intrinsic::x86_fma_vfmsubadd_pd:
15538 case Intrinsic::x86_fma_vfmadd_ps_256:
15539 case Intrinsic::x86_fma_vfmadd_pd_256:
15540 case Intrinsic::x86_fma_vfmsub_ps_256:
15541 case Intrinsic::x86_fma_vfmsub_pd_256:
15542 case Intrinsic::x86_fma_vfnmadd_ps_256:
15543 case Intrinsic::x86_fma_vfnmadd_pd_256:
15544 case Intrinsic::x86_fma_vfnmsub_ps_256:
15545 case Intrinsic::x86_fma_vfnmsub_pd_256:
15546 case Intrinsic::x86_fma_vfmaddsub_ps_256:
15547 case Intrinsic::x86_fma_vfmaddsub_pd_256:
15548 case Intrinsic::x86_fma_vfmsubadd_ps_256:
15549 case Intrinsic::x86_fma_vfmsubadd_pd_256:
15550 return DAG.getNode(getOpcodeForFMAIntrinsic(IntNo), dl, Op.getValueType(),
15551 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
15555 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
15556 SDValue Src, SDValue Mask, SDValue Base,
15557 SDValue Index, SDValue ScaleOp, SDValue Chain,
15558 const X86Subtarget * Subtarget) {
15560 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
15561 assert(C && "Invalid scale type");
15562 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
15563 EVT MaskVT = MVT::getVectorVT(MVT::i1,
15564 Index.getSimpleValueType().getVectorNumElements());
15566 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
15568 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
15570 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
15571 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
15572 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
15573 SDValue Segment = DAG.getRegister(0, MVT::i32);
15574 if (Src.getOpcode() == ISD::UNDEF)
15575 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
15576 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
15577 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
15578 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
15579 return DAG.getMergeValues(RetOps, dl);
15582 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
15583 SDValue Src, SDValue Mask, SDValue Base,
15584 SDValue Index, SDValue ScaleOp, SDValue Chain) {
15586 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
15587 assert(C && "Invalid scale type");
15588 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
15589 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
15590 SDValue Segment = DAG.getRegister(0, MVT::i32);
15591 EVT MaskVT = MVT::getVectorVT(MVT::i1,
15592 Index.getSimpleValueType().getVectorNumElements());
15594 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
15596 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
15598 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
15599 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
15600 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
15601 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
15602 return SDValue(Res, 1);
15605 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
15606 SDValue Mask, SDValue Base, SDValue Index,
15607 SDValue ScaleOp, SDValue Chain) {
15609 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
15610 assert(C && "Invalid scale type");
15611 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
15612 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
15613 SDValue Segment = DAG.getRegister(0, MVT::i32);
15615 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
15617 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
15619 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
15621 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
15622 //SDVTList VTs = DAG.getVTList(MVT::Other);
15623 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
15624 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
15625 return SDValue(Res, 0);
15628 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
15629 // read performance monitor counters (x86_rdpmc).
15630 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
15631 SelectionDAG &DAG, const X86Subtarget *Subtarget,
15632 SmallVectorImpl<SDValue> &Results) {
15633 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
15634 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
15637 // The ECX register is used to select the index of the performance counter
15639 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
15641 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
15643 // Reads the content of a 64-bit performance counter and returns it in the
15644 // registers EDX:EAX.
15645 if (Subtarget->is64Bit()) {
15646 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
15647 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
15650 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
15651 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
15654 Chain = HI.getValue(1);
15656 if (Subtarget->is64Bit()) {
15657 // The EAX register is loaded with the low-order 32 bits. The EDX register
15658 // is loaded with the supported high-order bits of the counter.
15659 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
15660 DAG.getConstant(32, MVT::i8));
15661 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
15662 Results.push_back(Chain);
15666 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
15667 SDValue Ops[] = { LO, HI };
15668 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
15669 Results.push_back(Pair);
15670 Results.push_back(Chain);
15673 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
15674 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
15675 // also used to custom lower READCYCLECOUNTER nodes.
15676 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
15677 SelectionDAG &DAG, const X86Subtarget *Subtarget,
15678 SmallVectorImpl<SDValue> &Results) {
15679 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
15680 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
15683 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
15684 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
15685 // and the EAX register is loaded with the low-order 32 bits.
15686 if (Subtarget->is64Bit()) {
15687 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
15688 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
15691 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
15692 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
15695 SDValue Chain = HI.getValue(1);
15697 if (Opcode == X86ISD::RDTSCP_DAG) {
15698 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
15700 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
15701 // the ECX register. Add 'ecx' explicitly to the chain.
15702 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
15704 // Explicitly store the content of ECX at the location passed in input
15705 // to the 'rdtscp' intrinsic.
15706 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
15707 MachinePointerInfo(), false, false, 0);
15710 if (Subtarget->is64Bit()) {
15711 // The EDX register is loaded with the high-order 32 bits of the MSR, and
15712 // the EAX register is loaded with the low-order 32 bits.
15713 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
15714 DAG.getConstant(32, MVT::i8));
15715 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
15716 Results.push_back(Chain);
15720 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
15721 SDValue Ops[] = { LO, HI };
15722 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
15723 Results.push_back(Pair);
15724 Results.push_back(Chain);
15727 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
15728 SelectionDAG &DAG) {
15729 SmallVector<SDValue, 2> Results;
15731 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
15733 return DAG.getMergeValues(Results, DL);
15737 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
15738 SelectionDAG &DAG) {
15739 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
15741 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
15746 switch(IntrData->Type) {
15748 llvm_unreachable("Unknown Intrinsic Type");
15752 // Emit the node with the right value type.
15753 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
15754 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
15756 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
15757 // Otherwise return the value from Rand, which is always 0, casted to i32.
15758 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
15759 DAG.getConstant(1, Op->getValueType(1)),
15760 DAG.getConstant(X86::COND_B, MVT::i32),
15761 SDValue(Result.getNode(), 1) };
15762 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
15763 DAG.getVTList(Op->getValueType(1), MVT::Glue),
15766 // Return { result, isValid, chain }.
15767 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
15768 SDValue(Result.getNode(), 2));
15771 //gather(v1, mask, index, base, scale);
15772 SDValue Chain = Op.getOperand(0);
15773 SDValue Src = Op.getOperand(2);
15774 SDValue Base = Op.getOperand(3);
15775 SDValue Index = Op.getOperand(4);
15776 SDValue Mask = Op.getOperand(5);
15777 SDValue Scale = Op.getOperand(6);
15778 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain,
15782 //scatter(base, mask, index, v1, scale);
15783 SDValue Chain = Op.getOperand(0);
15784 SDValue Base = Op.getOperand(2);
15785 SDValue Mask = Op.getOperand(3);
15786 SDValue Index = Op.getOperand(4);
15787 SDValue Src = Op.getOperand(5);
15788 SDValue Scale = Op.getOperand(6);
15789 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain);
15792 SDValue Hint = Op.getOperand(6);
15794 if (dyn_cast<ConstantSDNode> (Hint) == nullptr ||
15795 (HintVal = dyn_cast<ConstantSDNode> (Hint)->getZExtValue()) > 1)
15796 llvm_unreachable("Wrong prefetch hint in intrinsic: should be 0 or 1");
15797 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
15798 SDValue Chain = Op.getOperand(0);
15799 SDValue Mask = Op.getOperand(2);
15800 SDValue Index = Op.getOperand(3);
15801 SDValue Base = Op.getOperand(4);
15802 SDValue Scale = Op.getOperand(5);
15803 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
15805 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
15807 SmallVector<SDValue, 2> Results;
15808 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget, Results);
15809 return DAG.getMergeValues(Results, dl);
15811 // Read Performance Monitoring Counters.
15813 SmallVector<SDValue, 2> Results;
15814 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
15815 return DAG.getMergeValues(Results, dl);
15817 // XTEST intrinsics.
15819 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
15820 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
15821 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15822 DAG.getConstant(X86::COND_NE, MVT::i8),
15824 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
15825 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
15826 Ret, SDValue(InTrans.getNode(), 1));
15830 SmallVector<SDValue, 2> Results;
15831 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
15832 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
15833 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
15834 DAG.getConstant(-1, MVT::i8));
15835 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
15836 Op.getOperand(4), GenCF.getValue(1));
15837 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
15838 Op.getOperand(5), MachinePointerInfo(),
15840 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15841 DAG.getConstant(X86::COND_B, MVT::i8),
15843 Results.push_back(SetCC);
15844 Results.push_back(Store);
15845 return DAG.getMergeValues(Results, dl);
15850 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
15851 SelectionDAG &DAG) const {
15852 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
15853 MFI->setReturnAddressIsTaken(true);
15855 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
15858 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15860 EVT PtrVT = getPointerTy();
15863 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
15864 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
15865 DAG.getSubtarget().getRegisterInfo());
15866 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
15867 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
15868 DAG.getNode(ISD::ADD, dl, PtrVT,
15869 FrameAddr, Offset),
15870 MachinePointerInfo(), false, false, false, 0);
15873 // Just load the return address.
15874 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
15875 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
15876 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
15879 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
15880 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
15881 MFI->setFrameAddressIsTaken(true);
15883 EVT VT = Op.getValueType();
15884 SDLoc dl(Op); // FIXME probably not meaningful
15885 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15886 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
15887 DAG.getSubtarget().getRegisterInfo());
15888 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
15889 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
15890 (FrameReg == X86::EBP && VT == MVT::i32)) &&
15891 "Invalid Frame Register!");
15892 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
15894 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
15895 MachinePointerInfo(),
15896 false, false, false, 0);
15900 // FIXME? Maybe this could be a TableGen attribute on some registers and
15901 // this table could be generated automatically from RegInfo.
15902 unsigned X86TargetLowering::getRegisterByName(const char* RegName,
15904 unsigned Reg = StringSwitch<unsigned>(RegName)
15905 .Case("esp", X86::ESP)
15906 .Case("rsp", X86::RSP)
15910 report_fatal_error("Invalid register name global variable");
15913 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
15914 SelectionDAG &DAG) const {
15915 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
15916 DAG.getSubtarget().getRegisterInfo());
15917 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
15920 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
15921 SDValue Chain = Op.getOperand(0);
15922 SDValue Offset = Op.getOperand(1);
15923 SDValue Handler = Op.getOperand(2);
15926 EVT PtrVT = getPointerTy();
15927 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
15928 DAG.getSubtarget().getRegisterInfo());
15929 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
15930 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
15931 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
15932 "Invalid Frame Register!");
15933 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
15934 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
15936 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
15937 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
15938 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
15939 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
15941 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
15943 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
15944 DAG.getRegister(StoreAddrReg, PtrVT));
15947 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
15948 SelectionDAG &DAG) const {
15950 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
15951 DAG.getVTList(MVT::i32, MVT::Other),
15952 Op.getOperand(0), Op.getOperand(1));
15955 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
15956 SelectionDAG &DAG) const {
15958 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
15959 Op.getOperand(0), Op.getOperand(1));
15962 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
15963 return Op.getOperand(0);
15966 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
15967 SelectionDAG &DAG) const {
15968 SDValue Root = Op.getOperand(0);
15969 SDValue Trmp = Op.getOperand(1); // trampoline
15970 SDValue FPtr = Op.getOperand(2); // nested function
15971 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
15974 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
15975 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
15977 if (Subtarget->is64Bit()) {
15978 SDValue OutChains[6];
15980 // Large code-model.
15981 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
15982 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
15984 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
15985 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
15987 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
15989 // Load the pointer to the nested function into R11.
15990 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
15991 SDValue Addr = Trmp;
15992 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
15993 Addr, MachinePointerInfo(TrmpAddr),
15996 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15997 DAG.getConstant(2, MVT::i64));
15998 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
15999 MachinePointerInfo(TrmpAddr, 2),
16002 // Load the 'nest' parameter value into R10.
16003 // R10 is specified in X86CallingConv.td
16004 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
16005 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16006 DAG.getConstant(10, MVT::i64));
16007 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
16008 Addr, MachinePointerInfo(TrmpAddr, 10),
16011 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16012 DAG.getConstant(12, MVT::i64));
16013 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
16014 MachinePointerInfo(TrmpAddr, 12),
16017 // Jump to the nested function.
16018 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
16019 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16020 DAG.getConstant(20, MVT::i64));
16021 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
16022 Addr, MachinePointerInfo(TrmpAddr, 20),
16025 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
16026 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16027 DAG.getConstant(22, MVT::i64));
16028 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
16029 MachinePointerInfo(TrmpAddr, 22),
16032 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
16034 const Function *Func =
16035 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
16036 CallingConv::ID CC = Func->getCallingConv();
16041 llvm_unreachable("Unsupported calling convention");
16042 case CallingConv::C:
16043 case CallingConv::X86_StdCall: {
16044 // Pass 'nest' parameter in ECX.
16045 // Must be kept in sync with X86CallingConv.td
16046 NestReg = X86::ECX;
16048 // Check that ECX wasn't needed by an 'inreg' parameter.
16049 FunctionType *FTy = Func->getFunctionType();
16050 const AttributeSet &Attrs = Func->getAttributes();
16052 if (!Attrs.isEmpty() && !Func->isVarArg()) {
16053 unsigned InRegCount = 0;
16056 for (FunctionType::param_iterator I = FTy->param_begin(),
16057 E = FTy->param_end(); I != E; ++I, ++Idx)
16058 if (Attrs.hasAttribute(Idx, Attribute::InReg))
16059 // FIXME: should only count parameters that are lowered to integers.
16060 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
16062 if (InRegCount > 2) {
16063 report_fatal_error("Nest register in use - reduce number of inreg"
16069 case CallingConv::X86_FastCall:
16070 case CallingConv::X86_ThisCall:
16071 case CallingConv::Fast:
16072 // Pass 'nest' parameter in EAX.
16073 // Must be kept in sync with X86CallingConv.td
16074 NestReg = X86::EAX;
16078 SDValue OutChains[4];
16079 SDValue Addr, Disp;
16081 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16082 DAG.getConstant(10, MVT::i32));
16083 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
16085 // This is storing the opcode for MOV32ri.
16086 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
16087 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
16088 OutChains[0] = DAG.getStore(Root, dl,
16089 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
16090 Trmp, MachinePointerInfo(TrmpAddr),
16093 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16094 DAG.getConstant(1, MVT::i32));
16095 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
16096 MachinePointerInfo(TrmpAddr, 1),
16099 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
16100 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16101 DAG.getConstant(5, MVT::i32));
16102 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
16103 MachinePointerInfo(TrmpAddr, 5),
16106 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16107 DAG.getConstant(6, MVT::i32));
16108 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
16109 MachinePointerInfo(TrmpAddr, 6),
16112 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
16116 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
16117 SelectionDAG &DAG) const {
16119 The rounding mode is in bits 11:10 of FPSR, and has the following
16121 00 Round to nearest
16126 FLT_ROUNDS, on the other hand, expects the following:
16133 To perform the conversion, we do:
16134 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
16137 MachineFunction &MF = DAG.getMachineFunction();
16138 const TargetMachine &TM = MF.getTarget();
16139 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
16140 unsigned StackAlignment = TFI.getStackAlignment();
16141 MVT VT = Op.getSimpleValueType();
16144 // Save FP Control Word to stack slot
16145 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
16146 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
16148 MachineMemOperand *MMO =
16149 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
16150 MachineMemOperand::MOStore, 2, 2);
16152 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
16153 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
16154 DAG.getVTList(MVT::Other),
16155 Ops, MVT::i16, MMO);
16157 // Load FP Control Word from stack slot
16158 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
16159 MachinePointerInfo(), false, false, false, 0);
16161 // Transform as necessary
16163 DAG.getNode(ISD::SRL, DL, MVT::i16,
16164 DAG.getNode(ISD::AND, DL, MVT::i16,
16165 CWD, DAG.getConstant(0x800, MVT::i16)),
16166 DAG.getConstant(11, MVT::i8));
16168 DAG.getNode(ISD::SRL, DL, MVT::i16,
16169 DAG.getNode(ISD::AND, DL, MVT::i16,
16170 CWD, DAG.getConstant(0x400, MVT::i16)),
16171 DAG.getConstant(9, MVT::i8));
16174 DAG.getNode(ISD::AND, DL, MVT::i16,
16175 DAG.getNode(ISD::ADD, DL, MVT::i16,
16176 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
16177 DAG.getConstant(1, MVT::i16)),
16178 DAG.getConstant(3, MVT::i16));
16180 return DAG.getNode((VT.getSizeInBits() < 16 ?
16181 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
16184 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
16185 MVT VT = Op.getSimpleValueType();
16187 unsigned NumBits = VT.getSizeInBits();
16190 Op = Op.getOperand(0);
16191 if (VT == MVT::i8) {
16192 // Zero extend to i32 since there is not an i8 bsr.
16194 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
16197 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
16198 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
16199 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
16201 // If src is zero (i.e. bsr sets ZF), returns NumBits.
16204 DAG.getConstant(NumBits+NumBits-1, OpVT),
16205 DAG.getConstant(X86::COND_E, MVT::i8),
16208 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
16210 // Finally xor with NumBits-1.
16211 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
16214 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
16218 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
16219 MVT VT = Op.getSimpleValueType();
16221 unsigned NumBits = VT.getSizeInBits();
16224 Op = Op.getOperand(0);
16225 if (VT == MVT::i8) {
16226 // Zero extend to i32 since there is not an i8 bsr.
16228 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
16231 // Issue a bsr (scan bits in reverse).
16232 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
16233 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
16235 // And xor with NumBits-1.
16236 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
16239 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
16243 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
16244 MVT VT = Op.getSimpleValueType();
16245 unsigned NumBits = VT.getSizeInBits();
16247 Op = Op.getOperand(0);
16249 // Issue a bsf (scan bits forward) which also sets EFLAGS.
16250 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
16251 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
16253 // If src is zero (i.e. bsf sets ZF), returns NumBits.
16256 DAG.getConstant(NumBits, VT),
16257 DAG.getConstant(X86::COND_E, MVT::i8),
16260 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
16263 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
16264 // ones, and then concatenate the result back.
16265 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
16266 MVT VT = Op.getSimpleValueType();
16268 assert(VT.is256BitVector() && VT.isInteger() &&
16269 "Unsupported value type for operation");
16271 unsigned NumElems = VT.getVectorNumElements();
16274 // Extract the LHS vectors
16275 SDValue LHS = Op.getOperand(0);
16276 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
16277 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
16279 // Extract the RHS vectors
16280 SDValue RHS = Op.getOperand(1);
16281 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
16282 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
16284 MVT EltVT = VT.getVectorElementType();
16285 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
16287 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
16288 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
16289 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
16292 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
16293 assert(Op.getSimpleValueType().is256BitVector() &&
16294 Op.getSimpleValueType().isInteger() &&
16295 "Only handle AVX 256-bit vector integer operation");
16296 return Lower256IntArith(Op, DAG);
16299 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
16300 assert(Op.getSimpleValueType().is256BitVector() &&
16301 Op.getSimpleValueType().isInteger() &&
16302 "Only handle AVX 256-bit vector integer operation");
16303 return Lower256IntArith(Op, DAG);
16306 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
16307 SelectionDAG &DAG) {
16309 MVT VT = Op.getSimpleValueType();
16311 // Decompose 256-bit ops into smaller 128-bit ops.
16312 if (VT.is256BitVector() && !Subtarget->hasInt256())
16313 return Lower256IntArith(Op, DAG);
16315 SDValue A = Op.getOperand(0);
16316 SDValue B = Op.getOperand(1);
16318 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
16319 if (VT == MVT::v4i32) {
16320 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
16321 "Should not custom lower when pmuldq is available!");
16323 // Extract the odd parts.
16324 static const int UnpackMask[] = { 1, -1, 3, -1 };
16325 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
16326 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
16328 // Multiply the even parts.
16329 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
16330 // Now multiply odd parts.
16331 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
16333 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
16334 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
16336 // Merge the two vectors back together with a shuffle. This expands into 2
16338 static const int ShufMask[] = { 0, 4, 2, 6 };
16339 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
16342 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
16343 "Only know how to lower V2I64/V4I64/V8I64 multiply");
16345 // Ahi = psrlqi(a, 32);
16346 // Bhi = psrlqi(b, 32);
16348 // AloBlo = pmuludq(a, b);
16349 // AloBhi = pmuludq(a, Bhi);
16350 // AhiBlo = pmuludq(Ahi, b);
16352 // AloBhi = psllqi(AloBhi, 32);
16353 // AhiBlo = psllqi(AhiBlo, 32);
16354 // return AloBlo + AloBhi + AhiBlo;
16356 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
16357 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
16359 // Bit cast to 32-bit vectors for MULUDQ
16360 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
16361 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
16362 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
16363 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
16364 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
16365 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
16367 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
16368 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
16369 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
16371 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
16372 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
16374 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
16375 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
16378 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
16379 assert(Subtarget->isTargetWin64() && "Unexpected target");
16380 EVT VT = Op.getValueType();
16381 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
16382 "Unexpected return type for lowering");
16386 switch (Op->getOpcode()) {
16387 default: llvm_unreachable("Unexpected request for libcall!");
16388 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
16389 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
16390 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
16391 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
16392 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
16393 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
16397 SDValue InChain = DAG.getEntryNode();
16399 TargetLowering::ArgListTy Args;
16400 TargetLowering::ArgListEntry Entry;
16401 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
16402 EVT ArgVT = Op->getOperand(i).getValueType();
16403 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
16404 "Unexpected argument type for lowering");
16405 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
16406 Entry.Node = StackPtr;
16407 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
16409 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
16410 Entry.Ty = PointerType::get(ArgTy,0);
16411 Entry.isSExt = false;
16412 Entry.isZExt = false;
16413 Args.push_back(Entry);
16416 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
16419 TargetLowering::CallLoweringInfo CLI(DAG);
16420 CLI.setDebugLoc(dl).setChain(InChain)
16421 .setCallee(getLibcallCallingConv(LC),
16422 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
16423 Callee, std::move(Args), 0)
16424 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
16426 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
16427 return DAG.getNode(ISD::BITCAST, dl, VT, CallInfo.first);
16430 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
16431 SelectionDAG &DAG) {
16432 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
16433 EVT VT = Op0.getValueType();
16436 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
16437 (VT == MVT::v8i32 && Subtarget->hasInt256()));
16439 // PMULxD operations multiply each even value (starting at 0) of LHS with
16440 // the related value of RHS and produce a widen result.
16441 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
16442 // => <2 x i64> <ae|cg>
16444 // In other word, to have all the results, we need to perform two PMULxD:
16445 // 1. one with the even values.
16446 // 2. one with the odd values.
16447 // To achieve #2, with need to place the odd values at an even position.
16449 // Place the odd value at an even position (basically, shift all values 1
16450 // step to the left):
16451 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
16452 // <a|b|c|d> => <b|undef|d|undef>
16453 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
16454 // <e|f|g|h> => <f|undef|h|undef>
16455 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
16457 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
16459 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
16460 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
16462 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
16463 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
16464 // => <2 x i64> <ae|cg>
16465 SDValue Mul1 = DAG.getNode(ISD::BITCAST, dl, VT,
16466 DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
16467 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
16468 // => <2 x i64> <bf|dh>
16469 SDValue Mul2 = DAG.getNode(ISD::BITCAST, dl, VT,
16470 DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
16472 // Shuffle it back into the right order.
16473 SDValue Highs, Lows;
16474 if (VT == MVT::v8i32) {
16475 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
16476 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
16477 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
16478 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
16480 const int HighMask[] = {1, 5, 3, 7};
16481 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
16482 const int LowMask[] = {0, 4, 2, 6};
16483 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
16486 // If we have a signed multiply but no PMULDQ fix up the high parts of a
16487 // unsigned multiply.
16488 if (IsSigned && !Subtarget->hasSSE41()) {
16490 DAG.getConstant(31, DAG.getTargetLoweringInfo().getShiftAmountTy(VT));
16491 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
16492 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
16493 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
16494 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
16496 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
16497 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
16500 // The first result of MUL_LOHI is actually the low value, followed by the
16502 SDValue Ops[] = {Lows, Highs};
16503 return DAG.getMergeValues(Ops, dl);
16506 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
16507 const X86Subtarget *Subtarget) {
16508 MVT VT = Op.getSimpleValueType();
16510 SDValue R = Op.getOperand(0);
16511 SDValue Amt = Op.getOperand(1);
16513 // Optimize shl/srl/sra with constant shift amount.
16514 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
16515 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
16516 uint64_t ShiftAmt = ShiftConst->getZExtValue();
16518 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
16519 (Subtarget->hasInt256() &&
16520 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16)) ||
16521 (Subtarget->hasAVX512() &&
16522 (VT == MVT::v8i64 || VT == MVT::v16i32))) {
16523 if (Op.getOpcode() == ISD::SHL)
16524 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
16526 if (Op.getOpcode() == ISD::SRL)
16527 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
16529 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
16530 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
16534 if (VT == MVT::v16i8) {
16535 if (Op.getOpcode() == ISD::SHL) {
16536 // Make a large shift.
16537 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
16538 MVT::v8i16, R, ShiftAmt,
16540 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
16541 // Zero out the rightmost bits.
16542 SmallVector<SDValue, 16> V(16,
16543 DAG.getConstant(uint8_t(-1U << ShiftAmt),
16545 return DAG.getNode(ISD::AND, dl, VT, SHL,
16546 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
16548 if (Op.getOpcode() == ISD::SRL) {
16549 // Make a large shift.
16550 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
16551 MVT::v8i16, R, ShiftAmt,
16553 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
16554 // Zero out the leftmost bits.
16555 SmallVector<SDValue, 16> V(16,
16556 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
16558 return DAG.getNode(ISD::AND, dl, VT, SRL,
16559 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
16561 if (Op.getOpcode() == ISD::SRA) {
16562 if (ShiftAmt == 7) {
16563 // R s>> 7 === R s< 0
16564 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
16565 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
16568 // R s>> a === ((R u>> a) ^ m) - m
16569 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
16570 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
16572 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
16573 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
16574 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
16577 llvm_unreachable("Unknown shift opcode.");
16580 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
16581 if (Op.getOpcode() == ISD::SHL) {
16582 // Make a large shift.
16583 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
16584 MVT::v16i16, R, ShiftAmt,
16586 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
16587 // Zero out the rightmost bits.
16588 SmallVector<SDValue, 32> V(32,
16589 DAG.getConstant(uint8_t(-1U << ShiftAmt),
16591 return DAG.getNode(ISD::AND, dl, VT, SHL,
16592 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
16594 if (Op.getOpcode() == ISD::SRL) {
16595 // Make a large shift.
16596 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
16597 MVT::v16i16, R, ShiftAmt,
16599 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
16600 // Zero out the leftmost bits.
16601 SmallVector<SDValue, 32> V(32,
16602 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
16604 return DAG.getNode(ISD::AND, dl, VT, SRL,
16605 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
16607 if (Op.getOpcode() == ISD::SRA) {
16608 if (ShiftAmt == 7) {
16609 // R s>> 7 === R s< 0
16610 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
16611 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
16614 // R s>> a === ((R u>> a) ^ m) - m
16615 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
16616 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
16618 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
16619 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
16620 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
16623 llvm_unreachable("Unknown shift opcode.");
16628 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
16629 if (!Subtarget->is64Bit() &&
16630 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
16631 Amt.getOpcode() == ISD::BITCAST &&
16632 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
16633 Amt = Amt.getOperand(0);
16634 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
16635 VT.getVectorNumElements();
16636 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
16637 uint64_t ShiftAmt = 0;
16638 for (unsigned i = 0; i != Ratio; ++i) {
16639 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
16643 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
16645 // Check remaining shift amounts.
16646 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
16647 uint64_t ShAmt = 0;
16648 for (unsigned j = 0; j != Ratio; ++j) {
16649 ConstantSDNode *C =
16650 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
16654 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
16656 if (ShAmt != ShiftAmt)
16659 switch (Op.getOpcode()) {
16661 llvm_unreachable("Unknown shift opcode!");
16663 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
16666 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
16669 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
16677 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
16678 const X86Subtarget* Subtarget) {
16679 MVT VT = Op.getSimpleValueType();
16681 SDValue R = Op.getOperand(0);
16682 SDValue Amt = Op.getOperand(1);
16684 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
16685 VT == MVT::v4i32 || VT == MVT::v8i16 ||
16686 (Subtarget->hasInt256() &&
16687 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
16688 VT == MVT::v8i32 || VT == MVT::v16i16)) ||
16689 (Subtarget->hasAVX512() && (VT == MVT::v8i64 || VT == MVT::v16i32))) {
16691 EVT EltVT = VT.getVectorElementType();
16693 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
16694 unsigned NumElts = VT.getVectorNumElements();
16696 for (i = 0; i != NumElts; ++i) {
16697 if (Amt.getOperand(i).getOpcode() == ISD::UNDEF)
16701 for (j = i; j != NumElts; ++j) {
16702 SDValue Arg = Amt.getOperand(j);
16703 if (Arg.getOpcode() == ISD::UNDEF) continue;
16704 if (Arg != Amt.getOperand(i))
16707 if (i != NumElts && j == NumElts)
16708 BaseShAmt = Amt.getOperand(i);
16710 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
16711 Amt = Amt.getOperand(0);
16712 if (Amt.getOpcode() == ISD::VECTOR_SHUFFLE &&
16713 cast<ShuffleVectorSDNode>(Amt)->isSplat()) {
16714 SDValue InVec = Amt.getOperand(0);
16715 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
16716 unsigned NumElts = InVec.getValueType().getVectorNumElements();
16718 for (; i != NumElts; ++i) {
16719 SDValue Arg = InVec.getOperand(i);
16720 if (Arg.getOpcode() == ISD::UNDEF) continue;
16724 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
16725 if (ConstantSDNode *C =
16726 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
16727 unsigned SplatIdx =
16728 cast<ShuffleVectorSDNode>(Amt)->getSplatIndex();
16729 if (C->getZExtValue() == SplatIdx)
16730 BaseShAmt = InVec.getOperand(1);
16733 if (!BaseShAmt.getNode())
16734 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Amt,
16735 DAG.getIntPtrConstant(0));
16739 if (BaseShAmt.getNode()) {
16740 if (EltVT.bitsGT(MVT::i32))
16741 BaseShAmt = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BaseShAmt);
16742 else if (EltVT.bitsLT(MVT::i32))
16743 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
16745 switch (Op.getOpcode()) {
16747 llvm_unreachable("Unknown shift opcode!");
16749 switch (VT.SimpleTy) {
16750 default: return SDValue();
16759 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
16762 switch (VT.SimpleTy) {
16763 default: return SDValue();
16770 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
16773 switch (VT.SimpleTy) {
16774 default: return SDValue();
16783 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);
16789 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
16790 if (!Subtarget->is64Bit() &&
16791 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64) ||
16792 (Subtarget->hasAVX512() && VT == MVT::v8i64)) &&
16793 Amt.getOpcode() == ISD::BITCAST &&
16794 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
16795 Amt = Amt.getOperand(0);
16796 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
16797 VT.getVectorNumElements();
16798 std::vector<SDValue> Vals(Ratio);
16799 for (unsigned i = 0; i != Ratio; ++i)
16800 Vals[i] = Amt.getOperand(i);
16801 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
16802 for (unsigned j = 0; j != Ratio; ++j)
16803 if (Vals[j] != Amt.getOperand(i + j))
16806 switch (Op.getOpcode()) {
16808 llvm_unreachable("Unknown shift opcode!");
16810 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1));
16812 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1));
16814 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1));
16821 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
16822 SelectionDAG &DAG) {
16823 MVT VT = Op.getSimpleValueType();
16825 SDValue R = Op.getOperand(0);
16826 SDValue Amt = Op.getOperand(1);
16829 assert(VT.isVector() && "Custom lowering only for vector shifts!");
16830 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
16832 V = LowerScalarImmediateShift(Op, DAG, Subtarget);
16836 V = LowerScalarVariableShift(Op, DAG, Subtarget);
16840 if (Subtarget->hasAVX512() && (VT == MVT::v16i32 || VT == MVT::v8i64))
16842 // AVX2 has VPSLLV/VPSRAV/VPSRLV.
16843 if (Subtarget->hasInt256()) {
16844 if (Op.getOpcode() == ISD::SRL &&
16845 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
16846 VT == MVT::v4i64 || VT == MVT::v8i32))
16848 if (Op.getOpcode() == ISD::SHL &&
16849 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
16850 VT == MVT::v4i64 || VT == MVT::v8i32))
16852 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
16856 // If possible, lower this packed shift into a vector multiply instead of
16857 // expanding it into a sequence of scalar shifts.
16858 // Do this only if the vector shift count is a constant build_vector.
16859 if (Op.getOpcode() == ISD::SHL &&
16860 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
16861 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
16862 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
16863 SmallVector<SDValue, 8> Elts;
16864 EVT SVT = VT.getScalarType();
16865 unsigned SVTBits = SVT.getSizeInBits();
16866 const APInt &One = APInt(SVTBits, 1);
16867 unsigned NumElems = VT.getVectorNumElements();
16869 for (unsigned i=0; i !=NumElems; ++i) {
16870 SDValue Op = Amt->getOperand(i);
16871 if (Op->getOpcode() == ISD::UNDEF) {
16872 Elts.push_back(Op);
16876 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
16877 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
16878 uint64_t ShAmt = C.getZExtValue();
16879 if (ShAmt >= SVTBits) {
16880 Elts.push_back(DAG.getUNDEF(SVT));
16883 Elts.push_back(DAG.getConstant(One.shl(ShAmt), SVT));
16885 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
16886 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
16889 // Lower SHL with variable shift amount.
16890 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
16891 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
16893 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
16894 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
16895 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
16896 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
16899 // If possible, lower this shift as a sequence of two shifts by
16900 // constant plus a MOVSS/MOVSD instead of scalarizing it.
16902 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
16904 // Could be rewritten as:
16905 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
16907 // The advantage is that the two shifts from the example would be
16908 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
16909 // the vector shift into four scalar shifts plus four pairs of vector
16911 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
16912 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
16913 unsigned TargetOpcode = X86ISD::MOVSS;
16914 bool CanBeSimplified;
16915 // The splat value for the first packed shift (the 'X' from the example).
16916 SDValue Amt1 = Amt->getOperand(0);
16917 // The splat value for the second packed shift (the 'Y' from the example).
16918 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
16919 Amt->getOperand(2);
16921 // See if it is possible to replace this node with a sequence of
16922 // two shifts followed by a MOVSS/MOVSD
16923 if (VT == MVT::v4i32) {
16924 // Check if it is legal to use a MOVSS.
16925 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
16926 Amt2 == Amt->getOperand(3);
16927 if (!CanBeSimplified) {
16928 // Otherwise, check if we can still simplify this node using a MOVSD.
16929 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
16930 Amt->getOperand(2) == Amt->getOperand(3);
16931 TargetOpcode = X86ISD::MOVSD;
16932 Amt2 = Amt->getOperand(2);
16935 // Do similar checks for the case where the machine value type
16937 CanBeSimplified = Amt1 == Amt->getOperand(1);
16938 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
16939 CanBeSimplified = Amt2 == Amt->getOperand(i);
16941 if (!CanBeSimplified) {
16942 TargetOpcode = X86ISD::MOVSD;
16943 CanBeSimplified = true;
16944 Amt2 = Amt->getOperand(4);
16945 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
16946 CanBeSimplified = Amt1 == Amt->getOperand(i);
16947 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
16948 CanBeSimplified = Amt2 == Amt->getOperand(j);
16952 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
16953 isa<ConstantSDNode>(Amt2)) {
16954 // Replace this node with two shifts followed by a MOVSS/MOVSD.
16955 EVT CastVT = MVT::v4i32;
16957 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), VT);
16958 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
16960 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), VT);
16961 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
16962 if (TargetOpcode == X86ISD::MOVSD)
16963 CastVT = MVT::v2i64;
16964 SDValue BitCast1 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift1);
16965 SDValue BitCast2 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift2);
16966 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
16968 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
16972 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
16973 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
16976 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
16977 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
16979 // Turn 'a' into a mask suitable for VSELECT
16980 SDValue VSelM = DAG.getConstant(0x80, VT);
16981 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
16982 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
16984 SDValue CM1 = DAG.getConstant(0x0f, VT);
16985 SDValue CM2 = DAG.getConstant(0x3f, VT);
16987 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
16988 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
16989 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 4, DAG);
16990 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
16991 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
16994 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
16995 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
16996 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
16998 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
16999 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
17000 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 2, DAG);
17001 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
17002 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
17005 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
17006 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
17007 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
17009 // return VSELECT(r, r+r, a);
17010 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
17011 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
17015 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
17016 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
17017 // solution better.
17018 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
17019 MVT NewVT = VT == MVT::v8i16 ? MVT::v8i32 : MVT::v16i16;
17021 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
17022 R = DAG.getNode(ExtOpc, dl, NewVT, R);
17023 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, NewVT, Amt);
17024 return DAG.getNode(ISD::TRUNCATE, dl, VT,
17025 DAG.getNode(Op.getOpcode(), dl, NewVT, R, Amt));
17028 // Decompose 256-bit shifts into smaller 128-bit shifts.
17029 if (VT.is256BitVector()) {
17030 unsigned NumElems = VT.getVectorNumElements();
17031 MVT EltVT = VT.getVectorElementType();
17032 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
17034 // Extract the two vectors
17035 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
17036 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
17038 // Recreate the shift amount vectors
17039 SDValue Amt1, Amt2;
17040 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
17041 // Constant shift amount
17042 SmallVector<SDValue, 4> Amt1Csts;
17043 SmallVector<SDValue, 4> Amt2Csts;
17044 for (unsigned i = 0; i != NumElems/2; ++i)
17045 Amt1Csts.push_back(Amt->getOperand(i));
17046 for (unsigned i = NumElems/2; i != NumElems; ++i)
17047 Amt2Csts.push_back(Amt->getOperand(i));
17049 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
17050 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
17052 // Variable shift amount
17053 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
17054 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
17057 // Issue new vector shifts for the smaller types
17058 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
17059 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
17061 // Concatenate the result back
17062 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
17068 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
17069 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
17070 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
17071 // looks for this combo and may remove the "setcc" instruction if the "setcc"
17072 // has only one use.
17073 SDNode *N = Op.getNode();
17074 SDValue LHS = N->getOperand(0);
17075 SDValue RHS = N->getOperand(1);
17076 unsigned BaseOp = 0;
17079 switch (Op.getOpcode()) {
17080 default: llvm_unreachable("Unknown ovf instruction!");
17082 // A subtract of one will be selected as a INC. Note that INC doesn't
17083 // set CF, so we can't do this for UADDO.
17084 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
17086 BaseOp = X86ISD::INC;
17087 Cond = X86::COND_O;
17090 BaseOp = X86ISD::ADD;
17091 Cond = X86::COND_O;
17094 BaseOp = X86ISD::ADD;
17095 Cond = X86::COND_B;
17098 // A subtract of one will be selected as a DEC. Note that DEC doesn't
17099 // set CF, so we can't do this for USUBO.
17100 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
17102 BaseOp = X86ISD::DEC;
17103 Cond = X86::COND_O;
17106 BaseOp = X86ISD::SUB;
17107 Cond = X86::COND_O;
17110 BaseOp = X86ISD::SUB;
17111 Cond = X86::COND_B;
17114 BaseOp = X86ISD::SMUL;
17115 Cond = X86::COND_O;
17117 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
17118 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
17120 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
17123 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
17124 DAG.getConstant(X86::COND_O, MVT::i32),
17125 SDValue(Sum.getNode(), 2));
17127 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
17131 // Also sets EFLAGS.
17132 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
17133 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
17136 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
17137 DAG.getConstant(Cond, MVT::i32),
17138 SDValue(Sum.getNode(), 1));
17140 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
17143 // Sign extension of the low part of vector elements. This may be used either
17144 // when sign extend instructions are not available or if the vector element
17145 // sizes already match the sign-extended size. If the vector elements are in
17146 // their pre-extended size and sign extend instructions are available, that will
17147 // be handled by LowerSIGN_EXTEND.
17148 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
17149 SelectionDAG &DAG) const {
17151 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
17152 MVT VT = Op.getSimpleValueType();
17154 if (!Subtarget->hasSSE2() || !VT.isVector())
17157 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
17158 ExtraVT.getScalarType().getSizeInBits();
17160 switch (VT.SimpleTy) {
17161 default: return SDValue();
17164 if (!Subtarget->hasFp256())
17166 if (!Subtarget->hasInt256()) {
17167 // needs to be split
17168 unsigned NumElems = VT.getVectorNumElements();
17170 // Extract the LHS vectors
17171 SDValue LHS = Op.getOperand(0);
17172 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
17173 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
17175 MVT EltVT = VT.getVectorElementType();
17176 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
17178 EVT ExtraEltVT = ExtraVT.getVectorElementType();
17179 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
17180 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
17182 SDValue Extra = DAG.getValueType(ExtraVT);
17184 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
17185 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
17187 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
17192 SDValue Op0 = Op.getOperand(0);
17194 // This is a sign extension of some low part of vector elements without
17195 // changing the size of the vector elements themselves:
17196 // Shift-Left + Shift-Right-Algebraic.
17197 SDValue Shl = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, Op0,
17199 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, Shl, BitsDiff,
17205 /// Returns true if the operand type is exactly twice the native width, and
17206 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
17207 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
17208 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
17209 bool X86TargetLowering::needsCmpXchgNb(const Type *MemType) const {
17210 const X86Subtarget &Subtarget =
17211 getTargetMachine().getSubtarget<X86Subtarget>();
17212 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
17215 return !Subtarget.is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
17216 else if (OpWidth == 128)
17217 return Subtarget.hasCmpxchg16b();
17222 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
17223 return needsCmpXchgNb(SI->getValueOperand()->getType());
17226 bool X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *SI) const {
17227 return false; // FIXME, currently these are expanded separately in this file.
17230 bool X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
17231 const X86Subtarget &Subtarget =
17232 getTargetMachine().getSubtarget<X86Subtarget>();
17233 unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;
17234 const Type *MemType = AI->getType();
17236 // If the operand is too big, we must see if cmpxchg8/16b is available
17237 // and default to library calls otherwise.
17238 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
17239 return needsCmpXchgNb(MemType);
17241 AtomicRMWInst::BinOp Op = AI->getOperation();
17244 llvm_unreachable("Unknown atomic operation");
17245 case AtomicRMWInst::Xchg:
17246 case AtomicRMWInst::Add:
17247 case AtomicRMWInst::Sub:
17248 // It's better to use xadd, xsub or xchg for these in all cases.
17250 case AtomicRMWInst::Or:
17251 case AtomicRMWInst::And:
17252 case AtomicRMWInst::Xor:
17253 // If the atomicrmw's result isn't actually used, we can just add a "lock"
17254 // prefix to a normal instruction for these operations.
17255 return !AI->use_empty();
17256 case AtomicRMWInst::Nand:
17257 case AtomicRMWInst::Max:
17258 case AtomicRMWInst::Min:
17259 case AtomicRMWInst::UMax:
17260 case AtomicRMWInst::UMin:
17261 // These always require a non-trivial set of data operations on x86. We must
17262 // use a cmpxchg loop.
17267 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
17268 SelectionDAG &DAG) {
17270 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
17271 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
17272 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
17273 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
17275 // The only fence that needs an instruction is a sequentially-consistent
17276 // cross-thread fence.
17277 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
17278 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
17279 // no-sse2). There isn't any reason to disable it if the target processor
17281 if (Subtarget->hasSSE2() || Subtarget->is64Bit())
17282 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
17284 SDValue Chain = Op.getOperand(0);
17285 SDValue Zero = DAG.getConstant(0, MVT::i32);
17287 DAG.getRegister(X86::ESP, MVT::i32), // Base
17288 DAG.getTargetConstant(1, MVT::i8), // Scale
17289 DAG.getRegister(0, MVT::i32), // Index
17290 DAG.getTargetConstant(0, MVT::i32), // Disp
17291 DAG.getRegister(0, MVT::i32), // Segment.
17295 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
17296 return SDValue(Res, 0);
17299 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
17300 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
17303 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
17304 SelectionDAG &DAG) {
17305 MVT T = Op.getSimpleValueType();
17309 switch(T.SimpleTy) {
17310 default: llvm_unreachable("Invalid value type!");
17311 case MVT::i8: Reg = X86::AL; size = 1; break;
17312 case MVT::i16: Reg = X86::AX; size = 2; break;
17313 case MVT::i32: Reg = X86::EAX; size = 4; break;
17315 assert(Subtarget->is64Bit() && "Node not type legal!");
17316 Reg = X86::RAX; size = 8;
17319 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
17320 Op.getOperand(2), SDValue());
17321 SDValue Ops[] = { cpIn.getValue(0),
17324 DAG.getTargetConstant(size, MVT::i8),
17325 cpIn.getValue(1) };
17326 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17327 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
17328 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
17332 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
17333 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
17334 MVT::i32, cpOut.getValue(2));
17335 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
17336 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
17338 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
17339 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
17340 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
17344 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
17345 SelectionDAG &DAG) {
17346 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
17347 MVT DstVT = Op.getSimpleValueType();
17349 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
17350 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
17351 if (DstVT != MVT::f64)
17352 // This conversion needs to be expanded.
17355 SDValue InVec = Op->getOperand(0);
17357 unsigned NumElts = SrcVT.getVectorNumElements();
17358 EVT SVT = SrcVT.getVectorElementType();
17360 // Widen the vector in input in the case of MVT::v2i32.
17361 // Example: from MVT::v2i32 to MVT::v4i32.
17362 SmallVector<SDValue, 16> Elts;
17363 for (unsigned i = 0, e = NumElts; i != e; ++i)
17364 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
17365 DAG.getIntPtrConstant(i)));
17367 // Explicitly mark the extra elements as Undef.
17368 SDValue Undef = DAG.getUNDEF(SVT);
17369 for (unsigned i = NumElts, e = NumElts * 2; i != e; ++i)
17370 Elts.push_back(Undef);
17372 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
17373 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
17374 SDValue ToV2F64 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, BV);
17375 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
17376 DAG.getIntPtrConstant(0));
17379 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
17380 Subtarget->hasMMX() && "Unexpected custom BITCAST");
17381 assert((DstVT == MVT::i64 ||
17382 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
17383 "Unexpected custom BITCAST");
17384 // i64 <=> MMX conversions are Legal.
17385 if (SrcVT==MVT::i64 && DstVT.isVector())
17387 if (DstVT==MVT::i64 && SrcVT.isVector())
17389 // MMX <=> MMX conversions are Legal.
17390 if (SrcVT.isVector() && DstVT.isVector())
17392 // All other conversions need to be expanded.
17396 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
17397 SDNode *Node = Op.getNode();
17399 EVT T = Node->getValueType(0);
17400 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
17401 DAG.getConstant(0, T), Node->getOperand(2));
17402 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
17403 cast<AtomicSDNode>(Node)->getMemoryVT(),
17404 Node->getOperand(0),
17405 Node->getOperand(1), negOp,
17406 cast<AtomicSDNode>(Node)->getMemOperand(),
17407 cast<AtomicSDNode>(Node)->getOrdering(),
17408 cast<AtomicSDNode>(Node)->getSynchScope());
17411 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
17412 SDNode *Node = Op.getNode();
17414 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
17416 // Convert seq_cst store -> xchg
17417 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
17418 // FIXME: On 32-bit, store -> fist or movq would be more efficient
17419 // (The only way to get a 16-byte store is cmpxchg16b)
17420 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
17421 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
17422 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
17423 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
17424 cast<AtomicSDNode>(Node)->getMemoryVT(),
17425 Node->getOperand(0),
17426 Node->getOperand(1), Node->getOperand(2),
17427 cast<AtomicSDNode>(Node)->getMemOperand(),
17428 cast<AtomicSDNode>(Node)->getOrdering(),
17429 cast<AtomicSDNode>(Node)->getSynchScope());
17430 return Swap.getValue(1);
17432 // Other atomic stores have a simple pattern.
17436 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
17437 EVT VT = Op.getNode()->getSimpleValueType(0);
17439 // Let legalize expand this if it isn't a legal type yet.
17440 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
17443 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
17446 bool ExtraOp = false;
17447 switch (Op.getOpcode()) {
17448 default: llvm_unreachable("Invalid code");
17449 case ISD::ADDC: Opc = X86ISD::ADD; break;
17450 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
17451 case ISD::SUBC: Opc = X86ISD::SUB; break;
17452 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
17456 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
17458 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
17459 Op.getOperand(1), Op.getOperand(2));
17462 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
17463 SelectionDAG &DAG) {
17464 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
17466 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
17467 // which returns the values as { float, float } (in XMM0) or
17468 // { double, double } (which is returned in XMM0, XMM1).
17470 SDValue Arg = Op.getOperand(0);
17471 EVT ArgVT = Arg.getValueType();
17472 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
17474 TargetLowering::ArgListTy Args;
17475 TargetLowering::ArgListEntry Entry;
17479 Entry.isSExt = false;
17480 Entry.isZExt = false;
17481 Args.push_back(Entry);
17483 bool isF64 = ArgVT == MVT::f64;
17484 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
17485 // the small struct {f32, f32} is returned in (eax, edx). For f64,
17486 // the results are returned via SRet in memory.
17487 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
17488 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17489 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
17491 Type *RetTy = isF64
17492 ? (Type*)StructType::get(ArgTy, ArgTy, NULL)
17493 : (Type*)VectorType::get(ArgTy, 4);
17495 TargetLowering::CallLoweringInfo CLI(DAG);
17496 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
17497 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
17499 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
17502 // Returned in xmm0 and xmm1.
17503 return CallResult.first;
17505 // Returned in bits 0:31 and 32:64 xmm0.
17506 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
17507 CallResult.first, DAG.getIntPtrConstant(0));
17508 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
17509 CallResult.first, DAG.getIntPtrConstant(1));
17510 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
17511 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
17514 /// LowerOperation - Provide custom lowering hooks for some operations.
17516 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
17517 switch (Op.getOpcode()) {
17518 default: llvm_unreachable("Should not custom lower this!");
17519 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
17520 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
17521 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
17522 return LowerCMP_SWAP(Op, Subtarget, DAG);
17523 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
17524 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
17525 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
17526 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
17527 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
17528 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
17529 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
17530 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
17531 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
17532 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
17533 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
17534 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
17535 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
17536 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
17537 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
17538 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
17539 case ISD::SHL_PARTS:
17540 case ISD::SRA_PARTS:
17541 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
17542 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
17543 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
17544 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
17545 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
17546 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
17547 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
17548 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
17549 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
17550 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
17551 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
17553 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
17554 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
17555 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
17556 case ISD::SETCC: return LowerSETCC(Op, DAG);
17557 case ISD::SELECT: return LowerSELECT(Op, DAG);
17558 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
17559 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
17560 case ISD::VASTART: return LowerVASTART(Op, DAG);
17561 case ISD::VAARG: return LowerVAARG(Op, DAG);
17562 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
17563 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
17564 case ISD::INTRINSIC_VOID:
17565 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
17566 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
17567 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
17568 case ISD::FRAME_TO_ARGS_OFFSET:
17569 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
17570 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
17571 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
17572 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
17573 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
17574 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
17575 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
17576 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
17577 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
17578 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
17579 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
17580 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
17581 case ISD::UMUL_LOHI:
17582 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
17585 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
17591 case ISD::UMULO: return LowerXALUO(Op, DAG);
17592 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
17593 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
17597 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
17598 case ISD::ADD: return LowerADD(Op, DAG);
17599 case ISD::SUB: return LowerSUB(Op, DAG);
17600 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
17604 static void ReplaceATOMIC_LOAD(SDNode *Node,
17605 SmallVectorImpl<SDValue> &Results,
17606 SelectionDAG &DAG) {
17608 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
17610 // Convert wide load -> cmpxchg8b/cmpxchg16b
17611 // FIXME: On 32-bit, load -> fild or movq would be more efficient
17612 // (The only way to get a 16-byte load is cmpxchg16b)
17613 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment.
17614 SDValue Zero = DAG.getConstant(0, VT);
17615 SDVTList VTs = DAG.getVTList(VT, MVT::i1, MVT::Other);
17617 DAG.getAtomicCmpSwap(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl, VT, VTs,
17618 Node->getOperand(0), Node->getOperand(1), Zero, Zero,
17619 cast<AtomicSDNode>(Node)->getMemOperand(),
17620 cast<AtomicSDNode>(Node)->getOrdering(),
17621 cast<AtomicSDNode>(Node)->getOrdering(),
17622 cast<AtomicSDNode>(Node)->getSynchScope());
17623 Results.push_back(Swap.getValue(0));
17624 Results.push_back(Swap.getValue(2));
17627 /// ReplaceNodeResults - Replace a node with an illegal result type
17628 /// with a new node built out of custom code.
17629 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
17630 SmallVectorImpl<SDValue>&Results,
17631 SelectionDAG &DAG) const {
17633 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17634 switch (N->getOpcode()) {
17636 llvm_unreachable("Do not know how to custom type legalize this operation!");
17637 case ISD::SIGN_EXTEND_INREG:
17642 // We don't want to expand or promote these.
17649 case ISD::UDIVREM: {
17650 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
17651 Results.push_back(V);
17654 case ISD::FP_TO_SINT:
17655 case ISD::FP_TO_UINT: {
17656 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
17658 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
17661 std::pair<SDValue,SDValue> Vals =
17662 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
17663 SDValue FIST = Vals.first, StackSlot = Vals.second;
17664 if (FIST.getNode()) {
17665 EVT VT = N->getValueType(0);
17666 // Return a load from the stack slot.
17667 if (StackSlot.getNode())
17668 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
17669 MachinePointerInfo(),
17670 false, false, false, 0));
17672 Results.push_back(FIST);
17676 case ISD::UINT_TO_FP: {
17677 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
17678 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
17679 N->getValueType(0) != MVT::v2f32)
17681 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
17683 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
17685 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
17686 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
17687 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
17688 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
17689 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
17690 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
17693 case ISD::FP_ROUND: {
17694 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
17696 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
17697 Results.push_back(V);
17700 case ISD::INTRINSIC_W_CHAIN: {
17701 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
17703 default : llvm_unreachable("Do not know how to custom type "
17704 "legalize this intrinsic operation!");
17705 case Intrinsic::x86_rdtsc:
17706 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
17708 case Intrinsic::x86_rdtscp:
17709 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
17711 case Intrinsic::x86_rdpmc:
17712 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
17715 case ISD::READCYCLECOUNTER: {
17716 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
17719 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
17720 EVT T = N->getValueType(0);
17721 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
17722 bool Regs64bit = T == MVT::i128;
17723 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
17724 SDValue cpInL, cpInH;
17725 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
17726 DAG.getConstant(0, HalfT));
17727 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
17728 DAG.getConstant(1, HalfT));
17729 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
17730 Regs64bit ? X86::RAX : X86::EAX,
17732 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
17733 Regs64bit ? X86::RDX : X86::EDX,
17734 cpInH, cpInL.getValue(1));
17735 SDValue swapInL, swapInH;
17736 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
17737 DAG.getConstant(0, HalfT));
17738 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
17739 DAG.getConstant(1, HalfT));
17740 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
17741 Regs64bit ? X86::RBX : X86::EBX,
17742 swapInL, cpInH.getValue(1));
17743 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
17744 Regs64bit ? X86::RCX : X86::ECX,
17745 swapInH, swapInL.getValue(1));
17746 SDValue Ops[] = { swapInH.getValue(0),
17748 swapInH.getValue(1) };
17749 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17750 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
17751 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
17752 X86ISD::LCMPXCHG8_DAG;
17753 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
17754 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
17755 Regs64bit ? X86::RAX : X86::EAX,
17756 HalfT, Result.getValue(1));
17757 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
17758 Regs64bit ? X86::RDX : X86::EDX,
17759 HalfT, cpOutL.getValue(2));
17760 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
17762 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
17763 MVT::i32, cpOutH.getValue(2));
17765 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17766 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
17767 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
17769 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
17770 Results.push_back(Success);
17771 Results.push_back(EFLAGS.getValue(1));
17774 case ISD::ATOMIC_SWAP:
17775 case ISD::ATOMIC_LOAD_ADD:
17776 case ISD::ATOMIC_LOAD_SUB:
17777 case ISD::ATOMIC_LOAD_AND:
17778 case ISD::ATOMIC_LOAD_OR:
17779 case ISD::ATOMIC_LOAD_XOR:
17780 case ISD::ATOMIC_LOAD_NAND:
17781 case ISD::ATOMIC_LOAD_MIN:
17782 case ISD::ATOMIC_LOAD_MAX:
17783 case ISD::ATOMIC_LOAD_UMIN:
17784 case ISD::ATOMIC_LOAD_UMAX:
17785 // Delegate to generic TypeLegalization. Situations we can really handle
17786 // should have already been dealt with by AtomicExpandPass.cpp.
17788 case ISD::ATOMIC_LOAD: {
17789 ReplaceATOMIC_LOAD(N, Results, DAG);
17792 case ISD::BITCAST: {
17793 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
17794 EVT DstVT = N->getValueType(0);
17795 EVT SrcVT = N->getOperand(0)->getValueType(0);
17797 if (SrcVT != MVT::f64 ||
17798 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
17801 unsigned NumElts = DstVT.getVectorNumElements();
17802 EVT SVT = DstVT.getVectorElementType();
17803 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
17804 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
17805 MVT::v2f64, N->getOperand(0));
17806 SDValue ToVecInt = DAG.getNode(ISD::BITCAST, dl, WiderVT, Expanded);
17808 if (ExperimentalVectorWideningLegalization) {
17809 // If we are legalizing vectors by widening, we already have the desired
17810 // legal vector type, just return it.
17811 Results.push_back(ToVecInt);
17815 SmallVector<SDValue, 8> Elts;
17816 for (unsigned i = 0, e = NumElts; i != e; ++i)
17817 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
17818 ToVecInt, DAG.getIntPtrConstant(i)));
17820 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
17825 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
17827 default: return nullptr;
17828 case X86ISD::BSF: return "X86ISD::BSF";
17829 case X86ISD::BSR: return "X86ISD::BSR";
17830 case X86ISD::SHLD: return "X86ISD::SHLD";
17831 case X86ISD::SHRD: return "X86ISD::SHRD";
17832 case X86ISD::FAND: return "X86ISD::FAND";
17833 case X86ISD::FANDN: return "X86ISD::FANDN";
17834 case X86ISD::FOR: return "X86ISD::FOR";
17835 case X86ISD::FXOR: return "X86ISD::FXOR";
17836 case X86ISD::FSRL: return "X86ISD::FSRL";
17837 case X86ISD::FILD: return "X86ISD::FILD";
17838 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
17839 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
17840 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
17841 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
17842 case X86ISD::FLD: return "X86ISD::FLD";
17843 case X86ISD::FST: return "X86ISD::FST";
17844 case X86ISD::CALL: return "X86ISD::CALL";
17845 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
17846 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
17847 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
17848 case X86ISD::BT: return "X86ISD::BT";
17849 case X86ISD::CMP: return "X86ISD::CMP";
17850 case X86ISD::COMI: return "X86ISD::COMI";
17851 case X86ISD::UCOMI: return "X86ISD::UCOMI";
17852 case X86ISD::CMPM: return "X86ISD::CMPM";
17853 case X86ISD::CMPMU: return "X86ISD::CMPMU";
17854 case X86ISD::SETCC: return "X86ISD::SETCC";
17855 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
17856 case X86ISD::FSETCC: return "X86ISD::FSETCC";
17857 case X86ISD::CMOV: return "X86ISD::CMOV";
17858 case X86ISD::BRCOND: return "X86ISD::BRCOND";
17859 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
17860 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
17861 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
17862 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
17863 case X86ISD::Wrapper: return "X86ISD::Wrapper";
17864 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
17865 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
17866 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
17867 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
17868 case X86ISD::PINSRB: return "X86ISD::PINSRB";
17869 case X86ISD::PINSRW: return "X86ISD::PINSRW";
17870 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
17871 case X86ISD::ANDNP: return "X86ISD::ANDNP";
17872 case X86ISD::PSIGN: return "X86ISD::PSIGN";
17873 case X86ISD::BLENDV: return "X86ISD::BLENDV";
17874 case X86ISD::BLENDI: return "X86ISD::BLENDI";
17875 case X86ISD::SUBUS: return "X86ISD::SUBUS";
17876 case X86ISD::HADD: return "X86ISD::HADD";
17877 case X86ISD::HSUB: return "X86ISD::HSUB";
17878 case X86ISD::FHADD: return "X86ISD::FHADD";
17879 case X86ISD::FHSUB: return "X86ISD::FHSUB";
17880 case X86ISD::UMAX: return "X86ISD::UMAX";
17881 case X86ISD::UMIN: return "X86ISD::UMIN";
17882 case X86ISD::SMAX: return "X86ISD::SMAX";
17883 case X86ISD::SMIN: return "X86ISD::SMIN";
17884 case X86ISD::FMAX: return "X86ISD::FMAX";
17885 case X86ISD::FMIN: return "X86ISD::FMIN";
17886 case X86ISD::FMAXC: return "X86ISD::FMAXC";
17887 case X86ISD::FMINC: return "X86ISD::FMINC";
17888 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
17889 case X86ISD::FRCP: return "X86ISD::FRCP";
17890 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
17891 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
17892 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
17893 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
17894 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
17895 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
17896 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
17897 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
17898 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
17899 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
17900 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
17901 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
17902 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
17903 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
17904 case X86ISD::VZEXT: return "X86ISD::VZEXT";
17905 case X86ISD::VSEXT: return "X86ISD::VSEXT";
17906 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
17907 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
17908 case X86ISD::VINSERT: return "X86ISD::VINSERT";
17909 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
17910 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
17911 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
17912 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
17913 case X86ISD::VSHL: return "X86ISD::VSHL";
17914 case X86ISD::VSRL: return "X86ISD::VSRL";
17915 case X86ISD::VSRA: return "X86ISD::VSRA";
17916 case X86ISD::VSHLI: return "X86ISD::VSHLI";
17917 case X86ISD::VSRLI: return "X86ISD::VSRLI";
17918 case X86ISD::VSRAI: return "X86ISD::VSRAI";
17919 case X86ISD::CMPP: return "X86ISD::CMPP";
17920 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
17921 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
17922 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
17923 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
17924 case X86ISD::ADD: return "X86ISD::ADD";
17925 case X86ISD::SUB: return "X86ISD::SUB";
17926 case X86ISD::ADC: return "X86ISD::ADC";
17927 case X86ISD::SBB: return "X86ISD::SBB";
17928 case X86ISD::SMUL: return "X86ISD::SMUL";
17929 case X86ISD::UMUL: return "X86ISD::UMUL";
17930 case X86ISD::INC: return "X86ISD::INC";
17931 case X86ISD::DEC: return "X86ISD::DEC";
17932 case X86ISD::OR: return "X86ISD::OR";
17933 case X86ISD::XOR: return "X86ISD::XOR";
17934 case X86ISD::AND: return "X86ISD::AND";
17935 case X86ISD::BEXTR: return "X86ISD::BEXTR";
17936 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
17937 case X86ISD::PTEST: return "X86ISD::PTEST";
17938 case X86ISD::TESTP: return "X86ISD::TESTP";
17939 case X86ISD::TESTM: return "X86ISD::TESTM";
17940 case X86ISD::TESTNM: return "X86ISD::TESTNM";
17941 case X86ISD::KORTEST: return "X86ISD::KORTEST";
17942 case X86ISD::PACKSS: return "X86ISD::PACKSS";
17943 case X86ISD::PACKUS: return "X86ISD::PACKUS";
17944 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
17945 case X86ISD::VALIGN: return "X86ISD::VALIGN";
17946 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
17947 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
17948 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
17949 case X86ISD::SHUFP: return "X86ISD::SHUFP";
17950 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
17951 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
17952 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
17953 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
17954 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
17955 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
17956 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
17957 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
17958 case X86ISD::MOVSD: return "X86ISD::MOVSD";
17959 case X86ISD::MOVSS: return "X86ISD::MOVSS";
17960 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
17961 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
17962 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
17963 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
17964 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
17965 case X86ISD::VPERMILP: return "X86ISD::VPERMILP";
17966 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
17967 case X86ISD::VPERMV: return "X86ISD::VPERMV";
17968 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
17969 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
17970 case X86ISD::VPERMI: return "X86ISD::VPERMI";
17971 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
17972 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
17973 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
17974 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
17975 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
17976 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
17977 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
17978 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
17979 case X86ISD::SAHF: return "X86ISD::SAHF";
17980 case X86ISD::RDRAND: return "X86ISD::RDRAND";
17981 case X86ISD::RDSEED: return "X86ISD::RDSEED";
17982 case X86ISD::FMADD: return "X86ISD::FMADD";
17983 case X86ISD::FMSUB: return "X86ISD::FMSUB";
17984 case X86ISD::FNMADD: return "X86ISD::FNMADD";
17985 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
17986 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
17987 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
17988 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
17989 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
17990 case X86ISD::XTEST: return "X86ISD::XTEST";
17994 // isLegalAddressingMode - Return true if the addressing mode represented
17995 // by AM is legal for this target, for a load/store of the specified type.
17996 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
17998 // X86 supports extremely general addressing modes.
17999 CodeModel::Model M = getTargetMachine().getCodeModel();
18000 Reloc::Model R = getTargetMachine().getRelocationModel();
18002 // X86 allows a sign-extended 32-bit immediate field as a displacement.
18003 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
18008 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
18010 // If a reference to this global requires an extra load, we can't fold it.
18011 if (isGlobalStubReference(GVFlags))
18014 // If BaseGV requires a register for the PIC base, we cannot also have a
18015 // BaseReg specified.
18016 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
18019 // If lower 4G is not available, then we must use rip-relative addressing.
18020 if ((M != CodeModel::Small || R != Reloc::Static) &&
18021 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
18025 switch (AM.Scale) {
18031 // These scales always work.
18036 // These scales are formed with basereg+scalereg. Only accept if there is
18041 default: // Other stuff never works.
18048 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
18049 unsigned Bits = Ty->getScalarSizeInBits();
18051 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
18052 // particularly cheaper than those without.
18056 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
18057 // variable shifts just as cheap as scalar ones.
18058 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
18061 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
18062 // fully general vector.
18066 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
18067 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
18069 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
18070 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
18071 return NumBits1 > NumBits2;
18074 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
18075 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
18078 if (!isTypeLegal(EVT::getEVT(Ty1)))
18081 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
18083 // Assuming the caller doesn't have a zeroext or signext return parameter,
18084 // truncation all the way down to i1 is valid.
18088 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
18089 return isInt<32>(Imm);
18092 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
18093 // Can also use sub to handle negated immediates.
18094 return isInt<32>(Imm);
18097 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
18098 if (!VT1.isInteger() || !VT2.isInteger())
18100 unsigned NumBits1 = VT1.getSizeInBits();
18101 unsigned NumBits2 = VT2.getSizeInBits();
18102 return NumBits1 > NumBits2;
18105 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
18106 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
18107 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
18110 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
18111 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
18112 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
18115 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
18116 EVT VT1 = Val.getValueType();
18117 if (isZExtFree(VT1, VT2))
18120 if (Val.getOpcode() != ISD::LOAD)
18123 if (!VT1.isSimple() || !VT1.isInteger() ||
18124 !VT2.isSimple() || !VT2.isInteger())
18127 switch (VT1.getSimpleVT().SimpleTy) {
18132 // X86 has 8, 16, and 32-bit zero-extending loads.
18140 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
18141 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
18144 VT = VT.getScalarType();
18146 if (!VT.isSimple())
18149 switch (VT.getSimpleVT().SimpleTy) {
18160 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
18161 // i16 instructions are longer (0x66 prefix) and potentially slower.
18162 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
18165 /// isShuffleMaskLegal - Targets can use this to indicate that they only
18166 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
18167 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
18168 /// are assumed to be legal.
18170 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
18172 if (!VT.isSimple())
18175 MVT SVT = VT.getSimpleVT();
18177 // Very little shuffling can be done for 64-bit vectors right now.
18178 if (VT.getSizeInBits() == 64)
18181 // If this is a single-input shuffle with no 128 bit lane crossings we can
18182 // lower it into pshufb.
18183 if ((SVT.is128BitVector() && Subtarget->hasSSSE3()) ||
18184 (SVT.is256BitVector() && Subtarget->hasInt256())) {
18185 bool isLegal = true;
18186 for (unsigned I = 0, E = M.size(); I != E; ++I) {
18187 if (M[I] >= (int)SVT.getVectorNumElements() ||
18188 ShuffleCrosses128bitLane(SVT, I, M[I])) {
18197 // FIXME: blends, shifts.
18198 return (SVT.getVectorNumElements() == 2 ||
18199 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
18200 isMOVLMask(M, SVT) ||
18201 isMOVHLPSMask(M, SVT) ||
18202 isSHUFPMask(M, SVT) ||
18203 isPSHUFDMask(M, SVT) ||
18204 isPSHUFHWMask(M, SVT, Subtarget->hasInt256()) ||
18205 isPSHUFLWMask(M, SVT, Subtarget->hasInt256()) ||
18206 isPALIGNRMask(M, SVT, Subtarget) ||
18207 isUNPCKLMask(M, SVT, Subtarget->hasInt256()) ||
18208 isUNPCKHMask(M, SVT, Subtarget->hasInt256()) ||
18209 isUNPCKL_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
18210 isUNPCKH_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
18211 isBlendMask(M, SVT, Subtarget->hasSSE41(), Subtarget->hasInt256()));
18215 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
18217 if (!VT.isSimple())
18220 MVT SVT = VT.getSimpleVT();
18221 unsigned NumElts = SVT.getVectorNumElements();
18222 // FIXME: This collection of masks seems suspect.
18225 if (NumElts == 4 && SVT.is128BitVector()) {
18226 return (isMOVLMask(Mask, SVT) ||
18227 isCommutedMOVLMask(Mask, SVT, true) ||
18228 isSHUFPMask(Mask, SVT) ||
18229 isSHUFPMask(Mask, SVT, /* Commuted */ true));
18234 //===----------------------------------------------------------------------===//
18235 // X86 Scheduler Hooks
18236 //===----------------------------------------------------------------------===//
18238 /// Utility function to emit xbegin specifying the start of an RTM region.
18239 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
18240 const TargetInstrInfo *TII) {
18241 DebugLoc DL = MI->getDebugLoc();
18243 const BasicBlock *BB = MBB->getBasicBlock();
18244 MachineFunction::iterator I = MBB;
18247 // For the v = xbegin(), we generate
18258 MachineBasicBlock *thisMBB = MBB;
18259 MachineFunction *MF = MBB->getParent();
18260 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
18261 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
18262 MF->insert(I, mainMBB);
18263 MF->insert(I, sinkMBB);
18265 // Transfer the remainder of BB and its successor edges to sinkMBB.
18266 sinkMBB->splice(sinkMBB->begin(), MBB,
18267 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
18268 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
18272 // # fallthrough to mainMBB
18273 // # abortion to sinkMBB
18274 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
18275 thisMBB->addSuccessor(mainMBB);
18276 thisMBB->addSuccessor(sinkMBB);
18280 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
18281 mainMBB->addSuccessor(sinkMBB);
18284 // EAX is live into the sinkMBB
18285 sinkMBB->addLiveIn(X86::EAX);
18286 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
18287 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
18290 MI->eraseFromParent();
18294 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
18295 // or XMM0_V32I8 in AVX all of this code can be replaced with that
18296 // in the .td file.
18297 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
18298 const TargetInstrInfo *TII) {
18300 switch (MI->getOpcode()) {
18301 default: llvm_unreachable("illegal opcode!");
18302 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
18303 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
18304 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
18305 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
18306 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
18307 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
18308 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
18309 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
18312 DebugLoc dl = MI->getDebugLoc();
18313 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
18315 unsigned NumArgs = MI->getNumOperands();
18316 for (unsigned i = 1; i < NumArgs; ++i) {
18317 MachineOperand &Op = MI->getOperand(i);
18318 if (!(Op.isReg() && Op.isImplicit()))
18319 MIB.addOperand(Op);
18321 if (MI->hasOneMemOperand())
18322 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
18324 BuildMI(*BB, MI, dl,
18325 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
18326 .addReg(X86::XMM0);
18328 MI->eraseFromParent();
18332 // FIXME: Custom handling because TableGen doesn't support multiple implicit
18333 // defs in an instruction pattern
18334 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
18335 const TargetInstrInfo *TII) {
18337 switch (MI->getOpcode()) {
18338 default: llvm_unreachable("illegal opcode!");
18339 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
18340 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
18341 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
18342 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
18343 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
18344 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
18345 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
18346 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
18349 DebugLoc dl = MI->getDebugLoc();
18350 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
18352 unsigned NumArgs = MI->getNumOperands(); // remove the results
18353 for (unsigned i = 1; i < NumArgs; ++i) {
18354 MachineOperand &Op = MI->getOperand(i);
18355 if (!(Op.isReg() && Op.isImplicit()))
18356 MIB.addOperand(Op);
18358 if (MI->hasOneMemOperand())
18359 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
18361 BuildMI(*BB, MI, dl,
18362 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
18365 MI->eraseFromParent();
18369 static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
18370 const TargetInstrInfo *TII,
18371 const X86Subtarget* Subtarget) {
18372 DebugLoc dl = MI->getDebugLoc();
18374 // Address into RAX/EAX, other two args into ECX, EDX.
18375 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
18376 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
18377 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
18378 for (int i = 0; i < X86::AddrNumOperands; ++i)
18379 MIB.addOperand(MI->getOperand(i));
18381 unsigned ValOps = X86::AddrNumOperands;
18382 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
18383 .addReg(MI->getOperand(ValOps).getReg());
18384 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
18385 .addReg(MI->getOperand(ValOps+1).getReg());
18387 // The instruction doesn't actually take any operands though.
18388 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
18390 MI->eraseFromParent(); // The pseudo is gone now.
18394 MachineBasicBlock *
18395 X86TargetLowering::EmitVAARG64WithCustomInserter(
18397 MachineBasicBlock *MBB) const {
18398 // Emit va_arg instruction on X86-64.
18400 // Operands to this pseudo-instruction:
18401 // 0 ) Output : destination address (reg)
18402 // 1-5) Input : va_list address (addr, i64mem)
18403 // 6 ) ArgSize : Size (in bytes) of vararg type
18404 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
18405 // 8 ) Align : Alignment of type
18406 // 9 ) EFLAGS (implicit-def)
18408 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
18409 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
18411 unsigned DestReg = MI->getOperand(0).getReg();
18412 MachineOperand &Base = MI->getOperand(1);
18413 MachineOperand &Scale = MI->getOperand(2);
18414 MachineOperand &Index = MI->getOperand(3);
18415 MachineOperand &Disp = MI->getOperand(4);
18416 MachineOperand &Segment = MI->getOperand(5);
18417 unsigned ArgSize = MI->getOperand(6).getImm();
18418 unsigned ArgMode = MI->getOperand(7).getImm();
18419 unsigned Align = MI->getOperand(8).getImm();
18421 // Memory Reference
18422 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
18423 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
18424 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
18426 // Machine Information
18427 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
18428 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
18429 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
18430 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
18431 DebugLoc DL = MI->getDebugLoc();
18433 // struct va_list {
18436 // i64 overflow_area (address)
18437 // i64 reg_save_area (address)
18439 // sizeof(va_list) = 24
18440 // alignment(va_list) = 8
18442 unsigned TotalNumIntRegs = 6;
18443 unsigned TotalNumXMMRegs = 8;
18444 bool UseGPOffset = (ArgMode == 1);
18445 bool UseFPOffset = (ArgMode == 2);
18446 unsigned MaxOffset = TotalNumIntRegs * 8 +
18447 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
18449 /* Align ArgSize to a multiple of 8 */
18450 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
18451 bool NeedsAlign = (Align > 8);
18453 MachineBasicBlock *thisMBB = MBB;
18454 MachineBasicBlock *overflowMBB;
18455 MachineBasicBlock *offsetMBB;
18456 MachineBasicBlock *endMBB;
18458 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
18459 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
18460 unsigned OffsetReg = 0;
18462 if (!UseGPOffset && !UseFPOffset) {
18463 // If we only pull from the overflow region, we don't create a branch.
18464 // We don't need to alter control flow.
18465 OffsetDestReg = 0; // unused
18466 OverflowDestReg = DestReg;
18468 offsetMBB = nullptr;
18469 overflowMBB = thisMBB;
18472 // First emit code to check if gp_offset (or fp_offset) is below the bound.
18473 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
18474 // If not, pull from overflow_area. (branch to overflowMBB)
18479 // offsetMBB overflowMBB
18484 // Registers for the PHI in endMBB
18485 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
18486 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
18488 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
18489 MachineFunction *MF = MBB->getParent();
18490 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18491 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18492 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18494 MachineFunction::iterator MBBIter = MBB;
18497 // Insert the new basic blocks
18498 MF->insert(MBBIter, offsetMBB);
18499 MF->insert(MBBIter, overflowMBB);
18500 MF->insert(MBBIter, endMBB);
18502 // Transfer the remainder of MBB and its successor edges to endMBB.
18503 endMBB->splice(endMBB->begin(), thisMBB,
18504 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
18505 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
18507 // Make offsetMBB and overflowMBB successors of thisMBB
18508 thisMBB->addSuccessor(offsetMBB);
18509 thisMBB->addSuccessor(overflowMBB);
18511 // endMBB is a successor of both offsetMBB and overflowMBB
18512 offsetMBB->addSuccessor(endMBB);
18513 overflowMBB->addSuccessor(endMBB);
18515 // Load the offset value into a register
18516 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
18517 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
18521 .addDisp(Disp, UseFPOffset ? 4 : 0)
18522 .addOperand(Segment)
18523 .setMemRefs(MMOBegin, MMOEnd);
18525 // Check if there is enough room left to pull this argument.
18526 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
18528 .addImm(MaxOffset + 8 - ArgSizeA8);
18530 // Branch to "overflowMBB" if offset >= max
18531 // Fall through to "offsetMBB" otherwise
18532 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
18533 .addMBB(overflowMBB);
18536 // In offsetMBB, emit code to use the reg_save_area.
18538 assert(OffsetReg != 0);
18540 // Read the reg_save_area address.
18541 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
18542 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
18547 .addOperand(Segment)
18548 .setMemRefs(MMOBegin, MMOEnd);
18550 // Zero-extend the offset
18551 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
18552 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
18555 .addImm(X86::sub_32bit);
18557 // Add the offset to the reg_save_area to get the final address.
18558 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
18559 .addReg(OffsetReg64)
18560 .addReg(RegSaveReg);
18562 // Compute the offset for the next argument
18563 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
18564 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
18566 .addImm(UseFPOffset ? 16 : 8);
18568 // Store it back into the va_list.
18569 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
18573 .addDisp(Disp, UseFPOffset ? 4 : 0)
18574 .addOperand(Segment)
18575 .addReg(NextOffsetReg)
18576 .setMemRefs(MMOBegin, MMOEnd);
18579 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
18584 // Emit code to use overflow area
18587 // Load the overflow_area address into a register.
18588 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
18589 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
18594 .addOperand(Segment)
18595 .setMemRefs(MMOBegin, MMOEnd);
18597 // If we need to align it, do so. Otherwise, just copy the address
18598 // to OverflowDestReg.
18600 // Align the overflow address
18601 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
18602 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
18604 // aligned_addr = (addr + (align-1)) & ~(align-1)
18605 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
18606 .addReg(OverflowAddrReg)
18609 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
18611 .addImm(~(uint64_t)(Align-1));
18613 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
18614 .addReg(OverflowAddrReg);
18617 // Compute the next overflow address after this argument.
18618 // (the overflow address should be kept 8-byte aligned)
18619 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
18620 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
18621 .addReg(OverflowDestReg)
18622 .addImm(ArgSizeA8);
18624 // Store the new overflow address.
18625 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
18630 .addOperand(Segment)
18631 .addReg(NextAddrReg)
18632 .setMemRefs(MMOBegin, MMOEnd);
18634 // If we branched, emit the PHI to the front of endMBB.
18636 BuildMI(*endMBB, endMBB->begin(), DL,
18637 TII->get(X86::PHI), DestReg)
18638 .addReg(OffsetDestReg).addMBB(offsetMBB)
18639 .addReg(OverflowDestReg).addMBB(overflowMBB);
18642 // Erase the pseudo instruction
18643 MI->eraseFromParent();
18648 MachineBasicBlock *
18649 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
18651 MachineBasicBlock *MBB) const {
18652 // Emit code to save XMM registers to the stack. The ABI says that the
18653 // number of registers to save is given in %al, so it's theoretically
18654 // possible to do an indirect jump trick to avoid saving all of them,
18655 // however this code takes a simpler approach and just executes all
18656 // of the stores if %al is non-zero. It's less code, and it's probably
18657 // easier on the hardware branch predictor, and stores aren't all that
18658 // expensive anyway.
18660 // Create the new basic blocks. One block contains all the XMM stores,
18661 // and one block is the final destination regardless of whether any
18662 // stores were performed.
18663 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
18664 MachineFunction *F = MBB->getParent();
18665 MachineFunction::iterator MBBIter = MBB;
18667 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
18668 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
18669 F->insert(MBBIter, XMMSaveMBB);
18670 F->insert(MBBIter, EndMBB);
18672 // Transfer the remainder of MBB and its successor edges to EndMBB.
18673 EndMBB->splice(EndMBB->begin(), MBB,
18674 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
18675 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
18677 // The original block will now fall through to the XMM save block.
18678 MBB->addSuccessor(XMMSaveMBB);
18679 // The XMMSaveMBB will fall through to the end block.
18680 XMMSaveMBB->addSuccessor(EndMBB);
18682 // Now add the instructions.
18683 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
18684 DebugLoc DL = MI->getDebugLoc();
18686 unsigned CountReg = MI->getOperand(0).getReg();
18687 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
18688 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
18690 if (!Subtarget->isTargetWin64()) {
18691 // If %al is 0, branch around the XMM save block.
18692 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
18693 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
18694 MBB->addSuccessor(EndMBB);
18697 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
18698 // that was just emitted, but clearly shouldn't be "saved".
18699 assert((MI->getNumOperands() <= 3 ||
18700 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
18701 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
18702 && "Expected last argument to be EFLAGS");
18703 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
18704 // In the XMM save block, save all the XMM argument registers.
18705 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
18706 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
18707 MachineMemOperand *MMO =
18708 F->getMachineMemOperand(
18709 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
18710 MachineMemOperand::MOStore,
18711 /*Size=*/16, /*Align=*/16);
18712 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
18713 .addFrameIndex(RegSaveFrameIndex)
18714 .addImm(/*Scale=*/1)
18715 .addReg(/*IndexReg=*/0)
18716 .addImm(/*Disp=*/Offset)
18717 .addReg(/*Segment=*/0)
18718 .addReg(MI->getOperand(i).getReg())
18719 .addMemOperand(MMO);
18722 MI->eraseFromParent(); // The pseudo instruction is gone now.
18727 // The EFLAGS operand of SelectItr might be missing a kill marker
18728 // because there were multiple uses of EFLAGS, and ISel didn't know
18729 // which to mark. Figure out whether SelectItr should have had a
18730 // kill marker, and set it if it should. Returns the correct kill
18732 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
18733 MachineBasicBlock* BB,
18734 const TargetRegisterInfo* TRI) {
18735 // Scan forward through BB for a use/def of EFLAGS.
18736 MachineBasicBlock::iterator miI(std::next(SelectItr));
18737 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
18738 const MachineInstr& mi = *miI;
18739 if (mi.readsRegister(X86::EFLAGS))
18741 if (mi.definesRegister(X86::EFLAGS))
18742 break; // Should have kill-flag - update below.
18745 // If we hit the end of the block, check whether EFLAGS is live into a
18747 if (miI == BB->end()) {
18748 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
18749 sEnd = BB->succ_end();
18750 sItr != sEnd; ++sItr) {
18751 MachineBasicBlock* succ = *sItr;
18752 if (succ->isLiveIn(X86::EFLAGS))
18757 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
18758 // out. SelectMI should have a kill flag on EFLAGS.
18759 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
18763 MachineBasicBlock *
18764 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
18765 MachineBasicBlock *BB) const {
18766 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
18767 DebugLoc DL = MI->getDebugLoc();
18769 // To "insert" a SELECT_CC instruction, we actually have to insert the
18770 // diamond control-flow pattern. The incoming instruction knows the
18771 // destination vreg to set, the condition code register to branch on, the
18772 // true/false values to select between, and a branch opcode to use.
18773 const BasicBlock *LLVM_BB = BB->getBasicBlock();
18774 MachineFunction::iterator It = BB;
18780 // cmpTY ccX, r1, r2
18782 // fallthrough --> copy0MBB
18783 MachineBasicBlock *thisMBB = BB;
18784 MachineFunction *F = BB->getParent();
18785 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
18786 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
18787 F->insert(It, copy0MBB);
18788 F->insert(It, sinkMBB);
18790 // If the EFLAGS register isn't dead in the terminator, then claim that it's
18791 // live into the sink and copy blocks.
18792 const TargetRegisterInfo *TRI =
18793 BB->getParent()->getSubtarget().getRegisterInfo();
18794 if (!MI->killsRegister(X86::EFLAGS) &&
18795 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
18796 copy0MBB->addLiveIn(X86::EFLAGS);
18797 sinkMBB->addLiveIn(X86::EFLAGS);
18800 // Transfer the remainder of BB and its successor edges to sinkMBB.
18801 sinkMBB->splice(sinkMBB->begin(), BB,
18802 std::next(MachineBasicBlock::iterator(MI)), BB->end());
18803 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
18805 // Add the true and fallthrough blocks as its successors.
18806 BB->addSuccessor(copy0MBB);
18807 BB->addSuccessor(sinkMBB);
18809 // Create the conditional branch instruction.
18811 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
18812 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
18815 // %FalseValue = ...
18816 // # fallthrough to sinkMBB
18817 copy0MBB->addSuccessor(sinkMBB);
18820 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
18822 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
18823 TII->get(X86::PHI), MI->getOperand(0).getReg())
18824 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
18825 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
18827 MI->eraseFromParent(); // The pseudo instruction is gone now.
18831 MachineBasicBlock *
18832 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB,
18833 bool Is64Bit) const {
18834 MachineFunction *MF = BB->getParent();
18835 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
18836 DebugLoc DL = MI->getDebugLoc();
18837 const BasicBlock *LLVM_BB = BB->getBasicBlock();
18839 assert(MF->shouldSplitStack());
18841 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
18842 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30;
18845 // ... [Till the alloca]
18846 // If stacklet is not large enough, jump to mallocMBB
18849 // Allocate by subtracting from RSP
18850 // Jump to continueMBB
18853 // Allocate by call to runtime
18857 // [rest of original BB]
18860 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18861 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18862 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18864 MachineRegisterInfo &MRI = MF->getRegInfo();
18865 const TargetRegisterClass *AddrRegClass =
18866 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32);
18868 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
18869 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
18870 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
18871 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
18872 sizeVReg = MI->getOperand(1).getReg(),
18873 physSPReg = Is64Bit ? X86::RSP : X86::ESP;
18875 MachineFunction::iterator MBBIter = BB;
18878 MF->insert(MBBIter, bumpMBB);
18879 MF->insert(MBBIter, mallocMBB);
18880 MF->insert(MBBIter, continueMBB);
18882 continueMBB->splice(continueMBB->begin(), BB,
18883 std::next(MachineBasicBlock::iterator(MI)), BB->end());
18884 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
18886 // Add code to the main basic block to check if the stack limit has been hit,
18887 // and if so, jump to mallocMBB otherwise to bumpMBB.
18888 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
18889 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
18890 .addReg(tmpSPVReg).addReg(sizeVReg);
18891 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr))
18892 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
18893 .addReg(SPLimitVReg);
18894 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
18896 // bumpMBB simply decreases the stack pointer, since we know the current
18897 // stacklet has enough space.
18898 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
18899 .addReg(SPLimitVReg);
18900 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
18901 .addReg(SPLimitVReg);
18902 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
18904 // Calls into a routine in libgcc to allocate more space from the heap.
18905 const uint32_t *RegMask = MF->getTarget()
18906 .getSubtargetImpl()
18907 ->getRegisterInfo()
18908 ->getCallPreservedMask(CallingConv::C);
18910 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
18912 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
18913 .addExternalSymbol("__morestack_allocate_stack_space")
18914 .addRegMask(RegMask)
18915 .addReg(X86::RDI, RegState::Implicit)
18916 .addReg(X86::RAX, RegState::ImplicitDefine);
18918 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
18920 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
18921 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
18922 .addExternalSymbol("__morestack_allocate_stack_space")
18923 .addRegMask(RegMask)
18924 .addReg(X86::EAX, RegState::ImplicitDefine);
18928 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
18931 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
18932 .addReg(Is64Bit ? X86::RAX : X86::EAX);
18933 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
18935 // Set up the CFG correctly.
18936 BB->addSuccessor(bumpMBB);
18937 BB->addSuccessor(mallocMBB);
18938 mallocMBB->addSuccessor(continueMBB);
18939 bumpMBB->addSuccessor(continueMBB);
18941 // Take care of the PHI nodes.
18942 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
18943 MI->getOperand(0).getReg())
18944 .addReg(mallocPtrVReg).addMBB(mallocMBB)
18945 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
18947 // Delete the original pseudo instruction.
18948 MI->eraseFromParent();
18951 return continueMBB;
18954 MachineBasicBlock *
18955 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
18956 MachineBasicBlock *BB) const {
18957 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
18958 DebugLoc DL = MI->getDebugLoc();
18960 assert(!Subtarget->isTargetMacho());
18962 // The lowering is pretty easy: we're just emitting the call to _alloca. The
18963 // non-trivial part is impdef of ESP.
18965 if (Subtarget->isTargetWin64()) {
18966 if (Subtarget->isTargetCygMing()) {
18967 // ___chkstk(Mingw64):
18968 // Clobbers R10, R11, RAX and EFLAGS.
18970 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
18971 .addExternalSymbol("___chkstk")
18972 .addReg(X86::RAX, RegState::Implicit)
18973 .addReg(X86::RSP, RegState::Implicit)
18974 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
18975 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
18976 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
18978 // __chkstk(MSVCRT): does not update stack pointer.
18979 // Clobbers R10, R11 and EFLAGS.
18980 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
18981 .addExternalSymbol("__chkstk")
18982 .addReg(X86::RAX, RegState::Implicit)
18983 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
18984 // RAX has the offset to be subtracted from RSP.
18985 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
18990 const char *StackProbeSymbol =
18991 Subtarget->isTargetKnownWindowsMSVC() ? "_chkstk" : "_alloca";
18993 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
18994 .addExternalSymbol(StackProbeSymbol)
18995 .addReg(X86::EAX, RegState::Implicit)
18996 .addReg(X86::ESP, RegState::Implicit)
18997 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
18998 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
18999 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
19002 MI->eraseFromParent(); // The pseudo instruction is gone now.
19006 MachineBasicBlock *
19007 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
19008 MachineBasicBlock *BB) const {
19009 // This is pretty easy. We're taking the value that we received from
19010 // our load from the relocation, sticking it in either RDI (x86-64)
19011 // or EAX and doing an indirect call. The return value will then
19012 // be in the normal return register.
19013 MachineFunction *F = BB->getParent();
19014 const X86InstrInfo *TII =
19015 static_cast<const X86InstrInfo *>(F->getSubtarget().getInstrInfo());
19016 DebugLoc DL = MI->getDebugLoc();
19018 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
19019 assert(MI->getOperand(3).isGlobal() && "This should be a global");
19021 // Get a register mask for the lowered call.
19022 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
19023 // proper register mask.
19024 const uint32_t *RegMask = F->getTarget()
19025 .getSubtargetImpl()
19026 ->getRegisterInfo()
19027 ->getCallPreservedMask(CallingConv::C);
19028 if (Subtarget->is64Bit()) {
19029 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
19030 TII->get(X86::MOV64rm), X86::RDI)
19032 .addImm(0).addReg(0)
19033 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
19034 MI->getOperand(3).getTargetFlags())
19036 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
19037 addDirectMem(MIB, X86::RDI);
19038 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
19039 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
19040 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
19041 TII->get(X86::MOV32rm), X86::EAX)
19043 .addImm(0).addReg(0)
19044 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
19045 MI->getOperand(3).getTargetFlags())
19047 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
19048 addDirectMem(MIB, X86::EAX);
19049 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
19051 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
19052 TII->get(X86::MOV32rm), X86::EAX)
19053 .addReg(TII->getGlobalBaseReg(F))
19054 .addImm(0).addReg(0)
19055 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
19056 MI->getOperand(3).getTargetFlags())
19058 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
19059 addDirectMem(MIB, X86::EAX);
19060 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
19063 MI->eraseFromParent(); // The pseudo instruction is gone now.
19067 MachineBasicBlock *
19068 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
19069 MachineBasicBlock *MBB) const {
19070 DebugLoc DL = MI->getDebugLoc();
19071 MachineFunction *MF = MBB->getParent();
19072 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
19073 MachineRegisterInfo &MRI = MF->getRegInfo();
19075 const BasicBlock *BB = MBB->getBasicBlock();
19076 MachineFunction::iterator I = MBB;
19079 // Memory Reference
19080 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
19081 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
19084 unsigned MemOpndSlot = 0;
19086 unsigned CurOp = 0;
19088 DstReg = MI->getOperand(CurOp++).getReg();
19089 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
19090 assert(RC->hasType(MVT::i32) && "Invalid destination!");
19091 unsigned mainDstReg = MRI.createVirtualRegister(RC);
19092 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
19094 MemOpndSlot = CurOp;
19096 MVT PVT = getPointerTy();
19097 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
19098 "Invalid Pointer Size!");
19100 // For v = setjmp(buf), we generate
19103 // buf[LabelOffset] = restoreMBB
19104 // SjLjSetup restoreMBB
19110 // v = phi(main, restore)
19115 MachineBasicBlock *thisMBB = MBB;
19116 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
19117 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
19118 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
19119 MF->insert(I, mainMBB);
19120 MF->insert(I, sinkMBB);
19121 MF->push_back(restoreMBB);
19123 MachineInstrBuilder MIB;
19125 // Transfer the remainder of BB and its successor edges to sinkMBB.
19126 sinkMBB->splice(sinkMBB->begin(), MBB,
19127 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
19128 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
19131 unsigned PtrStoreOpc = 0;
19132 unsigned LabelReg = 0;
19133 const int64_t LabelOffset = 1 * PVT.getStoreSize();
19134 Reloc::Model RM = MF->getTarget().getRelocationModel();
19135 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
19136 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
19138 // Prepare IP either in reg or imm.
19139 if (!UseImmLabel) {
19140 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
19141 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
19142 LabelReg = MRI.createVirtualRegister(PtrRC);
19143 if (Subtarget->is64Bit()) {
19144 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
19148 .addMBB(restoreMBB)
19151 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
19152 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
19153 .addReg(XII->getGlobalBaseReg(MF))
19156 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
19160 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
19162 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
19163 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
19164 if (i == X86::AddrDisp)
19165 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
19167 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
19170 MIB.addReg(LabelReg);
19172 MIB.addMBB(restoreMBB);
19173 MIB.setMemRefs(MMOBegin, MMOEnd);
19175 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
19176 .addMBB(restoreMBB);
19178 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
19179 MF->getSubtarget().getRegisterInfo());
19180 MIB.addRegMask(RegInfo->getNoPreservedMask());
19181 thisMBB->addSuccessor(mainMBB);
19182 thisMBB->addSuccessor(restoreMBB);
19186 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
19187 mainMBB->addSuccessor(sinkMBB);
19190 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
19191 TII->get(X86::PHI), DstReg)
19192 .addReg(mainDstReg).addMBB(mainMBB)
19193 .addReg(restoreDstReg).addMBB(restoreMBB);
19196 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
19197 BuildMI(restoreMBB, DL, TII->get(X86::JMP_4)).addMBB(sinkMBB);
19198 restoreMBB->addSuccessor(sinkMBB);
19200 MI->eraseFromParent();
19204 MachineBasicBlock *
19205 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
19206 MachineBasicBlock *MBB) const {
19207 DebugLoc DL = MI->getDebugLoc();
19208 MachineFunction *MF = MBB->getParent();
19209 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
19210 MachineRegisterInfo &MRI = MF->getRegInfo();
19212 // Memory Reference
19213 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
19214 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
19216 MVT PVT = getPointerTy();
19217 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
19218 "Invalid Pointer Size!");
19220 const TargetRegisterClass *RC =
19221 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
19222 unsigned Tmp = MRI.createVirtualRegister(RC);
19223 // Since FP is only updated here but NOT referenced, it's treated as GPR.
19224 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
19225 MF->getSubtarget().getRegisterInfo());
19226 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
19227 unsigned SP = RegInfo->getStackRegister();
19229 MachineInstrBuilder MIB;
19231 const int64_t LabelOffset = 1 * PVT.getStoreSize();
19232 const int64_t SPOffset = 2 * PVT.getStoreSize();
19234 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
19235 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
19238 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
19239 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
19240 MIB.addOperand(MI->getOperand(i));
19241 MIB.setMemRefs(MMOBegin, MMOEnd);
19243 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
19244 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
19245 if (i == X86::AddrDisp)
19246 MIB.addDisp(MI->getOperand(i), LabelOffset);
19248 MIB.addOperand(MI->getOperand(i));
19250 MIB.setMemRefs(MMOBegin, MMOEnd);
19252 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
19253 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
19254 if (i == X86::AddrDisp)
19255 MIB.addDisp(MI->getOperand(i), SPOffset);
19257 MIB.addOperand(MI->getOperand(i));
19259 MIB.setMemRefs(MMOBegin, MMOEnd);
19261 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
19263 MI->eraseFromParent();
19267 // Replace 213-type (isel default) FMA3 instructions with 231-type for
19268 // accumulator loops. Writing back to the accumulator allows the coalescer
19269 // to remove extra copies in the loop.
19270 MachineBasicBlock *
19271 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
19272 MachineBasicBlock *MBB) const {
19273 MachineOperand &AddendOp = MI->getOperand(3);
19275 // Bail out early if the addend isn't a register - we can't switch these.
19276 if (!AddendOp.isReg())
19279 MachineFunction &MF = *MBB->getParent();
19280 MachineRegisterInfo &MRI = MF.getRegInfo();
19282 // Check whether the addend is defined by a PHI:
19283 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
19284 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
19285 if (!AddendDef.isPHI())
19288 // Look for the following pattern:
19290 // %addend = phi [%entry, 0], [%loop, %result]
19292 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
19296 // %addend = phi [%entry, 0], [%loop, %result]
19298 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
19300 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
19301 assert(AddendDef.getOperand(i).isReg());
19302 MachineOperand PHISrcOp = AddendDef.getOperand(i);
19303 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
19304 if (&PHISrcInst == MI) {
19305 // Found a matching instruction.
19306 unsigned NewFMAOpc = 0;
19307 switch (MI->getOpcode()) {
19308 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
19309 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
19310 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
19311 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
19312 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
19313 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
19314 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
19315 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
19316 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
19317 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
19318 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
19319 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
19320 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
19321 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
19322 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
19323 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
19324 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
19325 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
19326 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
19327 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
19328 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
19329 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
19330 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
19331 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
19332 default: llvm_unreachable("Unrecognized FMA variant.");
19335 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
19336 MachineInstrBuilder MIB =
19337 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
19338 .addOperand(MI->getOperand(0))
19339 .addOperand(MI->getOperand(3))
19340 .addOperand(MI->getOperand(2))
19341 .addOperand(MI->getOperand(1));
19342 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
19343 MI->eraseFromParent();
19350 MachineBasicBlock *
19351 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
19352 MachineBasicBlock *BB) const {
19353 switch (MI->getOpcode()) {
19354 default: llvm_unreachable("Unexpected instr type to insert");
19355 case X86::TAILJMPd64:
19356 case X86::TAILJMPr64:
19357 case X86::TAILJMPm64:
19358 llvm_unreachable("TAILJMP64 would not be touched here.");
19359 case X86::TCRETURNdi64:
19360 case X86::TCRETURNri64:
19361 case X86::TCRETURNmi64:
19363 case X86::WIN_ALLOCA:
19364 return EmitLoweredWinAlloca(MI, BB);
19365 case X86::SEG_ALLOCA_32:
19366 return EmitLoweredSegAlloca(MI, BB, false);
19367 case X86::SEG_ALLOCA_64:
19368 return EmitLoweredSegAlloca(MI, BB, true);
19369 case X86::TLSCall_32:
19370 case X86::TLSCall_64:
19371 return EmitLoweredTLSCall(MI, BB);
19372 case X86::CMOV_GR8:
19373 case X86::CMOV_FR32:
19374 case X86::CMOV_FR64:
19375 case X86::CMOV_V4F32:
19376 case X86::CMOV_V2F64:
19377 case X86::CMOV_V2I64:
19378 case X86::CMOV_V8F32:
19379 case X86::CMOV_V4F64:
19380 case X86::CMOV_V4I64:
19381 case X86::CMOV_V16F32:
19382 case X86::CMOV_V8F64:
19383 case X86::CMOV_V8I64:
19384 case X86::CMOV_GR16:
19385 case X86::CMOV_GR32:
19386 case X86::CMOV_RFP32:
19387 case X86::CMOV_RFP64:
19388 case X86::CMOV_RFP80:
19389 return EmitLoweredSelect(MI, BB);
19391 case X86::FP32_TO_INT16_IN_MEM:
19392 case X86::FP32_TO_INT32_IN_MEM:
19393 case X86::FP32_TO_INT64_IN_MEM:
19394 case X86::FP64_TO_INT16_IN_MEM:
19395 case X86::FP64_TO_INT32_IN_MEM:
19396 case X86::FP64_TO_INT64_IN_MEM:
19397 case X86::FP80_TO_INT16_IN_MEM:
19398 case X86::FP80_TO_INT32_IN_MEM:
19399 case X86::FP80_TO_INT64_IN_MEM: {
19400 MachineFunction *F = BB->getParent();
19401 const TargetInstrInfo *TII = F->getSubtarget().getInstrInfo();
19402 DebugLoc DL = MI->getDebugLoc();
19404 // Change the floating point control register to use "round towards zero"
19405 // mode when truncating to an integer value.
19406 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
19407 addFrameReference(BuildMI(*BB, MI, DL,
19408 TII->get(X86::FNSTCW16m)), CWFrameIdx);
19410 // Load the old value of the high byte of the control word...
19412 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
19413 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
19416 // Set the high part to be round to zero...
19417 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
19420 // Reload the modified control word now...
19421 addFrameReference(BuildMI(*BB, MI, DL,
19422 TII->get(X86::FLDCW16m)), CWFrameIdx);
19424 // Restore the memory image of control word to original value
19425 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
19428 // Get the X86 opcode to use.
19430 switch (MI->getOpcode()) {
19431 default: llvm_unreachable("illegal opcode!");
19432 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
19433 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
19434 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
19435 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
19436 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
19437 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
19438 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
19439 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
19440 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
19444 MachineOperand &Op = MI->getOperand(0);
19446 AM.BaseType = X86AddressMode::RegBase;
19447 AM.Base.Reg = Op.getReg();
19449 AM.BaseType = X86AddressMode::FrameIndexBase;
19450 AM.Base.FrameIndex = Op.getIndex();
19452 Op = MI->getOperand(1);
19454 AM.Scale = Op.getImm();
19455 Op = MI->getOperand(2);
19457 AM.IndexReg = Op.getImm();
19458 Op = MI->getOperand(3);
19459 if (Op.isGlobal()) {
19460 AM.GV = Op.getGlobal();
19462 AM.Disp = Op.getImm();
19464 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
19465 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
19467 // Reload the original control word now.
19468 addFrameReference(BuildMI(*BB, MI, DL,
19469 TII->get(X86::FLDCW16m)), CWFrameIdx);
19471 MI->eraseFromParent(); // The pseudo instruction is gone now.
19474 // String/text processing lowering.
19475 case X86::PCMPISTRM128REG:
19476 case X86::VPCMPISTRM128REG:
19477 case X86::PCMPISTRM128MEM:
19478 case X86::VPCMPISTRM128MEM:
19479 case X86::PCMPESTRM128REG:
19480 case X86::VPCMPESTRM128REG:
19481 case X86::PCMPESTRM128MEM:
19482 case X86::VPCMPESTRM128MEM:
19483 assert(Subtarget->hasSSE42() &&
19484 "Target must have SSE4.2 or AVX features enabled");
19485 return EmitPCMPSTRM(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
19487 // String/text processing lowering.
19488 case X86::PCMPISTRIREG:
19489 case X86::VPCMPISTRIREG:
19490 case X86::PCMPISTRIMEM:
19491 case X86::VPCMPISTRIMEM:
19492 case X86::PCMPESTRIREG:
19493 case X86::VPCMPESTRIREG:
19494 case X86::PCMPESTRIMEM:
19495 case X86::VPCMPESTRIMEM:
19496 assert(Subtarget->hasSSE42() &&
19497 "Target must have SSE4.2 or AVX features enabled");
19498 return EmitPCMPSTRI(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
19500 // Thread synchronization.
19502 return EmitMonitor(MI, BB, BB->getParent()->getSubtarget().getInstrInfo(),
19507 return EmitXBegin(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
19509 case X86::VASTART_SAVE_XMM_REGS:
19510 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
19512 case X86::VAARG_64:
19513 return EmitVAARG64WithCustomInserter(MI, BB);
19515 case X86::EH_SjLj_SetJmp32:
19516 case X86::EH_SjLj_SetJmp64:
19517 return emitEHSjLjSetJmp(MI, BB);
19519 case X86::EH_SjLj_LongJmp32:
19520 case X86::EH_SjLj_LongJmp64:
19521 return emitEHSjLjLongJmp(MI, BB);
19523 case TargetOpcode::STACKMAP:
19524 case TargetOpcode::PATCHPOINT:
19525 return emitPatchPoint(MI, BB);
19527 case X86::VFMADDPDr213r:
19528 case X86::VFMADDPSr213r:
19529 case X86::VFMADDSDr213r:
19530 case X86::VFMADDSSr213r:
19531 case X86::VFMSUBPDr213r:
19532 case X86::VFMSUBPSr213r:
19533 case X86::VFMSUBSDr213r:
19534 case X86::VFMSUBSSr213r:
19535 case X86::VFNMADDPDr213r:
19536 case X86::VFNMADDPSr213r:
19537 case X86::VFNMADDSDr213r:
19538 case X86::VFNMADDSSr213r:
19539 case X86::VFNMSUBPDr213r:
19540 case X86::VFNMSUBPSr213r:
19541 case X86::VFNMSUBSDr213r:
19542 case X86::VFNMSUBSSr213r:
19543 case X86::VFMADDPDr213rY:
19544 case X86::VFMADDPSr213rY:
19545 case X86::VFMSUBPDr213rY:
19546 case X86::VFMSUBPSr213rY:
19547 case X86::VFNMADDPDr213rY:
19548 case X86::VFNMADDPSr213rY:
19549 case X86::VFNMSUBPDr213rY:
19550 case X86::VFNMSUBPSr213rY:
19551 return emitFMA3Instr(MI, BB);
19555 //===----------------------------------------------------------------------===//
19556 // X86 Optimization Hooks
19557 //===----------------------------------------------------------------------===//
19559 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
19562 const SelectionDAG &DAG,
19563 unsigned Depth) const {
19564 unsigned BitWidth = KnownZero.getBitWidth();
19565 unsigned Opc = Op.getOpcode();
19566 assert((Opc >= ISD::BUILTIN_OP_END ||
19567 Opc == ISD::INTRINSIC_WO_CHAIN ||
19568 Opc == ISD::INTRINSIC_W_CHAIN ||
19569 Opc == ISD::INTRINSIC_VOID) &&
19570 "Should use MaskedValueIsZero if you don't know whether Op"
19571 " is a target node!");
19573 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
19587 // These nodes' second result is a boolean.
19588 if (Op.getResNo() == 0)
19591 case X86ISD::SETCC:
19592 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
19594 case ISD::INTRINSIC_WO_CHAIN: {
19595 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
19596 unsigned NumLoBits = 0;
19599 case Intrinsic::x86_sse_movmsk_ps:
19600 case Intrinsic::x86_avx_movmsk_ps_256:
19601 case Intrinsic::x86_sse2_movmsk_pd:
19602 case Intrinsic::x86_avx_movmsk_pd_256:
19603 case Intrinsic::x86_mmx_pmovmskb:
19604 case Intrinsic::x86_sse2_pmovmskb_128:
19605 case Intrinsic::x86_avx2_pmovmskb: {
19606 // High bits of movmskp{s|d}, pmovmskb are known zero.
19608 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
19609 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
19610 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
19611 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
19612 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
19613 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
19614 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
19615 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
19617 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
19626 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
19628 const SelectionDAG &,
19629 unsigned Depth) const {
19630 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
19631 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
19632 return Op.getValueType().getScalarType().getSizeInBits();
19638 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
19639 /// node is a GlobalAddress + offset.
19640 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
19641 const GlobalValue* &GA,
19642 int64_t &Offset) const {
19643 if (N->getOpcode() == X86ISD::Wrapper) {
19644 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
19645 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
19646 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
19650 return TargetLowering::isGAPlusOffset(N, GA, Offset);
19653 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
19654 /// same as extracting the high 128-bit part of 256-bit vector and then
19655 /// inserting the result into the low part of a new 256-bit vector
19656 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
19657 EVT VT = SVOp->getValueType(0);
19658 unsigned NumElems = VT.getVectorNumElements();
19660 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
19661 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
19662 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
19663 SVOp->getMaskElt(j) >= 0)
19669 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
19670 /// same as extracting the low 128-bit part of 256-bit vector and then
19671 /// inserting the result into the high part of a new 256-bit vector
19672 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
19673 EVT VT = SVOp->getValueType(0);
19674 unsigned NumElems = VT.getVectorNumElements();
19676 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
19677 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
19678 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
19679 SVOp->getMaskElt(j) >= 0)
19685 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
19686 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
19687 TargetLowering::DAGCombinerInfo &DCI,
19688 const X86Subtarget* Subtarget) {
19690 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
19691 SDValue V1 = SVOp->getOperand(0);
19692 SDValue V2 = SVOp->getOperand(1);
19693 EVT VT = SVOp->getValueType(0);
19694 unsigned NumElems = VT.getVectorNumElements();
19696 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
19697 V2.getOpcode() == ISD::CONCAT_VECTORS) {
19701 // V UNDEF BUILD_VECTOR UNDEF
19703 // CONCAT_VECTOR CONCAT_VECTOR
19706 // RESULT: V + zero extended
19708 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
19709 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
19710 V1.getOperand(1).getOpcode() != ISD::UNDEF)
19713 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
19716 // To match the shuffle mask, the first half of the mask should
19717 // be exactly the first vector, and all the rest a splat with the
19718 // first element of the second one.
19719 for (unsigned i = 0; i != NumElems/2; ++i)
19720 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
19721 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
19724 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
19725 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
19726 if (Ld->hasNUsesOfValue(1, 0)) {
19727 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
19728 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
19730 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
19732 Ld->getPointerInfo(),
19733 Ld->getAlignment(),
19734 false/*isVolatile*/, true/*ReadMem*/,
19735 false/*WriteMem*/);
19737 // Make sure the newly-created LOAD is in the same position as Ld in
19738 // terms of dependency. We create a TokenFactor for Ld and ResNode,
19739 // and update uses of Ld's output chain to use the TokenFactor.
19740 if (Ld->hasAnyUseOfValue(1)) {
19741 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
19742 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
19743 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
19744 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
19745 SDValue(ResNode.getNode(), 1));
19748 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
19752 // Emit a zeroed vector and insert the desired subvector on its
19754 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
19755 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
19756 return DCI.CombineTo(N, InsV);
19759 //===--------------------------------------------------------------------===//
19760 // Combine some shuffles into subvector extracts and inserts:
19763 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
19764 if (isShuffleHigh128VectorInsertLow(SVOp)) {
19765 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
19766 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
19767 return DCI.CombineTo(N, InsV);
19770 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
19771 if (isShuffleLow128VectorInsertHigh(SVOp)) {
19772 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
19773 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
19774 return DCI.CombineTo(N, InsV);
19780 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
19783 /// This is the leaf of the recursive combinine below. When we have found some
19784 /// chain of single-use x86 shuffle instructions and accumulated the combined
19785 /// shuffle mask represented by them, this will try to pattern match that mask
19786 /// into either a single instruction if there is a special purpose instruction
19787 /// for this operation, or into a PSHUFB instruction which is a fully general
19788 /// instruction but should only be used to replace chains over a certain depth.
19789 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
19790 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
19791 TargetLowering::DAGCombinerInfo &DCI,
19792 const X86Subtarget *Subtarget) {
19793 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
19795 // Find the operand that enters the chain. Note that multiple uses are OK
19796 // here, we're not going to remove the operand we find.
19797 SDValue Input = Op.getOperand(0);
19798 while (Input.getOpcode() == ISD::BITCAST)
19799 Input = Input.getOperand(0);
19801 MVT VT = Input.getSimpleValueType();
19802 MVT RootVT = Root.getSimpleValueType();
19805 // Just remove no-op shuffle masks.
19806 if (Mask.size() == 1) {
19807 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Input),
19812 // Use the float domain if the operand type is a floating point type.
19813 bool FloatDomain = VT.isFloatingPoint();
19815 // For floating point shuffles, we don't have free copies in the shuffle
19816 // instructions or the ability to load as part of the instruction, so
19817 // canonicalize their shuffles to UNPCK or MOV variants.
19819 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
19820 // vectors because it can have a load folded into it that UNPCK cannot. This
19821 // doesn't preclude something switching to the shorter encoding post-RA.
19823 if (Mask.equals(0, 0) || Mask.equals(1, 1)) {
19824 bool Lo = Mask.equals(0, 0);
19827 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
19828 // is no slower than UNPCKLPD but has the option to fold the input operand
19829 // into even an unaligned memory load.
19830 if (Lo && Subtarget->hasSSE3()) {
19831 Shuffle = X86ISD::MOVDDUP;
19832 ShuffleVT = MVT::v2f64;
19834 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
19835 // than the UNPCK variants.
19836 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
19837 ShuffleVT = MVT::v4f32;
19839 if (Depth == 1 && Root->getOpcode() == Shuffle)
19840 return false; // Nothing to do!
19841 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
19842 DCI.AddToWorklist(Op.getNode());
19843 if (Shuffle == X86ISD::MOVDDUP)
19844 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
19846 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
19847 DCI.AddToWorklist(Op.getNode());
19848 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
19852 if (Subtarget->hasSSE3() &&
19853 (Mask.equals(0, 0, 2, 2) || Mask.equals(1, 1, 3, 3))) {
19854 bool Lo = Mask.equals(0, 0, 2, 2);
19855 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
19856 MVT ShuffleVT = MVT::v4f32;
19857 if (Depth == 1 && Root->getOpcode() == Shuffle)
19858 return false; // Nothing to do!
19859 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
19860 DCI.AddToWorklist(Op.getNode());
19861 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
19862 DCI.AddToWorklist(Op.getNode());
19863 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
19867 if (Mask.equals(0, 0, 1, 1) || Mask.equals(2, 2, 3, 3)) {
19868 bool Lo = Mask.equals(0, 0, 1, 1);
19869 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
19870 MVT ShuffleVT = MVT::v4f32;
19871 if (Depth == 1 && Root->getOpcode() == Shuffle)
19872 return false; // Nothing to do!
19873 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
19874 DCI.AddToWorklist(Op.getNode());
19875 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
19876 DCI.AddToWorklist(Op.getNode());
19877 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
19883 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
19884 // variants as none of these have single-instruction variants that are
19885 // superior to the UNPCK formulation.
19886 if (!FloatDomain &&
19887 (Mask.equals(0, 0, 1, 1, 2, 2, 3, 3) ||
19888 Mask.equals(4, 4, 5, 5, 6, 6, 7, 7) ||
19889 Mask.equals(0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7) ||
19890 Mask.equals(8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15,
19892 bool Lo = Mask[0] == 0;
19893 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
19894 if (Depth == 1 && Root->getOpcode() == Shuffle)
19895 return false; // Nothing to do!
19897 switch (Mask.size()) {
19899 ShuffleVT = MVT::v8i16;
19902 ShuffleVT = MVT::v16i8;
19905 llvm_unreachable("Impossible mask size!");
19907 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
19908 DCI.AddToWorklist(Op.getNode());
19909 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
19910 DCI.AddToWorklist(Op.getNode());
19911 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
19916 // Don't try to re-form single instruction chains under any circumstances now
19917 // that we've done encoding canonicalization for them.
19921 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
19922 // can replace them with a single PSHUFB instruction profitably. Intel's
19923 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
19924 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
19925 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
19926 SmallVector<SDValue, 16> PSHUFBMask;
19927 assert(Mask.size() <= 16 && "Can't shuffle elements smaller than bytes!");
19928 int Ratio = 16 / Mask.size();
19929 for (unsigned i = 0; i < 16; ++i) {
19930 int M = Mask[i / Ratio] != SM_SentinelZero
19931 ? Ratio * Mask[i / Ratio] + i % Ratio
19933 PSHUFBMask.push_back(DAG.getConstant(M, MVT::i8));
19935 Op = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Input);
19936 DCI.AddToWorklist(Op.getNode());
19937 SDValue PSHUFBMaskOp =
19938 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, PSHUFBMask);
19939 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
19940 Op = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, Op, PSHUFBMaskOp);
19941 DCI.AddToWorklist(Op.getNode());
19942 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
19947 // Failed to find any combines.
19951 /// \brief Fully generic combining of x86 shuffle instructions.
19953 /// This should be the last combine run over the x86 shuffle instructions. Once
19954 /// they have been fully optimized, this will recursively consider all chains
19955 /// of single-use shuffle instructions, build a generic model of the cumulative
19956 /// shuffle operation, and check for simpler instructions which implement this
19957 /// operation. We use this primarily for two purposes:
19959 /// 1) Collapse generic shuffles to specialized single instructions when
19960 /// equivalent. In most cases, this is just an encoding size win, but
19961 /// sometimes we will collapse multiple generic shuffles into a single
19962 /// special-purpose shuffle.
19963 /// 2) Look for sequences of shuffle instructions with 3 or more total
19964 /// instructions, and replace them with the slightly more expensive SSSE3
19965 /// PSHUFB instruction if available. We do this as the last combining step
19966 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
19967 /// a suitable short sequence of other instructions. The PHUFB will either
19968 /// use a register or have to read from memory and so is slightly (but only
19969 /// slightly) more expensive than the other shuffle instructions.
19971 /// Because this is inherently a quadratic operation (for each shuffle in
19972 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
19973 /// This should never be an issue in practice as the shuffle lowering doesn't
19974 /// produce sequences of more than 8 instructions.
19976 /// FIXME: We will currently miss some cases where the redundant shuffling
19977 /// would simplify under the threshold for PSHUFB formation because of
19978 /// combine-ordering. To fix this, we should do the redundant instruction
19979 /// combining in this recursive walk.
19980 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
19981 ArrayRef<int> RootMask,
19982 int Depth, bool HasPSHUFB,
19984 TargetLowering::DAGCombinerInfo &DCI,
19985 const X86Subtarget *Subtarget) {
19986 // Bound the depth of our recursive combine because this is ultimately
19987 // quadratic in nature.
19991 // Directly rip through bitcasts to find the underlying operand.
19992 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
19993 Op = Op.getOperand(0);
19995 MVT VT = Op.getSimpleValueType();
19996 if (!VT.isVector())
19997 return false; // Bail if we hit a non-vector.
19998 // FIXME: This routine should be taught about 256-bit shuffles, or a 256-bit
19999 // version should be added.
20000 if (VT.getSizeInBits() != 128)
20003 assert(Root.getSimpleValueType().isVector() &&
20004 "Shuffles operate on vector types!");
20005 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
20006 "Can only combine shuffles of the same vector register size.");
20008 if (!isTargetShuffle(Op.getOpcode()))
20010 SmallVector<int, 16> OpMask;
20012 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
20013 // We only can combine unary shuffles which we can decode the mask for.
20014 if (!HaveMask || !IsUnary)
20017 assert(VT.getVectorNumElements() == OpMask.size() &&
20018 "Different mask size from vector size!");
20019 assert(((RootMask.size() > OpMask.size() &&
20020 RootMask.size() % OpMask.size() == 0) ||
20021 (OpMask.size() > RootMask.size() &&
20022 OpMask.size() % RootMask.size() == 0) ||
20023 OpMask.size() == RootMask.size()) &&
20024 "The smaller number of elements must divide the larger.");
20025 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
20026 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
20027 assert(((RootRatio == 1 && OpRatio == 1) ||
20028 (RootRatio == 1) != (OpRatio == 1)) &&
20029 "Must not have a ratio for both incoming and op masks!");
20031 SmallVector<int, 16> Mask;
20032 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
20034 // Merge this shuffle operation's mask into our accumulated mask. Note that
20035 // this shuffle's mask will be the first applied to the input, followed by the
20036 // root mask to get us all the way to the root value arrangement. The reason
20037 // for this order is that we are recursing up the operation chain.
20038 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
20039 int RootIdx = i / RootRatio;
20040 if (RootMask[RootIdx] == SM_SentinelZero) {
20041 // This is a zero-ed lane, we're done.
20042 Mask.push_back(SM_SentinelZero);
20046 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
20047 int OpIdx = RootMaskedIdx / OpRatio;
20048 if (OpMask[OpIdx] == SM_SentinelZero) {
20049 // The incoming lanes are zero, it doesn't matter which ones we are using.
20050 Mask.push_back(SM_SentinelZero);
20054 // Ok, we have non-zero lanes, map them through.
20055 Mask.push_back(OpMask[OpIdx] * OpRatio +
20056 RootMaskedIdx % OpRatio);
20059 // See if we can recurse into the operand to combine more things.
20060 switch (Op.getOpcode()) {
20061 case X86ISD::PSHUFB:
20063 case X86ISD::PSHUFD:
20064 case X86ISD::PSHUFHW:
20065 case X86ISD::PSHUFLW:
20066 if (Op.getOperand(0).hasOneUse() &&
20067 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
20068 HasPSHUFB, DAG, DCI, Subtarget))
20072 case X86ISD::UNPCKL:
20073 case X86ISD::UNPCKH:
20074 assert(Op.getOperand(0) == Op.getOperand(1) && "We only combine unary shuffles!");
20075 // We can't check for single use, we have to check that this shuffle is the only user.
20076 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
20077 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
20078 HasPSHUFB, DAG, DCI, Subtarget))
20083 // Minor canonicalization of the accumulated shuffle mask to make it easier
20084 // to match below. All this does is detect masks with squential pairs of
20085 // elements, and shrink them to the half-width mask. It does this in a loop
20086 // so it will reduce the size of the mask to the minimal width mask which
20087 // performs an equivalent shuffle.
20088 while (Mask.size() > 1 && canWidenShuffleElements(Mask)) {
20089 for (int i = 0, e = Mask.size() / 2; i < e; ++i)
20090 Mask[i] = Mask[2 * i] / 2;
20091 Mask.resize(Mask.size() / 2);
20094 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
20098 /// \brief Get the PSHUF-style mask from PSHUF node.
20100 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
20101 /// PSHUF-style masks that can be reused with such instructions.
20102 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
20103 SmallVector<int, 4> Mask;
20105 bool HaveMask = getTargetShuffleMask(N.getNode(), N.getSimpleValueType(), Mask, IsUnary);
20109 switch (N.getOpcode()) {
20110 case X86ISD::PSHUFD:
20112 case X86ISD::PSHUFLW:
20115 case X86ISD::PSHUFHW:
20116 Mask.erase(Mask.begin(), Mask.begin() + 4);
20117 for (int &M : Mask)
20121 llvm_unreachable("No valid shuffle instruction found!");
20125 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
20127 /// We walk up the chain and look for a combinable shuffle, skipping over
20128 /// shuffles that we could hoist this shuffle's transformation past without
20129 /// altering anything.
20131 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
20133 TargetLowering::DAGCombinerInfo &DCI) {
20134 assert(N.getOpcode() == X86ISD::PSHUFD &&
20135 "Called with something other than an x86 128-bit half shuffle!");
20138 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
20139 // of the shuffles in the chain so that we can form a fresh chain to replace
20141 SmallVector<SDValue, 8> Chain;
20142 SDValue V = N.getOperand(0);
20143 for (; V.hasOneUse(); V = V.getOperand(0)) {
20144 switch (V.getOpcode()) {
20146 return SDValue(); // Nothing combined!
20149 // Skip bitcasts as we always know the type for the target specific
20153 case X86ISD::PSHUFD:
20154 // Found another dword shuffle.
20157 case X86ISD::PSHUFLW:
20158 // Check that the low words (being shuffled) are the identity in the
20159 // dword shuffle, and the high words are self-contained.
20160 if (Mask[0] != 0 || Mask[1] != 1 ||
20161 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
20164 Chain.push_back(V);
20167 case X86ISD::PSHUFHW:
20168 // Check that the high words (being shuffled) are the identity in the
20169 // dword shuffle, and the low words are self-contained.
20170 if (Mask[2] != 2 || Mask[3] != 3 ||
20171 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
20174 Chain.push_back(V);
20177 case X86ISD::UNPCKL:
20178 case X86ISD::UNPCKH:
20179 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
20180 // shuffle into a preceding word shuffle.
20181 if (V.getValueType() != MVT::v16i8 && V.getValueType() != MVT::v8i16)
20184 // Search for a half-shuffle which we can combine with.
20185 unsigned CombineOp =
20186 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
20187 if (V.getOperand(0) != V.getOperand(1) ||
20188 !V->isOnlyUserOf(V.getOperand(0).getNode()))
20190 Chain.push_back(V);
20191 V = V.getOperand(0);
20193 switch (V.getOpcode()) {
20195 return SDValue(); // Nothing to combine.
20197 case X86ISD::PSHUFLW:
20198 case X86ISD::PSHUFHW:
20199 if (V.getOpcode() == CombineOp)
20202 Chain.push_back(V);
20206 V = V.getOperand(0);
20210 } while (V.hasOneUse());
20213 // Break out of the loop if we break out of the switch.
20217 if (!V.hasOneUse())
20218 // We fell out of the loop without finding a viable combining instruction.
20221 // Merge this node's mask and our incoming mask.
20222 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
20223 for (int &M : Mask)
20225 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
20226 getV4X86ShuffleImm8ForMask(Mask, DAG));
20228 // Rebuild the chain around this new shuffle.
20229 while (!Chain.empty()) {
20230 SDValue W = Chain.pop_back_val();
20232 if (V.getValueType() != W.getOperand(0).getValueType())
20233 V = DAG.getNode(ISD::BITCAST, DL, W.getOperand(0).getValueType(), V);
20235 switch (W.getOpcode()) {
20237 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
20239 case X86ISD::UNPCKL:
20240 case X86ISD::UNPCKH:
20241 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
20244 case X86ISD::PSHUFD:
20245 case X86ISD::PSHUFLW:
20246 case X86ISD::PSHUFHW:
20247 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
20251 if (V.getValueType() != N.getValueType())
20252 V = DAG.getNode(ISD::BITCAST, DL, N.getValueType(), V);
20254 // Return the new chain to replace N.
20258 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or pshufhw.
20260 /// We walk up the chain, skipping shuffles of the other half and looking
20261 /// through shuffles which switch halves trying to find a shuffle of the same
20262 /// pair of dwords.
20263 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
20265 TargetLowering::DAGCombinerInfo &DCI) {
20267 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
20268 "Called with something other than an x86 128-bit half shuffle!");
20270 unsigned CombineOpcode = N.getOpcode();
20272 // Walk up a single-use chain looking for a combinable shuffle.
20273 SDValue V = N.getOperand(0);
20274 for (; V.hasOneUse(); V = V.getOperand(0)) {
20275 switch (V.getOpcode()) {
20277 return false; // Nothing combined!
20280 // Skip bitcasts as we always know the type for the target specific
20284 case X86ISD::PSHUFLW:
20285 case X86ISD::PSHUFHW:
20286 if (V.getOpcode() == CombineOpcode)
20289 // Other-half shuffles are no-ops.
20292 // Break out of the loop if we break out of the switch.
20296 if (!V.hasOneUse())
20297 // We fell out of the loop without finding a viable combining instruction.
20300 // Combine away the bottom node as its shuffle will be accumulated into
20301 // a preceding shuffle.
20302 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
20304 // Record the old value.
20307 // Merge this node's mask and our incoming mask (adjusted to account for all
20308 // the pshufd instructions encountered).
20309 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
20310 for (int &M : Mask)
20312 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
20313 getV4X86ShuffleImm8ForMask(Mask, DAG));
20315 // Check that the shuffles didn't cancel each other out. If not, we need to
20316 // combine to the new one.
20318 // Replace the combinable shuffle with the combined one, updating all users
20319 // so that we re-evaluate the chain here.
20320 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
20325 /// \brief Try to combine x86 target specific shuffles.
20326 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
20327 TargetLowering::DAGCombinerInfo &DCI,
20328 const X86Subtarget *Subtarget) {
20330 MVT VT = N.getSimpleValueType();
20331 SmallVector<int, 4> Mask;
20333 switch (N.getOpcode()) {
20334 case X86ISD::PSHUFD:
20335 case X86ISD::PSHUFLW:
20336 case X86ISD::PSHUFHW:
20337 Mask = getPSHUFShuffleMask(N);
20338 assert(Mask.size() == 4);
20344 // Nuke no-op shuffles that show up after combining.
20345 if (isNoopShuffleMask(Mask))
20346 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
20348 // Look for simplifications involving one or two shuffle instructions.
20349 SDValue V = N.getOperand(0);
20350 switch (N.getOpcode()) {
20353 case X86ISD::PSHUFLW:
20354 case X86ISD::PSHUFHW:
20355 assert(VT == MVT::v8i16);
20358 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
20359 return SDValue(); // We combined away this shuffle, so we're done.
20361 // See if this reduces to a PSHUFD which is no more expensive and can
20362 // combine with more operations.
20363 if (canWidenShuffleElements(Mask)) {
20364 int DMask[] = {-1, -1, -1, -1};
20365 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
20366 DMask[DOffset + 0] = DOffset + Mask[0] / 2;
20367 DMask[DOffset + 1] = DOffset + Mask[2] / 2;
20368 V = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V);
20369 DCI.AddToWorklist(V.getNode());
20370 V = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V,
20371 getV4X86ShuffleImm8ForMask(DMask, DAG));
20372 DCI.AddToWorklist(V.getNode());
20373 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
20376 // Look for shuffle patterns which can be implemented as a single unpack.
20377 // FIXME: This doesn't handle the location of the PSHUFD generically, and
20378 // only works when we have a PSHUFD followed by two half-shuffles.
20379 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
20380 (V.getOpcode() == X86ISD::PSHUFLW ||
20381 V.getOpcode() == X86ISD::PSHUFHW) &&
20382 V.getOpcode() != N.getOpcode() &&
20384 SDValue D = V.getOperand(0);
20385 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
20386 D = D.getOperand(0);
20387 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
20388 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
20389 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
20390 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
20391 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
20393 for (int i = 0; i < 4; ++i) {
20394 WordMask[i + NOffset] = Mask[i] + NOffset;
20395 WordMask[i + VOffset] = VMask[i] + VOffset;
20397 // Map the word mask through the DWord mask.
20399 for (int i = 0; i < 8; ++i)
20400 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
20401 const int UnpackLoMask[] = {0, 0, 1, 1, 2, 2, 3, 3};
20402 const int UnpackHiMask[] = {4, 4, 5, 5, 6, 6, 7, 7};
20403 if (std::equal(std::begin(MappedMask), std::end(MappedMask),
20404 std::begin(UnpackLoMask)) ||
20405 std::equal(std::begin(MappedMask), std::end(MappedMask),
20406 std::begin(UnpackHiMask))) {
20407 // We can replace all three shuffles with an unpack.
20408 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, D.getOperand(0));
20409 DCI.AddToWorklist(V.getNode());
20410 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
20412 DL, MVT::v8i16, V, V);
20419 case X86ISD::PSHUFD:
20420 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
20429 /// \brief Try to combine a shuffle into a target-specific add-sub node.
20431 /// We combine this directly on the abstract vector shuffle nodes so it is
20432 /// easier to generically match. We also insert dummy vector shuffle nodes for
20433 /// the operands which explicitly discard the lanes which are unused by this
20434 /// operation to try to flow through the rest of the combiner the fact that
20435 /// they're unused.
20436 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
20438 EVT VT = N->getValueType(0);
20440 // We only handle target-independent shuffles.
20441 // FIXME: It would be easy and harmless to use the target shuffle mask
20442 // extraction tool to support more.
20443 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
20446 auto *SVN = cast<ShuffleVectorSDNode>(N);
20447 ArrayRef<int> Mask = SVN->getMask();
20448 SDValue V1 = N->getOperand(0);
20449 SDValue V2 = N->getOperand(1);
20451 // We require the first shuffle operand to be the SUB node, and the second to
20452 // be the ADD node.
20453 // FIXME: We should support the commuted patterns.
20454 if (V1->getOpcode() != ISD::FSUB || V2->getOpcode() != ISD::FADD)
20457 // If there are other uses of these operations we can't fold them.
20458 if (!V1->hasOneUse() || !V2->hasOneUse())
20461 // Ensure that both operations have the same operands. Note that we can
20462 // commute the FADD operands.
20463 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
20464 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
20465 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
20468 // We're looking for blends between FADD and FSUB nodes. We insist on these
20469 // nodes being lined up in a specific expected pattern.
20470 if (!(isShuffleEquivalent(Mask, 0, 3) ||
20471 isShuffleEquivalent(Mask, 0, 5, 2, 7) ||
20472 isShuffleEquivalent(Mask, 0, 9, 2, 11, 4, 13, 6, 15)))
20475 // Only specific types are legal at this point, assert so we notice if and
20476 // when these change.
20477 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
20478 VT == MVT::v4f64) &&
20479 "Unknown vector type encountered!");
20481 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
20484 /// PerformShuffleCombine - Performs several different shuffle combines.
20485 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
20486 TargetLowering::DAGCombinerInfo &DCI,
20487 const X86Subtarget *Subtarget) {
20489 SDValue N0 = N->getOperand(0);
20490 SDValue N1 = N->getOperand(1);
20491 EVT VT = N->getValueType(0);
20493 // Don't create instructions with illegal types after legalize types has run.
20494 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20495 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
20498 // If we have legalized the vector types, look for blends of FADD and FSUB
20499 // nodes that we can fuse into an ADDSUB node.
20500 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
20501 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
20504 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
20505 if (Subtarget->hasFp256() && VT.is256BitVector() &&
20506 N->getOpcode() == ISD::VECTOR_SHUFFLE)
20507 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
20509 // During Type Legalization, when promoting illegal vector types,
20510 // the backend might introduce new shuffle dag nodes and bitcasts.
20512 // This code performs the following transformation:
20513 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
20514 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
20516 // We do this only if both the bitcast and the BINOP dag nodes have
20517 // one use. Also, perform this transformation only if the new binary
20518 // operation is legal. This is to avoid introducing dag nodes that
20519 // potentially need to be further expanded (or custom lowered) into a
20520 // less optimal sequence of dag nodes.
20521 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
20522 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
20523 N0.getOpcode() == ISD::BITCAST) {
20524 SDValue BC0 = N0.getOperand(0);
20525 EVT SVT = BC0.getValueType();
20526 unsigned Opcode = BC0.getOpcode();
20527 unsigned NumElts = VT.getVectorNumElements();
20529 if (BC0.hasOneUse() && SVT.isVector() &&
20530 SVT.getVectorNumElements() * 2 == NumElts &&
20531 TLI.isOperationLegal(Opcode, VT)) {
20532 bool CanFold = false;
20544 unsigned SVTNumElts = SVT.getVectorNumElements();
20545 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
20546 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
20547 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
20548 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
20549 CanFold = SVOp->getMaskElt(i) < 0;
20552 SDValue BC00 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(0));
20553 SDValue BC01 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(1));
20554 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
20555 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
20560 // Only handle 128 wide vector from here on.
20561 if (!VT.is128BitVector())
20564 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
20565 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
20566 // consecutive, non-overlapping, and in the right order.
20567 SmallVector<SDValue, 16> Elts;
20568 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
20569 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
20571 SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true);
20575 if (isTargetShuffle(N->getOpcode())) {
20577 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
20578 if (Shuffle.getNode())
20581 // Try recursively combining arbitrary sequences of x86 shuffle
20582 // instructions into higher-order shuffles. We do this after combining
20583 // specific PSHUF instruction sequences into their minimal form so that we
20584 // can evaluate how many specialized shuffle instructions are involved in
20585 // a particular chain.
20586 SmallVector<int, 1> NonceMask; // Just a placeholder.
20587 NonceMask.push_back(0);
20588 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
20589 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
20591 return SDValue(); // This routine will use CombineTo to replace N.
20597 /// PerformTruncateCombine - Converts truncate operation to
20598 /// a sequence of vector shuffle operations.
20599 /// It is possible when we truncate 256-bit vector to 128-bit vector
20600 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
20601 TargetLowering::DAGCombinerInfo &DCI,
20602 const X86Subtarget *Subtarget) {
20606 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
20607 /// specific shuffle of a load can be folded into a single element load.
20608 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
20609 /// shuffles have been customed lowered so we need to handle those here.
20610 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
20611 TargetLowering::DAGCombinerInfo &DCI) {
20612 if (DCI.isBeforeLegalizeOps())
20615 SDValue InVec = N->getOperand(0);
20616 SDValue EltNo = N->getOperand(1);
20618 if (!isa<ConstantSDNode>(EltNo))
20621 EVT VT = InVec.getValueType();
20623 if (InVec.getOpcode() == ISD::BITCAST) {
20624 // Don't duplicate a load with other uses.
20625 if (!InVec.hasOneUse())
20627 EVT BCVT = InVec.getOperand(0).getValueType();
20628 if (BCVT.getVectorNumElements() != VT.getVectorNumElements())
20630 InVec = InVec.getOperand(0);
20633 if (!isTargetShuffle(InVec.getOpcode()))
20636 // Don't duplicate a load with other uses.
20637 if (!InVec.hasOneUse())
20640 SmallVector<int, 16> ShuffleMask;
20642 if (!getTargetShuffleMask(InVec.getNode(), VT.getSimpleVT(), ShuffleMask,
20646 // Select the input vector, guarding against out of range extract vector.
20647 unsigned NumElems = VT.getVectorNumElements();
20648 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
20649 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
20650 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
20651 : InVec.getOperand(1);
20653 // If inputs to shuffle are the same for both ops, then allow 2 uses
20654 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
20656 if (LdNode.getOpcode() == ISD::BITCAST) {
20657 // Don't duplicate a load with other uses.
20658 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
20661 AllowedUses = 1; // only allow 1 load use if we have a bitcast
20662 LdNode = LdNode.getOperand(0);
20665 if (!ISD::isNormalLoad(LdNode.getNode()))
20668 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
20670 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
20673 EVT EltVT = N->getValueType(0);
20674 // If there's a bitcast before the shuffle, check if the load type and
20675 // alignment is valid.
20676 unsigned Align = LN0->getAlignment();
20677 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20678 unsigned NewAlign = TLI.getDataLayout()->getABITypeAlignment(
20679 EltVT.getTypeForEVT(*DAG.getContext()));
20681 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
20684 // All checks match so transform back to vector_shuffle so that DAG combiner
20685 // can finish the job
20688 // Create shuffle node taking into account the case that its a unary shuffle
20689 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1);
20690 Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl,
20691 InVec.getOperand(0), Shuffle,
20693 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
20694 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
20698 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
20699 /// generation and convert it from being a bunch of shuffles and extracts
20700 /// to a simple store and scalar loads to extract the elements.
20701 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
20702 TargetLowering::DAGCombinerInfo &DCI) {
20703 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
20704 if (NewOp.getNode())
20707 SDValue InputVector = N->getOperand(0);
20709 // Detect whether we are trying to convert from mmx to i32 and the bitcast
20710 // from mmx to v2i32 has a single usage.
20711 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
20712 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
20713 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
20714 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
20715 N->getValueType(0),
20716 InputVector.getNode()->getOperand(0));
20718 // Only operate on vectors of 4 elements, where the alternative shuffling
20719 // gets to be more expensive.
20720 if (InputVector.getValueType() != MVT::v4i32)
20723 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
20724 // single use which is a sign-extend or zero-extend, and all elements are
20726 SmallVector<SDNode *, 4> Uses;
20727 unsigned ExtractedElements = 0;
20728 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
20729 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
20730 if (UI.getUse().getResNo() != InputVector.getResNo())
20733 SDNode *Extract = *UI;
20734 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
20737 if (Extract->getValueType(0) != MVT::i32)
20739 if (!Extract->hasOneUse())
20741 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
20742 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
20744 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
20747 // Record which element was extracted.
20748 ExtractedElements |=
20749 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
20751 Uses.push_back(Extract);
20754 // If not all the elements were used, this may not be worthwhile.
20755 if (ExtractedElements != 15)
20758 // Ok, we've now decided to do the transformation.
20759 SDLoc dl(InputVector);
20761 // Store the value to a temporary stack slot.
20762 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
20763 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
20764 MachinePointerInfo(), false, false, 0);
20766 // Replace each use (extract) with a load of the appropriate element.
20767 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
20768 UE = Uses.end(); UI != UE; ++UI) {
20769 SDNode *Extract = *UI;
20771 // cOMpute the element's address.
20772 SDValue Idx = Extract->getOperand(1);
20774 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
20775 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
20776 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20777 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
20779 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
20780 StackPtr, OffsetVal);
20782 // Load the scalar.
20783 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
20784 ScalarAddr, MachinePointerInfo(),
20785 false, false, false, 0);
20787 // Replace the exact with the load.
20788 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
20791 // The replacement was made in place; don't return anything.
20795 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
20796 static std::pair<unsigned, bool>
20797 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
20798 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
20799 if (!VT.isVector())
20800 return std::make_pair(0, false);
20802 bool NeedSplit = false;
20803 switch (VT.getSimpleVT().SimpleTy) {
20804 default: return std::make_pair(0, false);
20808 if (!Subtarget->hasAVX2())
20810 if (!Subtarget->hasAVX())
20811 return std::make_pair(0, false);
20816 if (!Subtarget->hasSSE2())
20817 return std::make_pair(0, false);
20820 // SSE2 has only a small subset of the operations.
20821 bool hasUnsigned = Subtarget->hasSSE41() ||
20822 (Subtarget->hasSSE2() && VT == MVT::v16i8);
20823 bool hasSigned = Subtarget->hasSSE41() ||
20824 (Subtarget->hasSSE2() && VT == MVT::v8i16);
20826 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
20829 // Check for x CC y ? x : y.
20830 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
20831 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
20836 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
20839 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
20842 Opc = hasSigned ? X86ISD::SMIN : 0; break;
20845 Opc = hasSigned ? X86ISD::SMAX : 0; break;
20847 // Check for x CC y ? y : x -- a min/max with reversed arms.
20848 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
20849 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
20854 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
20857 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
20860 Opc = hasSigned ? X86ISD::SMAX : 0; break;
20863 Opc = hasSigned ? X86ISD::SMIN : 0; break;
20867 return std::make_pair(Opc, NeedSplit);
20871 TransformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
20872 const X86Subtarget *Subtarget) {
20874 SDValue Cond = N->getOperand(0);
20875 SDValue LHS = N->getOperand(1);
20876 SDValue RHS = N->getOperand(2);
20878 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
20879 SDValue CondSrc = Cond->getOperand(0);
20880 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
20881 Cond = CondSrc->getOperand(0);
20884 MVT VT = N->getSimpleValueType(0);
20885 MVT EltVT = VT.getVectorElementType();
20886 unsigned NumElems = VT.getVectorNumElements();
20887 // There is no blend with immediate in AVX-512.
20888 if (VT.is512BitVector())
20891 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
20893 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
20896 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
20899 // A vselect where all conditions and data are constants can be optimized into
20900 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
20901 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
20902 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
20905 unsigned MaskValue = 0;
20906 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
20909 SmallVector<int, 8> ShuffleMask(NumElems, -1);
20910 for (unsigned i = 0; i < NumElems; ++i) {
20911 // Be sure we emit undef where we can.
20912 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
20913 ShuffleMask[i] = -1;
20915 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
20918 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
20921 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
20923 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
20924 TargetLowering::DAGCombinerInfo &DCI,
20925 const X86Subtarget *Subtarget) {
20927 SDValue Cond = N->getOperand(0);
20928 // Get the LHS/RHS of the select.
20929 SDValue LHS = N->getOperand(1);
20930 SDValue RHS = N->getOperand(2);
20931 EVT VT = LHS.getValueType();
20932 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20934 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
20935 // instructions match the semantics of the common C idiom x<y?x:y but not
20936 // x<=y?x:y, because of how they handle negative zero (which can be
20937 // ignored in unsafe-math mode).
20938 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
20939 VT != MVT::f80 && TLI.isTypeLegal(VT) &&
20940 (Subtarget->hasSSE2() ||
20941 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
20942 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
20944 unsigned Opcode = 0;
20945 // Check for x CC y ? x : y.
20946 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
20947 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
20951 // Converting this to a min would handle NaNs incorrectly, and swapping
20952 // the operands would cause it to handle comparisons between positive
20953 // and negative zero incorrectly.
20954 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
20955 if (!DAG.getTarget().Options.UnsafeFPMath &&
20956 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
20958 std::swap(LHS, RHS);
20960 Opcode = X86ISD::FMIN;
20963 // Converting this to a min would handle comparisons between positive
20964 // and negative zero incorrectly.
20965 if (!DAG.getTarget().Options.UnsafeFPMath &&
20966 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
20968 Opcode = X86ISD::FMIN;
20971 // Converting this to a min would handle both negative zeros and NaNs
20972 // incorrectly, but we can swap the operands to fix both.
20973 std::swap(LHS, RHS);
20977 Opcode = X86ISD::FMIN;
20981 // Converting this to a max would handle comparisons between positive
20982 // and negative zero incorrectly.
20983 if (!DAG.getTarget().Options.UnsafeFPMath &&
20984 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
20986 Opcode = X86ISD::FMAX;
20989 // Converting this to a max would handle NaNs incorrectly, and swapping
20990 // the operands would cause it to handle comparisons between positive
20991 // and negative zero incorrectly.
20992 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
20993 if (!DAG.getTarget().Options.UnsafeFPMath &&
20994 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
20996 std::swap(LHS, RHS);
20998 Opcode = X86ISD::FMAX;
21001 // Converting this to a max would handle both negative zeros and NaNs
21002 // incorrectly, but we can swap the operands to fix both.
21003 std::swap(LHS, RHS);
21007 Opcode = X86ISD::FMAX;
21010 // Check for x CC y ? y : x -- a min/max with reversed arms.
21011 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
21012 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
21016 // Converting this to a min would handle comparisons between positive
21017 // and negative zero incorrectly, and swapping the operands would
21018 // cause it to handle NaNs incorrectly.
21019 if (!DAG.getTarget().Options.UnsafeFPMath &&
21020 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
21021 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
21023 std::swap(LHS, RHS);
21025 Opcode = X86ISD::FMIN;
21028 // Converting this to a min would handle NaNs incorrectly.
21029 if (!DAG.getTarget().Options.UnsafeFPMath &&
21030 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
21032 Opcode = X86ISD::FMIN;
21035 // Converting this to a min would handle both negative zeros and NaNs
21036 // incorrectly, but we can swap the operands to fix both.
21037 std::swap(LHS, RHS);
21041 Opcode = X86ISD::FMIN;
21045 // Converting this to a max would handle NaNs incorrectly.
21046 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
21048 Opcode = X86ISD::FMAX;
21051 // Converting this to a max would handle comparisons between positive
21052 // and negative zero incorrectly, and swapping the operands would
21053 // cause it to handle NaNs incorrectly.
21054 if (!DAG.getTarget().Options.UnsafeFPMath &&
21055 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
21056 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
21058 std::swap(LHS, RHS);
21060 Opcode = X86ISD::FMAX;
21063 // Converting this to a max would handle both negative zeros and NaNs
21064 // incorrectly, but we can swap the operands to fix both.
21065 std::swap(LHS, RHS);
21069 Opcode = X86ISD::FMAX;
21075 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
21078 EVT CondVT = Cond.getValueType();
21079 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
21080 CondVT.getVectorElementType() == MVT::i1) {
21081 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
21082 // lowering on KNL. In this case we convert it to
21083 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
21084 // The same situation for all 128 and 256-bit vectors of i8 and i16.
21085 // Since SKX these selects have a proper lowering.
21086 EVT OpVT = LHS.getValueType();
21087 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
21088 (OpVT.getVectorElementType() == MVT::i8 ||
21089 OpVT.getVectorElementType() == MVT::i16) &&
21090 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
21091 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
21092 DCI.AddToWorklist(Cond.getNode());
21093 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
21096 // If this is a select between two integer constants, try to do some
21098 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
21099 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
21100 // Don't do this for crazy integer types.
21101 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
21102 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
21103 // so that TrueC (the true value) is larger than FalseC.
21104 bool NeedsCondInvert = false;
21106 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
21107 // Efficiently invertible.
21108 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
21109 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
21110 isa<ConstantSDNode>(Cond.getOperand(1))))) {
21111 NeedsCondInvert = true;
21112 std::swap(TrueC, FalseC);
21115 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
21116 if (FalseC->getAPIntValue() == 0 &&
21117 TrueC->getAPIntValue().isPowerOf2()) {
21118 if (NeedsCondInvert) // Invert the condition if needed.
21119 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
21120 DAG.getConstant(1, Cond.getValueType()));
21122 // Zero extend the condition if needed.
21123 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
21125 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
21126 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
21127 DAG.getConstant(ShAmt, MVT::i8));
21130 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
21131 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
21132 if (NeedsCondInvert) // Invert the condition if needed.
21133 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
21134 DAG.getConstant(1, Cond.getValueType()));
21136 // Zero extend the condition if needed.
21137 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
21138 FalseC->getValueType(0), Cond);
21139 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
21140 SDValue(FalseC, 0));
21143 // Optimize cases that will turn into an LEA instruction. This requires
21144 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
21145 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
21146 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
21147 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
21149 bool isFastMultiplier = false;
21151 switch ((unsigned char)Diff) {
21153 case 1: // result = add base, cond
21154 case 2: // result = lea base( , cond*2)
21155 case 3: // result = lea base(cond, cond*2)
21156 case 4: // result = lea base( , cond*4)
21157 case 5: // result = lea base(cond, cond*4)
21158 case 8: // result = lea base( , cond*8)
21159 case 9: // result = lea base(cond, cond*8)
21160 isFastMultiplier = true;
21165 if (isFastMultiplier) {
21166 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
21167 if (NeedsCondInvert) // Invert the condition if needed.
21168 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
21169 DAG.getConstant(1, Cond.getValueType()));
21171 // Zero extend the condition if needed.
21172 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
21174 // Scale the condition by the difference.
21176 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
21177 DAG.getConstant(Diff, Cond.getValueType()));
21179 // Add the base if non-zero.
21180 if (FalseC->getAPIntValue() != 0)
21181 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
21182 SDValue(FalseC, 0));
21189 // Canonicalize max and min:
21190 // (x > y) ? x : y -> (x >= y) ? x : y
21191 // (x < y) ? x : y -> (x <= y) ? x : y
21192 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
21193 // the need for an extra compare
21194 // against zero. e.g.
21195 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
21197 // testl %edi, %edi
21199 // cmovgl %edi, %eax
21203 // cmovsl %eax, %edi
21204 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
21205 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
21206 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
21207 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21212 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
21213 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
21214 Cond.getOperand(0), Cond.getOperand(1), NewCC);
21215 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
21220 // Early exit check
21221 if (!TLI.isTypeLegal(VT))
21224 // Match VSELECTs into subs with unsigned saturation.
21225 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
21226 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
21227 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
21228 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
21229 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21231 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
21232 // left side invert the predicate to simplify logic below.
21234 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
21236 CC = ISD::getSetCCInverse(CC, true);
21237 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
21241 if (Other.getNode() && Other->getNumOperands() == 2 &&
21242 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
21243 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
21244 SDValue CondRHS = Cond->getOperand(1);
21246 // Look for a general sub with unsigned saturation first.
21247 // x >= y ? x-y : 0 --> subus x, y
21248 // x > y ? x-y : 0 --> subus x, y
21249 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
21250 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
21251 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
21253 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
21254 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
21255 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
21256 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
21257 // If the RHS is a constant we have to reverse the const
21258 // canonicalization.
21259 // x > C-1 ? x+-C : 0 --> subus x, C
21260 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
21261 CondRHSConst->getAPIntValue() ==
21262 (-OpRHSConst->getAPIntValue() - 1))
21263 return DAG.getNode(
21264 X86ISD::SUBUS, DL, VT, OpLHS,
21265 DAG.getConstant(-OpRHSConst->getAPIntValue(), VT));
21267 // Another special case: If C was a sign bit, the sub has been
21268 // canonicalized into a xor.
21269 // FIXME: Would it be better to use computeKnownBits to determine
21270 // whether it's safe to decanonicalize the xor?
21271 // x s< 0 ? x^C : 0 --> subus x, C
21272 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
21273 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
21274 OpRHSConst->getAPIntValue().isSignBit())
21275 // Note that we have to rebuild the RHS constant here to ensure we
21276 // don't rely on particular values of undef lanes.
21277 return DAG.getNode(
21278 X86ISD::SUBUS, DL, VT, OpLHS,
21279 DAG.getConstant(OpRHSConst->getAPIntValue(), VT));
21284 // Try to match a min/max vector operation.
21285 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
21286 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
21287 unsigned Opc = ret.first;
21288 bool NeedSplit = ret.second;
21290 if (Opc && NeedSplit) {
21291 unsigned NumElems = VT.getVectorNumElements();
21292 // Extract the LHS vectors
21293 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
21294 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
21296 // Extract the RHS vectors
21297 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
21298 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
21300 // Create min/max for each subvector
21301 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
21302 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
21304 // Merge the result
21305 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
21307 return DAG.getNode(Opc, DL, VT, LHS, RHS);
21310 // Simplify vector selection if the selector will be produced by CMPP*/PCMP*.
21311 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
21312 // Check if SETCC has already been promoted
21313 TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT &&
21314 // Check that condition value type matches vselect operand type
21317 assert(Cond.getValueType().isVector() &&
21318 "vector select expects a vector selector!");
21320 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
21321 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
21323 if (!TValIsAllOnes && !FValIsAllZeros) {
21324 // Try invert the condition if true value is not all 1s and false value
21326 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
21327 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
21329 if (TValIsAllZeros || FValIsAllOnes) {
21330 SDValue CC = Cond.getOperand(2);
21331 ISD::CondCode NewCC =
21332 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
21333 Cond.getOperand(0).getValueType().isInteger());
21334 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
21335 std::swap(LHS, RHS);
21336 TValIsAllOnes = FValIsAllOnes;
21337 FValIsAllZeros = TValIsAllZeros;
21341 if (TValIsAllOnes || FValIsAllZeros) {
21344 if (TValIsAllOnes && FValIsAllZeros)
21346 else if (TValIsAllOnes)
21347 Ret = DAG.getNode(ISD::OR, DL, CondVT, Cond,
21348 DAG.getNode(ISD::BITCAST, DL, CondVT, RHS));
21349 else if (FValIsAllZeros)
21350 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
21351 DAG.getNode(ISD::BITCAST, DL, CondVT, LHS));
21353 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
21357 // Try to fold this VSELECT into a MOVSS/MOVSD
21358 if (N->getOpcode() == ISD::VSELECT &&
21359 Cond.getOpcode() == ISD::BUILD_VECTOR && !DCI.isBeforeLegalize()) {
21360 if (VT == MVT::v4i32 || VT == MVT::v4f32 ||
21361 (Subtarget->hasSSE2() && (VT == MVT::v2i64 || VT == MVT::v2f64))) {
21362 bool CanFold = false;
21363 unsigned NumElems = Cond.getNumOperands();
21367 if (isZero(Cond.getOperand(0))) {
21370 // fold (vselect <0,-1,-1,-1>, A, B) -> (movss A, B)
21371 // fold (vselect <0,-1> -> (movsd A, B)
21372 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
21373 CanFold = isAllOnes(Cond.getOperand(i));
21374 } else if (isAllOnes(Cond.getOperand(0))) {
21378 // fold (vselect <-1,0,0,0>, A, B) -> (movss B, A)
21379 // fold (vselect <-1,0> -> (movsd B, A)
21380 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
21381 CanFold = isZero(Cond.getOperand(i));
21385 if (VT == MVT::v4i32 || VT == MVT::v4f32)
21386 return getTargetShuffleNode(X86ISD::MOVSS, DL, VT, A, B, DAG);
21387 return getTargetShuffleNode(X86ISD::MOVSD, DL, VT, A, B, DAG);
21390 if (Subtarget->hasSSE2() && (VT == MVT::v4i32 || VT == MVT::v4f32)) {
21391 // fold (v4i32: vselect <0,0,-1,-1>, A, B) ->
21392 // (v4i32 (bitcast (movsd (v2i64 (bitcast A)),
21393 // (v2i64 (bitcast B)))))
21395 // fold (v4f32: vselect <0,0,-1,-1>, A, B) ->
21396 // (v4f32 (bitcast (movsd (v2f64 (bitcast A)),
21397 // (v2f64 (bitcast B)))))
21399 // fold (v4i32: vselect <-1,-1,0,0>, A, B) ->
21400 // (v4i32 (bitcast (movsd (v2i64 (bitcast B)),
21401 // (v2i64 (bitcast A)))))
21403 // fold (v4f32: vselect <-1,-1,0,0>, A, B) ->
21404 // (v4f32 (bitcast (movsd (v2f64 (bitcast B)),
21405 // (v2f64 (bitcast A)))))
21407 CanFold = (isZero(Cond.getOperand(0)) &&
21408 isZero(Cond.getOperand(1)) &&
21409 isAllOnes(Cond.getOperand(2)) &&
21410 isAllOnes(Cond.getOperand(3)));
21412 if (!CanFold && isAllOnes(Cond.getOperand(0)) &&
21413 isAllOnes(Cond.getOperand(1)) &&
21414 isZero(Cond.getOperand(2)) &&
21415 isZero(Cond.getOperand(3))) {
21417 std::swap(LHS, RHS);
21421 EVT NVT = (VT == MVT::v4i32) ? MVT::v2i64 : MVT::v2f64;
21422 SDValue NewA = DAG.getNode(ISD::BITCAST, DL, NVT, LHS);
21423 SDValue NewB = DAG.getNode(ISD::BITCAST, DL, NVT, RHS);
21424 SDValue Select = getTargetShuffleNode(X86ISD::MOVSD, DL, NVT, NewA,
21426 return DAG.getNode(ISD::BITCAST, DL, VT, Select);
21432 // If we know that this node is legal then we know that it is going to be
21433 // matched by one of the SSE/AVX BLEND instructions. These instructions only
21434 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
21435 // to simplify previous instructions.
21436 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
21437 !DCI.isBeforeLegalize() &&
21438 // We explicitly check against v8i16 and v16i16 because, although
21439 // they're marked as Custom, they might only be legal when Cond is a
21440 // build_vector of constants. This will be taken care in a later
21442 (TLI.isOperationLegalOrCustom(ISD::VSELECT, VT) && VT != MVT::v16i16 &&
21443 VT != MVT::v8i16)) {
21444 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
21446 // Don't optimize vector selects that map to mask-registers.
21450 // Check all uses of that condition operand to check whether it will be
21451 // consumed by non-BLEND instructions, which may depend on all bits are set
21453 for (SDNode::use_iterator I = Cond->use_begin(),
21454 E = Cond->use_end(); I != E; ++I)
21455 if (I->getOpcode() != ISD::VSELECT)
21456 // TODO: Add other opcodes eventually lowered into BLEND.
21459 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
21460 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
21462 APInt KnownZero, KnownOne;
21463 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
21464 DCI.isBeforeLegalizeOps());
21465 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
21466 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO))
21467 DCI.CommitTargetLoweringOpt(TLO);
21470 // We should generate an X86ISD::BLENDI from a vselect if its argument
21471 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
21472 // constants. This specific pattern gets generated when we split a
21473 // selector for a 512 bit vector in a machine without AVX512 (but with
21474 // 256-bit vectors), during legalization:
21476 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
21478 // Iff we find this pattern and the build_vectors are built from
21479 // constants, we translate the vselect into a shuffle_vector that we
21480 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
21481 if (N->getOpcode() == ISD::VSELECT && !DCI.isBeforeLegalize()) {
21482 SDValue Shuffle = TransformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
21483 if (Shuffle.getNode())
21490 // Check whether a boolean test is testing a boolean value generated by
21491 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
21494 // Simplify the following patterns:
21495 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
21496 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
21497 // to (Op EFLAGS Cond)
21499 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
21500 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
21501 // to (Op EFLAGS !Cond)
21503 // where Op could be BRCOND or CMOV.
21505 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
21506 // Quit if not CMP and SUB with its value result used.
21507 if (Cmp.getOpcode() != X86ISD::CMP &&
21508 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
21511 // Quit if not used as a boolean value.
21512 if (CC != X86::COND_E && CC != X86::COND_NE)
21515 // Check CMP operands. One of them should be 0 or 1 and the other should be
21516 // an SetCC or extended from it.
21517 SDValue Op1 = Cmp.getOperand(0);
21518 SDValue Op2 = Cmp.getOperand(1);
21521 const ConstantSDNode* C = nullptr;
21522 bool needOppositeCond = (CC == X86::COND_E);
21523 bool checkAgainstTrue = false; // Is it a comparison against 1?
21525 if ((C = dyn_cast<ConstantSDNode>(Op1)))
21527 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
21529 else // Quit if all operands are not constants.
21532 if (C->getZExtValue() == 1) {
21533 needOppositeCond = !needOppositeCond;
21534 checkAgainstTrue = true;
21535 } else if (C->getZExtValue() != 0)
21536 // Quit if the constant is neither 0 or 1.
21539 bool truncatedToBoolWithAnd = false;
21540 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
21541 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
21542 SetCC.getOpcode() == ISD::TRUNCATE ||
21543 SetCC.getOpcode() == ISD::AND) {
21544 if (SetCC.getOpcode() == ISD::AND) {
21546 ConstantSDNode *CS;
21547 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
21548 CS->getZExtValue() == 1)
21550 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
21551 CS->getZExtValue() == 1)
21555 SetCC = SetCC.getOperand(OpIdx);
21556 truncatedToBoolWithAnd = true;
21558 SetCC = SetCC.getOperand(0);
21561 switch (SetCC.getOpcode()) {
21562 case X86ISD::SETCC_CARRY:
21563 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
21564 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
21565 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
21566 // truncated to i1 using 'and'.
21567 if (checkAgainstTrue && !truncatedToBoolWithAnd)
21569 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
21570 "Invalid use of SETCC_CARRY!");
21572 case X86ISD::SETCC:
21573 // Set the condition code or opposite one if necessary.
21574 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
21575 if (needOppositeCond)
21576 CC = X86::GetOppositeBranchCondition(CC);
21577 return SetCC.getOperand(1);
21578 case X86ISD::CMOV: {
21579 // Check whether false/true value has canonical one, i.e. 0 or 1.
21580 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
21581 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
21582 // Quit if true value is not a constant.
21585 // Quit if false value is not a constant.
21587 SDValue Op = SetCC.getOperand(0);
21588 // Skip 'zext' or 'trunc' node.
21589 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
21590 Op.getOpcode() == ISD::TRUNCATE)
21591 Op = Op.getOperand(0);
21592 // A special case for rdrand/rdseed, where 0 is set if false cond is
21594 if ((Op.getOpcode() != X86ISD::RDRAND &&
21595 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
21598 // Quit if false value is not the constant 0 or 1.
21599 bool FValIsFalse = true;
21600 if (FVal && FVal->getZExtValue() != 0) {
21601 if (FVal->getZExtValue() != 1)
21603 // If FVal is 1, opposite cond is needed.
21604 needOppositeCond = !needOppositeCond;
21605 FValIsFalse = false;
21607 // Quit if TVal is not the constant opposite of FVal.
21608 if (FValIsFalse && TVal->getZExtValue() != 1)
21610 if (!FValIsFalse && TVal->getZExtValue() != 0)
21612 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
21613 if (needOppositeCond)
21614 CC = X86::GetOppositeBranchCondition(CC);
21615 return SetCC.getOperand(3);
21622 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
21623 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
21624 TargetLowering::DAGCombinerInfo &DCI,
21625 const X86Subtarget *Subtarget) {
21628 // If the flag operand isn't dead, don't touch this CMOV.
21629 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
21632 SDValue FalseOp = N->getOperand(0);
21633 SDValue TrueOp = N->getOperand(1);
21634 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
21635 SDValue Cond = N->getOperand(3);
21637 if (CC == X86::COND_E || CC == X86::COND_NE) {
21638 switch (Cond.getOpcode()) {
21642 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
21643 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
21644 return (CC == X86::COND_E) ? FalseOp : TrueOp;
21650 Flags = checkBoolTestSetCCCombine(Cond, CC);
21651 if (Flags.getNode() &&
21652 // Extra check as FCMOV only supports a subset of X86 cond.
21653 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
21654 SDValue Ops[] = { FalseOp, TrueOp,
21655 DAG.getConstant(CC, MVT::i8), Flags };
21656 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
21659 // If this is a select between two integer constants, try to do some
21660 // optimizations. Note that the operands are ordered the opposite of SELECT
21662 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
21663 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
21664 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
21665 // larger than FalseC (the false value).
21666 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
21667 CC = X86::GetOppositeBranchCondition(CC);
21668 std::swap(TrueC, FalseC);
21669 std::swap(TrueOp, FalseOp);
21672 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
21673 // This is efficient for any integer data type (including i8/i16) and
21675 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
21676 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
21677 DAG.getConstant(CC, MVT::i8), Cond);
21679 // Zero extend the condition if needed.
21680 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
21682 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
21683 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
21684 DAG.getConstant(ShAmt, MVT::i8));
21685 if (N->getNumValues() == 2) // Dead flag value?
21686 return DCI.CombineTo(N, Cond, SDValue());
21690 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
21691 // for any integer data type, including i8/i16.
21692 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
21693 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
21694 DAG.getConstant(CC, MVT::i8), Cond);
21696 // Zero extend the condition if needed.
21697 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
21698 FalseC->getValueType(0), Cond);
21699 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
21700 SDValue(FalseC, 0));
21702 if (N->getNumValues() == 2) // Dead flag value?
21703 return DCI.CombineTo(N, Cond, SDValue());
21707 // Optimize cases that will turn into an LEA instruction. This requires
21708 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
21709 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
21710 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
21711 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
21713 bool isFastMultiplier = false;
21715 switch ((unsigned char)Diff) {
21717 case 1: // result = add base, cond
21718 case 2: // result = lea base( , cond*2)
21719 case 3: // result = lea base(cond, cond*2)
21720 case 4: // result = lea base( , cond*4)
21721 case 5: // result = lea base(cond, cond*4)
21722 case 8: // result = lea base( , cond*8)
21723 case 9: // result = lea base(cond, cond*8)
21724 isFastMultiplier = true;
21729 if (isFastMultiplier) {
21730 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
21731 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
21732 DAG.getConstant(CC, MVT::i8), Cond);
21733 // Zero extend the condition if needed.
21734 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
21736 // Scale the condition by the difference.
21738 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
21739 DAG.getConstant(Diff, Cond.getValueType()));
21741 // Add the base if non-zero.
21742 if (FalseC->getAPIntValue() != 0)
21743 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
21744 SDValue(FalseC, 0));
21745 if (N->getNumValues() == 2) // Dead flag value?
21746 return DCI.CombineTo(N, Cond, SDValue());
21753 // Handle these cases:
21754 // (select (x != c), e, c) -> select (x != c), e, x),
21755 // (select (x == c), c, e) -> select (x == c), x, e)
21756 // where the c is an integer constant, and the "select" is the combination
21757 // of CMOV and CMP.
21759 // The rationale for this change is that the conditional-move from a constant
21760 // needs two instructions, however, conditional-move from a register needs
21761 // only one instruction.
21763 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
21764 // some instruction-combining opportunities. This opt needs to be
21765 // postponed as late as possible.
21767 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
21768 // the DCI.xxxx conditions are provided to postpone the optimization as
21769 // late as possible.
21771 ConstantSDNode *CmpAgainst = nullptr;
21772 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
21773 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
21774 !isa<ConstantSDNode>(Cond.getOperand(0))) {
21776 if (CC == X86::COND_NE &&
21777 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
21778 CC = X86::GetOppositeBranchCondition(CC);
21779 std::swap(TrueOp, FalseOp);
21782 if (CC == X86::COND_E &&
21783 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
21784 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
21785 DAG.getConstant(CC, MVT::i8), Cond };
21786 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
21794 static SDValue PerformINTRINSIC_WO_CHAINCombine(SDNode *N, SelectionDAG &DAG,
21795 const X86Subtarget *Subtarget) {
21796 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
21798 default: return SDValue();
21799 // SSE/AVX/AVX2 blend intrinsics.
21800 case Intrinsic::x86_avx2_pblendvb:
21801 case Intrinsic::x86_avx2_pblendw:
21802 case Intrinsic::x86_avx2_pblendd_128:
21803 case Intrinsic::x86_avx2_pblendd_256:
21804 // Don't try to simplify this intrinsic if we don't have AVX2.
21805 if (!Subtarget->hasAVX2())
21808 case Intrinsic::x86_avx_blend_pd_256:
21809 case Intrinsic::x86_avx_blend_ps_256:
21810 case Intrinsic::x86_avx_blendv_pd_256:
21811 case Intrinsic::x86_avx_blendv_ps_256:
21812 // Don't try to simplify this intrinsic if we don't have AVX.
21813 if (!Subtarget->hasAVX())
21816 case Intrinsic::x86_sse41_pblendw:
21817 case Intrinsic::x86_sse41_blendpd:
21818 case Intrinsic::x86_sse41_blendps:
21819 case Intrinsic::x86_sse41_blendvps:
21820 case Intrinsic::x86_sse41_blendvpd:
21821 case Intrinsic::x86_sse41_pblendvb: {
21822 SDValue Op0 = N->getOperand(1);
21823 SDValue Op1 = N->getOperand(2);
21824 SDValue Mask = N->getOperand(3);
21826 // Don't try to simplify this intrinsic if we don't have SSE4.1.
21827 if (!Subtarget->hasSSE41())
21830 // fold (blend A, A, Mask) -> A
21833 // fold (blend A, B, allZeros) -> A
21834 if (ISD::isBuildVectorAllZeros(Mask.getNode()))
21836 // fold (blend A, B, allOnes) -> B
21837 if (ISD::isBuildVectorAllOnes(Mask.getNode()))
21840 // Simplify the case where the mask is a constant i32 value.
21841 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Mask)) {
21842 if (C->isNullValue())
21844 if (C->isAllOnesValue())
21851 // Packed SSE2/AVX2 arithmetic shift immediate intrinsics.
21852 case Intrinsic::x86_sse2_psrai_w:
21853 case Intrinsic::x86_sse2_psrai_d:
21854 case Intrinsic::x86_avx2_psrai_w:
21855 case Intrinsic::x86_avx2_psrai_d:
21856 case Intrinsic::x86_sse2_psra_w:
21857 case Intrinsic::x86_sse2_psra_d:
21858 case Intrinsic::x86_avx2_psra_w:
21859 case Intrinsic::x86_avx2_psra_d: {
21860 SDValue Op0 = N->getOperand(1);
21861 SDValue Op1 = N->getOperand(2);
21862 EVT VT = Op0.getValueType();
21863 assert(VT.isVector() && "Expected a vector type!");
21865 if (isa<BuildVectorSDNode>(Op1))
21866 Op1 = Op1.getOperand(0);
21868 if (!isa<ConstantSDNode>(Op1))
21871 EVT SVT = VT.getVectorElementType();
21872 unsigned SVTBits = SVT.getSizeInBits();
21874 ConstantSDNode *CND = cast<ConstantSDNode>(Op1);
21875 const APInt &C = APInt(SVTBits, CND->getAPIntValue().getZExtValue());
21876 uint64_t ShAmt = C.getZExtValue();
21878 // Don't try to convert this shift into a ISD::SRA if the shift
21879 // count is bigger than or equal to the element size.
21880 if (ShAmt >= SVTBits)
21883 // Trivial case: if the shift count is zero, then fold this
21884 // into the first operand.
21888 // Replace this packed shift intrinsic with a target independent
21890 SDValue Splat = DAG.getConstant(C, VT);
21891 return DAG.getNode(ISD::SRA, SDLoc(N), VT, Op0, Splat);
21896 /// PerformMulCombine - Optimize a single multiply with constant into two
21897 /// in order to implement it with two cheaper instructions, e.g.
21898 /// LEA + SHL, LEA + LEA.
21899 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
21900 TargetLowering::DAGCombinerInfo &DCI) {
21901 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
21904 EVT VT = N->getValueType(0);
21905 if (VT != MVT::i64)
21908 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
21911 uint64_t MulAmt = C->getZExtValue();
21912 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
21915 uint64_t MulAmt1 = 0;
21916 uint64_t MulAmt2 = 0;
21917 if ((MulAmt % 9) == 0) {
21919 MulAmt2 = MulAmt / 9;
21920 } else if ((MulAmt % 5) == 0) {
21922 MulAmt2 = MulAmt / 5;
21923 } else if ((MulAmt % 3) == 0) {
21925 MulAmt2 = MulAmt / 3;
21928 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
21931 if (isPowerOf2_64(MulAmt2) &&
21932 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
21933 // If second multiplifer is pow2, issue it first. We want the multiply by
21934 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
21936 std::swap(MulAmt1, MulAmt2);
21939 if (isPowerOf2_64(MulAmt1))
21940 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
21941 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
21943 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
21944 DAG.getConstant(MulAmt1, VT));
21946 if (isPowerOf2_64(MulAmt2))
21947 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
21948 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
21950 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
21951 DAG.getConstant(MulAmt2, VT));
21953 // Do not add new nodes to DAG combiner worklist.
21954 DCI.CombineTo(N, NewMul, false);
21959 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
21960 SDValue N0 = N->getOperand(0);
21961 SDValue N1 = N->getOperand(1);
21962 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
21963 EVT VT = N0.getValueType();
21965 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
21966 // since the result of setcc_c is all zero's or all ones.
21967 if (VT.isInteger() && !VT.isVector() &&
21968 N1C && N0.getOpcode() == ISD::AND &&
21969 N0.getOperand(1).getOpcode() == ISD::Constant) {
21970 SDValue N00 = N0.getOperand(0);
21971 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
21972 ((N00.getOpcode() == ISD::ANY_EXTEND ||
21973 N00.getOpcode() == ISD::ZERO_EXTEND) &&
21974 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
21975 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
21976 APInt ShAmt = N1C->getAPIntValue();
21977 Mask = Mask.shl(ShAmt);
21979 return DAG.getNode(ISD::AND, SDLoc(N), VT,
21980 N00, DAG.getConstant(Mask, VT));
21984 // Hardware support for vector shifts is sparse which makes us scalarize the
21985 // vector operations in many cases. Also, on sandybridge ADD is faster than
21987 // (shl V, 1) -> add V,V
21988 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
21989 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
21990 assert(N0.getValueType().isVector() && "Invalid vector shift type");
21991 // We shift all of the values by one. In many cases we do not have
21992 // hardware support for this operation. This is better expressed as an ADD
21994 if (N1SplatC->getZExtValue() == 1)
21995 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
22001 /// \brief Returns a vector of 0s if the node in input is a vector logical
22002 /// shift by a constant amount which is known to be bigger than or equal
22003 /// to the vector element size in bits.
22004 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
22005 const X86Subtarget *Subtarget) {
22006 EVT VT = N->getValueType(0);
22008 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
22009 (!Subtarget->hasInt256() ||
22010 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
22013 SDValue Amt = N->getOperand(1);
22015 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
22016 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
22017 APInt ShiftAmt = AmtSplat->getAPIntValue();
22018 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
22020 // SSE2/AVX2 logical shifts always return a vector of 0s
22021 // if the shift amount is bigger than or equal to
22022 // the element size. The constant shift amount will be
22023 // encoded as a 8-bit immediate.
22024 if (ShiftAmt.trunc(8).uge(MaxAmount))
22025 return getZeroVector(VT, Subtarget, DAG, DL);
22031 /// PerformShiftCombine - Combine shifts.
22032 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
22033 TargetLowering::DAGCombinerInfo &DCI,
22034 const X86Subtarget *Subtarget) {
22035 if (N->getOpcode() == ISD::SHL) {
22036 SDValue V = PerformSHLCombine(N, DAG);
22037 if (V.getNode()) return V;
22040 if (N->getOpcode() != ISD::SRA) {
22041 // Try to fold this logical shift into a zero vector.
22042 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
22043 if (V.getNode()) return V;
22049 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
22050 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
22051 // and friends. Likewise for OR -> CMPNEQSS.
22052 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
22053 TargetLowering::DAGCombinerInfo &DCI,
22054 const X86Subtarget *Subtarget) {
22057 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
22058 // we're requiring SSE2 for both.
22059 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
22060 SDValue N0 = N->getOperand(0);
22061 SDValue N1 = N->getOperand(1);
22062 SDValue CMP0 = N0->getOperand(1);
22063 SDValue CMP1 = N1->getOperand(1);
22066 // The SETCCs should both refer to the same CMP.
22067 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
22070 SDValue CMP00 = CMP0->getOperand(0);
22071 SDValue CMP01 = CMP0->getOperand(1);
22072 EVT VT = CMP00.getValueType();
22074 if (VT == MVT::f32 || VT == MVT::f64) {
22075 bool ExpectingFlags = false;
22076 // Check for any users that want flags:
22077 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
22078 !ExpectingFlags && UI != UE; ++UI)
22079 switch (UI->getOpcode()) {
22084 ExpectingFlags = true;
22086 case ISD::CopyToReg:
22087 case ISD::SIGN_EXTEND:
22088 case ISD::ZERO_EXTEND:
22089 case ISD::ANY_EXTEND:
22093 if (!ExpectingFlags) {
22094 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
22095 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
22097 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
22098 X86::CondCode tmp = cc0;
22103 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
22104 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
22105 // FIXME: need symbolic constants for these magic numbers.
22106 // See X86ATTInstPrinter.cpp:printSSECC().
22107 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
22108 if (Subtarget->hasAVX512()) {
22109 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
22110 CMP01, DAG.getConstant(x86cc, MVT::i8));
22111 if (N->getValueType(0) != MVT::i1)
22112 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
22116 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
22117 CMP00.getValueType(), CMP00, CMP01,
22118 DAG.getConstant(x86cc, MVT::i8));
22120 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
22121 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
22123 if (is64BitFP && !Subtarget->is64Bit()) {
22124 // On a 32-bit target, we cannot bitcast the 64-bit float to a
22125 // 64-bit integer, since that's not a legal type. Since
22126 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
22127 // bits, but can do this little dance to extract the lowest 32 bits
22128 // and work with those going forward.
22129 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
22131 SDValue Vector32 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f32,
22133 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
22134 Vector32, DAG.getIntPtrConstant(0));
22138 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT, OnesOrZeroesF);
22139 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
22140 DAG.getConstant(1, IntVT));
22141 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
22142 return OneBitOfTruth;
22150 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
22151 /// so it can be folded inside ANDNP.
22152 static bool CanFoldXORWithAllOnes(const SDNode *N) {
22153 EVT VT = N->getValueType(0);
22155 // Match direct AllOnes for 128 and 256-bit vectors
22156 if (ISD::isBuildVectorAllOnes(N))
22159 // Look through a bit convert.
22160 if (N->getOpcode() == ISD::BITCAST)
22161 N = N->getOperand(0).getNode();
22163 // Sometimes the operand may come from a insert_subvector building a 256-bit
22165 if (VT.is256BitVector() &&
22166 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
22167 SDValue V1 = N->getOperand(0);
22168 SDValue V2 = N->getOperand(1);
22170 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
22171 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
22172 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
22173 ISD::isBuildVectorAllOnes(V2.getNode()))
22180 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
22181 // register. In most cases we actually compare or select YMM-sized registers
22182 // and mixing the two types creates horrible code. This method optimizes
22183 // some of the transition sequences.
22184 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
22185 TargetLowering::DAGCombinerInfo &DCI,
22186 const X86Subtarget *Subtarget) {
22187 EVT VT = N->getValueType(0);
22188 if (!VT.is256BitVector())
22191 assert((N->getOpcode() == ISD::ANY_EXTEND ||
22192 N->getOpcode() == ISD::ZERO_EXTEND ||
22193 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
22195 SDValue Narrow = N->getOperand(0);
22196 EVT NarrowVT = Narrow->getValueType(0);
22197 if (!NarrowVT.is128BitVector())
22200 if (Narrow->getOpcode() != ISD::XOR &&
22201 Narrow->getOpcode() != ISD::AND &&
22202 Narrow->getOpcode() != ISD::OR)
22205 SDValue N0 = Narrow->getOperand(0);
22206 SDValue N1 = Narrow->getOperand(1);
22209 // The Left side has to be a trunc.
22210 if (N0.getOpcode() != ISD::TRUNCATE)
22213 // The type of the truncated inputs.
22214 EVT WideVT = N0->getOperand(0)->getValueType(0);
22218 // The right side has to be a 'trunc' or a constant vector.
22219 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
22220 ConstantSDNode *RHSConstSplat = nullptr;
22221 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
22222 RHSConstSplat = RHSBV->getConstantSplatNode();
22223 if (!RHSTrunc && !RHSConstSplat)
22226 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22228 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
22231 // Set N0 and N1 to hold the inputs to the new wide operation.
22232 N0 = N0->getOperand(0);
22233 if (RHSConstSplat) {
22234 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
22235 SDValue(RHSConstSplat, 0));
22236 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
22237 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
22238 } else if (RHSTrunc) {
22239 N1 = N1->getOperand(0);
22242 // Generate the wide operation.
22243 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
22244 unsigned Opcode = N->getOpcode();
22246 case ISD::ANY_EXTEND:
22248 case ISD::ZERO_EXTEND: {
22249 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
22250 APInt Mask = APInt::getAllOnesValue(InBits);
22251 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
22252 return DAG.getNode(ISD::AND, DL, VT,
22253 Op, DAG.getConstant(Mask, VT));
22255 case ISD::SIGN_EXTEND:
22256 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
22257 Op, DAG.getValueType(NarrowVT));
22259 llvm_unreachable("Unexpected opcode");
22263 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
22264 TargetLowering::DAGCombinerInfo &DCI,
22265 const X86Subtarget *Subtarget) {
22266 EVT VT = N->getValueType(0);
22267 if (DCI.isBeforeLegalizeOps())
22270 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
22274 // Create BEXTR instructions
22275 // BEXTR is ((X >> imm) & (2**size-1))
22276 if (VT == MVT::i32 || VT == MVT::i64) {
22277 SDValue N0 = N->getOperand(0);
22278 SDValue N1 = N->getOperand(1);
22281 // Check for BEXTR.
22282 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
22283 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
22284 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
22285 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
22286 if (MaskNode && ShiftNode) {
22287 uint64_t Mask = MaskNode->getZExtValue();
22288 uint64_t Shift = ShiftNode->getZExtValue();
22289 if (isMask_64(Mask)) {
22290 uint64_t MaskSize = CountPopulation_64(Mask);
22291 if (Shift + MaskSize <= VT.getSizeInBits())
22292 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
22293 DAG.getConstant(Shift | (MaskSize << 8), VT));
22301 // Want to form ANDNP nodes:
22302 // 1) In the hopes of then easily combining them with OR and AND nodes
22303 // to form PBLEND/PSIGN.
22304 // 2) To match ANDN packed intrinsics
22305 if (VT != MVT::v2i64 && VT != MVT::v4i64)
22308 SDValue N0 = N->getOperand(0);
22309 SDValue N1 = N->getOperand(1);
22312 // Check LHS for vnot
22313 if (N0.getOpcode() == ISD::XOR &&
22314 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
22315 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
22316 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
22318 // Check RHS for vnot
22319 if (N1.getOpcode() == ISD::XOR &&
22320 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
22321 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
22322 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
22327 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
22328 TargetLowering::DAGCombinerInfo &DCI,
22329 const X86Subtarget *Subtarget) {
22330 if (DCI.isBeforeLegalizeOps())
22333 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
22337 SDValue N0 = N->getOperand(0);
22338 SDValue N1 = N->getOperand(1);
22339 EVT VT = N->getValueType(0);
22341 // look for psign/blend
22342 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
22343 if (!Subtarget->hasSSSE3() ||
22344 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
22347 // Canonicalize pandn to RHS
22348 if (N0.getOpcode() == X86ISD::ANDNP)
22350 // or (and (m, y), (pandn m, x))
22351 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
22352 SDValue Mask = N1.getOperand(0);
22353 SDValue X = N1.getOperand(1);
22355 if (N0.getOperand(0) == Mask)
22356 Y = N0.getOperand(1);
22357 if (N0.getOperand(1) == Mask)
22358 Y = N0.getOperand(0);
22360 // Check to see if the mask appeared in both the AND and ANDNP and
22364 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
22365 // Look through mask bitcast.
22366 if (Mask.getOpcode() == ISD::BITCAST)
22367 Mask = Mask.getOperand(0);
22368 if (X.getOpcode() == ISD::BITCAST)
22369 X = X.getOperand(0);
22370 if (Y.getOpcode() == ISD::BITCAST)
22371 Y = Y.getOperand(0);
22373 EVT MaskVT = Mask.getValueType();
22375 // Validate that the Mask operand is a vector sra node.
22376 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
22377 // there is no psrai.b
22378 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
22379 unsigned SraAmt = ~0;
22380 if (Mask.getOpcode() == ISD::SRA) {
22381 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
22382 if (auto *AmtConst = AmtBV->getConstantSplatNode())
22383 SraAmt = AmtConst->getZExtValue();
22384 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
22385 SDValue SraC = Mask.getOperand(1);
22386 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
22388 if ((SraAmt + 1) != EltBits)
22393 // Now we know we at least have a plendvb with the mask val. See if
22394 // we can form a psignb/w/d.
22395 // psign = x.type == y.type == mask.type && y = sub(0, x);
22396 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
22397 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
22398 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
22399 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
22400 "Unsupported VT for PSIGN");
22401 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
22402 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
22404 // PBLENDVB only available on SSE 4.1
22405 if (!Subtarget->hasSSE41())
22408 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
22410 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
22411 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
22412 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
22413 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
22414 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
22418 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
22421 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
22422 MachineFunction &MF = DAG.getMachineFunction();
22423 bool OptForSize = MF.getFunction()->getAttributes().
22424 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
22426 // SHLD/SHRD instructions have lower register pressure, but on some
22427 // platforms they have higher latency than the equivalent
22428 // series of shifts/or that would otherwise be generated.
22429 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
22430 // have higher latencies and we are not optimizing for size.
22431 if (!OptForSize && Subtarget->isSHLDSlow())
22434 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
22436 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
22438 if (!N0.hasOneUse() || !N1.hasOneUse())
22441 SDValue ShAmt0 = N0.getOperand(1);
22442 if (ShAmt0.getValueType() != MVT::i8)
22444 SDValue ShAmt1 = N1.getOperand(1);
22445 if (ShAmt1.getValueType() != MVT::i8)
22447 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
22448 ShAmt0 = ShAmt0.getOperand(0);
22449 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
22450 ShAmt1 = ShAmt1.getOperand(0);
22453 unsigned Opc = X86ISD::SHLD;
22454 SDValue Op0 = N0.getOperand(0);
22455 SDValue Op1 = N1.getOperand(0);
22456 if (ShAmt0.getOpcode() == ISD::SUB) {
22457 Opc = X86ISD::SHRD;
22458 std::swap(Op0, Op1);
22459 std::swap(ShAmt0, ShAmt1);
22462 unsigned Bits = VT.getSizeInBits();
22463 if (ShAmt1.getOpcode() == ISD::SUB) {
22464 SDValue Sum = ShAmt1.getOperand(0);
22465 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
22466 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
22467 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
22468 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
22469 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
22470 return DAG.getNode(Opc, DL, VT,
22472 DAG.getNode(ISD::TRUNCATE, DL,
22475 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
22476 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
22478 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
22479 return DAG.getNode(Opc, DL, VT,
22480 N0.getOperand(0), N1.getOperand(0),
22481 DAG.getNode(ISD::TRUNCATE, DL,
22488 // Generate NEG and CMOV for integer abs.
22489 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
22490 EVT VT = N->getValueType(0);
22492 // Since X86 does not have CMOV for 8-bit integer, we don't convert
22493 // 8-bit integer abs to NEG and CMOV.
22494 if (VT.isInteger() && VT.getSizeInBits() == 8)
22497 SDValue N0 = N->getOperand(0);
22498 SDValue N1 = N->getOperand(1);
22501 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
22502 // and change it to SUB and CMOV.
22503 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
22504 N0.getOpcode() == ISD::ADD &&
22505 N0.getOperand(1) == N1 &&
22506 N1.getOpcode() == ISD::SRA &&
22507 N1.getOperand(0) == N0.getOperand(0))
22508 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
22509 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
22510 // Generate SUB & CMOV.
22511 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
22512 DAG.getConstant(0, VT), N0.getOperand(0));
22514 SDValue Ops[] = { N0.getOperand(0), Neg,
22515 DAG.getConstant(X86::COND_GE, MVT::i8),
22516 SDValue(Neg.getNode(), 1) };
22517 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
22522 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
22523 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
22524 TargetLowering::DAGCombinerInfo &DCI,
22525 const X86Subtarget *Subtarget) {
22526 if (DCI.isBeforeLegalizeOps())
22529 if (Subtarget->hasCMov()) {
22530 SDValue RV = performIntegerAbsCombine(N, DAG);
22538 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
22539 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
22540 TargetLowering::DAGCombinerInfo &DCI,
22541 const X86Subtarget *Subtarget) {
22542 LoadSDNode *Ld = cast<LoadSDNode>(N);
22543 EVT RegVT = Ld->getValueType(0);
22544 EVT MemVT = Ld->getMemoryVT();
22546 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22548 // On Sandybridge unaligned 256bit loads are inefficient.
22549 ISD::LoadExtType Ext = Ld->getExtensionType();
22550 unsigned Alignment = Ld->getAlignment();
22551 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
22552 if (RegVT.is256BitVector() && !Subtarget->hasInt256() &&
22553 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
22554 unsigned NumElems = RegVT.getVectorNumElements();
22558 SDValue Ptr = Ld->getBasePtr();
22559 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
22561 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
22563 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
22564 Ld->getPointerInfo(), Ld->isVolatile(),
22565 Ld->isNonTemporal(), Ld->isInvariant(),
22567 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
22568 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
22569 Ld->getPointerInfo(), Ld->isVolatile(),
22570 Ld->isNonTemporal(), Ld->isInvariant(),
22571 std::min(16U, Alignment));
22572 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
22574 Load2.getValue(1));
22576 SDValue NewVec = DAG.getUNDEF(RegVT);
22577 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
22578 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
22579 return DCI.CombineTo(N, NewVec, TF, true);
22585 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
22586 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
22587 const X86Subtarget *Subtarget) {
22588 StoreSDNode *St = cast<StoreSDNode>(N);
22589 EVT VT = St->getValue().getValueType();
22590 EVT StVT = St->getMemoryVT();
22592 SDValue StoredVal = St->getOperand(1);
22593 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22595 // If we are saving a concatenation of two XMM registers, perform two stores.
22596 // On Sandy Bridge, 256-bit memory operations are executed by two
22597 // 128-bit ports. However, on Haswell it is better to issue a single 256-bit
22598 // memory operation.
22599 unsigned Alignment = St->getAlignment();
22600 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
22601 if (VT.is256BitVector() && !Subtarget->hasInt256() &&
22602 StVT == VT && !IsAligned) {
22603 unsigned NumElems = VT.getVectorNumElements();
22607 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
22608 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
22610 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
22611 SDValue Ptr0 = St->getBasePtr();
22612 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
22614 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
22615 St->getPointerInfo(), St->isVolatile(),
22616 St->isNonTemporal(), Alignment);
22617 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
22618 St->getPointerInfo(), St->isVolatile(),
22619 St->isNonTemporal(),
22620 std::min(16U, Alignment));
22621 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
22624 // Optimize trunc store (of multiple scalars) to shuffle and store.
22625 // First, pack all of the elements in one place. Next, store to memory
22626 // in fewer chunks.
22627 if (St->isTruncatingStore() && VT.isVector()) {
22628 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22629 unsigned NumElems = VT.getVectorNumElements();
22630 assert(StVT != VT && "Cannot truncate to the same type");
22631 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
22632 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
22634 // From, To sizes and ElemCount must be pow of two
22635 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
22636 // We are going to use the original vector elt for storing.
22637 // Accumulated smaller vector elements must be a multiple of the store size.
22638 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
22640 unsigned SizeRatio = FromSz / ToSz;
22642 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
22644 // Create a type on which we perform the shuffle
22645 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
22646 StVT.getScalarType(), NumElems*SizeRatio);
22648 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
22650 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
22651 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
22652 for (unsigned i = 0; i != NumElems; ++i)
22653 ShuffleVec[i] = i * SizeRatio;
22655 // Can't shuffle using an illegal type.
22656 if (!TLI.isTypeLegal(WideVecVT))
22659 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
22660 DAG.getUNDEF(WideVecVT),
22662 // At this point all of the data is stored at the bottom of the
22663 // register. We now need to save it to mem.
22665 // Find the largest store unit
22666 MVT StoreType = MVT::i8;
22667 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
22668 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
22669 MVT Tp = (MVT::SimpleValueType)tp;
22670 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
22674 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
22675 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
22676 (64 <= NumElems * ToSz))
22677 StoreType = MVT::f64;
22679 // Bitcast the original vector into a vector of store-size units
22680 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
22681 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
22682 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
22683 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
22684 SmallVector<SDValue, 8> Chains;
22685 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
22686 TLI.getPointerTy());
22687 SDValue Ptr = St->getBasePtr();
22689 // Perform one or more big stores into memory.
22690 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
22691 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
22692 StoreType, ShuffWide,
22693 DAG.getIntPtrConstant(i));
22694 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
22695 St->getPointerInfo(), St->isVolatile(),
22696 St->isNonTemporal(), St->getAlignment());
22697 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
22698 Chains.push_back(Ch);
22701 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
22704 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
22705 // the FP state in cases where an emms may be missing.
22706 // A preferable solution to the general problem is to figure out the right
22707 // places to insert EMMS. This qualifies as a quick hack.
22709 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
22710 if (VT.getSizeInBits() != 64)
22713 const Function *F = DAG.getMachineFunction().getFunction();
22714 bool NoImplicitFloatOps = F->getAttributes().
22715 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
22716 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
22717 && Subtarget->hasSSE2();
22718 if ((VT.isVector() ||
22719 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
22720 isa<LoadSDNode>(St->getValue()) &&
22721 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
22722 St->getChain().hasOneUse() && !St->isVolatile()) {
22723 SDNode* LdVal = St->getValue().getNode();
22724 LoadSDNode *Ld = nullptr;
22725 int TokenFactorIndex = -1;
22726 SmallVector<SDValue, 8> Ops;
22727 SDNode* ChainVal = St->getChain().getNode();
22728 // Must be a store of a load. We currently handle two cases: the load
22729 // is a direct child, and it's under an intervening TokenFactor. It is
22730 // possible to dig deeper under nested TokenFactors.
22731 if (ChainVal == LdVal)
22732 Ld = cast<LoadSDNode>(St->getChain());
22733 else if (St->getValue().hasOneUse() &&
22734 ChainVal->getOpcode() == ISD::TokenFactor) {
22735 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
22736 if (ChainVal->getOperand(i).getNode() == LdVal) {
22737 TokenFactorIndex = i;
22738 Ld = cast<LoadSDNode>(St->getValue());
22740 Ops.push_back(ChainVal->getOperand(i));
22744 if (!Ld || !ISD::isNormalLoad(Ld))
22747 // If this is not the MMX case, i.e. we are just turning i64 load/store
22748 // into f64 load/store, avoid the transformation if there are multiple
22749 // uses of the loaded value.
22750 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
22755 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
22756 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
22758 if (Subtarget->is64Bit() || F64IsLegal) {
22759 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
22760 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
22761 Ld->getPointerInfo(), Ld->isVolatile(),
22762 Ld->isNonTemporal(), Ld->isInvariant(),
22763 Ld->getAlignment());
22764 SDValue NewChain = NewLd.getValue(1);
22765 if (TokenFactorIndex != -1) {
22766 Ops.push_back(NewChain);
22767 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
22769 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
22770 St->getPointerInfo(),
22771 St->isVolatile(), St->isNonTemporal(),
22772 St->getAlignment());
22775 // Otherwise, lower to two pairs of 32-bit loads / stores.
22776 SDValue LoAddr = Ld->getBasePtr();
22777 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
22778 DAG.getConstant(4, MVT::i32));
22780 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
22781 Ld->getPointerInfo(),
22782 Ld->isVolatile(), Ld->isNonTemporal(),
22783 Ld->isInvariant(), Ld->getAlignment());
22784 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
22785 Ld->getPointerInfo().getWithOffset(4),
22786 Ld->isVolatile(), Ld->isNonTemporal(),
22788 MinAlign(Ld->getAlignment(), 4));
22790 SDValue NewChain = LoLd.getValue(1);
22791 if (TokenFactorIndex != -1) {
22792 Ops.push_back(LoLd);
22793 Ops.push_back(HiLd);
22794 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
22797 LoAddr = St->getBasePtr();
22798 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
22799 DAG.getConstant(4, MVT::i32));
22801 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
22802 St->getPointerInfo(),
22803 St->isVolatile(), St->isNonTemporal(),
22804 St->getAlignment());
22805 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
22806 St->getPointerInfo().getWithOffset(4),
22808 St->isNonTemporal(),
22809 MinAlign(St->getAlignment(), 4));
22810 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
22815 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
22816 /// and return the operands for the horizontal operation in LHS and RHS. A
22817 /// horizontal operation performs the binary operation on successive elements
22818 /// of its first operand, then on successive elements of its second operand,
22819 /// returning the resulting values in a vector. For example, if
22820 /// A = < float a0, float a1, float a2, float a3 >
22822 /// B = < float b0, float b1, float b2, float b3 >
22823 /// then the result of doing a horizontal operation on A and B is
22824 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
22825 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
22826 /// A horizontal-op B, for some already available A and B, and if so then LHS is
22827 /// set to A, RHS to B, and the routine returns 'true'.
22828 /// Note that the binary operation should have the property that if one of the
22829 /// operands is UNDEF then the result is UNDEF.
22830 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
22831 // Look for the following pattern: if
22832 // A = < float a0, float a1, float a2, float a3 >
22833 // B = < float b0, float b1, float b2, float b3 >
22835 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
22836 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
22837 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
22838 // which is A horizontal-op B.
22840 // At least one of the operands should be a vector shuffle.
22841 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
22842 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
22845 MVT VT = LHS.getSimpleValueType();
22847 assert((VT.is128BitVector() || VT.is256BitVector()) &&
22848 "Unsupported vector type for horizontal add/sub");
22850 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
22851 // operate independently on 128-bit lanes.
22852 unsigned NumElts = VT.getVectorNumElements();
22853 unsigned NumLanes = VT.getSizeInBits()/128;
22854 unsigned NumLaneElts = NumElts / NumLanes;
22855 assert((NumLaneElts % 2 == 0) &&
22856 "Vector type should have an even number of elements in each lane");
22857 unsigned HalfLaneElts = NumLaneElts/2;
22859 // View LHS in the form
22860 // LHS = VECTOR_SHUFFLE A, B, LMask
22861 // If LHS is not a shuffle then pretend it is the shuffle
22862 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
22863 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
22866 SmallVector<int, 16> LMask(NumElts);
22867 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
22868 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
22869 A = LHS.getOperand(0);
22870 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
22871 B = LHS.getOperand(1);
22872 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
22873 std::copy(Mask.begin(), Mask.end(), LMask.begin());
22875 if (LHS.getOpcode() != ISD::UNDEF)
22877 for (unsigned i = 0; i != NumElts; ++i)
22881 // Likewise, view RHS in the form
22882 // RHS = VECTOR_SHUFFLE C, D, RMask
22884 SmallVector<int, 16> RMask(NumElts);
22885 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
22886 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
22887 C = RHS.getOperand(0);
22888 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
22889 D = RHS.getOperand(1);
22890 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
22891 std::copy(Mask.begin(), Mask.end(), RMask.begin());
22893 if (RHS.getOpcode() != ISD::UNDEF)
22895 for (unsigned i = 0; i != NumElts; ++i)
22899 // Check that the shuffles are both shuffling the same vectors.
22900 if (!(A == C && B == D) && !(A == D && B == C))
22903 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
22904 if (!A.getNode() && !B.getNode())
22907 // If A and B occur in reverse order in RHS, then "swap" them (which means
22908 // rewriting the mask).
22910 CommuteVectorShuffleMask(RMask, NumElts);
22912 // At this point LHS and RHS are equivalent to
22913 // LHS = VECTOR_SHUFFLE A, B, LMask
22914 // RHS = VECTOR_SHUFFLE A, B, RMask
22915 // Check that the masks correspond to performing a horizontal operation.
22916 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
22917 for (unsigned i = 0; i != NumLaneElts; ++i) {
22918 int LIdx = LMask[i+l], RIdx = RMask[i+l];
22920 // Ignore any UNDEF components.
22921 if (LIdx < 0 || RIdx < 0 ||
22922 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
22923 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
22926 // Check that successive elements are being operated on. If not, this is
22927 // not a horizontal operation.
22928 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
22929 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
22930 if (!(LIdx == Index && RIdx == Index + 1) &&
22931 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
22936 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
22937 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
22941 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
22942 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
22943 const X86Subtarget *Subtarget) {
22944 EVT VT = N->getValueType(0);
22945 SDValue LHS = N->getOperand(0);
22946 SDValue RHS = N->getOperand(1);
22948 // Try to synthesize horizontal adds from adds of shuffles.
22949 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
22950 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
22951 isHorizontalBinOp(LHS, RHS, true))
22952 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
22956 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
22957 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
22958 const X86Subtarget *Subtarget) {
22959 EVT VT = N->getValueType(0);
22960 SDValue LHS = N->getOperand(0);
22961 SDValue RHS = N->getOperand(1);
22963 // Try to synthesize horizontal subs from subs of shuffles.
22964 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
22965 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
22966 isHorizontalBinOp(LHS, RHS, false))
22967 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
22971 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
22972 /// X86ISD::FXOR nodes.
22973 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
22974 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
22975 // F[X]OR(0.0, x) -> x
22976 // F[X]OR(x, 0.0) -> x
22977 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
22978 if (C->getValueAPF().isPosZero())
22979 return N->getOperand(1);
22980 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
22981 if (C->getValueAPF().isPosZero())
22982 return N->getOperand(0);
22986 /// PerformFMinFMaxCombine - Do target-specific dag combines on X86ISD::FMIN and
22987 /// X86ISD::FMAX nodes.
22988 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
22989 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
22991 // Only perform optimizations if UnsafeMath is used.
22992 if (!DAG.getTarget().Options.UnsafeFPMath)
22995 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
22996 // into FMINC and FMAXC, which are Commutative operations.
22997 unsigned NewOp = 0;
22998 switch (N->getOpcode()) {
22999 default: llvm_unreachable("unknown opcode");
23000 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
23001 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
23004 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
23005 N->getOperand(0), N->getOperand(1));
23008 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
23009 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
23010 // FAND(0.0, x) -> 0.0
23011 // FAND(x, 0.0) -> 0.0
23012 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
23013 if (C->getValueAPF().isPosZero())
23014 return N->getOperand(0);
23015 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
23016 if (C->getValueAPF().isPosZero())
23017 return N->getOperand(1);
23021 /// PerformFANDNCombine - Do target-specific dag combines on X86ISD::FANDN nodes
23022 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
23023 // FANDN(x, 0.0) -> 0.0
23024 // FANDN(0.0, x) -> x
23025 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
23026 if (C->getValueAPF().isPosZero())
23027 return N->getOperand(1);
23028 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
23029 if (C->getValueAPF().isPosZero())
23030 return N->getOperand(1);
23034 static SDValue PerformBTCombine(SDNode *N,
23036 TargetLowering::DAGCombinerInfo &DCI) {
23037 // BT ignores high bits in the bit index operand.
23038 SDValue Op1 = N->getOperand(1);
23039 if (Op1.hasOneUse()) {
23040 unsigned BitWidth = Op1.getValueSizeInBits();
23041 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
23042 APInt KnownZero, KnownOne;
23043 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
23044 !DCI.isBeforeLegalizeOps());
23045 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23046 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
23047 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
23048 DCI.CommitTargetLoweringOpt(TLO);
23053 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
23054 SDValue Op = N->getOperand(0);
23055 if (Op.getOpcode() == ISD::BITCAST)
23056 Op = Op.getOperand(0);
23057 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
23058 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
23059 VT.getVectorElementType().getSizeInBits() ==
23060 OpVT.getVectorElementType().getSizeInBits()) {
23061 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
23066 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
23067 const X86Subtarget *Subtarget) {
23068 EVT VT = N->getValueType(0);
23069 if (!VT.isVector())
23072 SDValue N0 = N->getOperand(0);
23073 SDValue N1 = N->getOperand(1);
23074 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
23077 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
23078 // both SSE and AVX2 since there is no sign-extended shift right
23079 // operation on a vector with 64-bit elements.
23080 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
23081 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
23082 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
23083 N0.getOpcode() == ISD::SIGN_EXTEND)) {
23084 SDValue N00 = N0.getOperand(0);
23086 // EXTLOAD has a better solution on AVX2,
23087 // it may be replaced with X86ISD::VSEXT node.
23088 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
23089 if (!ISD::isNormalLoad(N00.getNode()))
23092 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
23093 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
23095 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
23101 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
23102 TargetLowering::DAGCombinerInfo &DCI,
23103 const X86Subtarget *Subtarget) {
23104 if (!DCI.isBeforeLegalizeOps())
23107 if (!Subtarget->hasFp256())
23110 EVT VT = N->getValueType(0);
23111 if (VT.isVector() && VT.getSizeInBits() == 256) {
23112 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
23120 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
23121 const X86Subtarget* Subtarget) {
23123 EVT VT = N->getValueType(0);
23125 // Let legalize expand this if it isn't a legal type yet.
23126 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
23129 EVT ScalarVT = VT.getScalarType();
23130 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
23131 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
23134 SDValue A = N->getOperand(0);
23135 SDValue B = N->getOperand(1);
23136 SDValue C = N->getOperand(2);
23138 bool NegA = (A.getOpcode() == ISD::FNEG);
23139 bool NegB = (B.getOpcode() == ISD::FNEG);
23140 bool NegC = (C.getOpcode() == ISD::FNEG);
23142 // Negative multiplication when NegA xor NegB
23143 bool NegMul = (NegA != NegB);
23145 A = A.getOperand(0);
23147 B = B.getOperand(0);
23149 C = C.getOperand(0);
23153 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
23155 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
23157 return DAG.getNode(Opcode, dl, VT, A, B, C);
23160 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
23161 TargetLowering::DAGCombinerInfo &DCI,
23162 const X86Subtarget *Subtarget) {
23163 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
23164 // (and (i32 x86isd::setcc_carry), 1)
23165 // This eliminates the zext. This transformation is necessary because
23166 // ISD::SETCC is always legalized to i8.
23168 SDValue N0 = N->getOperand(0);
23169 EVT VT = N->getValueType(0);
23171 if (N0.getOpcode() == ISD::AND &&
23173 N0.getOperand(0).hasOneUse()) {
23174 SDValue N00 = N0.getOperand(0);
23175 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
23176 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
23177 if (!C || C->getZExtValue() != 1)
23179 return DAG.getNode(ISD::AND, dl, VT,
23180 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
23181 N00.getOperand(0), N00.getOperand(1)),
23182 DAG.getConstant(1, VT));
23186 if (N0.getOpcode() == ISD::TRUNCATE &&
23188 N0.getOperand(0).hasOneUse()) {
23189 SDValue N00 = N0.getOperand(0);
23190 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
23191 return DAG.getNode(ISD::AND, dl, VT,
23192 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
23193 N00.getOperand(0), N00.getOperand(1)),
23194 DAG.getConstant(1, VT));
23197 if (VT.is256BitVector()) {
23198 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
23206 // Optimize x == -y --> x+y == 0
23207 // x != -y --> x+y != 0
23208 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
23209 const X86Subtarget* Subtarget) {
23210 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
23211 SDValue LHS = N->getOperand(0);
23212 SDValue RHS = N->getOperand(1);
23213 EVT VT = N->getValueType(0);
23216 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
23217 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
23218 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
23219 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
23220 LHS.getValueType(), RHS, LHS.getOperand(1));
23221 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
23222 addV, DAG.getConstant(0, addV.getValueType()), CC);
23224 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
23225 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
23226 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
23227 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
23228 RHS.getValueType(), LHS, RHS.getOperand(1));
23229 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
23230 addV, DAG.getConstant(0, addV.getValueType()), CC);
23233 if (VT.getScalarType() == MVT::i1) {
23234 bool IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
23235 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
23236 bool IsVZero0 = ISD::isBuildVectorAllZeros(LHS.getNode());
23237 if (!IsSEXT0 && !IsVZero0)
23239 bool IsSEXT1 = (RHS.getOpcode() == ISD::SIGN_EXTEND) &&
23240 (RHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
23241 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
23243 if (!IsSEXT1 && !IsVZero1)
23246 if (IsSEXT0 && IsVZero1) {
23247 assert(VT == LHS.getOperand(0).getValueType() && "Uexpected operand type");
23248 if (CC == ISD::SETEQ)
23249 return DAG.getNOT(DL, LHS.getOperand(0), VT);
23250 return LHS.getOperand(0);
23252 if (IsSEXT1 && IsVZero0) {
23253 assert(VT == RHS.getOperand(0).getValueType() && "Uexpected operand type");
23254 if (CC == ISD::SETEQ)
23255 return DAG.getNOT(DL, RHS.getOperand(0), VT);
23256 return RHS.getOperand(0);
23263 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
23264 const X86Subtarget *Subtarget) {
23266 MVT VT = N->getOperand(1)->getSimpleValueType(0);
23267 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
23268 "X86insertps is only defined for v4x32");
23270 SDValue Ld = N->getOperand(1);
23271 if (MayFoldLoad(Ld)) {
23272 // Extract the countS bits from the immediate so we can get the proper
23273 // address when narrowing the vector load to a specific element.
23274 // When the second source op is a memory address, interps doesn't use
23275 // countS and just gets an f32 from that address.
23276 unsigned DestIndex =
23277 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
23278 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
23282 // Create this as a scalar to vector to match the instruction pattern.
23283 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
23284 // countS bits are ignored when loading from memory on insertps, which
23285 // means we don't need to explicitly set them to 0.
23286 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
23287 LoadScalarToVector, N->getOperand(2));
23290 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
23291 // as "sbb reg,reg", since it can be extended without zext and produces
23292 // an all-ones bit which is more useful than 0/1 in some cases.
23293 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
23296 return DAG.getNode(ISD::AND, DL, VT,
23297 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
23298 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
23299 DAG.getConstant(1, VT));
23300 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
23301 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
23302 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
23303 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS));
23306 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
23307 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
23308 TargetLowering::DAGCombinerInfo &DCI,
23309 const X86Subtarget *Subtarget) {
23311 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
23312 SDValue EFLAGS = N->getOperand(1);
23314 if (CC == X86::COND_A) {
23315 // Try to convert COND_A into COND_B in an attempt to facilitate
23316 // materializing "setb reg".
23318 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
23319 // cannot take an immediate as its first operand.
23321 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
23322 EFLAGS.getValueType().isInteger() &&
23323 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
23324 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
23325 EFLAGS.getNode()->getVTList(),
23326 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
23327 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
23328 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
23332 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
23333 // a zext and produces an all-ones bit which is more useful than 0/1 in some
23335 if (CC == X86::COND_B)
23336 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
23340 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
23341 if (Flags.getNode()) {
23342 SDValue Cond = DAG.getConstant(CC, MVT::i8);
23343 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
23349 // Optimize branch condition evaluation.
23351 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
23352 TargetLowering::DAGCombinerInfo &DCI,
23353 const X86Subtarget *Subtarget) {
23355 SDValue Chain = N->getOperand(0);
23356 SDValue Dest = N->getOperand(1);
23357 SDValue EFLAGS = N->getOperand(3);
23358 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
23362 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
23363 if (Flags.getNode()) {
23364 SDValue Cond = DAG.getConstant(CC, MVT::i8);
23365 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
23372 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
23373 SelectionDAG &DAG) {
23374 // Take advantage of vector comparisons producing 0 or -1 in each lane to
23375 // optimize away operation when it's from a constant.
23377 // The general transformation is:
23378 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
23379 // AND(VECTOR_CMP(x,y), constant2)
23380 // constant2 = UNARYOP(constant)
23382 // Early exit if this isn't a vector operation, the operand of the
23383 // unary operation isn't a bitwise AND, or if the sizes of the operations
23384 // aren't the same.
23385 EVT VT = N->getValueType(0);
23386 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
23387 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
23388 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
23391 // Now check that the other operand of the AND is a constant. We could
23392 // make the transformation for non-constant splats as well, but it's unclear
23393 // that would be a benefit as it would not eliminate any operations, just
23394 // perform one more step in scalar code before moving to the vector unit.
23395 if (BuildVectorSDNode *BV =
23396 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
23397 // Bail out if the vector isn't a constant.
23398 if (!BV->isConstant())
23401 // Everything checks out. Build up the new and improved node.
23403 EVT IntVT = BV->getValueType(0);
23404 // Create a new constant of the appropriate type for the transformed
23406 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
23407 // The AND node needs bitcasts to/from an integer vector type around it.
23408 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);
23409 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
23410 N->getOperand(0)->getOperand(0), MaskConst);
23411 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
23418 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
23419 const X86TargetLowering *XTLI) {
23420 // First try to optimize away the conversion entirely when it's
23421 // conditionally from a constant. Vectors only.
23422 SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG);
23423 if (Res != SDValue())
23426 // Now move on to more general possibilities.
23427 SDValue Op0 = N->getOperand(0);
23428 EVT InVT = Op0->getValueType(0);
23430 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
23431 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
23433 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
23434 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
23435 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
23438 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
23439 // a 32-bit target where SSE doesn't support i64->FP operations.
23440 if (Op0.getOpcode() == ISD::LOAD) {
23441 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
23442 EVT VT = Ld->getValueType(0);
23443 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
23444 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
23445 !XTLI->getSubtarget()->is64Bit() &&
23447 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
23448 Ld->getChain(), Op0, DAG);
23449 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
23456 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
23457 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
23458 X86TargetLowering::DAGCombinerInfo &DCI) {
23459 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
23460 // the result is either zero or one (depending on the input carry bit).
23461 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
23462 if (X86::isZeroNode(N->getOperand(0)) &&
23463 X86::isZeroNode(N->getOperand(1)) &&
23464 // We don't have a good way to replace an EFLAGS use, so only do this when
23466 SDValue(N, 1).use_empty()) {
23468 EVT VT = N->getValueType(0);
23469 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
23470 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
23471 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
23472 DAG.getConstant(X86::COND_B,MVT::i8),
23474 DAG.getConstant(1, VT));
23475 return DCI.CombineTo(N, Res1, CarryOut);
23481 // fold (add Y, (sete X, 0)) -> adc 0, Y
23482 // (add Y, (setne X, 0)) -> sbb -1, Y
23483 // (sub (sete X, 0), Y) -> sbb 0, Y
23484 // (sub (setne X, 0), Y) -> adc -1, Y
23485 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
23488 // Look through ZExts.
23489 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
23490 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
23493 SDValue SetCC = Ext.getOperand(0);
23494 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
23497 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
23498 if (CC != X86::COND_E && CC != X86::COND_NE)
23501 SDValue Cmp = SetCC.getOperand(1);
23502 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
23503 !X86::isZeroNode(Cmp.getOperand(1)) ||
23504 !Cmp.getOperand(0).getValueType().isInteger())
23507 SDValue CmpOp0 = Cmp.getOperand(0);
23508 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
23509 DAG.getConstant(1, CmpOp0.getValueType()));
23511 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
23512 if (CC == X86::COND_NE)
23513 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
23514 DL, OtherVal.getValueType(), OtherVal,
23515 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
23516 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
23517 DL, OtherVal.getValueType(), OtherVal,
23518 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
23521 /// PerformADDCombine - Do target-specific dag combines on integer adds.
23522 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
23523 const X86Subtarget *Subtarget) {
23524 EVT VT = N->getValueType(0);
23525 SDValue Op0 = N->getOperand(0);
23526 SDValue Op1 = N->getOperand(1);
23528 // Try to synthesize horizontal adds from adds of shuffles.
23529 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
23530 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
23531 isHorizontalBinOp(Op0, Op1, true))
23532 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
23534 return OptimizeConditionalInDecrement(N, DAG);
23537 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
23538 const X86Subtarget *Subtarget) {
23539 SDValue Op0 = N->getOperand(0);
23540 SDValue Op1 = N->getOperand(1);
23542 // X86 can't encode an immediate LHS of a sub. See if we can push the
23543 // negation into a preceding instruction.
23544 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
23545 // If the RHS of the sub is a XOR with one use and a constant, invert the
23546 // immediate. Then add one to the LHS of the sub so we can turn
23547 // X-Y -> X+~Y+1, saving one register.
23548 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
23549 isa<ConstantSDNode>(Op1.getOperand(1))) {
23550 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
23551 EVT VT = Op0.getValueType();
23552 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
23554 DAG.getConstant(~XorC, VT));
23555 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
23556 DAG.getConstant(C->getAPIntValue()+1, VT));
23560 // Try to synthesize horizontal adds from adds of shuffles.
23561 EVT VT = N->getValueType(0);
23562 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
23563 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
23564 isHorizontalBinOp(Op0, Op1, true))
23565 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
23567 return OptimizeConditionalInDecrement(N, DAG);
23570 /// performVZEXTCombine - Performs build vector combines
23571 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
23572 TargetLowering::DAGCombinerInfo &DCI,
23573 const X86Subtarget *Subtarget) {
23574 // (vzext (bitcast (vzext (x)) -> (vzext x)
23575 SDValue In = N->getOperand(0);
23576 while (In.getOpcode() == ISD::BITCAST)
23577 In = In.getOperand(0);
23579 if (In.getOpcode() != X86ISD::VZEXT)
23582 return DAG.getNode(X86ISD::VZEXT, SDLoc(N), N->getValueType(0),
23586 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
23587 DAGCombinerInfo &DCI) const {
23588 SelectionDAG &DAG = DCI.DAG;
23589 switch (N->getOpcode()) {
23591 case ISD::EXTRACT_VECTOR_ELT:
23592 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
23594 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget);
23595 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
23596 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
23597 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
23598 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
23599 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
23602 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
23603 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
23604 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
23605 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
23606 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
23607 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
23608 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
23609 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
23610 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
23612 case X86ISD::FOR: return PerformFORCombine(N, DAG);
23614 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
23615 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
23616 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
23617 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
23618 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
23619 case ISD::ANY_EXTEND:
23620 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
23621 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
23622 case ISD::SIGN_EXTEND_INREG:
23623 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
23624 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
23625 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
23626 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
23627 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
23628 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
23629 case X86ISD::SHUFP: // Handle all target specific shuffles
23630 case X86ISD::PALIGNR:
23631 case X86ISD::UNPCKH:
23632 case X86ISD::UNPCKL:
23633 case X86ISD::MOVHLPS:
23634 case X86ISD::MOVLHPS:
23635 case X86ISD::PSHUFB:
23636 case X86ISD::PSHUFD:
23637 case X86ISD::PSHUFHW:
23638 case X86ISD::PSHUFLW:
23639 case X86ISD::MOVSS:
23640 case X86ISD::MOVSD:
23641 case X86ISD::VPERMILP:
23642 case X86ISD::VPERM2X128:
23643 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
23644 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
23645 case ISD::INTRINSIC_WO_CHAIN:
23646 return PerformINTRINSIC_WO_CHAINCombine(N, DAG, Subtarget);
23647 case X86ISD::INSERTPS:
23648 return PerformINSERTPSCombine(N, DAG, Subtarget);
23649 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DAG, Subtarget);
23655 /// isTypeDesirableForOp - Return true if the target has native support for
23656 /// the specified value type and it is 'desirable' to use the type for the
23657 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
23658 /// instruction encodings are longer and some i16 instructions are slow.
23659 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
23660 if (!isTypeLegal(VT))
23662 if (VT != MVT::i16)
23669 case ISD::SIGN_EXTEND:
23670 case ISD::ZERO_EXTEND:
23671 case ISD::ANY_EXTEND:
23684 /// IsDesirableToPromoteOp - This method query the target whether it is
23685 /// beneficial for dag combiner to promote the specified node. If true, it
23686 /// should return the desired promotion type by reference.
23687 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
23688 EVT VT = Op.getValueType();
23689 if (VT != MVT::i16)
23692 bool Promote = false;
23693 bool Commute = false;
23694 switch (Op.getOpcode()) {
23697 LoadSDNode *LD = cast<LoadSDNode>(Op);
23698 // If the non-extending load has a single use and it's not live out, then it
23699 // might be folded.
23700 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
23701 Op.hasOneUse()*/) {
23702 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
23703 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
23704 // The only case where we'd want to promote LOAD (rather then it being
23705 // promoted as an operand is when it's only use is liveout.
23706 if (UI->getOpcode() != ISD::CopyToReg)
23713 case ISD::SIGN_EXTEND:
23714 case ISD::ZERO_EXTEND:
23715 case ISD::ANY_EXTEND:
23720 SDValue N0 = Op.getOperand(0);
23721 // Look out for (store (shl (load), x)).
23722 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
23735 SDValue N0 = Op.getOperand(0);
23736 SDValue N1 = Op.getOperand(1);
23737 if (!Commute && MayFoldLoad(N1))
23739 // Avoid disabling potential load folding opportunities.
23740 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
23742 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
23752 //===----------------------------------------------------------------------===//
23753 // X86 Inline Assembly Support
23754 //===----------------------------------------------------------------------===//
23757 // Helper to match a string separated by whitespace.
23758 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
23759 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
23761 for (unsigned i = 0, e = args.size(); i != e; ++i) {
23762 StringRef piece(*args[i]);
23763 if (!s.startswith(piece)) // Check if the piece matches.
23766 s = s.substr(piece.size());
23767 StringRef::size_type pos = s.find_first_not_of(" \t");
23768 if (pos == 0) // We matched a prefix.
23776 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
23779 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
23781 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
23782 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
23783 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
23784 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
23786 if (AsmPieces.size() == 3)
23788 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
23795 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
23796 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
23798 std::string AsmStr = IA->getAsmString();
23800 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
23801 if (!Ty || Ty->getBitWidth() % 16 != 0)
23804 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
23805 SmallVector<StringRef, 4> AsmPieces;
23806 SplitString(AsmStr, AsmPieces, ";\n");
23808 switch (AsmPieces.size()) {
23809 default: return false;
23811 // FIXME: this should verify that we are targeting a 486 or better. If not,
23812 // we will turn this bswap into something that will be lowered to logical
23813 // ops instead of emitting the bswap asm. For now, we don't support 486 or
23814 // lower so don't worry about this.
23816 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
23817 matchAsm(AsmPieces[0], "bswapl", "$0") ||
23818 matchAsm(AsmPieces[0], "bswapq", "$0") ||
23819 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
23820 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
23821 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
23822 // No need to check constraints, nothing other than the equivalent of
23823 // "=r,0" would be valid here.
23824 return IntrinsicLowering::LowerToByteSwap(CI);
23827 // rorw $$8, ${0:w} --> llvm.bswap.i16
23828 if (CI->getType()->isIntegerTy(16) &&
23829 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
23830 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
23831 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
23833 const std::string &ConstraintsStr = IA->getConstraintString();
23834 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
23835 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
23836 if (clobbersFlagRegisters(AsmPieces))
23837 return IntrinsicLowering::LowerToByteSwap(CI);
23841 if (CI->getType()->isIntegerTy(32) &&
23842 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
23843 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
23844 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
23845 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
23847 const std::string &ConstraintsStr = IA->getConstraintString();
23848 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
23849 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
23850 if (clobbersFlagRegisters(AsmPieces))
23851 return IntrinsicLowering::LowerToByteSwap(CI);
23854 if (CI->getType()->isIntegerTy(64)) {
23855 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
23856 if (Constraints.size() >= 2 &&
23857 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
23858 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
23859 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
23860 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
23861 matchAsm(AsmPieces[1], "bswap", "%edx") &&
23862 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
23863 return IntrinsicLowering::LowerToByteSwap(CI);
23871 /// getConstraintType - Given a constraint letter, return the type of
23872 /// constraint it is for this target.
23873 X86TargetLowering::ConstraintType
23874 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
23875 if (Constraint.size() == 1) {
23876 switch (Constraint[0]) {
23887 return C_RegisterClass;
23911 return TargetLowering::getConstraintType(Constraint);
23914 /// Examine constraint type and operand type and determine a weight value.
23915 /// This object must already have been set up with the operand type
23916 /// and the current alternative constraint selected.
23917 TargetLowering::ConstraintWeight
23918 X86TargetLowering::getSingleConstraintMatchWeight(
23919 AsmOperandInfo &info, const char *constraint) const {
23920 ConstraintWeight weight = CW_Invalid;
23921 Value *CallOperandVal = info.CallOperandVal;
23922 // If we don't have a value, we can't do a match,
23923 // but allow it at the lowest weight.
23924 if (!CallOperandVal)
23926 Type *type = CallOperandVal->getType();
23927 // Look at the constraint type.
23928 switch (*constraint) {
23930 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
23941 if (CallOperandVal->getType()->isIntegerTy())
23942 weight = CW_SpecificReg;
23947 if (type->isFloatingPointTy())
23948 weight = CW_SpecificReg;
23951 if (type->isX86_MMXTy() && Subtarget->hasMMX())
23952 weight = CW_SpecificReg;
23956 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
23957 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
23958 weight = CW_Register;
23961 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
23962 if (C->getZExtValue() <= 31)
23963 weight = CW_Constant;
23967 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
23968 if (C->getZExtValue() <= 63)
23969 weight = CW_Constant;
23973 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
23974 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
23975 weight = CW_Constant;
23979 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
23980 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
23981 weight = CW_Constant;
23985 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
23986 if (C->getZExtValue() <= 3)
23987 weight = CW_Constant;
23991 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
23992 if (C->getZExtValue() <= 0xff)
23993 weight = CW_Constant;
23998 if (dyn_cast<ConstantFP>(CallOperandVal)) {
23999 weight = CW_Constant;
24003 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24004 if ((C->getSExtValue() >= -0x80000000LL) &&
24005 (C->getSExtValue() <= 0x7fffffffLL))
24006 weight = CW_Constant;
24010 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24011 if (C->getZExtValue() <= 0xffffffff)
24012 weight = CW_Constant;
24019 /// LowerXConstraint - try to replace an X constraint, which matches anything,
24020 /// with another that has more specific requirements based on the type of the
24021 /// corresponding operand.
24022 const char *X86TargetLowering::
24023 LowerXConstraint(EVT ConstraintVT) const {
24024 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
24025 // 'f' like normal targets.
24026 if (ConstraintVT.isFloatingPoint()) {
24027 if (Subtarget->hasSSE2())
24029 if (Subtarget->hasSSE1())
24033 return TargetLowering::LowerXConstraint(ConstraintVT);
24036 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
24037 /// vector. If it is invalid, don't add anything to Ops.
24038 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
24039 std::string &Constraint,
24040 std::vector<SDValue>&Ops,
24041 SelectionDAG &DAG) const {
24044 // Only support length 1 constraints for now.
24045 if (Constraint.length() > 1) return;
24047 char ConstraintLetter = Constraint[0];
24048 switch (ConstraintLetter) {
24051 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24052 if (C->getZExtValue() <= 31) {
24053 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24059 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24060 if (C->getZExtValue() <= 63) {
24061 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24067 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24068 if (isInt<8>(C->getSExtValue())) {
24069 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24075 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24076 if (C->getZExtValue() <= 255) {
24077 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24083 // 32-bit signed value
24084 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24085 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
24086 C->getSExtValue())) {
24087 // Widen to 64 bits here to get it sign extended.
24088 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
24091 // FIXME gcc accepts some relocatable values here too, but only in certain
24092 // memory models; it's complicated.
24097 // 32-bit unsigned value
24098 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24099 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
24100 C->getZExtValue())) {
24101 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24105 // FIXME gcc accepts some relocatable values here too, but only in certain
24106 // memory models; it's complicated.
24110 // Literal immediates are always ok.
24111 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
24112 // Widen to 64 bits here to get it sign extended.
24113 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
24117 // In any sort of PIC mode addresses need to be computed at runtime by
24118 // adding in a register or some sort of table lookup. These can't
24119 // be used as immediates.
24120 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
24123 // If we are in non-pic codegen mode, we allow the address of a global (with
24124 // an optional displacement) to be used with 'i'.
24125 GlobalAddressSDNode *GA = nullptr;
24126 int64_t Offset = 0;
24128 // Match either (GA), (GA+C), (GA+C1+C2), etc.
24130 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
24131 Offset += GA->getOffset();
24133 } else if (Op.getOpcode() == ISD::ADD) {
24134 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
24135 Offset += C->getZExtValue();
24136 Op = Op.getOperand(0);
24139 } else if (Op.getOpcode() == ISD::SUB) {
24140 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
24141 Offset += -C->getZExtValue();
24142 Op = Op.getOperand(0);
24147 // Otherwise, this isn't something we can handle, reject it.
24151 const GlobalValue *GV = GA->getGlobal();
24152 // If we require an extra load to get this address, as in PIC mode, we
24153 // can't accept it.
24154 if (isGlobalStubReference(
24155 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
24158 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
24159 GA->getValueType(0), Offset);
24164 if (Result.getNode()) {
24165 Ops.push_back(Result);
24168 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
24171 std::pair<unsigned, const TargetRegisterClass*>
24172 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
24174 // First, see if this is a constraint that directly corresponds to an LLVM
24176 if (Constraint.size() == 1) {
24177 // GCC Constraint Letters
24178 switch (Constraint[0]) {
24180 // TODO: Slight differences here in allocation order and leaving
24181 // RIP in the class. Do they matter any more here than they do
24182 // in the normal allocation?
24183 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
24184 if (Subtarget->is64Bit()) {
24185 if (VT == MVT::i32 || VT == MVT::f32)
24186 return std::make_pair(0U, &X86::GR32RegClass);
24187 if (VT == MVT::i16)
24188 return std::make_pair(0U, &X86::GR16RegClass);
24189 if (VT == MVT::i8 || VT == MVT::i1)
24190 return std::make_pair(0U, &X86::GR8RegClass);
24191 if (VT == MVT::i64 || VT == MVT::f64)
24192 return std::make_pair(0U, &X86::GR64RegClass);
24195 // 32-bit fallthrough
24196 case 'Q': // Q_REGS
24197 if (VT == MVT::i32 || VT == MVT::f32)
24198 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
24199 if (VT == MVT::i16)
24200 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
24201 if (VT == MVT::i8 || VT == MVT::i1)
24202 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
24203 if (VT == MVT::i64)
24204 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
24206 case 'r': // GENERAL_REGS
24207 case 'l': // INDEX_REGS
24208 if (VT == MVT::i8 || VT == MVT::i1)
24209 return std::make_pair(0U, &X86::GR8RegClass);
24210 if (VT == MVT::i16)
24211 return std::make_pair(0U, &X86::GR16RegClass);
24212 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
24213 return std::make_pair(0U, &X86::GR32RegClass);
24214 return std::make_pair(0U, &X86::GR64RegClass);
24215 case 'R': // LEGACY_REGS
24216 if (VT == MVT::i8 || VT == MVT::i1)
24217 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
24218 if (VT == MVT::i16)
24219 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
24220 if (VT == MVT::i32 || !Subtarget->is64Bit())
24221 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
24222 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
24223 case 'f': // FP Stack registers.
24224 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
24225 // value to the correct fpstack register class.
24226 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
24227 return std::make_pair(0U, &X86::RFP32RegClass);
24228 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
24229 return std::make_pair(0U, &X86::RFP64RegClass);
24230 return std::make_pair(0U, &X86::RFP80RegClass);
24231 case 'y': // MMX_REGS if MMX allowed.
24232 if (!Subtarget->hasMMX()) break;
24233 return std::make_pair(0U, &X86::VR64RegClass);
24234 case 'Y': // SSE_REGS if SSE2 allowed
24235 if (!Subtarget->hasSSE2()) break;
24237 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
24238 if (!Subtarget->hasSSE1()) break;
24240 switch (VT.SimpleTy) {
24242 // Scalar SSE types.
24245 return std::make_pair(0U, &X86::FR32RegClass);
24248 return std::make_pair(0U, &X86::FR64RegClass);
24256 return std::make_pair(0U, &X86::VR128RegClass);
24264 return std::make_pair(0U, &X86::VR256RegClass);
24269 return std::make_pair(0U, &X86::VR512RegClass);
24275 // Use the default implementation in TargetLowering to convert the register
24276 // constraint into a member of a register class.
24277 std::pair<unsigned, const TargetRegisterClass*> Res;
24278 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
24280 // Not found as a standard register?
24282 // Map st(0) -> st(7) -> ST0
24283 if (Constraint.size() == 7 && Constraint[0] == '{' &&
24284 tolower(Constraint[1]) == 's' &&
24285 tolower(Constraint[2]) == 't' &&
24286 Constraint[3] == '(' &&
24287 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
24288 Constraint[5] == ')' &&
24289 Constraint[6] == '}') {
24291 Res.first = X86::FP0+Constraint[4]-'0';
24292 Res.second = &X86::RFP80RegClass;
24296 // GCC allows "st(0)" to be called just plain "st".
24297 if (StringRef("{st}").equals_lower(Constraint)) {
24298 Res.first = X86::FP0;
24299 Res.second = &X86::RFP80RegClass;
24304 if (StringRef("{flags}").equals_lower(Constraint)) {
24305 Res.first = X86::EFLAGS;
24306 Res.second = &X86::CCRRegClass;
24310 // 'A' means EAX + EDX.
24311 if (Constraint == "A") {
24312 Res.first = X86::EAX;
24313 Res.second = &X86::GR32_ADRegClass;
24319 // Otherwise, check to see if this is a register class of the wrong value
24320 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
24321 // turn into {ax},{dx}.
24322 if (Res.second->hasType(VT))
24323 return Res; // Correct type already, nothing to do.
24325 // All of the single-register GCC register classes map their values onto
24326 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
24327 // really want an 8-bit or 32-bit register, map to the appropriate register
24328 // class and return the appropriate register.
24329 if (Res.second == &X86::GR16RegClass) {
24330 if (VT == MVT::i8 || VT == MVT::i1) {
24331 unsigned DestReg = 0;
24332 switch (Res.first) {
24334 case X86::AX: DestReg = X86::AL; break;
24335 case X86::DX: DestReg = X86::DL; break;
24336 case X86::CX: DestReg = X86::CL; break;
24337 case X86::BX: DestReg = X86::BL; break;
24340 Res.first = DestReg;
24341 Res.second = &X86::GR8RegClass;
24343 } else if (VT == MVT::i32 || VT == MVT::f32) {
24344 unsigned DestReg = 0;
24345 switch (Res.first) {
24347 case X86::AX: DestReg = X86::EAX; break;
24348 case X86::DX: DestReg = X86::EDX; break;
24349 case X86::CX: DestReg = X86::ECX; break;
24350 case X86::BX: DestReg = X86::EBX; break;
24351 case X86::SI: DestReg = X86::ESI; break;
24352 case X86::DI: DestReg = X86::EDI; break;
24353 case X86::BP: DestReg = X86::EBP; break;
24354 case X86::SP: DestReg = X86::ESP; break;
24357 Res.first = DestReg;
24358 Res.second = &X86::GR32RegClass;
24360 } else if (VT == MVT::i64 || VT == MVT::f64) {
24361 unsigned DestReg = 0;
24362 switch (Res.first) {
24364 case X86::AX: DestReg = X86::RAX; break;
24365 case X86::DX: DestReg = X86::RDX; break;
24366 case X86::CX: DestReg = X86::RCX; break;
24367 case X86::BX: DestReg = X86::RBX; break;
24368 case X86::SI: DestReg = X86::RSI; break;
24369 case X86::DI: DestReg = X86::RDI; break;
24370 case X86::BP: DestReg = X86::RBP; break;
24371 case X86::SP: DestReg = X86::RSP; break;
24374 Res.first = DestReg;
24375 Res.second = &X86::GR64RegClass;
24378 } else if (Res.second == &X86::FR32RegClass ||
24379 Res.second == &X86::FR64RegClass ||
24380 Res.second == &X86::VR128RegClass ||
24381 Res.second == &X86::VR256RegClass ||
24382 Res.second == &X86::FR32XRegClass ||
24383 Res.second == &X86::FR64XRegClass ||
24384 Res.second == &X86::VR128XRegClass ||
24385 Res.second == &X86::VR256XRegClass ||
24386 Res.second == &X86::VR512RegClass) {
24387 // Handle references to XMM physical registers that got mapped into the
24388 // wrong class. This can happen with constraints like {xmm0} where the
24389 // target independent register mapper will just pick the first match it can
24390 // find, ignoring the required type.
24392 if (VT == MVT::f32 || VT == MVT::i32)
24393 Res.second = &X86::FR32RegClass;
24394 else if (VT == MVT::f64 || VT == MVT::i64)
24395 Res.second = &X86::FR64RegClass;
24396 else if (X86::VR128RegClass.hasType(VT))
24397 Res.second = &X86::VR128RegClass;
24398 else if (X86::VR256RegClass.hasType(VT))
24399 Res.second = &X86::VR256RegClass;
24400 else if (X86::VR512RegClass.hasType(VT))
24401 Res.second = &X86::VR512RegClass;
24407 int X86TargetLowering::getScalingFactorCost(const AddrMode &AM,
24409 // Scaling factors are not free at all.
24410 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
24411 // will take 2 allocations in the out of order engine instead of 1
24412 // for plain addressing mode, i.e. inst (reg1).
24414 // vaddps (%rsi,%drx), %ymm0, %ymm1
24415 // Requires two allocations (one for the load, one for the computation)
24417 // vaddps (%rsi), %ymm0, %ymm1
24418 // Requires just 1 allocation, i.e., freeing allocations for other operations
24419 // and having less micro operations to execute.
24421 // For some X86 architectures, this is even worse because for instance for
24422 // stores, the complex addressing mode forces the instruction to use the
24423 // "load" ports instead of the dedicated "store" port.
24424 // E.g., on Haswell:
24425 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
24426 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
24427 if (isLegalAddressingMode(AM, Ty))
24428 // Scale represents reg2 * scale, thus account for 1
24429 // as soon as we use a second register.
24430 return AM.Scale != 0;
24434 bool X86TargetLowering::isTargetFTOL() const {
24435 return Subtarget->isTargetKnownWindowsMSVC() && !Subtarget->is64Bit();