1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
16 #include "X86InstrBuilder.h"
17 #include "X86ISelLowering.h"
18 #include "X86MachineFunctionInfo.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/CallingConv.h"
21 #include "llvm/Constants.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/Function.h"
25 #include "llvm/Intrinsics.h"
26 #include "llvm/ADT/VectorExtras.h"
27 #include "llvm/Analysis/ScalarEvolutionExpressions.h"
28 #include "llvm/CodeGen/CallingConvLower.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/SelectionDAG.h"
33 #include "llvm/CodeGen/SSARegMap.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/Support/MathExtras.h"
36 #include "llvm/Target/TargetOptions.h"
37 #include "llvm/ADT/StringExtras.h"
38 #include "llvm/ParameterAttributes.h"
41 X86TargetLowering::X86TargetLowering(TargetMachine &TM)
42 : TargetLowering(TM) {
43 Subtarget = &TM.getSubtarget<X86Subtarget>();
44 X86ScalarSSEf64 = Subtarget->hasSSE2();
45 X86ScalarSSEf32 = Subtarget->hasSSE1();
46 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
48 RegInfo = TM.getRegisterInfo();
50 // Set up the TargetLowering object.
52 // X86 is weird, it always uses i8 for shift amounts and setcc results.
53 setShiftAmountType(MVT::i8);
54 setSetCCResultType(MVT::i8);
55 setSetCCResultContents(ZeroOrOneSetCCResult);
56 setSchedulingPreference(SchedulingForRegPressure);
57 setShiftAmountFlavor(Mask); // shl X, 32 == shl X, 0
58 setStackPointerRegisterToSaveRestore(X86StackPtr);
60 if (Subtarget->isTargetDarwin()) {
61 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
62 setUseUnderscoreSetJmp(false);
63 setUseUnderscoreLongJmp(false);
64 } else if (Subtarget->isTargetMingw()) {
65 // MS runtime is weird: it exports _setjmp, but longjmp!
66 setUseUnderscoreSetJmp(true);
67 setUseUnderscoreLongJmp(false);
69 setUseUnderscoreSetJmp(true);
70 setUseUnderscoreLongJmp(true);
73 // Set up the register classes.
74 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
75 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
76 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
77 if (Subtarget->is64Bit())
78 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
80 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Expand);
82 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
84 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
85 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
86 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
88 if (Subtarget->is64Bit()) {
89 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand);
90 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
93 // If SSE i64 SINT_TO_FP is not available, expand i32 UINT_TO_FP.
94 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Expand);
96 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
99 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
101 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
102 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
103 // SSE has no i16 to fp conversion, only i32
104 if (X86ScalarSSEf32) {
105 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
106 // f32 and f64 cases are Legal, f80 case is not
107 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
109 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
110 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
113 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
114 // are Legal, f80 is custom lowered.
115 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
116 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
118 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
120 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
121 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
123 if (X86ScalarSSEf32) {
124 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
125 // f32 and f64 cases are Legal, f80 case is not
126 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
128 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
129 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
132 // Handle FP_TO_UINT by promoting the destination to a larger signed
134 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
135 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
136 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
138 if (Subtarget->is64Bit()) {
139 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
140 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
142 if (X86ScalarSSEf32 && !Subtarget->hasSSE3())
143 // Expand FP_TO_UINT into a select.
144 // FIXME: We would like to use a Custom expander here eventually to do
145 // the optimal thing for SSE vs. the default expansion in the legalizer.
146 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
148 // With SSE3 we can use fisttpll to convert to a signed i64.
149 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
152 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
153 if (!X86ScalarSSEf64) {
154 setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand);
155 setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand);
158 // Divide and remainder are lowered to use div or idiv in legalize in
159 // order to expose the intermediate computations to trivial CSE. This is
160 // most noticeable when both x/y and x%y are being computed; they can be
161 // done with a single div or idiv.
162 setOperationAction(ISD::SDIV , MVT::i8 , Custom);
163 setOperationAction(ISD::UDIV , MVT::i8 , Custom);
164 setOperationAction(ISD::SREM , MVT::i8 , Custom);
165 setOperationAction(ISD::UREM , MVT::i8 , Custom);
166 setOperationAction(ISD::SDIV , MVT::i16 , Custom);
167 setOperationAction(ISD::UDIV , MVT::i16 , Custom);
168 setOperationAction(ISD::SREM , MVT::i16 , Custom);
169 setOperationAction(ISD::UREM , MVT::i16 , Custom);
170 setOperationAction(ISD::SDIV , MVT::i32 , Custom);
171 setOperationAction(ISD::UDIV , MVT::i32 , Custom);
172 setOperationAction(ISD::SREM , MVT::i32 , Custom);
173 setOperationAction(ISD::UREM , MVT::i32 , Custom);
174 setOperationAction(ISD::SDIV , MVT::i64 , Custom);
175 setOperationAction(ISD::UDIV , MVT::i64 , Custom);
176 setOperationAction(ISD::SREM , MVT::i64 , Custom);
177 setOperationAction(ISD::UREM , MVT::i64 , Custom);
179 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
180 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
181 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
182 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
183 setOperationAction(ISD::MEMMOVE , MVT::Other, Expand);
184 if (Subtarget->is64Bit())
185 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
186 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
187 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
188 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
189 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
190 setOperationAction(ISD::FREM , MVT::f64 , Expand);
192 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
193 setOperationAction(ISD::CTTZ , MVT::i8 , Expand);
194 setOperationAction(ISD::CTLZ , MVT::i8 , Expand);
195 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
196 setOperationAction(ISD::CTTZ , MVT::i16 , Expand);
197 setOperationAction(ISD::CTLZ , MVT::i16 , Expand);
198 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
199 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
200 setOperationAction(ISD::CTLZ , MVT::i32 , Expand);
201 if (Subtarget->is64Bit()) {
202 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
203 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
204 setOperationAction(ISD::CTLZ , MVT::i64 , Expand);
207 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
208 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
210 // These should be promoted to a larger select which is supported.
211 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
212 setOperationAction(ISD::SELECT , MVT::i8 , Promote);
213 // X86 wants to expand cmov itself.
214 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
215 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
216 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
217 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
218 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
219 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
220 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
221 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
222 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
223 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
224 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
225 if (Subtarget->is64Bit()) {
226 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
227 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
229 // X86 ret instruction may pop stack.
230 setOperationAction(ISD::RET , MVT::Other, Custom);
231 if (!Subtarget->is64Bit())
232 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
235 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
236 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
237 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
238 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
239 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
240 if (Subtarget->is64Bit()) {
241 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
242 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
243 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
244 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
246 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
247 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
248 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
249 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
250 // X86 wants to expand memset / memcpy itself.
251 setOperationAction(ISD::MEMSET , MVT::Other, Custom);
252 setOperationAction(ISD::MEMCPY , MVT::Other, Custom);
254 // Use the default ISD::LOCATION expansion.
255 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
256 // FIXME - use subtarget debug flags
257 if (!Subtarget->isTargetDarwin() &&
258 !Subtarget->isTargetELF() &&
259 !Subtarget->isTargetCygMing())
260 setOperationAction(ISD::LABEL, MVT::Other, Expand);
262 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
263 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
264 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
265 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
266 if (Subtarget->is64Bit()) {
268 setExceptionPointerRegister(X86::RAX);
269 setExceptionSelectorRegister(X86::RDX);
271 setExceptionPointerRegister(X86::EAX);
272 setExceptionSelectorRegister(X86::EDX);
274 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
276 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom);
278 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
279 setOperationAction(ISD::VASTART , MVT::Other, Custom);
280 setOperationAction(ISD::VAARG , MVT::Other, Expand);
281 setOperationAction(ISD::VAEND , MVT::Other, Expand);
282 if (Subtarget->is64Bit())
283 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
285 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
287 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
288 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
289 if (Subtarget->is64Bit())
290 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
291 if (Subtarget->isTargetCygMing())
292 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
294 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
296 if (X86ScalarSSEf64) {
297 // f32 and f64 use SSE.
298 // Set up the FP register classes.
299 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
300 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
302 // Use ANDPD to simulate FABS.
303 setOperationAction(ISD::FABS , MVT::f64, Custom);
304 setOperationAction(ISD::FABS , MVT::f32, Custom);
306 // Use XORP to simulate FNEG.
307 setOperationAction(ISD::FNEG , MVT::f64, Custom);
308 setOperationAction(ISD::FNEG , MVT::f32, Custom);
310 // Use ANDPD and ORPD to simulate FCOPYSIGN.
311 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
312 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
314 // We don't support sin/cos/fmod
315 setOperationAction(ISD::FSIN , MVT::f64, Expand);
316 setOperationAction(ISD::FCOS , MVT::f64, Expand);
317 setOperationAction(ISD::FREM , MVT::f64, Expand);
318 setOperationAction(ISD::FSIN , MVT::f32, Expand);
319 setOperationAction(ISD::FCOS , MVT::f32, Expand);
320 setOperationAction(ISD::FREM , MVT::f32, Expand);
322 // Expand FP immediates into loads from the stack, except for the special
324 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
325 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
326 addLegalFPImmediate(APFloat(+0.0)); // xorpd
327 addLegalFPImmediate(APFloat(+0.0f)); // xorps
329 // Conversions to long double (in X87) go through memory.
330 setConvertAction(MVT::f32, MVT::f80, Expand);
331 setConvertAction(MVT::f64, MVT::f80, Expand);
333 // Conversions from long double (in X87) go through memory.
334 setConvertAction(MVT::f80, MVT::f32, Expand);
335 setConvertAction(MVT::f80, MVT::f64, Expand);
336 } else if (X86ScalarSSEf32) {
337 // Use SSE for f32, x87 for f64.
338 // Set up the FP register classes.
339 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
340 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
342 // Use ANDPS to simulate FABS.
343 setOperationAction(ISD::FABS , MVT::f32, Custom);
345 // Use XORP to simulate FNEG.
346 setOperationAction(ISD::FNEG , MVT::f32, Custom);
348 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
350 // Use ANDPS and ORPS to simulate FCOPYSIGN.
351 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
352 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
354 // We don't support sin/cos/fmod
355 setOperationAction(ISD::FSIN , MVT::f32, Expand);
356 setOperationAction(ISD::FCOS , MVT::f32, Expand);
357 setOperationAction(ISD::FREM , MVT::f32, Expand);
359 // Expand FP immediates into loads from the stack, except for the special
361 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
362 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
363 addLegalFPImmediate(APFloat(+0.0f)); // xorps
364 addLegalFPImmediate(APFloat(+0.0)); // FLD0
365 addLegalFPImmediate(APFloat(+1.0)); // FLD1
366 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
367 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
369 // SSE->x87 conversions go through memory.
370 setConvertAction(MVT::f32, MVT::f64, Expand);
371 setConvertAction(MVT::f32, MVT::f80, Expand);
373 // x87->SSE truncations need to go through memory.
374 setConvertAction(MVT::f80, MVT::f32, Expand);
375 setConvertAction(MVT::f64, MVT::f32, Expand);
376 // And x87->x87 truncations also.
377 setConvertAction(MVT::f80, MVT::f64, Expand);
380 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
381 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
384 // f32 and f64 in x87.
385 // Set up the FP register classes.
386 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
387 addRegisterClass(MVT::f32, X86::RFP32RegisterClass);
389 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
390 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
391 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
392 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
394 // Floating truncations need to go through memory.
395 setConvertAction(MVT::f80, MVT::f32, Expand);
396 setConvertAction(MVT::f64, MVT::f32, Expand);
397 setConvertAction(MVT::f80, MVT::f64, Expand);
400 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
401 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
404 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
405 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
406 addLegalFPImmediate(APFloat(+0.0)); // FLD0
407 addLegalFPImmediate(APFloat(+1.0)); // FLD1
408 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
409 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
410 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
411 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
412 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
413 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
416 // Long double always uses X87.
417 addRegisterClass(MVT::f80, X86::RFP80RegisterClass);
418 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
419 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
420 setOperationAction(ISD::ConstantFP, MVT::f80, Expand);
422 // First set operation action for all vector types to expand. Then we
423 // will selectively turn on ones that can be effectively codegen'd.
424 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
425 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
426 setOperationAction(ISD::ADD , (MVT::ValueType)VT, Expand);
427 setOperationAction(ISD::SUB , (MVT::ValueType)VT, Expand);
428 setOperationAction(ISD::FADD, (MVT::ValueType)VT, Expand);
429 setOperationAction(ISD::FNEG, (MVT::ValueType)VT, Expand);
430 setOperationAction(ISD::FSUB, (MVT::ValueType)VT, Expand);
431 setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand);
432 setOperationAction(ISD::FMUL, (MVT::ValueType)VT, Expand);
433 setOperationAction(ISD::SDIV, (MVT::ValueType)VT, Expand);
434 setOperationAction(ISD::UDIV, (MVT::ValueType)VT, Expand);
435 setOperationAction(ISD::FDIV, (MVT::ValueType)VT, Expand);
436 setOperationAction(ISD::SREM, (MVT::ValueType)VT, Expand);
437 setOperationAction(ISD::UREM, (MVT::ValueType)VT, Expand);
438 setOperationAction(ISD::LOAD, (MVT::ValueType)VT, Expand);
439 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Expand);
440 setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
441 setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
442 setOperationAction(ISD::FABS, (MVT::ValueType)VT, Expand);
443 setOperationAction(ISD::FSIN, (MVT::ValueType)VT, Expand);
444 setOperationAction(ISD::FCOS, (MVT::ValueType)VT, Expand);
445 setOperationAction(ISD::FREM, (MVT::ValueType)VT, Expand);
446 setOperationAction(ISD::FPOWI, (MVT::ValueType)VT, Expand);
447 setOperationAction(ISD::FSQRT, (MVT::ValueType)VT, Expand);
448 setOperationAction(ISD::FCOPYSIGN, (MVT::ValueType)VT, Expand);
451 if (Subtarget->hasMMX()) {
452 addRegisterClass(MVT::v8i8, X86::VR64RegisterClass);
453 addRegisterClass(MVT::v4i16, X86::VR64RegisterClass);
454 addRegisterClass(MVT::v2i32, X86::VR64RegisterClass);
455 addRegisterClass(MVT::v1i64, X86::VR64RegisterClass);
457 // FIXME: add MMX packed arithmetics
459 setOperationAction(ISD::ADD, MVT::v8i8, Legal);
460 setOperationAction(ISD::ADD, MVT::v4i16, Legal);
461 setOperationAction(ISD::ADD, MVT::v2i32, Legal);
462 setOperationAction(ISD::ADD, MVT::v1i64, Legal);
464 setOperationAction(ISD::SUB, MVT::v8i8, Legal);
465 setOperationAction(ISD::SUB, MVT::v4i16, Legal);
466 setOperationAction(ISD::SUB, MVT::v2i32, Legal);
468 setOperationAction(ISD::MULHS, MVT::v4i16, Legal);
469 setOperationAction(ISD::MUL, MVT::v4i16, Legal);
471 setOperationAction(ISD::AND, MVT::v8i8, Promote);
472 AddPromotedToType (ISD::AND, MVT::v8i8, MVT::v1i64);
473 setOperationAction(ISD::AND, MVT::v4i16, Promote);
474 AddPromotedToType (ISD::AND, MVT::v4i16, MVT::v1i64);
475 setOperationAction(ISD::AND, MVT::v2i32, Promote);
476 AddPromotedToType (ISD::AND, MVT::v2i32, MVT::v1i64);
477 setOperationAction(ISD::AND, MVT::v1i64, Legal);
479 setOperationAction(ISD::OR, MVT::v8i8, Promote);
480 AddPromotedToType (ISD::OR, MVT::v8i8, MVT::v1i64);
481 setOperationAction(ISD::OR, MVT::v4i16, Promote);
482 AddPromotedToType (ISD::OR, MVT::v4i16, MVT::v1i64);
483 setOperationAction(ISD::OR, MVT::v2i32, Promote);
484 AddPromotedToType (ISD::OR, MVT::v2i32, MVT::v1i64);
485 setOperationAction(ISD::OR, MVT::v1i64, Legal);
487 setOperationAction(ISD::XOR, MVT::v8i8, Promote);
488 AddPromotedToType (ISD::XOR, MVT::v8i8, MVT::v1i64);
489 setOperationAction(ISD::XOR, MVT::v4i16, Promote);
490 AddPromotedToType (ISD::XOR, MVT::v4i16, MVT::v1i64);
491 setOperationAction(ISD::XOR, MVT::v2i32, Promote);
492 AddPromotedToType (ISD::XOR, MVT::v2i32, MVT::v1i64);
493 setOperationAction(ISD::XOR, MVT::v1i64, Legal);
495 setOperationAction(ISD::LOAD, MVT::v8i8, Promote);
496 AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v1i64);
497 setOperationAction(ISD::LOAD, MVT::v4i16, Promote);
498 AddPromotedToType (ISD::LOAD, MVT::v4i16, MVT::v1i64);
499 setOperationAction(ISD::LOAD, MVT::v2i32, Promote);
500 AddPromotedToType (ISD::LOAD, MVT::v2i32, MVT::v1i64);
501 setOperationAction(ISD::LOAD, MVT::v1i64, Legal);
503 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Custom);
504 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom);
505 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Custom);
506 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i64, Custom);
508 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom);
509 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
510 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i32, Custom);
511 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v1i64, Custom);
513 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Custom);
514 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Custom);
515 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Custom);
516 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Custom);
519 if (Subtarget->hasSSE1()) {
520 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
522 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
523 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
524 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
525 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
526 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
527 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
528 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
529 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
530 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
531 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
532 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
535 if (Subtarget->hasSSE2()) {
536 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
537 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
538 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
539 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
540 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
542 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
543 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
544 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
545 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
546 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
547 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
548 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
549 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
550 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
551 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
552 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
553 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
554 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
555 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
556 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
558 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
559 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
560 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
561 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
562 // Implement v4f32 insert_vector_elt in terms of SSE2 v8i16 ones.
563 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
565 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
566 for (unsigned VT = (unsigned)MVT::v16i8; VT != (unsigned)MVT::v2i64; VT++) {
567 setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Custom);
568 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Custom);
569 setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Custom);
571 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
572 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
573 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
574 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
575 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
576 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
578 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
579 for (unsigned VT = (unsigned)MVT::v16i8; VT != (unsigned)MVT::v2i64; VT++) {
580 setOperationAction(ISD::AND, (MVT::ValueType)VT, Promote);
581 AddPromotedToType (ISD::AND, (MVT::ValueType)VT, MVT::v2i64);
582 setOperationAction(ISD::OR, (MVT::ValueType)VT, Promote);
583 AddPromotedToType (ISD::OR, (MVT::ValueType)VT, MVT::v2i64);
584 setOperationAction(ISD::XOR, (MVT::ValueType)VT, Promote);
585 AddPromotedToType (ISD::XOR, (MVT::ValueType)VT, MVT::v2i64);
586 setOperationAction(ISD::LOAD, (MVT::ValueType)VT, Promote);
587 AddPromotedToType (ISD::LOAD, (MVT::ValueType)VT, MVT::v2i64);
588 setOperationAction(ISD::SELECT, (MVT::ValueType)VT, Promote);
589 AddPromotedToType (ISD::SELECT, (MVT::ValueType)VT, MVT::v2i64);
592 // Custom lower v2i64 and v2f64 selects.
593 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
594 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
595 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
596 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
599 // We want to custom lower some of our intrinsics.
600 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
602 // We have target-specific dag combine patterns for the following nodes:
603 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
604 setTargetDAGCombine(ISD::SELECT);
606 computeRegisterProperties();
608 // FIXME: These should be based on subtarget info. Plus, the values should
609 // be smaller when we are in optimizing for size mode.
610 maxStoresPerMemset = 16; // For %llvm.memset -> sequence of stores
611 maxStoresPerMemcpy = 16; // For %llvm.memcpy -> sequence of stores
612 maxStoresPerMemmove = 16; // For %llvm.memmove -> sequence of stores
613 allowUnalignedMemoryAccesses = true; // x86 supports it!
617 //===----------------------------------------------------------------------===//
618 // Return Value Calling Convention Implementation
619 //===----------------------------------------------------------------------===//
621 #include "X86GenCallingConv.inc"
623 /// LowerRET - Lower an ISD::RET node.
624 SDOperand X86TargetLowering::LowerRET(SDOperand Op, SelectionDAG &DAG) {
625 assert((Op.getNumOperands() & 1) == 1 && "ISD::RET should have odd # args");
627 SmallVector<CCValAssign, 16> RVLocs;
628 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
629 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
630 CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs);
631 CCInfo.AnalyzeReturn(Op.Val, RetCC_X86);
634 // If this is the first return lowered for this function, add the regs to the
635 // liveout set for the function.
636 if (DAG.getMachineFunction().liveout_empty()) {
637 for (unsigned i = 0; i != RVLocs.size(); ++i)
638 if (RVLocs[i].isRegLoc())
639 DAG.getMachineFunction().addLiveOut(RVLocs[i].getLocReg());
642 SDOperand Chain = Op.getOperand(0);
645 // Copy the result values into the output registers.
646 if (RVLocs.size() != 1 || !RVLocs[0].isRegLoc() ||
647 RVLocs[0].getLocReg() != X86::ST0) {
648 for (unsigned i = 0; i != RVLocs.size(); ++i) {
649 CCValAssign &VA = RVLocs[i];
650 assert(VA.isRegLoc() && "Can only return in registers!");
651 Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), Op.getOperand(i*2+1),
653 Flag = Chain.getValue(1);
656 // We need to handle a destination of ST0 specially, because it isn't really
658 SDOperand Value = Op.getOperand(1);
660 // If this is an FP return with ScalarSSE, we need to move the value from
661 // an XMM register onto the fp-stack.
662 if ((X86ScalarSSEf32 && RVLocs[0].getValVT()==MVT::f32) ||
663 (X86ScalarSSEf64 && RVLocs[0].getValVT()==MVT::f64)) {
666 // If this is a load into a scalarsse value, don't store the loaded value
667 // back to the stack, only to reload it: just replace the scalar-sse load.
668 if (ISD::isNON_EXTLoad(Value.Val) &&
669 (Chain == Value.getValue(1) || Chain == Value.getOperand(0))) {
670 Chain = Value.getOperand(0);
671 MemLoc = Value.getOperand(1);
673 // Spill the value to memory and reload it into top of stack.
674 unsigned Size = MVT::getSizeInBits(RVLocs[0].getValVT())/8;
675 MachineFunction &MF = DAG.getMachineFunction();
676 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
677 MemLoc = DAG.getFrameIndex(SSFI, getPointerTy());
678 Chain = DAG.getStore(Op.getOperand(0), Value, MemLoc, NULL, 0);
680 SDVTList Tys = DAG.getVTList(RVLocs[0].getValVT(), MVT::Other);
681 SDOperand Ops[] = {Chain, MemLoc, DAG.getValueType(RVLocs[0].getValVT())};
682 Value = DAG.getNode(X86ISD::FLD, Tys, Ops, 3);
683 Chain = Value.getValue(1);
686 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
687 SDOperand Ops[] = { Chain, Value };
688 Chain = DAG.getNode(X86ISD::FP_SET_RESULT, Tys, Ops, 2);
689 Flag = Chain.getValue(1);
692 SDOperand BytesToPop = DAG.getConstant(getBytesToPopOnReturn(), MVT::i16);
694 return DAG.getNode(X86ISD::RET_FLAG, MVT::Other, Chain, BytesToPop, Flag);
696 return DAG.getNode(X86ISD::RET_FLAG, MVT::Other, Chain, BytesToPop);
700 /// LowerCallResult - Lower the result values of an ISD::CALL into the
701 /// appropriate copies out of appropriate physical registers. This assumes that
702 /// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
703 /// being lowered. The returns a SDNode with the same number of values as the
705 SDNode *X86TargetLowering::
706 LowerCallResult(SDOperand Chain, SDOperand InFlag, SDNode *TheCall,
707 unsigned CallingConv, SelectionDAG &DAG) {
709 // Assign locations to each value returned by this call.
710 SmallVector<CCValAssign, 16> RVLocs;
711 bool isVarArg = cast<ConstantSDNode>(TheCall->getOperand(2))->getValue() != 0;
712 CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs);
713 CCInfo.AnalyzeCallResult(TheCall, RetCC_X86);
716 SmallVector<SDOperand, 8> ResultVals;
718 // Copy all of the result registers out of their specified physreg.
719 if (RVLocs.size() != 1 || RVLocs[0].getLocReg() != X86::ST0) {
720 for (unsigned i = 0; i != RVLocs.size(); ++i) {
721 Chain = DAG.getCopyFromReg(Chain, RVLocs[i].getLocReg(),
722 RVLocs[i].getValVT(), InFlag).getValue(1);
723 InFlag = Chain.getValue(2);
724 ResultVals.push_back(Chain.getValue(0));
727 // Copies from the FP stack are special, as ST0 isn't a valid register
728 // before the fp stackifier runs.
730 // Copy ST0 into an RFP register with FP_GET_RESULT.
731 SDVTList Tys = DAG.getVTList(RVLocs[0].getValVT(), MVT::Other, MVT::Flag);
732 SDOperand GROps[] = { Chain, InFlag };
733 SDOperand RetVal = DAG.getNode(X86ISD::FP_GET_RESULT, Tys, GROps, 2);
734 Chain = RetVal.getValue(1);
735 InFlag = RetVal.getValue(2);
737 // If we are using ScalarSSE, store ST(0) to the stack and reload it into
739 if ((X86ScalarSSEf32 && RVLocs[0].getValVT() == MVT::f32) ||
740 (X86ScalarSSEf64 && RVLocs[0].getValVT() == MVT::f64)) {
741 // FIXME: Currently the FST is flagged to the FP_GET_RESULT. This
742 // shouldn't be necessary except that RFP cannot be live across
743 // multiple blocks. When stackifier is fixed, they can be uncoupled.
744 MachineFunction &MF = DAG.getMachineFunction();
745 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
746 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
748 Chain, RetVal, StackSlot, DAG.getValueType(RVLocs[0].getValVT()), InFlag
750 Chain = DAG.getNode(X86ISD::FST, MVT::Other, Ops, 5);
751 RetVal = DAG.getLoad(RVLocs[0].getValVT(), Chain, StackSlot, NULL, 0);
752 Chain = RetVal.getValue(1);
754 ResultVals.push_back(RetVal);
757 // Merge everything together with a MERGE_VALUES node.
758 ResultVals.push_back(Chain);
759 return DAG.getNode(ISD::MERGE_VALUES, TheCall->getVTList(),
760 &ResultVals[0], ResultVals.size()).Val;
764 //===----------------------------------------------------------------------===//
765 // C & StdCall Calling Convention implementation
766 //===----------------------------------------------------------------------===//
767 // StdCall calling convention seems to be standard for many Windows' API
768 // routines and around. It differs from C calling convention just a little:
769 // callee should clean up the stack, not caller. Symbols should be also
770 // decorated in some fancy way :) It doesn't support any vector arguments.
772 /// AddLiveIn - This helper function adds the specified physical register to the
773 /// MachineFunction as a live in value. It also creates a corresponding virtual
775 static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
776 const TargetRegisterClass *RC) {
777 assert(RC->contains(PReg) && "Not the correct regclass!");
778 unsigned VReg = MF.getSSARegMap()->createVirtualRegister(RC);
779 MF.addLiveIn(PReg, VReg);
783 SDOperand X86TargetLowering::LowerMemArgument(SDOperand Op, SelectionDAG &DAG,
784 const CCValAssign &VA,
785 MachineFrameInfo *MFI,
786 SDOperand Root, unsigned i) {
787 // Create the nodes corresponding to a load from this parameter slot.
788 int FI = MFI->CreateFixedObject(MVT::getSizeInBits(VA.getValVT())/8,
789 VA.getLocMemOffset());
790 SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy());
792 unsigned Flags = cast<ConstantSDNode>(Op.getOperand(3 + i))->getValue();
794 if (Flags & ISD::ParamFlags::ByVal)
797 return DAG.getLoad(VA.getValVT(), Root, FIN, NULL, 0);
800 SDOperand X86TargetLowering::LowerCCCArguments(SDOperand Op, SelectionDAG &DAG,
802 unsigned NumArgs = Op.Val->getNumValues() - 1;
803 MachineFunction &MF = DAG.getMachineFunction();
804 MachineFrameInfo *MFI = MF.getFrameInfo();
805 SDOperand Root = Op.getOperand(0);
806 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
808 // Assign locations to all of the incoming arguments.
809 SmallVector<CCValAssign, 16> ArgLocs;
810 CCState CCInfo(MF.getFunction()->getCallingConv(), isVarArg,
811 getTargetMachine(), ArgLocs);
812 CCInfo.AnalyzeFormalArguments(Op.Val, CC_X86_32_C);
814 SmallVector<SDOperand, 8> ArgValues;
815 unsigned LastVal = ~0U;
816 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
817 CCValAssign &VA = ArgLocs[i];
818 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
820 assert(VA.getValNo() != LastVal &&
821 "Don't support value assigned to multiple locs yet");
822 LastVal = VA.getValNo();
825 MVT::ValueType RegVT = VA.getLocVT();
826 TargetRegisterClass *RC;
827 if (RegVT == MVT::i32)
828 RC = X86::GR32RegisterClass;
830 assert(MVT::isVector(RegVT));
831 RC = X86::VR128RegisterClass;
834 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
835 SDOperand ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT);
837 // If this is an 8 or 16-bit value, it is really passed promoted to 32
838 // bits. Insert an assert[sz]ext to capture this, then truncate to the
840 if (VA.getLocInfo() == CCValAssign::SExt)
841 ArgValue = DAG.getNode(ISD::AssertSext, RegVT, ArgValue,
842 DAG.getValueType(VA.getValVT()));
843 else if (VA.getLocInfo() == CCValAssign::ZExt)
844 ArgValue = DAG.getNode(ISD::AssertZext, RegVT, ArgValue,
845 DAG.getValueType(VA.getValVT()));
847 if (VA.getLocInfo() != CCValAssign::Full)
848 ArgValue = DAG.getNode(ISD::TRUNCATE, VA.getValVT(), ArgValue);
850 ArgValues.push_back(ArgValue);
852 assert(VA.isMemLoc());
853 ArgValues.push_back(LowerMemArgument(Op, DAG, VA, MFI, Root, i));
857 unsigned StackSize = CCInfo.getNextStackOffset();
859 ArgValues.push_back(Root);
861 // If the function takes variable number of arguments, make a frame index for
862 // the start of the first vararg value... for expansion of llvm.va_start.
864 VarArgsFrameIndex = MFI->CreateFixedObject(1, StackSize);
866 if (isStdCall && !isVarArg) {
867 BytesToPopOnReturn = StackSize; // Callee pops everything..
868 BytesCallerReserves = 0;
870 BytesToPopOnReturn = 0; // Callee pops nothing.
872 // If this is an sret function, the return should pop the hidden pointer.
874 (cast<ConstantSDNode>(Op.getOperand(3))->getValue() &
875 ISD::ParamFlags::StructReturn))
876 BytesToPopOnReturn = 4;
878 BytesCallerReserves = StackSize;
881 RegSaveFrameIndex = 0xAAAAAAA; // X86-64 only.
883 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
884 FuncInfo->setBytesToPopOnReturn(BytesToPopOnReturn);
886 // Return the new list of results.
887 return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(),
888 &ArgValues[0], ArgValues.size()).getValue(Op.ResNo);
891 SDOperand X86TargetLowering::LowerCCCCallTo(SDOperand Op, SelectionDAG &DAG,
893 SDOperand Chain = Op.getOperand(0);
894 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
895 bool isTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0;
896 SDOperand Callee = Op.getOperand(4);
897 unsigned NumOps = (Op.getNumOperands() - 5) / 2;
899 // Analyze operands of the call, assigning locations to each operand.
900 SmallVector<CCValAssign, 16> ArgLocs;
901 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
902 CCInfo.AnalyzeCallOperands(Op.Val, CC_X86_32_C);
904 // Get a count of how many bytes are to be pushed on the stack.
905 unsigned NumBytes = CCInfo.getNextStackOffset();
907 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes, getPointerTy()));
909 SmallVector<std::pair<unsigned, SDOperand>, 8> RegsToPass;
910 SmallVector<SDOperand, 8> MemOpChains;
914 // Walk the register/memloc assignments, inserting copies/loads.
915 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
916 CCValAssign &VA = ArgLocs[i];
917 SDOperand Arg = Op.getOperand(5+2*VA.getValNo());
919 // Promote the value if needed.
920 switch (VA.getLocInfo()) {
921 default: assert(0 && "Unknown loc info!");
922 case CCValAssign::Full: break;
923 case CCValAssign::SExt:
924 Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg);
926 case CCValAssign::ZExt:
927 Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg);
929 case CCValAssign::AExt:
930 Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg);
935 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
937 assert(VA.isMemLoc());
938 if (StackPtr.Val == 0)
939 StackPtr = DAG.getRegister(getStackPtrReg(), getPointerTy());
941 MemOpChains.push_back(LowerMemOpCallTo(Op, DAG, StackPtr, VA, Chain,
946 // If the first argument is an sret pointer, remember it.
947 bool isSRet = NumOps &&
948 (cast<ConstantSDNode>(Op.getOperand(6))->getValue() &
949 ISD::ParamFlags::StructReturn);
951 if (!MemOpChains.empty())
952 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
953 &MemOpChains[0], MemOpChains.size());
955 // Build a sequence of copy-to-reg nodes chained together with token chain
956 // and flag operands which copy the outgoing args into registers.
958 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
959 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
961 InFlag = Chain.getValue(1);
964 // ELF / PIC requires GOT in the EBX register before function calls via PLT
966 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
967 Subtarget->isPICStyleGOT()) {
968 Chain = DAG.getCopyToReg(Chain, X86::EBX,
969 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
971 InFlag = Chain.getValue(1);
974 // If the callee is a GlobalAddress node (quite common, every direct call is)
975 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
976 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
977 // We should use extra load for direct calls to dllimported functions in
979 if (!Subtarget->GVRequiresExtraLoad(G->getGlobal(),
980 getTargetMachine(), true))
981 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
982 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
983 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
985 // Returns a chain & a flag for retval copy to use.
986 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
987 SmallVector<SDOperand, 8> Ops;
988 Ops.push_back(Chain);
989 Ops.push_back(Callee);
991 // Add argument registers to the end of the list so that they are known live
993 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
994 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
995 RegsToPass[i].second.getValueType()));
997 // Add an implicit use GOT pointer in EBX.
998 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
999 Subtarget->isPICStyleGOT())
1000 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
1003 Ops.push_back(InFlag);
1005 Chain = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL,
1006 NodeTys, &Ops[0], Ops.size());
1007 InFlag = Chain.getValue(1);
1009 // Create the CALLSEQ_END node.
1010 unsigned NumBytesForCalleeToPush = 0;
1012 if (CC == CallingConv::X86_StdCall) {
1014 NumBytesForCalleeToPush = isSRet ? 4 : 0;
1016 NumBytesForCalleeToPush = NumBytes;
1018 // If this is is a call to a struct-return function, the callee
1019 // pops the hidden struct pointer, so we have to push it back.
1020 // This is common for Darwin/X86, Linux & Mingw32 targets.
1021 NumBytesForCalleeToPush = isSRet ? 4 : 0;
1024 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1026 Ops.push_back(Chain);
1027 Ops.push_back(DAG.getConstant(NumBytes, getPointerTy()));
1028 Ops.push_back(DAG.getConstant(NumBytesForCalleeToPush, getPointerTy()));
1029 Ops.push_back(InFlag);
1030 Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0], Ops.size());
1031 InFlag = Chain.getValue(1);
1033 // Handle result values, copying them out of physregs into vregs that we
1035 return SDOperand(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG), Op.ResNo);
1039 //===----------------------------------------------------------------------===//
1040 // FastCall Calling Convention implementation
1041 //===----------------------------------------------------------------------===//
1043 // The X86 'fastcall' calling convention passes up to two integer arguments in
1044 // registers (an appropriate portion of ECX/EDX), passes arguments in C order,
1045 // and requires that the callee pop its arguments off the stack (allowing proper
1046 // tail calls), and has the same return value conventions as C calling convs.
1048 // This calling convention always arranges for the callee pop value to be 8n+4
1049 // bytes, which is needed for tail recursion elimination and stack alignment
1052 X86TargetLowering::LowerFastCCArguments(SDOperand Op, SelectionDAG &DAG) {
1053 MachineFunction &MF = DAG.getMachineFunction();
1054 MachineFrameInfo *MFI = MF.getFrameInfo();
1055 SDOperand Root = Op.getOperand(0);
1056 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
1058 // Assign locations to all of the incoming arguments.
1059 SmallVector<CCValAssign, 16> ArgLocs;
1060 CCState CCInfo(MF.getFunction()->getCallingConv(), isVarArg,
1061 getTargetMachine(), ArgLocs);
1062 CCInfo.AnalyzeFormalArguments(Op.Val, CC_X86_32_FastCall);
1064 SmallVector<SDOperand, 8> ArgValues;
1065 unsigned LastVal = ~0U;
1066 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1067 CCValAssign &VA = ArgLocs[i];
1068 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1070 assert(VA.getValNo() != LastVal &&
1071 "Don't support value assigned to multiple locs yet");
1072 LastVal = VA.getValNo();
1074 if (VA.isRegLoc()) {
1075 MVT::ValueType RegVT = VA.getLocVT();
1076 TargetRegisterClass *RC;
1077 if (RegVT == MVT::i32)
1078 RC = X86::GR32RegisterClass;
1080 assert(MVT::isVector(RegVT));
1081 RC = X86::VR128RegisterClass;
1084 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
1085 SDOperand ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT);
1087 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1088 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1090 if (VA.getLocInfo() == CCValAssign::SExt)
1091 ArgValue = DAG.getNode(ISD::AssertSext, RegVT, ArgValue,
1092 DAG.getValueType(VA.getValVT()));
1093 else if (VA.getLocInfo() == CCValAssign::ZExt)
1094 ArgValue = DAG.getNode(ISD::AssertZext, RegVT, ArgValue,
1095 DAG.getValueType(VA.getValVT()));
1097 if (VA.getLocInfo() != CCValAssign::Full)
1098 ArgValue = DAG.getNode(ISD::TRUNCATE, VA.getValVT(), ArgValue);
1100 ArgValues.push_back(ArgValue);
1102 assert(VA.isMemLoc());
1103 ArgValues.push_back(LowerMemArgument(Op, DAG, VA, MFI, Root, i));
1107 ArgValues.push_back(Root);
1109 unsigned StackSize = CCInfo.getNextStackOffset();
1111 if (!Subtarget->isTargetCygMing() && !Subtarget->isTargetWindows()) {
1112 // Make sure the instruction takes 8n+4 bytes to make sure the start of the
1113 // arguments and the arguments after the retaddr has been pushed are aligned.
1114 if ((StackSize & 7) == 0)
1118 VarArgsFrameIndex = 0xAAAAAAA; // fastcc functions can't have varargs.
1119 RegSaveFrameIndex = 0xAAAAAAA; // X86-64 only.
1120 BytesToPopOnReturn = StackSize; // Callee pops all stack arguments.
1121 BytesCallerReserves = 0;
1123 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1124 FuncInfo->setBytesToPopOnReturn(BytesToPopOnReturn);
1126 // Return the new list of results.
1127 return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(),
1128 &ArgValues[0], ArgValues.size()).getValue(Op.ResNo);
1132 X86TargetLowering::LowerMemOpCallTo(SDOperand Op, SelectionDAG &DAG,
1133 const SDOperand &StackPtr,
1134 const CCValAssign &VA,
1137 SDOperand PtrOff = DAG.getConstant(VA.getLocMemOffset(), getPointerTy());
1138 PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
1139 SDOperand FlagsOp = Op.getOperand(6+2*VA.getValNo());
1140 unsigned Flags = cast<ConstantSDNode>(FlagsOp)->getValue();
1141 if (Flags & ISD::ParamFlags::ByVal) {
1142 unsigned Align = 1 << ((Flags & ISD::ParamFlags::ByValAlign) >>
1143 ISD::ParamFlags::ByValAlignOffs);
1145 unsigned Size = (Flags & ISD::ParamFlags::ByValSize) >>
1146 ISD::ParamFlags::ByValSizeOffs;
1148 SDOperand AlignNode = DAG.getConstant(Align, MVT::i32);
1149 SDOperand SizeNode = DAG.getConstant(Size, MVT::i32);
1151 return DAG.getNode(ISD::MEMCPY, MVT::Other, Chain, PtrOff, Arg, SizeNode,
1154 return DAG.getStore(Chain, Arg, PtrOff, NULL, 0);
1158 SDOperand X86TargetLowering::LowerFastCCCallTo(SDOperand Op, SelectionDAG &DAG,
1160 SDOperand Chain = Op.getOperand(0);
1161 bool isTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0;
1162 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
1163 SDOperand Callee = Op.getOperand(4);
1165 // Analyze operands of the call, assigning locations to each operand.
1166 SmallVector<CCValAssign, 16> ArgLocs;
1167 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
1168 CCInfo.AnalyzeCallOperands(Op.Val, CC_X86_32_FastCall);
1170 // Get a count of how many bytes are to be pushed on the stack.
1171 unsigned NumBytes = CCInfo.getNextStackOffset();
1173 if (!Subtarget->isTargetCygMing() && !Subtarget->isTargetWindows()) {
1174 // Make sure the instruction takes 8n+4 bytes to make sure the start of the
1175 // arguments and the arguments after the retaddr has been pushed are aligned.
1176 if ((NumBytes & 7) == 0)
1180 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes, getPointerTy()));
1182 SmallVector<std::pair<unsigned, SDOperand>, 8> RegsToPass;
1183 SmallVector<SDOperand, 8> MemOpChains;
1187 // Walk the register/memloc assignments, inserting copies/loads.
1188 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1189 CCValAssign &VA = ArgLocs[i];
1190 SDOperand Arg = Op.getOperand(5+2*VA.getValNo());
1192 // Promote the value if needed.
1193 switch (VA.getLocInfo()) {
1194 default: assert(0 && "Unknown loc info!");
1195 case CCValAssign::Full: break;
1196 case CCValAssign::SExt:
1197 Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg);
1199 case CCValAssign::ZExt:
1200 Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg);
1202 case CCValAssign::AExt:
1203 Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg);
1207 if (VA.isRegLoc()) {
1208 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1210 assert(VA.isMemLoc());
1211 if (StackPtr.Val == 0)
1212 StackPtr = DAG.getRegister(getStackPtrReg(), getPointerTy());
1214 MemOpChains.push_back(LowerMemOpCallTo(Op, DAG, StackPtr, VA, Chain,
1219 if (!MemOpChains.empty())
1220 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
1221 &MemOpChains[0], MemOpChains.size());
1223 // Build a sequence of copy-to-reg nodes chained together with token chain
1224 // and flag operands which copy the outgoing args into registers.
1226 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1227 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
1229 InFlag = Chain.getValue(1);
1232 // If the callee is a GlobalAddress node (quite common, every direct call is)
1233 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
1234 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1235 // We should use extra load for direct calls to dllimported functions in
1237 if (!Subtarget->GVRequiresExtraLoad(G->getGlobal(),
1238 getTargetMachine(), true))
1239 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
1240 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
1241 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
1243 // ELF / PIC requires GOT in the EBX register before function calls via PLT
1245 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1246 Subtarget->isPICStyleGOT()) {
1247 Chain = DAG.getCopyToReg(Chain, X86::EBX,
1248 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
1250 InFlag = Chain.getValue(1);
1253 // Returns a chain & a flag for retval copy to use.
1254 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1255 SmallVector<SDOperand, 8> Ops;
1256 Ops.push_back(Chain);
1257 Ops.push_back(Callee);
1259 // Add argument registers to the end of the list so that they are known live
1261 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1262 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1263 RegsToPass[i].second.getValueType()));
1265 // Add an implicit use GOT pointer in EBX.
1266 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1267 Subtarget->isPICStyleGOT())
1268 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
1271 Ops.push_back(InFlag);
1273 // FIXME: Do not generate X86ISD::TAILCALL for now.
1274 Chain = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL,
1275 NodeTys, &Ops[0], Ops.size());
1276 InFlag = Chain.getValue(1);
1278 // Returns a flag for retval copy to use.
1279 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1281 Ops.push_back(Chain);
1282 Ops.push_back(DAG.getConstant(NumBytes, getPointerTy()));
1283 Ops.push_back(DAG.getConstant(NumBytes, getPointerTy()));
1284 Ops.push_back(InFlag);
1285 Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0], Ops.size());
1286 InFlag = Chain.getValue(1);
1288 // Handle result values, copying them out of physregs into vregs that we
1290 return SDOperand(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG), Op.ResNo);
1294 //===----------------------------------------------------------------------===//
1295 // X86-64 C Calling Convention implementation
1296 //===----------------------------------------------------------------------===//
1299 X86TargetLowering::LowerX86_64CCCArguments(SDOperand Op, SelectionDAG &DAG) {
1300 MachineFunction &MF = DAG.getMachineFunction();
1301 MachineFrameInfo *MFI = MF.getFrameInfo();
1302 SDOperand Root = Op.getOperand(0);
1303 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
1305 static const unsigned GPR64ArgRegs[] = {
1306 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1308 static const unsigned XMMArgRegs[] = {
1309 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1310 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1314 // Assign locations to all of the incoming arguments.
1315 SmallVector<CCValAssign, 16> ArgLocs;
1316 CCState CCInfo(MF.getFunction()->getCallingConv(), isVarArg,
1317 getTargetMachine(), ArgLocs);
1318 CCInfo.AnalyzeFormalArguments(Op.Val, CC_X86_64_C);
1320 SmallVector<SDOperand, 8> ArgValues;
1321 unsigned LastVal = ~0U;
1322 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1323 CCValAssign &VA = ArgLocs[i];
1324 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1326 assert(VA.getValNo() != LastVal &&
1327 "Don't support value assigned to multiple locs yet");
1328 LastVal = VA.getValNo();
1330 if (VA.isRegLoc()) {
1331 MVT::ValueType RegVT = VA.getLocVT();
1332 TargetRegisterClass *RC;
1333 if (RegVT == MVT::i32)
1334 RC = X86::GR32RegisterClass;
1335 else if (RegVT == MVT::i64)
1336 RC = X86::GR64RegisterClass;
1337 else if (RegVT == MVT::f32)
1338 RC = X86::FR32RegisterClass;
1339 else if (RegVT == MVT::f64)
1340 RC = X86::FR64RegisterClass;
1342 assert(MVT::isVector(RegVT));
1343 if (MVT::getSizeInBits(RegVT) == 64) {
1344 RC = X86::GR64RegisterClass; // MMX values are passed in GPRs.
1347 RC = X86::VR128RegisterClass;
1350 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
1351 SDOperand ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT);
1353 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1354 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1356 if (VA.getLocInfo() == CCValAssign::SExt)
1357 ArgValue = DAG.getNode(ISD::AssertSext, RegVT, ArgValue,
1358 DAG.getValueType(VA.getValVT()));
1359 else if (VA.getLocInfo() == CCValAssign::ZExt)
1360 ArgValue = DAG.getNode(ISD::AssertZext, RegVT, ArgValue,
1361 DAG.getValueType(VA.getValVT()));
1363 if (VA.getLocInfo() != CCValAssign::Full)
1364 ArgValue = DAG.getNode(ISD::TRUNCATE, VA.getValVT(), ArgValue);
1366 // Handle MMX values passed in GPRs.
1367 if (RegVT != VA.getLocVT() && RC == X86::GR64RegisterClass &&
1368 MVT::getSizeInBits(RegVT) == 64)
1369 ArgValue = DAG.getNode(ISD::BIT_CONVERT, VA.getLocVT(), ArgValue);
1371 ArgValues.push_back(ArgValue);
1373 assert(VA.isMemLoc());
1374 ArgValues.push_back(LowerMemArgument(Op, DAG, VA, MFI, Root, i));
1378 unsigned StackSize = CCInfo.getNextStackOffset();
1380 // If the function takes variable number of arguments, make a frame index for
1381 // the start of the first vararg value... for expansion of llvm.va_start.
1383 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs, 6);
1384 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
1386 // For X86-64, if there are vararg parameters that are passed via
1387 // registers, then we must store them to their spots on the stack so they
1388 // may be loaded by deferencing the result of va_next.
1389 VarArgsGPOffset = NumIntRegs * 8;
1390 VarArgsFPOffset = 6 * 8 + NumXMMRegs * 16;
1391 VarArgsFrameIndex = MFI->CreateFixedObject(1, StackSize);
1392 RegSaveFrameIndex = MFI->CreateStackObject(6 * 8 + 8 * 16, 16);
1394 // Store the integer parameter registers.
1395 SmallVector<SDOperand, 8> MemOps;
1396 SDOperand RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
1397 SDOperand FIN = DAG.getNode(ISD::ADD, getPointerTy(), RSFIN,
1398 DAG.getConstant(VarArgsGPOffset, getPointerTy()));
1399 for (; NumIntRegs != 6; ++NumIntRegs) {
1400 unsigned VReg = AddLiveIn(MF, GPR64ArgRegs[NumIntRegs],
1401 X86::GR64RegisterClass);
1402 SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::i64);
1403 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
1404 MemOps.push_back(Store);
1405 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
1406 DAG.getConstant(8, getPointerTy()));
1409 // Now store the XMM (fp + vector) parameter registers.
1410 FIN = DAG.getNode(ISD::ADD, getPointerTy(), RSFIN,
1411 DAG.getConstant(VarArgsFPOffset, getPointerTy()));
1412 for (; NumXMMRegs != 8; ++NumXMMRegs) {
1413 unsigned VReg = AddLiveIn(MF, XMMArgRegs[NumXMMRegs],
1414 X86::VR128RegisterClass);
1415 SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::v4f32);
1416 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
1417 MemOps.push_back(Store);
1418 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
1419 DAG.getConstant(16, getPointerTy()));
1421 if (!MemOps.empty())
1422 Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
1423 &MemOps[0], MemOps.size());
1426 ArgValues.push_back(Root);
1428 BytesToPopOnReturn = 0; // Callee pops nothing.
1429 BytesCallerReserves = StackSize;
1431 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1432 FuncInfo->setBytesToPopOnReturn(BytesToPopOnReturn);
1434 // Return the new list of results.
1435 return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(),
1436 &ArgValues[0], ArgValues.size()).getValue(Op.ResNo);
1440 X86TargetLowering::LowerX86_64CCCCallTo(SDOperand Op, SelectionDAG &DAG,
1442 SDOperand Chain = Op.getOperand(0);
1443 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
1444 bool isTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0;
1445 SDOperand Callee = Op.getOperand(4);
1447 // Analyze operands of the call, assigning locations to each operand.
1448 SmallVector<CCValAssign, 16> ArgLocs;
1449 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
1450 CCInfo.AnalyzeCallOperands(Op.Val, CC_X86_64_C);
1452 // Get a count of how many bytes are to be pushed on the stack.
1453 unsigned NumBytes = CCInfo.getNextStackOffset();
1454 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes, getPointerTy()));
1456 SmallVector<std::pair<unsigned, SDOperand>, 8> RegsToPass;
1457 SmallVector<SDOperand, 8> MemOpChains;
1461 // Walk the register/memloc assignments, inserting copies/loads.
1462 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1463 CCValAssign &VA = ArgLocs[i];
1464 SDOperand Arg = Op.getOperand(5+2*VA.getValNo());
1466 // Promote the value if needed.
1467 switch (VA.getLocInfo()) {
1468 default: assert(0 && "Unknown loc info!");
1469 case CCValAssign::Full: break;
1470 case CCValAssign::SExt:
1471 Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg);
1473 case CCValAssign::ZExt:
1474 Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg);
1476 case CCValAssign::AExt:
1477 Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg);
1481 if (VA.isRegLoc()) {
1482 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1484 assert(VA.isMemLoc());
1485 if (StackPtr.Val == 0)
1486 StackPtr = DAG.getRegister(getStackPtrReg(), getPointerTy());
1488 MemOpChains.push_back(LowerMemOpCallTo(Op, DAG, StackPtr, VA, Chain,
1493 if (!MemOpChains.empty())
1494 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
1495 &MemOpChains[0], MemOpChains.size());
1497 // Build a sequence of copy-to-reg nodes chained together with token chain
1498 // and flag operands which copy the outgoing args into registers.
1500 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1501 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
1503 InFlag = Chain.getValue(1);
1507 // From AMD64 ABI document:
1508 // For calls that may call functions that use varargs or stdargs
1509 // (prototype-less calls or calls to functions containing ellipsis (...) in
1510 // the declaration) %al is used as hidden argument to specify the number
1511 // of SSE registers used. The contents of %al do not need to match exactly
1512 // the number of registers, but must be an ubound on the number of SSE
1513 // registers used and is in the range 0 - 8 inclusive.
1515 // Count the number of XMM registers allocated.
1516 static const unsigned XMMArgRegs[] = {
1517 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1518 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1520 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
1522 Chain = DAG.getCopyToReg(Chain, X86::AL,
1523 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
1524 InFlag = Chain.getValue(1);
1527 // If the callee is a GlobalAddress node (quite common, every direct call is)
1528 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
1529 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1530 // We should use extra load for direct calls to dllimported functions in
1532 if (getTargetMachine().getCodeModel() != CodeModel::Large
1533 && !Subtarget->GVRequiresExtraLoad(G->getGlobal(),
1534 getTargetMachine(), true))
1535 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
1536 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
1537 if (getTargetMachine().getCodeModel() != CodeModel::Large)
1538 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
1540 // Returns a chain & a flag for retval copy to use.
1541 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1542 SmallVector<SDOperand, 8> Ops;
1543 Ops.push_back(Chain);
1544 Ops.push_back(Callee);
1546 // Add argument registers to the end of the list so that they are known live
1548 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1549 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1550 RegsToPass[i].second.getValueType()));
1553 Ops.push_back(InFlag);
1555 // FIXME: Do not generate X86ISD::TAILCALL for now.
1556 Chain = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL,
1557 NodeTys, &Ops[0], Ops.size());
1558 InFlag = Chain.getValue(1);
1560 // Returns a flag for retval copy to use.
1561 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1563 Ops.push_back(Chain);
1564 Ops.push_back(DAG.getConstant(NumBytes, getPointerTy()));
1565 Ops.push_back(DAG.getConstant(0, getPointerTy()));
1566 Ops.push_back(InFlag);
1567 Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0], Ops.size());
1568 InFlag = Chain.getValue(1);
1570 // Handle result values, copying them out of physregs into vregs that we
1572 return SDOperand(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG), Op.ResNo);
1576 //===----------------------------------------------------------------------===//
1577 // Other Lowering Hooks
1578 //===----------------------------------------------------------------------===//
1581 SDOperand X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) {
1582 MachineFunction &MF = DAG.getMachineFunction();
1583 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1584 int ReturnAddrIndex = FuncInfo->getRAIndex();
1586 if (ReturnAddrIndex == 0) {
1587 // Set up a frame object for the return address.
1588 if (Subtarget->is64Bit())
1589 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(8, -8);
1591 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(4, -4);
1593 FuncInfo->setRAIndex(ReturnAddrIndex);
1596 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
1601 /// translateX86CC - do a one to one translation of a ISD::CondCode to the X86
1602 /// specific condition code. It returns a false if it cannot do a direct
1603 /// translation. X86CC is the translated CondCode. LHS/RHS are modified as
1605 static bool translateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
1606 unsigned &X86CC, SDOperand &LHS, SDOperand &RHS,
1607 SelectionDAG &DAG) {
1608 X86CC = X86::COND_INVALID;
1610 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
1611 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
1612 // X > -1 -> X == 0, jump !sign.
1613 RHS = DAG.getConstant(0, RHS.getValueType());
1614 X86CC = X86::COND_NS;
1616 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
1617 // X < 0 -> X == 0, jump on sign.
1618 X86CC = X86::COND_S;
1620 } else if (SetCCOpcode == ISD::SETLT && RHSC->getValue() == 1) {
1622 RHS = DAG.getConstant(0, RHS.getValueType());
1623 X86CC = X86::COND_LE;
1628 switch (SetCCOpcode) {
1630 case ISD::SETEQ: X86CC = X86::COND_E; break;
1631 case ISD::SETGT: X86CC = X86::COND_G; break;
1632 case ISD::SETGE: X86CC = X86::COND_GE; break;
1633 case ISD::SETLT: X86CC = X86::COND_L; break;
1634 case ISD::SETLE: X86CC = X86::COND_LE; break;
1635 case ISD::SETNE: X86CC = X86::COND_NE; break;
1636 case ISD::SETULT: X86CC = X86::COND_B; break;
1637 case ISD::SETUGT: X86CC = X86::COND_A; break;
1638 case ISD::SETULE: X86CC = X86::COND_BE; break;
1639 case ISD::SETUGE: X86CC = X86::COND_AE; break;
1642 // On a floating point condition, the flags are set as follows:
1644 // 0 | 0 | 0 | X > Y
1645 // 0 | 0 | 1 | X < Y
1646 // 1 | 0 | 0 | X == Y
1647 // 1 | 1 | 1 | unordered
1649 switch (SetCCOpcode) {
1652 case ISD::SETEQ: X86CC = X86::COND_E; break;
1653 case ISD::SETOLT: Flip = true; // Fallthrough
1655 case ISD::SETGT: X86CC = X86::COND_A; break;
1656 case ISD::SETOLE: Flip = true; // Fallthrough
1658 case ISD::SETGE: X86CC = X86::COND_AE; break;
1659 case ISD::SETUGT: Flip = true; // Fallthrough
1661 case ISD::SETLT: X86CC = X86::COND_B; break;
1662 case ISD::SETUGE: Flip = true; // Fallthrough
1664 case ISD::SETLE: X86CC = X86::COND_BE; break;
1666 case ISD::SETNE: X86CC = X86::COND_NE; break;
1667 case ISD::SETUO: X86CC = X86::COND_P; break;
1668 case ISD::SETO: X86CC = X86::COND_NP; break;
1671 std::swap(LHS, RHS);
1674 return X86CC != X86::COND_INVALID;
1677 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
1678 /// code. Current x86 isa includes the following FP cmov instructions:
1679 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
1680 static bool hasFPCMov(unsigned X86CC) {
1696 /// isUndefOrInRange - Op is either an undef node or a ConstantSDNode. Return
1697 /// true if Op is undef or if its value falls within the specified range (L, H].
1698 static bool isUndefOrInRange(SDOperand Op, unsigned Low, unsigned Hi) {
1699 if (Op.getOpcode() == ISD::UNDEF)
1702 unsigned Val = cast<ConstantSDNode>(Op)->getValue();
1703 return (Val >= Low && Val < Hi);
1706 /// isUndefOrEqual - Op is either an undef node or a ConstantSDNode. Return
1707 /// true if Op is undef or if its value equal to the specified value.
1708 static bool isUndefOrEqual(SDOperand Op, unsigned Val) {
1709 if (Op.getOpcode() == ISD::UNDEF)
1711 return cast<ConstantSDNode>(Op)->getValue() == Val;
1714 /// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand
1715 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
1716 bool X86::isPSHUFDMask(SDNode *N) {
1717 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1719 if (N->getNumOperands() != 2 && N->getNumOperands() != 4)
1722 // Check if the value doesn't reference the second vector.
1723 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1724 SDOperand Arg = N->getOperand(i);
1725 if (Arg.getOpcode() == ISD::UNDEF) continue;
1726 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1727 if (cast<ConstantSDNode>(Arg)->getValue() >= e)
1734 /// isPSHUFHWMask - Return true if the specified VECTOR_SHUFFLE operand
1735 /// specifies a shuffle of elements that is suitable for input to PSHUFHW.
1736 bool X86::isPSHUFHWMask(SDNode *N) {
1737 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1739 if (N->getNumOperands() != 8)
1742 // Lower quadword copied in order.
1743 for (unsigned i = 0; i != 4; ++i) {
1744 SDOperand Arg = N->getOperand(i);
1745 if (Arg.getOpcode() == ISD::UNDEF) continue;
1746 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1747 if (cast<ConstantSDNode>(Arg)->getValue() != i)
1751 // Upper quadword shuffled.
1752 for (unsigned i = 4; i != 8; ++i) {
1753 SDOperand Arg = N->getOperand(i);
1754 if (Arg.getOpcode() == ISD::UNDEF) continue;
1755 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1756 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
1757 if (Val < 4 || Val > 7)
1764 /// isPSHUFLWMask - Return true if the specified VECTOR_SHUFFLE operand
1765 /// specifies a shuffle of elements that is suitable for input to PSHUFLW.
1766 bool X86::isPSHUFLWMask(SDNode *N) {
1767 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1769 if (N->getNumOperands() != 8)
1772 // Upper quadword copied in order.
1773 for (unsigned i = 4; i != 8; ++i)
1774 if (!isUndefOrEqual(N->getOperand(i), i))
1777 // Lower quadword shuffled.
1778 for (unsigned i = 0; i != 4; ++i)
1779 if (!isUndefOrInRange(N->getOperand(i), 0, 4))
1785 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
1786 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
1787 static bool isSHUFPMask(const SDOperand *Elems, unsigned NumElems) {
1788 if (NumElems != 2 && NumElems != 4) return false;
1790 unsigned Half = NumElems / 2;
1791 for (unsigned i = 0; i < Half; ++i)
1792 if (!isUndefOrInRange(Elems[i], 0, NumElems))
1794 for (unsigned i = Half; i < NumElems; ++i)
1795 if (!isUndefOrInRange(Elems[i], NumElems, NumElems*2))
1801 bool X86::isSHUFPMask(SDNode *N) {
1802 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1803 return ::isSHUFPMask(N->op_begin(), N->getNumOperands());
1806 /// isCommutedSHUFP - Returns true if the shuffle mask is exactly
1807 /// the reverse of what x86 shuffles want. x86 shuffles requires the lower
1808 /// half elements to come from vector 1 (which would equal the dest.) and
1809 /// the upper half to come from vector 2.
1810 static bool isCommutedSHUFP(const SDOperand *Ops, unsigned NumOps) {
1811 if (NumOps != 2 && NumOps != 4) return false;
1813 unsigned Half = NumOps / 2;
1814 for (unsigned i = 0; i < Half; ++i)
1815 if (!isUndefOrInRange(Ops[i], NumOps, NumOps*2))
1817 for (unsigned i = Half; i < NumOps; ++i)
1818 if (!isUndefOrInRange(Ops[i], 0, NumOps))
1823 static bool isCommutedSHUFP(SDNode *N) {
1824 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1825 return isCommutedSHUFP(N->op_begin(), N->getNumOperands());
1828 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
1829 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
1830 bool X86::isMOVHLPSMask(SDNode *N) {
1831 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1833 if (N->getNumOperands() != 4)
1836 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
1837 return isUndefOrEqual(N->getOperand(0), 6) &&
1838 isUndefOrEqual(N->getOperand(1), 7) &&
1839 isUndefOrEqual(N->getOperand(2), 2) &&
1840 isUndefOrEqual(N->getOperand(3), 3);
1843 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
1844 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
1846 bool X86::isMOVHLPS_v_undef_Mask(SDNode *N) {
1847 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1849 if (N->getNumOperands() != 4)
1852 // Expect bit0 == 2, bit1 == 3, bit2 == 2, bit3 == 3
1853 return isUndefOrEqual(N->getOperand(0), 2) &&
1854 isUndefOrEqual(N->getOperand(1), 3) &&
1855 isUndefOrEqual(N->getOperand(2), 2) &&
1856 isUndefOrEqual(N->getOperand(3), 3);
1859 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
1860 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
1861 bool X86::isMOVLPMask(SDNode *N) {
1862 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1864 unsigned NumElems = N->getNumOperands();
1865 if (NumElems != 2 && NumElems != 4)
1868 for (unsigned i = 0; i < NumElems/2; ++i)
1869 if (!isUndefOrEqual(N->getOperand(i), i + NumElems))
1872 for (unsigned i = NumElems/2; i < NumElems; ++i)
1873 if (!isUndefOrEqual(N->getOperand(i), i))
1879 /// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand
1880 /// specifies a shuffle of elements that is suitable for input to MOVHP{S|D}
1882 bool X86::isMOVHPMask(SDNode *N) {
1883 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1885 unsigned NumElems = N->getNumOperands();
1886 if (NumElems != 2 && NumElems != 4)
1889 for (unsigned i = 0; i < NumElems/2; ++i)
1890 if (!isUndefOrEqual(N->getOperand(i), i))
1893 for (unsigned i = 0; i < NumElems/2; ++i) {
1894 SDOperand Arg = N->getOperand(i + NumElems/2);
1895 if (!isUndefOrEqual(Arg, i + NumElems))
1902 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
1903 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
1904 bool static isUNPCKLMask(const SDOperand *Elts, unsigned NumElts,
1905 bool V2IsSplat = false) {
1906 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
1909 for (unsigned i = 0, j = 0; i != NumElts; i += 2, ++j) {
1910 SDOperand BitI = Elts[i];
1911 SDOperand BitI1 = Elts[i+1];
1912 if (!isUndefOrEqual(BitI, j))
1915 if (isUndefOrEqual(BitI1, NumElts))
1918 if (!isUndefOrEqual(BitI1, j + NumElts))
1926 bool X86::isUNPCKLMask(SDNode *N, bool V2IsSplat) {
1927 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1928 return ::isUNPCKLMask(N->op_begin(), N->getNumOperands(), V2IsSplat);
1931 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
1932 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
1933 bool static isUNPCKHMask(const SDOperand *Elts, unsigned NumElts,
1934 bool V2IsSplat = false) {
1935 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
1938 for (unsigned i = 0, j = 0; i != NumElts; i += 2, ++j) {
1939 SDOperand BitI = Elts[i];
1940 SDOperand BitI1 = Elts[i+1];
1941 if (!isUndefOrEqual(BitI, j + NumElts/2))
1944 if (isUndefOrEqual(BitI1, NumElts))
1947 if (!isUndefOrEqual(BitI1, j + NumElts/2 + NumElts))
1955 bool X86::isUNPCKHMask(SDNode *N, bool V2IsSplat) {
1956 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1957 return ::isUNPCKHMask(N->op_begin(), N->getNumOperands(), V2IsSplat);
1960 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
1961 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
1963 bool X86::isUNPCKL_v_undef_Mask(SDNode *N) {
1964 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1966 unsigned NumElems = N->getNumOperands();
1967 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
1970 for (unsigned i = 0, j = 0; i != NumElems; i += 2, ++j) {
1971 SDOperand BitI = N->getOperand(i);
1972 SDOperand BitI1 = N->getOperand(i+1);
1974 if (!isUndefOrEqual(BitI, j))
1976 if (!isUndefOrEqual(BitI1, j))
1983 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
1984 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
1986 bool X86::isUNPCKH_v_undef_Mask(SDNode *N) {
1987 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1989 unsigned NumElems = N->getNumOperands();
1990 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
1993 for (unsigned i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) {
1994 SDOperand BitI = N->getOperand(i);
1995 SDOperand BitI1 = N->getOperand(i + 1);
1997 if (!isUndefOrEqual(BitI, j))
1999 if (!isUndefOrEqual(BitI1, j))
2006 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
2007 /// specifies a shuffle of elements that is suitable for input to MOVSS,
2008 /// MOVSD, and MOVD, i.e. setting the lowest element.
2009 static bool isMOVLMask(const SDOperand *Elts, unsigned NumElts) {
2010 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
2013 if (!isUndefOrEqual(Elts[0], NumElts))
2016 for (unsigned i = 1; i < NumElts; ++i) {
2017 if (!isUndefOrEqual(Elts[i], i))
2024 bool X86::isMOVLMask(SDNode *N) {
2025 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2026 return ::isMOVLMask(N->op_begin(), N->getNumOperands());
2029 /// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
2030 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
2031 /// element of vector 2 and the other elements to come from vector 1 in order.
2032 static bool isCommutedMOVL(const SDOperand *Ops, unsigned NumOps,
2033 bool V2IsSplat = false,
2034 bool V2IsUndef = false) {
2035 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
2038 if (!isUndefOrEqual(Ops[0], 0))
2041 for (unsigned i = 1; i < NumOps; ++i) {
2042 SDOperand Arg = Ops[i];
2043 if (!(isUndefOrEqual(Arg, i+NumOps) ||
2044 (V2IsUndef && isUndefOrInRange(Arg, NumOps, NumOps*2)) ||
2045 (V2IsSplat && isUndefOrEqual(Arg, NumOps))))
2052 static bool isCommutedMOVL(SDNode *N, bool V2IsSplat = false,
2053 bool V2IsUndef = false) {
2054 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2055 return isCommutedMOVL(N->op_begin(), N->getNumOperands(),
2056 V2IsSplat, V2IsUndef);
2059 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2060 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
2061 bool X86::isMOVSHDUPMask(SDNode *N) {
2062 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2064 if (N->getNumOperands() != 4)
2067 // Expect 1, 1, 3, 3
2068 for (unsigned i = 0; i < 2; ++i) {
2069 SDOperand Arg = N->getOperand(i);
2070 if (Arg.getOpcode() == ISD::UNDEF) continue;
2071 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2072 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2073 if (Val != 1) return false;
2077 for (unsigned i = 2; i < 4; ++i) {
2078 SDOperand Arg = N->getOperand(i);
2079 if (Arg.getOpcode() == ISD::UNDEF) continue;
2080 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2081 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2082 if (Val != 3) return false;
2086 // Don't use movshdup if it can be done with a shufps.
2090 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2091 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
2092 bool X86::isMOVSLDUPMask(SDNode *N) {
2093 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2095 if (N->getNumOperands() != 4)
2098 // Expect 0, 0, 2, 2
2099 for (unsigned i = 0; i < 2; ++i) {
2100 SDOperand Arg = N->getOperand(i);
2101 if (Arg.getOpcode() == ISD::UNDEF) continue;
2102 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2103 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2104 if (Val != 0) return false;
2108 for (unsigned i = 2; i < 4; ++i) {
2109 SDOperand Arg = N->getOperand(i);
2110 if (Arg.getOpcode() == ISD::UNDEF) continue;
2111 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2112 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2113 if (Val != 2) return false;
2117 // Don't use movshdup if it can be done with a shufps.
2121 /// isIdentityMask - Return true if the specified VECTOR_SHUFFLE operand
2122 /// specifies a identity operation on the LHS or RHS.
2123 static bool isIdentityMask(SDNode *N, bool RHS = false) {
2124 unsigned NumElems = N->getNumOperands();
2125 for (unsigned i = 0; i < NumElems; ++i)
2126 if (!isUndefOrEqual(N->getOperand(i), i + (RHS ? NumElems : 0)))
2131 /// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies
2132 /// a splat of a single element.
2133 static bool isSplatMask(SDNode *N) {
2134 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2136 // This is a splat operation if each element of the permute is the same, and
2137 // if the value doesn't reference the second vector.
2138 unsigned NumElems = N->getNumOperands();
2139 SDOperand ElementBase;
2141 for (; i != NumElems; ++i) {
2142 SDOperand Elt = N->getOperand(i);
2143 if (isa<ConstantSDNode>(Elt)) {
2149 if (!ElementBase.Val)
2152 for (; i != NumElems; ++i) {
2153 SDOperand Arg = N->getOperand(i);
2154 if (Arg.getOpcode() == ISD::UNDEF) continue;
2155 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2156 if (Arg != ElementBase) return false;
2159 // Make sure it is a splat of the first vector operand.
2160 return cast<ConstantSDNode>(ElementBase)->getValue() < NumElems;
2163 /// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies
2164 /// a splat of a single element and it's a 2 or 4 element mask.
2165 bool X86::isSplatMask(SDNode *N) {
2166 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2168 // We can only splat 64-bit, and 32-bit quantities with a single instruction.
2169 if (N->getNumOperands() != 4 && N->getNumOperands() != 2)
2171 return ::isSplatMask(N);
2174 /// isSplatLoMask - Return true if the specified VECTOR_SHUFFLE operand
2175 /// specifies a splat of zero element.
2176 bool X86::isSplatLoMask(SDNode *N) {
2177 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2179 for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i)
2180 if (!isUndefOrEqual(N->getOperand(i), 0))
2185 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
2186 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP*
2188 unsigned X86::getShuffleSHUFImmediate(SDNode *N) {
2189 unsigned NumOperands = N->getNumOperands();
2190 unsigned Shift = (NumOperands == 4) ? 2 : 1;
2192 for (unsigned i = 0; i < NumOperands; ++i) {
2194 SDOperand Arg = N->getOperand(NumOperands-i-1);
2195 if (Arg.getOpcode() != ISD::UNDEF)
2196 Val = cast<ConstantSDNode>(Arg)->getValue();
2197 if (Val >= NumOperands) Val -= NumOperands;
2199 if (i != NumOperands - 1)
2206 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
2207 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFHW
2209 unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
2211 // 8 nodes, but we only care about the last 4.
2212 for (unsigned i = 7; i >= 4; --i) {
2214 SDOperand Arg = N->getOperand(i);
2215 if (Arg.getOpcode() != ISD::UNDEF)
2216 Val = cast<ConstantSDNode>(Arg)->getValue();
2225 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
2226 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFLW
2228 unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
2230 // 8 nodes, but we only care about the first 4.
2231 for (int i = 3; i >= 0; --i) {
2233 SDOperand Arg = N->getOperand(i);
2234 if (Arg.getOpcode() != ISD::UNDEF)
2235 Val = cast<ConstantSDNode>(Arg)->getValue();
2244 /// isPSHUFHW_PSHUFLWMask - true if the specified VECTOR_SHUFFLE operand
2245 /// specifies a 8 element shuffle that can be broken into a pair of
2246 /// PSHUFHW and PSHUFLW.
2247 static bool isPSHUFHW_PSHUFLWMask(SDNode *N) {
2248 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2250 if (N->getNumOperands() != 8)
2253 // Lower quadword shuffled.
2254 for (unsigned i = 0; i != 4; ++i) {
2255 SDOperand Arg = N->getOperand(i);
2256 if (Arg.getOpcode() == ISD::UNDEF) continue;
2257 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2258 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2263 // Upper quadword shuffled.
2264 for (unsigned i = 4; i != 8; ++i) {
2265 SDOperand Arg = N->getOperand(i);
2266 if (Arg.getOpcode() == ISD::UNDEF) continue;
2267 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2268 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2269 if (Val < 4 || Val > 7)
2276 /// CommuteVectorShuffle - Swap vector_shuffle operandsas well as
2277 /// values in ther permute mask.
2278 static SDOperand CommuteVectorShuffle(SDOperand Op, SDOperand &V1,
2279 SDOperand &V2, SDOperand &Mask,
2280 SelectionDAG &DAG) {
2281 MVT::ValueType VT = Op.getValueType();
2282 MVT::ValueType MaskVT = Mask.getValueType();
2283 MVT::ValueType EltVT = MVT::getVectorElementType(MaskVT);
2284 unsigned NumElems = Mask.getNumOperands();
2285 SmallVector<SDOperand, 8> MaskVec;
2287 for (unsigned i = 0; i != NumElems; ++i) {
2288 SDOperand Arg = Mask.getOperand(i);
2289 if (Arg.getOpcode() == ISD::UNDEF) {
2290 MaskVec.push_back(DAG.getNode(ISD::UNDEF, EltVT));
2293 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2294 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2296 MaskVec.push_back(DAG.getConstant(Val + NumElems, EltVT));
2298 MaskVec.push_back(DAG.getConstant(Val - NumElems, EltVT));
2302 Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2303 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
2306 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
2307 /// match movhlps. The lower half elements should come from upper half of
2308 /// V1 (and in order), and the upper half elements should come from the upper
2309 /// half of V2 (and in order).
2310 static bool ShouldXformToMOVHLPS(SDNode *Mask) {
2311 unsigned NumElems = Mask->getNumOperands();
2314 for (unsigned i = 0, e = 2; i != e; ++i)
2315 if (!isUndefOrEqual(Mask->getOperand(i), i+2))
2317 for (unsigned i = 2; i != 4; ++i)
2318 if (!isUndefOrEqual(Mask->getOperand(i), i+4))
2323 /// isScalarLoadToVector - Returns true if the node is a scalar load that
2324 /// is promoted to a vector.
2325 static inline bool isScalarLoadToVector(SDNode *N) {
2326 if (N->getOpcode() == ISD::SCALAR_TO_VECTOR) {
2327 N = N->getOperand(0).Val;
2328 return ISD::isNON_EXTLoad(N);
2333 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
2334 /// match movlp{s|d}. The lower half elements should come from lower half of
2335 /// V1 (and in order), and the upper half elements should come from the upper
2336 /// half of V2 (and in order). And since V1 will become the source of the
2337 /// MOVLP, it must be either a vector load or a scalar load to vector.
2338 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2, SDNode *Mask) {
2339 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
2341 // Is V2 is a vector load, don't do this transformation. We will try to use
2342 // load folding shufps op.
2343 if (ISD::isNON_EXTLoad(V2))
2346 unsigned NumElems = Mask->getNumOperands();
2347 if (NumElems != 2 && NumElems != 4)
2349 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
2350 if (!isUndefOrEqual(Mask->getOperand(i), i))
2352 for (unsigned i = NumElems/2; i != NumElems; ++i)
2353 if (!isUndefOrEqual(Mask->getOperand(i), i+NumElems))
2358 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
2360 static bool isSplatVector(SDNode *N) {
2361 if (N->getOpcode() != ISD::BUILD_VECTOR)
2364 SDOperand SplatValue = N->getOperand(0);
2365 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
2366 if (N->getOperand(i) != SplatValue)
2371 /// isUndefShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
2373 static bool isUndefShuffle(SDNode *N) {
2374 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
2377 SDOperand V1 = N->getOperand(0);
2378 SDOperand V2 = N->getOperand(1);
2379 SDOperand Mask = N->getOperand(2);
2380 unsigned NumElems = Mask.getNumOperands();
2381 for (unsigned i = 0; i != NumElems; ++i) {
2382 SDOperand Arg = Mask.getOperand(i);
2383 if (Arg.getOpcode() != ISD::UNDEF) {
2384 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2385 if (Val < NumElems && V1.getOpcode() != ISD::UNDEF)
2387 else if (Val >= NumElems && V2.getOpcode() != ISD::UNDEF)
2394 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
2396 static inline bool isZeroNode(SDOperand Elt) {
2397 return ((isa<ConstantSDNode>(Elt) &&
2398 cast<ConstantSDNode>(Elt)->getValue() == 0) ||
2399 (isa<ConstantFPSDNode>(Elt) &&
2400 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
2403 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
2404 /// to an zero vector.
2405 static bool isZeroShuffle(SDNode *N) {
2406 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
2409 SDOperand V1 = N->getOperand(0);
2410 SDOperand V2 = N->getOperand(1);
2411 SDOperand Mask = N->getOperand(2);
2412 unsigned NumElems = Mask.getNumOperands();
2413 for (unsigned i = 0; i != NumElems; ++i) {
2414 SDOperand Arg = Mask.getOperand(i);
2415 if (Arg.getOpcode() != ISD::UNDEF) {
2416 unsigned Idx = cast<ConstantSDNode>(Arg)->getValue();
2417 if (Idx < NumElems) {
2418 unsigned Opc = V1.Val->getOpcode();
2419 if (Opc == ISD::UNDEF)
2421 if (Opc != ISD::BUILD_VECTOR ||
2422 !isZeroNode(V1.Val->getOperand(Idx)))
2424 } else if (Idx >= NumElems) {
2425 unsigned Opc = V2.Val->getOpcode();
2426 if (Opc == ISD::UNDEF)
2428 if (Opc != ISD::BUILD_VECTOR ||
2429 !isZeroNode(V2.Val->getOperand(Idx - NumElems)))
2437 /// getZeroVector - Returns a vector of specified type with all zero elements.
2439 static SDOperand getZeroVector(MVT::ValueType VT, SelectionDAG &DAG) {
2440 assert(MVT::isVector(VT) && "Expected a vector type");
2441 unsigned NumElems = MVT::getVectorNumElements(VT);
2442 MVT::ValueType EVT = MVT::getVectorElementType(VT);
2443 bool isFP = MVT::isFloatingPoint(EVT);
2444 SDOperand Zero = isFP ? DAG.getConstantFP(0.0, EVT) : DAG.getConstant(0, EVT);
2445 SmallVector<SDOperand, 8> ZeroVec(NumElems, Zero);
2446 return DAG.getNode(ISD::BUILD_VECTOR, VT, &ZeroVec[0], ZeroVec.size());
2449 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
2450 /// that point to V2 points to its first element.
2451 static SDOperand NormalizeMask(SDOperand Mask, SelectionDAG &DAG) {
2452 assert(Mask.getOpcode() == ISD::BUILD_VECTOR);
2454 bool Changed = false;
2455 SmallVector<SDOperand, 8> MaskVec;
2456 unsigned NumElems = Mask.getNumOperands();
2457 for (unsigned i = 0; i != NumElems; ++i) {
2458 SDOperand Arg = Mask.getOperand(i);
2459 if (Arg.getOpcode() != ISD::UNDEF) {
2460 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2461 if (Val > NumElems) {
2462 Arg = DAG.getConstant(NumElems, Arg.getValueType());
2466 MaskVec.push_back(Arg);
2470 Mask = DAG.getNode(ISD::BUILD_VECTOR, Mask.getValueType(),
2471 &MaskVec[0], MaskVec.size());
2475 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
2476 /// operation of specified width.
2477 static SDOperand getMOVLMask(unsigned NumElems, SelectionDAG &DAG) {
2478 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2479 MVT::ValueType BaseVT = MVT::getVectorElementType(MaskVT);
2481 SmallVector<SDOperand, 8> MaskVec;
2482 MaskVec.push_back(DAG.getConstant(NumElems, BaseVT));
2483 for (unsigned i = 1; i != NumElems; ++i)
2484 MaskVec.push_back(DAG.getConstant(i, BaseVT));
2485 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2488 /// getUnpacklMask - Returns a vector_shuffle mask for an unpackl operation
2489 /// of specified width.
2490 static SDOperand getUnpacklMask(unsigned NumElems, SelectionDAG &DAG) {
2491 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2492 MVT::ValueType BaseVT = MVT::getVectorElementType(MaskVT);
2493 SmallVector<SDOperand, 8> MaskVec;
2494 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
2495 MaskVec.push_back(DAG.getConstant(i, BaseVT));
2496 MaskVec.push_back(DAG.getConstant(i + NumElems, BaseVT));
2498 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2501 /// getUnpackhMask - Returns a vector_shuffle mask for an unpackh operation
2502 /// of specified width.
2503 static SDOperand getUnpackhMask(unsigned NumElems, SelectionDAG &DAG) {
2504 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2505 MVT::ValueType BaseVT = MVT::getVectorElementType(MaskVT);
2506 unsigned Half = NumElems/2;
2507 SmallVector<SDOperand, 8> MaskVec;
2508 for (unsigned i = 0; i != Half; ++i) {
2509 MaskVec.push_back(DAG.getConstant(i + Half, BaseVT));
2510 MaskVec.push_back(DAG.getConstant(i + NumElems + Half, BaseVT));
2512 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2515 /// PromoteSplat - Promote a splat of v8i16 or v16i8 to v4i32.
2517 static SDOperand PromoteSplat(SDOperand Op, SelectionDAG &DAG) {
2518 SDOperand V1 = Op.getOperand(0);
2519 SDOperand Mask = Op.getOperand(2);
2520 MVT::ValueType VT = Op.getValueType();
2521 unsigned NumElems = Mask.getNumOperands();
2522 Mask = getUnpacklMask(NumElems, DAG);
2523 while (NumElems != 4) {
2524 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V1, Mask);
2527 V1 = DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, V1);
2529 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(4);
2530 Mask = getZeroVector(MaskVT, DAG);
2531 SDOperand Shuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v4i32, V1,
2532 DAG.getNode(ISD::UNDEF, MVT::v4i32), Mask);
2533 return DAG.getNode(ISD::BIT_CONVERT, VT, Shuffle);
2536 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
2537 /// vector of zero or undef vector.
2538 static SDOperand getShuffleVectorZeroOrUndef(SDOperand V2, MVT::ValueType VT,
2539 unsigned NumElems, unsigned Idx,
2540 bool isZero, SelectionDAG &DAG) {
2541 SDOperand V1 = isZero ? getZeroVector(VT, DAG) : DAG.getNode(ISD::UNDEF, VT);
2542 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2543 MVT::ValueType EVT = MVT::getVectorElementType(MaskVT);
2544 SDOperand Zero = DAG.getConstant(0, EVT);
2545 SmallVector<SDOperand, 8> MaskVec(NumElems, Zero);
2546 MaskVec[Idx] = DAG.getConstant(NumElems, EVT);
2547 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2548 &MaskVec[0], MaskVec.size());
2549 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
2552 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
2554 static SDOperand LowerBuildVectorv16i8(SDOperand Op, unsigned NonZeros,
2555 unsigned NumNonZero, unsigned NumZero,
2556 SelectionDAG &DAG, TargetLowering &TLI) {
2562 for (unsigned i = 0; i < 16; ++i) {
2563 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
2564 if (ThisIsNonZero && First) {
2566 V = getZeroVector(MVT::v8i16, DAG);
2568 V = DAG.getNode(ISD::UNDEF, MVT::v8i16);
2573 SDOperand ThisElt(0, 0), LastElt(0, 0);
2574 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
2575 if (LastIsNonZero) {
2576 LastElt = DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, Op.getOperand(i-1));
2578 if (ThisIsNonZero) {
2579 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, Op.getOperand(i));
2580 ThisElt = DAG.getNode(ISD::SHL, MVT::i16,
2581 ThisElt, DAG.getConstant(8, MVT::i8));
2583 ThisElt = DAG.getNode(ISD::OR, MVT::i16, ThisElt, LastElt);
2588 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, V, ThisElt,
2589 DAG.getConstant(i/2, TLI.getPointerTy()));
2593 return DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, V);
2596 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
2598 static SDOperand LowerBuildVectorv8i16(SDOperand Op, unsigned NonZeros,
2599 unsigned NumNonZero, unsigned NumZero,
2600 SelectionDAG &DAG, TargetLowering &TLI) {
2606 for (unsigned i = 0; i < 8; ++i) {
2607 bool isNonZero = (NonZeros & (1 << i)) != 0;
2611 V = getZeroVector(MVT::v8i16, DAG);
2613 V = DAG.getNode(ISD::UNDEF, MVT::v8i16);
2616 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, V, Op.getOperand(i),
2617 DAG.getConstant(i, TLI.getPointerTy()));
2625 X86TargetLowering::LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) {
2626 // All zero's are handled with pxor.
2627 if (ISD::isBuildVectorAllZeros(Op.Val))
2630 // All one's are handled with pcmpeqd.
2631 if (ISD::isBuildVectorAllOnes(Op.Val))
2634 MVT::ValueType VT = Op.getValueType();
2635 MVT::ValueType EVT = MVT::getVectorElementType(VT);
2636 unsigned EVTBits = MVT::getSizeInBits(EVT);
2638 unsigned NumElems = Op.getNumOperands();
2639 unsigned NumZero = 0;
2640 unsigned NumNonZero = 0;
2641 unsigned NonZeros = 0;
2642 unsigned NumNonZeroImms = 0;
2643 std::set<SDOperand> Values;
2644 for (unsigned i = 0; i < NumElems; ++i) {
2645 SDOperand Elt = Op.getOperand(i);
2646 if (Elt.getOpcode() != ISD::UNDEF) {
2648 if (isZeroNode(Elt))
2651 NonZeros |= (1 << i);
2653 if (Elt.getOpcode() == ISD::Constant ||
2654 Elt.getOpcode() == ISD::ConstantFP)
2660 if (NumNonZero == 0) {
2662 // All undef vector. Return an UNDEF.
2663 return DAG.getNode(ISD::UNDEF, VT);
2665 // A mix of zero and undef. Return a zero vector.
2666 return getZeroVector(VT, DAG);
2669 // Splat is obviously ok. Let legalizer expand it to a shuffle.
2670 if (Values.size() == 1)
2673 // Special case for single non-zero element.
2674 if (NumNonZero == 1) {
2675 unsigned Idx = CountTrailingZeros_32(NonZeros);
2676 SDOperand Item = Op.getOperand(Idx);
2677 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Item);
2679 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
2680 return getShuffleVectorZeroOrUndef(Item, VT, NumElems, Idx,
2683 if (EVTBits == 32) {
2684 // Turn it into a shuffle of zero and zero-extended scalar to vector.
2685 Item = getShuffleVectorZeroOrUndef(Item, VT, NumElems, 0, NumZero > 0,
2687 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2688 MVT::ValueType MaskEVT = MVT::getVectorElementType(MaskVT);
2689 SmallVector<SDOperand, 8> MaskVec;
2690 for (unsigned i = 0; i < NumElems; i++)
2691 MaskVec.push_back(DAG.getConstant((i == Idx) ? 0 : 1, MaskEVT));
2692 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2693 &MaskVec[0], MaskVec.size());
2694 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, Item,
2695 DAG.getNode(ISD::UNDEF, VT), Mask);
2699 // A vector full of immediates; various special cases are already
2700 // handled, so this is best done with a single constant-pool load.
2701 if (NumNonZero == NumNonZeroImms)
2704 // Let legalizer expand 2-wide build_vectors.
2708 // If element VT is < 32 bits, convert it to inserts into a zero vector.
2709 if (EVTBits == 8 && NumElems == 16) {
2710 SDOperand V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
2712 if (V.Val) return V;
2715 if (EVTBits == 16 && NumElems == 8) {
2716 SDOperand V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
2718 if (V.Val) return V;
2721 // If element VT is == 32 bits, turn it into a number of shuffles.
2722 SmallVector<SDOperand, 8> V;
2724 if (NumElems == 4 && NumZero > 0) {
2725 for (unsigned i = 0; i < 4; ++i) {
2726 bool isZero = !(NonZeros & (1 << i));
2728 V[i] = getZeroVector(VT, DAG);
2730 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(i));
2733 for (unsigned i = 0; i < 2; ++i) {
2734 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
2737 V[i] = V[i*2]; // Must be a zero vector.
2740 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2+1], V[i*2],
2741 getMOVLMask(NumElems, DAG));
2744 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2], V[i*2+1],
2745 getMOVLMask(NumElems, DAG));
2748 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2], V[i*2+1],
2749 getUnpacklMask(NumElems, DAG));
2754 // Take advantage of the fact GR32 to VR128 scalar_to_vector (i.e. movd)
2755 // clears the upper bits.
2756 // FIXME: we can do the same for v4f32 case when we know both parts of
2757 // the lower half come from scalar_to_vector (loadf32). We should do
2758 // that in post legalizer dag combiner with target specific hooks.
2759 if (MVT::isInteger(EVT) && (NonZeros & (0x3 << 2)) == 0)
2761 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2762 MVT::ValueType EVT = MVT::getVectorElementType(MaskVT);
2763 SmallVector<SDOperand, 8> MaskVec;
2764 bool Reverse = (NonZeros & 0x3) == 2;
2765 for (unsigned i = 0; i < 2; ++i)
2767 MaskVec.push_back(DAG.getConstant(1-i, EVT));
2769 MaskVec.push_back(DAG.getConstant(i, EVT));
2770 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2;
2771 for (unsigned i = 0; i < 2; ++i)
2773 MaskVec.push_back(DAG.getConstant(1-i+NumElems, EVT));
2775 MaskVec.push_back(DAG.getConstant(i+NumElems, EVT));
2776 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2777 &MaskVec[0], MaskVec.size());
2778 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[0], V[1], ShufMask);
2781 if (Values.size() > 2) {
2782 // Expand into a number of unpckl*.
2784 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
2785 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
2786 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
2787 SDOperand UnpckMask = getUnpacklMask(NumElems, DAG);
2788 for (unsigned i = 0; i < NumElems; ++i)
2789 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(i));
2791 while (NumElems != 0) {
2792 for (unsigned i = 0; i < NumElems; ++i)
2793 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i], V[i + NumElems],
2804 X86TargetLowering::LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) {
2805 SDOperand V1 = Op.getOperand(0);
2806 SDOperand V2 = Op.getOperand(1);
2807 SDOperand PermMask = Op.getOperand(2);
2808 MVT::ValueType VT = Op.getValueType();
2809 unsigned NumElems = PermMask.getNumOperands();
2810 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
2811 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
2812 bool V1IsSplat = false;
2813 bool V2IsSplat = false;
2815 if (isUndefShuffle(Op.Val))
2816 return DAG.getNode(ISD::UNDEF, VT);
2818 if (isZeroShuffle(Op.Val))
2819 return getZeroVector(VT, DAG);
2821 if (isIdentityMask(PermMask.Val))
2823 else if (isIdentityMask(PermMask.Val, true))
2826 if (isSplatMask(PermMask.Val)) {
2827 if (NumElems <= 4) return Op;
2828 // Promote it to a v4i32 splat.
2829 return PromoteSplat(Op, DAG);
2832 if (X86::isMOVLMask(PermMask.Val))
2833 return (V1IsUndef) ? V2 : Op;
2835 if (X86::isMOVSHDUPMask(PermMask.Val) ||
2836 X86::isMOVSLDUPMask(PermMask.Val) ||
2837 X86::isMOVHLPSMask(PermMask.Val) ||
2838 X86::isMOVHPMask(PermMask.Val) ||
2839 X86::isMOVLPMask(PermMask.Val))
2842 if (ShouldXformToMOVHLPS(PermMask.Val) ||
2843 ShouldXformToMOVLP(V1.Val, V2.Val, PermMask.Val))
2844 return CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
2846 bool Commuted = false;
2847 V1IsSplat = isSplatVector(V1.Val);
2848 V2IsSplat = isSplatVector(V2.Val);
2849 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) {
2850 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
2851 std::swap(V1IsSplat, V2IsSplat);
2852 std::swap(V1IsUndef, V2IsUndef);
2856 if (isCommutedMOVL(PermMask.Val, V2IsSplat, V2IsUndef)) {
2857 if (V2IsUndef) return V1;
2858 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
2860 // V2 is a splat, so the mask may be malformed. That is, it may point
2861 // to any V2 element. The instruction selectior won't like this. Get
2862 // a corrected mask and commute to form a proper MOVS{S|D}.
2863 SDOperand NewMask = getMOVLMask(NumElems, DAG);
2864 if (NewMask.Val != PermMask.Val)
2865 Op = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
2870 if (X86::isUNPCKL_v_undef_Mask(PermMask.Val) ||
2871 X86::isUNPCKH_v_undef_Mask(PermMask.Val) ||
2872 X86::isUNPCKLMask(PermMask.Val) ||
2873 X86::isUNPCKHMask(PermMask.Val))
2877 // Normalize mask so all entries that point to V2 points to its first
2878 // element then try to match unpck{h|l} again. If match, return a
2879 // new vector_shuffle with the corrected mask.
2880 SDOperand NewMask = NormalizeMask(PermMask, DAG);
2881 if (NewMask.Val != PermMask.Val) {
2882 if (X86::isUNPCKLMask(PermMask.Val, true)) {
2883 SDOperand NewMask = getUnpacklMask(NumElems, DAG);
2884 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
2885 } else if (X86::isUNPCKHMask(PermMask.Val, true)) {
2886 SDOperand NewMask = getUnpackhMask(NumElems, DAG);
2887 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
2892 // Normalize the node to match x86 shuffle ops if needed
2893 if (V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(PermMask.Val))
2894 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
2897 // Commute is back and try unpck* again.
2898 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
2899 if (X86::isUNPCKL_v_undef_Mask(PermMask.Val) ||
2900 X86::isUNPCKH_v_undef_Mask(PermMask.Val) ||
2901 X86::isUNPCKLMask(PermMask.Val) ||
2902 X86::isUNPCKHMask(PermMask.Val))
2906 // If VT is integer, try PSHUF* first, then SHUFP*.
2907 if (MVT::isInteger(VT)) {
2908 // MMX doesn't have PSHUFD; it does have PSHUFW. While it's theoretically
2909 // possible to shuffle a v2i32 using PSHUFW, that's not yet implemented.
2910 if (((MVT::getSizeInBits(VT) != 64 || NumElems == 4) &&
2911 X86::isPSHUFDMask(PermMask.Val)) ||
2912 X86::isPSHUFHWMask(PermMask.Val) ||
2913 X86::isPSHUFLWMask(PermMask.Val)) {
2914 if (V2.getOpcode() != ISD::UNDEF)
2915 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1,
2916 DAG.getNode(ISD::UNDEF, V1.getValueType()),PermMask);
2920 if (X86::isSHUFPMask(PermMask.Val) &&
2921 MVT::getSizeInBits(VT) != 64) // Don't do this for MMX.
2924 // Handle v8i16 shuffle high / low shuffle node pair.
2925 if (VT == MVT::v8i16 && isPSHUFHW_PSHUFLWMask(PermMask.Val)) {
2926 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2927 MVT::ValueType BaseVT = MVT::getVectorElementType(MaskVT);
2928 SmallVector<SDOperand, 8> MaskVec;
2929 for (unsigned i = 0; i != 4; ++i)
2930 MaskVec.push_back(PermMask.getOperand(i));
2931 for (unsigned i = 4; i != 8; ++i)
2932 MaskVec.push_back(DAG.getConstant(i, BaseVT));
2933 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2934 &MaskVec[0], MaskVec.size());
2935 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
2937 for (unsigned i = 0; i != 4; ++i)
2938 MaskVec.push_back(DAG.getConstant(i, BaseVT));
2939 for (unsigned i = 4; i != 8; ++i)
2940 MaskVec.push_back(PermMask.getOperand(i));
2941 Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0],MaskVec.size());
2942 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
2945 // Floating point cases in the other order.
2946 if (X86::isSHUFPMask(PermMask.Val))
2948 if (X86::isPSHUFDMask(PermMask.Val) ||
2949 X86::isPSHUFHWMask(PermMask.Val) ||
2950 X86::isPSHUFLWMask(PermMask.Val)) {
2951 if (V2.getOpcode() != ISD::UNDEF)
2952 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1,
2953 DAG.getNode(ISD::UNDEF, V1.getValueType()),PermMask);
2958 if (NumElems == 4 &&
2959 // Don't do this for MMX.
2960 MVT::getSizeInBits(VT) != 64) {
2961 MVT::ValueType MaskVT = PermMask.getValueType();
2962 MVT::ValueType MaskEVT = MVT::getVectorElementType(MaskVT);
2963 SmallVector<std::pair<int, int>, 8> Locs;
2964 Locs.reserve(NumElems);
2965 SmallVector<SDOperand, 8> Mask1(NumElems, DAG.getNode(ISD::UNDEF, MaskEVT));
2966 SmallVector<SDOperand, 8> Mask2(NumElems, DAG.getNode(ISD::UNDEF, MaskEVT));
2969 // If no more than two elements come from either vector. This can be
2970 // implemented with two shuffles. First shuffle gather the elements.
2971 // The second shuffle, which takes the first shuffle as both of its
2972 // vector operands, put the elements into the right order.
2973 for (unsigned i = 0; i != NumElems; ++i) {
2974 SDOperand Elt = PermMask.getOperand(i);
2975 if (Elt.getOpcode() == ISD::UNDEF) {
2976 Locs[i] = std::make_pair(-1, -1);
2978 unsigned Val = cast<ConstantSDNode>(Elt)->getValue();
2979 if (Val < NumElems) {
2980 Locs[i] = std::make_pair(0, NumLo);
2984 Locs[i] = std::make_pair(1, NumHi);
2985 if (2+NumHi < NumElems)
2986 Mask1[2+NumHi] = Elt;
2991 if (NumLo <= 2 && NumHi <= 2) {
2992 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
2993 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2994 &Mask1[0], Mask1.size()));
2995 for (unsigned i = 0; i != NumElems; ++i) {
2996 if (Locs[i].first == -1)
2999 unsigned Idx = (i < NumElems/2) ? 0 : NumElems;
3000 Idx += Locs[i].first * (NumElems/2) + Locs[i].second;
3001 Mask2[i] = DAG.getConstant(Idx, MaskEVT);
3005 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V1,
3006 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3007 &Mask2[0], Mask2.size()));
3010 // Break it into (shuffle shuffle_hi, shuffle_lo).
3012 SmallVector<SDOperand,8> LoMask(NumElems, DAG.getNode(ISD::UNDEF, MaskEVT));
3013 SmallVector<SDOperand,8> HiMask(NumElems, DAG.getNode(ISD::UNDEF, MaskEVT));
3014 SmallVector<SDOperand,8> *MaskPtr = &LoMask;
3015 unsigned MaskIdx = 0;
3017 unsigned HiIdx = NumElems/2;
3018 for (unsigned i = 0; i != NumElems; ++i) {
3019 if (i == NumElems/2) {
3025 SDOperand Elt = PermMask.getOperand(i);
3026 if (Elt.getOpcode() == ISD::UNDEF) {
3027 Locs[i] = std::make_pair(-1, -1);
3028 } else if (cast<ConstantSDNode>(Elt)->getValue() < NumElems) {
3029 Locs[i] = std::make_pair(MaskIdx, LoIdx);
3030 (*MaskPtr)[LoIdx] = Elt;
3033 Locs[i] = std::make_pair(MaskIdx, HiIdx);
3034 (*MaskPtr)[HiIdx] = Elt;
3039 SDOperand LoShuffle =
3040 DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
3041 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3042 &LoMask[0], LoMask.size()));
3043 SDOperand HiShuffle =
3044 DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
3045 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3046 &HiMask[0], HiMask.size()));
3047 SmallVector<SDOperand, 8> MaskOps;
3048 for (unsigned i = 0; i != NumElems; ++i) {
3049 if (Locs[i].first == -1) {
3050 MaskOps.push_back(DAG.getNode(ISD::UNDEF, MaskEVT));
3052 unsigned Idx = Locs[i].first * NumElems + Locs[i].second;
3053 MaskOps.push_back(DAG.getConstant(Idx, MaskEVT));
3056 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, LoShuffle, HiShuffle,
3057 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3058 &MaskOps[0], MaskOps.size()));
3065 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) {
3066 if (!isa<ConstantSDNode>(Op.getOperand(1)))
3069 MVT::ValueType VT = Op.getValueType();
3070 // TODO: handle v16i8.
3071 if (MVT::getSizeInBits(VT) == 16) {
3072 // Transform it so it match pextrw which produces a 32-bit result.
3073 MVT::ValueType EVT = (MVT::ValueType)(VT+1);
3074 SDOperand Extract = DAG.getNode(X86ISD::PEXTRW, EVT,
3075 Op.getOperand(0), Op.getOperand(1));
3076 SDOperand Assert = DAG.getNode(ISD::AssertZext, EVT, Extract,
3077 DAG.getValueType(VT));
3078 return DAG.getNode(ISD::TRUNCATE, VT, Assert);
3079 } else if (MVT::getSizeInBits(VT) == 32) {
3080 SDOperand Vec = Op.getOperand(0);
3081 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
3084 // SHUFPS the element to the lowest double word, then movss.
3085 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(4);
3086 SmallVector<SDOperand, 8> IdxVec;
3087 IdxVec.push_back(DAG.getConstant(Idx, MVT::getVectorElementType(MaskVT)));
3088 IdxVec.push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorElementType(MaskVT)));
3089 IdxVec.push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorElementType(MaskVT)));
3090 IdxVec.push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorElementType(MaskVT)));
3091 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3092 &IdxVec[0], IdxVec.size());
3093 Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(),
3094 Vec, DAG.getNode(ISD::UNDEF, Vec.getValueType()), Mask);
3095 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec,
3096 DAG.getConstant(0, getPointerTy()));
3097 } else if (MVT::getSizeInBits(VT) == 64) {
3098 SDOperand Vec = Op.getOperand(0);
3099 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
3103 // UNPCKHPD the element to the lowest double word, then movsd.
3104 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
3105 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
3106 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(4);
3107 SmallVector<SDOperand, 8> IdxVec;
3108 IdxVec.push_back(DAG.getConstant(1, MVT::getVectorElementType(MaskVT)));
3109 IdxVec.push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorElementType(MaskVT)));
3110 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3111 &IdxVec[0], IdxVec.size());
3112 Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(),
3113 Vec, DAG.getNode(ISD::UNDEF, Vec.getValueType()), Mask);
3114 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec,
3115 DAG.getConstant(0, getPointerTy()));
3122 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) {
3123 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
3124 // as its second argument.
3125 MVT::ValueType VT = Op.getValueType();
3126 MVT::ValueType BaseVT = MVT::getVectorElementType(VT);
3127 SDOperand N0 = Op.getOperand(0);
3128 SDOperand N1 = Op.getOperand(1);
3129 SDOperand N2 = Op.getOperand(2);
3130 if (MVT::getSizeInBits(BaseVT) == 16) {
3131 if (N1.getValueType() != MVT::i32)
3132 N1 = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, N1);
3133 if (N2.getValueType() != MVT::i32)
3134 N2 = DAG.getConstant(cast<ConstantSDNode>(N2)->getValue(),getPointerTy());
3135 return DAG.getNode(X86ISD::PINSRW, VT, N0, N1, N2);
3136 } else if (MVT::getSizeInBits(BaseVT) == 32) {
3137 unsigned Idx = cast<ConstantSDNode>(N2)->getValue();
3140 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, N1);
3141 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(4);
3142 MVT::ValueType BaseVT = MVT::getVectorElementType(MaskVT);
3143 SmallVector<SDOperand, 8> MaskVec;
3144 MaskVec.push_back(DAG.getConstant(4, BaseVT));
3145 for (unsigned i = 1; i <= 3; ++i)
3146 MaskVec.push_back(DAG.getConstant(i, BaseVT));
3147 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, N0, N1,
3148 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3149 &MaskVec[0], MaskVec.size()));
3151 // Use two pinsrw instructions to insert a 32 bit value.
3153 if (MVT::isFloatingPoint(N1.getValueType())) {
3154 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v4f32, N1);
3155 N1 = DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, N1);
3156 N1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i32, N1,
3157 DAG.getConstant(0, getPointerTy()));
3159 N0 = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, N0);
3160 N0 = DAG.getNode(X86ISD::PINSRW, MVT::v8i16, N0, N1,
3161 DAG.getConstant(Idx, getPointerTy()));
3162 N1 = DAG.getNode(ISD::SRL, MVT::i32, N1, DAG.getConstant(16, MVT::i8));
3163 N0 = DAG.getNode(X86ISD::PINSRW, MVT::v8i16, N0, N1,
3164 DAG.getConstant(Idx+1, getPointerTy()));
3165 return DAG.getNode(ISD::BIT_CONVERT, VT, N0);
3173 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG) {
3174 SDOperand AnyExt = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, Op.getOperand(0));
3175 return DAG.getNode(X86ISD::S2VEC, Op.getValueType(), AnyExt);
3178 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
3179 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
3180 // one of the above mentioned nodes. It has to be wrapped because otherwise
3181 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
3182 // be used to form addressing mode. These wrapped nodes will be selected
3185 X86TargetLowering::LowerConstantPool(SDOperand Op, SelectionDAG &DAG) {
3186 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
3187 SDOperand Result = DAG.getTargetConstantPool(CP->getConstVal(),
3189 CP->getAlignment());
3190 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
3191 // With PIC, the address is actually $g + Offset.
3192 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
3193 !Subtarget->isPICStyleRIPRel()) {
3194 Result = DAG.getNode(ISD::ADD, getPointerTy(),
3195 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
3203 X86TargetLowering::LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG) {
3204 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
3205 SDOperand Result = DAG.getTargetGlobalAddress(GV, getPointerTy());
3206 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
3207 // With PIC, the address is actually $g + Offset.
3208 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
3209 !Subtarget->isPICStyleRIPRel()) {
3210 Result = DAG.getNode(ISD::ADD, getPointerTy(),
3211 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
3215 // For Darwin & Mingw32, external and weak symbols are indirect, so we want to
3216 // load the value at address GV, not the value of GV itself. This means that
3217 // the GlobalAddress must be in the base or index register of the address, not
3218 // the GV offset field. Platform check is inside GVRequiresExtraLoad() call
3219 // The same applies for external symbols during PIC codegen
3220 if (Subtarget->GVRequiresExtraLoad(GV, getTargetMachine(), false))
3221 Result = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), Result, NULL, 0);
3226 // Lower ISD::GlobalTLSAddress using the "general dynamic" model
3228 LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
3229 const MVT::ValueType PtrVT) {
3231 SDOperand Chain = DAG.getCopyToReg(DAG.getEntryNode(), X86::EBX,
3232 DAG.getNode(X86ISD::GlobalBaseReg,
3234 InFlag = Chain.getValue(1);
3236 // emit leal symbol@TLSGD(,%ebx,1), %eax
3237 SDVTList NodeTys = DAG.getVTList(PtrVT, MVT::Other, MVT::Flag);
3238 SDOperand TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
3239 GA->getValueType(0),
3241 SDOperand Ops[] = { Chain, TGA, InFlag };
3242 SDOperand Result = DAG.getNode(X86ISD::TLSADDR, NodeTys, Ops, 3);
3243 InFlag = Result.getValue(2);
3244 Chain = Result.getValue(1);
3246 // call ___tls_get_addr. This function receives its argument in
3247 // the register EAX.
3248 Chain = DAG.getCopyToReg(Chain, X86::EAX, Result, InFlag);
3249 InFlag = Chain.getValue(1);
3251 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
3252 SDOperand Ops1[] = { Chain,
3253 DAG.getTargetExternalSymbol("___tls_get_addr",
3255 DAG.getRegister(X86::EAX, PtrVT),
3256 DAG.getRegister(X86::EBX, PtrVT),
3258 Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops1, 5);
3259 InFlag = Chain.getValue(1);
3261 return DAG.getCopyFromReg(Chain, X86::EAX, PtrVT, InFlag);
3264 // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
3265 // "local exec" model.
3267 LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
3268 const MVT::ValueType PtrVT) {
3269 // Get the Thread Pointer
3270 SDOperand ThreadPointer = DAG.getNode(X86ISD::THREAD_POINTER, PtrVT);
3271 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
3273 SDOperand TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
3274 GA->getValueType(0),
3276 SDOperand Offset = DAG.getNode(X86ISD::Wrapper, PtrVT, TGA);
3278 if (GA->getGlobal()->isDeclaration()) // initial exec TLS model
3279 Offset = DAG.getLoad(PtrVT, DAG.getEntryNode(), Offset, NULL, 0);
3281 // The address of the thread local variable is the add of the thread
3282 // pointer with the offset of the variable.
3283 return DAG.getNode(ISD::ADD, PtrVT, ThreadPointer, Offset);
3287 X86TargetLowering::LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG) {
3288 // TODO: implement the "local dynamic" model
3289 // TODO: implement the "initial exec"model for pic executables
3290 assert(!Subtarget->is64Bit() && Subtarget->isTargetELF() &&
3291 "TLS not implemented for non-ELF and 64-bit targets");
3292 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
3293 // If the relocation model is PIC, use the "General Dynamic" TLS Model,
3294 // otherwise use the "Local Exec"TLS Model
3295 if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
3296 return LowerToTLSGeneralDynamicModel(GA, DAG, getPointerTy());
3298 return LowerToTLSExecModel(GA, DAG, getPointerTy());
3302 X86TargetLowering::LowerExternalSymbol(SDOperand Op, SelectionDAG &DAG) {
3303 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
3304 SDOperand Result = DAG.getTargetExternalSymbol(Sym, getPointerTy());
3305 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
3306 // With PIC, the address is actually $g + Offset.
3307 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
3308 !Subtarget->isPICStyleRIPRel()) {
3309 Result = DAG.getNode(ISD::ADD, getPointerTy(),
3310 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
3317 SDOperand X86TargetLowering::LowerJumpTable(SDOperand Op, SelectionDAG &DAG) {
3318 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
3319 SDOperand Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy());
3320 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
3321 // With PIC, the address is actually $g + Offset.
3322 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
3323 !Subtarget->isPICStyleRIPRel()) {
3324 Result = DAG.getNode(ISD::ADD, getPointerTy(),
3325 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
3332 SDOperand X86TargetLowering::LowerShift(SDOperand Op, SelectionDAG &DAG) {
3333 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 &&
3334 "Not an i64 shift!");
3335 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
3336 SDOperand ShOpLo = Op.getOperand(0);
3337 SDOperand ShOpHi = Op.getOperand(1);
3338 SDOperand ShAmt = Op.getOperand(2);
3339 SDOperand Tmp1 = isSRA ?
3340 DAG.getNode(ISD::SRA, MVT::i32, ShOpHi, DAG.getConstant(31, MVT::i8)) :
3341 DAG.getConstant(0, MVT::i32);
3343 SDOperand Tmp2, Tmp3;
3344 if (Op.getOpcode() == ISD::SHL_PARTS) {
3345 Tmp2 = DAG.getNode(X86ISD::SHLD, MVT::i32, ShOpHi, ShOpLo, ShAmt);
3346 Tmp3 = DAG.getNode(ISD::SHL, MVT::i32, ShOpLo, ShAmt);
3348 Tmp2 = DAG.getNode(X86ISD::SHRD, MVT::i32, ShOpLo, ShOpHi, ShAmt);
3349 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, MVT::i32, ShOpHi, ShAmt);
3352 const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::Other, MVT::Flag);
3353 SDOperand AndNode = DAG.getNode(ISD::AND, MVT::i8, ShAmt,
3354 DAG.getConstant(32, MVT::i8));
3355 SDOperand COps[]={DAG.getEntryNode(), AndNode, DAG.getConstant(0, MVT::i8)};
3356 SDOperand Cond = NewCCModeling
3357 ? DAG.getNode(X86ISD::CMP_NEW, MVT::i32,
3358 AndNode, DAG.getConstant(0, MVT::i8))
3359 : DAG.getNode(X86ISD::CMP, VTs, 2, COps, 3).getValue(1);
3362 SDOperand CC = DAG.getConstant(X86::COND_NE, MVT::i8);
3363 unsigned Opc = NewCCModeling ? X86ISD::CMOV_NEW : X86ISD::CMOV;
3364 VTs = DAG.getNodeValueTypes(MVT::i32, MVT::Flag);
3365 SmallVector<SDOperand, 4> Ops;
3366 if (Op.getOpcode() == ISD::SHL_PARTS) {
3367 Ops.push_back(Tmp2);
3368 Ops.push_back(Tmp3);
3370 Ops.push_back(Cond);
3372 Hi = DAG.getNode(Opc, MVT::i32, &Ops[0], Ops.size());
3374 Hi = DAG.getNode(Opc, VTs, 2, &Ops[0], Ops.size());
3375 Cond = Hi.getValue(1);
3379 Ops.push_back(Tmp3);
3380 Ops.push_back(Tmp1);
3382 Ops.push_back(Cond);
3384 Lo = DAG.getNode(Opc, MVT::i32, &Ops[0], Ops.size());
3386 Lo = DAG.getNode(Opc, VTs, 2, &Ops[0], Ops.size());
3388 Ops.push_back(Tmp2);
3389 Ops.push_back(Tmp3);
3391 Ops.push_back(Cond);
3393 Lo = DAG.getNode(Opc, MVT::i32, &Ops[0], Ops.size());
3395 Lo = DAG.getNode(Opc, VTs, 2, &Ops[0], Ops.size());
3396 Cond = Lo.getValue(1);
3400 Ops.push_back(Tmp3);
3401 Ops.push_back(Tmp1);
3403 Ops.push_back(Cond);
3405 Hi = DAG.getNode(Opc, MVT::i32, &Ops[0], Ops.size());
3407 Hi = DAG.getNode(Opc, VTs, 2, &Ops[0], Ops.size());
3410 VTs = DAG.getNodeValueTypes(MVT::i32, MVT::i32);
3414 return DAG.getNode(ISD::MERGE_VALUES, VTs, 2, &Ops[0], Ops.size());
3417 SDOperand X86TargetLowering::LowerIntegerDivOrRem(SDOperand Op, SelectionDAG &DAG) {
3418 unsigned Opcode = Op.getOpcode();
3419 MVT::ValueType NVT = Op.getValueType();
3420 bool isSigned = Opcode == ISD::SDIV || Opcode == ISD::SREM;
3421 bool isDiv = Opcode == ISD::SDIV || Opcode == ISD::UDIV;
3422 unsigned Opc = isSigned ? X86ISD::IDIV : X86ISD::DIV;
3424 SDOperand Ops[] = { Op.getOperand(0), Op.getOperand(1) };
3425 SDOperand DR = DAG.getNode(Opc, DAG.getVTList(NVT, NVT), Ops, 2);
3430 return SDOperand(DR.Val, 1);
3433 SDOperand X86TargetLowering::LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
3434 assert(Op.getOperand(0).getValueType() <= MVT::i64 &&
3435 Op.getOperand(0).getValueType() >= MVT::i16 &&
3436 "Unknown SINT_TO_FP to lower!");
3439 MVT::ValueType SrcVT = Op.getOperand(0).getValueType();
3440 unsigned Size = MVT::getSizeInBits(SrcVT)/8;
3441 MachineFunction &MF = DAG.getMachineFunction();
3442 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
3443 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
3444 SDOperand Chain = DAG.getStore(DAG.getEntryNode(), Op.getOperand(0),
3445 StackSlot, NULL, 0);
3447 // These are really Legal; caller falls through into that case.
3448 if (SrcVT==MVT::i32 && Op.getValueType() == MVT::f32 && X86ScalarSSEf32)
3450 if (SrcVT==MVT::i32 && Op.getValueType() == MVT::f64 && X86ScalarSSEf64)
3452 if (SrcVT==MVT::i64 && Op.getValueType() != MVT::f80 &&
3453 Subtarget->is64Bit())
3458 bool useSSE = (X86ScalarSSEf32 && Op.getValueType() == MVT::f32) ||
3459 (X86ScalarSSEf64 && Op.getValueType() == MVT::f64);
3461 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag);
3463 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
3464 SmallVector<SDOperand, 8> Ops;
3465 Ops.push_back(Chain);
3466 Ops.push_back(StackSlot);
3467 Ops.push_back(DAG.getValueType(SrcVT));
3468 Result = DAG.getNode(useSSE ? X86ISD::FILD_FLAG :X86ISD::FILD,
3469 Tys, &Ops[0], Ops.size());
3472 Chain = Result.getValue(1);
3473 SDOperand InFlag = Result.getValue(2);
3475 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
3476 // shouldn't be necessary except that RFP cannot be live across
3477 // multiple blocks. When stackifier is fixed, they can be uncoupled.
3478 MachineFunction &MF = DAG.getMachineFunction();
3479 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
3480 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
3481 Tys = DAG.getVTList(MVT::Other);
3482 SmallVector<SDOperand, 8> Ops;
3483 Ops.push_back(Chain);
3484 Ops.push_back(Result);
3485 Ops.push_back(StackSlot);
3486 Ops.push_back(DAG.getValueType(Op.getValueType()));
3487 Ops.push_back(InFlag);
3488 Chain = DAG.getNode(X86ISD::FST, Tys, &Ops[0], Ops.size());
3489 Result = DAG.getLoad(Op.getValueType(), Chain, StackSlot, NULL, 0);
3495 SDOperand X86TargetLowering::LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) {
3496 assert(Op.getValueType() <= MVT::i64 && Op.getValueType() >= MVT::i16 &&
3497 "Unknown FP_TO_SINT to lower!");
3498 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
3501 MachineFunction &MF = DAG.getMachineFunction();
3502 unsigned MemSize = MVT::getSizeInBits(Op.getValueType())/8;
3503 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
3504 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
3506 // These are really Legal.
3507 if (Op.getValueType() == MVT::i32 &&
3508 X86ScalarSSEf32 && Op.getOperand(0).getValueType() == MVT::f32)
3510 if (Op.getValueType() == MVT::i32 &&
3511 X86ScalarSSEf64 && Op.getOperand(0).getValueType() == MVT::f64)
3513 if (Subtarget->is64Bit() &&
3514 Op.getValueType() == MVT::i64 &&
3515 Op.getOperand(0).getValueType() != MVT::f80)
3519 switch (Op.getValueType()) {
3520 default: assert(0 && "Invalid FP_TO_SINT to lower!");
3521 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
3522 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
3523 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
3526 SDOperand Chain = DAG.getEntryNode();
3527 SDOperand Value = Op.getOperand(0);
3528 if ((X86ScalarSSEf32 && Op.getOperand(0).getValueType() == MVT::f32) ||
3529 (X86ScalarSSEf64 && Op.getOperand(0).getValueType() == MVT::f64)) {
3530 assert(Op.getValueType() == MVT::i64 && "Invalid FP_TO_SINT to lower!");
3531 Chain = DAG.getStore(Chain, Value, StackSlot, NULL, 0);
3532 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
3534 Chain, StackSlot, DAG.getValueType(Op.getOperand(0).getValueType())
3536 Value = DAG.getNode(X86ISD::FLD, Tys, Ops, 3);
3537 Chain = Value.getValue(1);
3538 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
3539 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
3542 // Build the FP_TO_INT*_IN_MEM
3543 SDOperand Ops[] = { Chain, Value, StackSlot };
3544 SDOperand FIST = DAG.getNode(Opc, MVT::Other, Ops, 3);
3547 return DAG.getLoad(Op.getValueType(), FIST, StackSlot, NULL, 0);
3550 SDOperand X86TargetLowering::LowerFABS(SDOperand Op, SelectionDAG &DAG) {
3551 MVT::ValueType VT = Op.getValueType();
3552 MVT::ValueType EltVT = VT;
3553 if (MVT::isVector(VT))
3554 EltVT = MVT::getVectorElementType(VT);
3555 const Type *OpNTy = MVT::getTypeForValueType(EltVT);
3556 std::vector<Constant*> CV;
3557 if (EltVT == MVT::f64) {
3558 Constant *C = ConstantFP::get(OpNTy, APFloat(APInt(64, ~(1ULL << 63))));
3562 Constant *C = ConstantFP::get(OpNTy, APFloat(APInt(32, ~(1U << 31))));
3568 Constant *C = ConstantVector::get(CV);
3569 SDOperand CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
3570 SDOperand Mask = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0,
3572 return DAG.getNode(X86ISD::FAND, VT, Op.getOperand(0), Mask);
3575 SDOperand X86TargetLowering::LowerFNEG(SDOperand Op, SelectionDAG &DAG) {
3576 MVT::ValueType VT = Op.getValueType();
3577 MVT::ValueType EltVT = VT;
3578 unsigned EltNum = 1;
3579 if (MVT::isVector(VT)) {
3580 EltVT = MVT::getVectorElementType(VT);
3581 EltNum = MVT::getVectorNumElements(VT);
3583 const Type *OpNTy = MVT::getTypeForValueType(EltVT);
3584 std::vector<Constant*> CV;
3585 if (EltVT == MVT::f64) {
3586 Constant *C = ConstantFP::get(OpNTy, APFloat(APInt(64, 1ULL << 63)));
3590 Constant *C = ConstantFP::get(OpNTy, APFloat(APInt(32, 1U << 31)));
3596 Constant *C = ConstantVector::get(CV);
3597 SDOperand CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
3598 SDOperand Mask = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0,
3600 if (MVT::isVector(VT)) {
3601 return DAG.getNode(ISD::BIT_CONVERT, VT,
3602 DAG.getNode(ISD::XOR, MVT::v2i64,
3603 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, Op.getOperand(0)),
3604 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, Mask)));
3606 return DAG.getNode(X86ISD::FXOR, VT, Op.getOperand(0), Mask);
3610 SDOperand X86TargetLowering::LowerFCOPYSIGN(SDOperand Op, SelectionDAG &DAG) {
3611 SDOperand Op0 = Op.getOperand(0);
3612 SDOperand Op1 = Op.getOperand(1);
3613 MVT::ValueType VT = Op.getValueType();
3614 MVT::ValueType SrcVT = Op1.getValueType();
3615 const Type *SrcTy = MVT::getTypeForValueType(SrcVT);
3617 // If second operand is smaller, extend it first.
3618 if (MVT::getSizeInBits(SrcVT) < MVT::getSizeInBits(VT)) {
3619 Op1 = DAG.getNode(ISD::FP_EXTEND, VT, Op1);
3621 SrcTy = MVT::getTypeForValueType(SrcVT);
3624 // First get the sign bit of second operand.
3625 std::vector<Constant*> CV;
3626 if (SrcVT == MVT::f64) {
3627 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(64, 1ULL << 63))));
3628 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(64, 0))));
3630 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(32, 1U << 31))));
3631 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(32, 0))));
3632 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(32, 0))));
3633 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(32, 0))));
3635 Constant *C = ConstantVector::get(CV);
3636 SDOperand CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
3637 SDOperand Mask1 = DAG.getLoad(SrcVT, DAG.getEntryNode(), CPIdx, NULL, 0,
3639 SDOperand SignBit = DAG.getNode(X86ISD::FAND, SrcVT, Op1, Mask1);
3641 // Shift sign bit right or left if the two operands have different types.
3642 if (MVT::getSizeInBits(SrcVT) > MVT::getSizeInBits(VT)) {
3643 // Op0 is MVT::f32, Op1 is MVT::f64.
3644 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v2f64, SignBit);
3645 SignBit = DAG.getNode(X86ISD::FSRL, MVT::v2f64, SignBit,
3646 DAG.getConstant(32, MVT::i32));
3647 SignBit = DAG.getNode(ISD::BIT_CONVERT, MVT::v4f32, SignBit);
3648 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::f32, SignBit,
3649 DAG.getConstant(0, getPointerTy()));
3652 // Clear first operand sign bit.
3654 if (VT == MVT::f64) {
3655 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(64, ~(1ULL << 63)))));
3656 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(64, 0))));
3658 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(32, ~(1U << 31)))));
3659 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(32, 0))));
3660 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(32, 0))));
3661 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(32, 0))));
3663 C = ConstantVector::get(CV);
3664 CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
3665 SDOperand Mask2 = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0,
3667 SDOperand Val = DAG.getNode(X86ISD::FAND, VT, Op0, Mask2);
3669 // Or the value with the sign bit.
3670 return DAG.getNode(X86ISD::FOR, VT, Val, SignBit);
3673 SDOperand X86TargetLowering::LowerSETCC(SDOperand Op, SelectionDAG &DAG,
3675 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
3677 SDOperand Op0 = Op.getOperand(0);
3678 SDOperand Op1 = Op.getOperand(1);
3679 SDOperand CC = Op.getOperand(2);
3680 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
3681 const MVT::ValueType *VTs1 = DAG.getNodeValueTypes(MVT::Other, MVT::Flag);
3682 const MVT::ValueType *VTs2 = DAG.getNodeValueTypes(MVT::i8, MVT::Flag);
3683 bool isFP = MVT::isFloatingPoint(Op.getOperand(1).getValueType());
3686 if (translateX86CC(cast<CondCodeSDNode>(CC)->get(), isFP, X86CC,
3688 SDOperand Ops1[] = { Chain, Op0, Op1 };
3689 Cond = DAG.getNode(X86ISD::CMP, VTs1, 2, Ops1, 3).getValue(1);
3690 SDOperand Ops2[] = { DAG.getConstant(X86CC, MVT::i8), Cond };
3691 return DAG.getNode(X86ISD::SETCC, VTs2, 2, Ops2, 2);
3694 assert(isFP && "Illegal integer SetCC!");
3696 SDOperand COps[] = { Chain, Op0, Op1 };
3697 Cond = DAG.getNode(X86ISD::CMP, VTs1, 2, COps, 3).getValue(1);
3699 switch (SetCCOpcode) {
3700 default: assert(false && "Illegal floating point SetCC!");
3701 case ISD::SETOEQ: { // !PF & ZF
3702 SDOperand Ops1[] = { DAG.getConstant(X86::COND_NP, MVT::i8), Cond };
3703 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, VTs2, 2, Ops1, 2);
3704 SDOperand Ops2[] = { DAG.getConstant(X86::COND_E, MVT::i8),
3706 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, VTs2, 2, Ops2, 2);
3707 return DAG.getNode(ISD::AND, MVT::i8, Tmp1, Tmp2);
3709 case ISD::SETUNE: { // PF | !ZF
3710 SDOperand Ops1[] = { DAG.getConstant(X86::COND_P, MVT::i8), Cond };
3711 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, VTs2, 2, Ops1, 2);
3712 SDOperand Ops2[] = { DAG.getConstant(X86::COND_NE, MVT::i8),
3714 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, VTs2, 2, Ops2, 2);
3715 return DAG.getNode(ISD::OR, MVT::i8, Tmp1, Tmp2);
3720 SDOperand X86TargetLowering::LowerSETCC_New(SDOperand Op, SelectionDAG &DAG) {
3721 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
3722 SDOperand Op0 = Op.getOperand(0);
3723 SDOperand Op1 = Op.getOperand(1);
3724 SDOperand CC = Op.getOperand(2);
3725 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
3726 bool isFP = MVT::isFloatingPoint(Op.getOperand(1).getValueType());
3729 SDOperand Cond = DAG.getNode(X86ISD::CMP_NEW, MVT::i32, Op0, Op1);
3730 if (translateX86CC(cast<CondCodeSDNode>(CC)->get(), isFP, X86CC,
3732 return DAG.getNode(X86ISD::SETCC_NEW, MVT::i8,
3733 DAG.getConstant(X86CC, MVT::i8), Cond);
3735 assert(isFP && "Illegal integer SetCC!");
3737 switch (SetCCOpcode) {
3738 default: assert(false && "Illegal floating point SetCC!");
3739 case ISD::SETOEQ: { // !PF & ZF
3740 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC_NEW, MVT::i8,
3741 DAG.getConstant(X86::COND_NP, MVT::i8), Cond);
3742 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC_NEW, MVT::i8,
3743 DAG.getConstant(X86::COND_E, MVT::i8), Cond);
3744 return DAG.getNode(ISD::AND, MVT::i8, Tmp1, Tmp2);
3746 case ISD::SETUNE: { // PF | !ZF
3747 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC_NEW, MVT::i8,
3748 DAG.getConstant(X86::COND_P, MVT::i8), Cond);
3749 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC_NEW, MVT::i8,
3750 DAG.getConstant(X86::COND_NE, MVT::i8), Cond);
3751 return DAG.getNode(ISD::OR, MVT::i8, Tmp1, Tmp2);
3757 SDOperand X86TargetLowering::LowerSELECT(SDOperand Op, SelectionDAG &DAG) {
3758 bool addTest = true;
3759 SDOperand Chain = DAG.getEntryNode();
3760 SDOperand Cond = Op.getOperand(0);
3762 const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::Other, MVT::Flag);
3764 if (Cond.getOpcode() == ISD::SETCC)
3765 Cond = LowerSETCC(Cond, DAG, Chain);
3767 if (Cond.getOpcode() == X86ISD::SETCC) {
3768 CC = Cond.getOperand(0);
3770 // If condition flag is set by a X86ISD::CMP, then make a copy of it
3771 // (since flag operand cannot be shared). Use it as the condition setting
3772 // operand in place of the X86ISD::SETCC.
3773 // If the X86ISD::SETCC has more than one use, then perhaps it's better
3774 // to use a test instead of duplicating the X86ISD::CMP (for register
3775 // pressure reason)?
3776 SDOperand Cmp = Cond.getOperand(1);
3777 unsigned Opc = Cmp.getOpcode();
3778 bool IllegalFPCMov =
3779 ! ((X86ScalarSSEf32 && Op.getValueType()==MVT::f32) ||
3780 (X86ScalarSSEf64 && Op.getValueType()==MVT::f64)) &&
3781 !hasFPCMov(cast<ConstantSDNode>(CC)->getSignExtended());
3782 if ((Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI) &&
3784 SDOperand Ops[] = { Chain, Cmp.getOperand(1), Cmp.getOperand(2) };
3785 Cond = DAG.getNode(Opc, VTs, 2, Ops, 3);
3791 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
3792 SDOperand Ops[] = { Chain, Cond, DAG.getConstant(0, MVT::i8) };
3793 Cond = DAG.getNode(X86ISD::CMP, VTs, 2, Ops, 3);
3796 VTs = DAG.getNodeValueTypes(Op.getValueType(), MVT::Flag);
3797 SmallVector<SDOperand, 4> Ops;
3798 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
3799 // condition is true.
3800 Ops.push_back(Op.getOperand(2));
3801 Ops.push_back(Op.getOperand(1));
3803 Ops.push_back(Cond.getValue(1));
3804 return DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size());
3807 SDOperand X86TargetLowering::LowerSELECT_New(SDOperand Op, SelectionDAG &DAG) {
3808 bool addTest = true;
3809 SDOperand Cond = Op.getOperand(0);
3812 if (Cond.getOpcode() == ISD::SETCC)
3813 Cond = LowerSETCC_New(Cond, DAG);
3815 if (Cond.getOpcode() == X86ISD::SETCC_NEW) {
3816 CC = Cond.getOperand(0);
3818 // If condition flag is set by a X86ISD::CMP, then make a copy of it
3819 // (since flag operand cannot be shared). Use it as the condition setting
3820 // operand in place of the X86ISD::SETCC.
3821 // If the X86ISD::SETCC has more than one use, then perhaps it's better
3822 // to use a test instead of duplicating the X86ISD::CMP (for register
3823 // pressure reason)?
3824 SDOperand Cmp = Cond.getOperand(1);
3825 unsigned Opc = Cmp.getOpcode();
3826 bool IllegalFPCMov =
3827 ! ((X86ScalarSSEf32 && Op.getValueType()==MVT::f32) ||
3828 (X86ScalarSSEf64 && Op.getValueType()==MVT::f64)) &&
3829 !hasFPCMov(cast<ConstantSDNode>(CC)->getSignExtended());
3830 if ((Opc == X86ISD::CMP_NEW ||
3831 Opc == X86ISD::COMI_NEW ||
3832 Opc == X86ISD::UCOMI_NEW) &&
3834 Cond = DAG.getNode(Opc, MVT::i32, Cmp.getOperand(0), Cmp.getOperand(1));
3840 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
3841 Cond = DAG.getNode(X86ISD::CMP_NEW, MVT::i32, Cond,
3842 DAG.getConstant(0, MVT::i8));
3845 const MVT::ValueType *VTs = DAG.getNodeValueTypes(Op.getValueType(),
3847 SmallVector<SDOperand, 4> Ops;
3848 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
3849 // condition is true.
3850 Ops.push_back(Op.getOperand(2));
3851 Ops.push_back(Op.getOperand(1));
3853 Ops.push_back(Cond);
3854 return DAG.getNode(X86ISD::CMOV_NEW, VTs, 2, &Ops[0], Ops.size());
3857 SDOperand X86TargetLowering::LowerBRCOND(SDOperand Op, SelectionDAG &DAG) {
3858 bool addTest = true;
3859 SDOperand Chain = Op.getOperand(0);
3860 SDOperand Cond = Op.getOperand(1);
3861 SDOperand Dest = Op.getOperand(2);
3863 const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::Other, MVT::Flag);
3865 if (Cond.getOpcode() == ISD::SETCC)
3866 Cond = LowerSETCC(Cond, DAG, Chain);
3868 if (Cond.getOpcode() == X86ISD::SETCC) {
3869 CC = Cond.getOperand(0);
3871 // If condition flag is set by a X86ISD::CMP, then make a copy of it
3872 // (since flag operand cannot be shared). Use it as the condition setting
3873 // operand in place of the X86ISD::SETCC.
3874 // If the X86ISD::SETCC has more than one use, then perhaps it's better
3875 // to use a test instead of duplicating the X86ISD::CMP (for register
3876 // pressure reason)?
3877 SDOperand Cmp = Cond.getOperand(1);
3878 unsigned Opc = Cmp.getOpcode();
3879 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI) {
3880 SDOperand Ops[] = { Chain, Cmp.getOperand(1), Cmp.getOperand(2) };
3881 Cond = DAG.getNode(Opc, VTs, 2, Ops, 3);
3887 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
3888 SDOperand Ops[] = { Chain, Cond, DAG.getConstant(0, MVT::i8) };
3889 Cond = DAG.getNode(X86ISD::CMP, VTs, 2, Ops, 3);
3891 return DAG.getNode(X86ISD::BRCOND, Op.getValueType(),
3892 Cond, Op.getOperand(2), CC, Cond.getValue(1));
3895 SDOperand X86TargetLowering::LowerBRCOND_New(SDOperand Op, SelectionDAG &DAG) {
3896 bool addTest = true;
3897 SDOperand Chain = Op.getOperand(0);
3898 SDOperand Cond = Op.getOperand(1);
3899 SDOperand Dest = Op.getOperand(2);
3902 if (Cond.getOpcode() == ISD::SETCC)
3903 Cond = LowerSETCC_New(Cond, DAG);
3905 if (Cond.getOpcode() == X86ISD::SETCC_NEW) {
3906 CC = Cond.getOperand(0);
3908 // If condition flag is set by a X86ISD::CMP, then make a copy of it
3909 // (since flag operand cannot be shared). Use it as the condition setting
3910 // operand in place of the X86ISD::SETCC.
3911 // If the X86ISD::SETCC has more than one use, then perhaps it's better
3912 // to use a test instead of duplicating the X86ISD::CMP (for register
3913 // pressure reason)?
3914 SDOperand Cmp = Cond.getOperand(1);
3915 unsigned Opc = Cmp.getOpcode();
3916 if (Opc == X86ISD::CMP_NEW ||
3917 Opc == X86ISD::COMI_NEW ||
3918 Opc == X86ISD::UCOMI_NEW) {
3919 Cond = DAG.getNode(Opc, MVT::i32, Cmp.getOperand(0), Cmp.getOperand(1));
3925 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
3926 Cond= DAG.getNode(X86ISD::CMP_NEW, MVT::i32, Cond, DAG.getConstant(0, MVT::i8));
3928 return DAG.getNode(X86ISD::BRCOND_NEW, Op.getValueType(),
3929 Chain, Op.getOperand(2), CC, Cond);
3932 SDOperand X86TargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) {
3933 unsigned CallingConv= cast<ConstantSDNode>(Op.getOperand(1))->getValue();
3935 if (Subtarget->is64Bit())
3936 return LowerX86_64CCCCallTo(Op, DAG, CallingConv);
3938 switch (CallingConv) {
3940 assert(0 && "Unsupported calling convention");
3941 case CallingConv::Fast:
3942 // TODO: Implement fastcc
3944 case CallingConv::C:
3945 case CallingConv::X86_StdCall:
3946 return LowerCCCCallTo(Op, DAG, CallingConv);
3947 case CallingConv::X86_FastCall:
3948 return LowerFastCCCallTo(Op, DAG, CallingConv);
3953 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
3954 // Calls to _alloca is needed to probe the stack when allocating more than 4k
3955 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
3956 // that the guard pages used by the OS virtual memory manager are allocated in
3957 // correct sequence.
3959 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDOperand Op,
3960 SelectionDAG &DAG) {
3961 assert(Subtarget->isTargetCygMing() &&
3962 "This should be used only on Cygwin/Mingw targets");
3965 SDOperand Chain = Op.getOperand(0);
3966 SDOperand Size = Op.getOperand(1);
3967 // FIXME: Ensure alignment here
3971 MVT::ValueType IntPtr = getPointerTy();
3972 MVT::ValueType SPTy = (Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
3974 Chain = DAG.getCopyToReg(Chain, X86::EAX, Size, Flag);
3975 Flag = Chain.getValue(1);
3977 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
3978 SDOperand Ops[] = { Chain,
3979 DAG.getTargetExternalSymbol("_alloca", IntPtr),
3980 DAG.getRegister(X86::EAX, IntPtr),
3982 Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops, 4);
3983 Flag = Chain.getValue(1);
3985 Chain = DAG.getCopyFromReg(Chain, X86StackPtr, SPTy).getValue(1);
3987 std::vector<MVT::ValueType> Tys;
3988 Tys.push_back(SPTy);
3989 Tys.push_back(MVT::Other);
3990 SDOperand Ops1[2] = { Chain.getValue(0), Chain };
3991 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops1, 2);
3995 X86TargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) {
3996 MachineFunction &MF = DAG.getMachineFunction();
3997 const Function* Fn = MF.getFunction();
3998 if (Fn->hasExternalLinkage() &&
3999 Subtarget->isTargetCygMing() &&
4000 Fn->getName() == "main")
4001 MF.getInfo<X86MachineFunctionInfo>()->setForceFramePointer(true);
4003 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
4004 if (Subtarget->is64Bit())
4005 return LowerX86_64CCCArguments(Op, DAG);
4009 assert(0 && "Unsupported calling convention");
4010 case CallingConv::Fast:
4011 // TODO: implement fastcc.
4014 case CallingConv::C:
4015 return LowerCCCArguments(Op, DAG);
4016 case CallingConv::X86_StdCall:
4017 MF.getInfo<X86MachineFunctionInfo>()->setDecorationStyle(StdCall);
4018 return LowerCCCArguments(Op, DAG, true);
4019 case CallingConv::X86_FastCall:
4020 MF.getInfo<X86MachineFunctionInfo>()->setDecorationStyle(FastCall);
4021 return LowerFastCCArguments(Op, DAG);
4025 SDOperand X86TargetLowering::LowerMEMSET(SDOperand Op, SelectionDAG &DAG) {
4026 SDOperand InFlag(0, 0);
4027 SDOperand Chain = Op.getOperand(0);
4029 (unsigned)cast<ConstantSDNode>(Op.getOperand(4))->getValue();
4030 if (Align == 0) Align = 1;
4032 ConstantSDNode *I = dyn_cast<ConstantSDNode>(Op.getOperand(3));
4033 // If not DWORD aligned or size is more than the threshold, call memset.
4034 // The libc version is likely to be faster for these cases. It can use the
4035 // address value and run time information about the CPU.
4036 if ((Align & 3) != 0 ||
4037 (I && I->getValue() > Subtarget->getMinRepStrSizeThreshold())) {
4038 MVT::ValueType IntPtr = getPointerTy();
4039 const Type *IntPtrTy = getTargetData()->getIntPtrType();
4040 TargetLowering::ArgListTy Args;
4041 TargetLowering::ArgListEntry Entry;
4042 Entry.Node = Op.getOperand(1);
4043 Entry.Ty = IntPtrTy;
4044 Args.push_back(Entry);
4045 // Extend the unsigned i8 argument to be an int value for the call.
4046 Entry.Node = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Op.getOperand(2));
4047 Entry.Ty = IntPtrTy;
4048 Args.push_back(Entry);
4049 Entry.Node = Op.getOperand(3);
4050 Args.push_back(Entry);
4051 std::pair<SDOperand,SDOperand> CallResult =
4052 LowerCallTo(Chain, Type::VoidTy, false, false, CallingConv::C, false,
4053 DAG.getExternalSymbol("memset", IntPtr), Args, DAG);
4054 return CallResult.second;
4059 ConstantSDNode *ValC = dyn_cast<ConstantSDNode>(Op.getOperand(2));
4060 unsigned BytesLeft = 0;
4061 bool TwoRepStos = false;
4064 uint64_t Val = ValC->getValue() & 255;
4066 // If the value is a constant, then we can potentially use larger sets.
4067 switch (Align & 3) {
4068 case 2: // WORD aligned
4071 Val = (Val << 8) | Val;
4073 case 0: // DWORD aligned
4076 Val = (Val << 8) | Val;
4077 Val = (Val << 16) | Val;
4078 if (Subtarget->is64Bit() && ((Align & 0xF) == 0)) { // QWORD aligned
4081 Val = (Val << 32) | Val;
4084 default: // Byte aligned
4087 Count = Op.getOperand(3);
4091 if (AVT > MVT::i8) {
4093 unsigned UBytes = MVT::getSizeInBits(AVT) / 8;
4094 Count = DAG.getConstant(I->getValue() / UBytes, getPointerTy());
4095 BytesLeft = I->getValue() % UBytes;
4097 assert(AVT >= MVT::i32 &&
4098 "Do not use rep;stos if not at least DWORD aligned");
4099 Count = DAG.getNode(ISD::SRL, Op.getOperand(3).getValueType(),
4100 Op.getOperand(3), DAG.getConstant(2, MVT::i8));
4105 Chain = DAG.getCopyToReg(Chain, ValReg, DAG.getConstant(Val, AVT),
4107 InFlag = Chain.getValue(1);
4110 Count = Op.getOperand(3);
4111 Chain = DAG.getCopyToReg(Chain, X86::AL, Op.getOperand(2), InFlag);
4112 InFlag = Chain.getValue(1);
4115 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RCX : X86::ECX,
4117 InFlag = Chain.getValue(1);
4118 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RDI : X86::EDI,
4119 Op.getOperand(1), InFlag);
4120 InFlag = Chain.getValue(1);
4122 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
4123 SmallVector<SDOperand, 8> Ops;
4124 Ops.push_back(Chain);
4125 Ops.push_back(DAG.getValueType(AVT));
4126 Ops.push_back(InFlag);
4127 Chain = DAG.getNode(X86ISD::REP_STOS, Tys, &Ops[0], Ops.size());
4130 InFlag = Chain.getValue(1);
4131 Count = Op.getOperand(3);
4132 MVT::ValueType CVT = Count.getValueType();
4133 SDOperand Left = DAG.getNode(ISD::AND, CVT, Count,
4134 DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT));
4135 Chain = DAG.getCopyToReg(Chain, (CVT == MVT::i64) ? X86::RCX : X86::ECX,
4137 InFlag = Chain.getValue(1);
4138 Tys = DAG.getVTList(MVT::Other, MVT::Flag);
4140 Ops.push_back(Chain);
4141 Ops.push_back(DAG.getValueType(MVT::i8));
4142 Ops.push_back(InFlag);
4143 Chain = DAG.getNode(X86ISD::REP_STOS, Tys, &Ops[0], Ops.size());
4144 } else if (BytesLeft) {
4145 // Issue stores for the last 1 - 7 bytes.
4147 unsigned Val = ValC->getValue() & 255;
4148 unsigned Offset = I->getValue() - BytesLeft;
4149 SDOperand DstAddr = Op.getOperand(1);
4150 MVT::ValueType AddrVT = DstAddr.getValueType();
4151 if (BytesLeft >= 4) {
4152 Val = (Val << 8) | Val;
4153 Val = (Val << 16) | Val;
4154 Value = DAG.getConstant(Val, MVT::i32);
4155 Chain = DAG.getStore(Chain, Value,
4156 DAG.getNode(ISD::ADD, AddrVT, DstAddr,
4157 DAG.getConstant(Offset, AddrVT)),
4162 if (BytesLeft >= 2) {
4163 Value = DAG.getConstant((Val << 8) | Val, MVT::i16);
4164 Chain = DAG.getStore(Chain, Value,
4165 DAG.getNode(ISD::ADD, AddrVT, DstAddr,
4166 DAG.getConstant(Offset, AddrVT)),
4171 if (BytesLeft == 1) {
4172 Value = DAG.getConstant(Val, MVT::i8);
4173 Chain = DAG.getStore(Chain, Value,
4174 DAG.getNode(ISD::ADD, AddrVT, DstAddr,
4175 DAG.getConstant(Offset, AddrVT)),
4183 SDOperand X86TargetLowering::LowerMEMCPY(SDOperand Op, SelectionDAG &DAG) {
4184 SDOperand Chain = Op.getOperand(0);
4186 (unsigned)cast<ConstantSDNode>(Op.getOperand(4))->getValue();
4187 if (Align == 0) Align = 1;
4189 ConstantSDNode *I = dyn_cast<ConstantSDNode>(Op.getOperand(3));
4190 // If not DWORD aligned or size is more than the threshold, call memcpy.
4191 // The libc version is likely to be faster for these cases. It can use the
4192 // address value and run time information about the CPU.
4193 // With glibc 2.6.1 on a core 2, coping an array of 100M longs was 30% faster
4194 if ((Align & 3) != 0 ||
4195 (I && I->getValue() > Subtarget->getMinRepStrSizeThreshold())) {
4196 MVT::ValueType IntPtr = getPointerTy();
4197 TargetLowering::ArgListTy Args;
4198 TargetLowering::ArgListEntry Entry;
4199 Entry.Ty = getTargetData()->getIntPtrType();
4200 Entry.Node = Op.getOperand(1); Args.push_back(Entry);
4201 Entry.Node = Op.getOperand(2); Args.push_back(Entry);
4202 Entry.Node = Op.getOperand(3); Args.push_back(Entry);
4203 std::pair<SDOperand,SDOperand> CallResult =
4204 LowerCallTo(Chain, Type::VoidTy, false, false, CallingConv::C, false,
4205 DAG.getExternalSymbol("memcpy", IntPtr), Args, DAG);
4206 return CallResult.second;
4211 unsigned BytesLeft = 0;
4212 bool TwoRepMovs = false;
4213 switch (Align & 3) {
4214 case 2: // WORD aligned
4217 case 0: // DWORD aligned
4219 if (Subtarget->is64Bit() && ((Align & 0xF) == 0)) // QWORD aligned
4222 default: // Byte aligned
4224 Count = Op.getOperand(3);
4228 if (AVT > MVT::i8) {
4230 unsigned UBytes = MVT::getSizeInBits(AVT) / 8;
4231 Count = DAG.getConstant(I->getValue() / UBytes, getPointerTy());
4232 BytesLeft = I->getValue() % UBytes;
4234 assert(AVT >= MVT::i32 &&
4235 "Do not use rep;movs if not at least DWORD aligned");
4236 Count = DAG.getNode(ISD::SRL, Op.getOperand(3).getValueType(),
4237 Op.getOperand(3), DAG.getConstant(2, MVT::i8));
4242 SDOperand InFlag(0, 0);
4243 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RCX : X86::ECX,
4245 InFlag = Chain.getValue(1);
4246 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RDI : X86::EDI,
4247 Op.getOperand(1), InFlag);
4248 InFlag = Chain.getValue(1);
4249 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RSI : X86::ESI,
4250 Op.getOperand(2), InFlag);
4251 InFlag = Chain.getValue(1);
4253 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
4254 SmallVector<SDOperand, 8> Ops;
4255 Ops.push_back(Chain);
4256 Ops.push_back(DAG.getValueType(AVT));
4257 Ops.push_back(InFlag);
4258 Chain = DAG.getNode(X86ISD::REP_MOVS, Tys, &Ops[0], Ops.size());
4261 InFlag = Chain.getValue(1);
4262 Count = Op.getOperand(3);
4263 MVT::ValueType CVT = Count.getValueType();
4264 SDOperand Left = DAG.getNode(ISD::AND, CVT, Count,
4265 DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT));
4266 Chain = DAG.getCopyToReg(Chain, (CVT == MVT::i64) ? X86::RCX : X86::ECX,
4268 InFlag = Chain.getValue(1);
4269 Tys = DAG.getVTList(MVT::Other, MVT::Flag);
4271 Ops.push_back(Chain);
4272 Ops.push_back(DAG.getValueType(MVT::i8));
4273 Ops.push_back(InFlag);
4274 Chain = DAG.getNode(X86ISD::REP_MOVS, Tys, &Ops[0], Ops.size());
4275 } else if (BytesLeft) {
4276 // Issue loads and stores for the last 1 - 7 bytes.
4277 unsigned Offset = I->getValue() - BytesLeft;
4278 SDOperand DstAddr = Op.getOperand(1);
4279 MVT::ValueType DstVT = DstAddr.getValueType();
4280 SDOperand SrcAddr = Op.getOperand(2);
4281 MVT::ValueType SrcVT = SrcAddr.getValueType();
4283 if (BytesLeft >= 4) {
4284 Value = DAG.getLoad(MVT::i32, Chain,
4285 DAG.getNode(ISD::ADD, SrcVT, SrcAddr,
4286 DAG.getConstant(Offset, SrcVT)),
4288 Chain = Value.getValue(1);
4289 Chain = DAG.getStore(Chain, Value,
4290 DAG.getNode(ISD::ADD, DstVT, DstAddr,
4291 DAG.getConstant(Offset, DstVT)),
4296 if (BytesLeft >= 2) {
4297 Value = DAG.getLoad(MVT::i16, Chain,
4298 DAG.getNode(ISD::ADD, SrcVT, SrcAddr,
4299 DAG.getConstant(Offset, SrcVT)),
4301 Chain = Value.getValue(1);
4302 Chain = DAG.getStore(Chain, Value,
4303 DAG.getNode(ISD::ADD, DstVT, DstAddr,
4304 DAG.getConstant(Offset, DstVT)),
4310 if (BytesLeft == 1) {
4311 Value = DAG.getLoad(MVT::i8, Chain,
4312 DAG.getNode(ISD::ADD, SrcVT, SrcAddr,
4313 DAG.getConstant(Offset, SrcVT)),
4315 Chain = Value.getValue(1);
4316 Chain = DAG.getStore(Chain, Value,
4317 DAG.getNode(ISD::ADD, DstVT, DstAddr,
4318 DAG.getConstant(Offset, DstVT)),
4327 X86TargetLowering::LowerREADCYCLCECOUNTER(SDOperand Op, SelectionDAG &DAG) {
4328 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
4329 SDOperand TheOp = Op.getOperand(0);
4330 SDOperand rd = DAG.getNode(X86ISD::RDTSC_DAG, Tys, &TheOp, 1);
4331 if (Subtarget->is64Bit()) {
4332 SDOperand Copy1 = DAG.getCopyFromReg(rd, X86::RAX, MVT::i64, rd.getValue(1));
4333 SDOperand Copy2 = DAG.getCopyFromReg(Copy1.getValue(1), X86::RDX,
4334 MVT::i64, Copy1.getValue(2));
4335 SDOperand Tmp = DAG.getNode(ISD::SHL, MVT::i64, Copy2,
4336 DAG.getConstant(32, MVT::i8));
4338 DAG.getNode(ISD::OR, MVT::i64, Copy1, Tmp), Copy2.getValue(1)
4341 Tys = DAG.getVTList(MVT::i64, MVT::Other);
4342 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops, 2);
4345 SDOperand Copy1 = DAG.getCopyFromReg(rd, X86::EAX, MVT::i32, rd.getValue(1));
4346 SDOperand Copy2 = DAG.getCopyFromReg(Copy1.getValue(1), X86::EDX,
4347 MVT::i32, Copy1.getValue(2));
4348 SDOperand Ops[] = { Copy1, Copy2, Copy2.getValue(1) };
4349 Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
4350 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops, 3);
4353 SDOperand X86TargetLowering::LowerVASTART(SDOperand Op, SelectionDAG &DAG) {
4354 SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2));
4356 if (!Subtarget->is64Bit()) {
4357 // vastart just stores the address of the VarArgsFrameIndex slot into the
4358 // memory location argument.
4359 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
4360 return DAG.getStore(Op.getOperand(0), FR,Op.getOperand(1), SV->getValue(),
4365 // gp_offset (0 - 6 * 8)
4366 // fp_offset (48 - 48 + 8 * 16)
4367 // overflow_arg_area (point to parameters coming in memory).
4369 SmallVector<SDOperand, 8> MemOps;
4370 SDOperand FIN = Op.getOperand(1);
4372 SDOperand Store = DAG.getStore(Op.getOperand(0),
4373 DAG.getConstant(VarArgsGPOffset, MVT::i32),
4374 FIN, SV->getValue(), SV->getOffset());
4375 MemOps.push_back(Store);
4378 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
4379 DAG.getConstant(4, getPointerTy()));
4380 Store = DAG.getStore(Op.getOperand(0),
4381 DAG.getConstant(VarArgsFPOffset, MVT::i32),
4382 FIN, SV->getValue(), SV->getOffset());
4383 MemOps.push_back(Store);
4385 // Store ptr to overflow_arg_area
4386 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
4387 DAG.getConstant(4, getPointerTy()));
4388 SDOperand OVFIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
4389 Store = DAG.getStore(Op.getOperand(0), OVFIN, FIN, SV->getValue(),
4391 MemOps.push_back(Store);
4393 // Store ptr to reg_save_area.
4394 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
4395 DAG.getConstant(8, getPointerTy()));
4396 SDOperand RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
4397 Store = DAG.getStore(Op.getOperand(0), RSFIN, FIN, SV->getValue(),
4399 MemOps.push_back(Store);
4400 return DAG.getNode(ISD::TokenFactor, MVT::Other, &MemOps[0], MemOps.size());
4403 SDOperand X86TargetLowering::LowerVACOPY(SDOperand Op, SelectionDAG &DAG) {
4404 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
4405 SDOperand Chain = Op.getOperand(0);
4406 SDOperand DstPtr = Op.getOperand(1);
4407 SDOperand SrcPtr = Op.getOperand(2);
4408 SrcValueSDNode *DstSV = cast<SrcValueSDNode>(Op.getOperand(3));
4409 SrcValueSDNode *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4));
4411 SrcPtr = DAG.getLoad(getPointerTy(), Chain, SrcPtr,
4412 SrcSV->getValue(), SrcSV->getOffset());
4413 Chain = SrcPtr.getValue(1);
4414 for (unsigned i = 0; i < 3; ++i) {
4415 SDOperand Val = DAG.getLoad(MVT::i64, Chain, SrcPtr,
4416 SrcSV->getValue(), SrcSV->getOffset());
4417 Chain = Val.getValue(1);
4418 Chain = DAG.getStore(Chain, Val, DstPtr,
4419 DstSV->getValue(), DstSV->getOffset());
4422 SrcPtr = DAG.getNode(ISD::ADD, getPointerTy(), SrcPtr,
4423 DAG.getConstant(8, getPointerTy()));
4424 DstPtr = DAG.getNode(ISD::ADD, getPointerTy(), DstPtr,
4425 DAG.getConstant(8, getPointerTy()));
4431 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG) {
4432 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getValue();
4434 default: return SDOperand(); // Don't custom lower most intrinsics.
4435 // Comparison intrinsics.
4436 case Intrinsic::x86_sse_comieq_ss:
4437 case Intrinsic::x86_sse_comilt_ss:
4438 case Intrinsic::x86_sse_comile_ss:
4439 case Intrinsic::x86_sse_comigt_ss:
4440 case Intrinsic::x86_sse_comige_ss:
4441 case Intrinsic::x86_sse_comineq_ss:
4442 case Intrinsic::x86_sse_ucomieq_ss:
4443 case Intrinsic::x86_sse_ucomilt_ss:
4444 case Intrinsic::x86_sse_ucomile_ss:
4445 case Intrinsic::x86_sse_ucomigt_ss:
4446 case Intrinsic::x86_sse_ucomige_ss:
4447 case Intrinsic::x86_sse_ucomineq_ss:
4448 case Intrinsic::x86_sse2_comieq_sd:
4449 case Intrinsic::x86_sse2_comilt_sd:
4450 case Intrinsic::x86_sse2_comile_sd:
4451 case Intrinsic::x86_sse2_comigt_sd:
4452 case Intrinsic::x86_sse2_comige_sd:
4453 case Intrinsic::x86_sse2_comineq_sd:
4454 case Intrinsic::x86_sse2_ucomieq_sd:
4455 case Intrinsic::x86_sse2_ucomilt_sd:
4456 case Intrinsic::x86_sse2_ucomile_sd:
4457 case Intrinsic::x86_sse2_ucomigt_sd:
4458 case Intrinsic::x86_sse2_ucomige_sd:
4459 case Intrinsic::x86_sse2_ucomineq_sd: {
4461 ISD::CondCode CC = ISD::SETCC_INVALID;
4464 case Intrinsic::x86_sse_comieq_ss:
4465 case Intrinsic::x86_sse2_comieq_sd:
4469 case Intrinsic::x86_sse_comilt_ss:
4470 case Intrinsic::x86_sse2_comilt_sd:
4474 case Intrinsic::x86_sse_comile_ss:
4475 case Intrinsic::x86_sse2_comile_sd:
4479 case Intrinsic::x86_sse_comigt_ss:
4480 case Intrinsic::x86_sse2_comigt_sd:
4484 case Intrinsic::x86_sse_comige_ss:
4485 case Intrinsic::x86_sse2_comige_sd:
4489 case Intrinsic::x86_sse_comineq_ss:
4490 case Intrinsic::x86_sse2_comineq_sd:
4494 case Intrinsic::x86_sse_ucomieq_ss:
4495 case Intrinsic::x86_sse2_ucomieq_sd:
4496 Opc = X86ISD::UCOMI;
4499 case Intrinsic::x86_sse_ucomilt_ss:
4500 case Intrinsic::x86_sse2_ucomilt_sd:
4501 Opc = X86ISD::UCOMI;
4504 case Intrinsic::x86_sse_ucomile_ss:
4505 case Intrinsic::x86_sse2_ucomile_sd:
4506 Opc = X86ISD::UCOMI;
4509 case Intrinsic::x86_sse_ucomigt_ss:
4510 case Intrinsic::x86_sse2_ucomigt_sd:
4511 Opc = X86ISD::UCOMI;
4514 case Intrinsic::x86_sse_ucomige_ss:
4515 case Intrinsic::x86_sse2_ucomige_sd:
4516 Opc = X86ISD::UCOMI;
4519 case Intrinsic::x86_sse_ucomineq_ss:
4520 case Intrinsic::x86_sse2_ucomineq_sd:
4521 Opc = X86ISD::UCOMI;
4527 SDOperand LHS = Op.getOperand(1);
4528 SDOperand RHS = Op.getOperand(2);
4529 translateX86CC(CC, true, X86CC, LHS, RHS, DAG);
4531 if (NewCCModeling) {
4532 Opc = (Opc == X86ISD::UCOMI) ? X86ISD::UCOMI_NEW : X86ISD::COMI_NEW;
4533 SDOperand Cond = DAG.getNode(Opc, MVT::i32, LHS, RHS);
4534 SDOperand SetCC = DAG.getNode(X86ISD::SETCC_NEW, MVT::i8,
4535 DAG.getConstant(X86CC, MVT::i8), Cond);
4536 return DAG.getNode(ISD::ANY_EXTEND, MVT::i32, SetCC);
4538 const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::Other, MVT::Flag);
4539 SDOperand Ops1[] = { DAG.getEntryNode(), LHS, RHS };
4540 SDOperand Cond = DAG.getNode(Opc, VTs, 2, Ops1, 3);
4541 VTs = DAG.getNodeValueTypes(MVT::i8, MVT::Flag);
4542 SDOperand Ops2[] = { DAG.getConstant(X86CC, MVT::i8), Cond };
4543 SDOperand SetCC = DAG.getNode(X86ISD::SETCC, VTs, 2, Ops2, 2);
4544 return DAG.getNode(ISD::ANY_EXTEND, MVT::i32, SetCC);
4550 SDOperand X86TargetLowering::LowerRETURNADDR(SDOperand Op, SelectionDAG &DAG) {
4551 // Depths > 0 not supported yet!
4552 if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0)
4555 // Just load the return address
4556 SDOperand RetAddrFI = getReturnAddressFrameIndex(DAG);
4557 return DAG.getLoad(getPointerTy(), DAG.getEntryNode(), RetAddrFI, NULL, 0);
4560 SDOperand X86TargetLowering::LowerFRAMEADDR(SDOperand Op, SelectionDAG &DAG) {
4561 // Depths > 0 not supported yet!
4562 if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0)
4565 SDOperand RetAddrFI = getReturnAddressFrameIndex(DAG);
4566 return DAG.getNode(ISD::SUB, getPointerTy(), RetAddrFI,
4567 DAG.getConstant(4, getPointerTy()));
4570 SDOperand X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDOperand Op,
4571 SelectionDAG &DAG) {
4572 // Is not yet supported on x86-64
4573 if (Subtarget->is64Bit())
4576 return DAG.getConstant(8, getPointerTy());
4579 SDOperand X86TargetLowering::LowerEH_RETURN(SDOperand Op, SelectionDAG &DAG)
4581 assert(!Subtarget->is64Bit() &&
4582 "Lowering of eh_return builtin is not supported yet on x86-64");
4584 MachineFunction &MF = DAG.getMachineFunction();
4585 SDOperand Chain = Op.getOperand(0);
4586 SDOperand Offset = Op.getOperand(1);
4587 SDOperand Handler = Op.getOperand(2);
4589 SDOperand Frame = DAG.getRegister(RegInfo->getFrameRegister(MF),
4592 SDOperand StoreAddr = DAG.getNode(ISD::SUB, getPointerTy(), Frame,
4593 DAG.getConstant(-4UL, getPointerTy()));
4594 StoreAddr = DAG.getNode(ISD::ADD, getPointerTy(), StoreAddr, Offset);
4595 Chain = DAG.getStore(Chain, Handler, StoreAddr, NULL, 0);
4596 Chain = DAG.getCopyToReg(Chain, X86::ECX, StoreAddr);
4597 MF.addLiveOut(X86::ECX);
4599 return DAG.getNode(X86ISD::EH_RETURN, MVT::Other,
4600 Chain, DAG.getRegister(X86::ECX, getPointerTy()));
4603 SDOperand X86TargetLowering::LowerTRAMPOLINE(SDOperand Op,
4604 SelectionDAG &DAG) {
4605 SDOperand Root = Op.getOperand(0);
4606 SDOperand Trmp = Op.getOperand(1); // trampoline
4607 SDOperand FPtr = Op.getOperand(2); // nested function
4608 SDOperand Nest = Op.getOperand(3); // 'nest' parameter value
4610 SrcValueSDNode *TrmpSV = cast<SrcValueSDNode>(Op.getOperand(4));
4612 if (Subtarget->is64Bit()) {
4613 return SDOperand(); // not yet supported
4615 Function *Func = (Function *)
4616 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
4617 unsigned CC = Func->getCallingConv();
4622 assert(0 && "Unsupported calling convention");
4623 case CallingConv::C:
4624 case CallingConv::Fast:
4625 case CallingConv::X86_StdCall: {
4626 // Pass 'nest' parameter in ECX.
4627 // Must be kept in sync with X86CallingConv.td
4630 // Check that ECX wasn't needed by an 'inreg' parameter.
4631 const FunctionType *FTy = Func->getFunctionType();
4632 const ParamAttrsList *Attrs = FTy->getParamAttrs();
4634 if (Attrs && !Func->isVarArg()) {
4635 unsigned InRegCount = 0;
4638 for (FunctionType::param_iterator I = FTy->param_begin(),
4639 E = FTy->param_end(); I != E; ++I, ++Idx)
4640 if (Attrs->paramHasAttr(Idx, ParamAttr::InReg))
4641 // FIXME: should only count parameters that are lowered to integers.
4642 InRegCount += (getTargetData()->getTypeSizeInBits(*I) + 31) / 32;
4644 if (InRegCount > 2) {
4645 cerr << "Nest register in use - reduce number of inreg parameters!\n";
4651 case CallingConv::X86_FastCall:
4652 // Pass 'nest' parameter in EAX.
4653 // Must be kept in sync with X86CallingConv.td
4658 const X86InstrInfo *TII =
4659 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
4661 SDOperand OutChains[4];
4662 SDOperand Addr, Disp;
4664 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(10, MVT::i32));
4665 Disp = DAG.getNode(ISD::SUB, MVT::i32, FPtr, Addr);
4667 unsigned char MOV32ri = TII->getBaseOpcodeFor(X86::MOV32ri);
4668 unsigned char N86Reg = ((X86RegisterInfo&)RegInfo).getX86RegNum(NestReg);
4669 OutChains[0] = DAG.getStore(Root, DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
4670 Trmp, TrmpSV->getValue(), TrmpSV->getOffset());
4672 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(1, MVT::i32));
4673 OutChains[1] = DAG.getStore(Root, Nest, Addr, TrmpSV->getValue(),
4674 TrmpSV->getOffset() + 1, false, 1);
4676 unsigned char JMP = TII->getBaseOpcodeFor(X86::JMP);
4677 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(5, MVT::i32));
4678 OutChains[2] = DAG.getStore(Root, DAG.getConstant(JMP, MVT::i8), Addr,
4679 TrmpSV->getValue() + 5, TrmpSV->getOffset());
4681 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(6, MVT::i32));
4682 OutChains[3] = DAG.getStore(Root, Disp, Addr, TrmpSV->getValue(),
4683 TrmpSV->getOffset() + 6, false, 1);
4686 { Trmp, DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains, 4) };
4687 return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(), Ops, 2);
4691 /// LowerOperation - Provide custom lowering hooks for some operations.
4693 SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
4694 switch (Op.getOpcode()) {
4695 default: assert(0 && "Should not custom lower this!");
4696 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
4697 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
4698 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
4699 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
4700 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
4701 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
4702 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
4703 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
4704 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
4705 case ISD::SHL_PARTS:
4706 case ISD::SRA_PARTS:
4707 case ISD::SRL_PARTS: return LowerShift(Op, DAG);
4711 case ISD::UREM: return LowerIntegerDivOrRem(Op, DAG);
4712 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
4713 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
4714 case ISD::FABS: return LowerFABS(Op, DAG);
4715 case ISD::FNEG: return LowerFNEG(Op, DAG);
4716 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
4717 case ISD::SETCC: return NewCCModeling
4718 ? LowerSETCC_New(Op, DAG)
4719 : LowerSETCC(Op, DAG, DAG.getEntryNode());
4720 case ISD::SELECT: return NewCCModeling
4721 ? LowerSELECT_New(Op, DAG)
4722 : LowerSELECT(Op, DAG);
4723 case ISD::BRCOND: return NewCCModeling
4724 ? LowerBRCOND_New(Op, DAG)
4725 : LowerBRCOND(Op, DAG);
4726 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
4727 case ISD::CALL: return LowerCALL(Op, DAG);
4728 case ISD::RET: return LowerRET(Op, DAG);
4729 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
4730 case ISD::MEMSET: return LowerMEMSET(Op, DAG);
4731 case ISD::MEMCPY: return LowerMEMCPY(Op, DAG);
4732 case ISD::READCYCLECOUNTER: return LowerREADCYCLCECOUNTER(Op, DAG);
4733 case ISD::VASTART: return LowerVASTART(Op, DAG);
4734 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
4735 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
4736 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
4737 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
4738 case ISD::FRAME_TO_ARGS_OFFSET:
4739 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
4740 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
4741 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
4742 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG);
4747 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
4749 default: return NULL;
4750 case X86ISD::SHLD: return "X86ISD::SHLD";
4751 case X86ISD::SHRD: return "X86ISD::SHRD";
4752 case X86ISD::FAND: return "X86ISD::FAND";
4753 case X86ISD::FOR: return "X86ISD::FOR";
4754 case X86ISD::FXOR: return "X86ISD::FXOR";
4755 case X86ISD::FSRL: return "X86ISD::FSRL";
4756 case X86ISD::FILD: return "X86ISD::FILD";
4757 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
4758 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
4759 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
4760 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
4761 case X86ISD::FLD: return "X86ISD::FLD";
4762 case X86ISD::FST: return "X86ISD::FST";
4763 case X86ISD::FP_GET_RESULT: return "X86ISD::FP_GET_RESULT";
4764 case X86ISD::FP_SET_RESULT: return "X86ISD::FP_SET_RESULT";
4765 case X86ISD::CALL: return "X86ISD::CALL";
4766 case X86ISD::TAILCALL: return "X86ISD::TAILCALL";
4767 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
4768 case X86ISD::CMP: return "X86ISD::CMP";
4769 case X86ISD::CMP_NEW: return "X86ISD::CMP_NEW";
4770 case X86ISD::COMI: return "X86ISD::COMI";
4771 case X86ISD::COMI_NEW: return "X86ISD::COMI_NEW";
4772 case X86ISD::UCOMI: return "X86ISD::UCOMI";
4773 case X86ISD::UCOMI_NEW: return "X86ISD::UCOMI_NEW";
4774 case X86ISD::SETCC: return "X86ISD::SETCC";
4775 case X86ISD::SETCC_NEW: return "X86ISD::SETCC_NEW";
4776 case X86ISD::CMOV: return "X86ISD::CMOV";
4777 case X86ISD::CMOV_NEW: return "X86ISD::CMOV_NEW";
4778 case X86ISD::BRCOND: return "X86ISD::BRCOND";
4779 case X86ISD::BRCOND_NEW: return "X86ISD::BRCOND_NEW";
4780 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
4781 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
4782 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
4783 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
4784 case X86ISD::Wrapper: return "X86ISD::Wrapper";
4785 case X86ISD::S2VEC: return "X86ISD::S2VEC";
4786 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
4787 case X86ISD::PINSRW: return "X86ISD::PINSRW";
4788 case X86ISD::FMAX: return "X86ISD::FMAX";
4789 case X86ISD::FMIN: return "X86ISD::FMIN";
4790 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
4791 case X86ISD::FRCP: return "X86ISD::FRCP";
4792 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
4793 case X86ISD::THREAD_POINTER: return "X86ISD::THREAD_POINTER";
4794 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
4795 case X86ISD::DIV: return "X86ISD::DIV";
4796 case X86ISD::IDIV: return "X86ISD::IDIV";
4800 // isLegalAddressingMode - Return true if the addressing mode represented
4801 // by AM is legal for this target, for a load/store of the specified type.
4802 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
4803 const Type *Ty) const {
4804 // X86 supports extremely general addressing modes.
4806 // X86 allows a sign-extended 32-bit immediate field as a displacement.
4807 if (AM.BaseOffs <= -(1LL << 32) || AM.BaseOffs >= (1LL << 32)-1)
4811 // We can only fold this if we don't need an extra load.
4812 if (Subtarget->GVRequiresExtraLoad(AM.BaseGV, getTargetMachine(), false))
4815 // X86-64 only supports addr of globals in small code model.
4816 if (Subtarget->is64Bit()) {
4817 if (getTargetMachine().getCodeModel() != CodeModel::Small)
4819 // If lower 4G is not available, then we must use rip-relative addressing.
4820 if (AM.BaseOffs || AM.Scale > 1)
4831 // These scales always work.
4836 // These scales are formed with basereg+scalereg. Only accept if there is
4841 default: // Other stuff never works.
4849 /// isShuffleMaskLegal - Targets can use this to indicate that they only
4850 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
4851 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
4852 /// are assumed to be legal.
4854 X86TargetLowering::isShuffleMaskLegal(SDOperand Mask, MVT::ValueType VT) const {
4855 // Only do shuffles on 128-bit vector types for now.
4856 if (MVT::getSizeInBits(VT) == 64) return false;
4857 return (Mask.Val->getNumOperands() <= 4 ||
4858 isIdentityMask(Mask.Val) ||
4859 isIdentityMask(Mask.Val, true) ||
4860 isSplatMask(Mask.Val) ||
4861 isPSHUFHW_PSHUFLWMask(Mask.Val) ||
4862 X86::isUNPCKLMask(Mask.Val) ||
4863 X86::isUNPCKHMask(Mask.Val) ||
4864 X86::isUNPCKL_v_undef_Mask(Mask.Val) ||
4865 X86::isUNPCKH_v_undef_Mask(Mask.Val));
4868 bool X86TargetLowering::isVectorClearMaskLegal(std::vector<SDOperand> &BVOps,
4870 SelectionDAG &DAG) const {
4871 unsigned NumElts = BVOps.size();
4872 // Only do shuffles on 128-bit vector types for now.
4873 if (MVT::getSizeInBits(EVT) * NumElts == 64) return false;
4874 if (NumElts == 2) return true;
4876 return (isMOVLMask(&BVOps[0], 4) ||
4877 isCommutedMOVL(&BVOps[0], 4, true) ||
4878 isSHUFPMask(&BVOps[0], 4) ||
4879 isCommutedSHUFP(&BVOps[0], 4));
4884 //===----------------------------------------------------------------------===//
4885 // X86 Scheduler Hooks
4886 //===----------------------------------------------------------------------===//
4889 X86TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
4890 MachineBasicBlock *BB) {
4891 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4892 switch (MI->getOpcode()) {
4893 default: assert(false && "Unexpected instr type to insert");
4894 case X86::CMOV_FR32:
4895 case X86::CMOV_FR64:
4896 case X86::CMOV_V4F32:
4897 case X86::CMOV_V2F64:
4898 case X86::CMOV_V2I64:
4900 case X86::NEW_CMOV_FR32:
4901 case X86::NEW_CMOV_FR64:
4902 case X86::NEW_CMOV_V4F32:
4903 case X86::NEW_CMOV_V2F64:
4904 case X86::NEW_CMOV_V2I64: {
4905 // To "insert" a SELECT_CC instruction, we actually have to insert the
4906 // diamond control-flow pattern. The incoming instruction knows the
4907 // destination vreg to set, the condition code register to branch on, the
4908 // true/false values to select between, and a branch opcode to use.
4909 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4910 ilist<MachineBasicBlock>::iterator It = BB;
4916 // cmpTY ccX, r1, r2
4918 // fallthrough --> copy0MBB
4919 MachineBasicBlock *thisMBB = BB;
4920 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
4921 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
4923 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
4924 BuildMI(BB, TII->get(Opc)).addMBB(sinkMBB);
4925 MachineFunction *F = BB->getParent();
4926 F->getBasicBlockList().insert(It, copy0MBB);
4927 F->getBasicBlockList().insert(It, sinkMBB);
4928 // Update machine-CFG edges by first adding all successors of the current
4929 // block to the new block which will contain the Phi node for the select.
4930 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
4931 e = BB->succ_end(); i != e; ++i)
4932 sinkMBB->addSuccessor(*i);
4933 // Next, remove all successors of the current block, and add the true
4934 // and fallthrough blocks as its successors.
4935 while(!BB->succ_empty())
4936 BB->removeSuccessor(BB->succ_begin());
4937 BB->addSuccessor(copy0MBB);
4938 BB->addSuccessor(sinkMBB);
4941 // %FalseValue = ...
4942 // # fallthrough to sinkMBB
4945 // Update machine-CFG edges
4946 BB->addSuccessor(sinkMBB);
4949 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
4952 BuildMI(BB, TII->get(X86::PHI), MI->getOperand(0).getReg())
4953 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
4954 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
4956 delete MI; // The pseudo instruction is gone now.
4960 case X86::FP32_TO_INT16_IN_MEM:
4961 case X86::FP32_TO_INT32_IN_MEM:
4962 case X86::FP32_TO_INT64_IN_MEM:
4963 case X86::FP64_TO_INT16_IN_MEM:
4964 case X86::FP64_TO_INT32_IN_MEM:
4965 case X86::FP64_TO_INT64_IN_MEM:
4966 case X86::FP80_TO_INT16_IN_MEM:
4967 case X86::FP80_TO_INT32_IN_MEM:
4968 case X86::FP80_TO_INT64_IN_MEM: {
4969 // Change the floating point control register to use "round towards zero"
4970 // mode when truncating to an integer value.
4971 MachineFunction *F = BB->getParent();
4972 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2);
4973 addFrameReference(BuildMI(BB, TII->get(X86::FNSTCW16m)), CWFrameIdx);
4975 // Load the old value of the high byte of the control word...
4977 F->getSSARegMap()->createVirtualRegister(X86::GR16RegisterClass);
4978 addFrameReference(BuildMI(BB, TII->get(X86::MOV16rm), OldCW), CWFrameIdx);
4980 // Set the high part to be round to zero...
4981 addFrameReference(BuildMI(BB, TII->get(X86::MOV16mi)), CWFrameIdx)
4984 // Reload the modified control word now...
4985 addFrameReference(BuildMI(BB, TII->get(X86::FLDCW16m)), CWFrameIdx);
4987 // Restore the memory image of control word to original value
4988 addFrameReference(BuildMI(BB, TII->get(X86::MOV16mr)), CWFrameIdx)
4991 // Get the X86 opcode to use.
4993 switch (MI->getOpcode()) {
4994 default: assert(0 && "illegal opcode!");
4995 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
4996 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
4997 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
4998 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
4999 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
5000 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
5001 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
5002 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
5003 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
5007 MachineOperand &Op = MI->getOperand(0);
5008 if (Op.isRegister()) {
5009 AM.BaseType = X86AddressMode::RegBase;
5010 AM.Base.Reg = Op.getReg();
5012 AM.BaseType = X86AddressMode::FrameIndexBase;
5013 AM.Base.FrameIndex = Op.getFrameIndex();
5015 Op = MI->getOperand(1);
5016 if (Op.isImmediate())
5017 AM.Scale = Op.getImm();
5018 Op = MI->getOperand(2);
5019 if (Op.isImmediate())
5020 AM.IndexReg = Op.getImm();
5021 Op = MI->getOperand(3);
5022 if (Op.isGlobalAddress()) {
5023 AM.GV = Op.getGlobal();
5025 AM.Disp = Op.getImm();
5027 addFullAddress(BuildMI(BB, TII->get(Opc)), AM)
5028 .addReg(MI->getOperand(4).getReg());
5030 // Reload the original control word now.
5031 addFrameReference(BuildMI(BB, TII->get(X86::FLDCW16m)), CWFrameIdx);
5033 delete MI; // The pseudo instruction is gone now.
5039 //===----------------------------------------------------------------------===//
5040 // X86 Optimization Hooks
5041 //===----------------------------------------------------------------------===//
5043 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
5045 uint64_t &KnownZero,
5047 const SelectionDAG &DAG,
5048 unsigned Depth) const {
5049 unsigned Opc = Op.getOpcode();
5050 assert((Opc >= ISD::BUILTIN_OP_END ||
5051 Opc == ISD::INTRINSIC_WO_CHAIN ||
5052 Opc == ISD::INTRINSIC_W_CHAIN ||
5053 Opc == ISD::INTRINSIC_VOID) &&
5054 "Should use MaskedValueIsZero if you don't know whether Op"
5055 " is a target node!");
5057 KnownZero = KnownOne = 0; // Don't know anything.
5061 case X86ISD::SETCC_NEW:
5062 KnownZero |= (MVT::getIntVTBitMask(Op.getValueType()) ^ 1ULL);
5067 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
5068 /// element of the result of the vector shuffle.
5069 static SDOperand getShuffleScalarElt(SDNode *N, unsigned i, SelectionDAG &DAG) {
5070 MVT::ValueType VT = N->getValueType(0);
5071 SDOperand PermMask = N->getOperand(2);
5072 unsigned NumElems = PermMask.getNumOperands();
5073 SDOperand V = (i < NumElems) ? N->getOperand(0) : N->getOperand(1);
5075 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR) {
5077 ? V.getOperand(0) : DAG.getNode(ISD::UNDEF, MVT::getVectorElementType(VT));
5078 } else if (V.getOpcode() == ISD::VECTOR_SHUFFLE) {
5079 SDOperand Idx = PermMask.getOperand(i);
5080 if (Idx.getOpcode() == ISD::UNDEF)
5081 return DAG.getNode(ISD::UNDEF, MVT::getVectorElementType(VT));
5082 return getShuffleScalarElt(V.Val,cast<ConstantSDNode>(Idx)->getValue(),DAG);
5087 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
5088 /// node is a GlobalAddress + an offset.
5089 static bool isGAPlusOffset(SDNode *N, GlobalValue* &GA, int64_t &Offset) {
5090 unsigned Opc = N->getOpcode();
5091 if (Opc == X86ISD::Wrapper) {
5092 if (dyn_cast<GlobalAddressSDNode>(N->getOperand(0))) {
5093 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
5096 } else if (Opc == ISD::ADD) {
5097 SDOperand N1 = N->getOperand(0);
5098 SDOperand N2 = N->getOperand(1);
5099 if (isGAPlusOffset(N1.Val, GA, Offset)) {
5100 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2);
5102 Offset += V->getSignExtended();
5105 } else if (isGAPlusOffset(N2.Val, GA, Offset)) {
5106 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1);
5108 Offset += V->getSignExtended();
5116 /// isConsecutiveLoad - Returns true if N is loading from an address of Base
5118 static bool isConsecutiveLoad(SDNode *N, SDNode *Base, int Dist, int Size,
5119 MachineFrameInfo *MFI) {
5120 if (N->getOperand(0).Val != Base->getOperand(0).Val)
5123 SDOperand Loc = N->getOperand(1);
5124 SDOperand BaseLoc = Base->getOperand(1);
5125 if (Loc.getOpcode() == ISD::FrameIndex) {
5126 if (BaseLoc.getOpcode() != ISD::FrameIndex)
5128 int FI = cast<FrameIndexSDNode>(Loc)->getIndex();
5129 int BFI = cast<FrameIndexSDNode>(BaseLoc)->getIndex();
5130 int FS = MFI->getObjectSize(FI);
5131 int BFS = MFI->getObjectSize(BFI);
5132 if (FS != BFS || FS != Size) return false;
5133 return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) + Dist*Size);
5135 GlobalValue *GV1 = NULL;
5136 GlobalValue *GV2 = NULL;
5137 int64_t Offset1 = 0;
5138 int64_t Offset2 = 0;
5139 bool isGA1 = isGAPlusOffset(Loc.Val, GV1, Offset1);
5140 bool isGA2 = isGAPlusOffset(BaseLoc.Val, GV2, Offset2);
5141 if (isGA1 && isGA2 && GV1 == GV2)
5142 return Offset1 == (Offset2 + Dist*Size);
5148 static bool isBaseAlignment16(SDNode *Base, MachineFrameInfo *MFI,
5149 const X86Subtarget *Subtarget) {
5152 if (isGAPlusOffset(Base, GV, Offset))
5153 return (GV->getAlignment() >= 16 && (Offset % 16) == 0);
5155 assert(Base->getOpcode() == ISD::FrameIndex && "Unexpected base node!");
5156 int BFI = cast<FrameIndexSDNode>(Base)->getIndex();
5158 // Fixed objects do not specify alignment, however the offsets are known.
5159 return ((Subtarget->getStackAlignment() % 16) == 0 &&
5160 (MFI->getObjectOffset(BFI) % 16) == 0);
5162 return MFI->getObjectAlignment(BFI) >= 16;
5168 /// PerformShuffleCombine - Combine a vector_shuffle that is equal to
5169 /// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load
5170 /// if the load addresses are consecutive, non-overlapping, and in the right
5172 static SDOperand PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
5173 const X86Subtarget *Subtarget) {
5174 MachineFunction &MF = DAG.getMachineFunction();
5175 MachineFrameInfo *MFI = MF.getFrameInfo();
5176 MVT::ValueType VT = N->getValueType(0);
5177 MVT::ValueType EVT = MVT::getVectorElementType(VT);
5178 SDOperand PermMask = N->getOperand(2);
5179 int NumElems = (int)PermMask.getNumOperands();
5180 SDNode *Base = NULL;
5181 for (int i = 0; i < NumElems; ++i) {
5182 SDOperand Idx = PermMask.getOperand(i);
5183 if (Idx.getOpcode() == ISD::UNDEF) {
5184 if (!Base) return SDOperand();
5187 getShuffleScalarElt(N, cast<ConstantSDNode>(Idx)->getValue(), DAG);
5188 if (!Arg.Val || !ISD::isNON_EXTLoad(Arg.Val))
5192 else if (!isConsecutiveLoad(Arg.Val, Base,
5193 i, MVT::getSizeInBits(EVT)/8,MFI))
5198 bool isAlign16 = isBaseAlignment16(Base->getOperand(1).Val, MFI, Subtarget);
5199 LoadSDNode *LD = cast<LoadSDNode>(Base);
5201 return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(), LD->getSrcValue(),
5202 LD->getSrcValueOffset(), LD->isVolatile());
5204 return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(), LD->getSrcValue(),
5205 LD->getSrcValueOffset(), LD->isVolatile(),
5206 LD->getAlignment());
5210 /// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes.
5211 static SDOperand PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
5212 const X86Subtarget *Subtarget) {
5213 SDOperand Cond = N->getOperand(0);
5215 // If we have SSE[12] support, try to form min/max nodes.
5216 if (Subtarget->hasSSE2() &&
5217 (N->getValueType(0) == MVT::f32 || N->getValueType(0) == MVT::f64)) {
5218 if (Cond.getOpcode() == ISD::SETCC) {
5219 // Get the LHS/RHS of the select.
5220 SDOperand LHS = N->getOperand(1);
5221 SDOperand RHS = N->getOperand(2);
5222 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
5224 unsigned Opcode = 0;
5225 if (LHS == Cond.getOperand(0) && RHS == Cond.getOperand(1)) {
5228 case ISD::SETOLE: // (X <= Y) ? X : Y -> min
5231 if (!UnsafeFPMath) break;
5233 case ISD::SETOLT: // (X olt/lt Y) ? X : Y -> min
5235 Opcode = X86ISD::FMIN;
5238 case ISD::SETOGT: // (X > Y) ? X : Y -> max
5241 if (!UnsafeFPMath) break;
5243 case ISD::SETUGE: // (X uge/ge Y) ? X : Y -> max
5245 Opcode = X86ISD::FMAX;
5248 } else if (LHS == Cond.getOperand(1) && RHS == Cond.getOperand(0)) {
5251 case ISD::SETOGT: // (X > Y) ? Y : X -> min
5254 if (!UnsafeFPMath) break;
5256 case ISD::SETUGE: // (X uge/ge Y) ? Y : X -> min
5258 Opcode = X86ISD::FMIN;
5261 case ISD::SETOLE: // (X <= Y) ? Y : X -> max
5264 if (!UnsafeFPMath) break;
5266 case ISD::SETOLT: // (X olt/lt Y) ? Y : X -> max
5268 Opcode = X86ISD::FMAX;
5274 return DAG.getNode(Opcode, N->getValueType(0), LHS, RHS);
5283 SDOperand X86TargetLowering::PerformDAGCombine(SDNode *N,
5284 DAGCombinerInfo &DCI) const {
5285 SelectionDAG &DAG = DCI.DAG;
5286 switch (N->getOpcode()) {
5288 case ISD::VECTOR_SHUFFLE:
5289 return PerformShuffleCombine(N, DAG, Subtarget);
5291 return PerformSELECTCombine(N, DAG, Subtarget);
5297 //===----------------------------------------------------------------------===//
5298 // X86 Inline Assembly Support
5299 //===----------------------------------------------------------------------===//
5301 /// getConstraintType - Given a constraint letter, return the type of
5302 /// constraint it is for this target.
5303 X86TargetLowering::ConstraintType
5304 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
5305 if (Constraint.size() == 1) {
5306 switch (Constraint[0]) {
5315 return C_RegisterClass;
5320 return TargetLowering::getConstraintType(Constraint);
5323 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
5324 /// vector. If it is invalid, don't add anything to Ops.
5325 void X86TargetLowering::LowerAsmOperandForConstraint(SDOperand Op,
5327 std::vector<SDOperand>&Ops,
5328 SelectionDAG &DAG) {
5329 SDOperand Result(0, 0);
5331 switch (Constraint) {
5334 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
5335 if (C->getValue() <= 31) {
5336 Result = DAG.getTargetConstant(C->getValue(), Op.getValueType());
5342 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
5343 if (C->getValue() <= 255) {
5344 Result = DAG.getTargetConstant(C->getValue(), Op.getValueType());
5350 // Literal immediates are always ok.
5351 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
5352 Result = DAG.getTargetConstant(CST->getValue(), Op.getValueType());
5356 // If we are in non-pic codegen mode, we allow the address of a global (with
5357 // an optional displacement) to be used with 'i'.
5358 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op);
5361 // Match either (GA) or (GA+C)
5363 Offset = GA->getOffset();
5364 } else if (Op.getOpcode() == ISD::ADD) {
5365 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
5366 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
5368 Offset = GA->getOffset()+C->getValue();
5370 C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
5371 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
5373 Offset = GA->getOffset()+C->getValue();
5380 // If addressing this global requires a load (e.g. in PIC mode), we can't
5382 if (Subtarget->GVRequiresExtraLoad(GA->getGlobal(), getTargetMachine(),
5386 Op = DAG.getTargetGlobalAddress(GA->getGlobal(), GA->getValueType(0),
5392 // Otherwise, not valid for this mode.
5398 Ops.push_back(Result);
5401 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
5404 std::vector<unsigned> X86TargetLowering::
5405 getRegClassForInlineAsmConstraint(const std::string &Constraint,
5406 MVT::ValueType VT) const {
5407 if (Constraint.size() == 1) {
5408 // FIXME: not handling fp-stack yet!
5409 switch (Constraint[0]) { // GCC X86 Constraint Letters
5410 default: break; // Unknown constraint letter
5411 case 'A': // EAX/EDX
5412 if (VT == MVT::i32 || VT == MVT::i64)
5413 return make_vector<unsigned>(X86::EAX, X86::EDX, 0);
5415 case 'q': // Q_REGS (GENERAL_REGS in 64-bit mode)
5418 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0);
5419 else if (VT == MVT::i16)
5420 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0);
5421 else if (VT == MVT::i8)
5422 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 0);
5427 return std::vector<unsigned>();
5430 std::pair<unsigned, const TargetRegisterClass*>
5431 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
5432 MVT::ValueType VT) const {
5433 // First, see if this is a constraint that directly corresponds to an LLVM
5435 if (Constraint.size() == 1) {
5436 // GCC Constraint Letters
5437 switch (Constraint[0]) {
5439 case 'r': // GENERAL_REGS
5440 case 'R': // LEGACY_REGS
5441 case 'l': // INDEX_REGS
5442 if (VT == MVT::i64 && Subtarget->is64Bit())
5443 return std::make_pair(0U, X86::GR64RegisterClass);
5445 return std::make_pair(0U, X86::GR32RegisterClass);
5446 else if (VT == MVT::i16)
5447 return std::make_pair(0U, X86::GR16RegisterClass);
5448 else if (VT == MVT::i8)
5449 return std::make_pair(0U, X86::GR8RegisterClass);
5451 case 'y': // MMX_REGS if MMX allowed.
5452 if (!Subtarget->hasMMX()) break;
5453 return std::make_pair(0U, X86::VR64RegisterClass);
5455 case 'Y': // SSE_REGS if SSE2 allowed
5456 if (!Subtarget->hasSSE2()) break;
5458 case 'x': // SSE_REGS if SSE1 allowed
5459 if (!Subtarget->hasSSE1()) break;
5463 // Scalar SSE types.
5466 return std::make_pair(0U, X86::FR32RegisterClass);
5469 return std::make_pair(0U, X86::FR64RegisterClass);
5477 return std::make_pair(0U, X86::VR128RegisterClass);
5483 // Use the default implementation in TargetLowering to convert the register
5484 // constraint into a member of a register class.
5485 std::pair<unsigned, const TargetRegisterClass*> Res;
5486 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
5488 // Not found as a standard register?
5489 if (Res.second == 0) {
5490 // GCC calls "st(0)" just plain "st".
5491 if (StringsEqualNoCase("{st}", Constraint)) {
5492 Res.first = X86::ST0;
5493 Res.second = X86::RFP80RegisterClass;
5499 // Otherwise, check to see if this is a register class of the wrong value
5500 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
5501 // turn into {ax},{dx}.
5502 if (Res.second->hasType(VT))
5503 return Res; // Correct type already, nothing to do.
5505 // All of the single-register GCC register classes map their values onto
5506 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
5507 // really want an 8-bit or 32-bit register, map to the appropriate register
5508 // class and return the appropriate register.
5509 if (Res.second != X86::GR16RegisterClass)
5512 if (VT == MVT::i8) {
5513 unsigned DestReg = 0;
5514 switch (Res.first) {
5516 case X86::AX: DestReg = X86::AL; break;
5517 case X86::DX: DestReg = X86::DL; break;
5518 case X86::CX: DestReg = X86::CL; break;
5519 case X86::BX: DestReg = X86::BL; break;
5522 Res.first = DestReg;
5523 Res.second = Res.second = X86::GR8RegisterClass;
5525 } else if (VT == MVT::i32) {
5526 unsigned DestReg = 0;
5527 switch (Res.first) {
5529 case X86::AX: DestReg = X86::EAX; break;
5530 case X86::DX: DestReg = X86::EDX; break;
5531 case X86::CX: DestReg = X86::ECX; break;
5532 case X86::BX: DestReg = X86::EBX; break;
5533 case X86::SI: DestReg = X86::ESI; break;
5534 case X86::DI: DestReg = X86::EDI; break;
5535 case X86::BP: DestReg = X86::EBP; break;
5536 case X86::SP: DestReg = X86::ESP; break;
5539 Res.first = DestReg;
5540 Res.second = Res.second = X86::GR32RegisterClass;
5542 } else if (VT == MVT::i64) {
5543 unsigned DestReg = 0;
5544 switch (Res.first) {
5546 case X86::AX: DestReg = X86::RAX; break;
5547 case X86::DX: DestReg = X86::RDX; break;
5548 case X86::CX: DestReg = X86::RCX; break;
5549 case X86::BX: DestReg = X86::RBX; break;
5550 case X86::SI: DestReg = X86::RSI; break;
5551 case X86::DI: DestReg = X86::RDI; break;
5552 case X86::BP: DestReg = X86::RBP; break;
5553 case X86::SP: DestReg = X86::RSP; break;
5556 Res.first = DestReg;
5557 Res.second = Res.second = X86::GR64RegisterClass;