1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
16 #include "X86ISelLowering.h"
18 #include "X86InstrBuilder.h"
19 #include "X86TargetMachine.h"
20 #include "X86TargetObjectFile.h"
21 #include "Utils/X86ShuffleDecode.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/GlobalAlias.h"
26 #include "llvm/GlobalVariable.h"
27 #include "llvm/Function.h"
28 #include "llvm/Instructions.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/LLVMContext.h"
31 #include "llvm/CodeGen/IntrinsicLowering.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/CodeGen/MachineFunction.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineJumpTableInfo.h"
36 #include "llvm/CodeGen/MachineModuleInfo.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/MC/MCAsmInfo.h"
39 #include "llvm/MC/MCContext.h"
40 #include "llvm/MC/MCExpr.h"
41 #include "llvm/MC/MCSymbol.h"
42 #include "llvm/ADT/SmallSet.h"
43 #include "llvm/ADT/Statistic.h"
44 #include "llvm/ADT/StringExtras.h"
45 #include "llvm/ADT/VariadicFunction.h"
46 #include "llvm/Support/CallSite.h"
47 #include "llvm/Support/Debug.h"
48 #include "llvm/Support/ErrorHandling.h"
49 #include "llvm/Support/MathExtras.h"
50 #include "llvm/Target/TargetOptions.h"
54 STATISTIC(NumTailCalls, "Number of tail calls");
56 // Forward declarations.
57 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
60 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
61 /// sets things up to match to an AVX VEXTRACTF128 instruction or a
62 /// simple subregister reference. Idx is an index in the 128 bits we
63 /// want. It need not be aligned to a 128-bit bounday. That makes
64 /// lowering EXTRACT_VECTOR_ELT operations easier.
65 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
66 SelectionDAG &DAG, DebugLoc dl) {
67 EVT VT = Vec.getValueType();
68 assert(VT.getSizeInBits() == 256 && "Unexpected vector size!");
69 EVT ElVT = VT.getVectorElementType();
70 int Factor = VT.getSizeInBits()/128;
71 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
72 VT.getVectorNumElements()/Factor);
74 // Extract from UNDEF is UNDEF.
75 if (Vec.getOpcode() == ISD::UNDEF)
76 return DAG.getUNDEF(ResultVT);
78 // Extract the relevant 128 bits. Generate an EXTRACT_SUBVECTOR
79 // we can match to VEXTRACTF128.
80 unsigned ElemsPerChunk = 128 / ElVT.getSizeInBits();
82 // This is the index of the first element of the 128-bit chunk
84 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / 128)
87 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
88 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
94 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
95 /// sets things up to match to an AVX VINSERTF128 instruction or a
96 /// simple superregister reference. Idx is an index in the 128 bits
97 /// we want. It need not be aligned to a 128-bit bounday. That makes
98 /// lowering INSERT_VECTOR_ELT operations easier.
99 static SDValue Insert128BitVector(SDValue Result, SDValue Vec,
100 unsigned IdxVal, SelectionDAG &DAG,
102 EVT VT = Vec.getValueType();
103 assert(VT.getSizeInBits() == 128 && "Unexpected vector size!");
105 EVT ElVT = VT.getVectorElementType();
106 EVT ResultVT = Result.getValueType();
108 // Insert the relevant 128 bits.
109 unsigned ElemsPerChunk = 128/ElVT.getSizeInBits();
111 // This is the index of the first element of the 128-bit chunk
113 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/128)
116 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
117 Result = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
122 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
123 /// instructions. This is used because creating CONCAT_VECTOR nodes of
124 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
125 /// large BUILD_VECTORS.
126 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
127 unsigned NumElems, SelectionDAG &DAG,
129 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
130 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
133 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
134 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
135 bool is64Bit = Subtarget->is64Bit();
137 if (Subtarget->isTargetEnvMacho()) {
139 return new X8664_MachoTargetObjectFile();
140 return new TargetLoweringObjectFileMachO();
143 if (Subtarget->isTargetELF())
144 return new TargetLoweringObjectFileELF();
145 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
146 return new TargetLoweringObjectFileCOFF();
147 llvm_unreachable("unknown subtarget type");
150 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
151 : TargetLowering(TM, createTLOF(TM)) {
152 Subtarget = &TM.getSubtarget<X86Subtarget>();
153 X86ScalarSSEf64 = Subtarget->hasSSE2();
154 X86ScalarSSEf32 = Subtarget->hasSSE1();
155 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
157 RegInfo = TM.getRegisterInfo();
158 TD = getTargetData();
160 // Set up the TargetLowering object.
161 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
163 // X86 is weird, it always uses i8 for shift amounts and setcc results.
164 setBooleanContents(ZeroOrOneBooleanContent);
165 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
166 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
168 // For 64-bit since we have so many registers use the ILP scheduler, for
169 // 32-bit code use the register pressure specific scheduling.
170 // For 32 bit Atom, use Hybrid (register pressure + latency) scheduling.
171 if (Subtarget->is64Bit())
172 setSchedulingPreference(Sched::ILP);
173 else if (Subtarget->isAtom())
174 setSchedulingPreference(Sched::Hybrid);
176 setSchedulingPreference(Sched::RegPressure);
177 setStackPointerRegisterToSaveRestore(X86StackPtr);
179 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) {
180 // Setup Windows compiler runtime calls.
181 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
182 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
183 setLibcallName(RTLIB::SREM_I64, "_allrem");
184 setLibcallName(RTLIB::UREM_I64, "_aullrem");
185 setLibcallName(RTLIB::MUL_I64, "_allmul");
186 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
187 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
188 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
189 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
190 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
192 // The _ftol2 runtime function has an unusual calling conv, which
193 // is modeled by a special pseudo-instruction.
194 setLibcallName(RTLIB::FPTOUINT_F64_I64, 0);
195 setLibcallName(RTLIB::FPTOUINT_F32_I64, 0);
196 setLibcallName(RTLIB::FPTOUINT_F64_I32, 0);
197 setLibcallName(RTLIB::FPTOUINT_F32_I32, 0);
200 if (Subtarget->isTargetDarwin()) {
201 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
202 setUseUnderscoreSetJmp(false);
203 setUseUnderscoreLongJmp(false);
204 } else if (Subtarget->isTargetMingw()) {
205 // MS runtime is weird: it exports _setjmp, but longjmp!
206 setUseUnderscoreSetJmp(true);
207 setUseUnderscoreLongJmp(false);
209 setUseUnderscoreSetJmp(true);
210 setUseUnderscoreLongJmp(true);
213 // Set up the register classes.
214 addRegisterClass(MVT::i8, &X86::GR8RegClass);
215 addRegisterClass(MVT::i16, &X86::GR16RegClass);
216 addRegisterClass(MVT::i32, &X86::GR32RegClass);
217 if (Subtarget->is64Bit())
218 addRegisterClass(MVT::i64, &X86::GR64RegClass);
220 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
222 // We don't accept any truncstore of integer registers.
223 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
224 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
225 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
226 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
227 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
228 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
230 // SETOEQ and SETUNE require checking two conditions.
231 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
232 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
233 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
234 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
235 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
236 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
238 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
240 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
241 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
242 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
244 if (Subtarget->is64Bit()) {
245 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
246 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
247 } else if (!TM.Options.UseSoftFloat) {
248 // We have an algorithm for SSE2->double, and we turn this into a
249 // 64-bit FILD followed by conditional FADD for other targets.
250 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
251 // We have an algorithm for SSE2, and we turn this into a 64-bit
252 // FILD for other targets.
253 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
256 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
258 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
259 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
261 if (!TM.Options.UseSoftFloat) {
262 // SSE has no i16 to fp conversion, only i32
263 if (X86ScalarSSEf32) {
264 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
265 // f32 and f64 cases are Legal, f80 case is not
266 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
268 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
269 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
272 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
273 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
276 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
277 // are Legal, f80 is custom lowered.
278 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
279 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
281 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
283 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
284 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
286 if (X86ScalarSSEf32) {
287 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
288 // f32 and f64 cases are Legal, f80 case is not
289 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
291 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
292 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
295 // Handle FP_TO_UINT by promoting the destination to a larger signed
297 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
298 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
299 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
301 if (Subtarget->is64Bit()) {
302 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
303 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
304 } else if (!TM.Options.UseSoftFloat) {
305 // Since AVX is a superset of SSE3, only check for SSE here.
306 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
307 // Expand FP_TO_UINT into a select.
308 // FIXME: We would like to use a Custom expander here eventually to do
309 // the optimal thing for SSE vs. the default expansion in the legalizer.
310 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
312 // With SSE3 we can use fisttpll to convert to a signed i64; without
313 // SSE, we're stuck with a fistpll.
314 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
317 if (isTargetFTOL()) {
318 // Use the _ftol2 runtime function, which has a pseudo-instruction
319 // to handle its weird calling convention.
320 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
323 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
324 if (!X86ScalarSSEf64) {
325 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
326 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
327 if (Subtarget->is64Bit()) {
328 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
329 // Without SSE, i64->f64 goes through memory.
330 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
334 // Scalar integer divide and remainder are lowered to use operations that
335 // produce two results, to match the available instructions. This exposes
336 // the two-result form to trivial CSE, which is able to combine x/y and x%y
337 // into a single instruction.
339 // Scalar integer multiply-high is also lowered to use two-result
340 // operations, to match the available instructions. However, plain multiply
341 // (low) operations are left as Legal, as there are single-result
342 // instructions for this in x86. Using the two-result multiply instructions
343 // when both high and low results are needed must be arranged by dagcombine.
344 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
346 setOperationAction(ISD::MULHS, VT, Expand);
347 setOperationAction(ISD::MULHU, VT, Expand);
348 setOperationAction(ISD::SDIV, VT, Expand);
349 setOperationAction(ISD::UDIV, VT, Expand);
350 setOperationAction(ISD::SREM, VT, Expand);
351 setOperationAction(ISD::UREM, VT, Expand);
353 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
354 setOperationAction(ISD::ADDC, VT, Custom);
355 setOperationAction(ISD::ADDE, VT, Custom);
356 setOperationAction(ISD::SUBC, VT, Custom);
357 setOperationAction(ISD::SUBE, VT, Custom);
360 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
361 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
362 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
363 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
364 if (Subtarget->is64Bit())
365 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
366 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
367 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
368 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
369 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
370 setOperationAction(ISD::FREM , MVT::f32 , Expand);
371 setOperationAction(ISD::FREM , MVT::f64 , Expand);
372 setOperationAction(ISD::FREM , MVT::f80 , Expand);
373 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
375 // Promote the i8 variants and force them on up to i32 which has a shorter
377 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
378 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
379 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
380 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
381 if (Subtarget->hasBMI()) {
382 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
383 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
384 if (Subtarget->is64Bit())
385 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
387 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
388 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
389 if (Subtarget->is64Bit())
390 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
393 if (Subtarget->hasLZCNT()) {
394 // When promoting the i8 variants, force them to i32 for a shorter
396 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
397 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
398 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
399 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
400 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
401 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
402 if (Subtarget->is64Bit())
403 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
405 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
406 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
407 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
408 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
409 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
410 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
411 if (Subtarget->is64Bit()) {
412 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
413 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
417 if (Subtarget->hasPOPCNT()) {
418 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
420 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
421 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
422 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
423 if (Subtarget->is64Bit())
424 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
427 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
428 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
430 // These should be promoted to a larger select which is supported.
431 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
432 // X86 wants to expand cmov itself.
433 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
434 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
435 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
436 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
437 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
438 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
439 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
440 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
441 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
442 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
443 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
444 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
445 if (Subtarget->is64Bit()) {
446 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
447 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
449 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
452 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
453 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
454 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
455 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
456 if (Subtarget->is64Bit())
457 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
458 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
459 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
460 if (Subtarget->is64Bit()) {
461 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
462 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
463 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
464 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
465 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
467 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
468 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
469 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
470 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
471 if (Subtarget->is64Bit()) {
472 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
473 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
474 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
477 if (Subtarget->hasSSE1())
478 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
480 setOperationAction(ISD::MEMBARRIER , MVT::Other, Custom);
481 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
483 // On X86 and X86-64, atomic operations are lowered to locked instructions.
484 // Locked instructions, in turn, have implicit fence semantics (all memory
485 // operations are flushed before issuing the locked instruction, and they
486 // are not buffered), so we can fold away the common pattern of
487 // fence-atomic-fence.
488 setShouldFoldAtomicFences(true);
490 // Expand certain atomics
491 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
493 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom);
494 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
495 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
498 if (!Subtarget->is64Bit()) {
499 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
500 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
501 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
502 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
503 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
504 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
505 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
506 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
509 if (Subtarget->hasCmpxchg16b()) {
510 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom);
513 // FIXME - use subtarget debug flags
514 if (!Subtarget->isTargetDarwin() &&
515 !Subtarget->isTargetELF() &&
516 !Subtarget->isTargetCygMing()) {
517 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
520 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
521 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
522 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
523 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
524 if (Subtarget->is64Bit()) {
525 setExceptionPointerRegister(X86::RAX);
526 setExceptionSelectorRegister(X86::RDX);
528 setExceptionPointerRegister(X86::EAX);
529 setExceptionSelectorRegister(X86::EDX);
531 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
532 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
534 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
535 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
537 setOperationAction(ISD::TRAP, MVT::Other, Legal);
539 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
540 setOperationAction(ISD::VASTART , MVT::Other, Custom);
541 setOperationAction(ISD::VAEND , MVT::Other, Expand);
542 if (Subtarget->is64Bit()) {
543 setOperationAction(ISD::VAARG , MVT::Other, Custom);
544 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
546 setOperationAction(ISD::VAARG , MVT::Other, Expand);
547 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
550 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
551 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
553 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
554 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
555 MVT::i64 : MVT::i32, Custom);
556 else if (TM.Options.EnableSegmentedStacks)
557 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
558 MVT::i64 : MVT::i32, Custom);
560 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
561 MVT::i64 : MVT::i32, Expand);
563 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
564 // f32 and f64 use SSE.
565 // Set up the FP register classes.
566 addRegisterClass(MVT::f32, &X86::FR32RegClass);
567 addRegisterClass(MVT::f64, &X86::FR64RegClass);
569 // Use ANDPD to simulate FABS.
570 setOperationAction(ISD::FABS , MVT::f64, Custom);
571 setOperationAction(ISD::FABS , MVT::f32, Custom);
573 // Use XORP to simulate FNEG.
574 setOperationAction(ISD::FNEG , MVT::f64, Custom);
575 setOperationAction(ISD::FNEG , MVT::f32, Custom);
577 // Use ANDPD and ORPD to simulate FCOPYSIGN.
578 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
579 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
581 // Lower this to FGETSIGNx86 plus an AND.
582 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
583 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
585 // We don't support sin/cos/fmod
586 setOperationAction(ISD::FSIN , MVT::f64, Expand);
587 setOperationAction(ISD::FCOS , MVT::f64, Expand);
588 setOperationAction(ISD::FSIN , MVT::f32, Expand);
589 setOperationAction(ISD::FCOS , MVT::f32, Expand);
591 // Expand FP immediates into loads from the stack, except for the special
593 addLegalFPImmediate(APFloat(+0.0)); // xorpd
594 addLegalFPImmediate(APFloat(+0.0f)); // xorps
595 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
596 // Use SSE for f32, x87 for f64.
597 // Set up the FP register classes.
598 addRegisterClass(MVT::f32, &X86::FR32RegClass);
599 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
601 // Use ANDPS to simulate FABS.
602 setOperationAction(ISD::FABS , MVT::f32, Custom);
604 // Use XORP to simulate FNEG.
605 setOperationAction(ISD::FNEG , MVT::f32, Custom);
607 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
609 // Use ANDPS and ORPS to simulate FCOPYSIGN.
610 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
611 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
613 // We don't support sin/cos/fmod
614 setOperationAction(ISD::FSIN , MVT::f32, Expand);
615 setOperationAction(ISD::FCOS , MVT::f32, Expand);
617 // Special cases we handle for FP constants.
618 addLegalFPImmediate(APFloat(+0.0f)); // xorps
619 addLegalFPImmediate(APFloat(+0.0)); // FLD0
620 addLegalFPImmediate(APFloat(+1.0)); // FLD1
621 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
622 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
624 if (!TM.Options.UnsafeFPMath) {
625 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
626 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
628 } else if (!TM.Options.UseSoftFloat) {
629 // f32 and f64 in x87.
630 // Set up the FP register classes.
631 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
632 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
634 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
635 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
636 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
637 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
639 if (!TM.Options.UnsafeFPMath) {
640 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
641 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
643 addLegalFPImmediate(APFloat(+0.0)); // FLD0
644 addLegalFPImmediate(APFloat(+1.0)); // FLD1
645 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
646 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
647 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
648 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
649 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
650 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
653 // We don't support FMA.
654 setOperationAction(ISD::FMA, MVT::f64, Expand);
655 setOperationAction(ISD::FMA, MVT::f32, Expand);
657 // Long double always uses X87.
658 if (!TM.Options.UseSoftFloat) {
659 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
660 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
661 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
663 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
664 addLegalFPImmediate(TmpFlt); // FLD0
666 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
669 APFloat TmpFlt2(+1.0);
670 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
672 addLegalFPImmediate(TmpFlt2); // FLD1
673 TmpFlt2.changeSign();
674 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
677 if (!TM.Options.UnsafeFPMath) {
678 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
679 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
682 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
683 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
684 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
685 setOperationAction(ISD::FRINT, MVT::f80, Expand);
686 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
687 setOperationAction(ISD::FMA, MVT::f80, Expand);
690 // Always use a library call for pow.
691 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
692 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
693 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
695 setOperationAction(ISD::FLOG, MVT::f80, Expand);
696 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
697 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
698 setOperationAction(ISD::FEXP, MVT::f80, Expand);
699 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
701 // First set operation action for all vector types to either promote
702 // (for widening) or expand (for scalarization). Then we will selectively
703 // turn on ones that can be effectively codegen'd.
704 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
705 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
706 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
707 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
708 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
709 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
710 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
711 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
712 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
713 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
714 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
715 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
716 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
717 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
718 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
719 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
720 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
721 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
722 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
723 setOperationAction(ISD::INSERT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
724 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
725 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
726 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
727 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
728 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
729 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
730 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
731 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
732 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
733 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
734 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
735 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
736 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
737 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
738 setOperationAction(ISD::CTTZ_ZERO_UNDEF, (MVT::SimpleValueType)VT, Expand);
739 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
740 setOperationAction(ISD::CTLZ_ZERO_UNDEF, (MVT::SimpleValueType)VT, Expand);
741 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
742 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
743 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
744 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
745 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
746 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
747 setOperationAction(ISD::SETCC, (MVT::SimpleValueType)VT, Expand);
748 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
749 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
750 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
751 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand);
752 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand);
753 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand);
754 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand);
755 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
756 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
757 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand);
758 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand);
759 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand);
760 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand);
761 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand);
762 setOperationAction(ISD::VSELECT, (MVT::SimpleValueType)VT, Expand);
763 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
764 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
765 setTruncStoreAction((MVT::SimpleValueType)VT,
766 (MVT::SimpleValueType)InnerVT, Expand);
767 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
768 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
769 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
772 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
773 // with -msoft-float, disable use of MMX as well.
774 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
775 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
776 // No operations on x86mmx supported, everything uses intrinsics.
779 // MMX-sized vectors (other than x86mmx) are expected to be expanded
780 // into smaller operations.
781 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
782 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
783 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
784 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
785 setOperationAction(ISD::AND, MVT::v8i8, Expand);
786 setOperationAction(ISD::AND, MVT::v4i16, Expand);
787 setOperationAction(ISD::AND, MVT::v2i32, Expand);
788 setOperationAction(ISD::AND, MVT::v1i64, Expand);
789 setOperationAction(ISD::OR, MVT::v8i8, Expand);
790 setOperationAction(ISD::OR, MVT::v4i16, Expand);
791 setOperationAction(ISD::OR, MVT::v2i32, Expand);
792 setOperationAction(ISD::OR, MVT::v1i64, Expand);
793 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
794 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
795 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
796 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
797 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
798 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
799 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
800 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
801 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
802 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
803 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
804 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
805 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
806 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
807 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
808 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
809 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
811 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
812 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
814 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
815 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
816 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
817 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
818 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
819 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
820 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
821 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
822 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
823 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
824 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
825 setOperationAction(ISD::SETCC, MVT::v4f32, Custom);
828 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
829 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
831 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
832 // registers cannot be used even for integer operations.
833 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
834 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
835 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
836 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
838 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
839 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
840 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
841 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
842 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
843 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
844 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
845 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
846 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
847 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
848 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
849 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
850 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
851 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
852 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
853 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
855 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
856 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
857 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
858 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
860 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
861 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
862 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
863 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
864 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
866 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Custom);
867 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Custom);
868 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom);
869 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom);
870 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
872 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
873 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) {
874 EVT VT = (MVT::SimpleValueType)i;
875 // Do not attempt to custom lower non-power-of-2 vectors
876 if (!isPowerOf2_32(VT.getVectorNumElements()))
878 // Do not attempt to custom lower non-128-bit vectors
879 if (!VT.is128BitVector())
881 setOperationAction(ISD::BUILD_VECTOR,
882 VT.getSimpleVT().SimpleTy, Custom);
883 setOperationAction(ISD::VECTOR_SHUFFLE,
884 VT.getSimpleVT().SimpleTy, Custom);
885 setOperationAction(ISD::EXTRACT_VECTOR_ELT,
886 VT.getSimpleVT().SimpleTy, Custom);
889 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
890 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
891 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
892 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
893 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
894 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
896 if (Subtarget->is64Bit()) {
897 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
898 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
901 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
902 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) {
903 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
906 // Do not attempt to promote non-128-bit vectors
907 if (!VT.is128BitVector())
910 setOperationAction(ISD::AND, SVT, Promote);
911 AddPromotedToType (ISD::AND, SVT, MVT::v2i64);
912 setOperationAction(ISD::OR, SVT, Promote);
913 AddPromotedToType (ISD::OR, SVT, MVT::v2i64);
914 setOperationAction(ISD::XOR, SVT, Promote);
915 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64);
916 setOperationAction(ISD::LOAD, SVT, Promote);
917 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64);
918 setOperationAction(ISD::SELECT, SVT, Promote);
919 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64);
922 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
924 // Custom lower v2i64 and v2f64 selects.
925 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
926 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
927 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
928 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
930 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
931 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
934 if (Subtarget->hasSSE41()) {
935 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
936 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
937 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
938 setOperationAction(ISD::FRINT, MVT::f32, Legal);
939 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
940 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
941 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
942 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
943 setOperationAction(ISD::FRINT, MVT::f64, Legal);
944 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
946 // FIXME: Do we need to handle scalar-to-vector here?
947 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
949 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
950 setOperationAction(ISD::VSELECT, MVT::v2i64, Legal);
951 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
952 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
953 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
955 // i8 and i16 vectors are custom , because the source register and source
956 // source memory operand types are not the same width. f32 vectors are
957 // custom since the immediate controlling the insert encodes additional
959 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
960 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
961 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
962 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
964 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
965 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
966 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
967 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
969 // FIXME: these should be Legal but thats only for the case where
970 // the index is constant. For now custom expand to deal with that.
971 if (Subtarget->is64Bit()) {
972 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
973 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
977 if (Subtarget->hasSSE2()) {
978 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
979 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
981 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
982 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
984 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
985 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
987 if (Subtarget->hasAVX2()) {
988 setOperationAction(ISD::SRL, MVT::v2i64, Legal);
989 setOperationAction(ISD::SRL, MVT::v4i32, Legal);
991 setOperationAction(ISD::SHL, MVT::v2i64, Legal);
992 setOperationAction(ISD::SHL, MVT::v4i32, Legal);
994 setOperationAction(ISD::SRA, MVT::v4i32, Legal);
996 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
997 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
999 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1000 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1002 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1006 if (Subtarget->hasSSE42())
1007 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
1009 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX()) {
1010 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1011 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1012 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1013 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1014 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1015 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1017 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1018 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1019 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1021 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1022 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1023 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1024 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1025 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1026 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1028 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1029 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1030 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1031 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1032 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1033 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1035 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1036 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1037 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1039 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f64, Custom);
1040 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i64, Custom);
1041 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom);
1042 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom);
1043 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i8, Custom);
1044 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i16, Custom);
1046 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1047 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1049 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1050 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1052 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1053 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1055 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1056 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1057 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1058 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1060 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1061 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1062 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1064 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal);
1065 setOperationAction(ISD::VSELECT, MVT::v4i64, Legal);
1066 setOperationAction(ISD::VSELECT, MVT::v8i32, Legal);
1067 setOperationAction(ISD::VSELECT, MVT::v8f32, Legal);
1069 if (Subtarget->hasAVX2()) {
1070 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1071 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1072 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1073 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1075 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1076 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1077 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1078 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1080 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1081 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1082 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1083 // Don't lower v32i8 because there is no 128-bit byte mul
1085 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1087 setOperationAction(ISD::SRL, MVT::v4i64, Legal);
1088 setOperationAction(ISD::SRL, MVT::v8i32, Legal);
1090 setOperationAction(ISD::SHL, MVT::v4i64, Legal);
1091 setOperationAction(ISD::SHL, MVT::v8i32, Legal);
1093 setOperationAction(ISD::SRA, MVT::v8i32, Legal);
1095 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1096 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1097 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1098 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1100 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1101 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1102 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1103 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1105 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1106 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1107 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1108 // Don't lower v32i8 because there is no 128-bit byte mul
1110 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1111 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1113 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1114 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1116 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1119 // Custom lower several nodes for 256-bit types.
1120 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
1121 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
1122 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
1125 // Extract subvector is special because the value type
1126 // (result) is 128-bit but the source is 256-bit wide.
1127 if (VT.is128BitVector())
1128 setOperationAction(ISD::EXTRACT_SUBVECTOR, SVT, Custom);
1130 // Do not attempt to custom lower other non-256-bit vectors
1131 if (!VT.is256BitVector())
1134 setOperationAction(ISD::BUILD_VECTOR, SVT, Custom);
1135 setOperationAction(ISD::VECTOR_SHUFFLE, SVT, Custom);
1136 setOperationAction(ISD::INSERT_VECTOR_ELT, SVT, Custom);
1137 setOperationAction(ISD::EXTRACT_VECTOR_ELT, SVT, Custom);
1138 setOperationAction(ISD::SCALAR_TO_VECTOR, SVT, Custom);
1139 setOperationAction(ISD::INSERT_SUBVECTOR, SVT, Custom);
1142 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1143 for (unsigned i = (unsigned)MVT::v32i8; i != (unsigned)MVT::v4i64; ++i) {
1144 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
1147 // Do not attempt to promote non-256-bit vectors
1148 if (!VT.is256BitVector())
1151 setOperationAction(ISD::AND, SVT, Promote);
1152 AddPromotedToType (ISD::AND, SVT, MVT::v4i64);
1153 setOperationAction(ISD::OR, SVT, Promote);
1154 AddPromotedToType (ISD::OR, SVT, MVT::v4i64);
1155 setOperationAction(ISD::XOR, SVT, Promote);
1156 AddPromotedToType (ISD::XOR, SVT, MVT::v4i64);
1157 setOperationAction(ISD::LOAD, SVT, Promote);
1158 AddPromotedToType (ISD::LOAD, SVT, MVT::v4i64);
1159 setOperationAction(ISD::SELECT, SVT, Promote);
1160 AddPromotedToType (ISD::SELECT, SVT, MVT::v4i64);
1164 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1165 // of this type with custom code.
1166 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
1167 VT != (unsigned)MVT::LAST_VECTOR_VALUETYPE; VT++) {
1168 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1172 // We want to custom lower some of our intrinsics.
1173 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1176 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1177 // handle type legalization for these operations here.
1179 // FIXME: We really should do custom legalization for addition and
1180 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1181 // than generic legalization for 64-bit multiplication-with-overflow, though.
1182 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1183 // Add/Sub/Mul with overflow operations are custom lowered.
1185 setOperationAction(ISD::SADDO, VT, Custom);
1186 setOperationAction(ISD::UADDO, VT, Custom);
1187 setOperationAction(ISD::SSUBO, VT, Custom);
1188 setOperationAction(ISD::USUBO, VT, Custom);
1189 setOperationAction(ISD::SMULO, VT, Custom);
1190 setOperationAction(ISD::UMULO, VT, Custom);
1193 // There are no 8-bit 3-address imul/mul instructions
1194 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1195 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1197 if (!Subtarget->is64Bit()) {
1198 // These libcalls are not available in 32-bit.
1199 setLibcallName(RTLIB::SHL_I128, 0);
1200 setLibcallName(RTLIB::SRL_I128, 0);
1201 setLibcallName(RTLIB::SRA_I128, 0);
1204 // We have target-specific dag combine patterns for the following nodes:
1205 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1206 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1207 setTargetDAGCombine(ISD::VSELECT);
1208 setTargetDAGCombine(ISD::SELECT);
1209 setTargetDAGCombine(ISD::SHL);
1210 setTargetDAGCombine(ISD::SRA);
1211 setTargetDAGCombine(ISD::SRL);
1212 setTargetDAGCombine(ISD::OR);
1213 setTargetDAGCombine(ISD::AND);
1214 setTargetDAGCombine(ISD::ADD);
1215 setTargetDAGCombine(ISD::FADD);
1216 setTargetDAGCombine(ISD::FSUB);
1217 setTargetDAGCombine(ISD::SUB);
1218 setTargetDAGCombine(ISD::LOAD);
1219 setTargetDAGCombine(ISD::STORE);
1220 setTargetDAGCombine(ISD::ZERO_EXTEND);
1221 setTargetDAGCombine(ISD::ANY_EXTEND);
1222 setTargetDAGCombine(ISD::SIGN_EXTEND);
1223 setTargetDAGCombine(ISD::TRUNCATE);
1224 setTargetDAGCombine(ISD::UINT_TO_FP);
1225 setTargetDAGCombine(ISD::SINT_TO_FP);
1226 setTargetDAGCombine(ISD::FP_TO_SINT);
1227 if (Subtarget->is64Bit())
1228 setTargetDAGCombine(ISD::MUL);
1229 if (Subtarget->hasBMI())
1230 setTargetDAGCombine(ISD::XOR);
1232 computeRegisterProperties();
1234 // On Darwin, -Os means optimize for size without hurting performance,
1235 // do not reduce the limit.
1236 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1237 maxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1238 maxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1239 maxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1240 maxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1241 maxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1242 setPrefLoopAlignment(4); // 2^4 bytes.
1243 benefitFromCodePlacementOpt = true;
1245 setPrefFunctionAlignment(4); // 2^4 bytes.
1249 EVT X86TargetLowering::getSetCCResultType(EVT VT) const {
1250 if (!VT.isVector()) return MVT::i8;
1251 return VT.changeVectorElementTypeToInteger();
1255 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1256 /// the desired ByVal argument alignment.
1257 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1260 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1261 if (VTy->getBitWidth() == 128)
1263 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1264 unsigned EltAlign = 0;
1265 getMaxByValAlign(ATy->getElementType(), EltAlign);
1266 if (EltAlign > MaxAlign)
1267 MaxAlign = EltAlign;
1268 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1269 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1270 unsigned EltAlign = 0;
1271 getMaxByValAlign(STy->getElementType(i), EltAlign);
1272 if (EltAlign > MaxAlign)
1273 MaxAlign = EltAlign;
1280 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1281 /// function arguments in the caller parameter area. For X86, aggregates
1282 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1283 /// are at 4-byte boundaries.
1284 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1285 if (Subtarget->is64Bit()) {
1286 // Max of 8 and alignment of type.
1287 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1294 if (Subtarget->hasSSE1())
1295 getMaxByValAlign(Ty, Align);
1299 /// getOptimalMemOpType - Returns the target specific optimal type for load
1300 /// and store operations as a result of memset, memcpy, and memmove
1301 /// lowering. If DstAlign is zero that means it's safe to destination
1302 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1303 /// means there isn't a need to check it against alignment requirement,
1304 /// probably because the source does not need to be loaded. If
1305 /// 'IsZeroVal' is true, that means it's safe to return a
1306 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
1307 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
1308 /// constant so it does not need to be loaded.
1309 /// It returns EVT::Other if the type should be determined using generic
1310 /// target-independent logic.
1312 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1313 unsigned DstAlign, unsigned SrcAlign,
1316 MachineFunction &MF) const {
1317 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like
1318 // linux. This is because the stack realignment code can't handle certain
1319 // cases like PR2962. This should be removed when PR2962 is fixed.
1320 const Function *F = MF.getFunction();
1322 !F->hasFnAttr(Attribute::NoImplicitFloat)) {
1324 (Subtarget->isUnalignedMemAccessFast() ||
1325 ((DstAlign == 0 || DstAlign >= 16) &&
1326 (SrcAlign == 0 || SrcAlign >= 16))) &&
1327 Subtarget->getStackAlignment() >= 16) {
1328 if (Subtarget->getStackAlignment() >= 32) {
1329 if (Subtarget->hasAVX2())
1331 if (Subtarget->hasAVX())
1334 if (Subtarget->hasSSE2())
1336 if (Subtarget->hasSSE1())
1338 } else if (!MemcpyStrSrc && Size >= 8 &&
1339 !Subtarget->is64Bit() &&
1340 Subtarget->getStackAlignment() >= 8 &&
1341 Subtarget->hasSSE2()) {
1342 // Do not use f64 to lower memcpy if source is string constant. It's
1343 // better to use i32 to avoid the loads.
1347 if (Subtarget->is64Bit() && Size >= 8)
1352 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1353 /// current function. The returned value is a member of the
1354 /// MachineJumpTableInfo::JTEntryKind enum.
1355 unsigned X86TargetLowering::getJumpTableEncoding() const {
1356 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1358 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1359 Subtarget->isPICStyleGOT())
1360 return MachineJumpTableInfo::EK_Custom32;
1362 // Otherwise, use the normal jump table encoding heuristics.
1363 return TargetLowering::getJumpTableEncoding();
1367 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1368 const MachineBasicBlock *MBB,
1369 unsigned uid,MCContext &Ctx) const{
1370 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1371 Subtarget->isPICStyleGOT());
1372 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1374 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1375 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1378 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1380 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1381 SelectionDAG &DAG) const {
1382 if (!Subtarget->is64Bit())
1383 // This doesn't have DebugLoc associated with it, but is not really the
1384 // same as a Register.
1385 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy());
1389 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1390 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1392 const MCExpr *X86TargetLowering::
1393 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1394 MCContext &Ctx) const {
1395 // X86-64 uses RIP relative addressing based on the jump table label.
1396 if (Subtarget->isPICStyleRIPRel())
1397 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1399 // Otherwise, the reference is relative to the PIC base.
1400 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1403 // FIXME: Why this routine is here? Move to RegInfo!
1404 std::pair<const TargetRegisterClass*, uint8_t>
1405 X86TargetLowering::findRepresentativeClass(EVT VT) const{
1406 const TargetRegisterClass *RRC = 0;
1408 switch (VT.getSimpleVT().SimpleTy) {
1410 return TargetLowering::findRepresentativeClass(VT);
1411 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1412 RRC = Subtarget->is64Bit() ?
1413 (const TargetRegisterClass*)&X86::GR64RegClass :
1414 (const TargetRegisterClass*)&X86::GR32RegClass;
1417 RRC = &X86::VR64RegClass;
1419 case MVT::f32: case MVT::f64:
1420 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1421 case MVT::v4f32: case MVT::v2f64:
1422 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1424 RRC = &X86::VR128RegClass;
1427 return std::make_pair(RRC, Cost);
1430 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1431 unsigned &Offset) const {
1432 if (!Subtarget->isTargetLinux())
1435 if (Subtarget->is64Bit()) {
1436 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1438 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1451 //===----------------------------------------------------------------------===//
1452 // Return Value Calling Convention Implementation
1453 //===----------------------------------------------------------------------===//
1455 #include "X86GenCallingConv.inc"
1458 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1459 MachineFunction &MF, bool isVarArg,
1460 const SmallVectorImpl<ISD::OutputArg> &Outs,
1461 LLVMContext &Context) const {
1462 SmallVector<CCValAssign, 16> RVLocs;
1463 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1465 return CCInfo.CheckReturn(Outs, RetCC_X86);
1469 X86TargetLowering::LowerReturn(SDValue Chain,
1470 CallingConv::ID CallConv, bool isVarArg,
1471 const SmallVectorImpl<ISD::OutputArg> &Outs,
1472 const SmallVectorImpl<SDValue> &OutVals,
1473 DebugLoc dl, SelectionDAG &DAG) const {
1474 MachineFunction &MF = DAG.getMachineFunction();
1475 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1477 SmallVector<CCValAssign, 16> RVLocs;
1478 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1479 RVLocs, *DAG.getContext());
1480 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1482 // Add the regs to the liveout set for the function.
1483 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
1484 for (unsigned i = 0; i != RVLocs.size(); ++i)
1485 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg()))
1486 MRI.addLiveOut(RVLocs[i].getLocReg());
1490 SmallVector<SDValue, 6> RetOps;
1491 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1492 // Operand #1 = Bytes To Pop
1493 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1496 // Copy the result values into the output registers.
1497 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1498 CCValAssign &VA = RVLocs[i];
1499 assert(VA.isRegLoc() && "Can only return in registers!");
1500 SDValue ValToCopy = OutVals[i];
1501 EVT ValVT = ValToCopy.getValueType();
1503 // If this is x86-64, and we disabled SSE, we can't return FP values,
1504 // or SSE or MMX vectors.
1505 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1506 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1507 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
1508 report_fatal_error("SSE register return with SSE disabled");
1510 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1511 // llvm-gcc has never done it right and no one has noticed, so this
1512 // should be OK for now.
1513 if (ValVT == MVT::f64 &&
1514 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
1515 report_fatal_error("SSE2 register return with SSE2 disabled");
1517 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1518 // the RET instruction and handled by the FP Stackifier.
1519 if (VA.getLocReg() == X86::ST0 ||
1520 VA.getLocReg() == X86::ST1) {
1521 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1522 // change the value to the FP stack register class.
1523 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1524 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1525 RetOps.push_back(ValToCopy);
1526 // Don't emit a copytoreg.
1530 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1531 // which is returned in RAX / RDX.
1532 if (Subtarget->is64Bit()) {
1533 if (ValVT == MVT::x86mmx) {
1534 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1535 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1536 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1538 // If we don't have SSE2 available, convert to v4f32 so the generated
1539 // register is legal.
1540 if (!Subtarget->hasSSE2())
1541 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1546 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1547 Flag = Chain.getValue(1);
1550 // The x86-64 ABI for returning structs by value requires that we copy
1551 // the sret argument into %rax for the return. We saved the argument into
1552 // a virtual register in the entry block, so now we copy the value out
1554 if (Subtarget->is64Bit() &&
1555 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1556 MachineFunction &MF = DAG.getMachineFunction();
1557 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1558 unsigned Reg = FuncInfo->getSRetReturnReg();
1560 "SRetReturnReg should have been set in LowerFormalArguments().");
1561 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1563 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag);
1564 Flag = Chain.getValue(1);
1566 // RAX now acts like a return value.
1567 MRI.addLiveOut(X86::RAX);
1570 RetOps[0] = Chain; // Update chain.
1572 // Add the flag if we have it.
1574 RetOps.push_back(Flag);
1576 return DAG.getNode(X86ISD::RET_FLAG, dl,
1577 MVT::Other, &RetOps[0], RetOps.size());
1580 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
1581 if (N->getNumValues() != 1)
1583 if (!N->hasNUsesOfValue(1, 0))
1586 SDValue TCChain = Chain;
1587 SDNode *Copy = *N->use_begin();
1588 if (Copy->getOpcode() == ISD::CopyToReg) {
1589 // If the copy has a glue operand, we conservatively assume it isn't safe to
1590 // perform a tail call.
1591 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
1593 TCChain = Copy->getOperand(0);
1594 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
1597 bool HasRet = false;
1598 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1600 if (UI->getOpcode() != X86ISD::RET_FLAG)
1613 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
1614 ISD::NodeType ExtendKind) const {
1616 // TODO: Is this also valid on 32-bit?
1617 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
1618 ReturnMVT = MVT::i8;
1620 ReturnMVT = MVT::i32;
1622 EVT MinVT = getRegisterType(Context, ReturnMVT);
1623 return VT.bitsLT(MinVT) ? MinVT : VT;
1626 /// LowerCallResult - Lower the result values of a call into the
1627 /// appropriate copies out of appropriate physical registers.
1630 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1631 CallingConv::ID CallConv, bool isVarArg,
1632 const SmallVectorImpl<ISD::InputArg> &Ins,
1633 DebugLoc dl, SelectionDAG &DAG,
1634 SmallVectorImpl<SDValue> &InVals) const {
1636 // Assign locations to each value returned by this call.
1637 SmallVector<CCValAssign, 16> RVLocs;
1638 bool Is64Bit = Subtarget->is64Bit();
1639 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1640 getTargetMachine(), RVLocs, *DAG.getContext());
1641 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1643 // Copy all of the result registers out of their specified physreg.
1644 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1645 CCValAssign &VA = RVLocs[i];
1646 EVT CopyVT = VA.getValVT();
1648 // If this is x86-64, and we disabled SSE, we can't return FP values
1649 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1650 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
1651 report_fatal_error("SSE register return with SSE disabled");
1656 // If this is a call to a function that returns an fp value on the floating
1657 // point stack, we must guarantee the the value is popped from the stack, so
1658 // a CopyFromReg is not good enough - the copy instruction may be eliminated
1659 // if the return value is not used. We use the FpPOP_RETVAL instruction
1661 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {
1662 // If we prefer to use the value in xmm registers, copy it out as f80 and
1663 // use a truncate to move it from fp stack reg to xmm reg.
1664 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
1665 SDValue Ops[] = { Chain, InFlag };
1666 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT,
1667 MVT::Other, MVT::Glue, Ops, 2), 1);
1668 Val = Chain.getValue(0);
1670 // Round the f80 to the right size, which also moves it to the appropriate
1672 if (CopyVT != VA.getValVT())
1673 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1674 // This truncation won't change the value.
1675 DAG.getIntPtrConstant(1));
1677 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1678 CopyVT, InFlag).getValue(1);
1679 Val = Chain.getValue(0);
1681 InFlag = Chain.getValue(2);
1682 InVals.push_back(Val);
1689 //===----------------------------------------------------------------------===//
1690 // C & StdCall & Fast Calling Convention implementation
1691 //===----------------------------------------------------------------------===//
1692 // StdCall calling convention seems to be standard for many Windows' API
1693 // routines and around. It differs from C calling convention just a little:
1694 // callee should clean up the stack, not caller. Symbols should be also
1695 // decorated in some fancy way :) It doesn't support any vector arguments.
1696 // For info on fast calling convention see Fast Calling Convention (tail call)
1697 // implementation LowerX86_32FastCCCallTo.
1699 /// CallIsStructReturn - Determines whether a call uses struct return
1701 static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
1705 return Outs[0].Flags.isSRet();
1708 /// ArgsAreStructReturn - Determines whether a function uses struct
1709 /// return semantics.
1711 ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
1715 return Ins[0].Flags.isSRet();
1718 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1719 /// by "Src" to address "Dst" with size and alignment information specified by
1720 /// the specific parameter attribute. The copy will be passed as a byval
1721 /// function parameter.
1723 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1724 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1726 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1728 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1729 /*isVolatile*/false, /*AlwaysInline=*/true,
1730 MachinePointerInfo(), MachinePointerInfo());
1733 /// IsTailCallConvention - Return true if the calling convention is one that
1734 /// supports tail call optimization.
1735 static bool IsTailCallConvention(CallingConv::ID CC) {
1736 return (CC == CallingConv::Fast || CC == CallingConv::GHC);
1739 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
1740 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
1744 CallingConv::ID CalleeCC = CS.getCallingConv();
1745 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C)
1751 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
1752 /// a tailcall target by changing its ABI.
1753 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
1754 bool GuaranteedTailCallOpt) {
1755 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
1759 X86TargetLowering::LowerMemArgument(SDValue Chain,
1760 CallingConv::ID CallConv,
1761 const SmallVectorImpl<ISD::InputArg> &Ins,
1762 DebugLoc dl, SelectionDAG &DAG,
1763 const CCValAssign &VA,
1764 MachineFrameInfo *MFI,
1766 // Create the nodes corresponding to a load from this parameter slot.
1767 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1768 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv,
1769 getTargetMachine().Options.GuaranteedTailCallOpt);
1770 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1773 // If value is passed by pointer we have address passed instead of the value
1775 if (VA.getLocInfo() == CCValAssign::Indirect)
1776 ValVT = VA.getLocVT();
1778 ValVT = VA.getValVT();
1780 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1781 // changed with more analysis.
1782 // In case of tail call optimization mark all arguments mutable. Since they
1783 // could be overwritten by lowering of arguments in case of a tail call.
1784 if (Flags.isByVal()) {
1785 unsigned Bytes = Flags.getByValSize();
1786 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
1787 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
1788 return DAG.getFrameIndex(FI, getPointerTy());
1790 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
1791 VA.getLocMemOffset(), isImmutable);
1792 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1793 return DAG.getLoad(ValVT, dl, Chain, FIN,
1794 MachinePointerInfo::getFixedStack(FI),
1795 false, false, false, 0);
1800 X86TargetLowering::LowerFormalArguments(SDValue Chain,
1801 CallingConv::ID CallConv,
1803 const SmallVectorImpl<ISD::InputArg> &Ins,
1806 SmallVectorImpl<SDValue> &InVals)
1808 MachineFunction &MF = DAG.getMachineFunction();
1809 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1811 const Function* Fn = MF.getFunction();
1812 if (Fn->hasExternalLinkage() &&
1813 Subtarget->isTargetCygMing() &&
1814 Fn->getName() == "main")
1815 FuncInfo->setForceFramePointer(true);
1817 MachineFrameInfo *MFI = MF.getFrameInfo();
1818 bool Is64Bit = Subtarget->is64Bit();
1819 bool IsWindows = Subtarget->isTargetWindows();
1820 bool IsWin64 = Subtarget->isTargetWin64();
1822 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
1823 "Var args not supported with calling convention fastcc or ghc");
1825 // Assign locations to all of the incoming arguments.
1826 SmallVector<CCValAssign, 16> ArgLocs;
1827 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1828 ArgLocs, *DAG.getContext());
1830 // Allocate shadow area for Win64
1832 CCInfo.AllocateStack(32, 8);
1835 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
1837 unsigned LastVal = ~0U;
1839 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1840 CCValAssign &VA = ArgLocs[i];
1841 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1843 assert(VA.getValNo() != LastVal &&
1844 "Don't support value assigned to multiple locs yet");
1846 LastVal = VA.getValNo();
1848 if (VA.isRegLoc()) {
1849 EVT RegVT = VA.getLocVT();
1850 const TargetRegisterClass *RC;
1851 if (RegVT == MVT::i32)
1852 RC = &X86::GR32RegClass;
1853 else if (Is64Bit && RegVT == MVT::i64)
1854 RC = &X86::GR64RegClass;
1855 else if (RegVT == MVT::f32)
1856 RC = &X86::FR32RegClass;
1857 else if (RegVT == MVT::f64)
1858 RC = &X86::FR64RegClass;
1859 else if (RegVT.isVector() && RegVT.getSizeInBits() == 256)
1860 RC = &X86::VR256RegClass;
1861 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128)
1862 RC = &X86::VR128RegClass;
1863 else if (RegVT == MVT::x86mmx)
1864 RC = &X86::VR64RegClass;
1866 llvm_unreachable("Unknown argument type!");
1868 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1869 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1871 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1872 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1874 if (VA.getLocInfo() == CCValAssign::SExt)
1875 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1876 DAG.getValueType(VA.getValVT()));
1877 else if (VA.getLocInfo() == CCValAssign::ZExt)
1878 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1879 DAG.getValueType(VA.getValVT()));
1880 else if (VA.getLocInfo() == CCValAssign::BCvt)
1881 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
1883 if (VA.isExtInLoc()) {
1884 // Handle MMX values passed in XMM regs.
1885 if (RegVT.isVector()) {
1886 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(),
1889 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1892 assert(VA.isMemLoc());
1893 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
1896 // If value is passed via pointer - do a load.
1897 if (VA.getLocInfo() == CCValAssign::Indirect)
1898 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
1899 MachinePointerInfo(), false, false, false, 0);
1901 InVals.push_back(ArgValue);
1904 // The x86-64 ABI for returning structs by value requires that we copy
1905 // the sret argument into %rax for the return. Save the argument into
1906 // a virtual register so that we can access it from the return points.
1907 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) {
1908 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1909 unsigned Reg = FuncInfo->getSRetReturnReg();
1911 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1912 FuncInfo->setSRetReturnReg(Reg);
1914 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
1915 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
1918 unsigned StackSize = CCInfo.getNextStackOffset();
1919 // Align stack specially for tail calls.
1920 if (FuncIsMadeTailCallSafe(CallConv,
1921 MF.getTarget().Options.GuaranteedTailCallOpt))
1922 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1924 // If the function takes variable number of arguments, make a frame index for
1925 // the start of the first vararg value... for expansion of llvm.va_start.
1927 if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
1928 CallConv != CallingConv::X86_ThisCall)) {
1929 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
1932 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
1934 // FIXME: We should really autogenerate these arrays
1935 static const uint16_t GPR64ArgRegsWin64[] = {
1936 X86::RCX, X86::RDX, X86::R8, X86::R9
1938 static const uint16_t GPR64ArgRegs64Bit[] = {
1939 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1941 static const uint16_t XMMArgRegs64Bit[] = {
1942 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1943 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1945 const uint16_t *GPR64ArgRegs;
1946 unsigned NumXMMRegs = 0;
1949 // The XMM registers which might contain var arg parameters are shadowed
1950 // in their paired GPR. So we only need to save the GPR to their home
1952 TotalNumIntRegs = 4;
1953 GPR64ArgRegs = GPR64ArgRegsWin64;
1955 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
1956 GPR64ArgRegs = GPR64ArgRegs64Bit;
1958 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit,
1961 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
1964 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat);
1965 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
1966 "SSE register cannot be used when SSE is disabled!");
1967 assert(!(NumXMMRegs && MF.getTarget().Options.UseSoftFloat &&
1968 NoImplicitFloatOps) &&
1969 "SSE register cannot be used when SSE is disabled!");
1970 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
1971 !Subtarget->hasSSE1())
1972 // Kernel mode asks for SSE to be disabled, so don't push them
1974 TotalNumXMMRegs = 0;
1977 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering();
1978 // Get to the caller-allocated home save location. Add 8 to account
1979 // for the return address.
1980 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
1981 FuncInfo->setRegSaveFrameIndex(
1982 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
1983 // Fixup to set vararg frame on shadow area (4 x i64).
1985 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
1987 // For X86-64, if there are vararg parameters that are passed via
1988 // registers, then we must store them to their spots on the stack so
1989 // they may be loaded by deferencing the result of va_next.
1990 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
1991 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
1992 FuncInfo->setRegSaveFrameIndex(
1993 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
1997 // Store the integer parameter registers.
1998 SmallVector<SDValue, 8> MemOps;
1999 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2001 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2002 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
2003 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2004 DAG.getIntPtrConstant(Offset));
2005 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
2006 &X86::GR64RegClass);
2007 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2009 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2010 MachinePointerInfo::getFixedStack(
2011 FuncInfo->getRegSaveFrameIndex(), Offset),
2013 MemOps.push_back(Store);
2017 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
2018 // Now store the XMM (fp + vector) parameter registers.
2019 SmallVector<SDValue, 11> SaveXMMOps;
2020 SaveXMMOps.push_back(Chain);
2022 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2023 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
2024 SaveXMMOps.push_back(ALVal);
2026 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2027 FuncInfo->getRegSaveFrameIndex()));
2028 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2029 FuncInfo->getVarArgsFPOffset()));
2031 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
2032 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs],
2033 &X86::VR128RegClass);
2034 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
2035 SaveXMMOps.push_back(Val);
2037 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2039 &SaveXMMOps[0], SaveXMMOps.size()));
2042 if (!MemOps.empty())
2043 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2044 &MemOps[0], MemOps.size());
2048 // Some CCs need callee pop.
2049 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2050 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2051 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2053 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2054 // If this is an sret function, the return should pop the hidden pointer.
2055 if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows &&
2056 ArgsAreStructReturn(Ins))
2057 FuncInfo->setBytesToPopOnReturn(4);
2061 // RegSaveFrameIndex is X86-64 only.
2062 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2063 if (CallConv == CallingConv::X86_FastCall ||
2064 CallConv == CallingConv::X86_ThisCall)
2065 // fastcc functions can't have varargs.
2066 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2069 FuncInfo->setArgumentStackSize(StackSize);
2075 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2076 SDValue StackPtr, SDValue Arg,
2077 DebugLoc dl, SelectionDAG &DAG,
2078 const CCValAssign &VA,
2079 ISD::ArgFlagsTy Flags) const {
2080 unsigned LocMemOffset = VA.getLocMemOffset();
2081 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2082 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2083 if (Flags.isByVal())
2084 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2086 return DAG.getStore(Chain, dl, Arg, PtrOff,
2087 MachinePointerInfo::getStack(LocMemOffset),
2091 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2092 /// optimization is performed and it is required.
2094 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2095 SDValue &OutRetAddr, SDValue Chain,
2096 bool IsTailCall, bool Is64Bit,
2097 int FPDiff, DebugLoc dl) const {
2098 // Adjust the Return address stack slot.
2099 EVT VT = getPointerTy();
2100 OutRetAddr = getReturnAddressFrameIndex(DAG);
2102 // Load the "old" Return address.
2103 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2104 false, false, false, 0);
2105 return SDValue(OutRetAddr.getNode(), 1);
2108 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2109 /// optimization is performed and it is required (FPDiff!=0).
2111 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
2112 SDValue Chain, SDValue RetAddrFrIdx,
2113 bool Is64Bit, int FPDiff, DebugLoc dl) {
2114 // Store the return address to the appropriate stack slot.
2115 if (!FPDiff) return Chain;
2116 // Calculate the new stack slot for the return address.
2117 int SlotSize = Is64Bit ? 8 : 4;
2118 int NewReturnAddrFI =
2119 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false);
2120 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
2121 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
2122 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2123 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2129 X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
2130 CallingConv::ID CallConv, bool isVarArg,
2131 bool doesNotRet, bool &isTailCall,
2132 const SmallVectorImpl<ISD::OutputArg> &Outs,
2133 const SmallVectorImpl<SDValue> &OutVals,
2134 const SmallVectorImpl<ISD::InputArg> &Ins,
2135 DebugLoc dl, SelectionDAG &DAG,
2136 SmallVectorImpl<SDValue> &InVals) const {
2137 MachineFunction &MF = DAG.getMachineFunction();
2138 bool Is64Bit = Subtarget->is64Bit();
2139 bool IsWin64 = Subtarget->isTargetWin64();
2140 bool IsWindows = Subtarget->isTargetWindows();
2141 bool IsStructRet = CallIsStructReturn(Outs);
2142 bool IsSibcall = false;
2144 if (MF.getTarget().Options.DisableTailCalls)
2148 // Check if it's really possible to do a tail call.
2149 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2150 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
2151 Outs, OutVals, Ins, DAG);
2153 // Sibcalls are automatically detected tailcalls which do not require
2155 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2162 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2163 "Var args not supported with calling convention fastcc or ghc");
2165 // Analyze operands of the call, assigning locations to each operand.
2166 SmallVector<CCValAssign, 16> ArgLocs;
2167 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
2168 ArgLocs, *DAG.getContext());
2170 // Allocate shadow area for Win64
2172 CCInfo.AllocateStack(32, 8);
2175 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2177 // Get a count of how many bytes are to be pushed on the stack.
2178 unsigned NumBytes = CCInfo.getNextStackOffset();
2180 // This is a sibcall. The memory operands are available in caller's
2181 // own caller's stack.
2183 else if (getTargetMachine().Options.GuaranteedTailCallOpt &&
2184 IsTailCallConvention(CallConv))
2185 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2188 if (isTailCall && !IsSibcall) {
2189 // Lower arguments at fp - stackoffset + fpdiff.
2190 unsigned NumBytesCallerPushed =
2191 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
2192 FPDiff = NumBytesCallerPushed - NumBytes;
2194 // Set the delta of movement of the returnaddr stackslot.
2195 // But only set if delta is greater than previous delta.
2196 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
2197 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
2201 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
2203 SDValue RetAddrFrIdx;
2204 // Load return address for tail calls.
2205 if (isTailCall && FPDiff)
2206 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2207 Is64Bit, FPDiff, dl);
2209 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2210 SmallVector<SDValue, 8> MemOpChains;
2213 // Walk the register/memloc assignments, inserting copies/loads. In the case
2214 // of tail call optimization arguments are handle later.
2215 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2216 CCValAssign &VA = ArgLocs[i];
2217 EVT RegVT = VA.getLocVT();
2218 SDValue Arg = OutVals[i];
2219 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2220 bool isByVal = Flags.isByVal();
2222 // Promote the value if needed.
2223 switch (VA.getLocInfo()) {
2224 default: llvm_unreachable("Unknown loc info!");
2225 case CCValAssign::Full: break;
2226 case CCValAssign::SExt:
2227 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2229 case CCValAssign::ZExt:
2230 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2232 case CCValAssign::AExt:
2233 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) {
2234 // Special case: passing MMX values in XMM registers.
2235 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2236 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2237 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2239 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2241 case CCValAssign::BCvt:
2242 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2244 case CCValAssign::Indirect: {
2245 // Store the argument.
2246 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2247 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2248 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2249 MachinePointerInfo::getFixedStack(FI),
2256 if (VA.isRegLoc()) {
2257 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2258 if (isVarArg && IsWin64) {
2259 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2260 // shadow reg if callee is a varargs function.
2261 unsigned ShadowReg = 0;
2262 switch (VA.getLocReg()) {
2263 case X86::XMM0: ShadowReg = X86::RCX; break;
2264 case X86::XMM1: ShadowReg = X86::RDX; break;
2265 case X86::XMM2: ShadowReg = X86::R8; break;
2266 case X86::XMM3: ShadowReg = X86::R9; break;
2269 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2271 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2272 assert(VA.isMemLoc());
2273 if (StackPtr.getNode() == 0)
2274 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy());
2275 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2276 dl, DAG, VA, Flags));
2280 if (!MemOpChains.empty())
2281 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2282 &MemOpChains[0], MemOpChains.size());
2284 // Build a sequence of copy-to-reg nodes chained together with token chain
2285 // and flag operands which copy the outgoing args into registers.
2287 // Tail call byval lowering might overwrite argument registers so in case of
2288 // tail call optimization the copies to registers are lowered later.
2290 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2291 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2292 RegsToPass[i].second, InFlag);
2293 InFlag = Chain.getValue(1);
2296 if (Subtarget->isPICStyleGOT()) {
2297 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2300 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX,
2301 DAG.getNode(X86ISD::GlobalBaseReg,
2302 DebugLoc(), getPointerTy()),
2304 InFlag = Chain.getValue(1);
2306 // If we are tail calling and generating PIC/GOT style code load the
2307 // address of the callee into ECX. The value in ecx is used as target of
2308 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2309 // for tail calls on PIC/GOT architectures. Normally we would just put the
2310 // address of GOT into ebx and then call target@PLT. But for tail calls
2311 // ebx would be restored (since ebx is callee saved) before jumping to the
2314 // Note: The actual moving to ECX is done further down.
2315 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2316 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2317 !G->getGlobal()->hasProtectedVisibility())
2318 Callee = LowerGlobalAddress(Callee, DAG);
2319 else if (isa<ExternalSymbolSDNode>(Callee))
2320 Callee = LowerExternalSymbol(Callee, DAG);
2324 if (Is64Bit && isVarArg && !IsWin64) {
2325 // From AMD64 ABI document:
2326 // For calls that may call functions that use varargs or stdargs
2327 // (prototype-less calls or calls to functions containing ellipsis (...) in
2328 // the declaration) %al is used as hidden argument to specify the number
2329 // of SSE registers used. The contents of %al do not need to match exactly
2330 // the number of registers, but must be an ubound on the number of SSE
2331 // registers used and is in the range 0 - 8 inclusive.
2333 // Count the number of XMM registers allocated.
2334 static const uint16_t XMMArgRegs[] = {
2335 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2336 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2338 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2339 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2340 && "SSE registers cannot be used when SSE is disabled");
2342 Chain = DAG.getCopyToReg(Chain, dl, X86::AL,
2343 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
2344 InFlag = Chain.getValue(1);
2348 // For tail calls lower the arguments to the 'real' stack slot.
2350 // Force all the incoming stack arguments to be loaded from the stack
2351 // before any new outgoing arguments are stored to the stack, because the
2352 // outgoing stack slots may alias the incoming argument stack slots, and
2353 // the alias isn't otherwise explicit. This is slightly more conservative
2354 // than necessary, because it means that each store effectively depends
2355 // on every argument instead of just those arguments it would clobber.
2356 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2358 SmallVector<SDValue, 8> MemOpChains2;
2361 // Do not flag preceding copytoreg stuff together with the following stuff.
2363 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2364 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2365 CCValAssign &VA = ArgLocs[i];
2368 assert(VA.isMemLoc());
2369 SDValue Arg = OutVals[i];
2370 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2371 // Create frame index.
2372 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2373 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2374 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2375 FIN = DAG.getFrameIndex(FI, getPointerTy());
2377 if (Flags.isByVal()) {
2378 // Copy relative to framepointer.
2379 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2380 if (StackPtr.getNode() == 0)
2381 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr,
2383 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2385 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2389 // Store relative to framepointer.
2390 MemOpChains2.push_back(
2391 DAG.getStore(ArgChain, dl, Arg, FIN,
2392 MachinePointerInfo::getFixedStack(FI),
2398 if (!MemOpChains2.empty())
2399 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2400 &MemOpChains2[0], MemOpChains2.size());
2402 // Copy arguments to their registers.
2403 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2404 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2405 RegsToPass[i].second, InFlag);
2406 InFlag = Chain.getValue(1);
2410 // Store the return address to the appropriate stack slot.
2411 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
2415 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2416 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2417 // In the 64-bit large code model, we have to make all calls
2418 // through a register, since the call instruction's 32-bit
2419 // pc-relative offset may not be large enough to hold the whole
2421 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2422 // If the callee is a GlobalAddress node (quite common, every direct call
2423 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2426 // We should use extra load for direct calls to dllimported functions in
2428 const GlobalValue *GV = G->getGlobal();
2429 if (!GV->hasDLLImportLinkage()) {
2430 unsigned char OpFlags = 0;
2431 bool ExtraLoad = false;
2432 unsigned WrapperKind = ISD::DELETED_NODE;
2434 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2435 // external symbols most go through the PLT in PIC mode. If the symbol
2436 // has hidden or protected visibility, or if it is static or local, then
2437 // we don't need to use the PLT - we can directly call it.
2438 if (Subtarget->isTargetELF() &&
2439 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2440 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2441 OpFlags = X86II::MO_PLT;
2442 } else if (Subtarget->isPICStyleStubAny() &&
2443 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2444 (!Subtarget->getTargetTriple().isMacOSX() ||
2445 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2446 // PC-relative references to external symbols should go through $stub,
2447 // unless we're building with the leopard linker or later, which
2448 // automatically synthesizes these stubs.
2449 OpFlags = X86II::MO_DARWIN_STUB;
2450 } else if (Subtarget->isPICStyleRIPRel() &&
2451 isa<Function>(GV) &&
2452 cast<Function>(GV)->hasFnAttr(Attribute::NonLazyBind)) {
2453 // If the function is marked as non-lazy, generate an indirect call
2454 // which loads from the GOT directly. This avoids runtime overhead
2455 // at the cost of eager binding (and one extra byte of encoding).
2456 OpFlags = X86II::MO_GOTPCREL;
2457 WrapperKind = X86ISD::WrapperRIP;
2461 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2462 G->getOffset(), OpFlags);
2464 // Add a wrapper if needed.
2465 if (WrapperKind != ISD::DELETED_NODE)
2466 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
2467 // Add extra indirection if needed.
2469 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
2470 MachinePointerInfo::getGOT(),
2471 false, false, false, 0);
2473 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2474 unsigned char OpFlags = 0;
2476 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
2477 // external symbols should go through the PLT.
2478 if (Subtarget->isTargetELF() &&
2479 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2480 OpFlags = X86II::MO_PLT;
2481 } else if (Subtarget->isPICStyleStubAny() &&
2482 (!Subtarget->getTargetTriple().isMacOSX() ||
2483 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2484 // PC-relative references to external symbols should go through $stub,
2485 // unless we're building with the leopard linker or later, which
2486 // automatically synthesizes these stubs.
2487 OpFlags = X86II::MO_DARWIN_STUB;
2490 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2494 // Returns a chain & a flag for retval copy to use.
2495 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2496 SmallVector<SDValue, 8> Ops;
2498 if (!IsSibcall && isTailCall) {
2499 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2500 DAG.getIntPtrConstant(0, true), InFlag);
2501 InFlag = Chain.getValue(1);
2504 Ops.push_back(Chain);
2505 Ops.push_back(Callee);
2508 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2510 // Add argument registers to the end of the list so that they are known live
2512 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2513 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2514 RegsToPass[i].second.getValueType()));
2516 // Add an implicit use GOT pointer in EBX.
2517 if (!isTailCall && Subtarget->isPICStyleGOT())
2518 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
2520 // Add an implicit use of AL for non-Windows x86 64-bit vararg functions.
2521 if (Is64Bit && isVarArg && !IsWin64)
2522 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
2524 // Add a register mask operand representing the call-preserved registers.
2525 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2526 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
2527 assert(Mask && "Missing call preserved mask for calling convention");
2528 Ops.push_back(DAG.getRegisterMask(Mask));
2530 if (InFlag.getNode())
2531 Ops.push_back(InFlag);
2535 //// If this is the first return lowered for this function, add the regs
2536 //// to the liveout set for the function.
2537 // This isn't right, although it's probably harmless on x86; liveouts
2538 // should be computed from returns not tail calls. Consider a void
2539 // function making a tail call to a function returning int.
2540 return DAG.getNode(X86ISD::TC_RETURN, dl,
2541 NodeTys, &Ops[0], Ops.size());
2544 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2545 InFlag = Chain.getValue(1);
2547 // Create the CALLSEQ_END node.
2548 unsigned NumBytesForCalleeToPush;
2549 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2550 getTargetMachine().Options.GuaranteedTailCallOpt))
2551 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2552 else if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows &&
2554 // If this is a call to a struct-return function, the callee
2555 // pops the hidden struct pointer, so we have to push it back.
2556 // This is common for Darwin/X86, Linux & Mingw32 targets.
2557 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
2558 NumBytesForCalleeToPush = 4;
2560 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2562 // Returns a flag for retval copy to use.
2564 Chain = DAG.getCALLSEQ_END(Chain,
2565 DAG.getIntPtrConstant(NumBytes, true),
2566 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2569 InFlag = Chain.getValue(1);
2572 // Handle result values, copying them out of physregs into vregs that we
2574 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2575 Ins, dl, DAG, InVals);
2579 //===----------------------------------------------------------------------===//
2580 // Fast Calling Convention (tail call) implementation
2581 //===----------------------------------------------------------------------===//
2583 // Like std call, callee cleans arguments, convention except that ECX is
2584 // reserved for storing the tail called function address. Only 2 registers are
2585 // free for argument passing (inreg). Tail call optimization is performed
2587 // * tailcallopt is enabled
2588 // * caller/callee are fastcc
2589 // On X86_64 architecture with GOT-style position independent code only local
2590 // (within module) calls are supported at the moment.
2591 // To keep the stack aligned according to platform abi the function
2592 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2593 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2594 // If a tail called function callee has more arguments than the caller the
2595 // caller needs to make sure that there is room to move the RETADDR to. This is
2596 // achieved by reserving an area the size of the argument delta right after the
2597 // original REtADDR, but before the saved framepointer or the spilled registers
2598 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2610 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2611 /// for a 16 byte align requirement.
2613 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2614 SelectionDAG& DAG) const {
2615 MachineFunction &MF = DAG.getMachineFunction();
2616 const TargetMachine &TM = MF.getTarget();
2617 const TargetFrameLowering &TFI = *TM.getFrameLowering();
2618 unsigned StackAlignment = TFI.getStackAlignment();
2619 uint64_t AlignMask = StackAlignment - 1;
2620 int64_t Offset = StackSize;
2621 uint64_t SlotSize = TD->getPointerSize();
2622 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2623 // Number smaller than 12 so just add the difference.
2624 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2626 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2627 Offset = ((~AlignMask) & Offset) + StackAlignment +
2628 (StackAlignment-SlotSize);
2633 /// MatchingStackOffset - Return true if the given stack call argument is
2634 /// already available in the same position (relatively) of the caller's
2635 /// incoming argument stack.
2637 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2638 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
2639 const X86InstrInfo *TII) {
2640 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
2642 if (Arg.getOpcode() == ISD::CopyFromReg) {
2643 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2644 if (!TargetRegisterInfo::isVirtualRegister(VR))
2646 MachineInstr *Def = MRI->getVRegDef(VR);
2649 if (!Flags.isByVal()) {
2650 if (!TII->isLoadFromStackSlot(Def, FI))
2653 unsigned Opcode = Def->getOpcode();
2654 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
2655 Def->getOperand(1).isFI()) {
2656 FI = Def->getOperand(1).getIndex();
2657 Bytes = Flags.getByValSize();
2661 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2662 if (Flags.isByVal())
2663 // ByVal argument is passed in as a pointer but it's now being
2664 // dereferenced. e.g.
2665 // define @foo(%struct.X* %A) {
2666 // tail call @bar(%struct.X* byval %A)
2669 SDValue Ptr = Ld->getBasePtr();
2670 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2673 FI = FINode->getIndex();
2674 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
2675 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
2676 FI = FINode->getIndex();
2677 Bytes = Flags.getByValSize();
2681 assert(FI != INT_MAX);
2682 if (!MFI->isFixedObjectIndex(FI))
2684 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
2687 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2688 /// for tail call optimization. Targets which want to do tail call
2689 /// optimization should implement this function.
2691 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2692 CallingConv::ID CalleeCC,
2694 bool isCalleeStructRet,
2695 bool isCallerStructRet,
2696 const SmallVectorImpl<ISD::OutputArg> &Outs,
2697 const SmallVectorImpl<SDValue> &OutVals,
2698 const SmallVectorImpl<ISD::InputArg> &Ins,
2699 SelectionDAG& DAG) const {
2700 if (!IsTailCallConvention(CalleeCC) &&
2701 CalleeCC != CallingConv::C)
2704 // If -tailcallopt is specified, make fastcc functions tail-callable.
2705 const MachineFunction &MF = DAG.getMachineFunction();
2706 const Function *CallerF = DAG.getMachineFunction().getFunction();
2707 CallingConv::ID CallerCC = CallerF->getCallingConv();
2708 bool CCMatch = CallerCC == CalleeCC;
2710 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2711 if (IsTailCallConvention(CalleeCC) && CCMatch)
2716 // Look for obvious safe cases to perform tail call optimization that do not
2717 // require ABI changes. This is what gcc calls sibcall.
2719 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
2720 // emit a special epilogue.
2721 if (RegInfo->needsStackRealignment(MF))
2724 // Also avoid sibcall optimization if either caller or callee uses struct
2725 // return semantics.
2726 if (isCalleeStructRet || isCallerStructRet)
2729 // An stdcall caller is expected to clean up its arguments; the callee
2730 // isn't going to do that.
2731 if (!CCMatch && CallerCC==CallingConv::X86_StdCall)
2734 // Do not sibcall optimize vararg calls unless all arguments are passed via
2736 if (isVarArg && !Outs.empty()) {
2738 // Optimizing for varargs on Win64 is unlikely to be safe without
2739 // additional testing.
2740 if (Subtarget->isTargetWin64())
2743 SmallVector<CCValAssign, 16> ArgLocs;
2744 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2745 getTargetMachine(), ArgLocs, *DAG.getContext());
2747 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2748 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
2749 if (!ArgLocs[i].isRegLoc())
2753 // If the call result is in ST0 / ST1, it needs to be popped off the x87
2754 // stack. Therefore, if it's not used by the call it is not safe to optimize
2755 // this into a sibcall.
2756 bool Unused = false;
2757 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
2764 SmallVector<CCValAssign, 16> RVLocs;
2765 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(),
2766 getTargetMachine(), RVLocs, *DAG.getContext());
2767 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2768 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2769 CCValAssign &VA = RVLocs[i];
2770 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
2775 // If the calling conventions do not match, then we'd better make sure the
2776 // results are returned in the same way as what the caller expects.
2778 SmallVector<CCValAssign, 16> RVLocs1;
2779 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
2780 getTargetMachine(), RVLocs1, *DAG.getContext());
2781 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
2783 SmallVector<CCValAssign, 16> RVLocs2;
2784 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
2785 getTargetMachine(), RVLocs2, *DAG.getContext());
2786 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
2788 if (RVLocs1.size() != RVLocs2.size())
2790 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2791 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2793 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2795 if (RVLocs1[i].isRegLoc()) {
2796 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2799 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2805 // If the callee takes no arguments then go on to check the results of the
2807 if (!Outs.empty()) {
2808 // Check if stack adjustment is needed. For now, do not do this if any
2809 // argument is passed on the stack.
2810 SmallVector<CCValAssign, 16> ArgLocs;
2811 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2812 getTargetMachine(), ArgLocs, *DAG.getContext());
2814 // Allocate shadow area for Win64
2815 if (Subtarget->isTargetWin64()) {
2816 CCInfo.AllocateStack(32, 8);
2819 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2820 if (CCInfo.getNextStackOffset()) {
2821 MachineFunction &MF = DAG.getMachineFunction();
2822 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
2825 // Check if the arguments are already laid out in the right way as
2826 // the caller's fixed stack objects.
2827 MachineFrameInfo *MFI = MF.getFrameInfo();
2828 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2829 const X86InstrInfo *TII =
2830 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
2831 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2832 CCValAssign &VA = ArgLocs[i];
2833 SDValue Arg = OutVals[i];
2834 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2835 if (VA.getLocInfo() == CCValAssign::Indirect)
2837 if (!VA.isRegLoc()) {
2838 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2845 // If the tailcall address may be in a register, then make sure it's
2846 // possible to register allocate for it. In 32-bit, the call address can
2847 // only target EAX, EDX, or ECX since the tail call must be scheduled after
2848 // callee-saved registers are restored. These happen to be the same
2849 // registers used to pass 'inreg' arguments so watch out for those.
2850 if (!Subtarget->is64Bit() &&
2851 !isa<GlobalAddressSDNode>(Callee) &&
2852 !isa<ExternalSymbolSDNode>(Callee)) {
2853 unsigned NumInRegs = 0;
2854 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2855 CCValAssign &VA = ArgLocs[i];
2858 unsigned Reg = VA.getLocReg();
2861 case X86::EAX: case X86::EDX: case X86::ECX:
2862 if (++NumInRegs == 3)
2874 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const {
2875 return X86::createFastISel(funcInfo);
2879 //===----------------------------------------------------------------------===//
2880 // Other Lowering Hooks
2881 //===----------------------------------------------------------------------===//
2883 static bool MayFoldLoad(SDValue Op) {
2884 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
2887 static bool MayFoldIntoStore(SDValue Op) {
2888 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
2891 static bool isTargetShuffle(unsigned Opcode) {
2893 default: return false;
2894 case X86ISD::PSHUFD:
2895 case X86ISD::PSHUFHW:
2896 case X86ISD::PSHUFLW:
2898 case X86ISD::PALIGN:
2899 case X86ISD::MOVLHPS:
2900 case X86ISD::MOVLHPD:
2901 case X86ISD::MOVHLPS:
2902 case X86ISD::MOVLPS:
2903 case X86ISD::MOVLPD:
2904 case X86ISD::MOVSHDUP:
2905 case X86ISD::MOVSLDUP:
2906 case X86ISD::MOVDDUP:
2909 case X86ISD::UNPCKL:
2910 case X86ISD::UNPCKH:
2911 case X86ISD::VPERMILP:
2912 case X86ISD::VPERM2X128:
2917 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2918 SDValue V1, SelectionDAG &DAG) {
2920 default: llvm_unreachable("Unknown x86 shuffle node");
2921 case X86ISD::MOVSHDUP:
2922 case X86ISD::MOVSLDUP:
2923 case X86ISD::MOVDDUP:
2924 return DAG.getNode(Opc, dl, VT, V1);
2928 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2929 SDValue V1, unsigned TargetMask,
2930 SelectionDAG &DAG) {
2932 default: llvm_unreachable("Unknown x86 shuffle node");
2933 case X86ISD::PSHUFD:
2934 case X86ISD::PSHUFHW:
2935 case X86ISD::PSHUFLW:
2936 case X86ISD::VPERMILP:
2937 case X86ISD::VPERMI:
2938 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
2942 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2943 SDValue V1, SDValue V2, unsigned TargetMask,
2944 SelectionDAG &DAG) {
2946 default: llvm_unreachable("Unknown x86 shuffle node");
2947 case X86ISD::PALIGN:
2949 case X86ISD::VPERM2X128:
2950 return DAG.getNode(Opc, dl, VT, V1, V2,
2951 DAG.getConstant(TargetMask, MVT::i8));
2955 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2956 SDValue V1, SDValue V2, SelectionDAG &DAG) {
2958 default: llvm_unreachable("Unknown x86 shuffle node");
2959 case X86ISD::MOVLHPS:
2960 case X86ISD::MOVLHPD:
2961 case X86ISD::MOVHLPS:
2962 case X86ISD::MOVLPS:
2963 case X86ISD::MOVLPD:
2966 case X86ISD::UNPCKL:
2967 case X86ISD::UNPCKH:
2968 return DAG.getNode(Opc, dl, VT, V1, V2);
2972 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
2973 MachineFunction &MF = DAG.getMachineFunction();
2974 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2975 int ReturnAddrIndex = FuncInfo->getRAIndex();
2977 if (ReturnAddrIndex == 0) {
2978 // Set up a frame object for the return address.
2979 uint64_t SlotSize = TD->getPointerSize();
2980 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
2982 FuncInfo->setRAIndex(ReturnAddrIndex);
2985 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
2989 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
2990 bool hasSymbolicDisplacement) {
2991 // Offset should fit into 32 bit immediate field.
2992 if (!isInt<32>(Offset))
2995 // If we don't have a symbolic displacement - we don't have any extra
2997 if (!hasSymbolicDisplacement)
3000 // FIXME: Some tweaks might be needed for medium code model.
3001 if (M != CodeModel::Small && M != CodeModel::Kernel)
3004 // For small code model we assume that latest object is 16MB before end of 31
3005 // bits boundary. We may also accept pretty large negative constants knowing
3006 // that all objects are in the positive half of address space.
3007 if (M == CodeModel::Small && Offset < 16*1024*1024)
3010 // For kernel code model we know that all object resist in the negative half
3011 // of 32bits address space. We may not accept negative offsets, since they may
3012 // be just off and we may accept pretty large positive ones.
3013 if (M == CodeModel::Kernel && Offset > 0)
3019 /// isCalleePop - Determines whether the callee is required to pop its
3020 /// own arguments. Callee pop is necessary to support tail calls.
3021 bool X86::isCalleePop(CallingConv::ID CallingConv,
3022 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3026 switch (CallingConv) {
3029 case CallingConv::X86_StdCall:
3031 case CallingConv::X86_FastCall:
3033 case CallingConv::X86_ThisCall:
3035 case CallingConv::Fast:
3037 case CallingConv::GHC:
3042 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3043 /// specific condition code, returning the condition code and the LHS/RHS of the
3044 /// comparison to make.
3045 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3046 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3048 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3049 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3050 // X > -1 -> X == 0, jump !sign.
3051 RHS = DAG.getConstant(0, RHS.getValueType());
3052 return X86::COND_NS;
3054 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3055 // X < 0 -> X == 0, jump on sign.
3058 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3060 RHS = DAG.getConstant(0, RHS.getValueType());
3061 return X86::COND_LE;
3065 switch (SetCCOpcode) {
3066 default: llvm_unreachable("Invalid integer condition!");
3067 case ISD::SETEQ: return X86::COND_E;
3068 case ISD::SETGT: return X86::COND_G;
3069 case ISD::SETGE: return X86::COND_GE;
3070 case ISD::SETLT: return X86::COND_L;
3071 case ISD::SETLE: return X86::COND_LE;
3072 case ISD::SETNE: return X86::COND_NE;
3073 case ISD::SETULT: return X86::COND_B;
3074 case ISD::SETUGT: return X86::COND_A;
3075 case ISD::SETULE: return X86::COND_BE;
3076 case ISD::SETUGE: return X86::COND_AE;
3080 // First determine if it is required or is profitable to flip the operands.
3082 // If LHS is a foldable load, but RHS is not, flip the condition.
3083 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3084 !ISD::isNON_EXTLoad(RHS.getNode())) {
3085 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3086 std::swap(LHS, RHS);
3089 switch (SetCCOpcode) {
3095 std::swap(LHS, RHS);
3099 // On a floating point condition, the flags are set as follows:
3101 // 0 | 0 | 0 | X > Y
3102 // 0 | 0 | 1 | X < Y
3103 // 1 | 0 | 0 | X == Y
3104 // 1 | 1 | 1 | unordered
3105 switch (SetCCOpcode) {
3106 default: llvm_unreachable("Condcode should be pre-legalized away");
3108 case ISD::SETEQ: return X86::COND_E;
3109 case ISD::SETOLT: // flipped
3111 case ISD::SETGT: return X86::COND_A;
3112 case ISD::SETOLE: // flipped
3114 case ISD::SETGE: return X86::COND_AE;
3115 case ISD::SETUGT: // flipped
3117 case ISD::SETLT: return X86::COND_B;
3118 case ISD::SETUGE: // flipped
3120 case ISD::SETLE: return X86::COND_BE;
3122 case ISD::SETNE: return X86::COND_NE;
3123 case ISD::SETUO: return X86::COND_P;
3124 case ISD::SETO: return X86::COND_NP;
3126 case ISD::SETUNE: return X86::COND_INVALID;
3130 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3131 /// code. Current x86 isa includes the following FP cmov instructions:
3132 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3133 static bool hasFPCMov(unsigned X86CC) {
3149 /// isFPImmLegal - Returns true if the target can instruction select the
3150 /// specified FP immediate natively. If false, the legalizer will
3151 /// materialize the FP immediate as a load from a constant pool.
3152 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3153 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3154 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3160 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3161 /// the specified range (L, H].
3162 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3163 return (Val < 0) || (Val >= Low && Val < Hi);
3166 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3167 /// specified value.
3168 static bool isUndefOrEqual(int Val, int CmpVal) {
3169 if (Val < 0 || Val == CmpVal)
3174 /// isSequentialOrUndefInRange - Return true if every element in Mask, begining
3175 /// from position Pos and ending in Pos+Size, falls within the specified
3176 /// sequential range (L, L+Pos]. or is undef.
3177 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3178 int Pos, int Size, int Low) {
3179 for (int i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3180 if (!isUndefOrEqual(Mask[i], Low))
3185 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3186 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3187 /// the second operand.
3188 static bool isPSHUFDMask(ArrayRef<int> Mask, EVT VT) {
3189 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3190 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3191 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3192 return (Mask[0] < 2 && Mask[1] < 2);
3196 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3197 /// is suitable for input to PSHUFHW.
3198 static bool isPSHUFHWMask(ArrayRef<int> Mask, EVT VT) {
3199 if (VT != MVT::v8i16)
3202 // Lower quadword copied in order or undef.
3203 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3206 // Upper quadword shuffled.
3207 for (unsigned i = 4; i != 8; ++i)
3208 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7))
3214 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3215 /// is suitable for input to PSHUFLW.
3216 static bool isPSHUFLWMask(ArrayRef<int> Mask, EVT VT) {
3217 if (VT != MVT::v8i16)
3220 // Upper quadword copied in order.
3221 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3224 // Lower quadword shuffled.
3225 for (unsigned i = 0; i != 4; ++i)
3232 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
3233 /// is suitable for input to PALIGNR.
3234 static bool isPALIGNRMask(ArrayRef<int> Mask, EVT VT,
3235 const X86Subtarget *Subtarget) {
3236 if ((VT.getSizeInBits() == 128 && !Subtarget->hasSSSE3()) ||
3237 (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2()))
3240 unsigned NumElts = VT.getVectorNumElements();
3241 unsigned NumLanes = VT.getSizeInBits()/128;
3242 unsigned NumLaneElts = NumElts/NumLanes;
3244 // Do not handle 64-bit element shuffles with palignr.
3245 if (NumLaneElts == 2)
3248 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3250 for (i = 0; i != NumLaneElts; ++i) {
3255 // Lane is all undef, go to next lane
3256 if (i == NumLaneElts)
3259 int Start = Mask[i+l];
3261 // Make sure its in this lane in one of the sources
3262 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3263 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3266 // If not lane 0, then we must match lane 0
3267 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3270 // Correct second source to be contiguous with first source
3271 if (Start >= (int)NumElts)
3272 Start -= NumElts - NumLaneElts;
3274 // Make sure we're shifting in the right direction.
3275 if (Start <= (int)(i+l))
3280 // Check the rest of the elements to see if they are consecutive.
3281 for (++i; i != NumLaneElts; ++i) {
3282 int Idx = Mask[i+l];
3284 // Make sure its in this lane
3285 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3286 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3289 // If not lane 0, then we must match lane 0
3290 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3293 if (Idx >= (int)NumElts)
3294 Idx -= NumElts - NumLaneElts;
3296 if (!isUndefOrEqual(Idx, Start+i))
3305 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3306 /// the two vector operands have swapped position.
3307 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
3308 unsigned NumElems) {
3309 for (unsigned i = 0; i != NumElems; ++i) {
3313 else if (idx < (int)NumElems)
3314 Mask[i] = idx + NumElems;
3316 Mask[i] = idx - NumElems;
3320 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
3321 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
3322 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
3323 /// reverse of what x86 shuffles want.
3324 static bool isSHUFPMask(ArrayRef<int> Mask, EVT VT, bool HasAVX,
3325 bool Commuted = false) {
3326 if (!HasAVX && VT.getSizeInBits() == 256)
3329 unsigned NumElems = VT.getVectorNumElements();
3330 unsigned NumLanes = VT.getSizeInBits()/128;
3331 unsigned NumLaneElems = NumElems/NumLanes;
3333 if (NumLaneElems != 2 && NumLaneElems != 4)
3336 // VSHUFPSY divides the resulting vector into 4 chunks.
3337 // The sources are also splitted into 4 chunks, and each destination
3338 // chunk must come from a different source chunk.
3340 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
3341 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
3343 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
3344 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
3346 // VSHUFPDY divides the resulting vector into 4 chunks.
3347 // The sources are also splitted into 4 chunks, and each destination
3348 // chunk must come from a different source chunk.
3350 // SRC1 => X3 X2 X1 X0
3351 // SRC2 => Y3 Y2 Y1 Y0
3353 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
3355 unsigned HalfLaneElems = NumLaneElems/2;
3356 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
3357 for (unsigned i = 0; i != NumLaneElems; ++i) {
3358 int Idx = Mask[i+l];
3359 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
3360 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
3362 // For VSHUFPSY, the mask of the second half must be the same as the
3363 // first but with the appropriate offsets. This works in the same way as
3364 // VPERMILPS works with masks.
3365 if (NumElems != 8 || l == 0 || Mask[i] < 0)
3367 if (!isUndefOrEqual(Idx, Mask[i]+l))
3375 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
3376 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
3377 static bool isMOVHLPSMask(ArrayRef<int> Mask, EVT VT) {
3378 unsigned NumElems = VT.getVectorNumElements();
3380 if (VT.getSizeInBits() != 128)
3386 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
3387 return isUndefOrEqual(Mask[0], 6) &&
3388 isUndefOrEqual(Mask[1], 7) &&
3389 isUndefOrEqual(Mask[2], 2) &&
3390 isUndefOrEqual(Mask[3], 3);
3393 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
3394 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
3396 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, EVT VT) {
3397 unsigned NumElems = VT.getVectorNumElements();
3399 if (VT.getSizeInBits() != 128)
3405 return isUndefOrEqual(Mask[0], 2) &&
3406 isUndefOrEqual(Mask[1], 3) &&
3407 isUndefOrEqual(Mask[2], 2) &&
3408 isUndefOrEqual(Mask[3], 3);
3411 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
3412 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
3413 static bool isMOVLPMask(ArrayRef<int> Mask, EVT VT) {
3414 if (VT.getSizeInBits() != 128)
3417 unsigned NumElems = VT.getVectorNumElements();
3419 if (NumElems != 2 && NumElems != 4)
3422 for (unsigned i = 0; i != NumElems/2; ++i)
3423 if (!isUndefOrEqual(Mask[i], i + NumElems))
3426 for (unsigned i = NumElems/2; i != NumElems; ++i)
3427 if (!isUndefOrEqual(Mask[i], i))
3433 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
3434 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
3435 static bool isMOVLHPSMask(ArrayRef<int> Mask, EVT VT) {
3436 unsigned NumElems = VT.getVectorNumElements();
3438 if ((NumElems != 2 && NumElems != 4)
3439 || VT.getSizeInBits() > 128)
3442 for (unsigned i = 0; i != NumElems/2; ++i)
3443 if (!isUndefOrEqual(Mask[i], i))
3446 for (unsigned i = 0; i != NumElems/2; ++i)
3447 if (!isUndefOrEqual(Mask[i + NumElems/2], i + NumElems))
3453 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
3454 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
3455 static bool isUNPCKLMask(ArrayRef<int> Mask, EVT VT,
3456 bool HasAVX2, bool V2IsSplat = false) {
3457 unsigned NumElts = VT.getVectorNumElements();
3459 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3460 "Unsupported vector type for unpckh");
3462 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3463 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3466 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3467 // independently on 128-bit lanes.
3468 unsigned NumLanes = VT.getSizeInBits()/128;
3469 unsigned NumLaneElts = NumElts/NumLanes;
3471 for (unsigned l = 0; l != NumLanes; ++l) {
3472 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts;
3473 i != (l+1)*NumLaneElts;
3476 int BitI1 = Mask[i+1];
3477 if (!isUndefOrEqual(BitI, j))
3480 if (!isUndefOrEqual(BitI1, NumElts))
3483 if (!isUndefOrEqual(BitI1, j + NumElts))
3492 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
3493 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
3494 static bool isUNPCKHMask(ArrayRef<int> Mask, EVT VT,
3495 bool HasAVX2, bool V2IsSplat = false) {
3496 unsigned NumElts = VT.getVectorNumElements();
3498 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3499 "Unsupported vector type for unpckh");
3501 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3502 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3505 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3506 // independently on 128-bit lanes.
3507 unsigned NumLanes = VT.getSizeInBits()/128;
3508 unsigned NumLaneElts = NumElts/NumLanes;
3510 for (unsigned l = 0; l != NumLanes; ++l) {
3511 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2;
3512 i != (l+1)*NumLaneElts; i += 2, ++j) {
3514 int BitI1 = Mask[i+1];
3515 if (!isUndefOrEqual(BitI, j))
3518 if (isUndefOrEqual(BitI1, NumElts))
3521 if (!isUndefOrEqual(BitI1, j+NumElts))
3529 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
3530 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
3532 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, EVT VT,
3534 unsigned NumElts = VT.getVectorNumElements();
3536 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3537 "Unsupported vector type for unpckh");
3539 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3540 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3543 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
3544 // FIXME: Need a better way to get rid of this, there's no latency difference
3545 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
3546 // the former later. We should also remove the "_undef" special mask.
3547 if (NumElts == 4 && VT.getSizeInBits() == 256)
3550 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3551 // independently on 128-bit lanes.
3552 unsigned NumLanes = VT.getSizeInBits()/128;
3553 unsigned NumLaneElts = NumElts/NumLanes;
3555 for (unsigned l = 0; l != NumLanes; ++l) {
3556 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts;
3557 i != (l+1)*NumLaneElts;
3560 int BitI1 = Mask[i+1];
3562 if (!isUndefOrEqual(BitI, j))
3564 if (!isUndefOrEqual(BitI1, j))
3572 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
3573 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
3575 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, EVT VT, bool HasAVX2) {
3576 unsigned NumElts = VT.getVectorNumElements();
3578 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3579 "Unsupported vector type for unpckh");
3581 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3582 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3585 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3586 // independently on 128-bit lanes.
3587 unsigned NumLanes = VT.getSizeInBits()/128;
3588 unsigned NumLaneElts = NumElts/NumLanes;
3590 for (unsigned l = 0; l != NumLanes; ++l) {
3591 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2;
3592 i != (l+1)*NumLaneElts; i += 2, ++j) {
3594 int BitI1 = Mask[i+1];
3595 if (!isUndefOrEqual(BitI, j))
3597 if (!isUndefOrEqual(BitI1, j))
3604 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
3605 /// specifies a shuffle of elements that is suitable for input to MOVSS,
3606 /// MOVSD, and MOVD, i.e. setting the lowest element.
3607 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
3608 if (VT.getVectorElementType().getSizeInBits() < 32)
3610 if (VT.getSizeInBits() == 256)
3613 unsigned NumElts = VT.getVectorNumElements();
3615 if (!isUndefOrEqual(Mask[0], NumElts))
3618 for (unsigned i = 1; i != NumElts; ++i)
3619 if (!isUndefOrEqual(Mask[i], i))
3625 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
3626 /// as permutations between 128-bit chunks or halves. As an example: this
3628 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
3629 /// The first half comes from the second half of V1 and the second half from the
3630 /// the second half of V2.
3631 static bool isVPERM2X128Mask(ArrayRef<int> Mask, EVT VT, bool HasAVX) {
3632 if (!HasAVX || VT.getSizeInBits() != 256)
3635 // The shuffle result is divided into half A and half B. In total the two
3636 // sources have 4 halves, namely: C, D, E, F. The final values of A and
3637 // B must come from C, D, E or F.
3638 unsigned HalfSize = VT.getVectorNumElements()/2;
3639 bool MatchA = false, MatchB = false;
3641 // Check if A comes from one of C, D, E, F.
3642 for (unsigned Half = 0; Half != 4; ++Half) {
3643 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
3649 // Check if B comes from one of C, D, E, F.
3650 for (unsigned Half = 0; Half != 4; ++Half) {
3651 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
3657 return MatchA && MatchB;
3660 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
3661 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
3662 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
3663 EVT VT = SVOp->getValueType(0);
3665 unsigned HalfSize = VT.getVectorNumElements()/2;
3667 unsigned FstHalf = 0, SndHalf = 0;
3668 for (unsigned i = 0; i < HalfSize; ++i) {
3669 if (SVOp->getMaskElt(i) > 0) {
3670 FstHalf = SVOp->getMaskElt(i)/HalfSize;
3674 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
3675 if (SVOp->getMaskElt(i) > 0) {
3676 SndHalf = SVOp->getMaskElt(i)/HalfSize;
3681 return (FstHalf | (SndHalf << 4));
3684 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
3685 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
3686 /// Note that VPERMIL mask matching is different depending whether theunderlying
3687 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
3688 /// to the same elements of the low, but to the higher half of the source.
3689 /// In VPERMILPD the two lanes could be shuffled independently of each other
3690 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
3691 static bool isVPERMILPMask(ArrayRef<int> Mask, EVT VT, bool HasAVX) {
3695 unsigned NumElts = VT.getVectorNumElements();
3696 // Only match 256-bit with 32/64-bit types
3697 if (VT.getSizeInBits() != 256 || (NumElts != 4 && NumElts != 8))
3700 unsigned NumLanes = VT.getSizeInBits()/128;
3701 unsigned LaneSize = NumElts/NumLanes;
3702 for (unsigned l = 0; l != NumElts; l += LaneSize) {
3703 for (unsigned i = 0; i != LaneSize; ++i) {
3704 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
3706 if (NumElts != 8 || l == 0)
3708 // VPERMILPS handling
3711 if (!isUndefOrEqual(Mask[i+l], Mask[i]+l))
3719 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
3720 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
3721 /// element of vector 2 and the other elements to come from vector 1 in order.
3722 static bool isCommutedMOVLMask(ArrayRef<int> Mask, EVT VT,
3723 bool V2IsSplat = false, bool V2IsUndef = false) {
3724 unsigned NumOps = VT.getVectorNumElements();
3725 if (VT.getSizeInBits() == 256)
3727 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
3730 if (!isUndefOrEqual(Mask[0], 0))
3733 for (unsigned i = 1; i != NumOps; ++i)
3734 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
3735 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
3736 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
3742 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3743 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
3744 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
3745 static bool isMOVSHDUPMask(ArrayRef<int> Mask, EVT VT,
3746 const X86Subtarget *Subtarget) {
3747 if (!Subtarget->hasSSE3())
3750 unsigned NumElems = VT.getVectorNumElements();
3752 if ((VT.getSizeInBits() == 128 && NumElems != 4) ||
3753 (VT.getSizeInBits() == 256 && NumElems != 8))
3756 // "i+1" is the value the indexed mask element must have
3757 for (unsigned i = 0; i != NumElems; i += 2)
3758 if (!isUndefOrEqual(Mask[i], i+1) ||
3759 !isUndefOrEqual(Mask[i+1], i+1))
3765 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3766 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
3767 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
3768 static bool isMOVSLDUPMask(ArrayRef<int> Mask, EVT VT,
3769 const X86Subtarget *Subtarget) {
3770 if (!Subtarget->hasSSE3())
3773 unsigned NumElems = VT.getVectorNumElements();
3775 if ((VT.getSizeInBits() == 128 && NumElems != 4) ||
3776 (VT.getSizeInBits() == 256 && NumElems != 8))
3779 // "i" is the value the indexed mask element must have
3780 for (unsigned i = 0; i != NumElems; i += 2)
3781 if (!isUndefOrEqual(Mask[i], i) ||
3782 !isUndefOrEqual(Mask[i+1], i))
3788 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
3789 /// specifies a shuffle of elements that is suitable for input to 256-bit
3790 /// version of MOVDDUP.
3791 static bool isMOVDDUPYMask(ArrayRef<int> Mask, EVT VT, bool HasAVX) {
3792 unsigned NumElts = VT.getVectorNumElements();
3794 if (!HasAVX || VT.getSizeInBits() != 256 || NumElts != 4)
3797 for (unsigned i = 0; i != NumElts/2; ++i)
3798 if (!isUndefOrEqual(Mask[i], 0))
3800 for (unsigned i = NumElts/2; i != NumElts; ++i)
3801 if (!isUndefOrEqual(Mask[i], NumElts/2))
3806 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3807 /// specifies a shuffle of elements that is suitable for input to 128-bit
3808 /// version of MOVDDUP.
3809 static bool isMOVDDUPMask(ArrayRef<int> Mask, EVT VT) {
3810 if (VT.getSizeInBits() != 128)
3813 unsigned e = VT.getVectorNumElements() / 2;
3814 for (unsigned i = 0; i != e; ++i)
3815 if (!isUndefOrEqual(Mask[i], i))
3817 for (unsigned i = 0; i != e; ++i)
3818 if (!isUndefOrEqual(Mask[e+i], i))
3823 /// isVEXTRACTF128Index - Return true if the specified
3824 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
3825 /// suitable for input to VEXTRACTF128.
3826 bool X86::isVEXTRACTF128Index(SDNode *N) {
3827 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3830 // The index should be aligned on a 128-bit boundary.
3832 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
3834 unsigned VL = N->getValueType(0).getVectorNumElements();
3835 unsigned VBits = N->getValueType(0).getSizeInBits();
3836 unsigned ElSize = VBits / VL;
3837 bool Result = (Index * ElSize) % 128 == 0;
3842 /// isVINSERTF128Index - Return true if the specified INSERT_SUBVECTOR
3843 /// operand specifies a subvector insert that is suitable for input to
3845 bool X86::isVINSERTF128Index(SDNode *N) {
3846 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
3849 // The index should be aligned on a 128-bit boundary.
3851 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
3853 unsigned VL = N->getValueType(0).getVectorNumElements();
3854 unsigned VBits = N->getValueType(0).getSizeInBits();
3855 unsigned ElSize = VBits / VL;
3856 bool Result = (Index * ElSize) % 128 == 0;
3861 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
3862 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
3863 /// Handles 128-bit and 256-bit.
3864 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
3865 EVT VT = N->getValueType(0);
3867 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3868 "Unsupported vector type for PSHUF/SHUFP");
3870 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
3871 // independently on 128-bit lanes.
3872 unsigned NumElts = VT.getVectorNumElements();
3873 unsigned NumLanes = VT.getSizeInBits()/128;
3874 unsigned NumLaneElts = NumElts/NumLanes;
3876 assert((NumLaneElts == 2 || NumLaneElts == 4) &&
3877 "Only supports 2 or 4 elements per lane");
3879 unsigned Shift = (NumLaneElts == 4) ? 1 : 0;
3881 for (unsigned i = 0; i != NumElts; ++i) {
3882 int Elt = N->getMaskElt(i);
3883 if (Elt < 0) continue;
3885 unsigned ShAmt = i << Shift;
3886 if (ShAmt >= 8) ShAmt -= 8;
3887 Mask |= Elt << ShAmt;
3893 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
3894 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
3895 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
3897 // 8 nodes, but we only care about the last 4.
3898 for (unsigned i = 7; i >= 4; --i) {
3899 int Val = N->getMaskElt(i);
3908 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
3909 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
3910 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
3912 // 8 nodes, but we only care about the first 4.
3913 for (int i = 3; i >= 0; --i) {
3914 int Val = N->getMaskElt(i);
3923 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
3924 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
3925 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
3926 EVT VT = SVOp->getValueType(0);
3927 unsigned EltSize = VT.getVectorElementType().getSizeInBits() >> 3;
3929 unsigned NumElts = VT.getVectorNumElements();
3930 unsigned NumLanes = VT.getSizeInBits()/128;
3931 unsigned NumLaneElts = NumElts/NumLanes;
3935 for (i = 0; i != NumElts; ++i) {
3936 Val = SVOp->getMaskElt(i);
3940 if (Val >= (int)NumElts)
3941 Val -= NumElts - NumLaneElts;
3943 assert(Val - i > 0 && "PALIGNR imm should be positive");
3944 return (Val - i) * EltSize;
3947 /// getExtractVEXTRACTF128Immediate - Return the appropriate immediate
3948 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
3950 unsigned X86::getExtractVEXTRACTF128Immediate(SDNode *N) {
3951 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3952 llvm_unreachable("Illegal extract subvector for VEXTRACTF128");
3955 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
3957 EVT VecVT = N->getOperand(0).getValueType();
3958 EVT ElVT = VecVT.getVectorElementType();
3960 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
3961 return Index / NumElemsPerChunk;
3964 /// getInsertVINSERTF128Immediate - Return the appropriate immediate
3965 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
3967 unsigned X86::getInsertVINSERTF128Immediate(SDNode *N) {
3968 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
3969 llvm_unreachable("Illegal insert subvector for VINSERTF128");
3972 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
3974 EVT VecVT = N->getValueType(0);
3975 EVT ElVT = VecVT.getVectorElementType();
3977 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
3978 return Index / NumElemsPerChunk;
3981 /// getShuffleCLImmediate - Return the appropriate immediate to shuffle
3982 /// the specified VECTOR_SHUFFLE mask with VPERMQ and VPERMPD instructions.
3983 /// Handles 256-bit.
3984 static unsigned getShuffleCLImmediate(ShuffleVectorSDNode *N) {
3985 EVT VT = N->getValueType(0);
3987 unsigned NumElts = VT.getVectorNumElements();
3989 assert((VT.is256BitVector() && NumElts == 4) &&
3990 "Unsupported vector type for VPERMQ/VPERMPD");
3993 for (unsigned i = 0; i != NumElts; ++i) {
3994 int Elt = N->getMaskElt(i);
3997 Mask |= Elt << (i*2);
4002 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4004 bool X86::isZeroNode(SDValue Elt) {
4005 return ((isa<ConstantSDNode>(Elt) &&
4006 cast<ConstantSDNode>(Elt)->isNullValue()) ||
4007 (isa<ConstantFPSDNode>(Elt) &&
4008 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
4011 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
4012 /// their permute mask.
4013 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
4014 SelectionDAG &DAG) {
4015 EVT VT = SVOp->getValueType(0);
4016 unsigned NumElems = VT.getVectorNumElements();
4017 SmallVector<int, 8> MaskVec;
4019 for (unsigned i = 0; i != NumElems; ++i) {
4020 int idx = SVOp->getMaskElt(i);
4022 MaskVec.push_back(idx);
4023 else if (idx < (int)NumElems)
4024 MaskVec.push_back(idx + NumElems);
4026 MaskVec.push_back(idx - NumElems);
4028 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1),
4029 SVOp->getOperand(0), &MaskVec[0]);
4032 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4033 /// match movhlps. The lower half elements should come from upper half of
4034 /// V1 (and in order), and the upper half elements should come from the upper
4035 /// half of V2 (and in order).
4036 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, EVT VT) {
4037 if (VT.getSizeInBits() != 128)
4039 if (VT.getVectorNumElements() != 4)
4041 for (unsigned i = 0, e = 2; i != e; ++i)
4042 if (!isUndefOrEqual(Mask[i], i+2))
4044 for (unsigned i = 2; i != 4; ++i)
4045 if (!isUndefOrEqual(Mask[i], i+4))
4050 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4051 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4053 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
4054 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4056 N = N->getOperand(0).getNode();
4057 if (!ISD::isNON_EXTLoad(N))
4060 *LD = cast<LoadSDNode>(N);
4064 // Test whether the given value is a vector value which will be legalized
4066 static bool WillBeConstantPoolLoad(SDNode *N) {
4067 if (N->getOpcode() != ISD::BUILD_VECTOR)
4070 // Check for any non-constant elements.
4071 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4072 switch (N->getOperand(i).getNode()->getOpcode()) {
4074 case ISD::ConstantFP:
4081 // Vectors of all-zeros and all-ones are materialized with special
4082 // instructions rather than being loaded.
4083 return !ISD::isBuildVectorAllZeros(N) &&
4084 !ISD::isBuildVectorAllOnes(N);
4087 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
4088 /// match movlp{s|d}. The lower half elements should come from lower half of
4089 /// V1 (and in order), and the upper half elements should come from the upper
4090 /// half of V2 (and in order). And since V1 will become the source of the
4091 /// MOVLP, it must be either a vector load or a scalar load to vector.
4092 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
4093 ArrayRef<int> Mask, EVT VT) {
4094 if (VT.getSizeInBits() != 128)
4097 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
4099 // Is V2 is a vector load, don't do this transformation. We will try to use
4100 // load folding shufps op.
4101 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
4104 unsigned NumElems = VT.getVectorNumElements();
4106 if (NumElems != 2 && NumElems != 4)
4108 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4109 if (!isUndefOrEqual(Mask[i], i))
4111 for (unsigned i = NumElems/2; i != NumElems; ++i)
4112 if (!isUndefOrEqual(Mask[i], i+NumElems))
4117 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
4119 static bool isSplatVector(SDNode *N) {
4120 if (N->getOpcode() != ISD::BUILD_VECTOR)
4123 SDValue SplatValue = N->getOperand(0);
4124 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
4125 if (N->getOperand(i) != SplatValue)
4130 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
4131 /// to an zero vector.
4132 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
4133 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
4134 SDValue V1 = N->getOperand(0);
4135 SDValue V2 = N->getOperand(1);
4136 unsigned NumElems = N->getValueType(0).getVectorNumElements();
4137 for (unsigned i = 0; i != NumElems; ++i) {
4138 int Idx = N->getMaskElt(i);
4139 if (Idx >= (int)NumElems) {
4140 unsigned Opc = V2.getOpcode();
4141 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
4143 if (Opc != ISD::BUILD_VECTOR ||
4144 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
4146 } else if (Idx >= 0) {
4147 unsigned Opc = V1.getOpcode();
4148 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
4150 if (Opc != ISD::BUILD_VECTOR ||
4151 !X86::isZeroNode(V1.getOperand(Idx)))
4158 /// getZeroVector - Returns a vector of specified type with all zero elements.
4160 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4161 SelectionDAG &DAG, DebugLoc dl) {
4162 assert(VT.isVector() && "Expected a vector type");
4163 unsigned Size = VT.getSizeInBits();
4165 // Always build SSE zero vectors as <4 x i32> bitcasted
4166 // to their dest type. This ensures they get CSE'd.
4168 if (Size == 128) { // SSE
4169 if (Subtarget->hasSSE2()) { // SSE2
4170 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4171 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4173 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4174 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4176 } else if (Size == 256) { // AVX
4177 if (Subtarget->hasAVX2()) { // AVX2
4178 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4179 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4180 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8);
4182 // 256-bit logic and arithmetic instructions in AVX are all
4183 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4184 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4185 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4186 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops, 8);
4189 llvm_unreachable("Unexpected vector type");
4191 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4194 /// getOnesVector - Returns a vector of specified type with all bits set.
4195 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4196 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4197 /// Then bitcast to their original type, ensuring they get CSE'd.
4198 static SDValue getOnesVector(EVT VT, bool HasAVX2, SelectionDAG &DAG,
4200 assert(VT.isVector() && "Expected a vector type");
4201 unsigned Size = VT.getSizeInBits();
4203 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
4206 if (HasAVX2) { // AVX2
4207 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4208 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8);
4210 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4211 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4213 } else if (Size == 128) {
4214 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4216 llvm_unreachable("Unexpected vector type");
4218 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4221 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
4222 /// that point to V2 points to its first element.
4223 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
4224 for (unsigned i = 0; i != NumElems; ++i) {
4225 if (Mask[i] > (int)NumElems) {
4231 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4232 /// operation of specified width.
4233 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4235 unsigned NumElems = VT.getVectorNumElements();
4236 SmallVector<int, 8> Mask;
4237 Mask.push_back(NumElems);
4238 for (unsigned i = 1; i != NumElems; ++i)
4240 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4243 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4244 static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4246 unsigned NumElems = VT.getVectorNumElements();
4247 SmallVector<int, 8> Mask;
4248 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4250 Mask.push_back(i + NumElems);
4252 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4255 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4256 static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4258 unsigned NumElems = VT.getVectorNumElements();
4259 unsigned Half = NumElems/2;
4260 SmallVector<int, 8> Mask;
4261 for (unsigned i = 0; i != Half; ++i) {
4262 Mask.push_back(i + Half);
4263 Mask.push_back(i + NumElems + Half);
4265 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4268 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
4269 // a generic shuffle instruction because the target has no such instructions.
4270 // Generate shuffles which repeat i16 and i8 several times until they can be
4271 // represented by v4f32 and then be manipulated by target suported shuffles.
4272 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
4273 EVT VT = V.getValueType();
4274 int NumElems = VT.getVectorNumElements();
4275 DebugLoc dl = V.getDebugLoc();
4277 while (NumElems > 4) {
4278 if (EltNo < NumElems/2) {
4279 V = getUnpackl(DAG, dl, VT, V, V);
4281 V = getUnpackh(DAG, dl, VT, V, V);
4282 EltNo -= NumElems/2;
4289 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
4290 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
4291 EVT VT = V.getValueType();
4292 DebugLoc dl = V.getDebugLoc();
4293 unsigned Size = VT.getSizeInBits();
4296 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
4297 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
4298 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
4300 } else if (Size == 256) {
4301 // To use VPERMILPS to splat scalars, the second half of indicies must
4302 // refer to the higher part, which is a duplication of the lower one,
4303 // because VPERMILPS can only handle in-lane permutations.
4304 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
4305 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
4307 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
4308 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
4311 llvm_unreachable("Vector size not supported");
4313 return DAG.getNode(ISD::BITCAST, dl, VT, V);
4316 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
4317 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
4318 EVT SrcVT = SV->getValueType(0);
4319 SDValue V1 = SV->getOperand(0);
4320 DebugLoc dl = SV->getDebugLoc();
4322 int EltNo = SV->getSplatIndex();
4323 int NumElems = SrcVT.getVectorNumElements();
4324 unsigned Size = SrcVT.getSizeInBits();
4326 assert(((Size == 128 && NumElems > 4) || Size == 256) &&
4327 "Unknown how to promote splat for type");
4329 // Extract the 128-bit part containing the splat element and update
4330 // the splat element index when it refers to the higher register.
4332 unsigned Idx = (EltNo >= NumElems/2) ? NumElems/2 : 0;
4333 V1 = Extract128BitVector(V1, Idx, DAG, dl);
4335 EltNo -= NumElems/2;
4338 // All i16 and i8 vector types can't be used directly by a generic shuffle
4339 // instruction because the target has no such instruction. Generate shuffles
4340 // which repeat i16 and i8 several times until they fit in i32, and then can
4341 // be manipulated by target suported shuffles.
4342 EVT EltVT = SrcVT.getVectorElementType();
4343 if (EltVT == MVT::i8 || EltVT == MVT::i16)
4344 V1 = PromoteSplati8i16(V1, DAG, EltNo);
4346 // Recreate the 256-bit vector and place the same 128-bit vector
4347 // into the low and high part. This is necessary because we want
4348 // to use VPERM* to shuffle the vectors
4350 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
4353 return getLegalSplat(DAG, V1, EltNo);
4356 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
4357 /// vector of zero or undef vector. This produces a shuffle where the low
4358 /// element of V2 is swizzled into the zero/undef vector, landing at element
4359 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4360 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4362 const X86Subtarget *Subtarget,
4363 SelectionDAG &DAG) {
4364 EVT VT = V2.getValueType();
4366 ? getZeroVector(VT, Subtarget, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT);
4367 unsigned NumElems = VT.getVectorNumElements();
4368 SmallVector<int, 16> MaskVec;
4369 for (unsigned i = 0; i != NumElems; ++i)
4370 // If this is the insertion idx, put the low elt of V2 here.
4371 MaskVec.push_back(i == Idx ? NumElems : i);
4372 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]);
4375 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
4376 /// target specific opcode. Returns true if the Mask could be calculated.
4377 /// Sets IsUnary to true if only uses one source.
4378 static bool getTargetShuffleMask(SDNode *N, EVT VT,
4379 SmallVectorImpl<int> &Mask, bool &IsUnary) {
4380 unsigned NumElems = VT.getVectorNumElements();
4384 switch(N->getOpcode()) {
4386 ImmN = N->getOperand(N->getNumOperands()-1);
4387 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4389 case X86ISD::UNPCKH:
4390 DecodeUNPCKHMask(VT, Mask);
4392 case X86ISD::UNPCKL:
4393 DecodeUNPCKLMask(VT, Mask);
4395 case X86ISD::MOVHLPS:
4396 DecodeMOVHLPSMask(NumElems, Mask);
4398 case X86ISD::MOVLHPS:
4399 DecodeMOVLHPSMask(NumElems, Mask);
4401 case X86ISD::PSHUFD:
4402 case X86ISD::VPERMILP:
4403 ImmN = N->getOperand(N->getNumOperands()-1);
4404 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4407 case X86ISD::PSHUFHW:
4408 ImmN = N->getOperand(N->getNumOperands()-1);
4409 DecodePSHUFHWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4412 case X86ISD::PSHUFLW:
4413 ImmN = N->getOperand(N->getNumOperands()-1);
4414 DecodePSHUFLWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4418 case X86ISD::MOVSD: {
4419 // The index 0 always comes from the first element of the second source,
4420 // this is why MOVSS and MOVSD are used in the first place. The other
4421 // elements come from the other positions of the first source vector
4422 Mask.push_back(NumElems);
4423 for (unsigned i = 1; i != NumElems; ++i) {
4428 case X86ISD::VPERM2X128:
4429 ImmN = N->getOperand(N->getNumOperands()-1);
4430 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4431 if (Mask.empty()) return false;
4433 case X86ISD::MOVDDUP:
4434 case X86ISD::MOVLHPD:
4435 case X86ISD::MOVLPD:
4436 case X86ISD::MOVLPS:
4437 case X86ISD::MOVSHDUP:
4438 case X86ISD::MOVSLDUP:
4439 case X86ISD::PALIGN:
4440 // Not yet implemented
4442 default: llvm_unreachable("unknown target shuffle node");
4448 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
4449 /// element of the result of the vector shuffle.
4450 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
4453 return SDValue(); // Limit search depth.
4455 SDValue V = SDValue(N, 0);
4456 EVT VT = V.getValueType();
4457 unsigned Opcode = V.getOpcode();
4459 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4460 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4461 int Elt = SV->getMaskElt(Index);
4464 return DAG.getUNDEF(VT.getVectorElementType());
4466 unsigned NumElems = VT.getVectorNumElements();
4467 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
4468 : SV->getOperand(1);
4469 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
4472 // Recurse into target specific vector shuffles to find scalars.
4473 if (isTargetShuffle(Opcode)) {
4474 unsigned NumElems = VT.getVectorNumElements();
4475 SmallVector<int, 16> ShuffleMask;
4479 if (!getTargetShuffleMask(N, VT, ShuffleMask, IsUnary))
4482 int Elt = ShuffleMask[Index];
4484 return DAG.getUNDEF(VT.getVectorElementType());
4486 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
4488 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
4492 // Actual nodes that may contain scalar elements
4493 if (Opcode == ISD::BITCAST) {
4494 V = V.getOperand(0);
4495 EVT SrcVT = V.getValueType();
4496 unsigned NumElems = VT.getVectorNumElements();
4498 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
4502 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
4503 return (Index == 0) ? V.getOperand(0)
4504 : DAG.getUNDEF(VT.getVectorElementType());
4506 if (V.getOpcode() == ISD::BUILD_VECTOR)
4507 return V.getOperand(Index);
4512 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
4513 /// shuffle operation which come from a consecutively from a zero. The
4514 /// search can start in two different directions, from left or right.
4516 unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp, unsigned NumElems,
4517 bool ZerosFromLeft, SelectionDAG &DAG) {
4519 for (i = 0; i != NumElems; ++i) {
4520 unsigned Index = ZerosFromLeft ? i : NumElems-i-1;
4521 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
4522 if (!(Elt.getNode() &&
4523 (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt))))
4530 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
4531 /// correspond consecutively to elements from one of the vector operands,
4532 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
4534 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
4535 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
4536 unsigned NumElems, unsigned &OpNum) {
4537 bool SeenV1 = false;
4538 bool SeenV2 = false;
4540 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
4541 int Idx = SVOp->getMaskElt(i);
4542 // Ignore undef indicies
4546 if (Idx < (int)NumElems)
4551 // Only accept consecutive elements from the same vector
4552 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
4556 OpNum = SeenV1 ? 0 : 1;
4560 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
4561 /// logical left shift of a vector.
4562 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4563 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4564 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4565 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4566 false /* check zeros from right */, DAG);
4572 // Considering the elements in the mask that are not consecutive zeros,
4573 // check if they consecutively come from only one of the source vectors.
4575 // V1 = {X, A, B, C} 0
4577 // vector_shuffle V1, V2 <1, 2, 3, X>
4579 if (!isShuffleMaskConsecutive(SVOp,
4580 0, // Mask Start Index
4581 NumElems-NumZeros, // Mask End Index(exclusive)
4582 NumZeros, // Where to start looking in the src vector
4583 NumElems, // Number of elements in vector
4584 OpSrc)) // Which source operand ?
4589 ShVal = SVOp->getOperand(OpSrc);
4593 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
4594 /// logical left shift of a vector.
4595 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4596 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4597 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4598 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4599 true /* check zeros from left */, DAG);
4605 // Considering the elements in the mask that are not consecutive zeros,
4606 // check if they consecutively come from only one of the source vectors.
4608 // 0 { A, B, X, X } = V2
4610 // vector_shuffle V1, V2 <X, X, 4, 5>
4612 if (!isShuffleMaskConsecutive(SVOp,
4613 NumZeros, // Mask Start Index
4614 NumElems, // Mask End Index(exclusive)
4615 0, // Where to start looking in the src vector
4616 NumElems, // Number of elements in vector
4617 OpSrc)) // Which source operand ?
4622 ShVal = SVOp->getOperand(OpSrc);
4626 /// isVectorShift - Returns true if the shuffle can be implemented as a
4627 /// logical left or right shift of a vector.
4628 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4629 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4630 // Although the logic below support any bitwidth size, there are no
4631 // shift instructions which handle more than 128-bit vectors.
4632 if (SVOp->getValueType(0).getSizeInBits() > 128)
4635 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
4636 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
4642 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
4644 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
4645 unsigned NumNonZero, unsigned NumZero,
4647 const X86Subtarget* Subtarget,
4648 const TargetLowering &TLI) {
4652 DebugLoc dl = Op.getDebugLoc();
4655 for (unsigned i = 0; i < 16; ++i) {
4656 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
4657 if (ThisIsNonZero && First) {
4659 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4661 V = DAG.getUNDEF(MVT::v8i16);
4666 SDValue ThisElt(0, 0), LastElt(0, 0);
4667 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
4668 if (LastIsNonZero) {
4669 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
4670 MVT::i16, Op.getOperand(i-1));
4672 if (ThisIsNonZero) {
4673 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
4674 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
4675 ThisElt, DAG.getConstant(8, MVT::i8));
4677 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
4681 if (ThisElt.getNode())
4682 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
4683 DAG.getIntPtrConstant(i/2));
4687 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
4690 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
4692 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
4693 unsigned NumNonZero, unsigned NumZero,
4695 const X86Subtarget* Subtarget,
4696 const TargetLowering &TLI) {
4700 DebugLoc dl = Op.getDebugLoc();
4703 for (unsigned i = 0; i < 8; ++i) {
4704 bool isNonZero = (NonZeros & (1 << i)) != 0;
4708 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4710 V = DAG.getUNDEF(MVT::v8i16);
4713 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4714 MVT::v8i16, V, Op.getOperand(i),
4715 DAG.getIntPtrConstant(i));
4722 /// getVShift - Return a vector logical shift node.
4724 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
4725 unsigned NumBits, SelectionDAG &DAG,
4726 const TargetLowering &TLI, DebugLoc dl) {
4727 assert(VT.getSizeInBits() == 128 && "Unknown type for VShift");
4728 EVT ShVT = MVT::v2i64;
4729 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
4730 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
4731 return DAG.getNode(ISD::BITCAST, dl, VT,
4732 DAG.getNode(Opc, dl, ShVT, SrcOp,
4733 DAG.getConstant(NumBits,
4734 TLI.getShiftAmountTy(SrcOp.getValueType()))));
4738 X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
4739 SelectionDAG &DAG) const {
4741 // Check if the scalar load can be widened into a vector load. And if
4742 // the address is "base + cst" see if the cst can be "absorbed" into
4743 // the shuffle mask.
4744 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
4745 SDValue Ptr = LD->getBasePtr();
4746 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
4748 EVT PVT = LD->getValueType(0);
4749 if (PVT != MVT::i32 && PVT != MVT::f32)
4754 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
4755 FI = FINode->getIndex();
4757 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
4758 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
4759 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
4760 Offset = Ptr.getConstantOperandVal(1);
4761 Ptr = Ptr.getOperand(0);
4766 // FIXME: 256-bit vector instructions don't require a strict alignment,
4767 // improve this code to support it better.
4768 unsigned RequiredAlign = VT.getSizeInBits()/8;
4769 SDValue Chain = LD->getChain();
4770 // Make sure the stack object alignment is at least 16 or 32.
4771 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4772 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
4773 if (MFI->isFixedObjectIndex(FI)) {
4774 // Can't change the alignment. FIXME: It's possible to compute
4775 // the exact stack offset and reference FI + adjust offset instead.
4776 // If someone *really* cares about this. That's the way to implement it.
4779 MFI->setObjectAlignment(FI, RequiredAlign);
4783 // (Offset % 16 or 32) must be multiple of 4. Then address is then
4784 // Ptr + (Offset & ~15).
4787 if ((Offset % RequiredAlign) & 3)
4789 int64_t StartOffset = Offset & ~(RequiredAlign-1);
4791 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(),
4792 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
4794 int EltNo = (Offset - StartOffset) >> 2;
4795 int NumElems = VT.getVectorNumElements();
4797 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
4798 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
4799 LD->getPointerInfo().getWithOffset(StartOffset),
4800 false, false, false, 0);
4802 SmallVector<int, 8> Mask;
4803 for (int i = 0; i < NumElems; ++i)
4804 Mask.push_back(EltNo);
4806 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
4812 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
4813 /// vector of type 'VT', see if the elements can be replaced by a single large
4814 /// load which has the same value as a build_vector whose operands are 'elts'.
4816 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
4818 /// FIXME: we'd also like to handle the case where the last elements are zero
4819 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
4820 /// There's even a handy isZeroNode for that purpose.
4821 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
4822 DebugLoc &DL, SelectionDAG &DAG) {
4823 EVT EltVT = VT.getVectorElementType();
4824 unsigned NumElems = Elts.size();
4826 LoadSDNode *LDBase = NULL;
4827 unsigned LastLoadedElt = -1U;
4829 // For each element in the initializer, see if we've found a load or an undef.
4830 // If we don't find an initial load element, or later load elements are
4831 // non-consecutive, bail out.
4832 for (unsigned i = 0; i < NumElems; ++i) {
4833 SDValue Elt = Elts[i];
4835 if (!Elt.getNode() ||
4836 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
4839 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
4841 LDBase = cast<LoadSDNode>(Elt.getNode());
4845 if (Elt.getOpcode() == ISD::UNDEF)
4848 LoadSDNode *LD = cast<LoadSDNode>(Elt);
4849 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
4854 // If we have found an entire vector of loads and undefs, then return a large
4855 // load of the entire vector width starting at the base pointer. If we found
4856 // consecutive loads for the low half, generate a vzext_load node.
4857 if (LastLoadedElt == NumElems - 1) {
4858 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
4859 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4860 LDBase->getPointerInfo(),
4861 LDBase->isVolatile(), LDBase->isNonTemporal(),
4862 LDBase->isInvariant(), 0);
4863 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4864 LDBase->getPointerInfo(),
4865 LDBase->isVolatile(), LDBase->isNonTemporal(),
4866 LDBase->isInvariant(), LDBase->getAlignment());
4868 if (NumElems == 4 && LastLoadedElt == 1 &&
4869 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
4870 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
4871 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
4873 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, 2, MVT::i64,
4874 LDBase->getPointerInfo(),
4875 LDBase->getAlignment(),
4876 false/*isVolatile*/, true/*ReadMem*/,
4878 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
4883 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
4884 /// to generate a splat value for the following cases:
4885 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
4886 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
4887 /// a scalar load, or a constant.
4888 /// The VBROADCAST node is returned when a pattern is found,
4889 /// or SDValue() otherwise.
4891 X86TargetLowering::LowerVectorBroadcast(SDValue &Op, SelectionDAG &DAG) const {
4892 if (!Subtarget->hasAVX())
4895 EVT VT = Op.getValueType();
4896 DebugLoc dl = Op.getDebugLoc();
4901 switch (Op.getOpcode()) {
4903 // Unknown pattern found.
4906 case ISD::BUILD_VECTOR: {
4907 // The BUILD_VECTOR node must be a splat.
4908 if (!isSplatVector(Op.getNode()))
4911 Ld = Op.getOperand(0);
4912 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
4913 Ld.getOpcode() == ISD::ConstantFP);
4915 // The suspected load node has several users. Make sure that all
4916 // of its users are from the BUILD_VECTOR node.
4917 // Constants may have multiple users.
4918 if (!ConstSplatVal && !Ld->hasNUsesOfValue(VT.getVectorNumElements(), 0))
4923 case ISD::VECTOR_SHUFFLE: {
4924 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
4926 // Shuffles must have a splat mask where the first element is
4928 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
4931 SDValue Sc = Op.getOperand(0);
4932 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR)
4935 Ld = Sc.getOperand(0);
4936 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
4937 Ld.getOpcode() == ISD::ConstantFP);
4939 // The scalar_to_vector node and the suspected
4940 // load node must have exactly one user.
4941 // Constants may have multiple users.
4942 if (!ConstSplatVal && (!Sc.hasOneUse() || !Ld.hasOneUse()))
4948 bool Is256 = VT.getSizeInBits() == 256;
4949 bool Is128 = VT.getSizeInBits() == 128;
4951 // Handle the broadcasting a single constant scalar from the constant pool
4952 // into a vector. On Sandybridge it is still better to load a constant vector
4953 // from the constant pool and not to broadcast it from a scalar.
4954 if (ConstSplatVal && Subtarget->hasAVX2()) {
4955 EVT CVT = Ld.getValueType();
4956 assert(!CVT.isVector() && "Must not broadcast a vector type");
4957 unsigned ScalarSize = CVT.getSizeInBits();
4959 if ((Is256 && (ScalarSize == 32 || ScalarSize == 64)) ||
4960 (Is128 && (ScalarSize == 32))) {
4962 const Constant *C = 0;
4963 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
4964 C = CI->getConstantIntValue();
4965 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
4966 C = CF->getConstantFPValue();
4968 assert(C && "Invalid constant type");
4970 SDValue CP = DAG.getConstantPool(C, getPointerTy());
4971 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
4972 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
4973 MachinePointerInfo::getConstantPool(),
4974 false, false, false, Alignment);
4976 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
4980 // The scalar source must be a normal load.
4981 if (!ISD::isNormalLoad(Ld.getNode()))
4984 // Reject loads that have uses of the chain result
4985 if (Ld->hasAnyUseOfValue(1))
4988 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
4990 // VBroadcast to YMM
4991 if (Is256 && (ScalarSize == 32 || ScalarSize == 64))
4992 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
4994 // VBroadcast to XMM
4995 if (Is128 && (ScalarSize == 32))
4996 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
4998 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
4999 // double since there is vbroadcastsd xmm
5000 if (Subtarget->hasAVX2() && Ld.getValueType().isInteger()) {
5001 // VBroadcast to YMM
5002 if (Is256 && (ScalarSize == 8 || ScalarSize == 16))
5003 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5005 // VBroadcast to XMM
5006 if (Is128 && (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64))
5007 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5010 // Unsupported broadcast.
5015 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
5016 DebugLoc dl = Op.getDebugLoc();
5018 EVT VT = Op.getValueType();
5019 EVT ExtVT = VT.getVectorElementType();
5020 unsigned NumElems = Op.getNumOperands();
5022 // Vectors containing all zeros can be matched by pxor and xorps later
5023 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5024 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
5025 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
5026 if (VT == MVT::v4i32 || VT == MVT::v8i32)
5029 return getZeroVector(VT, Subtarget, DAG, dl);
5032 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
5033 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
5034 // vpcmpeqd on 256-bit vectors.
5035 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5036 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasAVX2()))
5039 return getOnesVector(VT, Subtarget->hasAVX2(), DAG, dl);
5042 SDValue Broadcast = LowerVectorBroadcast(Op, DAG);
5043 if (Broadcast.getNode())
5046 unsigned EVTBits = ExtVT.getSizeInBits();
5048 unsigned NumZero = 0;
5049 unsigned NumNonZero = 0;
5050 unsigned NonZeros = 0;
5051 bool IsAllConstants = true;
5052 SmallSet<SDValue, 8> Values;
5053 for (unsigned i = 0; i < NumElems; ++i) {
5054 SDValue Elt = Op.getOperand(i);
5055 if (Elt.getOpcode() == ISD::UNDEF)
5058 if (Elt.getOpcode() != ISD::Constant &&
5059 Elt.getOpcode() != ISD::ConstantFP)
5060 IsAllConstants = false;
5061 if (X86::isZeroNode(Elt))
5064 NonZeros |= (1 << i);
5069 // All undef vector. Return an UNDEF. All zero vectors were handled above.
5070 if (NumNonZero == 0)
5071 return DAG.getUNDEF(VT);
5073 // Special case for single non-zero, non-undef, element.
5074 if (NumNonZero == 1) {
5075 unsigned Idx = CountTrailingZeros_32(NonZeros);
5076 SDValue Item = Op.getOperand(Idx);
5078 // If this is an insertion of an i64 value on x86-32, and if the top bits of
5079 // the value are obviously zero, truncate the value to i32 and do the
5080 // insertion that way. Only do this if the value is non-constant or if the
5081 // value is a constant being inserted into element 0. It is cheaper to do
5082 // a constant pool load than it is to do a movd + shuffle.
5083 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
5084 (!IsAllConstants || Idx == 0)) {
5085 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
5087 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
5088 EVT VecVT = MVT::v4i32;
5089 unsigned VecElts = 4;
5091 // Truncate the value (which may itself be a constant) to i32, and
5092 // convert it to a vector with movd (S2V+shuffle to zero extend).
5093 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
5094 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
5095 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5097 // Now we have our 32-bit value zero extended in the low element of
5098 // a vector. If Idx != 0, swizzle it into place.
5100 SmallVector<int, 4> Mask;
5101 Mask.push_back(Idx);
5102 for (unsigned i = 1; i != VecElts; ++i)
5104 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
5107 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5111 // If we have a constant or non-constant insertion into the low element of
5112 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
5113 // the rest of the elements. This will be matched as movd/movq/movss/movsd
5114 // depending on what the source datatype is.
5117 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5119 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
5120 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
5121 if (VT.getSizeInBits() == 256) {
5122 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
5123 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
5124 Item, DAG.getIntPtrConstant(0));
5126 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!");
5127 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5128 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
5129 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5132 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
5133 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
5134 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5135 if (VT.getSizeInBits() == 256) {
5136 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
5137 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
5139 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!");
5140 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5142 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5146 // Is it a vector logical left shift?
5147 if (NumElems == 2 && Idx == 1 &&
5148 X86::isZeroNode(Op.getOperand(0)) &&
5149 !X86::isZeroNode(Op.getOperand(1))) {
5150 unsigned NumBits = VT.getSizeInBits();
5151 return getVShift(true, VT,
5152 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5153 VT, Op.getOperand(1)),
5154 NumBits/2, DAG, *this, dl);
5157 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
5160 // Otherwise, if this is a vector with i32 or f32 elements, and the element
5161 // is a non-constant being inserted into an element other than the low one,
5162 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
5163 // movd/movss) to move this into the low element, then shuffle it into
5165 if (EVTBits == 32) {
5166 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5168 // Turn it into a shuffle of zero and zero-extended scalar to vector.
5169 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
5170 SmallVector<int, 8> MaskVec;
5171 for (unsigned i = 0; i < NumElems; i++)
5172 MaskVec.push_back(i == Idx ? 0 : 1);
5173 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
5177 // Splat is obviously ok. Let legalizer expand it to a shuffle.
5178 if (Values.size() == 1) {
5179 if (EVTBits == 32) {
5180 // Instead of a shuffle like this:
5181 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
5182 // Check if it's possible to issue this instead.
5183 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
5184 unsigned Idx = CountTrailingZeros_32(NonZeros);
5185 SDValue Item = Op.getOperand(Idx);
5186 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
5187 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
5192 // A vector full of immediates; various special cases are already
5193 // handled, so this is best done with a single constant-pool load.
5197 // For AVX-length vectors, build the individual 128-bit pieces and use
5198 // shuffles to put them in place.
5199 if (VT.getSizeInBits() == 256) {
5200 SmallVector<SDValue, 32> V;
5201 for (unsigned i = 0; i != NumElems; ++i)
5202 V.push_back(Op.getOperand(i));
5204 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
5206 // Build both the lower and upper subvector.
5207 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2);
5208 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2],
5211 // Recreate the wider vector with the lower and upper part.
5212 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
5215 // Let legalizer expand 2-wide build_vectors.
5216 if (EVTBits == 64) {
5217 if (NumNonZero == 1) {
5218 // One half is zero or undef.
5219 unsigned Idx = CountTrailingZeros_32(NonZeros);
5220 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
5221 Op.getOperand(Idx));
5222 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
5227 // If element VT is < 32 bits, convert it to inserts into a zero vector.
5228 if (EVTBits == 8 && NumElems == 16) {
5229 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
5231 if (V.getNode()) return V;
5234 if (EVTBits == 16 && NumElems == 8) {
5235 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
5237 if (V.getNode()) return V;
5240 // If element VT is == 32 bits, turn it into a number of shuffles.
5241 SmallVector<SDValue, 8> V(NumElems);
5242 if (NumElems == 4 && NumZero > 0) {
5243 for (unsigned i = 0; i < 4; ++i) {
5244 bool isZero = !(NonZeros & (1 << i));
5246 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
5248 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5251 for (unsigned i = 0; i < 2; ++i) {
5252 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
5255 V[i] = V[i*2]; // Must be a zero vector.
5258 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
5261 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
5264 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
5269 bool Reverse1 = (NonZeros & 0x3) == 2;
5270 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
5274 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
5275 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
5277 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
5280 if (Values.size() > 1 && VT.getSizeInBits() == 128) {
5281 // Check for a build vector of consecutive loads.
5282 for (unsigned i = 0; i < NumElems; ++i)
5283 V[i] = Op.getOperand(i);
5285 // Check for elements which are consecutive loads.
5286 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG);
5290 // For SSE 4.1, use insertps to put the high elements into the low element.
5291 if (getSubtarget()->hasSSE41()) {
5293 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
5294 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
5296 Result = DAG.getUNDEF(VT);
5298 for (unsigned i = 1; i < NumElems; ++i) {
5299 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
5300 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
5301 Op.getOperand(i), DAG.getIntPtrConstant(i));
5306 // Otherwise, expand into a number of unpckl*, start by extending each of
5307 // our (non-undef) elements to the full vector width with the element in the
5308 // bottom slot of the vector (which generates no code for SSE).
5309 for (unsigned i = 0; i < NumElems; ++i) {
5310 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
5311 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5313 V[i] = DAG.getUNDEF(VT);
5316 // Next, we iteratively mix elements, e.g. for v4f32:
5317 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
5318 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
5319 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
5320 unsigned EltStride = NumElems >> 1;
5321 while (EltStride != 0) {
5322 for (unsigned i = 0; i < EltStride; ++i) {
5323 // If V[i+EltStride] is undef and this is the first round of mixing,
5324 // then it is safe to just drop this shuffle: V[i] is already in the
5325 // right place, the one element (since it's the first round) being
5326 // inserted as undef can be dropped. This isn't safe for successive
5327 // rounds because they will permute elements within both vectors.
5328 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
5329 EltStride == NumElems/2)
5332 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
5341 // LowerMMXCONCAT_VECTORS - We support concatenate two MMX registers and place
5342 // them in a MMX register. This is better than doing a stack convert.
5343 static SDValue LowerMMXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5344 DebugLoc dl = Op.getDebugLoc();
5345 EVT ResVT = Op.getValueType();
5347 assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 ||
5348 ResVT == MVT::v8i16 || ResVT == MVT::v16i8);
5350 SDValue InVec = DAG.getNode(ISD::BITCAST,dl, MVT::v1i64, Op.getOperand(0));
5351 SDValue VecOp = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
5352 InVec = Op.getOperand(1);
5353 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
5354 unsigned NumElts = ResVT.getVectorNumElements();
5355 VecOp = DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp);
5356 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp,
5357 InVec.getOperand(0), DAG.getIntPtrConstant(NumElts/2+1));
5359 InVec = DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, InVec);
5360 SDValue VecOp2 = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
5361 Mask[0] = 0; Mask[1] = 2;
5362 VecOp = DAG.getVectorShuffle(MVT::v2i64, dl, VecOp, VecOp2, Mask);
5364 return DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp);
5367 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
5368 // to create 256-bit vectors from two other 128-bit ones.
5369 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5370 DebugLoc dl = Op.getDebugLoc();
5371 EVT ResVT = Op.getValueType();
5373 assert(ResVT.getSizeInBits() == 256 && "Value type must be 256-bit wide");
5375 SDValue V1 = Op.getOperand(0);
5376 SDValue V2 = Op.getOperand(1);
5377 unsigned NumElems = ResVT.getVectorNumElements();
5379 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
5383 X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const {
5384 EVT ResVT = Op.getValueType();
5386 assert(Op.getNumOperands() == 2);
5387 assert((ResVT.getSizeInBits() == 128 || ResVT.getSizeInBits() == 256) &&
5388 "Unsupported CONCAT_VECTORS for value type");
5390 // We support concatenate two MMX registers and place them in a MMX register.
5391 // This is better than doing a stack convert.
5392 if (ResVT.is128BitVector())
5393 return LowerMMXCONCAT_VECTORS(Op, DAG);
5395 // 256-bit AVX can use the vinsertf128 instruction to create 256-bit vectors
5396 // from two other 128-bit ones.
5397 return LowerAVXCONCAT_VECTORS(Op, DAG);
5400 // Try to lower a shuffle node into a simple blend instruction.
5401 static SDValue LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
5402 const X86Subtarget *Subtarget,
5403 SelectionDAG &DAG) {
5404 SDValue V1 = SVOp->getOperand(0);
5405 SDValue V2 = SVOp->getOperand(1);
5406 DebugLoc dl = SVOp->getDebugLoc();
5407 MVT VT = SVOp->getValueType(0).getSimpleVT();
5408 unsigned NumElems = VT.getVectorNumElements();
5410 if (!Subtarget->hasSSE41())
5416 switch (VT.SimpleTy) {
5417 default: return SDValue();
5419 ISDNo = X86ISD::BLENDPW;
5424 ISDNo = X86ISD::BLENDPS;
5429 ISDNo = X86ISD::BLENDPD;
5434 if (!Subtarget->hasAVX())
5436 ISDNo = X86ISD::BLENDPS;
5441 if (!Subtarget->hasAVX())
5443 ISDNo = X86ISD::BLENDPD;
5447 if (!Subtarget->hasAVX2())
5449 ISDNo = X86ISD::BLENDPW;
5453 assert(ISDNo && "Invalid Op Number");
5455 unsigned MaskVals = 0;
5457 for (unsigned i = 0; i != NumElems; ++i) {
5458 int EltIdx = SVOp->getMaskElt(i);
5459 if (EltIdx == (int)i || EltIdx < 0)
5461 else if (EltIdx == (int)(i + NumElems))
5462 continue; // Bit is set to zero;
5467 V1 = DAG.getNode(ISD::BITCAST, dl, OpTy, V1);
5468 V2 = DAG.getNode(ISD::BITCAST, dl, OpTy, V2);
5469 SDValue Ret = DAG.getNode(ISDNo, dl, OpTy, V1, V2,
5470 DAG.getConstant(MaskVals, MVT::i32));
5471 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
5474 // v8i16 shuffles - Prefer shuffles in the following order:
5475 // 1. [all] pshuflw, pshufhw, optional move
5476 // 2. [ssse3] 1 x pshufb
5477 // 3. [ssse3] 2 x pshufb + 1 x por
5478 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
5480 X86TargetLowering::LowerVECTOR_SHUFFLEv8i16(SDValue Op,
5481 SelectionDAG &DAG) const {
5482 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5483 SDValue V1 = SVOp->getOperand(0);
5484 SDValue V2 = SVOp->getOperand(1);
5485 DebugLoc dl = SVOp->getDebugLoc();
5486 SmallVector<int, 8> MaskVals;
5488 // Determine if more than 1 of the words in each of the low and high quadwords
5489 // of the result come from the same quadword of one of the two inputs. Undef
5490 // mask values count as coming from any quadword, for better codegen.
5491 unsigned LoQuad[] = { 0, 0, 0, 0 };
5492 unsigned HiQuad[] = { 0, 0, 0, 0 };
5493 std::bitset<4> InputQuads;
5494 for (unsigned i = 0; i < 8; ++i) {
5495 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
5496 int EltIdx = SVOp->getMaskElt(i);
5497 MaskVals.push_back(EltIdx);
5506 InputQuads.set(EltIdx / 4);
5509 int BestLoQuad = -1;
5510 unsigned MaxQuad = 1;
5511 for (unsigned i = 0; i < 4; ++i) {
5512 if (LoQuad[i] > MaxQuad) {
5514 MaxQuad = LoQuad[i];
5518 int BestHiQuad = -1;
5520 for (unsigned i = 0; i < 4; ++i) {
5521 if (HiQuad[i] > MaxQuad) {
5523 MaxQuad = HiQuad[i];
5527 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
5528 // of the two input vectors, shuffle them into one input vector so only a
5529 // single pshufb instruction is necessary. If There are more than 2 input
5530 // quads, disable the next transformation since it does not help SSSE3.
5531 bool V1Used = InputQuads[0] || InputQuads[1];
5532 bool V2Used = InputQuads[2] || InputQuads[3];
5533 if (Subtarget->hasSSSE3()) {
5534 if (InputQuads.count() == 2 && V1Used && V2Used) {
5535 BestLoQuad = InputQuads[0] ? 0 : 1;
5536 BestHiQuad = InputQuads[2] ? 2 : 3;
5538 if (InputQuads.count() > 2) {
5544 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
5545 // the shuffle mask. If a quad is scored as -1, that means that it contains
5546 // words from all 4 input quadwords.
5548 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
5550 BestLoQuad < 0 ? 0 : BestLoQuad,
5551 BestHiQuad < 0 ? 1 : BestHiQuad
5553 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
5554 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
5555 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
5556 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
5558 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
5559 // source words for the shuffle, to aid later transformations.
5560 bool AllWordsInNewV = true;
5561 bool InOrder[2] = { true, true };
5562 for (unsigned i = 0; i != 8; ++i) {
5563 int idx = MaskVals[i];
5565 InOrder[i/4] = false;
5566 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
5568 AllWordsInNewV = false;
5572 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
5573 if (AllWordsInNewV) {
5574 for (int i = 0; i != 8; ++i) {
5575 int idx = MaskVals[i];
5578 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
5579 if ((idx != i) && idx < 4)
5581 if ((idx != i) && idx > 3)
5590 // If we've eliminated the use of V2, and the new mask is a pshuflw or
5591 // pshufhw, that's as cheap as it gets. Return the new shuffle.
5592 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
5593 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
5594 unsigned TargetMask = 0;
5595 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
5596 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
5597 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
5598 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
5599 getShufflePSHUFLWImmediate(SVOp);
5600 V1 = NewV.getOperand(0);
5601 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
5605 // If we have SSSE3, and all words of the result are from 1 input vector,
5606 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
5607 // is present, fall back to case 4.
5608 if (Subtarget->hasSSSE3()) {
5609 SmallVector<SDValue,16> pshufbMask;
5611 // If we have elements from both input vectors, set the high bit of the
5612 // shuffle mask element to zero out elements that come from V2 in the V1
5613 // mask, and elements that come from V1 in the V2 mask, so that the two
5614 // results can be OR'd together.
5615 bool TwoInputs = V1Used && V2Used;
5616 for (unsigned i = 0; i != 8; ++i) {
5617 int EltIdx = MaskVals[i] * 2;
5618 if (TwoInputs && (EltIdx >= 16)) {
5619 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5620 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5623 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
5624 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8));
5626 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1);
5627 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5628 DAG.getNode(ISD::BUILD_VECTOR, dl,
5629 MVT::v16i8, &pshufbMask[0], 16));
5631 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5633 // Calculate the shuffle mask for the second input, shuffle it, and
5634 // OR it with the first shuffled input.
5636 for (unsigned i = 0; i != 8; ++i) {
5637 int EltIdx = MaskVals[i] * 2;
5639 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5640 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5643 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
5644 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8));
5646 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2);
5647 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
5648 DAG.getNode(ISD::BUILD_VECTOR, dl,
5649 MVT::v16i8, &pshufbMask[0], 16));
5650 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5651 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5654 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
5655 // and update MaskVals with new element order.
5656 std::bitset<8> InOrder;
5657 if (BestLoQuad >= 0) {
5658 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
5659 for (int i = 0; i != 4; ++i) {
5660 int idx = MaskVals[i];
5663 } else if ((idx / 4) == BestLoQuad) {
5668 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5671 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
5672 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
5673 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
5675 getShufflePSHUFLWImmediate(SVOp), DAG);
5679 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
5680 // and update MaskVals with the new element order.
5681 if (BestHiQuad >= 0) {
5682 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
5683 for (unsigned i = 4; i != 8; ++i) {
5684 int idx = MaskVals[i];
5687 } else if ((idx / 4) == BestHiQuad) {
5688 MaskV[i] = (idx & 3) + 4;
5692 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5695 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
5696 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
5697 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
5699 getShufflePSHUFHWImmediate(SVOp), DAG);
5703 // In case BestHi & BestLo were both -1, which means each quadword has a word
5704 // from each of the four input quadwords, calculate the InOrder bitvector now
5705 // before falling through to the insert/extract cleanup.
5706 if (BestLoQuad == -1 && BestHiQuad == -1) {
5708 for (int i = 0; i != 8; ++i)
5709 if (MaskVals[i] < 0 || MaskVals[i] == i)
5713 // The other elements are put in the right place using pextrw and pinsrw.
5714 for (unsigned i = 0; i != 8; ++i) {
5717 int EltIdx = MaskVals[i];
5720 SDValue ExtOp = (EltIdx < 8)
5721 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
5722 DAG.getIntPtrConstant(EltIdx))
5723 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
5724 DAG.getIntPtrConstant(EltIdx - 8));
5725 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
5726 DAG.getIntPtrConstant(i));
5731 // v16i8 shuffles - Prefer shuffles in the following order:
5732 // 1. [ssse3] 1 x pshufb
5733 // 2. [ssse3] 2 x pshufb + 1 x por
5734 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
5736 SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
5738 const X86TargetLowering &TLI) {
5739 SDValue V1 = SVOp->getOperand(0);
5740 SDValue V2 = SVOp->getOperand(1);
5741 DebugLoc dl = SVOp->getDebugLoc();
5742 ArrayRef<int> MaskVals = SVOp->getMask();
5744 // If we have SSSE3, case 1 is generated when all result bytes come from
5745 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
5746 // present, fall back to case 3.
5747 // FIXME: kill V2Only once shuffles are canonizalized by getNode.
5750 for (unsigned i = 0; i < 16; ++i) {
5751 int EltIdx = MaskVals[i];
5760 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
5761 if (TLI.getSubtarget()->hasSSSE3()) {
5762 SmallVector<SDValue,16> pshufbMask;
5764 // If all result elements are from one input vector, then only translate
5765 // undef mask values to 0x80 (zero out result) in the pshufb mask.
5767 // Otherwise, we have elements from both input vectors, and must zero out
5768 // elements that come from V2 in the first mask, and V1 in the second mask
5769 // so that we can OR them together.
5770 bool TwoInputs = !(V1Only || V2Only);
5771 for (unsigned i = 0; i != 16; ++i) {
5772 int EltIdx = MaskVals[i];
5773 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) {
5774 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5777 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
5779 // If all the elements are from V2, assign it to V1 and return after
5780 // building the first pshufb.
5783 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5784 DAG.getNode(ISD::BUILD_VECTOR, dl,
5785 MVT::v16i8, &pshufbMask[0], 16));
5789 // Calculate the shuffle mask for the second input, shuffle it, and
5790 // OR it with the first shuffled input.
5792 for (unsigned i = 0; i != 16; ++i) {
5793 int EltIdx = MaskVals[i];
5795 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5798 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
5800 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
5801 DAG.getNode(ISD::BUILD_VECTOR, dl,
5802 MVT::v16i8, &pshufbMask[0], 16));
5803 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5806 // No SSSE3 - Calculate in place words and then fix all out of place words
5807 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
5808 // the 16 different words that comprise the two doublequadword input vectors.
5809 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5810 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
5811 SDValue NewV = V2Only ? V2 : V1;
5812 for (int i = 0; i != 8; ++i) {
5813 int Elt0 = MaskVals[i*2];
5814 int Elt1 = MaskVals[i*2+1];
5816 // This word of the result is all undef, skip it.
5817 if (Elt0 < 0 && Elt1 < 0)
5820 // This word of the result is already in the correct place, skip it.
5821 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1))
5823 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17))
5826 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
5827 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
5830 // If Elt0 and Elt1 are defined, are consecutive, and can be load
5831 // using a single extract together, load it and store it.
5832 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
5833 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
5834 DAG.getIntPtrConstant(Elt1 / 2));
5835 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
5836 DAG.getIntPtrConstant(i));
5840 // If Elt1 is defined, extract it from the appropriate source. If the
5841 // source byte is not also odd, shift the extracted word left 8 bits
5842 // otherwise clear the bottom 8 bits if we need to do an or.
5844 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
5845 DAG.getIntPtrConstant(Elt1 / 2));
5846 if ((Elt1 & 1) == 0)
5847 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
5849 TLI.getShiftAmountTy(InsElt.getValueType())));
5851 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
5852 DAG.getConstant(0xFF00, MVT::i16));
5854 // If Elt0 is defined, extract it from the appropriate source. If the
5855 // source byte is not also even, shift the extracted word right 8 bits. If
5856 // Elt1 was also defined, OR the extracted values together before
5857 // inserting them in the result.
5859 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
5860 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
5861 if ((Elt0 & 1) != 0)
5862 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
5864 TLI.getShiftAmountTy(InsElt0.getValueType())));
5866 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
5867 DAG.getConstant(0x00FF, MVT::i16));
5868 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
5871 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
5872 DAG.getIntPtrConstant(i));
5874 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
5877 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
5878 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
5879 /// done when every pair / quad of shuffle mask elements point to elements in
5880 /// the right sequence. e.g.
5881 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
5883 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
5884 SelectionDAG &DAG, DebugLoc dl) {
5885 EVT VT = SVOp->getValueType(0);
5886 SDValue V1 = SVOp->getOperand(0);
5887 SDValue V2 = SVOp->getOperand(1);
5888 unsigned NumElems = VT.getVectorNumElements();
5889 unsigned NewWidth = (NumElems == 4) ? 2 : 4;
5891 switch (VT.getSimpleVT().SimpleTy) {
5892 default: llvm_unreachable("Unexpected!");
5893 case MVT::v4f32: NewVT = MVT::v2f64; break;
5894 case MVT::v4i32: NewVT = MVT::v2i64; break;
5895 case MVT::v8i16: NewVT = MVT::v4i32; break;
5896 case MVT::v16i8: NewVT = MVT::v4i32; break;
5899 int Scale = NumElems / NewWidth;
5900 SmallVector<int, 8> MaskVec;
5901 for (unsigned i = 0; i < NumElems; i += Scale) {
5903 for (int j = 0; j < Scale; ++j) {
5904 int EltIdx = SVOp->getMaskElt(i+j);
5908 StartIdx = EltIdx - (EltIdx % Scale);
5909 if (EltIdx != StartIdx + j)
5913 MaskVec.push_back(-1);
5915 MaskVec.push_back(StartIdx / Scale);
5918 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
5919 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
5920 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
5923 /// getVZextMovL - Return a zero-extending vector move low node.
5925 static SDValue getVZextMovL(EVT VT, EVT OpVT,
5926 SDValue SrcOp, SelectionDAG &DAG,
5927 const X86Subtarget *Subtarget, DebugLoc dl) {
5928 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
5929 LoadSDNode *LD = NULL;
5930 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
5931 LD = dyn_cast<LoadSDNode>(SrcOp);
5933 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
5935 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
5936 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
5937 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
5938 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
5939 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
5941 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
5942 return DAG.getNode(ISD::BITCAST, dl, VT,
5943 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
5944 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5952 return DAG.getNode(ISD::BITCAST, dl, VT,
5953 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
5954 DAG.getNode(ISD::BITCAST, dl,
5958 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
5959 /// which could not be matched by any known target speficic shuffle
5961 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
5962 EVT VT = SVOp->getValueType(0);
5964 unsigned NumElems = VT.getVectorNumElements();
5965 unsigned NumLaneElems = NumElems / 2;
5967 DebugLoc dl = SVOp->getDebugLoc();
5968 MVT EltVT = VT.getVectorElementType().getSimpleVT();
5969 EVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
5972 SmallVector<int, 16> Mask;
5973 for (unsigned l = 0; l < 2; ++l) {
5974 // Build a shuffle mask for the output, discovering on the fly which
5975 // input vectors to use as shuffle operands (recorded in InputUsed).
5976 // If building a suitable shuffle vector proves too hard, then bail
5977 // out with useBuildVector set.
5978 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
5979 unsigned LaneStart = l * NumLaneElems;
5980 for (unsigned i = 0; i != NumLaneElems; ++i) {
5981 // The mask element. This indexes into the input.
5982 int Idx = SVOp->getMaskElt(i+LaneStart);
5984 // the mask element does not index into any input vector.
5989 // The input vector this mask element indexes into.
5990 int Input = Idx / NumLaneElems;
5992 // Turn the index into an offset from the start of the input vector.
5993 Idx -= Input * NumLaneElems;
5995 // Find or create a shuffle vector operand to hold this input.
5997 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
5998 if (InputUsed[OpNo] == Input)
5999 // This input vector is already an operand.
6001 if (InputUsed[OpNo] < 0) {
6002 // Create a new operand for this input vector.
6003 InputUsed[OpNo] = Input;
6008 if (OpNo >= array_lengthof(InputUsed)) {
6009 // More than two input vectors used! Give up.
6013 // Add the mask index for the new shuffle vector.
6014 Mask.push_back(Idx + OpNo * NumLaneElems);
6017 if (InputUsed[0] < 0) {
6018 // No input vectors were used! The result is undefined.
6019 Shufs[l] = DAG.getUNDEF(NVT);
6021 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
6022 (InputUsed[0] % 2) * NumLaneElems,
6024 // If only one input was used, use an undefined vector for the other.
6025 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
6026 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
6027 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
6028 // At least one input vector was used. Create a new shuffle vector.
6029 Shufs[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
6035 // Concatenate the result back
6036 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Shufs[0], Shufs[1]);
6039 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
6040 /// 4 elements, and match them with several different shuffle types.
6042 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
6043 SDValue V1 = SVOp->getOperand(0);
6044 SDValue V2 = SVOp->getOperand(1);
6045 DebugLoc dl = SVOp->getDebugLoc();
6046 EVT VT = SVOp->getValueType(0);
6048 assert(VT.getSizeInBits() == 128 && "Unsupported vector size");
6050 std::pair<int, int> Locs[4];
6051 int Mask1[] = { -1, -1, -1, -1 };
6052 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
6056 for (unsigned i = 0; i != 4; ++i) {
6057 int Idx = PermMask[i];
6059 Locs[i] = std::make_pair(-1, -1);
6061 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
6063 Locs[i] = std::make_pair(0, NumLo);
6067 Locs[i] = std::make_pair(1, NumHi);
6069 Mask1[2+NumHi] = Idx;
6075 if (NumLo <= 2 && NumHi <= 2) {
6076 // If no more than two elements come from either vector. This can be
6077 // implemented with two shuffles. First shuffle gather the elements.
6078 // The second shuffle, which takes the first shuffle as both of its
6079 // vector operands, put the elements into the right order.
6080 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6082 int Mask2[] = { -1, -1, -1, -1 };
6084 for (unsigned i = 0; i != 4; ++i)
6085 if (Locs[i].first != -1) {
6086 unsigned Idx = (i < 2) ? 0 : 4;
6087 Idx += Locs[i].first * 2 + Locs[i].second;
6091 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
6094 if (NumLo == 3 || NumHi == 3) {
6095 // Otherwise, we must have three elements from one vector, call it X, and
6096 // one element from the other, call it Y. First, use a shufps to build an
6097 // intermediate vector with the one element from Y and the element from X
6098 // that will be in the same half in the final destination (the indexes don't
6099 // matter). Then, use a shufps to build the final vector, taking the half
6100 // containing the element from Y from the intermediate, and the other half
6103 // Normalize it so the 3 elements come from V1.
6104 CommuteVectorShuffleMask(PermMask, 4);
6108 // Find the element from V2.
6110 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
6111 int Val = PermMask[HiIndex];
6118 Mask1[0] = PermMask[HiIndex];
6120 Mask1[2] = PermMask[HiIndex^1];
6122 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6125 Mask1[0] = PermMask[0];
6126 Mask1[1] = PermMask[1];
6127 Mask1[2] = HiIndex & 1 ? 6 : 4;
6128 Mask1[3] = HiIndex & 1 ? 4 : 6;
6129 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6132 Mask1[0] = HiIndex & 1 ? 2 : 0;
6133 Mask1[1] = HiIndex & 1 ? 0 : 2;
6134 Mask1[2] = PermMask[2];
6135 Mask1[3] = PermMask[3];
6140 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
6143 // Break it into (shuffle shuffle_hi, shuffle_lo).
6144 int LoMask[] = { -1, -1, -1, -1 };
6145 int HiMask[] = { -1, -1, -1, -1 };
6147 int *MaskPtr = LoMask;
6148 unsigned MaskIdx = 0;
6151 for (unsigned i = 0; i != 4; ++i) {
6158 int Idx = PermMask[i];
6160 Locs[i] = std::make_pair(-1, -1);
6161 } else if (Idx < 4) {
6162 Locs[i] = std::make_pair(MaskIdx, LoIdx);
6163 MaskPtr[LoIdx] = Idx;
6166 Locs[i] = std::make_pair(MaskIdx, HiIdx);
6167 MaskPtr[HiIdx] = Idx;
6172 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
6173 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
6174 int MaskOps[] = { -1, -1, -1, -1 };
6175 for (unsigned i = 0; i != 4; ++i)
6176 if (Locs[i].first != -1)
6177 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
6178 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
6181 static bool MayFoldVectorLoad(SDValue V) {
6182 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6183 V = V.getOperand(0);
6184 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6185 V = V.getOperand(0);
6186 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
6187 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
6188 // BUILD_VECTOR (load), undef
6189 V = V.getOperand(0);
6195 // FIXME: the version above should always be used. Since there's
6196 // a bug where several vector shuffles can't be folded because the
6197 // DAG is not updated during lowering and a node claims to have two
6198 // uses while it only has one, use this version, and let isel match
6199 // another instruction if the load really happens to have more than
6200 // one use. Remove this version after this bug get fixed.
6201 // rdar://8434668, PR8156
6202 static bool RelaxedMayFoldVectorLoad(SDValue V) {
6203 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6204 V = V.getOperand(0);
6205 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6206 V = V.getOperand(0);
6207 if (ISD::isNormalLoad(V.getNode()))
6213 SDValue getMOVDDup(SDValue &Op, DebugLoc &dl, SDValue V1, SelectionDAG &DAG) {
6214 EVT VT = Op.getValueType();
6216 // Canonizalize to v2f64.
6217 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
6218 return DAG.getNode(ISD::BITCAST, dl, VT,
6219 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
6224 SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG,
6226 SDValue V1 = Op.getOperand(0);
6227 SDValue V2 = Op.getOperand(1);
6228 EVT VT = Op.getValueType();
6230 assert(VT != MVT::v2i64 && "unsupported shuffle type");
6232 if (HasSSE2 && VT == MVT::v2f64)
6233 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
6235 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
6236 return DAG.getNode(ISD::BITCAST, dl, VT,
6237 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
6238 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
6239 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
6243 SDValue getMOVHighToLow(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG) {
6244 SDValue V1 = Op.getOperand(0);
6245 SDValue V2 = Op.getOperand(1);
6246 EVT VT = Op.getValueType();
6248 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
6249 "unsupported shuffle type");
6251 if (V2.getOpcode() == ISD::UNDEF)
6255 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
6259 SDValue getMOVLP(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
6260 SDValue V1 = Op.getOperand(0);
6261 SDValue V2 = Op.getOperand(1);
6262 EVT VT = Op.getValueType();
6263 unsigned NumElems = VT.getVectorNumElements();
6265 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
6266 // operand of these instructions is only memory, so check if there's a
6267 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
6269 bool CanFoldLoad = false;
6271 // Trivial case, when V2 comes from a load.
6272 if (MayFoldVectorLoad(V2))
6275 // When V1 is a load, it can be folded later into a store in isel, example:
6276 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
6278 // (MOVLPSmr addr:$src1, VR128:$src2)
6279 // So, recognize this potential and also use MOVLPS or MOVLPD
6280 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
6283 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6285 if (HasSSE2 && NumElems == 2)
6286 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
6289 // If we don't care about the second element, procede to use movss.
6290 if (SVOp->getMaskElt(1) != -1)
6291 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
6294 // movl and movlp will both match v2i64, but v2i64 is never matched by
6295 // movl earlier because we make it strict to avoid messing with the movlp load
6296 // folding logic (see the code above getMOVLP call). Match it here then,
6297 // this is horrible, but will stay like this until we move all shuffle
6298 // matching to x86 specific nodes. Note that for the 1st condition all
6299 // types are matched with movsd.
6301 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
6302 // as to remove this logic from here, as much as possible
6303 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
6304 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6305 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6308 assert(VT != MVT::v4i32 && "unsupported shuffle type");
6310 // Invert the operand order and use SHUFPS to match it.
6311 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
6312 getShuffleSHUFImmediate(SVOp), DAG);
6316 X86TargetLowering::NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG) const {
6317 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6318 EVT VT = Op.getValueType();
6319 DebugLoc dl = Op.getDebugLoc();
6320 SDValue V1 = Op.getOperand(0);
6321 SDValue V2 = Op.getOperand(1);
6323 if (isZeroShuffle(SVOp))
6324 return getZeroVector(VT, Subtarget, DAG, dl);
6326 // Handle splat operations
6327 if (SVOp->isSplat()) {
6328 unsigned NumElem = VT.getVectorNumElements();
6329 int Size = VT.getSizeInBits();
6331 // Use vbroadcast whenever the splat comes from a foldable load
6332 SDValue Broadcast = LowerVectorBroadcast(Op, DAG);
6333 if (Broadcast.getNode())
6336 // Handle splats by matching through known shuffle masks
6337 if ((Size == 128 && NumElem <= 4) ||
6338 (Size == 256 && NumElem < 8))
6341 // All remaning splats are promoted to target supported vector shuffles.
6342 return PromoteSplat(SVOp, DAG);
6345 // If the shuffle can be profitably rewritten as a narrower shuffle, then
6347 if (VT == MVT::v8i16 || VT == MVT::v16i8) {
6348 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6349 if (NewOp.getNode())
6350 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
6351 } else if ((VT == MVT::v4i32 ||
6352 (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
6353 // FIXME: Figure out a cleaner way to do this.
6354 // Try to make use of movq to zero out the top part.
6355 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
6356 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6357 if (NewOp.getNode()) {
6358 EVT NewVT = NewOp.getValueType();
6359 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
6360 NewVT, true, false))
6361 return getVZextMovL(VT, NewVT, NewOp.getOperand(0),
6362 DAG, Subtarget, dl);
6364 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
6365 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6366 if (NewOp.getNode()) {
6367 EVT NewVT = NewOp.getValueType();
6368 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
6369 return getVZextMovL(VT, NewVT, NewOp.getOperand(1),
6370 DAG, Subtarget, dl);
6378 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
6379 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6380 SDValue V1 = Op.getOperand(0);
6381 SDValue V2 = Op.getOperand(1);
6382 EVT VT = Op.getValueType();
6383 DebugLoc dl = Op.getDebugLoc();
6384 unsigned NumElems = VT.getVectorNumElements();
6385 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
6386 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
6387 bool V1IsSplat = false;
6388 bool V2IsSplat = false;
6389 bool HasSSE2 = Subtarget->hasSSE2();
6390 bool HasAVX = Subtarget->hasAVX();
6391 bool HasAVX2 = Subtarget->hasAVX2();
6392 MachineFunction &MF = DAG.getMachineFunction();
6393 bool OptForSize = MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize);
6395 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
6397 if (V1IsUndef && V2IsUndef)
6398 return DAG.getUNDEF(VT);
6400 assert(!V1IsUndef && "Op 1 of shuffle should not be undef");
6402 // Vector shuffle lowering takes 3 steps:
6404 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
6405 // narrowing and commutation of operands should be handled.
6406 // 2) Matching of shuffles with known shuffle masks to x86 target specific
6408 // 3) Rewriting of unmatched masks into new generic shuffle operations,
6409 // so the shuffle can be broken into other shuffles and the legalizer can
6410 // try the lowering again.
6412 // The general idea is that no vector_shuffle operation should be left to
6413 // be matched during isel, all of them must be converted to a target specific
6416 // Normalize the input vectors. Here splats, zeroed vectors, profitable
6417 // narrowing and commutation of operands should be handled. The actual code
6418 // doesn't include all of those, work in progress...
6419 SDValue NewOp = NormalizeVectorShuffle(Op, DAG);
6420 if (NewOp.getNode())
6423 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
6425 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
6426 // unpckh_undef). Only use pshufd if speed is more important than size.
6427 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasAVX2))
6428 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6429 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasAVX2))
6430 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6432 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
6433 V2IsUndef && RelaxedMayFoldVectorLoad(V1))
6434 return getMOVDDup(Op, dl, V1, DAG);
6436 if (isMOVHLPS_v_undef_Mask(M, VT))
6437 return getMOVHighToLow(Op, dl, DAG);
6439 // Use to match splats
6440 if (HasSSE2 && isUNPCKHMask(M, VT, HasAVX2) && V2IsUndef &&
6441 (VT == MVT::v2f64 || VT == MVT::v2i64))
6442 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6444 if (isPSHUFDMask(M, VT)) {
6445 // The actual implementation will match the mask in the if above and then
6446 // during isel it can match several different instructions, not only pshufd
6447 // as its name says, sad but true, emulate the behavior for now...
6448 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
6449 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
6451 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
6453 if (HasAVX && (VT == MVT::v4f32 || VT == MVT::v2f64))
6454 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, TargetMask, DAG);
6456 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
6457 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
6459 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
6463 // Check if this can be converted into a logical shift.
6464 bool isLeft = false;
6467 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
6468 if (isShift && ShVal.hasOneUse()) {
6469 // If the shifted value has multiple uses, it may be cheaper to use
6470 // v_set0 + movlhps or movhlps, etc.
6471 EVT EltVT = VT.getVectorElementType();
6472 ShAmt *= EltVT.getSizeInBits();
6473 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6476 if (isMOVLMask(M, VT)) {
6477 if (ISD::isBuildVectorAllZeros(V1.getNode()))
6478 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
6479 if (!isMOVLPMask(M, VT)) {
6480 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
6481 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6483 if (VT == MVT::v4i32 || VT == MVT::v4f32)
6484 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6488 // FIXME: fold these into legal mask.
6489 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasAVX2))
6490 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
6492 if (isMOVHLPSMask(M, VT))
6493 return getMOVHighToLow(Op, dl, DAG);
6495 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
6496 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
6498 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
6499 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
6501 if (isMOVLPMask(M, VT))
6502 return getMOVLP(Op, dl, DAG, HasSSE2);
6504 if (ShouldXformToMOVHLPS(M, VT) ||
6505 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
6506 return CommuteVectorShuffle(SVOp, DAG);
6509 // No better options. Use a vshldq / vsrldq.
6510 EVT EltVT = VT.getVectorElementType();
6511 ShAmt *= EltVT.getSizeInBits();
6512 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6515 bool Commuted = false;
6516 // FIXME: This should also accept a bitcast of a splat? Be careful, not
6517 // 1,1,1,1 -> v8i16 though.
6518 V1IsSplat = isSplatVector(V1.getNode());
6519 V2IsSplat = isSplatVector(V2.getNode());
6521 // Canonicalize the splat or undef, if present, to be on the RHS.
6522 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
6523 CommuteVectorShuffleMask(M, NumElems);
6525 std::swap(V1IsSplat, V2IsSplat);
6529 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
6530 // Shuffling low element of v1 into undef, just return v1.
6533 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
6534 // the instruction selector will not match, so get a canonical MOVL with
6535 // swapped operands to undo the commute.
6536 return getMOVL(DAG, dl, VT, V2, V1);
6539 if (isUNPCKLMask(M, VT, HasAVX2))
6540 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
6542 if (isUNPCKHMask(M, VT, HasAVX2))
6543 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
6546 // Normalize mask so all entries that point to V2 points to its first
6547 // element then try to match unpck{h|l} again. If match, return a
6548 // new vector_shuffle with the corrected mask.p
6549 SmallVector<int, 8> NewMask(M.begin(), M.end());
6550 NormalizeMask(NewMask, NumElems);
6551 if (isUNPCKLMask(NewMask, VT, HasAVX2, true))
6552 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
6553 if (isUNPCKHMask(NewMask, VT, HasAVX2, true))
6554 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
6558 // Commute is back and try unpck* again.
6559 // FIXME: this seems wrong.
6560 CommuteVectorShuffleMask(M, NumElems);
6562 std::swap(V1IsSplat, V2IsSplat);
6565 if (isUNPCKLMask(M, VT, HasAVX2))
6566 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
6568 if (isUNPCKHMask(M, VT, HasAVX2))
6569 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
6572 // Normalize the node to match x86 shuffle ops if needed
6573 if (!V2IsUndef && (isSHUFPMask(M, VT, HasAVX, /* Commuted */ true)))
6574 return CommuteVectorShuffle(SVOp, DAG);
6576 // The checks below are all present in isShuffleMaskLegal, but they are
6577 // inlined here right now to enable us to directly emit target specific
6578 // nodes, and remove one by one until they don't return Op anymore.
6580 if (isPALIGNRMask(M, VT, Subtarget))
6581 return getTargetShuffleNode(X86ISD::PALIGN, dl, VT, V1, V2,
6582 getShufflePALIGNRImmediate(SVOp),
6585 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
6586 SVOp->getSplatIndex() == 0 && V2IsUndef) {
6587 if (VT == MVT::v2f64 || VT == MVT::v2i64)
6588 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6591 if (isPSHUFHWMask(M, VT))
6592 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
6593 getShufflePSHUFHWImmediate(SVOp),
6596 if (isPSHUFLWMask(M, VT))
6597 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
6598 getShufflePSHUFLWImmediate(SVOp),
6601 if (isSHUFPMask(M, VT, HasAVX))
6602 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
6603 getShuffleSHUFImmediate(SVOp), DAG);
6605 if (isUNPCKL_v_undef_Mask(M, VT, HasAVX2))
6606 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6607 if (isUNPCKH_v_undef_Mask(M, VT, HasAVX2))
6608 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6610 //===--------------------------------------------------------------------===//
6611 // Generate target specific nodes for 128 or 256-bit shuffles only
6612 // supported in the AVX instruction set.
6615 // Handle VMOVDDUPY permutations
6616 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasAVX))
6617 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
6619 // Handle VPERMILPS/D* permutations
6620 if (isVPERMILPMask(M, VT, HasAVX)) {
6621 if (HasAVX2 && VT == MVT::v8i32)
6622 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
6623 getShuffleSHUFImmediate(SVOp), DAG);
6624 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1,
6625 getShuffleSHUFImmediate(SVOp), DAG);
6628 // Handle VPERM2F128/VPERM2I128 permutations
6629 if (isVPERM2X128Mask(M, VT, HasAVX))
6630 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
6631 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
6633 SDValue BlendOp = LowerVECTOR_SHUFFLEtoBlend(SVOp, Subtarget, DAG);
6634 if (BlendOp.getNode())
6637 if (V2IsUndef && HasAVX2 && (VT == MVT::v8i32 || VT == MVT::v8f32)) {
6638 SmallVector<SDValue, 8> permclMask;
6639 for (unsigned i = 0; i != 8; ++i) {
6640 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MVT::i32));
6642 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32,
6644 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
6645 return DAG.getNode(X86ISD::VPERMV, dl, VT,
6646 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
6649 if (V2IsUndef && HasAVX2 && (VT == MVT::v4i64 || VT == MVT::v4f64))
6650 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1,
6651 getShuffleCLImmediate(SVOp), DAG);
6654 //===--------------------------------------------------------------------===//
6655 // Since no target specific shuffle was selected for this generic one,
6656 // lower it into other known shuffles. FIXME: this isn't true yet, but
6657 // this is the plan.
6660 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
6661 if (VT == MVT::v8i16) {
6662 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, DAG);
6663 if (NewOp.getNode())
6667 if (VT == MVT::v16i8) {
6668 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this);
6669 if (NewOp.getNode())
6673 // Handle all 128-bit wide vectors with 4 elements, and match them with
6674 // several different shuffle types.
6675 if (NumElems == 4 && VT.getSizeInBits() == 128)
6676 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
6678 // Handle general 256-bit shuffles
6679 if (VT.is256BitVector())
6680 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
6686 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
6687 SelectionDAG &DAG) const {
6688 EVT VT = Op.getValueType();
6689 DebugLoc dl = Op.getDebugLoc();
6691 if (Op.getOperand(0).getValueType().getSizeInBits() != 128)
6694 if (VT.getSizeInBits() == 8) {
6695 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
6696 Op.getOperand(0), Op.getOperand(1));
6697 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
6698 DAG.getValueType(VT));
6699 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6702 if (VT.getSizeInBits() == 16) {
6703 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6704 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
6706 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
6707 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6708 DAG.getNode(ISD::BITCAST, dl,
6712 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
6713 Op.getOperand(0), Op.getOperand(1));
6714 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
6715 DAG.getValueType(VT));
6716 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6719 if (VT == MVT::f32) {
6720 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
6721 // the result back to FR32 register. It's only worth matching if the
6722 // result has a single use which is a store or a bitcast to i32. And in
6723 // the case of a store, it's not worth it if the index is a constant 0,
6724 // because a MOVSSmr can be used instead, which is smaller and faster.
6725 if (!Op.hasOneUse())
6727 SDNode *User = *Op.getNode()->use_begin();
6728 if ((User->getOpcode() != ISD::STORE ||
6729 (isa<ConstantSDNode>(Op.getOperand(1)) &&
6730 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
6731 (User->getOpcode() != ISD::BITCAST ||
6732 User->getValueType(0) != MVT::i32))
6734 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6735 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
6738 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
6741 if (VT == MVT::i32 || VT == MVT::i64) {
6742 // ExtractPS/pextrq works with constant index.
6743 if (isa<ConstantSDNode>(Op.getOperand(1)))
6751 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
6752 SelectionDAG &DAG) const {
6753 if (!isa<ConstantSDNode>(Op.getOperand(1)))
6756 SDValue Vec = Op.getOperand(0);
6757 EVT VecVT = Vec.getValueType();
6759 // If this is a 256-bit vector result, first extract the 128-bit vector and
6760 // then extract the element from the 128-bit vector.
6761 if (VecVT.getSizeInBits() == 256) {
6762 DebugLoc dl = Op.getNode()->getDebugLoc();
6763 unsigned NumElems = VecVT.getVectorNumElements();
6764 SDValue Idx = Op.getOperand(1);
6765 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
6767 // Get the 128-bit vector.
6768 bool Upper = IdxVal >= NumElems/2;
6769 Vec = Extract128BitVector(Vec, Upper ? NumElems/2 : 0, DAG, dl);
6771 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
6772 Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : Idx);
6775 assert(Vec.getValueSizeInBits() <= 128 && "Unexpected vector length");
6777 if (Subtarget->hasSSE41()) {
6778 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
6783 EVT VT = Op.getValueType();
6784 DebugLoc dl = Op.getDebugLoc();
6785 // TODO: handle v16i8.
6786 if (VT.getSizeInBits() == 16) {
6787 SDValue Vec = Op.getOperand(0);
6788 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6790 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
6791 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6792 DAG.getNode(ISD::BITCAST, dl,
6795 // Transform it so it match pextrw which produces a 32-bit result.
6796 EVT EltVT = MVT::i32;
6797 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
6798 Op.getOperand(0), Op.getOperand(1));
6799 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
6800 DAG.getValueType(VT));
6801 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6804 if (VT.getSizeInBits() == 32) {
6805 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6809 // SHUFPS the element to the lowest double word, then movss.
6810 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
6811 EVT VVT = Op.getOperand(0).getValueType();
6812 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
6813 DAG.getUNDEF(VVT), Mask);
6814 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
6815 DAG.getIntPtrConstant(0));
6818 if (VT.getSizeInBits() == 64) {
6819 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
6820 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
6821 // to match extract_elt for f64.
6822 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6826 // UNPCKHPD the element to the lowest double word, then movsd.
6827 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
6828 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
6829 int Mask[2] = { 1, -1 };
6830 EVT VVT = Op.getOperand(0).getValueType();
6831 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
6832 DAG.getUNDEF(VVT), Mask);
6833 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
6834 DAG.getIntPtrConstant(0));
6841 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op,
6842 SelectionDAG &DAG) const {
6843 EVT VT = Op.getValueType();
6844 EVT EltVT = VT.getVectorElementType();
6845 DebugLoc dl = Op.getDebugLoc();
6847 SDValue N0 = Op.getOperand(0);
6848 SDValue N1 = Op.getOperand(1);
6849 SDValue N2 = Op.getOperand(2);
6851 if (VT.getSizeInBits() == 256)
6854 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
6855 isa<ConstantSDNode>(N2)) {
6857 if (VT == MVT::v8i16)
6858 Opc = X86ISD::PINSRW;
6859 else if (VT == MVT::v16i8)
6860 Opc = X86ISD::PINSRB;
6862 Opc = X86ISD::PINSRB;
6864 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
6866 if (N1.getValueType() != MVT::i32)
6867 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
6868 if (N2.getValueType() != MVT::i32)
6869 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
6870 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
6873 if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
6874 // Bits [7:6] of the constant are the source select. This will always be
6875 // zero here. The DAG Combiner may combine an extract_elt index into these
6876 // bits. For example (insert (extract, 3), 2) could be matched by putting
6877 // the '3' into bits [7:6] of X86ISD::INSERTPS.
6878 // Bits [5:4] of the constant are the destination select. This is the
6879 // value of the incoming immediate.
6880 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
6881 // combine either bitwise AND or insert of float 0.0 to set these bits.
6882 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
6883 // Create this as a scalar to vector..
6884 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
6885 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
6888 if ((EltVT == MVT::i32 || EltVT == MVT::i64) && isa<ConstantSDNode>(N2)) {
6889 // PINSR* works with constant index.
6896 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
6897 EVT VT = Op.getValueType();
6898 EVT EltVT = VT.getVectorElementType();
6900 DebugLoc dl = Op.getDebugLoc();
6901 SDValue N0 = Op.getOperand(0);
6902 SDValue N1 = Op.getOperand(1);
6903 SDValue N2 = Op.getOperand(2);
6905 // If this is a 256-bit vector result, first extract the 128-bit vector,
6906 // insert the element into the extracted half and then place it back.
6907 if (VT.getSizeInBits() == 256) {
6908 if (!isa<ConstantSDNode>(N2))
6911 // Get the desired 128-bit vector half.
6912 unsigned NumElems = VT.getVectorNumElements();
6913 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue();
6914 bool Upper = IdxVal >= NumElems/2;
6915 unsigned Ins128Idx = Upper ? NumElems/2 : 0;
6916 SDValue V = Extract128BitVector(N0, Ins128Idx, DAG, dl);
6918 // Insert the element into the desired half.
6919 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V,
6920 N1, Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : N2);
6922 // Insert the changed part back to the 256-bit vector
6923 return Insert128BitVector(N0, V, Ins128Idx, DAG, dl);
6926 if (Subtarget->hasSSE41())
6927 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
6929 if (EltVT == MVT::i8)
6932 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
6933 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
6934 // as its second argument.
6935 if (N1.getValueType() != MVT::i32)
6936 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
6937 if (N2.getValueType() != MVT::i32)
6938 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
6939 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
6945 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6946 LLVMContext *Context = DAG.getContext();
6947 DebugLoc dl = Op.getDebugLoc();
6948 EVT OpVT = Op.getValueType();
6950 // If this is a 256-bit vector result, first insert into a 128-bit
6951 // vector and then insert into the 256-bit vector.
6952 if (OpVT.getSizeInBits() > 128) {
6953 // Insert into a 128-bit vector.
6954 EVT VT128 = EVT::getVectorVT(*Context,
6955 OpVT.getVectorElementType(),
6956 OpVT.getVectorNumElements() / 2);
6958 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
6960 // Insert the 128-bit vector.
6961 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
6964 if (Op.getValueType() == MVT::v1i64 &&
6965 Op.getOperand(0).getValueType() == MVT::i64)
6966 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
6968 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
6969 assert(Op.getValueType().getSimpleVT().getSizeInBits() == 128 &&
6970 "Expected an SSE type!");
6971 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(),
6972 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
6975 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
6976 // a simple subregister reference or explicit instructions to grab
6977 // upper bits of a vector.
6979 X86TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const {
6980 if (Subtarget->hasAVX()) {
6981 DebugLoc dl = Op.getNode()->getDebugLoc();
6982 SDValue Vec = Op.getNode()->getOperand(0);
6983 SDValue Idx = Op.getNode()->getOperand(1);
6985 if (Op.getNode()->getValueType(0).getSizeInBits() == 128 &&
6986 Vec.getNode()->getValueType(0).getSizeInBits() == 256 &&
6987 isa<ConstantSDNode>(Idx)) {
6988 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
6989 return Extract128BitVector(Vec, IdxVal, DAG, dl);
6995 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
6996 // simple superregister reference or explicit instructions to insert
6997 // the upper bits of a vector.
6999 X86TargetLowering::LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const {
7000 if (Subtarget->hasAVX()) {
7001 DebugLoc dl = Op.getNode()->getDebugLoc();
7002 SDValue Vec = Op.getNode()->getOperand(0);
7003 SDValue SubVec = Op.getNode()->getOperand(1);
7004 SDValue Idx = Op.getNode()->getOperand(2);
7006 if (Op.getNode()->getValueType(0).getSizeInBits() == 256 &&
7007 SubVec.getNode()->getValueType(0).getSizeInBits() == 128 &&
7008 isa<ConstantSDNode>(Idx)) {
7009 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7010 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
7016 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
7017 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
7018 // one of the above mentioned nodes. It has to be wrapped because otherwise
7019 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
7020 // be used to form addressing mode. These wrapped nodes will be selected
7023 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
7024 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
7026 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7028 unsigned char OpFlag = 0;
7029 unsigned WrapperKind = X86ISD::Wrapper;
7030 CodeModel::Model M = getTargetMachine().getCodeModel();
7032 if (Subtarget->isPICStyleRIPRel() &&
7033 (M == CodeModel::Small || M == CodeModel::Kernel))
7034 WrapperKind = X86ISD::WrapperRIP;
7035 else if (Subtarget->isPICStyleGOT())
7036 OpFlag = X86II::MO_GOTOFF;
7037 else if (Subtarget->isPICStyleStubPIC())
7038 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7040 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
7042 CP->getOffset(), OpFlag);
7043 DebugLoc DL = CP->getDebugLoc();
7044 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7045 // With PIC, the address is actually $g + Offset.
7047 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7048 DAG.getNode(X86ISD::GlobalBaseReg,
7049 DebugLoc(), getPointerTy()),
7056 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
7057 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
7059 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7061 unsigned char OpFlag = 0;
7062 unsigned WrapperKind = X86ISD::Wrapper;
7063 CodeModel::Model M = getTargetMachine().getCodeModel();
7065 if (Subtarget->isPICStyleRIPRel() &&
7066 (M == CodeModel::Small || M == CodeModel::Kernel))
7067 WrapperKind = X86ISD::WrapperRIP;
7068 else if (Subtarget->isPICStyleGOT())
7069 OpFlag = X86II::MO_GOTOFF;
7070 else if (Subtarget->isPICStyleStubPIC())
7071 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7073 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
7075 DebugLoc DL = JT->getDebugLoc();
7076 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7078 // With PIC, the address is actually $g + Offset.
7080 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7081 DAG.getNode(X86ISD::GlobalBaseReg,
7082 DebugLoc(), getPointerTy()),
7089 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
7090 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
7092 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7094 unsigned char OpFlag = 0;
7095 unsigned WrapperKind = X86ISD::Wrapper;
7096 CodeModel::Model M = getTargetMachine().getCodeModel();
7098 if (Subtarget->isPICStyleRIPRel() &&
7099 (M == CodeModel::Small || M == CodeModel::Kernel)) {
7100 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
7101 OpFlag = X86II::MO_GOTPCREL;
7102 WrapperKind = X86ISD::WrapperRIP;
7103 } else if (Subtarget->isPICStyleGOT()) {
7104 OpFlag = X86II::MO_GOT;
7105 } else if (Subtarget->isPICStyleStubPIC()) {
7106 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
7107 } else if (Subtarget->isPICStyleStubNoDynamic()) {
7108 OpFlag = X86II::MO_DARWIN_NONLAZY;
7111 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
7113 DebugLoc DL = Op.getDebugLoc();
7114 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7117 // With PIC, the address is actually $g + Offset.
7118 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
7119 !Subtarget->is64Bit()) {
7120 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7121 DAG.getNode(X86ISD::GlobalBaseReg,
7122 DebugLoc(), getPointerTy()),
7126 // For symbols that require a load from a stub to get the address, emit the
7128 if (isGlobalStubReference(OpFlag))
7129 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
7130 MachinePointerInfo::getGOT(), false, false, false, 0);
7136 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
7137 // Create the TargetBlockAddressAddress node.
7138 unsigned char OpFlags =
7139 Subtarget->ClassifyBlockAddressReference();
7140 CodeModel::Model M = getTargetMachine().getCodeModel();
7141 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
7142 DebugLoc dl = Op.getDebugLoc();
7143 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(),
7144 /*isTarget=*/true, OpFlags);
7146 if (Subtarget->isPICStyleRIPRel() &&
7147 (M == CodeModel::Small || M == CodeModel::Kernel))
7148 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7150 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7152 // With PIC, the address is actually $g + Offset.
7153 if (isGlobalRelativeToPICBase(OpFlags)) {
7154 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7155 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7163 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
7165 SelectionDAG &DAG) const {
7166 // Create the TargetGlobalAddress node, folding in the constant
7167 // offset if it is legal.
7168 unsigned char OpFlags =
7169 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
7170 CodeModel::Model M = getTargetMachine().getCodeModel();
7172 if (OpFlags == X86II::MO_NO_FLAG &&
7173 X86::isOffsetSuitableForCodeModel(Offset, M)) {
7174 // A direct static reference to a global.
7175 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
7178 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
7181 if (Subtarget->isPICStyleRIPRel() &&
7182 (M == CodeModel::Small || M == CodeModel::Kernel))
7183 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7185 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7187 // With PIC, the address is actually $g + Offset.
7188 if (isGlobalRelativeToPICBase(OpFlags)) {
7189 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7190 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7194 // For globals that require a load from a stub to get the address, emit the
7196 if (isGlobalStubReference(OpFlags))
7197 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
7198 MachinePointerInfo::getGOT(), false, false, false, 0);
7200 // If there was a non-zero offset that we didn't fold, create an explicit
7203 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
7204 DAG.getConstant(Offset, getPointerTy()));
7210 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
7211 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
7212 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
7213 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
7217 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
7218 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
7219 unsigned char OperandFlags) {
7220 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7221 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7222 DebugLoc dl = GA->getDebugLoc();
7223 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7224 GA->getValueType(0),
7228 SDValue Ops[] = { Chain, TGA, *InFlag };
7229 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3);
7231 SDValue Ops[] = { Chain, TGA };
7232 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2);
7235 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
7236 MFI->setAdjustsStack(true);
7238 SDValue Flag = Chain.getValue(1);
7239 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
7242 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
7244 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7247 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
7248 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
7249 DAG.getNode(X86ISD::GlobalBaseReg,
7250 DebugLoc(), PtrVT), InFlag);
7251 InFlag = Chain.getValue(1);
7253 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
7256 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
7258 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7260 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
7261 X86::RAX, X86II::MO_TLSGD);
7264 // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
7265 // "local exec" model.
7266 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7267 const EVT PtrVT, TLSModel::Model model,
7269 DebugLoc dl = GA->getDebugLoc();
7271 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
7272 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
7273 is64Bit ? 257 : 256));
7275 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
7276 DAG.getIntPtrConstant(0),
7277 MachinePointerInfo(Ptr),
7278 false, false, false, 0);
7280 unsigned char OperandFlags = 0;
7281 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
7283 unsigned WrapperKind = X86ISD::Wrapper;
7284 if (model == TLSModel::LocalExec) {
7285 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
7286 } else if (is64Bit) {
7287 assert(model == TLSModel::InitialExec);
7288 OperandFlags = X86II::MO_GOTTPOFF;
7289 WrapperKind = X86ISD::WrapperRIP;
7291 assert(model == TLSModel::InitialExec);
7292 OperandFlags = X86II::MO_INDNTPOFF;
7295 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
7297 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7298 GA->getValueType(0),
7299 GA->getOffset(), OperandFlags);
7300 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
7302 if (model == TLSModel::InitialExec)
7303 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
7304 MachinePointerInfo::getGOT(), false, false, false, 0);
7306 // The address of the thread local variable is the add of the thread
7307 // pointer with the offset of the variable.
7308 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
7312 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
7314 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
7315 const GlobalValue *GV = GA->getGlobal();
7317 if (Subtarget->isTargetELF()) {
7318 // TODO: implement the "local dynamic" model
7319 // TODO: implement the "initial exec"model for pic executables
7321 // If GV is an alias then use the aliasee for determining
7322 // thread-localness.
7323 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
7324 GV = GA->resolveAliasedGlobal(false);
7326 TLSModel::Model model = getTargetMachine().getTLSModel(GV);
7329 case TLSModel::GeneralDynamic:
7330 case TLSModel::LocalDynamic: // not implemented
7331 if (Subtarget->is64Bit())
7332 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
7333 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
7335 case TLSModel::InitialExec:
7336 case TLSModel::LocalExec:
7337 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
7338 Subtarget->is64Bit());
7340 llvm_unreachable("Unknown TLS model.");
7343 if (Subtarget->isTargetDarwin()) {
7344 // Darwin only has one model of TLS. Lower to that.
7345 unsigned char OpFlag = 0;
7346 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
7347 X86ISD::WrapperRIP : X86ISD::Wrapper;
7349 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7351 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) &&
7352 !Subtarget->is64Bit();
7354 OpFlag = X86II::MO_TLVP_PIC_BASE;
7356 OpFlag = X86II::MO_TLVP;
7357 DebugLoc DL = Op.getDebugLoc();
7358 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
7359 GA->getValueType(0),
7360 GA->getOffset(), OpFlag);
7361 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7363 // With PIC32, the address is actually $g + Offset.
7365 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7366 DAG.getNode(X86ISD::GlobalBaseReg,
7367 DebugLoc(), getPointerTy()),
7370 // Lowering the machine isd will make sure everything is in the right
7372 SDValue Chain = DAG.getEntryNode();
7373 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7374 SDValue Args[] = { Chain, Offset };
7375 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2);
7377 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
7378 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7379 MFI->setAdjustsStack(true);
7381 // And our return value (tls address) is in the standard call return value
7383 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
7384 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
7388 if (Subtarget->isTargetWindows()) {
7389 // Just use the implicit TLS architecture
7390 // Need to generate someting similar to:
7391 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
7393 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
7394 // mov rcx, qword [rdx+rcx*8]
7395 // mov eax, .tls$:tlsvar
7396 // [rax+rcx] contains the address
7397 // Windows 64bit: gs:0x58
7398 // Windows 32bit: fs:__tls_array
7400 // If GV is an alias then use the aliasee for determining
7401 // thread-localness.
7402 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
7403 GV = GA->resolveAliasedGlobal(false);
7404 DebugLoc dl = GA->getDebugLoc();
7405 SDValue Chain = DAG.getEntryNode();
7407 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
7408 // %gs:0x58 (64-bit).
7409 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
7410 ? Type::getInt8PtrTy(*DAG.getContext(),
7412 : Type::getInt32PtrTy(*DAG.getContext(),
7415 SDValue ThreadPointer = DAG.getLoad(getPointerTy(), dl, Chain,
7416 Subtarget->is64Bit()
7417 ? DAG.getIntPtrConstant(0x58)
7418 : DAG.getExternalSymbol("_tls_array",
7420 MachinePointerInfo(Ptr),
7421 false, false, false, 0);
7423 // Load the _tls_index variable
7424 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
7425 if (Subtarget->is64Bit())
7426 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
7427 IDX, MachinePointerInfo(), MVT::i32,
7430 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
7431 false, false, false, 0);
7433 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
7435 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
7437 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
7438 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
7439 false, false, false, 0);
7441 // Get the offset of start of .tls section
7442 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7443 GA->getValueType(0),
7444 GA->getOffset(), X86II::MO_SECREL);
7445 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
7447 // The address of the thread local variable is the add of the thread
7448 // pointer with the offset of the variable.
7449 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
7452 llvm_unreachable("TLS not implemented for this target.");
7456 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
7457 /// and take a 2 x i32 value to shift plus a shift amount.
7458 SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const{
7459 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
7460 EVT VT = Op.getValueType();
7461 unsigned VTBits = VT.getSizeInBits();
7462 DebugLoc dl = Op.getDebugLoc();
7463 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
7464 SDValue ShOpLo = Op.getOperand(0);
7465 SDValue ShOpHi = Op.getOperand(1);
7466 SDValue ShAmt = Op.getOperand(2);
7467 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
7468 DAG.getConstant(VTBits - 1, MVT::i8))
7469 : DAG.getConstant(0, VT);
7472 if (Op.getOpcode() == ISD::SHL_PARTS) {
7473 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
7474 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
7476 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
7477 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
7480 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
7481 DAG.getConstant(VTBits, MVT::i8));
7482 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
7483 AndNode, DAG.getConstant(0, MVT::i8));
7486 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
7487 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
7488 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
7490 if (Op.getOpcode() == ISD::SHL_PARTS) {
7491 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7492 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7494 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7495 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7498 SDValue Ops[2] = { Lo, Hi };
7499 return DAG.getMergeValues(Ops, 2, dl);
7502 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
7503 SelectionDAG &DAG) const {
7504 EVT SrcVT = Op.getOperand(0).getValueType();
7506 if (SrcVT.isVector())
7509 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
7510 "Unknown SINT_TO_FP to lower!");
7512 // These are really Legal; return the operand so the caller accepts it as
7514 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
7516 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
7517 Subtarget->is64Bit()) {
7521 DebugLoc dl = Op.getDebugLoc();
7522 unsigned Size = SrcVT.getSizeInBits()/8;
7523 MachineFunction &MF = DAG.getMachineFunction();
7524 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
7525 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7526 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7528 MachinePointerInfo::getFixedStack(SSFI),
7530 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
7533 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
7535 SelectionDAG &DAG) const {
7537 DebugLoc DL = Op.getDebugLoc();
7539 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
7541 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
7543 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
7545 unsigned ByteSize = SrcVT.getSizeInBits()/8;
7547 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
7548 MachineMemOperand *MMO;
7550 int SSFI = FI->getIndex();
7552 DAG.getMachineFunction()
7553 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7554 MachineMemOperand::MOLoad, ByteSize, ByteSize);
7556 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
7557 StackSlot = StackSlot.getOperand(1);
7559 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
7560 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
7562 Tys, Ops, array_lengthof(Ops),
7566 Chain = Result.getValue(1);
7567 SDValue InFlag = Result.getValue(2);
7569 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
7570 // shouldn't be necessary except that RFP cannot be live across
7571 // multiple blocks. When stackifier is fixed, they can be uncoupled.
7572 MachineFunction &MF = DAG.getMachineFunction();
7573 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
7574 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
7575 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7576 Tys = DAG.getVTList(MVT::Other);
7578 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
7580 MachineMemOperand *MMO =
7581 DAG.getMachineFunction()
7582 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7583 MachineMemOperand::MOStore, SSFISize, SSFISize);
7585 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
7586 Ops, array_lengthof(Ops),
7587 Op.getValueType(), MMO);
7588 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
7589 MachinePointerInfo::getFixedStack(SSFI),
7590 false, false, false, 0);
7596 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
7597 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
7598 SelectionDAG &DAG) const {
7599 // This algorithm is not obvious. Here it is what we're trying to output:
7602 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
7603 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
7607 pshufd $0x4e, %xmm0, %xmm1
7612 DebugLoc dl = Op.getDebugLoc();
7613 LLVMContext *Context = DAG.getContext();
7615 // Build some magic constants.
7616 const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
7617 Constant *C0 = ConstantDataVector::get(*Context, CV0);
7618 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
7620 SmallVector<Constant*,2> CV1;
7622 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL))));
7624 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL))));
7625 Constant *C1 = ConstantVector::get(CV1);
7626 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
7628 // Load the 64-bit value into an XMM register.
7629 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
7631 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
7632 MachinePointerInfo::getConstantPool(),
7633 false, false, false, 16);
7634 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
7635 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
7638 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
7639 MachinePointerInfo::getConstantPool(),
7640 false, false, false, 16);
7641 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
7642 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
7645 if (Subtarget->hasSSE3()) {
7646 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
7647 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
7649 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
7650 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
7652 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
7653 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
7657 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
7658 DAG.getIntPtrConstant(0));
7661 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
7662 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
7663 SelectionDAG &DAG) const {
7664 DebugLoc dl = Op.getDebugLoc();
7665 // FP constant to bias correct the final result.
7666 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
7669 // Load the 32-bit value into an XMM register.
7670 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
7673 // Zero out the upper parts of the register.
7674 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
7676 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
7677 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
7678 DAG.getIntPtrConstant(0));
7680 // Or the load with the bias.
7681 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
7682 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7683 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
7685 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7686 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
7687 MVT::v2f64, Bias)));
7688 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
7689 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
7690 DAG.getIntPtrConstant(0));
7692 // Subtract the bias.
7693 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
7695 // Handle final rounding.
7696 EVT DestVT = Op.getValueType();
7698 if (DestVT.bitsLT(MVT::f64))
7699 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
7700 DAG.getIntPtrConstant(0));
7701 if (DestVT.bitsGT(MVT::f64))
7702 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
7704 // Handle final rounding.
7708 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
7709 SelectionDAG &DAG) const {
7710 SDValue N0 = Op.getOperand(0);
7711 DebugLoc dl = Op.getDebugLoc();
7713 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
7714 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
7715 // the optimization here.
7716 if (DAG.SignBitIsZero(N0))
7717 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
7719 EVT SrcVT = N0.getValueType();
7720 EVT DstVT = Op.getValueType();
7721 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
7722 return LowerUINT_TO_FP_i64(Op, DAG);
7723 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
7724 return LowerUINT_TO_FP_i32(Op, DAG);
7725 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
7728 // Make a 64-bit buffer, and use it to build an FILD.
7729 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
7730 if (SrcVT == MVT::i32) {
7731 SDValue WordOff = DAG.getConstant(4, getPointerTy());
7732 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
7733 getPointerTy(), StackSlot, WordOff);
7734 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7735 StackSlot, MachinePointerInfo(),
7737 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
7738 OffsetSlot, MachinePointerInfo(),
7740 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
7744 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
7745 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7746 StackSlot, MachinePointerInfo(),
7748 // For i64 source, we need to add the appropriate power of 2 if the input
7749 // was negative. This is the same as the optimization in
7750 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
7751 // we must be careful to do the computation in x87 extended precision, not
7752 // in SSE. (The generic code can't know it's OK to do this, or how to.)
7753 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
7754 MachineMemOperand *MMO =
7755 DAG.getMachineFunction()
7756 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7757 MachineMemOperand::MOLoad, 8, 8);
7759 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
7760 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
7761 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops, 3,
7764 APInt FF(32, 0x5F800000ULL);
7766 // Check whether the sign bit is set.
7767 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
7768 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
7771 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
7772 SDValue FudgePtr = DAG.getConstantPool(
7773 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
7776 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
7777 SDValue Zero = DAG.getIntPtrConstant(0);
7778 SDValue Four = DAG.getIntPtrConstant(4);
7779 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
7781 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
7783 // Load the value out, extending it from f32 to f80.
7784 // FIXME: Avoid the extend by constructing the right constant pool?
7785 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
7786 FudgePtr, MachinePointerInfo::getConstantPool(),
7787 MVT::f32, false, false, 4);
7788 // Extend everything to 80 bits to force it to be done on x87.
7789 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
7790 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
7793 std::pair<SDValue,SDValue> X86TargetLowering::
7794 FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned, bool IsReplace) const {
7795 DebugLoc DL = Op.getDebugLoc();
7797 EVT DstTy = Op.getValueType();
7799 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
7800 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
7804 assert(DstTy.getSimpleVT() <= MVT::i64 &&
7805 DstTy.getSimpleVT() >= MVT::i16 &&
7806 "Unknown FP_TO_INT to lower!");
7808 // These are really Legal.
7809 if (DstTy == MVT::i32 &&
7810 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
7811 return std::make_pair(SDValue(), SDValue());
7812 if (Subtarget->is64Bit() &&
7813 DstTy == MVT::i64 &&
7814 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
7815 return std::make_pair(SDValue(), SDValue());
7817 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
7818 // stack slot, or into the FTOL runtime function.
7819 MachineFunction &MF = DAG.getMachineFunction();
7820 unsigned MemSize = DstTy.getSizeInBits()/8;
7821 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
7822 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7825 if (!IsSigned && isIntegerTypeFTOL(DstTy))
7826 Opc = X86ISD::WIN_FTOL;
7828 switch (DstTy.getSimpleVT().SimpleTy) {
7829 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
7830 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
7831 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
7832 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
7835 SDValue Chain = DAG.getEntryNode();
7836 SDValue Value = Op.getOperand(0);
7837 EVT TheVT = Op.getOperand(0).getValueType();
7838 // FIXME This causes a redundant load/store if the SSE-class value is already
7839 // in memory, such as if it is on the callstack.
7840 if (isScalarFPTypeInSSEReg(TheVT)) {
7841 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
7842 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
7843 MachinePointerInfo::getFixedStack(SSFI),
7845 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
7847 Chain, StackSlot, DAG.getValueType(TheVT)
7850 MachineMemOperand *MMO =
7851 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7852 MachineMemOperand::MOLoad, MemSize, MemSize);
7853 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, 3,
7855 Chain = Value.getValue(1);
7856 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
7857 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7860 MachineMemOperand *MMO =
7861 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7862 MachineMemOperand::MOStore, MemSize, MemSize);
7864 if (Opc != X86ISD::WIN_FTOL) {
7865 // Build the FP_TO_INT*_IN_MEM
7866 SDValue Ops[] = { Chain, Value, StackSlot };
7867 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
7868 Ops, 3, DstTy, MMO);
7869 return std::make_pair(FIST, StackSlot);
7871 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
7872 DAG.getVTList(MVT::Other, MVT::Glue),
7874 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
7875 MVT::i32, ftol.getValue(1));
7876 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
7877 MVT::i32, eax.getValue(2));
7878 SDValue Ops[] = { eax, edx };
7879 SDValue pair = IsReplace
7880 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops, 2)
7881 : DAG.getMergeValues(Ops, 2, DL);
7882 return std::make_pair(pair, SDValue());
7886 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
7887 SelectionDAG &DAG) const {
7888 if (Op.getValueType().isVector())
7891 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
7892 /*IsSigned=*/ true, /*IsReplace=*/ false);
7893 SDValue FIST = Vals.first, StackSlot = Vals.second;
7894 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
7895 if (FIST.getNode() == 0) return Op;
7897 if (StackSlot.getNode())
7899 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
7900 FIST, StackSlot, MachinePointerInfo(),
7901 false, false, false, 0);
7903 // The node is the result.
7907 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
7908 SelectionDAG &DAG) const {
7909 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
7910 /*IsSigned=*/ false, /*IsReplace=*/ false);
7911 SDValue FIST = Vals.first, StackSlot = Vals.second;
7912 assert(FIST.getNode() && "Unexpected failure");
7914 if (StackSlot.getNode())
7916 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
7917 FIST, StackSlot, MachinePointerInfo(),
7918 false, false, false, 0);
7920 // The node is the result.
7924 SDValue X86TargetLowering::LowerFABS(SDValue Op,
7925 SelectionDAG &DAG) const {
7926 LLVMContext *Context = DAG.getContext();
7927 DebugLoc dl = Op.getDebugLoc();
7928 EVT VT = Op.getValueType();
7931 EltVT = VT.getVectorElementType();
7933 if (EltVT == MVT::f64) {
7934 C = ConstantVector::getSplat(2,
7935 ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
7937 C = ConstantVector::getSplat(4,
7938 ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
7940 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7941 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
7942 MachinePointerInfo::getConstantPool(),
7943 false, false, false, 16);
7944 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
7947 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const {
7948 LLVMContext *Context = DAG.getContext();
7949 DebugLoc dl = Op.getDebugLoc();
7950 EVT VT = Op.getValueType();
7952 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
7953 if (VT.isVector()) {
7954 EltVT = VT.getVectorElementType();
7955 NumElts = VT.getVectorNumElements();
7958 if (EltVT == MVT::f64)
7959 C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)));
7961 C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)));
7962 C = ConstantVector::getSplat(NumElts, C);
7963 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7964 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
7965 MachinePointerInfo::getConstantPool(),
7966 false, false, false, 16);
7967 if (VT.isVector()) {
7968 MVT XORVT = VT.getSizeInBits() == 128 ? MVT::v2i64 : MVT::v4i64;
7969 return DAG.getNode(ISD::BITCAST, dl, VT,
7970 DAG.getNode(ISD::XOR, dl, XORVT,
7971 DAG.getNode(ISD::BITCAST, dl, XORVT,
7973 DAG.getNode(ISD::BITCAST, dl, XORVT, Mask)));
7976 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
7979 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
7980 LLVMContext *Context = DAG.getContext();
7981 SDValue Op0 = Op.getOperand(0);
7982 SDValue Op1 = Op.getOperand(1);
7983 DebugLoc dl = Op.getDebugLoc();
7984 EVT VT = Op.getValueType();
7985 EVT SrcVT = Op1.getValueType();
7987 // If second operand is smaller, extend it first.
7988 if (SrcVT.bitsLT(VT)) {
7989 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
7992 // And if it is bigger, shrink it first.
7993 if (SrcVT.bitsGT(VT)) {
7994 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
7998 // At this point the operands and the result should have the same
7999 // type, and that won't be f80 since that is not custom lowered.
8001 // First get the sign bit of second operand.
8002 SmallVector<Constant*,4> CV;
8003 if (SrcVT == MVT::f64) {
8004 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))));
8005 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
8007 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))));
8008 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8009 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8010 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8012 Constant *C = ConstantVector::get(CV);
8013 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8014 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
8015 MachinePointerInfo::getConstantPool(),
8016 false, false, false, 16);
8017 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
8019 // Shift sign bit right or left if the two operands have different types.
8020 if (SrcVT.bitsGT(VT)) {
8021 // Op0 is MVT::f32, Op1 is MVT::f64.
8022 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
8023 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
8024 DAG.getConstant(32, MVT::i32));
8025 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
8026 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
8027 DAG.getIntPtrConstant(0));
8030 // Clear first operand sign bit.
8032 if (VT == MVT::f64) {
8033 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
8034 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
8036 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
8037 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8038 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8039 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8041 C = ConstantVector::get(CV);
8042 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8043 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8044 MachinePointerInfo::getConstantPool(),
8045 false, false, false, 16);
8046 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
8048 // Or the value with the sign bit.
8049 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
8052 SDValue X86TargetLowering::LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) const {
8053 SDValue N0 = Op.getOperand(0);
8054 DebugLoc dl = Op.getDebugLoc();
8055 EVT VT = Op.getValueType();
8057 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
8058 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
8059 DAG.getConstant(1, VT));
8060 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
8063 /// Emit nodes that will be selected as "test Op0,Op0", or something
8065 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
8066 SelectionDAG &DAG) const {
8067 DebugLoc dl = Op.getDebugLoc();
8069 // CF and OF aren't always set the way we want. Determine which
8070 // of these we need.
8071 bool NeedCF = false;
8072 bool NeedOF = false;
8075 case X86::COND_A: case X86::COND_AE:
8076 case X86::COND_B: case X86::COND_BE:
8079 case X86::COND_G: case X86::COND_GE:
8080 case X86::COND_L: case X86::COND_LE:
8081 case X86::COND_O: case X86::COND_NO:
8086 // See if we can use the EFLAGS value from the operand instead of
8087 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
8088 // we prove that the arithmetic won't overflow, we can't use OF or CF.
8089 if (Op.getResNo() != 0 || NeedOF || NeedCF)
8090 // Emit a CMP with 0, which is the TEST pattern.
8091 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
8092 DAG.getConstant(0, Op.getValueType()));
8094 unsigned Opcode = 0;
8095 unsigned NumOperands = 0;
8096 switch (Op.getNode()->getOpcode()) {
8098 // Due to an isel shortcoming, be conservative if this add is likely to be
8099 // selected as part of a load-modify-store instruction. When the root node
8100 // in a match is a store, isel doesn't know how to remap non-chain non-flag
8101 // uses of other nodes in the match, such as the ADD in this case. This
8102 // leads to the ADD being left around and reselected, with the result being
8103 // two adds in the output. Alas, even if none our users are stores, that
8104 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
8105 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
8106 // climbing the DAG back to the root, and it doesn't seem to be worth the
8108 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8109 UE = Op.getNode()->use_end(); UI != UE; ++UI)
8110 if (UI->getOpcode() != ISD::CopyToReg &&
8111 UI->getOpcode() != ISD::SETCC &&
8112 UI->getOpcode() != ISD::STORE)
8115 if (ConstantSDNode *C =
8116 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) {
8117 // An add of one will be selected as an INC.
8118 if (C->getAPIntValue() == 1) {
8119 Opcode = X86ISD::INC;
8124 // An add of negative one (subtract of one) will be selected as a DEC.
8125 if (C->getAPIntValue().isAllOnesValue()) {
8126 Opcode = X86ISD::DEC;
8132 // Otherwise use a regular EFLAGS-setting add.
8133 Opcode = X86ISD::ADD;
8137 // If the primary and result isn't used, don't bother using X86ISD::AND,
8138 // because a TEST instruction will be better.
8139 bool NonFlagUse = false;
8140 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8141 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
8143 unsigned UOpNo = UI.getOperandNo();
8144 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
8145 // Look pass truncate.
8146 UOpNo = User->use_begin().getOperandNo();
8147 User = *User->use_begin();
8150 if (User->getOpcode() != ISD::BRCOND &&
8151 User->getOpcode() != ISD::SETCC &&
8152 (User->getOpcode() != ISD::SELECT || UOpNo != 0)) {
8165 // Due to the ISEL shortcoming noted above, be conservative if this op is
8166 // likely to be selected as part of a load-modify-store instruction.
8167 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8168 UE = Op.getNode()->use_end(); UI != UE; ++UI)
8169 if (UI->getOpcode() == ISD::STORE)
8172 // Otherwise use a regular EFLAGS-setting instruction.
8173 switch (Op.getNode()->getOpcode()) {
8174 default: llvm_unreachable("unexpected operator!");
8175 case ISD::SUB: Opcode = X86ISD::SUB; break;
8176 case ISD::OR: Opcode = X86ISD::OR; break;
8177 case ISD::XOR: Opcode = X86ISD::XOR; break;
8178 case ISD::AND: Opcode = X86ISD::AND; break;
8190 return SDValue(Op.getNode(), 1);
8197 // Emit a CMP with 0, which is the TEST pattern.
8198 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
8199 DAG.getConstant(0, Op.getValueType()));
8201 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
8202 SmallVector<SDValue, 4> Ops;
8203 for (unsigned i = 0; i != NumOperands; ++i)
8204 Ops.push_back(Op.getOperand(i));
8206 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
8207 DAG.ReplaceAllUsesWith(Op, New);
8208 return SDValue(New.getNode(), 1);
8211 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
8213 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
8214 SelectionDAG &DAG) const {
8215 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
8216 if (C->getAPIntValue() == 0)
8217 return EmitTest(Op0, X86CC, DAG);
8219 DebugLoc dl = Op0.getDebugLoc();
8220 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
8223 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
8224 /// if it's possible.
8225 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
8226 DebugLoc dl, SelectionDAG &DAG) const {
8227 SDValue Op0 = And.getOperand(0);
8228 SDValue Op1 = And.getOperand(1);
8229 if (Op0.getOpcode() == ISD::TRUNCATE)
8230 Op0 = Op0.getOperand(0);
8231 if (Op1.getOpcode() == ISD::TRUNCATE)
8232 Op1 = Op1.getOperand(0);
8235 if (Op1.getOpcode() == ISD::SHL)
8236 std::swap(Op0, Op1);
8237 if (Op0.getOpcode() == ISD::SHL) {
8238 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
8239 if (And00C->getZExtValue() == 1) {
8240 // If we looked past a truncate, check that it's only truncating away
8242 unsigned BitWidth = Op0.getValueSizeInBits();
8243 unsigned AndBitWidth = And.getValueSizeInBits();
8244 if (BitWidth > AndBitWidth) {
8246 DAG.ComputeMaskedBits(Op0, Zeros, Ones);
8247 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
8251 RHS = Op0.getOperand(1);
8253 } else if (Op1.getOpcode() == ISD::Constant) {
8254 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
8255 uint64_t AndRHSVal = AndRHS->getZExtValue();
8256 SDValue AndLHS = Op0;
8258 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
8259 LHS = AndLHS.getOperand(0);
8260 RHS = AndLHS.getOperand(1);
8263 // Use BT if the immediate can't be encoded in a TEST instruction.
8264 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
8266 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
8270 if (LHS.getNode()) {
8271 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
8272 // instruction. Since the shift amount is in-range-or-undefined, we know
8273 // that doing a bittest on the i32 value is ok. We extend to i32 because
8274 // the encoding for the i16 version is larger than the i32 version.
8275 // Also promote i16 to i32 for performance / code size reason.
8276 if (LHS.getValueType() == MVT::i8 ||
8277 LHS.getValueType() == MVT::i16)
8278 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
8280 // If the operand types disagree, extend the shift amount to match. Since
8281 // BT ignores high bits (like shifts) we can use anyextend.
8282 if (LHS.getValueType() != RHS.getValueType())
8283 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
8285 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
8286 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
8287 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8288 DAG.getConstant(Cond, MVT::i8), BT);
8294 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
8296 if (Op.getValueType().isVector()) return LowerVSETCC(Op, DAG);
8298 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
8299 SDValue Op0 = Op.getOperand(0);
8300 SDValue Op1 = Op.getOperand(1);
8301 DebugLoc dl = Op.getDebugLoc();
8302 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
8304 // Optimize to BT if possible.
8305 // Lower (X & (1 << N)) == 0 to BT(X, N).
8306 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
8307 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
8308 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
8309 Op1.getOpcode() == ISD::Constant &&
8310 cast<ConstantSDNode>(Op1)->isNullValue() &&
8311 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
8312 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
8313 if (NewSetCC.getNode())
8317 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
8319 if (Op1.getOpcode() == ISD::Constant &&
8320 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
8321 cast<ConstantSDNode>(Op1)->isNullValue()) &&
8322 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
8324 // If the input is a setcc, then reuse the input setcc or use a new one with
8325 // the inverted condition.
8326 if (Op0.getOpcode() == X86ISD::SETCC) {
8327 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
8328 bool Invert = (CC == ISD::SETNE) ^
8329 cast<ConstantSDNode>(Op1)->isNullValue();
8330 if (!Invert) return Op0;
8332 CCode = X86::GetOppositeBranchCondition(CCode);
8333 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8334 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1));
8338 bool isFP = Op1.getValueType().isFloatingPoint();
8339 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
8340 if (X86CC == X86::COND_INVALID)
8343 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG);
8344 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8345 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
8348 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
8349 // ones, and then concatenate the result back.
8350 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
8351 EVT VT = Op.getValueType();
8353 assert(VT.getSizeInBits() == 256 && Op.getOpcode() == ISD::SETCC &&
8354 "Unsupported value type for operation");
8356 int NumElems = VT.getVectorNumElements();
8357 DebugLoc dl = Op.getDebugLoc();
8358 SDValue CC = Op.getOperand(2);
8360 // Extract the LHS vectors
8361 SDValue LHS = Op.getOperand(0);
8362 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
8363 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
8365 // Extract the RHS vectors
8366 SDValue RHS = Op.getOperand(1);
8367 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
8368 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
8370 // Issue the operation on the smaller types and concatenate the result back
8371 MVT EltVT = VT.getVectorElementType().getSimpleVT();
8372 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
8373 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
8374 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
8375 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
8379 SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const {
8381 SDValue Op0 = Op.getOperand(0);
8382 SDValue Op1 = Op.getOperand(1);
8383 SDValue CC = Op.getOperand(2);
8384 EVT VT = Op.getValueType();
8385 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
8386 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
8387 DebugLoc dl = Op.getDebugLoc();
8391 EVT EltVT = Op0.getValueType().getVectorElementType();
8392 assert(EltVT == MVT::f32 || EltVT == MVT::f64); (void)EltVT;
8396 // SSE Condition code mapping:
8405 switch (SetCCOpcode) {
8408 case ISD::SETEQ: SSECC = 0; break;
8410 case ISD::SETGT: Swap = true; // Fallthrough
8412 case ISD::SETOLT: SSECC = 1; break;
8414 case ISD::SETGE: Swap = true; // Fallthrough
8416 case ISD::SETOLE: SSECC = 2; break;
8417 case ISD::SETUO: SSECC = 3; break;
8419 case ISD::SETNE: SSECC = 4; break;
8420 case ISD::SETULE: Swap = true;
8421 case ISD::SETUGE: SSECC = 5; break;
8422 case ISD::SETULT: Swap = true;
8423 case ISD::SETUGT: SSECC = 6; break;
8424 case ISD::SETO: SSECC = 7; break;
8427 std::swap(Op0, Op1);
8429 // In the two special cases we can't handle, emit two comparisons.
8431 if (SetCCOpcode == ISD::SETUEQ) {
8433 UNORD = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8434 DAG.getConstant(3, MVT::i8));
8435 EQ = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8436 DAG.getConstant(0, MVT::i8));
8437 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ);
8439 if (SetCCOpcode == ISD::SETONE) {
8441 ORD = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8442 DAG.getConstant(7, MVT::i8));
8443 NEQ = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8444 DAG.getConstant(4, MVT::i8));
8445 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ);
8447 llvm_unreachable("Illegal FP comparison");
8449 // Handle all other FP comparisons here.
8450 return DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8451 DAG.getConstant(SSECC, MVT::i8));
8454 // Break 256-bit integer vector compare into smaller ones.
8455 if (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2())
8456 return Lower256IntVSETCC(Op, DAG);
8458 // We are handling one of the integer comparisons here. Since SSE only has
8459 // GT and EQ comparisons for integer, swapping operands and multiple
8460 // operations may be required for some comparisons.
8462 bool Swap = false, Invert = false, FlipSigns = false;
8464 switch (SetCCOpcode) {
8466 case ISD::SETNE: Invert = true;
8467 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
8468 case ISD::SETLT: Swap = true;
8469 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
8470 case ISD::SETGE: Swap = true;
8471 case ISD::SETLE: Opc = X86ISD::PCMPGT; Invert = true; break;
8472 case ISD::SETULT: Swap = true;
8473 case ISD::SETUGT: Opc = X86ISD::PCMPGT; FlipSigns = true; break;
8474 case ISD::SETUGE: Swap = true;
8475 case ISD::SETULE: Opc = X86ISD::PCMPGT; FlipSigns = true; Invert = true; break;
8478 std::swap(Op0, Op1);
8480 // Check that the operation in question is available (most are plain SSE2,
8481 // but PCMPGTQ and PCMPEQQ have different requirements).
8482 if (Opc == X86ISD::PCMPGT && VT == MVT::v2i64 && !Subtarget->hasSSE42())
8484 if (Opc == X86ISD::PCMPEQ && VT == MVT::v2i64 && !Subtarget->hasSSE41())
8487 // Since SSE has no unsigned integer comparisons, we need to flip the sign
8488 // bits of the inputs before performing those operations.
8490 EVT EltVT = VT.getVectorElementType();
8491 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
8493 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
8494 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
8496 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
8497 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
8500 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
8502 // If the logical-not of the result is required, perform that now.
8504 Result = DAG.getNOT(dl, Result, VT);
8509 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
8510 static bool isX86LogicalCmp(SDValue Op) {
8511 unsigned Opc = Op.getNode()->getOpcode();
8512 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI)
8514 if (Op.getResNo() == 1 &&
8515 (Opc == X86ISD::ADD ||
8516 Opc == X86ISD::SUB ||
8517 Opc == X86ISD::ADC ||
8518 Opc == X86ISD::SBB ||
8519 Opc == X86ISD::SMUL ||
8520 Opc == X86ISD::UMUL ||
8521 Opc == X86ISD::INC ||
8522 Opc == X86ISD::DEC ||
8523 Opc == X86ISD::OR ||
8524 Opc == X86ISD::XOR ||
8525 Opc == X86ISD::AND))
8528 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
8534 static bool isZero(SDValue V) {
8535 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
8536 return C && C->isNullValue();
8539 static bool isAllOnes(SDValue V) {
8540 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
8541 return C && C->isAllOnesValue();
8544 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
8545 bool addTest = true;
8546 SDValue Cond = Op.getOperand(0);
8547 SDValue Op1 = Op.getOperand(1);
8548 SDValue Op2 = Op.getOperand(2);
8549 DebugLoc DL = Op.getDebugLoc();
8552 if (Cond.getOpcode() == ISD::SETCC) {
8553 SDValue NewCond = LowerSETCC(Cond, DAG);
8554 if (NewCond.getNode())
8558 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
8559 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
8560 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
8561 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
8562 if (Cond.getOpcode() == X86ISD::SETCC &&
8563 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
8564 isZero(Cond.getOperand(1).getOperand(1))) {
8565 SDValue Cmp = Cond.getOperand(1);
8567 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
8569 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
8570 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
8571 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
8573 SDValue CmpOp0 = Cmp.getOperand(0);
8574 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
8575 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
8577 SDValue Res = // Res = 0 or -1.
8578 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
8579 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
8581 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
8582 Res = DAG.getNOT(DL, Res, Res.getValueType());
8584 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
8585 if (N2C == 0 || !N2C->isNullValue())
8586 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
8591 // Look past (and (setcc_carry (cmp ...)), 1).
8592 if (Cond.getOpcode() == ISD::AND &&
8593 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
8594 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
8595 if (C && C->getAPIntValue() == 1)
8596 Cond = Cond.getOperand(0);
8599 // If condition flag is set by a X86ISD::CMP, then use it as the condition
8600 // setting operand in place of the X86ISD::SETCC.
8601 unsigned CondOpcode = Cond.getOpcode();
8602 if (CondOpcode == X86ISD::SETCC ||
8603 CondOpcode == X86ISD::SETCC_CARRY) {
8604 CC = Cond.getOperand(0);
8606 SDValue Cmp = Cond.getOperand(1);
8607 unsigned Opc = Cmp.getOpcode();
8608 EVT VT = Op.getValueType();
8610 bool IllegalFPCMov = false;
8611 if (VT.isFloatingPoint() && !VT.isVector() &&
8612 !isScalarFPTypeInSSEReg(VT)) // FPStack?
8613 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
8615 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
8616 Opc == X86ISD::BT) { // FIXME
8620 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
8621 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
8622 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
8623 Cond.getOperand(0).getValueType() != MVT::i8)) {
8624 SDValue LHS = Cond.getOperand(0);
8625 SDValue RHS = Cond.getOperand(1);
8629 switch (CondOpcode) {
8630 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
8631 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
8632 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
8633 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
8634 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
8635 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
8636 default: llvm_unreachable("unexpected overflowing operator");
8638 if (CondOpcode == ISD::UMULO)
8639 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
8642 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
8644 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
8646 if (CondOpcode == ISD::UMULO)
8647 Cond = X86Op.getValue(2);
8649 Cond = X86Op.getValue(1);
8651 CC = DAG.getConstant(X86Cond, MVT::i8);
8656 // Look pass the truncate.
8657 if (Cond.getOpcode() == ISD::TRUNCATE)
8658 Cond = Cond.getOperand(0);
8660 // We know the result of AND is compared against zero. Try to match
8662 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
8663 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
8664 if (NewSetCC.getNode()) {
8665 CC = NewSetCC.getOperand(0);
8666 Cond = NewSetCC.getOperand(1);
8673 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8674 Cond = EmitTest(Cond, X86::COND_NE, DAG);
8677 // a < b ? -1 : 0 -> RES = ~setcc_carry
8678 // a < b ? 0 : -1 -> RES = setcc_carry
8679 // a >= b ? -1 : 0 -> RES = setcc_carry
8680 // a >= b ? 0 : -1 -> RES = ~setcc_carry
8681 if (Cond.getOpcode() == X86ISD::CMP) {
8682 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
8684 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
8685 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
8686 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
8687 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
8688 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
8689 return DAG.getNOT(DL, Res, Res.getValueType());
8694 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
8695 // condition is true.
8696 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
8697 SDValue Ops[] = { Op2, Op1, CC, Cond };
8698 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops));
8701 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
8702 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
8703 // from the AND / OR.
8704 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
8705 Opc = Op.getOpcode();
8706 if (Opc != ISD::OR && Opc != ISD::AND)
8708 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
8709 Op.getOperand(0).hasOneUse() &&
8710 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
8711 Op.getOperand(1).hasOneUse());
8714 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
8715 // 1 and that the SETCC node has a single use.
8716 static bool isXor1OfSetCC(SDValue Op) {
8717 if (Op.getOpcode() != ISD::XOR)
8719 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
8720 if (N1C && N1C->getAPIntValue() == 1) {
8721 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
8722 Op.getOperand(0).hasOneUse();
8727 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
8728 bool addTest = true;
8729 SDValue Chain = Op.getOperand(0);
8730 SDValue Cond = Op.getOperand(1);
8731 SDValue Dest = Op.getOperand(2);
8732 DebugLoc dl = Op.getDebugLoc();
8734 bool Inverted = false;
8736 if (Cond.getOpcode() == ISD::SETCC) {
8737 // Check for setcc([su]{add,sub,mul}o == 0).
8738 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
8739 isa<ConstantSDNode>(Cond.getOperand(1)) &&
8740 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
8741 Cond.getOperand(0).getResNo() == 1 &&
8742 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
8743 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
8744 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
8745 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
8746 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
8747 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
8749 Cond = Cond.getOperand(0);
8751 SDValue NewCond = LowerSETCC(Cond, DAG);
8752 if (NewCond.getNode())
8757 // FIXME: LowerXALUO doesn't handle these!!
8758 else if (Cond.getOpcode() == X86ISD::ADD ||
8759 Cond.getOpcode() == X86ISD::SUB ||
8760 Cond.getOpcode() == X86ISD::SMUL ||
8761 Cond.getOpcode() == X86ISD::UMUL)
8762 Cond = LowerXALUO(Cond, DAG);
8765 // Look pass (and (setcc_carry (cmp ...)), 1).
8766 if (Cond.getOpcode() == ISD::AND &&
8767 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
8768 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
8769 if (C && C->getAPIntValue() == 1)
8770 Cond = Cond.getOperand(0);
8773 // If condition flag is set by a X86ISD::CMP, then use it as the condition
8774 // setting operand in place of the X86ISD::SETCC.
8775 unsigned CondOpcode = Cond.getOpcode();
8776 if (CondOpcode == X86ISD::SETCC ||
8777 CondOpcode == X86ISD::SETCC_CARRY) {
8778 CC = Cond.getOperand(0);
8780 SDValue Cmp = Cond.getOperand(1);
8781 unsigned Opc = Cmp.getOpcode();
8782 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
8783 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
8787 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
8791 // These can only come from an arithmetic instruction with overflow,
8792 // e.g. SADDO, UADDO.
8793 Cond = Cond.getNode()->getOperand(1);
8799 CondOpcode = Cond.getOpcode();
8800 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
8801 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
8802 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
8803 Cond.getOperand(0).getValueType() != MVT::i8)) {
8804 SDValue LHS = Cond.getOperand(0);
8805 SDValue RHS = Cond.getOperand(1);
8809 switch (CondOpcode) {
8810 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
8811 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
8812 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
8813 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
8814 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
8815 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
8816 default: llvm_unreachable("unexpected overflowing operator");
8819 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
8820 if (CondOpcode == ISD::UMULO)
8821 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
8824 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
8826 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
8828 if (CondOpcode == ISD::UMULO)
8829 Cond = X86Op.getValue(2);
8831 Cond = X86Op.getValue(1);
8833 CC = DAG.getConstant(X86Cond, MVT::i8);
8837 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
8838 SDValue Cmp = Cond.getOperand(0).getOperand(1);
8839 if (CondOpc == ISD::OR) {
8840 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
8841 // two branches instead of an explicit OR instruction with a
8843 if (Cmp == Cond.getOperand(1).getOperand(1) &&
8844 isX86LogicalCmp(Cmp)) {
8845 CC = Cond.getOperand(0).getOperand(0);
8846 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8847 Chain, Dest, CC, Cmp);
8848 CC = Cond.getOperand(1).getOperand(0);
8852 } else { // ISD::AND
8853 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
8854 // two branches instead of an explicit AND instruction with a
8855 // separate test. However, we only do this if this block doesn't
8856 // have a fall-through edge, because this requires an explicit
8857 // jmp when the condition is false.
8858 if (Cmp == Cond.getOperand(1).getOperand(1) &&
8859 isX86LogicalCmp(Cmp) &&
8860 Op.getNode()->hasOneUse()) {
8861 X86::CondCode CCode =
8862 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
8863 CCode = X86::GetOppositeBranchCondition(CCode);
8864 CC = DAG.getConstant(CCode, MVT::i8);
8865 SDNode *User = *Op.getNode()->use_begin();
8866 // Look for an unconditional branch following this conditional branch.
8867 // We need this because we need to reverse the successors in order
8868 // to implement FCMP_OEQ.
8869 if (User->getOpcode() == ISD::BR) {
8870 SDValue FalseBB = User->getOperand(1);
8872 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
8873 assert(NewBR == User);
8877 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8878 Chain, Dest, CC, Cmp);
8879 X86::CondCode CCode =
8880 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
8881 CCode = X86::GetOppositeBranchCondition(CCode);
8882 CC = DAG.getConstant(CCode, MVT::i8);
8888 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
8889 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
8890 // It should be transformed during dag combiner except when the condition
8891 // is set by a arithmetics with overflow node.
8892 X86::CondCode CCode =
8893 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
8894 CCode = X86::GetOppositeBranchCondition(CCode);
8895 CC = DAG.getConstant(CCode, MVT::i8);
8896 Cond = Cond.getOperand(0).getOperand(1);
8898 } else if (Cond.getOpcode() == ISD::SETCC &&
8899 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
8900 // For FCMP_OEQ, we can emit
8901 // two branches instead of an explicit AND instruction with a
8902 // separate test. However, we only do this if this block doesn't
8903 // have a fall-through edge, because this requires an explicit
8904 // jmp when the condition is false.
8905 if (Op.getNode()->hasOneUse()) {
8906 SDNode *User = *Op.getNode()->use_begin();
8907 // Look for an unconditional branch following this conditional branch.
8908 // We need this because we need to reverse the successors in order
8909 // to implement FCMP_OEQ.
8910 if (User->getOpcode() == ISD::BR) {
8911 SDValue FalseBB = User->getOperand(1);
8913 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
8914 assert(NewBR == User);
8918 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
8919 Cond.getOperand(0), Cond.getOperand(1));
8920 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8921 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8922 Chain, Dest, CC, Cmp);
8923 CC = DAG.getConstant(X86::COND_P, MVT::i8);
8928 } else if (Cond.getOpcode() == ISD::SETCC &&
8929 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
8930 // For FCMP_UNE, we can emit
8931 // two branches instead of an explicit AND instruction with a
8932 // separate test. However, we only do this if this block doesn't
8933 // have a fall-through edge, because this requires an explicit
8934 // jmp when the condition is false.
8935 if (Op.getNode()->hasOneUse()) {
8936 SDNode *User = *Op.getNode()->use_begin();
8937 // Look for an unconditional branch following this conditional branch.
8938 // We need this because we need to reverse the successors in order
8939 // to implement FCMP_UNE.
8940 if (User->getOpcode() == ISD::BR) {
8941 SDValue FalseBB = User->getOperand(1);
8943 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
8944 assert(NewBR == User);
8947 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
8948 Cond.getOperand(0), Cond.getOperand(1));
8949 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8950 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8951 Chain, Dest, CC, Cmp);
8952 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
8962 // Look pass the truncate.
8963 if (Cond.getOpcode() == ISD::TRUNCATE)
8964 Cond = Cond.getOperand(0);
8966 // We know the result of AND is compared against zero. Try to match
8968 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
8969 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
8970 if (NewSetCC.getNode()) {
8971 CC = NewSetCC.getOperand(0);
8972 Cond = NewSetCC.getOperand(1);
8979 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8980 Cond = EmitTest(Cond, X86::COND_NE, DAG);
8982 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8983 Chain, Dest, CC, Cond);
8987 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
8988 // Calls to _alloca is needed to probe the stack when allocating more than 4k
8989 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
8990 // that the guard pages used by the OS virtual memory manager are allocated in
8991 // correct sequence.
8993 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
8994 SelectionDAG &DAG) const {
8995 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows() ||
8996 getTargetMachine().Options.EnableSegmentedStacks) &&
8997 "This should be used only on Windows targets or when segmented stacks "
8999 assert(!Subtarget->isTargetEnvMacho() && "Not implemented");
9000 DebugLoc dl = Op.getDebugLoc();
9003 SDValue Chain = Op.getOperand(0);
9004 SDValue Size = Op.getOperand(1);
9005 // FIXME: Ensure alignment here
9007 bool Is64Bit = Subtarget->is64Bit();
9008 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32;
9010 if (getTargetMachine().Options.EnableSegmentedStacks) {
9011 MachineFunction &MF = DAG.getMachineFunction();
9012 MachineRegisterInfo &MRI = MF.getRegInfo();
9015 // The 64 bit implementation of segmented stacks needs to clobber both r10
9016 // r11. This makes it impossible to use it along with nested parameters.
9017 const Function *F = MF.getFunction();
9019 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
9021 if (I->hasNestAttr())
9022 report_fatal_error("Cannot use segmented stacks with functions that "
9023 "have nested arguments.");
9026 const TargetRegisterClass *AddrRegClass =
9027 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32);
9028 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
9029 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
9030 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
9031 DAG.getRegister(Vreg, SPTy));
9032 SDValue Ops1[2] = { Value, Chain };
9033 return DAG.getMergeValues(Ops1, 2, dl);
9036 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
9038 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
9039 Flag = Chain.getValue(1);
9040 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
9042 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
9043 Flag = Chain.getValue(1);
9045 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1);
9047 SDValue Ops1[2] = { Chain.getValue(0), Chain };
9048 return DAG.getMergeValues(Ops1, 2, dl);
9052 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
9053 MachineFunction &MF = DAG.getMachineFunction();
9054 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
9056 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
9057 DebugLoc DL = Op.getDebugLoc();
9059 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
9060 // vastart just stores the address of the VarArgsFrameIndex slot into the
9061 // memory location argument.
9062 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
9064 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
9065 MachinePointerInfo(SV), false, false, 0);
9069 // gp_offset (0 - 6 * 8)
9070 // fp_offset (48 - 48 + 8 * 16)
9071 // overflow_arg_area (point to parameters coming in memory).
9073 SmallVector<SDValue, 8> MemOps;
9074 SDValue FIN = Op.getOperand(1);
9076 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
9077 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
9079 FIN, MachinePointerInfo(SV), false, false, 0);
9080 MemOps.push_back(Store);
9083 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9084 FIN, DAG.getIntPtrConstant(4));
9085 Store = DAG.getStore(Op.getOperand(0), DL,
9086 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
9088 FIN, MachinePointerInfo(SV, 4), false, false, 0);
9089 MemOps.push_back(Store);
9091 // Store ptr to overflow_arg_area
9092 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9093 FIN, DAG.getIntPtrConstant(4));
9094 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
9096 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
9097 MachinePointerInfo(SV, 8),
9099 MemOps.push_back(Store);
9101 // Store ptr to reg_save_area.
9102 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9103 FIN, DAG.getIntPtrConstant(8));
9104 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
9106 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
9107 MachinePointerInfo(SV, 16), false, false, 0);
9108 MemOps.push_back(Store);
9109 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
9110 &MemOps[0], MemOps.size());
9113 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
9114 assert(Subtarget->is64Bit() &&
9115 "LowerVAARG only handles 64-bit va_arg!");
9116 assert((Subtarget->isTargetLinux() ||
9117 Subtarget->isTargetDarwin()) &&
9118 "Unhandled target in LowerVAARG");
9119 assert(Op.getNode()->getNumOperands() == 4);
9120 SDValue Chain = Op.getOperand(0);
9121 SDValue SrcPtr = Op.getOperand(1);
9122 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
9123 unsigned Align = Op.getConstantOperandVal(3);
9124 DebugLoc dl = Op.getDebugLoc();
9126 EVT ArgVT = Op.getNode()->getValueType(0);
9127 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
9128 uint32_t ArgSize = getTargetData()->getTypeAllocSize(ArgTy);
9131 // Decide which area this value should be read from.
9132 // TODO: Implement the AMD64 ABI in its entirety. This simple
9133 // selection mechanism works only for the basic types.
9134 if (ArgVT == MVT::f80) {
9135 llvm_unreachable("va_arg for f80 not yet implemented");
9136 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
9137 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
9138 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
9139 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
9141 llvm_unreachable("Unhandled argument type in LowerVAARG");
9145 // Sanity Check: Make sure using fp_offset makes sense.
9146 assert(!getTargetMachine().Options.UseSoftFloat &&
9147 !(DAG.getMachineFunction()
9148 .getFunction()->hasFnAttr(Attribute::NoImplicitFloat)) &&
9149 Subtarget->hasSSE1());
9152 // Insert VAARG_64 node into the DAG
9153 // VAARG_64 returns two values: Variable Argument Address, Chain
9154 SmallVector<SDValue, 11> InstOps;
9155 InstOps.push_back(Chain);
9156 InstOps.push_back(SrcPtr);
9157 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
9158 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
9159 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
9160 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
9161 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
9162 VTs, &InstOps[0], InstOps.size(),
9164 MachinePointerInfo(SV),
9169 Chain = VAARG.getValue(1);
9171 // Load the next argument and return it
9172 return DAG.getLoad(ArgVT, dl,
9175 MachinePointerInfo(),
9176 false, false, false, 0);
9179 SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const {
9180 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
9181 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
9182 SDValue Chain = Op.getOperand(0);
9183 SDValue DstPtr = Op.getOperand(1);
9184 SDValue SrcPtr = Op.getOperand(2);
9185 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
9186 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
9187 DebugLoc DL = Op.getDebugLoc();
9189 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
9190 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
9192 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
9195 // getTargetVShiftNOde - Handle vector element shifts where the shift amount
9196 // may or may not be a constant. Takes immediate version of shift as input.
9197 static SDValue getTargetVShiftNode(unsigned Opc, DebugLoc dl, EVT VT,
9198 SDValue SrcOp, SDValue ShAmt,
9199 SelectionDAG &DAG) {
9200 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
9202 if (isa<ConstantSDNode>(ShAmt)) {
9204 default: llvm_unreachable("Unknown target vector shift node");
9208 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
9212 // Change opcode to non-immediate version
9214 default: llvm_unreachable("Unknown target vector shift node");
9215 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
9216 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
9217 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
9220 // Need to build a vector containing shift amount
9221 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
9224 ShOps[1] = DAG.getConstant(0, MVT::i32);
9225 ShOps[2] = DAG.getUNDEF(MVT::i32);
9226 ShOps[3] = DAG.getUNDEF(MVT::i32);
9227 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, &ShOps[0], 4);
9228 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt);
9229 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
9233 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const {
9234 DebugLoc dl = Op.getDebugLoc();
9235 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9237 default: return SDValue(); // Don't custom lower most intrinsics.
9238 // Comparison intrinsics.
9239 case Intrinsic::x86_sse_comieq_ss:
9240 case Intrinsic::x86_sse_comilt_ss:
9241 case Intrinsic::x86_sse_comile_ss:
9242 case Intrinsic::x86_sse_comigt_ss:
9243 case Intrinsic::x86_sse_comige_ss:
9244 case Intrinsic::x86_sse_comineq_ss:
9245 case Intrinsic::x86_sse_ucomieq_ss:
9246 case Intrinsic::x86_sse_ucomilt_ss:
9247 case Intrinsic::x86_sse_ucomile_ss:
9248 case Intrinsic::x86_sse_ucomigt_ss:
9249 case Intrinsic::x86_sse_ucomige_ss:
9250 case Intrinsic::x86_sse_ucomineq_ss:
9251 case Intrinsic::x86_sse2_comieq_sd:
9252 case Intrinsic::x86_sse2_comilt_sd:
9253 case Intrinsic::x86_sse2_comile_sd:
9254 case Intrinsic::x86_sse2_comigt_sd:
9255 case Intrinsic::x86_sse2_comige_sd:
9256 case Intrinsic::x86_sse2_comineq_sd:
9257 case Intrinsic::x86_sse2_ucomieq_sd:
9258 case Intrinsic::x86_sse2_ucomilt_sd:
9259 case Intrinsic::x86_sse2_ucomile_sd:
9260 case Intrinsic::x86_sse2_ucomigt_sd:
9261 case Intrinsic::x86_sse2_ucomige_sd:
9262 case Intrinsic::x86_sse2_ucomineq_sd: {
9264 ISD::CondCode CC = ISD::SETCC_INVALID;
9266 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
9267 case Intrinsic::x86_sse_comieq_ss:
9268 case Intrinsic::x86_sse2_comieq_sd:
9272 case Intrinsic::x86_sse_comilt_ss:
9273 case Intrinsic::x86_sse2_comilt_sd:
9277 case Intrinsic::x86_sse_comile_ss:
9278 case Intrinsic::x86_sse2_comile_sd:
9282 case Intrinsic::x86_sse_comigt_ss:
9283 case Intrinsic::x86_sse2_comigt_sd:
9287 case Intrinsic::x86_sse_comige_ss:
9288 case Intrinsic::x86_sse2_comige_sd:
9292 case Intrinsic::x86_sse_comineq_ss:
9293 case Intrinsic::x86_sse2_comineq_sd:
9297 case Intrinsic::x86_sse_ucomieq_ss:
9298 case Intrinsic::x86_sse2_ucomieq_sd:
9299 Opc = X86ISD::UCOMI;
9302 case Intrinsic::x86_sse_ucomilt_ss:
9303 case Intrinsic::x86_sse2_ucomilt_sd:
9304 Opc = X86ISD::UCOMI;
9307 case Intrinsic::x86_sse_ucomile_ss:
9308 case Intrinsic::x86_sse2_ucomile_sd:
9309 Opc = X86ISD::UCOMI;
9312 case Intrinsic::x86_sse_ucomigt_ss:
9313 case Intrinsic::x86_sse2_ucomigt_sd:
9314 Opc = X86ISD::UCOMI;
9317 case Intrinsic::x86_sse_ucomige_ss:
9318 case Intrinsic::x86_sse2_ucomige_sd:
9319 Opc = X86ISD::UCOMI;
9322 case Intrinsic::x86_sse_ucomineq_ss:
9323 case Intrinsic::x86_sse2_ucomineq_sd:
9324 Opc = X86ISD::UCOMI;
9329 SDValue LHS = Op.getOperand(1);
9330 SDValue RHS = Op.getOperand(2);
9331 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
9332 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
9333 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
9334 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9335 DAG.getConstant(X86CC, MVT::i8), Cond);
9336 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
9338 // XOP comparison intrinsics
9339 case Intrinsic::x86_xop_vpcomltb:
9340 case Intrinsic::x86_xop_vpcomltw:
9341 case Intrinsic::x86_xop_vpcomltd:
9342 case Intrinsic::x86_xop_vpcomltq:
9343 case Intrinsic::x86_xop_vpcomltub:
9344 case Intrinsic::x86_xop_vpcomltuw:
9345 case Intrinsic::x86_xop_vpcomltud:
9346 case Intrinsic::x86_xop_vpcomltuq:
9347 case Intrinsic::x86_xop_vpcomleb:
9348 case Intrinsic::x86_xop_vpcomlew:
9349 case Intrinsic::x86_xop_vpcomled:
9350 case Intrinsic::x86_xop_vpcomleq:
9351 case Intrinsic::x86_xop_vpcomleub:
9352 case Intrinsic::x86_xop_vpcomleuw:
9353 case Intrinsic::x86_xop_vpcomleud:
9354 case Intrinsic::x86_xop_vpcomleuq:
9355 case Intrinsic::x86_xop_vpcomgtb:
9356 case Intrinsic::x86_xop_vpcomgtw:
9357 case Intrinsic::x86_xop_vpcomgtd:
9358 case Intrinsic::x86_xop_vpcomgtq:
9359 case Intrinsic::x86_xop_vpcomgtub:
9360 case Intrinsic::x86_xop_vpcomgtuw:
9361 case Intrinsic::x86_xop_vpcomgtud:
9362 case Intrinsic::x86_xop_vpcomgtuq:
9363 case Intrinsic::x86_xop_vpcomgeb:
9364 case Intrinsic::x86_xop_vpcomgew:
9365 case Intrinsic::x86_xop_vpcomged:
9366 case Intrinsic::x86_xop_vpcomgeq:
9367 case Intrinsic::x86_xop_vpcomgeub:
9368 case Intrinsic::x86_xop_vpcomgeuw:
9369 case Intrinsic::x86_xop_vpcomgeud:
9370 case Intrinsic::x86_xop_vpcomgeuq:
9371 case Intrinsic::x86_xop_vpcomeqb:
9372 case Intrinsic::x86_xop_vpcomeqw:
9373 case Intrinsic::x86_xop_vpcomeqd:
9374 case Intrinsic::x86_xop_vpcomeqq:
9375 case Intrinsic::x86_xop_vpcomequb:
9376 case Intrinsic::x86_xop_vpcomequw:
9377 case Intrinsic::x86_xop_vpcomequd:
9378 case Intrinsic::x86_xop_vpcomequq:
9379 case Intrinsic::x86_xop_vpcomneb:
9380 case Intrinsic::x86_xop_vpcomnew:
9381 case Intrinsic::x86_xop_vpcomned:
9382 case Intrinsic::x86_xop_vpcomneq:
9383 case Intrinsic::x86_xop_vpcomneub:
9384 case Intrinsic::x86_xop_vpcomneuw:
9385 case Intrinsic::x86_xop_vpcomneud:
9386 case Intrinsic::x86_xop_vpcomneuq:
9387 case Intrinsic::x86_xop_vpcomfalseb:
9388 case Intrinsic::x86_xop_vpcomfalsew:
9389 case Intrinsic::x86_xop_vpcomfalsed:
9390 case Intrinsic::x86_xop_vpcomfalseq:
9391 case Intrinsic::x86_xop_vpcomfalseub:
9392 case Intrinsic::x86_xop_vpcomfalseuw:
9393 case Intrinsic::x86_xop_vpcomfalseud:
9394 case Intrinsic::x86_xop_vpcomfalseuq:
9395 case Intrinsic::x86_xop_vpcomtrueb:
9396 case Intrinsic::x86_xop_vpcomtruew:
9397 case Intrinsic::x86_xop_vpcomtrued:
9398 case Intrinsic::x86_xop_vpcomtrueq:
9399 case Intrinsic::x86_xop_vpcomtrueub:
9400 case Intrinsic::x86_xop_vpcomtrueuw:
9401 case Intrinsic::x86_xop_vpcomtrueud:
9402 case Intrinsic::x86_xop_vpcomtrueuq: {
9407 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
9408 case Intrinsic::x86_xop_vpcomltb:
9409 case Intrinsic::x86_xop_vpcomltw:
9410 case Intrinsic::x86_xop_vpcomltd:
9411 case Intrinsic::x86_xop_vpcomltq:
9413 Opc = X86ISD::VPCOM;
9415 case Intrinsic::x86_xop_vpcomltub:
9416 case Intrinsic::x86_xop_vpcomltuw:
9417 case Intrinsic::x86_xop_vpcomltud:
9418 case Intrinsic::x86_xop_vpcomltuq:
9420 Opc = X86ISD::VPCOMU;
9422 case Intrinsic::x86_xop_vpcomleb:
9423 case Intrinsic::x86_xop_vpcomlew:
9424 case Intrinsic::x86_xop_vpcomled:
9425 case Intrinsic::x86_xop_vpcomleq:
9427 Opc = X86ISD::VPCOM;
9429 case Intrinsic::x86_xop_vpcomleub:
9430 case Intrinsic::x86_xop_vpcomleuw:
9431 case Intrinsic::x86_xop_vpcomleud:
9432 case Intrinsic::x86_xop_vpcomleuq:
9434 Opc = X86ISD::VPCOMU;
9436 case Intrinsic::x86_xop_vpcomgtb:
9437 case Intrinsic::x86_xop_vpcomgtw:
9438 case Intrinsic::x86_xop_vpcomgtd:
9439 case Intrinsic::x86_xop_vpcomgtq:
9441 Opc = X86ISD::VPCOM;
9443 case Intrinsic::x86_xop_vpcomgtub:
9444 case Intrinsic::x86_xop_vpcomgtuw:
9445 case Intrinsic::x86_xop_vpcomgtud:
9446 case Intrinsic::x86_xop_vpcomgtuq:
9448 Opc = X86ISD::VPCOMU;
9450 case Intrinsic::x86_xop_vpcomgeb:
9451 case Intrinsic::x86_xop_vpcomgew:
9452 case Intrinsic::x86_xop_vpcomged:
9453 case Intrinsic::x86_xop_vpcomgeq:
9455 Opc = X86ISD::VPCOM;
9457 case Intrinsic::x86_xop_vpcomgeub:
9458 case Intrinsic::x86_xop_vpcomgeuw:
9459 case Intrinsic::x86_xop_vpcomgeud:
9460 case Intrinsic::x86_xop_vpcomgeuq:
9462 Opc = X86ISD::VPCOMU;
9464 case Intrinsic::x86_xop_vpcomeqb:
9465 case Intrinsic::x86_xop_vpcomeqw:
9466 case Intrinsic::x86_xop_vpcomeqd:
9467 case Intrinsic::x86_xop_vpcomeqq:
9469 Opc = X86ISD::VPCOM;
9471 case Intrinsic::x86_xop_vpcomequb:
9472 case Intrinsic::x86_xop_vpcomequw:
9473 case Intrinsic::x86_xop_vpcomequd:
9474 case Intrinsic::x86_xop_vpcomequq:
9476 Opc = X86ISD::VPCOMU;
9478 case Intrinsic::x86_xop_vpcomneb:
9479 case Intrinsic::x86_xop_vpcomnew:
9480 case Intrinsic::x86_xop_vpcomned:
9481 case Intrinsic::x86_xop_vpcomneq:
9483 Opc = X86ISD::VPCOM;
9485 case Intrinsic::x86_xop_vpcomneub:
9486 case Intrinsic::x86_xop_vpcomneuw:
9487 case Intrinsic::x86_xop_vpcomneud:
9488 case Intrinsic::x86_xop_vpcomneuq:
9490 Opc = X86ISD::VPCOMU;
9492 case Intrinsic::x86_xop_vpcomfalseb:
9493 case Intrinsic::x86_xop_vpcomfalsew:
9494 case Intrinsic::x86_xop_vpcomfalsed:
9495 case Intrinsic::x86_xop_vpcomfalseq:
9497 Opc = X86ISD::VPCOM;
9499 case Intrinsic::x86_xop_vpcomfalseub:
9500 case Intrinsic::x86_xop_vpcomfalseuw:
9501 case Intrinsic::x86_xop_vpcomfalseud:
9502 case Intrinsic::x86_xop_vpcomfalseuq:
9504 Opc = X86ISD::VPCOMU;
9506 case Intrinsic::x86_xop_vpcomtrueb:
9507 case Intrinsic::x86_xop_vpcomtruew:
9508 case Intrinsic::x86_xop_vpcomtrued:
9509 case Intrinsic::x86_xop_vpcomtrueq:
9511 Opc = X86ISD::VPCOM;
9513 case Intrinsic::x86_xop_vpcomtrueub:
9514 case Intrinsic::x86_xop_vpcomtrueuw:
9515 case Intrinsic::x86_xop_vpcomtrueud:
9516 case Intrinsic::x86_xop_vpcomtrueuq:
9518 Opc = X86ISD::VPCOMU;
9522 SDValue LHS = Op.getOperand(1);
9523 SDValue RHS = Op.getOperand(2);
9524 return DAG.getNode(Opc, dl, Op.getValueType(), LHS, RHS,
9525 DAG.getConstant(CC, MVT::i8));
9528 // Arithmetic intrinsics.
9529 case Intrinsic::x86_sse2_pmulu_dq:
9530 case Intrinsic::x86_avx2_pmulu_dq:
9531 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
9532 Op.getOperand(1), Op.getOperand(2));
9533 case Intrinsic::x86_sse3_hadd_ps:
9534 case Intrinsic::x86_sse3_hadd_pd:
9535 case Intrinsic::x86_avx_hadd_ps_256:
9536 case Intrinsic::x86_avx_hadd_pd_256:
9537 return DAG.getNode(X86ISD::FHADD, dl, Op.getValueType(),
9538 Op.getOperand(1), Op.getOperand(2));
9539 case Intrinsic::x86_sse3_hsub_ps:
9540 case Intrinsic::x86_sse3_hsub_pd:
9541 case Intrinsic::x86_avx_hsub_ps_256:
9542 case Intrinsic::x86_avx_hsub_pd_256:
9543 return DAG.getNode(X86ISD::FHSUB, dl, Op.getValueType(),
9544 Op.getOperand(1), Op.getOperand(2));
9545 case Intrinsic::x86_ssse3_phadd_w_128:
9546 case Intrinsic::x86_ssse3_phadd_d_128:
9547 case Intrinsic::x86_avx2_phadd_w:
9548 case Intrinsic::x86_avx2_phadd_d:
9549 return DAG.getNode(X86ISD::HADD, dl, Op.getValueType(),
9550 Op.getOperand(1), Op.getOperand(2));
9551 case Intrinsic::x86_ssse3_phsub_w_128:
9552 case Intrinsic::x86_ssse3_phsub_d_128:
9553 case Intrinsic::x86_avx2_phsub_w:
9554 case Intrinsic::x86_avx2_phsub_d:
9555 return DAG.getNode(X86ISD::HSUB, dl, Op.getValueType(),
9556 Op.getOperand(1), Op.getOperand(2));
9557 case Intrinsic::x86_avx2_psllv_d:
9558 case Intrinsic::x86_avx2_psllv_q:
9559 case Intrinsic::x86_avx2_psllv_d_256:
9560 case Intrinsic::x86_avx2_psllv_q_256:
9561 return DAG.getNode(ISD::SHL, dl, Op.getValueType(),
9562 Op.getOperand(1), Op.getOperand(2));
9563 case Intrinsic::x86_avx2_psrlv_d:
9564 case Intrinsic::x86_avx2_psrlv_q:
9565 case Intrinsic::x86_avx2_psrlv_d_256:
9566 case Intrinsic::x86_avx2_psrlv_q_256:
9567 return DAG.getNode(ISD::SRL, dl, Op.getValueType(),
9568 Op.getOperand(1), Op.getOperand(2));
9569 case Intrinsic::x86_avx2_psrav_d:
9570 case Intrinsic::x86_avx2_psrav_d_256:
9571 return DAG.getNode(ISD::SRA, dl, Op.getValueType(),
9572 Op.getOperand(1), Op.getOperand(2));
9573 case Intrinsic::x86_ssse3_pshuf_b_128:
9574 case Intrinsic::x86_avx2_pshuf_b:
9575 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
9576 Op.getOperand(1), Op.getOperand(2));
9577 case Intrinsic::x86_ssse3_psign_b_128:
9578 case Intrinsic::x86_ssse3_psign_w_128:
9579 case Intrinsic::x86_ssse3_psign_d_128:
9580 case Intrinsic::x86_avx2_psign_b:
9581 case Intrinsic::x86_avx2_psign_w:
9582 case Intrinsic::x86_avx2_psign_d:
9583 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
9584 Op.getOperand(1), Op.getOperand(2));
9585 case Intrinsic::x86_sse41_insertps:
9586 return DAG.getNode(X86ISD::INSERTPS, dl, Op.getValueType(),
9587 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
9588 case Intrinsic::x86_avx_vperm2f128_ps_256:
9589 case Intrinsic::x86_avx_vperm2f128_pd_256:
9590 case Intrinsic::x86_avx_vperm2f128_si_256:
9591 case Intrinsic::x86_avx2_vperm2i128:
9592 return DAG.getNode(X86ISD::VPERM2X128, dl, Op.getValueType(),
9593 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
9594 case Intrinsic::x86_avx2_permd:
9595 case Intrinsic::x86_avx2_permps:
9596 // Operands intentionally swapped. Mask is last operand to intrinsic,
9597 // but second operand for node/intruction.
9598 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
9599 Op.getOperand(2), Op.getOperand(1));
9601 // ptest and testp intrinsics. The intrinsic these come from are designed to
9602 // return an integer value, not just an instruction so lower it to the ptest
9603 // or testp pattern and a setcc for the result.
9604 case Intrinsic::x86_sse41_ptestz:
9605 case Intrinsic::x86_sse41_ptestc:
9606 case Intrinsic::x86_sse41_ptestnzc:
9607 case Intrinsic::x86_avx_ptestz_256:
9608 case Intrinsic::x86_avx_ptestc_256:
9609 case Intrinsic::x86_avx_ptestnzc_256:
9610 case Intrinsic::x86_avx_vtestz_ps:
9611 case Intrinsic::x86_avx_vtestc_ps:
9612 case Intrinsic::x86_avx_vtestnzc_ps:
9613 case Intrinsic::x86_avx_vtestz_pd:
9614 case Intrinsic::x86_avx_vtestc_pd:
9615 case Intrinsic::x86_avx_vtestnzc_pd:
9616 case Intrinsic::x86_avx_vtestz_ps_256:
9617 case Intrinsic::x86_avx_vtestc_ps_256:
9618 case Intrinsic::x86_avx_vtestnzc_ps_256:
9619 case Intrinsic::x86_avx_vtestz_pd_256:
9620 case Intrinsic::x86_avx_vtestc_pd_256:
9621 case Intrinsic::x86_avx_vtestnzc_pd_256: {
9622 bool IsTestPacked = false;
9625 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
9626 case Intrinsic::x86_avx_vtestz_ps:
9627 case Intrinsic::x86_avx_vtestz_pd:
9628 case Intrinsic::x86_avx_vtestz_ps_256:
9629 case Intrinsic::x86_avx_vtestz_pd_256:
9630 IsTestPacked = true; // Fallthrough
9631 case Intrinsic::x86_sse41_ptestz:
9632 case Intrinsic::x86_avx_ptestz_256:
9634 X86CC = X86::COND_E;
9636 case Intrinsic::x86_avx_vtestc_ps:
9637 case Intrinsic::x86_avx_vtestc_pd:
9638 case Intrinsic::x86_avx_vtestc_ps_256:
9639 case Intrinsic::x86_avx_vtestc_pd_256:
9640 IsTestPacked = true; // Fallthrough
9641 case Intrinsic::x86_sse41_ptestc:
9642 case Intrinsic::x86_avx_ptestc_256:
9644 X86CC = X86::COND_B;
9646 case Intrinsic::x86_avx_vtestnzc_ps:
9647 case Intrinsic::x86_avx_vtestnzc_pd:
9648 case Intrinsic::x86_avx_vtestnzc_ps_256:
9649 case Intrinsic::x86_avx_vtestnzc_pd_256:
9650 IsTestPacked = true; // Fallthrough
9651 case Intrinsic::x86_sse41_ptestnzc:
9652 case Intrinsic::x86_avx_ptestnzc_256:
9654 X86CC = X86::COND_A;
9658 SDValue LHS = Op.getOperand(1);
9659 SDValue RHS = Op.getOperand(2);
9660 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
9661 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
9662 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
9663 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
9664 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
9667 // SSE/AVX shift intrinsics
9668 case Intrinsic::x86_sse2_psll_w:
9669 case Intrinsic::x86_sse2_psll_d:
9670 case Intrinsic::x86_sse2_psll_q:
9671 case Intrinsic::x86_avx2_psll_w:
9672 case Intrinsic::x86_avx2_psll_d:
9673 case Intrinsic::x86_avx2_psll_q:
9674 return DAG.getNode(X86ISD::VSHL, dl, Op.getValueType(),
9675 Op.getOperand(1), Op.getOperand(2));
9676 case Intrinsic::x86_sse2_psrl_w:
9677 case Intrinsic::x86_sse2_psrl_d:
9678 case Intrinsic::x86_sse2_psrl_q:
9679 case Intrinsic::x86_avx2_psrl_w:
9680 case Intrinsic::x86_avx2_psrl_d:
9681 case Intrinsic::x86_avx2_psrl_q:
9682 return DAG.getNode(X86ISD::VSRL, dl, Op.getValueType(),
9683 Op.getOperand(1), Op.getOperand(2));
9684 case Intrinsic::x86_sse2_psra_w:
9685 case Intrinsic::x86_sse2_psra_d:
9686 case Intrinsic::x86_avx2_psra_w:
9687 case Intrinsic::x86_avx2_psra_d:
9688 return DAG.getNode(X86ISD::VSRA, dl, Op.getValueType(),
9689 Op.getOperand(1), Op.getOperand(2));
9690 case Intrinsic::x86_sse2_pslli_w:
9691 case Intrinsic::x86_sse2_pslli_d:
9692 case Intrinsic::x86_sse2_pslli_q:
9693 case Intrinsic::x86_avx2_pslli_w:
9694 case Intrinsic::x86_avx2_pslli_d:
9695 case Intrinsic::x86_avx2_pslli_q:
9696 return getTargetVShiftNode(X86ISD::VSHLI, dl, Op.getValueType(),
9697 Op.getOperand(1), Op.getOperand(2), DAG);
9698 case Intrinsic::x86_sse2_psrli_w:
9699 case Intrinsic::x86_sse2_psrli_d:
9700 case Intrinsic::x86_sse2_psrli_q:
9701 case Intrinsic::x86_avx2_psrli_w:
9702 case Intrinsic::x86_avx2_psrli_d:
9703 case Intrinsic::x86_avx2_psrli_q:
9704 return getTargetVShiftNode(X86ISD::VSRLI, dl, Op.getValueType(),
9705 Op.getOperand(1), Op.getOperand(2), DAG);
9706 case Intrinsic::x86_sse2_psrai_w:
9707 case Intrinsic::x86_sse2_psrai_d:
9708 case Intrinsic::x86_avx2_psrai_w:
9709 case Intrinsic::x86_avx2_psrai_d:
9710 return getTargetVShiftNode(X86ISD::VSRAI, dl, Op.getValueType(),
9711 Op.getOperand(1), Op.getOperand(2), DAG);
9712 // Fix vector shift instructions where the last operand is a non-immediate
9714 case Intrinsic::x86_mmx_pslli_w:
9715 case Intrinsic::x86_mmx_pslli_d:
9716 case Intrinsic::x86_mmx_pslli_q:
9717 case Intrinsic::x86_mmx_psrli_w:
9718 case Intrinsic::x86_mmx_psrli_d:
9719 case Intrinsic::x86_mmx_psrli_q:
9720 case Intrinsic::x86_mmx_psrai_w:
9721 case Intrinsic::x86_mmx_psrai_d: {
9722 SDValue ShAmt = Op.getOperand(2);
9723 if (isa<ConstantSDNode>(ShAmt))
9726 unsigned NewIntNo = 0;
9728 case Intrinsic::x86_mmx_pslli_w:
9729 NewIntNo = Intrinsic::x86_mmx_psll_w;
9731 case Intrinsic::x86_mmx_pslli_d:
9732 NewIntNo = Intrinsic::x86_mmx_psll_d;
9734 case Intrinsic::x86_mmx_pslli_q:
9735 NewIntNo = Intrinsic::x86_mmx_psll_q;
9737 case Intrinsic::x86_mmx_psrli_w:
9738 NewIntNo = Intrinsic::x86_mmx_psrl_w;
9740 case Intrinsic::x86_mmx_psrli_d:
9741 NewIntNo = Intrinsic::x86_mmx_psrl_d;
9743 case Intrinsic::x86_mmx_psrli_q:
9744 NewIntNo = Intrinsic::x86_mmx_psrl_q;
9746 case Intrinsic::x86_mmx_psrai_w:
9747 NewIntNo = Intrinsic::x86_mmx_psra_w;
9749 case Intrinsic::x86_mmx_psrai_d:
9750 NewIntNo = Intrinsic::x86_mmx_psra_d;
9752 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
9755 // The vector shift intrinsics with scalars uses 32b shift amounts but
9756 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
9758 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, ShAmt,
9759 DAG.getConstant(0, MVT::i32));
9760 // FIXME this must be lowered to get rid of the invalid type.
9762 EVT VT = Op.getValueType();
9763 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt);
9764 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9765 DAG.getConstant(NewIntNo, MVT::i32),
9766 Op.getOperand(1), ShAmt);
9771 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
9772 SelectionDAG &DAG) const {
9773 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
9774 MFI->setReturnAddressIsTaken(true);
9776 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9777 DebugLoc dl = Op.getDebugLoc();
9780 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
9782 DAG.getConstant(TD->getPointerSize(),
9783 Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
9784 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9785 DAG.getNode(ISD::ADD, dl, getPointerTy(),
9787 MachinePointerInfo(), false, false, false, 0);
9790 // Just load the return address.
9791 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
9792 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9793 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
9796 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
9797 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
9798 MFI->setFrameAddressIsTaken(true);
9800 EVT VT = Op.getValueType();
9801 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
9802 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9803 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
9804 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
9806 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
9807 MachinePointerInfo(),
9808 false, false, false, 0);
9812 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
9813 SelectionDAG &DAG) const {
9814 return DAG.getIntPtrConstant(2*TD->getPointerSize());
9817 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
9818 MachineFunction &MF = DAG.getMachineFunction();
9819 SDValue Chain = Op.getOperand(0);
9820 SDValue Offset = Op.getOperand(1);
9821 SDValue Handler = Op.getOperand(2);
9822 DebugLoc dl = Op.getDebugLoc();
9824 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
9825 Subtarget->is64Bit() ? X86::RBP : X86::EBP,
9827 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
9829 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Frame,
9830 DAG.getIntPtrConstant(TD->getPointerSize()));
9831 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
9832 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
9834 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
9835 MF.getRegInfo().addLiveOut(StoreAddrReg);
9837 return DAG.getNode(X86ISD::EH_RETURN, dl,
9839 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
9842 SDValue X86TargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
9843 SelectionDAG &DAG) const {
9844 return Op.getOperand(0);
9847 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
9848 SelectionDAG &DAG) const {
9849 SDValue Root = Op.getOperand(0);
9850 SDValue Trmp = Op.getOperand(1); // trampoline
9851 SDValue FPtr = Op.getOperand(2); // nested function
9852 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
9853 DebugLoc dl = Op.getDebugLoc();
9855 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
9857 if (Subtarget->is64Bit()) {
9858 SDValue OutChains[6];
9860 // Large code-model.
9861 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
9862 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
9864 const unsigned char N86R10 = X86_MC::getX86RegNum(X86::R10);
9865 const unsigned char N86R11 = X86_MC::getX86RegNum(X86::R11);
9867 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
9869 // Load the pointer to the nested function into R11.
9870 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
9871 SDValue Addr = Trmp;
9872 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9873 Addr, MachinePointerInfo(TrmpAddr),
9876 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9877 DAG.getConstant(2, MVT::i64));
9878 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
9879 MachinePointerInfo(TrmpAddr, 2),
9882 // Load the 'nest' parameter value into R10.
9883 // R10 is specified in X86CallingConv.td
9884 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
9885 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9886 DAG.getConstant(10, MVT::i64));
9887 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9888 Addr, MachinePointerInfo(TrmpAddr, 10),
9891 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9892 DAG.getConstant(12, MVT::i64));
9893 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
9894 MachinePointerInfo(TrmpAddr, 12),
9897 // Jump to the nested function.
9898 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
9899 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9900 DAG.getConstant(20, MVT::i64));
9901 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9902 Addr, MachinePointerInfo(TrmpAddr, 20),
9905 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
9906 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9907 DAG.getConstant(22, MVT::i64));
9908 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
9909 MachinePointerInfo(TrmpAddr, 22),
9912 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6);
9914 const Function *Func =
9915 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
9916 CallingConv::ID CC = Func->getCallingConv();
9921 llvm_unreachable("Unsupported calling convention");
9922 case CallingConv::C:
9923 case CallingConv::X86_StdCall: {
9924 // Pass 'nest' parameter in ECX.
9925 // Must be kept in sync with X86CallingConv.td
9928 // Check that ECX wasn't needed by an 'inreg' parameter.
9929 FunctionType *FTy = Func->getFunctionType();
9930 const AttrListPtr &Attrs = Func->getAttributes();
9932 if (!Attrs.isEmpty() && !Func->isVarArg()) {
9933 unsigned InRegCount = 0;
9936 for (FunctionType::param_iterator I = FTy->param_begin(),
9937 E = FTy->param_end(); I != E; ++I, ++Idx)
9938 if (Attrs.paramHasAttr(Idx, Attribute::InReg))
9939 // FIXME: should only count parameters that are lowered to integers.
9940 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
9942 if (InRegCount > 2) {
9943 report_fatal_error("Nest register in use - reduce number of inreg"
9949 case CallingConv::X86_FastCall:
9950 case CallingConv::X86_ThisCall:
9951 case CallingConv::Fast:
9952 // Pass 'nest' parameter in EAX.
9953 // Must be kept in sync with X86CallingConv.td
9958 SDValue OutChains[4];
9961 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9962 DAG.getConstant(10, MVT::i32));
9963 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
9965 // This is storing the opcode for MOV32ri.
9966 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
9967 const unsigned char N86Reg = X86_MC::getX86RegNum(NestReg);
9968 OutChains[0] = DAG.getStore(Root, dl,
9969 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
9970 Trmp, MachinePointerInfo(TrmpAddr),
9973 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9974 DAG.getConstant(1, MVT::i32));
9975 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
9976 MachinePointerInfo(TrmpAddr, 1),
9979 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
9980 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9981 DAG.getConstant(5, MVT::i32));
9982 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
9983 MachinePointerInfo(TrmpAddr, 5),
9986 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9987 DAG.getConstant(6, MVT::i32));
9988 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
9989 MachinePointerInfo(TrmpAddr, 6),
9992 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4);
9996 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
9997 SelectionDAG &DAG) const {
9999 The rounding mode is in bits 11:10 of FPSR, and has the following
10001 00 Round to nearest
10006 FLT_ROUNDS, on the other hand, expects the following:
10013 To perform the conversion, we do:
10014 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
10017 MachineFunction &MF = DAG.getMachineFunction();
10018 const TargetMachine &TM = MF.getTarget();
10019 const TargetFrameLowering &TFI = *TM.getFrameLowering();
10020 unsigned StackAlignment = TFI.getStackAlignment();
10021 EVT VT = Op.getValueType();
10022 DebugLoc DL = Op.getDebugLoc();
10024 // Save FP Control Word to stack slot
10025 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
10026 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
10029 MachineMemOperand *MMO =
10030 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
10031 MachineMemOperand::MOStore, 2, 2);
10033 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
10034 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
10035 DAG.getVTList(MVT::Other),
10036 Ops, 2, MVT::i16, MMO);
10038 // Load FP Control Word from stack slot
10039 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
10040 MachinePointerInfo(), false, false, false, 0);
10042 // Transform as necessary
10044 DAG.getNode(ISD::SRL, DL, MVT::i16,
10045 DAG.getNode(ISD::AND, DL, MVT::i16,
10046 CWD, DAG.getConstant(0x800, MVT::i16)),
10047 DAG.getConstant(11, MVT::i8));
10049 DAG.getNode(ISD::SRL, DL, MVT::i16,
10050 DAG.getNode(ISD::AND, DL, MVT::i16,
10051 CWD, DAG.getConstant(0x400, MVT::i16)),
10052 DAG.getConstant(9, MVT::i8));
10055 DAG.getNode(ISD::AND, DL, MVT::i16,
10056 DAG.getNode(ISD::ADD, DL, MVT::i16,
10057 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
10058 DAG.getConstant(1, MVT::i16)),
10059 DAG.getConstant(3, MVT::i16));
10062 return DAG.getNode((VT.getSizeInBits() < 16 ?
10063 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
10066 SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const {
10067 EVT VT = Op.getValueType();
10069 unsigned NumBits = VT.getSizeInBits();
10070 DebugLoc dl = Op.getDebugLoc();
10072 Op = Op.getOperand(0);
10073 if (VT == MVT::i8) {
10074 // Zero extend to i32 since there is not an i8 bsr.
10076 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
10079 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
10080 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
10081 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
10083 // If src is zero (i.e. bsr sets ZF), returns NumBits.
10086 DAG.getConstant(NumBits+NumBits-1, OpVT),
10087 DAG.getConstant(X86::COND_E, MVT::i8),
10090 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
10092 // Finally xor with NumBits-1.
10093 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
10096 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
10100 SDValue X86TargetLowering::LowerCTLZ_ZERO_UNDEF(SDValue Op,
10101 SelectionDAG &DAG) const {
10102 EVT VT = Op.getValueType();
10104 unsigned NumBits = VT.getSizeInBits();
10105 DebugLoc dl = Op.getDebugLoc();
10107 Op = Op.getOperand(0);
10108 if (VT == MVT::i8) {
10109 // Zero extend to i32 since there is not an i8 bsr.
10111 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
10114 // Issue a bsr (scan bits in reverse).
10115 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
10116 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
10118 // And xor with NumBits-1.
10119 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
10122 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
10126 SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) const {
10127 EVT VT = Op.getValueType();
10128 unsigned NumBits = VT.getSizeInBits();
10129 DebugLoc dl = Op.getDebugLoc();
10130 Op = Op.getOperand(0);
10132 // Issue a bsf (scan bits forward) which also sets EFLAGS.
10133 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
10134 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
10136 // If src is zero (i.e. bsf sets ZF), returns NumBits.
10139 DAG.getConstant(NumBits, VT),
10140 DAG.getConstant(X86::COND_E, MVT::i8),
10143 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops, array_lengthof(Ops));
10146 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
10147 // ones, and then concatenate the result back.
10148 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
10149 EVT VT = Op.getValueType();
10151 assert(VT.getSizeInBits() == 256 && VT.isInteger() &&
10152 "Unsupported value type for operation");
10154 int NumElems = VT.getVectorNumElements();
10155 DebugLoc dl = Op.getDebugLoc();
10157 // Extract the LHS vectors
10158 SDValue LHS = Op.getOperand(0);
10159 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
10160 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
10162 // Extract the RHS vectors
10163 SDValue RHS = Op.getOperand(1);
10164 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
10165 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
10167 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10168 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
10170 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
10171 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
10172 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
10175 SDValue X86TargetLowering::LowerADD(SDValue Op, SelectionDAG &DAG) const {
10176 assert(Op.getValueType().getSizeInBits() == 256 &&
10177 Op.getValueType().isInteger() &&
10178 "Only handle AVX 256-bit vector integer operation");
10179 return Lower256IntArith(Op, DAG);
10182 SDValue X86TargetLowering::LowerSUB(SDValue Op, SelectionDAG &DAG) const {
10183 assert(Op.getValueType().getSizeInBits() == 256 &&
10184 Op.getValueType().isInteger() &&
10185 "Only handle AVX 256-bit vector integer operation");
10186 return Lower256IntArith(Op, DAG);
10189 SDValue X86TargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
10190 EVT VT = Op.getValueType();
10192 // Decompose 256-bit ops into smaller 128-bit ops.
10193 if (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2())
10194 return Lower256IntArith(Op, DAG);
10196 assert((VT == MVT::v2i64 || VT == MVT::v4i64) &&
10197 "Only know how to lower V2I64/V4I64 multiply");
10199 DebugLoc dl = Op.getDebugLoc();
10201 // Ahi = psrlqi(a, 32);
10202 // Bhi = psrlqi(b, 32);
10204 // AloBlo = pmuludq(a, b);
10205 // AloBhi = pmuludq(a, Bhi);
10206 // AhiBlo = pmuludq(Ahi, b);
10208 // AloBhi = psllqi(AloBhi, 32);
10209 // AhiBlo = psllqi(AhiBlo, 32);
10210 // return AloBlo + AloBhi + AhiBlo;
10212 SDValue A = Op.getOperand(0);
10213 SDValue B = Op.getOperand(1);
10215 SDValue ShAmt = DAG.getConstant(32, MVT::i32);
10217 SDValue Ahi = DAG.getNode(X86ISD::VSRLI, dl, VT, A, ShAmt);
10218 SDValue Bhi = DAG.getNode(X86ISD::VSRLI, dl, VT, B, ShAmt);
10220 // Bit cast to 32-bit vectors for MULUDQ
10221 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 : MVT::v8i32;
10222 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
10223 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
10224 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
10225 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
10227 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
10228 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
10229 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
10231 AloBhi = DAG.getNode(X86ISD::VSHLI, dl, VT, AloBhi, ShAmt);
10232 AhiBlo = DAG.getNode(X86ISD::VSHLI, dl, VT, AhiBlo, ShAmt);
10234 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
10235 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
10238 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const {
10240 EVT VT = Op.getValueType();
10241 DebugLoc dl = Op.getDebugLoc();
10242 SDValue R = Op.getOperand(0);
10243 SDValue Amt = Op.getOperand(1);
10244 LLVMContext *Context = DAG.getContext();
10246 if (!Subtarget->hasSSE2())
10249 // Optimize shl/srl/sra with constant shift amount.
10250 if (isSplatVector(Amt.getNode())) {
10251 SDValue SclrAmt = Amt->getOperand(0);
10252 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
10253 uint64_t ShiftAmt = C->getZExtValue();
10255 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
10256 (Subtarget->hasAVX2() &&
10257 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16))) {
10258 if (Op.getOpcode() == ISD::SHL)
10259 return DAG.getNode(X86ISD::VSHLI, dl, VT, R,
10260 DAG.getConstant(ShiftAmt, MVT::i32));
10261 if (Op.getOpcode() == ISD::SRL)
10262 return DAG.getNode(X86ISD::VSRLI, dl, VT, R,
10263 DAG.getConstant(ShiftAmt, MVT::i32));
10264 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
10265 return DAG.getNode(X86ISD::VSRAI, dl, VT, R,
10266 DAG.getConstant(ShiftAmt, MVT::i32));
10269 if (VT == MVT::v16i8) {
10270 if (Op.getOpcode() == ISD::SHL) {
10271 // Make a large shift.
10272 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, R,
10273 DAG.getConstant(ShiftAmt, MVT::i32));
10274 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
10275 // Zero out the rightmost bits.
10276 SmallVector<SDValue, 16> V(16,
10277 DAG.getConstant(uint8_t(-1U << ShiftAmt),
10279 return DAG.getNode(ISD::AND, dl, VT, SHL,
10280 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
10282 if (Op.getOpcode() == ISD::SRL) {
10283 // Make a large shift.
10284 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v8i16, R,
10285 DAG.getConstant(ShiftAmt, MVT::i32));
10286 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
10287 // Zero out the leftmost bits.
10288 SmallVector<SDValue, 16> V(16,
10289 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
10291 return DAG.getNode(ISD::AND, dl, VT, SRL,
10292 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
10294 if (Op.getOpcode() == ISD::SRA) {
10295 if (ShiftAmt == 7) {
10296 // R s>> 7 === R s< 0
10297 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
10298 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
10301 // R s>> a === ((R u>> a) ^ m) - m
10302 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
10303 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
10305 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16);
10306 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
10307 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
10310 llvm_unreachable("Unknown shift opcode.");
10313 if (Subtarget->hasAVX2() && VT == MVT::v32i8) {
10314 if (Op.getOpcode() == ISD::SHL) {
10315 // Make a large shift.
10316 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v16i16, R,
10317 DAG.getConstant(ShiftAmt, MVT::i32));
10318 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
10319 // Zero out the rightmost bits.
10320 SmallVector<SDValue, 32> V(32,
10321 DAG.getConstant(uint8_t(-1U << ShiftAmt),
10323 return DAG.getNode(ISD::AND, dl, VT, SHL,
10324 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
10326 if (Op.getOpcode() == ISD::SRL) {
10327 // Make a large shift.
10328 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v16i16, R,
10329 DAG.getConstant(ShiftAmt, MVT::i32));
10330 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
10331 // Zero out the leftmost bits.
10332 SmallVector<SDValue, 32> V(32,
10333 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
10335 return DAG.getNode(ISD::AND, dl, VT, SRL,
10336 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
10338 if (Op.getOpcode() == ISD::SRA) {
10339 if (ShiftAmt == 7) {
10340 // R s>> 7 === R s< 0
10341 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
10342 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
10345 // R s>> a === ((R u>> a) ^ m) - m
10346 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
10347 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
10349 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32);
10350 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
10351 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
10354 llvm_unreachable("Unknown shift opcode.");
10359 // Lower SHL with variable shift amount.
10360 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
10361 Op = DAG.getNode(X86ISD::VSHLI, dl, VT, Op.getOperand(1),
10362 DAG.getConstant(23, MVT::i32));
10364 const uint32_t CV[] = { 0x3f800000U, 0x3f800000U, 0x3f800000U, 0x3f800000U};
10365 Constant *C = ConstantDataVector::get(*Context, CV);
10366 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
10367 SDValue Addend = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
10368 MachinePointerInfo::getConstantPool(),
10369 false, false, false, 16);
10371 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Addend);
10372 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
10373 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
10374 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
10376 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
10377 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
10380 Op = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, Op.getOperand(1),
10381 DAG.getConstant(5, MVT::i32));
10382 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
10384 // Turn 'a' into a mask suitable for VSELECT
10385 SDValue VSelM = DAG.getConstant(0x80, VT);
10386 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
10387 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
10389 SDValue CM1 = DAG.getConstant(0x0f, VT);
10390 SDValue CM2 = DAG.getConstant(0x3f, VT);
10392 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
10393 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
10394 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M,
10395 DAG.getConstant(4, MVT::i32), DAG);
10396 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
10397 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
10400 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
10401 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
10402 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
10404 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
10405 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
10406 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M,
10407 DAG.getConstant(2, MVT::i32), DAG);
10408 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
10409 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
10412 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
10413 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
10414 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
10416 // return VSELECT(r, r+r, a);
10417 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
10418 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
10422 // Decompose 256-bit shifts into smaller 128-bit shifts.
10423 if (VT.getSizeInBits() == 256) {
10424 unsigned NumElems = VT.getVectorNumElements();
10425 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10426 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
10428 // Extract the two vectors
10429 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
10430 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
10432 // Recreate the shift amount vectors
10433 SDValue Amt1, Amt2;
10434 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
10435 // Constant shift amount
10436 SmallVector<SDValue, 4> Amt1Csts;
10437 SmallVector<SDValue, 4> Amt2Csts;
10438 for (unsigned i = 0; i != NumElems/2; ++i)
10439 Amt1Csts.push_back(Amt->getOperand(i));
10440 for (unsigned i = NumElems/2; i != NumElems; ++i)
10441 Amt2Csts.push_back(Amt->getOperand(i));
10443 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
10444 &Amt1Csts[0], NumElems/2);
10445 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
10446 &Amt2Csts[0], NumElems/2);
10448 // Variable shift amount
10449 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
10450 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
10453 // Issue new vector shifts for the smaller types
10454 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
10455 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
10457 // Concatenate the result back
10458 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
10464 SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const {
10465 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
10466 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
10467 // looks for this combo and may remove the "setcc" instruction if the "setcc"
10468 // has only one use.
10469 SDNode *N = Op.getNode();
10470 SDValue LHS = N->getOperand(0);
10471 SDValue RHS = N->getOperand(1);
10472 unsigned BaseOp = 0;
10474 DebugLoc DL = Op.getDebugLoc();
10475 switch (Op.getOpcode()) {
10476 default: llvm_unreachable("Unknown ovf instruction!");
10478 // A subtract of one will be selected as a INC. Note that INC doesn't
10479 // set CF, so we can't do this for UADDO.
10480 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
10482 BaseOp = X86ISD::INC;
10483 Cond = X86::COND_O;
10486 BaseOp = X86ISD::ADD;
10487 Cond = X86::COND_O;
10490 BaseOp = X86ISD::ADD;
10491 Cond = X86::COND_B;
10494 // A subtract of one will be selected as a DEC. Note that DEC doesn't
10495 // set CF, so we can't do this for USUBO.
10496 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
10498 BaseOp = X86ISD::DEC;
10499 Cond = X86::COND_O;
10502 BaseOp = X86ISD::SUB;
10503 Cond = X86::COND_O;
10506 BaseOp = X86ISD::SUB;
10507 Cond = X86::COND_B;
10510 BaseOp = X86ISD::SMUL;
10511 Cond = X86::COND_O;
10513 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
10514 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
10516 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
10519 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
10520 DAG.getConstant(X86::COND_O, MVT::i32),
10521 SDValue(Sum.getNode(), 2));
10523 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
10527 // Also sets EFLAGS.
10528 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
10529 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
10532 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
10533 DAG.getConstant(Cond, MVT::i32),
10534 SDValue(Sum.getNode(), 1));
10536 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
10539 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
10540 SelectionDAG &DAG) const {
10541 DebugLoc dl = Op.getDebugLoc();
10542 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
10543 EVT VT = Op.getValueType();
10545 if (!Subtarget->hasSSE2() || !VT.isVector())
10548 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
10549 ExtraVT.getScalarType().getSizeInBits();
10550 SDValue ShAmt = DAG.getConstant(BitsDiff, MVT::i32);
10552 switch (VT.getSimpleVT().SimpleTy) {
10553 default: return SDValue();
10556 if (!Subtarget->hasAVX())
10558 if (!Subtarget->hasAVX2()) {
10559 // needs to be split
10560 int NumElems = VT.getVectorNumElements();
10562 // Extract the LHS vectors
10563 SDValue LHS = Op.getOperand(0);
10564 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
10565 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
10567 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10568 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
10570 EVT ExtraEltVT = ExtraVT.getVectorElementType();
10571 int ExtraNumElems = ExtraVT.getVectorNumElements();
10572 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
10574 SDValue Extra = DAG.getValueType(ExtraVT);
10576 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
10577 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
10579 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);;
10584 SDValue Tmp1 = getTargetVShiftNode(X86ISD::VSHLI, dl, VT,
10585 Op.getOperand(0), ShAmt, DAG);
10586 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, Tmp1, ShAmt, DAG);
10592 SDValue X86TargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const{
10593 DebugLoc dl = Op.getDebugLoc();
10595 // Go ahead and emit the fence on x86-64 even if we asked for no-sse2.
10596 // There isn't any reason to disable it if the target processor supports it.
10597 if (!Subtarget->hasSSE2() && !Subtarget->is64Bit()) {
10598 SDValue Chain = Op.getOperand(0);
10599 SDValue Zero = DAG.getConstant(0, MVT::i32);
10601 DAG.getRegister(X86::ESP, MVT::i32), // Base
10602 DAG.getTargetConstant(1, MVT::i8), // Scale
10603 DAG.getRegister(0, MVT::i32), // Index
10604 DAG.getTargetConstant(0, MVT::i32), // Disp
10605 DAG.getRegister(0, MVT::i32), // Segment.
10610 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
10611 array_lengthof(Ops));
10612 return SDValue(Res, 0);
10615 unsigned isDev = cast<ConstantSDNode>(Op.getOperand(5))->getZExtValue();
10617 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
10619 unsigned Op1 = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10620 unsigned Op2 = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
10621 unsigned Op3 = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
10622 unsigned Op4 = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
10624 // def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
10625 if (!Op1 && !Op2 && !Op3 && Op4)
10626 return DAG.getNode(X86ISD::SFENCE, dl, MVT::Other, Op.getOperand(0));
10628 // def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
10629 if (Op1 && !Op2 && !Op3 && !Op4)
10630 return DAG.getNode(X86ISD::LFENCE, dl, MVT::Other, Op.getOperand(0));
10632 // def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm), (i8 1)),
10634 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
10637 SDValue X86TargetLowering::LowerATOMIC_FENCE(SDValue Op,
10638 SelectionDAG &DAG) const {
10639 DebugLoc dl = Op.getDebugLoc();
10640 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
10641 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
10642 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
10643 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
10645 // The only fence that needs an instruction is a sequentially-consistent
10646 // cross-thread fence.
10647 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
10648 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
10649 // no-sse2). There isn't any reason to disable it if the target processor
10651 if (Subtarget->hasSSE2() || Subtarget->is64Bit())
10652 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
10654 SDValue Chain = Op.getOperand(0);
10655 SDValue Zero = DAG.getConstant(0, MVT::i32);
10657 DAG.getRegister(X86::ESP, MVT::i32), // Base
10658 DAG.getTargetConstant(1, MVT::i8), // Scale
10659 DAG.getRegister(0, MVT::i32), // Index
10660 DAG.getTargetConstant(0, MVT::i32), // Disp
10661 DAG.getRegister(0, MVT::i32), // Segment.
10666 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
10667 array_lengthof(Ops));
10668 return SDValue(Res, 0);
10671 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
10672 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
10676 SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const {
10677 EVT T = Op.getValueType();
10678 DebugLoc DL = Op.getDebugLoc();
10681 switch(T.getSimpleVT().SimpleTy) {
10682 default: llvm_unreachable("Invalid value type!");
10683 case MVT::i8: Reg = X86::AL; size = 1; break;
10684 case MVT::i16: Reg = X86::AX; size = 2; break;
10685 case MVT::i32: Reg = X86::EAX; size = 4; break;
10687 assert(Subtarget->is64Bit() && "Node not type legal!");
10688 Reg = X86::RAX; size = 8;
10691 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
10692 Op.getOperand(2), SDValue());
10693 SDValue Ops[] = { cpIn.getValue(0),
10696 DAG.getTargetConstant(size, MVT::i8),
10697 cpIn.getValue(1) };
10698 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10699 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
10700 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
10703 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
10707 SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
10708 SelectionDAG &DAG) const {
10709 assert(Subtarget->is64Bit() && "Result not type legalized?");
10710 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10711 SDValue TheChain = Op.getOperand(0);
10712 DebugLoc dl = Op.getDebugLoc();
10713 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
10714 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
10715 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
10717 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
10718 DAG.getConstant(32, MVT::i8));
10720 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
10723 return DAG.getMergeValues(Ops, 2, dl);
10726 SDValue X86TargetLowering::LowerBITCAST(SDValue Op,
10727 SelectionDAG &DAG) const {
10728 EVT SrcVT = Op.getOperand(0).getValueType();
10729 EVT DstVT = Op.getValueType();
10730 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
10731 Subtarget->hasMMX() && "Unexpected custom BITCAST");
10732 assert((DstVT == MVT::i64 ||
10733 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
10734 "Unexpected custom BITCAST");
10735 // i64 <=> MMX conversions are Legal.
10736 if (SrcVT==MVT::i64 && DstVT.isVector())
10738 if (DstVT==MVT::i64 && SrcVT.isVector())
10740 // MMX <=> MMX conversions are Legal.
10741 if (SrcVT.isVector() && DstVT.isVector())
10743 // All other conversions need to be expanded.
10747 SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const {
10748 SDNode *Node = Op.getNode();
10749 DebugLoc dl = Node->getDebugLoc();
10750 EVT T = Node->getValueType(0);
10751 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
10752 DAG.getConstant(0, T), Node->getOperand(2));
10753 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
10754 cast<AtomicSDNode>(Node)->getMemoryVT(),
10755 Node->getOperand(0),
10756 Node->getOperand(1), negOp,
10757 cast<AtomicSDNode>(Node)->getSrcValue(),
10758 cast<AtomicSDNode>(Node)->getAlignment(),
10759 cast<AtomicSDNode>(Node)->getOrdering(),
10760 cast<AtomicSDNode>(Node)->getSynchScope());
10763 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
10764 SDNode *Node = Op.getNode();
10765 DebugLoc dl = Node->getDebugLoc();
10766 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
10768 // Convert seq_cst store -> xchg
10769 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
10770 // FIXME: On 32-bit, store -> fist or movq would be more efficient
10771 // (The only way to get a 16-byte store is cmpxchg16b)
10772 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
10773 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
10774 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
10775 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
10776 cast<AtomicSDNode>(Node)->getMemoryVT(),
10777 Node->getOperand(0),
10778 Node->getOperand(1), Node->getOperand(2),
10779 cast<AtomicSDNode>(Node)->getMemOperand(),
10780 cast<AtomicSDNode>(Node)->getOrdering(),
10781 cast<AtomicSDNode>(Node)->getSynchScope());
10782 return Swap.getValue(1);
10784 // Other atomic stores have a simple pattern.
10788 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
10789 EVT VT = Op.getNode()->getValueType(0);
10791 // Let legalize expand this if it isn't a legal type yet.
10792 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
10795 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
10798 bool ExtraOp = false;
10799 switch (Op.getOpcode()) {
10800 default: llvm_unreachable("Invalid code");
10801 case ISD::ADDC: Opc = X86ISD::ADD; break;
10802 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
10803 case ISD::SUBC: Opc = X86ISD::SUB; break;
10804 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
10808 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
10810 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
10811 Op.getOperand(1), Op.getOperand(2));
10814 /// LowerOperation - Provide custom lowering hooks for some operations.
10816 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
10817 switch (Op.getOpcode()) {
10818 default: llvm_unreachable("Should not custom lower this!");
10819 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
10820 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op,DAG);
10821 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op,DAG);
10822 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG);
10823 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
10824 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
10825 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
10826 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
10827 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
10828 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
10829 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
10830 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
10831 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, DAG);
10832 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
10833 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
10834 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
10835 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
10836 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
10837 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
10838 case ISD::SHL_PARTS:
10839 case ISD::SRA_PARTS:
10840 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
10841 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
10842 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
10843 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
10844 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
10845 case ISD::FABS: return LowerFABS(Op, DAG);
10846 case ISD::FNEG: return LowerFNEG(Op, DAG);
10847 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
10848 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
10849 case ISD::SETCC: return LowerSETCC(Op, DAG);
10850 case ISD::SELECT: return LowerSELECT(Op, DAG);
10851 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
10852 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
10853 case ISD::VASTART: return LowerVASTART(Op, DAG);
10854 case ISD::VAARG: return LowerVAARG(Op, DAG);
10855 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
10856 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
10857 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
10858 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
10859 case ISD::FRAME_TO_ARGS_OFFSET:
10860 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
10861 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
10862 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
10863 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
10864 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
10865 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
10866 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
10867 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
10868 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
10869 case ISD::MUL: return LowerMUL(Op, DAG);
10872 case ISD::SHL: return LowerShift(Op, DAG);
10878 case ISD::UMULO: return LowerXALUO(Op, DAG);
10879 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
10880 case ISD::BITCAST: return LowerBITCAST(Op, DAG);
10884 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
10885 case ISD::ADD: return LowerADD(Op, DAG);
10886 case ISD::SUB: return LowerSUB(Op, DAG);
10890 static void ReplaceATOMIC_LOAD(SDNode *Node,
10891 SmallVectorImpl<SDValue> &Results,
10892 SelectionDAG &DAG) {
10893 DebugLoc dl = Node->getDebugLoc();
10894 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
10896 // Convert wide load -> cmpxchg8b/cmpxchg16b
10897 // FIXME: On 32-bit, load -> fild or movq would be more efficient
10898 // (The only way to get a 16-byte load is cmpxchg16b)
10899 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment.
10900 SDValue Zero = DAG.getConstant(0, VT);
10901 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT,
10902 Node->getOperand(0),
10903 Node->getOperand(1), Zero, Zero,
10904 cast<AtomicSDNode>(Node)->getMemOperand(),
10905 cast<AtomicSDNode>(Node)->getOrdering(),
10906 cast<AtomicSDNode>(Node)->getSynchScope());
10907 Results.push_back(Swap.getValue(0));
10908 Results.push_back(Swap.getValue(1));
10911 void X86TargetLowering::
10912 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
10913 SelectionDAG &DAG, unsigned NewOp) const {
10914 DebugLoc dl = Node->getDebugLoc();
10915 assert (Node->getValueType(0) == MVT::i64 &&
10916 "Only know how to expand i64 atomics");
10918 SDValue Chain = Node->getOperand(0);
10919 SDValue In1 = Node->getOperand(1);
10920 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
10921 Node->getOperand(2), DAG.getIntPtrConstant(0));
10922 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
10923 Node->getOperand(2), DAG.getIntPtrConstant(1));
10924 SDValue Ops[] = { Chain, In1, In2L, In2H };
10925 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
10927 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64,
10928 cast<MemSDNode>(Node)->getMemOperand());
10929 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
10930 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
10931 Results.push_back(Result.getValue(2));
10934 /// ReplaceNodeResults - Replace a node with an illegal result type
10935 /// with a new node built out of custom code.
10936 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
10937 SmallVectorImpl<SDValue>&Results,
10938 SelectionDAG &DAG) const {
10939 DebugLoc dl = N->getDebugLoc();
10940 switch (N->getOpcode()) {
10942 llvm_unreachable("Do not know how to custom type legalize this operation!");
10943 case ISD::SIGN_EXTEND_INREG:
10948 // We don't want to expand or promote these.
10950 case ISD::FP_TO_SINT:
10951 case ISD::FP_TO_UINT: {
10952 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
10954 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
10957 std::pair<SDValue,SDValue> Vals =
10958 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
10959 SDValue FIST = Vals.first, StackSlot = Vals.second;
10960 if (FIST.getNode() != 0) {
10961 EVT VT = N->getValueType(0);
10962 // Return a load from the stack slot.
10963 if (StackSlot.getNode() != 0)
10964 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
10965 MachinePointerInfo(),
10966 false, false, false, 0));
10968 Results.push_back(FIST);
10972 case ISD::READCYCLECOUNTER: {
10973 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10974 SDValue TheChain = N->getOperand(0);
10975 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
10976 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
10978 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
10980 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
10981 SDValue Ops[] = { eax, edx };
10982 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
10983 Results.push_back(edx.getValue(1));
10986 case ISD::ATOMIC_CMP_SWAP: {
10987 EVT T = N->getValueType(0);
10988 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
10989 bool Regs64bit = T == MVT::i128;
10990 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
10991 SDValue cpInL, cpInH;
10992 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
10993 DAG.getConstant(0, HalfT));
10994 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
10995 DAG.getConstant(1, HalfT));
10996 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
10997 Regs64bit ? X86::RAX : X86::EAX,
10999 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
11000 Regs64bit ? X86::RDX : X86::EDX,
11001 cpInH, cpInL.getValue(1));
11002 SDValue swapInL, swapInH;
11003 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
11004 DAG.getConstant(0, HalfT));
11005 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
11006 DAG.getConstant(1, HalfT));
11007 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
11008 Regs64bit ? X86::RBX : X86::EBX,
11009 swapInL, cpInH.getValue(1));
11010 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
11011 Regs64bit ? X86::RCX : X86::ECX,
11012 swapInH, swapInL.getValue(1));
11013 SDValue Ops[] = { swapInH.getValue(0),
11015 swapInH.getValue(1) };
11016 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
11017 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
11018 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
11019 X86ISD::LCMPXCHG8_DAG;
11020 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys,
11022 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
11023 Regs64bit ? X86::RAX : X86::EAX,
11024 HalfT, Result.getValue(1));
11025 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
11026 Regs64bit ? X86::RDX : X86::EDX,
11027 HalfT, cpOutL.getValue(2));
11028 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
11029 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF, 2));
11030 Results.push_back(cpOutH.getValue(1));
11033 case ISD::ATOMIC_LOAD_ADD:
11034 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG);
11036 case ISD::ATOMIC_LOAD_AND:
11037 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG);
11039 case ISD::ATOMIC_LOAD_NAND:
11040 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG);
11042 case ISD::ATOMIC_LOAD_OR:
11043 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG);
11045 case ISD::ATOMIC_LOAD_SUB:
11046 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG);
11048 case ISD::ATOMIC_LOAD_XOR:
11049 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG);
11051 case ISD::ATOMIC_SWAP:
11052 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG);
11054 case ISD::ATOMIC_LOAD:
11055 ReplaceATOMIC_LOAD(N, Results, DAG);
11059 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
11061 default: return NULL;
11062 case X86ISD::BSF: return "X86ISD::BSF";
11063 case X86ISD::BSR: return "X86ISD::BSR";
11064 case X86ISD::SHLD: return "X86ISD::SHLD";
11065 case X86ISD::SHRD: return "X86ISD::SHRD";
11066 case X86ISD::FAND: return "X86ISD::FAND";
11067 case X86ISD::FOR: return "X86ISD::FOR";
11068 case X86ISD::FXOR: return "X86ISD::FXOR";
11069 case X86ISD::FSRL: return "X86ISD::FSRL";
11070 case X86ISD::FILD: return "X86ISD::FILD";
11071 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
11072 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
11073 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
11074 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
11075 case X86ISD::FLD: return "X86ISD::FLD";
11076 case X86ISD::FST: return "X86ISD::FST";
11077 case X86ISD::CALL: return "X86ISD::CALL";
11078 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
11079 case X86ISD::BT: return "X86ISD::BT";
11080 case X86ISD::CMP: return "X86ISD::CMP";
11081 case X86ISD::COMI: return "X86ISD::COMI";
11082 case X86ISD::UCOMI: return "X86ISD::UCOMI";
11083 case X86ISD::SETCC: return "X86ISD::SETCC";
11084 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
11085 case X86ISD::FSETCCsd: return "X86ISD::FSETCCsd";
11086 case X86ISD::FSETCCss: return "X86ISD::FSETCCss";
11087 case X86ISD::CMOV: return "X86ISD::CMOV";
11088 case X86ISD::BRCOND: return "X86ISD::BRCOND";
11089 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
11090 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
11091 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
11092 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
11093 case X86ISD::Wrapper: return "X86ISD::Wrapper";
11094 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
11095 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
11096 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
11097 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
11098 case X86ISD::PINSRB: return "X86ISD::PINSRB";
11099 case X86ISD::PINSRW: return "X86ISD::PINSRW";
11100 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
11101 case X86ISD::ANDNP: return "X86ISD::ANDNP";
11102 case X86ISD::PSIGN: return "X86ISD::PSIGN";
11103 case X86ISD::BLENDV: return "X86ISD::BLENDV";
11104 case X86ISD::BLENDPW: return "X86ISD::BLENDPW";
11105 case X86ISD::BLENDPS: return "X86ISD::BLENDPS";
11106 case X86ISD::BLENDPD: return "X86ISD::BLENDPD";
11107 case X86ISD::HADD: return "X86ISD::HADD";
11108 case X86ISD::HSUB: return "X86ISD::HSUB";
11109 case X86ISD::FHADD: return "X86ISD::FHADD";
11110 case X86ISD::FHSUB: return "X86ISD::FHSUB";
11111 case X86ISD::FMAX: return "X86ISD::FMAX";
11112 case X86ISD::FMIN: return "X86ISD::FMIN";
11113 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
11114 case X86ISD::FRCP: return "X86ISD::FRCP";
11115 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
11116 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
11117 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
11118 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
11119 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
11120 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
11121 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
11122 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
11123 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
11124 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
11125 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
11126 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
11127 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
11128 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
11129 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
11130 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
11131 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
11132 case X86ISD::VSHL: return "X86ISD::VSHL";
11133 case X86ISD::VSRL: return "X86ISD::VSRL";
11134 case X86ISD::VSRA: return "X86ISD::VSRA";
11135 case X86ISD::VSHLI: return "X86ISD::VSHLI";
11136 case X86ISD::VSRLI: return "X86ISD::VSRLI";
11137 case X86ISD::VSRAI: return "X86ISD::VSRAI";
11138 case X86ISD::CMPP: return "X86ISD::CMPP";
11139 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
11140 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
11141 case X86ISD::ADD: return "X86ISD::ADD";
11142 case X86ISD::SUB: return "X86ISD::SUB";
11143 case X86ISD::ADC: return "X86ISD::ADC";
11144 case X86ISD::SBB: return "X86ISD::SBB";
11145 case X86ISD::SMUL: return "X86ISD::SMUL";
11146 case X86ISD::UMUL: return "X86ISD::UMUL";
11147 case X86ISD::INC: return "X86ISD::INC";
11148 case X86ISD::DEC: return "X86ISD::DEC";
11149 case X86ISD::OR: return "X86ISD::OR";
11150 case X86ISD::XOR: return "X86ISD::XOR";
11151 case X86ISD::AND: return "X86ISD::AND";
11152 case X86ISD::ANDN: return "X86ISD::ANDN";
11153 case X86ISD::BLSI: return "X86ISD::BLSI";
11154 case X86ISD::BLSMSK: return "X86ISD::BLSMSK";
11155 case X86ISD::BLSR: return "X86ISD::BLSR";
11156 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
11157 case X86ISD::PTEST: return "X86ISD::PTEST";
11158 case X86ISD::TESTP: return "X86ISD::TESTP";
11159 case X86ISD::PALIGN: return "X86ISD::PALIGN";
11160 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
11161 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
11162 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
11163 case X86ISD::SHUFP: return "X86ISD::SHUFP";
11164 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
11165 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
11166 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
11167 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
11168 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
11169 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
11170 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
11171 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
11172 case X86ISD::MOVSD: return "X86ISD::MOVSD";
11173 case X86ISD::MOVSS: return "X86ISD::MOVSS";
11174 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
11175 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
11176 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
11177 case X86ISD::VPERMILP: return "X86ISD::VPERMILP";
11178 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
11179 case X86ISD::VPERMV: return "X86ISD::VPERMV";
11180 case X86ISD::VPERMI: return "X86ISD::VPERMI";
11181 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
11182 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
11183 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
11184 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
11185 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
11186 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
11187 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
11191 // isLegalAddressingMode - Return true if the addressing mode represented
11192 // by AM is legal for this target, for a load/store of the specified type.
11193 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
11195 // X86 supports extremely general addressing modes.
11196 CodeModel::Model M = getTargetMachine().getCodeModel();
11197 Reloc::Model R = getTargetMachine().getRelocationModel();
11199 // X86 allows a sign-extended 32-bit immediate field as a displacement.
11200 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
11205 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
11207 // If a reference to this global requires an extra load, we can't fold it.
11208 if (isGlobalStubReference(GVFlags))
11211 // If BaseGV requires a register for the PIC base, we cannot also have a
11212 // BaseReg specified.
11213 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
11216 // If lower 4G is not available, then we must use rip-relative addressing.
11217 if ((M != CodeModel::Small || R != Reloc::Static) &&
11218 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
11222 switch (AM.Scale) {
11228 // These scales always work.
11233 // These scales are formed with basereg+scalereg. Only accept if there is
11238 default: // Other stuff never works.
11246 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
11247 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
11249 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
11250 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
11251 if (NumBits1 <= NumBits2)
11256 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
11257 if (!VT1.isInteger() || !VT2.isInteger())
11259 unsigned NumBits1 = VT1.getSizeInBits();
11260 unsigned NumBits2 = VT2.getSizeInBits();
11261 if (NumBits1 <= NumBits2)
11266 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
11267 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
11268 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
11271 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
11272 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
11273 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
11276 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
11277 // i16 instructions are longer (0x66 prefix) and potentially slower.
11278 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
11281 /// isShuffleMaskLegal - Targets can use this to indicate that they only
11282 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
11283 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
11284 /// are assumed to be legal.
11286 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
11288 // Very little shuffling can be done for 64-bit vectors right now.
11289 if (VT.getSizeInBits() == 64)
11292 // FIXME: pshufb, blends, shifts.
11293 return (VT.getVectorNumElements() == 2 ||
11294 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
11295 isMOVLMask(M, VT) ||
11296 isSHUFPMask(M, VT, Subtarget->hasAVX()) ||
11297 isPSHUFDMask(M, VT) ||
11298 isPSHUFHWMask(M, VT) ||
11299 isPSHUFLWMask(M, VT) ||
11300 isPALIGNRMask(M, VT, Subtarget) ||
11301 isUNPCKLMask(M, VT, Subtarget->hasAVX2()) ||
11302 isUNPCKHMask(M, VT, Subtarget->hasAVX2()) ||
11303 isUNPCKL_v_undef_Mask(M, VT, Subtarget->hasAVX2()) ||
11304 isUNPCKH_v_undef_Mask(M, VT, Subtarget->hasAVX2()));
11308 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
11310 unsigned NumElts = VT.getVectorNumElements();
11311 // FIXME: This collection of masks seems suspect.
11314 if (NumElts == 4 && VT.getSizeInBits() == 128) {
11315 return (isMOVLMask(Mask, VT) ||
11316 isCommutedMOVLMask(Mask, VT, true) ||
11317 isSHUFPMask(Mask, VT, Subtarget->hasAVX()) ||
11318 isSHUFPMask(Mask, VT, Subtarget->hasAVX(), /* Commuted */ true));
11323 //===----------------------------------------------------------------------===//
11324 // X86 Scheduler Hooks
11325 //===----------------------------------------------------------------------===//
11327 // private utility function
11328 MachineBasicBlock *
11329 X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
11330 MachineBasicBlock *MBB,
11337 const TargetRegisterClass *RC,
11338 bool Invert) const {
11339 // For the atomic bitwise operator, we generate
11342 // ld t1 = [bitinstr.addr]
11343 // op t2 = t1, [bitinstr.val]
11344 // not t3 = t2 (if Invert)
11346 // lcs dest = [bitinstr.addr], t3 [EAX is implicit]
11348 // fallthrough -->nextMBB
11349 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11350 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11351 MachineFunction::iterator MBBIter = MBB;
11354 /// First build the CFG
11355 MachineFunction *F = MBB->getParent();
11356 MachineBasicBlock *thisMBB = MBB;
11357 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11358 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11359 F->insert(MBBIter, newMBB);
11360 F->insert(MBBIter, nextMBB);
11362 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11363 nextMBB->splice(nextMBB->begin(), thisMBB,
11364 llvm::next(MachineBasicBlock::iterator(bInstr)),
11366 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11368 // Update thisMBB to fall through to newMBB
11369 thisMBB->addSuccessor(newMBB);
11371 // newMBB jumps to itself and fall through to nextMBB
11372 newMBB->addSuccessor(nextMBB);
11373 newMBB->addSuccessor(newMBB);
11375 // Insert instructions into newMBB based on incoming instruction
11376 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
11377 "unexpected number of operands");
11378 DebugLoc dl = bInstr->getDebugLoc();
11379 MachineOperand& destOper = bInstr->getOperand(0);
11380 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11381 int numArgs = bInstr->getNumOperands() - 1;
11382 for (int i=0; i < numArgs; ++i)
11383 argOpers[i] = &bInstr->getOperand(i+1);
11385 // x86 address has 4 operands: base, index, scale, and displacement
11386 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11387 int valArgIndx = lastAddrIndx + 1;
11389 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
11390 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1);
11391 for (int i=0; i <= lastAddrIndx; ++i)
11392 (*MIB).addOperand(*argOpers[i]);
11394 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
11395 assert((argOpers[valArgIndx]->isReg() ||
11396 argOpers[valArgIndx]->isImm()) &&
11397 "invalid operand");
11398 if (argOpers[valArgIndx]->isReg())
11399 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2);
11401 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2);
11403 (*MIB).addOperand(*argOpers[valArgIndx]);
11405 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
11407 MIB = BuildMI(newMBB, dl, TII->get(notOpc), t3).addReg(t2);
11412 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), EAXreg);
11415 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc));
11416 for (int i=0; i <= lastAddrIndx; ++i)
11417 (*MIB).addOperand(*argOpers[i]);
11419 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11420 (*MIB).setMemRefs(bInstr->memoperands_begin(),
11421 bInstr->memoperands_end());
11423 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
11424 MIB.addReg(EAXreg);
11427 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11429 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
11433 // private utility function: 64 bit atomics on 32 bit host.
11434 MachineBasicBlock *
11435 X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
11436 MachineBasicBlock *MBB,
11441 bool Invert) const {
11442 // For the atomic bitwise operator, we generate
11443 // thisMBB (instructions are in pairs, except cmpxchg8b)
11444 // ld t1,t2 = [bitinstr.addr]
11446 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4)
11447 // op t5, t6 <- out1, out2, [bitinstr.val]
11448 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val])
11449 // neg t7, t8 < t5, t6 (if Invert)
11450 // mov ECX, EBX <- t5, t6
11451 // mov EAX, EDX <- t1, t2
11452 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit]
11453 // mov t3, t4 <- EAX, EDX
11455 // result in out1, out2
11456 // fallthrough -->nextMBB
11458 const TargetRegisterClass *RC = &X86::GR32RegClass;
11459 const unsigned LoadOpc = X86::MOV32rm;
11460 const unsigned NotOpc = X86::NOT32r;
11461 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11462 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11463 MachineFunction::iterator MBBIter = MBB;
11466 /// First build the CFG
11467 MachineFunction *F = MBB->getParent();
11468 MachineBasicBlock *thisMBB = MBB;
11469 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11470 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11471 F->insert(MBBIter, newMBB);
11472 F->insert(MBBIter, nextMBB);
11474 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11475 nextMBB->splice(nextMBB->begin(), thisMBB,
11476 llvm::next(MachineBasicBlock::iterator(bInstr)),
11478 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11480 // Update thisMBB to fall through to newMBB
11481 thisMBB->addSuccessor(newMBB);
11483 // newMBB jumps to itself and fall through to nextMBB
11484 newMBB->addSuccessor(nextMBB);
11485 newMBB->addSuccessor(newMBB);
11487 DebugLoc dl = bInstr->getDebugLoc();
11488 // Insert instructions into newMBB based on incoming instruction
11489 // There are 8 "real" operands plus 9 implicit def/uses, ignored here.
11490 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 14 &&
11491 "unexpected number of operands");
11492 MachineOperand& dest1Oper = bInstr->getOperand(0);
11493 MachineOperand& dest2Oper = bInstr->getOperand(1);
11494 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11495 for (int i=0; i < 2 + X86::AddrNumOperands; ++i) {
11496 argOpers[i] = &bInstr->getOperand(i+2);
11498 // We use some of the operands multiple times, so conservatively just
11499 // clear any kill flags that might be present.
11500 if (argOpers[i]->isReg() && argOpers[i]->isUse())
11501 argOpers[i]->setIsKill(false);
11504 // x86 address has 5 operands: base, index, scale, displacement, and segment.
11505 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11507 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
11508 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1);
11509 for (int i=0; i <= lastAddrIndx; ++i)
11510 (*MIB).addOperand(*argOpers[i]);
11511 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
11512 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2);
11513 // add 4 to displacement.
11514 for (int i=0; i <= lastAddrIndx-2; ++i)
11515 (*MIB).addOperand(*argOpers[i]);
11516 MachineOperand newOp3 = *(argOpers[3]);
11517 if (newOp3.isImm())
11518 newOp3.setImm(newOp3.getImm()+4);
11520 newOp3.setOffset(newOp3.getOffset()+4);
11521 (*MIB).addOperand(newOp3);
11522 (*MIB).addOperand(*argOpers[lastAddrIndx]);
11524 // t3/4 are defined later, at the bottom of the loop
11525 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
11526 unsigned t4 = F->getRegInfo().createVirtualRegister(RC);
11527 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg())
11528 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB);
11529 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg())
11530 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB);
11532 // The subsequent operations should be using the destination registers of
11533 // the PHI instructions.
11534 t1 = dest1Oper.getReg();
11535 t2 = dest2Oper.getReg();
11537 int valArgIndx = lastAddrIndx + 1;
11538 assert((argOpers[valArgIndx]->isReg() ||
11539 argOpers[valArgIndx]->isImm()) &&
11540 "invalid operand");
11541 unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
11542 unsigned t6 = F->getRegInfo().createVirtualRegister(RC);
11543 if (argOpers[valArgIndx]->isReg())
11544 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5);
11546 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5);
11547 if (regOpcL != X86::MOV32rr)
11549 (*MIB).addOperand(*argOpers[valArgIndx]);
11550 assert(argOpers[valArgIndx + 1]->isReg() ==
11551 argOpers[valArgIndx]->isReg());
11552 assert(argOpers[valArgIndx + 1]->isImm() ==
11553 argOpers[valArgIndx]->isImm());
11554 if (argOpers[valArgIndx + 1]->isReg())
11555 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6);
11557 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6);
11558 if (regOpcH != X86::MOV32rr)
11560 (*MIB).addOperand(*argOpers[valArgIndx + 1]);
11564 t7 = F->getRegInfo().createVirtualRegister(RC);
11565 t8 = F->getRegInfo().createVirtualRegister(RC);
11566 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t7).addReg(t5);
11567 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t8).addReg(t6);
11573 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
11575 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EDX);
11578 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EBX);
11580 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::ECX);
11583 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B));
11584 for (int i=0; i <= lastAddrIndx; ++i)
11585 (*MIB).addOperand(*argOpers[i]);
11587 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11588 (*MIB).setMemRefs(bInstr->memoperands_begin(),
11589 bInstr->memoperands_end());
11591 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t3);
11592 MIB.addReg(X86::EAX);
11593 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t4);
11594 MIB.addReg(X86::EDX);
11597 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11599 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
11603 // private utility function
11604 MachineBasicBlock *
11605 X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
11606 MachineBasicBlock *MBB,
11607 unsigned cmovOpc) const {
11608 // For the atomic min/max operator, we generate
11611 // ld t1 = [min/max.addr]
11612 // mov t2 = [min/max.val]
11614 // cmov[cond] t2 = t1
11616 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
11618 // fallthrough -->nextMBB
11620 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11621 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11622 MachineFunction::iterator MBBIter = MBB;
11625 /// First build the CFG
11626 MachineFunction *F = MBB->getParent();
11627 MachineBasicBlock *thisMBB = MBB;
11628 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11629 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11630 F->insert(MBBIter, newMBB);
11631 F->insert(MBBIter, nextMBB);
11633 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11634 nextMBB->splice(nextMBB->begin(), thisMBB,
11635 llvm::next(MachineBasicBlock::iterator(mInstr)),
11637 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11639 // Update thisMBB to fall through to newMBB
11640 thisMBB->addSuccessor(newMBB);
11642 // newMBB jumps to newMBB and fall through to nextMBB
11643 newMBB->addSuccessor(nextMBB);
11644 newMBB->addSuccessor(newMBB);
11646 DebugLoc dl = mInstr->getDebugLoc();
11647 // Insert instructions into newMBB based on incoming instruction
11648 assert(mInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
11649 "unexpected number of operands");
11650 MachineOperand& destOper = mInstr->getOperand(0);
11651 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11652 int numArgs = mInstr->getNumOperands() - 1;
11653 for (int i=0; i < numArgs; ++i)
11654 argOpers[i] = &mInstr->getOperand(i+1);
11656 // x86 address has 4 operands: base, index, scale, and displacement
11657 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11658 int valArgIndx = lastAddrIndx + 1;
11660 unsigned t1 = F->getRegInfo().createVirtualRegister(&X86::GR32RegClass);
11661 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1);
11662 for (int i=0; i <= lastAddrIndx; ++i)
11663 (*MIB).addOperand(*argOpers[i]);
11665 // We only support register and immediate values
11666 assert((argOpers[valArgIndx]->isReg() ||
11667 argOpers[valArgIndx]->isImm()) &&
11668 "invalid operand");
11670 unsigned t2 = F->getRegInfo().createVirtualRegister(&X86::GR32RegClass);
11671 if (argOpers[valArgIndx]->isReg())
11672 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t2);
11674 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
11675 (*MIB).addOperand(*argOpers[valArgIndx]);
11677 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
11680 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr));
11685 unsigned t3 = F->getRegInfo().createVirtualRegister(&X86::GR32RegClass);
11686 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3);
11690 // Cmp and exchange if none has modified the memory location
11691 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32));
11692 for (int i=0; i <= lastAddrIndx; ++i)
11693 (*MIB).addOperand(*argOpers[i]);
11695 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11696 (*MIB).setMemRefs(mInstr->memoperands_begin(),
11697 mInstr->memoperands_end());
11699 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
11700 MIB.addReg(X86::EAX);
11703 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11705 mInstr->eraseFromParent(); // The pseudo instruction is gone now.
11709 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
11710 // or XMM0_V32I8 in AVX all of this code can be replaced with that
11711 // in the .td file.
11712 MachineBasicBlock *
11713 X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB,
11714 unsigned numArgs, bool memArg) const {
11715 assert(Subtarget->hasSSE42() &&
11716 "Target must have SSE4.2 or AVX features enabled");
11718 DebugLoc dl = MI->getDebugLoc();
11719 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11721 if (!Subtarget->hasAVX()) {
11723 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm;
11725 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr;
11728 Opc = numArgs == 3 ? X86::VPCMPISTRM128rm : X86::VPCMPESTRM128rm;
11730 Opc = numArgs == 3 ? X86::VPCMPISTRM128rr : X86::VPCMPESTRM128rr;
11733 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
11734 for (unsigned i = 0; i < numArgs; ++i) {
11735 MachineOperand &Op = MI->getOperand(i+1);
11736 if (!(Op.isReg() && Op.isImplicit()))
11737 MIB.addOperand(Op);
11739 BuildMI(*BB, MI, dl,
11740 TII->get(Subtarget->hasAVX() ? X86::VMOVAPSrr : X86::MOVAPSrr),
11741 MI->getOperand(0).getReg())
11742 .addReg(X86::XMM0);
11744 MI->eraseFromParent();
11748 MachineBasicBlock *
11749 X86TargetLowering::EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB) const {
11750 DebugLoc dl = MI->getDebugLoc();
11751 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11753 // Address into RAX/EAX, other two args into ECX, EDX.
11754 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
11755 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
11756 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
11757 for (int i = 0; i < X86::AddrNumOperands; ++i)
11758 MIB.addOperand(MI->getOperand(i));
11760 unsigned ValOps = X86::AddrNumOperands;
11761 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
11762 .addReg(MI->getOperand(ValOps).getReg());
11763 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
11764 .addReg(MI->getOperand(ValOps+1).getReg());
11766 // The instruction doesn't actually take any operands though.
11767 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
11769 MI->eraseFromParent(); // The pseudo is gone now.
11773 MachineBasicBlock *
11774 X86TargetLowering::EmitMwait(MachineInstr *MI, MachineBasicBlock *BB) const {
11775 DebugLoc dl = MI->getDebugLoc();
11776 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11778 // First arg in ECX, the second in EAX.
11779 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
11780 .addReg(MI->getOperand(0).getReg());
11781 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EAX)
11782 .addReg(MI->getOperand(1).getReg());
11784 // The instruction doesn't actually take any operands though.
11785 BuildMI(*BB, MI, dl, TII->get(X86::MWAITrr));
11787 MI->eraseFromParent(); // The pseudo is gone now.
11791 MachineBasicBlock *
11792 X86TargetLowering::EmitVAARG64WithCustomInserter(
11794 MachineBasicBlock *MBB) const {
11795 // Emit va_arg instruction on X86-64.
11797 // Operands to this pseudo-instruction:
11798 // 0 ) Output : destination address (reg)
11799 // 1-5) Input : va_list address (addr, i64mem)
11800 // 6 ) ArgSize : Size (in bytes) of vararg type
11801 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
11802 // 8 ) Align : Alignment of type
11803 // 9 ) EFLAGS (implicit-def)
11805 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
11806 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
11808 unsigned DestReg = MI->getOperand(0).getReg();
11809 MachineOperand &Base = MI->getOperand(1);
11810 MachineOperand &Scale = MI->getOperand(2);
11811 MachineOperand &Index = MI->getOperand(3);
11812 MachineOperand &Disp = MI->getOperand(4);
11813 MachineOperand &Segment = MI->getOperand(5);
11814 unsigned ArgSize = MI->getOperand(6).getImm();
11815 unsigned ArgMode = MI->getOperand(7).getImm();
11816 unsigned Align = MI->getOperand(8).getImm();
11818 // Memory Reference
11819 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
11820 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
11821 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
11823 // Machine Information
11824 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11825 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
11826 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
11827 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
11828 DebugLoc DL = MI->getDebugLoc();
11830 // struct va_list {
11833 // i64 overflow_area (address)
11834 // i64 reg_save_area (address)
11836 // sizeof(va_list) = 24
11837 // alignment(va_list) = 8
11839 unsigned TotalNumIntRegs = 6;
11840 unsigned TotalNumXMMRegs = 8;
11841 bool UseGPOffset = (ArgMode == 1);
11842 bool UseFPOffset = (ArgMode == 2);
11843 unsigned MaxOffset = TotalNumIntRegs * 8 +
11844 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
11846 /* Align ArgSize to a multiple of 8 */
11847 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
11848 bool NeedsAlign = (Align > 8);
11850 MachineBasicBlock *thisMBB = MBB;
11851 MachineBasicBlock *overflowMBB;
11852 MachineBasicBlock *offsetMBB;
11853 MachineBasicBlock *endMBB;
11855 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
11856 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
11857 unsigned OffsetReg = 0;
11859 if (!UseGPOffset && !UseFPOffset) {
11860 // If we only pull from the overflow region, we don't create a branch.
11861 // We don't need to alter control flow.
11862 OffsetDestReg = 0; // unused
11863 OverflowDestReg = DestReg;
11866 overflowMBB = thisMBB;
11869 // First emit code to check if gp_offset (or fp_offset) is below the bound.
11870 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
11871 // If not, pull from overflow_area. (branch to overflowMBB)
11876 // offsetMBB overflowMBB
11881 // Registers for the PHI in endMBB
11882 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
11883 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
11885 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11886 MachineFunction *MF = MBB->getParent();
11887 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11888 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11889 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11891 MachineFunction::iterator MBBIter = MBB;
11894 // Insert the new basic blocks
11895 MF->insert(MBBIter, offsetMBB);
11896 MF->insert(MBBIter, overflowMBB);
11897 MF->insert(MBBIter, endMBB);
11899 // Transfer the remainder of MBB and its successor edges to endMBB.
11900 endMBB->splice(endMBB->begin(), thisMBB,
11901 llvm::next(MachineBasicBlock::iterator(MI)),
11903 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11905 // Make offsetMBB and overflowMBB successors of thisMBB
11906 thisMBB->addSuccessor(offsetMBB);
11907 thisMBB->addSuccessor(overflowMBB);
11909 // endMBB is a successor of both offsetMBB and overflowMBB
11910 offsetMBB->addSuccessor(endMBB);
11911 overflowMBB->addSuccessor(endMBB);
11913 // Load the offset value into a register
11914 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
11915 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
11919 .addDisp(Disp, UseFPOffset ? 4 : 0)
11920 .addOperand(Segment)
11921 .setMemRefs(MMOBegin, MMOEnd);
11923 // Check if there is enough room left to pull this argument.
11924 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
11926 .addImm(MaxOffset + 8 - ArgSizeA8);
11928 // Branch to "overflowMBB" if offset >= max
11929 // Fall through to "offsetMBB" otherwise
11930 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
11931 .addMBB(overflowMBB);
11934 // In offsetMBB, emit code to use the reg_save_area.
11936 assert(OffsetReg != 0);
11938 // Read the reg_save_area address.
11939 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
11940 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
11945 .addOperand(Segment)
11946 .setMemRefs(MMOBegin, MMOEnd);
11948 // Zero-extend the offset
11949 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
11950 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
11953 .addImm(X86::sub_32bit);
11955 // Add the offset to the reg_save_area to get the final address.
11956 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
11957 .addReg(OffsetReg64)
11958 .addReg(RegSaveReg);
11960 // Compute the offset for the next argument
11961 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
11962 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
11964 .addImm(UseFPOffset ? 16 : 8);
11966 // Store it back into the va_list.
11967 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
11971 .addDisp(Disp, UseFPOffset ? 4 : 0)
11972 .addOperand(Segment)
11973 .addReg(NextOffsetReg)
11974 .setMemRefs(MMOBegin, MMOEnd);
11977 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
11982 // Emit code to use overflow area
11985 // Load the overflow_area address into a register.
11986 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
11987 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
11992 .addOperand(Segment)
11993 .setMemRefs(MMOBegin, MMOEnd);
11995 // If we need to align it, do so. Otherwise, just copy the address
11996 // to OverflowDestReg.
11998 // Align the overflow address
11999 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
12000 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
12002 // aligned_addr = (addr + (align-1)) & ~(align-1)
12003 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
12004 .addReg(OverflowAddrReg)
12007 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
12009 .addImm(~(uint64_t)(Align-1));
12011 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
12012 .addReg(OverflowAddrReg);
12015 // Compute the next overflow address after this argument.
12016 // (the overflow address should be kept 8-byte aligned)
12017 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
12018 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
12019 .addReg(OverflowDestReg)
12020 .addImm(ArgSizeA8);
12022 // Store the new overflow address.
12023 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
12028 .addOperand(Segment)
12029 .addReg(NextAddrReg)
12030 .setMemRefs(MMOBegin, MMOEnd);
12032 // If we branched, emit the PHI to the front of endMBB.
12034 BuildMI(*endMBB, endMBB->begin(), DL,
12035 TII->get(X86::PHI), DestReg)
12036 .addReg(OffsetDestReg).addMBB(offsetMBB)
12037 .addReg(OverflowDestReg).addMBB(overflowMBB);
12040 // Erase the pseudo instruction
12041 MI->eraseFromParent();
12046 MachineBasicBlock *
12047 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
12049 MachineBasicBlock *MBB) const {
12050 // Emit code to save XMM registers to the stack. The ABI says that the
12051 // number of registers to save is given in %al, so it's theoretically
12052 // possible to do an indirect jump trick to avoid saving all of them,
12053 // however this code takes a simpler approach and just executes all
12054 // of the stores if %al is non-zero. It's less code, and it's probably
12055 // easier on the hardware branch predictor, and stores aren't all that
12056 // expensive anyway.
12058 // Create the new basic blocks. One block contains all the XMM stores,
12059 // and one block is the final destination regardless of whether any
12060 // stores were performed.
12061 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
12062 MachineFunction *F = MBB->getParent();
12063 MachineFunction::iterator MBBIter = MBB;
12065 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
12066 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
12067 F->insert(MBBIter, XMMSaveMBB);
12068 F->insert(MBBIter, EndMBB);
12070 // Transfer the remainder of MBB and its successor edges to EndMBB.
12071 EndMBB->splice(EndMBB->begin(), MBB,
12072 llvm::next(MachineBasicBlock::iterator(MI)),
12074 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
12076 // The original block will now fall through to the XMM save block.
12077 MBB->addSuccessor(XMMSaveMBB);
12078 // The XMMSaveMBB will fall through to the end block.
12079 XMMSaveMBB->addSuccessor(EndMBB);
12081 // Now add the instructions.
12082 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12083 DebugLoc DL = MI->getDebugLoc();
12085 unsigned CountReg = MI->getOperand(0).getReg();
12086 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
12087 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
12089 if (!Subtarget->isTargetWin64()) {
12090 // If %al is 0, branch around the XMM save block.
12091 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
12092 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
12093 MBB->addSuccessor(EndMBB);
12096 unsigned MOVOpc = Subtarget->hasAVX() ? X86::VMOVAPSmr : X86::MOVAPSmr;
12097 // In the XMM save block, save all the XMM argument registers.
12098 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
12099 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
12100 MachineMemOperand *MMO =
12101 F->getMachineMemOperand(
12102 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
12103 MachineMemOperand::MOStore,
12104 /*Size=*/16, /*Align=*/16);
12105 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
12106 .addFrameIndex(RegSaveFrameIndex)
12107 .addImm(/*Scale=*/1)
12108 .addReg(/*IndexReg=*/0)
12109 .addImm(/*Disp=*/Offset)
12110 .addReg(/*Segment=*/0)
12111 .addReg(MI->getOperand(i).getReg())
12112 .addMemOperand(MMO);
12115 MI->eraseFromParent(); // The pseudo instruction is gone now.
12120 // The EFLAGS operand of SelectItr might be missing a kill marker
12121 // because there were multiple uses of EFLAGS, and ISel didn't know
12122 // which to mark. Figure out whether SelectItr should have had a
12123 // kill marker, and set it if it should. Returns the correct kill
12125 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
12126 MachineBasicBlock* BB,
12127 const TargetRegisterInfo* TRI) {
12128 // Scan forward through BB for a use/def of EFLAGS.
12129 MachineBasicBlock::iterator miI(llvm::next(SelectItr));
12130 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
12131 const MachineInstr& mi = *miI;
12132 if (mi.readsRegister(X86::EFLAGS))
12134 if (mi.definesRegister(X86::EFLAGS))
12135 break; // Should have kill-flag - update below.
12138 // If we hit the end of the block, check whether EFLAGS is live into a
12140 if (miI == BB->end()) {
12141 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
12142 sEnd = BB->succ_end();
12143 sItr != sEnd; ++sItr) {
12144 MachineBasicBlock* succ = *sItr;
12145 if (succ->isLiveIn(X86::EFLAGS))
12150 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
12151 // out. SelectMI should have a kill flag on EFLAGS.
12152 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
12156 MachineBasicBlock *
12157 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
12158 MachineBasicBlock *BB) const {
12159 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12160 DebugLoc DL = MI->getDebugLoc();
12162 // To "insert" a SELECT_CC instruction, we actually have to insert the
12163 // diamond control-flow pattern. The incoming instruction knows the
12164 // destination vreg to set, the condition code register to branch on, the
12165 // true/false values to select between, and a branch opcode to use.
12166 const BasicBlock *LLVM_BB = BB->getBasicBlock();
12167 MachineFunction::iterator It = BB;
12173 // cmpTY ccX, r1, r2
12175 // fallthrough --> copy0MBB
12176 MachineBasicBlock *thisMBB = BB;
12177 MachineFunction *F = BB->getParent();
12178 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
12179 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
12180 F->insert(It, copy0MBB);
12181 F->insert(It, sinkMBB);
12183 // If the EFLAGS register isn't dead in the terminator, then claim that it's
12184 // live into the sink and copy blocks.
12185 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
12186 if (!MI->killsRegister(X86::EFLAGS) &&
12187 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
12188 copy0MBB->addLiveIn(X86::EFLAGS);
12189 sinkMBB->addLiveIn(X86::EFLAGS);
12192 // Transfer the remainder of BB and its successor edges to sinkMBB.
12193 sinkMBB->splice(sinkMBB->begin(), BB,
12194 llvm::next(MachineBasicBlock::iterator(MI)),
12196 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
12198 // Add the true and fallthrough blocks as its successors.
12199 BB->addSuccessor(copy0MBB);
12200 BB->addSuccessor(sinkMBB);
12202 // Create the conditional branch instruction.
12204 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
12205 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
12208 // %FalseValue = ...
12209 // # fallthrough to sinkMBB
12210 copy0MBB->addSuccessor(sinkMBB);
12213 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
12215 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
12216 TII->get(X86::PHI), MI->getOperand(0).getReg())
12217 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
12218 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
12220 MI->eraseFromParent(); // The pseudo instruction is gone now.
12224 MachineBasicBlock *
12225 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB,
12226 bool Is64Bit) const {
12227 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12228 DebugLoc DL = MI->getDebugLoc();
12229 MachineFunction *MF = BB->getParent();
12230 const BasicBlock *LLVM_BB = BB->getBasicBlock();
12232 assert(getTargetMachine().Options.EnableSegmentedStacks);
12234 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
12235 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30;
12238 // ... [Till the alloca]
12239 // If stacklet is not large enough, jump to mallocMBB
12242 // Allocate by subtracting from RSP
12243 // Jump to continueMBB
12246 // Allocate by call to runtime
12250 // [rest of original BB]
12253 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12254 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12255 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12257 MachineRegisterInfo &MRI = MF->getRegInfo();
12258 const TargetRegisterClass *AddrRegClass =
12259 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32);
12261 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
12262 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
12263 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
12264 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
12265 sizeVReg = MI->getOperand(1).getReg(),
12266 physSPReg = Is64Bit ? X86::RSP : X86::ESP;
12268 MachineFunction::iterator MBBIter = BB;
12271 MF->insert(MBBIter, bumpMBB);
12272 MF->insert(MBBIter, mallocMBB);
12273 MF->insert(MBBIter, continueMBB);
12275 continueMBB->splice(continueMBB->begin(), BB, llvm::next
12276 (MachineBasicBlock::iterator(MI)), BB->end());
12277 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
12279 // Add code to the main basic block to check if the stack limit has been hit,
12280 // and if so, jump to mallocMBB otherwise to bumpMBB.
12281 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
12282 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
12283 .addReg(tmpSPVReg).addReg(sizeVReg);
12284 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr))
12285 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
12286 .addReg(SPLimitVReg);
12287 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
12289 // bumpMBB simply decreases the stack pointer, since we know the current
12290 // stacklet has enough space.
12291 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
12292 .addReg(SPLimitVReg);
12293 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
12294 .addReg(SPLimitVReg);
12295 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
12297 // Calls into a routine in libgcc to allocate more space from the heap.
12298 const uint32_t *RegMask =
12299 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
12301 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
12303 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
12304 .addExternalSymbol("__morestack_allocate_stack_space").addReg(X86::RDI)
12305 .addRegMask(RegMask)
12306 .addReg(X86::RAX, RegState::ImplicitDefine);
12308 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
12310 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
12311 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
12312 .addExternalSymbol("__morestack_allocate_stack_space")
12313 .addRegMask(RegMask)
12314 .addReg(X86::EAX, RegState::ImplicitDefine);
12318 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
12321 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
12322 .addReg(Is64Bit ? X86::RAX : X86::EAX);
12323 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
12325 // Set up the CFG correctly.
12326 BB->addSuccessor(bumpMBB);
12327 BB->addSuccessor(mallocMBB);
12328 mallocMBB->addSuccessor(continueMBB);
12329 bumpMBB->addSuccessor(continueMBB);
12331 // Take care of the PHI nodes.
12332 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
12333 MI->getOperand(0).getReg())
12334 .addReg(mallocPtrVReg).addMBB(mallocMBB)
12335 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
12337 // Delete the original pseudo instruction.
12338 MI->eraseFromParent();
12341 return continueMBB;
12344 MachineBasicBlock *
12345 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
12346 MachineBasicBlock *BB) const {
12347 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12348 DebugLoc DL = MI->getDebugLoc();
12350 assert(!Subtarget->isTargetEnvMacho());
12352 // The lowering is pretty easy: we're just emitting the call to _alloca. The
12353 // non-trivial part is impdef of ESP.
12355 if (Subtarget->isTargetWin64()) {
12356 if (Subtarget->isTargetCygMing()) {
12357 // ___chkstk(Mingw64):
12358 // Clobbers R10, R11, RAX and EFLAGS.
12360 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
12361 .addExternalSymbol("___chkstk")
12362 .addReg(X86::RAX, RegState::Implicit)
12363 .addReg(X86::RSP, RegState::Implicit)
12364 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
12365 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
12366 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
12368 // __chkstk(MSVCRT): does not update stack pointer.
12369 // Clobbers R10, R11 and EFLAGS.
12370 // FIXME: RAX(allocated size) might be reused and not killed.
12371 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
12372 .addExternalSymbol("__chkstk")
12373 .addReg(X86::RAX, RegState::Implicit)
12374 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
12375 // RAX has the offset to subtracted from RSP.
12376 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
12381 const char *StackProbeSymbol =
12382 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca";
12384 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
12385 .addExternalSymbol(StackProbeSymbol)
12386 .addReg(X86::EAX, RegState::Implicit)
12387 .addReg(X86::ESP, RegState::Implicit)
12388 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
12389 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
12390 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
12393 MI->eraseFromParent(); // The pseudo instruction is gone now.
12397 MachineBasicBlock *
12398 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
12399 MachineBasicBlock *BB) const {
12400 // This is pretty easy. We're taking the value that we received from
12401 // our load from the relocation, sticking it in either RDI (x86-64)
12402 // or EAX and doing an indirect call. The return value will then
12403 // be in the normal return register.
12404 const X86InstrInfo *TII
12405 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo());
12406 DebugLoc DL = MI->getDebugLoc();
12407 MachineFunction *F = BB->getParent();
12409 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
12410 assert(MI->getOperand(3).isGlobal() && "This should be a global");
12412 // Get a register mask for the lowered call.
12413 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
12414 // proper register mask.
12415 const uint32_t *RegMask =
12416 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
12417 if (Subtarget->is64Bit()) {
12418 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
12419 TII->get(X86::MOV64rm), X86::RDI)
12421 .addImm(0).addReg(0)
12422 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
12423 MI->getOperand(3).getTargetFlags())
12425 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
12426 addDirectMem(MIB, X86::RDI);
12427 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
12428 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
12429 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
12430 TII->get(X86::MOV32rm), X86::EAX)
12432 .addImm(0).addReg(0)
12433 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
12434 MI->getOperand(3).getTargetFlags())
12436 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
12437 addDirectMem(MIB, X86::EAX);
12438 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
12440 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
12441 TII->get(X86::MOV32rm), X86::EAX)
12442 .addReg(TII->getGlobalBaseReg(F))
12443 .addImm(0).addReg(0)
12444 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
12445 MI->getOperand(3).getTargetFlags())
12447 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
12448 addDirectMem(MIB, X86::EAX);
12449 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
12452 MI->eraseFromParent(); // The pseudo instruction is gone now.
12456 MachineBasicBlock *
12457 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
12458 MachineBasicBlock *BB) const {
12459 switch (MI->getOpcode()) {
12460 default: llvm_unreachable("Unexpected instr type to insert");
12461 case X86::TAILJMPd64:
12462 case X86::TAILJMPr64:
12463 case X86::TAILJMPm64:
12464 llvm_unreachable("TAILJMP64 would not be touched here.");
12465 case X86::TCRETURNdi64:
12466 case X86::TCRETURNri64:
12467 case X86::TCRETURNmi64:
12469 case X86::WIN_ALLOCA:
12470 return EmitLoweredWinAlloca(MI, BB);
12471 case X86::SEG_ALLOCA_32:
12472 return EmitLoweredSegAlloca(MI, BB, false);
12473 case X86::SEG_ALLOCA_64:
12474 return EmitLoweredSegAlloca(MI, BB, true);
12475 case X86::TLSCall_32:
12476 case X86::TLSCall_64:
12477 return EmitLoweredTLSCall(MI, BB);
12478 case X86::CMOV_GR8:
12479 case X86::CMOV_FR32:
12480 case X86::CMOV_FR64:
12481 case X86::CMOV_V4F32:
12482 case X86::CMOV_V2F64:
12483 case X86::CMOV_V2I64:
12484 case X86::CMOV_V8F32:
12485 case X86::CMOV_V4F64:
12486 case X86::CMOV_V4I64:
12487 case X86::CMOV_GR16:
12488 case X86::CMOV_GR32:
12489 case X86::CMOV_RFP32:
12490 case X86::CMOV_RFP64:
12491 case X86::CMOV_RFP80:
12492 return EmitLoweredSelect(MI, BB);
12494 case X86::FP32_TO_INT16_IN_MEM:
12495 case X86::FP32_TO_INT32_IN_MEM:
12496 case X86::FP32_TO_INT64_IN_MEM:
12497 case X86::FP64_TO_INT16_IN_MEM:
12498 case X86::FP64_TO_INT32_IN_MEM:
12499 case X86::FP64_TO_INT64_IN_MEM:
12500 case X86::FP80_TO_INT16_IN_MEM:
12501 case X86::FP80_TO_INT32_IN_MEM:
12502 case X86::FP80_TO_INT64_IN_MEM: {
12503 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12504 DebugLoc DL = MI->getDebugLoc();
12506 // Change the floating point control register to use "round towards zero"
12507 // mode when truncating to an integer value.
12508 MachineFunction *F = BB->getParent();
12509 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
12510 addFrameReference(BuildMI(*BB, MI, DL,
12511 TII->get(X86::FNSTCW16m)), CWFrameIdx);
12513 // Load the old value of the high byte of the control word...
12515 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
12516 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
12519 // Set the high part to be round to zero...
12520 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
12523 // Reload the modified control word now...
12524 addFrameReference(BuildMI(*BB, MI, DL,
12525 TII->get(X86::FLDCW16m)), CWFrameIdx);
12527 // Restore the memory image of control word to original value
12528 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
12531 // Get the X86 opcode to use.
12533 switch (MI->getOpcode()) {
12534 default: llvm_unreachable("illegal opcode!");
12535 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
12536 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
12537 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
12538 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
12539 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
12540 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
12541 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
12542 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
12543 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
12547 MachineOperand &Op = MI->getOperand(0);
12549 AM.BaseType = X86AddressMode::RegBase;
12550 AM.Base.Reg = Op.getReg();
12552 AM.BaseType = X86AddressMode::FrameIndexBase;
12553 AM.Base.FrameIndex = Op.getIndex();
12555 Op = MI->getOperand(1);
12557 AM.Scale = Op.getImm();
12558 Op = MI->getOperand(2);
12560 AM.IndexReg = Op.getImm();
12561 Op = MI->getOperand(3);
12562 if (Op.isGlobal()) {
12563 AM.GV = Op.getGlobal();
12565 AM.Disp = Op.getImm();
12567 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
12568 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
12570 // Reload the original control word now.
12571 addFrameReference(BuildMI(*BB, MI, DL,
12572 TII->get(X86::FLDCW16m)), CWFrameIdx);
12574 MI->eraseFromParent(); // The pseudo instruction is gone now.
12577 // String/text processing lowering.
12578 case X86::PCMPISTRM128REG:
12579 case X86::VPCMPISTRM128REG:
12580 return EmitPCMP(MI, BB, 3, false /* in-mem */);
12581 case X86::PCMPISTRM128MEM:
12582 case X86::VPCMPISTRM128MEM:
12583 return EmitPCMP(MI, BB, 3, true /* in-mem */);
12584 case X86::PCMPESTRM128REG:
12585 case X86::VPCMPESTRM128REG:
12586 return EmitPCMP(MI, BB, 5, false /* in mem */);
12587 case X86::PCMPESTRM128MEM:
12588 case X86::VPCMPESTRM128MEM:
12589 return EmitPCMP(MI, BB, 5, true /* in mem */);
12591 // Thread synchronization.
12593 return EmitMonitor(MI, BB);
12595 return EmitMwait(MI, BB);
12597 // Atomic Lowering.
12598 case X86::ATOMAND32:
12599 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
12600 X86::AND32ri, X86::MOV32rm,
12602 X86::NOT32r, X86::EAX,
12603 &X86::GR32RegClass);
12604 case X86::ATOMOR32:
12605 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
12606 X86::OR32ri, X86::MOV32rm,
12608 X86::NOT32r, X86::EAX,
12609 &X86::GR32RegClass);
12610 case X86::ATOMXOR32:
12611 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
12612 X86::XOR32ri, X86::MOV32rm,
12614 X86::NOT32r, X86::EAX,
12615 &X86::GR32RegClass);
12616 case X86::ATOMNAND32:
12617 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
12618 X86::AND32ri, X86::MOV32rm,
12620 X86::NOT32r, X86::EAX,
12621 &X86::GR32RegClass, true);
12622 case X86::ATOMMIN32:
12623 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
12624 case X86::ATOMMAX32:
12625 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
12626 case X86::ATOMUMIN32:
12627 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
12628 case X86::ATOMUMAX32:
12629 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
12631 case X86::ATOMAND16:
12632 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
12633 X86::AND16ri, X86::MOV16rm,
12635 X86::NOT16r, X86::AX,
12636 &X86::GR16RegClass);
12637 case X86::ATOMOR16:
12638 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
12639 X86::OR16ri, X86::MOV16rm,
12641 X86::NOT16r, X86::AX,
12642 &X86::GR16RegClass);
12643 case X86::ATOMXOR16:
12644 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr,
12645 X86::XOR16ri, X86::MOV16rm,
12647 X86::NOT16r, X86::AX,
12648 &X86::GR16RegClass);
12649 case X86::ATOMNAND16:
12650 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
12651 X86::AND16ri, X86::MOV16rm,
12653 X86::NOT16r, X86::AX,
12654 &X86::GR16RegClass, true);
12655 case X86::ATOMMIN16:
12656 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr);
12657 case X86::ATOMMAX16:
12658 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr);
12659 case X86::ATOMUMIN16:
12660 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr);
12661 case X86::ATOMUMAX16:
12662 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr);
12664 case X86::ATOMAND8:
12665 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
12666 X86::AND8ri, X86::MOV8rm,
12668 X86::NOT8r, X86::AL,
12669 &X86::GR8RegClass);
12671 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
12672 X86::OR8ri, X86::MOV8rm,
12674 X86::NOT8r, X86::AL,
12675 &X86::GR8RegClass);
12676 case X86::ATOMXOR8:
12677 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr,
12678 X86::XOR8ri, X86::MOV8rm,
12680 X86::NOT8r, X86::AL,
12681 &X86::GR8RegClass);
12682 case X86::ATOMNAND8:
12683 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
12684 X86::AND8ri, X86::MOV8rm,
12686 X86::NOT8r, X86::AL,
12687 &X86::GR8RegClass, true);
12688 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
12689 // This group is for 64-bit host.
12690 case X86::ATOMAND64:
12691 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
12692 X86::AND64ri32, X86::MOV64rm,
12694 X86::NOT64r, X86::RAX,
12695 &X86::GR64RegClass);
12696 case X86::ATOMOR64:
12697 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
12698 X86::OR64ri32, X86::MOV64rm,
12700 X86::NOT64r, X86::RAX,
12701 &X86::GR64RegClass);
12702 case X86::ATOMXOR64:
12703 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr,
12704 X86::XOR64ri32, X86::MOV64rm,
12706 X86::NOT64r, X86::RAX,
12707 &X86::GR64RegClass);
12708 case X86::ATOMNAND64:
12709 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
12710 X86::AND64ri32, X86::MOV64rm,
12712 X86::NOT64r, X86::RAX,
12713 &X86::GR64RegClass, true);
12714 case X86::ATOMMIN64:
12715 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr);
12716 case X86::ATOMMAX64:
12717 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr);
12718 case X86::ATOMUMIN64:
12719 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr);
12720 case X86::ATOMUMAX64:
12721 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr);
12723 // This group does 64-bit operations on a 32-bit host.
12724 case X86::ATOMAND6432:
12725 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12726 X86::AND32rr, X86::AND32rr,
12727 X86::AND32ri, X86::AND32ri,
12729 case X86::ATOMOR6432:
12730 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12731 X86::OR32rr, X86::OR32rr,
12732 X86::OR32ri, X86::OR32ri,
12734 case X86::ATOMXOR6432:
12735 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12736 X86::XOR32rr, X86::XOR32rr,
12737 X86::XOR32ri, X86::XOR32ri,
12739 case X86::ATOMNAND6432:
12740 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12741 X86::AND32rr, X86::AND32rr,
12742 X86::AND32ri, X86::AND32ri,
12744 case X86::ATOMADD6432:
12745 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12746 X86::ADD32rr, X86::ADC32rr,
12747 X86::ADD32ri, X86::ADC32ri,
12749 case X86::ATOMSUB6432:
12750 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12751 X86::SUB32rr, X86::SBB32rr,
12752 X86::SUB32ri, X86::SBB32ri,
12754 case X86::ATOMSWAP6432:
12755 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12756 X86::MOV32rr, X86::MOV32rr,
12757 X86::MOV32ri, X86::MOV32ri,
12759 case X86::VASTART_SAVE_XMM_REGS:
12760 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
12762 case X86::VAARG_64:
12763 return EmitVAARG64WithCustomInserter(MI, BB);
12767 //===----------------------------------------------------------------------===//
12768 // X86 Optimization Hooks
12769 //===----------------------------------------------------------------------===//
12771 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
12774 const SelectionDAG &DAG,
12775 unsigned Depth) const {
12776 unsigned BitWidth = KnownZero.getBitWidth();
12777 unsigned Opc = Op.getOpcode();
12778 assert((Opc >= ISD::BUILTIN_OP_END ||
12779 Opc == ISD::INTRINSIC_WO_CHAIN ||
12780 Opc == ISD::INTRINSIC_W_CHAIN ||
12781 Opc == ISD::INTRINSIC_VOID) &&
12782 "Should use MaskedValueIsZero if you don't know whether Op"
12783 " is a target node!");
12785 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
12799 // These nodes' second result is a boolean.
12800 if (Op.getResNo() == 0)
12803 case X86ISD::SETCC:
12804 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
12806 case ISD::INTRINSIC_WO_CHAIN: {
12807 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
12808 unsigned NumLoBits = 0;
12811 case Intrinsic::x86_sse_movmsk_ps:
12812 case Intrinsic::x86_avx_movmsk_ps_256:
12813 case Intrinsic::x86_sse2_movmsk_pd:
12814 case Intrinsic::x86_avx_movmsk_pd_256:
12815 case Intrinsic::x86_mmx_pmovmskb:
12816 case Intrinsic::x86_sse2_pmovmskb_128:
12817 case Intrinsic::x86_avx2_pmovmskb: {
12818 // High bits of movmskp{s|d}, pmovmskb are known zero.
12820 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
12821 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
12822 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
12823 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
12824 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
12825 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
12826 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
12827 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
12829 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
12838 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
12839 unsigned Depth) const {
12840 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
12841 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
12842 return Op.getValueType().getScalarType().getSizeInBits();
12848 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
12849 /// node is a GlobalAddress + offset.
12850 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
12851 const GlobalValue* &GA,
12852 int64_t &Offset) const {
12853 if (N->getOpcode() == X86ISD::Wrapper) {
12854 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
12855 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
12856 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
12860 return TargetLowering::isGAPlusOffset(N, GA, Offset);
12863 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
12864 /// same as extracting the high 128-bit part of 256-bit vector and then
12865 /// inserting the result into the low part of a new 256-bit vector
12866 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
12867 EVT VT = SVOp->getValueType(0);
12868 int NumElems = VT.getVectorNumElements();
12870 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
12871 for (int i = 0, j = NumElems/2; i < NumElems/2; ++i, ++j)
12872 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
12873 SVOp->getMaskElt(j) >= 0)
12879 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
12880 /// same as extracting the low 128-bit part of 256-bit vector and then
12881 /// inserting the result into the high part of a new 256-bit vector
12882 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
12883 EVT VT = SVOp->getValueType(0);
12884 int NumElems = VT.getVectorNumElements();
12886 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
12887 for (int i = NumElems/2, j = 0; i < NumElems; ++i, ++j)
12888 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
12889 SVOp->getMaskElt(j) >= 0)
12895 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
12896 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
12897 TargetLowering::DAGCombinerInfo &DCI,
12898 const X86Subtarget* Subtarget) {
12899 DebugLoc dl = N->getDebugLoc();
12900 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
12901 SDValue V1 = SVOp->getOperand(0);
12902 SDValue V2 = SVOp->getOperand(1);
12903 EVT VT = SVOp->getValueType(0);
12904 int NumElems = VT.getVectorNumElements();
12906 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
12907 V2.getOpcode() == ISD::CONCAT_VECTORS) {
12911 // V UNDEF BUILD_VECTOR UNDEF
12913 // CONCAT_VECTOR CONCAT_VECTOR
12916 // RESULT: V + zero extended
12918 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
12919 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
12920 V1.getOperand(1).getOpcode() != ISD::UNDEF)
12923 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
12926 // To match the shuffle mask, the first half of the mask should
12927 // be exactly the first vector, and all the rest a splat with the
12928 // first element of the second one.
12929 for (int i = 0; i < NumElems/2; ++i)
12930 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
12931 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
12934 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
12935 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
12936 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
12937 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
12939 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2,
12941 Ld->getPointerInfo(),
12942 Ld->getAlignment(),
12943 false/*isVolatile*/, true/*ReadMem*/,
12944 false/*WriteMem*/);
12945 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
12948 // Emit a zeroed vector and insert the desired subvector on its
12950 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
12951 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
12952 return DCI.CombineTo(N, InsV);
12955 //===--------------------------------------------------------------------===//
12956 // Combine some shuffles into subvector extracts and inserts:
12959 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
12960 if (isShuffleHigh128VectorInsertLow(SVOp)) {
12961 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
12962 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
12963 return DCI.CombineTo(N, InsV);
12966 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
12967 if (isShuffleLow128VectorInsertHigh(SVOp)) {
12968 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
12969 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
12970 return DCI.CombineTo(N, InsV);
12976 /// PerformShuffleCombine - Performs several different shuffle combines.
12977 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
12978 TargetLowering::DAGCombinerInfo &DCI,
12979 const X86Subtarget *Subtarget) {
12980 DebugLoc dl = N->getDebugLoc();
12981 EVT VT = N->getValueType(0);
12983 // Don't create instructions with illegal types after legalize types has run.
12984 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12985 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
12988 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
12989 if (Subtarget->hasAVX() && VT.getSizeInBits() == 256 &&
12990 N->getOpcode() == ISD::VECTOR_SHUFFLE)
12991 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
12993 // Only handle 128 wide vector from here on.
12994 if (VT.getSizeInBits() != 128)
12997 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
12998 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
12999 // consecutive, non-overlapping, and in the right order.
13000 SmallVector<SDValue, 16> Elts;
13001 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
13002 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
13004 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG);
13008 /// PerformTruncateCombine - Converts truncate operation to
13009 /// a sequence of vector shuffle operations.
13010 /// It is possible when we truncate 256-bit vector to 128-bit vector
13012 SDValue X86TargetLowering::PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
13013 DAGCombinerInfo &DCI) const {
13014 if (!DCI.isBeforeLegalizeOps())
13017 if (!Subtarget->hasAVX()) return SDValue();
13019 EVT VT = N->getValueType(0);
13020 SDValue Op = N->getOperand(0);
13021 EVT OpVT = Op.getValueType();
13022 DebugLoc dl = N->getDebugLoc();
13024 if ((VT == MVT::v4i32) && (OpVT == MVT::v4i64)) {
13026 if (Subtarget->hasAVX2()) {
13027 // AVX2: v4i64 -> v4i32
13030 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
13032 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v8i32, Op);
13033 Op = DAG.getVectorShuffle(MVT::v8i32, dl, Op, DAG.getUNDEF(MVT::v8i32),
13036 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, Op,
13037 DAG.getIntPtrConstant(0));
13040 // AVX: v4i64 -> v4i32
13041 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Op,
13042 DAG.getIntPtrConstant(0));
13044 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Op,
13045 DAG.getIntPtrConstant(2));
13047 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpLo);
13048 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpHi);
13051 static const int ShufMask1[] = {0, 2, 0, 0};
13053 OpLo = DAG.getVectorShuffle(VT, dl, OpLo, DAG.getUNDEF(VT), ShufMask1);
13054 OpHi = DAG.getVectorShuffle(VT, dl, OpHi, DAG.getUNDEF(VT), ShufMask1);
13057 static const int ShufMask2[] = {0, 1, 4, 5};
13059 return DAG.getVectorShuffle(VT, dl, OpLo, OpHi, ShufMask2);
13062 if ((VT == MVT::v8i16) && (OpVT == MVT::v8i32)) {
13064 if (Subtarget->hasAVX2()) {
13065 // AVX2: v8i32 -> v8i16
13067 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v32i8, Op);
13070 SmallVector<SDValue,32> pshufbMask;
13071 for (unsigned i = 0; i < 2; ++i) {
13072 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
13073 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
13074 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
13075 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
13076 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
13077 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
13078 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
13079 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
13080 for (unsigned j = 0; j < 8; ++j)
13081 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
13083 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v32i8,
13084 &pshufbMask[0], 32);
13085 Op = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v32i8, Op, BV);
13087 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4i64, Op);
13089 static const int ShufMask[] = {0, 2, -1, -1};
13090 Op = DAG.getVectorShuffle(MVT::v4i64, dl, Op, DAG.getUNDEF(MVT::v4i64),
13093 Op = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Op,
13094 DAG.getIntPtrConstant(0));
13096 return DAG.getNode(ISD::BITCAST, dl, VT, Op);
13099 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i32, Op,
13100 DAG.getIntPtrConstant(0));
13102 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i32, Op,
13103 DAG.getIntPtrConstant(4));
13105 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLo);
13106 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpHi);
13109 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
13110 -1, -1, -1, -1, -1, -1, -1, -1};
13112 OpLo = DAG.getVectorShuffle(MVT::v16i8, dl, OpLo, DAG.getUNDEF(MVT::v16i8),
13114 OpHi = DAG.getVectorShuffle(MVT::v16i8, dl, OpHi, DAG.getUNDEF(MVT::v16i8),
13117 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpLo);
13118 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpHi);
13121 static const int ShufMask2[] = {0, 1, 4, 5};
13123 SDValue res = DAG.getVectorShuffle(MVT::v4i32, dl, OpLo, OpHi, ShufMask2);
13124 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, res);
13130 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
13131 /// specific shuffle of a load can be folded into a single element load.
13132 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
13133 /// shuffles have been customed lowered so we need to handle those here.
13134 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
13135 TargetLowering::DAGCombinerInfo &DCI) {
13136 if (DCI.isBeforeLegalizeOps())
13139 SDValue InVec = N->getOperand(0);
13140 SDValue EltNo = N->getOperand(1);
13142 if (!isa<ConstantSDNode>(EltNo))
13145 EVT VT = InVec.getValueType();
13147 bool HasShuffleIntoBitcast = false;
13148 if (InVec.getOpcode() == ISD::BITCAST) {
13149 // Don't duplicate a load with other uses.
13150 if (!InVec.hasOneUse())
13152 EVT BCVT = InVec.getOperand(0).getValueType();
13153 if (BCVT.getVectorNumElements() != VT.getVectorNumElements())
13155 InVec = InVec.getOperand(0);
13156 HasShuffleIntoBitcast = true;
13159 if (!isTargetShuffle(InVec.getOpcode()))
13162 // Don't duplicate a load with other uses.
13163 if (!InVec.hasOneUse())
13166 SmallVector<int, 16> ShuffleMask;
13168 if (!getTargetShuffleMask(InVec.getNode(), VT, ShuffleMask, UnaryShuffle))
13171 // Select the input vector, guarding against out of range extract vector.
13172 unsigned NumElems = VT.getVectorNumElements();
13173 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
13174 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
13175 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
13176 : InVec.getOperand(1);
13178 // If inputs to shuffle are the same for both ops, then allow 2 uses
13179 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
13181 if (LdNode.getOpcode() == ISD::BITCAST) {
13182 // Don't duplicate a load with other uses.
13183 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
13186 AllowedUses = 1; // only allow 1 load use if we have a bitcast
13187 LdNode = LdNode.getOperand(0);
13190 if (!ISD::isNormalLoad(LdNode.getNode()))
13193 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
13195 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
13198 if (HasShuffleIntoBitcast) {
13199 // If there's a bitcast before the shuffle, check if the load type and
13200 // alignment is valid.
13201 unsigned Align = LN0->getAlignment();
13202 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13203 unsigned NewAlign = TLI.getTargetData()->
13204 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
13206 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
13210 // All checks match so transform back to vector_shuffle so that DAG combiner
13211 // can finish the job
13212 DebugLoc dl = N->getDebugLoc();
13214 // Create shuffle node taking into account the case that its a unary shuffle
13215 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1);
13216 Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl,
13217 InVec.getOperand(0), Shuffle,
13219 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
13220 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
13224 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
13225 /// generation and convert it from being a bunch of shuffles and extracts
13226 /// to a simple store and scalar loads to extract the elements.
13227 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
13228 TargetLowering::DAGCombinerInfo &DCI) {
13229 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
13230 if (NewOp.getNode())
13233 SDValue InputVector = N->getOperand(0);
13235 // Only operate on vectors of 4 elements, where the alternative shuffling
13236 // gets to be more expensive.
13237 if (InputVector.getValueType() != MVT::v4i32)
13240 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
13241 // single use which is a sign-extend or zero-extend, and all elements are
13243 SmallVector<SDNode *, 4> Uses;
13244 unsigned ExtractedElements = 0;
13245 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
13246 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
13247 if (UI.getUse().getResNo() != InputVector.getResNo())
13250 SDNode *Extract = *UI;
13251 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
13254 if (Extract->getValueType(0) != MVT::i32)
13256 if (!Extract->hasOneUse())
13258 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
13259 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
13261 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
13264 // Record which element was extracted.
13265 ExtractedElements |=
13266 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
13268 Uses.push_back(Extract);
13271 // If not all the elements were used, this may not be worthwhile.
13272 if (ExtractedElements != 15)
13275 // Ok, we've now decided to do the transformation.
13276 DebugLoc dl = InputVector.getDebugLoc();
13278 // Store the value to a temporary stack slot.
13279 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
13280 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
13281 MachinePointerInfo(), false, false, 0);
13283 // Replace each use (extract) with a load of the appropriate element.
13284 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
13285 UE = Uses.end(); UI != UE; ++UI) {
13286 SDNode *Extract = *UI;
13288 // cOMpute the element's address.
13289 SDValue Idx = Extract->getOperand(1);
13291 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
13292 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
13293 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13294 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
13296 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
13297 StackPtr, OffsetVal);
13299 // Load the scalar.
13300 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
13301 ScalarAddr, MachinePointerInfo(),
13302 false, false, false, 0);
13304 // Replace the exact with the load.
13305 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
13308 // The replacement was made in place; don't return anything.
13312 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
13314 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
13315 TargetLowering::DAGCombinerInfo &DCI,
13316 const X86Subtarget *Subtarget) {
13319 DebugLoc DL = N->getDebugLoc();
13320 SDValue Cond = N->getOperand(0);
13321 // Get the LHS/RHS of the select.
13322 SDValue LHS = N->getOperand(1);
13323 SDValue RHS = N->getOperand(2);
13324 EVT VT = LHS.getValueType();
13326 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
13327 // instructions match the semantics of the common C idiom x<y?x:y but not
13328 // x<=y?x:y, because of how they handle negative zero (which can be
13329 // ignored in unsafe-math mode).
13330 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
13331 VT != MVT::f80 && DAG.getTargetLoweringInfo().isTypeLegal(VT) &&
13332 (Subtarget->hasSSE2() ||
13333 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
13334 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
13336 unsigned Opcode = 0;
13337 // Check for x CC y ? x : y.
13338 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
13339 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
13343 // Converting this to a min would handle NaNs incorrectly, and swapping
13344 // the operands would cause it to handle comparisons between positive
13345 // and negative zero incorrectly.
13346 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
13347 if (!DAG.getTarget().Options.UnsafeFPMath &&
13348 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
13350 std::swap(LHS, RHS);
13352 Opcode = X86ISD::FMIN;
13355 // Converting this to a min would handle comparisons between positive
13356 // and negative zero incorrectly.
13357 if (!DAG.getTarget().Options.UnsafeFPMath &&
13358 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
13360 Opcode = X86ISD::FMIN;
13363 // Converting this to a min would handle both negative zeros and NaNs
13364 // incorrectly, but we can swap the operands to fix both.
13365 std::swap(LHS, RHS);
13369 Opcode = X86ISD::FMIN;
13373 // Converting this to a max would handle comparisons between positive
13374 // and negative zero incorrectly.
13375 if (!DAG.getTarget().Options.UnsafeFPMath &&
13376 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
13378 Opcode = X86ISD::FMAX;
13381 // Converting this to a max would handle NaNs incorrectly, and swapping
13382 // the operands would cause it to handle comparisons between positive
13383 // and negative zero incorrectly.
13384 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
13385 if (!DAG.getTarget().Options.UnsafeFPMath &&
13386 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
13388 std::swap(LHS, RHS);
13390 Opcode = X86ISD::FMAX;
13393 // Converting this to a max would handle both negative zeros and NaNs
13394 // incorrectly, but we can swap the operands to fix both.
13395 std::swap(LHS, RHS);
13399 Opcode = X86ISD::FMAX;
13402 // Check for x CC y ? y : x -- a min/max with reversed arms.
13403 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
13404 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
13408 // Converting this to a min would handle comparisons between positive
13409 // and negative zero incorrectly, and swapping the operands would
13410 // cause it to handle NaNs incorrectly.
13411 if (!DAG.getTarget().Options.UnsafeFPMath &&
13412 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
13413 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
13415 std::swap(LHS, RHS);
13417 Opcode = X86ISD::FMIN;
13420 // Converting this to a min would handle NaNs incorrectly.
13421 if (!DAG.getTarget().Options.UnsafeFPMath &&
13422 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
13424 Opcode = X86ISD::FMIN;
13427 // Converting this to a min would handle both negative zeros and NaNs
13428 // incorrectly, but we can swap the operands to fix both.
13429 std::swap(LHS, RHS);
13433 Opcode = X86ISD::FMIN;
13437 // Converting this to a max would handle NaNs incorrectly.
13438 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
13440 Opcode = X86ISD::FMAX;
13443 // Converting this to a max would handle comparisons between positive
13444 // and negative zero incorrectly, and swapping the operands would
13445 // cause it to handle NaNs incorrectly.
13446 if (!DAG.getTarget().Options.UnsafeFPMath &&
13447 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
13448 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
13450 std::swap(LHS, RHS);
13452 Opcode = X86ISD::FMAX;
13455 // Converting this to a max would handle both negative zeros and NaNs
13456 // incorrectly, but we can swap the operands to fix both.
13457 std::swap(LHS, RHS);
13461 Opcode = X86ISD::FMAX;
13467 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
13470 // If this is a select between two integer constants, try to do some
13472 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
13473 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
13474 // Don't do this for crazy integer types.
13475 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
13476 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
13477 // so that TrueC (the true value) is larger than FalseC.
13478 bool NeedsCondInvert = false;
13480 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
13481 // Efficiently invertible.
13482 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
13483 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
13484 isa<ConstantSDNode>(Cond.getOperand(1))))) {
13485 NeedsCondInvert = true;
13486 std::swap(TrueC, FalseC);
13489 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
13490 if (FalseC->getAPIntValue() == 0 &&
13491 TrueC->getAPIntValue().isPowerOf2()) {
13492 if (NeedsCondInvert) // Invert the condition if needed.
13493 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
13494 DAG.getConstant(1, Cond.getValueType()));
13496 // Zero extend the condition if needed.
13497 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
13499 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
13500 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
13501 DAG.getConstant(ShAmt, MVT::i8));
13504 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
13505 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
13506 if (NeedsCondInvert) // Invert the condition if needed.
13507 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
13508 DAG.getConstant(1, Cond.getValueType()));
13510 // Zero extend the condition if needed.
13511 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
13512 FalseC->getValueType(0), Cond);
13513 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13514 SDValue(FalseC, 0));
13517 // Optimize cases that will turn into an LEA instruction. This requires
13518 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
13519 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
13520 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
13521 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
13523 bool isFastMultiplier = false;
13525 switch ((unsigned char)Diff) {
13527 case 1: // result = add base, cond
13528 case 2: // result = lea base( , cond*2)
13529 case 3: // result = lea base(cond, cond*2)
13530 case 4: // result = lea base( , cond*4)
13531 case 5: // result = lea base(cond, cond*4)
13532 case 8: // result = lea base( , cond*8)
13533 case 9: // result = lea base(cond, cond*8)
13534 isFastMultiplier = true;
13539 if (isFastMultiplier) {
13540 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
13541 if (NeedsCondInvert) // Invert the condition if needed.
13542 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
13543 DAG.getConstant(1, Cond.getValueType()));
13545 // Zero extend the condition if needed.
13546 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
13548 // Scale the condition by the difference.
13550 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
13551 DAG.getConstant(Diff, Cond.getValueType()));
13553 // Add the base if non-zero.
13554 if (FalseC->getAPIntValue() != 0)
13555 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13556 SDValue(FalseC, 0));
13563 // Canonicalize max and min:
13564 // (x > y) ? x : y -> (x >= y) ? x : y
13565 // (x < y) ? x : y -> (x <= y) ? x : y
13566 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
13567 // the need for an extra compare
13568 // against zero. e.g.
13569 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
13571 // testl %edi, %edi
13573 // cmovgl %edi, %eax
13577 // cmovsl %eax, %edi
13578 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
13579 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
13580 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
13581 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
13586 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
13587 Cond = DAG.getSetCC(Cond.getDebugLoc(), Cond.getValueType(),
13588 Cond.getOperand(0), Cond.getOperand(1), NewCC);
13589 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
13594 // If we know that this node is legal then we know that it is going to be
13595 // matched by one of the SSE/AVX BLEND instructions. These instructions only
13596 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
13597 // to simplify previous instructions.
13598 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13599 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
13600 !DCI.isBeforeLegalize() &&
13601 TLI.isOperationLegal(ISD::VSELECT, VT)) {
13602 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
13603 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
13604 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
13606 APInt KnownZero, KnownOne;
13607 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
13608 DCI.isBeforeLegalizeOps());
13609 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
13610 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO))
13611 DCI.CommitTargetLoweringOpt(TLO);
13617 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
13618 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
13619 TargetLowering::DAGCombinerInfo &DCI) {
13620 DebugLoc DL = N->getDebugLoc();
13622 // If the flag operand isn't dead, don't touch this CMOV.
13623 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
13626 SDValue FalseOp = N->getOperand(0);
13627 SDValue TrueOp = N->getOperand(1);
13628 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
13629 SDValue Cond = N->getOperand(3);
13630 if (CC == X86::COND_E || CC == X86::COND_NE) {
13631 switch (Cond.getOpcode()) {
13635 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
13636 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
13637 return (CC == X86::COND_E) ? FalseOp : TrueOp;
13641 // If this is a select between two integer constants, try to do some
13642 // optimizations. Note that the operands are ordered the opposite of SELECT
13644 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
13645 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
13646 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
13647 // larger than FalseC (the false value).
13648 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
13649 CC = X86::GetOppositeBranchCondition(CC);
13650 std::swap(TrueC, FalseC);
13653 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
13654 // This is efficient for any integer data type (including i8/i16) and
13656 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
13657 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13658 DAG.getConstant(CC, MVT::i8), Cond);
13660 // Zero extend the condition if needed.
13661 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
13663 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
13664 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
13665 DAG.getConstant(ShAmt, MVT::i8));
13666 if (N->getNumValues() == 2) // Dead flag value?
13667 return DCI.CombineTo(N, Cond, SDValue());
13671 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
13672 // for any integer data type, including i8/i16.
13673 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
13674 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13675 DAG.getConstant(CC, MVT::i8), Cond);
13677 // Zero extend the condition if needed.
13678 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
13679 FalseC->getValueType(0), Cond);
13680 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13681 SDValue(FalseC, 0));
13683 if (N->getNumValues() == 2) // Dead flag value?
13684 return DCI.CombineTo(N, Cond, SDValue());
13688 // Optimize cases that will turn into an LEA instruction. This requires
13689 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
13690 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
13691 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
13692 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
13694 bool isFastMultiplier = false;
13696 switch ((unsigned char)Diff) {
13698 case 1: // result = add base, cond
13699 case 2: // result = lea base( , cond*2)
13700 case 3: // result = lea base(cond, cond*2)
13701 case 4: // result = lea base( , cond*4)
13702 case 5: // result = lea base(cond, cond*4)
13703 case 8: // result = lea base( , cond*8)
13704 case 9: // result = lea base(cond, cond*8)
13705 isFastMultiplier = true;
13710 if (isFastMultiplier) {
13711 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
13712 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13713 DAG.getConstant(CC, MVT::i8), Cond);
13714 // Zero extend the condition if needed.
13715 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
13717 // Scale the condition by the difference.
13719 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
13720 DAG.getConstant(Diff, Cond.getValueType()));
13722 // Add the base if non-zero.
13723 if (FalseC->getAPIntValue() != 0)
13724 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13725 SDValue(FalseC, 0));
13726 if (N->getNumValues() == 2) // Dead flag value?
13727 return DCI.CombineTo(N, Cond, SDValue());
13737 /// PerformMulCombine - Optimize a single multiply with constant into two
13738 /// in order to implement it with two cheaper instructions, e.g.
13739 /// LEA + SHL, LEA + LEA.
13740 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
13741 TargetLowering::DAGCombinerInfo &DCI) {
13742 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
13745 EVT VT = N->getValueType(0);
13746 if (VT != MVT::i64)
13749 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
13752 uint64_t MulAmt = C->getZExtValue();
13753 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
13756 uint64_t MulAmt1 = 0;
13757 uint64_t MulAmt2 = 0;
13758 if ((MulAmt % 9) == 0) {
13760 MulAmt2 = MulAmt / 9;
13761 } else if ((MulAmt % 5) == 0) {
13763 MulAmt2 = MulAmt / 5;
13764 } else if ((MulAmt % 3) == 0) {
13766 MulAmt2 = MulAmt / 3;
13769 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
13770 DebugLoc DL = N->getDebugLoc();
13772 if (isPowerOf2_64(MulAmt2) &&
13773 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
13774 // If second multiplifer is pow2, issue it first. We want the multiply by
13775 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
13777 std::swap(MulAmt1, MulAmt2);
13780 if (isPowerOf2_64(MulAmt1))
13781 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
13782 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
13784 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
13785 DAG.getConstant(MulAmt1, VT));
13787 if (isPowerOf2_64(MulAmt2))
13788 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
13789 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
13791 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
13792 DAG.getConstant(MulAmt2, VT));
13794 // Do not add new nodes to DAG combiner worklist.
13795 DCI.CombineTo(N, NewMul, false);
13800 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
13801 SDValue N0 = N->getOperand(0);
13802 SDValue N1 = N->getOperand(1);
13803 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
13804 EVT VT = N0.getValueType();
13806 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
13807 // since the result of setcc_c is all zero's or all ones.
13808 if (VT.isInteger() && !VT.isVector() &&
13809 N1C && N0.getOpcode() == ISD::AND &&
13810 N0.getOperand(1).getOpcode() == ISD::Constant) {
13811 SDValue N00 = N0.getOperand(0);
13812 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
13813 ((N00.getOpcode() == ISD::ANY_EXTEND ||
13814 N00.getOpcode() == ISD::ZERO_EXTEND) &&
13815 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
13816 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
13817 APInt ShAmt = N1C->getAPIntValue();
13818 Mask = Mask.shl(ShAmt);
13820 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
13821 N00, DAG.getConstant(Mask, VT));
13826 // Hardware support for vector shifts is sparse which makes us scalarize the
13827 // vector operations in many cases. Also, on sandybridge ADD is faster than
13829 // (shl V, 1) -> add V,V
13830 if (isSplatVector(N1.getNode())) {
13831 assert(N0.getValueType().isVector() && "Invalid vector shift type");
13832 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1->getOperand(0));
13833 // We shift all of the values by one. In many cases we do not have
13834 // hardware support for this operation. This is better expressed as an ADD
13836 if (N1C && (1 == N1C->getZExtValue())) {
13837 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, N0);
13844 /// PerformShiftCombine - Transforms vector shift nodes to use vector shifts
13846 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
13847 TargetLowering::DAGCombinerInfo &DCI,
13848 const X86Subtarget *Subtarget) {
13849 EVT VT = N->getValueType(0);
13850 if (N->getOpcode() == ISD::SHL) {
13851 SDValue V = PerformSHLCombine(N, DAG);
13852 if (V.getNode()) return V;
13855 // On X86 with SSE2 support, we can transform this to a vector shift if
13856 // all elements are shifted by the same amount. We can't do this in legalize
13857 // because the a constant vector is typically transformed to a constant pool
13858 // so we have no knowledge of the shift amount.
13859 if (!Subtarget->hasSSE2())
13862 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
13863 (!Subtarget->hasAVX2() ||
13864 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
13867 SDValue ShAmtOp = N->getOperand(1);
13868 EVT EltVT = VT.getVectorElementType();
13869 DebugLoc DL = N->getDebugLoc();
13870 SDValue BaseShAmt = SDValue();
13871 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
13872 unsigned NumElts = VT.getVectorNumElements();
13874 for (; i != NumElts; ++i) {
13875 SDValue Arg = ShAmtOp.getOperand(i);
13876 if (Arg.getOpcode() == ISD::UNDEF) continue;
13880 // Handle the case where the build_vector is all undef
13881 // FIXME: Should DAG allow this?
13885 for (; i != NumElts; ++i) {
13886 SDValue Arg = ShAmtOp.getOperand(i);
13887 if (Arg.getOpcode() == ISD::UNDEF) continue;
13888 if (Arg != BaseShAmt) {
13892 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
13893 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) {
13894 SDValue InVec = ShAmtOp.getOperand(0);
13895 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
13896 unsigned NumElts = InVec.getValueType().getVectorNumElements();
13898 for (; i != NumElts; ++i) {
13899 SDValue Arg = InVec.getOperand(i);
13900 if (Arg.getOpcode() == ISD::UNDEF) continue;
13904 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
13905 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
13906 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex();
13907 if (C->getZExtValue() == SplatIdx)
13908 BaseShAmt = InVec.getOperand(1);
13911 if (BaseShAmt.getNode() == 0) {
13912 // Don't create instructions with illegal types after legalize
13914 if (!DAG.getTargetLoweringInfo().isTypeLegal(EltVT) &&
13915 !DCI.isBeforeLegalize())
13918 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
13919 DAG.getIntPtrConstant(0));
13924 // The shift amount is an i32.
13925 if (EltVT.bitsGT(MVT::i32))
13926 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt);
13927 else if (EltVT.bitsLT(MVT::i32))
13928 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt);
13930 // The shift amount is identical so we can do a vector shift.
13931 SDValue ValOp = N->getOperand(0);
13932 switch (N->getOpcode()) {
13934 llvm_unreachable("Unknown shift opcode!");
13936 switch (VT.getSimpleVT().SimpleTy) {
13937 default: return SDValue();
13944 return getTargetVShiftNode(X86ISD::VSHLI, DL, VT, ValOp, BaseShAmt, DAG);
13947 switch (VT.getSimpleVT().SimpleTy) {
13948 default: return SDValue();
13953 return getTargetVShiftNode(X86ISD::VSRAI, DL, VT, ValOp, BaseShAmt, DAG);
13956 switch (VT.getSimpleVT().SimpleTy) {
13957 default: return SDValue();
13964 return getTargetVShiftNode(X86ISD::VSRLI, DL, VT, ValOp, BaseShAmt, DAG);
13970 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
13971 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
13972 // and friends. Likewise for OR -> CMPNEQSS.
13973 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
13974 TargetLowering::DAGCombinerInfo &DCI,
13975 const X86Subtarget *Subtarget) {
13978 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
13979 // we're requiring SSE2 for both.
13980 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
13981 SDValue N0 = N->getOperand(0);
13982 SDValue N1 = N->getOperand(1);
13983 SDValue CMP0 = N0->getOperand(1);
13984 SDValue CMP1 = N1->getOperand(1);
13985 DebugLoc DL = N->getDebugLoc();
13987 // The SETCCs should both refer to the same CMP.
13988 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
13991 SDValue CMP00 = CMP0->getOperand(0);
13992 SDValue CMP01 = CMP0->getOperand(1);
13993 EVT VT = CMP00.getValueType();
13995 if (VT == MVT::f32 || VT == MVT::f64) {
13996 bool ExpectingFlags = false;
13997 // Check for any users that want flags:
13998 for (SDNode::use_iterator UI = N->use_begin(),
14000 !ExpectingFlags && UI != UE; ++UI)
14001 switch (UI->getOpcode()) {
14006 ExpectingFlags = true;
14008 case ISD::CopyToReg:
14009 case ISD::SIGN_EXTEND:
14010 case ISD::ZERO_EXTEND:
14011 case ISD::ANY_EXTEND:
14015 if (!ExpectingFlags) {
14016 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
14017 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
14019 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
14020 X86::CondCode tmp = cc0;
14025 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
14026 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
14027 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
14028 X86ISD::NodeType NTOperator = is64BitFP ?
14029 X86ISD::FSETCCsd : X86ISD::FSETCCss;
14030 // FIXME: need symbolic constants for these magic numbers.
14031 // See X86ATTInstPrinter.cpp:printSSECC().
14032 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
14033 SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, MVT::f32, CMP00, CMP01,
14034 DAG.getConstant(x86cc, MVT::i8));
14035 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32,
14037 SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI,
14038 DAG.getConstant(1, MVT::i32));
14039 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
14040 return OneBitOfTruth;
14048 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
14049 /// so it can be folded inside ANDNP.
14050 static bool CanFoldXORWithAllOnes(const SDNode *N) {
14051 EVT VT = N->getValueType(0);
14053 // Match direct AllOnes for 128 and 256-bit vectors
14054 if (ISD::isBuildVectorAllOnes(N))
14057 // Look through a bit convert.
14058 if (N->getOpcode() == ISD::BITCAST)
14059 N = N->getOperand(0).getNode();
14061 // Sometimes the operand may come from a insert_subvector building a 256-bit
14063 if (VT.getSizeInBits() == 256 &&
14064 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
14065 SDValue V1 = N->getOperand(0);
14066 SDValue V2 = N->getOperand(1);
14068 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
14069 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
14070 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
14071 ISD::isBuildVectorAllOnes(V2.getNode()))
14078 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
14079 TargetLowering::DAGCombinerInfo &DCI,
14080 const X86Subtarget *Subtarget) {
14081 if (DCI.isBeforeLegalizeOps())
14084 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
14088 EVT VT = N->getValueType(0);
14090 // Create ANDN, BLSI, and BLSR instructions
14091 // BLSI is X & (-X)
14092 // BLSR is X & (X-1)
14093 if (Subtarget->hasBMI() && (VT == MVT::i32 || VT == MVT::i64)) {
14094 SDValue N0 = N->getOperand(0);
14095 SDValue N1 = N->getOperand(1);
14096 DebugLoc DL = N->getDebugLoc();
14098 // Check LHS for not
14099 if (N0.getOpcode() == ISD::XOR && isAllOnes(N0.getOperand(1)))
14100 return DAG.getNode(X86ISD::ANDN, DL, VT, N0.getOperand(0), N1);
14101 // Check RHS for not
14102 if (N1.getOpcode() == ISD::XOR && isAllOnes(N1.getOperand(1)))
14103 return DAG.getNode(X86ISD::ANDN, DL, VT, N1.getOperand(0), N0);
14105 // Check LHS for neg
14106 if (N0.getOpcode() == ISD::SUB && N0.getOperand(1) == N1 &&
14107 isZero(N0.getOperand(0)))
14108 return DAG.getNode(X86ISD::BLSI, DL, VT, N1);
14110 // Check RHS for neg
14111 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1) == N0 &&
14112 isZero(N1.getOperand(0)))
14113 return DAG.getNode(X86ISD::BLSI, DL, VT, N0);
14115 // Check LHS for X-1
14116 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
14117 isAllOnes(N0.getOperand(1)))
14118 return DAG.getNode(X86ISD::BLSR, DL, VT, N1);
14120 // Check RHS for X-1
14121 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
14122 isAllOnes(N1.getOperand(1)))
14123 return DAG.getNode(X86ISD::BLSR, DL, VT, N0);
14128 // Want to form ANDNP nodes:
14129 // 1) In the hopes of then easily combining them with OR and AND nodes
14130 // to form PBLEND/PSIGN.
14131 // 2) To match ANDN packed intrinsics
14132 if (VT != MVT::v2i64 && VT != MVT::v4i64)
14135 SDValue N0 = N->getOperand(0);
14136 SDValue N1 = N->getOperand(1);
14137 DebugLoc DL = N->getDebugLoc();
14139 // Check LHS for vnot
14140 if (N0.getOpcode() == ISD::XOR &&
14141 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
14142 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
14143 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
14145 // Check RHS for vnot
14146 if (N1.getOpcode() == ISD::XOR &&
14147 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
14148 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
14149 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
14154 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
14155 TargetLowering::DAGCombinerInfo &DCI,
14156 const X86Subtarget *Subtarget) {
14157 if (DCI.isBeforeLegalizeOps())
14160 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
14164 EVT VT = N->getValueType(0);
14166 SDValue N0 = N->getOperand(0);
14167 SDValue N1 = N->getOperand(1);
14169 // look for psign/blend
14170 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
14171 if (!Subtarget->hasSSSE3() ||
14172 (VT == MVT::v4i64 && !Subtarget->hasAVX2()))
14175 // Canonicalize pandn to RHS
14176 if (N0.getOpcode() == X86ISD::ANDNP)
14178 // or (and (m, y), (pandn m, x))
14179 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
14180 SDValue Mask = N1.getOperand(0);
14181 SDValue X = N1.getOperand(1);
14183 if (N0.getOperand(0) == Mask)
14184 Y = N0.getOperand(1);
14185 if (N0.getOperand(1) == Mask)
14186 Y = N0.getOperand(0);
14188 // Check to see if the mask appeared in both the AND and ANDNP and
14192 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
14193 // Look through mask bitcast.
14194 if (Mask.getOpcode() == ISD::BITCAST)
14195 Mask = Mask.getOperand(0);
14196 if (X.getOpcode() == ISD::BITCAST)
14197 X = X.getOperand(0);
14198 if (Y.getOpcode() == ISD::BITCAST)
14199 Y = Y.getOperand(0);
14201 EVT MaskVT = Mask.getValueType();
14203 // Validate that the Mask operand is a vector sra node.
14204 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
14205 // there is no psrai.b
14206 if (Mask.getOpcode() != X86ISD::VSRAI)
14209 // Check that the SRA is all signbits.
14210 SDValue SraC = Mask.getOperand(1);
14211 unsigned SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
14212 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
14213 if ((SraAmt + 1) != EltBits)
14216 DebugLoc DL = N->getDebugLoc();
14218 // Now we know we at least have a plendvb with the mask val. See if
14219 // we can form a psignb/w/d.
14220 // psign = x.type == y.type == mask.type && y = sub(0, x);
14221 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
14222 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
14223 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
14224 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
14225 "Unsupported VT for PSIGN");
14226 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
14227 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
14229 // PBLENDVB only available on SSE 4.1
14230 if (!Subtarget->hasSSE41())
14233 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
14235 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
14236 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
14237 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
14238 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
14239 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
14243 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
14246 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
14247 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
14249 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
14251 if (!N0.hasOneUse() || !N1.hasOneUse())
14254 SDValue ShAmt0 = N0.getOperand(1);
14255 if (ShAmt0.getValueType() != MVT::i8)
14257 SDValue ShAmt1 = N1.getOperand(1);
14258 if (ShAmt1.getValueType() != MVT::i8)
14260 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
14261 ShAmt0 = ShAmt0.getOperand(0);
14262 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
14263 ShAmt1 = ShAmt1.getOperand(0);
14265 DebugLoc DL = N->getDebugLoc();
14266 unsigned Opc = X86ISD::SHLD;
14267 SDValue Op0 = N0.getOperand(0);
14268 SDValue Op1 = N1.getOperand(0);
14269 if (ShAmt0.getOpcode() == ISD::SUB) {
14270 Opc = X86ISD::SHRD;
14271 std::swap(Op0, Op1);
14272 std::swap(ShAmt0, ShAmt1);
14275 unsigned Bits = VT.getSizeInBits();
14276 if (ShAmt1.getOpcode() == ISD::SUB) {
14277 SDValue Sum = ShAmt1.getOperand(0);
14278 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
14279 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
14280 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
14281 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
14282 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
14283 return DAG.getNode(Opc, DL, VT,
14285 DAG.getNode(ISD::TRUNCATE, DL,
14288 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
14289 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
14291 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
14292 return DAG.getNode(Opc, DL, VT,
14293 N0.getOperand(0), N1.getOperand(0),
14294 DAG.getNode(ISD::TRUNCATE, DL,
14301 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
14302 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
14303 TargetLowering::DAGCombinerInfo &DCI,
14304 const X86Subtarget *Subtarget) {
14305 if (DCI.isBeforeLegalizeOps())
14308 EVT VT = N->getValueType(0);
14310 if (VT != MVT::i32 && VT != MVT::i64)
14313 assert(Subtarget->hasBMI() && "Creating BLSMSK requires BMI instructions");
14315 // Create BLSMSK instructions by finding X ^ (X-1)
14316 SDValue N0 = N->getOperand(0);
14317 SDValue N1 = N->getOperand(1);
14318 DebugLoc DL = N->getDebugLoc();
14320 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
14321 isAllOnes(N0.getOperand(1)))
14322 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N1);
14324 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
14325 isAllOnes(N1.getOperand(1)))
14326 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N0);
14331 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
14332 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
14333 const X86Subtarget *Subtarget) {
14334 LoadSDNode *Ld = cast<LoadSDNode>(N);
14335 EVT RegVT = Ld->getValueType(0);
14336 EVT MemVT = Ld->getMemoryVT();
14337 DebugLoc dl = Ld->getDebugLoc();
14338 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14340 ISD::LoadExtType Ext = Ld->getExtensionType();
14342 // If this is a vector EXT Load then attempt to optimize it using a
14343 // shuffle. We need SSE4 for the shuffles.
14344 // TODO: It is possible to support ZExt by zeroing the undef values
14345 // during the shuffle phase or after the shuffle.
14346 if (RegVT.isVector() && RegVT.isInteger() &&
14347 Ext == ISD::EXTLOAD && Subtarget->hasSSE41()) {
14348 assert(MemVT != RegVT && "Cannot extend to the same type");
14349 assert(MemVT.isVector() && "Must load a vector from memory");
14351 unsigned NumElems = RegVT.getVectorNumElements();
14352 unsigned RegSz = RegVT.getSizeInBits();
14353 unsigned MemSz = MemVT.getSizeInBits();
14354 assert(RegSz > MemSz && "Register size must be greater than the mem size");
14355 // All sizes must be a power of two
14356 if (!isPowerOf2_32(RegSz * MemSz * NumElems)) return SDValue();
14358 // Attempt to load the original value using a single load op.
14359 // Find a scalar type which is equal to the loaded word size.
14360 MVT SclrLoadTy = MVT::i8;
14361 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
14362 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
14363 MVT Tp = (MVT::SimpleValueType)tp;
14364 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() == MemSz) {
14370 // Proceed if a load word is found.
14371 if (SclrLoadTy.getSizeInBits() != MemSz) return SDValue();
14373 EVT LoadUnitVecVT = EVT::getVectorVT(*DAG.getContext(), SclrLoadTy,
14374 RegSz/SclrLoadTy.getSizeInBits());
14376 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
14377 RegSz/MemVT.getScalarType().getSizeInBits());
14378 // Can't shuffle using an illegal type.
14379 if (!TLI.isTypeLegal(WideVecVT)) return SDValue();
14381 // Perform a single load.
14382 SDValue ScalarLoad = DAG.getLoad(SclrLoadTy, dl, Ld->getChain(),
14384 Ld->getPointerInfo(), Ld->isVolatile(),
14385 Ld->isNonTemporal(), Ld->isInvariant(),
14386 Ld->getAlignment());
14388 // Insert the word loaded into a vector.
14389 SDValue ScalarInVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
14390 LoadUnitVecVT, ScalarLoad);
14392 // Bitcast the loaded value to a vector of the original element type, in
14393 // the size of the target vector type.
14394 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT,
14396 unsigned SizeRatio = RegSz/MemSz;
14398 // Redistribute the loaded elements into the different locations.
14399 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
14400 for (unsigned i = 0; i < NumElems; i++) ShuffleVec[i*SizeRatio] = i;
14402 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
14403 DAG.getUNDEF(WideVecVT),
14406 // Bitcast to the requested type.
14407 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
14408 // Replace the original load with the new sequence
14409 // and return the new chain.
14410 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Shuff);
14411 return SDValue(ScalarLoad.getNode(), 1);
14417 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
14418 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
14419 const X86Subtarget *Subtarget) {
14420 StoreSDNode *St = cast<StoreSDNode>(N);
14421 EVT VT = St->getValue().getValueType();
14422 EVT StVT = St->getMemoryVT();
14423 DebugLoc dl = St->getDebugLoc();
14424 SDValue StoredVal = St->getOperand(1);
14425 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14427 // If we are saving a concatenation of two XMM registers, perform two stores.
14428 // This is better in Sandy Bridge cause one 256-bit mem op is done via two
14429 // 128-bit ones. If in the future the cost becomes only one memory access the
14430 // first version would be better.
14431 if (VT.getSizeInBits() == 256 &&
14432 StoredVal.getNode()->getOpcode() == ISD::CONCAT_VECTORS &&
14433 StoredVal.getNumOperands() == 2) {
14435 SDValue Value0 = StoredVal.getOperand(0);
14436 SDValue Value1 = StoredVal.getOperand(1);
14438 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
14439 SDValue Ptr0 = St->getBasePtr();
14440 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
14442 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
14443 St->getPointerInfo(), St->isVolatile(),
14444 St->isNonTemporal(), St->getAlignment());
14445 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
14446 St->getPointerInfo(), St->isVolatile(),
14447 St->isNonTemporal(), St->getAlignment());
14448 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
14451 // Optimize trunc store (of multiple scalars) to shuffle and store.
14452 // First, pack all of the elements in one place. Next, store to memory
14453 // in fewer chunks.
14454 if (St->isTruncatingStore() && VT.isVector()) {
14455 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14456 unsigned NumElems = VT.getVectorNumElements();
14457 assert(StVT != VT && "Cannot truncate to the same type");
14458 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
14459 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
14461 // From, To sizes and ElemCount must be pow of two
14462 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
14463 // We are going to use the original vector elt for storing.
14464 // Accumulated smaller vector elements must be a multiple of the store size.
14465 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
14467 unsigned SizeRatio = FromSz / ToSz;
14469 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
14471 // Create a type on which we perform the shuffle
14472 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
14473 StVT.getScalarType(), NumElems*SizeRatio);
14475 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
14477 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
14478 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
14479 for (unsigned i = 0; i < NumElems; i++ ) ShuffleVec[i] = i * SizeRatio;
14481 // Can't shuffle using an illegal type
14482 if (!TLI.isTypeLegal(WideVecVT)) return SDValue();
14484 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
14485 DAG.getUNDEF(WideVecVT),
14487 // At this point all of the data is stored at the bottom of the
14488 // register. We now need to save it to mem.
14490 // Find the largest store unit
14491 MVT StoreType = MVT::i8;
14492 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
14493 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
14494 MVT Tp = (MVT::SimpleValueType)tp;
14495 if (TLI.isTypeLegal(Tp) && StoreType.getSizeInBits() < NumElems * ToSz)
14499 // Bitcast the original vector into a vector of store-size units
14500 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
14501 StoreType, VT.getSizeInBits()/EVT(StoreType).getSizeInBits());
14502 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
14503 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
14504 SmallVector<SDValue, 8> Chains;
14505 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
14506 TLI.getPointerTy());
14507 SDValue Ptr = St->getBasePtr();
14509 // Perform one or more big stores into memory.
14510 for (unsigned i = 0; i < (ToSz*NumElems)/StoreType.getSizeInBits() ; i++) {
14511 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
14512 StoreType, ShuffWide,
14513 DAG.getIntPtrConstant(i));
14514 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
14515 St->getPointerInfo(), St->isVolatile(),
14516 St->isNonTemporal(), St->getAlignment());
14517 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
14518 Chains.push_back(Ch);
14521 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
14526 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
14527 // the FP state in cases where an emms may be missing.
14528 // A preferable solution to the general problem is to figure out the right
14529 // places to insert EMMS. This qualifies as a quick hack.
14531 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
14532 if (VT.getSizeInBits() != 64)
14535 const Function *F = DAG.getMachineFunction().getFunction();
14536 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
14537 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
14538 && Subtarget->hasSSE2();
14539 if ((VT.isVector() ||
14540 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
14541 isa<LoadSDNode>(St->getValue()) &&
14542 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
14543 St->getChain().hasOneUse() && !St->isVolatile()) {
14544 SDNode* LdVal = St->getValue().getNode();
14545 LoadSDNode *Ld = 0;
14546 int TokenFactorIndex = -1;
14547 SmallVector<SDValue, 8> Ops;
14548 SDNode* ChainVal = St->getChain().getNode();
14549 // Must be a store of a load. We currently handle two cases: the load
14550 // is a direct child, and it's under an intervening TokenFactor. It is
14551 // possible to dig deeper under nested TokenFactors.
14552 if (ChainVal == LdVal)
14553 Ld = cast<LoadSDNode>(St->getChain());
14554 else if (St->getValue().hasOneUse() &&
14555 ChainVal->getOpcode() == ISD::TokenFactor) {
14556 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
14557 if (ChainVal->getOperand(i).getNode() == LdVal) {
14558 TokenFactorIndex = i;
14559 Ld = cast<LoadSDNode>(St->getValue());
14561 Ops.push_back(ChainVal->getOperand(i));
14565 if (!Ld || !ISD::isNormalLoad(Ld))
14568 // If this is not the MMX case, i.e. we are just turning i64 load/store
14569 // into f64 load/store, avoid the transformation if there are multiple
14570 // uses of the loaded value.
14571 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
14574 DebugLoc LdDL = Ld->getDebugLoc();
14575 DebugLoc StDL = N->getDebugLoc();
14576 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
14577 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
14579 if (Subtarget->is64Bit() || F64IsLegal) {
14580 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
14581 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
14582 Ld->getPointerInfo(), Ld->isVolatile(),
14583 Ld->isNonTemporal(), Ld->isInvariant(),
14584 Ld->getAlignment());
14585 SDValue NewChain = NewLd.getValue(1);
14586 if (TokenFactorIndex != -1) {
14587 Ops.push_back(NewChain);
14588 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
14591 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
14592 St->getPointerInfo(),
14593 St->isVolatile(), St->isNonTemporal(),
14594 St->getAlignment());
14597 // Otherwise, lower to two pairs of 32-bit loads / stores.
14598 SDValue LoAddr = Ld->getBasePtr();
14599 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
14600 DAG.getConstant(4, MVT::i32));
14602 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
14603 Ld->getPointerInfo(),
14604 Ld->isVolatile(), Ld->isNonTemporal(),
14605 Ld->isInvariant(), Ld->getAlignment());
14606 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
14607 Ld->getPointerInfo().getWithOffset(4),
14608 Ld->isVolatile(), Ld->isNonTemporal(),
14610 MinAlign(Ld->getAlignment(), 4));
14612 SDValue NewChain = LoLd.getValue(1);
14613 if (TokenFactorIndex != -1) {
14614 Ops.push_back(LoLd);
14615 Ops.push_back(HiLd);
14616 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
14620 LoAddr = St->getBasePtr();
14621 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
14622 DAG.getConstant(4, MVT::i32));
14624 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
14625 St->getPointerInfo(),
14626 St->isVolatile(), St->isNonTemporal(),
14627 St->getAlignment());
14628 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
14629 St->getPointerInfo().getWithOffset(4),
14631 St->isNonTemporal(),
14632 MinAlign(St->getAlignment(), 4));
14633 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
14638 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
14639 /// and return the operands for the horizontal operation in LHS and RHS. A
14640 /// horizontal operation performs the binary operation on successive elements
14641 /// of its first operand, then on successive elements of its second operand,
14642 /// returning the resulting values in a vector. For example, if
14643 /// A = < float a0, float a1, float a2, float a3 >
14645 /// B = < float b0, float b1, float b2, float b3 >
14646 /// then the result of doing a horizontal operation on A and B is
14647 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
14648 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
14649 /// A horizontal-op B, for some already available A and B, and if so then LHS is
14650 /// set to A, RHS to B, and the routine returns 'true'.
14651 /// Note that the binary operation should have the property that if one of the
14652 /// operands is UNDEF then the result is UNDEF.
14653 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
14654 // Look for the following pattern: if
14655 // A = < float a0, float a1, float a2, float a3 >
14656 // B = < float b0, float b1, float b2, float b3 >
14658 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
14659 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
14660 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
14661 // which is A horizontal-op B.
14663 // At least one of the operands should be a vector shuffle.
14664 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
14665 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
14668 EVT VT = LHS.getValueType();
14670 assert((VT.is128BitVector() || VT.is256BitVector()) &&
14671 "Unsupported vector type for horizontal add/sub");
14673 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
14674 // operate independently on 128-bit lanes.
14675 unsigned NumElts = VT.getVectorNumElements();
14676 unsigned NumLanes = VT.getSizeInBits()/128;
14677 unsigned NumLaneElts = NumElts / NumLanes;
14678 assert((NumLaneElts % 2 == 0) &&
14679 "Vector type should have an even number of elements in each lane");
14680 unsigned HalfLaneElts = NumLaneElts/2;
14682 // View LHS in the form
14683 // LHS = VECTOR_SHUFFLE A, B, LMask
14684 // If LHS is not a shuffle then pretend it is the shuffle
14685 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
14686 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
14689 SmallVector<int, 16> LMask(NumElts);
14690 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
14691 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
14692 A = LHS.getOperand(0);
14693 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
14694 B = LHS.getOperand(1);
14695 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
14696 std::copy(Mask.begin(), Mask.end(), LMask.begin());
14698 if (LHS.getOpcode() != ISD::UNDEF)
14700 for (unsigned i = 0; i != NumElts; ++i)
14704 // Likewise, view RHS in the form
14705 // RHS = VECTOR_SHUFFLE C, D, RMask
14707 SmallVector<int, 16> RMask(NumElts);
14708 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
14709 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
14710 C = RHS.getOperand(0);
14711 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
14712 D = RHS.getOperand(1);
14713 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
14714 std::copy(Mask.begin(), Mask.end(), RMask.begin());
14716 if (RHS.getOpcode() != ISD::UNDEF)
14718 for (unsigned i = 0; i != NumElts; ++i)
14722 // Check that the shuffles are both shuffling the same vectors.
14723 if (!(A == C && B == D) && !(A == D && B == C))
14726 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
14727 if (!A.getNode() && !B.getNode())
14730 // If A and B occur in reverse order in RHS, then "swap" them (which means
14731 // rewriting the mask).
14733 CommuteVectorShuffleMask(RMask, NumElts);
14735 // At this point LHS and RHS are equivalent to
14736 // LHS = VECTOR_SHUFFLE A, B, LMask
14737 // RHS = VECTOR_SHUFFLE A, B, RMask
14738 // Check that the masks correspond to performing a horizontal operation.
14739 for (unsigned i = 0; i != NumElts; ++i) {
14740 int LIdx = LMask[i], RIdx = RMask[i];
14742 // Ignore any UNDEF components.
14743 if (LIdx < 0 || RIdx < 0 ||
14744 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
14745 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
14748 // Check that successive elements are being operated on. If not, this is
14749 // not a horizontal operation.
14750 unsigned Src = (i/HalfLaneElts) % 2; // each lane is split between srcs
14751 unsigned LaneStart = (i/NumLaneElts) * NumLaneElts;
14752 int Index = 2*(i%HalfLaneElts) + NumElts*Src + LaneStart;
14753 if (!(LIdx == Index && RIdx == Index + 1) &&
14754 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
14758 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
14759 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
14763 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
14764 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
14765 const X86Subtarget *Subtarget) {
14766 EVT VT = N->getValueType(0);
14767 SDValue LHS = N->getOperand(0);
14768 SDValue RHS = N->getOperand(1);
14770 // Try to synthesize horizontal adds from adds of shuffles.
14771 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
14772 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
14773 isHorizontalBinOp(LHS, RHS, true))
14774 return DAG.getNode(X86ISD::FHADD, N->getDebugLoc(), VT, LHS, RHS);
14778 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
14779 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
14780 const X86Subtarget *Subtarget) {
14781 EVT VT = N->getValueType(0);
14782 SDValue LHS = N->getOperand(0);
14783 SDValue RHS = N->getOperand(1);
14785 // Try to synthesize horizontal subs from subs of shuffles.
14786 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
14787 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
14788 isHorizontalBinOp(LHS, RHS, false))
14789 return DAG.getNode(X86ISD::FHSUB, N->getDebugLoc(), VT, LHS, RHS);
14793 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
14794 /// X86ISD::FXOR nodes.
14795 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
14796 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
14797 // F[X]OR(0.0, x) -> x
14798 // F[X]OR(x, 0.0) -> x
14799 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
14800 if (C->getValueAPF().isPosZero())
14801 return N->getOperand(1);
14802 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
14803 if (C->getValueAPF().isPosZero())
14804 return N->getOperand(0);
14808 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
14809 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
14810 // FAND(0.0, x) -> 0.0
14811 // FAND(x, 0.0) -> 0.0
14812 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
14813 if (C->getValueAPF().isPosZero())
14814 return N->getOperand(0);
14815 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
14816 if (C->getValueAPF().isPosZero())
14817 return N->getOperand(1);
14821 static SDValue PerformBTCombine(SDNode *N,
14823 TargetLowering::DAGCombinerInfo &DCI) {
14824 // BT ignores high bits in the bit index operand.
14825 SDValue Op1 = N->getOperand(1);
14826 if (Op1.hasOneUse()) {
14827 unsigned BitWidth = Op1.getValueSizeInBits();
14828 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
14829 APInt KnownZero, KnownOne;
14830 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
14831 !DCI.isBeforeLegalizeOps());
14832 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14833 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
14834 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
14835 DCI.CommitTargetLoweringOpt(TLO);
14840 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
14841 SDValue Op = N->getOperand(0);
14842 if (Op.getOpcode() == ISD::BITCAST)
14843 Op = Op.getOperand(0);
14844 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
14845 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
14846 VT.getVectorElementType().getSizeInBits() ==
14847 OpVT.getVectorElementType().getSizeInBits()) {
14848 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op);
14853 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
14854 TargetLowering::DAGCombinerInfo &DCI,
14855 const X86Subtarget *Subtarget) {
14856 if (!DCI.isBeforeLegalizeOps())
14859 if (!Subtarget->hasAVX())
14862 EVT VT = N->getValueType(0);
14863 SDValue Op = N->getOperand(0);
14864 EVT OpVT = Op.getValueType();
14865 DebugLoc dl = N->getDebugLoc();
14867 if ((VT == MVT::v4i64 && OpVT == MVT::v4i32) ||
14868 (VT == MVT::v8i32 && OpVT == MVT::v8i16)) {
14870 if (Subtarget->hasAVX2()) {
14871 return DAG.getNode(X86ISD::VSEXT_MOVL, dl, VT, Op);
14874 // Optimize vectors in AVX mode
14875 // Sign extend v8i16 to v8i32 and
14878 // Divide input vector into two parts
14879 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
14880 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
14881 // concat the vectors to original VT
14883 unsigned NumElems = OpVT.getVectorNumElements();
14884 SmallVector<int,8> ShufMask1(NumElems, -1);
14885 for (unsigned i = 0; i < NumElems/2; i++) ShufMask1[i] = i;
14887 SDValue OpLo = DAG.getVectorShuffle(OpVT, dl, Op, DAG.getUNDEF(OpVT),
14890 SmallVector<int,8> ShufMask2(NumElems, -1);
14891 for (unsigned i = 0; i < NumElems/2; i++) ShufMask2[i] = i + NumElems/2;
14893 SDValue OpHi = DAG.getVectorShuffle(OpVT, dl, Op, DAG.getUNDEF(OpVT),
14896 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), VT.getScalarType(),
14897 VT.getVectorNumElements()/2);
14899 OpLo = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpLo);
14900 OpHi = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpHi);
14902 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
14907 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
14908 const X86Subtarget *Subtarget) {
14909 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
14910 // (and (i32 x86isd::setcc_carry), 1)
14911 // This eliminates the zext. This transformation is necessary because
14912 // ISD::SETCC is always legalized to i8.
14913 DebugLoc dl = N->getDebugLoc();
14914 SDValue N0 = N->getOperand(0);
14915 EVT VT = N->getValueType(0);
14916 EVT OpVT = N0.getValueType();
14918 if (N0.getOpcode() == ISD::AND &&
14920 N0.getOperand(0).hasOneUse()) {
14921 SDValue N00 = N0.getOperand(0);
14922 if (N00.getOpcode() != X86ISD::SETCC_CARRY)
14924 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
14925 if (!C || C->getZExtValue() != 1)
14927 return DAG.getNode(ISD::AND, dl, VT,
14928 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
14929 N00.getOperand(0), N00.getOperand(1)),
14930 DAG.getConstant(1, VT));
14933 // Optimize vectors in AVX mode:
14936 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
14937 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
14938 // Concat upper and lower parts.
14941 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
14942 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
14943 // Concat upper and lower parts.
14945 if (Subtarget->hasAVX()) {
14947 if (((VT == MVT::v8i32) && (OpVT == MVT::v8i16)) ||
14948 ((VT == MVT::v4i64) && (OpVT == MVT::v4i32))) {
14950 if (Subtarget->hasAVX2())
14951 return DAG.getNode(X86ISD::VZEXT_MOVL, dl, VT, N0);
14953 SDValue ZeroVec = getZeroVector(OpVT, Subtarget, DAG, dl);
14954 SDValue OpLo = getTargetShuffleNode(X86ISD::UNPCKL, dl, OpVT, N0, ZeroVec,
14956 SDValue OpHi = getTargetShuffleNode(X86ISD::UNPCKH, dl, OpVT, N0, ZeroVec,
14959 EVT HVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
14960 VT.getVectorNumElements()/2);
14962 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
14963 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
14965 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
14972 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
14973 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG) {
14974 unsigned X86CC = N->getConstantOperandVal(0);
14975 SDValue EFLAG = N->getOperand(1);
14976 DebugLoc DL = N->getDebugLoc();
14978 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
14979 // a zext and produces an all-ones bit which is more useful than 0/1 in some
14981 if (X86CC == X86::COND_B)
14982 return DAG.getNode(ISD::AND, DL, MVT::i8,
14983 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
14984 DAG.getConstant(X86CC, MVT::i8), EFLAG),
14985 DAG.getConstant(1, MVT::i8));
14990 static SDValue PerformUINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
14991 const X86TargetLowering *XTLI) {
14992 SDValue Op0 = N->getOperand(0);
14993 EVT InVT = Op0->getValueType(0);
14994 if (!InVT.isSimple())
14997 // UINT_TO_FP(v4i8) -> SINT_TO_FP(ZEXT(v4i8 to v4i32))
14998 MVT SrcVT = InVT.getSimpleVT();
14999 if (SrcVT == MVT::v8i8 || SrcVT == MVT::v4i8) {
15000 DebugLoc dl = N->getDebugLoc();
15001 MVT DstVT = (SrcVT.getVectorNumElements() == 4 ? MVT::v4i32 : MVT::v8i32);
15002 SDValue P = DAG.getNode(ISD::ZERO_EXTEND, dl, DstVT, Op0);
15003 // Notice that we use SINT_TO_FP because we know that the high bits
15004 // are zero and SINT_TO_FP is better supported by the hardware.
15005 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
15011 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
15012 const X86TargetLowering *XTLI) {
15013 SDValue Op0 = N->getOperand(0);
15014 EVT InVT = Op0->getValueType(0);
15015 if (!InVT.isSimple())
15018 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
15019 MVT SrcVT = InVT.getSimpleVT();
15020 if (SrcVT == MVT::v8i8 || SrcVT == MVT::v4i8) {
15021 DebugLoc dl = N->getDebugLoc();
15022 MVT DstVT = (SrcVT.getVectorNumElements() == 4 ? MVT::v4i32 : MVT::v8i32);
15023 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
15024 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
15027 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
15028 // a 32-bit target where SSE doesn't support i64->FP operations.
15029 if (Op0.getOpcode() == ISD::LOAD) {
15030 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
15031 EVT VT = Ld->getValueType(0);
15032 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
15033 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
15034 !XTLI->getSubtarget()->is64Bit() &&
15035 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
15036 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
15037 Ld->getChain(), Op0, DAG);
15038 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
15045 static SDValue PerformFP_TO_SINTCombine(SDNode *N, SelectionDAG &DAG,
15046 const X86TargetLowering *XTLI) {
15047 EVT InVT = N->getValueType(0);
15048 if (!InVT.isSimple())
15051 // v4i8 = FP_TO_SINT() -> v4i8 = TRUNCATE (V4i32 = FP_TO_SINT()
15052 MVT VT = InVT.getSimpleVT();
15053 if (VT == MVT::v8i8 || VT == MVT::v4i8) {
15054 DebugLoc dl = N->getDebugLoc();
15055 MVT DstVT = (VT.getVectorNumElements() == 4 ? MVT::v4i32 : MVT::v8i32);
15056 SDValue I = DAG.getNode(ISD::FP_TO_SINT, dl, DstVT, N->getOperand(0));
15057 return DAG.getNode(ISD::TRUNCATE, dl, VT, I);
15063 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
15064 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
15065 X86TargetLowering::DAGCombinerInfo &DCI) {
15066 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
15067 // the result is either zero or one (depending on the input carry bit).
15068 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
15069 if (X86::isZeroNode(N->getOperand(0)) &&
15070 X86::isZeroNode(N->getOperand(1)) &&
15071 // We don't have a good way to replace an EFLAGS use, so only do this when
15073 SDValue(N, 1).use_empty()) {
15074 DebugLoc DL = N->getDebugLoc();
15075 EVT VT = N->getValueType(0);
15076 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
15077 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
15078 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
15079 DAG.getConstant(X86::COND_B,MVT::i8),
15081 DAG.getConstant(1, VT));
15082 return DCI.CombineTo(N, Res1, CarryOut);
15088 // fold (add Y, (sete X, 0)) -> adc 0, Y
15089 // (add Y, (setne X, 0)) -> sbb -1, Y
15090 // (sub (sete X, 0), Y) -> sbb 0, Y
15091 // (sub (setne X, 0), Y) -> adc -1, Y
15092 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
15093 DebugLoc DL = N->getDebugLoc();
15095 // Look through ZExts.
15096 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
15097 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
15100 SDValue SetCC = Ext.getOperand(0);
15101 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
15104 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
15105 if (CC != X86::COND_E && CC != X86::COND_NE)
15108 SDValue Cmp = SetCC.getOperand(1);
15109 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
15110 !X86::isZeroNode(Cmp.getOperand(1)) ||
15111 !Cmp.getOperand(0).getValueType().isInteger())
15114 SDValue CmpOp0 = Cmp.getOperand(0);
15115 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
15116 DAG.getConstant(1, CmpOp0.getValueType()));
15118 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
15119 if (CC == X86::COND_NE)
15120 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
15121 DL, OtherVal.getValueType(), OtherVal,
15122 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
15123 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
15124 DL, OtherVal.getValueType(), OtherVal,
15125 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
15128 /// PerformADDCombine - Do target-specific dag combines on integer adds.
15129 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
15130 const X86Subtarget *Subtarget) {
15131 EVT VT = N->getValueType(0);
15132 SDValue Op0 = N->getOperand(0);
15133 SDValue Op1 = N->getOperand(1);
15135 // Try to synthesize horizontal adds from adds of shuffles.
15136 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
15137 (Subtarget->hasAVX2() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
15138 isHorizontalBinOp(Op0, Op1, true))
15139 return DAG.getNode(X86ISD::HADD, N->getDebugLoc(), VT, Op0, Op1);
15141 return OptimizeConditionalInDecrement(N, DAG);
15144 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
15145 const X86Subtarget *Subtarget) {
15146 SDValue Op0 = N->getOperand(0);
15147 SDValue Op1 = N->getOperand(1);
15149 // X86 can't encode an immediate LHS of a sub. See if we can push the
15150 // negation into a preceding instruction.
15151 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
15152 // If the RHS of the sub is a XOR with one use and a constant, invert the
15153 // immediate. Then add one to the LHS of the sub so we can turn
15154 // X-Y -> X+~Y+1, saving one register.
15155 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
15156 isa<ConstantSDNode>(Op1.getOperand(1))) {
15157 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
15158 EVT VT = Op0.getValueType();
15159 SDValue NewXor = DAG.getNode(ISD::XOR, Op1.getDebugLoc(), VT,
15161 DAG.getConstant(~XorC, VT));
15162 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, NewXor,
15163 DAG.getConstant(C->getAPIntValue()+1, VT));
15167 // Try to synthesize horizontal adds from adds of shuffles.
15168 EVT VT = N->getValueType(0);
15169 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
15170 (Subtarget->hasAVX2() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
15171 isHorizontalBinOp(Op0, Op1, true))
15172 return DAG.getNode(X86ISD::HSUB, N->getDebugLoc(), VT, Op0, Op1);
15174 return OptimizeConditionalInDecrement(N, DAG);
15177 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
15178 DAGCombinerInfo &DCI) const {
15179 SelectionDAG &DAG = DCI.DAG;
15180 switch (N->getOpcode()) {
15182 case ISD::EXTRACT_VECTOR_ELT:
15183 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
15185 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget);
15186 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI);
15187 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
15188 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
15189 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
15190 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
15193 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
15194 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
15195 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
15196 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
15197 case ISD::LOAD: return PerformLOADCombine(N, DAG, Subtarget);
15198 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
15199 case ISD::UINT_TO_FP: return PerformUINT_TO_FPCombine(N, DAG, this);
15200 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
15201 case ISD::FP_TO_SINT: return PerformFP_TO_SINTCombine(N, DAG, this);
15202 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
15203 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
15205 case X86ISD::FOR: return PerformFORCombine(N, DAG);
15206 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
15207 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
15208 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
15209 case ISD::ANY_EXTEND:
15210 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, Subtarget);
15211 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
15212 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG, DCI);
15213 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG);
15214 case X86ISD::SHUFP: // Handle all target specific shuffles
15215 case X86ISD::PALIGN:
15216 case X86ISD::UNPCKH:
15217 case X86ISD::UNPCKL:
15218 case X86ISD::MOVHLPS:
15219 case X86ISD::MOVLHPS:
15220 case X86ISD::PSHUFD:
15221 case X86ISD::PSHUFHW:
15222 case X86ISD::PSHUFLW:
15223 case X86ISD::MOVSS:
15224 case X86ISD::MOVSD:
15225 case X86ISD::VPERMILP:
15226 case X86ISD::VPERM2X128:
15227 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
15233 /// isTypeDesirableForOp - Return true if the target has native support for
15234 /// the specified value type and it is 'desirable' to use the type for the
15235 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
15236 /// instruction encodings are longer and some i16 instructions are slow.
15237 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
15238 if (!isTypeLegal(VT))
15240 if (VT != MVT::i16)
15247 case ISD::SIGN_EXTEND:
15248 case ISD::ZERO_EXTEND:
15249 case ISD::ANY_EXTEND:
15262 /// IsDesirableToPromoteOp - This method query the target whether it is
15263 /// beneficial for dag combiner to promote the specified node. If true, it
15264 /// should return the desired promotion type by reference.
15265 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
15266 EVT VT = Op.getValueType();
15267 if (VT != MVT::i16)
15270 bool Promote = false;
15271 bool Commute = false;
15272 switch (Op.getOpcode()) {
15275 LoadSDNode *LD = cast<LoadSDNode>(Op);
15276 // If the non-extending load has a single use and it's not live out, then it
15277 // might be folded.
15278 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
15279 Op.hasOneUse()*/) {
15280 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
15281 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
15282 // The only case where we'd want to promote LOAD (rather then it being
15283 // promoted as an operand is when it's only use is liveout.
15284 if (UI->getOpcode() != ISD::CopyToReg)
15291 case ISD::SIGN_EXTEND:
15292 case ISD::ZERO_EXTEND:
15293 case ISD::ANY_EXTEND:
15298 SDValue N0 = Op.getOperand(0);
15299 // Look out for (store (shl (load), x)).
15300 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
15313 SDValue N0 = Op.getOperand(0);
15314 SDValue N1 = Op.getOperand(1);
15315 if (!Commute && MayFoldLoad(N1))
15317 // Avoid disabling potential load folding opportunities.
15318 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
15320 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
15330 //===----------------------------------------------------------------------===//
15331 // X86 Inline Assembly Support
15332 //===----------------------------------------------------------------------===//
15335 // Helper to match a string separated by whitespace.
15336 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
15337 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
15339 for (unsigned i = 0, e = args.size(); i != e; ++i) {
15340 StringRef piece(*args[i]);
15341 if (!s.startswith(piece)) // Check if the piece matches.
15344 s = s.substr(piece.size());
15345 StringRef::size_type pos = s.find_first_not_of(" \t");
15346 if (pos == 0) // We matched a prefix.
15354 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
15357 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
15358 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
15360 std::string AsmStr = IA->getAsmString();
15362 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
15363 if (!Ty || Ty->getBitWidth() % 16 != 0)
15366 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
15367 SmallVector<StringRef, 4> AsmPieces;
15368 SplitString(AsmStr, AsmPieces, ";\n");
15370 switch (AsmPieces.size()) {
15371 default: return false;
15373 // FIXME: this should verify that we are targeting a 486 or better. If not,
15374 // we will turn this bswap into something that will be lowered to logical
15375 // ops instead of emitting the bswap asm. For now, we don't support 486 or
15376 // lower so don't worry about this.
15378 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
15379 matchAsm(AsmPieces[0], "bswapl", "$0") ||
15380 matchAsm(AsmPieces[0], "bswapq", "$0") ||
15381 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
15382 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
15383 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
15384 // No need to check constraints, nothing other than the equivalent of
15385 // "=r,0" would be valid here.
15386 return IntrinsicLowering::LowerToByteSwap(CI);
15389 // rorw $$8, ${0:w} --> llvm.bswap.i16
15390 if (CI->getType()->isIntegerTy(16) &&
15391 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
15392 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
15393 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
15395 const std::string &ConstraintsStr = IA->getConstraintString();
15396 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
15397 std::sort(AsmPieces.begin(), AsmPieces.end());
15398 if (AsmPieces.size() == 4 &&
15399 AsmPieces[0] == "~{cc}" &&
15400 AsmPieces[1] == "~{dirflag}" &&
15401 AsmPieces[2] == "~{flags}" &&
15402 AsmPieces[3] == "~{fpsr}")
15403 return IntrinsicLowering::LowerToByteSwap(CI);
15407 if (CI->getType()->isIntegerTy(32) &&
15408 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
15409 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
15410 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
15411 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
15413 const std::string &ConstraintsStr = IA->getConstraintString();
15414 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
15415 std::sort(AsmPieces.begin(), AsmPieces.end());
15416 if (AsmPieces.size() == 4 &&
15417 AsmPieces[0] == "~{cc}" &&
15418 AsmPieces[1] == "~{dirflag}" &&
15419 AsmPieces[2] == "~{flags}" &&
15420 AsmPieces[3] == "~{fpsr}")
15421 return IntrinsicLowering::LowerToByteSwap(CI);
15424 if (CI->getType()->isIntegerTy(64)) {
15425 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
15426 if (Constraints.size() >= 2 &&
15427 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
15428 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
15429 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
15430 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
15431 matchAsm(AsmPieces[1], "bswap", "%edx") &&
15432 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
15433 return IntrinsicLowering::LowerToByteSwap(CI);
15443 /// getConstraintType - Given a constraint letter, return the type of
15444 /// constraint it is for this target.
15445 X86TargetLowering::ConstraintType
15446 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
15447 if (Constraint.size() == 1) {
15448 switch (Constraint[0]) {
15459 return C_RegisterClass;
15483 return TargetLowering::getConstraintType(Constraint);
15486 /// Examine constraint type and operand type and determine a weight value.
15487 /// This object must already have been set up with the operand type
15488 /// and the current alternative constraint selected.
15489 TargetLowering::ConstraintWeight
15490 X86TargetLowering::getSingleConstraintMatchWeight(
15491 AsmOperandInfo &info, const char *constraint) const {
15492 ConstraintWeight weight = CW_Invalid;
15493 Value *CallOperandVal = info.CallOperandVal;
15494 // If we don't have a value, we can't do a match,
15495 // but allow it at the lowest weight.
15496 if (CallOperandVal == NULL)
15498 Type *type = CallOperandVal->getType();
15499 // Look at the constraint type.
15500 switch (*constraint) {
15502 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
15513 if (CallOperandVal->getType()->isIntegerTy())
15514 weight = CW_SpecificReg;
15519 if (type->isFloatingPointTy())
15520 weight = CW_SpecificReg;
15523 if (type->isX86_MMXTy() && Subtarget->hasMMX())
15524 weight = CW_SpecificReg;
15528 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
15529 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasAVX()))
15530 weight = CW_Register;
15533 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
15534 if (C->getZExtValue() <= 31)
15535 weight = CW_Constant;
15539 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15540 if (C->getZExtValue() <= 63)
15541 weight = CW_Constant;
15545 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15546 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
15547 weight = CW_Constant;
15551 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15552 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
15553 weight = CW_Constant;
15557 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15558 if (C->getZExtValue() <= 3)
15559 weight = CW_Constant;
15563 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15564 if (C->getZExtValue() <= 0xff)
15565 weight = CW_Constant;
15570 if (dyn_cast<ConstantFP>(CallOperandVal)) {
15571 weight = CW_Constant;
15575 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15576 if ((C->getSExtValue() >= -0x80000000LL) &&
15577 (C->getSExtValue() <= 0x7fffffffLL))
15578 weight = CW_Constant;
15582 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15583 if (C->getZExtValue() <= 0xffffffff)
15584 weight = CW_Constant;
15591 /// LowerXConstraint - try to replace an X constraint, which matches anything,
15592 /// with another that has more specific requirements based on the type of the
15593 /// corresponding operand.
15594 const char *X86TargetLowering::
15595 LowerXConstraint(EVT ConstraintVT) const {
15596 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
15597 // 'f' like normal targets.
15598 if (ConstraintVT.isFloatingPoint()) {
15599 if (Subtarget->hasSSE2())
15601 if (Subtarget->hasSSE1())
15605 return TargetLowering::LowerXConstraint(ConstraintVT);
15608 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
15609 /// vector. If it is invalid, don't add anything to Ops.
15610 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
15611 std::string &Constraint,
15612 std::vector<SDValue>&Ops,
15613 SelectionDAG &DAG) const {
15614 SDValue Result(0, 0);
15616 // Only support length 1 constraints for now.
15617 if (Constraint.length() > 1) return;
15619 char ConstraintLetter = Constraint[0];
15620 switch (ConstraintLetter) {
15623 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15624 if (C->getZExtValue() <= 31) {
15625 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15631 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15632 if (C->getZExtValue() <= 63) {
15633 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15639 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15640 if ((int8_t)C->getSExtValue() == C->getSExtValue()) {
15641 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15647 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15648 if (C->getZExtValue() <= 255) {
15649 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15655 // 32-bit signed value
15656 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15657 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
15658 C->getSExtValue())) {
15659 // Widen to 64 bits here to get it sign extended.
15660 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
15663 // FIXME gcc accepts some relocatable values here too, but only in certain
15664 // memory models; it's complicated.
15669 // 32-bit unsigned value
15670 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15671 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
15672 C->getZExtValue())) {
15673 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15677 // FIXME gcc accepts some relocatable values here too, but only in certain
15678 // memory models; it's complicated.
15682 // Literal immediates are always ok.
15683 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
15684 // Widen to 64 bits here to get it sign extended.
15685 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
15689 // In any sort of PIC mode addresses need to be computed at runtime by
15690 // adding in a register or some sort of table lookup. These can't
15691 // be used as immediates.
15692 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
15695 // If we are in non-pic codegen mode, we allow the address of a global (with
15696 // an optional displacement) to be used with 'i'.
15697 GlobalAddressSDNode *GA = 0;
15698 int64_t Offset = 0;
15700 // Match either (GA), (GA+C), (GA+C1+C2), etc.
15702 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
15703 Offset += GA->getOffset();
15705 } else if (Op.getOpcode() == ISD::ADD) {
15706 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
15707 Offset += C->getZExtValue();
15708 Op = Op.getOperand(0);
15711 } else if (Op.getOpcode() == ISD::SUB) {
15712 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
15713 Offset += -C->getZExtValue();
15714 Op = Op.getOperand(0);
15719 // Otherwise, this isn't something we can handle, reject it.
15723 const GlobalValue *GV = GA->getGlobal();
15724 // If we require an extra load to get this address, as in PIC mode, we
15725 // can't accept it.
15726 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
15727 getTargetMachine())))
15730 Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(),
15731 GA->getValueType(0), Offset);
15736 if (Result.getNode()) {
15737 Ops.push_back(Result);
15740 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
15743 std::pair<unsigned, const TargetRegisterClass*>
15744 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
15746 // First, see if this is a constraint that directly corresponds to an LLVM
15748 if (Constraint.size() == 1) {
15749 // GCC Constraint Letters
15750 switch (Constraint[0]) {
15752 // TODO: Slight differences here in allocation order and leaving
15753 // RIP in the class. Do they matter any more here than they do
15754 // in the normal allocation?
15755 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
15756 if (Subtarget->is64Bit()) {
15757 if (VT == MVT::i32 || VT == MVT::f32)
15758 return std::make_pair(0U, &X86::GR32RegClass);
15759 if (VT == MVT::i16)
15760 return std::make_pair(0U, &X86::GR16RegClass);
15761 if (VT == MVT::i8 || VT == MVT::i1)
15762 return std::make_pair(0U, &X86::GR8RegClass);
15763 if (VT == MVT::i64 || VT == MVT::f64)
15764 return std::make_pair(0U, &X86::GR64RegClass);
15767 // 32-bit fallthrough
15768 case 'Q': // Q_REGS
15769 if (VT == MVT::i32 || VT == MVT::f32)
15770 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
15771 if (VT == MVT::i16)
15772 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
15773 if (VT == MVT::i8 || VT == MVT::i1)
15774 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
15775 if (VT == MVT::i64)
15776 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
15778 case 'r': // GENERAL_REGS
15779 case 'l': // INDEX_REGS
15780 if (VT == MVT::i8 || VT == MVT::i1)
15781 return std::make_pair(0U, &X86::GR8RegClass);
15782 if (VT == MVT::i16)
15783 return std::make_pair(0U, &X86::GR16RegClass);
15784 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
15785 return std::make_pair(0U, &X86::GR32RegClass);
15786 return std::make_pair(0U, &X86::GR64RegClass);
15787 case 'R': // LEGACY_REGS
15788 if (VT == MVT::i8 || VT == MVT::i1)
15789 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
15790 if (VT == MVT::i16)
15791 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
15792 if (VT == MVT::i32 || !Subtarget->is64Bit())
15793 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
15794 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
15795 case 'f': // FP Stack registers.
15796 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
15797 // value to the correct fpstack register class.
15798 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
15799 return std::make_pair(0U, &X86::RFP32RegClass);
15800 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
15801 return std::make_pair(0U, &X86::RFP64RegClass);
15802 return std::make_pair(0U, &X86::RFP80RegClass);
15803 case 'y': // MMX_REGS if MMX allowed.
15804 if (!Subtarget->hasMMX()) break;
15805 return std::make_pair(0U, &X86::VR64RegClass);
15806 case 'Y': // SSE_REGS if SSE2 allowed
15807 if (!Subtarget->hasSSE2()) break;
15809 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
15810 if (!Subtarget->hasSSE1()) break;
15812 switch (VT.getSimpleVT().SimpleTy) {
15814 // Scalar SSE types.
15817 return std::make_pair(0U, &X86::FR32RegClass);
15820 return std::make_pair(0U, &X86::FR64RegClass);
15828 return std::make_pair(0U, &X86::VR128RegClass);
15836 return std::make_pair(0U, &X86::VR256RegClass);
15842 // Use the default implementation in TargetLowering to convert the register
15843 // constraint into a member of a register class.
15844 std::pair<unsigned, const TargetRegisterClass*> Res;
15845 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
15847 // Not found as a standard register?
15848 if (Res.second == 0) {
15849 // Map st(0) -> st(7) -> ST0
15850 if (Constraint.size() == 7 && Constraint[0] == '{' &&
15851 tolower(Constraint[1]) == 's' &&
15852 tolower(Constraint[2]) == 't' &&
15853 Constraint[3] == '(' &&
15854 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
15855 Constraint[5] == ')' &&
15856 Constraint[6] == '}') {
15858 Res.first = X86::ST0+Constraint[4]-'0';
15859 Res.second = &X86::RFP80RegClass;
15863 // GCC allows "st(0)" to be called just plain "st".
15864 if (StringRef("{st}").equals_lower(Constraint)) {
15865 Res.first = X86::ST0;
15866 Res.second = &X86::RFP80RegClass;
15871 if (StringRef("{flags}").equals_lower(Constraint)) {
15872 Res.first = X86::EFLAGS;
15873 Res.second = &X86::CCRRegClass;
15877 // 'A' means EAX + EDX.
15878 if (Constraint == "A") {
15879 Res.first = X86::EAX;
15880 Res.second = &X86::GR32_ADRegClass;
15886 // Otherwise, check to see if this is a register class of the wrong value
15887 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
15888 // turn into {ax},{dx}.
15889 if (Res.second->hasType(VT))
15890 return Res; // Correct type already, nothing to do.
15892 // All of the single-register GCC register classes map their values onto
15893 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
15894 // really want an 8-bit or 32-bit register, map to the appropriate register
15895 // class and return the appropriate register.
15896 if (Res.second == &X86::GR16RegClass) {
15897 if (VT == MVT::i8) {
15898 unsigned DestReg = 0;
15899 switch (Res.first) {
15901 case X86::AX: DestReg = X86::AL; break;
15902 case X86::DX: DestReg = X86::DL; break;
15903 case X86::CX: DestReg = X86::CL; break;
15904 case X86::BX: DestReg = X86::BL; break;
15907 Res.first = DestReg;
15908 Res.second = &X86::GR8RegClass;
15910 } else if (VT == MVT::i32) {
15911 unsigned DestReg = 0;
15912 switch (Res.first) {
15914 case X86::AX: DestReg = X86::EAX; break;
15915 case X86::DX: DestReg = X86::EDX; break;
15916 case X86::CX: DestReg = X86::ECX; break;
15917 case X86::BX: DestReg = X86::EBX; break;
15918 case X86::SI: DestReg = X86::ESI; break;
15919 case X86::DI: DestReg = X86::EDI; break;
15920 case X86::BP: DestReg = X86::EBP; break;
15921 case X86::SP: DestReg = X86::ESP; break;
15924 Res.first = DestReg;
15925 Res.second = &X86::GR32RegClass;
15927 } else if (VT == MVT::i64) {
15928 unsigned DestReg = 0;
15929 switch (Res.first) {
15931 case X86::AX: DestReg = X86::RAX; break;
15932 case X86::DX: DestReg = X86::RDX; break;
15933 case X86::CX: DestReg = X86::RCX; break;
15934 case X86::BX: DestReg = X86::RBX; break;
15935 case X86::SI: DestReg = X86::RSI; break;
15936 case X86::DI: DestReg = X86::RDI; break;
15937 case X86::BP: DestReg = X86::RBP; break;
15938 case X86::SP: DestReg = X86::RSP; break;
15941 Res.first = DestReg;
15942 Res.second = &X86::GR64RegClass;
15945 } else if (Res.second == &X86::FR32RegClass ||
15946 Res.second == &X86::FR64RegClass ||
15947 Res.second == &X86::VR128RegClass) {
15948 // Handle references to XMM physical registers that got mapped into the
15949 // wrong class. This can happen with constraints like {xmm0} where the
15950 // target independent register mapper will just pick the first match it can
15951 // find, ignoring the required type.
15952 if (VT == MVT::f32)
15953 Res.second = &X86::FR32RegClass;
15954 else if (VT == MVT::f64)
15955 Res.second = &X86::FR64RegClass;
15956 else if (X86::VR128RegClass.hasType(VT))
15957 Res.second = &X86::VR128RegClass;