1 //===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
16 #include "X86ISelLowering.h"
17 #include "X86TargetMachine.h"
18 #include "llvm/CallingConv.h"
19 #include "llvm/Function.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/SelectionDAG.h"
24 #include "llvm/CodeGen/SSARegMap.h"
25 #include "llvm/Target/TargetOptions.h"
29 #include "llvm/Support/CommandLine.h"
30 static cl::opt<bool> EnableFastCC("enable-x86-fastcc", cl::Hidden,
31 cl::desc("Enable fastcc on X86"));
33 X86TargetLowering::X86TargetLowering(TargetMachine &TM)
34 : TargetLowering(TM) {
35 // Set up the TargetLowering object.
37 // X86 is weird, it always uses i8 for shift amounts and setcc results.
38 setShiftAmountType(MVT::i8);
39 setSetCCResultType(MVT::i8);
40 setSetCCResultContents(ZeroOrOneSetCCResult);
41 setShiftAmountFlavor(Mask); // shl X, 32 == shl X, 0
43 // Set up the register classes.
44 addRegisterClass(MVT::i8, X86::R8RegisterClass);
45 addRegisterClass(MVT::i16, X86::R16RegisterClass);
46 addRegisterClass(MVT::i32, X86::R32RegisterClass);
48 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
50 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
51 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
52 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
53 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
55 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
57 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
58 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
61 // We can handle SINT_TO_FP and FP_TO_SINT from/TO i64 even though i64
63 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
64 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
65 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
66 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
69 // Handle FP_TO_UINT by promoting the destination to a larger signed
71 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
72 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
73 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
76 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
78 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
80 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
81 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
82 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
84 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
85 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
88 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
90 setOperationAction(ISD::BRCONDTWOWAY , MVT::Other, Expand);
91 setOperationAction(ISD::BRTWOWAY_CC , MVT::Other, Expand);
92 setOperationAction(ISD::MEMMOVE , MVT::Other, Expand);
93 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Expand);
94 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
95 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
96 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
97 setOperationAction(ISD::SEXTLOAD , MVT::i1 , Expand);
98 setOperationAction(ISD::FREM , MVT::f64 , Expand);
99 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
100 setOperationAction(ISD::CTTZ , MVT::i8 , Expand);
101 setOperationAction(ISD::CTLZ , MVT::i8 , Expand);
102 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
103 setOperationAction(ISD::CTTZ , MVT::i16 , Expand);
104 setOperationAction(ISD::CTLZ , MVT::i16 , Expand);
105 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
106 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
107 setOperationAction(ISD::CTLZ , MVT::i32 , Expand);
108 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
111 setOperationAction(ISD::ROTL , MVT::i8 , Expand);
112 setOperationAction(ISD::ROTR , MVT::i8 , Expand);
113 setOperationAction(ISD::ROTL , MVT::i16 , Expand);
114 setOperationAction(ISD::ROTR , MVT::i16 , Expand);
115 setOperationAction(ISD::ROTL , MVT::i32 , Expand);
116 setOperationAction(ISD::ROTR , MVT::i32 , Expand);
119 setOperationAction(ISD::READIO , MVT::i1 , Expand);
120 setOperationAction(ISD::READIO , MVT::i8 , Expand);
121 setOperationAction(ISD::READIO , MVT::i16 , Expand);
122 setOperationAction(ISD::READIO , MVT::i32 , Expand);
123 setOperationAction(ISD::WRITEIO , MVT::i1 , Expand);
124 setOperationAction(ISD::WRITEIO , MVT::i8 , Expand);
125 setOperationAction(ISD::WRITEIO , MVT::i16 , Expand);
126 setOperationAction(ISD::WRITEIO , MVT::i32 , Expand);
128 // These should be promoted to a larger select which is supported.
129 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
130 setOperationAction(ISD::SELECT , MVT::i8 , Promote);
132 // X86 wants to expand cmov itself.
133 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
134 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
135 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
136 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
137 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
138 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
139 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
140 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
141 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
142 // X86 ret instruction may pop stack.
143 setOperationAction(ISD::RET , MVT::Other, Custom);
145 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
146 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
147 setOperationAction(ISD::ADD_PARTS , MVT::i32 , Custom);
148 setOperationAction(ISD::SUB_PARTS , MVT::i32 , Custom);
149 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
150 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
151 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
152 // X86 wants to expand memset / memcpy itself.
153 setOperationAction(ISD::MEMSET , MVT::Other, Custom);
154 setOperationAction(ISD::MEMCPY , MVT::Other, Custom);
157 // We don't have line number support yet.
158 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
159 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
160 setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
163 // Set up the FP register classes.
164 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
165 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
167 // SSE has no load+extend ops
168 setOperationAction(ISD::EXTLOAD, MVT::f32, Expand);
169 setOperationAction(ISD::ZEXTLOAD, MVT::f32, Expand);
171 // SSE has no i16 to fp conversion, only i32
172 setOperationAction(ISD::SINT_TO_FP, MVT::i16, Promote);
173 setOperationAction(ISD::FP_TO_SINT, MVT::i16, Promote);
175 // Expand FP_TO_UINT into a select.
176 // FIXME: We would like to use a Custom expander here eventually to do
177 // the optimal thing for SSE vs. the default expansion in the legalizer.
178 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
180 // We don't support sin/cos/sqrt/fmod
181 setOperationAction(ISD::FSIN , MVT::f64, Expand);
182 setOperationAction(ISD::FCOS , MVT::f64, Expand);
183 setOperationAction(ISD::FABS , MVT::f64, Expand);
184 setOperationAction(ISD::FNEG , MVT::f64, Expand);
185 setOperationAction(ISD::FREM , MVT::f64, Expand);
186 setOperationAction(ISD::FSIN , MVT::f32, Expand);
187 setOperationAction(ISD::FCOS , MVT::f32, Expand);
188 setOperationAction(ISD::FABS , MVT::f32, Expand);
189 setOperationAction(ISD::FNEG , MVT::f32, Expand);
190 setOperationAction(ISD::FREM , MVT::f32, Expand);
192 addLegalFPImmediate(+0.0); // xorps / xorpd
194 // Set up the FP register classes.
195 addRegisterClass(MVT::f64, X86::RFPRegisterClass);
198 setOperationAction(ISD::SINT_TO_FP, MVT::i16, Custom);
199 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
203 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
204 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
207 addLegalFPImmediate(+0.0); // FLD0
208 addLegalFPImmediate(+1.0); // FLD1
209 addLegalFPImmediate(-0.0); // FLD0/FCHS
210 addLegalFPImmediate(-1.0); // FLD1/FCHS
212 computeRegisterProperties();
214 maxStoresPerMemSet = 8; // For %llvm.memset -> sequence of stores
215 maxStoresPerMemCpy = 8; // For %llvm.memcpy -> sequence of stores
216 maxStoresPerMemMove = 8; // For %llvm.memmove -> sequence of stores
217 allowUnalignedMemoryAccesses = true; // x86 supports it!
220 std::vector<SDOperand>
221 X86TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
222 if (F.getCallingConv() == CallingConv::Fast && EnableFastCC)
223 return LowerFastCCArguments(F, DAG);
224 return LowerCCCArguments(F, DAG);
227 std::pair<SDOperand, SDOperand>
228 X86TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
229 bool isVarArg, unsigned CallingConv,
231 SDOperand Callee, ArgListTy &Args,
233 assert((!isVarArg || CallingConv == CallingConv::C) &&
234 "Only C takes varargs!");
236 // If the callee is a GlobalAddress node (quite common, every direct call is)
237 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
238 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
239 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
240 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
241 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
243 if (CallingConv == CallingConv::Fast && EnableFastCC)
244 return LowerFastCCCallTo(Chain, RetTy, isTailCall, Callee, Args, DAG);
245 return LowerCCCCallTo(Chain, RetTy, isVarArg, isTailCall, Callee, Args, DAG);
248 SDOperand X86TargetLowering::LowerReturnTo(SDOperand Chain, SDOperand Op,
251 return DAG.getNode(ISD::RET, MVT::Other, Chain, Op);
254 MVT::ValueType OpVT = Op.getValueType();
256 default: assert(0 && "Unknown type to return!");
258 Copy = DAG.getCopyToReg(Chain, X86::EAX, Op, SDOperand());
261 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op,
262 DAG.getConstant(1, MVT::i32));
263 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op,
264 DAG.getConstant(0, MVT::i32));
265 Copy = DAG.getCopyToReg(Chain, X86::EDX, Hi, SDOperand());
266 Copy = DAG.getCopyToReg(Copy, X86::EAX, Lo, Copy.getValue(1));
272 if (OpVT == MVT::f32)
273 Op = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Op);
274 std::vector<MVT::ValueType> Tys;
275 Tys.push_back(MVT::Other);
276 Tys.push_back(MVT::Flag);
277 std::vector<SDOperand> Ops;
278 Ops.push_back(Chain);
280 Copy = DAG.getNode(X86ISD::FP_SET_RESULT, Tys, Ops);
282 // Spill the value to memory and reload it into top of stack.
283 unsigned Size = MVT::getSizeInBits(OpVT)/8;
284 MachineFunction &MF = DAG.getMachineFunction();
285 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
286 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
287 Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain, Op,
288 StackSlot, DAG.getSrcValue(NULL));
289 std::vector<MVT::ValueType> Tys;
290 Tys.push_back(MVT::f64);
291 Tys.push_back(MVT::Other);
292 std::vector<SDOperand> Ops;
293 Ops.push_back(Chain);
294 Ops.push_back(StackSlot);
295 Ops.push_back(DAG.getValueType(OpVT));
296 Copy = DAG.getNode(X86ISD::FLD, Tys, Ops);
298 Tys.push_back(MVT::Other);
299 Tys.push_back(MVT::Flag);
301 Ops.push_back(Copy.getValue(1));
303 Copy = DAG.getNode(X86ISD::FP_SET_RESULT, Tys, Ops);
308 return DAG.getNode(X86ISD::RET_FLAG, MVT::Other,
309 Copy, DAG.getConstant(getBytesToPopOnReturn(), MVT::i16),
313 //===----------------------------------------------------------------------===//
314 // C Calling Convention implementation
315 //===----------------------------------------------------------------------===//
317 std::vector<SDOperand>
318 X86TargetLowering::LowerCCCArguments(Function &F, SelectionDAG &DAG) {
319 std::vector<SDOperand> ArgValues;
321 MachineFunction &MF = DAG.getMachineFunction();
322 MachineFrameInfo *MFI = MF.getFrameInfo();
324 // Add DAG nodes to load the arguments... On entry to a function on the X86,
325 // the stack frame looks like this:
327 // [ESP] -- return address
328 // [ESP + 4] -- first argument (leftmost lexically)
329 // [ESP + 8] -- second argument, if first argument is four bytes in size
332 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
333 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
334 MVT::ValueType ObjectVT = getValueType(I->getType());
335 unsigned ArgIncrement = 4;
338 default: assert(0 && "Unhandled argument type!");
340 case MVT::i8: ObjSize = 1; break;
341 case MVT::i16: ObjSize = 2; break;
342 case MVT::i32: ObjSize = 4; break;
343 case MVT::i64: ObjSize = ArgIncrement = 8; break;
344 case MVT::f32: ObjSize = 4; break;
345 case MVT::f64: ObjSize = ArgIncrement = 8; break;
347 // Create the frame index object for this incoming parameter...
348 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
350 // Create the SelectionDAG nodes corresponding to a load from this parameter
351 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
353 // Don't codegen dead arguments. FIXME: remove this check when we can nuke
357 ArgValue = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN,
358 DAG.getSrcValue(NULL));
360 if (MVT::isInteger(ObjectVT))
361 ArgValue = DAG.getConstant(0, ObjectVT);
363 ArgValue = DAG.getConstantFP(0, ObjectVT);
365 ArgValues.push_back(ArgValue);
367 ArgOffset += ArgIncrement; // Move on to the next argument...
370 // If the function takes variable number of arguments, make a frame index for
371 // the start of the first vararg value... for expansion of llvm.va_start.
373 VarArgsFrameIndex = MFI->CreateFixedObject(1, ArgOffset);
374 ReturnAddrIndex = 0; // No return address slot generated yet.
375 BytesToPopOnReturn = 0; // Callee pops nothing.
376 BytesCallerReserves = ArgOffset;
378 // Finally, inform the code generator which regs we return values in.
379 switch (getValueType(F.getReturnType())) {
380 default: assert(0 && "Unknown type!");
381 case MVT::isVoid: break;
386 MF.addLiveOut(X86::EAX);
389 MF.addLiveOut(X86::EAX);
390 MF.addLiveOut(X86::EDX);
394 MF.addLiveOut(X86::ST0);
400 std::pair<SDOperand, SDOperand>
401 X86TargetLowering::LowerCCCCallTo(SDOperand Chain, const Type *RetTy,
402 bool isVarArg, bool isTailCall,
403 SDOperand Callee, ArgListTy &Args,
405 // Count how many bytes are to be pushed on the stack.
406 unsigned NumBytes = 0;
410 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
411 DAG.getConstant(0, getPointerTy()));
413 for (unsigned i = 0, e = Args.size(); i != e; ++i)
414 switch (getValueType(Args[i].second)) {
415 default: assert(0 && "Unknown value type!");
429 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
430 DAG.getConstant(NumBytes, getPointerTy()));
432 // Arguments go on the stack in reverse order, as specified by the ABI.
433 unsigned ArgOffset = 0;
434 SDOperand StackPtr = DAG.getRegister(X86::ESP, MVT::i32);
435 std::vector<SDOperand> Stores;
437 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
438 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
439 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
441 switch (getValueType(Args[i].second)) {
442 default: assert(0 && "Unexpected ValueType for argument!");
446 // Promote the integer to 32 bits. If the input type is signed use a
447 // sign extend, otherwise use a zero extend.
448 if (Args[i].second->isSigned())
449 Args[i].first =DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Args[i].first);
451 Args[i].first =DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Args[i].first);
456 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
457 Args[i].first, PtrOff,
458 DAG.getSrcValue(NULL)));
463 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
464 Args[i].first, PtrOff,
465 DAG.getSrcValue(NULL)));
470 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores);
473 std::vector<MVT::ValueType> RetVals;
474 MVT::ValueType RetTyVT = getValueType(RetTy);
475 RetVals.push_back(MVT::Other);
477 // The result values produced have to be legal. Promote the result.
479 case MVT::isVoid: break;
481 RetVals.push_back(RetTyVT);
486 RetVals.push_back(MVT::i32);
490 RetVals.push_back(MVT::f32);
492 RetVals.push_back(MVT::f64);
495 RetVals.push_back(MVT::i32);
496 RetVals.push_back(MVT::i32);
501 std::vector<MVT::ValueType> NodeTys;
502 NodeTys.push_back(MVT::Other); // Returns a chain
503 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
504 std::vector<SDOperand> Ops;
505 Ops.push_back(Chain);
506 Ops.push_back(Callee);
508 // FIXME: Do not generate X86ISD::TAILCALL for now.
509 Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops);
510 SDOperand InFlag = Chain.getValue(1);
513 if (RetTyVT != MVT::isVoid) {
515 default: assert(0 && "Unknown value type to return!");
518 RetVal = DAG.getCopyFromReg(Chain, X86::AL, MVT::i8, InFlag);
519 Chain = RetVal.getValue(1);
522 RetVal = DAG.getCopyFromReg(Chain, X86::AX, MVT::i16, InFlag);
523 Chain = RetVal.getValue(1);
526 RetVal = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, InFlag);
527 Chain = RetVal.getValue(1);
530 SDOperand Lo = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, InFlag);
531 SDOperand Hi = DAG.getCopyFromReg(Lo.getValue(1), X86::EDX, MVT::i32,
533 RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi);
534 Chain = Hi.getValue(1);
539 std::vector<MVT::ValueType> Tys;
540 Tys.push_back(MVT::f64);
541 Tys.push_back(MVT::Other);
542 std::vector<SDOperand> Ops;
543 Ops.push_back(Chain);
544 Ops.push_back(InFlag);
545 RetVal = DAG.getNode(X86ISD::FP_GET_RESULT, Tys, Ops);
546 Chain = RetVal.getValue(1);
548 unsigned Size = MVT::getSizeInBits(MVT::f64)/8;
549 MachineFunction &MF = DAG.getMachineFunction();
550 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
551 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
553 Tys.push_back(MVT::Other);
555 Ops.push_back(Chain);
556 Ops.push_back(RetVal);
557 Ops.push_back(StackSlot);
558 Ops.push_back(DAG.getValueType(RetTyVT));
559 Chain = DAG.getNode(X86ISD::FST, Tys, Ops);
560 RetVal = DAG.getLoad(RetTyVT, Chain, StackSlot,
561 DAG.getSrcValue(NULL));
562 Chain = RetVal.getValue(1);
563 } else if (RetTyVT == MVT::f32)
564 RetVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, RetVal);
570 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
571 DAG.getConstant(NumBytes, getPointerTy()),
572 DAG.getConstant(0, getPointerTy()));
573 return std::make_pair(RetVal, Chain);
575 std::vector<SDOperand> Ops;
576 Ops.push_back(Chain);
577 Ops.push_back(Callee);
578 Ops.push_back(DAG.getConstant(NumBytes, getPointerTy()));
579 Ops.push_back(DAG.getConstant(0, getPointerTy()));
581 SDOperand TheCall = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL,
586 case MVT::isVoid: break;
588 ResultVal = TheCall.getValue(1);
593 ResultVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, TheCall.getValue(1));
596 // FIXME: we would really like to remember that this FP_ROUND operation is
597 // okay to eliminate if we allow excess FP precision.
598 ResultVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, TheCall.getValue(1));
601 ResultVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, TheCall.getValue(1),
602 TheCall.getValue(2));
606 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, TheCall);
607 return std::make_pair(ResultVal, Chain);
612 X86TargetLowering::LowerVAStart(SDOperand Chain, SDOperand VAListP,
613 Value *VAListV, SelectionDAG &DAG) {
614 // vastart just stores the address of the VarArgsFrameIndex slot.
615 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32);
616 return DAG.getNode(ISD::STORE, MVT::Other, Chain, FR, VAListP,
617 DAG.getSrcValue(VAListV));
621 std::pair<SDOperand,SDOperand>
622 X86TargetLowering::LowerVAArg(SDOperand Chain, SDOperand VAListP,
623 Value *VAListV, const Type *ArgTy,
625 MVT::ValueType ArgVT = getValueType(ArgTy);
626 SDOperand Val = DAG.getLoad(MVT::i32, Chain,
627 VAListP, DAG.getSrcValue(VAListV));
628 SDOperand Result = DAG.getLoad(ArgVT, Chain, Val,
629 DAG.getSrcValue(NULL));
631 if (ArgVT == MVT::i32)
634 assert((ArgVT == MVT::i64 || ArgVT == MVT::f64) &&
635 "Other types should have been promoted for varargs!");
638 Val = DAG.getNode(ISD::ADD, Val.getValueType(), Val,
639 DAG.getConstant(Amt, Val.getValueType()));
640 Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain,
641 Val, VAListP, DAG.getSrcValue(VAListV));
642 return std::make_pair(Result, Chain);
645 //===----------------------------------------------------------------------===//
646 // Fast Calling Convention implementation
647 //===----------------------------------------------------------------------===//
649 // The X86 'fast' calling convention passes up to two integer arguments in
650 // registers (an appropriate portion of EAX/EDX), passes arguments in C order,
651 // and requires that the callee pop its arguments off the stack (allowing proper
652 // tail calls), and has the same return value conventions as C calling convs.
654 // This calling convention always arranges for the callee pop value to be 8n+4
655 // bytes, which is needed for tail recursion elimination and stack alignment
658 // Note that this can be enhanced in the future to pass fp vals in registers
659 // (when we have a global fp allocator) and do other tricks.
662 /// AddLiveIn - This helper function adds the specified physical register to the
663 /// MachineFunction as a live in value. It also creates a corresponding virtual
665 static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
666 TargetRegisterClass *RC) {
667 assert(RC->contains(PReg) && "Not the correct regclass!");
668 unsigned VReg = MF.getSSARegMap()->createVirtualRegister(RC);
669 MF.addLiveIn(PReg, VReg);
674 std::vector<SDOperand>
675 X86TargetLowering::LowerFastCCArguments(Function &F, SelectionDAG &DAG) {
676 std::vector<SDOperand> ArgValues;
678 MachineFunction &MF = DAG.getMachineFunction();
679 MachineFrameInfo *MFI = MF.getFrameInfo();
681 // Add DAG nodes to load the arguments... On entry to a function the stack
682 // frame looks like this:
684 // [ESP] -- return address
685 // [ESP + 4] -- first nonreg argument (leftmost lexically)
686 // [ESP + 8] -- second nonreg argument, if first argument is 4 bytes in size
688 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
690 // Keep track of the number of integer regs passed so far. This can be either
691 // 0 (neither EAX or EDX used), 1 (EAX is used) or 2 (EAX and EDX are both
693 unsigned NumIntRegs = 0;
695 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
696 MVT::ValueType ObjectVT = getValueType(I->getType());
697 unsigned ArgIncrement = 4;
698 unsigned ObjSize = 0;
702 default: assert(0 && "Unhandled argument type!");
705 if (NumIntRegs < 2) {
706 if (!I->use_empty()) {
707 unsigned VReg = AddLiveIn(MF, NumIntRegs ? X86::DL : X86::AL,
708 X86::R8RegisterClass);
709 ArgValue = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i8);
710 DAG.setRoot(ArgValue.getValue(1));
711 if (ObjectVT == MVT::i1)
712 // FIXME: Should insert a assertzext here.
713 ArgValue = DAG.getNode(ISD::TRUNCATE, MVT::i1, ArgValue);
722 if (NumIntRegs < 2) {
723 if (!I->use_empty()) {
724 unsigned VReg = AddLiveIn(MF, NumIntRegs ? X86::DX : X86::AX,
725 X86::R16RegisterClass);
726 ArgValue = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i16);
727 DAG.setRoot(ArgValue.getValue(1));
735 if (NumIntRegs < 2) {
736 if (!I->use_empty()) {
737 unsigned VReg = AddLiveIn(MF,NumIntRegs ? X86::EDX : X86::EAX,
738 X86::R32RegisterClass);
739 ArgValue = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
740 DAG.setRoot(ArgValue.getValue(1));
748 if (NumIntRegs == 0) {
749 if (!I->use_empty()) {
750 unsigned BotReg = AddLiveIn(MF, X86::EAX, X86::R32RegisterClass);
751 unsigned TopReg = AddLiveIn(MF, X86::EDX, X86::R32RegisterClass);
753 SDOperand Low = DAG.getCopyFromReg(DAG.getRoot(), BotReg, MVT::i32);
754 SDOperand Hi = DAG.getCopyFromReg(Low.getValue(1), TopReg, MVT::i32);
755 DAG.setRoot(Hi.getValue(1));
757 ArgValue = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Low, Hi);
761 } else if (NumIntRegs == 1) {
762 if (!I->use_empty()) {
763 unsigned BotReg = AddLiveIn(MF, X86::EDX, X86::R32RegisterClass);
764 SDOperand Low = DAG.getCopyFromReg(DAG.getRoot(), BotReg, MVT::i32);
765 DAG.setRoot(Low.getValue(1));
767 // Load the high part from memory.
768 // Create the frame index object for this incoming parameter...
769 int FI = MFI->CreateFixedObject(4, ArgOffset);
770 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
771 SDOperand Hi = DAG.getLoad(MVT::i32, DAG.getEntryNode(), FIN,
772 DAG.getSrcValue(NULL));
773 ArgValue = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Low, Hi);
779 ObjSize = ArgIncrement = 8;
781 case MVT::f32: ObjSize = 4; break;
782 case MVT::f64: ObjSize = ArgIncrement = 8; break;
785 // Don't codegen dead arguments. FIXME: remove this check when we can nuke
787 if (ObjSize && !I->use_empty()) {
788 // Create the frame index object for this incoming parameter...
789 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
791 // Create the SelectionDAG nodes corresponding to a load from this
793 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
795 ArgValue = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN,
796 DAG.getSrcValue(NULL));
797 } else if (ArgValue.Val == 0) {
798 if (MVT::isInteger(ObjectVT))
799 ArgValue = DAG.getConstant(0, ObjectVT);
801 ArgValue = DAG.getConstantFP(0, ObjectVT);
803 ArgValues.push_back(ArgValue);
806 ArgOffset += ArgIncrement; // Move on to the next argument.
809 // Make sure the instruction takes 8n+4 bytes to make sure the start of the
810 // arguments and the arguments after the retaddr has been pushed are aligned.
811 if ((ArgOffset & 7) == 0)
814 VarArgsFrameIndex = 0xAAAAAAA; // fastcc functions can't have varargs.
815 ReturnAddrIndex = 0; // No return address slot generated yet.
816 BytesToPopOnReturn = ArgOffset; // Callee pops all stack arguments.
817 BytesCallerReserves = 0;
819 // Finally, inform the code generator which regs we return values in.
820 switch (getValueType(F.getReturnType())) {
821 default: assert(0 && "Unknown type!");
822 case MVT::isVoid: break;
827 MF.addLiveOut(X86::EAX);
830 MF.addLiveOut(X86::EAX);
831 MF.addLiveOut(X86::EDX);
835 MF.addLiveOut(X86::ST0);
841 std::pair<SDOperand, SDOperand>
842 X86TargetLowering::LowerFastCCCallTo(SDOperand Chain, const Type *RetTy,
843 bool isTailCall, SDOperand Callee,
844 ArgListTy &Args, SelectionDAG &DAG) {
845 // Count how many bytes are to be pushed on the stack.
846 unsigned NumBytes = 0;
848 // Keep track of the number of integer regs passed so far. This can be either
849 // 0 (neither EAX or EDX used), 1 (EAX is used) or 2 (EAX and EDX are both
851 unsigned NumIntRegs = 0;
853 for (unsigned i = 0, e = Args.size(); i != e; ++i)
854 switch (getValueType(Args[i].second)) {
855 default: assert(0 && "Unknown value type!");
860 if (NumIntRegs < 2) {
869 if (NumIntRegs == 0) {
872 } else if (NumIntRegs == 1) {
884 // Make sure the instruction takes 8n+4 bytes to make sure the start of the
885 // arguments and the arguments after the retaddr has been pushed are aligned.
886 if ((NumBytes & 7) == 0)
889 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
890 DAG.getConstant(NumBytes, getPointerTy()));
892 // Arguments go on the stack in reverse order, as specified by the ABI.
893 unsigned ArgOffset = 0;
894 SDOperand StackPtr = DAG.getCopyFromReg(DAG.getEntryNode(),
897 std::vector<SDOperand> Stores;
898 std::vector<SDOperand> RegValuesToPass;
899 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
900 switch (getValueType(Args[i].second)) {
901 default: assert(0 && "Unexpected ValueType for argument!");
903 Args[i].first = DAG.getNode(ISD::ANY_EXTEND, MVT::i8, Args[i].first);
908 if (NumIntRegs < 2) {
909 RegValuesToPass.push_back(Args[i].first);
915 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
916 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
917 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
918 Args[i].first, PtrOff,
919 DAG.getSrcValue(NULL)));
924 if (NumIntRegs < 2) { // Can pass part of it in regs?
925 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
926 Args[i].first, DAG.getConstant(1, MVT::i32));
927 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
928 Args[i].first, DAG.getConstant(0, MVT::i32));
929 RegValuesToPass.push_back(Lo);
931 if (NumIntRegs < 2) { // Pass both parts in regs?
932 RegValuesToPass.push_back(Hi);
935 // Pass the high part in memory.
936 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
937 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
938 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
939 Hi, PtrOff, DAG.getSrcValue(NULL)));
946 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
947 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
948 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
949 Args[i].first, PtrOff,
950 DAG.getSrcValue(NULL)));
956 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores);
958 // Make sure the instruction takes 8n+4 bytes to make sure the start of the
959 // arguments and the arguments after the retaddr has been pushed are aligned.
960 if ((ArgOffset & 7) == 0)
963 std::vector<MVT::ValueType> RetVals;
964 MVT::ValueType RetTyVT = getValueType(RetTy);
966 RetVals.push_back(MVT::Other);
968 // The result values produced have to be legal. Promote the result.
970 case MVT::isVoid: break;
972 RetVals.push_back(RetTyVT);
977 RetVals.push_back(MVT::i32);
981 RetVals.push_back(MVT::f32);
983 RetVals.push_back(MVT::f64);
986 RetVals.push_back(MVT::i32);
987 RetVals.push_back(MVT::i32);
992 // Build a sequence of copy-to-reg nodes chained together with token chain
993 // and flag operands which copy the outgoing args into registers.
995 for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) {
997 SDOperand RegToPass = RegValuesToPass[i];
998 switch (RegToPass.getValueType()) {
999 default: assert(0 && "Bad thing to pass in regs");
1001 CCReg = (i == 0) ? X86::AL : X86::DL;
1004 CCReg = (i == 0) ? X86::AX : X86::DX;
1007 CCReg = (i == 0) ? X86::EAX : X86::EDX;
1011 Chain = DAG.getCopyToReg(Chain, CCReg, RegToPass, InFlag);
1012 InFlag = Chain.getValue(1);
1015 std::vector<MVT::ValueType> NodeTys;
1016 NodeTys.push_back(MVT::Other); // Returns a chain
1017 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
1018 std::vector<SDOperand> Ops;
1019 Ops.push_back(Chain);
1020 Ops.push_back(Callee);
1022 Ops.push_back(InFlag);
1024 // FIXME: Do not generate X86ISD::TAILCALL for now.
1025 Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops);
1026 InFlag = Chain.getValue(1);
1029 if (RetTyVT != MVT::isVoid) {
1031 default: assert(0 && "Unknown value type to return!");
1034 RetVal = DAG.getCopyFromReg(Chain, X86::AL, MVT::i8, InFlag);
1035 Chain = RetVal.getValue(1);
1038 RetVal = DAG.getCopyFromReg(Chain, X86::AX, MVT::i16, InFlag);
1039 Chain = RetVal.getValue(1);
1042 RetVal = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, InFlag);
1043 Chain = RetVal.getValue(1);
1046 SDOperand Lo = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, InFlag);
1047 SDOperand Hi = DAG.getCopyFromReg(Lo.getValue(1), X86::EDX, MVT::i32,
1049 RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi);
1050 Chain = Hi.getValue(1);
1055 std::vector<MVT::ValueType> Tys;
1056 Tys.push_back(MVT::f64);
1057 Tys.push_back(MVT::Other);
1058 std::vector<SDOperand> Ops;
1059 Ops.push_back(Chain);
1060 Ops.push_back(InFlag);
1061 RetVal = DAG.getNode(X86ISD::FP_GET_RESULT, Tys, Ops);
1062 Chain = RetVal.getValue(1);
1064 unsigned Size = MVT::getSizeInBits(MVT::f64)/8;
1065 MachineFunction &MF = DAG.getMachineFunction();
1066 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
1067 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
1069 Tys.push_back(MVT::Other);
1071 Ops.push_back(Chain);
1072 Ops.push_back(RetVal);
1073 Ops.push_back(StackSlot);
1074 Ops.push_back(DAG.getValueType(RetTyVT));
1075 Chain = DAG.getNode(X86ISD::FST, Tys, Ops);
1076 RetVal = DAG.getLoad(RetTyVT, Chain, StackSlot,
1077 DAG.getSrcValue(NULL));
1078 Chain = RetVal.getValue(1);
1079 } else if (RetTyVT == MVT::f32)
1080 RetVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, RetVal);
1086 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
1087 DAG.getConstant(ArgOffset, getPointerTy()),
1088 DAG.getConstant(ArgOffset, getPointerTy()));
1089 return std::make_pair(RetVal, Chain);
1091 std::vector<SDOperand> Ops;
1092 Ops.push_back(Chain);
1093 Ops.push_back(Callee);
1094 Ops.push_back(DAG.getConstant(ArgOffset, getPointerTy()));
1095 // Callee pops all arg values on the stack.
1096 Ops.push_back(DAG.getConstant(ArgOffset, getPointerTy()));
1098 // Pass register arguments as needed.
1099 Ops.insert(Ops.end(), RegValuesToPass.begin(), RegValuesToPass.end());
1101 SDOperand TheCall = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL,
1103 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, TheCall);
1105 SDOperand ResultVal;
1107 case MVT::isVoid: break;
1109 ResultVal = TheCall.getValue(1);
1114 ResultVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, TheCall.getValue(1));
1117 // FIXME: we would really like to remember that this FP_ROUND operation is
1118 // okay to eliminate if we allow excess FP precision.
1119 ResultVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, TheCall.getValue(1));
1122 ResultVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, TheCall.getValue(1),
1123 TheCall.getValue(2));
1127 return std::make_pair(ResultVal, Chain);
1131 SDOperand X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) {
1132 if (ReturnAddrIndex == 0) {
1133 // Set up a frame object for the return address.
1134 MachineFunction &MF = DAG.getMachineFunction();
1135 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(4, -4);
1138 return DAG.getFrameIndex(ReturnAddrIndex, MVT::i32);
1143 std::pair<SDOperand, SDOperand> X86TargetLowering::
1144 LowerFrameReturnAddress(bool isFrameAddress, SDOperand Chain, unsigned Depth,
1145 SelectionDAG &DAG) {
1147 if (Depth) // Depths > 0 not supported yet!
1148 Result = DAG.getConstant(0, getPointerTy());
1150 SDOperand RetAddrFI = getReturnAddressFrameIndex(DAG);
1151 if (!isFrameAddress)
1152 // Just load the return address
1153 Result = DAG.getLoad(MVT::i32, DAG.getEntryNode(), RetAddrFI,
1154 DAG.getSrcValue(NULL));
1156 Result = DAG.getNode(ISD::SUB, MVT::i32, RetAddrFI,
1157 DAG.getConstant(4, MVT::i32));
1159 return std::make_pair(Result, Chain);
1162 /// getCondBrOpcodeForX86CC - Returns the X86 conditional branch opcode
1163 /// which corresponds to the condition code.
1164 static unsigned getCondBrOpcodeForX86CC(unsigned X86CC) {
1166 default: assert(0 && "Unknown X86 conditional code!");
1167 case X86ISD::COND_A: return X86::JA;
1168 case X86ISD::COND_AE: return X86::JAE;
1169 case X86ISD::COND_B: return X86::JB;
1170 case X86ISD::COND_BE: return X86::JBE;
1171 case X86ISD::COND_E: return X86::JE;
1172 case X86ISD::COND_G: return X86::JG;
1173 case X86ISD::COND_GE: return X86::JGE;
1174 case X86ISD::COND_L: return X86::JL;
1175 case X86ISD::COND_LE: return X86::JLE;
1176 case X86ISD::COND_NE: return X86::JNE;
1177 case X86ISD::COND_NO: return X86::JNO;
1178 case X86ISD::COND_NP: return X86::JNP;
1179 case X86ISD::COND_NS: return X86::JNS;
1180 case X86ISD::COND_O: return X86::JO;
1181 case X86ISD::COND_P: return X86::JP;
1182 case X86ISD::COND_S: return X86::JS;
1186 /// getX86CC - do a one to one translation of a ISD::CondCode to the X86
1187 /// specific condition code. It returns a X86ISD::COND_INVALID if it cannot
1188 /// do a direct translation.
1189 static unsigned getX86CC(SDOperand CC, bool isFP) {
1190 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
1191 unsigned X86CC = X86ISD::COND_INVALID;
1193 switch (SetCCOpcode) {
1195 case ISD::SETEQ: X86CC = X86ISD::COND_E; break;
1196 case ISD::SETGT: X86CC = X86ISD::COND_G; break;
1197 case ISD::SETGE: X86CC = X86ISD::COND_GE; break;
1198 case ISD::SETLT: X86CC = X86ISD::COND_L; break;
1199 case ISD::SETLE: X86CC = X86ISD::COND_LE; break;
1200 case ISD::SETNE: X86CC = X86ISD::COND_NE; break;
1201 case ISD::SETULT: X86CC = X86ISD::COND_B; break;
1202 case ISD::SETUGT: X86CC = X86ISD::COND_A; break;
1203 case ISD::SETULE: X86CC = X86ISD::COND_BE; break;
1204 case ISD::SETUGE: X86CC = X86ISD::COND_AE; break;
1207 // On a floating point condition, the flags are set as follows:
1209 // 0 | 0 | 0 | X > Y
1210 // 0 | 0 | 1 | X < Y
1211 // 1 | 0 | 0 | X == Y
1212 // 1 | 1 | 1 | unordered
1213 switch (SetCCOpcode) {
1216 case ISD::SETEQ: X86CC = X86ISD::COND_E; break;
1218 case ISD::SETGT: X86CC = X86ISD::COND_A; break;
1220 case ISD::SETGE: X86CC = X86ISD::COND_AE; break;
1222 case ISD::SETLT: X86CC = X86ISD::COND_B; break;
1224 case ISD::SETLE: X86CC = X86ISD::COND_BE; break;
1226 case ISD::SETNE: X86CC = X86ISD::COND_NE; break;
1227 case ISD::SETUO: X86CC = X86ISD::COND_P; break;
1228 case ISD::SETO: X86CC = X86ISD::COND_NP; break;
1234 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
1235 /// code. Current x86 isa includes the following FP cmov instructions:
1236 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
1237 static bool hasFPCMov(unsigned X86CC) {
1241 case X86ISD::COND_B:
1242 case X86ISD::COND_BE:
1243 case X86ISD::COND_E:
1244 case X86ISD::COND_P:
1245 case X86ISD::COND_A:
1246 case X86ISD::COND_AE:
1247 case X86ISD::COND_NE:
1248 case X86ISD::COND_NP:
1254 X86TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
1255 MachineBasicBlock *BB) {
1256 assert((MI->getOpcode() == X86::CMOV_FR32 ||
1257 MI->getOpcode() == X86::CMOV_FR64) &&
1258 "Unexpected instr type to insert");
1260 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
1261 // control-flow pattern. The incoming instruction knows the destination vreg
1262 // to set, the condition code register to branch on, the true/false values to
1263 // select between, and a branch opcode to use.
1264 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1265 ilist<MachineBasicBlock>::iterator It = BB;
1271 // cmpTY ccX, r1, r2
1273 // fallthrough --> copy0MBB
1274 MachineBasicBlock *thisMBB = BB;
1275 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
1276 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
1277 unsigned Opc = getCondBrOpcodeForX86CC(MI->getOperand(3).getImmedValue());
1278 BuildMI(BB, Opc, 1).addMBB(sinkMBB);
1279 MachineFunction *F = BB->getParent();
1280 F->getBasicBlockList().insert(It, copy0MBB);
1281 F->getBasicBlockList().insert(It, sinkMBB);
1282 // Update machine-CFG edges
1283 BB->addSuccessor(copy0MBB);
1284 BB->addSuccessor(sinkMBB);
1287 // %FalseValue = ...
1288 // # fallthrough to sinkMBB
1291 // Update machine-CFG edges
1292 BB->addSuccessor(sinkMBB);
1295 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
1298 BuildMI(BB, X86::PHI, 4, MI->getOperand(0).getReg())
1299 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
1300 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
1302 delete MI; // The pseudo instruction is gone now.
1307 //===----------------------------------------------------------------------===//
1308 // X86 Custom Lowering Hooks
1309 //===----------------------------------------------------------------------===//
1311 /// LowerOperation - Provide custom lowering hooks for some operations.
1313 SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
1314 switch (Op.getOpcode()) {
1315 default: assert(0 && "Should not custom lower this!");
1316 case ISD::ADD_PARTS:
1317 case ISD::SUB_PARTS: {
1318 assert(Op.getNumOperands() == 4 && Op.getValueType() == MVT::i32 &&
1319 "Not an i64 add/sub!");
1320 bool isAdd = Op.getOpcode() == ISD::ADD_PARTS;
1321 std::vector<MVT::ValueType> Tys;
1322 Tys.push_back(MVT::i32);
1323 Tys.push_back(MVT::Flag);
1324 std::vector<SDOperand> Ops;
1325 Ops.push_back(Op.getOperand(0));
1326 Ops.push_back(Op.getOperand(2));
1327 SDOperand Lo = DAG.getNode(isAdd ? X86ISD::ADD_FLAG : X86ISD::SUB_FLAG,
1329 SDOperand Hi = DAG.getNode(isAdd ? X86ISD::ADC : X86ISD::SBB, MVT::i32,
1330 Op.getOperand(1), Op.getOperand(3),
1333 Tys.push_back(MVT::i32);
1334 Tys.push_back(MVT::i32);
1338 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops);
1340 case ISD::SHL_PARTS:
1341 case ISD::SRA_PARTS:
1342 case ISD::SRL_PARTS: {
1343 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 &&
1344 "Not an i64 shift!");
1345 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
1346 SDOperand ShOpLo = Op.getOperand(0);
1347 SDOperand ShOpHi = Op.getOperand(1);
1348 SDOperand ShAmt = Op.getOperand(2);
1349 SDOperand Tmp1 = isSRA ? DAG.getNode(ISD::SRA, MVT::i32, ShOpHi,
1350 DAG.getConstant(31, MVT::i32))
1351 : DAG.getConstant(0, MVT::i32);
1353 SDOperand Tmp2, Tmp3;
1354 if (Op.getOpcode() == ISD::SHL_PARTS) {
1355 Tmp2 = DAG.getNode(X86ISD::SHLD, MVT::i32, ShOpHi, ShOpLo, ShAmt);
1356 Tmp3 = DAG.getNode(ISD::SHL, MVT::i32, ShOpLo, ShAmt);
1358 Tmp2 = DAG.getNode(X86ISD::SHRD, MVT::i32, ShOpLo, ShOpHi, ShAmt);
1359 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SHL, MVT::i32, ShOpHi, ShAmt);
1362 SDOperand InFlag = DAG.getNode(X86ISD::TEST, MVT::Flag,
1363 ShAmt, DAG.getConstant(32, MVT::i8));
1366 SDOperand CC = DAG.getConstant(X86ISD::COND_NE, MVT::i8);
1368 std::vector<MVT::ValueType> Tys;
1369 Tys.push_back(MVT::i32);
1370 Tys.push_back(MVT::Flag);
1371 std::vector<SDOperand> Ops;
1372 if (Op.getOpcode() == ISD::SHL_PARTS) {
1373 Ops.push_back(Tmp2);
1374 Ops.push_back(Tmp3);
1376 Ops.push_back(InFlag);
1377 Hi = DAG.getNode(X86ISD::CMOV, Tys, Ops);
1378 InFlag = Hi.getValue(1);
1381 Ops.push_back(Tmp3);
1382 Ops.push_back(Tmp1);
1384 Ops.push_back(InFlag);
1385 Lo = DAG.getNode(X86ISD::CMOV, Tys, Ops);
1387 Ops.push_back(Tmp2);
1388 Ops.push_back(Tmp3);
1390 Ops.push_back(InFlag);
1391 Lo = DAG.getNode(X86ISD::CMOV, Tys, Ops);
1392 InFlag = Lo.getValue(1);
1395 Ops.push_back(Tmp3);
1396 Ops.push_back(Tmp1);
1398 Ops.push_back(InFlag);
1399 Hi = DAG.getNode(X86ISD::CMOV, Tys, Ops);
1403 Tys.push_back(MVT::i32);
1404 Tys.push_back(MVT::i32);
1408 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops);
1410 case ISD::SINT_TO_FP: {
1411 assert(Op.getValueType() == MVT::f64 &&
1412 Op.getOperand(0).getValueType() <= MVT::i64 &&
1413 Op.getOperand(0).getValueType() >= MVT::i16 &&
1414 "Unknown SINT_TO_FP to lower!");
1417 MVT::ValueType SrcVT = Op.getOperand(0).getValueType();
1418 unsigned Size = MVT::getSizeInBits(SrcVT)/8;
1419 MachineFunction &MF = DAG.getMachineFunction();
1420 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
1421 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
1422 SDOperand Chain = DAG.getNode(ISD::STORE, MVT::Other,
1423 DAG.getEntryNode(), Op.getOperand(0),
1424 StackSlot, DAG.getSrcValue(NULL));
1427 std::vector<MVT::ValueType> Tys;
1428 Tys.push_back(MVT::f64);
1429 Tys.push_back(MVT::Flag);
1430 std::vector<SDOperand> Ops;
1431 Ops.push_back(Chain);
1432 Ops.push_back(StackSlot);
1433 Ops.push_back(DAG.getValueType(SrcVT));
1434 Result = DAG.getNode(X86ISD::FILD, Tys, Ops);
1437 case ISD::FP_TO_SINT: {
1438 assert(Op.getValueType() <= MVT::i64 && Op.getValueType() >= MVT::i16 &&
1439 Op.getOperand(0).getValueType() == MVT::f64 &&
1440 "Unknown FP_TO_SINT to lower!");
1441 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
1443 MachineFunction &MF = DAG.getMachineFunction();
1444 unsigned MemSize = MVT::getSizeInBits(Op.getValueType())/8;
1445 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
1446 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
1449 switch (Op.getValueType()) {
1450 default: assert(0 && "Invalid FP_TO_SINT to lower!");
1451 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
1452 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
1453 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
1456 // Build the FP_TO_INT*_IN_MEM
1457 std::vector<SDOperand> Ops;
1458 Ops.push_back(DAG.getEntryNode());
1459 Ops.push_back(Op.getOperand(0));
1460 Ops.push_back(StackSlot);
1461 SDOperand FIST = DAG.getNode(Opc, MVT::Other, Ops);
1464 return DAG.getLoad(Op.getValueType(), FIST, StackSlot,
1465 DAG.getSrcValue(NULL));
1467 case ISD::READCYCLECOUNTER: {
1468 std::vector<MVT::ValueType> Tys;
1469 Tys.push_back(MVT::Other);
1470 Tys.push_back(MVT::Flag);
1471 std::vector<SDOperand> Ops;
1472 Ops.push_back(Op.getOperand(0));
1473 SDOperand rd = DAG.getNode(X86ISD::RDTSC_DAG, Tys, Ops);
1475 Ops.push_back(DAG.getCopyFromReg(rd, X86::EAX, MVT::i32, rd.getValue(1)));
1476 Ops.push_back(DAG.getCopyFromReg(Ops[0].getValue(1), X86::EDX,
1477 MVT::i32, Ops[0].getValue(2)));
1478 Ops.push_back(Ops[1].getValue(1));
1479 Tys[0] = Tys[1] = MVT::i32;
1480 Tys.push_back(MVT::Other);
1481 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops);
1484 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
1485 SDOperand CC = Op.getOperand(2);
1486 SDOperand Cond = DAG.getNode(X86ISD::CMP, MVT::Flag,
1487 Op.getOperand(0), Op.getOperand(1));
1488 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
1489 bool isFP = MVT::isFloatingPoint(Op.getOperand(1).getValueType());
1490 unsigned X86CC = getX86CC(CC, isFP);
1491 if (X86CC != X86ISD::COND_INVALID) {
1492 return DAG.getNode(X86ISD::SETCC, MVT::i8,
1493 DAG.getConstant(X86CC, MVT::i8), Cond);
1495 assert(isFP && "Illegal integer SetCC!");
1497 std::vector<MVT::ValueType> Tys;
1498 std::vector<SDOperand> Ops;
1499 switch (SetCCOpcode) {
1500 default: assert(false && "Illegal floating point SetCC!");
1501 case ISD::SETOEQ: { // !PF & ZF
1502 Tys.push_back(MVT::i8);
1503 Tys.push_back(MVT::Flag);
1504 Ops.push_back(DAG.getConstant(X86ISD::COND_NP, MVT::i8));
1505 Ops.push_back(Cond);
1506 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, Tys, Ops);
1507 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8,
1508 DAG.getConstant(X86ISD::COND_E, MVT::i8),
1510 return DAG.getNode(ISD::AND, MVT::i8, Tmp1, Tmp2);
1512 case ISD::SETOLT: { // !PF & CF
1513 Tys.push_back(MVT::i8);
1514 Tys.push_back(MVT::Flag);
1515 Ops.push_back(DAG.getConstant(X86ISD::COND_NP, MVT::i8));
1516 Ops.push_back(Cond);
1517 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, Tys, Ops);
1518 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8,
1519 DAG.getConstant(X86ISD::COND_B, MVT::i8),
1521 return DAG.getNode(ISD::AND, MVT::i8, Tmp1, Tmp2);
1523 case ISD::SETOLE: { // !PF & (CF || ZF)
1524 Tys.push_back(MVT::i8);
1525 Tys.push_back(MVT::Flag);
1526 Ops.push_back(DAG.getConstant(X86ISD::COND_NP, MVT::i8));
1527 Ops.push_back(Cond);
1528 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, Tys, Ops);
1529 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8,
1530 DAG.getConstant(X86ISD::COND_BE, MVT::i8),
1532 return DAG.getNode(ISD::AND, MVT::i8, Tmp1, Tmp2);
1534 case ISD::SETUGT: { // PF | (!ZF & !CF)
1535 Tys.push_back(MVT::i8);
1536 Tys.push_back(MVT::Flag);
1537 Ops.push_back(DAG.getConstant(X86ISD::COND_P, MVT::i8));
1538 Ops.push_back(Cond);
1539 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, Tys, Ops);
1540 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8,
1541 DAG.getConstant(X86ISD::COND_A, MVT::i8),
1543 return DAG.getNode(ISD::OR, MVT::i8, Tmp1, Tmp2);
1545 case ISD::SETUGE: { // PF | !CF
1546 Tys.push_back(MVT::i8);
1547 Tys.push_back(MVT::Flag);
1548 Ops.push_back(DAG.getConstant(X86ISD::COND_P, MVT::i8));
1549 Ops.push_back(Cond);
1550 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, Tys, Ops);
1551 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8,
1552 DAG.getConstant(X86ISD::COND_AE, MVT::i8),
1554 return DAG.getNode(ISD::OR, MVT::i8, Tmp1, Tmp2);
1556 case ISD::SETUNE: { // PF | !ZF
1557 Tys.push_back(MVT::i8);
1558 Tys.push_back(MVT::Flag);
1559 Ops.push_back(DAG.getConstant(X86ISD::COND_P, MVT::i8));
1560 Ops.push_back(Cond);
1561 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, Tys, Ops);
1562 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8,
1563 DAG.getConstant(X86ISD::COND_NE, MVT::i8),
1565 return DAG.getNode(ISD::OR, MVT::i8, Tmp1, Tmp2);
1571 MVT::ValueType VT = Op.getValueType();
1572 bool isFP = MVT::isFloatingPoint(VT);
1573 bool isFPStack = isFP && (X86Vector < SSE2);
1574 bool isFPSSE = isFP && (X86Vector >= SSE2);
1575 bool isValid = false;
1576 SDOperand Op0 = Op.getOperand(0);
1578 if (Op0.getOpcode() == X86ISD::SETCC) {
1579 CC = Op0.getOperand(0);
1580 Cond = Op0.getOperand(1);
1582 !(isFPStack && !hasFPCMov(cast<ConstantSDNode>(CC)->getSignExtended()));
1583 } else if (Op0.getOpcode() == ISD::SETCC) {
1584 CC = Op0.getOperand(2);
1585 bool isFP = MVT::isFloatingPoint(Op0.getOperand(1).getValueType());
1586 unsigned X86CC = getX86CC(CC, isFP);
1587 CC = DAG.getConstant(X86CC, MVT::i8);
1588 Cond = DAG.getNode(X86ISD::CMP, MVT::Flag,
1589 Op0.getOperand(0), Op0.getOperand(1));
1594 CC = DAG.getConstant(X86ISD::COND_E, MVT::i8);
1595 Cond = DAG.getNode(X86ISD::TEST, MVT::Flag, Op0, Op0);
1598 std::vector<MVT::ValueType> Tys;
1599 Tys.push_back(Op.getValueType());
1600 Tys.push_back(MVT::Flag);
1601 std::vector<SDOperand> Ops;
1602 Ops.push_back(Op.getOperand(1));
1603 Ops.push_back(Op.getOperand(2));
1605 Ops.push_back(Cond);
1606 return DAG.getNode(X86ISD::CMOV, Tys, Ops);
1609 SDOperand Cond = Op.getOperand(1);
1610 SDOperand Dest = Op.getOperand(2);
1612 // TODO: handle Cond == OR / AND / XOR
1613 if (Cond.getOpcode() == X86ISD::SETCC) {
1614 CC = Cond.getOperand(0);
1615 Cond = Cond.getOperand(1);
1616 } else if (Cond.getOpcode() == ISD::SETCC) {
1617 CC = Cond.getOperand(2);
1618 bool isFP = MVT::isFloatingPoint(Cond.getOperand(1).getValueType());
1619 unsigned X86CC = getX86CC(CC, isFP);
1620 CC = DAG.getConstant(X86CC, MVT::i8);
1621 Cond = DAG.getNode(X86ISD::CMP, MVT::Flag,
1622 Cond.getOperand(0), Cond.getOperand(1));
1624 CC = DAG.getConstant(X86ISD::COND_NE, MVT::i8);
1625 Cond = DAG.getNode(X86ISD::TEST, MVT::Flag, Cond, Cond);
1627 return DAG.getNode(X86ISD::BRCOND, Op.getValueType(),
1628 Op.getOperand(0), Op.getOperand(2), CC, Cond);
1631 // Can only be return void.
1632 return DAG.getNode(X86ISD::RET_FLAG, MVT::Other, Op.getOperand(0),
1633 DAG.getConstant(getBytesToPopOnReturn(), MVT::i16));
1637 SDOperand Chain = Op.getOperand(0);
1639 (unsigned)cast<ConstantSDNode>(Op.getOperand(4))->getValue();
1640 if (Align == 0) Align = 1;
1644 if (ConstantSDNode *ValC = dyn_cast<ConstantSDNode>(Op.getOperand(2))) {
1646 unsigned Val = ValC->getValue() & 255;
1648 // If the value is a constant, then we can potentially use larger sets.
1649 switch (Align & 3) {
1650 case 2: // WORD aligned
1652 if (ConstantSDNode *I = dyn_cast<ConstantSDNode>(Op.getOperand(3)))
1653 Count = DAG.getConstant(I->getValue() / 2, MVT::i32);
1655 Count = DAG.getNode(ISD::SRL, MVT::i32, Op.getOperand(3),
1656 DAG.getConstant(1, MVT::i8));
1657 Val = (Val << 8) | Val;
1660 case 0: // DWORD aligned
1662 if (ConstantSDNode *I = dyn_cast<ConstantSDNode>(Op.getOperand(3)))
1663 Count = DAG.getConstant(I->getValue() / 4, MVT::i32);
1665 Count = DAG.getNode(ISD::SRL, MVT::i32, Op.getOperand(3),
1666 DAG.getConstant(2, MVT::i8));
1667 Val = (Val << 8) | Val;
1668 Val = (Val << 16) | Val;
1671 default: // Byte aligned
1673 Count = Op.getOperand(3);
1678 Chain = DAG.getCopyToReg(Chain, ValReg, DAG.getConstant(Val, AVT),
1680 InFlag = Chain.getValue(1);
1683 Count = Op.getOperand(3);
1684 Chain = DAG.getCopyToReg(Chain, X86::AL, Op.getOperand(2), InFlag);
1685 InFlag = Chain.getValue(1);
1688 Chain = DAG.getCopyToReg(Chain, X86::ECX, Count, InFlag);
1689 InFlag = Chain.getValue(1);
1690 Chain = DAG.getCopyToReg(Chain, X86::EDI, Op.getOperand(1), InFlag);
1691 InFlag = Chain.getValue(1);
1693 return DAG.getNode(X86ISD::REP_STOS, MVT::Other, Chain,
1694 DAG.getValueType(AVT), InFlag);
1697 SDOperand Chain = Op.getOperand(0);
1699 (unsigned)cast<ConstantSDNode>(Op.getOperand(4))->getValue();
1700 if (Align == 0) Align = 1;
1704 switch (Align & 3) {
1705 case 2: // WORD aligned
1707 if (ConstantSDNode *I = dyn_cast<ConstantSDNode>(Op.getOperand(3)))
1708 Count = DAG.getConstant(I->getValue() / 2, MVT::i32);
1710 Count = DAG.getNode(ISD::SRL, MVT::i32, Op.getOperand(3),
1711 DAG.getConstant(1, MVT::i8));
1713 case 0: // DWORD aligned
1715 if (ConstantSDNode *I = dyn_cast<ConstantSDNode>(Op.getOperand(3)))
1716 Count = DAG.getConstant(I->getValue() / 4, MVT::i32);
1718 Count = DAG.getNode(ISD::SRL, MVT::i32, Op.getOperand(3),
1719 DAG.getConstant(2, MVT::i8));
1721 default: // Byte aligned
1723 Count = Op.getOperand(3);
1728 Chain = DAG.getCopyToReg(Chain, X86::ECX, Count, InFlag);
1729 InFlag = Chain.getValue(1);
1730 Chain = DAG.getCopyToReg(Chain, X86::EDI, Op.getOperand(1), InFlag);
1731 InFlag = Chain.getValue(1);
1732 Chain = DAG.getCopyToReg(Chain, X86::ESI, Op.getOperand(2), InFlag);
1733 InFlag = Chain.getValue(1);
1735 return DAG.getNode(X86ISD::REP_MOVS, MVT::Other, Chain,
1736 DAG.getValueType(AVT), InFlag);
1738 case ISD::GlobalAddress: {
1740 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1741 // For Darwin, external and weak symbols are indirect, so we want to load
1742 // the value at address GV, not the value of GV itself. This means that
1743 // the GlobalAddress must be in the base or index register of the address,
1744 // not the GV offset field.
1745 if (getTargetMachine().
1746 getSubtarget<X86Subtarget>().getIndirectExternAndWeakGlobals() &&
1747 (GV->hasWeakLinkage() || GV->isExternal()))
1748 Result = DAG.getLoad(MVT::i32, DAG.getEntryNode(),
1749 DAG.getTargetGlobalAddress(GV, getPointerTy()),
1750 DAG.getSrcValue(NULL));
1756 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
1758 default: return NULL;
1759 case X86ISD::ADD_FLAG: return "X86ISD::ADD_FLAG";
1760 case X86ISD::SUB_FLAG: return "X86ISD::SUB_FLAG";
1761 case X86ISD::ADC: return "X86ISD::ADC";
1762 case X86ISD::SBB: return "X86ISD::SBB";
1763 case X86ISD::SHLD: return "X86ISD::SHLD";
1764 case X86ISD::SHRD: return "X86ISD::SHRD";
1765 case X86ISD::FILD: return "X86ISD::FILD";
1766 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
1767 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
1768 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
1769 case X86ISD::FLD: return "X86ISD::FLD";
1770 case X86ISD::FST: return "X86ISD::FST";
1771 case X86ISD::FP_GET_RESULT: return "X86ISD::FP_GET_RESULT";
1772 case X86ISD::FP_SET_RESULT: return "X86ISD::FP_SET_RESULT";
1773 case X86ISD::CALL: return "X86ISD::CALL";
1774 case X86ISD::TAILCALL: return "X86ISD::TAILCALL";
1775 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
1776 case X86ISD::CMP: return "X86ISD::CMP";
1777 case X86ISD::TEST: return "X86ISD::TEST";
1778 case X86ISD::SETCC: return "X86ISD::SETCC";
1779 case X86ISD::CMOV: return "X86ISD::CMOV";
1780 case X86ISD::BRCOND: return "X86ISD::BRCOND";
1781 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
1782 case X86ISD::REP_STOS: return "X86ISD::RET_STOS";
1783 case X86ISD::REP_MOVS: return "X86ISD::RET_MOVS";
1787 bool X86TargetLowering::isMaskedValueZeroForTargetNode(const SDOperand &Op,
1788 uint64_t Mask) const {
1790 unsigned Opc = Op.getOpcode();
1794 assert(Opc >= ISD::BUILTIN_OP_END && "Expected a target specific node");
1796 case X86ISD::SETCC: return (Mask & 1) == 0;