1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86FrameLowering.h"
19 #include "X86InstrBuilder.h"
20 #include "X86MachineFunctionInfo.h"
21 #include "X86TargetMachine.h"
22 #include "X86TargetObjectFile.h"
23 #include "llvm/ADT/SmallBitVector.h"
24 #include "llvm/ADT/SmallSet.h"
25 #include "llvm/ADT/Statistic.h"
26 #include "llvm/ADT/StringExtras.h"
27 #include "llvm/ADT/StringSwitch.h"
28 #include "llvm/Analysis/EHPersonalities.h"
29 #include "llvm/CodeGen/IntrinsicLowering.h"
30 #include "llvm/CodeGen/MachineFrameInfo.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineJumpTableInfo.h"
34 #include "llvm/CodeGen/MachineModuleInfo.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/WinEHFuncInfo.h"
37 #include "llvm/IR/CallSite.h"
38 #include "llvm/IR/CallingConv.h"
39 #include "llvm/IR/Constants.h"
40 #include "llvm/IR/DerivedTypes.h"
41 #include "llvm/IR/Function.h"
42 #include "llvm/IR/GlobalAlias.h"
43 #include "llvm/IR/GlobalVariable.h"
44 #include "llvm/IR/Instructions.h"
45 #include "llvm/IR/Intrinsics.h"
46 #include "llvm/MC/MCAsmInfo.h"
47 #include "llvm/MC/MCContext.h"
48 #include "llvm/MC/MCExpr.h"
49 #include "llvm/MC/MCSymbol.h"
50 #include "llvm/Support/CommandLine.h"
51 #include "llvm/Support/Debug.h"
52 #include "llvm/Support/ErrorHandling.h"
53 #include "llvm/Support/MathExtras.h"
54 #include "llvm/Target/TargetOptions.h"
55 #include "X86IntrinsicsInfo.h"
61 #define DEBUG_TYPE "x86-isel"
63 STATISTIC(NumTailCalls, "Number of tail calls");
65 static cl::opt<bool> ExperimentalVectorWideningLegalization(
66 "x86-experimental-vector-widening-legalization", cl::init(false),
67 cl::desc("Enable an experimental vector type legalization through widening "
68 "rather than promotion."),
71 X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
72 const X86Subtarget &STI)
73 : TargetLowering(TM), Subtarget(&STI) {
74 X86ScalarSSEf64 = Subtarget->hasSSE2();
75 X86ScalarSSEf32 = Subtarget->hasSSE1();
76 MVT PtrVT = MVT::getIntegerVT(8 * TM.getPointerSize());
78 // Set up the TargetLowering object.
80 // X86 is weird. It always uses i8 for shift amounts and setcc results.
81 setBooleanContents(ZeroOrOneBooleanContent);
82 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
83 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
85 // For 64-bit, since we have so many registers, use the ILP scheduler.
86 // For 32-bit, use the register pressure specific scheduling.
87 // For Atom, always use ILP scheduling.
88 if (Subtarget->isAtom())
89 setSchedulingPreference(Sched::ILP);
90 else if (Subtarget->is64Bit())
91 setSchedulingPreference(Sched::ILP);
93 setSchedulingPreference(Sched::RegPressure);
94 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
95 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
97 // Bypass expensive divides on Atom when compiling with O2.
98 if (TM.getOptLevel() >= CodeGenOpt::Default) {
99 if (Subtarget->hasSlowDivide32())
100 addBypassSlowDiv(32, 8);
101 if (Subtarget->hasSlowDivide64() && Subtarget->is64Bit())
102 addBypassSlowDiv(64, 16);
105 if (Subtarget->isTargetKnownWindowsMSVC()) {
106 // Setup Windows compiler runtime calls.
107 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
108 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
109 setLibcallName(RTLIB::SREM_I64, "_allrem");
110 setLibcallName(RTLIB::UREM_I64, "_aullrem");
111 setLibcallName(RTLIB::MUL_I64, "_allmul");
112 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
113 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
114 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
115 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
116 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
119 if (Subtarget->isTargetDarwin()) {
120 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
121 setUseUnderscoreSetJmp(false);
122 setUseUnderscoreLongJmp(false);
123 } else if (Subtarget->isTargetWindowsGNU()) {
124 // MS runtime is weird: it exports _setjmp, but longjmp!
125 setUseUnderscoreSetJmp(true);
126 setUseUnderscoreLongJmp(false);
128 setUseUnderscoreSetJmp(true);
129 setUseUnderscoreLongJmp(true);
132 // Set up the register classes.
133 addRegisterClass(MVT::i8, &X86::GR8RegClass);
134 addRegisterClass(MVT::i16, &X86::GR16RegClass);
135 addRegisterClass(MVT::i32, &X86::GR32RegClass);
136 if (Subtarget->is64Bit())
137 addRegisterClass(MVT::i64, &X86::GR64RegClass);
139 for (MVT VT : MVT::integer_valuetypes())
140 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
142 // We don't accept any truncstore of integer registers.
143 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
144 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
145 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
146 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
147 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
148 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
150 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
152 // SETOEQ and SETUNE require checking two conditions.
153 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
154 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
155 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
156 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
157 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
158 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
160 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
162 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
163 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
164 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
166 if (Subtarget->is64Bit()) {
167 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512())
168 // f32/f64 are legal, f80 is custom.
169 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
171 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
172 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
173 } else if (!Subtarget->useSoftFloat()) {
174 // We have an algorithm for SSE2->double, and we turn this into a
175 // 64-bit FILD followed by conditional FADD for other targets.
176 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
177 // We have an algorithm for SSE2, and we turn this into a 64-bit
178 // FILD or VCVTUSI2SS/SD for other targets.
179 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
182 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
184 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
185 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
187 if (!Subtarget->useSoftFloat()) {
188 // SSE has no i16 to fp conversion, only i32
189 if (X86ScalarSSEf32) {
190 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
191 // f32 and f64 cases are Legal, f80 case is not
192 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
194 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
195 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
198 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
199 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
202 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
204 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
205 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
207 if (!Subtarget->useSoftFloat()) {
208 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
209 // are Legal, f80 is custom lowered.
210 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
211 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
213 if (X86ScalarSSEf32) {
214 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
215 // f32 and f64 cases are Legal, f80 case is not
216 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
218 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
219 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
222 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
223 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Expand);
224 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Expand);
227 // Handle FP_TO_UINT by promoting the destination to a larger signed
229 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
230 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
231 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
233 if (Subtarget->is64Bit()) {
234 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512()) {
235 // FP_TO_UINT-i32/i64 is legal for f32/f64, but custom for f80.
236 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
237 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
239 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
240 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
242 } else if (!Subtarget->useSoftFloat()) {
243 // Since AVX is a superset of SSE3, only check for SSE here.
244 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
245 // Expand FP_TO_UINT into a select.
246 // FIXME: We would like to use a Custom expander here eventually to do
247 // the optimal thing for SSE vs. the default expansion in the legalizer.
248 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
250 // With AVX512 we can use vcvts[ds]2usi for f32/f64->i32, f80 is custom.
251 // With SSE3 we can use fisttpll to convert to a signed i64; without
252 // SSE, we're stuck with a fistpll.
253 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
255 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
258 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
259 if (!X86ScalarSSEf64) {
260 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
261 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
262 if (Subtarget->is64Bit()) {
263 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
264 // Without SSE, i64->f64 goes through memory.
265 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
269 // Scalar integer divide and remainder are lowered to use operations that
270 // produce two results, to match the available instructions. This exposes
271 // the two-result form to trivial CSE, which is able to combine x/y and x%y
272 // into a single instruction.
274 // Scalar integer multiply-high is also lowered to use two-result
275 // operations, to match the available instructions. However, plain multiply
276 // (low) operations are left as Legal, as there are single-result
277 // instructions for this in x86. Using the two-result multiply instructions
278 // when both high and low results are needed must be arranged by dagcombine.
279 for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
280 setOperationAction(ISD::MULHS, VT, Expand);
281 setOperationAction(ISD::MULHU, VT, Expand);
282 setOperationAction(ISD::SDIV, VT, Expand);
283 setOperationAction(ISD::UDIV, VT, Expand);
284 setOperationAction(ISD::SREM, VT, Expand);
285 setOperationAction(ISD::UREM, VT, Expand);
287 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
288 setOperationAction(ISD::ADDC, VT, Custom);
289 setOperationAction(ISD::ADDE, VT, Custom);
290 setOperationAction(ISD::SUBC, VT, Custom);
291 setOperationAction(ISD::SUBE, VT, Custom);
294 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
295 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
296 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
297 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
298 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
299 setOperationAction(ISD::BR_CC , MVT::f128, Expand);
300 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
301 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
302 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
303 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
304 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
305 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
306 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
307 setOperationAction(ISD::SELECT_CC , MVT::f128, Expand);
308 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
309 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
310 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
311 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
312 if (Subtarget->is64Bit())
313 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
314 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
315 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
316 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
317 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
319 if (Subtarget->is32Bit() && Subtarget->isTargetKnownWindowsMSVC()) {
320 // On 32 bit MSVC, `fmodf(f32)` is not defined - only `fmod(f64)`
321 // is. We should promote the value to 64-bits to solve this.
322 // This is what the CRT headers do - `fmodf` is an inline header
323 // function casting to f64 and calling `fmod`.
324 setOperationAction(ISD::FREM , MVT::f32 , Promote);
326 setOperationAction(ISD::FREM , MVT::f32 , Expand);
329 setOperationAction(ISD::FREM , MVT::f64 , Expand);
330 setOperationAction(ISD::FREM , MVT::f80 , Expand);
331 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
333 // Promote the i8 variants and force them on up to i32 which has a shorter
335 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
336 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
337 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
338 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
339 if (Subtarget->hasBMI()) {
340 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
341 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
342 if (Subtarget->is64Bit())
343 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
345 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
346 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
347 if (Subtarget->is64Bit())
348 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
351 if (Subtarget->hasLZCNT()) {
352 // When promoting the i8 variants, force them to i32 for a shorter
354 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
355 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
356 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
357 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
358 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
359 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
360 if (Subtarget->is64Bit())
361 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
363 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
364 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
365 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
366 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
367 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
368 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
369 if (Subtarget->is64Bit()) {
370 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
371 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
375 // Special handling for half-precision floating point conversions.
376 // If we don't have F16C support, then lower half float conversions
377 // into library calls.
378 if (Subtarget->useSoftFloat() || !Subtarget->hasF16C()) {
379 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
380 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
383 // There's never any support for operations beyond MVT::f32.
384 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
385 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
386 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
387 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
389 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
390 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
391 setLoadExtAction(ISD::EXTLOAD, MVT::f80, MVT::f16, Expand);
392 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
393 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
394 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
396 if (Subtarget->hasPOPCNT()) {
397 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
399 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
400 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
401 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
402 if (Subtarget->is64Bit())
403 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
406 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
408 if (!Subtarget->hasMOVBE())
409 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
411 // These should be promoted to a larger select which is supported.
412 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
413 // X86 wants to expand cmov itself.
414 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
415 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
416 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
417 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
418 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
419 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
420 setOperationAction(ISD::SELECT , MVT::f128 , Custom);
421 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
422 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
423 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
424 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
425 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
426 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
427 setOperationAction(ISD::SETCC , MVT::f128 , Custom);
428 setOperationAction(ISD::SETCCE , MVT::i8 , Custom);
429 setOperationAction(ISD::SETCCE , MVT::i16 , Custom);
430 setOperationAction(ISD::SETCCE , MVT::i32 , Custom);
431 if (Subtarget->is64Bit()) {
432 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
433 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
434 setOperationAction(ISD::SETCCE , MVT::i64 , Custom);
436 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
437 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
438 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
439 // support continuation, user-level threading, and etc.. As a result, no
440 // other SjLj exception interfaces are implemented and please don't build
441 // your own exception handling based on them.
442 // LLVM/Clang supports zero-cost DWARF exception handling.
443 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
444 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
447 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
448 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
449 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
450 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
451 if (Subtarget->is64Bit())
452 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
453 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
454 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
455 if (Subtarget->is64Bit()) {
456 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
457 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
458 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
459 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
460 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
462 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
463 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
464 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
465 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
466 if (Subtarget->is64Bit()) {
467 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
468 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
469 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
472 if (Subtarget->hasSSE1())
473 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
475 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
477 // Expand certain atomics
478 for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
479 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
480 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
481 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
484 if (Subtarget->hasCmpxchg16b()) {
485 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
488 // FIXME - use subtarget debug flags
489 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
490 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
491 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
494 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
495 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
497 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
498 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
500 setOperationAction(ISD::TRAP, MVT::Other, Legal);
501 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
503 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
504 setOperationAction(ISD::VASTART , MVT::Other, Custom);
505 setOperationAction(ISD::VAEND , MVT::Other, Expand);
506 if (Subtarget->is64Bit()) {
507 setOperationAction(ISD::VAARG , MVT::Other, Custom);
508 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
510 // TargetInfo::CharPtrBuiltinVaList
511 setOperationAction(ISD::VAARG , MVT::Other, Expand);
512 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
515 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
516 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
518 setOperationAction(ISD::DYNAMIC_STACKALLOC, PtrVT, Custom);
520 // GC_TRANSITION_START and GC_TRANSITION_END need custom lowering.
521 setOperationAction(ISD::GC_TRANSITION_START, MVT::Other, Custom);
522 setOperationAction(ISD::GC_TRANSITION_END, MVT::Other, Custom);
524 if (!Subtarget->useSoftFloat() && X86ScalarSSEf64) {
525 // f32 and f64 use SSE.
526 // Set up the FP register classes.
527 addRegisterClass(MVT::f32, &X86::FR32RegClass);
528 addRegisterClass(MVT::f64, &X86::FR64RegClass);
530 // Use ANDPD to simulate FABS.
531 setOperationAction(ISD::FABS , MVT::f64, Custom);
532 setOperationAction(ISD::FABS , MVT::f32, Custom);
534 // Use XORP to simulate FNEG.
535 setOperationAction(ISD::FNEG , MVT::f64, Custom);
536 setOperationAction(ISD::FNEG , MVT::f32, Custom);
538 // Use ANDPD and ORPD to simulate FCOPYSIGN.
539 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
540 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
542 // Lower this to FGETSIGNx86 plus an AND.
543 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
544 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
546 // We don't support sin/cos/fmod
547 setOperationAction(ISD::FSIN , MVT::f64, Expand);
548 setOperationAction(ISD::FCOS , MVT::f64, Expand);
549 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
550 setOperationAction(ISD::FSIN , MVT::f32, Expand);
551 setOperationAction(ISD::FCOS , MVT::f32, Expand);
552 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
554 // Expand FP immediates into loads from the stack, except for the special
556 addLegalFPImmediate(APFloat(+0.0)); // xorpd
557 addLegalFPImmediate(APFloat(+0.0f)); // xorps
558 } else if (!Subtarget->useSoftFloat() && X86ScalarSSEf32) {
559 // Use SSE for f32, x87 for f64.
560 // Set up the FP register classes.
561 addRegisterClass(MVT::f32, &X86::FR32RegClass);
562 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
564 // Use ANDPS to simulate FABS.
565 setOperationAction(ISD::FABS , MVT::f32, Custom);
567 // Use XORP to simulate FNEG.
568 setOperationAction(ISD::FNEG , MVT::f32, Custom);
570 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
572 // Use ANDPS and ORPS to simulate FCOPYSIGN.
573 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
574 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
576 // We don't support sin/cos/fmod
577 setOperationAction(ISD::FSIN , MVT::f32, Expand);
578 setOperationAction(ISD::FCOS , MVT::f32, Expand);
579 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
581 // Special cases we handle for FP constants.
582 addLegalFPImmediate(APFloat(+0.0f)); // xorps
583 addLegalFPImmediate(APFloat(+0.0)); // FLD0
584 addLegalFPImmediate(APFloat(+1.0)); // FLD1
585 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
586 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
588 if (!TM.Options.UnsafeFPMath) {
589 setOperationAction(ISD::FSIN , MVT::f64, Expand);
590 setOperationAction(ISD::FCOS , MVT::f64, Expand);
591 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
593 } else if (!Subtarget->useSoftFloat()) {
594 // f32 and f64 in x87.
595 // Set up the FP register classes.
596 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
597 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
599 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
600 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
601 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
602 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
604 if (!TM.Options.UnsafeFPMath) {
605 setOperationAction(ISD::FSIN , MVT::f64, Expand);
606 setOperationAction(ISD::FSIN , MVT::f32, Expand);
607 setOperationAction(ISD::FCOS , MVT::f64, Expand);
608 setOperationAction(ISD::FCOS , MVT::f32, Expand);
609 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
610 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
612 addLegalFPImmediate(APFloat(+0.0)); // FLD0
613 addLegalFPImmediate(APFloat(+1.0)); // FLD1
614 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
615 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
616 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
617 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
618 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
619 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
622 // We don't support FMA.
623 setOperationAction(ISD::FMA, MVT::f64, Expand);
624 setOperationAction(ISD::FMA, MVT::f32, Expand);
626 // Long double always uses X87, except f128 in MMX.
627 if (!Subtarget->useSoftFloat()) {
628 if (Subtarget->is64Bit() && Subtarget->hasMMX()) {
629 addRegisterClass(MVT::f128, &X86::FR128RegClass);
630 ValueTypeActions.setTypeAction(MVT::f128, TypeSoftenFloat);
631 setOperationAction(ISD::FABS , MVT::f128, Custom);
632 setOperationAction(ISD::FNEG , MVT::f128, Custom);
633 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Custom);
636 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
637 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
638 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
640 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
641 addLegalFPImmediate(TmpFlt); // FLD0
643 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
646 APFloat TmpFlt2(+1.0);
647 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
649 addLegalFPImmediate(TmpFlt2); // FLD1
650 TmpFlt2.changeSign();
651 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
654 if (!TM.Options.UnsafeFPMath) {
655 setOperationAction(ISD::FSIN , MVT::f80, Expand);
656 setOperationAction(ISD::FCOS , MVT::f80, Expand);
657 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
660 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
661 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
662 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
663 setOperationAction(ISD::FRINT, MVT::f80, Expand);
664 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
665 setOperationAction(ISD::FMA, MVT::f80, Expand);
668 // Always use a library call for pow.
669 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
670 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
671 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
673 setOperationAction(ISD::FLOG, MVT::f80, Expand);
674 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
675 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
676 setOperationAction(ISD::FEXP, MVT::f80, Expand);
677 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
678 setOperationAction(ISD::FMINNUM, MVT::f80, Expand);
679 setOperationAction(ISD::FMAXNUM, MVT::f80, Expand);
681 // First set operation action for all vector types to either promote
682 // (for widening) or expand (for scalarization). Then we will selectively
683 // turn on ones that can be effectively codegen'd.
684 for (MVT VT : MVT::vector_valuetypes()) {
685 setOperationAction(ISD::ADD , VT, Expand);
686 setOperationAction(ISD::SUB , VT, Expand);
687 setOperationAction(ISD::FADD, VT, Expand);
688 setOperationAction(ISD::FNEG, VT, Expand);
689 setOperationAction(ISD::FSUB, VT, Expand);
690 setOperationAction(ISD::MUL , VT, Expand);
691 setOperationAction(ISD::FMUL, VT, Expand);
692 setOperationAction(ISD::SDIV, VT, Expand);
693 setOperationAction(ISD::UDIV, VT, Expand);
694 setOperationAction(ISD::FDIV, VT, Expand);
695 setOperationAction(ISD::SREM, VT, Expand);
696 setOperationAction(ISD::UREM, VT, Expand);
697 setOperationAction(ISD::LOAD, VT, Expand);
698 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
699 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
700 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
701 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
702 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
703 setOperationAction(ISD::FABS, VT, Expand);
704 setOperationAction(ISD::FSIN, VT, Expand);
705 setOperationAction(ISD::FSINCOS, VT, Expand);
706 setOperationAction(ISD::FCOS, VT, Expand);
707 setOperationAction(ISD::FSINCOS, VT, Expand);
708 setOperationAction(ISD::FREM, VT, Expand);
709 setOperationAction(ISD::FMA, VT, Expand);
710 setOperationAction(ISD::FPOWI, VT, Expand);
711 setOperationAction(ISD::FSQRT, VT, Expand);
712 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
713 setOperationAction(ISD::FFLOOR, VT, Expand);
714 setOperationAction(ISD::FCEIL, VT, Expand);
715 setOperationAction(ISD::FTRUNC, VT, Expand);
716 setOperationAction(ISD::FRINT, VT, Expand);
717 setOperationAction(ISD::FNEARBYINT, VT, Expand);
718 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
719 setOperationAction(ISD::MULHS, VT, Expand);
720 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
721 setOperationAction(ISD::MULHU, VT, Expand);
722 setOperationAction(ISD::SDIVREM, VT, Expand);
723 setOperationAction(ISD::UDIVREM, VT, Expand);
724 setOperationAction(ISD::FPOW, VT, Expand);
725 setOperationAction(ISD::CTPOP, VT, Expand);
726 setOperationAction(ISD::CTTZ, VT, Expand);
727 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
728 setOperationAction(ISD::CTLZ, VT, Expand);
729 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
730 setOperationAction(ISD::SHL, VT, Expand);
731 setOperationAction(ISD::SRA, VT, Expand);
732 setOperationAction(ISD::SRL, VT, Expand);
733 setOperationAction(ISD::ROTL, VT, Expand);
734 setOperationAction(ISD::ROTR, VT, Expand);
735 setOperationAction(ISD::BSWAP, VT, Expand);
736 setOperationAction(ISD::SETCC, VT, Expand);
737 setOperationAction(ISD::FLOG, VT, Expand);
738 setOperationAction(ISD::FLOG2, VT, Expand);
739 setOperationAction(ISD::FLOG10, VT, Expand);
740 setOperationAction(ISD::FEXP, VT, Expand);
741 setOperationAction(ISD::FEXP2, VT, Expand);
742 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
743 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
744 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
745 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
746 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
747 setOperationAction(ISD::TRUNCATE, VT, Expand);
748 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
749 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
750 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
751 setOperationAction(ISD::VSELECT, VT, Expand);
752 setOperationAction(ISD::SELECT_CC, VT, Expand);
753 for (MVT InnerVT : MVT::vector_valuetypes()) {
754 setTruncStoreAction(InnerVT, VT, Expand);
756 setLoadExtAction(ISD::SEXTLOAD, InnerVT, VT, Expand);
757 setLoadExtAction(ISD::ZEXTLOAD, InnerVT, VT, Expand);
759 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like
760 // types, we have to deal with them whether we ask for Expansion or not.
761 // Setting Expand causes its own optimisation problems though, so leave
763 if (VT.getVectorElementType() == MVT::i1)
764 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
766 // EXTLOAD for MVT::f16 vectors is not legal because f16 vectors are
767 // split/scalarized right now.
768 if (VT.getVectorElementType() == MVT::f16)
769 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
773 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
774 // with -msoft-float, disable use of MMX as well.
775 if (!Subtarget->useSoftFloat() && Subtarget->hasMMX()) {
776 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
777 // No operations on x86mmx supported, everything uses intrinsics.
780 // MMX-sized vectors (other than x86mmx) are expected to be expanded
781 // into smaller operations.
782 for (MVT MMXTy : {MVT::v8i8, MVT::v4i16, MVT::v2i32, MVT::v1i64}) {
783 setOperationAction(ISD::MULHS, MMXTy, Expand);
784 setOperationAction(ISD::AND, MMXTy, Expand);
785 setOperationAction(ISD::OR, MMXTy, Expand);
786 setOperationAction(ISD::XOR, MMXTy, Expand);
787 setOperationAction(ISD::SCALAR_TO_VECTOR, MMXTy, Expand);
788 setOperationAction(ISD::SELECT, MMXTy, Expand);
789 setOperationAction(ISD::BITCAST, MMXTy, Expand);
791 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
793 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE1()) {
794 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
796 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
797 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
798 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
799 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
800 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
801 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
802 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
803 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
804 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
805 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
806 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
807 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
808 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
809 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
812 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE2()) {
813 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
815 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
816 // registers cannot be used even for integer operations.
817 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
818 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
819 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
820 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
822 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
823 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
824 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
825 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
826 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
827 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
828 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
829 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
830 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
831 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
832 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
833 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
834 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
835 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
836 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
837 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
838 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
839 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
840 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
841 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
842 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
843 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
844 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
846 setOperationAction(ISD::SMAX, MVT::v8i16, Legal);
847 setOperationAction(ISD::UMAX, MVT::v16i8, Legal);
848 setOperationAction(ISD::SMIN, MVT::v8i16, Legal);
849 setOperationAction(ISD::UMIN, MVT::v16i8, Legal);
851 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
852 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
853 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
854 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
856 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
857 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
858 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
859 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
860 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
862 setOperationAction(ISD::CTPOP, MVT::v16i8, Custom);
863 setOperationAction(ISD::CTPOP, MVT::v8i16, Custom);
864 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
865 setOperationAction(ISD::CTPOP, MVT::v2i64, Custom);
867 setOperationAction(ISD::CTTZ, MVT::v16i8, Custom);
868 setOperationAction(ISD::CTTZ, MVT::v8i16, Custom);
869 setOperationAction(ISD::CTTZ, MVT::v4i32, Custom);
870 // ISD::CTTZ v2i64 - scalarization is faster.
871 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i8, Custom);
872 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i16, Custom);
873 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i32, Custom);
874 // ISD::CTTZ_ZERO_UNDEF v2i64 - scalarization is faster.
876 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
877 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32 }) {
878 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
879 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
880 setOperationAction(ISD::VSELECT, VT, Custom);
881 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
884 // We support custom legalizing of sext and anyext loads for specific
885 // memory vector types which we can load as a scalar (or sequence of
886 // scalars) and extend in-register to a legal 128-bit vector type. For sext
887 // loads these must work with a single scalar load.
888 for (MVT VT : MVT::integer_vector_valuetypes()) {
889 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i8, Custom);
890 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i16, Custom);
891 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v8i8, Custom);
892 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i8, Custom);
893 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Custom);
894 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i32, Custom);
895 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i8, Custom);
896 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Custom);
897 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8i8, Custom);
900 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
901 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
902 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
903 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
904 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
905 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
906 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
907 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
909 if (Subtarget->is64Bit()) {
910 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
911 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
914 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
915 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32 }) {
916 setOperationAction(ISD::AND, VT, Promote);
917 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
918 setOperationAction(ISD::OR, VT, Promote);
919 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
920 setOperationAction(ISD::XOR, VT, Promote);
921 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
922 setOperationAction(ISD::LOAD, VT, Promote);
923 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
924 setOperationAction(ISD::SELECT, VT, Promote);
925 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
928 // Custom lower v2i64 and v2f64 selects.
929 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
930 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
931 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
932 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
934 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
935 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
937 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
939 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
940 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
941 // As there is no 64-bit GPR available, we need build a special custom
942 // sequence to convert from v2i32 to v2f32.
943 if (!Subtarget->is64Bit())
944 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
946 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
947 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
949 for (MVT VT : MVT::fp_vector_valuetypes())
950 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2f32, Legal);
952 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
953 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
954 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
957 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE41()) {
958 for (MVT RoundedTy : {MVT::f32, MVT::f64, MVT::v4f32, MVT::v2f64}) {
959 setOperationAction(ISD::FFLOOR, RoundedTy, Legal);
960 setOperationAction(ISD::FCEIL, RoundedTy, Legal);
961 setOperationAction(ISD::FTRUNC, RoundedTy, Legal);
962 setOperationAction(ISD::FRINT, RoundedTy, Legal);
963 setOperationAction(ISD::FNEARBYINT, RoundedTy, Legal);
966 setOperationAction(ISD::SMAX, MVT::v16i8, Legal);
967 setOperationAction(ISD::SMAX, MVT::v4i32, Legal);
968 setOperationAction(ISD::UMAX, MVT::v8i16, Legal);
969 setOperationAction(ISD::UMAX, MVT::v4i32, Legal);
970 setOperationAction(ISD::SMIN, MVT::v16i8, Legal);
971 setOperationAction(ISD::SMIN, MVT::v4i32, Legal);
972 setOperationAction(ISD::UMIN, MVT::v8i16, Legal);
973 setOperationAction(ISD::UMIN, MVT::v4i32, Legal);
975 // FIXME: Do we need to handle scalar-to-vector here?
976 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
978 // We directly match byte blends in the backend as they match the VSELECT
980 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
982 // SSE41 brings specific instructions for doing vector sign extend even in
983 // cases where we don't have SRA.
984 for (MVT VT : MVT::integer_vector_valuetypes()) {
985 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i8, Custom);
986 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i16, Custom);
987 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i32, Custom);
990 // SSE41 also has vector sign/zero extending loads, PMOV[SZ]X
991 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
992 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
993 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
994 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
995 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
996 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
998 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
999 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
1000 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
1001 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
1002 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
1003 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
1005 // i8 and i16 vectors are custom because the source register and source
1006 // source memory operand types are not the same width. f32 vectors are
1007 // custom since the immediate controlling the insert encodes additional
1009 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1010 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1011 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1012 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1014 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1015 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1016 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1017 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1019 // FIXME: these should be Legal, but that's only for the case where
1020 // the index is constant. For now custom expand to deal with that.
1021 if (Subtarget->is64Bit()) {
1022 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1023 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1027 if (Subtarget->hasSSE2()) {
1028 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v2i64, Custom);
1029 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v4i32, Custom);
1030 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v8i16, Custom);
1032 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1033 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1035 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1036 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1038 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1039 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1041 // In the customized shift lowering, the legal cases in AVX2 will be
1043 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1044 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1046 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1047 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1049 setOperationAction(ISD::SRA, MVT::v2i64, Custom);
1050 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1053 if (Subtarget->hasXOP()) {
1054 setOperationAction(ISD::ROTL, MVT::v16i8, Custom);
1055 setOperationAction(ISD::ROTL, MVT::v8i16, Custom);
1056 setOperationAction(ISD::ROTL, MVT::v4i32, Custom);
1057 setOperationAction(ISD::ROTL, MVT::v2i64, Custom);
1058 setOperationAction(ISD::ROTL, MVT::v32i8, Custom);
1059 setOperationAction(ISD::ROTL, MVT::v16i16, Custom);
1060 setOperationAction(ISD::ROTL, MVT::v8i32, Custom);
1061 setOperationAction(ISD::ROTL, MVT::v4i64, Custom);
1064 if (!Subtarget->useSoftFloat() && Subtarget->hasFp256()) {
1065 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1066 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1067 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1068 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1069 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1070 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1072 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1073 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1074 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1076 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1077 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1078 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1079 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1080 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1081 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1082 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1083 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1084 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1085 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1086 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1087 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1089 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1090 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1091 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1092 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1093 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1094 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1095 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1096 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1097 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1098 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1099 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1100 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1102 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1103 // even though v8i16 is a legal type.
1104 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1105 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1106 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1108 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1109 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1110 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1112 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1113 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1115 for (MVT VT : MVT::fp_vector_valuetypes())
1116 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4f32, Legal);
1118 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1119 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1121 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1122 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1124 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1125 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1127 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1128 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1129 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1130 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1132 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1133 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1134 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1136 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1137 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1138 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1139 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1140 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1141 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1142 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1143 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1144 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1145 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1146 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1147 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1149 setOperationAction(ISD::CTPOP, MVT::v32i8, Custom);
1150 setOperationAction(ISD::CTPOP, MVT::v16i16, Custom);
1151 setOperationAction(ISD::CTPOP, MVT::v8i32, Custom);
1152 setOperationAction(ISD::CTPOP, MVT::v4i64, Custom);
1154 setOperationAction(ISD::CTTZ, MVT::v32i8, Custom);
1155 setOperationAction(ISD::CTTZ, MVT::v16i16, Custom);
1156 setOperationAction(ISD::CTTZ, MVT::v8i32, Custom);
1157 setOperationAction(ISD::CTTZ, MVT::v4i64, Custom);
1158 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v32i8, Custom);
1159 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i16, Custom);
1160 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i32, Custom);
1161 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i64, Custom);
1163 if (Subtarget->hasAnyFMA()) {
1164 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1165 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1166 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1167 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1168 setOperationAction(ISD::FMA, MVT::f32, Legal);
1169 setOperationAction(ISD::FMA, MVT::f64, Legal);
1172 if (Subtarget->hasInt256()) {
1173 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1174 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1175 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1176 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1178 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1179 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1180 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1181 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1183 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1184 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1185 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1186 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1188 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1189 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1190 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1191 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1193 setOperationAction(ISD::SMAX, MVT::v32i8, Legal);
1194 setOperationAction(ISD::SMAX, MVT::v16i16, Legal);
1195 setOperationAction(ISD::SMAX, MVT::v8i32, Legal);
1196 setOperationAction(ISD::UMAX, MVT::v32i8, Legal);
1197 setOperationAction(ISD::UMAX, MVT::v16i16, Legal);
1198 setOperationAction(ISD::UMAX, MVT::v8i32, Legal);
1199 setOperationAction(ISD::SMIN, MVT::v32i8, Legal);
1200 setOperationAction(ISD::SMIN, MVT::v16i16, Legal);
1201 setOperationAction(ISD::SMIN, MVT::v8i32, Legal);
1202 setOperationAction(ISD::UMIN, MVT::v32i8, Legal);
1203 setOperationAction(ISD::UMIN, MVT::v16i16, Legal);
1204 setOperationAction(ISD::UMIN, MVT::v8i32, Legal);
1206 // The custom lowering for UINT_TO_FP for v8i32 becomes interesting
1207 // when we have a 256bit-wide blend with immediate.
1208 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Custom);
1210 // AVX2 also has wider vector sign/zero extending loads, VPMOV[SZ]X
1211 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1212 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1213 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1214 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1215 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1216 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1218 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1219 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1220 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1221 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1222 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1223 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1225 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1226 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1227 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1228 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1230 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1231 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1232 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1233 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1235 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1236 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1237 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1238 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1240 setOperationAction(ISD::SMAX, MVT::v32i8, Custom);
1241 setOperationAction(ISD::SMAX, MVT::v16i16, Custom);
1242 setOperationAction(ISD::SMAX, MVT::v8i32, Custom);
1243 setOperationAction(ISD::UMAX, MVT::v32i8, Custom);
1244 setOperationAction(ISD::UMAX, MVT::v16i16, Custom);
1245 setOperationAction(ISD::UMAX, MVT::v8i32, Custom);
1246 setOperationAction(ISD::SMIN, MVT::v32i8, Custom);
1247 setOperationAction(ISD::SMIN, MVT::v16i16, Custom);
1248 setOperationAction(ISD::SMIN, MVT::v8i32, Custom);
1249 setOperationAction(ISD::UMIN, MVT::v32i8, Custom);
1250 setOperationAction(ISD::UMIN, MVT::v16i16, Custom);
1251 setOperationAction(ISD::UMIN, MVT::v8i32, Custom);
1254 // In the customized shift lowering, the legal cases in AVX2 will be
1256 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1257 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1259 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1260 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1262 setOperationAction(ISD::SRA, MVT::v4i64, Custom);
1263 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1265 // Custom lower several nodes for 256-bit types.
1266 for (MVT VT : MVT::vector_valuetypes()) {
1267 if (VT.getScalarSizeInBits() >= 32) {
1268 setOperationAction(ISD::MLOAD, VT, Legal);
1269 setOperationAction(ISD::MSTORE, VT, Legal);
1271 // Extract subvector is special because the value type
1272 // (result) is 128-bit but the source is 256-bit wide.
1273 if (VT.is128BitVector()) {
1274 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1276 // Do not attempt to custom lower other non-256-bit vectors
1277 if (!VT.is256BitVector())
1280 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1281 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1282 setOperationAction(ISD::VSELECT, VT, Custom);
1283 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1284 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1285 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1286 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1287 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1290 if (Subtarget->hasInt256())
1291 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1293 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1294 for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32 }) {
1295 setOperationAction(ISD::AND, VT, Promote);
1296 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1297 setOperationAction(ISD::OR, VT, Promote);
1298 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1299 setOperationAction(ISD::XOR, VT, Promote);
1300 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1301 setOperationAction(ISD::LOAD, VT, Promote);
1302 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1303 setOperationAction(ISD::SELECT, VT, Promote);
1304 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1308 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512()) {
1309 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1310 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1311 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1312 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1314 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1315 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1316 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1318 for (MVT VT : MVT::fp_vector_valuetypes())
1319 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8f32, Legal);
1321 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i32, MVT::v16i8, Legal);
1322 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i32, MVT::v16i8, Legal);
1323 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i32, MVT::v16i16, Legal);
1324 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i32, MVT::v16i16, Legal);
1325 setLoadExtAction(ISD::ZEXTLOAD, MVT::v32i16, MVT::v32i8, Legal);
1326 setLoadExtAction(ISD::SEXTLOAD, MVT::v32i16, MVT::v32i8, Legal);
1327 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i8, Legal);
1328 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i8, Legal);
1329 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i16, Legal);
1330 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i16, Legal);
1331 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i32, Legal);
1332 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i32, Legal);
1334 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1335 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1336 setOperationAction(ISD::SELECT_CC, MVT::i1, Expand);
1337 setOperationAction(ISD::XOR, MVT::i1, Legal);
1338 setOperationAction(ISD::OR, MVT::i1, Legal);
1339 setOperationAction(ISD::AND, MVT::i1, Legal);
1340 setOperationAction(ISD::SUB, MVT::i1, Custom);
1341 setOperationAction(ISD::ADD, MVT::i1, Custom);
1342 setOperationAction(ISD::MUL, MVT::i1, Custom);
1343 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1344 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1345 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1346 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1347 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1349 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1350 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1351 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1352 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1353 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1354 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1355 setOperationAction(ISD::FABS, MVT::v16f32, Custom);
1357 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1358 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1359 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1360 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1361 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1362 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1363 setOperationAction(ISD::FABS, MVT::v8f64, Custom);
1364 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1365 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1367 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1368 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1369 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1370 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1371 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1372 setOperationAction(ISD::SINT_TO_FP, MVT::v8i1, Custom);
1373 setOperationAction(ISD::SINT_TO_FP, MVT::v16i1, Custom);
1374 setOperationAction(ISD::SINT_TO_FP, MVT::v16i8, Promote);
1375 setOperationAction(ISD::SINT_TO_FP, MVT::v16i16, Promote);
1376 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1377 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1378 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1379 setOperationAction(ISD::UINT_TO_FP, MVT::v16i8, Custom);
1380 setOperationAction(ISD::UINT_TO_FP, MVT::v16i16, Custom);
1381 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1382 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1384 setTruncStoreAction(MVT::v8i64, MVT::v8i8, Legal);
1385 setTruncStoreAction(MVT::v8i64, MVT::v8i16, Legal);
1386 setTruncStoreAction(MVT::v8i64, MVT::v8i32, Legal);
1387 setTruncStoreAction(MVT::v16i32, MVT::v16i8, Legal);
1388 setTruncStoreAction(MVT::v16i32, MVT::v16i16, Legal);
1389 if (Subtarget->hasVLX()){
1390 setTruncStoreAction(MVT::v4i64, MVT::v4i8, Legal);
1391 setTruncStoreAction(MVT::v4i64, MVT::v4i16, Legal);
1392 setTruncStoreAction(MVT::v4i64, MVT::v4i32, Legal);
1393 setTruncStoreAction(MVT::v8i32, MVT::v8i8, Legal);
1394 setTruncStoreAction(MVT::v8i32, MVT::v8i16, Legal);
1396 setTruncStoreAction(MVT::v2i64, MVT::v2i8, Legal);
1397 setTruncStoreAction(MVT::v2i64, MVT::v2i16, Legal);
1398 setTruncStoreAction(MVT::v2i64, MVT::v2i32, Legal);
1399 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Legal);
1400 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Legal);
1402 setOperationAction(ISD::MLOAD, MVT::v8i32, Custom);
1403 setOperationAction(ISD::MLOAD, MVT::v8f32, Custom);
1404 setOperationAction(ISD::MSTORE, MVT::v8i32, Custom);
1405 setOperationAction(ISD::MSTORE, MVT::v8f32, Custom);
1407 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1408 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1409 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1410 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i1, Custom);
1411 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i1, Custom);
1412 if (Subtarget->hasDQI()) {
1413 setOperationAction(ISD::TRUNCATE, MVT::v2i1, Custom);
1414 setOperationAction(ISD::TRUNCATE, MVT::v4i1, Custom);
1416 setOperationAction(ISD::SINT_TO_FP, MVT::v8i64, Legal);
1417 setOperationAction(ISD::UINT_TO_FP, MVT::v8i64, Legal);
1418 setOperationAction(ISD::FP_TO_SINT, MVT::v8i64, Legal);
1419 setOperationAction(ISD::FP_TO_UINT, MVT::v8i64, Legal);
1420 if (Subtarget->hasVLX()) {
1421 setOperationAction(ISD::SINT_TO_FP, MVT::v4i64, Legal);
1422 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
1423 setOperationAction(ISD::UINT_TO_FP, MVT::v4i64, Legal);
1424 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
1425 setOperationAction(ISD::FP_TO_SINT, MVT::v4i64, Legal);
1426 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
1427 setOperationAction(ISD::FP_TO_UINT, MVT::v4i64, Legal);
1428 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
1431 if (Subtarget->hasVLX()) {
1432 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1433 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1434 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1435 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1436 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1437 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1438 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1439 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1441 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1442 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1443 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1444 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1445 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1446 setOperationAction(ISD::ANY_EXTEND, MVT::v16i32, Custom);
1447 setOperationAction(ISD::ANY_EXTEND, MVT::v8i64, Custom);
1448 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1449 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1450 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1451 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1452 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1453 if (Subtarget->hasDQI()) {
1454 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i32, Custom);
1455 setOperationAction(ISD::SIGN_EXTEND, MVT::v2i64, Custom);
1457 setOperationAction(ISD::FFLOOR, MVT::v16f32, Legal);
1458 setOperationAction(ISD::FFLOOR, MVT::v8f64, Legal);
1459 setOperationAction(ISD::FCEIL, MVT::v16f32, Legal);
1460 setOperationAction(ISD::FCEIL, MVT::v8f64, Legal);
1461 setOperationAction(ISD::FTRUNC, MVT::v16f32, Legal);
1462 setOperationAction(ISD::FTRUNC, MVT::v8f64, Legal);
1463 setOperationAction(ISD::FRINT, MVT::v16f32, Legal);
1464 setOperationAction(ISD::FRINT, MVT::v8f64, Legal);
1465 setOperationAction(ISD::FNEARBYINT, MVT::v16f32, Legal);
1466 setOperationAction(ISD::FNEARBYINT, MVT::v8f64, Legal);
1468 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1469 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1470 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1471 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1472 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Custom);
1474 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1475 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1477 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1479 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1480 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1481 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v16i1, Custom);
1482 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1483 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1484 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1485 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1486 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1487 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1488 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1489 setOperationAction(ISD::SELECT, MVT::v16i1, Custom);
1490 setOperationAction(ISD::SELECT, MVT::v8i1, Custom);
1492 setOperationAction(ISD::SMAX, MVT::v16i32, Legal);
1493 setOperationAction(ISD::SMAX, MVT::v8i64, Legal);
1494 setOperationAction(ISD::UMAX, MVT::v16i32, Legal);
1495 setOperationAction(ISD::UMAX, MVT::v8i64, Legal);
1496 setOperationAction(ISD::SMIN, MVT::v16i32, Legal);
1497 setOperationAction(ISD::SMIN, MVT::v8i64, Legal);
1498 setOperationAction(ISD::UMIN, MVT::v16i32, Legal);
1499 setOperationAction(ISD::UMIN, MVT::v8i64, Legal);
1501 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1502 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1504 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1505 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1507 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1509 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1510 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1512 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1513 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1515 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1516 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1518 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1519 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1520 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1521 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1522 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1523 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1525 if (Subtarget->hasCDI()) {
1526 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1527 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1528 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i64, Legal);
1529 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v16i32, Legal);
1531 setOperationAction(ISD::CTLZ, MVT::v8i16, Custom);
1532 setOperationAction(ISD::CTLZ, MVT::v16i8, Custom);
1533 setOperationAction(ISD::CTLZ, MVT::v16i16, Custom);
1534 setOperationAction(ISD::CTLZ, MVT::v32i8, Custom);
1535 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i16, Custom);
1536 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v16i8, Custom);
1537 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v16i16, Custom);
1538 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v32i8, Custom);
1540 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i64, Custom);
1541 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i32, Custom);
1543 if (Subtarget->hasVLX()) {
1544 setOperationAction(ISD::CTLZ, MVT::v4i64, Legal);
1545 setOperationAction(ISD::CTLZ, MVT::v8i32, Legal);
1546 setOperationAction(ISD::CTLZ, MVT::v2i64, Legal);
1547 setOperationAction(ISD::CTLZ, MVT::v4i32, Legal);
1548 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i64, Legal);
1549 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i32, Legal);
1550 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v2i64, Legal);
1551 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i32, Legal);
1553 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i64, Custom);
1554 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i32, Custom);
1555 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v2i64, Custom);
1556 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i32, Custom);
1558 setOperationAction(ISD::CTLZ, MVT::v4i64, Custom);
1559 setOperationAction(ISD::CTLZ, MVT::v8i32, Custom);
1560 setOperationAction(ISD::CTLZ, MVT::v2i64, Custom);
1561 setOperationAction(ISD::CTLZ, MVT::v4i32, Custom);
1562 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i64, Custom);
1563 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i32, Custom);
1564 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v2i64, Custom);
1565 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i32, Custom);
1567 } // Subtarget->hasCDI()
1569 if (Subtarget->hasDQI()) {
1570 setOperationAction(ISD::MUL, MVT::v2i64, Legal);
1571 setOperationAction(ISD::MUL, MVT::v4i64, Legal);
1572 setOperationAction(ISD::MUL, MVT::v8i64, Legal);
1574 // Custom lower several nodes.
1575 for (MVT VT : MVT::vector_valuetypes()) {
1576 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1578 setOperationAction(ISD::AND, VT, Legal);
1579 setOperationAction(ISD::OR, VT, Legal);
1580 setOperationAction(ISD::XOR, VT, Legal);
1582 if ((VT.is128BitVector() || VT.is256BitVector()) && EltSize >= 32) {
1583 setOperationAction(ISD::MGATHER, VT, Custom);
1584 setOperationAction(ISD::MSCATTER, VT, Custom);
1586 // Extract subvector is special because the value type
1587 // (result) is 256/128-bit but the source is 512-bit wide.
1588 if (VT.is128BitVector() || VT.is256BitVector()) {
1589 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1591 if (VT.getVectorElementType() == MVT::i1)
1592 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1594 // Do not attempt to custom lower other non-512-bit vectors
1595 if (!VT.is512BitVector())
1598 if (EltSize >= 32) {
1599 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1600 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1601 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1602 setOperationAction(ISD::VSELECT, VT, Legal);
1603 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1604 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1605 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1606 setOperationAction(ISD::MLOAD, VT, Legal);
1607 setOperationAction(ISD::MSTORE, VT, Legal);
1608 setOperationAction(ISD::MGATHER, VT, Legal);
1609 setOperationAction(ISD::MSCATTER, VT, Custom);
1612 for (auto VT : { MVT::v64i8, MVT::v32i16, MVT::v16i32 }) {
1613 setOperationAction(ISD::SELECT, VT, Promote);
1614 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1618 if (!Subtarget->useSoftFloat() && Subtarget->hasBWI()) {
1619 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1620 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1622 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1623 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1625 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1626 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1627 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1628 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1629 setOperationAction(ISD::ADD, MVT::v32i16, Legal);
1630 setOperationAction(ISD::ADD, MVT::v64i8, Legal);
1631 setOperationAction(ISD::SUB, MVT::v32i16, Legal);
1632 setOperationAction(ISD::SUB, MVT::v64i8, Legal);
1633 setOperationAction(ISD::MUL, MVT::v32i16, Legal);
1634 setOperationAction(ISD::MULHS, MVT::v32i16, Legal);
1635 setOperationAction(ISD::MULHU, MVT::v32i16, Legal);
1636 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i1, Custom);
1637 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i1, Custom);
1638 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i16, Custom);
1639 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i8, Custom);
1640 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i1, Custom);
1641 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i1, Custom);
1642 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i16, Custom);
1643 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i8, Custom);
1644 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v32i16, Custom);
1645 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v64i8, Custom);
1646 setOperationAction(ISD::SELECT, MVT::v32i1, Custom);
1647 setOperationAction(ISD::SELECT, MVT::v64i1, Custom);
1648 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i8, Custom);
1649 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i8, Custom);
1650 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i16, Custom);
1651 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i16, Custom);
1652 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v32i16, Custom);
1653 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v64i8, Custom);
1654 setOperationAction(ISD::SIGN_EXTEND, MVT::v64i8, Custom);
1655 setOperationAction(ISD::ZERO_EXTEND, MVT::v64i8, Custom);
1656 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v32i1, Custom);
1657 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v64i1, Custom);
1658 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v32i16, Custom);
1659 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v64i8, Custom);
1660 setOperationAction(ISD::VSELECT, MVT::v32i16, Legal);
1661 setOperationAction(ISD::VSELECT, MVT::v64i8, Legal);
1662 setOperationAction(ISD::TRUNCATE, MVT::v32i1, Custom);
1663 setOperationAction(ISD::TRUNCATE, MVT::v64i1, Custom);
1664 setOperationAction(ISD::TRUNCATE, MVT::v32i8, Custom);
1665 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v32i1, Custom);
1666 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v64i1, Custom);
1668 setOperationAction(ISD::SMAX, MVT::v64i8, Legal);
1669 setOperationAction(ISD::SMAX, MVT::v32i16, Legal);
1670 setOperationAction(ISD::UMAX, MVT::v64i8, Legal);
1671 setOperationAction(ISD::UMAX, MVT::v32i16, Legal);
1672 setOperationAction(ISD::SMIN, MVT::v64i8, Legal);
1673 setOperationAction(ISD::SMIN, MVT::v32i16, Legal);
1674 setOperationAction(ISD::UMIN, MVT::v64i8, Legal);
1675 setOperationAction(ISD::UMIN, MVT::v32i16, Legal);
1677 setTruncStoreAction(MVT::v32i16, MVT::v32i8, Legal);
1678 setTruncStoreAction(MVT::v16i16, MVT::v16i8, Legal);
1679 if (Subtarget->hasVLX())
1680 setTruncStoreAction(MVT::v8i16, MVT::v8i8, Legal);
1682 if (Subtarget->hasCDI()) {
1683 setOperationAction(ISD::CTLZ, MVT::v32i16, Custom);
1684 setOperationAction(ISD::CTLZ, MVT::v64i8, Custom);
1685 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v32i16, Custom);
1686 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v64i8, Custom);
1689 for (auto VT : { MVT::v64i8, MVT::v32i16 }) {
1690 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1691 setOperationAction(ISD::VSELECT, VT, Legal);
1695 if (!Subtarget->useSoftFloat() && Subtarget->hasVLX()) {
1696 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1697 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1699 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1700 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1701 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i1, Custom);
1702 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1703 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Custom);
1704 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v4i1, Custom);
1705 setOperationAction(ISD::SELECT, MVT::v4i1, Custom);
1706 setOperationAction(ISD::SELECT, MVT::v2i1, Custom);
1707 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i1, Custom);
1708 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i1, Custom);
1709 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i1, Custom);
1710 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i1, Custom);
1712 setOperationAction(ISD::AND, MVT::v8i32, Legal);
1713 setOperationAction(ISD::OR, MVT::v8i32, Legal);
1714 setOperationAction(ISD::XOR, MVT::v8i32, Legal);
1715 setOperationAction(ISD::AND, MVT::v4i32, Legal);
1716 setOperationAction(ISD::OR, MVT::v4i32, Legal);
1717 setOperationAction(ISD::XOR, MVT::v4i32, Legal);
1718 setOperationAction(ISD::SRA, MVT::v2i64, Custom);
1719 setOperationAction(ISD::SRA, MVT::v4i64, Custom);
1721 setOperationAction(ISD::SMAX, MVT::v2i64, Legal);
1722 setOperationAction(ISD::SMAX, MVT::v4i64, Legal);
1723 setOperationAction(ISD::UMAX, MVT::v2i64, Legal);
1724 setOperationAction(ISD::UMAX, MVT::v4i64, Legal);
1725 setOperationAction(ISD::SMIN, MVT::v2i64, Legal);
1726 setOperationAction(ISD::SMIN, MVT::v4i64, Legal);
1727 setOperationAction(ISD::UMIN, MVT::v2i64, Legal);
1728 setOperationAction(ISD::UMIN, MVT::v4i64, Legal);
1731 // We want to custom lower some of our intrinsics.
1732 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1733 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1734 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1735 if (!Subtarget->is64Bit()) {
1736 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1737 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom);
1740 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1741 // handle type legalization for these operations here.
1743 // FIXME: We really should do custom legalization for addition and
1744 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1745 // than generic legalization for 64-bit multiplication-with-overflow, though.
1746 for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
1747 if (VT == MVT::i64 && !Subtarget->is64Bit())
1749 // Add/Sub/Mul with overflow operations are custom lowered.
1750 setOperationAction(ISD::SADDO, VT, Custom);
1751 setOperationAction(ISD::UADDO, VT, Custom);
1752 setOperationAction(ISD::SSUBO, VT, Custom);
1753 setOperationAction(ISD::USUBO, VT, Custom);
1754 setOperationAction(ISD::SMULO, VT, Custom);
1755 setOperationAction(ISD::UMULO, VT, Custom);
1758 if (!Subtarget->is64Bit()) {
1759 // These libcalls are not available in 32-bit.
1760 setLibcallName(RTLIB::SHL_I128, nullptr);
1761 setLibcallName(RTLIB::SRL_I128, nullptr);
1762 setLibcallName(RTLIB::SRA_I128, nullptr);
1765 // Combine sin / cos into one node or libcall if possible.
1766 if (Subtarget->hasSinCos()) {
1767 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1768 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1769 if (Subtarget->isTargetDarwin()) {
1770 // For MacOSX, we don't want the normal expansion of a libcall to sincos.
1771 // We want to issue a libcall to __sincos_stret to avoid memory traffic.
1772 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1773 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1777 if (Subtarget->isTargetWin64()) {
1778 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1779 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1780 setOperationAction(ISD::SREM, MVT::i128, Custom);
1781 setOperationAction(ISD::UREM, MVT::i128, Custom);
1782 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1783 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1786 // We have target-specific dag combine patterns for the following nodes:
1787 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1788 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1789 setTargetDAGCombine(ISD::BITCAST);
1790 setTargetDAGCombine(ISD::VSELECT);
1791 setTargetDAGCombine(ISD::SELECT);
1792 setTargetDAGCombine(ISD::SHL);
1793 setTargetDAGCombine(ISD::SRA);
1794 setTargetDAGCombine(ISD::SRL);
1795 setTargetDAGCombine(ISD::OR);
1796 setTargetDAGCombine(ISD::AND);
1797 setTargetDAGCombine(ISD::ADD);
1798 setTargetDAGCombine(ISD::FADD);
1799 setTargetDAGCombine(ISD::FSUB);
1800 setTargetDAGCombine(ISD::FNEG);
1801 setTargetDAGCombine(ISD::FMA);
1802 setTargetDAGCombine(ISD::FMAXNUM);
1803 setTargetDAGCombine(ISD::SUB);
1804 setTargetDAGCombine(ISD::LOAD);
1805 setTargetDAGCombine(ISD::MLOAD);
1806 setTargetDAGCombine(ISD::STORE);
1807 setTargetDAGCombine(ISD::MSTORE);
1808 setTargetDAGCombine(ISD::TRUNCATE);
1809 setTargetDAGCombine(ISD::ZERO_EXTEND);
1810 setTargetDAGCombine(ISD::ANY_EXTEND);
1811 setTargetDAGCombine(ISD::SIGN_EXTEND);
1812 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1813 setTargetDAGCombine(ISD::SINT_TO_FP);
1814 setTargetDAGCombine(ISD::UINT_TO_FP);
1815 setTargetDAGCombine(ISD::SETCC);
1816 setTargetDAGCombine(ISD::BUILD_VECTOR);
1817 setTargetDAGCombine(ISD::MUL);
1818 setTargetDAGCombine(ISD::XOR);
1819 setTargetDAGCombine(ISD::MSCATTER);
1820 setTargetDAGCombine(ISD::MGATHER);
1822 computeRegisterProperties(Subtarget->getRegisterInfo());
1824 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1825 MaxStoresPerMemsetOptSize = 8;
1826 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1827 MaxStoresPerMemcpyOptSize = 4;
1828 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1829 MaxStoresPerMemmoveOptSize = 4;
1830 setPrefLoopAlignment(4); // 2^4 bytes.
1832 // A predictable cmov does not hurt on an in-order CPU.
1833 // FIXME: Use a CPU attribute to trigger this, not a CPU model.
1834 PredictableSelectIsExpensive = !Subtarget->isAtom();
1835 EnableExtLdPromotion = true;
1836 setPrefFunctionAlignment(4); // 2^4 bytes.
1838 verifyIntrinsicTables();
1841 // This has so far only been implemented for 64-bit MachO.
1842 bool X86TargetLowering::useLoadStackGuardNode() const {
1843 return Subtarget->isTargetMachO() && Subtarget->is64Bit();
1846 TargetLoweringBase::LegalizeTypeAction
1847 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1848 if (ExperimentalVectorWideningLegalization &&
1849 VT.getVectorNumElements() != 1 &&
1850 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1851 return TypeWidenVector;
1853 return TargetLoweringBase::getPreferredVectorAction(VT);
1856 EVT X86TargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,
1859 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1861 if (VT.isSimple()) {
1862 MVT VVT = VT.getSimpleVT();
1863 const unsigned NumElts = VVT.getVectorNumElements();
1864 const MVT EltVT = VVT.getVectorElementType();
1865 if (VVT.is512BitVector()) {
1866 if (Subtarget->hasAVX512())
1867 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1868 EltVT == MVT::f32 || EltVT == MVT::f64)
1870 case 8: return MVT::v8i1;
1871 case 16: return MVT::v16i1;
1873 if (Subtarget->hasBWI())
1874 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1876 case 32: return MVT::v32i1;
1877 case 64: return MVT::v64i1;
1881 if (VVT.is256BitVector() || VVT.is128BitVector()) {
1882 if (Subtarget->hasVLX())
1883 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1884 EltVT == MVT::f32 || EltVT == MVT::f64)
1886 case 2: return MVT::v2i1;
1887 case 4: return MVT::v4i1;
1888 case 8: return MVT::v8i1;
1890 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1891 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1893 case 8: return MVT::v8i1;
1894 case 16: return MVT::v16i1;
1895 case 32: return MVT::v32i1;
1900 return VT.changeVectorElementTypeToInteger();
1903 /// Helper for getByValTypeAlignment to determine
1904 /// the desired ByVal argument alignment.
1905 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1908 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1909 if (VTy->getBitWidth() == 128)
1911 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1912 unsigned EltAlign = 0;
1913 getMaxByValAlign(ATy->getElementType(), EltAlign);
1914 if (EltAlign > MaxAlign)
1915 MaxAlign = EltAlign;
1916 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1917 for (auto *EltTy : STy->elements()) {
1918 unsigned EltAlign = 0;
1919 getMaxByValAlign(EltTy, EltAlign);
1920 if (EltAlign > MaxAlign)
1921 MaxAlign = EltAlign;
1928 /// Return the desired alignment for ByVal aggregate
1929 /// function arguments in the caller parameter area. For X86, aggregates
1930 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1931 /// are at 4-byte boundaries.
1932 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty,
1933 const DataLayout &DL) const {
1934 if (Subtarget->is64Bit()) {
1935 // Max of 8 and alignment of type.
1936 unsigned TyAlign = DL.getABITypeAlignment(Ty);
1943 if (Subtarget->hasSSE1())
1944 getMaxByValAlign(Ty, Align);
1948 /// Returns the target specific optimal type for load
1949 /// and store operations as a result of memset, memcpy, and memmove
1950 /// lowering. If DstAlign is zero that means it's safe to destination
1951 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1952 /// means there isn't a need to check it against alignment requirement,
1953 /// probably because the source does not need to be loaded. If 'IsMemset' is
1954 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1955 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1956 /// source is constant so it does not need to be loaded.
1957 /// It returns EVT::Other if the type should be determined using generic
1958 /// target-independent logic.
1960 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1961 unsigned DstAlign, unsigned SrcAlign,
1962 bool IsMemset, bool ZeroMemset,
1964 MachineFunction &MF) const {
1965 const Function *F = MF.getFunction();
1966 if ((!IsMemset || ZeroMemset) &&
1967 !F->hasFnAttribute(Attribute::NoImplicitFloat)) {
1969 (!Subtarget->isUnalignedMem16Slow() ||
1970 ((DstAlign == 0 || DstAlign >= 16) &&
1971 (SrcAlign == 0 || SrcAlign >= 16)))) {
1973 // FIXME: Check if unaligned 32-byte accesses are slow.
1974 if (Subtarget->hasInt256())
1976 if (Subtarget->hasFp256())
1979 if (Subtarget->hasSSE2())
1981 if (Subtarget->hasSSE1())
1983 } else if (!MemcpyStrSrc && Size >= 8 &&
1984 !Subtarget->is64Bit() &&
1985 Subtarget->hasSSE2()) {
1986 // Do not use f64 to lower memcpy if source is string constant. It's
1987 // better to use i32 to avoid the loads.
1991 // This is a compromise. If we reach here, unaligned accesses may be slow on
1992 // this target. However, creating smaller, aligned accesses could be even
1993 // slower and would certainly be a lot more code.
1994 if (Subtarget->is64Bit() && Size >= 8)
1999 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
2001 return X86ScalarSSEf32;
2002 else if (VT == MVT::f64)
2003 return X86ScalarSSEf64;
2008 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
2013 switch (VT.getSizeInBits()) {
2015 // 8-byte and under are always assumed to be fast.
2019 *Fast = !Subtarget->isUnalignedMem16Slow();
2022 *Fast = !Subtarget->isUnalignedMem32Slow();
2024 // TODO: What about AVX-512 (512-bit) accesses?
2027 // Misaligned accesses of any size are always allowed.
2031 /// Return the entry encoding for a jump table in the
2032 /// current function. The returned value is a member of the
2033 /// MachineJumpTableInfo::JTEntryKind enum.
2034 unsigned X86TargetLowering::getJumpTableEncoding() const {
2035 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
2037 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2038 Subtarget->isPICStyleGOT())
2039 return MachineJumpTableInfo::EK_Custom32;
2041 // Otherwise, use the normal jump table encoding heuristics.
2042 return TargetLowering::getJumpTableEncoding();
2045 bool X86TargetLowering::useSoftFloat() const {
2046 return Subtarget->useSoftFloat();
2050 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
2051 const MachineBasicBlock *MBB,
2052 unsigned uid,MCContext &Ctx) const{
2053 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
2054 Subtarget->isPICStyleGOT());
2055 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
2057 return MCSymbolRefExpr::create(MBB->getSymbol(),
2058 MCSymbolRefExpr::VK_GOTOFF, Ctx);
2061 /// Returns relocation base for the given PIC jumptable.
2062 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
2063 SelectionDAG &DAG) const {
2064 if (!Subtarget->is64Bit())
2065 // This doesn't have SDLoc associated with it, but is not really the
2066 // same as a Register.
2067 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(),
2068 getPointerTy(DAG.getDataLayout()));
2072 /// This returns the relocation base for the given PIC jumptable,
2073 /// the same as getPICJumpTableRelocBase, but as an MCExpr.
2074 const MCExpr *X86TargetLowering::
2075 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
2076 MCContext &Ctx) const {
2077 // X86-64 uses RIP relative addressing based on the jump table label.
2078 if (Subtarget->isPICStyleRIPRel())
2079 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
2081 // Otherwise, the reference is relative to the PIC base.
2082 return MCSymbolRefExpr::create(MF->getPICBaseSymbol(), Ctx);
2085 std::pair<const TargetRegisterClass *, uint8_t>
2086 X86TargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
2088 const TargetRegisterClass *RRC = nullptr;
2090 switch (VT.SimpleTy) {
2092 return TargetLowering::findRepresentativeClass(TRI, VT);
2093 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
2094 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
2097 RRC = &X86::VR64RegClass;
2099 case MVT::f32: case MVT::f64:
2100 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
2101 case MVT::v4f32: case MVT::v2f64:
2102 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
2104 RRC = &X86::VR128RegClass;
2107 return std::make_pair(RRC, Cost);
2110 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
2111 unsigned &Offset) const {
2112 if (!Subtarget->isTargetLinux())
2115 if (Subtarget->is64Bit()) {
2116 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
2118 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
2130 Value *X86TargetLowering::getSafeStackPointerLocation(IRBuilder<> &IRB) const {
2131 if (!Subtarget->isTargetAndroid())
2132 return TargetLowering::getSafeStackPointerLocation(IRB);
2134 // Android provides a fixed TLS slot for the SafeStack pointer. See the
2135 // definition of TLS_SLOT_SAFESTACK in
2136 // https://android.googlesource.com/platform/bionic/+/master/libc/private/bionic_tls.h
2137 unsigned AddressSpace, Offset;
2138 if (Subtarget->is64Bit()) {
2139 // %fs:0x48, unless we're using a Kernel code model, in which case it's %gs:
2141 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
2151 return ConstantExpr::getIntToPtr(
2152 ConstantInt::get(Type::getInt32Ty(IRB.getContext()), Offset),
2153 Type::getInt8PtrTy(IRB.getContext())->getPointerTo(AddressSpace));
2156 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
2157 unsigned DestAS) const {
2158 assert(SrcAS != DestAS && "Expected different address spaces!");
2160 return SrcAS < 256 && DestAS < 256;
2163 //===----------------------------------------------------------------------===//
2164 // Return Value Calling Convention Implementation
2165 //===----------------------------------------------------------------------===//
2167 #include "X86GenCallingConv.inc"
2169 bool X86TargetLowering::CanLowerReturn(
2170 CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
2171 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
2172 SmallVector<CCValAssign, 16> RVLocs;
2173 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
2174 return CCInfo.CheckReturn(Outs, RetCC_X86);
2177 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
2178 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
2183 X86TargetLowering::LowerReturn(SDValue Chain,
2184 CallingConv::ID CallConv, bool isVarArg,
2185 const SmallVectorImpl<ISD::OutputArg> &Outs,
2186 const SmallVectorImpl<SDValue> &OutVals,
2187 SDLoc dl, SelectionDAG &DAG) const {
2188 MachineFunction &MF = DAG.getMachineFunction();
2189 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2191 if (CallConv == CallingConv::X86_INTR && !Outs.empty())
2192 report_fatal_error("X86 interrupts may not return any value");
2194 SmallVector<CCValAssign, 16> RVLocs;
2195 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
2196 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
2199 SmallVector<SDValue, 6> RetOps;
2200 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
2201 // Operand #1 = Bytes To Pop
2202 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(), dl,
2205 // Copy the result values into the output registers.
2206 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2207 CCValAssign &VA = RVLocs[i];
2208 assert(VA.isRegLoc() && "Can only return in registers!");
2209 SDValue ValToCopy = OutVals[i];
2210 EVT ValVT = ValToCopy.getValueType();
2212 // Promote values to the appropriate types.
2213 if (VA.getLocInfo() == CCValAssign::SExt)
2214 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2215 else if (VA.getLocInfo() == CCValAssign::ZExt)
2216 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2217 else if (VA.getLocInfo() == CCValAssign::AExt) {
2218 if (ValVT.isVector() && ValVT.getVectorElementType() == MVT::i1)
2219 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2221 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2223 else if (VA.getLocInfo() == CCValAssign::BCvt)
2224 ValToCopy = DAG.getBitcast(VA.getLocVT(), ValToCopy);
2226 assert(VA.getLocInfo() != CCValAssign::FPExt &&
2227 "Unexpected FP-extend for return value.");
2229 // If this is x86-64, and we disabled SSE, we can't return FP values,
2230 // or SSE or MMX vectors.
2231 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
2232 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2233 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
2234 report_fatal_error("SSE register return with SSE disabled");
2236 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
2237 // llvm-gcc has never done it right and no one has noticed, so this
2238 // should be OK for now.
2239 if (ValVT == MVT::f64 &&
2240 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
2241 report_fatal_error("SSE2 register return with SSE2 disabled");
2243 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2244 // the RET instruction and handled by the FP Stackifier.
2245 if (VA.getLocReg() == X86::FP0 ||
2246 VA.getLocReg() == X86::FP1) {
2247 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2248 // change the value to the FP stack register class.
2249 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2250 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2251 RetOps.push_back(ValToCopy);
2252 // Don't emit a copytoreg.
2256 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2257 // which is returned in RAX / RDX.
2258 if (Subtarget->is64Bit()) {
2259 if (ValVT == MVT::x86mmx) {
2260 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2261 ValToCopy = DAG.getBitcast(MVT::i64, ValToCopy);
2262 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2264 // If we don't have SSE2 available, convert to v4f32 so the generated
2265 // register is legal.
2266 if (!Subtarget->hasSSE2())
2267 ValToCopy = DAG.getBitcast(MVT::v4f32, ValToCopy);
2272 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2273 Flag = Chain.getValue(1);
2274 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2277 // All x86 ABIs require that for returning structs by value we copy
2278 // the sret argument into %rax/%eax (depending on ABI) for the return.
2279 // We saved the argument into a virtual register in the entry block,
2280 // so now we copy the value out and into %rax/%eax.
2282 // Checking Function.hasStructRetAttr() here is insufficient because the IR
2283 // may not have an explicit sret argument. If FuncInfo.CanLowerReturn is
2284 // false, then an sret argument may be implicitly inserted in the SelDAG. In
2285 // either case FuncInfo->setSRetReturnReg() will have been called.
2286 if (unsigned SRetReg = FuncInfo->getSRetReturnReg()) {
2287 SDValue Val = DAG.getCopyFromReg(Chain, dl, SRetReg,
2288 getPointerTy(MF.getDataLayout()));
2291 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2292 X86::RAX : X86::EAX;
2293 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2294 Flag = Chain.getValue(1);
2296 // RAX/EAX now acts like a return value.
2298 DAG.getRegister(RetValReg, getPointerTy(DAG.getDataLayout())));
2301 RetOps[0] = Chain; // Update chain.
2303 // Add the flag if we have it.
2305 RetOps.push_back(Flag);
2307 X86ISD::NodeType opcode = X86ISD::RET_FLAG;
2308 if (CallConv == CallingConv::X86_INTR)
2309 opcode = X86ISD::IRET;
2310 return DAG.getNode(opcode, dl, MVT::Other, RetOps);
2313 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2314 if (N->getNumValues() != 1)
2316 if (!N->hasNUsesOfValue(1, 0))
2319 SDValue TCChain = Chain;
2320 SDNode *Copy = *N->use_begin();
2321 if (Copy->getOpcode() == ISD::CopyToReg) {
2322 // If the copy has a glue operand, we conservatively assume it isn't safe to
2323 // perform a tail call.
2324 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2326 TCChain = Copy->getOperand(0);
2327 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2330 bool HasRet = false;
2331 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2333 if (UI->getOpcode() != X86ISD::RET_FLAG)
2335 // If we are returning more than one value, we can definitely
2336 // not make a tail call see PR19530
2337 if (UI->getNumOperands() > 4)
2339 if (UI->getNumOperands() == 4 &&
2340 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2353 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2354 ISD::NodeType ExtendKind) const {
2356 // TODO: Is this also valid on 32-bit?
2357 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2358 ReturnMVT = MVT::i8;
2360 ReturnMVT = MVT::i32;
2362 EVT MinVT = getRegisterType(Context, ReturnMVT);
2363 return VT.bitsLT(MinVT) ? MinVT : VT;
2366 /// Lower the result values of a call into the
2367 /// appropriate copies out of appropriate physical registers.
2370 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2371 CallingConv::ID CallConv, bool isVarArg,
2372 const SmallVectorImpl<ISD::InputArg> &Ins,
2373 SDLoc dl, SelectionDAG &DAG,
2374 SmallVectorImpl<SDValue> &InVals) const {
2376 // Assign locations to each value returned by this call.
2377 SmallVector<CCValAssign, 16> RVLocs;
2378 bool Is64Bit = Subtarget->is64Bit();
2379 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2381 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2383 // Copy all of the result registers out of their specified physreg.
2384 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2385 CCValAssign &VA = RVLocs[i];
2386 EVT CopyVT = VA.getLocVT();
2388 // If this is x86-64, and we disabled SSE, we can't return FP values
2389 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64 || CopyVT == MVT::f128) &&
2390 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2391 report_fatal_error("SSE register return with SSE disabled");
2394 // If we prefer to use the value in xmm registers, copy it out as f80 and
2395 // use a truncate to move it from fp stack reg to xmm reg.
2396 bool RoundAfterCopy = false;
2397 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2398 isScalarFPTypeInSSEReg(VA.getValVT())) {
2400 RoundAfterCopy = (CopyVT != VA.getLocVT());
2403 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2404 CopyVT, InFlag).getValue(1);
2405 SDValue Val = Chain.getValue(0);
2408 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2409 // This truncation won't change the value.
2410 DAG.getIntPtrConstant(1, dl));
2412 if (VA.isExtInLoc() && VA.getValVT().getScalarType() == MVT::i1)
2413 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
2415 InFlag = Chain.getValue(2);
2416 InVals.push_back(Val);
2422 //===----------------------------------------------------------------------===//
2423 // C & StdCall & Fast Calling Convention implementation
2424 //===----------------------------------------------------------------------===//
2425 // StdCall calling convention seems to be standard for many Windows' API
2426 // routines and around. It differs from C calling convention just a little:
2427 // callee should clean up the stack, not caller. Symbols should be also
2428 // decorated in some fancy way :) It doesn't support any vector arguments.
2429 // For info on fast calling convention see Fast Calling Convention (tail call)
2430 // implementation LowerX86_32FastCCCallTo.
2432 /// CallIsStructReturn - Determines whether a call uses struct return
2434 enum StructReturnType {
2439 static StructReturnType
2440 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2442 return NotStructReturn;
2444 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2445 if (!Flags.isSRet())
2446 return NotStructReturn;
2447 if (Flags.isInReg())
2448 return RegStructReturn;
2449 return StackStructReturn;
2452 /// Determines whether a function uses struct return semantics.
2453 static StructReturnType
2454 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2456 return NotStructReturn;
2458 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2459 if (!Flags.isSRet())
2460 return NotStructReturn;
2461 if (Flags.isInReg())
2462 return RegStructReturn;
2463 return StackStructReturn;
2466 /// Make a copy of an aggregate at address specified by "Src" to address
2467 /// "Dst" with size and alignment information specified by the specific
2468 /// parameter attribute. The copy will be passed as a byval function parameter.
2470 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2471 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2473 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
2475 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2476 /*isVolatile*/false, /*AlwaysInline=*/true,
2477 /*isTailCall*/false,
2478 MachinePointerInfo(), MachinePointerInfo());
2481 /// Return true if the calling convention is one that we can guarantee TCO for.
2482 static bool canGuaranteeTCO(CallingConv::ID CC) {
2483 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2484 CC == CallingConv::HiPE || CC == CallingConv::HHVM);
2487 /// Return true if we might ever do TCO for calls with this calling convention.
2488 static bool mayTailCallThisCC(CallingConv::ID CC) {
2490 // C calling conventions:
2491 case CallingConv::C:
2492 case CallingConv::X86_64_Win64:
2493 case CallingConv::X86_64_SysV:
2494 // Callee pop conventions:
2495 case CallingConv::X86_ThisCall:
2496 case CallingConv::X86_StdCall:
2497 case CallingConv::X86_VectorCall:
2498 case CallingConv::X86_FastCall:
2501 return canGuaranteeTCO(CC);
2505 /// Return true if the function is being made into a tailcall target by
2506 /// changing its ABI.
2507 static bool shouldGuaranteeTCO(CallingConv::ID CC, bool GuaranteedTailCallOpt) {
2508 return GuaranteedTailCallOpt && canGuaranteeTCO(CC);
2511 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2513 CI->getParent()->getParent()->getFnAttribute("disable-tail-calls");
2514 if (!CI->isTailCall() || Attr.getValueAsString() == "true")
2518 CallingConv::ID CalleeCC = CS.getCallingConv();
2519 if (!mayTailCallThisCC(CalleeCC))
2526 X86TargetLowering::LowerMemArgument(SDValue Chain,
2527 CallingConv::ID CallConv,
2528 const SmallVectorImpl<ISD::InputArg> &Ins,
2529 SDLoc dl, SelectionDAG &DAG,
2530 const CCValAssign &VA,
2531 MachineFrameInfo *MFI,
2533 // Create the nodes corresponding to a load from this parameter slot.
2534 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2535 bool AlwaysUseMutable = shouldGuaranteeTCO(
2536 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2537 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2540 // If value is passed by pointer we have address passed instead of the value
2542 bool ExtendedInMem = VA.isExtInLoc() &&
2543 VA.getValVT().getScalarType() == MVT::i1;
2545 if (VA.getLocInfo() == CCValAssign::Indirect || ExtendedInMem)
2546 ValVT = VA.getLocVT();
2548 ValVT = VA.getValVT();
2550 // Calculate SP offset of interrupt parameter, re-arrange the slot normally
2551 // taken by a return address.
2553 if (CallConv == CallingConv::X86_INTR) {
2554 const X86Subtarget& Subtarget =
2555 static_cast<const X86Subtarget&>(DAG.getSubtarget());
2556 // X86 interrupts may take one or two arguments.
2557 // On the stack there will be no return address as in regular call.
2558 // Offset of last argument need to be set to -4/-8 bytes.
2559 // Where offset of the first argument out of two, should be set to 0 bytes.
2560 Offset = (Subtarget.is64Bit() ? 8 : 4) * ((i + 1) % Ins.size() - 1);
2563 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2564 // changed with more analysis.
2565 // In case of tail call optimization mark all arguments mutable. Since they
2566 // could be overwritten by lowering of arguments in case of a tail call.
2567 if (Flags.isByVal()) {
2568 unsigned Bytes = Flags.getByValSize();
2569 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2570 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2571 // Adjust SP offset of interrupt parameter.
2572 if (CallConv == CallingConv::X86_INTR) {
2573 MFI->setObjectOffset(FI, Offset);
2575 return DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
2577 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2578 VA.getLocMemOffset(), isImmutable);
2579 // Adjust SP offset of interrupt parameter.
2580 if (CallConv == CallingConv::X86_INTR) {
2581 MFI->setObjectOffset(FI, Offset);
2584 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
2585 SDValue Val = DAG.getLoad(
2586 ValVT, dl, Chain, FIN,
2587 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI), false,
2589 return ExtendedInMem ?
2590 DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val) : Val;
2594 // FIXME: Get this from tablegen.
2595 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2596 const X86Subtarget *Subtarget) {
2597 assert(Subtarget->is64Bit());
2599 if (Subtarget->isCallingConvWin64(CallConv)) {
2600 static const MCPhysReg GPR64ArgRegsWin64[] = {
2601 X86::RCX, X86::RDX, X86::R8, X86::R9
2603 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2606 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2607 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2609 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2612 // FIXME: Get this from tablegen.
2613 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2614 CallingConv::ID CallConv,
2615 const X86Subtarget *Subtarget) {
2616 assert(Subtarget->is64Bit());
2617 if (Subtarget->isCallingConvWin64(CallConv)) {
2618 // The XMM registers which might contain var arg parameters are shadowed
2619 // in their paired GPR. So we only need to save the GPR to their home
2621 // TODO: __vectorcall will change this.
2625 const Function *Fn = MF.getFunction();
2626 bool NoImplicitFloatOps = Fn->hasFnAttribute(Attribute::NoImplicitFloat);
2627 bool isSoftFloat = Subtarget->useSoftFloat();
2628 assert(!(isSoftFloat && NoImplicitFloatOps) &&
2629 "SSE register cannot be used when SSE is disabled!");
2630 if (isSoftFloat || NoImplicitFloatOps || !Subtarget->hasSSE1())
2631 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2635 static const MCPhysReg XMMArgRegs64Bit[] = {
2636 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2637 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2639 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2642 SDValue X86TargetLowering::LowerFormalArguments(
2643 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
2644 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG,
2645 SmallVectorImpl<SDValue> &InVals) const {
2646 MachineFunction &MF = DAG.getMachineFunction();
2647 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2648 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
2650 const Function* Fn = MF.getFunction();
2651 if (Fn->hasExternalLinkage() &&
2652 Subtarget->isTargetCygMing() &&
2653 Fn->getName() == "main")
2654 FuncInfo->setForceFramePointer(true);
2656 MachineFrameInfo *MFI = MF.getFrameInfo();
2657 bool Is64Bit = Subtarget->is64Bit();
2658 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2660 assert(!(isVarArg && canGuaranteeTCO(CallConv)) &&
2661 "Var args not supported with calling convention fastcc, ghc or hipe");
2663 if (CallConv == CallingConv::X86_INTR) {
2664 bool isLegal = Ins.size() == 1 ||
2665 (Ins.size() == 2 && ((Is64Bit && Ins[1].VT == MVT::i64) ||
2666 (!Is64Bit && Ins[1].VT == MVT::i32)));
2668 report_fatal_error("X86 interrupts may take one or two arguments");
2671 // Assign locations to all of the incoming arguments.
2672 SmallVector<CCValAssign, 16> ArgLocs;
2673 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2675 // Allocate shadow area for Win64
2677 CCInfo.AllocateStack(32, 8);
2679 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2681 unsigned LastVal = ~0U;
2683 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2684 CCValAssign &VA = ArgLocs[i];
2685 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2687 assert(VA.getValNo() != LastVal &&
2688 "Don't support value assigned to multiple locs yet");
2690 LastVal = VA.getValNo();
2692 if (VA.isRegLoc()) {
2693 EVT RegVT = VA.getLocVT();
2694 const TargetRegisterClass *RC;
2695 if (RegVT == MVT::i32)
2696 RC = &X86::GR32RegClass;
2697 else if (Is64Bit && RegVT == MVT::i64)
2698 RC = &X86::GR64RegClass;
2699 else if (RegVT == MVT::f32)
2700 RC = &X86::FR32RegClass;
2701 else if (RegVT == MVT::f64)
2702 RC = &X86::FR64RegClass;
2703 else if (RegVT == MVT::f128)
2704 RC = &X86::FR128RegClass;
2705 else if (RegVT.is512BitVector())
2706 RC = &X86::VR512RegClass;
2707 else if (RegVT.is256BitVector())
2708 RC = &X86::VR256RegClass;
2709 else if (RegVT.is128BitVector())
2710 RC = &X86::VR128RegClass;
2711 else if (RegVT == MVT::x86mmx)
2712 RC = &X86::VR64RegClass;
2713 else if (RegVT == MVT::i1)
2714 RC = &X86::VK1RegClass;
2715 else if (RegVT == MVT::v8i1)
2716 RC = &X86::VK8RegClass;
2717 else if (RegVT == MVT::v16i1)
2718 RC = &X86::VK16RegClass;
2719 else if (RegVT == MVT::v32i1)
2720 RC = &X86::VK32RegClass;
2721 else if (RegVT == MVT::v64i1)
2722 RC = &X86::VK64RegClass;
2724 llvm_unreachable("Unknown argument type!");
2726 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2727 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2729 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2730 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2732 if (VA.getLocInfo() == CCValAssign::SExt)
2733 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2734 DAG.getValueType(VA.getValVT()));
2735 else if (VA.getLocInfo() == CCValAssign::ZExt)
2736 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2737 DAG.getValueType(VA.getValVT()));
2738 else if (VA.getLocInfo() == CCValAssign::BCvt)
2739 ArgValue = DAG.getBitcast(VA.getValVT(), ArgValue);
2741 if (VA.isExtInLoc()) {
2742 // Handle MMX values passed in XMM regs.
2743 if (RegVT.isVector() && VA.getValVT().getScalarType() != MVT::i1)
2744 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2746 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2749 assert(VA.isMemLoc());
2750 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2753 // If value is passed via pointer - do a load.
2754 if (VA.getLocInfo() == CCValAssign::Indirect)
2755 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2756 MachinePointerInfo(), false, false, false, 0);
2758 InVals.push_back(ArgValue);
2761 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2762 // All x86 ABIs require that for returning structs by value we copy the
2763 // sret argument into %rax/%eax (depending on ABI) for the return. Save
2764 // the argument into a virtual register so that we can access it from the
2766 if (Ins[i].Flags.isSRet()) {
2767 unsigned Reg = FuncInfo->getSRetReturnReg();
2769 MVT PtrTy = getPointerTy(DAG.getDataLayout());
2770 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2771 FuncInfo->setSRetReturnReg(Reg);
2773 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2774 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2779 unsigned StackSize = CCInfo.getNextStackOffset();
2780 // Align stack specially for tail calls.
2781 if (shouldGuaranteeTCO(CallConv,
2782 MF.getTarget().Options.GuaranteedTailCallOpt))
2783 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2785 // If the function takes variable number of arguments, make a frame index for
2786 // the start of the first vararg value... for expansion of llvm.va_start. We
2787 // can skip this if there are no va_start calls.
2788 if (MFI->hasVAStart() &&
2789 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2790 CallConv != CallingConv::X86_ThisCall))) {
2791 FuncInfo->setVarArgsFrameIndex(
2792 MFI->CreateFixedObject(1, StackSize, true));
2795 // Figure out if XMM registers are in use.
2796 assert(!(Subtarget->useSoftFloat() &&
2797 Fn->hasFnAttribute(Attribute::NoImplicitFloat)) &&
2798 "SSE register cannot be used when SSE is disabled!");
2800 // 64-bit calling conventions support varargs and register parameters, so we
2801 // have to do extra work to spill them in the prologue.
2802 if (Is64Bit && isVarArg && MFI->hasVAStart()) {
2803 // Find the first unallocated argument registers.
2804 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2805 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2806 unsigned NumIntRegs = CCInfo.getFirstUnallocated(ArgGPRs);
2807 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(ArgXMMs);
2808 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2809 "SSE register cannot be used when SSE is disabled!");
2811 // Gather all the live in physical registers.
2812 SmallVector<SDValue, 6> LiveGPRs;
2813 SmallVector<SDValue, 8> LiveXMMRegs;
2815 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2816 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2818 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2820 if (!ArgXMMs.empty()) {
2821 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2822 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2823 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2824 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2825 LiveXMMRegs.push_back(
2826 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2831 // Get to the caller-allocated home save location. Add 8 to account
2832 // for the return address.
2833 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2834 FuncInfo->setRegSaveFrameIndex(
2835 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2836 // Fixup to set vararg frame on shadow area (4 x i64).
2838 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2840 // For X86-64, if there are vararg parameters that are passed via
2841 // registers, then we must store them to their spots on the stack so
2842 // they may be loaded by deferencing the result of va_next.
2843 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2844 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2845 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2846 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2849 // Store the integer parameter registers.
2850 SmallVector<SDValue, 8> MemOps;
2851 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2852 getPointerTy(DAG.getDataLayout()));
2853 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2854 for (SDValue Val : LiveGPRs) {
2855 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
2856 RSFIN, DAG.getIntPtrConstant(Offset, dl));
2858 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2859 MachinePointerInfo::getFixedStack(
2860 DAG.getMachineFunction(),
2861 FuncInfo->getRegSaveFrameIndex(), Offset),
2863 MemOps.push_back(Store);
2867 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2868 // Now store the XMM (fp + vector) parameter registers.
2869 SmallVector<SDValue, 12> SaveXMMOps;
2870 SaveXMMOps.push_back(Chain);
2871 SaveXMMOps.push_back(ALVal);
2872 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2873 FuncInfo->getRegSaveFrameIndex(), dl));
2874 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2875 FuncInfo->getVarArgsFPOffset(), dl));
2876 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2878 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2879 MVT::Other, SaveXMMOps));
2882 if (!MemOps.empty())
2883 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2886 if (isVarArg && MFI->hasMustTailInVarArgFunc()) {
2887 // Find the largest legal vector type.
2888 MVT VecVT = MVT::Other;
2889 // FIXME: Only some x86_32 calling conventions support AVX512.
2890 if (Subtarget->hasAVX512() &&
2891 (Is64Bit || (CallConv == CallingConv::X86_VectorCall ||
2892 CallConv == CallingConv::Intel_OCL_BI)))
2893 VecVT = MVT::v16f32;
2894 else if (Subtarget->hasAVX())
2896 else if (Subtarget->hasSSE2())
2899 // We forward some GPRs and some vector types.
2900 SmallVector<MVT, 2> RegParmTypes;
2901 MVT IntVT = Is64Bit ? MVT::i64 : MVT::i32;
2902 RegParmTypes.push_back(IntVT);
2903 if (VecVT != MVT::Other)
2904 RegParmTypes.push_back(VecVT);
2906 // Compute the set of forwarded registers. The rest are scratch.
2907 SmallVectorImpl<ForwardedRegister> &Forwards =
2908 FuncInfo->getForwardedMustTailRegParms();
2909 CCInfo.analyzeMustTailForwardedRegisters(Forwards, RegParmTypes, CC_X86);
2911 // Conservatively forward AL on x86_64, since it might be used for varargs.
2912 if (Is64Bit && !CCInfo.isAllocated(X86::AL)) {
2913 unsigned ALVReg = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2914 Forwards.push_back(ForwardedRegister(ALVReg, X86::AL, MVT::i8));
2917 // Copy all forwards from physical to virtual registers.
2918 for (ForwardedRegister &F : Forwards) {
2919 // FIXME: Can we use a less constrained schedule?
2920 SDValue RegVal = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2921 F.VReg = MF.getRegInfo().createVirtualRegister(getRegClassFor(F.VT));
2922 Chain = DAG.getCopyToReg(Chain, dl, F.VReg, RegVal);
2926 // Some CCs need callee pop.
2927 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2928 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2929 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2930 } else if (CallConv == CallingConv::X86_INTR && Ins.size() == 2) {
2931 // X86 interrupts must pop the error code if present
2932 FuncInfo->setBytesToPopOnReturn(Is64Bit ? 8 : 4);
2934 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2935 // If this is an sret function, the return should pop the hidden pointer.
2936 if (!Is64Bit && !canGuaranteeTCO(CallConv) &&
2937 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2938 argsAreStructReturn(Ins) == StackStructReturn)
2939 FuncInfo->setBytesToPopOnReturn(4);
2943 // RegSaveFrameIndex is X86-64 only.
2944 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2945 if (CallConv == CallingConv::X86_FastCall ||
2946 CallConv == CallingConv::X86_ThisCall)
2947 // fastcc functions can't have varargs.
2948 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2951 FuncInfo->setArgumentStackSize(StackSize);
2953 if (WinEHFuncInfo *EHInfo = MF.getWinEHFuncInfo()) {
2954 EHPersonality Personality = classifyEHPersonality(Fn->getPersonalityFn());
2955 if (Personality == EHPersonality::CoreCLR) {
2957 // TODO: Add a mechanism to frame lowering that will allow us to indicate
2958 // that we'd prefer this slot be allocated towards the bottom of the frame
2959 // (i.e. near the stack pointer after allocating the frame). Every
2960 // funclet needs a copy of this slot in its (mostly empty) frame, and the
2961 // offset from the bottom of this and each funclet's frame must be the
2962 // same, so the size of funclets' (mostly empty) frames is dictated by
2963 // how far this slot is from the bottom (since they allocate just enough
2964 // space to accomodate holding this slot at the correct offset).
2965 int PSPSymFI = MFI->CreateStackObject(8, 8, /*isSS=*/false);
2966 EHInfo->PSPSymFrameIdx = PSPSymFI;
2974 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2975 SDValue StackPtr, SDValue Arg,
2976 SDLoc dl, SelectionDAG &DAG,
2977 const CCValAssign &VA,
2978 ISD::ArgFlagsTy Flags) const {
2979 unsigned LocMemOffset = VA.getLocMemOffset();
2980 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
2981 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
2983 if (Flags.isByVal())
2984 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2986 return DAG.getStore(
2987 Chain, dl, Arg, PtrOff,
2988 MachinePointerInfo::getStack(DAG.getMachineFunction(), LocMemOffset),
2992 /// Emit a load of return address if tail call
2993 /// optimization is performed and it is required.
2995 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2996 SDValue &OutRetAddr, SDValue Chain,
2997 bool IsTailCall, bool Is64Bit,
2998 int FPDiff, SDLoc dl) const {
2999 // Adjust the Return address stack slot.
3000 EVT VT = getPointerTy(DAG.getDataLayout());
3001 OutRetAddr = getReturnAddressFrameIndex(DAG);
3003 // Load the "old" Return address.
3004 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
3005 false, false, false, 0);
3006 return SDValue(OutRetAddr.getNode(), 1);
3009 /// Emit a store of the return address if tail call
3010 /// optimization is performed and it is required (FPDiff!=0).
3011 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
3012 SDValue Chain, SDValue RetAddrFrIdx,
3013 EVT PtrVT, unsigned SlotSize,
3014 int FPDiff, SDLoc dl) {
3015 // Store the return address to the appropriate stack slot.
3016 if (!FPDiff) return Chain;
3017 // Calculate the new stack slot for the return address.
3018 int NewReturnAddrFI =
3019 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
3021 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
3022 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
3023 MachinePointerInfo::getFixedStack(
3024 DAG.getMachineFunction(), NewReturnAddrFI),
3029 /// Returns a vector_shuffle mask for an movs{s|d}, movd
3030 /// operation of specified width.
3031 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
3033 unsigned NumElems = VT.getVectorNumElements();
3034 SmallVector<int, 8> Mask;
3035 Mask.push_back(NumElems);
3036 for (unsigned i = 1; i != NumElems; ++i)
3038 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3042 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
3043 SmallVectorImpl<SDValue> &InVals) const {
3044 SelectionDAG &DAG = CLI.DAG;
3046 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
3047 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
3048 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
3049 SDValue Chain = CLI.Chain;
3050 SDValue Callee = CLI.Callee;
3051 CallingConv::ID CallConv = CLI.CallConv;
3052 bool &isTailCall = CLI.IsTailCall;
3053 bool isVarArg = CLI.IsVarArg;
3055 MachineFunction &MF = DAG.getMachineFunction();
3056 bool Is64Bit = Subtarget->is64Bit();
3057 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
3058 StructReturnType SR = callIsStructReturn(Outs);
3059 bool IsSibcall = false;
3060 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
3061 auto Attr = MF.getFunction()->getFnAttribute("disable-tail-calls");
3063 if (CallConv == CallingConv::X86_INTR)
3064 report_fatal_error("X86 interrupts may not be called directly");
3066 if (Attr.getValueAsString() == "true")
3069 if (Subtarget->isPICStyleGOT() &&
3070 !MF.getTarget().Options.GuaranteedTailCallOpt) {
3071 // If we are using a GOT, disable tail calls to external symbols with
3072 // default visibility. Tail calling such a symbol requires using a GOT
3073 // relocation, which forces early binding of the symbol. This breaks code
3074 // that require lazy function symbol resolution. Using musttail or
3075 // GuaranteedTailCallOpt will override this.
3076 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
3077 if (!G || (!G->getGlobal()->hasLocalLinkage() &&
3078 G->getGlobal()->hasDefaultVisibility()))
3082 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
3084 // Force this to be a tail call. The verifier rules are enough to ensure
3085 // that we can lower this successfully without moving the return address
3088 } else if (isTailCall) {
3089 // Check if it's really possible to do a tail call.
3090 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
3091 isVarArg, SR != NotStructReturn,
3092 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
3093 Outs, OutVals, Ins, DAG);
3095 // Sibcalls are automatically detected tailcalls which do not require
3097 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
3104 assert(!(isVarArg && canGuaranteeTCO(CallConv)) &&
3105 "Var args not supported with calling convention fastcc, ghc or hipe");
3107 // Analyze operands of the call, assigning locations to each operand.
3108 SmallVector<CCValAssign, 16> ArgLocs;
3109 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
3111 // Allocate shadow area for Win64
3113 CCInfo.AllocateStack(32, 8);
3115 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3117 // Get a count of how many bytes are to be pushed on the stack.
3118 unsigned NumBytes = CCInfo.getAlignedCallFrameSize();
3120 // This is a sibcall. The memory operands are available in caller's
3121 // own caller's stack.
3123 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
3124 canGuaranteeTCO(CallConv))
3125 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
3128 if (isTailCall && !IsSibcall && !IsMustTail) {
3129 // Lower arguments at fp - stackoffset + fpdiff.
3130 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
3132 FPDiff = NumBytesCallerPushed - NumBytes;
3134 // Set the delta of movement of the returnaddr stackslot.
3135 // But only set if delta is greater than previous delta.
3136 if (FPDiff < X86Info->getTCReturnAddrDelta())
3137 X86Info->setTCReturnAddrDelta(FPDiff);
3140 unsigned NumBytesToPush = NumBytes;
3141 unsigned NumBytesToPop = NumBytes;
3143 // If we have an inalloca argument, all stack space has already been allocated
3144 // for us and be right at the top of the stack. We don't support multiple
3145 // arguments passed in memory when using inalloca.
3146 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
3148 if (!ArgLocs.back().isMemLoc())
3149 report_fatal_error("cannot use inalloca attribute on a register "
3151 if (ArgLocs.back().getLocMemOffset() != 0)
3152 report_fatal_error("any parameter with the inalloca attribute must be "
3153 "the only memory argument");
3157 Chain = DAG.getCALLSEQ_START(
3158 Chain, DAG.getIntPtrConstant(NumBytesToPush, dl, true), dl);
3160 SDValue RetAddrFrIdx;
3161 // Load return address for tail calls.
3162 if (isTailCall && FPDiff)
3163 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
3164 Is64Bit, FPDiff, dl);
3166 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
3167 SmallVector<SDValue, 8> MemOpChains;
3170 // Walk the register/memloc assignments, inserting copies/loads. In the case
3171 // of tail call optimization arguments are handle later.
3172 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3173 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3174 // Skip inalloca arguments, they have already been written.
3175 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3176 if (Flags.isInAlloca())
3179 CCValAssign &VA = ArgLocs[i];
3180 EVT RegVT = VA.getLocVT();
3181 SDValue Arg = OutVals[i];
3182 bool isByVal = Flags.isByVal();
3184 // Promote the value if needed.
3185 switch (VA.getLocInfo()) {
3186 default: llvm_unreachable("Unknown loc info!");
3187 case CCValAssign::Full: break;
3188 case CCValAssign::SExt:
3189 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
3191 case CCValAssign::ZExt:
3192 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
3194 case CCValAssign::AExt:
3195 if (Arg.getValueType().isVector() &&
3196 Arg.getValueType().getVectorElementType() == MVT::i1)
3197 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
3198 else if (RegVT.is128BitVector()) {
3199 // Special case: passing MMX values in XMM registers.
3200 Arg = DAG.getBitcast(MVT::i64, Arg);
3201 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
3202 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
3204 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
3206 case CCValAssign::BCvt:
3207 Arg = DAG.getBitcast(RegVT, Arg);
3209 case CCValAssign::Indirect: {
3210 // Store the argument.
3211 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
3212 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
3213 Chain = DAG.getStore(
3214 Chain, dl, Arg, SpillSlot,
3215 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI),
3222 if (VA.isRegLoc()) {
3223 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
3224 if (isVarArg && IsWin64) {
3225 // Win64 ABI requires argument XMM reg to be copied to the corresponding
3226 // shadow reg if callee is a varargs function.
3227 unsigned ShadowReg = 0;
3228 switch (VA.getLocReg()) {
3229 case X86::XMM0: ShadowReg = X86::RCX; break;
3230 case X86::XMM1: ShadowReg = X86::RDX; break;
3231 case X86::XMM2: ShadowReg = X86::R8; break;
3232 case X86::XMM3: ShadowReg = X86::R9; break;
3235 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
3237 } else if (!IsSibcall && (!isTailCall || isByVal)) {
3238 assert(VA.isMemLoc());
3239 if (!StackPtr.getNode())
3240 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
3241 getPointerTy(DAG.getDataLayout()));
3242 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
3243 dl, DAG, VA, Flags));
3247 if (!MemOpChains.empty())
3248 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
3250 if (Subtarget->isPICStyleGOT()) {
3251 // ELF / PIC requires GOT in the EBX register before function calls via PLT
3254 RegsToPass.push_back(std::make_pair(
3255 unsigned(X86::EBX), DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(),
3256 getPointerTy(DAG.getDataLayout()))));
3258 // If we are tail calling and generating PIC/GOT style code load the
3259 // address of the callee into ECX. The value in ecx is used as target of
3260 // the tail jump. This is done to circumvent the ebx/callee-saved problem
3261 // for tail calls on PIC/GOT architectures. Normally we would just put the
3262 // address of GOT into ebx and then call target@PLT. But for tail calls
3263 // ebx would be restored (since ebx is callee saved) before jumping to the
3266 // Note: The actual moving to ECX is done further down.
3267 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
3268 if (G && !G->getGlobal()->hasLocalLinkage() &&
3269 G->getGlobal()->hasDefaultVisibility())
3270 Callee = LowerGlobalAddress(Callee, DAG);
3271 else if (isa<ExternalSymbolSDNode>(Callee))
3272 Callee = LowerExternalSymbol(Callee, DAG);
3276 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
3277 // From AMD64 ABI document:
3278 // For calls that may call functions that use varargs or stdargs
3279 // (prototype-less calls or calls to functions containing ellipsis (...) in
3280 // the declaration) %al is used as hidden argument to specify the number
3281 // of SSE registers used. The contents of %al do not need to match exactly
3282 // the number of registers, but must be an ubound on the number of SSE
3283 // registers used and is in the range 0 - 8 inclusive.
3285 // Count the number of XMM registers allocated.
3286 static const MCPhysReg XMMArgRegs[] = {
3287 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
3288 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
3290 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs);
3291 assert((Subtarget->hasSSE1() || !NumXMMRegs)
3292 && "SSE registers cannot be used when SSE is disabled");
3294 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
3295 DAG.getConstant(NumXMMRegs, dl,
3299 if (isVarArg && IsMustTail) {
3300 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
3301 for (const auto &F : Forwards) {
3302 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
3303 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
3307 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
3308 // don't need this because the eligibility check rejects calls that require
3309 // shuffling arguments passed in memory.
3310 if (!IsSibcall && isTailCall) {
3311 // Force all the incoming stack arguments to be loaded from the stack
3312 // before any new outgoing arguments are stored to the stack, because the
3313 // outgoing stack slots may alias the incoming argument stack slots, and
3314 // the alias isn't otherwise explicit. This is slightly more conservative
3315 // than necessary, because it means that each store effectively depends
3316 // on every argument instead of just those arguments it would clobber.
3317 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
3319 SmallVector<SDValue, 8> MemOpChains2;
3322 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3323 CCValAssign &VA = ArgLocs[i];
3326 assert(VA.isMemLoc());
3327 SDValue Arg = OutVals[i];
3328 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3329 // Skip inalloca arguments. They don't require any work.
3330 if (Flags.isInAlloca())
3332 // Create frame index.
3333 int32_t Offset = VA.getLocMemOffset()+FPDiff;
3334 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
3335 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3336 FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
3338 if (Flags.isByVal()) {
3339 // Copy relative to framepointer.
3340 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset(), dl);
3341 if (!StackPtr.getNode())
3342 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
3343 getPointerTy(DAG.getDataLayout()));
3344 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
3347 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3351 // Store relative to framepointer.
3352 MemOpChains2.push_back(DAG.getStore(
3353 ArgChain, dl, Arg, FIN,
3354 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI),
3359 if (!MemOpChains2.empty())
3360 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3362 // Store the return address to the appropriate stack slot.
3363 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3364 getPointerTy(DAG.getDataLayout()),
3365 RegInfo->getSlotSize(), FPDiff, dl);
3368 // Build a sequence of copy-to-reg nodes chained together with token chain
3369 // and flag operands which copy the outgoing args into registers.
3371 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3372 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3373 RegsToPass[i].second, InFlag);
3374 InFlag = Chain.getValue(1);
3377 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3378 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3379 // In the 64-bit large code model, we have to make all calls
3380 // through a register, since the call instruction's 32-bit
3381 // pc-relative offset may not be large enough to hold the whole
3383 } else if (Callee->getOpcode() == ISD::GlobalAddress) {
3384 // If the callee is a GlobalAddress node (quite common, every direct call
3385 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3387 GlobalAddressSDNode* G = cast<GlobalAddressSDNode>(Callee);
3389 // We should use extra load for direct calls to dllimported functions in
3391 const GlobalValue *GV = G->getGlobal();
3392 if (!GV->hasDLLImportStorageClass()) {
3393 unsigned char OpFlags = 0;
3394 bool ExtraLoad = false;
3395 unsigned WrapperKind = ISD::DELETED_NODE;
3397 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3398 // external symbols most go through the PLT in PIC mode. If the symbol
3399 // has hidden or protected visibility, or if it is static or local, then
3400 // we don't need to use the PLT - we can directly call it.
3401 if (Subtarget->isTargetELF() &&
3402 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3403 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3404 OpFlags = X86II::MO_PLT;
3405 } else if (Subtarget->isPICStyleStubAny() &&
3406 !GV->isStrongDefinitionForLinker() &&
3407 (!Subtarget->getTargetTriple().isMacOSX() ||
3408 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3409 // PC-relative references to external symbols should go through $stub,
3410 // unless we're building with the leopard linker or later, which
3411 // automatically synthesizes these stubs.
3412 OpFlags = X86II::MO_DARWIN_STUB;
3413 } else if (Subtarget->isPICStyleRIPRel() && isa<Function>(GV) &&
3414 cast<Function>(GV)->hasFnAttribute(Attribute::NonLazyBind)) {
3415 // If the function is marked as non-lazy, generate an indirect call
3416 // which loads from the GOT directly. This avoids runtime overhead
3417 // at the cost of eager binding (and one extra byte of encoding).
3418 OpFlags = X86II::MO_GOTPCREL;
3419 WrapperKind = X86ISD::WrapperRIP;
3423 Callee = DAG.getTargetGlobalAddress(
3424 GV, dl, getPointerTy(DAG.getDataLayout()), G->getOffset(), OpFlags);
3426 // Add a wrapper if needed.
3427 if (WrapperKind != ISD::DELETED_NODE)
3428 Callee = DAG.getNode(X86ISD::WrapperRIP, dl,
3429 getPointerTy(DAG.getDataLayout()), Callee);
3430 // Add extra indirection if needed.
3432 Callee = DAG.getLoad(
3433 getPointerTy(DAG.getDataLayout()), dl, DAG.getEntryNode(), Callee,
3434 MachinePointerInfo::getGOT(DAG.getMachineFunction()), false, false,
3437 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3438 unsigned char OpFlags = 0;
3440 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3441 // external symbols should go through the PLT.
3442 if (Subtarget->isTargetELF() &&
3443 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3444 OpFlags = X86II::MO_PLT;
3445 } else if (Subtarget->isPICStyleStubAny() &&
3446 (!Subtarget->getTargetTriple().isMacOSX() ||
3447 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3448 // PC-relative references to external symbols should go through $stub,
3449 // unless we're building with the leopard linker or later, which
3450 // automatically synthesizes these stubs.
3451 OpFlags = X86II::MO_DARWIN_STUB;
3454 Callee = DAG.getTargetExternalSymbol(
3455 S->getSymbol(), getPointerTy(DAG.getDataLayout()), OpFlags);
3456 } else if (Subtarget->isTarget64BitILP32() &&
3457 Callee->getValueType(0) == MVT::i32) {
3458 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3459 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3462 // Returns a chain & a flag for retval copy to use.
3463 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3464 SmallVector<SDValue, 8> Ops;
3466 if (!IsSibcall && isTailCall) {
3467 Chain = DAG.getCALLSEQ_END(Chain,
3468 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
3469 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
3470 InFlag = Chain.getValue(1);
3473 Ops.push_back(Chain);
3474 Ops.push_back(Callee);
3477 Ops.push_back(DAG.getConstant(FPDiff, dl, MVT::i32));
3479 // Add argument registers to the end of the list so that they are known live
3481 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3482 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3483 RegsToPass[i].second.getValueType()));
3485 // Add a register mask operand representing the call-preserved registers.
3486 const uint32_t *Mask = RegInfo->getCallPreservedMask(MF, CallConv);
3487 assert(Mask && "Missing call preserved mask for calling convention");
3489 // If this is an invoke in a 32-bit function using a funclet-based
3490 // personality, assume the function clobbers all registers. If an exception
3491 // is thrown, the runtime will not restore CSRs.
3492 // FIXME: Model this more precisely so that we can register allocate across
3493 // the normal edge and spill and fill across the exceptional edge.
3494 if (!Is64Bit && CLI.CS && CLI.CS->isInvoke()) {
3495 const Function *CallerFn = MF.getFunction();
3496 EHPersonality Pers =
3497 CallerFn->hasPersonalityFn()
3498 ? classifyEHPersonality(CallerFn->getPersonalityFn())
3499 : EHPersonality::Unknown;
3500 if (isFuncletEHPersonality(Pers))
3501 Mask = RegInfo->getNoPreservedMask();
3504 Ops.push_back(DAG.getRegisterMask(Mask));
3506 if (InFlag.getNode())
3507 Ops.push_back(InFlag);
3511 //// If this is the first return lowered for this function, add the regs
3512 //// to the liveout set for the function.
3513 // This isn't right, although it's probably harmless on x86; liveouts
3514 // should be computed from returns not tail calls. Consider a void
3515 // function making a tail call to a function returning int.
3516 MF.getFrameInfo()->setHasTailCall();
3517 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3520 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3521 InFlag = Chain.getValue(1);
3523 // Create the CALLSEQ_END node.
3524 unsigned NumBytesForCalleeToPop;
3525 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3526 DAG.getTarget().Options.GuaranteedTailCallOpt))
3527 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3528 else if (!Is64Bit && !canGuaranteeTCO(CallConv) &&
3529 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3530 SR == StackStructReturn)
3531 // If this is a call to a struct-return function, the callee
3532 // pops the hidden struct pointer, so we have to push it back.
3533 // This is common for Darwin/X86, Linux & Mingw32 targets.
3534 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3535 NumBytesForCalleeToPop = 4;
3537 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3539 // Returns a flag for retval copy to use.
3541 Chain = DAG.getCALLSEQ_END(Chain,
3542 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
3543 DAG.getIntPtrConstant(NumBytesForCalleeToPop, dl,
3546 InFlag = Chain.getValue(1);
3549 // Handle result values, copying them out of physregs into vregs that we
3551 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3552 Ins, dl, DAG, InVals);
3555 //===----------------------------------------------------------------------===//
3556 // Fast Calling Convention (tail call) implementation
3557 //===----------------------------------------------------------------------===//
3559 // Like std call, callee cleans arguments, convention except that ECX is
3560 // reserved for storing the tail called function address. Only 2 registers are
3561 // free for argument passing (inreg). Tail call optimization is performed
3563 // * tailcallopt is enabled
3564 // * caller/callee are fastcc
3565 // On X86_64 architecture with GOT-style position independent code only local
3566 // (within module) calls are supported at the moment.
3567 // To keep the stack aligned according to platform abi the function
3568 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3569 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3570 // If a tail called function callee has more arguments than the caller the
3571 // caller needs to make sure that there is room to move the RETADDR to. This is
3572 // achieved by reserving an area the size of the argument delta right after the
3573 // original RETADDR, but before the saved framepointer or the spilled registers
3574 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3586 /// Make the stack size align e.g 16n + 12 aligned for a 16-byte align
3589 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3590 SelectionDAG& DAG) const {
3591 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3592 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
3593 unsigned StackAlignment = TFI.getStackAlignment();
3594 uint64_t AlignMask = StackAlignment - 1;
3595 int64_t Offset = StackSize;
3596 unsigned SlotSize = RegInfo->getSlotSize();
3597 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3598 // Number smaller than 12 so just add the difference.
3599 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3601 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3602 Offset = ((~AlignMask) & Offset) + StackAlignment +
3603 (StackAlignment-SlotSize);
3608 /// Return true if the given stack call argument is already available in the
3609 /// same position (relatively) of the caller's incoming argument stack.
3611 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3612 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3613 const X86InstrInfo *TII) {
3614 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3616 if (Arg.getOpcode() == ISD::CopyFromReg) {
3617 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3618 if (!TargetRegisterInfo::isVirtualRegister(VR))
3620 MachineInstr *Def = MRI->getVRegDef(VR);
3623 if (!Flags.isByVal()) {
3624 if (!TII->isLoadFromStackSlot(Def, FI))
3627 unsigned Opcode = Def->getOpcode();
3628 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r ||
3629 Opcode == X86::LEA64_32r) &&
3630 Def->getOperand(1).isFI()) {
3631 FI = Def->getOperand(1).getIndex();
3632 Bytes = Flags.getByValSize();
3636 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3637 if (Flags.isByVal())
3638 // ByVal argument is passed in as a pointer but it's now being
3639 // dereferenced. e.g.
3640 // define @foo(%struct.X* %A) {
3641 // tail call @bar(%struct.X* byval %A)
3644 SDValue Ptr = Ld->getBasePtr();
3645 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3648 FI = FINode->getIndex();
3649 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3650 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3651 FI = FINode->getIndex();
3652 Bytes = Flags.getByValSize();
3656 assert(FI != INT_MAX);
3657 if (!MFI->isFixedObjectIndex(FI))
3659 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3662 /// Check whether the call is eligible for tail call optimization. Targets
3663 /// that want to do tail call optimization should implement this function.
3664 bool X86TargetLowering::IsEligibleForTailCallOptimization(
3665 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
3666 bool isCalleeStructRet, bool isCallerStructRet, Type *RetTy,
3667 const SmallVectorImpl<ISD::OutputArg> &Outs,
3668 const SmallVectorImpl<SDValue> &OutVals,
3669 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const {
3670 if (!mayTailCallThisCC(CalleeCC))
3673 // If -tailcallopt is specified, make fastcc functions tail-callable.
3674 MachineFunction &MF = DAG.getMachineFunction();
3675 const Function *CallerF = MF.getFunction();
3677 // If the function return type is x86_fp80 and the callee return type is not,
3678 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3679 // perform a tailcall optimization here.
3680 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3683 CallingConv::ID CallerCC = CallerF->getCallingConv();
3684 bool CCMatch = CallerCC == CalleeCC;
3685 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3686 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3688 // Win64 functions have extra shadow space for argument homing. Don't do the
3689 // sibcall if the caller and callee have mismatched expectations for this
3691 if (IsCalleeWin64 != IsCallerWin64)
3694 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3695 if (canGuaranteeTCO(CalleeCC) && CCMatch)
3700 // Look for obvious safe cases to perform tail call optimization that do not
3701 // require ABI changes. This is what gcc calls sibcall.
3703 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3704 // emit a special epilogue.
3705 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3706 if (RegInfo->needsStackRealignment(MF))
3709 // Also avoid sibcall optimization if either caller or callee uses struct
3710 // return semantics.
3711 if (isCalleeStructRet || isCallerStructRet)
3714 // Do not sibcall optimize vararg calls unless all arguments are passed via
3716 if (isVarArg && !Outs.empty()) {
3717 // Optimizing for varargs on Win64 is unlikely to be safe without
3718 // additional testing.
3719 if (IsCalleeWin64 || IsCallerWin64)
3722 SmallVector<CCValAssign, 16> ArgLocs;
3723 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3726 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3727 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3728 if (!ArgLocs[i].isRegLoc())
3732 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3733 // stack. Therefore, if it's not used by the call it is not safe to optimize
3734 // this into a sibcall.
3735 bool Unused = false;
3736 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3743 SmallVector<CCValAssign, 16> RVLocs;
3744 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3746 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3747 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3748 CCValAssign &VA = RVLocs[i];
3749 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3754 // If the calling conventions do not match, then we'd better make sure the
3755 // results are returned in the same way as what the caller expects.
3757 SmallVector<CCValAssign, 16> RVLocs1;
3758 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3760 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3762 SmallVector<CCValAssign, 16> RVLocs2;
3763 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3765 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3767 if (RVLocs1.size() != RVLocs2.size())
3769 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3770 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3772 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3774 if (RVLocs1[i].isRegLoc()) {
3775 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3778 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3784 unsigned StackArgsSize = 0;
3786 // If the callee takes no arguments then go on to check the results of the
3788 if (!Outs.empty()) {
3789 // Check if stack adjustment is needed. For now, do not do this if any
3790 // argument is passed on the stack.
3791 SmallVector<CCValAssign, 16> ArgLocs;
3792 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3795 // Allocate shadow area for Win64
3797 CCInfo.AllocateStack(32, 8);
3799 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3800 StackArgsSize = CCInfo.getNextStackOffset();
3802 if (CCInfo.getNextStackOffset()) {
3803 // Check if the arguments are already laid out in the right way as
3804 // the caller's fixed stack objects.
3805 MachineFrameInfo *MFI = MF.getFrameInfo();
3806 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3807 const X86InstrInfo *TII = Subtarget->getInstrInfo();
3808 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3809 CCValAssign &VA = ArgLocs[i];
3810 SDValue Arg = OutVals[i];
3811 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3812 if (VA.getLocInfo() == CCValAssign::Indirect)
3814 if (!VA.isRegLoc()) {
3815 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3822 // If the tailcall address may be in a register, then make sure it's
3823 // possible to register allocate for it. In 32-bit, the call address can
3824 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3825 // callee-saved registers are restored. These happen to be the same
3826 // registers used to pass 'inreg' arguments so watch out for those.
3827 if (!Subtarget->is64Bit() &&
3828 ((!isa<GlobalAddressSDNode>(Callee) &&
3829 !isa<ExternalSymbolSDNode>(Callee)) ||
3830 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3831 unsigned NumInRegs = 0;
3832 // In PIC we need an extra register to formulate the address computation
3834 unsigned MaxInRegs =
3835 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3837 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3838 CCValAssign &VA = ArgLocs[i];
3841 unsigned Reg = VA.getLocReg();
3844 case X86::EAX: case X86::EDX: case X86::ECX:
3845 if (++NumInRegs == MaxInRegs)
3853 bool CalleeWillPop =
3854 X86::isCalleePop(CalleeCC, Subtarget->is64Bit(), isVarArg,
3855 MF.getTarget().Options.GuaranteedTailCallOpt);
3857 if (unsigned BytesToPop =
3858 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn()) {
3859 // If we have bytes to pop, the callee must pop them.
3860 bool CalleePopMatches = CalleeWillPop && BytesToPop == StackArgsSize;
3861 if (!CalleePopMatches)
3863 } else if (CalleeWillPop && StackArgsSize > 0) {
3864 // If we don't have bytes to pop, make sure the callee doesn't pop any.
3872 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3873 const TargetLibraryInfo *libInfo) const {
3874 return X86::createFastISel(funcInfo, libInfo);
3877 //===----------------------------------------------------------------------===//
3878 // Other Lowering Hooks
3879 //===----------------------------------------------------------------------===//
3881 static bool MayFoldLoad(SDValue Op) {
3882 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3885 static bool MayFoldIntoStore(SDValue Op) {
3886 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3889 static bool isTargetShuffle(unsigned Opcode) {
3891 default: return false;
3892 case X86ISD::BLENDI:
3893 case X86ISD::PSHUFB:
3894 case X86ISD::PSHUFD:
3895 case X86ISD::PSHUFHW:
3896 case X86ISD::PSHUFLW:
3898 case X86ISD::PALIGNR:
3899 case X86ISD::MOVLHPS:
3900 case X86ISD::MOVLHPD:
3901 case X86ISD::MOVHLPS:
3902 case X86ISD::MOVLPS:
3903 case X86ISD::MOVLPD:
3904 case X86ISD::MOVSHDUP:
3905 case X86ISD::MOVSLDUP:
3906 case X86ISD::MOVDDUP:
3909 case X86ISD::UNPCKL:
3910 case X86ISD::UNPCKH:
3911 case X86ISD::VPERMILPI:
3912 case X86ISD::VPERM2X128:
3913 case X86ISD::VPERMI:
3914 case X86ISD::VPERMV:
3915 case X86ISD::VPERMV3:
3920 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, MVT VT,
3921 SDValue V1, unsigned TargetMask,
3922 SelectionDAG &DAG) {
3924 default: llvm_unreachable("Unknown x86 shuffle node");
3925 case X86ISD::PSHUFD:
3926 case X86ISD::PSHUFHW:
3927 case X86ISD::PSHUFLW:
3928 case X86ISD::VPERMILPI:
3929 case X86ISD::VPERMI:
3930 return DAG.getNode(Opc, dl, VT, V1,
3931 DAG.getConstant(TargetMask, dl, MVT::i8));
3935 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, MVT VT,
3936 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3938 default: llvm_unreachable("Unknown x86 shuffle node");
3939 case X86ISD::MOVLHPS:
3940 case X86ISD::MOVLHPD:
3941 case X86ISD::MOVHLPS:
3942 case X86ISD::MOVLPS:
3943 case X86ISD::MOVLPD:
3946 case X86ISD::UNPCKL:
3947 case X86ISD::UNPCKH:
3948 return DAG.getNode(Opc, dl, VT, V1, V2);
3952 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3953 MachineFunction &MF = DAG.getMachineFunction();
3954 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3955 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3956 int ReturnAddrIndex = FuncInfo->getRAIndex();
3958 if (ReturnAddrIndex == 0) {
3959 // Set up a frame object for the return address.
3960 unsigned SlotSize = RegInfo->getSlotSize();
3961 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3964 FuncInfo->setRAIndex(ReturnAddrIndex);
3967 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy(DAG.getDataLayout()));
3970 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3971 bool hasSymbolicDisplacement) {
3972 // Offset should fit into 32 bit immediate field.
3973 if (!isInt<32>(Offset))
3976 // If we don't have a symbolic displacement - we don't have any extra
3978 if (!hasSymbolicDisplacement)
3981 // FIXME: Some tweaks might be needed for medium code model.
3982 if (M != CodeModel::Small && M != CodeModel::Kernel)
3985 // For small code model we assume that latest object is 16MB before end of 31
3986 // bits boundary. We may also accept pretty large negative constants knowing
3987 // that all objects are in the positive half of address space.
3988 if (M == CodeModel::Small && Offset < 16*1024*1024)
3991 // For kernel code model we know that all object resist in the negative half
3992 // of 32bits address space. We may not accept negative offsets, since they may
3993 // be just off and we may accept pretty large positive ones.
3994 if (M == CodeModel::Kernel && Offset >= 0)
4000 /// Determines whether the callee is required to pop its own arguments.
4001 /// Callee pop is necessary to support tail calls.
4002 bool X86::isCalleePop(CallingConv::ID CallingConv,
4003 bool is64Bit, bool IsVarArg, bool GuaranteeTCO) {
4004 // If GuaranteeTCO is true, we force some calls to be callee pop so that we
4005 // can guarantee TCO.
4006 if (!IsVarArg && shouldGuaranteeTCO(CallingConv, GuaranteeTCO))
4009 switch (CallingConv) {
4012 case CallingConv::X86_StdCall:
4013 case CallingConv::X86_FastCall:
4014 case CallingConv::X86_ThisCall:
4015 case CallingConv::X86_VectorCall:
4020 /// \brief Return true if the condition is an unsigned comparison operation.
4021 static bool isX86CCUnsigned(unsigned X86CC) {
4023 default: llvm_unreachable("Invalid integer condition!");
4024 case X86::COND_E: return true;
4025 case X86::COND_G: return false;
4026 case X86::COND_GE: return false;
4027 case X86::COND_L: return false;
4028 case X86::COND_LE: return false;
4029 case X86::COND_NE: return true;
4030 case X86::COND_B: return true;
4031 case X86::COND_A: return true;
4032 case X86::COND_BE: return true;
4033 case X86::COND_AE: return true;
4037 static X86::CondCode TranslateIntegerX86CC(ISD::CondCode SetCCOpcode) {
4038 switch (SetCCOpcode) {
4039 default: llvm_unreachable("Invalid integer condition!");
4040 case ISD::SETEQ: return X86::COND_E;
4041 case ISD::SETGT: return X86::COND_G;
4042 case ISD::SETGE: return X86::COND_GE;
4043 case ISD::SETLT: return X86::COND_L;
4044 case ISD::SETLE: return X86::COND_LE;
4045 case ISD::SETNE: return X86::COND_NE;
4046 case ISD::SETULT: return X86::COND_B;
4047 case ISD::SETUGT: return X86::COND_A;
4048 case ISD::SETULE: return X86::COND_BE;
4049 case ISD::SETUGE: return X86::COND_AE;
4053 /// Do a one-to-one translation of a ISD::CondCode to the X86-specific
4054 /// condition code, returning the condition code and the LHS/RHS of the
4055 /// comparison to make.
4056 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, SDLoc DL, bool isFP,
4057 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
4059 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
4060 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
4061 // X > -1 -> X == 0, jump !sign.
4062 RHS = DAG.getConstant(0, DL, RHS.getValueType());
4063 return X86::COND_NS;
4065 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
4066 // X < 0 -> X == 0, jump on sign.
4069 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
4071 RHS = DAG.getConstant(0, DL, RHS.getValueType());
4072 return X86::COND_LE;
4076 return TranslateIntegerX86CC(SetCCOpcode);
4079 // First determine if it is required or is profitable to flip the operands.
4081 // If LHS is a foldable load, but RHS is not, flip the condition.
4082 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
4083 !ISD::isNON_EXTLoad(RHS.getNode())) {
4084 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
4085 std::swap(LHS, RHS);
4088 switch (SetCCOpcode) {
4094 std::swap(LHS, RHS);
4098 // On a floating point condition, the flags are set as follows:
4100 // 0 | 0 | 0 | X > Y
4101 // 0 | 0 | 1 | X < Y
4102 // 1 | 0 | 0 | X == Y
4103 // 1 | 1 | 1 | unordered
4104 switch (SetCCOpcode) {
4105 default: llvm_unreachable("Condcode should be pre-legalized away");
4107 case ISD::SETEQ: return X86::COND_E;
4108 case ISD::SETOLT: // flipped
4110 case ISD::SETGT: return X86::COND_A;
4111 case ISD::SETOLE: // flipped
4113 case ISD::SETGE: return X86::COND_AE;
4114 case ISD::SETUGT: // flipped
4116 case ISD::SETLT: return X86::COND_B;
4117 case ISD::SETUGE: // flipped
4119 case ISD::SETLE: return X86::COND_BE;
4121 case ISD::SETNE: return X86::COND_NE;
4122 case ISD::SETUO: return X86::COND_P;
4123 case ISD::SETO: return X86::COND_NP;
4125 case ISD::SETUNE: return X86::COND_INVALID;
4129 /// Is there a floating point cmov for the specific X86 condition code?
4130 /// Current x86 isa includes the following FP cmov instructions:
4131 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
4132 static bool hasFPCMov(unsigned X86CC) {
4148 /// Returns true if the target can instruction select the
4149 /// specified FP immediate natively. If false, the legalizer will
4150 /// materialize the FP immediate as a load from a constant pool.
4151 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
4152 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
4153 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
4159 bool X86TargetLowering::shouldReduceLoadWidth(SDNode *Load,
4160 ISD::LoadExtType ExtTy,
4162 // "ELF Handling for Thread-Local Storage" specifies that R_X86_64_GOTTPOFF
4163 // relocation target a movq or addq instruction: don't let the load shrink.
4164 SDValue BasePtr = cast<LoadSDNode>(Load)->getBasePtr();
4165 if (BasePtr.getOpcode() == X86ISD::WrapperRIP)
4166 if (const auto *GA = dyn_cast<GlobalAddressSDNode>(BasePtr.getOperand(0)))
4167 return GA->getTargetFlags() != X86II::MO_GOTTPOFF;
4171 /// \brief Returns true if it is beneficial to convert a load of a constant
4172 /// to just the constant itself.
4173 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
4175 assert(Ty->isIntegerTy());
4177 unsigned BitSize = Ty->getPrimitiveSizeInBits();
4178 if (BitSize == 0 || BitSize > 64)
4183 bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT,
4184 unsigned Index) const {
4185 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))
4188 return (Index == 0 || Index == ResVT.getVectorNumElements());
4191 bool X86TargetLowering::isCheapToSpeculateCttz() const {
4192 // Speculate cttz only if we can directly use TZCNT.
4193 return Subtarget->hasBMI();
4196 bool X86TargetLowering::isCheapToSpeculateCtlz() const {
4197 // Speculate ctlz only if we can directly use LZCNT.
4198 return Subtarget->hasLZCNT();
4201 /// Return true if every element in Mask, beginning
4202 /// from position Pos and ending in Pos+Size is undef.
4203 static bool isUndefInRange(ArrayRef<int> Mask, unsigned Pos, unsigned Size) {
4204 for (unsigned i = Pos, e = Pos + Size; i != e; ++i)
4210 /// Return true if Val is undef or if its value falls within the
4211 /// specified range (L, H].
4212 static bool isUndefOrInRange(int Val, int Low, int Hi) {
4213 return (Val < 0) || (Val >= Low && Val < Hi);
4216 /// Val is either less than zero (undef) or equal to the specified value.
4217 static bool isUndefOrEqual(int Val, int CmpVal) {
4218 return (Val < 0 || Val == CmpVal);
4221 /// Return true if every element in Mask, beginning
4222 /// from position Pos and ending in Pos+Size, falls within the specified
4223 /// sequential range (Low, Low+Size]. or is undef.
4224 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
4225 unsigned Pos, unsigned Size, int Low) {
4226 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
4227 if (!isUndefOrEqual(Mask[i], Low))
4232 /// Return true if the specified EXTRACT_SUBVECTOR operand specifies a vector
4233 /// extract that is suitable for instruction that extract 128 or 256 bit vectors
4234 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4235 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4236 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4239 // The index should be aligned on a vecWidth-bit boundary.
4241 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4243 MVT VT = N->getSimpleValueType(0);
4244 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4245 bool Result = (Index * ElSize) % vecWidth == 0;
4250 /// Return true if the specified INSERT_SUBVECTOR
4251 /// operand specifies a subvector insert that is suitable for input to
4252 /// insertion of 128 or 256-bit subvectors
4253 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4254 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4255 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4257 // The index should be aligned on a vecWidth-bit boundary.
4259 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4261 MVT VT = N->getSimpleValueType(0);
4262 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4263 bool Result = (Index * ElSize) % vecWidth == 0;
4268 bool X86::isVINSERT128Index(SDNode *N) {
4269 return isVINSERTIndex(N, 128);
4272 bool X86::isVINSERT256Index(SDNode *N) {
4273 return isVINSERTIndex(N, 256);
4276 bool X86::isVEXTRACT128Index(SDNode *N) {
4277 return isVEXTRACTIndex(N, 128);
4280 bool X86::isVEXTRACT256Index(SDNode *N) {
4281 return isVEXTRACTIndex(N, 256);
4284 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4285 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4286 assert(isa<ConstantSDNode>(N->getOperand(1).getNode()) &&
4287 "Illegal extract subvector for VEXTRACT");
4290 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4292 MVT VecVT = N->getOperand(0).getSimpleValueType();
4293 MVT ElVT = VecVT.getVectorElementType();
4295 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4296 return Index / NumElemsPerChunk;
4299 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4300 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4301 assert(isa<ConstantSDNode>(N->getOperand(2).getNode()) &&
4302 "Illegal insert subvector for VINSERT");
4305 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4307 MVT VecVT = N->getSimpleValueType(0);
4308 MVT ElVT = VecVT.getVectorElementType();
4310 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4311 return Index / NumElemsPerChunk;
4314 /// Return the appropriate immediate to extract the specified
4315 /// EXTRACT_SUBVECTOR index with VEXTRACTF128 and VINSERTI128 instructions.
4316 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4317 return getExtractVEXTRACTImmediate(N, 128);
4320 /// Return the appropriate immediate to extract the specified
4321 /// EXTRACT_SUBVECTOR index with VEXTRACTF64x4 and VINSERTI64x4 instructions.
4322 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4323 return getExtractVEXTRACTImmediate(N, 256);
4326 /// Return the appropriate immediate to insert at the specified
4327 /// INSERT_SUBVECTOR index with VINSERTF128 and VINSERTI128 instructions.
4328 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4329 return getInsertVINSERTImmediate(N, 128);
4332 /// Return the appropriate immediate to insert at the specified
4333 /// INSERT_SUBVECTOR index with VINSERTF46x4 and VINSERTI64x4 instructions.
4334 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4335 return getInsertVINSERTImmediate(N, 256);
4338 /// Returns true if Elt is a constant zero or a floating point constant +0.0.
4339 bool X86::isZeroNode(SDValue Elt) {
4340 return isNullConstant(Elt) || isNullFPConstant(Elt);
4343 // Build a vector of constants
4344 // Use an UNDEF node if MaskElt == -1.
4345 // Spilt 64-bit constants in the 32-bit mode.
4346 static SDValue getConstVector(ArrayRef<int> Values, MVT VT,
4348 SDLoc dl, bool IsMask = false) {
4350 SmallVector<SDValue, 32> Ops;
4353 MVT ConstVecVT = VT;
4354 unsigned NumElts = VT.getVectorNumElements();
4355 bool In64BitMode = DAG.getTargetLoweringInfo().isTypeLegal(MVT::i64);
4356 if (!In64BitMode && VT.getVectorElementType() == MVT::i64) {
4357 ConstVecVT = MVT::getVectorVT(MVT::i32, NumElts * 2);
4361 MVT EltVT = ConstVecVT.getVectorElementType();
4362 for (unsigned i = 0; i < NumElts; ++i) {
4363 bool IsUndef = Values[i] < 0 && IsMask;
4364 SDValue OpNode = IsUndef ? DAG.getUNDEF(EltVT) :
4365 DAG.getConstant(Values[i], dl, EltVT);
4366 Ops.push_back(OpNode);
4368 Ops.push_back(IsUndef ? DAG.getUNDEF(EltVT) :
4369 DAG.getConstant(0, dl, EltVT));
4371 SDValue ConstsNode = DAG.getNode(ISD::BUILD_VECTOR, dl, ConstVecVT, Ops);
4373 ConstsNode = DAG.getBitcast(VT, ConstsNode);
4377 /// Returns a vector of specified type with all zero elements.
4378 static SDValue getZeroVector(MVT VT, const X86Subtarget *Subtarget,
4379 SelectionDAG &DAG, SDLoc dl) {
4380 assert(VT.isVector() && "Expected a vector type");
4382 // Always build SSE zero vectors as <4 x i32> bitcasted
4383 // to their dest type. This ensures they get CSE'd.
4385 if (VT.is128BitVector()) { // SSE
4386 if (Subtarget->hasSSE2()) { // SSE2
4387 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4388 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4390 SDValue Cst = DAG.getConstantFP(+0.0, dl, MVT::f32);
4391 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4393 } else if (VT.is256BitVector()) { // AVX
4394 if (Subtarget->hasInt256()) { // AVX2
4395 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4396 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4397 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4399 // 256-bit logic and arithmetic instructions in AVX are all
4400 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4401 SDValue Cst = DAG.getConstantFP(+0.0, dl, MVT::f32);
4402 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4403 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
4405 } else if (VT.is512BitVector()) { // AVX-512
4406 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4407 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4408 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4409 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
4410 } else if (VT.getVectorElementType() == MVT::i1) {
4412 assert((Subtarget->hasBWI() || VT.getVectorNumElements() <= 16)
4413 && "Unexpected vector type");
4414 assert((Subtarget->hasVLX() || VT.getVectorNumElements() >= 8)
4415 && "Unexpected vector type");
4416 SDValue Cst = DAG.getConstant(0, dl, MVT::i1);
4417 SmallVector<SDValue, 64> Ops(VT.getVectorNumElements(), Cst);
4418 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
4420 llvm_unreachable("Unexpected vector type");
4422 return DAG.getBitcast(VT, Vec);
4425 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
4426 SelectionDAG &DAG, SDLoc dl,
4427 unsigned vectorWidth) {
4428 assert((vectorWidth == 128 || vectorWidth == 256) &&
4429 "Unsupported vector width");
4430 EVT VT = Vec.getValueType();
4431 EVT ElVT = VT.getVectorElementType();
4432 unsigned Factor = VT.getSizeInBits()/vectorWidth;
4433 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
4434 VT.getVectorNumElements()/Factor);
4436 // Extract from UNDEF is UNDEF.
4437 if (Vec.getOpcode() == ISD::UNDEF)
4438 return DAG.getUNDEF(ResultVT);
4440 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
4441 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
4442 assert(isPowerOf2_32(ElemsPerChunk) && "Elements per chunk not power of 2");
4444 // This is the index of the first element of the vectorWidth-bit chunk
4445 // we want. Since ElemsPerChunk is a power of 2 just need to clear bits.
4446 IdxVal &= ~(ElemsPerChunk - 1);
4448 // If the input is a buildvector just emit a smaller one.
4449 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
4450 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
4451 makeArrayRef(Vec->op_begin() + IdxVal, ElemsPerChunk));
4453 SDValue VecIdx = DAG.getIntPtrConstant(IdxVal, dl);
4454 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, VecIdx);
4457 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
4458 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
4459 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
4460 /// instructions or a simple subregister reference. Idx is an index in the
4461 /// 128 bits we want. It need not be aligned to a 128-bit boundary. That makes
4462 /// lowering EXTRACT_VECTOR_ELT operations easier.
4463 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
4464 SelectionDAG &DAG, SDLoc dl) {
4465 assert((Vec.getValueType().is256BitVector() ||
4466 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
4467 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
4470 /// Generate a DAG to grab 256-bits from a 512-bit vector.
4471 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
4472 SelectionDAG &DAG, SDLoc dl) {
4473 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
4474 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
4477 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
4478 unsigned IdxVal, SelectionDAG &DAG,
4479 SDLoc dl, unsigned vectorWidth) {
4480 assert((vectorWidth == 128 || vectorWidth == 256) &&
4481 "Unsupported vector width");
4482 // Inserting UNDEF is Result
4483 if (Vec.getOpcode() == ISD::UNDEF)
4485 EVT VT = Vec.getValueType();
4486 EVT ElVT = VT.getVectorElementType();
4487 EVT ResultVT = Result.getValueType();
4489 // Insert the relevant vectorWidth bits.
4490 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
4491 assert(isPowerOf2_32(ElemsPerChunk) && "Elements per chunk not power of 2");
4493 // This is the index of the first element of the vectorWidth-bit chunk
4494 // we want. Since ElemsPerChunk is a power of 2 just need to clear bits.
4495 IdxVal &= ~(ElemsPerChunk - 1);
4497 SDValue VecIdx = DAG.getIntPtrConstant(IdxVal, dl);
4498 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, VecIdx);
4501 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
4502 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
4503 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
4504 /// simple superregister reference. Idx is an index in the 128 bits
4505 /// we want. It need not be aligned to a 128-bit boundary. That makes
4506 /// lowering INSERT_VECTOR_ELT operations easier.
4507 static SDValue Insert128BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4508 SelectionDAG &DAG, SDLoc dl) {
4509 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
4511 // For insertion into the zero index (low half) of a 256-bit vector, it is
4512 // more efficient to generate a blend with immediate instead of an insert*128.
4513 // We are still creating an INSERT_SUBVECTOR below with an undef node to
4514 // extend the subvector to the size of the result vector. Make sure that
4515 // we are not recursing on that node by checking for undef here.
4516 if (IdxVal == 0 && Result.getValueType().is256BitVector() &&
4517 Result.getOpcode() != ISD::UNDEF) {
4518 EVT ResultVT = Result.getValueType();
4519 SDValue ZeroIndex = DAG.getIntPtrConstant(0, dl);
4520 SDValue Undef = DAG.getUNDEF(ResultVT);
4521 SDValue Vec256 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Undef,
4524 // The blend instruction, and therefore its mask, depend on the data type.
4525 MVT ScalarType = ResultVT.getVectorElementType().getSimpleVT();
4526 if (ScalarType.isFloatingPoint()) {
4527 // Choose either vblendps (float) or vblendpd (double).
4528 unsigned ScalarSize = ScalarType.getSizeInBits();
4529 assert((ScalarSize == 64 || ScalarSize == 32) && "Unknown float type");
4530 unsigned MaskVal = (ScalarSize == 64) ? 0x03 : 0x0f;
4531 SDValue Mask = DAG.getConstant(MaskVal, dl, MVT::i8);
4532 return DAG.getNode(X86ISD::BLENDI, dl, ResultVT, Result, Vec256, Mask);
4535 const X86Subtarget &Subtarget =
4536 static_cast<const X86Subtarget &>(DAG.getSubtarget());
4538 // AVX2 is needed for 256-bit integer blend support.
4539 // Integers must be cast to 32-bit because there is only vpblendd;
4540 // vpblendw can't be used for this because it has a handicapped mask.
4542 // If we don't have AVX2, then cast to float. Using a wrong domain blend
4543 // is still more efficient than using the wrong domain vinsertf128 that
4544 // will be created by InsertSubVector().
4545 MVT CastVT = Subtarget.hasAVX2() ? MVT::v8i32 : MVT::v8f32;
4547 SDValue Mask = DAG.getConstant(0x0f, dl, MVT::i8);
4548 Vec256 = DAG.getBitcast(CastVT, Vec256);
4549 Vec256 = DAG.getNode(X86ISD::BLENDI, dl, CastVT, Result, Vec256, Mask);
4550 return DAG.getBitcast(ResultVT, Vec256);
4553 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
4556 static SDValue Insert256BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4557 SelectionDAG &DAG, SDLoc dl) {
4558 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
4559 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
4562 /// Insert i1-subvector to i1-vector.
4563 static SDValue Insert1BitVector(SDValue Op, SelectionDAG &DAG) {
4566 SDValue Vec = Op.getOperand(0);
4567 SDValue SubVec = Op.getOperand(1);
4568 SDValue Idx = Op.getOperand(2);
4570 if (!isa<ConstantSDNode>(Idx))
4573 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
4574 if (IdxVal == 0 && Vec.isUndef()) // the operation is legal
4577 MVT OpVT = Op.getSimpleValueType();
4578 MVT SubVecVT = SubVec.getSimpleValueType();
4579 unsigned NumElems = OpVT.getVectorNumElements();
4580 unsigned SubVecNumElems = SubVecVT.getVectorNumElements();
4582 assert(IdxVal + SubVecNumElems <= NumElems &&
4583 IdxVal % SubVecVT.getSizeInBits() == 0 &&
4584 "Unexpected index value in INSERT_SUBVECTOR");
4586 // There are 3 possible cases:
4587 // 1. Subvector should be inserted in the lower part (IdxVal == 0)
4588 // 2. Subvector should be inserted in the upper part
4589 // (IdxVal + SubVecNumElems == NumElems)
4590 // 3. Subvector should be inserted in the middle (for example v2i1
4591 // to v16i1, index 2)
4593 SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
4594 SDValue Undef = DAG.getUNDEF(OpVT);
4595 SDValue WideSubVec =
4596 DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, Undef, SubVec, ZeroIdx);
4598 return DAG.getNode(X86ISD::VSHLI, dl, OpVT, WideSubVec,
4599 DAG.getConstant(IdxVal, dl, MVT::i8));
4601 if (ISD::isBuildVectorAllZeros(Vec.getNode())) {
4602 unsigned ShiftLeft = NumElems - SubVecNumElems;
4603 unsigned ShiftRight = NumElems - SubVecNumElems - IdxVal;
4604 WideSubVec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, WideSubVec,
4605 DAG.getConstant(ShiftLeft, dl, MVT::i8));
4606 return ShiftRight ? DAG.getNode(X86ISD::VSRLI, dl, OpVT, WideSubVec,
4607 DAG.getConstant(ShiftRight, dl, MVT::i8)) : WideSubVec;
4611 // Zero lower bits of the Vec
4612 SDValue ShiftBits = DAG.getConstant(SubVecNumElems, dl, MVT::i8);
4613 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
4614 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
4615 // Merge them together
4616 return DAG.getNode(ISD::OR, dl, OpVT, Vec, WideSubVec);
4619 // Simple case when we put subvector in the upper part
4620 if (IdxVal + SubVecNumElems == NumElems) {
4621 // Zero upper bits of the Vec
4622 WideSubVec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec,
4623 DAG.getConstant(IdxVal, dl, MVT::i8));
4624 SDValue ShiftBits = DAG.getConstant(SubVecNumElems, dl, MVT::i8);
4625 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
4626 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
4627 return DAG.getNode(ISD::OR, dl, OpVT, Vec, WideSubVec);
4629 // Subvector should be inserted in the middle - use shuffle
4630 SmallVector<int, 64> Mask;
4631 for (unsigned i = 0; i < NumElems; ++i)
4632 Mask.push_back(i >= IdxVal && i < IdxVal + SubVecNumElems ?
4634 return DAG.getVectorShuffle(OpVT, dl, WideSubVec, Vec, Mask);
4637 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
4638 /// instructions. This is used because creating CONCAT_VECTOR nodes of
4639 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
4640 /// large BUILD_VECTORS.
4641 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
4642 unsigned NumElems, SelectionDAG &DAG,
4644 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
4645 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
4648 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
4649 unsigned NumElems, SelectionDAG &DAG,
4651 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
4652 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
4655 /// Returns a vector of specified type with all bits set.
4656 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4657 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4658 /// Then bitcast to their original type, ensuring they get CSE'd.
4659 static SDValue getOnesVector(EVT VT, const X86Subtarget *Subtarget,
4660 SelectionDAG &DAG, SDLoc dl) {
4661 assert(VT.isVector() && "Expected a vector type");
4663 SDValue Cst = DAG.getConstant(~0U, dl, MVT::i32);
4665 if (VT.is512BitVector()) {
4666 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4667 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4668 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
4669 } else if (VT.is256BitVector()) {
4670 if (Subtarget->hasInt256()) { // AVX2
4671 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4672 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4674 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4675 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4677 } else if (VT.is128BitVector()) {
4678 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4680 llvm_unreachable("Unexpected vector type");
4682 return DAG.getBitcast(VT, Vec);
4685 /// Returns a vector_shuffle node for an unpackl operation.
4686 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4688 unsigned NumElems = VT.getVectorNumElements();
4689 SmallVector<int, 8> Mask;
4690 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4692 Mask.push_back(i + NumElems);
4694 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4697 /// Returns a vector_shuffle node for an unpackh operation.
4698 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4700 unsigned NumElems = VT.getVectorNumElements();
4701 SmallVector<int, 8> Mask;
4702 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
4703 Mask.push_back(i + Half);
4704 Mask.push_back(i + NumElems + Half);
4706 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4709 /// Return a vector_shuffle of the specified vector of zero or undef vector.
4710 /// This produces a shuffle where the low element of V2 is swizzled into the
4711 /// zero/undef vector, landing at element Idx.
4712 /// This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4713 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4715 const X86Subtarget *Subtarget,
4716 SelectionDAG &DAG) {
4717 MVT VT = V2.getSimpleValueType();
4719 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
4720 unsigned NumElems = VT.getVectorNumElements();
4721 SmallVector<int, 16> MaskVec;
4722 for (unsigned i = 0; i != NumElems; ++i)
4723 // If this is the insertion idx, put the low elt of V2 here.
4724 MaskVec.push_back(i == Idx ? NumElems : i);
4725 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
4728 /// Calculates the shuffle mask corresponding to the target-specific opcode.
4729 /// Returns true if the Mask could be calculated. Sets IsUnary to true if only
4730 /// uses one source. Note that this will set IsUnary for shuffles which use a
4731 /// single input multiple times, and in those cases it will
4732 /// adjust the mask to only have indices within that single input.
4733 /// FIXME: Add support for Decode*Mask functions that return SM_SentinelZero.
4734 static bool getTargetShuffleMask(SDNode *N, MVT VT,
4735 SmallVectorImpl<int> &Mask, bool &IsUnary) {
4736 unsigned NumElems = VT.getVectorNumElements();
4740 bool IsFakeUnary = false;
4741 switch(N->getOpcode()) {
4742 case X86ISD::BLENDI:
4743 ImmN = N->getOperand(N->getNumOperands()-1);
4744 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4747 ImmN = N->getOperand(N->getNumOperands()-1);
4748 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4749 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4751 case X86ISD::UNPCKH:
4752 DecodeUNPCKHMask(VT, Mask);
4753 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4755 case X86ISD::UNPCKL:
4756 DecodeUNPCKLMask(VT, Mask);
4757 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4759 case X86ISD::MOVHLPS:
4760 DecodeMOVHLPSMask(NumElems, Mask);
4761 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4763 case X86ISD::MOVLHPS:
4764 DecodeMOVLHPSMask(NumElems, Mask);
4765 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4767 case X86ISD::PALIGNR:
4768 ImmN = N->getOperand(N->getNumOperands()-1);
4769 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4771 case X86ISD::PSHUFD:
4772 case X86ISD::VPERMILPI:
4773 ImmN = N->getOperand(N->getNumOperands()-1);
4774 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4777 case X86ISD::PSHUFHW:
4778 ImmN = N->getOperand(N->getNumOperands()-1);
4779 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4782 case X86ISD::PSHUFLW:
4783 ImmN = N->getOperand(N->getNumOperands()-1);
4784 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4787 case X86ISD::PSHUFB: {
4789 SDValue MaskNode = N->getOperand(1);
4790 while (MaskNode->getOpcode() == ISD::BITCAST)
4791 MaskNode = MaskNode->getOperand(0);
4793 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4794 // If we have a build-vector, then things are easy.
4795 MVT VT = MaskNode.getSimpleValueType();
4796 assert(VT.isVector() &&
4797 "Can't produce a non-vector with a build_vector!");
4798 if (!VT.isInteger())
4801 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
4803 SmallVector<uint64_t, 32> RawMask;
4804 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
4805 SDValue Op = MaskNode->getOperand(i);
4806 if (Op->getOpcode() == ISD::UNDEF) {
4807 RawMask.push_back((uint64_t)SM_SentinelUndef);
4810 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
4813 APInt MaskElement = CN->getAPIntValue();
4815 // We now have to decode the element which could be any integer size and
4816 // extract each byte of it.
4817 for (int j = 0; j < NumBytesPerElement; ++j) {
4818 // Note that this is x86 and so always little endian: the low byte is
4819 // the first byte of the mask.
4820 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
4821 MaskElement = MaskElement.lshr(8);
4824 DecodePSHUFBMask(RawMask, Mask);
4828 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4832 SDValue Ptr = MaskLoad->getBasePtr();
4833 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4834 Ptr->getOpcode() == X86ISD::WrapperRIP)
4835 Ptr = Ptr->getOperand(0);
4837 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4838 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4841 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
4842 DecodePSHUFBMask(C, Mask);
4850 case X86ISD::VPERMI:
4851 ImmN = N->getOperand(N->getNumOperands()-1);
4852 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4857 DecodeScalarMoveMask(VT, /* IsLoad */ false, Mask);
4859 case X86ISD::VPERM2X128:
4860 ImmN = N->getOperand(N->getNumOperands()-1);
4861 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4862 if (Mask.empty()) return false;
4863 // Mask only contains negative index if an element is zero.
4864 if (std::any_of(Mask.begin(), Mask.end(),
4865 [](int M){ return M == SM_SentinelZero; }))
4868 case X86ISD::MOVSLDUP:
4869 DecodeMOVSLDUPMask(VT, Mask);
4872 case X86ISD::MOVSHDUP:
4873 DecodeMOVSHDUPMask(VT, Mask);
4876 case X86ISD::MOVDDUP:
4877 DecodeMOVDDUPMask(VT, Mask);
4880 case X86ISD::MOVLHPD:
4881 case X86ISD::MOVLPD:
4882 case X86ISD::MOVLPS:
4883 // Not yet implemented
4885 case X86ISD::VPERMV: {
4887 SDValue MaskNode = N->getOperand(0);
4888 while (MaskNode->getOpcode() == ISD::BITCAST)
4889 MaskNode = MaskNode->getOperand(0);
4891 unsigned MaskLoBits = Log2_64(VT.getVectorNumElements());
4892 SmallVector<uint64_t, 32> RawMask;
4893 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4894 // If we have a build-vector, then things are easy.
4895 assert(MaskNode.getSimpleValueType().isInteger() &&
4896 MaskNode.getSimpleValueType().getVectorNumElements() ==
4897 VT.getVectorNumElements());
4899 for (unsigned i = 0; i < MaskNode->getNumOperands(); ++i) {
4900 SDValue Op = MaskNode->getOperand(i);
4901 if (Op->getOpcode() == ISD::UNDEF)
4902 RawMask.push_back((uint64_t)SM_SentinelUndef);
4903 else if (isa<ConstantSDNode>(Op)) {
4904 APInt MaskElement = cast<ConstantSDNode>(Op)->getAPIntValue();
4905 RawMask.push_back(MaskElement.getLoBits(MaskLoBits).getZExtValue());
4909 DecodeVPERMVMask(RawMask, Mask);
4912 if (MaskNode->getOpcode() == X86ISD::VBROADCAST) {
4913 unsigned NumEltsInMask = MaskNode->getNumOperands();
4914 MaskNode = MaskNode->getOperand(0);
4915 auto *CN = dyn_cast<ConstantSDNode>(MaskNode);
4917 APInt MaskEltValue = CN->getAPIntValue();
4918 for (unsigned i = 0; i < NumEltsInMask; ++i)
4919 RawMask.push_back(MaskEltValue.getLoBits(MaskLoBits).getZExtValue());
4920 DecodeVPERMVMask(RawMask, Mask);
4923 // It may be a scalar load
4926 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4930 SDValue Ptr = MaskLoad->getBasePtr();
4931 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4932 Ptr->getOpcode() == X86ISD::WrapperRIP)
4933 Ptr = Ptr->getOperand(0);
4935 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4936 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4939 auto *C = dyn_cast<Constant>(MaskCP->getConstVal());
4941 DecodeVPERMVMask(C, VT, Mask);
4948 case X86ISD::VPERMV3: {
4950 SDValue MaskNode = N->getOperand(1);
4951 while (MaskNode->getOpcode() == ISD::BITCAST)
4952 MaskNode = MaskNode->getOperand(1);
4954 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4955 // If we have a build-vector, then things are easy.
4956 assert(MaskNode.getSimpleValueType().isInteger() &&
4957 MaskNode.getSimpleValueType().getVectorNumElements() ==
4958 VT.getVectorNumElements());
4960 SmallVector<uint64_t, 32> RawMask;
4961 unsigned MaskLoBits = Log2_64(VT.getVectorNumElements()*2);
4963 for (unsigned i = 0; i < MaskNode->getNumOperands(); ++i) {
4964 SDValue Op = MaskNode->getOperand(i);
4965 if (Op->getOpcode() == ISD::UNDEF)
4966 RawMask.push_back((uint64_t)SM_SentinelUndef);
4968 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
4971 APInt MaskElement = CN->getAPIntValue();
4972 RawMask.push_back(MaskElement.getLoBits(MaskLoBits).getZExtValue());
4975 DecodeVPERMV3Mask(RawMask, Mask);
4979 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4983 SDValue Ptr = MaskLoad->getBasePtr();
4984 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4985 Ptr->getOpcode() == X86ISD::WrapperRIP)
4986 Ptr = Ptr->getOperand(0);
4988 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4989 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4992 auto *C = dyn_cast<Constant>(MaskCP->getConstVal());
4994 DecodeVPERMV3Mask(C, VT, Mask);
5001 default: llvm_unreachable("unknown target shuffle node");
5004 // If we have a fake unary shuffle, the shuffle mask is spread across two
5005 // inputs that are actually the same node. Re-map the mask to always point
5006 // into the first input.
5009 if (M >= (int)Mask.size())
5015 /// Returns the scalar element that will make up the ith
5016 /// element of the result of the vector shuffle.
5017 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
5020 return SDValue(); // Limit search depth.
5022 SDValue V = SDValue(N, 0);
5023 EVT VT = V.getValueType();
5024 unsigned Opcode = V.getOpcode();
5026 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
5027 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
5028 int Elt = SV->getMaskElt(Index);
5031 return DAG.getUNDEF(VT.getVectorElementType());
5033 unsigned NumElems = VT.getVectorNumElements();
5034 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
5035 : SV->getOperand(1);
5036 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
5039 // Recurse into target specific vector shuffles to find scalars.
5040 if (isTargetShuffle(Opcode)) {
5041 MVT ShufVT = V.getSimpleValueType();
5042 unsigned NumElems = ShufVT.getVectorNumElements();
5043 SmallVector<int, 16> ShuffleMask;
5046 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
5049 int Elt = ShuffleMask[Index];
5051 return DAG.getUNDEF(ShufVT.getVectorElementType());
5053 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
5055 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
5059 // Actual nodes that may contain scalar elements
5060 if (Opcode == ISD::BITCAST) {
5061 V = V.getOperand(0);
5062 EVT SrcVT = V.getValueType();
5063 unsigned NumElems = VT.getVectorNumElements();
5065 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5069 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5070 return (Index == 0) ? V.getOperand(0)
5071 : DAG.getUNDEF(VT.getVectorElementType());
5073 if (V.getOpcode() == ISD::BUILD_VECTOR)
5074 return V.getOperand(Index);
5079 /// Custom lower build_vector of v16i8.
5080 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5081 unsigned NumNonZero, unsigned NumZero,
5083 const X86Subtarget* Subtarget,
5084 const TargetLowering &TLI) {
5092 // SSE4.1 - use PINSRB to insert each byte directly.
5093 if (Subtarget->hasSSE41()) {
5094 for (unsigned i = 0; i < 16; ++i) {
5095 bool isNonZero = (NonZeros & (1 << i)) != 0;
5099 V = getZeroVector(MVT::v16i8, Subtarget, DAG, dl);
5101 V = DAG.getUNDEF(MVT::v16i8);
5104 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5105 MVT::v16i8, V, Op.getOperand(i),
5106 DAG.getIntPtrConstant(i, dl));
5113 // Pre-SSE4.1 - merge byte pairs and insert with PINSRW.
5114 for (unsigned i = 0; i < 16; ++i) {
5115 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5116 if (ThisIsNonZero && First) {
5118 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5120 V = DAG.getUNDEF(MVT::v8i16);
5125 SDValue ThisElt, LastElt;
5126 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5127 if (LastIsNonZero) {
5128 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5129 MVT::i16, Op.getOperand(i-1));
5131 if (ThisIsNonZero) {
5132 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5133 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5134 ThisElt, DAG.getConstant(8, dl, MVT::i8));
5136 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5140 if (ThisElt.getNode())
5141 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5142 DAG.getIntPtrConstant(i/2, dl));
5146 return DAG.getBitcast(MVT::v16i8, V);
5149 /// Custom lower build_vector of v8i16.
5150 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5151 unsigned NumNonZero, unsigned NumZero,
5153 const X86Subtarget* Subtarget,
5154 const TargetLowering &TLI) {
5161 for (unsigned i = 0; i < 8; ++i) {
5162 bool isNonZero = (NonZeros & (1 << i)) != 0;
5166 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5168 V = DAG.getUNDEF(MVT::v8i16);
5171 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5172 MVT::v8i16, V, Op.getOperand(i),
5173 DAG.getIntPtrConstant(i, dl));
5180 /// Custom lower build_vector of v4i32 or v4f32.
5181 static SDValue LowerBuildVectorv4x32(SDValue Op, SelectionDAG &DAG,
5182 const X86Subtarget *Subtarget,
5183 const TargetLowering &TLI) {
5184 // Find all zeroable elements.
5185 std::bitset<4> Zeroable;
5186 for (int i=0; i < 4; ++i) {
5187 SDValue Elt = Op->getOperand(i);
5188 Zeroable[i] = (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt));
5190 assert(Zeroable.size() - Zeroable.count() > 1 &&
5191 "We expect at least two non-zero elements!");
5193 // We only know how to deal with build_vector nodes where elements are either
5194 // zeroable or extract_vector_elt with constant index.
5195 SDValue FirstNonZero;
5196 unsigned FirstNonZeroIdx;
5197 for (unsigned i=0; i < 4; ++i) {
5200 SDValue Elt = Op->getOperand(i);
5201 if (Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5202 !isa<ConstantSDNode>(Elt.getOperand(1)))
5204 // Make sure that this node is extracting from a 128-bit vector.
5205 MVT VT = Elt.getOperand(0).getSimpleValueType();
5206 if (!VT.is128BitVector())
5208 if (!FirstNonZero.getNode()) {
5210 FirstNonZeroIdx = i;
5214 assert(FirstNonZero.getNode() && "Unexpected build vector of all zeros!");
5215 SDValue V1 = FirstNonZero.getOperand(0);
5216 MVT VT = V1.getSimpleValueType();
5218 // See if this build_vector can be lowered as a blend with zero.
5220 unsigned EltMaskIdx, EltIdx;
5222 for (EltIdx = 0; EltIdx < 4; ++EltIdx) {
5223 if (Zeroable[EltIdx]) {
5224 // The zero vector will be on the right hand side.
5225 Mask[EltIdx] = EltIdx+4;
5229 Elt = Op->getOperand(EltIdx);
5230 // By construction, Elt is a EXTRACT_VECTOR_ELT with constant index.
5231 EltMaskIdx = cast<ConstantSDNode>(Elt.getOperand(1))->getZExtValue();
5232 if (Elt.getOperand(0) != V1 || EltMaskIdx != EltIdx)
5234 Mask[EltIdx] = EltIdx;
5238 // Let the shuffle legalizer deal with blend operations.
5239 SDValue VZero = getZeroVector(VT, Subtarget, DAG, SDLoc(Op));
5240 if (V1.getSimpleValueType() != VT)
5241 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), VT, V1);
5242 return DAG.getVectorShuffle(VT, SDLoc(V1), V1, VZero, &Mask[0]);
5245 // See if we can lower this build_vector to a INSERTPS.
5246 if (!Subtarget->hasSSE41())
5249 SDValue V2 = Elt.getOperand(0);
5250 if (Elt == FirstNonZero && EltIdx == FirstNonZeroIdx)
5253 bool CanFold = true;
5254 for (unsigned i = EltIdx + 1; i < 4 && CanFold; ++i) {
5258 SDValue Current = Op->getOperand(i);
5259 SDValue SrcVector = Current->getOperand(0);
5262 CanFold = SrcVector == V1 &&
5263 cast<ConstantSDNode>(Current.getOperand(1))->getZExtValue() == i;
5269 assert(V1.getNode() && "Expected at least two non-zero elements!");
5270 if (V1.getSimpleValueType() != MVT::v4f32)
5271 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), MVT::v4f32, V1);
5272 if (V2.getSimpleValueType() != MVT::v4f32)
5273 V2 = DAG.getNode(ISD::BITCAST, SDLoc(V2), MVT::v4f32, V2);
5275 // Ok, we can emit an INSERTPS instruction.
5276 unsigned ZMask = Zeroable.to_ulong();
5278 unsigned InsertPSMask = EltMaskIdx << 6 | EltIdx << 4 | ZMask;
5279 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
5281 SDValue Result = DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
5282 DAG.getIntPtrConstant(InsertPSMask, DL));
5283 return DAG.getBitcast(VT, Result);
5286 /// Return a vector logical shift node.
5287 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5288 unsigned NumBits, SelectionDAG &DAG,
5289 const TargetLowering &TLI, SDLoc dl) {
5290 assert(VT.is128BitVector() && "Unknown type for VShift");
5291 MVT ShVT = MVT::v2i64;
5292 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5293 SrcOp = DAG.getBitcast(ShVT, SrcOp);
5294 MVT ScalarShiftTy = TLI.getScalarShiftAmountTy(DAG.getDataLayout(), VT);
5295 assert(NumBits % 8 == 0 && "Only support byte sized shifts");
5296 SDValue ShiftVal = DAG.getConstant(NumBits/8, dl, ScalarShiftTy);
5297 return DAG.getBitcast(VT, DAG.getNode(Opc, dl, ShVT, SrcOp, ShiftVal));
5301 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5303 // Check if the scalar load can be widened into a vector load. And if
5304 // the address is "base + cst" see if the cst can be "absorbed" into
5305 // the shuffle mask.
5306 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5307 SDValue Ptr = LD->getBasePtr();
5308 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5310 EVT PVT = LD->getValueType(0);
5311 if (PVT != MVT::i32 && PVT != MVT::f32)
5316 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5317 FI = FINode->getIndex();
5319 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5320 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5321 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5322 Offset = Ptr.getConstantOperandVal(1);
5323 Ptr = Ptr.getOperand(0);
5328 // FIXME: 256-bit vector instructions don't require a strict alignment,
5329 // improve this code to support it better.
5330 unsigned RequiredAlign = VT.getSizeInBits()/8;
5331 SDValue Chain = LD->getChain();
5332 // Make sure the stack object alignment is at least 16 or 32.
5333 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5334 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5335 if (MFI->isFixedObjectIndex(FI)) {
5336 // Can't change the alignment. FIXME: It's possible to compute
5337 // the exact stack offset and reference FI + adjust offset instead.
5338 // If someone *really* cares about this. That's the way to implement it.
5341 MFI->setObjectAlignment(FI, RequiredAlign);
5345 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5346 // Ptr + (Offset & ~15).
5349 if ((Offset % RequiredAlign) & 3)
5351 int64_t StartOffset = Offset & ~int64_t(RequiredAlign - 1);
5354 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
5355 DAG.getConstant(StartOffset, DL, Ptr.getValueType()));
5358 int EltNo = (Offset - StartOffset) >> 2;
5359 unsigned NumElems = VT.getVectorNumElements();
5361 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5362 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5363 LD->getPointerInfo().getWithOffset(StartOffset),
5364 false, false, false, 0);
5366 SmallVector<int, 8> Mask(NumElems, EltNo);
5368 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5374 /// Given the initializing elements 'Elts' of a vector of type 'VT', see if the
5375 /// elements can be replaced by a single large load which has the same value as
5376 /// a build_vector or insert_subvector whose loaded operands are 'Elts'.
5378 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5380 /// FIXME: we'd also like to handle the case where the last elements are zero
5381 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5382 /// There's even a handy isZeroNode for that purpose.
5383 static SDValue EltsFromConsecutiveLoads(EVT VT, ArrayRef<SDValue> Elts,
5384 SDLoc &DL, SelectionDAG &DAG,
5385 bool isAfterLegalize) {
5386 unsigned NumElems = Elts.size();
5388 LoadSDNode *LDBase = nullptr;
5389 unsigned LastLoadedElt = -1U;
5391 // For each element in the initializer, see if we've found a load or an undef.
5392 // If we don't find an initial load element, or later load elements are
5393 // non-consecutive, bail out.
5394 for (unsigned i = 0; i < NumElems; ++i) {
5395 SDValue Elt = Elts[i];
5396 // Look through a bitcast.
5397 if (Elt.getNode() && Elt.getOpcode() == ISD::BITCAST)
5398 Elt = Elt.getOperand(0);
5399 if (!Elt.getNode() ||
5400 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5403 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5405 LDBase = cast<LoadSDNode>(Elt.getNode());
5409 if (Elt.getOpcode() == ISD::UNDEF)
5412 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5413 EVT LdVT = Elt.getValueType();
5414 // Each loaded element must be the correct fractional portion of the
5415 // requested vector load.
5416 if (LdVT.getSizeInBits() != VT.getSizeInBits() / NumElems)
5418 if (!DAG.isConsecutiveLoad(LD, LDBase, LdVT.getSizeInBits() / 8, i))
5423 // If we have found an entire vector of loads and undefs, then return a large
5424 // load of the entire vector width starting at the base pointer. If we found
5425 // consecutive loads for the low half, generate a vzext_load node.
5426 if (LastLoadedElt == NumElems - 1) {
5427 assert(LDBase && "Did not find base load for merging consecutive loads");
5428 EVT EltVT = LDBase->getValueType(0);
5429 // Ensure that the input vector size for the merged loads matches the
5430 // cumulative size of the input elements.
5431 if (VT.getSizeInBits() != EltVT.getSizeInBits() * NumElems)
5434 if (isAfterLegalize &&
5435 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
5438 SDValue NewLd = SDValue();
5440 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5441 LDBase->getPointerInfo(), LDBase->isVolatile(),
5442 LDBase->isNonTemporal(), LDBase->isInvariant(),
5443 LDBase->getAlignment());
5445 if (LDBase->hasAnyUseOfValue(1)) {
5446 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5448 SDValue(NewLd.getNode(), 1));
5449 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5450 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5451 SDValue(NewLd.getNode(), 1));
5457 //TODO: The code below fires only for for loading the low v2i32 / v2f32
5458 //of a v4i32 / v4f32. It's probably worth generalizing.
5459 EVT EltVT = VT.getVectorElementType();
5460 if (NumElems == 4 && LastLoadedElt == 1 && (EltVT.getSizeInBits() == 32) &&
5461 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5462 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5463 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5465 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
5466 LDBase->getPointerInfo(),
5467 LDBase->getAlignment(),
5468 false/*isVolatile*/, true/*ReadMem*/,
5471 // Make sure the newly-created LOAD is in the same position as LDBase in
5472 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5473 // update uses of LDBase's output chain to use the TokenFactor.
5474 if (LDBase->hasAnyUseOfValue(1)) {
5475 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5476 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5477 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5478 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5479 SDValue(ResNode.getNode(), 1));
5482 return DAG.getBitcast(VT, ResNode);
5487 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
5488 /// to generate a splat value for the following cases:
5489 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
5490 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
5491 /// a scalar load, or a constant.
5492 /// The VBROADCAST node is returned when a pattern is found,
5493 /// or SDValue() otherwise.
5494 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
5495 SelectionDAG &DAG) {
5496 // VBROADCAST requires AVX.
5497 // TODO: Splats could be generated for non-AVX CPUs using SSE
5498 // instructions, but there's less potential gain for only 128-bit vectors.
5499 if (!Subtarget->hasAVX())
5502 MVT VT = Op.getSimpleValueType();
5505 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
5506 "Unsupported vector type for broadcast.");
5511 switch (Op.getOpcode()) {
5513 // Unknown pattern found.
5516 case ISD::BUILD_VECTOR: {
5517 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
5518 BitVector UndefElements;
5519 SDValue Splat = BVOp->getSplatValue(&UndefElements);
5521 // We need a splat of a single value to use broadcast, and it doesn't
5522 // make any sense if the value is only in one element of the vector.
5523 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
5527 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5528 Ld.getOpcode() == ISD::ConstantFP);
5530 // Make sure that all of the users of a non-constant load are from the
5531 // BUILD_VECTOR node.
5532 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
5537 case ISD::VECTOR_SHUFFLE: {
5538 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5540 // Shuffles must have a splat mask where the first element is
5542 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
5545 SDValue Sc = Op.getOperand(0);
5546 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
5547 Sc.getOpcode() != ISD::BUILD_VECTOR) {
5549 if (!Subtarget->hasInt256())
5552 // Use the register form of the broadcast instruction available on AVX2.
5553 if (VT.getSizeInBits() >= 256)
5554 Sc = Extract128BitVector(Sc, 0, DAG, dl);
5555 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
5558 Ld = Sc.getOperand(0);
5559 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5560 Ld.getOpcode() == ISD::ConstantFP);
5562 // The scalar_to_vector node and the suspected
5563 // load node must have exactly one user.
5564 // Constants may have multiple users.
5566 // AVX-512 has register version of the broadcast
5567 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
5568 Ld.getValueType().getSizeInBits() >= 32;
5569 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
5576 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5577 bool IsGE256 = (VT.getSizeInBits() >= 256);
5579 // When optimizing for size, generate up to 5 extra bytes for a broadcast
5580 // instruction to save 8 or more bytes of constant pool data.
5581 // TODO: If multiple splats are generated to load the same constant,
5582 // it may be detrimental to overall size. There needs to be a way to detect
5583 // that condition to know if this is truly a size win.
5584 bool OptForSize = DAG.getMachineFunction().getFunction()->optForSize();
5586 // Handle broadcasting a single constant scalar from the constant pool
5588 // On Sandybridge (no AVX2), it is still better to load a constant vector
5589 // from the constant pool and not to broadcast it from a scalar.
5590 // But override that restriction when optimizing for size.
5591 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
5592 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
5593 EVT CVT = Ld.getValueType();
5594 assert(!CVT.isVector() && "Must not broadcast a vector type");
5596 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
5597 // For size optimization, also splat v2f64 and v2i64, and for size opt
5598 // with AVX2, also splat i8 and i16.
5599 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
5600 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
5601 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
5602 const Constant *C = nullptr;
5603 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
5604 C = CI->getConstantIntValue();
5605 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
5606 C = CF->getConstantFPValue();
5608 assert(C && "Invalid constant type");
5610 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5612 DAG.getConstantPool(C, TLI.getPointerTy(DAG.getDataLayout()));
5613 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
5615 CVT, dl, DAG.getEntryNode(), CP,
5616 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), false,
5617 false, false, Alignment);
5619 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5623 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
5625 // Handle AVX2 in-register broadcasts.
5626 if (!IsLoad && Subtarget->hasInt256() &&
5627 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
5628 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5630 // The scalar source must be a normal load.
5634 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
5635 (Subtarget->hasVLX() && ScalarSize == 64))
5636 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5638 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5639 // double since there is no vbroadcastsd xmm
5640 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
5641 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
5642 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5645 // Unsupported broadcast.
5649 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
5650 /// underlying vector and index.
5652 /// Modifies \p ExtractedFromVec to the real vector and returns the real
5654 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
5656 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
5657 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
5660 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
5662 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
5664 // (extract_vector_elt (vector_shuffle<2,u,u,u>
5665 // (extract_subvector (v8f32 %vreg0), Constant<4>),
5668 // In this case the vector is the extract_subvector expression and the index
5669 // is 2, as specified by the shuffle.
5670 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
5671 SDValue ShuffleVec = SVOp->getOperand(0);
5672 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
5673 assert(ShuffleVecVT.getVectorElementType() ==
5674 ExtractedFromVec.getSimpleValueType().getVectorElementType());
5676 int ShuffleIdx = SVOp->getMaskElt(Idx);
5677 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
5678 ExtractedFromVec = ShuffleVec;
5684 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
5685 MVT VT = Op.getSimpleValueType();
5687 // Skip if insert_vec_elt is not supported.
5688 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5689 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
5693 unsigned NumElems = Op.getNumOperands();
5697 SmallVector<unsigned, 4> InsertIndices;
5698 SmallVector<int, 8> Mask(NumElems, -1);
5700 for (unsigned i = 0; i != NumElems; ++i) {
5701 unsigned Opc = Op.getOperand(i).getOpcode();
5703 if (Opc == ISD::UNDEF)
5706 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
5707 // Quit if more than 1 elements need inserting.
5708 if (InsertIndices.size() > 1)
5711 InsertIndices.push_back(i);
5715 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
5716 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
5717 // Quit if non-constant index.
5718 if (!isa<ConstantSDNode>(ExtIdx))
5720 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
5722 // Quit if extracted from vector of different type.
5723 if (ExtractedFromVec.getValueType() != VT)
5726 if (!VecIn1.getNode())
5727 VecIn1 = ExtractedFromVec;
5728 else if (VecIn1 != ExtractedFromVec) {
5729 if (!VecIn2.getNode())
5730 VecIn2 = ExtractedFromVec;
5731 else if (VecIn2 != ExtractedFromVec)
5732 // Quit if more than 2 vectors to shuffle
5736 if (ExtractedFromVec == VecIn1)
5738 else if (ExtractedFromVec == VecIn2)
5739 Mask[i] = Idx + NumElems;
5742 if (!VecIn1.getNode())
5745 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
5746 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
5747 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
5748 unsigned Idx = InsertIndices[i];
5749 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
5750 DAG.getIntPtrConstant(Idx, DL));
5756 static SDValue ConvertI1VectorToInteger(SDValue Op, SelectionDAG &DAG) {
5757 assert(ISD::isBuildVectorOfConstantSDNodes(Op.getNode()) &&
5758 Op.getScalarValueSizeInBits() == 1 &&
5759 "Can not convert non-constant vector");
5760 uint64_t Immediate = 0;
5761 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5762 SDValue In = Op.getOperand(idx);
5763 if (In.getOpcode() != ISD::UNDEF)
5764 Immediate |= cast<ConstantSDNode>(In)->getZExtValue() << idx;
5768 MVT::getIntegerVT(std::max((int)Op.getValueType().getSizeInBits(), 8));
5769 return DAG.getConstant(Immediate, dl, VT);
5771 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
5773 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
5775 MVT VT = Op.getSimpleValueType();
5776 assert((VT.getVectorElementType() == MVT::i1) &&
5777 "Unexpected type in LowerBUILD_VECTORvXi1!");
5780 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5781 SDValue Cst = DAG.getTargetConstant(0, dl, MVT::i1);
5782 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5783 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5786 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5787 SDValue Cst = DAG.getTargetConstant(1, dl, MVT::i1);
5788 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5789 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5792 if (ISD::isBuildVectorOfConstantSDNodes(Op.getNode())) {
5793 SDValue Imm = ConvertI1VectorToInteger(Op, DAG);
5794 if (Imm.getValueSizeInBits() == VT.getSizeInBits())
5795 return DAG.getBitcast(VT, Imm);
5796 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, Imm);
5797 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, ExtVec,
5798 DAG.getIntPtrConstant(0, dl));
5801 // Vector has one or more non-const elements
5802 uint64_t Immediate = 0;
5803 SmallVector<unsigned, 16> NonConstIdx;
5804 bool IsSplat = true;
5805 bool HasConstElts = false;
5807 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5808 SDValue In = Op.getOperand(idx);
5809 if (In.getOpcode() == ISD::UNDEF)
5811 if (!isa<ConstantSDNode>(In))
5812 NonConstIdx.push_back(idx);
5814 Immediate |= cast<ConstantSDNode>(In)->getZExtValue() << idx;
5815 HasConstElts = true;
5819 else if (In != Op.getOperand(SplatIdx))
5823 // for splat use " (select i1 splat_elt, all-ones, all-zeroes)"
5825 return DAG.getNode(ISD::SELECT, dl, VT, Op.getOperand(SplatIdx),
5826 DAG.getConstant(1, dl, VT),
5827 DAG.getConstant(0, dl, VT));
5829 // insert elements one by one
5833 MVT ImmVT = MVT::getIntegerVT(std::max((int)VT.getSizeInBits(), 8));
5834 Imm = DAG.getConstant(Immediate, dl, ImmVT);
5836 else if (HasConstElts)
5837 Imm = DAG.getConstant(0, dl, VT);
5839 Imm = DAG.getUNDEF(VT);
5840 if (Imm.getValueSizeInBits() == VT.getSizeInBits())
5841 DstVec = DAG.getBitcast(VT, Imm);
5843 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, Imm);
5844 DstVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, ExtVec,
5845 DAG.getIntPtrConstant(0, dl));
5848 for (unsigned i = 0; i < NonConstIdx.size(); ++i) {
5849 unsigned InsertIdx = NonConstIdx[i];
5850 DstVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
5851 Op.getOperand(InsertIdx),
5852 DAG.getIntPtrConstant(InsertIdx, dl));
5857 /// \brief Return true if \p N implements a horizontal binop and return the
5858 /// operands for the horizontal binop into V0 and V1.
5860 /// This is a helper function of LowerToHorizontalOp().
5861 /// This function checks that the build_vector \p N in input implements a
5862 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
5863 /// operation to match.
5864 /// For example, if \p Opcode is equal to ISD::ADD, then this function
5865 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
5866 /// is equal to ISD::SUB, then this function checks if this is a horizontal
5869 /// This function only analyzes elements of \p N whose indices are
5870 /// in range [BaseIdx, LastIdx).
5871 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
5873 unsigned BaseIdx, unsigned LastIdx,
5874 SDValue &V0, SDValue &V1) {
5875 EVT VT = N->getValueType(0);
5877 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
5878 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
5879 "Invalid Vector in input!");
5881 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
5882 bool CanFold = true;
5883 unsigned ExpectedVExtractIdx = BaseIdx;
5884 unsigned NumElts = LastIdx - BaseIdx;
5885 V0 = DAG.getUNDEF(VT);
5886 V1 = DAG.getUNDEF(VT);
5888 // Check if N implements a horizontal binop.
5889 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
5890 SDValue Op = N->getOperand(i + BaseIdx);
5893 if (Op->getOpcode() == ISD::UNDEF) {
5894 // Update the expected vector extract index.
5895 if (i * 2 == NumElts)
5896 ExpectedVExtractIdx = BaseIdx;
5897 ExpectedVExtractIdx += 2;
5901 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
5906 SDValue Op0 = Op.getOperand(0);
5907 SDValue Op1 = Op.getOperand(1);
5909 // Try to match the following pattern:
5910 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
5911 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5912 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5913 Op0.getOperand(0) == Op1.getOperand(0) &&
5914 isa<ConstantSDNode>(Op0.getOperand(1)) &&
5915 isa<ConstantSDNode>(Op1.getOperand(1)));
5919 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
5920 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
5922 if (i * 2 < NumElts) {
5923 if (V0.getOpcode() == ISD::UNDEF) {
5924 V0 = Op0.getOperand(0);
5925 if (V0.getValueType() != VT)
5929 if (V1.getOpcode() == ISD::UNDEF) {
5930 V1 = Op0.getOperand(0);
5931 if (V1.getValueType() != VT)
5934 if (i * 2 == NumElts)
5935 ExpectedVExtractIdx = BaseIdx;
5938 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
5939 if (I0 == ExpectedVExtractIdx)
5940 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
5941 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
5942 // Try to match the following dag sequence:
5943 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
5944 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
5948 ExpectedVExtractIdx += 2;
5954 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
5955 /// a concat_vector.
5957 /// This is a helper function of LowerToHorizontalOp().
5958 /// This function expects two 256-bit vectors called V0 and V1.
5959 /// At first, each vector is split into two separate 128-bit vectors.
5960 /// Then, the resulting 128-bit vectors are used to implement two
5961 /// horizontal binary operations.
5963 /// The kind of horizontal binary operation is defined by \p X86Opcode.
5965 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
5966 /// the two new horizontal binop.
5967 /// When Mode is set, the first horizontal binop dag node would take as input
5968 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
5969 /// horizontal binop dag node would take as input the lower 128-bit of V1
5970 /// and the upper 128-bit of V1.
5972 /// HADD V0_LO, V0_HI
5973 /// HADD V1_LO, V1_HI
5975 /// Otherwise, the first horizontal binop dag node takes as input the lower
5976 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
5977 /// dag node takes the upper 128-bit of V0 and the upper 128-bit of V1.
5979 /// HADD V0_LO, V1_LO
5980 /// HADD V0_HI, V1_HI
5982 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
5983 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
5984 /// the upper 128-bits of the result.
5985 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
5986 SDLoc DL, SelectionDAG &DAG,
5987 unsigned X86Opcode, bool Mode,
5988 bool isUndefLO, bool isUndefHI) {
5989 EVT VT = V0.getValueType();
5990 assert(VT.is256BitVector() && VT == V1.getValueType() &&
5991 "Invalid nodes in input!");
5993 unsigned NumElts = VT.getVectorNumElements();
5994 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
5995 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
5996 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
5997 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
5998 EVT NewVT = V0_LO.getValueType();
6000 SDValue LO = DAG.getUNDEF(NewVT);
6001 SDValue HI = DAG.getUNDEF(NewVT);
6004 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6005 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
6006 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
6007 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
6008 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
6010 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6011 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
6012 V1_LO->getOpcode() != ISD::UNDEF))
6013 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
6015 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
6016 V1_HI->getOpcode() != ISD::UNDEF))
6017 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
6020 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
6023 /// Try to fold a build_vector that performs an 'addsub' to an X86ISD::ADDSUB
6025 static SDValue LowerToAddSub(const BuildVectorSDNode *BV,
6026 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
6027 MVT VT = BV->getSimpleValueType(0);
6028 if ((!Subtarget->hasSSE3() || (VT != MVT::v4f32 && VT != MVT::v2f64)) &&
6029 (!Subtarget->hasAVX() || (VT != MVT::v8f32 && VT != MVT::v4f64)))
6033 unsigned NumElts = VT.getVectorNumElements();
6034 SDValue InVec0 = DAG.getUNDEF(VT);
6035 SDValue InVec1 = DAG.getUNDEF(VT);
6037 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
6038 VT == MVT::v2f64) && "build_vector with an invalid type found!");
6040 // Odd-numbered elements in the input build vector are obtained from
6041 // adding two integer/float elements.
6042 // Even-numbered elements in the input build vector are obtained from
6043 // subtracting two integer/float elements.
6044 unsigned ExpectedOpcode = ISD::FSUB;
6045 unsigned NextExpectedOpcode = ISD::FADD;
6046 bool AddFound = false;
6047 bool SubFound = false;
6049 for (unsigned i = 0, e = NumElts; i != e; ++i) {
6050 SDValue Op = BV->getOperand(i);
6052 // Skip 'undef' values.
6053 unsigned Opcode = Op.getOpcode();
6054 if (Opcode == ISD::UNDEF) {
6055 std::swap(ExpectedOpcode, NextExpectedOpcode);
6059 // Early exit if we found an unexpected opcode.
6060 if (Opcode != ExpectedOpcode)
6063 SDValue Op0 = Op.getOperand(0);
6064 SDValue Op1 = Op.getOperand(1);
6066 // Try to match the following pattern:
6067 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
6068 // Early exit if we cannot match that sequence.
6069 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6070 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6071 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
6072 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
6073 Op0.getOperand(1) != Op1.getOperand(1))
6076 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6080 // We found a valid add/sub node. Update the information accordingly.
6086 // Update InVec0 and InVec1.
6087 if (InVec0.getOpcode() == ISD::UNDEF) {
6088 InVec0 = Op0.getOperand(0);
6089 if (InVec0.getSimpleValueType() != VT)
6092 if (InVec1.getOpcode() == ISD::UNDEF) {
6093 InVec1 = Op1.getOperand(0);
6094 if (InVec1.getSimpleValueType() != VT)
6098 // Make sure that operands in input to each add/sub node always
6099 // come from a same pair of vectors.
6100 if (InVec0 != Op0.getOperand(0)) {
6101 if (ExpectedOpcode == ISD::FSUB)
6104 // FADD is commutable. Try to commute the operands
6105 // and then test again.
6106 std::swap(Op0, Op1);
6107 if (InVec0 != Op0.getOperand(0))
6111 if (InVec1 != Op1.getOperand(0))
6114 // Update the pair of expected opcodes.
6115 std::swap(ExpectedOpcode, NextExpectedOpcode);
6118 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
6119 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
6120 InVec1.getOpcode() != ISD::UNDEF)
6121 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
6126 /// Lower BUILD_VECTOR to a horizontal add/sub operation if possible.
6127 static SDValue LowerToHorizontalOp(const BuildVectorSDNode *BV,
6128 const X86Subtarget *Subtarget,
6129 SelectionDAG &DAG) {
6130 MVT VT = BV->getSimpleValueType(0);
6131 unsigned NumElts = VT.getVectorNumElements();
6132 unsigned NumUndefsLO = 0;
6133 unsigned NumUndefsHI = 0;
6134 unsigned Half = NumElts/2;
6136 // Count the number of UNDEF operands in the build_vector in input.
6137 for (unsigned i = 0, e = Half; i != e; ++i)
6138 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6141 for (unsigned i = Half, e = NumElts; i != e; ++i)
6142 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6145 // Early exit if this is either a build_vector of all UNDEFs or all the
6146 // operands but one are UNDEF.
6147 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
6151 SDValue InVec0, InVec1;
6152 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
6153 // Try to match an SSE3 float HADD/HSUB.
6154 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6155 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6157 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6158 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6159 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
6160 // Try to match an SSSE3 integer HADD/HSUB.
6161 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6162 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
6164 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6165 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
6168 if (!Subtarget->hasAVX())
6171 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
6172 // Try to match an AVX horizontal add/sub of packed single/double
6173 // precision floating point values from 256-bit vectors.
6174 SDValue InVec2, InVec3;
6175 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
6176 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
6177 ((InVec0.getOpcode() == ISD::UNDEF ||
6178 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6179 ((InVec1.getOpcode() == ISD::UNDEF ||
6180 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6181 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6183 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
6184 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
6185 ((InVec0.getOpcode() == ISD::UNDEF ||
6186 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6187 ((InVec1.getOpcode() == ISD::UNDEF ||
6188 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6189 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6190 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
6191 // Try to match an AVX2 horizontal add/sub of signed integers.
6192 SDValue InVec2, InVec3;
6194 bool CanFold = true;
6196 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
6197 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
6198 ((InVec0.getOpcode() == ISD::UNDEF ||
6199 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6200 ((InVec1.getOpcode() == ISD::UNDEF ||
6201 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6202 X86Opcode = X86ISD::HADD;
6203 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
6204 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
6205 ((InVec0.getOpcode() == ISD::UNDEF ||
6206 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6207 ((InVec1.getOpcode() == ISD::UNDEF ||
6208 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6209 X86Opcode = X86ISD::HSUB;
6214 // Fold this build_vector into a single horizontal add/sub.
6215 // Do this only if the target has AVX2.
6216 if (Subtarget->hasAVX2())
6217 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
6219 // Do not try to expand this build_vector into a pair of horizontal
6220 // add/sub if we can emit a pair of scalar add/sub.
6221 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6224 // Convert this build_vector into a pair of horizontal binop followed by
6226 bool isUndefLO = NumUndefsLO == Half;
6227 bool isUndefHI = NumUndefsHI == Half;
6228 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
6229 isUndefLO, isUndefHI);
6233 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
6234 VT == MVT::v16i16) && Subtarget->hasAVX()) {
6236 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6237 X86Opcode = X86ISD::HADD;
6238 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6239 X86Opcode = X86ISD::HSUB;
6240 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6241 X86Opcode = X86ISD::FHADD;
6242 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6243 X86Opcode = X86ISD::FHSUB;
6247 // Don't try to expand this build_vector into a pair of horizontal add/sub
6248 // if we can simply emit a pair of scalar add/sub.
6249 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6252 // Convert this build_vector into two horizontal add/sub followed by
6254 bool isUndefLO = NumUndefsLO == Half;
6255 bool isUndefHI = NumUndefsHI == Half;
6256 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
6257 isUndefLO, isUndefHI);
6264 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6267 MVT VT = Op.getSimpleValueType();
6268 MVT ExtVT = VT.getVectorElementType();
6269 unsigned NumElems = Op.getNumOperands();
6271 // Generate vectors for predicate vectors.
6272 if (VT.getVectorElementType() == MVT::i1 && Subtarget->hasAVX512())
6273 return LowerBUILD_VECTORvXi1(Op, DAG);
6275 // Vectors containing all zeros can be matched by pxor and xorps later
6276 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6277 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6278 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6279 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6282 return getZeroVector(VT, Subtarget, DAG, dl);
6285 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6286 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6287 // vpcmpeqd on 256-bit vectors.
6288 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6289 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6292 if (!VT.is512BitVector())
6293 return getOnesVector(VT, Subtarget, DAG, dl);
6296 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(Op.getNode());
6297 if (SDValue AddSub = LowerToAddSub(BV, Subtarget, DAG))
6299 if (SDValue HorizontalOp = LowerToHorizontalOp(BV, Subtarget, DAG))
6300 return HorizontalOp;
6301 if (SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG))
6304 unsigned EVTBits = ExtVT.getSizeInBits();
6306 unsigned NumZero = 0;
6307 unsigned NumNonZero = 0;
6308 uint64_t NonZeros = 0;
6309 bool IsAllConstants = true;
6310 SmallSet<SDValue, 8> Values;
6311 for (unsigned i = 0; i < NumElems; ++i) {
6312 SDValue Elt = Op.getOperand(i);
6313 if (Elt.getOpcode() == ISD::UNDEF)
6316 if (Elt.getOpcode() != ISD::Constant &&
6317 Elt.getOpcode() != ISD::ConstantFP)
6318 IsAllConstants = false;
6319 if (X86::isZeroNode(Elt))
6322 assert(i < sizeof(NonZeros) * 8); // Make sure the shift is within range.
6323 NonZeros |= ((uint64_t)1 << i);
6328 // All undef vector. Return an UNDEF. All zero vectors were handled above.
6329 if (NumNonZero == 0)
6330 return DAG.getUNDEF(VT);
6332 // Special case for single non-zero, non-undef, element.
6333 if (NumNonZero == 1) {
6334 unsigned Idx = countTrailingZeros(NonZeros);
6335 SDValue Item = Op.getOperand(Idx);
6337 // If this is an insertion of an i64 value on x86-32, and if the top bits of
6338 // the value are obviously zero, truncate the value to i32 and do the
6339 // insertion that way. Only do this if the value is non-constant or if the
6340 // value is a constant being inserted into element 0. It is cheaper to do
6341 // a constant pool load than it is to do a movd + shuffle.
6342 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6343 (!IsAllConstants || Idx == 0)) {
6344 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6346 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6347 MVT VecVT = MVT::v4i32;
6349 // Truncate the value (which may itself be a constant) to i32, and
6350 // convert it to a vector with movd (S2V+shuffle to zero extend).
6351 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6352 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6353 return DAG.getBitcast(VT, getShuffleVectorZeroOrUndef(
6354 Item, Idx * 2, true, Subtarget, DAG));
6358 // If we have a constant or non-constant insertion into the low element of
6359 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
6360 // the rest of the elements. This will be matched as movd/movq/movss/movsd
6361 // depending on what the source datatype is.
6364 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6366 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
6367 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6368 if (VT.is512BitVector()) {
6369 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6370 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6371 Item, DAG.getIntPtrConstant(0, dl));
6373 assert((VT.is128BitVector() || VT.is256BitVector()) &&
6374 "Expected an SSE value type!");
6375 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6376 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6377 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6380 // We can't directly insert an i8 or i16 into a vector, so zero extend
6382 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6383 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6384 if (VT.is256BitVector()) {
6385 if (Subtarget->hasAVX()) {
6386 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v8i32, Item);
6387 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6389 // Without AVX, we need to extend to a 128-bit vector and then
6390 // insert into the 256-bit vector.
6391 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6392 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6393 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6396 assert(VT.is128BitVector() && "Expected an SSE value type!");
6397 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6398 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6400 return DAG.getBitcast(VT, Item);
6404 // Is it a vector logical left shift?
6405 if (NumElems == 2 && Idx == 1 &&
6406 X86::isZeroNode(Op.getOperand(0)) &&
6407 !X86::isZeroNode(Op.getOperand(1))) {
6408 unsigned NumBits = VT.getSizeInBits();
6409 return getVShift(true, VT,
6410 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6411 VT, Op.getOperand(1)),
6412 NumBits/2, DAG, *this, dl);
6415 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
6418 // Otherwise, if this is a vector with i32 or f32 elements, and the element
6419 // is a non-constant being inserted into an element other than the low one,
6420 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
6421 // movd/movss) to move this into the low element, then shuffle it into
6423 if (EVTBits == 32) {
6424 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6425 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
6429 // Splat is obviously ok. Let legalizer expand it to a shuffle.
6430 if (Values.size() == 1) {
6431 if (EVTBits == 32) {
6432 // Instead of a shuffle like this:
6433 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
6434 // Check if it's possible to issue this instead.
6435 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
6436 unsigned Idx = countTrailingZeros(NonZeros);
6437 SDValue Item = Op.getOperand(Idx);
6438 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
6439 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6444 // A vector full of immediates; various special cases are already
6445 // handled, so this is best done with a single constant-pool load.
6449 // For AVX-length vectors, see if we can use a vector load to get all of the
6450 // elements, otherwise build the individual 128-bit pieces and use
6451 // shuffles to put them in place.
6452 if (VT.is256BitVector() || VT.is512BitVector()) {
6453 SmallVector<SDValue, 64> V(Op->op_begin(), Op->op_begin() + NumElems);
6455 // Check for a build vector of consecutive loads.
6456 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
6459 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
6461 // Build both the lower and upper subvector.
6462 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6463 makeArrayRef(&V[0], NumElems/2));
6464 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6465 makeArrayRef(&V[NumElems / 2], NumElems/2));
6467 // Recreate the wider vector with the lower and upper part.
6468 if (VT.is256BitVector())
6469 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6470 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6473 // Let legalizer expand 2-wide build_vectors.
6474 if (EVTBits == 64) {
6475 if (NumNonZero == 1) {
6476 // One half is zero or undef.
6477 unsigned Idx = countTrailingZeros(NonZeros);
6478 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
6479 Op.getOperand(Idx));
6480 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
6485 // If element VT is < 32 bits, convert it to inserts into a zero vector.
6486 if (EVTBits == 8 && NumElems == 16)
6487 if (SDValue V = LowerBuildVectorv16i8(Op, NonZeros, NumNonZero, NumZero,
6488 DAG, Subtarget, *this))
6491 if (EVTBits == 16 && NumElems == 8)
6492 if (SDValue V = LowerBuildVectorv8i16(Op, NonZeros, NumNonZero, NumZero,
6493 DAG, Subtarget, *this))
6496 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
6497 if (EVTBits == 32 && NumElems == 4)
6498 if (SDValue V = LowerBuildVectorv4x32(Op, DAG, Subtarget, *this))
6501 // If element VT is == 32 bits, turn it into a number of shuffles.
6502 SmallVector<SDValue, 8> V(NumElems);
6503 if (NumElems == 4 && NumZero > 0) {
6504 for (unsigned i = 0; i < 4; ++i) {
6505 bool isZero = !(NonZeros & (1ULL << i));
6507 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
6509 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6512 for (unsigned i = 0; i < 2; ++i) {
6513 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
6516 V[i] = V[i*2]; // Must be a zero vector.
6519 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
6522 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
6525 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
6530 bool Reverse1 = (NonZeros & 0x3) == 2;
6531 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
6535 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
6536 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
6538 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
6541 if (Values.size() > 1 && VT.is128BitVector()) {
6542 // Check for a build vector of consecutive loads.
6543 for (unsigned i = 0; i < NumElems; ++i)
6544 V[i] = Op.getOperand(i);
6546 // Check for elements which are consecutive loads.
6547 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
6550 // Check for a build vector from mostly shuffle plus few inserting.
6551 if (SDValue Sh = buildFromShuffleMostly(Op, DAG))
6554 // For SSE 4.1, use insertps to put the high elements into the low element.
6555 if (Subtarget->hasSSE41()) {
6557 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
6558 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
6560 Result = DAG.getUNDEF(VT);
6562 for (unsigned i = 1; i < NumElems; ++i) {
6563 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
6564 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
6565 Op.getOperand(i), DAG.getIntPtrConstant(i, dl));
6570 // Otherwise, expand into a number of unpckl*, start by extending each of
6571 // our (non-undef) elements to the full vector width with the element in the
6572 // bottom slot of the vector (which generates no code for SSE).
6573 for (unsigned i = 0; i < NumElems; ++i) {
6574 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
6575 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6577 V[i] = DAG.getUNDEF(VT);
6580 // Next, we iteratively mix elements, e.g. for v4f32:
6581 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
6582 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
6583 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
6584 unsigned EltStride = NumElems >> 1;
6585 while (EltStride != 0) {
6586 for (unsigned i = 0; i < EltStride; ++i) {
6587 // If V[i+EltStride] is undef and this is the first round of mixing,
6588 // then it is safe to just drop this shuffle: V[i] is already in the
6589 // right place, the one element (since it's the first round) being
6590 // inserted as undef can be dropped. This isn't safe for successive
6591 // rounds because they will permute elements within both vectors.
6592 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
6593 EltStride == NumElems/2)
6596 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
6605 // 256-bit AVX can use the vinsertf128 instruction
6606 // to create 256-bit vectors from two other 128-bit ones.
6607 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6609 MVT ResVT = Op.getSimpleValueType();
6611 assert((ResVT.is256BitVector() ||
6612 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
6614 SDValue V1 = Op.getOperand(0);
6615 SDValue V2 = Op.getOperand(1);
6616 unsigned NumElems = ResVT.getVectorNumElements();
6617 if (ResVT.is256BitVector())
6618 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6620 if (Op.getNumOperands() == 4) {
6621 MVT HalfVT = MVT::getVectorVT(ResVT.getVectorElementType(),
6622 ResVT.getVectorNumElements()/2);
6623 SDValue V3 = Op.getOperand(2);
6624 SDValue V4 = Op.getOperand(3);
6625 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
6626 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
6628 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6631 static SDValue LowerCONCAT_VECTORSvXi1(SDValue Op,
6632 const X86Subtarget *Subtarget,
6633 SelectionDAG & DAG) {
6635 MVT ResVT = Op.getSimpleValueType();
6636 unsigned NumOfOperands = Op.getNumOperands();
6638 assert(isPowerOf2_32(NumOfOperands) &&
6639 "Unexpected number of operands in CONCAT_VECTORS");
6641 SDValue Undef = DAG.getUNDEF(ResVT);
6642 if (NumOfOperands > 2) {
6643 // Specialize the cases when all, or all but one, of the operands are undef.
6644 unsigned NumOfDefinedOps = 0;
6646 for (unsigned i = 0; i < NumOfOperands; i++)
6647 if (!Op.getOperand(i).isUndef()) {
6651 if (NumOfDefinedOps == 0)
6653 if (NumOfDefinedOps == 1) {
6654 unsigned SubVecNumElts =
6655 Op.getOperand(OpIdx).getValueType().getVectorNumElements();
6656 SDValue IdxVal = DAG.getIntPtrConstant(SubVecNumElts * OpIdx, dl);
6657 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef,
6658 Op.getOperand(OpIdx), IdxVal);
6661 MVT HalfVT = MVT::getVectorVT(ResVT.getVectorElementType(),
6662 ResVT.getVectorNumElements()/2);
6663 SmallVector<SDValue, 2> Ops;
6664 for (unsigned i = 0; i < NumOfOperands/2; i++)
6665 Ops.push_back(Op.getOperand(i));
6666 SDValue Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops);
6668 for (unsigned i = NumOfOperands/2; i < NumOfOperands; i++)
6669 Ops.push_back(Op.getOperand(i));
6670 SDValue Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops);
6671 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
6675 SDValue V1 = Op.getOperand(0);
6676 SDValue V2 = Op.getOperand(1);
6677 unsigned NumElems = ResVT.getVectorNumElements();
6678 assert(V1.getValueType() == V2.getValueType() &&
6679 V1.getValueType().getVectorNumElements() == NumElems/2 &&
6680 "Unexpected operands in CONCAT_VECTORS");
6682 if (ResVT.getSizeInBits() >= 16)
6683 return Op; // The operation is legal with KUNPCK
6685 bool IsZeroV1 = ISD::isBuildVectorAllZeros(V1.getNode());
6686 bool IsZeroV2 = ISD::isBuildVectorAllZeros(V2.getNode());
6687 SDValue ZeroVec = getZeroVector(ResVT, Subtarget, DAG, dl);
6688 if (IsZeroV1 && IsZeroV2)
6691 SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
6693 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V1, ZeroIdx);
6695 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, ZeroVec, V1, ZeroIdx);
6697 SDValue IdxVal = DAG.getIntPtrConstant(NumElems/2, dl);
6699 V2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V2, IdxVal);
6702 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, ZeroVec, V2, IdxVal);
6704 V1 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V1, ZeroIdx);
6705 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, V1, V2, IdxVal);
6708 static SDValue LowerCONCAT_VECTORS(SDValue Op,
6709 const X86Subtarget *Subtarget,
6710 SelectionDAG &DAG) {
6711 MVT VT = Op.getSimpleValueType();
6712 if (VT.getVectorElementType() == MVT::i1)
6713 return LowerCONCAT_VECTORSvXi1(Op, Subtarget, DAG);
6715 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
6716 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
6717 Op.getNumOperands() == 4)));
6719 // AVX can use the vinsertf128 instruction to create 256-bit vectors
6720 // from two other 128-bit ones.
6722 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
6723 return LowerAVXCONCAT_VECTORS(Op, DAG);
6726 //===----------------------------------------------------------------------===//
6727 // Vector shuffle lowering
6729 // This is an experimental code path for lowering vector shuffles on x86. It is
6730 // designed to handle arbitrary vector shuffles and blends, gracefully
6731 // degrading performance as necessary. It works hard to recognize idiomatic
6732 // shuffles and lower them to optimal instruction patterns without leaving
6733 // a framework that allows reasonably efficient handling of all vector shuffle
6735 //===----------------------------------------------------------------------===//
6737 /// \brief Tiny helper function to identify a no-op mask.
6739 /// This is a somewhat boring predicate function. It checks whether the mask
6740 /// array input, which is assumed to be a single-input shuffle mask of the kind
6741 /// used by the X86 shuffle instructions (not a fully general
6742 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
6743 /// in-place shuffle are 'no-op's.
6744 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
6745 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6746 if (Mask[i] != -1 && Mask[i] != i)
6751 /// \brief Helper function to classify a mask as a single-input mask.
6753 /// This isn't a generic single-input test because in the vector shuffle
6754 /// lowering we canonicalize single inputs to be the first input operand. This
6755 /// means we can more quickly test for a single input by only checking whether
6756 /// an input from the second operand exists. We also assume that the size of
6757 /// mask corresponds to the size of the input vectors which isn't true in the
6758 /// fully general case.
6759 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
6761 if (M >= (int)Mask.size())
6766 /// \brief Test whether there are elements crossing 128-bit lanes in this
6769 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
6770 /// and we routinely test for these.
6771 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
6772 int LaneSize = 128 / VT.getScalarSizeInBits();
6773 int Size = Mask.size();
6774 for (int i = 0; i < Size; ++i)
6775 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
6780 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
6782 /// This checks a shuffle mask to see if it is performing the same
6783 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
6784 /// that it is also not lane-crossing. It may however involve a blend from the
6785 /// same lane of a second vector.
6787 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
6788 /// non-trivial to compute in the face of undef lanes. The representation is
6789 /// *not* suitable for use with existing 128-bit shuffles as it will contain
6790 /// entries from both V1 and V2 inputs to the wider mask.
6792 is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
6793 SmallVectorImpl<int> &RepeatedMask) {
6794 int LaneSize = 128 / VT.getScalarSizeInBits();
6795 RepeatedMask.resize(LaneSize, -1);
6796 int Size = Mask.size();
6797 for (int i = 0; i < Size; ++i) {
6800 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
6801 // This entry crosses lanes, so there is no way to model this shuffle.
6804 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
6805 if (RepeatedMask[i % LaneSize] == -1)
6806 // This is the first non-undef entry in this slot of a 128-bit lane.
6807 RepeatedMask[i % LaneSize] =
6808 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
6809 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
6810 // Found a mismatch with the repeated mask.
6816 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
6819 /// This is a fast way to test a shuffle mask against a fixed pattern:
6821 /// if (isShuffleEquivalent(Mask, 3, 2, {1, 0})) { ... }
6823 /// It returns true if the mask is exactly as wide as the argument list, and
6824 /// each element of the mask is either -1 (signifying undef) or the value given
6825 /// in the argument.
6826 static bool isShuffleEquivalent(SDValue V1, SDValue V2, ArrayRef<int> Mask,
6827 ArrayRef<int> ExpectedMask) {
6828 if (Mask.size() != ExpectedMask.size())
6831 int Size = Mask.size();
6833 // If the values are build vectors, we can look through them to find
6834 // equivalent inputs that make the shuffles equivalent.
6835 auto *BV1 = dyn_cast<BuildVectorSDNode>(V1);
6836 auto *BV2 = dyn_cast<BuildVectorSDNode>(V2);
6838 for (int i = 0; i < Size; ++i)
6839 if (Mask[i] != -1 && Mask[i] != ExpectedMask[i]) {
6840 auto *MaskBV = Mask[i] < Size ? BV1 : BV2;
6841 auto *ExpectedBV = ExpectedMask[i] < Size ? BV1 : BV2;
6842 if (!MaskBV || !ExpectedBV ||
6843 MaskBV->getOperand(Mask[i] % Size) !=
6844 ExpectedBV->getOperand(ExpectedMask[i] % Size))
6851 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
6853 /// This helper function produces an 8-bit shuffle immediate corresponding to
6854 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
6855 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
6858 /// NB: We rely heavily on "undef" masks preserving the input lane.
6859 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask, SDLoc DL,
6860 SelectionDAG &DAG) {
6861 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
6862 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
6863 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
6864 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
6865 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
6868 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
6869 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
6870 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
6871 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
6872 return DAG.getConstant(Imm, DL, MVT::i8);
6875 /// \brief Compute whether each element of a shuffle is zeroable.
6877 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
6878 /// Either it is an undef element in the shuffle mask, the element of the input
6879 /// referenced is undef, or the element of the input referenced is known to be
6880 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
6881 /// as many lanes with this technique as possible to simplify the remaining
6883 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
6884 SDValue V1, SDValue V2) {
6885 SmallBitVector Zeroable(Mask.size(), false);
6887 while (V1.getOpcode() == ISD::BITCAST)
6888 V1 = V1->getOperand(0);
6889 while (V2.getOpcode() == ISD::BITCAST)
6890 V2 = V2->getOperand(0);
6892 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
6893 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
6895 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6897 // Handle the easy cases.
6898 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
6903 // If this is an index into a build_vector node (which has the same number
6904 // of elements), dig out the input value and use it.
6905 SDValue V = M < Size ? V1 : V2;
6906 if (V.getOpcode() != ISD::BUILD_VECTOR || Size != (int)V.getNumOperands())
6909 SDValue Input = V.getOperand(M % Size);
6910 // The UNDEF opcode check really should be dead code here, but not quite
6911 // worth asserting on (it isn't invalid, just unexpected).
6912 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
6919 // X86 has dedicated unpack instructions that can handle specific blend
6920 // operations: UNPCKH and UNPCKL.
6921 static SDValue lowerVectorShuffleWithUNPCK(SDLoc DL, MVT VT, ArrayRef<int> Mask,
6922 SDValue V1, SDValue V2,
6923 SelectionDAG &DAG) {
6924 int NumElts = VT.getVectorNumElements();
6925 int NumEltsInLane = 128 / VT.getScalarSizeInBits();
6926 SmallVector<int, 8> Unpckl;
6927 SmallVector<int, 8> Unpckh;
6929 for (int i = 0; i < NumElts; ++i) {
6930 unsigned LaneStart = (i / NumEltsInLane) * NumEltsInLane;
6931 int LoPos = (i % NumEltsInLane) / 2 + LaneStart + NumElts * (i % 2);
6932 int HiPos = LoPos + NumEltsInLane / 2;
6933 Unpckl.push_back(LoPos);
6934 Unpckh.push_back(HiPos);
6937 if (isShuffleEquivalent(V1, V2, Mask, Unpckl))
6938 return DAG.getNode(X86ISD::UNPCKL, DL, VT, V1, V2);
6939 if (isShuffleEquivalent(V1, V2, Mask, Unpckh))
6940 return DAG.getNode(X86ISD::UNPCKH, DL, VT, V1, V2);
6942 // Commute and try again.
6943 ShuffleVectorSDNode::commuteMask(Unpckl);
6944 if (isShuffleEquivalent(V1, V2, Mask, Unpckl))
6945 return DAG.getNode(X86ISD::UNPCKL, DL, VT, V2, V1);
6947 ShuffleVectorSDNode::commuteMask(Unpckh);
6948 if (isShuffleEquivalent(V1, V2, Mask, Unpckh))
6949 return DAG.getNode(X86ISD::UNPCKH, DL, VT, V2, V1);
6954 /// \brief Try to emit a bitmask instruction for a shuffle.
6956 /// This handles cases where we can model a blend exactly as a bitmask due to
6957 /// one of the inputs being zeroable.
6958 static SDValue lowerVectorShuffleAsBitMask(SDLoc DL, MVT VT, SDValue V1,
6959 SDValue V2, ArrayRef<int> Mask,
6960 SelectionDAG &DAG) {
6961 MVT EltVT = VT.getVectorElementType();
6962 int NumEltBits = EltVT.getSizeInBits();
6963 MVT IntEltVT = MVT::getIntegerVT(NumEltBits);
6964 SDValue Zero = DAG.getConstant(0, DL, IntEltVT);
6965 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), DL,
6967 if (EltVT.isFloatingPoint()) {
6968 Zero = DAG.getBitcast(EltVT, Zero);
6969 AllOnes = DAG.getBitcast(EltVT, AllOnes);
6971 SmallVector<SDValue, 16> VMaskOps(Mask.size(), Zero);
6972 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6974 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6977 if (Mask[i] % Size != i)
6978 return SDValue(); // Not a blend.
6980 V = Mask[i] < Size ? V1 : V2;
6981 else if (V != (Mask[i] < Size ? V1 : V2))
6982 return SDValue(); // Can only let one input through the mask.
6984 VMaskOps[i] = AllOnes;
6987 return SDValue(); // No non-zeroable elements!
6989 SDValue VMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, VMaskOps);
6990 V = DAG.getNode(VT.isFloatingPoint()
6991 ? (unsigned) X86ISD::FAND : (unsigned) ISD::AND,
6996 /// \brief Try to emit a blend instruction for a shuffle using bit math.
6998 /// This is used as a fallback approach when first class blend instructions are
6999 /// unavailable. Currently it is only suitable for integer vectors, but could
7000 /// be generalized for floating point vectors if desirable.
7001 static SDValue lowerVectorShuffleAsBitBlend(SDLoc DL, MVT VT, SDValue V1,
7002 SDValue V2, ArrayRef<int> Mask,
7003 SelectionDAG &DAG) {
7004 assert(VT.isInteger() && "Only supports integer vector types!");
7005 MVT EltVT = VT.getVectorElementType();
7006 int NumEltBits = EltVT.getSizeInBits();
7007 SDValue Zero = DAG.getConstant(0, DL, EltVT);
7008 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), DL,
7010 SmallVector<SDValue, 16> MaskOps;
7011 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7012 if (Mask[i] != -1 && Mask[i] != i && Mask[i] != i + Size)
7013 return SDValue(); // Shuffled input!
7014 MaskOps.push_back(Mask[i] < Size ? AllOnes : Zero);
7017 SDValue V1Mask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, MaskOps);
7018 V1 = DAG.getNode(ISD::AND, DL, VT, V1, V1Mask);
7019 // We have to cast V2 around.
7020 MVT MaskVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
7021 V2 = DAG.getBitcast(VT, DAG.getNode(X86ISD::ANDNP, DL, MaskVT,
7022 DAG.getBitcast(MaskVT, V1Mask),
7023 DAG.getBitcast(MaskVT, V2)));
7024 return DAG.getNode(ISD::OR, DL, VT, V1, V2);
7027 /// \brief Try to emit a blend instruction for a shuffle.
7029 /// This doesn't do any checks for the availability of instructions for blending
7030 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
7031 /// be matched in the backend with the type given. What it does check for is
7032 /// that the shuffle mask is a blend, or convertible into a blend with zero.
7033 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
7034 SDValue V2, ArrayRef<int> Original,
7035 const X86Subtarget *Subtarget,
7036 SelectionDAG &DAG) {
7037 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
7038 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
7039 SmallVector<int, 8> Mask(Original.begin(), Original.end());
7040 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7041 bool ForceV1Zero = false, ForceV2Zero = false;
7043 // Attempt to generate the binary blend mask. If an input is zero then
7044 // we can use any lane.
7045 // TODO: generalize the zero matching to any scalar like isShuffleEquivalent.
7046 unsigned BlendMask = 0;
7047 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7053 if (M == i + Size) {
7054 BlendMask |= 1u << i;
7065 BlendMask |= 1u << i;
7070 return SDValue(); // Shuffled input!
7073 // Create a REAL zero vector - ISD::isBuildVectorAllZeros allows UNDEFs.
7075 V1 = getZeroVector(VT, Subtarget, DAG, DL);
7077 V2 = getZeroVector(VT, Subtarget, DAG, DL);
7079 auto ScaleBlendMask = [](unsigned BlendMask, int Size, int Scale) {
7080 unsigned ScaledMask = 0;
7081 for (int i = 0; i != Size; ++i)
7082 if (BlendMask & (1u << i))
7083 for (int j = 0; j != Scale; ++j)
7084 ScaledMask |= 1u << (i * Scale + j);
7088 switch (VT.SimpleTy) {
7093 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
7094 DAG.getConstant(BlendMask, DL, MVT::i8));
7098 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7102 // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
7103 // that instruction.
7104 if (Subtarget->hasAVX2()) {
7105 // Scale the blend by the number of 32-bit dwords per element.
7106 int Scale = VT.getScalarSizeInBits() / 32;
7107 BlendMask = ScaleBlendMask(BlendMask, Mask.size(), Scale);
7108 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
7109 V1 = DAG.getBitcast(BlendVT, V1);
7110 V2 = DAG.getBitcast(BlendVT, V2);
7111 return DAG.getBitcast(
7112 VT, DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
7113 DAG.getConstant(BlendMask, DL, MVT::i8)));
7117 // For integer shuffles we need to expand the mask and cast the inputs to
7118 // v8i16s prior to blending.
7119 int Scale = 8 / VT.getVectorNumElements();
7120 BlendMask = ScaleBlendMask(BlendMask, Mask.size(), Scale);
7121 V1 = DAG.getBitcast(MVT::v8i16, V1);
7122 V2 = DAG.getBitcast(MVT::v8i16, V2);
7123 return DAG.getBitcast(VT,
7124 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
7125 DAG.getConstant(BlendMask, DL, MVT::i8)));
7129 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7130 SmallVector<int, 8> RepeatedMask;
7131 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
7132 // We can lower these with PBLENDW which is mirrored across 128-bit lanes.
7133 assert(RepeatedMask.size() == 8 && "Repeated mask size doesn't match!");
7135 for (int i = 0; i < 8; ++i)
7136 if (RepeatedMask[i] >= 16)
7137 BlendMask |= 1u << i;
7138 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,
7139 DAG.getConstant(BlendMask, DL, MVT::i8));
7145 assert((VT.is128BitVector() || Subtarget->hasAVX2()) &&
7146 "256-bit byte-blends require AVX2 support!");
7148 // Attempt to lower to a bitmask if we can. VPAND is faster than VPBLENDVB.
7149 if (SDValue Masked = lowerVectorShuffleAsBitMask(DL, VT, V1, V2, Mask, DAG))
7152 // Scale the blend by the number of bytes per element.
7153 int Scale = VT.getScalarSizeInBits() / 8;
7155 // This form of blend is always done on bytes. Compute the byte vector
7157 MVT BlendVT = MVT::getVectorVT(MVT::i8, VT.getSizeInBits() / 8);
7159 // Compute the VSELECT mask. Note that VSELECT is really confusing in the
7160 // mix of LLVM's code generator and the x86 backend. We tell the code
7161 // generator that boolean values in the elements of an x86 vector register
7162 // are -1 for true and 0 for false. We then use the LLVM semantics of 'true'
7163 // mapping a select to operand #1, and 'false' mapping to operand #2. The
7164 // reality in x86 is that vector masks (pre-AVX-512) use only the high bit
7165 // of the element (the remaining are ignored) and 0 in that high bit would
7166 // mean operand #1 while 1 in the high bit would mean operand #2. So while
7167 // the LLVM model for boolean values in vector elements gets the relevant
7168 // bit set, it is set backwards and over constrained relative to x86's
7170 SmallVector<SDValue, 32> VSELECTMask;
7171 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7172 for (int j = 0; j < Scale; ++j)
7173 VSELECTMask.push_back(
7174 Mask[i] < 0 ? DAG.getUNDEF(MVT::i8)
7175 : DAG.getConstant(Mask[i] < Size ? -1 : 0, DL,
7178 V1 = DAG.getBitcast(BlendVT, V1);
7179 V2 = DAG.getBitcast(BlendVT, V2);
7180 return DAG.getBitcast(VT, DAG.getNode(ISD::VSELECT, DL, BlendVT,
7181 DAG.getNode(ISD::BUILD_VECTOR, DL,
7182 BlendVT, VSELECTMask),
7187 llvm_unreachable("Not a supported integer vector type!");
7191 /// \brief Try to lower as a blend of elements from two inputs followed by
7192 /// a single-input permutation.
7194 /// This matches the pattern where we can blend elements from two inputs and
7195 /// then reduce the shuffle to a single-input permutation.
7196 static SDValue lowerVectorShuffleAsBlendAndPermute(SDLoc DL, MVT VT, SDValue V1,
7199 SelectionDAG &DAG) {
7200 // We build up the blend mask while checking whether a blend is a viable way
7201 // to reduce the shuffle.
7202 SmallVector<int, 32> BlendMask(Mask.size(), -1);
7203 SmallVector<int, 32> PermuteMask(Mask.size(), -1);
7205 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7209 assert(Mask[i] < Size * 2 && "Shuffle input is out of bounds.");
7211 if (BlendMask[Mask[i] % Size] == -1)
7212 BlendMask[Mask[i] % Size] = Mask[i];
7213 else if (BlendMask[Mask[i] % Size] != Mask[i])
7214 return SDValue(); // Can't blend in the needed input!
7216 PermuteMask[i] = Mask[i] % Size;
7219 SDValue V = DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
7220 return DAG.getVectorShuffle(VT, DL, V, DAG.getUNDEF(VT), PermuteMask);
7223 /// \brief Generic routine to decompose a shuffle and blend into indepndent
7224 /// blends and permutes.
7226 /// This matches the extremely common pattern for handling combined
7227 /// shuffle+blend operations on newer X86 ISAs where we have very fast blend
7228 /// operations. It will try to pick the best arrangement of shuffles and
7230 static SDValue lowerVectorShuffleAsDecomposedShuffleBlend(SDLoc DL, MVT VT,
7234 SelectionDAG &DAG) {
7235 // Shuffle the input elements into the desired positions in V1 and V2 and
7236 // blend them together.
7237 SmallVector<int, 32> V1Mask(Mask.size(), -1);
7238 SmallVector<int, 32> V2Mask(Mask.size(), -1);
7239 SmallVector<int, 32> BlendMask(Mask.size(), -1);
7240 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7241 if (Mask[i] >= 0 && Mask[i] < Size) {
7242 V1Mask[i] = Mask[i];
7244 } else if (Mask[i] >= Size) {
7245 V2Mask[i] = Mask[i] - Size;
7246 BlendMask[i] = i + Size;
7249 // Try to lower with the simpler initial blend strategy unless one of the
7250 // input shuffles would be a no-op. We prefer to shuffle inputs as the
7251 // shuffle may be able to fold with a load or other benefit. However, when
7252 // we'll have to do 2x as many shuffles in order to achieve this, blending
7253 // first is a better strategy.
7254 if (!isNoopShuffleMask(V1Mask) && !isNoopShuffleMask(V2Mask))
7255 if (SDValue BlendPerm =
7256 lowerVectorShuffleAsBlendAndPermute(DL, VT, V1, V2, Mask, DAG))
7259 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
7260 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
7261 return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
7264 /// \brief Try to lower a vector shuffle as a byte rotation.
7266 /// SSSE3 has a generic PALIGNR instruction in x86 that will do an arbitrary
7267 /// byte-rotation of the concatenation of two vectors; pre-SSSE3 can use
7268 /// a PSRLDQ/PSLLDQ/POR pattern to get a similar effect. This routine will
7269 /// try to generically lower a vector shuffle through such an pattern. It
7270 /// does not check for the profitability of lowering either as PALIGNR or
7271 /// PSRLDQ/PSLLDQ/POR, only whether the mask is valid to lower in that form.
7272 /// This matches shuffle vectors that look like:
7274 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
7276 /// Essentially it concatenates V1 and V2, shifts right by some number of
7277 /// elements, and takes the low elements as the result. Note that while this is
7278 /// specified as a *right shift* because x86 is little-endian, it is a *left
7279 /// rotate* of the vector lanes.
7280 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
7283 const X86Subtarget *Subtarget,
7284 SelectionDAG &DAG) {
7285 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7287 int NumElts = Mask.size();
7288 int NumLanes = VT.getSizeInBits() / 128;
7289 int NumLaneElts = NumElts / NumLanes;
7291 // We need to detect various ways of spelling a rotation:
7292 // [11, 12, 13, 14, 15, 0, 1, 2]
7293 // [-1, 12, 13, 14, -1, -1, 1, -1]
7294 // [-1, -1, -1, -1, -1, -1, 1, 2]
7295 // [ 3, 4, 5, 6, 7, 8, 9, 10]
7296 // [-1, 4, 5, 6, -1, -1, 9, -1]
7297 // [-1, 4, 5, 6, -1, -1, -1, -1]
7300 for (int l = 0; l < NumElts; l += NumLaneElts) {
7301 for (int i = 0; i < NumLaneElts; ++i) {
7302 if (Mask[l + i] == -1)
7304 assert(Mask[l + i] >= 0 && "Only -1 is a valid negative mask element!");
7306 // Get the mod-Size index and lane correct it.
7307 int LaneIdx = (Mask[l + i] % NumElts) - l;
7308 // Make sure it was in this lane.
7309 if (LaneIdx < 0 || LaneIdx >= NumLaneElts)
7312 // Determine where a rotated vector would have started.
7313 int StartIdx = i - LaneIdx;
7315 // The identity rotation isn't interesting, stop.
7318 // If we found the tail of a vector the rotation must be the missing
7319 // front. If we found the head of a vector, it must be how much of the
7321 int CandidateRotation = StartIdx < 0 ? -StartIdx : NumLaneElts - StartIdx;
7324 Rotation = CandidateRotation;
7325 else if (Rotation != CandidateRotation)
7326 // The rotations don't match, so we can't match this mask.
7329 // Compute which value this mask is pointing at.
7330 SDValue MaskV = Mask[l + i] < NumElts ? V1 : V2;
7332 // Compute which of the two target values this index should be assigned
7333 // to. This reflects whether the high elements are remaining or the low
7334 // elements are remaining.
7335 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
7337 // Either set up this value if we've not encountered it before, or check
7338 // that it remains consistent.
7341 else if (TargetV != MaskV)
7342 // This may be a rotation, but it pulls from the inputs in some
7343 // unsupported interleaving.
7348 // Check that we successfully analyzed the mask, and normalize the results.
7349 assert(Rotation != 0 && "Failed to locate a viable rotation!");
7350 assert((Lo || Hi) && "Failed to find a rotated input vector!");
7356 // The actual rotate instruction rotates bytes, so we need to scale the
7357 // rotation based on how many bytes are in the vector lane.
7358 int Scale = 16 / NumLaneElts;
7360 // SSSE3 targets can use the palignr instruction.
7361 if (Subtarget->hasSSSE3()) {
7362 // Cast the inputs to i8 vector of correct length to match PALIGNR.
7363 MVT AlignVT = MVT::getVectorVT(MVT::i8, 16 * NumLanes);
7364 Lo = DAG.getBitcast(AlignVT, Lo);
7365 Hi = DAG.getBitcast(AlignVT, Hi);
7367 return DAG.getBitcast(
7368 VT, DAG.getNode(X86ISD::PALIGNR, DL, AlignVT, Lo, Hi,
7369 DAG.getConstant(Rotation * Scale, DL, MVT::i8)));
7372 assert(VT.is128BitVector() &&
7373 "Rotate-based lowering only supports 128-bit lowering!");
7374 assert(Mask.size() <= 16 &&
7375 "Can shuffle at most 16 bytes in a 128-bit vector!");
7377 // Default SSE2 implementation
7378 int LoByteShift = 16 - Rotation * Scale;
7379 int HiByteShift = Rotation * Scale;
7381 // Cast the inputs to v2i64 to match PSLLDQ/PSRLDQ.
7382 Lo = DAG.getBitcast(MVT::v2i64, Lo);
7383 Hi = DAG.getBitcast(MVT::v2i64, Hi);
7385 SDValue LoShift = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, Lo,
7386 DAG.getConstant(LoByteShift, DL, MVT::i8));
7387 SDValue HiShift = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, Hi,
7388 DAG.getConstant(HiByteShift, DL, MVT::i8));
7389 return DAG.getBitcast(VT,
7390 DAG.getNode(ISD::OR, DL, MVT::v2i64, LoShift, HiShift));
7393 /// \brief Try to lower a vector shuffle as a bit shift (shifts in zeros).
7395 /// Attempts to match a shuffle mask against the PSLL(W/D/Q/DQ) and
7396 /// PSRL(W/D/Q/DQ) SSE2 and AVX2 logical bit-shift instructions. The function
7397 /// matches elements from one of the input vectors shuffled to the left or
7398 /// right with zeroable elements 'shifted in'. It handles both the strictly
7399 /// bit-wise element shifts and the byte shift across an entire 128-bit double
7402 /// PSHL : (little-endian) left bit shift.
7403 /// [ zz, 0, zz, 2 ]
7404 /// [ -1, 4, zz, -1 ]
7405 /// PSRL : (little-endian) right bit shift.
7407 /// [ -1, -1, 7, zz]
7408 /// PSLLDQ : (little-endian) left byte shift
7409 /// [ zz, 0, 1, 2, 3, 4, 5, 6]
7410 /// [ zz, zz, -1, -1, 2, 3, 4, -1]
7411 /// [ zz, zz, zz, zz, zz, zz, -1, 1]
7412 /// PSRLDQ : (little-endian) right byte shift
7413 /// [ 5, 6, 7, zz, zz, zz, zz, zz]
7414 /// [ -1, 5, 6, 7, zz, zz, zz, zz]
7415 /// [ 1, 2, -1, -1, -1, -1, zz, zz]
7416 static SDValue lowerVectorShuffleAsShift(SDLoc DL, MVT VT, SDValue V1,
7417 SDValue V2, ArrayRef<int> Mask,
7418 SelectionDAG &DAG) {
7419 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7421 int Size = Mask.size();
7422 assert(Size == (int)VT.getVectorNumElements() && "Unexpected mask size");
7424 auto CheckZeros = [&](int Shift, int Scale, bool Left) {
7425 for (int i = 0; i < Size; i += Scale)
7426 for (int j = 0; j < Shift; ++j)
7427 if (!Zeroable[i + j + (Left ? 0 : (Scale - Shift))])
7433 auto MatchShift = [&](int Shift, int Scale, bool Left, SDValue V) {
7434 for (int i = 0; i != Size; i += Scale) {
7435 unsigned Pos = Left ? i + Shift : i;
7436 unsigned Low = Left ? i : i + Shift;
7437 unsigned Len = Scale - Shift;
7438 if (!isSequentialOrUndefInRange(Mask, Pos, Len,
7439 Low + (V == V1 ? 0 : Size)))
7443 int ShiftEltBits = VT.getScalarSizeInBits() * Scale;
7444 bool ByteShift = ShiftEltBits > 64;
7445 unsigned OpCode = Left ? (ByteShift ? X86ISD::VSHLDQ : X86ISD::VSHLI)
7446 : (ByteShift ? X86ISD::VSRLDQ : X86ISD::VSRLI);
7447 int ShiftAmt = Shift * VT.getScalarSizeInBits() / (ByteShift ? 8 : 1);
7449 // Normalize the scale for byte shifts to still produce an i64 element
7451 Scale = ByteShift ? Scale / 2 : Scale;
7453 // We need to round trip through the appropriate type for the shift.
7454 MVT ShiftSVT = MVT::getIntegerVT(VT.getScalarSizeInBits() * Scale);
7455 MVT ShiftVT = MVT::getVectorVT(ShiftSVT, Size / Scale);
7456 assert(DAG.getTargetLoweringInfo().isTypeLegal(ShiftVT) &&
7457 "Illegal integer vector type");
7458 V = DAG.getBitcast(ShiftVT, V);
7460 V = DAG.getNode(OpCode, DL, ShiftVT, V,
7461 DAG.getConstant(ShiftAmt, DL, MVT::i8));
7462 return DAG.getBitcast(VT, V);
7465 // SSE/AVX supports logical shifts up to 64-bit integers - so we can just
7466 // keep doubling the size of the integer elements up to that. We can
7467 // then shift the elements of the integer vector by whole multiples of
7468 // their width within the elements of the larger integer vector. Test each
7469 // multiple to see if we can find a match with the moved element indices
7470 // and that the shifted in elements are all zeroable.
7471 for (int Scale = 2; Scale * VT.getScalarSizeInBits() <= 128; Scale *= 2)
7472 for (int Shift = 1; Shift != Scale; ++Shift)
7473 for (bool Left : {true, false})
7474 if (CheckZeros(Shift, Scale, Left))
7475 for (SDValue V : {V1, V2})
7476 if (SDValue Match = MatchShift(Shift, Scale, Left, V))
7483 /// \brief Try to lower a vector shuffle using SSE4a EXTRQ/INSERTQ.
7484 static SDValue lowerVectorShuffleWithSSE4A(SDLoc DL, MVT VT, SDValue V1,
7485 SDValue V2, ArrayRef<int> Mask,
7486 SelectionDAG &DAG) {
7487 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7488 assert(!Zeroable.all() && "Fully zeroable shuffle mask");
7490 int Size = Mask.size();
7491 int HalfSize = Size / 2;
7492 assert(Size == (int)VT.getVectorNumElements() && "Unexpected mask size");
7494 // Upper half must be undefined.
7495 if (!isUndefInRange(Mask, HalfSize, HalfSize))
7498 // EXTRQ: Extract Len elements from lower half of source, starting at Idx.
7499 // Remainder of lower half result is zero and upper half is all undef.
7500 auto LowerAsEXTRQ = [&]() {
7501 // Determine the extraction length from the part of the
7502 // lower half that isn't zeroable.
7504 for (; Len > 0; --Len)
7505 if (!Zeroable[Len - 1])
7507 assert(Len > 0 && "Zeroable shuffle mask");
7509 // Attempt to match first Len sequential elements from the lower half.
7512 for (int i = 0; i != Len; ++i) {
7516 SDValue &V = (M < Size ? V1 : V2);
7519 // The extracted elements must start at a valid index and all mask
7520 // elements must be in the lower half.
7521 if (i > M || M >= HalfSize)
7524 if (Idx < 0 || (Src == V && Idx == (M - i))) {
7535 assert((Idx + Len) <= HalfSize && "Illegal extraction mask");
7536 int BitLen = (Len * VT.getScalarSizeInBits()) & 0x3f;
7537 int BitIdx = (Idx * VT.getScalarSizeInBits()) & 0x3f;
7538 return DAG.getNode(X86ISD::EXTRQI, DL, VT, Src,
7539 DAG.getConstant(BitLen, DL, MVT::i8),
7540 DAG.getConstant(BitIdx, DL, MVT::i8));
7543 if (SDValue ExtrQ = LowerAsEXTRQ())
7546 // INSERTQ: Extract lowest Len elements from lower half of second source and
7547 // insert over first source, starting at Idx.
7548 // { A[0], .., A[Idx-1], B[0], .., B[Len-1], A[Idx+Len], .., UNDEF, ... }
7549 auto LowerAsInsertQ = [&]() {
7550 for (int Idx = 0; Idx != HalfSize; ++Idx) {
7553 // Attempt to match first source from mask before insertion point.
7554 if (isUndefInRange(Mask, 0, Idx)) {
7556 } else if (isSequentialOrUndefInRange(Mask, 0, Idx, 0)) {
7558 } else if (isSequentialOrUndefInRange(Mask, 0, Idx, Size)) {
7564 // Extend the extraction length looking to match both the insertion of
7565 // the second source and the remaining elements of the first.
7566 for (int Hi = Idx + 1; Hi <= HalfSize; ++Hi) {
7571 if (isSequentialOrUndefInRange(Mask, Idx, Len, 0)) {
7573 } else if (isSequentialOrUndefInRange(Mask, Idx, Len, Size)) {
7579 // Match the remaining elements of the lower half.
7580 if (isUndefInRange(Mask, Hi, HalfSize - Hi)) {
7582 } else if ((!Base || (Base == V1)) &&
7583 isSequentialOrUndefInRange(Mask, Hi, HalfSize - Hi, Hi)) {
7585 } else if ((!Base || (Base == V2)) &&
7586 isSequentialOrUndefInRange(Mask, Hi, HalfSize - Hi,
7593 // We may not have a base (first source) - this can safely be undefined.
7595 Base = DAG.getUNDEF(VT);
7597 int BitLen = (Len * VT.getScalarSizeInBits()) & 0x3f;
7598 int BitIdx = (Idx * VT.getScalarSizeInBits()) & 0x3f;
7599 return DAG.getNode(X86ISD::INSERTQI, DL, VT, Base, Insert,
7600 DAG.getConstant(BitLen, DL, MVT::i8),
7601 DAG.getConstant(BitIdx, DL, MVT::i8));
7608 if (SDValue InsertQ = LowerAsInsertQ())
7614 /// \brief Lower a vector shuffle as a zero or any extension.
7616 /// Given a specific number of elements, element bit width, and extension
7617 /// stride, produce either a zero or any extension based on the available
7618 /// features of the subtarget. The extended elements are consecutive and
7619 /// begin and can start from an offseted element index in the input; to
7620 /// avoid excess shuffling the offset must either being in the bottom lane
7621 /// or at the start of a higher lane. All extended elements must be from
7623 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7624 SDLoc DL, MVT VT, int Scale, int Offset, bool AnyExt, SDValue InputV,
7625 ArrayRef<int> Mask, const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7626 assert(Scale > 1 && "Need a scale to extend.");
7627 int EltBits = VT.getScalarSizeInBits();
7628 int NumElements = VT.getVectorNumElements();
7629 int NumEltsPerLane = 128 / EltBits;
7630 int OffsetLane = Offset / NumEltsPerLane;
7631 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
7632 "Only 8, 16, and 32 bit elements can be extended.");
7633 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
7634 assert(0 <= Offset && "Extension offset must be positive.");
7635 assert((Offset < NumEltsPerLane || Offset % NumEltsPerLane == 0) &&
7636 "Extension offset must be in the first lane or start an upper lane.");
7638 // Check that an index is in same lane as the base offset.
7639 auto SafeOffset = [&](int Idx) {
7640 return OffsetLane == (Idx / NumEltsPerLane);
7643 // Shift along an input so that the offset base moves to the first element.
7644 auto ShuffleOffset = [&](SDValue V) {
7648 SmallVector<int, 8> ShMask((unsigned)NumElements, -1);
7649 for (int i = 0; i * Scale < NumElements; ++i) {
7650 int SrcIdx = i + Offset;
7651 ShMask[i] = SafeOffset(SrcIdx) ? SrcIdx : -1;
7653 return DAG.getVectorShuffle(VT, DL, V, DAG.getUNDEF(VT), ShMask);
7656 // Found a valid zext mask! Try various lowering strategies based on the
7657 // input type and available ISA extensions.
7658 if (Subtarget->hasSSE41()) {
7659 // Not worth offseting 128-bit vectors if scale == 2, a pattern using
7660 // PUNPCK will catch this in a later shuffle match.
7661 if (Offset && Scale == 2 && VT.is128BitVector())
7663 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
7664 NumElements / Scale);
7665 InputV = DAG.getNode(X86ISD::VZEXT, DL, ExtVT, ShuffleOffset(InputV));
7666 return DAG.getBitcast(VT, InputV);
7669 assert(VT.is128BitVector() && "Only 128-bit vectors can be extended.");
7671 // For any extends we can cheat for larger element sizes and use shuffle
7672 // instructions that can fold with a load and/or copy.
7673 if (AnyExt && EltBits == 32) {
7674 int PSHUFDMask[4] = {Offset, -1, SafeOffset(Offset + 1) ? Offset + 1 : -1,
7676 return DAG.getBitcast(
7677 VT, DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7678 DAG.getBitcast(MVT::v4i32, InputV),
7679 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
7681 if (AnyExt && EltBits == 16 && Scale > 2) {
7682 int PSHUFDMask[4] = {Offset / 2, -1,
7683 SafeOffset(Offset + 1) ? (Offset + 1) / 2 : -1, -1};
7684 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7685 DAG.getBitcast(MVT::v4i32, InputV),
7686 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG));
7687 int PSHUFWMask[4] = {1, -1, -1, -1};
7688 unsigned OddEvenOp = (Offset & 1 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW);
7689 return DAG.getBitcast(
7690 VT, DAG.getNode(OddEvenOp, DL, MVT::v8i16,
7691 DAG.getBitcast(MVT::v8i16, InputV),
7692 getV4X86ShuffleImm8ForMask(PSHUFWMask, DL, DAG)));
7695 // The SSE4A EXTRQ instruction can efficiently extend the first 2 lanes
7697 if ((Scale * EltBits) == 64 && EltBits < 32 && Subtarget->hasSSE4A()) {
7698 assert(NumElements == (int)Mask.size() && "Unexpected shuffle mask size!");
7699 assert(VT.is128BitVector() && "Unexpected vector width!");
7701 int LoIdx = Offset * EltBits;
7702 SDValue Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7703 DAG.getNode(X86ISD::EXTRQI, DL, VT, InputV,
7704 DAG.getConstant(EltBits, DL, MVT::i8),
7705 DAG.getConstant(LoIdx, DL, MVT::i8)));
7707 if (isUndefInRange(Mask, NumElements / 2, NumElements / 2) ||
7708 !SafeOffset(Offset + 1))
7709 return DAG.getNode(ISD::BITCAST, DL, VT, Lo);
7711 int HiIdx = (Offset + 1) * EltBits;
7712 SDValue Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7713 DAG.getNode(X86ISD::EXTRQI, DL, VT, InputV,
7714 DAG.getConstant(EltBits, DL, MVT::i8),
7715 DAG.getConstant(HiIdx, DL, MVT::i8)));
7716 return DAG.getNode(ISD::BITCAST, DL, VT,
7717 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, Lo, Hi));
7720 // If this would require more than 2 unpack instructions to expand, use
7721 // pshufb when available. We can only use more than 2 unpack instructions
7722 // when zero extending i8 elements which also makes it easier to use pshufb.
7723 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
7724 assert(NumElements == 16 && "Unexpected byte vector width!");
7725 SDValue PSHUFBMask[16];
7726 for (int i = 0; i < 16; ++i) {
7727 int Idx = Offset + (i / Scale);
7728 PSHUFBMask[i] = DAG.getConstant(
7729 (i % Scale == 0 && SafeOffset(Idx)) ? Idx : 0x80, DL, MVT::i8);
7731 InputV = DAG.getBitcast(MVT::v16i8, InputV);
7732 return DAG.getBitcast(VT,
7733 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
7734 DAG.getNode(ISD::BUILD_VECTOR, DL,
7735 MVT::v16i8, PSHUFBMask)));
7738 // If we are extending from an offset, ensure we start on a boundary that
7739 // we can unpack from.
7740 int AlignToUnpack = Offset % (NumElements / Scale);
7741 if (AlignToUnpack) {
7742 SmallVector<int, 8> ShMask((unsigned)NumElements, -1);
7743 for (int i = AlignToUnpack; i < NumElements; ++i)
7744 ShMask[i - AlignToUnpack] = i;
7745 InputV = DAG.getVectorShuffle(VT, DL, InputV, DAG.getUNDEF(VT), ShMask);
7746 Offset -= AlignToUnpack;
7749 // Otherwise emit a sequence of unpacks.
7751 unsigned UnpackLoHi = X86ISD::UNPCKL;
7752 if (Offset >= (NumElements / 2)) {
7753 UnpackLoHi = X86ISD::UNPCKH;
7754 Offset -= (NumElements / 2);
7757 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7758 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
7759 : getZeroVector(InputVT, Subtarget, DAG, DL);
7760 InputV = DAG.getBitcast(InputVT, InputV);
7761 InputV = DAG.getNode(UnpackLoHi, DL, InputVT, InputV, Ext);
7765 } while (Scale > 1);
7766 return DAG.getBitcast(VT, InputV);
7769 /// \brief Try to lower a vector shuffle as a zero extension on any microarch.
7771 /// This routine will try to do everything in its power to cleverly lower
7772 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
7773 /// check for the profitability of this lowering, it tries to aggressively
7774 /// match this pattern. It will use all of the micro-architectural details it
7775 /// can to emit an efficient lowering. It handles both blends with all-zero
7776 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
7777 /// masking out later).
7779 /// The reason we have dedicated lowering for zext-style shuffles is that they
7780 /// are both incredibly common and often quite performance sensitive.
7781 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
7782 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7783 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7784 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7786 int Bits = VT.getSizeInBits();
7787 int NumLanes = Bits / 128;
7788 int NumElements = VT.getVectorNumElements();
7789 int NumEltsPerLane = NumElements / NumLanes;
7790 assert(VT.getScalarSizeInBits() <= 32 &&
7791 "Exceeds 32-bit integer zero extension limit");
7792 assert((int)Mask.size() == NumElements && "Unexpected shuffle mask size");
7794 // Define a helper function to check a particular ext-scale and lower to it if
7796 auto Lower = [&](int Scale) -> SDValue {
7801 for (int i = 0; i < NumElements; ++i) {
7804 continue; // Valid anywhere but doesn't tell us anything.
7805 if (i % Scale != 0) {
7806 // Each of the extended elements need to be zeroable.
7810 // We no longer are in the anyext case.
7815 // Each of the base elements needs to be consecutive indices into the
7816 // same input vector.
7817 SDValue V = M < NumElements ? V1 : V2;
7818 M = M % NumElements;
7821 Offset = M - (i / Scale);
7822 } else if (InputV != V)
7823 return SDValue(); // Flip-flopping inputs.
7825 // Offset must start in the lowest 128-bit lane or at the start of an
7827 // FIXME: Is it ever worth allowing a negative base offset?
7828 if (!((0 <= Offset && Offset < NumEltsPerLane) ||
7829 (Offset % NumEltsPerLane) == 0))
7832 // If we are offsetting, all referenced entries must come from the same
7834 if (Offset && (Offset / NumEltsPerLane) != (M / NumEltsPerLane))
7837 if ((M % NumElements) != (Offset + (i / Scale)))
7838 return SDValue(); // Non-consecutive strided elements.
7842 // If we fail to find an input, we have a zero-shuffle which should always
7843 // have already been handled.
7844 // FIXME: Maybe handle this here in case during blending we end up with one?
7848 // If we are offsetting, don't extend if we only match a single input, we
7849 // can always do better by using a basic PSHUF or PUNPCK.
7850 if (Offset != 0 && Matches < 2)
7853 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7854 DL, VT, Scale, Offset, AnyExt, InputV, Mask, Subtarget, DAG);
7857 // The widest scale possible for extending is to a 64-bit integer.
7858 assert(Bits % 64 == 0 &&
7859 "The number of bits in a vector must be divisible by 64 on x86!");
7860 int NumExtElements = Bits / 64;
7862 // Each iteration, try extending the elements half as much, but into twice as
7864 for (; NumExtElements < NumElements; NumExtElements *= 2) {
7865 assert(NumElements % NumExtElements == 0 &&
7866 "The input vector size must be divisible by the extended size.");
7867 if (SDValue V = Lower(NumElements / NumExtElements))
7871 // General extends failed, but 128-bit vectors may be able to use MOVQ.
7875 // Returns one of the source operands if the shuffle can be reduced to a
7876 // MOVQ, copying the lower 64-bits and zero-extending to the upper 64-bits.
7877 auto CanZExtLowHalf = [&]() {
7878 for (int i = NumElements / 2; i != NumElements; ++i)
7881 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, 0))
7883 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, NumElements))
7888 if (SDValue V = CanZExtLowHalf()) {
7889 V = DAG.getBitcast(MVT::v2i64, V);
7890 V = DAG.getNode(X86ISD::VZEXT_MOVL, DL, MVT::v2i64, V);
7891 return DAG.getBitcast(VT, V);
7894 // No viable ext lowering found.
7898 /// \brief Try to get a scalar value for a specific element of a vector.
7900 /// Looks through BUILD_VECTOR and SCALAR_TO_VECTOR nodes to find a scalar.
7901 static SDValue getScalarValueForVectorElement(SDValue V, int Idx,
7902 SelectionDAG &DAG) {
7903 MVT VT = V.getSimpleValueType();
7904 MVT EltVT = VT.getVectorElementType();
7905 while (V.getOpcode() == ISD::BITCAST)
7906 V = V.getOperand(0);
7907 // If the bitcasts shift the element size, we can't extract an equivalent
7909 MVT NewVT = V.getSimpleValueType();
7910 if (!NewVT.isVector() || NewVT.getScalarSizeInBits() != VT.getScalarSizeInBits())
7913 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7914 (Idx == 0 && V.getOpcode() == ISD::SCALAR_TO_VECTOR)) {
7915 // Ensure the scalar operand is the same size as the destination.
7916 // FIXME: Add support for scalar truncation where possible.
7917 SDValue S = V.getOperand(Idx);
7918 if (EltVT.getSizeInBits() == S.getSimpleValueType().getSizeInBits())
7919 return DAG.getNode(ISD::BITCAST, SDLoc(V), EltVT, S);
7925 /// \brief Helper to test for a load that can be folded with x86 shuffles.
7927 /// This is particularly important because the set of instructions varies
7928 /// significantly based on whether the operand is a load or not.
7929 static bool isShuffleFoldableLoad(SDValue V) {
7930 while (V.getOpcode() == ISD::BITCAST)
7931 V = V.getOperand(0);
7933 return ISD::isNON_EXTLoad(V.getNode());
7936 /// \brief Try to lower insertion of a single element into a zero vector.
7938 /// This is a common pattern that we have especially efficient patterns to lower
7939 /// across all subtarget feature sets.
7940 static SDValue lowerVectorShuffleAsElementInsertion(
7941 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7942 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7943 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7945 MVT EltVT = VT.getVectorElementType();
7947 int V2Index = std::find_if(Mask.begin(), Mask.end(),
7948 [&Mask](int M) { return M >= (int)Mask.size(); }) -
7950 bool IsV1Zeroable = true;
7951 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7952 if (i != V2Index && !Zeroable[i]) {
7953 IsV1Zeroable = false;
7957 // Check for a single input from a SCALAR_TO_VECTOR node.
7958 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
7959 // all the smarts here sunk into that routine. However, the current
7960 // lowering of BUILD_VECTOR makes that nearly impossible until the old
7961 // vector shuffle lowering is dead.
7962 SDValue V2S = getScalarValueForVectorElement(V2, Mask[V2Index] - Mask.size(),
7964 if (V2S && DAG.getTargetLoweringInfo().isTypeLegal(V2S.getValueType())) {
7965 // We need to zext the scalar if it is smaller than an i32.
7966 V2S = DAG.getBitcast(EltVT, V2S);
7967 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
7968 // Using zext to expand a narrow element won't work for non-zero
7973 // Zero-extend directly to i32.
7975 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
7977 V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S);
7978 } else if (Mask[V2Index] != (int)Mask.size() || EltVT == MVT::i8 ||
7979 EltVT == MVT::i16) {
7980 // Either not inserting from the low element of the input or the input
7981 // element size is too small to use VZEXT_MOVL to clear the high bits.
7985 if (!IsV1Zeroable) {
7986 // If V1 can't be treated as a zero vector we have fewer options to lower
7987 // this. We can't support integer vectors or non-zero targets cheaply, and
7988 // the V1 elements can't be permuted in any way.
7989 assert(VT == ExtVT && "Cannot change extended type when non-zeroable!");
7990 if (!VT.isFloatingPoint() || V2Index != 0)
7992 SmallVector<int, 8> V1Mask(Mask.begin(), Mask.end());
7993 V1Mask[V2Index] = -1;
7994 if (!isNoopShuffleMask(V1Mask))
7996 // This is essentially a special case blend operation, but if we have
7997 // general purpose blend operations, they are always faster. Bail and let
7998 // the rest of the lowering handle these as blends.
7999 if (Subtarget->hasSSE41())
8002 // Otherwise, use MOVSD or MOVSS.
8003 assert((EltVT == MVT::f32 || EltVT == MVT::f64) &&
8004 "Only two types of floating point element types to handle!");
8005 return DAG.getNode(EltVT == MVT::f32 ? X86ISD::MOVSS : X86ISD::MOVSD, DL,
8009 // This lowering only works for the low element with floating point vectors.
8010 if (VT.isFloatingPoint() && V2Index != 0)
8013 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT, V2);
8015 V2 = DAG.getBitcast(VT, V2);
8018 // If we have 4 or fewer lanes we can cheaply shuffle the element into
8019 // the desired position. Otherwise it is more efficient to do a vector
8020 // shift left. We know that we can do a vector shift left because all
8021 // the inputs are zero.
8022 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
8023 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
8024 V2Shuffle[V2Index] = 0;
8025 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
8027 V2 = DAG.getBitcast(MVT::v2i64, V2);
8029 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
8030 DAG.getConstant(V2Index * EltVT.getSizeInBits() / 8, DL,
8031 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(
8032 DAG.getDataLayout(), VT)));
8033 V2 = DAG.getBitcast(VT, V2);
8039 /// \brief Try to lower broadcast of a single - truncated - integer element,
8040 /// coming from a scalar_to_vector/build_vector node \p V0 with larger elements.
8042 /// This assumes we have AVX2.
8043 static SDValue lowerVectorShuffleAsTruncBroadcast(SDLoc DL, MVT VT, SDValue V0,
8045 const X86Subtarget *Subtarget,
8046 SelectionDAG &DAG) {
8047 assert(Subtarget->hasAVX2() &&
8048 "We can only lower integer broadcasts with AVX2!");
8050 EVT EltVT = VT.getVectorElementType();
8051 EVT V0VT = V0.getValueType();
8053 assert(VT.isInteger() && "Unexpected non-integer trunc broadcast!");
8054 assert(V0VT.isVector() && "Unexpected non-vector vector-sized value!");
8056 EVT V0EltVT = V0VT.getVectorElementType();
8057 if (!V0EltVT.isInteger())
8060 const unsigned EltSize = EltVT.getSizeInBits();
8061 const unsigned V0EltSize = V0EltVT.getSizeInBits();
8063 // This is only a truncation if the original element type is larger.
8064 if (V0EltSize <= EltSize)
8067 assert(((V0EltSize % EltSize) == 0) &&
8068 "Scalar type sizes must all be powers of 2 on x86!");
8070 const unsigned V0Opc = V0.getOpcode();
8071 const unsigned Scale = V0EltSize / EltSize;
8072 const unsigned V0BroadcastIdx = BroadcastIdx / Scale;
8074 if ((V0Opc != ISD::SCALAR_TO_VECTOR || V0BroadcastIdx != 0) &&
8075 V0Opc != ISD::BUILD_VECTOR)
8078 SDValue Scalar = V0.getOperand(V0BroadcastIdx);
8080 // If we're extracting non-least-significant bits, shift so we can truncate.
8081 // Hopefully, we can fold away the trunc/srl/load into the broadcast.
8082 // Even if we can't (and !isShuffleFoldableLoad(Scalar)), prefer
8083 // vpbroadcast+vmovd+shr to vpshufb(m)+vmovd.
8084 if (const int OffsetIdx = BroadcastIdx % Scale)
8085 Scalar = DAG.getNode(ISD::SRL, DL, Scalar.getValueType(), Scalar,
8086 DAG.getConstant(OffsetIdx * EltSize, DL, Scalar.getValueType()));
8088 return DAG.getNode(X86ISD::VBROADCAST, DL, VT,
8089 DAG.getNode(ISD::TRUNCATE, DL, EltVT, Scalar));
8092 /// \brief Try to lower broadcast of a single element.
8094 /// For convenience, this code also bundles all of the subtarget feature set
8095 /// filtering. While a little annoying to re-dispatch on type here, there isn't
8096 /// a convenient way to factor it out.
8097 /// FIXME: This is very similar to LowerVectorBroadcast - can we merge them?
8098 static SDValue lowerVectorShuffleAsBroadcast(SDLoc DL, MVT VT, SDValue V,
8100 const X86Subtarget *Subtarget,
8101 SelectionDAG &DAG) {
8102 if (!Subtarget->hasAVX())
8104 if (VT.isInteger() && !Subtarget->hasAVX2())
8107 // Check that the mask is a broadcast.
8108 int BroadcastIdx = -1;
8110 if (M >= 0 && BroadcastIdx == -1)
8112 else if (M >= 0 && M != BroadcastIdx)
8115 assert(BroadcastIdx < (int)Mask.size() && "We only expect to be called with "
8116 "a sorted mask where the broadcast "
8119 // Go up the chain of (vector) values to find a scalar load that we can
8120 // combine with the broadcast.
8122 switch (V.getOpcode()) {
8123 case ISD::CONCAT_VECTORS: {
8124 int OperandSize = Mask.size() / V.getNumOperands();
8125 V = V.getOperand(BroadcastIdx / OperandSize);
8126 BroadcastIdx %= OperandSize;
8130 case ISD::INSERT_SUBVECTOR: {
8131 SDValue VOuter = V.getOperand(0), VInner = V.getOperand(1);
8132 auto ConstantIdx = dyn_cast<ConstantSDNode>(V.getOperand(2));
8136 int BeginIdx = (int)ConstantIdx->getZExtValue();
8138 BeginIdx + (int)VInner.getSimpleValueType().getVectorNumElements();
8139 if (BroadcastIdx >= BeginIdx && BroadcastIdx < EndIdx) {
8140 BroadcastIdx -= BeginIdx;
8151 // Check if this is a broadcast of a scalar. We special case lowering
8152 // for scalars so that we can more effectively fold with loads.
8153 // First, look through bitcast: if the original value has a larger element
8154 // type than the shuffle, the broadcast element is in essence truncated.
8155 // Make that explicit to ease folding.
8156 if (V.getOpcode() == ISD::BITCAST && VT.isInteger())
8157 if (SDValue TruncBroadcast = lowerVectorShuffleAsTruncBroadcast(
8158 DL, VT, V.getOperand(0), BroadcastIdx, Subtarget, DAG))
8159 return TruncBroadcast;
8161 // Also check the simpler case, where we can directly reuse the scalar.
8162 if (V.getOpcode() == ISD::BUILD_VECTOR ||
8163 (V.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)) {
8164 V = V.getOperand(BroadcastIdx);
8166 // If the scalar isn't a load, we can't broadcast from it in AVX1.
8167 // Only AVX2 has register broadcasts.
8168 if (!Subtarget->hasAVX2() && !isShuffleFoldableLoad(V))
8170 } else if (MayFoldLoad(V) && !cast<LoadSDNode>(V)->isVolatile()) {
8171 // If we are broadcasting a load that is only used by the shuffle
8172 // then we can reduce the vector load to the broadcasted scalar load.
8173 LoadSDNode *Ld = cast<LoadSDNode>(V);
8174 SDValue BaseAddr = Ld->getOperand(1);
8175 EVT AddrVT = BaseAddr.getValueType();
8176 EVT SVT = VT.getScalarType();
8177 unsigned Offset = BroadcastIdx * SVT.getStoreSize();
8178 SDValue NewAddr = DAG.getNode(
8179 ISD::ADD, DL, AddrVT, BaseAddr,
8180 DAG.getConstant(Offset, DL, AddrVT));
8181 V = DAG.getLoad(SVT, DL, Ld->getChain(), NewAddr,
8182 DAG.getMachineFunction().getMachineMemOperand(
8183 Ld->getMemOperand(), Offset, SVT.getStoreSize()));
8184 } else if (BroadcastIdx != 0 || !Subtarget->hasAVX2()) {
8185 // We can't broadcast from a vector register without AVX2, and we can only
8186 // broadcast from the zero-element of a vector register.
8190 return DAG.getNode(X86ISD::VBROADCAST, DL, VT, V);
8193 // Check for whether we can use INSERTPS to perform the shuffle. We only use
8194 // INSERTPS when the V1 elements are already in the correct locations
8195 // because otherwise we can just always use two SHUFPS instructions which
8196 // are much smaller to encode than a SHUFPS and an INSERTPS. We can also
8197 // perform INSERTPS if a single V1 element is out of place and all V2
8198 // elements are zeroable.
8199 static SDValue lowerVectorShuffleAsInsertPS(SDValue Op, SDValue V1, SDValue V2,
8201 SelectionDAG &DAG) {
8202 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
8203 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8204 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8205 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8207 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
8210 int V1DstIndex = -1;
8211 int V2DstIndex = -1;
8212 bool V1UsedInPlace = false;
8214 for (int i = 0; i < 4; ++i) {
8215 // Synthesize a zero mask from the zeroable elements (includes undefs).
8221 // Flag if we use any V1 inputs in place.
8223 V1UsedInPlace = true;
8227 // We can only insert a single non-zeroable element.
8228 if (V1DstIndex != -1 || V2DstIndex != -1)
8232 // V1 input out of place for insertion.
8235 // V2 input for insertion.
8240 // Don't bother if we have no (non-zeroable) element for insertion.
8241 if (V1DstIndex == -1 && V2DstIndex == -1)
8244 // Determine element insertion src/dst indices. The src index is from the
8245 // start of the inserted vector, not the start of the concatenated vector.
8246 unsigned V2SrcIndex = 0;
8247 if (V1DstIndex != -1) {
8248 // If we have a V1 input out of place, we use V1 as the V2 element insertion
8249 // and don't use the original V2 at all.
8250 V2SrcIndex = Mask[V1DstIndex];
8251 V2DstIndex = V1DstIndex;
8254 V2SrcIndex = Mask[V2DstIndex] - 4;
8257 // If no V1 inputs are used in place, then the result is created only from
8258 // the zero mask and the V2 insertion - so remove V1 dependency.
8260 V1 = DAG.getUNDEF(MVT::v4f32);
8262 unsigned InsertPSMask = V2SrcIndex << 6 | V2DstIndex << 4 | ZMask;
8263 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
8265 // Insert the V2 element into the desired position.
8267 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
8268 DAG.getConstant(InsertPSMask, DL, MVT::i8));
8271 /// \brief Try to lower a shuffle as a permute of the inputs followed by an
8272 /// UNPCK instruction.
8274 /// This specifically targets cases where we end up with alternating between
8275 /// the two inputs, and so can permute them into something that feeds a single
8276 /// UNPCK instruction. Note that this routine only targets integer vectors
8277 /// because for floating point vectors we have a generalized SHUFPS lowering
8278 /// strategy that handles everything that doesn't *exactly* match an unpack,
8279 /// making this clever lowering unnecessary.
8280 static SDValue lowerVectorShuffleAsPermuteAndUnpack(SDLoc DL, MVT VT,
8281 SDValue V1, SDValue V2,
8283 SelectionDAG &DAG) {
8284 assert(!VT.isFloatingPoint() &&
8285 "This routine only supports integer vectors.");
8286 assert(!isSingleInputShuffleMask(Mask) &&
8287 "This routine should only be used when blending two inputs.");
8288 assert(Mask.size() >= 2 && "Single element masks are invalid.");
8290 int Size = Mask.size();
8292 int NumLoInputs = std::count_if(Mask.begin(), Mask.end(), [Size](int M) {
8293 return M >= 0 && M % Size < Size / 2;
8295 int NumHiInputs = std::count_if(
8296 Mask.begin(), Mask.end(), [Size](int M) { return M % Size >= Size / 2; });
8298 bool UnpackLo = NumLoInputs >= NumHiInputs;
8300 auto TryUnpack = [&](MVT UnpackVT, int Scale) {
8301 SmallVector<int, 32> V1Mask(Mask.size(), -1);
8302 SmallVector<int, 32> V2Mask(Mask.size(), -1);
8304 for (int i = 0; i < Size; ++i) {
8308 // Each element of the unpack contains Scale elements from this mask.
8309 int UnpackIdx = i / Scale;
8311 // We only handle the case where V1 feeds the first slots of the unpack.
8312 // We rely on canonicalization to ensure this is the case.
8313 if ((UnpackIdx % 2 == 0) != (Mask[i] < Size))
8316 // Setup the mask for this input. The indexing is tricky as we have to
8317 // handle the unpack stride.
8318 SmallVectorImpl<int> &VMask = (UnpackIdx % 2 == 0) ? V1Mask : V2Mask;
8319 VMask[(UnpackIdx / 2) * Scale + i % Scale + (UnpackLo ? 0 : Size / 2)] =
8323 // If we will have to shuffle both inputs to use the unpack, check whether
8324 // we can just unpack first and shuffle the result. If so, skip this unpack.
8325 if ((NumLoInputs == 0 || NumHiInputs == 0) && !isNoopShuffleMask(V1Mask) &&
8326 !isNoopShuffleMask(V2Mask))
8329 // Shuffle the inputs into place.
8330 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
8331 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
8333 // Cast the inputs to the type we will use to unpack them.
8334 V1 = DAG.getBitcast(UnpackVT, V1);
8335 V2 = DAG.getBitcast(UnpackVT, V2);
8337 // Unpack the inputs and cast the result back to the desired type.
8338 return DAG.getBitcast(
8339 VT, DAG.getNode(UnpackLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
8343 // We try each unpack from the largest to the smallest to try and find one
8344 // that fits this mask.
8345 int OrigNumElements = VT.getVectorNumElements();
8346 int OrigScalarSize = VT.getScalarSizeInBits();
8347 for (int ScalarSize = 64; ScalarSize >= OrigScalarSize; ScalarSize /= 2) {
8348 int Scale = ScalarSize / OrigScalarSize;
8349 int NumElements = OrigNumElements / Scale;
8350 MVT UnpackVT = MVT::getVectorVT(MVT::getIntegerVT(ScalarSize), NumElements);
8351 if (SDValue Unpack = TryUnpack(UnpackVT, Scale))
8355 // If none of the unpack-rooted lowerings worked (or were profitable) try an
8357 if (NumLoInputs == 0 || NumHiInputs == 0) {
8358 assert((NumLoInputs > 0 || NumHiInputs > 0) &&
8359 "We have to have *some* inputs!");
8360 int HalfOffset = NumLoInputs == 0 ? Size / 2 : 0;
8362 // FIXME: We could consider the total complexity of the permute of each
8363 // possible unpacking. Or at the least we should consider how many
8364 // half-crossings are created.
8365 // FIXME: We could consider commuting the unpacks.
8367 SmallVector<int, 32> PermMask;
8368 PermMask.assign(Size, -1);
8369 for (int i = 0; i < Size; ++i) {
8373 assert(Mask[i] % Size >= HalfOffset && "Found input from wrong half!");
8376 2 * ((Mask[i] % Size) - HalfOffset) + (Mask[i] < Size ? 0 : 1);
8378 return DAG.getVectorShuffle(
8379 VT, DL, DAG.getNode(NumLoInputs == 0 ? X86ISD::UNPCKH : X86ISD::UNPCKL,
8381 DAG.getUNDEF(VT), PermMask);
8387 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
8389 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
8390 /// support for floating point shuffles but not integer shuffles. These
8391 /// instructions will incur a domain crossing penalty on some chips though so
8392 /// it is better to avoid lowering through this for integer vectors where
8394 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8395 const X86Subtarget *Subtarget,
8396 SelectionDAG &DAG) {
8398 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
8399 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8400 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8401 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8402 ArrayRef<int> Mask = SVOp->getMask();
8403 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8405 if (isSingleInputShuffleMask(Mask)) {
8406 // Use low duplicate instructions for masks that match their pattern.
8407 if (Subtarget->hasSSE3())
8408 if (isShuffleEquivalent(V1, V2, Mask, {0, 0}))
8409 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v2f64, V1);
8411 // Straight shuffle of a single input vector. Simulate this by using the
8412 // single input as both of the "inputs" to this instruction..
8413 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
8415 if (Subtarget->hasAVX()) {
8416 // If we have AVX, we can use VPERMILPS which will allow folding a load
8417 // into the shuffle.
8418 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
8419 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
8422 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v2f64, V1, V1,
8423 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
8425 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
8426 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
8428 // If we have a single input, insert that into V1 if we can do so cheaply.
8429 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
8430 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8431 DL, MVT::v2f64, V1, V2, Mask, Subtarget, DAG))
8433 // Try inverting the insertion since for v2 masks it is easy to do and we
8434 // can't reliably sort the mask one way or the other.
8435 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
8436 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
8437 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8438 DL, MVT::v2f64, V2, V1, InverseMask, Subtarget, DAG))
8442 // Try to use one of the special instruction patterns to handle two common
8443 // blend patterns if a zero-blend above didn't work.
8444 if (isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
8445 isShuffleEquivalent(V1, V2, Mask, {1, 3}))
8446 if (SDValue V1S = getScalarValueForVectorElement(V1, Mask[0], DAG))
8447 // We can either use a special instruction to load over the low double or
8448 // to move just the low double.
8450 isShuffleFoldableLoad(V1S) ? X86ISD::MOVLPD : X86ISD::MOVSD,
8452 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64, V1S));
8454 if (Subtarget->hasSSE41())
8455 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
8459 // Use dedicated unpack instructions for masks that match their pattern.
8461 lowerVectorShuffleWithUNPCK(DL, MVT::v2f64, Mask, V1, V2, DAG))
8464 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
8465 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v2f64, V1, V2,
8466 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
8469 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
8471 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
8472 /// the integer unit to minimize domain crossing penalties. However, for blends
8473 /// it falls back to the floating point shuffle operation with appropriate bit
8475 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8476 const X86Subtarget *Subtarget,
8477 SelectionDAG &DAG) {
8479 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
8480 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8481 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8482 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8483 ArrayRef<int> Mask = SVOp->getMask();
8484 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8486 if (isSingleInputShuffleMask(Mask)) {
8487 // Check for being able to broadcast a single element.
8488 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v2i64, V1,
8489 Mask, Subtarget, DAG))
8492 // Straight shuffle of a single input vector. For everything from SSE2
8493 // onward this has a single fast instruction with no scary immediates.
8494 // We have to map the mask as it is actually a v4i32 shuffle instruction.
8495 V1 = DAG.getBitcast(MVT::v4i32, V1);
8496 int WidenedMask[4] = {
8497 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
8498 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
8499 return DAG.getBitcast(
8501 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8502 getV4X86ShuffleImm8ForMask(WidenedMask, DL, DAG)));
8504 assert(Mask[0] != -1 && "No undef lanes in multi-input v2 shuffles!");
8505 assert(Mask[1] != -1 && "No undef lanes in multi-input v2 shuffles!");
8506 assert(Mask[0] < 2 && "We sort V1 to be the first input.");
8507 assert(Mask[1] >= 2 && "We sort V2 to be the second input.");
8509 // If we have a blend of two PACKUS operations an the blend aligns with the
8510 // low and half halves, we can just merge the PACKUS operations. This is
8511 // particularly important as it lets us merge shuffles that this routine itself
8513 auto GetPackNode = [](SDValue V) {
8514 while (V.getOpcode() == ISD::BITCAST)
8515 V = V.getOperand(0);
8517 return V.getOpcode() == X86ISD::PACKUS ? V : SDValue();
8519 if (SDValue V1Pack = GetPackNode(V1))
8520 if (SDValue V2Pack = GetPackNode(V2))
8521 return DAG.getBitcast(MVT::v2i64,
8522 DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8,
8523 Mask[0] == 0 ? V1Pack.getOperand(0)
8524 : V1Pack.getOperand(1),
8525 Mask[1] == 2 ? V2Pack.getOperand(0)
8526 : V2Pack.getOperand(1)));
8528 // Try to use shift instructions.
8530 lowerVectorShuffleAsShift(DL, MVT::v2i64, V1, V2, Mask, DAG))
8533 // When loading a scalar and then shuffling it into a vector we can often do
8534 // the insertion cheaply.
8535 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8536 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
8538 // Try inverting the insertion since for v2 masks it is easy to do and we
8539 // can't reliably sort the mask one way or the other.
8540 int InverseMask[2] = {Mask[0] ^ 2, Mask[1] ^ 2};
8541 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8542 DL, MVT::v2i64, V2, V1, InverseMask, Subtarget, DAG))
8545 // We have different paths for blend lowering, but they all must use the
8546 // *exact* same predicate.
8547 bool IsBlendSupported = Subtarget->hasSSE41();
8548 if (IsBlendSupported)
8549 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
8553 // Use dedicated unpack instructions for masks that match their pattern.
8555 lowerVectorShuffleWithUNPCK(DL, MVT::v2i64, Mask, V1, V2, DAG))
8558 // Try to use byte rotation instructions.
8559 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8560 if (Subtarget->hasSSSE3())
8561 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8562 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
8565 // If we have direct support for blends, we should lower by decomposing into
8566 // a permute. That will be faster than the domain cross.
8567 if (IsBlendSupported)
8568 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v2i64, V1, V2,
8571 // We implement this with SHUFPD which is pretty lame because it will likely
8572 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
8573 // However, all the alternatives are still more cycles and newer chips don't
8574 // have this problem. It would be really nice if x86 had better shuffles here.
8575 V1 = DAG.getBitcast(MVT::v2f64, V1);
8576 V2 = DAG.getBitcast(MVT::v2f64, V2);
8577 return DAG.getBitcast(MVT::v2i64,
8578 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
8581 /// \brief Test whether this can be lowered with a single SHUFPS instruction.
8583 /// This is used to disable more specialized lowerings when the shufps lowering
8584 /// will happen to be efficient.
8585 static bool isSingleSHUFPSMask(ArrayRef<int> Mask) {
8586 // This routine only handles 128-bit shufps.
8587 assert(Mask.size() == 4 && "Unsupported mask size!");
8589 // To lower with a single SHUFPS we need to have the low half and high half
8590 // each requiring a single input.
8591 if (Mask[0] != -1 && Mask[1] != -1 && (Mask[0] < 4) != (Mask[1] < 4))
8593 if (Mask[2] != -1 && Mask[3] != -1 && (Mask[2] < 4) != (Mask[3] < 4))
8599 /// \brief Lower a vector shuffle using the SHUFPS instruction.
8601 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
8602 /// It makes no assumptions about whether this is the *best* lowering, it simply
8604 static SDValue lowerVectorShuffleWithSHUFPS(SDLoc DL, MVT VT,
8605 ArrayRef<int> Mask, SDValue V1,
8606 SDValue V2, SelectionDAG &DAG) {
8607 SDValue LowV = V1, HighV = V2;
8608 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
8611 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8613 if (NumV2Elements == 1) {
8615 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8618 // Compute the index adjacent to V2Index and in the same half by toggling
8620 int V2AdjIndex = V2Index ^ 1;
8622 if (Mask[V2AdjIndex] == -1) {
8623 // Handles all the cases where we have a single V2 element and an undef.
8624 // This will only ever happen in the high lanes because we commute the
8625 // vector otherwise.
8627 std::swap(LowV, HighV);
8628 NewMask[V2Index] -= 4;
8630 // Handle the case where the V2 element ends up adjacent to a V1 element.
8631 // To make this work, blend them together as the first step.
8632 int V1Index = V2AdjIndex;
8633 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
8634 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
8635 getV4X86ShuffleImm8ForMask(BlendMask, DL, DAG));
8637 // Now proceed to reconstruct the final blend as we have the necessary
8638 // high or low half formed.
8645 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
8646 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
8648 } else if (NumV2Elements == 2) {
8649 if (Mask[0] < 4 && Mask[1] < 4) {
8650 // Handle the easy case where we have V1 in the low lanes and V2 in the
8654 } else if (Mask[2] < 4 && Mask[3] < 4) {
8655 // We also handle the reversed case because this utility may get called
8656 // when we detect a SHUFPS pattern but can't easily commute the shuffle to
8657 // arrange things in the right direction.
8663 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
8664 // trying to place elements directly, just blend them and set up the final
8665 // shuffle to place them.
8667 // The first two blend mask elements are for V1, the second two are for
8669 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
8670 Mask[2] < 4 ? Mask[2] : Mask[3],
8671 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
8672 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
8673 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
8674 getV4X86ShuffleImm8ForMask(BlendMask, DL, DAG));
8676 // Now we do a normal shuffle of V1 by giving V1 as both operands to
8679 NewMask[0] = Mask[0] < 4 ? 0 : 2;
8680 NewMask[1] = Mask[0] < 4 ? 2 : 0;
8681 NewMask[2] = Mask[2] < 4 ? 1 : 3;
8682 NewMask[3] = Mask[2] < 4 ? 3 : 1;
8685 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
8686 getV4X86ShuffleImm8ForMask(NewMask, DL, DAG));
8689 /// \brief Lower 4-lane 32-bit floating point shuffles.
8691 /// Uses instructions exclusively from the floating point unit to minimize
8692 /// domain crossing penalties, as these are sufficient to implement all v4f32
8694 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8695 const X86Subtarget *Subtarget,
8696 SelectionDAG &DAG) {
8698 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
8699 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8700 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8701 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8702 ArrayRef<int> Mask = SVOp->getMask();
8703 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8706 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8708 if (NumV2Elements == 0) {
8709 // Check for being able to broadcast a single element.
8710 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4f32, V1,
8711 Mask, Subtarget, DAG))
8714 // Use even/odd duplicate instructions for masks that match their pattern.
8715 if (Subtarget->hasSSE3()) {
8716 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
8717 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v4f32, V1);
8718 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3}))
8719 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v4f32, V1);
8722 if (Subtarget->hasAVX()) {
8723 // If we have AVX, we can use VPERMILPS which will allow folding a load
8724 // into the shuffle.
8725 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
8726 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8729 // Otherwise, use a straight shuffle of a single input vector. We pass the
8730 // input vector to both operands to simulate this with a SHUFPS.
8731 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
8732 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8735 // There are special ways we can lower some single-element blends. However, we
8736 // have custom ways we can lower more complex single-element blends below that
8737 // we defer to if both this and BLENDPS fail to match, so restrict this to
8738 // when the V2 input is targeting element 0 of the mask -- that is the fast
8740 if (NumV2Elements == 1 && Mask[0] >= 4)
8741 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4f32, V1, V2,
8742 Mask, Subtarget, DAG))
8745 if (Subtarget->hasSSE41()) {
8746 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
8750 // Use INSERTPS if we can complete the shuffle efficiently.
8751 if (SDValue V = lowerVectorShuffleAsInsertPS(Op, V1, V2, Mask, DAG))
8754 if (!isSingleSHUFPSMask(Mask))
8755 if (SDValue BlendPerm = lowerVectorShuffleAsBlendAndPermute(
8756 DL, MVT::v4f32, V1, V2, Mask, DAG))
8760 // Use dedicated unpack instructions for masks that match their pattern.
8762 lowerVectorShuffleWithUNPCK(DL, MVT::v4f32, Mask, V1, V2, DAG))
8765 // Otherwise fall back to a SHUFPS lowering strategy.
8766 return lowerVectorShuffleWithSHUFPS(DL, MVT::v4f32, Mask, V1, V2, DAG);
8769 /// \brief Lower 4-lane i32 vector shuffles.
8771 /// We try to handle these with integer-domain shuffles where we can, but for
8772 /// blends we use the floating point domain blend instructions.
8773 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8774 const X86Subtarget *Subtarget,
8775 SelectionDAG &DAG) {
8777 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
8778 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8779 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8780 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8781 ArrayRef<int> Mask = SVOp->getMask();
8782 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8784 // Whenever we can lower this as a zext, that instruction is strictly faster
8785 // than any alternative. It also allows us to fold memory operands into the
8786 // shuffle in many cases.
8787 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
8788 Mask, Subtarget, DAG))
8792 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8794 if (NumV2Elements == 0) {
8795 // Check for being able to broadcast a single element.
8796 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i32, V1,
8797 Mask, Subtarget, DAG))
8800 // Straight shuffle of a single input vector. For everything from SSE2
8801 // onward this has a single fast instruction with no scary immediates.
8802 // We coerce the shuffle pattern to be compatible with UNPCK instructions
8803 // but we aren't actually going to use the UNPCK instruction because doing
8804 // so prevents folding a load into this instruction or making a copy.
8805 const int UnpackLoMask[] = {0, 0, 1, 1};
8806 const int UnpackHiMask[] = {2, 2, 3, 3};
8807 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 1, 1}))
8808 Mask = UnpackLoMask;
8809 else if (isShuffleEquivalent(V1, V2, Mask, {2, 2, 3, 3}))
8810 Mask = UnpackHiMask;
8812 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8813 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8816 // Try to use shift instructions.
8818 lowerVectorShuffleAsShift(DL, MVT::v4i32, V1, V2, Mask, DAG))
8821 // There are special ways we can lower some single-element blends.
8822 if (NumV2Elements == 1)
8823 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4i32, V1, V2,
8824 Mask, Subtarget, DAG))
8827 // We have different paths for blend lowering, but they all must use the
8828 // *exact* same predicate.
8829 bool IsBlendSupported = Subtarget->hasSSE41();
8830 if (IsBlendSupported)
8831 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
8835 if (SDValue Masked =
8836 lowerVectorShuffleAsBitMask(DL, MVT::v4i32, V1, V2, Mask, DAG))
8839 // Use dedicated unpack instructions for masks that match their pattern.
8841 lowerVectorShuffleWithUNPCK(DL, MVT::v4i32, Mask, V1, V2, DAG))
8844 // Try to use byte rotation instructions.
8845 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8846 if (Subtarget->hasSSSE3())
8847 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8848 DL, MVT::v4i32, V1, V2, Mask, Subtarget, DAG))
8851 // If we have direct support for blends, we should lower by decomposing into
8852 // a permute. That will be faster than the domain cross.
8853 if (IsBlendSupported)
8854 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i32, V1, V2,
8857 // Try to lower by permuting the inputs into an unpack instruction.
8858 if (SDValue Unpack = lowerVectorShuffleAsPermuteAndUnpack(DL, MVT::v4i32, V1,
8862 // We implement this with SHUFPS because it can blend from two vectors.
8863 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
8864 // up the inputs, bypassing domain shift penalties that we would encur if we
8865 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
8867 return DAG.getBitcast(
8869 DAG.getVectorShuffle(MVT::v4f32, DL, DAG.getBitcast(MVT::v4f32, V1),
8870 DAG.getBitcast(MVT::v4f32, V2), Mask));
8873 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
8874 /// shuffle lowering, and the most complex part.
8876 /// The lowering strategy is to try to form pairs of input lanes which are
8877 /// targeted at the same half of the final vector, and then use a dword shuffle
8878 /// to place them onto the right half, and finally unpack the paired lanes into
8879 /// their final position.
8881 /// The exact breakdown of how to form these dword pairs and align them on the
8882 /// correct sides is really tricky. See the comments within the function for
8883 /// more of the details.
8885 /// This code also handles repeated 128-bit lanes of v8i16 shuffles, but each
8886 /// lane must shuffle the *exact* same way. In fact, you must pass a v8 Mask to
8887 /// this routine for it to work correctly. To shuffle a 256-bit or 512-bit i16
8888 /// vector, form the analogous 128-bit 8-element Mask.
8889 static SDValue lowerV8I16GeneralSingleInputVectorShuffle(
8890 SDLoc DL, MVT VT, SDValue V, MutableArrayRef<int> Mask,
8891 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
8892 assert(VT.getVectorElementType() == MVT::i16 && "Bad input type!");
8893 MVT PSHUFDVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
8895 assert(Mask.size() == 8 && "Shuffle mask length doen't match!");
8896 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
8897 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
8899 SmallVector<int, 4> LoInputs;
8900 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
8901 [](int M) { return M >= 0; });
8902 std::sort(LoInputs.begin(), LoInputs.end());
8903 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
8904 SmallVector<int, 4> HiInputs;
8905 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
8906 [](int M) { return M >= 0; });
8907 std::sort(HiInputs.begin(), HiInputs.end());
8908 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
8910 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
8911 int NumHToL = LoInputs.size() - NumLToL;
8913 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
8914 int NumHToH = HiInputs.size() - NumLToH;
8915 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
8916 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
8917 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
8918 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
8920 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
8921 // such inputs we can swap two of the dwords across the half mark and end up
8922 // with <=2 inputs to each half in each half. Once there, we can fall through
8923 // to the generic code below. For example:
8925 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8926 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
8928 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
8929 // and an existing 2-into-2 on the other half. In this case we may have to
8930 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
8931 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
8932 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
8933 // because any other situation (including a 3-into-1 or 1-into-3 in the other
8934 // half than the one we target for fixing) will be fixed when we re-enter this
8935 // path. We will also combine away any sequence of PSHUFD instructions that
8936 // result into a single instruction. Here is an example of the tricky case:
8938 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8939 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
8941 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
8943 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
8944 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
8946 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
8947 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
8949 // The result is fine to be handled by the generic logic.
8950 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
8951 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
8952 int AOffset, int BOffset) {
8953 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
8954 "Must call this with A having 3 or 1 inputs from the A half.");
8955 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
8956 "Must call this with B having 1 or 3 inputs from the B half.");
8957 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
8958 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
8960 bool ThreeAInputs = AToAInputs.size() == 3;
8962 // Compute the index of dword with only one word among the three inputs in
8963 // a half by taking the sum of the half with three inputs and subtracting
8964 // the sum of the actual three inputs. The difference is the remaining
8967 int &TripleDWord = ThreeAInputs ? ADWord : BDWord;
8968 int &OneInputDWord = ThreeAInputs ? BDWord : ADWord;
8969 int TripleInputOffset = ThreeAInputs ? AOffset : BOffset;
8970 ArrayRef<int> TripleInputs = ThreeAInputs ? AToAInputs : BToAInputs;
8971 int OneInput = ThreeAInputs ? BToAInputs[0] : AToAInputs[0];
8972 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
8973 int TripleNonInputIdx =
8974 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
8975 TripleDWord = TripleNonInputIdx / 2;
8977 // We use xor with one to compute the adjacent DWord to whichever one the
8979 OneInputDWord = (OneInput / 2) ^ 1;
8981 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
8982 // and BToA inputs. If there is also such a problem with the BToB and AToB
8983 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
8984 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
8985 // is essential that we don't *create* a 3<-1 as then we might oscillate.
8986 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
8987 // Compute how many inputs will be flipped by swapping these DWords. We
8989 // to balance this to ensure we don't form a 3-1 shuffle in the other
8991 int NumFlippedAToBInputs =
8992 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
8993 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
8994 int NumFlippedBToBInputs =
8995 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
8996 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
8997 if ((NumFlippedAToBInputs == 1 &&
8998 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
8999 (NumFlippedBToBInputs == 1 &&
9000 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
9001 // We choose whether to fix the A half or B half based on whether that
9002 // half has zero flipped inputs. At zero, we may not be able to fix it
9003 // with that half. We also bias towards fixing the B half because that
9004 // will more commonly be the high half, and we have to bias one way.
9005 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
9006 ArrayRef<int> Inputs) {
9007 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
9008 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
9009 PinnedIdx ^ 1) != Inputs.end();
9010 // Determine whether the free index is in the flipped dword or the
9011 // unflipped dword based on where the pinned index is. We use this bit
9012 // in an xor to conditionally select the adjacent dword.
9013 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
9014 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
9015 FixFreeIdx) != Inputs.end();
9016 if (IsFixIdxInput == IsFixFreeIdxInput)
9018 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
9019 FixFreeIdx) != Inputs.end();
9020 assert(IsFixIdxInput != IsFixFreeIdxInput &&
9021 "We need to be changing the number of flipped inputs!");
9022 int PSHUFHalfMask[] = {0, 1, 2, 3};
9023 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
9024 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
9026 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DL, DAG));
9029 if (M != -1 && M == FixIdx)
9031 else if (M != -1 && M == FixFreeIdx)
9034 if (NumFlippedBToBInputs != 0) {
9036 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
9037 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
9039 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
9040 int APinnedIdx = ThreeAInputs ? TripleNonInputIdx : OneInput;
9041 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
9046 int PSHUFDMask[] = {0, 1, 2, 3};
9047 PSHUFDMask[ADWord] = BDWord;
9048 PSHUFDMask[BDWord] = ADWord;
9051 DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT, DAG.getBitcast(PSHUFDVT, V),
9052 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
9054 // Adjust the mask to match the new locations of A and B.
9056 if (M != -1 && M/2 == ADWord)
9057 M = 2 * BDWord + M % 2;
9058 else if (M != -1 && M/2 == BDWord)
9059 M = 2 * ADWord + M % 2;
9061 // Recurse back into this routine to re-compute state now that this isn't
9062 // a 3 and 1 problem.
9063 return lowerV8I16GeneralSingleInputVectorShuffle(DL, VT, V, Mask, Subtarget,
9066 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
9067 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
9068 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
9069 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
9071 // At this point there are at most two inputs to the low and high halves from
9072 // each half. That means the inputs can always be grouped into dwords and
9073 // those dwords can then be moved to the correct half with a dword shuffle.
9074 // We use at most one low and one high word shuffle to collect these paired
9075 // inputs into dwords, and finally a dword shuffle to place them.
9076 int PSHUFLMask[4] = {-1, -1, -1, -1};
9077 int PSHUFHMask[4] = {-1, -1, -1, -1};
9078 int PSHUFDMask[4] = {-1, -1, -1, -1};
9080 // First fix the masks for all the inputs that are staying in their
9081 // original halves. This will then dictate the targets of the cross-half
9083 auto fixInPlaceInputs =
9084 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
9085 MutableArrayRef<int> SourceHalfMask,
9086 MutableArrayRef<int> HalfMask, int HalfOffset) {
9087 if (InPlaceInputs.empty())
9089 if (InPlaceInputs.size() == 1) {
9090 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
9091 InPlaceInputs[0] - HalfOffset;
9092 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
9095 if (IncomingInputs.empty()) {
9096 // Just fix all of the in place inputs.
9097 for (int Input : InPlaceInputs) {
9098 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
9099 PSHUFDMask[Input / 2] = Input / 2;
9104 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
9105 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
9106 InPlaceInputs[0] - HalfOffset;
9107 // Put the second input next to the first so that they are packed into
9108 // a dword. We find the adjacent index by toggling the low bit.
9109 int AdjIndex = InPlaceInputs[0] ^ 1;
9110 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
9111 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
9112 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
9114 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
9115 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
9117 // Now gather the cross-half inputs and place them into a free dword of
9118 // their target half.
9119 // FIXME: This operation could almost certainly be simplified dramatically to
9120 // look more like the 3-1 fixing operation.
9121 auto moveInputsToRightHalf = [&PSHUFDMask](
9122 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
9123 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
9124 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
9126 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
9127 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
9129 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
9131 int LowWord = Word & ~1;
9132 int HighWord = Word | 1;
9133 return isWordClobbered(SourceHalfMask, LowWord) ||
9134 isWordClobbered(SourceHalfMask, HighWord);
9137 if (IncomingInputs.empty())
9140 if (ExistingInputs.empty()) {
9141 // Map any dwords with inputs from them into the right half.
9142 for (int Input : IncomingInputs) {
9143 // If the source half mask maps over the inputs, turn those into
9144 // swaps and use the swapped lane.
9145 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
9146 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
9147 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
9148 Input - SourceOffset;
9149 // We have to swap the uses in our half mask in one sweep.
9150 for (int &M : HalfMask)
9151 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
9153 else if (M == Input)
9154 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
9156 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
9157 Input - SourceOffset &&
9158 "Previous placement doesn't match!");
9160 // Note that this correctly re-maps both when we do a swap and when
9161 // we observe the other side of the swap above. We rely on that to
9162 // avoid swapping the members of the input list directly.
9163 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
9166 // Map the input's dword into the correct half.
9167 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
9168 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
9170 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
9172 "Previous placement doesn't match!");
9175 // And just directly shift any other-half mask elements to be same-half
9176 // as we will have mirrored the dword containing the element into the
9177 // same position within that half.
9178 for (int &M : HalfMask)
9179 if (M >= SourceOffset && M < SourceOffset + 4) {
9180 M = M - SourceOffset + DestOffset;
9181 assert(M >= 0 && "This should never wrap below zero!");
9186 // Ensure we have the input in a viable dword of its current half. This
9187 // is particularly tricky because the original position may be clobbered
9188 // by inputs being moved and *staying* in that half.
9189 if (IncomingInputs.size() == 1) {
9190 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
9191 int InputFixed = std::find(std::begin(SourceHalfMask),
9192 std::end(SourceHalfMask), -1) -
9193 std::begin(SourceHalfMask) + SourceOffset;
9194 SourceHalfMask[InputFixed - SourceOffset] =
9195 IncomingInputs[0] - SourceOffset;
9196 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
9198 IncomingInputs[0] = InputFixed;
9200 } else if (IncomingInputs.size() == 2) {
9201 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
9202 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
9203 // We have two non-adjacent or clobbered inputs we need to extract from
9204 // the source half. To do this, we need to map them into some adjacent
9205 // dword slot in the source mask.
9206 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
9207 IncomingInputs[1] - SourceOffset};
9209 // If there is a free slot in the source half mask adjacent to one of
9210 // the inputs, place the other input in it. We use (Index XOR 1) to
9211 // compute an adjacent index.
9212 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
9213 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
9214 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
9215 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
9216 InputsFixed[1] = InputsFixed[0] ^ 1;
9217 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
9218 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
9219 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
9220 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
9221 InputsFixed[0] = InputsFixed[1] ^ 1;
9222 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
9223 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
9224 // The two inputs are in the same DWord but it is clobbered and the
9225 // adjacent DWord isn't used at all. Move both inputs to the free
9227 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
9228 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
9229 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
9230 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
9232 // The only way we hit this point is if there is no clobbering
9233 // (because there are no off-half inputs to this half) and there is no
9234 // free slot adjacent to one of the inputs. In this case, we have to
9235 // swap an input with a non-input.
9236 for (int i = 0; i < 4; ++i)
9237 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
9238 "We can't handle any clobbers here!");
9239 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
9240 "Cannot have adjacent inputs here!");
9242 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
9243 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
9245 // We also have to update the final source mask in this case because
9246 // it may need to undo the above swap.
9247 for (int &M : FinalSourceHalfMask)
9248 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
9249 M = InputsFixed[1] + SourceOffset;
9250 else if (M == InputsFixed[1] + SourceOffset)
9251 M = (InputsFixed[0] ^ 1) + SourceOffset;
9253 InputsFixed[1] = InputsFixed[0] ^ 1;
9256 // Point everything at the fixed inputs.
9257 for (int &M : HalfMask)
9258 if (M == IncomingInputs[0])
9259 M = InputsFixed[0] + SourceOffset;
9260 else if (M == IncomingInputs[1])
9261 M = InputsFixed[1] + SourceOffset;
9263 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
9264 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
9267 llvm_unreachable("Unhandled input size!");
9270 // Now hoist the DWord down to the right half.
9271 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
9272 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
9273 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
9274 for (int &M : HalfMask)
9275 for (int Input : IncomingInputs)
9277 M = FreeDWord * 2 + Input % 2;
9279 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
9280 /*SourceOffset*/ 4, /*DestOffset*/ 0);
9281 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
9282 /*SourceOffset*/ 0, /*DestOffset*/ 4);
9284 // Now enact all the shuffles we've computed to move the inputs into their
9286 if (!isNoopShuffleMask(PSHUFLMask))
9287 V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
9288 getV4X86ShuffleImm8ForMask(PSHUFLMask, DL, DAG));
9289 if (!isNoopShuffleMask(PSHUFHMask))
9290 V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
9291 getV4X86ShuffleImm8ForMask(PSHUFHMask, DL, DAG));
9292 if (!isNoopShuffleMask(PSHUFDMask))
9295 DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT, DAG.getBitcast(PSHUFDVT, V),
9296 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
9298 // At this point, each half should contain all its inputs, and we can then
9299 // just shuffle them into their final position.
9300 assert(std::count_if(LoMask.begin(), LoMask.end(),
9301 [](int M) { return M >= 4; }) == 0 &&
9302 "Failed to lift all the high half inputs to the low mask!");
9303 assert(std::count_if(HiMask.begin(), HiMask.end(),
9304 [](int M) { return M >= 0 && M < 4; }) == 0 &&
9305 "Failed to lift all the low half inputs to the high mask!");
9307 // Do a half shuffle for the low mask.
9308 if (!isNoopShuffleMask(LoMask))
9309 V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
9310 getV4X86ShuffleImm8ForMask(LoMask, DL, DAG));
9312 // Do a half shuffle with the high mask after shifting its values down.
9313 for (int &M : HiMask)
9316 if (!isNoopShuffleMask(HiMask))
9317 V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
9318 getV4X86ShuffleImm8ForMask(HiMask, DL, DAG));
9323 /// \brief Helper to form a PSHUFB-based shuffle+blend.
9324 static SDValue lowerVectorShuffleAsPSHUFB(SDLoc DL, MVT VT, SDValue V1,
9325 SDValue V2, ArrayRef<int> Mask,
9326 SelectionDAG &DAG, bool &V1InUse,
9328 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
9334 int Size = Mask.size();
9335 int Scale = 16 / Size;
9336 for (int i = 0; i < 16; ++i) {
9337 if (Mask[i / Scale] == -1) {
9338 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
9340 const int ZeroMask = 0x80;
9341 int V1Idx = Mask[i / Scale] < Size ? Mask[i / Scale] * Scale + i % Scale
9343 int V2Idx = Mask[i / Scale] < Size
9345 : (Mask[i / Scale] - Size) * Scale + i % Scale;
9346 if (Zeroable[i / Scale])
9347 V1Idx = V2Idx = ZeroMask;
9348 V1Mask[i] = DAG.getConstant(V1Idx, DL, MVT::i8);
9349 V2Mask[i] = DAG.getConstant(V2Idx, DL, MVT::i8);
9350 V1InUse |= (ZeroMask != V1Idx);
9351 V2InUse |= (ZeroMask != V2Idx);
9356 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
9357 DAG.getBitcast(MVT::v16i8, V1),
9358 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
9360 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
9361 DAG.getBitcast(MVT::v16i8, V2),
9362 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
9364 // If we need shuffled inputs from both, blend the two.
9366 if (V1InUse && V2InUse)
9367 V = DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
9369 V = V1InUse ? V1 : V2;
9371 // Cast the result back to the correct type.
9372 return DAG.getBitcast(VT, V);
9375 /// \brief Generic lowering of 8-lane i16 shuffles.
9377 /// This handles both single-input shuffles and combined shuffle/blends with
9378 /// two inputs. The single input shuffles are immediately delegated to
9379 /// a dedicated lowering routine.
9381 /// The blends are lowered in one of three fundamental ways. If there are few
9382 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
9383 /// of the input is significantly cheaper when lowered as an interleaving of
9384 /// the two inputs, try to interleave them. Otherwise, blend the low and high
9385 /// halves of the inputs separately (making them have relatively few inputs)
9386 /// and then concatenate them.
9387 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9388 const X86Subtarget *Subtarget,
9389 SelectionDAG &DAG) {
9391 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
9392 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9393 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9394 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9395 ArrayRef<int> OrigMask = SVOp->getMask();
9396 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9397 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
9398 MutableArrayRef<int> Mask(MaskStorage);
9400 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9402 // Whenever we can lower this as a zext, that instruction is strictly faster
9403 // than any alternative.
9404 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9405 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
9408 auto isV1 = [](int M) { return M >= 0 && M < 8; };
9410 auto isV2 = [](int M) { return M >= 8; };
9412 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
9414 if (NumV2Inputs == 0) {
9415 // Check for being able to broadcast a single element.
9416 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8i16, V1,
9417 Mask, Subtarget, DAG))
9420 // Try to use shift instructions.
9422 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V1, Mask, DAG))
9425 // Use dedicated unpack instructions for masks that match their pattern.
9427 lowerVectorShuffleWithUNPCK(DL, MVT::v8i16, Mask, V1, V2, DAG))
9430 // Try to use byte rotation instructions.
9431 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(DL, MVT::v8i16, V1, V1,
9432 Mask, Subtarget, DAG))
9435 return lowerV8I16GeneralSingleInputVectorShuffle(DL, MVT::v8i16, V1, Mask,
9439 assert(std::any_of(Mask.begin(), Mask.end(), isV1) &&
9440 "All single-input shuffles should be canonicalized to be V1-input "
9443 // Try to use shift instructions.
9445 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V2, Mask, DAG))
9448 // See if we can use SSE4A Extraction / Insertion.
9449 if (Subtarget->hasSSE4A())
9450 if (SDValue V = lowerVectorShuffleWithSSE4A(DL, MVT::v8i16, V1, V2, Mask, DAG))
9453 // There are special ways we can lower some single-element blends.
9454 if (NumV2Inputs == 1)
9455 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v8i16, V1, V2,
9456 Mask, Subtarget, DAG))
9459 // We have different paths for blend lowering, but they all must use the
9460 // *exact* same predicate.
9461 bool IsBlendSupported = Subtarget->hasSSE41();
9462 if (IsBlendSupported)
9463 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
9467 if (SDValue Masked =
9468 lowerVectorShuffleAsBitMask(DL, MVT::v8i16, V1, V2, Mask, DAG))
9471 // Use dedicated unpack instructions for masks that match their pattern.
9473 lowerVectorShuffleWithUNPCK(DL, MVT::v8i16, Mask, V1, V2, DAG))
9476 // Try to use byte rotation instructions.
9477 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9478 DL, MVT::v8i16, V1, V2, Mask, Subtarget, DAG))
9481 if (SDValue BitBlend =
9482 lowerVectorShuffleAsBitBlend(DL, MVT::v8i16, V1, V2, Mask, DAG))
9485 if (SDValue Unpack = lowerVectorShuffleAsPermuteAndUnpack(DL, MVT::v8i16, V1,
9489 // If we can't directly blend but can use PSHUFB, that will be better as it
9490 // can both shuffle and set up the inefficient blend.
9491 if (!IsBlendSupported && Subtarget->hasSSSE3()) {
9492 bool V1InUse, V2InUse;
9493 return lowerVectorShuffleAsPSHUFB(DL, MVT::v8i16, V1, V2, Mask, DAG,
9497 // We can always bit-blend if we have to so the fallback strategy is to
9498 // decompose into single-input permutes and blends.
9499 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i16, V1, V2,
9503 /// \brief Check whether a compaction lowering can be done by dropping even
9504 /// elements and compute how many times even elements must be dropped.
9506 /// This handles shuffles which take every Nth element where N is a power of
9507 /// two. Example shuffle masks:
9509 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
9510 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
9511 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
9512 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
9513 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
9514 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
9516 /// Any of these lanes can of course be undef.
9518 /// This routine only supports N <= 3.
9519 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
9522 /// \returns N above, or the number of times even elements must be dropped if
9523 /// there is such a number. Otherwise returns zero.
9524 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
9525 // Figure out whether we're looping over two inputs or just one.
9526 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9528 // The modulus for the shuffle vector entries is based on whether this is
9529 // a single input or not.
9530 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
9531 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
9532 "We should only be called with masks with a power-of-2 size!");
9534 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
9536 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
9537 // and 2^3 simultaneously. This is because we may have ambiguity with
9538 // partially undef inputs.
9539 bool ViableForN[3] = {true, true, true};
9541 for (int i = 0, e = Mask.size(); i < e; ++i) {
9542 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
9547 bool IsAnyViable = false;
9548 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9549 if (ViableForN[j]) {
9552 // The shuffle mask must be equal to (i * 2^N) % M.
9553 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
9556 ViableForN[j] = false;
9558 // Early exit if we exhaust the possible powers of two.
9563 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9567 // Return 0 as there is no viable power of two.
9571 /// \brief Generic lowering of v16i8 shuffles.
9573 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
9574 /// detect any complexity reducing interleaving. If that doesn't help, it uses
9575 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
9576 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
9578 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9579 const X86Subtarget *Subtarget,
9580 SelectionDAG &DAG) {
9582 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
9583 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9584 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9585 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9586 ArrayRef<int> Mask = SVOp->getMask();
9587 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9589 // Try to use shift instructions.
9591 lowerVectorShuffleAsShift(DL, MVT::v16i8, V1, V2, Mask, DAG))
9594 // Try to use byte rotation instructions.
9595 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9596 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
9599 // Try to use a zext lowering.
9600 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9601 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
9604 // See if we can use SSE4A Extraction / Insertion.
9605 if (Subtarget->hasSSE4A())
9606 if (SDValue V = lowerVectorShuffleWithSSE4A(DL, MVT::v16i8, V1, V2, Mask, DAG))
9610 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
9612 // For single-input shuffles, there are some nicer lowering tricks we can use.
9613 if (NumV2Elements == 0) {
9614 // Check for being able to broadcast a single element.
9615 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v16i8, V1,
9616 Mask, Subtarget, DAG))
9619 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
9620 // Notably, this handles splat and partial-splat shuffles more efficiently.
9621 // However, it only makes sense if the pre-duplication shuffle simplifies
9622 // things significantly. Currently, this means we need to be able to
9623 // express the pre-duplication shuffle as an i16 shuffle.
9625 // FIXME: We should check for other patterns which can be widened into an
9626 // i16 shuffle as well.
9627 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
9628 for (int i = 0; i < 16; i += 2)
9629 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
9634 auto tryToWidenViaDuplication = [&]() -> SDValue {
9635 if (!canWidenViaDuplication(Mask))
9637 SmallVector<int, 4> LoInputs;
9638 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
9639 [](int M) { return M >= 0 && M < 8; });
9640 std::sort(LoInputs.begin(), LoInputs.end());
9641 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
9643 SmallVector<int, 4> HiInputs;
9644 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
9645 [](int M) { return M >= 8; });
9646 std::sort(HiInputs.begin(), HiInputs.end());
9647 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
9650 bool TargetLo = LoInputs.size() >= HiInputs.size();
9651 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
9652 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
9654 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9655 SmallDenseMap<int, int, 8> LaneMap;
9656 for (int I : InPlaceInputs) {
9657 PreDupI16Shuffle[I/2] = I/2;
9660 int j = TargetLo ? 0 : 4, je = j + 4;
9661 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
9662 // Check if j is already a shuffle of this input. This happens when
9663 // there are two adjacent bytes after we move the low one.
9664 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
9665 // If we haven't yet mapped the input, search for a slot into which
9667 while (j < je && PreDupI16Shuffle[j] != -1)
9671 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
9674 // Map this input with the i16 shuffle.
9675 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
9678 // Update the lane map based on the mapping we ended up with.
9679 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
9681 V1 = DAG.getBitcast(
9683 DAG.getVectorShuffle(MVT::v8i16, DL, DAG.getBitcast(MVT::v8i16, V1),
9684 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
9686 // Unpack the bytes to form the i16s that will be shuffled into place.
9687 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9688 MVT::v16i8, V1, V1);
9690 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9691 for (int i = 0; i < 16; ++i)
9692 if (Mask[i] != -1) {
9693 int MappedMask = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
9694 assert(MappedMask < 8 && "Invalid v8 shuffle mask!");
9695 if (PostDupI16Shuffle[i / 2] == -1)
9696 PostDupI16Shuffle[i / 2] = MappedMask;
9698 assert(PostDupI16Shuffle[i / 2] == MappedMask &&
9699 "Conflicting entrties in the original shuffle!");
9701 return DAG.getBitcast(
9703 DAG.getVectorShuffle(MVT::v8i16, DL, DAG.getBitcast(MVT::v8i16, V1),
9704 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
9706 if (SDValue V = tryToWidenViaDuplication())
9710 if (SDValue Masked =
9711 lowerVectorShuffleAsBitMask(DL, MVT::v16i8, V1, V2, Mask, DAG))
9714 // Use dedicated unpack instructions for masks that match their pattern.
9716 lowerVectorShuffleWithUNPCK(DL, MVT::v16i8, Mask, V1, V2, DAG))
9719 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
9720 // with PSHUFB. It is important to do this before we attempt to generate any
9721 // blends but after all of the single-input lowerings. If the single input
9722 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
9723 // want to preserve that and we can DAG combine any longer sequences into
9724 // a PSHUFB in the end. But once we start blending from multiple inputs,
9725 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
9726 // and there are *very* few patterns that would actually be faster than the
9727 // PSHUFB approach because of its ability to zero lanes.
9729 // FIXME: The only exceptions to the above are blends which are exact
9730 // interleavings with direct instructions supporting them. We currently don't
9731 // handle those well here.
9732 if (Subtarget->hasSSSE3()) {
9733 bool V1InUse = false;
9734 bool V2InUse = false;
9736 SDValue PSHUFB = lowerVectorShuffleAsPSHUFB(DL, MVT::v16i8, V1, V2, Mask,
9737 DAG, V1InUse, V2InUse);
9739 // If both V1 and V2 are in use and we can use a direct blend or an unpack,
9740 // do so. This avoids using them to handle blends-with-zero which is
9741 // important as a single pshufb is significantly faster for that.
9742 if (V1InUse && V2InUse) {
9743 if (Subtarget->hasSSE41())
9744 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i8, V1, V2,
9745 Mask, Subtarget, DAG))
9748 // We can use an unpack to do the blending rather than an or in some
9749 // cases. Even though the or may be (very minorly) more efficient, we
9750 // preference this lowering because there are common cases where part of
9751 // the complexity of the shuffles goes away when we do the final blend as
9753 // FIXME: It might be worth trying to detect if the unpack-feeding
9754 // shuffles will both be pshufb, in which case we shouldn't bother with
9756 if (SDValue Unpack = lowerVectorShuffleAsPermuteAndUnpack(
9757 DL, MVT::v16i8, V1, V2, Mask, DAG))
9764 // There are special ways we can lower some single-element blends.
9765 if (NumV2Elements == 1)
9766 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v16i8, V1, V2,
9767 Mask, Subtarget, DAG))
9770 if (SDValue BitBlend =
9771 lowerVectorShuffleAsBitBlend(DL, MVT::v16i8, V1, V2, Mask, DAG))
9774 // Check whether a compaction lowering can be done. This handles shuffles
9775 // which take every Nth element for some even N. See the helper function for
9778 // We special case these as they can be particularly efficiently handled with
9779 // the PACKUSB instruction on x86 and they show up in common patterns of
9780 // rearranging bytes to truncate wide elements.
9781 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
9782 // NumEvenDrops is the power of two stride of the elements. Another way of
9783 // thinking about it is that we need to drop the even elements this many
9784 // times to get the original input.
9785 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9787 // First we need to zero all the dropped bytes.
9788 assert(NumEvenDrops <= 3 &&
9789 "No support for dropping even elements more than 3 times.");
9790 // We use the mask type to pick which bytes are preserved based on how many
9791 // elements are dropped.
9792 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
9793 SDValue ByteClearMask = DAG.getBitcast(
9794 MVT::v16i8, DAG.getConstant(0xFF, DL, MaskVTs[NumEvenDrops - 1]));
9795 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
9797 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
9799 // Now pack things back together.
9800 V1 = DAG.getBitcast(MVT::v8i16, V1);
9801 V2 = IsSingleInput ? V1 : DAG.getBitcast(MVT::v8i16, V2);
9802 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
9803 for (int i = 1; i < NumEvenDrops; ++i) {
9804 Result = DAG.getBitcast(MVT::v8i16, Result);
9805 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
9811 // Handle multi-input cases by blending single-input shuffles.
9812 if (NumV2Elements > 0)
9813 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v16i8, V1, V2,
9816 // The fallback path for single-input shuffles widens this into two v8i16
9817 // vectors with unpacks, shuffles those, and then pulls them back together
9821 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9822 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9823 for (int i = 0; i < 16; ++i)
9825 (i < 8 ? LoBlendMask[i] : HiBlendMask[i % 8]) = Mask[i];
9827 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
9829 SDValue VLoHalf, VHiHalf;
9830 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
9831 // them out and avoid using UNPCK{L,H} to extract the elements of V as
9833 if (std::none_of(std::begin(LoBlendMask), std::end(LoBlendMask),
9834 [](int M) { return M >= 0 && M % 2 == 1; }) &&
9835 std::none_of(std::begin(HiBlendMask), std::end(HiBlendMask),
9836 [](int M) { return M >= 0 && M % 2 == 1; })) {
9837 // Use a mask to drop the high bytes.
9838 VLoHalf = DAG.getBitcast(MVT::v8i16, V);
9839 VLoHalf = DAG.getNode(ISD::AND, DL, MVT::v8i16, VLoHalf,
9840 DAG.getConstant(0x00FF, DL, MVT::v8i16));
9842 // This will be a single vector shuffle instead of a blend so nuke VHiHalf.
9843 VHiHalf = DAG.getUNDEF(MVT::v8i16);
9845 // Squash the masks to point directly into VLoHalf.
9846 for (int &M : LoBlendMask)
9849 for (int &M : HiBlendMask)
9853 // Otherwise just unpack the low half of V into VLoHalf and the high half into
9854 // VHiHalf so that we can blend them as i16s.
9855 VLoHalf = DAG.getBitcast(
9856 MVT::v8i16, DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
9857 VHiHalf = DAG.getBitcast(
9858 MVT::v8i16, DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
9861 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, LoBlendMask);
9862 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, HiBlendMask);
9864 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
9867 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
9869 /// This routine breaks down the specific type of 128-bit shuffle and
9870 /// dispatches to the lowering routines accordingly.
9871 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9872 MVT VT, const X86Subtarget *Subtarget,
9873 SelectionDAG &DAG) {
9874 switch (VT.SimpleTy) {
9876 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9878 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9880 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9882 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9884 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9886 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9889 llvm_unreachable("Unimplemented!");
9893 /// \brief Helper function to test whether a shuffle mask could be
9894 /// simplified by widening the elements being shuffled.
9896 /// Appends the mask for wider elements in WidenedMask if valid. Otherwise
9897 /// leaves it in an unspecified state.
9899 /// NOTE: This must handle normal vector shuffle masks and *target* vector
9900 /// shuffle masks. The latter have the special property of a '-2' representing
9901 /// a zero-ed lane of a vector.
9902 static bool canWidenShuffleElements(ArrayRef<int> Mask,
9903 SmallVectorImpl<int> &WidenedMask) {
9904 for (int i = 0, Size = Mask.size(); i < Size; i += 2) {
9905 // If both elements are undef, its trivial.
9906 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] == SM_SentinelUndef) {
9907 WidenedMask.push_back(SM_SentinelUndef);
9911 // Check for an undef mask and a mask value properly aligned to fit with
9912 // a pair of values. If we find such a case, use the non-undef mask's value.
9913 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] >= 0 && Mask[i + 1] % 2 == 1) {
9914 WidenedMask.push_back(Mask[i + 1] / 2);
9917 if (Mask[i + 1] == SM_SentinelUndef && Mask[i] >= 0 && Mask[i] % 2 == 0) {
9918 WidenedMask.push_back(Mask[i] / 2);
9922 // When zeroing, we need to spread the zeroing across both lanes to widen.
9923 if (Mask[i] == SM_SentinelZero || Mask[i + 1] == SM_SentinelZero) {
9924 if ((Mask[i] == SM_SentinelZero || Mask[i] == SM_SentinelUndef) &&
9925 (Mask[i + 1] == SM_SentinelZero || Mask[i + 1] == SM_SentinelUndef)) {
9926 WidenedMask.push_back(SM_SentinelZero);
9932 // Finally check if the two mask values are adjacent and aligned with
9934 if (Mask[i] != SM_SentinelUndef && Mask[i] % 2 == 0 && Mask[i] + 1 == Mask[i + 1]) {
9935 WidenedMask.push_back(Mask[i] / 2);
9939 // Otherwise we can't safely widen the elements used in this shuffle.
9942 assert(WidenedMask.size() == Mask.size() / 2 &&
9943 "Incorrect size of mask after widening the elements!");
9948 /// \brief Generic routine to split vector shuffle into half-sized shuffles.
9950 /// This routine just extracts two subvectors, shuffles them independently, and
9951 /// then concatenates them back together. This should work effectively with all
9952 /// AVX vector shuffle types.
9953 static SDValue splitAndLowerVectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9954 SDValue V2, ArrayRef<int> Mask,
9955 SelectionDAG &DAG) {
9956 assert(VT.getSizeInBits() >= 256 &&
9957 "Only for 256-bit or wider vector shuffles!");
9958 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
9959 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
9961 ArrayRef<int> LoMask = Mask.slice(0, Mask.size() / 2);
9962 ArrayRef<int> HiMask = Mask.slice(Mask.size() / 2);
9964 int NumElements = VT.getVectorNumElements();
9965 int SplitNumElements = NumElements / 2;
9966 MVT ScalarVT = VT.getVectorElementType();
9967 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
9969 // Rather than splitting build-vectors, just build two narrower build
9970 // vectors. This helps shuffling with splats and zeros.
9971 auto SplitVector = [&](SDValue V) {
9972 while (V.getOpcode() == ISD::BITCAST)
9973 V = V->getOperand(0);
9975 MVT OrigVT = V.getSimpleValueType();
9976 int OrigNumElements = OrigVT.getVectorNumElements();
9977 int OrigSplitNumElements = OrigNumElements / 2;
9978 MVT OrigScalarVT = OrigVT.getVectorElementType();
9979 MVT OrigSplitVT = MVT::getVectorVT(OrigScalarVT, OrigNumElements / 2);
9983 auto *BV = dyn_cast<BuildVectorSDNode>(V);
9985 LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
9986 DAG.getIntPtrConstant(0, DL));
9987 HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
9988 DAG.getIntPtrConstant(OrigSplitNumElements, DL));
9991 SmallVector<SDValue, 16> LoOps, HiOps;
9992 for (int i = 0; i < OrigSplitNumElements; ++i) {
9993 LoOps.push_back(BV->getOperand(i));
9994 HiOps.push_back(BV->getOperand(i + OrigSplitNumElements));
9996 LoV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, LoOps);
9997 HiV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, HiOps);
9999 return std::make_pair(DAG.getBitcast(SplitVT, LoV),
10000 DAG.getBitcast(SplitVT, HiV));
10003 SDValue LoV1, HiV1, LoV2, HiV2;
10004 std::tie(LoV1, HiV1) = SplitVector(V1);
10005 std::tie(LoV2, HiV2) = SplitVector(V2);
10007 // Now create two 4-way blends of these half-width vectors.
10008 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
10009 bool UseLoV1 = false, UseHiV1 = false, UseLoV2 = false, UseHiV2 = false;
10010 SmallVector<int, 32> V1BlendMask, V2BlendMask, BlendMask;
10011 for (int i = 0; i < SplitNumElements; ++i) {
10012 int M = HalfMask[i];
10013 if (M >= NumElements) {
10014 if (M >= NumElements + SplitNumElements)
10018 V2BlendMask.push_back(M - NumElements);
10019 V1BlendMask.push_back(-1);
10020 BlendMask.push_back(SplitNumElements + i);
10021 } else if (M >= 0) {
10022 if (M >= SplitNumElements)
10026 V2BlendMask.push_back(-1);
10027 V1BlendMask.push_back(M);
10028 BlendMask.push_back(i);
10030 V2BlendMask.push_back(-1);
10031 V1BlendMask.push_back(-1);
10032 BlendMask.push_back(-1);
10036 // Because the lowering happens after all combining takes place, we need to
10037 // manually combine these blend masks as much as possible so that we create
10038 // a minimal number of high-level vector shuffle nodes.
10040 // First try just blending the halves of V1 or V2.
10041 if (!UseLoV1 && !UseHiV1 && !UseLoV2 && !UseHiV2)
10042 return DAG.getUNDEF(SplitVT);
10043 if (!UseLoV2 && !UseHiV2)
10044 return DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
10045 if (!UseLoV1 && !UseHiV1)
10046 return DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
10048 SDValue V1Blend, V2Blend;
10049 if (UseLoV1 && UseHiV1) {
10051 DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
10053 // We only use half of V1 so map the usage down into the final blend mask.
10054 V1Blend = UseLoV1 ? LoV1 : HiV1;
10055 for (int i = 0; i < SplitNumElements; ++i)
10056 if (BlendMask[i] >= 0 && BlendMask[i] < SplitNumElements)
10057 BlendMask[i] = V1BlendMask[i] - (UseLoV1 ? 0 : SplitNumElements);
10059 if (UseLoV2 && UseHiV2) {
10061 DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
10063 // We only use half of V2 so map the usage down into the final blend mask.
10064 V2Blend = UseLoV2 ? LoV2 : HiV2;
10065 for (int i = 0; i < SplitNumElements; ++i)
10066 if (BlendMask[i] >= SplitNumElements)
10067 BlendMask[i] = V2BlendMask[i] + (UseLoV2 ? SplitNumElements : 0);
10069 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
10071 SDValue Lo = HalfBlend(LoMask);
10072 SDValue Hi = HalfBlend(HiMask);
10073 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
10076 /// \brief Either split a vector in halves or decompose the shuffles and the
10079 /// This is provided as a good fallback for many lowerings of non-single-input
10080 /// shuffles with more than one 128-bit lane. In those cases, we want to select
10081 /// between splitting the shuffle into 128-bit components and stitching those
10082 /// back together vs. extracting the single-input shuffles and blending those
10084 static SDValue lowerVectorShuffleAsSplitOrBlend(SDLoc DL, MVT VT, SDValue V1,
10085 SDValue V2, ArrayRef<int> Mask,
10086 SelectionDAG &DAG) {
10087 assert(!isSingleInputShuffleMask(Mask) && "This routine must not be used to "
10088 "lower single-input shuffles as it "
10089 "could then recurse on itself.");
10090 int Size = Mask.size();
10092 // If this can be modeled as a broadcast of two elements followed by a blend,
10093 // prefer that lowering. This is especially important because broadcasts can
10094 // often fold with memory operands.
10095 auto DoBothBroadcast = [&] {
10096 int V1BroadcastIdx = -1, V2BroadcastIdx = -1;
10099 if (V2BroadcastIdx == -1)
10100 V2BroadcastIdx = M - Size;
10101 else if (M - Size != V2BroadcastIdx)
10103 } else if (M >= 0) {
10104 if (V1BroadcastIdx == -1)
10105 V1BroadcastIdx = M;
10106 else if (M != V1BroadcastIdx)
10111 if (DoBothBroadcast())
10112 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask,
10115 // If the inputs all stem from a single 128-bit lane of each input, then we
10116 // split them rather than blending because the split will decompose to
10117 // unusually few instructions.
10118 int LaneCount = VT.getSizeInBits() / 128;
10119 int LaneSize = Size / LaneCount;
10120 SmallBitVector LaneInputs[2];
10121 LaneInputs[0].resize(LaneCount, false);
10122 LaneInputs[1].resize(LaneCount, false);
10123 for (int i = 0; i < Size; ++i)
10125 LaneInputs[Mask[i] / Size][(Mask[i] % Size) / LaneSize] = true;
10126 if (LaneInputs[0].count() <= 1 && LaneInputs[1].count() <= 1)
10127 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10129 // Otherwise, just fall back to decomposed shuffles and a blend. This requires
10130 // that the decomposed single-input shuffles don't end up here.
10131 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
10134 /// \brief Lower a vector shuffle crossing multiple 128-bit lanes as
10135 /// a permutation and blend of those lanes.
10137 /// This essentially blends the out-of-lane inputs to each lane into the lane
10138 /// from a permuted copy of the vector. This lowering strategy results in four
10139 /// instructions in the worst case for a single-input cross lane shuffle which
10140 /// is lower than any other fully general cross-lane shuffle strategy I'm aware
10141 /// of. Special cases for each particular shuffle pattern should be handled
10142 /// prior to trying this lowering.
10143 static SDValue lowerVectorShuffleAsLanePermuteAndBlend(SDLoc DL, MVT VT,
10144 SDValue V1, SDValue V2,
10145 ArrayRef<int> Mask,
10146 SelectionDAG &DAG) {
10147 // FIXME: This should probably be generalized for 512-bit vectors as well.
10148 assert(VT.is256BitVector() && "Only for 256-bit vector shuffles!");
10149 int LaneSize = Mask.size() / 2;
10151 // If there are only inputs from one 128-bit lane, splitting will in fact be
10152 // less expensive. The flags track whether the given lane contains an element
10153 // that crosses to another lane.
10154 bool LaneCrossing[2] = {false, false};
10155 for (int i = 0, Size = Mask.size(); i < Size; ++i)
10156 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
10157 LaneCrossing[(Mask[i] % Size) / LaneSize] = true;
10158 if (!LaneCrossing[0] || !LaneCrossing[1])
10159 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10161 if (isSingleInputShuffleMask(Mask)) {
10162 SmallVector<int, 32> FlippedBlendMask;
10163 for (int i = 0, Size = Mask.size(); i < Size; ++i)
10164 FlippedBlendMask.push_back(
10165 Mask[i] < 0 ? -1 : (((Mask[i] % Size) / LaneSize == i / LaneSize)
10167 : Mask[i] % LaneSize +
10168 (i / LaneSize) * LaneSize + Size));
10170 // Flip the vector, and blend the results which should now be in-lane. The
10171 // VPERM2X128 mask uses the low 2 bits for the low source and bits 4 and
10172 // 5 for the high source. The value 3 selects the high half of source 2 and
10173 // the value 2 selects the low half of source 2. We only use source 2 to
10174 // allow folding it into a memory operand.
10175 unsigned PERMMask = 3 | 2 << 4;
10176 SDValue Flipped = DAG.getNode(X86ISD::VPERM2X128, DL, VT, DAG.getUNDEF(VT),
10177 V1, DAG.getConstant(PERMMask, DL, MVT::i8));
10178 return DAG.getVectorShuffle(VT, DL, V1, Flipped, FlippedBlendMask);
10181 // This now reduces to two single-input shuffles of V1 and V2 which at worst
10182 // will be handled by the above logic and a blend of the results, much like
10183 // other patterns in AVX.
10184 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
10187 /// \brief Handle lowering 2-lane 128-bit shuffles.
10188 static SDValue lowerV2X128VectorShuffle(SDLoc DL, MVT VT, SDValue V1,
10189 SDValue V2, ArrayRef<int> Mask,
10190 const X86Subtarget *Subtarget,
10191 SelectionDAG &DAG) {
10192 // TODO: If minimizing size and one of the inputs is a zero vector and the
10193 // the zero vector has only one use, we could use a VPERM2X128 to save the
10194 // instruction bytes needed to explicitly generate the zero vector.
10196 // Blends are faster and handle all the non-lane-crossing cases.
10197 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, VT, V1, V2, Mask,
10201 bool IsV1Zero = ISD::isBuildVectorAllZeros(V1.getNode());
10202 bool IsV2Zero = ISD::isBuildVectorAllZeros(V2.getNode());
10204 // If either input operand is a zero vector, use VPERM2X128 because its mask
10205 // allows us to replace the zero input with an implicit zero.
10206 if (!IsV1Zero && !IsV2Zero) {
10207 // Check for patterns which can be matched with a single insert of a 128-bit
10209 bool OnlyUsesV1 = isShuffleEquivalent(V1, V2, Mask, {0, 1, 0, 1});
10210 if (OnlyUsesV1 || isShuffleEquivalent(V1, V2, Mask, {0, 1, 4, 5})) {
10211 MVT SubVT = MVT::getVectorVT(VT.getVectorElementType(),
10212 VT.getVectorNumElements() / 2);
10213 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
10214 DAG.getIntPtrConstant(0, DL));
10215 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT,
10216 OnlyUsesV1 ? V1 : V2,
10217 DAG.getIntPtrConstant(0, DL));
10218 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
10222 // Otherwise form a 128-bit permutation. After accounting for undefs,
10223 // convert the 64-bit shuffle mask selection values into 128-bit
10224 // selection bits by dividing the indexes by 2 and shifting into positions
10225 // defined by a vperm2*128 instruction's immediate control byte.
10227 // The immediate permute control byte looks like this:
10228 // [1:0] - select 128 bits from sources for low half of destination
10230 // [3] - zero low half of destination
10231 // [5:4] - select 128 bits from sources for high half of destination
10233 // [7] - zero high half of destination
10235 int MaskLO = Mask[0];
10236 if (MaskLO == SM_SentinelUndef)
10237 MaskLO = Mask[1] == SM_SentinelUndef ? 0 : Mask[1];
10239 int MaskHI = Mask[2];
10240 if (MaskHI == SM_SentinelUndef)
10241 MaskHI = Mask[3] == SM_SentinelUndef ? 0 : Mask[3];
10243 unsigned PermMask = MaskLO / 2 | (MaskHI / 2) << 4;
10245 // If either input is a zero vector, replace it with an undef input.
10246 // Shuffle mask values < 4 are selecting elements of V1.
10247 // Shuffle mask values >= 4 are selecting elements of V2.
10248 // Adjust each half of the permute mask by clearing the half that was
10249 // selecting the zero vector and setting the zero mask bit.
10251 V1 = DAG.getUNDEF(VT);
10253 PermMask = (PermMask & 0xf0) | 0x08;
10255 PermMask = (PermMask & 0x0f) | 0x80;
10258 V2 = DAG.getUNDEF(VT);
10260 PermMask = (PermMask & 0xf0) | 0x08;
10262 PermMask = (PermMask & 0x0f) | 0x80;
10265 return DAG.getNode(X86ISD::VPERM2X128, DL, VT, V1, V2,
10266 DAG.getConstant(PermMask, DL, MVT::i8));
10269 /// \brief Lower a vector shuffle by first fixing the 128-bit lanes and then
10270 /// shuffling each lane.
10272 /// This will only succeed when the result of fixing the 128-bit lanes results
10273 /// in a single-input non-lane-crossing shuffle with a repeating shuffle mask in
10274 /// each 128-bit lanes. This handles many cases where we can quickly blend away
10275 /// the lane crosses early and then use simpler shuffles within each lane.
10277 /// FIXME: It might be worthwhile at some point to support this without
10278 /// requiring the 128-bit lane-relative shuffles to be repeating, but currently
10279 /// in x86 only floating point has interesting non-repeating shuffles, and even
10280 /// those are still *marginally* more expensive.
10281 static SDValue lowerVectorShuffleByMerging128BitLanes(
10282 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
10283 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
10284 assert(!isSingleInputShuffleMask(Mask) &&
10285 "This is only useful with multiple inputs.");
10287 int Size = Mask.size();
10288 int LaneSize = 128 / VT.getScalarSizeInBits();
10289 int NumLanes = Size / LaneSize;
10290 assert(NumLanes > 1 && "Only handles 256-bit and wider shuffles.");
10292 // See if we can build a hypothetical 128-bit lane-fixing shuffle mask. Also
10293 // check whether the in-128-bit lane shuffles share a repeating pattern.
10294 SmallVector<int, 4> Lanes;
10295 Lanes.resize(NumLanes, -1);
10296 SmallVector<int, 4> InLaneMask;
10297 InLaneMask.resize(LaneSize, -1);
10298 for (int i = 0; i < Size; ++i) {
10302 int j = i / LaneSize;
10304 if (Lanes[j] < 0) {
10305 // First entry we've seen for this lane.
10306 Lanes[j] = Mask[i] / LaneSize;
10307 } else if (Lanes[j] != Mask[i] / LaneSize) {
10308 // This doesn't match the lane selected previously!
10312 // Check that within each lane we have a consistent shuffle mask.
10313 int k = i % LaneSize;
10314 if (InLaneMask[k] < 0) {
10315 InLaneMask[k] = Mask[i] % LaneSize;
10316 } else if (InLaneMask[k] != Mask[i] % LaneSize) {
10317 // This doesn't fit a repeating in-lane mask.
10322 // First shuffle the lanes into place.
10323 MVT LaneVT = MVT::getVectorVT(VT.isFloatingPoint() ? MVT::f64 : MVT::i64,
10324 VT.getSizeInBits() / 64);
10325 SmallVector<int, 8> LaneMask;
10326 LaneMask.resize(NumLanes * 2, -1);
10327 for (int i = 0; i < NumLanes; ++i)
10328 if (Lanes[i] >= 0) {
10329 LaneMask[2 * i + 0] = 2*Lanes[i] + 0;
10330 LaneMask[2 * i + 1] = 2*Lanes[i] + 1;
10333 V1 = DAG.getBitcast(LaneVT, V1);
10334 V2 = DAG.getBitcast(LaneVT, V2);
10335 SDValue LaneShuffle = DAG.getVectorShuffle(LaneVT, DL, V1, V2, LaneMask);
10337 // Cast it back to the type we actually want.
10338 LaneShuffle = DAG.getBitcast(VT, LaneShuffle);
10340 // Now do a simple shuffle that isn't lane crossing.
10341 SmallVector<int, 8> NewMask;
10342 NewMask.resize(Size, -1);
10343 for (int i = 0; i < Size; ++i)
10345 NewMask[i] = (i / LaneSize) * LaneSize + Mask[i] % LaneSize;
10346 assert(!is128BitLaneCrossingShuffleMask(VT, NewMask) &&
10347 "Must not introduce lane crosses at this point!");
10349 return DAG.getVectorShuffle(VT, DL, LaneShuffle, DAG.getUNDEF(VT), NewMask);
10352 /// \brief Test whether the specified input (0 or 1) is in-place blended by the
10355 /// This returns true if the elements from a particular input are already in the
10356 /// slot required by the given mask and require no permutation.
10357 static bool isShuffleMaskInputInPlace(int Input, ArrayRef<int> Mask) {
10358 assert((Input == 0 || Input == 1) && "Only two inputs to shuffles.");
10359 int Size = Mask.size();
10360 for (int i = 0; i < Size; ++i)
10361 if (Mask[i] >= 0 && Mask[i] / Size == Input && Mask[i] % Size != i)
10367 static SDValue lowerVectorShuffleWithSHUFPD(SDLoc DL, MVT VT,
10368 ArrayRef<int> Mask, SDValue V1,
10369 SDValue V2, SelectionDAG &DAG) {
10371 // Mask for V8F64: 0/1, 8/9, 2/3, 10/11, 4/5, ..
10372 // Mask for V4F64; 0/1, 4/5, 2/3, 6/7..
10373 assert(VT.getScalarSizeInBits() == 64 && "Unexpected data type for VSHUFPD");
10374 int NumElts = VT.getVectorNumElements();
10375 bool ShufpdMask = true;
10376 bool CommutableMask = true;
10377 unsigned Immediate = 0;
10378 for (int i = 0; i < NumElts; ++i) {
10381 int Val = (i & 6) + NumElts * (i & 1);
10382 int CommutVal = (i & 0xe) + NumElts * ((i & 1)^1);
10383 if (Mask[i] < Val || Mask[i] > Val + 1)
10384 ShufpdMask = false;
10385 if (Mask[i] < CommutVal || Mask[i] > CommutVal + 1)
10386 CommutableMask = false;
10387 Immediate |= (Mask[i] % 2) << i;
10390 return DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
10391 DAG.getConstant(Immediate, DL, MVT::i8));
10392 if (CommutableMask)
10393 return DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
10394 DAG.getConstant(Immediate, DL, MVT::i8));
10398 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
10400 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
10401 /// isn't available.
10402 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10403 const X86Subtarget *Subtarget,
10404 SelectionDAG &DAG) {
10406 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10407 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10408 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10409 ArrayRef<int> Mask = SVOp->getMask();
10410 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10412 SmallVector<int, 4> WidenedMask;
10413 if (canWidenShuffleElements(Mask, WidenedMask))
10414 return lowerV2X128VectorShuffle(DL, MVT::v4f64, V1, V2, Mask, Subtarget,
10417 if (isSingleInputShuffleMask(Mask)) {
10418 // Check for being able to broadcast a single element.
10419 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4f64, V1,
10420 Mask, Subtarget, DAG))
10423 // Use low duplicate instructions for masks that match their pattern.
10424 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
10425 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v4f64, V1);
10427 if (!is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask)) {
10428 // Non-half-crossing single input shuffles can be lowerid with an
10429 // interleaved permutation.
10430 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
10431 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
10432 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
10433 DAG.getConstant(VPERMILPMask, DL, MVT::i8));
10436 // With AVX2 we have direct support for this permutation.
10437 if (Subtarget->hasAVX2())
10438 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4f64, V1,
10439 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
10441 // Otherwise, fall back.
10442 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v4f64, V1, V2, Mask,
10446 // Use dedicated unpack instructions for masks that match their pattern.
10448 lowerVectorShuffleWithUNPCK(DL, MVT::v4f64, Mask, V1, V2, DAG))
10451 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
10455 // Check if the blend happens to exactly fit that of SHUFPD.
10457 lowerVectorShuffleWithSHUFPD(DL, MVT::v4f64, Mask, V1, V2, DAG))
10460 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10461 // shuffle. However, if we have AVX2 and either inputs are already in place,
10462 // we will be able to shuffle even across lanes the other input in a single
10463 // instruction so skip this pattern.
10464 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10465 isShuffleMaskInputInPlace(1, Mask))))
10466 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10467 DL, MVT::v4f64, V1, V2, Mask, Subtarget, DAG))
10470 // If we have AVX2 then we always want to lower with a blend because an v4 we
10471 // can fully permute the elements.
10472 if (Subtarget->hasAVX2())
10473 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4f64, V1, V2,
10476 // Otherwise fall back on generic lowering.
10477 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v4f64, V1, V2, Mask, DAG);
10480 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
10482 /// This routine is only called when we have AVX2 and thus a reasonable
10483 /// instruction set for v4i64 shuffling..
10484 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10485 const X86Subtarget *Subtarget,
10486 SelectionDAG &DAG) {
10488 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10489 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10490 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10491 ArrayRef<int> Mask = SVOp->getMask();
10492 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10493 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
10495 SmallVector<int, 4> WidenedMask;
10496 if (canWidenShuffleElements(Mask, WidenedMask))
10497 return lowerV2X128VectorShuffle(DL, MVT::v4i64, V1, V2, Mask, Subtarget,
10500 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
10504 // Check for being able to broadcast a single element.
10505 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i64, V1,
10506 Mask, Subtarget, DAG))
10509 // When the shuffle is mirrored between the 128-bit lanes of the unit, we can
10510 // use lower latency instructions that will operate on both 128-bit lanes.
10511 SmallVector<int, 2> RepeatedMask;
10512 if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
10513 if (isSingleInputShuffleMask(Mask)) {
10514 int PSHUFDMask[] = {-1, -1, -1, -1};
10515 for (int i = 0; i < 2; ++i)
10516 if (RepeatedMask[i] >= 0) {
10517 PSHUFDMask[2 * i] = 2 * RepeatedMask[i];
10518 PSHUFDMask[2 * i + 1] = 2 * RepeatedMask[i] + 1;
10520 return DAG.getBitcast(
10522 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,
10523 DAG.getBitcast(MVT::v8i32, V1),
10524 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
10528 // AVX2 provides a direct instruction for permuting a single input across
10530 if (isSingleInputShuffleMask(Mask))
10531 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
10532 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
10534 // Try to use shift instructions.
10535 if (SDValue Shift =
10536 lowerVectorShuffleAsShift(DL, MVT::v4i64, V1, V2, Mask, DAG))
10539 // Use dedicated unpack instructions for masks that match their pattern.
10541 lowerVectorShuffleWithUNPCK(DL, MVT::v4i64, Mask, V1, V2, DAG))
10544 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10545 // shuffle. However, if we have AVX2 and either inputs are already in place,
10546 // we will be able to shuffle even across lanes the other input in a single
10547 // instruction so skip this pattern.
10548 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10549 isShuffleMaskInputInPlace(1, Mask))))
10550 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10551 DL, MVT::v4i64, V1, V2, Mask, Subtarget, DAG))
10554 // Otherwise fall back on generic blend lowering.
10555 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i64, V1, V2,
10559 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
10561 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
10562 /// isn't available.
10563 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10564 const X86Subtarget *Subtarget,
10565 SelectionDAG &DAG) {
10567 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10568 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10569 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10570 ArrayRef<int> Mask = SVOp->getMask();
10571 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10573 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
10577 // Check for being able to broadcast a single element.
10578 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8f32, V1,
10579 Mask, Subtarget, DAG))
10582 // If the shuffle mask is repeated in each 128-bit lane, we have many more
10583 // options to efficiently lower the shuffle.
10584 SmallVector<int, 4> RepeatedMask;
10585 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask, RepeatedMask)) {
10586 assert(RepeatedMask.size() == 4 &&
10587 "Repeated masks must be half the mask width!");
10589 // Use even/odd duplicate instructions for masks that match their pattern.
10590 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2, 4, 4, 6, 6}))
10591 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v8f32, V1);
10592 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3, 5, 5, 7, 7}))
10593 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v8f32, V1);
10595 if (isSingleInputShuffleMask(Mask))
10596 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
10597 getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
10599 // Use dedicated unpack instructions for masks that match their pattern.
10601 lowerVectorShuffleWithUNPCK(DL, MVT::v8f32, Mask, V1, V2, DAG))
10604 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
10605 // have already handled any direct blends. We also need to squash the
10606 // repeated mask into a simulated v4f32 mask.
10607 for (int i = 0; i < 4; ++i)
10608 if (RepeatedMask[i] >= 8)
10609 RepeatedMask[i] -= 4;
10610 return lowerVectorShuffleWithSHUFPS(DL, MVT::v8f32, RepeatedMask, V1, V2, DAG);
10613 // If we have a single input shuffle with different shuffle patterns in the
10614 // two 128-bit lanes use the variable mask to VPERMILPS.
10615 if (isSingleInputShuffleMask(Mask)) {
10616 SDValue VPermMask[8];
10617 for (int i = 0; i < 8; ++i)
10618 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10619 : DAG.getConstant(Mask[i], DL, MVT::i32);
10620 if (!is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
10621 return DAG.getNode(
10622 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
10623 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
10625 if (Subtarget->hasAVX2())
10626 return DAG.getNode(
10627 X86ISD::VPERMV, DL, MVT::v8f32,
10628 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
10630 // Otherwise, fall back.
10631 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v8f32, V1, V2, Mask,
10635 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10637 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10638 DL, MVT::v8f32, V1, V2, Mask, Subtarget, DAG))
10641 // If we have AVX2 then we always want to lower with a blend because at v8 we
10642 // can fully permute the elements.
10643 if (Subtarget->hasAVX2())
10644 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8f32, V1, V2,
10647 // Otherwise fall back on generic lowering.
10648 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v8f32, V1, V2, Mask, DAG);
10651 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
10653 /// This routine is only called when we have AVX2 and thus a reasonable
10654 /// instruction set for v8i32 shuffling..
10655 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10656 const X86Subtarget *Subtarget,
10657 SelectionDAG &DAG) {
10659 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10660 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10661 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10662 ArrayRef<int> Mask = SVOp->getMask();
10663 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10664 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
10666 // Whenever we can lower this as a zext, that instruction is strictly faster
10667 // than any alternative. It also allows us to fold memory operands into the
10668 // shuffle in many cases.
10669 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v8i32, V1, V2,
10670 Mask, Subtarget, DAG))
10673 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i32, V1, V2, Mask,
10677 // Check for being able to broadcast a single element.
10678 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8i32, V1,
10679 Mask, Subtarget, DAG))
10682 // If the shuffle mask is repeated in each 128-bit lane we can use more
10683 // efficient instructions that mirror the shuffles across the two 128-bit
10685 SmallVector<int, 4> RepeatedMask;
10686 if (is128BitLaneRepeatedShuffleMask(MVT::v8i32, Mask, RepeatedMask)) {
10687 assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
10688 if (isSingleInputShuffleMask(Mask))
10689 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32, V1,
10690 getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
10692 // Use dedicated unpack instructions for masks that match their pattern.
10694 lowerVectorShuffleWithUNPCK(DL, MVT::v8i32, Mask, V1, V2, DAG))
10698 // Try to use shift instructions.
10699 if (SDValue Shift =
10700 lowerVectorShuffleAsShift(DL, MVT::v8i32, V1, V2, Mask, DAG))
10703 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10704 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
10707 // If the shuffle patterns aren't repeated but it is a single input, directly
10708 // generate a cross-lane VPERMD instruction.
10709 if (isSingleInputShuffleMask(Mask)) {
10710 SDValue VPermMask[8];
10711 for (int i = 0; i < 8; ++i)
10712 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10713 : DAG.getConstant(Mask[i], DL, MVT::i32);
10714 return DAG.getNode(
10715 X86ISD::VPERMV, DL, MVT::v8i32,
10716 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
10719 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10721 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10722 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
10725 // Otherwise fall back on generic blend lowering.
10726 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i32, V1, V2,
10730 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
10732 /// This routine is only called when we have AVX2 and thus a reasonable
10733 /// instruction set for v16i16 shuffling..
10734 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10735 const X86Subtarget *Subtarget,
10736 SelectionDAG &DAG) {
10738 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10739 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10740 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10741 ArrayRef<int> Mask = SVOp->getMask();
10742 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10743 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
10745 // Whenever we can lower this as a zext, that instruction is strictly faster
10746 // than any alternative. It also allows us to fold memory operands into the
10747 // shuffle in many cases.
10748 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v16i16, V1, V2,
10749 Mask, Subtarget, DAG))
10752 // Check for being able to broadcast a single element.
10753 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v16i16, V1,
10754 Mask, Subtarget, DAG))
10757 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i16, V1, V2, Mask,
10761 // Use dedicated unpack instructions for masks that match their pattern.
10763 lowerVectorShuffleWithUNPCK(DL, MVT::v16i16, Mask, V1, V2, DAG))
10766 // Try to use shift instructions.
10767 if (SDValue Shift =
10768 lowerVectorShuffleAsShift(DL, MVT::v16i16, V1, V2, Mask, DAG))
10771 // Try to use byte rotation instructions.
10772 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10773 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
10776 if (isSingleInputShuffleMask(Mask)) {
10777 // There are no generalized cross-lane shuffle operations available on i16
10779 if (is128BitLaneCrossingShuffleMask(MVT::v16i16, Mask))
10780 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v16i16, V1, V2,
10783 SmallVector<int, 8> RepeatedMask;
10784 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
10785 // As this is a single-input shuffle, the repeated mask should be
10786 // a strictly valid v8i16 mask that we can pass through to the v8i16
10787 // lowering to handle even the v16 case.
10788 return lowerV8I16GeneralSingleInputVectorShuffle(
10789 DL, MVT::v16i16, V1, RepeatedMask, Subtarget, DAG);
10792 SDValue PSHUFBMask[32];
10793 for (int i = 0; i < 16; ++i) {
10794 if (Mask[i] == -1) {
10795 PSHUFBMask[2 * i] = PSHUFBMask[2 * i + 1] = DAG.getUNDEF(MVT::i8);
10799 int M = i < 8 ? Mask[i] : Mask[i] - 8;
10800 assert(M >= 0 && M < 8 && "Invalid single-input mask!");
10801 PSHUFBMask[2 * i] = DAG.getConstant(2 * M, DL, MVT::i8);
10802 PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, DL, MVT::i8);
10804 return DAG.getBitcast(MVT::v16i16,
10805 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8,
10806 DAG.getBitcast(MVT::v32i8, V1),
10807 DAG.getNode(ISD::BUILD_VECTOR, DL,
10808 MVT::v32i8, PSHUFBMask)));
10811 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10813 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10814 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
10817 // Otherwise fall back on generic lowering.
10818 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v16i16, V1, V2, Mask, DAG);
10821 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
10823 /// This routine is only called when we have AVX2 and thus a reasonable
10824 /// instruction set for v32i8 shuffling..
10825 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10826 const X86Subtarget *Subtarget,
10827 SelectionDAG &DAG) {
10829 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10830 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10831 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10832 ArrayRef<int> Mask = SVOp->getMask();
10833 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10834 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
10836 // Whenever we can lower this as a zext, that instruction is strictly faster
10837 // than any alternative. It also allows us to fold memory operands into the
10838 // shuffle in many cases.
10839 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v32i8, V1, V2,
10840 Mask, Subtarget, DAG))
10843 // Check for being able to broadcast a single element.
10844 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v32i8, V1,
10845 Mask, Subtarget, DAG))
10848 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v32i8, V1, V2, Mask,
10852 // Use dedicated unpack instructions for masks that match their pattern.
10854 lowerVectorShuffleWithUNPCK(DL, MVT::v32i8, Mask, V1, V2, DAG))
10857 // Try to use shift instructions.
10858 if (SDValue Shift =
10859 lowerVectorShuffleAsShift(DL, MVT::v32i8, V1, V2, Mask, DAG))
10862 // Try to use byte rotation instructions.
10863 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10864 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10867 if (isSingleInputShuffleMask(Mask)) {
10868 // There are no generalized cross-lane shuffle operations available on i8
10870 if (is128BitLaneCrossingShuffleMask(MVT::v32i8, Mask))
10871 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v32i8, V1, V2,
10874 SDValue PSHUFBMask[32];
10875 for (int i = 0; i < 32; ++i)
10878 ? DAG.getUNDEF(MVT::i8)
10879 : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16, DL,
10882 return DAG.getNode(
10883 X86ISD::PSHUFB, DL, MVT::v32i8, V1,
10884 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask));
10887 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10889 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10890 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10893 // Otherwise fall back on generic lowering.
10894 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v32i8, V1, V2, Mask, DAG);
10897 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
10899 /// This routine either breaks down the specific type of a 256-bit x86 vector
10900 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
10901 /// together based on the available instructions.
10902 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10903 MVT VT, const X86Subtarget *Subtarget,
10904 SelectionDAG &DAG) {
10906 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10907 ArrayRef<int> Mask = SVOp->getMask();
10909 // If we have a single input to the zero element, insert that into V1 if we
10910 // can do so cheaply.
10911 int NumElts = VT.getVectorNumElements();
10912 int NumV2Elements = std::count_if(Mask.begin(), Mask.end(), [NumElts](int M) {
10913 return M >= NumElts;
10916 if (NumV2Elements == 1 && Mask[0] >= NumElts)
10917 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
10918 DL, VT, V1, V2, Mask, Subtarget, DAG))
10921 // There is a really nice hard cut-over between AVX1 and AVX2 that means we
10922 // can check for those subtargets here and avoid much of the subtarget
10923 // querying in the per-vector-type lowering routines. With AVX1 we have
10924 // essentially *zero* ability to manipulate a 256-bit vector with integer
10925 // types. Since we'll use floating point types there eventually, just
10926 // immediately cast everything to a float and operate entirely in that domain.
10927 if (VT.isInteger() && !Subtarget->hasAVX2()) {
10928 int ElementBits = VT.getScalarSizeInBits();
10929 if (ElementBits < 32)
10930 // No floating point type available, decompose into 128-bit vectors.
10931 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10933 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
10934 VT.getVectorNumElements());
10935 V1 = DAG.getBitcast(FpVT, V1);
10936 V2 = DAG.getBitcast(FpVT, V2);
10937 return DAG.getBitcast(VT, DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
10940 switch (VT.SimpleTy) {
10942 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10944 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10946 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10948 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10950 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10952 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10955 llvm_unreachable("Not a valid 256-bit x86 vector type!");
10959 /// \brief Try to lower a vector shuffle as a 128-bit shuffles.
10960 static SDValue lowerV4X128VectorShuffle(SDLoc DL, MVT VT,
10961 ArrayRef<int> Mask,
10962 SDValue V1, SDValue V2,
10963 SelectionDAG &DAG) {
10964 assert(VT.getScalarSizeInBits() == 64 &&
10965 "Unexpected element type size for 128bit shuffle.");
10967 // To handle 256 bit vector requires VLX and most probably
10968 // function lowerV2X128VectorShuffle() is better solution.
10969 assert(VT.is512BitVector() && "Unexpected vector size for 128bit shuffle.");
10971 SmallVector<int, 4> WidenedMask;
10972 if (!canWidenShuffleElements(Mask, WidenedMask))
10975 // Form a 128-bit permutation.
10976 // Convert the 64-bit shuffle mask selection values into 128-bit selection
10977 // bits defined by a vshuf64x2 instruction's immediate control byte.
10978 unsigned PermMask = 0, Imm = 0;
10979 unsigned ControlBitsNum = WidenedMask.size() / 2;
10981 for (int i = 0, Size = WidenedMask.size(); i < Size; ++i) {
10982 if (WidenedMask[i] == SM_SentinelZero)
10985 // Use first element in place of undef mask.
10986 Imm = (WidenedMask[i] == SM_SentinelUndef) ? 0 : WidenedMask[i];
10987 PermMask |= (Imm % WidenedMask.size()) << (i * ControlBitsNum);
10990 return DAG.getNode(X86ISD::SHUF128, DL, VT, V1, V2,
10991 DAG.getConstant(PermMask, DL, MVT::i8));
10994 static SDValue lowerVectorShuffleWithPERMV(SDLoc DL, MVT VT,
10995 ArrayRef<int> Mask, SDValue V1,
10996 SDValue V2, SelectionDAG &DAG) {
10998 assert(VT.getScalarSizeInBits() >= 16 && "Unexpected data type for PERMV");
11000 MVT MaskEltVT = MVT::getIntegerVT(VT.getScalarSizeInBits());
11001 MVT MaskVecVT = MVT::getVectorVT(MaskEltVT, VT.getVectorNumElements());
11003 SDValue MaskNode = getConstVector(Mask, MaskVecVT, DAG, DL, true);
11004 if (isSingleInputShuffleMask(Mask))
11005 return DAG.getNode(X86ISD::VPERMV, DL, VT, MaskNode, V1);
11007 return DAG.getNode(X86ISD::VPERMV3, DL, VT, V1, MaskNode, V2);
11010 /// \brief Handle lowering of 8-lane 64-bit floating point shuffles.
11011 static SDValue lowerV8F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
11012 const X86Subtarget *Subtarget,
11013 SelectionDAG &DAG) {
11015 assert(V1.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
11016 assert(V2.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
11017 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11018 ArrayRef<int> Mask = SVOp->getMask();
11019 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
11021 if (SDValue Shuf128 =
11022 lowerV4X128VectorShuffle(DL, MVT::v8f64, Mask, V1, V2, DAG))
11025 if (SDValue Unpck =
11026 lowerVectorShuffleWithUNPCK(DL, MVT::v8f64, Mask, V1, V2, DAG))
11029 return lowerVectorShuffleWithPERMV(DL, MVT::v8f64, Mask, V1, V2, DAG);
11032 /// \brief Handle lowering of 16-lane 32-bit floating point shuffles.
11033 static SDValue lowerV16F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
11034 const X86Subtarget *Subtarget,
11035 SelectionDAG &DAG) {
11037 assert(V1.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
11038 assert(V2.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
11039 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11040 ArrayRef<int> Mask = SVOp->getMask();
11041 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
11043 if (SDValue Unpck =
11044 lowerVectorShuffleWithUNPCK(DL, MVT::v16f32, Mask, V1, V2, DAG))
11047 return lowerVectorShuffleWithPERMV(DL, MVT::v16f32, Mask, V1, V2, DAG);
11050 /// \brief Handle lowering of 8-lane 64-bit integer shuffles.
11051 static SDValue lowerV8I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
11052 const X86Subtarget *Subtarget,
11053 SelectionDAG &DAG) {
11055 assert(V1.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
11056 assert(V2.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
11057 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11058 ArrayRef<int> Mask = SVOp->getMask();
11059 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
11061 if (SDValue Shuf128 =
11062 lowerV4X128VectorShuffle(DL, MVT::v8i64, Mask, V1, V2, DAG))
11065 if (SDValue Unpck =
11066 lowerVectorShuffleWithUNPCK(DL, MVT::v8i64, Mask, V1, V2, DAG))
11069 return lowerVectorShuffleWithPERMV(DL, MVT::v8i64, Mask, V1, V2, DAG);
11072 /// \brief Handle lowering of 16-lane 32-bit integer shuffles.
11073 static SDValue lowerV16I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
11074 const X86Subtarget *Subtarget,
11075 SelectionDAG &DAG) {
11077 assert(V1.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
11078 assert(V2.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
11079 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11080 ArrayRef<int> Mask = SVOp->getMask();
11081 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
11083 if (SDValue Unpck =
11084 lowerVectorShuffleWithUNPCK(DL, MVT::v16i32, Mask, V1, V2, DAG))
11087 return lowerVectorShuffleWithPERMV(DL, MVT::v16i32, Mask, V1, V2, DAG);
11090 /// \brief Handle lowering of 32-lane 16-bit integer shuffles.
11091 static SDValue lowerV32I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
11092 const X86Subtarget *Subtarget,
11093 SelectionDAG &DAG) {
11095 assert(V1.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
11096 assert(V2.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
11097 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11098 ArrayRef<int> Mask = SVOp->getMask();
11099 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
11100 assert(Subtarget->hasBWI() && "We can only lower v32i16 with AVX-512-BWI!");
11102 return lowerVectorShuffleWithPERMV(DL, MVT::v32i16, Mask, V1, V2, DAG);
11105 /// \brief Handle lowering of 64-lane 8-bit integer shuffles.
11106 static SDValue lowerV64I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
11107 const X86Subtarget *Subtarget,
11108 SelectionDAG &DAG) {
11110 assert(V1.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
11111 assert(V2.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
11112 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11113 ArrayRef<int> Mask = SVOp->getMask();
11114 assert(Mask.size() == 64 && "Unexpected mask size for v64 shuffle!");
11115 assert(Subtarget->hasBWI() && "We can only lower v64i8 with AVX-512-BWI!");
11117 // FIXME: Implement direct support for this type!
11118 return splitAndLowerVectorShuffle(DL, MVT::v64i8, V1, V2, Mask, DAG);
11121 /// \brief High-level routine to lower various 512-bit x86 vector shuffles.
11123 /// This routine either breaks down the specific type of a 512-bit x86 vector
11124 /// shuffle or splits it into two 256-bit shuffles and fuses the results back
11125 /// together based on the available instructions.
11126 static SDValue lower512BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
11127 MVT VT, const X86Subtarget *Subtarget,
11128 SelectionDAG &DAG) {
11130 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11131 ArrayRef<int> Mask = SVOp->getMask();
11132 assert(Subtarget->hasAVX512() &&
11133 "Cannot lower 512-bit vectors w/ basic ISA!");
11135 // Check for being able to broadcast a single element.
11136 if (SDValue Broadcast =
11137 lowerVectorShuffleAsBroadcast(DL, VT, V1, Mask, Subtarget, DAG))
11140 // Dispatch to each element type for lowering. If we don't have supprot for
11141 // specific element type shuffles at 512 bits, immediately split them and
11142 // lower them. Each lowering routine of a given type is allowed to assume that
11143 // the requisite ISA extensions for that element type are available.
11144 switch (VT.SimpleTy) {
11146 return lowerV8F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
11148 return lowerV16F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
11150 return lowerV8I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
11152 return lowerV16I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
11154 if (Subtarget->hasBWI())
11155 return lowerV32I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
11158 if (Subtarget->hasBWI())
11159 return lowerV64I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
11163 llvm_unreachable("Not a valid 512-bit x86 vector type!");
11166 // Otherwise fall back on splitting.
11167 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
11170 // Lower vXi1 vector shuffles.
11171 // There is no a dedicated instruction on AVX-512 that shuffles the masks.
11172 // The only way to shuffle bits is to sign-extend the mask vector to SIMD
11173 // vector, shuffle and then truncate it back.
11174 static SDValue lower1BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
11175 MVT VT, const X86Subtarget *Subtarget,
11176 SelectionDAG &DAG) {
11178 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11179 ArrayRef<int> Mask = SVOp->getMask();
11180 assert(Subtarget->hasAVX512() &&
11181 "Cannot lower 512-bit vectors w/o basic ISA!");
11183 switch (VT.SimpleTy) {
11185 llvm_unreachable("Expected a vector of i1 elements");
11187 ExtVT = MVT::v2i64;
11190 ExtVT = MVT::v4i32;
11193 ExtVT = MVT::v8i64; // Take 512-bit type, more shuffles on KNL
11196 ExtVT = MVT::v16i32;
11199 ExtVT = MVT::v32i16;
11202 ExtVT = MVT::v64i8;
11206 if (ISD::isBuildVectorAllZeros(V1.getNode()))
11207 V1 = getZeroVector(ExtVT, Subtarget, DAG, DL);
11208 else if (ISD::isBuildVectorAllOnes(V1.getNode()))
11209 V1 = getOnesVector(ExtVT, Subtarget, DAG, DL);
11211 V1 = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, V1);
11214 V2 = DAG.getUNDEF(ExtVT);
11215 else if (ISD::isBuildVectorAllZeros(V2.getNode()))
11216 V2 = getZeroVector(ExtVT, Subtarget, DAG, DL);
11217 else if (ISD::isBuildVectorAllOnes(V2.getNode()))
11218 V2 = getOnesVector(ExtVT, Subtarget, DAG, DL);
11220 V2 = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, V2);
11221 return DAG.getNode(ISD::TRUNCATE, DL, VT,
11222 DAG.getVectorShuffle(ExtVT, DL, V1, V2, Mask));
11224 /// \brief Top-level lowering for x86 vector shuffles.
11226 /// This handles decomposition, canonicalization, and lowering of all x86
11227 /// vector shuffles. Most of the specific lowering strategies are encapsulated
11228 /// above in helper routines. The canonicalization attempts to widen shuffles
11229 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
11230 /// s.t. only one of the two inputs needs to be tested, etc.
11231 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
11232 SelectionDAG &DAG) {
11233 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11234 ArrayRef<int> Mask = SVOp->getMask();
11235 SDValue V1 = Op.getOperand(0);
11236 SDValue V2 = Op.getOperand(1);
11237 MVT VT = Op.getSimpleValueType();
11238 int NumElements = VT.getVectorNumElements();
11240 bool Is1BitVector = (VT.getVectorElementType() == MVT::i1);
11242 assert((VT.getSizeInBits() != 64 || Is1BitVector) &&
11243 "Can't lower MMX shuffles");
11245 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
11246 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
11247 if (V1IsUndef && V2IsUndef)
11248 return DAG.getUNDEF(VT);
11250 // When we create a shuffle node we put the UNDEF node to second operand,
11251 // but in some cases the first operand may be transformed to UNDEF.
11252 // In this case we should just commute the node.
11254 return DAG.getCommutedVectorShuffle(*SVOp);
11256 // Check for non-undef masks pointing at an undef vector and make the masks
11257 // undef as well. This makes it easier to match the shuffle based solely on
11261 if (M >= NumElements) {
11262 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
11263 for (int &M : NewMask)
11264 if (M >= NumElements)
11266 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
11269 // We actually see shuffles that are entirely re-arrangements of a set of
11270 // zero inputs. This mostly happens while decomposing complex shuffles into
11271 // simple ones. Directly lower these as a buildvector of zeros.
11272 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
11273 if (Zeroable.all())
11274 return getZeroVector(VT, Subtarget, DAG, dl);
11276 // Try to collapse shuffles into using a vector type with fewer elements but
11277 // wider element types. We cap this to not form integers or floating point
11278 // elements wider than 64 bits, but it might be interesting to form i128
11279 // integers to handle flipping the low and high halves of AVX 256-bit vectors.
11280 SmallVector<int, 16> WidenedMask;
11281 if (VT.getScalarSizeInBits() < 64 && !Is1BitVector &&
11282 canWidenShuffleElements(Mask, WidenedMask)) {
11283 MVT NewEltVT = VT.isFloatingPoint()
11284 ? MVT::getFloatingPointVT(VT.getScalarSizeInBits() * 2)
11285 : MVT::getIntegerVT(VT.getScalarSizeInBits() * 2);
11286 MVT NewVT = MVT::getVectorVT(NewEltVT, VT.getVectorNumElements() / 2);
11287 // Make sure that the new vector type is legal. For example, v2f64 isn't
11289 if (DAG.getTargetLoweringInfo().isTypeLegal(NewVT)) {
11290 V1 = DAG.getBitcast(NewVT, V1);
11291 V2 = DAG.getBitcast(NewVT, V2);
11292 return DAG.getBitcast(
11293 VT, DAG.getVectorShuffle(NewVT, dl, V1, V2, WidenedMask));
11297 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
11298 for (int M : SVOp->getMask())
11300 ++NumUndefElements;
11301 else if (M < NumElements)
11306 // Commute the shuffle as needed such that more elements come from V1 than
11307 // V2. This allows us to match the shuffle pattern strictly on how many
11308 // elements come from V1 without handling the symmetric cases.
11309 if (NumV2Elements > NumV1Elements)
11310 return DAG.getCommutedVectorShuffle(*SVOp);
11312 // When the number of V1 and V2 elements are the same, try to minimize the
11313 // number of uses of V2 in the low half of the vector. When that is tied,
11314 // ensure that the sum of indices for V1 is equal to or lower than the sum
11315 // indices for V2. When those are equal, try to ensure that the number of odd
11316 // indices for V1 is lower than the number of odd indices for V2.
11317 if (NumV1Elements == NumV2Elements) {
11318 int LowV1Elements = 0, LowV2Elements = 0;
11319 for (int M : SVOp->getMask().slice(0, NumElements / 2))
11320 if (M >= NumElements)
11324 if (LowV2Elements > LowV1Elements) {
11325 return DAG.getCommutedVectorShuffle(*SVOp);
11326 } else if (LowV2Elements == LowV1Elements) {
11327 int SumV1Indices = 0, SumV2Indices = 0;
11328 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
11329 if (SVOp->getMask()[i] >= NumElements)
11331 else if (SVOp->getMask()[i] >= 0)
11333 if (SumV2Indices < SumV1Indices) {
11334 return DAG.getCommutedVectorShuffle(*SVOp);
11335 } else if (SumV2Indices == SumV1Indices) {
11336 int NumV1OddIndices = 0, NumV2OddIndices = 0;
11337 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
11338 if (SVOp->getMask()[i] >= NumElements)
11339 NumV2OddIndices += i % 2;
11340 else if (SVOp->getMask()[i] >= 0)
11341 NumV1OddIndices += i % 2;
11342 if (NumV2OddIndices < NumV1OddIndices)
11343 return DAG.getCommutedVectorShuffle(*SVOp);
11348 // For each vector width, delegate to a specialized lowering routine.
11349 if (VT.is128BitVector())
11350 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11352 if (VT.is256BitVector())
11353 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11355 if (VT.is512BitVector())
11356 return lower512BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11359 return lower1BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11360 llvm_unreachable("Unimplemented!");
11363 // This function assumes its argument is a BUILD_VECTOR of constants or
11364 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
11366 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
11367 unsigned &MaskValue) {
11369 unsigned NumElems = BuildVector->getNumOperands();
11371 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
11372 // We don't handle the >2 lanes case right now.
11373 unsigned NumLanes = (NumElems - 1) / 8 + 1;
11377 unsigned NumElemsInLane = NumElems / NumLanes;
11379 // Blend for v16i16 should be symmetric for the both lanes.
11380 for (unsigned i = 0; i < NumElemsInLane; ++i) {
11381 SDValue EltCond = BuildVector->getOperand(i);
11382 SDValue SndLaneEltCond =
11383 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
11385 int Lane1Cond = -1, Lane2Cond = -1;
11386 if (isa<ConstantSDNode>(EltCond))
11387 Lane1Cond = !isNullConstant(EltCond);
11388 if (isa<ConstantSDNode>(SndLaneEltCond))
11389 Lane2Cond = !isNullConstant(SndLaneEltCond);
11391 unsigned LaneMask = 0;
11392 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
11393 // Lane1Cond != 0, means we want the first argument.
11394 // Lane1Cond == 0, means we want the second argument.
11395 // The encoding of this argument is 0 for the first argument, 1
11396 // for the second. Therefore, invert the condition.
11397 LaneMask = !Lane1Cond << i;
11398 else if (Lane1Cond < 0)
11399 LaneMask = !Lane2Cond << i;
11403 MaskValue |= LaneMask;
11405 MaskValue |= LaneMask << NumElemsInLane;
11410 /// \brief Try to lower a VSELECT instruction to a vector shuffle.
11411 static SDValue lowerVSELECTtoVectorShuffle(SDValue Op,
11412 const X86Subtarget *Subtarget,
11413 SelectionDAG &DAG) {
11414 SDValue Cond = Op.getOperand(0);
11415 SDValue LHS = Op.getOperand(1);
11416 SDValue RHS = Op.getOperand(2);
11418 MVT VT = Op.getSimpleValueType();
11420 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
11422 auto *CondBV = cast<BuildVectorSDNode>(Cond);
11424 // Only non-legal VSELECTs reach this lowering, convert those into generic
11425 // shuffles and re-use the shuffle lowering path for blends.
11426 SmallVector<int, 32> Mask;
11427 for (int i = 0, Size = VT.getVectorNumElements(); i < Size; ++i) {
11428 SDValue CondElt = CondBV->getOperand(i);
11430 isa<ConstantSDNode>(CondElt) ? i + (isNullConstant(CondElt) ? Size : 0)
11433 return DAG.getVectorShuffle(VT, dl, LHS, RHS, Mask);
11436 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
11437 // A vselect where all conditions and data are constants can be optimized into
11438 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
11439 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
11440 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
11441 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
11444 // Try to lower this to a blend-style vector shuffle. This can handle all
11445 // constant condition cases.
11446 if (SDValue BlendOp = lowerVSELECTtoVectorShuffle(Op, Subtarget, DAG))
11449 // Variable blends are only legal from SSE4.1 onward.
11450 if (!Subtarget->hasSSE41())
11453 // Only some types will be legal on some subtargets. If we can emit a legal
11454 // VSELECT-matching blend, return Op, and but if we need to expand, return
11456 switch (Op.getSimpleValueType().SimpleTy) {
11458 // Most of the vector types have blends past SSE4.1.
11462 // The byte blends for AVX vectors were introduced only in AVX2.
11463 if (Subtarget->hasAVX2())
11470 // AVX-512 BWI and VLX features support VSELECT with i16 elements.
11471 if (Subtarget->hasBWI() && Subtarget->hasVLX())
11474 // FIXME: We should custom lower this by fixing the condition and using i8
11480 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
11481 MVT VT = Op.getSimpleValueType();
11484 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
11487 if (VT.getSizeInBits() == 8) {
11488 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
11489 Op.getOperand(0), Op.getOperand(1));
11490 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
11491 DAG.getValueType(VT));
11492 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11495 if (VT.getSizeInBits() == 16) {
11496 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
11497 if (isNullConstant(Op.getOperand(1)))
11498 return DAG.getNode(
11499 ISD::TRUNCATE, dl, MVT::i16,
11500 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11501 DAG.getBitcast(MVT::v4i32, Op.getOperand(0)),
11502 Op.getOperand(1)));
11503 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
11504 Op.getOperand(0), Op.getOperand(1));
11505 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
11506 DAG.getValueType(VT));
11507 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11510 if (VT == MVT::f32) {
11511 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
11512 // the result back to FR32 register. It's only worth matching if the
11513 // result has a single use which is a store or a bitcast to i32. And in
11514 // the case of a store, it's not worth it if the index is a constant 0,
11515 // because a MOVSSmr can be used instead, which is smaller and faster.
11516 if (!Op.hasOneUse())
11518 SDNode *User = *Op.getNode()->use_begin();
11519 if ((User->getOpcode() != ISD::STORE ||
11520 isNullConstant(Op.getOperand(1))) &&
11521 (User->getOpcode() != ISD::BITCAST ||
11522 User->getValueType(0) != MVT::i32))
11524 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11525 DAG.getBitcast(MVT::v4i32, Op.getOperand(0)),
11527 return DAG.getBitcast(MVT::f32, Extract);
11530 if (VT == MVT::i32 || VT == MVT::i64) {
11531 // ExtractPS/pextrq works with constant index.
11532 if (isa<ConstantSDNode>(Op.getOperand(1)))
11538 /// Extract one bit from mask vector, like v16i1 or v8i1.
11539 /// AVX-512 feature.
11541 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
11542 SDValue Vec = Op.getOperand(0);
11544 MVT VecVT = Vec.getSimpleValueType();
11545 SDValue Idx = Op.getOperand(1);
11546 MVT EltVT = Op.getSimpleValueType();
11548 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
11549 assert((VecVT.getVectorNumElements() <= 16 || Subtarget->hasBWI()) &&
11550 "Unexpected vector type in ExtractBitFromMaskVector");
11552 // variable index can't be handled in mask registers,
11553 // extend vector to VR512
11554 if (!isa<ConstantSDNode>(Idx)) {
11555 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
11556 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
11557 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
11558 ExtVT.getVectorElementType(), Ext, Idx);
11559 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
11562 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11563 const TargetRegisterClass* rc = getRegClassFor(VecVT);
11564 if (!Subtarget->hasDQI() && (VecVT.getVectorNumElements() <= 8))
11565 rc = getRegClassFor(MVT::v16i1);
11566 unsigned MaxSift = rc->getSize()*8 - 1;
11567 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
11568 DAG.getConstant(MaxSift - IdxVal, dl, MVT::i8));
11569 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
11570 DAG.getConstant(MaxSift, dl, MVT::i8));
11571 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
11572 DAG.getIntPtrConstant(0, dl));
11576 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
11577 SelectionDAG &DAG) const {
11579 SDValue Vec = Op.getOperand(0);
11580 MVT VecVT = Vec.getSimpleValueType();
11581 SDValue Idx = Op.getOperand(1);
11583 if (Op.getSimpleValueType() == MVT::i1)
11584 return ExtractBitFromMaskVector(Op, DAG);
11586 if (!isa<ConstantSDNode>(Idx)) {
11587 if (VecVT.is512BitVector() ||
11588 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
11589 VecVT.getVectorElementType().getSizeInBits() == 32)) {
11592 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
11593 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
11594 MaskEltVT.getSizeInBits());
11596 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
11597 auto PtrVT = getPointerTy(DAG.getDataLayout());
11598 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
11599 getZeroVector(MaskVT, Subtarget, DAG, dl), Idx,
11600 DAG.getConstant(0, dl, PtrVT));
11601 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
11602 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Perm,
11603 DAG.getConstant(0, dl, PtrVT));
11608 // If this is a 256-bit vector result, first extract the 128-bit vector and
11609 // then extract the element from the 128-bit vector.
11610 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
11612 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11613 // Get the 128-bit vector.
11614 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
11615 MVT EltVT = VecVT.getVectorElementType();
11617 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
11618 assert(isPowerOf2_32(ElemsPerChunk) && "Elements per chunk not power of 2");
11620 // Find IdxVal modulo ElemsPerChunk. Since ElemsPerChunk is a power of 2
11621 // this can be done with a mask.
11622 IdxVal &= ElemsPerChunk - 1;
11623 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
11624 DAG.getConstant(IdxVal, dl, MVT::i32));
11627 assert(VecVT.is128BitVector() && "Unexpected vector length");
11629 if (Subtarget->hasSSE41())
11630 if (SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG))
11633 MVT VT = Op.getSimpleValueType();
11634 // TODO: handle v16i8.
11635 if (VT.getSizeInBits() == 16) {
11636 SDValue Vec = Op.getOperand(0);
11637 if (isNullConstant(Op.getOperand(1)))
11638 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
11639 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11640 DAG.getBitcast(MVT::v4i32, Vec),
11641 Op.getOperand(1)));
11642 // Transform it so it match pextrw which produces a 32-bit result.
11643 MVT EltVT = MVT::i32;
11644 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
11645 Op.getOperand(0), Op.getOperand(1));
11646 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
11647 DAG.getValueType(VT));
11648 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11651 if (VT.getSizeInBits() == 32) {
11652 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11656 // SHUFPS the element to the lowest double word, then movss.
11657 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
11658 MVT VVT = Op.getOperand(0).getSimpleValueType();
11659 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
11660 DAG.getUNDEF(VVT), Mask);
11661 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
11662 DAG.getIntPtrConstant(0, dl));
11665 if (VT.getSizeInBits() == 64) {
11666 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
11667 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
11668 // to match extract_elt for f64.
11669 if (isNullConstant(Op.getOperand(1)))
11672 // UNPCKHPD the element to the lowest double word, then movsd.
11673 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
11674 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
11675 int Mask[2] = { 1, -1 };
11676 MVT VVT = Op.getOperand(0).getSimpleValueType();
11677 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
11678 DAG.getUNDEF(VVT), Mask);
11679 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
11680 DAG.getIntPtrConstant(0, dl));
11686 /// Insert one bit to mask vector, like v16i1 or v8i1.
11687 /// AVX-512 feature.
11689 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
11691 SDValue Vec = Op.getOperand(0);
11692 SDValue Elt = Op.getOperand(1);
11693 SDValue Idx = Op.getOperand(2);
11694 MVT VecVT = Vec.getSimpleValueType();
11696 if (!isa<ConstantSDNode>(Idx)) {
11697 // Non constant index. Extend source and destination,
11698 // insert element and then truncate the result.
11699 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
11700 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
11701 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
11702 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
11703 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
11704 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
11707 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11708 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
11710 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
11711 DAG.getConstant(IdxVal, dl, MVT::i8));
11712 if (Vec.getOpcode() == ISD::UNDEF)
11714 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
11717 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
11718 SelectionDAG &DAG) const {
11719 MVT VT = Op.getSimpleValueType();
11720 MVT EltVT = VT.getVectorElementType();
11722 if (EltVT == MVT::i1)
11723 return InsertBitToMaskVector(Op, DAG);
11726 SDValue N0 = Op.getOperand(0);
11727 SDValue N1 = Op.getOperand(1);
11728 SDValue N2 = Op.getOperand(2);
11729 if (!isa<ConstantSDNode>(N2))
11731 auto *N2C = cast<ConstantSDNode>(N2);
11732 unsigned IdxVal = N2C->getZExtValue();
11734 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
11735 // into that, and then insert the subvector back into the result.
11736 if (VT.is256BitVector() || VT.is512BitVector()) {
11737 // With a 256-bit vector, we can insert into the zero element efficiently
11738 // using a blend if we have AVX or AVX2 and the right data type.
11739 if (VT.is256BitVector() && IdxVal == 0) {
11740 // TODO: It is worthwhile to cast integer to floating point and back
11741 // and incur a domain crossing penalty if that's what we'll end up
11742 // doing anyway after extracting to a 128-bit vector.
11743 if ((Subtarget->hasAVX() && (EltVT == MVT::f64 || EltVT == MVT::f32)) ||
11744 (Subtarget->hasAVX2() && EltVT == MVT::i32)) {
11745 SDValue N1Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, N1);
11746 N2 = DAG.getIntPtrConstant(1, dl);
11747 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1Vec, N2);
11751 // Get the desired 128-bit vector chunk.
11752 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
11754 // Insert the element into the desired chunk.
11755 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
11756 assert(isPowerOf2_32(NumEltsIn128));
11757 // Since NumEltsIn128 is a power of 2 we can use mask instead of modulo.
11758 unsigned IdxIn128 = IdxVal & (NumEltsIn128 - 1);
11760 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
11761 DAG.getConstant(IdxIn128, dl, MVT::i32));
11763 // Insert the changed part back into the bigger vector
11764 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
11766 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
11768 if (Subtarget->hasSSE41()) {
11769 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
11771 if (VT == MVT::v8i16) {
11772 Opc = X86ISD::PINSRW;
11774 assert(VT == MVT::v16i8);
11775 Opc = X86ISD::PINSRB;
11778 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
11780 if (N1.getValueType() != MVT::i32)
11781 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
11782 if (N2.getValueType() != MVT::i32)
11783 N2 = DAG.getIntPtrConstant(IdxVal, dl);
11784 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
11787 if (EltVT == MVT::f32) {
11788 // Bits [7:6] of the constant are the source select. This will always be
11789 // zero here. The DAG Combiner may combine an extract_elt index into
11790 // these bits. For example (insert (extract, 3), 2) could be matched by
11791 // putting the '3' into bits [7:6] of X86ISD::INSERTPS.
11792 // Bits [5:4] of the constant are the destination select. This is the
11793 // value of the incoming immediate.
11794 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
11795 // combine either bitwise AND or insert of float 0.0 to set these bits.
11797 bool MinSize = DAG.getMachineFunction().getFunction()->optForMinSize();
11798 if (IdxVal == 0 && (!MinSize || !MayFoldLoad(N1))) {
11799 // If this is an insertion of 32-bits into the low 32-bits of
11800 // a vector, we prefer to generate a blend with immediate rather
11801 // than an insertps. Blends are simpler operations in hardware and so
11802 // will always have equal or better performance than insertps.
11803 // But if optimizing for size and there's a load folding opportunity,
11804 // generate insertps because blendps does not have a 32-bit memory
11806 N2 = DAG.getIntPtrConstant(1, dl);
11807 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
11808 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1, N2);
11810 N2 = DAG.getIntPtrConstant(IdxVal << 4, dl);
11811 // Create this as a scalar to vector..
11812 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
11813 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
11816 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
11817 // PINSR* works with constant index.
11822 if (EltVT == MVT::i8)
11825 if (EltVT.getSizeInBits() == 16) {
11826 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
11827 // as its second argument.
11828 if (N1.getValueType() != MVT::i32)
11829 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
11830 if (N2.getValueType() != MVT::i32)
11831 N2 = DAG.getIntPtrConstant(IdxVal, dl);
11832 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
11837 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
11839 MVT OpVT = Op.getSimpleValueType();
11841 // If this is a 256-bit vector result, first insert into a 128-bit
11842 // vector and then insert into the 256-bit vector.
11843 if (!OpVT.is128BitVector()) {
11844 // Insert into a 128-bit vector.
11845 unsigned SizeFactor = OpVT.getSizeInBits()/128;
11846 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
11847 OpVT.getVectorNumElements() / SizeFactor);
11849 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
11851 // Insert the 128-bit vector.
11852 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
11855 if (OpVT == MVT::v1i64 &&
11856 Op.getOperand(0).getValueType() == MVT::i64)
11857 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
11859 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
11860 assert(OpVT.is128BitVector() && "Expected an SSE type!");
11861 return DAG.getBitcast(
11862 OpVT, DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, AnyExt));
11865 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
11866 // a simple subregister reference or explicit instructions to grab
11867 // upper bits of a vector.
11868 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
11869 SelectionDAG &DAG) {
11871 SDValue In = Op.getOperand(0);
11872 SDValue Idx = Op.getOperand(1);
11873 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11874 MVT ResVT = Op.getSimpleValueType();
11875 MVT InVT = In.getSimpleValueType();
11877 if (Subtarget->hasFp256()) {
11878 if (ResVT.is128BitVector() &&
11879 (InVT.is256BitVector() || InVT.is512BitVector()) &&
11880 isa<ConstantSDNode>(Idx)) {
11881 return Extract128BitVector(In, IdxVal, DAG, dl);
11883 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
11884 isa<ConstantSDNode>(Idx)) {
11885 return Extract256BitVector(In, IdxVal, DAG, dl);
11891 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
11892 // simple superregister reference or explicit instructions to insert
11893 // the upper bits of a vector.
11894 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
11895 SelectionDAG &DAG) {
11896 if (!Subtarget->hasAVX())
11900 SDValue Vec = Op.getOperand(0);
11901 SDValue SubVec = Op.getOperand(1);
11902 SDValue Idx = Op.getOperand(2);
11904 if (!isa<ConstantSDNode>(Idx))
11907 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11908 MVT OpVT = Op.getSimpleValueType();
11909 MVT SubVecVT = SubVec.getSimpleValueType();
11911 // Fold two 16-byte subvector loads into one 32-byte load:
11912 // (insert_subvector (insert_subvector undef, (load addr), 0),
11913 // (load addr + 16), Elts/2)
11915 if ((IdxVal == OpVT.getVectorNumElements() / 2) &&
11916 Vec.getOpcode() == ISD::INSERT_SUBVECTOR &&
11917 OpVT.is256BitVector() && SubVecVT.is128BitVector()) {
11918 auto *Idx2 = dyn_cast<ConstantSDNode>(Vec.getOperand(2));
11919 if (Idx2 && Idx2->getZExtValue() == 0) {
11920 SDValue SubVec2 = Vec.getOperand(1);
11921 // If needed, look through a bitcast to get to the load.
11922 if (SubVec2.getNode() && SubVec2.getOpcode() == ISD::BITCAST)
11923 SubVec2 = SubVec2.getOperand(0);
11925 if (auto *FirstLd = dyn_cast<LoadSDNode>(SubVec2)) {
11927 unsigned Alignment = FirstLd->getAlignment();
11928 unsigned AS = FirstLd->getAddressSpace();
11929 const X86TargetLowering *TLI = Subtarget->getTargetLowering();
11930 if (TLI->allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(),
11931 OpVT, AS, Alignment, &Fast) && Fast) {
11932 SDValue Ops[] = { SubVec2, SubVec };
11933 if (SDValue Ld = EltsFromConsecutiveLoads(OpVT, Ops, dl, DAG, false))
11940 if ((OpVT.is256BitVector() || OpVT.is512BitVector()) &&
11941 SubVecVT.is128BitVector())
11942 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
11944 if (OpVT.is512BitVector() && SubVecVT.is256BitVector())
11945 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
11947 if (OpVT.getVectorElementType() == MVT::i1)
11948 return Insert1BitVector(Op, DAG);
11953 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
11954 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
11955 // one of the above mentioned nodes. It has to be wrapped because otherwise
11956 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
11957 // be used to form addressing mode. These wrapped nodes will be selected
11960 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
11961 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
11963 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11964 // global base reg.
11965 unsigned char OpFlag = 0;
11966 unsigned WrapperKind = X86ISD::Wrapper;
11967 CodeModel::Model M = DAG.getTarget().getCodeModel();
11969 if (Subtarget->isPICStyleRIPRel() &&
11970 (M == CodeModel::Small || M == CodeModel::Kernel))
11971 WrapperKind = X86ISD::WrapperRIP;
11972 else if (Subtarget->isPICStyleGOT())
11973 OpFlag = X86II::MO_GOTOFF;
11974 else if (Subtarget->isPICStyleStubPIC())
11975 OpFlag = X86II::MO_PIC_BASE_OFFSET;
11977 auto PtrVT = getPointerTy(DAG.getDataLayout());
11978 SDValue Result = DAG.getTargetConstantPool(
11979 CP->getConstVal(), PtrVT, CP->getAlignment(), CP->getOffset(), OpFlag);
11981 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
11982 // With PIC, the address is actually $g + Offset.
11985 DAG.getNode(ISD::ADD, DL, PtrVT,
11986 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), Result);
11992 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
11993 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
11995 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11996 // global base reg.
11997 unsigned char OpFlag = 0;
11998 unsigned WrapperKind = X86ISD::Wrapper;
11999 CodeModel::Model M = DAG.getTarget().getCodeModel();
12001 if (Subtarget->isPICStyleRIPRel() &&
12002 (M == CodeModel::Small || M == CodeModel::Kernel))
12003 WrapperKind = X86ISD::WrapperRIP;
12004 else if (Subtarget->isPICStyleGOT())
12005 OpFlag = X86II::MO_GOTOFF;
12006 else if (Subtarget->isPICStyleStubPIC())
12007 OpFlag = X86II::MO_PIC_BASE_OFFSET;
12009 auto PtrVT = getPointerTy(DAG.getDataLayout());
12010 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, OpFlag);
12012 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
12014 // With PIC, the address is actually $g + Offset.
12017 DAG.getNode(ISD::ADD, DL, PtrVT,
12018 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), Result);
12024 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
12025 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
12027 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12028 // global base reg.
12029 unsigned char OpFlag = 0;
12030 unsigned WrapperKind = X86ISD::Wrapper;
12031 CodeModel::Model M = DAG.getTarget().getCodeModel();
12033 if (Subtarget->isPICStyleRIPRel() &&
12034 (M == CodeModel::Small || M == CodeModel::Kernel)) {
12035 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
12036 OpFlag = X86II::MO_GOTPCREL;
12037 WrapperKind = X86ISD::WrapperRIP;
12038 } else if (Subtarget->isPICStyleGOT()) {
12039 OpFlag = X86II::MO_GOT;
12040 } else if (Subtarget->isPICStyleStubPIC()) {
12041 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
12042 } else if (Subtarget->isPICStyleStubNoDynamic()) {
12043 OpFlag = X86II::MO_DARWIN_NONLAZY;
12046 auto PtrVT = getPointerTy(DAG.getDataLayout());
12047 SDValue Result = DAG.getTargetExternalSymbol(Sym, PtrVT, OpFlag);
12050 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
12052 // With PIC, the address is actually $g + Offset.
12053 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
12054 !Subtarget->is64Bit()) {
12056 DAG.getNode(ISD::ADD, DL, PtrVT,
12057 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), Result);
12060 // For symbols that require a load from a stub to get the address, emit the
12062 if (isGlobalStubReference(OpFlag))
12063 Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
12064 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
12065 false, false, false, 0);
12071 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
12072 // Create the TargetBlockAddressAddress node.
12073 unsigned char OpFlags =
12074 Subtarget->ClassifyBlockAddressReference();
12075 CodeModel::Model M = DAG.getTarget().getCodeModel();
12076 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
12077 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
12079 auto PtrVT = getPointerTy(DAG.getDataLayout());
12080 SDValue Result = DAG.getTargetBlockAddress(BA, PtrVT, Offset, OpFlags);
12082 if (Subtarget->isPICStyleRIPRel() &&
12083 (M == CodeModel::Small || M == CodeModel::Kernel))
12084 Result = DAG.getNode(X86ISD::WrapperRIP, dl, PtrVT, Result);
12086 Result = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, Result);
12088 // With PIC, the address is actually $g + Offset.
12089 if (isGlobalRelativeToPICBase(OpFlags)) {
12090 Result = DAG.getNode(ISD::ADD, dl, PtrVT,
12091 DAG.getNode(X86ISD::GlobalBaseReg, dl, PtrVT), Result);
12098 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
12099 int64_t Offset, SelectionDAG &DAG) const {
12100 // Create the TargetGlobalAddress node, folding in the constant
12101 // offset if it is legal.
12102 unsigned char OpFlags =
12103 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
12104 CodeModel::Model M = DAG.getTarget().getCodeModel();
12105 auto PtrVT = getPointerTy(DAG.getDataLayout());
12107 if (OpFlags == X86II::MO_NO_FLAG &&
12108 X86::isOffsetSuitableForCodeModel(Offset, M)) {
12109 // A direct static reference to a global.
12110 Result = DAG.getTargetGlobalAddress(GV, dl, PtrVT, Offset);
12113 Result = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, OpFlags);
12116 if (Subtarget->isPICStyleRIPRel() &&
12117 (M == CodeModel::Small || M == CodeModel::Kernel))
12118 Result = DAG.getNode(X86ISD::WrapperRIP, dl, PtrVT, Result);
12120 Result = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, Result);
12122 // With PIC, the address is actually $g + Offset.
12123 if (isGlobalRelativeToPICBase(OpFlags)) {
12124 Result = DAG.getNode(ISD::ADD, dl, PtrVT,
12125 DAG.getNode(X86ISD::GlobalBaseReg, dl, PtrVT), Result);
12128 // For globals that require a load from a stub to get the address, emit the
12130 if (isGlobalStubReference(OpFlags))
12131 Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
12132 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
12133 false, false, false, 0);
12135 // If there was a non-zero offset that we didn't fold, create an explicit
12136 // addition for it.
12138 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result,
12139 DAG.getConstant(Offset, dl, PtrVT));
12145 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
12146 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
12147 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
12148 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
12152 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
12153 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
12154 unsigned char OperandFlags, bool LocalDynamic = false) {
12155 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12156 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
12158 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12159 GA->getValueType(0),
12163 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
12167 SDValue Ops[] = { Chain, TGA, *InFlag };
12168 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
12170 SDValue Ops[] = { Chain, TGA };
12171 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
12174 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
12175 MFI->setAdjustsStack(true);
12176 MFI->setHasCalls(true);
12178 SDValue Flag = Chain.getValue(1);
12179 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
12182 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
12184 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12187 SDLoc dl(GA); // ? function entry point might be better
12188 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
12189 DAG.getNode(X86ISD::GlobalBaseReg,
12190 SDLoc(), PtrVT), InFlag);
12191 InFlag = Chain.getValue(1);
12193 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
12196 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
12198 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12200 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
12201 X86::RAX, X86II::MO_TLSGD);
12204 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
12210 // Get the start address of the TLS block for this module.
12211 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
12212 .getInfo<X86MachineFunctionInfo>();
12213 MFI->incNumLocalDynamicTLSAccesses();
12217 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
12218 X86II::MO_TLSLD, /*LocalDynamic=*/true);
12221 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
12222 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
12223 InFlag = Chain.getValue(1);
12224 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
12225 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
12228 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
12232 unsigned char OperandFlags = X86II::MO_DTPOFF;
12233 unsigned WrapperKind = X86ISD::Wrapper;
12234 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12235 GA->getValueType(0),
12236 GA->getOffset(), OperandFlags);
12237 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
12239 // Add x@dtpoff with the base.
12240 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
12243 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
12244 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12245 const EVT PtrVT, TLSModel::Model model,
12246 bool is64Bit, bool isPIC) {
12249 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
12250 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
12251 is64Bit ? 257 : 256));
12253 SDValue ThreadPointer =
12254 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0, dl),
12255 MachinePointerInfo(Ptr), false, false, false, 0);
12257 unsigned char OperandFlags = 0;
12258 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
12260 unsigned WrapperKind = X86ISD::Wrapper;
12261 if (model == TLSModel::LocalExec) {
12262 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
12263 } else if (model == TLSModel::InitialExec) {
12265 OperandFlags = X86II::MO_GOTTPOFF;
12266 WrapperKind = X86ISD::WrapperRIP;
12268 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
12271 llvm_unreachable("Unexpected model");
12274 // emit "addl x@ntpoff,%eax" (local exec)
12275 // or "addl x@indntpoff,%eax" (initial exec)
12276 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
12278 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
12279 GA->getOffset(), OperandFlags);
12280 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
12282 if (model == TLSModel::InitialExec) {
12283 if (isPIC && !is64Bit) {
12284 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
12285 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
12289 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
12290 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
12291 false, false, false, 0);
12294 // The address of the thread local variable is the add of the thread
12295 // pointer with the offset of the variable.
12296 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
12300 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
12302 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
12304 // Cygwin uses emutls.
12305 // FIXME: It may be EmulatedTLS-generic also for X86-Android.
12306 if (Subtarget->isTargetWindowsCygwin())
12307 return LowerToTLSEmulatedModel(GA, DAG);
12309 const GlobalValue *GV = GA->getGlobal();
12310 auto PtrVT = getPointerTy(DAG.getDataLayout());
12312 if (Subtarget->isTargetELF()) {
12313 if (DAG.getTarget().Options.EmulatedTLS)
12314 return LowerToTLSEmulatedModel(GA, DAG);
12315 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
12317 case TLSModel::GeneralDynamic:
12318 if (Subtarget->is64Bit())
12319 return LowerToTLSGeneralDynamicModel64(GA, DAG, PtrVT);
12320 return LowerToTLSGeneralDynamicModel32(GA, DAG, PtrVT);
12321 case TLSModel::LocalDynamic:
12322 return LowerToTLSLocalDynamicModel(GA, DAG, PtrVT,
12323 Subtarget->is64Bit());
12324 case TLSModel::InitialExec:
12325 case TLSModel::LocalExec:
12326 return LowerToTLSExecModel(GA, DAG, PtrVT, model, Subtarget->is64Bit(),
12327 DAG.getTarget().getRelocationModel() ==
12330 llvm_unreachable("Unknown TLS model.");
12333 if (Subtarget->isTargetDarwin()) {
12334 // Darwin only has one model of TLS. Lower to that.
12335 unsigned char OpFlag = 0;
12336 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
12337 X86ISD::WrapperRIP : X86ISD::Wrapper;
12339 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12340 // global base reg.
12341 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
12342 !Subtarget->is64Bit();
12344 OpFlag = X86II::MO_TLVP_PIC_BASE;
12346 OpFlag = X86II::MO_TLVP;
12348 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
12349 GA->getValueType(0),
12350 GA->getOffset(), OpFlag);
12351 SDValue Offset = DAG.getNode(WrapperKind, DL, PtrVT, Result);
12353 // With PIC32, the address is actually $g + Offset.
12355 Offset = DAG.getNode(ISD::ADD, DL, PtrVT,
12356 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
12359 // Lowering the machine isd will make sure everything is in the right
12361 SDValue Chain = DAG.getEntryNode();
12362 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
12363 SDValue Args[] = { Chain, Offset };
12364 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
12366 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
12367 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12368 MFI->setAdjustsStack(true);
12370 // And our return value (tls address) is in the standard call return value
12372 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
12373 return DAG.getCopyFromReg(Chain, DL, Reg, PtrVT, Chain.getValue(1));
12376 if (Subtarget->isTargetKnownWindowsMSVC() ||
12377 Subtarget->isTargetWindowsGNU()) {
12378 // Just use the implicit TLS architecture
12379 // Need to generate someting similar to:
12380 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
12382 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
12383 // mov rcx, qword [rdx+rcx*8]
12384 // mov eax, .tls$:tlsvar
12385 // [rax+rcx] contains the address
12386 // Windows 64bit: gs:0x58
12387 // Windows 32bit: fs:__tls_array
12390 SDValue Chain = DAG.getEntryNode();
12392 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
12393 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
12394 // use its literal value of 0x2C.
12395 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
12396 ? Type::getInt8PtrTy(*DAG.getContext(),
12398 : Type::getInt32PtrTy(*DAG.getContext(),
12401 SDValue TlsArray = Subtarget->is64Bit()
12402 ? DAG.getIntPtrConstant(0x58, dl)
12403 : (Subtarget->isTargetWindowsGNU()
12404 ? DAG.getIntPtrConstant(0x2C, dl)
12405 : DAG.getExternalSymbol("_tls_array", PtrVT));
12407 SDValue ThreadPointer =
12408 DAG.getLoad(PtrVT, dl, Chain, TlsArray, MachinePointerInfo(Ptr), false,
12412 if (GV->getThreadLocalMode() == GlobalVariable::LocalExecTLSModel) {
12413 res = ThreadPointer;
12415 // Load the _tls_index variable
12416 SDValue IDX = DAG.getExternalSymbol("_tls_index", PtrVT);
12417 if (Subtarget->is64Bit())
12418 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, PtrVT, Chain, IDX,
12419 MachinePointerInfo(), MVT::i32, false, false,
12422 IDX = DAG.getLoad(PtrVT, dl, Chain, IDX, MachinePointerInfo(), false,
12425 auto &DL = DAG.getDataLayout();
12427 DAG.getConstant(Log2_64_Ceil(DL.getPointerSize()), dl, PtrVT);
12428 IDX = DAG.getNode(ISD::SHL, dl, PtrVT, IDX, Scale);
12430 res = DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, IDX);
12433 res = DAG.getLoad(PtrVT, dl, Chain, res, MachinePointerInfo(), false, false,
12436 // Get the offset of start of .tls section
12437 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12438 GA->getValueType(0),
12439 GA->getOffset(), X86II::MO_SECREL);
12440 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, TGA);
12442 // The address of the thread local variable is the add of the thread
12443 // pointer with the offset of the variable.
12444 return DAG.getNode(ISD::ADD, dl, PtrVT, res, Offset);
12447 llvm_unreachable("TLS not implemented for this target.");
12450 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
12451 /// and take a 2 x i32 value to shift plus a shift amount.
12452 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
12453 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
12454 MVT VT = Op.getSimpleValueType();
12455 unsigned VTBits = VT.getSizeInBits();
12457 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
12458 SDValue ShOpLo = Op.getOperand(0);
12459 SDValue ShOpHi = Op.getOperand(1);
12460 SDValue ShAmt = Op.getOperand(2);
12461 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
12462 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
12464 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
12465 DAG.getConstant(VTBits - 1, dl, MVT::i8));
12466 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
12467 DAG.getConstant(VTBits - 1, dl, MVT::i8))
12468 : DAG.getConstant(0, dl, VT);
12470 SDValue Tmp2, Tmp3;
12471 if (Op.getOpcode() == ISD::SHL_PARTS) {
12472 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
12473 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
12475 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
12476 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
12479 // If the shift amount is larger or equal than the width of a part we can't
12480 // rely on the results of shld/shrd. Insert a test and select the appropriate
12481 // values for large shift amounts.
12482 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
12483 DAG.getConstant(VTBits, dl, MVT::i8));
12484 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
12485 AndNode, DAG.getConstant(0, dl, MVT::i8));
12488 SDValue CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
12489 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
12490 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
12492 if (Op.getOpcode() == ISD::SHL_PARTS) {
12493 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
12494 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
12496 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
12497 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
12500 SDValue Ops[2] = { Lo, Hi };
12501 return DAG.getMergeValues(Ops, dl);
12504 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
12505 SelectionDAG &DAG) const {
12506 SDValue Src = Op.getOperand(0);
12507 MVT SrcVT = Src.getSimpleValueType();
12508 MVT VT = Op.getSimpleValueType();
12511 if (SrcVT.isVector()) {
12512 if (SrcVT == MVT::v2i32 && VT == MVT::v2f64) {
12513 return DAG.getNode(X86ISD::CVTDQ2PD, dl, VT,
12514 DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4i32, Src,
12515 DAG.getUNDEF(SrcVT)));
12517 if (SrcVT.getVectorElementType() == MVT::i1) {
12518 MVT IntegerVT = MVT::getVectorVT(MVT::i32, SrcVT.getVectorNumElements());
12519 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
12520 DAG.getNode(ISD::SIGN_EXTEND, dl, IntegerVT, Src));
12525 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
12526 "Unknown SINT_TO_FP to lower!");
12528 // These are really Legal; return the operand so the caller accepts it as
12530 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
12532 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
12533 Subtarget->is64Bit()) {
12537 unsigned Size = SrcVT.getSizeInBits()/8;
12538 MachineFunction &MF = DAG.getMachineFunction();
12539 auto PtrVT = getPointerTy(MF.getDataLayout());
12540 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
12541 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12542 SDValue Chain = DAG.getStore(
12543 DAG.getEntryNode(), dl, Op.getOperand(0), StackSlot,
12544 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI), false,
12546 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
12549 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
12551 SelectionDAG &DAG) const {
12555 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
12557 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
12559 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
12561 unsigned ByteSize = SrcVT.getSizeInBits()/8;
12563 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
12564 MachineMemOperand *MMO;
12566 int SSFI = FI->getIndex();
12567 MMO = DAG.getMachineFunction().getMachineMemOperand(
12568 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12569 MachineMemOperand::MOLoad, ByteSize, ByteSize);
12571 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
12572 StackSlot = StackSlot.getOperand(1);
12574 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
12575 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
12577 Tys, Ops, SrcVT, MMO);
12580 Chain = Result.getValue(1);
12581 SDValue InFlag = Result.getValue(2);
12583 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
12584 // shouldn't be necessary except that RFP cannot be live across
12585 // multiple blocks. When stackifier is fixed, they can be uncoupled.
12586 MachineFunction &MF = DAG.getMachineFunction();
12587 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
12588 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
12589 auto PtrVT = getPointerTy(MF.getDataLayout());
12590 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12591 Tys = DAG.getVTList(MVT::Other);
12593 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
12595 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
12596 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12597 MachineMemOperand::MOStore, SSFISize, SSFISize);
12599 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
12600 Ops, Op.getValueType(), MMO);
12601 Result = DAG.getLoad(
12602 Op.getValueType(), DL, Chain, StackSlot,
12603 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12604 false, false, false, 0);
12610 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
12611 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
12612 SelectionDAG &DAG) const {
12613 // This algorithm is not obvious. Here it is what we're trying to output:
12616 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
12617 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
12619 haddpd %xmm0, %xmm0
12621 pshufd $0x4e, %xmm0, %xmm1
12627 LLVMContext *Context = DAG.getContext();
12629 // Build some magic constants.
12630 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
12631 Constant *C0 = ConstantDataVector::get(*Context, CV0);
12632 auto PtrVT = getPointerTy(DAG.getDataLayout());
12633 SDValue CPIdx0 = DAG.getConstantPool(C0, PtrVT, 16);
12635 SmallVector<Constant*,2> CV1;
12637 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
12638 APInt(64, 0x4330000000000000ULL))));
12640 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
12641 APInt(64, 0x4530000000000000ULL))));
12642 Constant *C1 = ConstantVector::get(CV1);
12643 SDValue CPIdx1 = DAG.getConstantPool(C1, PtrVT, 16);
12645 // Load the 64-bit value into an XMM register.
12646 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
12649 DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
12650 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
12651 false, false, false, 16);
12653 getUnpackl(DAG, dl, MVT::v4i32, DAG.getBitcast(MVT::v4i32, XR1), CLod0);
12656 DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
12657 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
12658 false, false, false, 16);
12659 SDValue XR2F = DAG.getBitcast(MVT::v2f64, Unpck1);
12660 // TODO: Are there any fast-math-flags to propagate here?
12661 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
12664 if (Subtarget->hasSSE3()) {
12665 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
12666 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
12668 SDValue S2F = DAG.getBitcast(MVT::v4i32, Sub);
12669 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
12671 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
12672 DAG.getBitcast(MVT::v2f64, Shuffle), Sub);
12675 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
12676 DAG.getIntPtrConstant(0, dl));
12679 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
12680 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
12681 SelectionDAG &DAG) const {
12683 // FP constant to bias correct the final result.
12684 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), dl,
12687 // Load the 32-bit value into an XMM register.
12688 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
12691 // Zero out the upper parts of the register.
12692 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
12694 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
12695 DAG.getBitcast(MVT::v2f64, Load),
12696 DAG.getIntPtrConstant(0, dl));
12698 // Or the load with the bias.
12699 SDValue Or = DAG.getNode(
12700 ISD::OR, dl, MVT::v2i64,
12701 DAG.getBitcast(MVT::v2i64,
12702 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, Load)),
12703 DAG.getBitcast(MVT::v2i64,
12704 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, Bias)));
12706 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
12707 DAG.getBitcast(MVT::v2f64, Or), DAG.getIntPtrConstant(0, dl));
12709 // Subtract the bias.
12710 // TODO: Are there any fast-math-flags to propagate here?
12711 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
12713 // Handle final rounding.
12714 MVT DestVT = Op.getSimpleValueType();
12716 if (DestVT.bitsLT(MVT::f64))
12717 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
12718 DAG.getIntPtrConstant(0, dl));
12719 if (DestVT.bitsGT(MVT::f64))
12720 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
12722 // Handle final rounding.
12726 static SDValue lowerUINT_TO_FP_vXi32(SDValue Op, SelectionDAG &DAG,
12727 const X86Subtarget &Subtarget) {
12728 // The algorithm is the following:
12729 // #ifdef __SSE4_1__
12730 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
12731 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
12732 // (uint4) 0x53000000, 0xaa);
12734 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
12735 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
12737 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
12738 // return (float4) lo + fhi;
12740 // We shouldn't use it when unsafe-fp-math is enabled though: we might later
12741 // reassociate the two FADDs, and if we do that, the algorithm fails
12742 // spectacularly (PR24512).
12743 // FIXME: If we ever have some kind of Machine FMF, this should be marked
12744 // as non-fast and always be enabled. Why isn't SDAG FMF enough? Because
12745 // there's also the MachineCombiner reassociations happening on Machine IR.
12746 if (DAG.getTarget().Options.UnsafeFPMath)
12750 SDValue V = Op->getOperand(0);
12751 MVT VecIntVT = V.getSimpleValueType();
12752 bool Is128 = VecIntVT == MVT::v4i32;
12753 MVT VecFloatVT = Is128 ? MVT::v4f32 : MVT::v8f32;
12754 // If we convert to something else than the supported type, e.g., to v4f64,
12756 if (VecFloatVT != Op->getSimpleValueType(0))
12759 unsigned NumElts = VecIntVT.getVectorNumElements();
12760 assert((VecIntVT == MVT::v4i32 || VecIntVT == MVT::v8i32) &&
12761 "Unsupported custom type");
12762 assert(NumElts <= 8 && "The size of the constant array must be fixed");
12764 // In the #idef/#else code, we have in common:
12765 // - The vector of constants:
12771 // Create the splat vector for 0x4b000000.
12772 SDValue CstLow = DAG.getConstant(0x4b000000, DL, MVT::i32);
12773 SDValue CstLowArray[] = {CstLow, CstLow, CstLow, CstLow,
12774 CstLow, CstLow, CstLow, CstLow};
12775 SDValue VecCstLow = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12776 makeArrayRef(&CstLowArray[0], NumElts));
12777 // Create the splat vector for 0x53000000.
12778 SDValue CstHigh = DAG.getConstant(0x53000000, DL, MVT::i32);
12779 SDValue CstHighArray[] = {CstHigh, CstHigh, CstHigh, CstHigh,
12780 CstHigh, CstHigh, CstHigh, CstHigh};
12781 SDValue VecCstHigh = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12782 makeArrayRef(&CstHighArray[0], NumElts));
12784 // Create the right shift.
12785 SDValue CstShift = DAG.getConstant(16, DL, MVT::i32);
12786 SDValue CstShiftArray[] = {CstShift, CstShift, CstShift, CstShift,
12787 CstShift, CstShift, CstShift, CstShift};
12788 SDValue VecCstShift = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12789 makeArrayRef(&CstShiftArray[0], NumElts));
12790 SDValue HighShift = DAG.getNode(ISD::SRL, DL, VecIntVT, V, VecCstShift);
12793 if (Subtarget.hasSSE41()) {
12794 MVT VecI16VT = Is128 ? MVT::v8i16 : MVT::v16i16;
12795 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
12796 SDValue VecCstLowBitcast = DAG.getBitcast(VecI16VT, VecCstLow);
12797 SDValue VecBitcast = DAG.getBitcast(VecI16VT, V);
12798 // Low will be bitcasted right away, so do not bother bitcasting back to its
12800 Low = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecBitcast,
12801 VecCstLowBitcast, DAG.getConstant(0xaa, DL, MVT::i32));
12802 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
12803 // (uint4) 0x53000000, 0xaa);
12804 SDValue VecCstHighBitcast = DAG.getBitcast(VecI16VT, VecCstHigh);
12805 SDValue VecShiftBitcast = DAG.getBitcast(VecI16VT, HighShift);
12806 // High will be bitcasted right away, so do not bother bitcasting back to
12807 // its original type.
12808 High = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecShiftBitcast,
12809 VecCstHighBitcast, DAG.getConstant(0xaa, DL, MVT::i32));
12811 SDValue CstMask = DAG.getConstant(0xffff, DL, MVT::i32);
12812 SDValue VecCstMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT, CstMask,
12813 CstMask, CstMask, CstMask);
12814 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
12815 SDValue LowAnd = DAG.getNode(ISD::AND, DL, VecIntVT, V, VecCstMask);
12816 Low = DAG.getNode(ISD::OR, DL, VecIntVT, LowAnd, VecCstLow);
12818 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
12819 High = DAG.getNode(ISD::OR, DL, VecIntVT, HighShift, VecCstHigh);
12822 // Create the vector constant for -(0x1.0p39f + 0x1.0p23f).
12823 SDValue CstFAdd = DAG.getConstantFP(
12824 APFloat(APFloat::IEEEsingle, APInt(32, 0xD3000080)), DL, MVT::f32);
12825 SDValue CstFAddArray[] = {CstFAdd, CstFAdd, CstFAdd, CstFAdd,
12826 CstFAdd, CstFAdd, CstFAdd, CstFAdd};
12827 SDValue VecCstFAdd = DAG.getNode(ISD::BUILD_VECTOR, DL, VecFloatVT,
12828 makeArrayRef(&CstFAddArray[0], NumElts));
12830 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
12831 SDValue HighBitcast = DAG.getBitcast(VecFloatVT, High);
12832 // TODO: Are there any fast-math-flags to propagate here?
12834 DAG.getNode(ISD::FADD, DL, VecFloatVT, HighBitcast, VecCstFAdd);
12835 // return (float4) lo + fhi;
12836 SDValue LowBitcast = DAG.getBitcast(VecFloatVT, Low);
12837 return DAG.getNode(ISD::FADD, DL, VecFloatVT, LowBitcast, FHigh);
12840 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
12841 SelectionDAG &DAG) const {
12842 SDValue N0 = Op.getOperand(0);
12843 MVT SVT = N0.getSimpleValueType();
12846 switch (SVT.SimpleTy) {
12848 llvm_unreachable("Custom UINT_TO_FP is not supported!");
12853 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
12854 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
12855 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
12859 return lowerUINT_TO_FP_vXi32(Op, DAG, *Subtarget);
12862 assert(Subtarget->hasAVX512());
12863 return DAG.getNode(ISD::UINT_TO_FP, dl, Op.getValueType(),
12864 DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v16i32, N0));
12868 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
12869 SelectionDAG &DAG) const {
12870 SDValue N0 = Op.getOperand(0);
12872 auto PtrVT = getPointerTy(DAG.getDataLayout());
12874 if (Op.getSimpleValueType().isVector())
12875 return lowerUINT_TO_FP_vec(Op, DAG);
12877 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
12878 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
12879 // the optimization here.
12880 if (DAG.SignBitIsZero(N0))
12881 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
12883 MVT SrcVT = N0.getSimpleValueType();
12884 MVT DstVT = Op.getSimpleValueType();
12886 if (Subtarget->hasAVX512() && isScalarFPTypeInSSEReg(DstVT) &&
12887 (SrcVT == MVT::i32 || (SrcVT == MVT::i64 && Subtarget->is64Bit()))) {
12888 // Conversions from unsigned i32 to f32/f64 are legal,
12889 // using VCVTUSI2SS/SD. Same for i64 in 64-bit mode.
12893 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
12894 return LowerUINT_TO_FP_i64(Op, DAG);
12895 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
12896 return LowerUINT_TO_FP_i32(Op, DAG);
12897 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
12900 // Make a 64-bit buffer, and use it to build an FILD.
12901 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
12902 if (SrcVT == MVT::i32) {
12903 SDValue WordOff = DAG.getConstant(4, dl, PtrVT);
12904 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, WordOff);
12905 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12906 StackSlot, MachinePointerInfo(),
12908 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, dl, MVT::i32),
12909 OffsetSlot, MachinePointerInfo(),
12911 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
12915 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
12916 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12917 StackSlot, MachinePointerInfo(),
12919 // For i64 source, we need to add the appropriate power of 2 if the input
12920 // was negative. This is the same as the optimization in
12921 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
12922 // we must be careful to do the computation in x87 extended precision, not
12923 // in SSE. (The generic code can't know it's OK to do this, or how to.)
12924 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
12925 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
12926 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12927 MachineMemOperand::MOLoad, 8, 8);
12929 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
12930 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
12931 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
12934 APInt FF(32, 0x5F800000ULL);
12936 // Check whether the sign bit is set.
12937 SDValue SignSet = DAG.getSetCC(
12938 dl, getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::i64),
12939 Op.getOperand(0), DAG.getConstant(0, dl, MVT::i64), ISD::SETLT);
12941 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
12942 SDValue FudgePtr = DAG.getConstantPool(
12943 ConstantInt::get(*DAG.getContext(), FF.zext(64)), PtrVT);
12945 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
12946 SDValue Zero = DAG.getIntPtrConstant(0, dl);
12947 SDValue Four = DAG.getIntPtrConstant(4, dl);
12948 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
12950 FudgePtr = DAG.getNode(ISD::ADD, dl, PtrVT, FudgePtr, Offset);
12952 // Load the value out, extending it from f32 to f80.
12953 // FIXME: Avoid the extend by constructing the right constant pool?
12954 SDValue Fudge = DAG.getExtLoad(
12955 ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(), FudgePtr,
12956 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), MVT::f32,
12957 false, false, false, 4);
12958 // Extend everything to 80 bits to force it to be done on x87.
12959 // TODO: Are there any fast-math-flags to propagate here?
12960 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
12961 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add,
12962 DAG.getIntPtrConstant(0, dl));
12965 // If the given FP_TO_SINT (IsSigned) or FP_TO_UINT (!IsSigned) operation
12966 // is legal, or has an fp128 or f16 source (which needs to be promoted to f32),
12967 // just return an <SDValue(), SDValue()> pair.
12968 // Otherwise it is assumed to be a conversion from one of f32, f64 or f80
12969 // to i16, i32 or i64, and we lower it to a legal sequence.
12970 // If lowered to the final integer result we return a <result, SDValue()> pair.
12971 // Otherwise we lower it to a sequence ending with a FIST, return a
12972 // <FIST, StackSlot> pair, and the caller is responsible for loading
12973 // the final integer result from StackSlot.
12974 std::pair<SDValue,SDValue>
12975 X86TargetLowering::FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
12976 bool IsSigned, bool IsReplace) const {
12979 EVT DstTy = Op.getValueType();
12980 EVT TheVT = Op.getOperand(0).getValueType();
12981 auto PtrVT = getPointerTy(DAG.getDataLayout());
12983 if (TheVT != MVT::f32 && TheVT != MVT::f64 && TheVT != MVT::f80) {
12984 // f16 must be promoted before using the lowering in this routine.
12985 // fp128 does not use this lowering.
12986 return std::make_pair(SDValue(), SDValue());
12989 // If using FIST to compute an unsigned i64, we'll need some fixup
12990 // to handle values above the maximum signed i64. A FIST is always
12991 // used for the 32-bit subtarget, but also for f80 on a 64-bit target.
12992 bool UnsignedFixup = !IsSigned &&
12993 DstTy == MVT::i64 &&
12994 (!Subtarget->is64Bit() ||
12995 !isScalarFPTypeInSSEReg(TheVT));
12997 if (!IsSigned && DstTy != MVT::i64 && !Subtarget->hasAVX512()) {
12998 // Replace the fp-to-uint32 operation with an fp-to-sint64 FIST.
12999 // The low 32 bits of the fist result will have the correct uint32 result.
13000 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
13004 assert(DstTy.getSimpleVT() <= MVT::i64 &&
13005 DstTy.getSimpleVT() >= MVT::i16 &&
13006 "Unknown FP_TO_INT to lower!");
13008 // These are really Legal.
13009 if (DstTy == MVT::i32 &&
13010 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
13011 return std::make_pair(SDValue(), SDValue());
13012 if (Subtarget->is64Bit() &&
13013 DstTy == MVT::i64 &&
13014 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
13015 return std::make_pair(SDValue(), SDValue());
13017 // We lower FP->int64 into FISTP64 followed by a load from a temporary
13019 MachineFunction &MF = DAG.getMachineFunction();
13020 unsigned MemSize = DstTy.getSizeInBits()/8;
13021 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
13022 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
13025 switch (DstTy.getSimpleVT().SimpleTy) {
13026 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
13027 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
13028 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
13029 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
13032 SDValue Chain = DAG.getEntryNode();
13033 SDValue Value = Op.getOperand(0);
13034 SDValue Adjust; // 0x0 or 0x80000000, for result sign bit adjustment.
13036 if (UnsignedFixup) {
13038 // Conversion to unsigned i64 is implemented with a select,
13039 // depending on whether the source value fits in the range
13040 // of a signed i64. Let Thresh be the FP equivalent of
13041 // 0x8000000000000000ULL.
13043 // Adjust i32 = (Value < Thresh) ? 0 : 0x80000000;
13044 // FistSrc = (Value < Thresh) ? Value : (Value - Thresh);
13045 // Fist-to-mem64 FistSrc
13046 // Add 0 or 0x800...0ULL to the 64-bit result, which is equivalent
13047 // to XOR'ing the high 32 bits with Adjust.
13049 // Being a power of 2, Thresh is exactly representable in all FP formats.
13050 // For X87 we'd like to use the smallest FP type for this constant, but
13051 // for DAG type consistency we have to match the FP operand type.
13053 APFloat Thresh(APFloat::IEEEsingle, APInt(32, 0x5f000000));
13054 LLVM_ATTRIBUTE_UNUSED APFloat::opStatus Status = APFloat::opOK;
13055 bool LosesInfo = false;
13056 if (TheVT == MVT::f64)
13057 // The rounding mode is irrelevant as the conversion should be exact.
13058 Status = Thresh.convert(APFloat::IEEEdouble, APFloat::rmNearestTiesToEven,
13060 else if (TheVT == MVT::f80)
13061 Status = Thresh.convert(APFloat::x87DoubleExtended,
13062 APFloat::rmNearestTiesToEven, &LosesInfo);
13064 assert(Status == APFloat::opOK && !LosesInfo &&
13065 "FP conversion should have been exact");
13067 SDValue ThreshVal = DAG.getConstantFP(Thresh, DL, TheVT);
13069 SDValue Cmp = DAG.getSetCC(DL,
13070 getSetCCResultType(DAG.getDataLayout(),
13071 *DAG.getContext(), TheVT),
13072 Value, ThreshVal, ISD::SETLT);
13073 Adjust = DAG.getSelect(DL, MVT::i32, Cmp,
13074 DAG.getConstant(0, DL, MVT::i32),
13075 DAG.getConstant(0x80000000, DL, MVT::i32));
13076 SDValue Sub = DAG.getNode(ISD::FSUB, DL, TheVT, Value, ThreshVal);
13077 Cmp = DAG.getSetCC(DL, getSetCCResultType(DAG.getDataLayout(),
13078 *DAG.getContext(), TheVT),
13079 Value, ThreshVal, ISD::SETLT);
13080 Value = DAG.getSelect(DL, TheVT, Cmp, Value, Sub);
13083 // FIXME This causes a redundant load/store if the SSE-class value is already
13084 // in memory, such as if it is on the callstack.
13085 if (isScalarFPTypeInSSEReg(TheVT)) {
13086 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
13087 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
13088 MachinePointerInfo::getFixedStack(MF, SSFI), false,
13090 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
13092 Chain, StackSlot, DAG.getValueType(TheVT)
13095 MachineMemOperand *MMO =
13096 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, SSFI),
13097 MachineMemOperand::MOLoad, MemSize, MemSize);
13098 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
13099 Chain = Value.getValue(1);
13100 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
13101 StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
13104 MachineMemOperand *MMO =
13105 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, SSFI),
13106 MachineMemOperand::MOStore, MemSize, MemSize);
13108 if (UnsignedFixup) {
13110 // Insert the FIST, load its result as two i32's,
13111 // and XOR the high i32 with Adjust.
13113 SDValue FistOps[] = { Chain, Value, StackSlot };
13114 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
13115 FistOps, DstTy, MMO);
13117 SDValue Low32 = DAG.getLoad(MVT::i32, DL, FIST, StackSlot,
13118 MachinePointerInfo(),
13119 false, false, false, 0);
13120 SDValue HighAddr = DAG.getNode(ISD::ADD, DL, PtrVT, StackSlot,
13121 DAG.getConstant(4, DL, PtrVT));
13123 SDValue High32 = DAG.getLoad(MVT::i32, DL, FIST, HighAddr,
13124 MachinePointerInfo(),
13125 false, false, false, 0);
13126 High32 = DAG.getNode(ISD::XOR, DL, MVT::i32, High32, Adjust);
13128 if (Subtarget->is64Bit()) {
13129 // Join High32 and Low32 into a 64-bit result.
13130 // (High32 << 32) | Low32
13131 Low32 = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, Low32);
13132 High32 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, High32);
13133 High32 = DAG.getNode(ISD::SHL, DL, MVT::i64, High32,
13134 DAG.getConstant(32, DL, MVT::i8));
13135 SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i64, High32, Low32);
13136 return std::make_pair(Result, SDValue());
13139 SDValue ResultOps[] = { Low32, High32 };
13141 SDValue pair = IsReplace
13142 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, ResultOps)
13143 : DAG.getMergeValues(ResultOps, DL);
13144 return std::make_pair(pair, SDValue());
13146 // Build the FP_TO_INT*_IN_MEM
13147 SDValue Ops[] = { Chain, Value, StackSlot };
13148 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
13150 return std::make_pair(FIST, StackSlot);
13154 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
13155 const X86Subtarget *Subtarget) {
13156 MVT VT = Op->getSimpleValueType(0);
13157 SDValue In = Op->getOperand(0);
13158 MVT InVT = In.getSimpleValueType();
13161 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
13162 return DAG.getNode(ISD::ZERO_EXTEND, dl, VT, In);
13164 // Optimize vectors in AVX mode:
13167 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
13168 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
13169 // Concat upper and lower parts.
13172 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
13173 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
13174 // Concat upper and lower parts.
13177 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
13178 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
13179 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
13182 if (Subtarget->hasInt256())
13183 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
13185 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
13186 SDValue Undef = DAG.getUNDEF(InVT);
13187 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
13188 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
13189 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
13191 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
13192 VT.getVectorNumElements()/2);
13194 OpLo = DAG.getBitcast(HVT, OpLo);
13195 OpHi = DAG.getBitcast(HVT, OpHi);
13197 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
13200 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
13201 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
13202 MVT VT = Op->getSimpleValueType(0);
13203 SDValue In = Op->getOperand(0);
13204 MVT InVT = In.getSimpleValueType();
13206 unsigned int NumElts = VT.getVectorNumElements();
13207 if (NumElts != 8 && NumElts != 16 && !Subtarget->hasBWI())
13210 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
13211 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
13213 assert(InVT.getVectorElementType() == MVT::i1);
13214 MVT ExtVT = NumElts == 8 ? MVT::v8i64 : MVT::v16i32;
13216 DAG.getConstant(APInt(ExtVT.getScalarSizeInBits(), 1), DL, ExtVT);
13218 DAG.getConstant(APInt::getNullValue(ExtVT.getScalarSizeInBits()), DL, ExtVT);
13220 SDValue V = DAG.getNode(ISD::VSELECT, DL, ExtVT, In, One, Zero);
13221 if (VT.is512BitVector())
13223 return DAG.getNode(X86ISD::VTRUNC, DL, VT, V);
13226 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13227 SelectionDAG &DAG) {
13228 if (Subtarget->hasFp256())
13229 if (SDValue Res = LowerAVXExtend(Op, DAG, Subtarget))
13235 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13236 SelectionDAG &DAG) {
13238 MVT VT = Op.getSimpleValueType();
13239 SDValue In = Op.getOperand(0);
13240 MVT SVT = In.getSimpleValueType();
13242 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
13243 return LowerZERO_EXTEND_AVX512(Op, Subtarget, DAG);
13245 if (Subtarget->hasFp256())
13246 if (SDValue Res = LowerAVXExtend(Op, DAG, Subtarget))
13249 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
13250 VT.getVectorNumElements() != SVT.getVectorNumElements());
13254 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
13256 MVT VT = Op.getSimpleValueType();
13257 SDValue In = Op.getOperand(0);
13258 MVT InVT = In.getSimpleValueType();
13260 if (VT == MVT::i1) {
13261 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
13262 "Invalid scalar TRUNCATE operation");
13263 if (InVT.getSizeInBits() >= 32)
13265 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
13266 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
13268 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
13269 "Invalid TRUNCATE operation");
13271 // move vector to mask - truncate solution for SKX
13272 if (VT.getVectorElementType() == MVT::i1) {
13273 if (InVT.is512BitVector() && InVT.getScalarSizeInBits() <= 16 &&
13274 Subtarget->hasBWI())
13275 return Op; // legal, will go to VPMOVB2M, VPMOVW2M
13276 if ((InVT.is256BitVector() || InVT.is128BitVector())
13277 && InVT.getScalarSizeInBits() <= 16 &&
13278 Subtarget->hasBWI() && Subtarget->hasVLX())
13279 return Op; // legal, will go to VPMOVB2M, VPMOVW2M
13280 if (InVT.is512BitVector() && InVT.getScalarSizeInBits() >= 32 &&
13281 Subtarget->hasDQI())
13282 return Op; // legal, will go to VPMOVD2M, VPMOVQ2M
13283 if ((InVT.is256BitVector() || InVT.is128BitVector())
13284 && InVT.getScalarSizeInBits() >= 32 &&
13285 Subtarget->hasDQI() && Subtarget->hasVLX())
13286 return Op; // legal, will go to VPMOVB2M, VPMOVQ2M
13289 if (VT.getVectorElementType() == MVT::i1) {
13290 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
13291 unsigned NumElts = InVT.getVectorNumElements();
13292 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
13293 if (InVT.getSizeInBits() < 512) {
13294 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
13295 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
13300 DAG.getConstant(APInt::getSignBit(InVT.getScalarSizeInBits()), DL, InVT);
13301 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
13302 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
13305 // vpmovqb/w/d, vpmovdb/w, vpmovwb
13306 if (Subtarget->hasAVX512()) {
13307 // word to byte only under BWI
13308 if (InVT == MVT::v16i16 && !Subtarget->hasBWI()) // v16i16 -> v16i8
13309 return DAG.getNode(X86ISD::VTRUNC, DL, VT,
13310 DAG.getNode(X86ISD::VSEXT, DL, MVT::v16i32, In));
13311 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
13313 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
13314 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
13315 if (Subtarget->hasInt256()) {
13316 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
13317 In = DAG.getBitcast(MVT::v8i32, In);
13318 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
13320 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
13321 DAG.getIntPtrConstant(0, DL));
13324 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13325 DAG.getIntPtrConstant(0, DL));
13326 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13327 DAG.getIntPtrConstant(2, DL));
13328 OpLo = DAG.getBitcast(MVT::v4i32, OpLo);
13329 OpHi = DAG.getBitcast(MVT::v4i32, OpHi);
13330 static const int ShufMask[] = {0, 2, 4, 6};
13331 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
13334 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
13335 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
13336 if (Subtarget->hasInt256()) {
13337 In = DAG.getBitcast(MVT::v32i8, In);
13339 SmallVector<SDValue,32> pshufbMask;
13340 for (unsigned i = 0; i < 2; ++i) {
13341 pshufbMask.push_back(DAG.getConstant(0x0, DL, MVT::i8));
13342 pshufbMask.push_back(DAG.getConstant(0x1, DL, MVT::i8));
13343 pshufbMask.push_back(DAG.getConstant(0x4, DL, MVT::i8));
13344 pshufbMask.push_back(DAG.getConstant(0x5, DL, MVT::i8));
13345 pshufbMask.push_back(DAG.getConstant(0x8, DL, MVT::i8));
13346 pshufbMask.push_back(DAG.getConstant(0x9, DL, MVT::i8));
13347 pshufbMask.push_back(DAG.getConstant(0xc, DL, MVT::i8));
13348 pshufbMask.push_back(DAG.getConstant(0xd, DL, MVT::i8));
13349 for (unsigned j = 0; j < 8; ++j)
13350 pshufbMask.push_back(DAG.getConstant(0x80, DL, MVT::i8));
13352 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
13353 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
13354 In = DAG.getBitcast(MVT::v4i64, In);
13356 static const int ShufMask[] = {0, 2, -1, -1};
13357 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
13359 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13360 DAG.getIntPtrConstant(0, DL));
13361 return DAG.getBitcast(VT, In);
13364 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
13365 DAG.getIntPtrConstant(0, DL));
13367 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
13368 DAG.getIntPtrConstant(4, DL));
13370 OpLo = DAG.getBitcast(MVT::v16i8, OpLo);
13371 OpHi = DAG.getBitcast(MVT::v16i8, OpHi);
13373 // The PSHUFB mask:
13374 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
13375 -1, -1, -1, -1, -1, -1, -1, -1};
13377 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
13378 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
13379 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
13381 OpLo = DAG.getBitcast(MVT::v4i32, OpLo);
13382 OpHi = DAG.getBitcast(MVT::v4i32, OpHi);
13384 // The MOVLHPS Mask:
13385 static const int ShufMask2[] = {0, 1, 4, 5};
13386 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
13387 return DAG.getBitcast(MVT::v8i16, res);
13390 // Handle truncation of V256 to V128 using shuffles.
13391 if (!VT.is128BitVector() || !InVT.is256BitVector())
13394 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
13396 unsigned NumElems = VT.getVectorNumElements();
13397 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
13399 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
13400 // Prepare truncation shuffle mask
13401 for (unsigned i = 0; i != NumElems; ++i)
13402 MaskVec[i] = i * 2;
13403 SDValue V = DAG.getVectorShuffle(NVT, DL, DAG.getBitcast(NVT, In),
13404 DAG.getUNDEF(NVT), &MaskVec[0]);
13405 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
13406 DAG.getIntPtrConstant(0, DL));
13409 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
13410 SelectionDAG &DAG) const {
13411 assert(!Op.getSimpleValueType().isVector());
13413 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13414 /*IsSigned=*/ true, /*IsReplace=*/ false);
13415 SDValue FIST = Vals.first, StackSlot = Vals.second;
13416 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
13417 if (!FIST.getNode())
13420 if (StackSlot.getNode())
13421 // Load the result.
13422 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13423 FIST, StackSlot, MachinePointerInfo(),
13424 false, false, false, 0);
13426 // The node is the result.
13430 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
13431 SelectionDAG &DAG) const {
13432 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13433 /*IsSigned=*/ false, /*IsReplace=*/ false);
13434 SDValue FIST = Vals.first, StackSlot = Vals.second;
13435 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
13436 if (!FIST.getNode())
13439 if (StackSlot.getNode())
13440 // Load the result.
13441 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13442 FIST, StackSlot, MachinePointerInfo(),
13443 false, false, false, 0);
13445 // The node is the result.
13449 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
13451 MVT VT = Op.getSimpleValueType();
13452 SDValue In = Op.getOperand(0);
13453 MVT SVT = In.getSimpleValueType();
13455 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
13457 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
13458 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
13459 In, DAG.getUNDEF(SVT)));
13462 /// The only differences between FABS and FNEG are the mask and the logic op.
13463 /// FNEG also has a folding opportunity for FNEG(FABS(x)).
13464 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
13465 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
13466 "Wrong opcode for lowering FABS or FNEG.");
13468 bool IsFABS = (Op.getOpcode() == ISD::FABS);
13470 // If this is a FABS and it has an FNEG user, bail out to fold the combination
13471 // into an FNABS. We'll lower the FABS after that if it is still in use.
13473 for (SDNode *User : Op->uses())
13474 if (User->getOpcode() == ISD::FNEG)
13478 MVT VT = Op.getSimpleValueType();
13480 bool IsF128 = (VT == MVT::f128);
13482 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
13483 // decide if we should generate a 16-byte constant mask when we only need 4 or
13484 // 8 bytes for the scalar case.
13490 if (VT.isVector()) {
13492 EltVT = VT.getVectorElementType();
13493 NumElts = VT.getVectorNumElements();
13494 } else if (IsF128) {
13495 // SSE instructions are used for optimized f128 logical operations.
13496 LogicVT = MVT::f128;
13500 // There are no scalar bitwise logical SSE/AVX instructions, so we
13501 // generate a 16-byte vector constant and logic op even for the scalar case.
13502 // Using a 16-byte mask allows folding the load of the mask with
13503 // the logic op, so it can save (~4 bytes) on code size.
13504 LogicVT = (VT == MVT::f64) ? MVT::v2f64 : MVT::v4f32;
13506 NumElts = (VT == MVT::f64) ? 2 : 4;
13509 unsigned EltBits = EltVT.getSizeInBits();
13510 LLVMContext *Context = DAG.getContext();
13511 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
13513 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
13514 Constant *C = ConstantInt::get(*Context, MaskElt);
13515 C = ConstantVector::getSplat(NumElts, C);
13516 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13517 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(DAG.getDataLayout()));
13518 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
13520 DAG.getLoad(LogicVT, dl, DAG.getEntryNode(), CPIdx,
13521 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
13522 false, false, false, Alignment);
13524 SDValue Op0 = Op.getOperand(0);
13525 bool IsFNABS = !IsFABS && (Op0.getOpcode() == ISD::FABS);
13527 IsFABS ? X86ISD::FAND : IsFNABS ? X86ISD::FOR : X86ISD::FXOR;
13528 SDValue Operand = IsFNABS ? Op0.getOperand(0) : Op0;
13530 if (VT.isVector() || IsF128)
13531 return DAG.getNode(LogicOp, dl, LogicVT, Operand, Mask);
13533 // For the scalar case extend to a 128-bit vector, perform the logic op,
13534 // and extract the scalar result back out.
13535 Operand = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Operand);
13536 SDValue LogicNode = DAG.getNode(LogicOp, dl, LogicVT, Operand, Mask);
13537 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, LogicNode,
13538 DAG.getIntPtrConstant(0, dl));
13541 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
13542 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13543 LLVMContext *Context = DAG.getContext();
13544 SDValue Op0 = Op.getOperand(0);
13545 SDValue Op1 = Op.getOperand(1);
13547 MVT VT = Op.getSimpleValueType();
13548 MVT SrcVT = Op1.getSimpleValueType();
13549 bool IsF128 = (VT == MVT::f128);
13551 // If second operand is smaller, extend it first.
13552 if (SrcVT.bitsLT(VT)) {
13553 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
13556 // And if it is bigger, shrink it first.
13557 if (SrcVT.bitsGT(VT)) {
13558 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1, dl));
13562 // At this point the operands and the result should have the same
13563 // type, and that won't be f80 since that is not custom lowered.
13564 assert((VT == MVT::f64 || VT == MVT::f32 || IsF128) &&
13565 "Unexpected type in LowerFCOPYSIGN");
13567 const fltSemantics &Sem =
13568 VT == MVT::f64 ? APFloat::IEEEdouble :
13569 (IsF128 ? APFloat::IEEEquad : APFloat::IEEEsingle);
13570 const unsigned SizeInBits = VT.getSizeInBits();
13572 SmallVector<Constant *, 4> CV(
13573 VT == MVT::f64 ? 2 : (IsF128 ? 1 : 4),
13574 ConstantFP::get(*Context, APFloat(Sem, APInt(SizeInBits, 0))));
13576 // First, clear all bits but the sign bit from the second operand (sign).
13577 CV[0] = ConstantFP::get(*Context,
13578 APFloat(Sem, APInt::getHighBitsSet(SizeInBits, 1)));
13579 Constant *C = ConstantVector::get(CV);
13580 auto PtrVT = TLI.getPointerTy(DAG.getDataLayout());
13581 SDValue CPIdx = DAG.getConstantPool(C, PtrVT, 16);
13583 // Perform all logic operations as 16-byte vectors because there are no
13584 // scalar FP logic instructions in SSE. This allows load folding of the
13585 // constants into the logic instructions.
13586 MVT LogicVT = (VT == MVT::f64) ? MVT::v2f64 : (IsF128 ? MVT::f128 : MVT::v4f32);
13588 DAG.getLoad(LogicVT, dl, DAG.getEntryNode(), CPIdx,
13589 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
13590 false, false, false, 16);
13592 Op1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Op1);
13593 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, LogicVT, Op1, Mask1);
13595 // Next, clear the sign bit from the first operand (magnitude).
13596 // If it's a constant, we can clear it here.
13597 if (ConstantFPSDNode *Op0CN = dyn_cast<ConstantFPSDNode>(Op0)) {
13598 APFloat APF = Op0CN->getValueAPF();
13599 // If the magnitude is a positive zero, the sign bit alone is enough.
13600 if (APF.isPosZero())
13601 return IsF128 ? SignBit :
13602 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SrcVT, SignBit,
13603 DAG.getIntPtrConstant(0, dl));
13605 CV[0] = ConstantFP::get(*Context, APF);
13607 CV[0] = ConstantFP::get(
13609 APFloat(Sem, APInt::getLowBitsSet(SizeInBits, SizeInBits - 1)));
13611 C = ConstantVector::get(CV);
13612 CPIdx = DAG.getConstantPool(C, PtrVT, 16);
13614 DAG.getLoad(LogicVT, dl, DAG.getEntryNode(), CPIdx,
13615 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
13616 false, false, false, 16);
13617 // If the magnitude operand wasn't a constant, we need to AND out the sign.
13618 if (!isa<ConstantFPSDNode>(Op0)) {
13620 Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Op0);
13621 Val = DAG.getNode(X86ISD::FAND, dl, LogicVT, Op0, Val);
13623 // OR the magnitude value with the sign bit.
13624 Val = DAG.getNode(X86ISD::FOR, dl, LogicVT, Val, SignBit);
13625 return IsF128 ? Val :
13626 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SrcVT, Val,
13627 DAG.getIntPtrConstant(0, dl));
13630 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
13631 SDValue N0 = Op.getOperand(0);
13633 MVT VT = Op.getSimpleValueType();
13635 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
13636 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
13637 DAG.getConstant(1, dl, VT));
13638 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, dl, VT));
13641 // Check whether an OR'd tree is PTEST-able.
13642 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
13643 SelectionDAG &DAG) {
13644 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
13646 if (!Subtarget->hasSSE41())
13649 if (!Op->hasOneUse())
13652 SDNode *N = Op.getNode();
13655 SmallVector<SDValue, 8> Opnds;
13656 DenseMap<SDValue, unsigned> VecInMap;
13657 SmallVector<SDValue, 8> VecIns;
13658 EVT VT = MVT::Other;
13660 // Recognize a special case where a vector is casted into wide integer to
13662 Opnds.push_back(N->getOperand(0));
13663 Opnds.push_back(N->getOperand(1));
13665 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
13666 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
13667 // BFS traverse all OR'd operands.
13668 if (I->getOpcode() == ISD::OR) {
13669 Opnds.push_back(I->getOperand(0));
13670 Opnds.push_back(I->getOperand(1));
13671 // Re-evaluate the number of nodes to be traversed.
13672 e += 2; // 2 more nodes (LHS and RHS) are pushed.
13676 // Quit if a non-EXTRACT_VECTOR_ELT
13677 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
13680 // Quit if without a constant index.
13681 SDValue Idx = I->getOperand(1);
13682 if (!isa<ConstantSDNode>(Idx))
13685 SDValue ExtractedFromVec = I->getOperand(0);
13686 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
13687 if (M == VecInMap.end()) {
13688 VT = ExtractedFromVec.getValueType();
13689 // Quit if not 128/256-bit vector.
13690 if (!VT.is128BitVector() && !VT.is256BitVector())
13692 // Quit if not the same type.
13693 if (VecInMap.begin() != VecInMap.end() &&
13694 VT != VecInMap.begin()->first.getValueType())
13696 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
13697 VecIns.push_back(ExtractedFromVec);
13699 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
13702 assert((VT.is128BitVector() || VT.is256BitVector()) &&
13703 "Not extracted from 128-/256-bit vector.");
13705 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
13707 for (DenseMap<SDValue, unsigned>::const_iterator
13708 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
13709 // Quit if not all elements are used.
13710 if (I->second != FullMask)
13714 MVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
13716 // Cast all vectors into TestVT for PTEST.
13717 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
13718 VecIns[i] = DAG.getBitcast(TestVT, VecIns[i]);
13720 // If more than one full vectors are evaluated, OR them first before PTEST.
13721 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
13722 // Each iteration will OR 2 nodes and append the result until there is only
13723 // 1 node left, i.e. the final OR'd value of all vectors.
13724 SDValue LHS = VecIns[Slot];
13725 SDValue RHS = VecIns[Slot + 1];
13726 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
13729 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
13730 VecIns.back(), VecIns.back());
13733 /// \brief return true if \c Op has a use that doesn't just read flags.
13734 static bool hasNonFlagsUse(SDValue Op) {
13735 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
13737 SDNode *User = *UI;
13738 unsigned UOpNo = UI.getOperandNo();
13739 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
13740 // Look pass truncate.
13741 UOpNo = User->use_begin().getOperandNo();
13742 User = *User->use_begin();
13745 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
13746 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
13752 /// Emit nodes that will be selected as "test Op0,Op0", or something
13754 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
13755 SelectionDAG &DAG) const {
13756 if (Op.getValueType() == MVT::i1) {
13757 SDValue ExtOp = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i8, Op);
13758 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, ExtOp,
13759 DAG.getConstant(0, dl, MVT::i8));
13761 // CF and OF aren't always set the way we want. Determine which
13762 // of these we need.
13763 bool NeedCF = false;
13764 bool NeedOF = false;
13767 case X86::COND_A: case X86::COND_AE:
13768 case X86::COND_B: case X86::COND_BE:
13771 case X86::COND_G: case X86::COND_GE:
13772 case X86::COND_L: case X86::COND_LE:
13773 case X86::COND_O: case X86::COND_NO: {
13774 // Check if we really need to set the
13775 // Overflow flag. If NoSignedWrap is present
13776 // that is not actually needed.
13777 switch (Op->getOpcode()) {
13782 const auto *BinNode = cast<BinaryWithFlagsSDNode>(Op.getNode());
13783 if (BinNode->Flags.hasNoSignedWrap())
13793 // See if we can use the EFLAGS value from the operand instead of
13794 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
13795 // we prove that the arithmetic won't overflow, we can't use OF or CF.
13796 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
13797 // Emit a CMP with 0, which is the TEST pattern.
13798 //if (Op.getValueType() == MVT::i1)
13799 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
13800 // DAG.getConstant(0, MVT::i1));
13801 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13802 DAG.getConstant(0, dl, Op.getValueType()));
13804 unsigned Opcode = 0;
13805 unsigned NumOperands = 0;
13807 // Truncate operations may prevent the merge of the SETCC instruction
13808 // and the arithmetic instruction before it. Attempt to truncate the operands
13809 // of the arithmetic instruction and use a reduced bit-width instruction.
13810 bool NeedTruncation = false;
13811 SDValue ArithOp = Op;
13812 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
13813 SDValue Arith = Op->getOperand(0);
13814 // Both the trunc and the arithmetic op need to have one user each.
13815 if (Arith->hasOneUse())
13816 switch (Arith.getOpcode()) {
13823 NeedTruncation = true;
13829 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
13830 // which may be the result of a CAST. We use the variable 'Op', which is the
13831 // non-casted variable when we check for possible users.
13832 switch (ArithOp.getOpcode()) {
13834 // Due to an isel shortcoming, be conservative if this add is likely to be
13835 // selected as part of a load-modify-store instruction. When the root node
13836 // in a match is a store, isel doesn't know how to remap non-chain non-flag
13837 // uses of other nodes in the match, such as the ADD in this case. This
13838 // leads to the ADD being left around and reselected, with the result being
13839 // two adds in the output. Alas, even if none our users are stores, that
13840 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
13841 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
13842 // climbing the DAG back to the root, and it doesn't seem to be worth the
13844 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13845 UE = Op.getNode()->use_end(); UI != UE; ++UI)
13846 if (UI->getOpcode() != ISD::CopyToReg &&
13847 UI->getOpcode() != ISD::SETCC &&
13848 UI->getOpcode() != ISD::STORE)
13851 if (ConstantSDNode *C =
13852 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
13853 // An add of one will be selected as an INC.
13854 if (C->isOne() && !Subtarget->slowIncDec()) {
13855 Opcode = X86ISD::INC;
13860 // An add of negative one (subtract of one) will be selected as a DEC.
13861 if (C->isAllOnesValue() && !Subtarget->slowIncDec()) {
13862 Opcode = X86ISD::DEC;
13868 // Otherwise use a regular EFLAGS-setting add.
13869 Opcode = X86ISD::ADD;
13874 // If we have a constant logical shift that's only used in a comparison
13875 // against zero turn it into an equivalent AND. This allows turning it into
13876 // a TEST instruction later.
13877 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
13878 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
13879 EVT VT = Op.getValueType();
13880 unsigned BitWidth = VT.getSizeInBits();
13881 unsigned ShAmt = Op->getConstantOperandVal(1);
13882 if (ShAmt >= BitWidth) // Avoid undefined shifts.
13884 APInt Mask = ArithOp.getOpcode() == ISD::SRL
13885 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
13886 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
13887 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
13889 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
13890 DAG.getConstant(Mask, dl, VT));
13891 DAG.ReplaceAllUsesWith(Op, New);
13897 // If the primary and result isn't used, don't bother using X86ISD::AND,
13898 // because a TEST instruction will be better.
13899 if (!hasNonFlagsUse(Op))
13905 // Due to the ISEL shortcoming noted above, be conservative if this op is
13906 // likely to be selected as part of a load-modify-store instruction.
13907 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13908 UE = Op.getNode()->use_end(); UI != UE; ++UI)
13909 if (UI->getOpcode() == ISD::STORE)
13912 // Otherwise use a regular EFLAGS-setting instruction.
13913 switch (ArithOp.getOpcode()) {
13914 default: llvm_unreachable("unexpected operator!");
13915 case ISD::SUB: Opcode = X86ISD::SUB; break;
13916 case ISD::XOR: Opcode = X86ISD::XOR; break;
13917 case ISD::AND: Opcode = X86ISD::AND; break;
13919 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
13920 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
13921 if (EFLAGS.getNode())
13924 Opcode = X86ISD::OR;
13938 return SDValue(Op.getNode(), 1);
13944 // If we found that truncation is beneficial, perform the truncation and
13946 if (NeedTruncation) {
13947 EVT VT = Op.getValueType();
13948 SDValue WideVal = Op->getOperand(0);
13949 EVT WideVT = WideVal.getValueType();
13950 unsigned ConvertedOp = 0;
13951 // Use a target machine opcode to prevent further DAGCombine
13952 // optimizations that may separate the arithmetic operations
13953 // from the setcc node.
13954 switch (WideVal.getOpcode()) {
13956 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
13957 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
13958 case ISD::AND: ConvertedOp = X86ISD::AND; break;
13959 case ISD::OR: ConvertedOp = X86ISD::OR; break;
13960 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
13964 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13965 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
13966 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
13967 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
13968 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
13974 // Emit a CMP with 0, which is the TEST pattern.
13975 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13976 DAG.getConstant(0, dl, Op.getValueType()));
13978 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
13979 SmallVector<SDValue, 4> Ops(Op->op_begin(), Op->op_begin() + NumOperands);
13981 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
13982 DAG.ReplaceAllUsesWith(Op, New);
13983 return SDValue(New.getNode(), 1);
13986 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
13988 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
13989 SDLoc dl, SelectionDAG &DAG) const {
13990 if (isNullConstant(Op1))
13991 return EmitTest(Op0, X86CC, dl, DAG);
13993 assert(!(isa<ConstantSDNode>(Op1) && Op0.getValueType() == MVT::i1) &&
13994 "Unexpected comparison operation for MVT::i1 operands");
13996 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
13997 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
13998 // Do the comparison at i32 if it's smaller, besides the Atom case.
13999 // This avoids subregister aliasing issues. Keep the smaller reference
14000 // if we're optimizing for size, however, as that'll allow better folding
14001 // of memory operations.
14002 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
14003 !DAG.getMachineFunction().getFunction()->optForMinSize() &&
14004 !Subtarget->isAtom()) {
14005 unsigned ExtendOp =
14006 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
14007 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
14008 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
14010 // Use SUB instead of CMP to enable CSE between SUB and CMP.
14011 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
14012 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
14014 return SDValue(Sub.getNode(), 1);
14016 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
14019 /// Convert a comparison if required by the subtarget.
14020 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
14021 SelectionDAG &DAG) const {
14022 // If the subtarget does not support the FUCOMI instruction, floating-point
14023 // comparisons have to be converted.
14024 if (Subtarget->hasCMov() ||
14025 Cmp.getOpcode() != X86ISD::CMP ||
14026 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
14027 !Cmp.getOperand(1).getValueType().isFloatingPoint())
14030 // The instruction selector will select an FUCOM instruction instead of
14031 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
14032 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
14033 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
14035 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
14036 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
14037 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
14038 DAG.getConstant(8, dl, MVT::i8));
14039 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
14041 // Some 64-bit targets lack SAHF support, but they do support FCOMI.
14042 assert(Subtarget->hasLAHFSAHF() && "Target doesn't support SAHF or FCOMI?");
14043 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
14046 /// The minimum architected relative accuracy is 2^-12. We need one
14047 /// Newton-Raphson step to have a good float result (24 bits of precision).
14048 SDValue X86TargetLowering::getRsqrtEstimate(SDValue Op,
14049 DAGCombinerInfo &DCI,
14050 unsigned &RefinementSteps,
14051 bool &UseOneConstNR) const {
14052 EVT VT = Op.getValueType();
14053 const char *RecipOp;
14055 // SSE1 has rsqrtss and rsqrtps. AVX adds a 256-bit variant for rsqrtps.
14056 // TODO: Add support for AVX512 (v16f32).
14057 // It is likely not profitable to do this for f64 because a double-precision
14058 // rsqrt estimate with refinement on x86 prior to FMA requires at least 16
14059 // instructions: convert to single, rsqrtss, convert back to double, refine
14060 // (3 steps = at least 13 insts). If an 'rsqrtsd' variant was added to the ISA
14061 // along with FMA, this could be a throughput win.
14062 if (VT == MVT::f32 && Subtarget->hasSSE1())
14064 else if ((VT == MVT::v4f32 && Subtarget->hasSSE1()) ||
14065 (VT == MVT::v8f32 && Subtarget->hasAVX()))
14066 RecipOp = "vec-sqrtf";
14070 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
14071 if (!Recips.isEnabled(RecipOp))
14074 RefinementSteps = Recips.getRefinementSteps(RecipOp);
14075 UseOneConstNR = false;
14076 return DCI.DAG.getNode(X86ISD::FRSQRT, SDLoc(Op), VT, Op);
14079 /// The minimum architected relative accuracy is 2^-12. We need one
14080 /// Newton-Raphson step to have a good float result (24 bits of precision).
14081 SDValue X86TargetLowering::getRecipEstimate(SDValue Op,
14082 DAGCombinerInfo &DCI,
14083 unsigned &RefinementSteps) const {
14084 EVT VT = Op.getValueType();
14085 const char *RecipOp;
14087 // SSE1 has rcpss and rcpps. AVX adds a 256-bit variant for rcpps.
14088 // TODO: Add support for AVX512 (v16f32).
14089 // It is likely not profitable to do this for f64 because a double-precision
14090 // reciprocal estimate with refinement on x86 prior to FMA requires
14091 // 15 instructions: convert to single, rcpss, convert back to double, refine
14092 // (3 steps = 12 insts). If an 'rcpsd' variant was added to the ISA
14093 // along with FMA, this could be a throughput win.
14094 if (VT == MVT::f32 && Subtarget->hasSSE1())
14096 else if ((VT == MVT::v4f32 && Subtarget->hasSSE1()) ||
14097 (VT == MVT::v8f32 && Subtarget->hasAVX()))
14098 RecipOp = "vec-divf";
14102 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
14103 if (!Recips.isEnabled(RecipOp))
14106 RefinementSteps = Recips.getRefinementSteps(RecipOp);
14107 return DCI.DAG.getNode(X86ISD::FRCP, SDLoc(Op), VT, Op);
14110 /// If we have at least two divisions that use the same divisor, convert to
14111 /// multplication by a reciprocal. This may need to be adjusted for a given
14112 /// CPU if a division's cost is not at least twice the cost of a multiplication.
14113 /// This is because we still need one division to calculate the reciprocal and
14114 /// then we need two multiplies by that reciprocal as replacements for the
14115 /// original divisions.
14116 unsigned X86TargetLowering::combineRepeatedFPDivisors() const {
14120 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
14121 /// if it's possible.
14122 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
14123 SDLoc dl, SelectionDAG &DAG) const {
14124 SDValue Op0 = And.getOperand(0);
14125 SDValue Op1 = And.getOperand(1);
14126 if (Op0.getOpcode() == ISD::TRUNCATE)
14127 Op0 = Op0.getOperand(0);
14128 if (Op1.getOpcode() == ISD::TRUNCATE)
14129 Op1 = Op1.getOperand(0);
14132 if (Op1.getOpcode() == ISD::SHL)
14133 std::swap(Op0, Op1);
14134 if (Op0.getOpcode() == ISD::SHL) {
14135 if (isOneConstant(Op0.getOperand(0))) {
14136 // If we looked past a truncate, check that it's only truncating away
14138 unsigned BitWidth = Op0.getValueSizeInBits();
14139 unsigned AndBitWidth = And.getValueSizeInBits();
14140 if (BitWidth > AndBitWidth) {
14142 DAG.computeKnownBits(Op0, Zeros, Ones);
14143 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
14147 RHS = Op0.getOperand(1);
14149 } else if (Op1.getOpcode() == ISD::Constant) {
14150 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
14151 uint64_t AndRHSVal = AndRHS->getZExtValue();
14152 SDValue AndLHS = Op0;
14154 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
14155 LHS = AndLHS.getOperand(0);
14156 RHS = AndLHS.getOperand(1);
14159 // Use BT if the immediate can't be encoded in a TEST instruction.
14160 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
14162 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), dl, LHS.getValueType());
14166 if (LHS.getNode()) {
14167 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
14168 // instruction. Since the shift amount is in-range-or-undefined, we know
14169 // that doing a bittest on the i32 value is ok. We extend to i32 because
14170 // the encoding for the i16 version is larger than the i32 version.
14171 // Also promote i16 to i32 for performance / code size reason.
14172 if (LHS.getValueType() == MVT::i8 ||
14173 LHS.getValueType() == MVT::i16)
14174 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
14176 // If the operand types disagree, extend the shift amount to match. Since
14177 // BT ignores high bits (like shifts) we can use anyextend.
14178 if (LHS.getValueType() != RHS.getValueType())
14179 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
14181 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
14182 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
14183 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14184 DAG.getConstant(Cond, dl, MVT::i8), BT);
14190 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
14192 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
14197 // SSE Condition code mapping:
14206 switch (SetCCOpcode) {
14207 default: llvm_unreachable("Unexpected SETCC condition");
14209 case ISD::SETEQ: SSECC = 0; break;
14211 case ISD::SETGT: Swap = true; // Fallthrough
14213 case ISD::SETOLT: SSECC = 1; break;
14215 case ISD::SETGE: Swap = true; // Fallthrough
14217 case ISD::SETOLE: SSECC = 2; break;
14218 case ISD::SETUO: SSECC = 3; break;
14220 case ISD::SETNE: SSECC = 4; break;
14221 case ISD::SETULE: Swap = true; // Fallthrough
14222 case ISD::SETUGE: SSECC = 5; break;
14223 case ISD::SETULT: Swap = true; // Fallthrough
14224 case ISD::SETUGT: SSECC = 6; break;
14225 case ISD::SETO: SSECC = 7; break;
14227 case ISD::SETONE: SSECC = 8; break;
14230 std::swap(Op0, Op1);
14235 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
14236 // ones, and then concatenate the result back.
14237 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
14238 MVT VT = Op.getSimpleValueType();
14240 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
14241 "Unsupported value type for operation");
14243 unsigned NumElems = VT.getVectorNumElements();
14245 SDValue CC = Op.getOperand(2);
14247 // Extract the LHS vectors
14248 SDValue LHS = Op.getOperand(0);
14249 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
14250 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
14252 // Extract the RHS vectors
14253 SDValue RHS = Op.getOperand(1);
14254 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
14255 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
14257 // Issue the operation on the smaller types and concatenate the result back
14258 MVT EltVT = VT.getVectorElementType();
14259 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
14260 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
14261 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
14262 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
14265 static SDValue LowerBoolVSETCC_AVX512(SDValue Op, SelectionDAG &DAG) {
14266 SDValue Op0 = Op.getOperand(0);
14267 SDValue Op1 = Op.getOperand(1);
14268 SDValue CC = Op.getOperand(2);
14269 MVT VT = Op.getSimpleValueType();
14272 assert(Op0.getSimpleValueType().getVectorElementType() == MVT::i1 &&
14273 "Unexpected type for boolean compare operation");
14274 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14275 SDValue NotOp0 = DAG.getNode(ISD::XOR, dl, VT, Op0,
14276 DAG.getConstant(-1, dl, VT));
14277 SDValue NotOp1 = DAG.getNode(ISD::XOR, dl, VT, Op1,
14278 DAG.getConstant(-1, dl, VT));
14279 switch (SetCCOpcode) {
14280 default: llvm_unreachable("Unexpected SETCC condition");
14282 // (x == y) -> ~(x ^ y)
14283 return DAG.getNode(ISD::XOR, dl, VT,
14284 DAG.getNode(ISD::XOR, dl, VT, Op0, Op1),
14285 DAG.getConstant(-1, dl, VT));
14287 // (x != y) -> (x ^ y)
14288 return DAG.getNode(ISD::XOR, dl, VT, Op0, Op1);
14291 // (x > y) -> (x & ~y)
14292 return DAG.getNode(ISD::AND, dl, VT, Op0, NotOp1);
14295 // (x < y) -> (~x & y)
14296 return DAG.getNode(ISD::AND, dl, VT, NotOp0, Op1);
14299 // (x <= y) -> (~x | y)
14300 return DAG.getNode(ISD::OR, dl, VT, NotOp0, Op1);
14303 // (x >=y) -> (x | ~y)
14304 return DAG.getNode(ISD::OR, dl, VT, Op0, NotOp1);
14308 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
14309 const X86Subtarget *Subtarget) {
14310 SDValue Op0 = Op.getOperand(0);
14311 SDValue Op1 = Op.getOperand(1);
14312 SDValue CC = Op.getOperand(2);
14313 MVT VT = Op.getSimpleValueType();
14316 assert(Op0.getSimpleValueType().getVectorElementType().getSizeInBits() >= 8 &&
14317 Op.getSimpleValueType().getVectorElementType() == MVT::i1 &&
14318 "Cannot set masked compare for this operation");
14320 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14322 bool Unsigned = false;
14325 switch (SetCCOpcode) {
14326 default: llvm_unreachable("Unexpected SETCC condition");
14327 case ISD::SETNE: SSECC = 4; break;
14328 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
14329 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
14330 case ISD::SETLT: Swap = true; //fall-through
14331 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
14332 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
14333 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
14334 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
14335 case ISD::SETULE: Unsigned = true; //fall-through
14336 case ISD::SETLE: SSECC = 2; break;
14340 std::swap(Op0, Op1);
14342 return DAG.getNode(Opc, dl, VT, Op0, Op1);
14343 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
14344 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14345 DAG.getConstant(SSECC, dl, MVT::i8));
14348 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
14349 /// operand \p Op1. If non-trivial (for example because it's not constant)
14350 /// return an empty value.
14351 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
14353 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
14357 MVT VT = Op1.getSimpleValueType();
14358 MVT EVT = VT.getVectorElementType();
14359 unsigned n = VT.getVectorNumElements();
14360 SmallVector<SDValue, 8> ULTOp1;
14362 for (unsigned i = 0; i < n; ++i) {
14363 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
14364 if (!Elt || Elt->isOpaque() || Elt->getSimpleValueType(0) != EVT)
14367 // Avoid underflow.
14368 APInt Val = Elt->getAPIntValue();
14372 ULTOp1.push_back(DAG.getConstant(Val - 1, dl, EVT));
14375 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
14378 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
14379 SelectionDAG &DAG) {
14380 SDValue Op0 = Op.getOperand(0);
14381 SDValue Op1 = Op.getOperand(1);
14382 SDValue CC = Op.getOperand(2);
14383 MVT VT = Op.getSimpleValueType();
14384 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14385 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
14390 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
14391 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
14394 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
14395 unsigned Opc = X86ISD::CMPP;
14396 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
14397 assert(VT.getVectorNumElements() <= 16);
14398 Opc = X86ISD::CMPM;
14400 // In the two special cases we can't handle, emit two comparisons.
14403 unsigned CombineOpc;
14404 if (SetCCOpcode == ISD::SETUEQ) {
14405 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
14407 assert(SetCCOpcode == ISD::SETONE);
14408 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
14411 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
14412 DAG.getConstant(CC0, dl, MVT::i8));
14413 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
14414 DAG.getConstant(CC1, dl, MVT::i8));
14415 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
14417 // Handle all other FP comparisons here.
14418 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14419 DAG.getConstant(SSECC, dl, MVT::i8));
14422 MVT VTOp0 = Op0.getSimpleValueType();
14423 assert(VTOp0 == Op1.getSimpleValueType() &&
14424 "Expected operands with same type!");
14425 assert(VT.getVectorNumElements() == VTOp0.getVectorNumElements() &&
14426 "Invalid number of packed elements for source and destination!");
14428 if (VT.is128BitVector() && VTOp0.is256BitVector()) {
14429 // On non-AVX512 targets, a vector of MVT::i1 is promoted by the type
14430 // legalizer to a wider vector type. In the case of 'vsetcc' nodes, the
14431 // legalizer firstly checks if the first operand in input to the setcc has
14432 // a legal type. If so, then it promotes the return type to that same type.
14433 // Otherwise, the return type is promoted to the 'next legal type' which,
14434 // for a vector of MVT::i1 is always a 128-bit integer vector type.
14436 // We reach this code only if the following two conditions are met:
14437 // 1. Both return type and operand type have been promoted to wider types
14438 // by the type legalizer.
14439 // 2. The original operand type has been promoted to a 256-bit vector.
14441 // Note that condition 2. only applies for AVX targets.
14442 SDValue NewOp = DAG.getSetCC(dl, VTOp0, Op0, Op1, SetCCOpcode);
14443 return DAG.getZExtOrTrunc(NewOp, dl, VT);
14446 // The non-AVX512 code below works under the assumption that source and
14447 // destination types are the same.
14448 assert((Subtarget->hasAVX512() || (VT == VTOp0)) &&
14449 "Value types for source and destination must be the same!");
14451 // Break 256-bit integer vector compare into smaller ones.
14452 if (VT.is256BitVector() && !Subtarget->hasInt256())
14453 return Lower256IntVSETCC(Op, DAG);
14455 MVT OpVT = Op1.getSimpleValueType();
14456 if (OpVT.getVectorElementType() == MVT::i1)
14457 return LowerBoolVSETCC_AVX512(Op, DAG);
14459 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
14460 if (Subtarget->hasAVX512()) {
14461 if (Op1.getSimpleValueType().is512BitVector() ||
14462 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
14463 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
14464 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
14466 // In AVX-512 architecture setcc returns mask with i1 elements,
14467 // But there is no compare instruction for i8 and i16 elements in KNL.
14468 // We are not talking about 512-bit operands in this case, these
14469 // types are illegal.
14471 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
14472 OpVT.getVectorElementType().getSizeInBits() >= 8))
14473 return DAG.getNode(ISD::TRUNCATE, dl, VT,
14474 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
14477 // Lower using XOP integer comparisons.
14478 if ((VT == MVT::v16i8 || VT == MVT::v8i16 ||
14479 VT == MVT::v4i32 || VT == MVT::v2i64) && Subtarget->hasXOP()) {
14480 // Translate compare code to XOP PCOM compare mode.
14481 unsigned CmpMode = 0;
14482 switch (SetCCOpcode) {
14483 default: llvm_unreachable("Unexpected SETCC condition");
14485 case ISD::SETLT: CmpMode = 0x00; break;
14487 case ISD::SETLE: CmpMode = 0x01; break;
14489 case ISD::SETGT: CmpMode = 0x02; break;
14491 case ISD::SETGE: CmpMode = 0x03; break;
14492 case ISD::SETEQ: CmpMode = 0x04; break;
14493 case ISD::SETNE: CmpMode = 0x05; break;
14496 // Are we comparing unsigned or signed integers?
14497 unsigned Opc = ISD::isUnsignedIntSetCC(SetCCOpcode)
14498 ? X86ISD::VPCOMU : X86ISD::VPCOM;
14500 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14501 DAG.getConstant(CmpMode, dl, MVT::i8));
14504 // We are handling one of the integer comparisons here. Since SSE only has
14505 // GT and EQ comparisons for integer, swapping operands and multiple
14506 // operations may be required for some comparisons.
14508 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
14509 bool Subus = false;
14511 switch (SetCCOpcode) {
14512 default: llvm_unreachable("Unexpected SETCC condition");
14513 case ISD::SETNE: Invert = true;
14514 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
14515 case ISD::SETLT: Swap = true;
14516 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
14517 case ISD::SETGE: Swap = true;
14518 case ISD::SETLE: Opc = X86ISD::PCMPGT;
14519 Invert = true; break;
14520 case ISD::SETULT: Swap = true;
14521 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
14522 FlipSigns = true; break;
14523 case ISD::SETUGE: Swap = true;
14524 case ISD::SETULE: Opc = X86ISD::PCMPGT;
14525 FlipSigns = true; Invert = true; break;
14528 // Special case: Use min/max operations for SETULE/SETUGE
14529 MVT VET = VT.getVectorElementType();
14531 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
14532 || (Subtarget->hasSSE2() && (VET == MVT::i8));
14535 switch (SetCCOpcode) {
14537 case ISD::SETULE: Opc = ISD::UMIN; MinMax = true; break;
14538 case ISD::SETUGE: Opc = ISD::UMAX; MinMax = true; break;
14541 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
14544 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
14545 if (!MinMax && hasSubus) {
14546 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
14548 // t = psubus Op0, Op1
14549 // pcmpeq t, <0..0>
14550 switch (SetCCOpcode) {
14552 case ISD::SETULT: {
14553 // If the comparison is against a constant we can turn this into a
14554 // setule. With psubus, setule does not require a swap. This is
14555 // beneficial because the constant in the register is no longer
14556 // destructed as the destination so it can be hoisted out of a loop.
14557 // Only do this pre-AVX since vpcmp* is no longer destructive.
14558 if (Subtarget->hasAVX())
14560 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
14561 if (ULEOp1.getNode()) {
14563 Subus = true; Invert = false; Swap = false;
14567 // Psubus is better than flip-sign because it requires no inversion.
14568 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
14569 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
14573 Opc = X86ISD::SUBUS;
14579 std::swap(Op0, Op1);
14581 // Check that the operation in question is available (most are plain SSE2,
14582 // but PCMPGTQ and PCMPEQQ have different requirements).
14583 if (VT == MVT::v2i64) {
14584 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
14585 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
14587 // First cast everything to the right type.
14588 Op0 = DAG.getBitcast(MVT::v4i32, Op0);
14589 Op1 = DAG.getBitcast(MVT::v4i32, Op1);
14591 // Since SSE has no unsigned integer comparisons, we need to flip the sign
14592 // bits of the inputs before performing those operations. The lower
14593 // compare is always unsigned.
14596 SB = DAG.getConstant(0x80000000U, dl, MVT::v4i32);
14598 SDValue Sign = DAG.getConstant(0x80000000U, dl, MVT::i32);
14599 SDValue Zero = DAG.getConstant(0x00000000U, dl, MVT::i32);
14600 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
14601 Sign, Zero, Sign, Zero);
14603 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
14604 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
14606 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
14607 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
14608 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
14610 // Create masks for only the low parts/high parts of the 64 bit integers.
14611 static const int MaskHi[] = { 1, 1, 3, 3 };
14612 static const int MaskLo[] = { 0, 0, 2, 2 };
14613 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
14614 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
14615 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
14617 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
14618 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
14621 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14623 return DAG.getBitcast(VT, Result);
14626 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
14627 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
14628 // pcmpeqd + pshufd + pand.
14629 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
14631 // First cast everything to the right type.
14632 Op0 = DAG.getBitcast(MVT::v4i32, Op0);
14633 Op1 = DAG.getBitcast(MVT::v4i32, Op1);
14636 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
14638 // Make sure the lower and upper halves are both all-ones.
14639 static const int Mask[] = { 1, 0, 3, 2 };
14640 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
14641 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
14644 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14646 return DAG.getBitcast(VT, Result);
14650 // Since SSE has no unsigned integer comparisons, we need to flip the sign
14651 // bits of the inputs before performing those operations.
14653 MVT EltVT = VT.getVectorElementType();
14654 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), dl,
14656 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
14657 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
14660 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
14662 // If the logical-not of the result is required, perform that now.
14664 Result = DAG.getNOT(dl, Result, VT);
14667 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
14670 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
14671 getZeroVector(VT, Subtarget, DAG, dl));
14676 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
14678 MVT VT = Op.getSimpleValueType();
14680 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
14682 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
14683 && "SetCC type must be 8-bit or 1-bit integer");
14684 SDValue Op0 = Op.getOperand(0);
14685 SDValue Op1 = Op.getOperand(1);
14687 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
14689 // Optimize to BT if possible.
14690 // Lower (X & (1 << N)) == 0 to BT(X, N).
14691 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
14692 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
14693 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
14694 isNullConstant(Op1) &&
14695 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14696 if (SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG)) {
14698 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewSetCC);
14703 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
14705 if ((isOneConstant(Op1) || isNullConstant(Op1)) &&
14706 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14708 // If the input is a setcc, then reuse the input setcc or use a new one with
14709 // the inverted condition.
14710 if (Op0.getOpcode() == X86ISD::SETCC) {
14711 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
14712 bool Invert = (CC == ISD::SETNE) ^ isNullConstant(Op1);
14716 CCode = X86::GetOppositeBranchCondition(CCode);
14717 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14718 DAG.getConstant(CCode, dl, MVT::i8),
14719 Op0.getOperand(1));
14721 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14725 if ((Op0.getValueType() == MVT::i1) && isOneConstant(Op1) &&
14726 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14728 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
14729 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, dl, MVT::i1), NewCC);
14732 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
14733 unsigned X86CC = TranslateX86CC(CC, dl, isFP, Op0, Op1, DAG);
14734 if (X86CC == X86::COND_INVALID)
14737 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
14738 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
14739 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14740 DAG.getConstant(X86CC, dl, MVT::i8), EFLAGS);
14742 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14746 SDValue X86TargetLowering::LowerSETCCE(SDValue Op, SelectionDAG &DAG) const {
14747 SDValue LHS = Op.getOperand(0);
14748 SDValue RHS = Op.getOperand(1);
14749 SDValue Carry = Op.getOperand(2);
14750 SDValue Cond = Op.getOperand(3);
14753 assert(LHS.getSimpleValueType().isInteger() && "SETCCE is integer only.");
14754 X86::CondCode CC = TranslateIntegerX86CC(cast<CondCodeSDNode>(Cond)->get());
14756 assert(Carry.getOpcode() != ISD::CARRY_FALSE);
14757 SDVTList VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
14758 SDValue Cmp = DAG.getNode(X86ISD::SBB, DL, VTs, LHS, RHS, Carry);
14759 return DAG.getNode(X86ISD::SETCC, DL, Op.getValueType(),
14760 DAG.getConstant(CC, DL, MVT::i8), Cmp.getValue(1));
14763 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
14764 static bool isX86LogicalCmp(SDValue Op) {
14765 unsigned Opc = Op.getNode()->getOpcode();
14766 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
14767 Opc == X86ISD::SAHF)
14769 if (Op.getResNo() == 1 &&
14770 (Opc == X86ISD::ADD ||
14771 Opc == X86ISD::SUB ||
14772 Opc == X86ISD::ADC ||
14773 Opc == X86ISD::SBB ||
14774 Opc == X86ISD::SMUL ||
14775 Opc == X86ISD::UMUL ||
14776 Opc == X86ISD::INC ||
14777 Opc == X86ISD::DEC ||
14778 Opc == X86ISD::OR ||
14779 Opc == X86ISD::XOR ||
14780 Opc == X86ISD::AND))
14783 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
14789 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
14790 if (V.getOpcode() != ISD::TRUNCATE)
14793 SDValue VOp0 = V.getOperand(0);
14794 unsigned InBits = VOp0.getValueSizeInBits();
14795 unsigned Bits = V.getValueSizeInBits();
14796 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
14799 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
14800 bool addTest = true;
14801 SDValue Cond = Op.getOperand(0);
14802 SDValue Op1 = Op.getOperand(1);
14803 SDValue Op2 = Op.getOperand(2);
14805 MVT VT = Op1.getSimpleValueType();
14808 // Lower FP selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
14809 // are available or VBLENDV if AVX is available.
14810 // Otherwise FP cmovs get lowered into a less efficient branch sequence later.
14811 if (Cond.getOpcode() == ISD::SETCC &&
14812 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
14813 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
14814 VT == Cond.getOperand(0).getSimpleValueType() && Cond->hasOneUse()) {
14815 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
14816 int SSECC = translateX86FSETCC(
14817 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
14820 if (Subtarget->hasAVX512()) {
14821 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
14822 DAG.getConstant(SSECC, DL, MVT::i8));
14823 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
14826 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
14827 DAG.getConstant(SSECC, DL, MVT::i8));
14829 // If we have AVX, we can use a variable vector select (VBLENDV) instead
14830 // of 3 logic instructions for size savings and potentially speed.
14831 // Unfortunately, there is no scalar form of VBLENDV.
14833 // If either operand is a constant, don't try this. We can expect to
14834 // optimize away at least one of the logic instructions later in that
14835 // case, so that sequence would be faster than a variable blend.
14837 // BLENDV was introduced with SSE 4.1, but the 2 register form implicitly
14838 // uses XMM0 as the selection register. That may need just as many
14839 // instructions as the AND/ANDN/OR sequence due to register moves, so
14842 if (Subtarget->hasAVX() &&
14843 !isa<ConstantFPSDNode>(Op1) && !isa<ConstantFPSDNode>(Op2)) {
14845 // Convert to vectors, do a VSELECT, and convert back to scalar.
14846 // All of the conversions should be optimized away.
14848 MVT VecVT = VT == MVT::f32 ? MVT::v4f32 : MVT::v2f64;
14849 SDValue VOp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op1);
14850 SDValue VOp2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op2);
14851 SDValue VCmp = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Cmp);
14853 MVT VCmpVT = VT == MVT::f32 ? MVT::v4i32 : MVT::v2i64;
14854 VCmp = DAG.getBitcast(VCmpVT, VCmp);
14856 SDValue VSel = DAG.getNode(ISD::VSELECT, DL, VecVT, VCmp, VOp1, VOp2);
14858 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT,
14859 VSel, DAG.getIntPtrConstant(0, DL));
14861 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
14862 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
14863 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
14867 if (VT.isVector() && VT.getVectorElementType() == MVT::i1) {
14869 if (ISD::isBuildVectorOfConstantSDNodes(Op1.getNode()))
14870 Op1Scalar = ConvertI1VectorToInteger(Op1, DAG);
14871 else if (Op1.getOpcode() == ISD::BITCAST && Op1.getOperand(0))
14872 Op1Scalar = Op1.getOperand(0);
14874 if (ISD::isBuildVectorOfConstantSDNodes(Op2.getNode()))
14875 Op2Scalar = ConvertI1VectorToInteger(Op2, DAG);
14876 else if (Op2.getOpcode() == ISD::BITCAST && Op2.getOperand(0))
14877 Op2Scalar = Op2.getOperand(0);
14878 if (Op1Scalar.getNode() && Op2Scalar.getNode()) {
14879 SDValue newSelect = DAG.getNode(ISD::SELECT, DL,
14880 Op1Scalar.getValueType(),
14881 Cond, Op1Scalar, Op2Scalar);
14882 if (newSelect.getValueSizeInBits() == VT.getSizeInBits())
14883 return DAG.getBitcast(VT, newSelect);
14884 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, newSelect);
14885 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, ExtVec,
14886 DAG.getIntPtrConstant(0, DL));
14890 if (VT == MVT::v4i1 || VT == MVT::v2i1) {
14891 SDValue zeroConst = DAG.getIntPtrConstant(0, DL);
14892 Op1 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,
14893 DAG.getUNDEF(MVT::v8i1), Op1, zeroConst);
14894 Op2 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,
14895 DAG.getUNDEF(MVT::v8i1), Op2, zeroConst);
14896 SDValue newSelect = DAG.getNode(ISD::SELECT, DL, MVT::v8i1,
14898 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, newSelect, zeroConst);
14901 if (Cond.getOpcode() == ISD::SETCC) {
14902 SDValue NewCond = LowerSETCC(Cond, DAG);
14903 if (NewCond.getNode())
14907 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
14908 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
14909 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
14910 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
14911 if (Cond.getOpcode() == X86ISD::SETCC &&
14912 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
14913 isNullConstant(Cond.getOperand(1).getOperand(1))) {
14914 SDValue Cmp = Cond.getOperand(1);
14916 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
14918 if ((isAllOnesConstant(Op1) || isAllOnesConstant(Op2)) &&
14919 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
14920 SDValue Y = isAllOnesConstant(Op2) ? Op1 : Op2;
14922 SDValue CmpOp0 = Cmp.getOperand(0);
14923 // Apply further optimizations for special cases
14924 // (select (x != 0), -1, 0) -> neg & sbb
14925 // (select (x == 0), 0, -1) -> neg & sbb
14926 if (isNullConstant(Y) &&
14927 (isAllOnesConstant(Op1) == (CondCode == X86::COND_NE))) {
14928 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
14929 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
14930 DAG.getConstant(0, DL,
14931 CmpOp0.getValueType()),
14933 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14934 DAG.getConstant(X86::COND_B, DL, MVT::i8),
14935 SDValue(Neg.getNode(), 1));
14939 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
14940 CmpOp0, DAG.getConstant(1, DL, CmpOp0.getValueType()));
14941 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14943 SDValue Res = // Res = 0 or -1.
14944 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14945 DAG.getConstant(X86::COND_B, DL, MVT::i8), Cmp);
14947 if (isAllOnesConstant(Op1) != (CondCode == X86::COND_E))
14948 Res = DAG.getNOT(DL, Res, Res.getValueType());
14950 if (!isNullConstant(Op2))
14951 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
14956 // Look past (and (setcc_carry (cmp ...)), 1).
14957 if (Cond.getOpcode() == ISD::AND &&
14958 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY &&
14959 isOneConstant(Cond.getOperand(1)))
14960 Cond = Cond.getOperand(0);
14962 // If condition flag is set by a X86ISD::CMP, then use it as the condition
14963 // setting operand in place of the X86ISD::SETCC.
14964 unsigned CondOpcode = Cond.getOpcode();
14965 if (CondOpcode == X86ISD::SETCC ||
14966 CondOpcode == X86ISD::SETCC_CARRY) {
14967 CC = Cond.getOperand(0);
14969 SDValue Cmp = Cond.getOperand(1);
14970 unsigned Opc = Cmp.getOpcode();
14971 MVT VT = Op.getSimpleValueType();
14973 bool IllegalFPCMov = false;
14974 if (VT.isFloatingPoint() && !VT.isVector() &&
14975 !isScalarFPTypeInSSEReg(VT)) // FPStack?
14976 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
14978 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
14979 Opc == X86ISD::BT) { // FIXME
14983 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
14984 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
14985 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
14986 Cond.getOperand(0).getValueType() != MVT::i8)) {
14987 SDValue LHS = Cond.getOperand(0);
14988 SDValue RHS = Cond.getOperand(1);
14989 unsigned X86Opcode;
14992 switch (CondOpcode) {
14993 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
14994 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
14995 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
14996 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
14997 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
14998 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
14999 default: llvm_unreachable("unexpected overflowing operator");
15001 if (CondOpcode == ISD::UMULO)
15002 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
15005 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
15007 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
15009 if (CondOpcode == ISD::UMULO)
15010 Cond = X86Op.getValue(2);
15012 Cond = X86Op.getValue(1);
15014 CC = DAG.getConstant(X86Cond, DL, MVT::i8);
15019 // Look past the truncate if the high bits are known zero.
15020 if (isTruncWithZeroHighBitsInput(Cond, DAG))
15021 Cond = Cond.getOperand(0);
15023 // We know the result of AND is compared against zero. Try to match
15025 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
15026 if (SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG)) {
15027 CC = NewSetCC.getOperand(0);
15028 Cond = NewSetCC.getOperand(1);
15035 CC = DAG.getConstant(X86::COND_NE, DL, MVT::i8);
15036 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
15039 // a < b ? -1 : 0 -> RES = ~setcc_carry
15040 // a < b ? 0 : -1 -> RES = setcc_carry
15041 // a >= b ? -1 : 0 -> RES = setcc_carry
15042 // a >= b ? 0 : -1 -> RES = ~setcc_carry
15043 if (Cond.getOpcode() == X86ISD::SUB) {
15044 Cond = ConvertCmpIfNecessary(Cond, DAG);
15045 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
15047 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
15048 (isAllOnesConstant(Op1) || isAllOnesConstant(Op2)) &&
15049 (isNullConstant(Op1) || isNullConstant(Op2))) {
15050 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15051 DAG.getConstant(X86::COND_B, DL, MVT::i8),
15053 if (isAllOnesConstant(Op1) != (CondCode == X86::COND_B))
15054 return DAG.getNOT(DL, Res, Res.getValueType());
15059 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
15060 // widen the cmov and push the truncate through. This avoids introducing a new
15061 // branch during isel and doesn't add any extensions.
15062 if (Op.getValueType() == MVT::i8 &&
15063 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
15064 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
15065 if (T1.getValueType() == T2.getValueType() &&
15066 // Blacklist CopyFromReg to avoid partial register stalls.
15067 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
15068 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
15069 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
15070 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
15074 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
15075 // condition is true.
15076 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
15077 SDValue Ops[] = { Op2, Op1, CC, Cond };
15078 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
15081 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op,
15082 const X86Subtarget *Subtarget,
15083 SelectionDAG &DAG) {
15084 MVT VT = Op->getSimpleValueType(0);
15085 SDValue In = Op->getOperand(0);
15086 MVT InVT = In.getSimpleValueType();
15087 MVT VTElt = VT.getVectorElementType();
15088 MVT InVTElt = InVT.getVectorElementType();
15092 if ((InVTElt == MVT::i1) &&
15093 (((Subtarget->hasBWI() && Subtarget->hasVLX() &&
15094 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() <= 16)) ||
15096 ((Subtarget->hasBWI() && VT.is512BitVector() &&
15097 VTElt.getSizeInBits() <= 16)) ||
15099 ((Subtarget->hasDQI() && Subtarget->hasVLX() &&
15100 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() >= 32)) ||
15102 ((Subtarget->hasDQI() && VT.is512BitVector() &&
15103 VTElt.getSizeInBits() >= 32))))
15104 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15106 unsigned int NumElts = VT.getVectorNumElements();
15108 if (NumElts != 8 && NumElts != 16 && !Subtarget->hasBWI())
15111 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1) {
15112 if (In.getOpcode() == X86ISD::VSEXT || In.getOpcode() == X86ISD::VZEXT)
15113 return DAG.getNode(In.getOpcode(), dl, VT, In.getOperand(0));
15114 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15117 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
15118 MVT ExtVT = NumElts == 8 ? MVT::v8i64 : MVT::v16i32;
15120 DAG.getConstant(APInt::getAllOnesValue(ExtVT.getScalarSizeInBits()), dl,
15123 DAG.getConstant(APInt::getNullValue(ExtVT.getScalarSizeInBits()), dl, ExtVT);
15125 SDValue V = DAG.getNode(ISD::VSELECT, dl, ExtVT, In, NegOne, Zero);
15126 if (VT.is512BitVector())
15128 return DAG.getNode(X86ISD::VTRUNC, dl, VT, V);
15131 static SDValue LowerSIGN_EXTEND_VECTOR_INREG(SDValue Op,
15132 const X86Subtarget *Subtarget,
15133 SelectionDAG &DAG) {
15134 SDValue In = Op->getOperand(0);
15135 MVT VT = Op->getSimpleValueType(0);
15136 MVT InVT = In.getSimpleValueType();
15137 assert(VT.getSizeInBits() == InVT.getSizeInBits());
15139 MVT InSVT = InVT.getVectorElementType();
15140 assert(VT.getVectorElementType().getSizeInBits() > InSVT.getSizeInBits());
15142 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
15144 if (InSVT != MVT::i32 && InSVT != MVT::i16 && InSVT != MVT::i8)
15149 // SSE41 targets can use the pmovsx* instructions directly.
15150 if (Subtarget->hasSSE41())
15151 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15153 // pre-SSE41 targets unpack lower lanes and then sign-extend using SRAI.
15157 // As SRAI is only available on i16/i32 types, we expand only up to i32
15158 // and handle i64 separately.
15159 while (CurrVT != VT && CurrVT.getVectorElementType() != MVT::i32) {
15160 Curr = DAG.getNode(X86ISD::UNPCKL, dl, CurrVT, DAG.getUNDEF(CurrVT), Curr);
15161 MVT CurrSVT = MVT::getIntegerVT(CurrVT.getScalarSizeInBits() * 2);
15162 CurrVT = MVT::getVectorVT(CurrSVT, CurrVT.getVectorNumElements() / 2);
15163 Curr = DAG.getBitcast(CurrVT, Curr);
15166 SDValue SignExt = Curr;
15167 if (CurrVT != InVT) {
15168 unsigned SignExtShift =
15169 CurrVT.getVectorElementType().getSizeInBits() - InSVT.getSizeInBits();
15170 SignExt = DAG.getNode(X86ISD::VSRAI, dl, CurrVT, Curr,
15171 DAG.getConstant(SignExtShift, dl, MVT::i8));
15177 if (VT == MVT::v2i64 && CurrVT == MVT::v4i32) {
15178 SDValue Sign = DAG.getNode(X86ISD::VSRAI, dl, CurrVT, Curr,
15179 DAG.getConstant(31, dl, MVT::i8));
15180 SDValue Ext = DAG.getVectorShuffle(CurrVT, dl, SignExt, Sign, {0, 4, 1, 5});
15181 return DAG.getBitcast(VT, Ext);
15187 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
15188 SelectionDAG &DAG) {
15189 MVT VT = Op->getSimpleValueType(0);
15190 SDValue In = Op->getOperand(0);
15191 MVT InVT = In.getSimpleValueType();
15194 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
15195 return LowerSIGN_EXTEND_AVX512(Op, Subtarget, DAG);
15197 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
15198 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
15199 (VT != MVT::v16i16 || InVT != MVT::v16i8))
15202 if (Subtarget->hasInt256())
15203 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15205 // Optimize vectors in AVX mode
15206 // Sign extend v8i16 to v8i32 and
15209 // Divide input vector into two parts
15210 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
15211 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
15212 // concat the vectors to original VT
15214 unsigned NumElems = InVT.getVectorNumElements();
15215 SDValue Undef = DAG.getUNDEF(InVT);
15217 SmallVector<int,8> ShufMask1(NumElems, -1);
15218 for (unsigned i = 0; i != NumElems/2; ++i)
15221 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
15223 SmallVector<int,8> ShufMask2(NumElems, -1);
15224 for (unsigned i = 0; i != NumElems/2; ++i)
15225 ShufMask2[i] = i + NumElems/2;
15227 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
15229 MVT HalfVT = MVT::getVectorVT(VT.getVectorElementType(),
15230 VT.getVectorNumElements()/2);
15232 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
15233 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
15235 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
15238 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
15239 // may emit an illegal shuffle but the expansion is still better than scalar
15240 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
15241 // we'll emit a shuffle and a arithmetic shift.
15242 // FIXME: Is the expansion actually better than scalar code? It doesn't seem so.
15243 // TODO: It is possible to support ZExt by zeroing the undef values during
15244 // the shuffle phase or after the shuffle.
15245 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
15246 SelectionDAG &DAG) {
15247 MVT RegVT = Op.getSimpleValueType();
15248 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
15249 assert(RegVT.isInteger() &&
15250 "We only custom lower integer vector sext loads.");
15252 // Nothing useful we can do without SSE2 shuffles.
15253 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
15255 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
15257 EVT MemVT = Ld->getMemoryVT();
15258 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15259 unsigned RegSz = RegVT.getSizeInBits();
15261 ISD::LoadExtType Ext = Ld->getExtensionType();
15263 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
15264 && "Only anyext and sext are currently implemented.");
15265 assert(MemVT != RegVT && "Cannot extend to the same type");
15266 assert(MemVT.isVector() && "Must load a vector from memory");
15268 unsigned NumElems = RegVT.getVectorNumElements();
15269 unsigned MemSz = MemVT.getSizeInBits();
15270 assert(RegSz > MemSz && "Register size must be greater than the mem size");
15272 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
15273 // The only way in which we have a legal 256-bit vector result but not the
15274 // integer 256-bit operations needed to directly lower a sextload is if we
15275 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
15276 // a 128-bit vector and a normal sign_extend to 256-bits that should get
15277 // correctly legalized. We do this late to allow the canonical form of
15278 // sextload to persist throughout the rest of the DAG combiner -- it wants
15279 // to fold together any extensions it can, and so will fuse a sign_extend
15280 // of an sextload into a sextload targeting a wider value.
15282 if (MemSz == 128) {
15283 // Just switch this to a normal load.
15284 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
15285 "it must be a legal 128-bit vector "
15287 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
15288 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
15289 Ld->isInvariant(), Ld->getAlignment());
15291 assert(MemSz < 128 &&
15292 "Can't extend a type wider than 128 bits to a 256 bit vector!");
15293 // Do an sext load to a 128-bit vector type. We want to use the same
15294 // number of elements, but elements half as wide. This will end up being
15295 // recursively lowered by this routine, but will succeed as we definitely
15296 // have all the necessary features if we're using AVX1.
15298 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
15299 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
15301 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
15302 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
15303 Ld->isNonTemporal(), Ld->isInvariant(),
15304 Ld->getAlignment());
15307 // Replace chain users with the new chain.
15308 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
15309 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
15311 // Finally, do a normal sign-extend to the desired register.
15312 return DAG.getSExtOrTrunc(Load, dl, RegVT);
15315 // All sizes must be a power of two.
15316 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
15317 "Non-power-of-two elements are not custom lowered!");
15319 // Attempt to load the original value using scalar loads.
15320 // Find the largest scalar type that divides the total loaded size.
15321 MVT SclrLoadTy = MVT::i8;
15322 for (MVT Tp : MVT::integer_valuetypes()) {
15323 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
15328 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
15329 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
15331 SclrLoadTy = MVT::f64;
15333 // Calculate the number of scalar loads that we need to perform
15334 // in order to load our vector from memory.
15335 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
15337 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
15338 "Can only lower sext loads with a single scalar load!");
15340 unsigned loadRegZize = RegSz;
15341 if (Ext == ISD::SEXTLOAD && RegSz >= 256)
15344 // Represent our vector as a sequence of elements which are the
15345 // largest scalar that we can load.
15346 EVT LoadUnitVecVT = EVT::getVectorVT(
15347 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
15349 // Represent the data using the same element type that is stored in
15350 // memory. In practice, we ''widen'' MemVT.
15352 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
15353 loadRegZize / MemVT.getScalarSizeInBits());
15355 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
15356 "Invalid vector type");
15358 // We can't shuffle using an illegal type.
15359 assert(TLI.isTypeLegal(WideVecVT) &&
15360 "We only lower types that form legal widened vector types");
15362 SmallVector<SDValue, 8> Chains;
15363 SDValue Ptr = Ld->getBasePtr();
15364 SDValue Increment = DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, dl,
15365 TLI.getPointerTy(DAG.getDataLayout()));
15366 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
15368 for (unsigned i = 0; i < NumLoads; ++i) {
15369 // Perform a single load.
15370 SDValue ScalarLoad =
15371 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
15372 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
15373 Ld->getAlignment());
15374 Chains.push_back(ScalarLoad.getValue(1));
15375 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
15376 // another round of DAGCombining.
15378 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
15380 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
15381 ScalarLoad, DAG.getIntPtrConstant(i, dl));
15383 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
15386 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
15388 // Bitcast the loaded value to a vector of the original element type, in
15389 // the size of the target vector type.
15390 SDValue SlicedVec = DAG.getBitcast(WideVecVT, Res);
15391 unsigned SizeRatio = RegSz / MemSz;
15393 if (Ext == ISD::SEXTLOAD) {
15394 // If we have SSE4.1, we can directly emit a VSEXT node.
15395 if (Subtarget->hasSSE41()) {
15396 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
15397 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15401 // Otherwise we'll use SIGN_EXTEND_VECTOR_INREG to sign extend the lowest
15403 assert(TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND_VECTOR_INREG, RegVT) &&
15404 "We can't implement a sext load without SIGN_EXTEND_VECTOR_INREG!");
15406 SDValue Shuff = DAG.getSignExtendVectorInReg(SlicedVec, dl, RegVT);
15407 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15411 // Redistribute the loaded elements into the different locations.
15412 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
15413 for (unsigned i = 0; i != NumElems; ++i)
15414 ShuffleVec[i * SizeRatio] = i;
15416 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
15417 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
15419 // Bitcast to the requested type.
15420 Shuff = DAG.getBitcast(RegVT, Shuff);
15421 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15425 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
15426 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
15427 // from the AND / OR.
15428 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
15429 Opc = Op.getOpcode();
15430 if (Opc != ISD::OR && Opc != ISD::AND)
15432 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
15433 Op.getOperand(0).hasOneUse() &&
15434 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
15435 Op.getOperand(1).hasOneUse());
15438 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
15439 // 1 and that the SETCC node has a single use.
15440 static bool isXor1OfSetCC(SDValue Op) {
15441 if (Op.getOpcode() != ISD::XOR)
15443 if (isOneConstant(Op.getOperand(1)))
15444 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
15445 Op.getOperand(0).hasOneUse();
15449 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
15450 bool addTest = true;
15451 SDValue Chain = Op.getOperand(0);
15452 SDValue Cond = Op.getOperand(1);
15453 SDValue Dest = Op.getOperand(2);
15456 bool Inverted = false;
15458 if (Cond.getOpcode() == ISD::SETCC) {
15459 // Check for setcc([su]{add,sub,mul}o == 0).
15460 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
15461 isNullConstant(Cond.getOperand(1)) &&
15462 Cond.getOperand(0).getResNo() == 1 &&
15463 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
15464 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
15465 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
15466 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
15467 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
15468 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
15470 Cond = Cond.getOperand(0);
15472 SDValue NewCond = LowerSETCC(Cond, DAG);
15473 if (NewCond.getNode())
15478 // FIXME: LowerXALUO doesn't handle these!!
15479 else if (Cond.getOpcode() == X86ISD::ADD ||
15480 Cond.getOpcode() == X86ISD::SUB ||
15481 Cond.getOpcode() == X86ISD::SMUL ||
15482 Cond.getOpcode() == X86ISD::UMUL)
15483 Cond = LowerXALUO(Cond, DAG);
15486 // Look pass (and (setcc_carry (cmp ...)), 1).
15487 if (Cond.getOpcode() == ISD::AND &&
15488 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY &&
15489 isOneConstant(Cond.getOperand(1)))
15490 Cond = Cond.getOperand(0);
15492 // If condition flag is set by a X86ISD::CMP, then use it as the condition
15493 // setting operand in place of the X86ISD::SETCC.
15494 unsigned CondOpcode = Cond.getOpcode();
15495 if (CondOpcode == X86ISD::SETCC ||
15496 CondOpcode == X86ISD::SETCC_CARRY) {
15497 CC = Cond.getOperand(0);
15499 SDValue Cmp = Cond.getOperand(1);
15500 unsigned Opc = Cmp.getOpcode();
15501 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
15502 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
15506 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
15510 // These can only come from an arithmetic instruction with overflow,
15511 // e.g. SADDO, UADDO.
15512 Cond = Cond.getNode()->getOperand(1);
15518 CondOpcode = Cond.getOpcode();
15519 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
15520 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
15521 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
15522 Cond.getOperand(0).getValueType() != MVT::i8)) {
15523 SDValue LHS = Cond.getOperand(0);
15524 SDValue RHS = Cond.getOperand(1);
15525 unsigned X86Opcode;
15528 // Keep this in sync with LowerXALUO, otherwise we might create redundant
15529 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
15531 switch (CondOpcode) {
15532 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
15534 if (isOneConstant(RHS)) {
15535 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
15538 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
15539 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
15541 if (isOneConstant(RHS)) {
15542 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
15545 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
15546 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
15547 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
15548 default: llvm_unreachable("unexpected overflowing operator");
15551 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
15552 if (CondOpcode == ISD::UMULO)
15553 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
15556 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
15558 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
15560 if (CondOpcode == ISD::UMULO)
15561 Cond = X86Op.getValue(2);
15563 Cond = X86Op.getValue(1);
15565 CC = DAG.getConstant(X86Cond, dl, MVT::i8);
15569 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
15570 SDValue Cmp = Cond.getOperand(0).getOperand(1);
15571 if (CondOpc == ISD::OR) {
15572 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
15573 // two branches instead of an explicit OR instruction with a
15575 if (Cmp == Cond.getOperand(1).getOperand(1) &&
15576 isX86LogicalCmp(Cmp)) {
15577 CC = Cond.getOperand(0).getOperand(0);
15578 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15579 Chain, Dest, CC, Cmp);
15580 CC = Cond.getOperand(1).getOperand(0);
15584 } else { // ISD::AND
15585 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
15586 // two branches instead of an explicit AND instruction with a
15587 // separate test. However, we only do this if this block doesn't
15588 // have a fall-through edge, because this requires an explicit
15589 // jmp when the condition is false.
15590 if (Cmp == Cond.getOperand(1).getOperand(1) &&
15591 isX86LogicalCmp(Cmp) &&
15592 Op.getNode()->hasOneUse()) {
15593 X86::CondCode CCode =
15594 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
15595 CCode = X86::GetOppositeBranchCondition(CCode);
15596 CC = DAG.getConstant(CCode, dl, MVT::i8);
15597 SDNode *User = *Op.getNode()->use_begin();
15598 // Look for an unconditional branch following this conditional branch.
15599 // We need this because we need to reverse the successors in order
15600 // to implement FCMP_OEQ.
15601 if (User->getOpcode() == ISD::BR) {
15602 SDValue FalseBB = User->getOperand(1);
15604 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15605 assert(NewBR == User);
15609 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15610 Chain, Dest, CC, Cmp);
15611 X86::CondCode CCode =
15612 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
15613 CCode = X86::GetOppositeBranchCondition(CCode);
15614 CC = DAG.getConstant(CCode, dl, MVT::i8);
15620 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
15621 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
15622 // It should be transformed during dag combiner except when the condition
15623 // is set by a arithmetics with overflow node.
15624 X86::CondCode CCode =
15625 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
15626 CCode = X86::GetOppositeBranchCondition(CCode);
15627 CC = DAG.getConstant(CCode, dl, MVT::i8);
15628 Cond = Cond.getOperand(0).getOperand(1);
15630 } else if (Cond.getOpcode() == ISD::SETCC &&
15631 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
15632 // For FCMP_OEQ, we can emit
15633 // two branches instead of an explicit AND instruction with a
15634 // separate test. However, we only do this if this block doesn't
15635 // have a fall-through edge, because this requires an explicit
15636 // jmp when the condition is false.
15637 if (Op.getNode()->hasOneUse()) {
15638 SDNode *User = *Op.getNode()->use_begin();
15639 // Look for an unconditional branch following this conditional branch.
15640 // We need this because we need to reverse the successors in order
15641 // to implement FCMP_OEQ.
15642 if (User->getOpcode() == ISD::BR) {
15643 SDValue FalseBB = User->getOperand(1);
15645 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15646 assert(NewBR == User);
15650 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
15651 Cond.getOperand(0), Cond.getOperand(1));
15652 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15653 CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
15654 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15655 Chain, Dest, CC, Cmp);
15656 CC = DAG.getConstant(X86::COND_P, dl, MVT::i8);
15661 } else if (Cond.getOpcode() == ISD::SETCC &&
15662 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
15663 // For FCMP_UNE, we can emit
15664 // two branches instead of an explicit AND instruction with a
15665 // separate test. However, we only do this if this block doesn't
15666 // have a fall-through edge, because this requires an explicit
15667 // jmp when the condition is false.
15668 if (Op.getNode()->hasOneUse()) {
15669 SDNode *User = *Op.getNode()->use_begin();
15670 // Look for an unconditional branch following this conditional branch.
15671 // We need this because we need to reverse the successors in order
15672 // to implement FCMP_UNE.
15673 if (User->getOpcode() == ISD::BR) {
15674 SDValue FalseBB = User->getOperand(1);
15676 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15677 assert(NewBR == User);
15680 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
15681 Cond.getOperand(0), Cond.getOperand(1));
15682 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15683 CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
15684 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15685 Chain, Dest, CC, Cmp);
15686 CC = DAG.getConstant(X86::COND_NP, dl, MVT::i8);
15696 // Look pass the truncate if the high bits are known zero.
15697 if (isTruncWithZeroHighBitsInput(Cond, DAG))
15698 Cond = Cond.getOperand(0);
15700 // We know the result of AND is compared against zero. Try to match
15702 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
15703 if (SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG)) {
15704 CC = NewSetCC.getOperand(0);
15705 Cond = NewSetCC.getOperand(1);
15712 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
15713 CC = DAG.getConstant(X86Cond, dl, MVT::i8);
15714 Cond = EmitTest(Cond, X86Cond, dl, DAG);
15716 Cond = ConvertCmpIfNecessary(Cond, DAG);
15717 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15718 Chain, Dest, CC, Cond);
15721 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
15722 // Calls to _alloca are needed to probe the stack when allocating more than 4k
15723 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
15724 // that the guard pages used by the OS virtual memory manager are allocated in
15725 // correct sequence.
15727 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
15728 SelectionDAG &DAG) const {
15729 MachineFunction &MF = DAG.getMachineFunction();
15730 bool SplitStack = MF.shouldSplitStack();
15731 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMachO()) ||
15736 SDNode *Node = Op.getNode();
15737 SDValue Chain = Op.getOperand(0);
15738 SDValue Size = Op.getOperand(1);
15739 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
15740 EVT VT = Node->getValueType(0);
15742 // Chain the dynamic stack allocation so that it doesn't modify the stack
15743 // pointer when other instructions are using the stack.
15744 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, dl, true), dl);
15746 bool Is64Bit = Subtarget->is64Bit();
15747 MVT SPTy = getPointerTy(DAG.getDataLayout());
15751 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15752 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
15753 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
15754 " not tell us which reg is the stack pointer!");
15755 EVT VT = Node->getValueType(0);
15756 SDValue Tmp3 = Node->getOperand(2);
15758 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
15759 Chain = SP.getValue(1);
15760 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
15761 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
15762 unsigned StackAlign = TFI.getStackAlignment();
15763 Result = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
15764 if (Align > StackAlign)
15765 Result = DAG.getNode(ISD::AND, dl, VT, Result,
15766 DAG.getConstant(-(uint64_t)Align, dl, VT));
15767 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Result); // Output chain
15768 } else if (SplitStack) {
15769 MachineRegisterInfo &MRI = MF.getRegInfo();
15772 // The 64 bit implementation of segmented stacks needs to clobber both r10
15773 // r11. This makes it impossible to use it along with nested parameters.
15774 const Function *F = MF.getFunction();
15776 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
15778 if (I->hasNestAttr())
15779 report_fatal_error("Cannot use segmented stacks with functions that "
15780 "have nested arguments.");
15783 const TargetRegisterClass *AddrRegClass = getRegClassFor(SPTy);
15784 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
15785 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
15786 Result = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
15787 DAG.getRegister(Vreg, SPTy));
15790 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
15792 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
15793 Flag = Chain.getValue(1);
15794 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
15796 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
15798 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15799 unsigned SPReg = RegInfo->getStackRegister();
15800 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
15801 Chain = SP.getValue(1);
15804 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
15805 DAG.getConstant(-(uint64_t)Align, dl, VT));
15806 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
15812 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, dl, true),
15813 DAG.getIntPtrConstant(0, dl, true), SDValue(), dl);
15815 SDValue Ops[2] = {Result, Chain};
15816 return DAG.getMergeValues(Ops, dl);
15819 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
15820 MachineFunction &MF = DAG.getMachineFunction();
15821 auto PtrVT = getPointerTy(MF.getDataLayout());
15822 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
15824 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15827 if (!Subtarget->is64Bit() ||
15828 Subtarget->isCallingConvWin64(MF.getFunction()->getCallingConv())) {
15829 // vastart just stores the address of the VarArgsFrameIndex slot into the
15830 // memory location argument.
15831 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
15832 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
15833 MachinePointerInfo(SV), false, false, 0);
15837 // gp_offset (0 - 6 * 8)
15838 // fp_offset (48 - 48 + 8 * 16)
15839 // overflow_arg_area (point to parameters coming in memory).
15841 SmallVector<SDValue, 8> MemOps;
15842 SDValue FIN = Op.getOperand(1);
15844 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
15845 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
15847 FIN, MachinePointerInfo(SV), false, false, 0);
15848 MemOps.push_back(Store);
15851 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(4, DL));
15852 Store = DAG.getStore(Op.getOperand(0), DL,
15853 DAG.getConstant(FuncInfo->getVarArgsFPOffset(), DL,
15855 FIN, MachinePointerInfo(SV, 4), false, false, 0);
15856 MemOps.push_back(Store);
15858 // Store ptr to overflow_arg_area
15859 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(4, DL));
15860 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
15861 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
15862 MachinePointerInfo(SV, 8),
15864 MemOps.push_back(Store);
15866 // Store ptr to reg_save_area.
15867 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(
15868 Subtarget->isTarget64BitLP64() ? 8 : 4, DL));
15869 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), PtrVT);
15870 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN, MachinePointerInfo(
15871 SV, Subtarget->isTarget64BitLP64() ? 16 : 12), false, false, 0);
15872 MemOps.push_back(Store);
15873 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
15876 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
15877 assert(Subtarget->is64Bit() &&
15878 "LowerVAARG only handles 64-bit va_arg!");
15879 assert(Op.getNode()->getNumOperands() == 4);
15881 MachineFunction &MF = DAG.getMachineFunction();
15882 if (Subtarget->isCallingConvWin64(MF.getFunction()->getCallingConv()))
15883 // The Win64 ABI uses char* instead of a structure.
15884 return DAG.expandVAArg(Op.getNode());
15886 SDValue Chain = Op.getOperand(0);
15887 SDValue SrcPtr = Op.getOperand(1);
15888 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15889 unsigned Align = Op.getConstantOperandVal(3);
15892 EVT ArgVT = Op.getNode()->getValueType(0);
15893 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
15894 uint32_t ArgSize = DAG.getDataLayout().getTypeAllocSize(ArgTy);
15897 // Decide which area this value should be read from.
15898 // TODO: Implement the AMD64 ABI in its entirety. This simple
15899 // selection mechanism works only for the basic types.
15900 if (ArgVT == MVT::f80) {
15901 llvm_unreachable("va_arg for f80 not yet implemented");
15902 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
15903 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
15904 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
15905 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
15907 llvm_unreachable("Unhandled argument type in LowerVAARG");
15910 if (ArgMode == 2) {
15911 // Sanity Check: Make sure using fp_offset makes sense.
15912 assert(!Subtarget->useSoftFloat() &&
15913 !(MF.getFunction()->hasFnAttribute(Attribute::NoImplicitFloat)) &&
15914 Subtarget->hasSSE1());
15917 // Insert VAARG_64 node into the DAG
15918 // VAARG_64 returns two values: Variable Argument Address, Chain
15919 SDValue InstOps[] = {Chain, SrcPtr, DAG.getConstant(ArgSize, dl, MVT::i32),
15920 DAG.getConstant(ArgMode, dl, MVT::i8),
15921 DAG.getConstant(Align, dl, MVT::i32)};
15922 SDVTList VTs = DAG.getVTList(getPointerTy(DAG.getDataLayout()), MVT::Other);
15923 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
15924 VTs, InstOps, MVT::i64,
15925 MachinePointerInfo(SV),
15927 /*Volatile=*/false,
15929 /*WriteMem=*/true);
15930 Chain = VAARG.getValue(1);
15932 // Load the next argument and return it
15933 return DAG.getLoad(ArgVT, dl,
15936 MachinePointerInfo(),
15937 false, false, false, 0);
15940 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
15941 SelectionDAG &DAG) {
15942 // X86-64 va_list is a struct { i32, i32, i8*, i8* }, except on Windows,
15943 // where a va_list is still an i8*.
15944 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
15945 if (Subtarget->isCallingConvWin64(
15946 DAG.getMachineFunction().getFunction()->getCallingConv()))
15947 // Probably a Win64 va_copy.
15948 return DAG.expandVACopy(Op.getNode());
15950 SDValue Chain = Op.getOperand(0);
15951 SDValue DstPtr = Op.getOperand(1);
15952 SDValue SrcPtr = Op.getOperand(2);
15953 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
15954 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
15957 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
15958 DAG.getIntPtrConstant(24, DL), 8, /*isVolatile*/false,
15960 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
15963 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
15964 // amount is a constant. Takes immediate version of shift as input.
15965 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
15966 SDValue SrcOp, uint64_t ShiftAmt,
15967 SelectionDAG &DAG) {
15968 MVT ElementType = VT.getVectorElementType();
15970 // Fold this packed shift into its first operand if ShiftAmt is 0.
15974 // Check for ShiftAmt >= element width
15975 if (ShiftAmt >= ElementType.getSizeInBits()) {
15976 if (Opc == X86ISD::VSRAI)
15977 ShiftAmt = ElementType.getSizeInBits() - 1;
15979 return DAG.getConstant(0, dl, VT);
15982 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
15983 && "Unknown target vector shift-by-constant node");
15985 // Fold this packed vector shift into a build vector if SrcOp is a
15986 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
15987 if (VT == SrcOp.getSimpleValueType() &&
15988 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
15989 SmallVector<SDValue, 8> Elts;
15990 unsigned NumElts = SrcOp->getNumOperands();
15991 ConstantSDNode *ND;
15994 default: llvm_unreachable(nullptr);
15995 case X86ISD::VSHLI:
15996 for (unsigned i=0; i!=NumElts; ++i) {
15997 SDValue CurrentOp = SrcOp->getOperand(i);
15998 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15999 Elts.push_back(CurrentOp);
16002 ND = cast<ConstantSDNode>(CurrentOp);
16003 const APInt &C = ND->getAPIntValue();
16004 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), dl, ElementType));
16007 case X86ISD::VSRLI:
16008 for (unsigned i=0; i!=NumElts; ++i) {
16009 SDValue CurrentOp = SrcOp->getOperand(i);
16010 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16011 Elts.push_back(CurrentOp);
16014 ND = cast<ConstantSDNode>(CurrentOp);
16015 const APInt &C = ND->getAPIntValue();
16016 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), dl, ElementType));
16019 case X86ISD::VSRAI:
16020 for (unsigned i=0; i!=NumElts; ++i) {
16021 SDValue CurrentOp = SrcOp->getOperand(i);
16022 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16023 Elts.push_back(CurrentOp);
16026 ND = cast<ConstantSDNode>(CurrentOp);
16027 const APInt &C = ND->getAPIntValue();
16028 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), dl, ElementType));
16033 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
16036 return DAG.getNode(Opc, dl, VT, SrcOp,
16037 DAG.getConstant(ShiftAmt, dl, MVT::i8));
16040 // getTargetVShiftNode - Handle vector element shifts where the shift amount
16041 // may or may not be a constant. Takes immediate version of shift as input.
16042 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
16043 SDValue SrcOp, SDValue ShAmt,
16044 SelectionDAG &DAG) {
16045 MVT SVT = ShAmt.getSimpleValueType();
16046 assert((SVT == MVT::i32 || SVT == MVT::i64) && "Unexpected value type!");
16048 // Catch shift-by-constant.
16049 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
16050 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
16051 CShAmt->getZExtValue(), DAG);
16053 // Change opcode to non-immediate version
16055 default: llvm_unreachable("Unknown target vector shift node");
16056 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
16057 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
16058 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
16061 const X86Subtarget &Subtarget =
16062 static_cast<const X86Subtarget &>(DAG.getSubtarget());
16063 if (Subtarget.hasSSE41() && ShAmt.getOpcode() == ISD::ZERO_EXTEND &&
16064 ShAmt.getOperand(0).getSimpleValueType() == MVT::i16) {
16065 // Let the shuffle legalizer expand this shift amount node.
16066 SDValue Op0 = ShAmt.getOperand(0);
16067 Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(Op0), MVT::v8i16, Op0);
16068 ShAmt = getShuffleVectorZeroOrUndef(Op0, 0, true, &Subtarget, DAG);
16070 // Need to build a vector containing shift amount.
16071 // SSE/AVX packed shifts only use the lower 64-bit of the shift count.
16072 SmallVector<SDValue, 4> ShOps;
16073 ShOps.push_back(ShAmt);
16074 if (SVT == MVT::i32) {
16075 ShOps.push_back(DAG.getConstant(0, dl, SVT));
16076 ShOps.push_back(DAG.getUNDEF(SVT));
16078 ShOps.push_back(DAG.getUNDEF(SVT));
16080 MVT BVT = SVT == MVT::i32 ? MVT::v4i32 : MVT::v2i64;
16081 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, BVT, ShOps);
16084 // The return type has to be a 128-bit type with the same element
16085 // type as the input type.
16086 MVT EltVT = VT.getVectorElementType();
16087 MVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
16089 ShAmt = DAG.getBitcast(ShVT, ShAmt);
16090 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
16093 /// \brief Return Mask with the necessary casting or extending
16094 /// for \p Mask according to \p MaskVT when lowering masking intrinsics
16095 static SDValue getMaskNode(SDValue Mask, MVT MaskVT,
16096 const X86Subtarget *Subtarget,
16097 SelectionDAG &DAG, SDLoc dl) {
16099 if (MaskVT.bitsGT(Mask.getSimpleValueType())) {
16100 // Mask should be extended
16101 Mask = DAG.getNode(ISD::ANY_EXTEND, dl,
16102 MVT::getIntegerVT(MaskVT.getSizeInBits()), Mask);
16105 if (Mask.getSimpleValueType() == MVT::i64 && Subtarget->is32Bit()) {
16106 if (MaskVT == MVT::v64i1) {
16107 assert(Subtarget->hasBWI() && "Expected AVX512BW target!");
16108 // In case 32bit mode, bitcast i64 is illegal, extend/split it.
16110 Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Mask,
16111 DAG.getConstant(0, dl, MVT::i32));
16112 Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Mask,
16113 DAG.getConstant(1, dl, MVT::i32));
16115 Lo = DAG.getBitcast(MVT::v32i1, Lo);
16116 Hi = DAG.getBitcast(MVT::v32i1, Hi);
16118 return DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v64i1, Lo, Hi);
16120 // MaskVT require < 64bit. Truncate mask (should succeed in any case),
16122 MVT TruncVT = MVT::getIntegerVT(MaskVT.getSizeInBits());
16123 return DAG.getBitcast(MaskVT,
16124 DAG.getNode(ISD::TRUNCATE, dl, TruncVT, Mask));
16128 MVT BitcastVT = MVT::getVectorVT(MVT::i1,
16129 Mask.getSimpleValueType().getSizeInBits());
16130 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16131 // are extracted by EXTRACT_SUBVECTOR.
16132 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16133 DAG.getBitcast(BitcastVT, Mask),
16134 DAG.getIntPtrConstant(0, dl));
16138 /// \brief Return (and \p Op, \p Mask) for compare instructions or
16139 /// (vselect \p Mask, \p Op, \p PreservedSrc) for others along with the
16140 /// necessary casting or extending for \p Mask when lowering masking intrinsics
16141 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
16142 SDValue PreservedSrc,
16143 const X86Subtarget *Subtarget,
16144 SelectionDAG &DAG) {
16145 MVT VT = Op.getSimpleValueType();
16146 MVT MaskVT = MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
16147 unsigned OpcodeSelect = ISD::VSELECT;
16150 if (isAllOnesConstant(Mask))
16153 SDValue VMask = getMaskNode(Mask, MaskVT, Subtarget, DAG, dl);
16155 switch (Op.getOpcode()) {
16157 case X86ISD::PCMPEQM:
16158 case X86ISD::PCMPGTM:
16160 case X86ISD::CMPMU:
16161 return DAG.getNode(ISD::AND, dl, VT, Op, VMask);
16162 case X86ISD::VFPCLASS:
16163 case X86ISD::VFPCLASSS:
16164 return DAG.getNode(ISD::OR, dl, VT, Op, VMask);
16165 case X86ISD::VTRUNC:
16166 case X86ISD::VTRUNCS:
16167 case X86ISD::VTRUNCUS:
16168 // We can't use ISD::VSELECT here because it is not always "Legal"
16169 // for the destination type. For example vpmovqb require only AVX512
16170 // and vselect that can operate on byte element type require BWI
16171 OpcodeSelect = X86ISD::SELECT;
16174 if (PreservedSrc.getOpcode() == ISD::UNDEF)
16175 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
16176 return DAG.getNode(OpcodeSelect, dl, VT, VMask, Op, PreservedSrc);
16179 /// \brief Creates an SDNode for a predicated scalar operation.
16180 /// \returns (X86vselect \p Mask, \p Op, \p PreservedSrc).
16181 /// The mask is coming as MVT::i8 and it should be truncated
16182 /// to MVT::i1 while lowering masking intrinsics.
16183 /// The main difference between ScalarMaskingNode and VectorMaskingNode is using
16184 /// "X86select" instead of "vselect". We just can't create the "vselect" node
16185 /// for a scalar instruction.
16186 static SDValue getScalarMaskingNode(SDValue Op, SDValue Mask,
16187 SDValue PreservedSrc,
16188 const X86Subtarget *Subtarget,
16189 SelectionDAG &DAG) {
16190 if (isAllOnesConstant(Mask))
16193 MVT VT = Op.getSimpleValueType();
16195 // The mask should be of type MVT::i1
16196 SDValue IMask = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Mask);
16198 if (Op.getOpcode() == X86ISD::FSETCC)
16199 return DAG.getNode(ISD::AND, dl, VT, Op, IMask);
16200 if (Op.getOpcode() == X86ISD::VFPCLASS ||
16201 Op.getOpcode() == X86ISD::VFPCLASSS)
16202 return DAG.getNode(ISD::OR, dl, VT, Op, IMask);
16204 if (PreservedSrc.getOpcode() == ISD::UNDEF)
16205 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
16206 return DAG.getNode(X86ISD::SELECT, dl, VT, IMask, Op, PreservedSrc);
16209 static int getSEHRegistrationNodeSize(const Function *Fn) {
16210 if (!Fn->hasPersonalityFn())
16211 report_fatal_error(
16212 "querying registration node size for function without personality");
16213 // The RegNodeSize is 6 32-bit words for SEH and 4 for C++ EH. See
16214 // WinEHStatePass for the full struct definition.
16215 switch (classifyEHPersonality(Fn->getPersonalityFn())) {
16216 case EHPersonality::MSVC_X86SEH: return 24;
16217 case EHPersonality::MSVC_CXX: return 16;
16220 report_fatal_error(
16221 "can only recover FP for 32-bit MSVC EH personality functions");
16224 /// When the MSVC runtime transfers control to us, either to an outlined
16225 /// function or when returning to a parent frame after catching an exception, we
16226 /// recover the parent frame pointer by doing arithmetic on the incoming EBP.
16227 /// Here's the math:
16228 /// RegNodeBase = EntryEBP - RegNodeSize
16229 /// ParentFP = RegNodeBase - ParentFrameOffset
16230 /// Subtracting RegNodeSize takes us to the offset of the registration node, and
16231 /// subtracting the offset (negative on x86) takes us back to the parent FP.
16232 static SDValue recoverFramePointer(SelectionDAG &DAG, const Function *Fn,
16233 SDValue EntryEBP) {
16234 MachineFunction &MF = DAG.getMachineFunction();
16237 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16238 MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout());
16240 // It's possible that the parent function no longer has a personality function
16241 // if the exceptional code was optimized away, in which case we just return
16242 // the incoming EBP.
16243 if (!Fn->hasPersonalityFn())
16246 // Get an MCSymbol that will ultimately resolve to the frame offset of the EH
16247 // registration, or the .set_setframe offset.
16248 MCSymbol *OffsetSym =
16249 MF.getMMI().getContext().getOrCreateParentFrameOffsetSymbol(
16250 GlobalValue::getRealLinkageName(Fn->getName()));
16251 SDValue OffsetSymVal = DAG.getMCSymbol(OffsetSym, PtrVT);
16252 SDValue ParentFrameOffset =
16253 DAG.getNode(ISD::LOCAL_RECOVER, dl, PtrVT, OffsetSymVal);
16255 // Return EntryEBP + ParentFrameOffset for x64. This adjusts from RSP after
16256 // prologue to RBP in the parent function.
16257 const X86Subtarget &Subtarget =
16258 static_cast<const X86Subtarget &>(DAG.getSubtarget());
16259 if (Subtarget.is64Bit())
16260 return DAG.getNode(ISD::ADD, dl, PtrVT, EntryEBP, ParentFrameOffset);
16262 int RegNodeSize = getSEHRegistrationNodeSize(Fn);
16263 // RegNodeBase = EntryEBP - RegNodeSize
16264 // ParentFP = RegNodeBase - ParentFrameOffset
16265 SDValue RegNodeBase = DAG.getNode(ISD::SUB, dl, PtrVT, EntryEBP,
16266 DAG.getConstant(RegNodeSize, dl, PtrVT));
16267 return DAG.getNode(ISD::SUB, dl, PtrVT, RegNodeBase, ParentFrameOffset);
16270 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
16271 SelectionDAG &DAG) {
16273 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16274 MVT VT = Op.getSimpleValueType();
16275 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
16277 switch(IntrData->Type) {
16278 case INTR_TYPE_1OP:
16279 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
16280 case INTR_TYPE_2OP:
16281 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16283 case INTR_TYPE_2OP_IMM8:
16284 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16285 DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op.getOperand(2)));
16286 case INTR_TYPE_3OP:
16287 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16288 Op.getOperand(2), Op.getOperand(3));
16289 case INTR_TYPE_4OP:
16290 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16291 Op.getOperand(2), Op.getOperand(3), Op.getOperand(4));
16292 case INTR_TYPE_1OP_MASK_RM: {
16293 SDValue Src = Op.getOperand(1);
16294 SDValue PassThru = Op.getOperand(2);
16295 SDValue Mask = Op.getOperand(3);
16296 SDValue RoundingMode;
16297 // We allways add rounding mode to the Node.
16298 // If the rounding mode is not specified, we add the
16299 // "current direction" mode.
16300 if (Op.getNumOperands() == 4)
16302 DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
16304 RoundingMode = Op.getOperand(4);
16305 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16306 if (IntrWithRoundingModeOpcode != 0)
16307 if (cast<ConstantSDNode>(RoundingMode)->getZExtValue() !=
16308 X86::STATIC_ROUNDING::CUR_DIRECTION)
16309 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16310 dl, Op.getValueType(), Src, RoundingMode),
16311 Mask, PassThru, Subtarget, DAG);
16312 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src,
16314 Mask, PassThru, Subtarget, DAG);
16316 case INTR_TYPE_1OP_MASK: {
16317 SDValue Src = Op.getOperand(1);
16318 SDValue PassThru = Op.getOperand(2);
16319 SDValue Mask = Op.getOperand(3);
16320 // We add rounding mode to the Node when
16321 // - RM Opcode is specified and
16322 // - RM is not "current direction".
16323 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16324 if (IntrWithRoundingModeOpcode != 0) {
16325 SDValue Rnd = Op.getOperand(4);
16326 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
16327 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
16328 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16329 dl, Op.getValueType(),
16331 Mask, PassThru, Subtarget, DAG);
16334 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src),
16335 Mask, PassThru, Subtarget, DAG);
16337 case INTR_TYPE_SCALAR_MASK: {
16338 SDValue Src1 = Op.getOperand(1);
16339 SDValue Src2 = Op.getOperand(2);
16340 SDValue passThru = Op.getOperand(3);
16341 SDValue Mask = Op.getOperand(4);
16342 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2),
16343 Mask, passThru, Subtarget, DAG);
16345 case INTR_TYPE_SCALAR_MASK_RM: {
16346 SDValue Src1 = Op.getOperand(1);
16347 SDValue Src2 = Op.getOperand(2);
16348 SDValue Src0 = Op.getOperand(3);
16349 SDValue Mask = Op.getOperand(4);
16350 // There are 2 kinds of intrinsics in this group:
16351 // (1) With suppress-all-exceptions (sae) or rounding mode- 6 operands
16352 // (2) With rounding mode and sae - 7 operands.
16353 if (Op.getNumOperands() == 6) {
16354 SDValue Sae = Op.getOperand(5);
16355 unsigned Opc = IntrData->Opc1 ? IntrData->Opc1 : IntrData->Opc0;
16356 return getScalarMaskingNode(DAG.getNode(Opc, dl, VT, Src1, Src2,
16358 Mask, Src0, Subtarget, DAG);
16360 assert(Op.getNumOperands() == 7 && "Unexpected intrinsic form");
16361 SDValue RoundingMode = Op.getOperand(5);
16362 SDValue Sae = Op.getOperand(6);
16363 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2,
16364 RoundingMode, Sae),
16365 Mask, Src0, Subtarget, DAG);
16367 case INTR_TYPE_2OP_MASK:
16368 case INTR_TYPE_2OP_IMM8_MASK: {
16369 SDValue Src1 = Op.getOperand(1);
16370 SDValue Src2 = Op.getOperand(2);
16371 SDValue PassThru = Op.getOperand(3);
16372 SDValue Mask = Op.getOperand(4);
16374 if (IntrData->Type == INTR_TYPE_2OP_IMM8_MASK)
16375 Src2 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Src2);
16377 // We specify 2 possible opcodes for intrinsics with rounding modes.
16378 // First, we check if the intrinsic may have non-default rounding mode,
16379 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16380 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16381 if (IntrWithRoundingModeOpcode != 0) {
16382 SDValue Rnd = Op.getOperand(5);
16383 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
16384 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
16385 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16386 dl, Op.getValueType(),
16388 Mask, PassThru, Subtarget, DAG);
16391 // TODO: Intrinsics should have fast-math-flags to propagate.
16392 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,Src1,Src2),
16393 Mask, PassThru, Subtarget, DAG);
16395 case INTR_TYPE_2OP_MASK_RM: {
16396 SDValue Src1 = Op.getOperand(1);
16397 SDValue Src2 = Op.getOperand(2);
16398 SDValue PassThru = Op.getOperand(3);
16399 SDValue Mask = Op.getOperand(4);
16400 // We specify 2 possible modes for intrinsics, with/without rounding
16402 // First, we check if the intrinsic have rounding mode (6 operands),
16403 // if not, we set rounding mode to "current".
16405 if (Op.getNumOperands() == 6)
16406 Rnd = Op.getOperand(5);
16408 Rnd = DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
16409 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16411 Mask, PassThru, Subtarget, DAG);
16413 case INTR_TYPE_3OP_SCALAR_MASK_RM: {
16414 SDValue Src1 = Op.getOperand(1);
16415 SDValue Src2 = Op.getOperand(2);
16416 SDValue Src3 = Op.getOperand(3);
16417 SDValue PassThru = Op.getOperand(4);
16418 SDValue Mask = Op.getOperand(5);
16419 SDValue Sae = Op.getOperand(6);
16421 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1,
16423 Mask, PassThru, Subtarget, DAG);
16425 case INTR_TYPE_3OP_MASK_RM: {
16426 SDValue Src1 = Op.getOperand(1);
16427 SDValue Src2 = Op.getOperand(2);
16428 SDValue Imm = Op.getOperand(3);
16429 SDValue PassThru = Op.getOperand(4);
16430 SDValue Mask = Op.getOperand(5);
16431 // We specify 2 possible modes for intrinsics, with/without rounding
16433 // First, we check if the intrinsic have rounding mode (7 operands),
16434 // if not, we set rounding mode to "current".
16436 if (Op.getNumOperands() == 7)
16437 Rnd = Op.getOperand(6);
16439 Rnd = DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
16440 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16441 Src1, Src2, Imm, Rnd),
16442 Mask, PassThru, Subtarget, DAG);
16444 case INTR_TYPE_3OP_IMM8_MASK:
16445 case INTR_TYPE_3OP_MASK:
16446 case INSERT_SUBVEC: {
16447 SDValue Src1 = Op.getOperand(1);
16448 SDValue Src2 = Op.getOperand(2);
16449 SDValue Src3 = Op.getOperand(3);
16450 SDValue PassThru = Op.getOperand(4);
16451 SDValue Mask = Op.getOperand(5);
16453 if (IntrData->Type == INTR_TYPE_3OP_IMM8_MASK)
16454 Src3 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Src3);
16455 else if (IntrData->Type == INSERT_SUBVEC) {
16456 // imm should be adapted to ISD::INSERT_SUBVECTOR behavior
16457 assert(isa<ConstantSDNode>(Src3) && "Expected a ConstantSDNode here!");
16458 unsigned Imm = cast<ConstantSDNode>(Src3)->getZExtValue();
16459 Imm *= Src2.getSimpleValueType().getVectorNumElements();
16460 Src3 = DAG.getTargetConstant(Imm, dl, MVT::i32);
16463 // We specify 2 possible opcodes for intrinsics with rounding modes.
16464 // First, we check if the intrinsic may have non-default rounding mode,
16465 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16466 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16467 if (IntrWithRoundingModeOpcode != 0) {
16468 SDValue Rnd = Op.getOperand(6);
16469 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
16470 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
16471 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16472 dl, Op.getValueType(),
16473 Src1, Src2, Src3, Rnd),
16474 Mask, PassThru, Subtarget, DAG);
16477 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16479 Mask, PassThru, Subtarget, DAG);
16481 case VPERM_3OP_MASKZ:
16482 case VPERM_3OP_MASK:{
16483 // Src2 is the PassThru
16484 SDValue Src1 = Op.getOperand(1);
16485 SDValue Src2 = Op.getOperand(2);
16486 SDValue Src3 = Op.getOperand(3);
16487 SDValue Mask = Op.getOperand(4);
16488 MVT VT = Op.getSimpleValueType();
16489 SDValue PassThru = SDValue();
16491 // set PassThru element
16492 if (IntrData->Type == VPERM_3OP_MASKZ)
16493 PassThru = getZeroVector(VT, Subtarget, DAG, dl);
16495 PassThru = DAG.getBitcast(VT, Src2);
16497 // Swap Src1 and Src2 in the node creation
16498 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0,
16499 dl, Op.getValueType(),
16501 Mask, PassThru, Subtarget, DAG);
16505 case FMA_OP_MASK: {
16506 SDValue Src1 = Op.getOperand(1);
16507 SDValue Src2 = Op.getOperand(2);
16508 SDValue Src3 = Op.getOperand(3);
16509 SDValue Mask = Op.getOperand(4);
16510 MVT VT = Op.getSimpleValueType();
16511 SDValue PassThru = SDValue();
16513 // set PassThru element
16514 if (IntrData->Type == FMA_OP_MASKZ)
16515 PassThru = getZeroVector(VT, Subtarget, DAG, dl);
16516 else if (IntrData->Type == FMA_OP_MASK3)
16521 // We specify 2 possible opcodes for intrinsics with rounding modes.
16522 // First, we check if the intrinsic may have non-default rounding mode,
16523 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16524 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16525 if (IntrWithRoundingModeOpcode != 0) {
16526 SDValue Rnd = Op.getOperand(5);
16527 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
16528 X86::STATIC_ROUNDING::CUR_DIRECTION)
16529 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16530 dl, Op.getValueType(),
16531 Src1, Src2, Src3, Rnd),
16532 Mask, PassThru, Subtarget, DAG);
16534 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0,
16535 dl, Op.getValueType(),
16537 Mask, PassThru, Subtarget, DAG);
16539 case TERLOG_OP_MASK:
16540 case TERLOG_OP_MASKZ: {
16541 SDValue Src1 = Op.getOperand(1);
16542 SDValue Src2 = Op.getOperand(2);
16543 SDValue Src3 = Op.getOperand(3);
16544 SDValue Src4 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op.getOperand(4));
16545 SDValue Mask = Op.getOperand(5);
16546 MVT VT = Op.getSimpleValueType();
16547 SDValue PassThru = Src1;
16548 // Set PassThru element.
16549 if (IntrData->Type == TERLOG_OP_MASKZ)
16550 PassThru = getZeroVector(VT, Subtarget, DAG, dl);
16552 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16553 Src1, Src2, Src3, Src4),
16554 Mask, PassThru, Subtarget, DAG);
16557 // FPclass intrinsics with mask
16558 SDValue Src1 = Op.getOperand(1);
16559 MVT VT = Src1.getSimpleValueType();
16560 MVT MaskVT = MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
16561 SDValue Imm = Op.getOperand(2);
16562 SDValue Mask = Op.getOperand(3);
16563 MVT BitcastVT = MVT::getVectorVT(MVT::i1,
16564 Mask.getSimpleValueType().getSizeInBits());
16565 SDValue FPclass = DAG.getNode(IntrData->Opc0, dl, MaskVT, Src1, Imm);
16566 SDValue FPclassMask = getVectorMaskingNode(FPclass, Mask,
16567 DAG.getTargetConstant(0, dl, MaskVT),
16569 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
16570 DAG.getUNDEF(BitcastVT), FPclassMask,
16571 DAG.getIntPtrConstant(0, dl));
16572 return DAG.getBitcast(Op.getValueType(), Res);
16575 SDValue Src1 = Op.getOperand(1);
16576 SDValue Imm = Op.getOperand(2);
16577 SDValue Mask = Op.getOperand(3);
16578 SDValue FPclass = DAG.getNode(IntrData->Opc0, dl, MVT::i1, Src1, Imm);
16579 SDValue FPclassMask = getScalarMaskingNode(FPclass, Mask,
16580 DAG.getTargetConstant(0, dl, MVT::i1), Subtarget, DAG);
16581 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i8, FPclassMask);
16584 case CMP_MASK_CC: {
16585 // Comparison intrinsics with masks.
16586 // Example of transformation:
16587 // (i8 (int_x86_avx512_mask_pcmpeq_q_128
16588 // (v2i64 %a), (v2i64 %b), (i8 %mask))) ->
16590 // (v8i1 (insert_subvector undef,
16591 // (v2i1 (and (PCMPEQM %a, %b),
16592 // (extract_subvector
16593 // (v8i1 (bitcast %mask)), 0))), 0))))
16594 MVT VT = Op.getOperand(1).getSimpleValueType();
16595 MVT MaskVT = MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
16596 SDValue Mask = Op.getOperand((IntrData->Type == CMP_MASK_CC) ? 4 : 3);
16597 MVT BitcastVT = MVT::getVectorVT(MVT::i1,
16598 Mask.getSimpleValueType().getSizeInBits());
16600 if (IntrData->Type == CMP_MASK_CC) {
16601 SDValue CC = Op.getOperand(3);
16602 CC = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, CC);
16603 // We specify 2 possible opcodes for intrinsics with rounding modes.
16604 // First, we check if the intrinsic may have non-default rounding mode,
16605 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16606 if (IntrData->Opc1 != 0) {
16607 SDValue Rnd = Op.getOperand(5);
16608 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
16609 X86::STATIC_ROUNDING::CUR_DIRECTION)
16610 Cmp = DAG.getNode(IntrData->Opc1, dl, MaskVT, Op.getOperand(1),
16611 Op.getOperand(2), CC, Rnd);
16613 //default rounding mode
16615 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16616 Op.getOperand(2), CC);
16619 assert(IntrData->Type == CMP_MASK && "Unexpected intrinsic type!");
16620 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16623 SDValue CmpMask = getVectorMaskingNode(Cmp, Mask,
16624 DAG.getTargetConstant(0, dl,
16627 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
16628 DAG.getUNDEF(BitcastVT), CmpMask,
16629 DAG.getIntPtrConstant(0, dl));
16630 return DAG.getBitcast(Op.getValueType(), Res);
16632 case CMP_MASK_SCALAR_CC: {
16633 SDValue Src1 = Op.getOperand(1);
16634 SDValue Src2 = Op.getOperand(2);
16635 SDValue CC = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op.getOperand(3));
16636 SDValue Mask = Op.getOperand(4);
16639 if (IntrData->Opc1 != 0) {
16640 SDValue Rnd = Op.getOperand(5);
16641 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
16642 X86::STATIC_ROUNDING::CUR_DIRECTION)
16643 Cmp = DAG.getNode(IntrData->Opc1, dl, MVT::i1, Src1, Src2, CC, Rnd);
16645 //default rounding mode
16647 Cmp = DAG.getNode(IntrData->Opc0, dl, MVT::i1, Src1, Src2, CC);
16649 SDValue CmpMask = getScalarMaskingNode(Cmp, Mask,
16650 DAG.getTargetConstant(0, dl,
16654 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::i8,
16655 DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i8, CmpMask),
16656 DAG.getValueType(MVT::i1));
16658 case COMI: { // Comparison intrinsics
16659 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
16660 SDValue LHS = Op.getOperand(1);
16661 SDValue RHS = Op.getOperand(2);
16662 unsigned X86CC = TranslateX86CC(CC, dl, true, LHS, RHS, DAG);
16663 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
16664 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
16665 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16666 DAG.getConstant(X86CC, dl, MVT::i8), Cond);
16667 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16669 case COMI_RM: { // Comparison intrinsics with Sae
16670 SDValue LHS = Op.getOperand(1);
16671 SDValue RHS = Op.getOperand(2);
16672 SDValue CC = Op.getOperand(3);
16673 SDValue Sae = Op.getOperand(4);
16674 auto ComiType = TranslateX86ConstCondToX86CC(CC);
16675 // choose between ordered and unordered (comi/ucomi)
16676 unsigned comiOp = std::get<0>(ComiType) ? IntrData->Opc0 : IntrData->Opc1;
16678 if (cast<ConstantSDNode>(Sae)->getZExtValue() !=
16679 X86::STATIC_ROUNDING::CUR_DIRECTION)
16680 Cond = DAG.getNode(comiOp, dl, MVT::i32, LHS, RHS, Sae);
16682 Cond = DAG.getNode(comiOp, dl, MVT::i32, LHS, RHS);
16683 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16684 DAG.getConstant(std::get<1>(ComiType), dl, MVT::i8), Cond);
16685 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16688 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
16689 Op.getOperand(1), Op.getOperand(2), DAG);
16691 return getVectorMaskingNode(getTargetVShiftNode(IntrData->Opc0, dl,
16692 Op.getSimpleValueType(),
16694 Op.getOperand(2), DAG),
16695 Op.getOperand(4), Op.getOperand(3), Subtarget,
16697 case COMPRESS_EXPAND_IN_REG: {
16698 SDValue Mask = Op.getOperand(3);
16699 SDValue DataToCompress = Op.getOperand(1);
16700 SDValue PassThru = Op.getOperand(2);
16701 if (isAllOnesConstant(Mask)) // return data as is
16702 return Op.getOperand(1);
16704 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16706 Mask, PassThru, Subtarget, DAG);
16709 SDValue Mask = Op.getOperand(1);
16710 MVT MaskVT = MVT::getVectorVT(MVT::i1, Mask.getSimpleValueType().getSizeInBits());
16711 Mask = DAG.getBitcast(MaskVT, Mask);
16712 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Mask);
16715 SDValue Mask = Op.getOperand(3);
16716 MVT VT = Op.getSimpleValueType();
16717 MVT MaskVT = MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
16718 SDValue VMask = getMaskNode(Mask, MaskVT, Subtarget, DAG, dl);
16719 return DAG.getNode(IntrData->Opc0, dl, VT, VMask, Op.getOperand(1),
16723 MVT VT = Op.getSimpleValueType();
16724 MVT MaskVT = MVT::getVectorVT(MVT::i1, VT.getSizeInBits()/2);
16726 SDValue Src1 = getMaskNode(Op.getOperand(1), MaskVT, Subtarget, DAG, dl);
16727 SDValue Src2 = getMaskNode(Op.getOperand(2), MaskVT, Subtarget, DAG, dl);
16728 // Arguments should be swapped.
16729 SDValue Res = DAG.getNode(IntrData->Opc0, dl,
16730 MVT::getVectorVT(MVT::i1, VT.getSizeInBits()),
16732 return DAG.getBitcast(VT, Res);
16740 default: return SDValue(); // Don't custom lower most intrinsics.
16742 case Intrinsic::x86_avx2_permd:
16743 case Intrinsic::x86_avx2_permps:
16744 // Operands intentionally swapped. Mask is last operand to intrinsic,
16745 // but second operand for node/instruction.
16746 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
16747 Op.getOperand(2), Op.getOperand(1));
16749 // ptest and testp intrinsics. The intrinsic these come from are designed to
16750 // return an integer value, not just an instruction so lower it to the ptest
16751 // or testp pattern and a setcc for the result.
16752 case Intrinsic::x86_sse41_ptestz:
16753 case Intrinsic::x86_sse41_ptestc:
16754 case Intrinsic::x86_sse41_ptestnzc:
16755 case Intrinsic::x86_avx_ptestz_256:
16756 case Intrinsic::x86_avx_ptestc_256:
16757 case Intrinsic::x86_avx_ptestnzc_256:
16758 case Intrinsic::x86_avx_vtestz_ps:
16759 case Intrinsic::x86_avx_vtestc_ps:
16760 case Intrinsic::x86_avx_vtestnzc_ps:
16761 case Intrinsic::x86_avx_vtestz_pd:
16762 case Intrinsic::x86_avx_vtestc_pd:
16763 case Intrinsic::x86_avx_vtestnzc_pd:
16764 case Intrinsic::x86_avx_vtestz_ps_256:
16765 case Intrinsic::x86_avx_vtestc_ps_256:
16766 case Intrinsic::x86_avx_vtestnzc_ps_256:
16767 case Intrinsic::x86_avx_vtestz_pd_256:
16768 case Intrinsic::x86_avx_vtestc_pd_256:
16769 case Intrinsic::x86_avx_vtestnzc_pd_256: {
16770 bool IsTestPacked = false;
16773 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
16774 case Intrinsic::x86_avx_vtestz_ps:
16775 case Intrinsic::x86_avx_vtestz_pd:
16776 case Intrinsic::x86_avx_vtestz_ps_256:
16777 case Intrinsic::x86_avx_vtestz_pd_256:
16778 IsTestPacked = true; // Fallthrough
16779 case Intrinsic::x86_sse41_ptestz:
16780 case Intrinsic::x86_avx_ptestz_256:
16782 X86CC = X86::COND_E;
16784 case Intrinsic::x86_avx_vtestc_ps:
16785 case Intrinsic::x86_avx_vtestc_pd:
16786 case Intrinsic::x86_avx_vtestc_ps_256:
16787 case Intrinsic::x86_avx_vtestc_pd_256:
16788 IsTestPacked = true; // Fallthrough
16789 case Intrinsic::x86_sse41_ptestc:
16790 case Intrinsic::x86_avx_ptestc_256:
16792 X86CC = X86::COND_B;
16794 case Intrinsic::x86_avx_vtestnzc_ps:
16795 case Intrinsic::x86_avx_vtestnzc_pd:
16796 case Intrinsic::x86_avx_vtestnzc_ps_256:
16797 case Intrinsic::x86_avx_vtestnzc_pd_256:
16798 IsTestPacked = true; // Fallthrough
16799 case Intrinsic::x86_sse41_ptestnzc:
16800 case Intrinsic::x86_avx_ptestnzc_256:
16802 X86CC = X86::COND_A;
16806 SDValue LHS = Op.getOperand(1);
16807 SDValue RHS = Op.getOperand(2);
16808 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
16809 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
16810 SDValue CC = DAG.getConstant(X86CC, dl, MVT::i8);
16811 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
16812 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16814 case Intrinsic::x86_avx512_kortestz_w:
16815 case Intrinsic::x86_avx512_kortestc_w: {
16816 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
16817 SDValue LHS = DAG.getBitcast(MVT::v16i1, Op.getOperand(1));
16818 SDValue RHS = DAG.getBitcast(MVT::v16i1, Op.getOperand(2));
16819 SDValue CC = DAG.getConstant(X86CC, dl, MVT::i8);
16820 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
16821 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
16822 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16825 case Intrinsic::x86_sse42_pcmpistria128:
16826 case Intrinsic::x86_sse42_pcmpestria128:
16827 case Intrinsic::x86_sse42_pcmpistric128:
16828 case Intrinsic::x86_sse42_pcmpestric128:
16829 case Intrinsic::x86_sse42_pcmpistrio128:
16830 case Intrinsic::x86_sse42_pcmpestrio128:
16831 case Intrinsic::x86_sse42_pcmpistris128:
16832 case Intrinsic::x86_sse42_pcmpestris128:
16833 case Intrinsic::x86_sse42_pcmpistriz128:
16834 case Intrinsic::x86_sse42_pcmpestriz128: {
16838 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16839 case Intrinsic::x86_sse42_pcmpistria128:
16840 Opcode = X86ISD::PCMPISTRI;
16841 X86CC = X86::COND_A;
16843 case Intrinsic::x86_sse42_pcmpestria128:
16844 Opcode = X86ISD::PCMPESTRI;
16845 X86CC = X86::COND_A;
16847 case Intrinsic::x86_sse42_pcmpistric128:
16848 Opcode = X86ISD::PCMPISTRI;
16849 X86CC = X86::COND_B;
16851 case Intrinsic::x86_sse42_pcmpestric128:
16852 Opcode = X86ISD::PCMPESTRI;
16853 X86CC = X86::COND_B;
16855 case Intrinsic::x86_sse42_pcmpistrio128:
16856 Opcode = X86ISD::PCMPISTRI;
16857 X86CC = X86::COND_O;
16859 case Intrinsic::x86_sse42_pcmpestrio128:
16860 Opcode = X86ISD::PCMPESTRI;
16861 X86CC = X86::COND_O;
16863 case Intrinsic::x86_sse42_pcmpistris128:
16864 Opcode = X86ISD::PCMPISTRI;
16865 X86CC = X86::COND_S;
16867 case Intrinsic::x86_sse42_pcmpestris128:
16868 Opcode = X86ISD::PCMPESTRI;
16869 X86CC = X86::COND_S;
16871 case Intrinsic::x86_sse42_pcmpistriz128:
16872 Opcode = X86ISD::PCMPISTRI;
16873 X86CC = X86::COND_E;
16875 case Intrinsic::x86_sse42_pcmpestriz128:
16876 Opcode = X86ISD::PCMPESTRI;
16877 X86CC = X86::COND_E;
16880 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
16881 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
16882 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
16883 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16884 DAG.getConstant(X86CC, dl, MVT::i8),
16885 SDValue(PCMP.getNode(), 1));
16886 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16889 case Intrinsic::x86_sse42_pcmpistri128:
16890 case Intrinsic::x86_sse42_pcmpestri128: {
16892 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
16893 Opcode = X86ISD::PCMPISTRI;
16895 Opcode = X86ISD::PCMPESTRI;
16897 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
16898 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
16899 return DAG.getNode(Opcode, dl, VTs, NewOps);
16902 case Intrinsic::x86_seh_lsda: {
16903 // Compute the symbol for the LSDA. We know it'll get emitted later.
16904 MachineFunction &MF = DAG.getMachineFunction();
16905 SDValue Op1 = Op.getOperand(1);
16906 auto *Fn = cast<Function>(cast<GlobalAddressSDNode>(Op1)->getGlobal());
16907 MCSymbol *LSDASym = MF.getMMI().getContext().getOrCreateLSDASymbol(
16908 GlobalValue::getRealLinkageName(Fn->getName()));
16910 // Generate a simple absolute symbol reference. This intrinsic is only
16911 // supported on 32-bit Windows, which isn't PIC.
16912 SDValue Result = DAG.getMCSymbol(LSDASym, VT);
16913 return DAG.getNode(X86ISD::Wrapper, dl, VT, Result);
16916 case Intrinsic::x86_seh_recoverfp: {
16917 SDValue FnOp = Op.getOperand(1);
16918 SDValue IncomingFPOp = Op.getOperand(2);
16919 GlobalAddressSDNode *GSD = dyn_cast<GlobalAddressSDNode>(FnOp);
16920 auto *Fn = dyn_cast_or_null<Function>(GSD ? GSD->getGlobal() : nullptr);
16922 report_fatal_error(
16923 "llvm.x86.seh.recoverfp must take a function as the first argument");
16924 return recoverFramePointer(DAG, Fn, IncomingFPOp);
16927 case Intrinsic::localaddress: {
16928 // Returns one of the stack, base, or frame pointer registers, depending on
16929 // which is used to reference local variables.
16930 MachineFunction &MF = DAG.getMachineFunction();
16931 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
16933 if (RegInfo->hasBasePointer(MF))
16934 Reg = RegInfo->getBaseRegister();
16935 else // This function handles the SP or FP case.
16936 Reg = RegInfo->getPtrSizedFrameRegister(MF);
16937 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
16942 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16943 SDValue Src, SDValue Mask, SDValue Base,
16944 SDValue Index, SDValue ScaleOp, SDValue Chain,
16945 const X86Subtarget * Subtarget) {
16947 auto *C = cast<ConstantSDNode>(ScaleOp);
16948 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
16949 MVT MaskVT = MVT::getVectorVT(MVT::i1,
16950 Index.getSimpleValueType().getVectorNumElements());
16952 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16954 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
16956 MVT BitcastVT = MVT::getVectorVT(MVT::i1,
16957 Mask.getSimpleValueType().getSizeInBits());
16959 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16960 // are extracted by EXTRACT_SUBVECTOR.
16961 MaskInReg = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16962 DAG.getBitcast(BitcastVT, Mask),
16963 DAG.getIntPtrConstant(0, dl));
16965 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
16966 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
16967 SDValue Segment = DAG.getRegister(0, MVT::i32);
16968 if (Src.getOpcode() == ISD::UNDEF)
16969 Src = getZeroVector(Op.getSimpleValueType(), Subtarget, DAG, dl);
16970 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
16971 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
16972 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
16973 return DAG.getMergeValues(RetOps, dl);
16976 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16977 SDValue Src, SDValue Mask, SDValue Base,
16978 SDValue Index, SDValue ScaleOp, SDValue Chain) {
16980 auto *C = cast<ConstantSDNode>(ScaleOp);
16981 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
16982 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
16983 SDValue Segment = DAG.getRegister(0, MVT::i32);
16984 MVT MaskVT = MVT::getVectorVT(MVT::i1,
16985 Index.getSimpleValueType().getVectorNumElements());
16987 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16989 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
16991 MVT BitcastVT = MVT::getVectorVT(MVT::i1,
16992 Mask.getSimpleValueType().getSizeInBits());
16994 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16995 // are extracted by EXTRACT_SUBVECTOR.
16996 MaskInReg = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16997 DAG.getBitcast(BitcastVT, Mask),
16998 DAG.getIntPtrConstant(0, dl));
17000 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
17001 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
17002 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
17003 return SDValue(Res, 1);
17006 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
17007 SDValue Mask, SDValue Base, SDValue Index,
17008 SDValue ScaleOp, SDValue Chain) {
17010 auto *C = cast<ConstantSDNode>(ScaleOp);
17011 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
17012 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
17013 SDValue Segment = DAG.getRegister(0, MVT::i32);
17015 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
17017 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
17019 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
17021 MaskInReg = DAG.getBitcast(MaskVT, Mask);
17022 //SDVTList VTs = DAG.getVTList(MVT::Other);
17023 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
17024 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
17025 return SDValue(Res, 0);
17028 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
17029 // read performance monitor counters (x86_rdpmc).
17030 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
17031 SelectionDAG &DAG, const X86Subtarget *Subtarget,
17032 SmallVectorImpl<SDValue> &Results) {
17033 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
17034 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17037 // The ECX register is used to select the index of the performance counter
17039 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
17041 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
17043 // Reads the content of a 64-bit performance counter and returns it in the
17044 // registers EDX:EAX.
17045 if (Subtarget->is64Bit()) {
17046 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
17047 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
17050 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
17051 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
17054 Chain = HI.getValue(1);
17056 if (Subtarget->is64Bit()) {
17057 // The EAX register is loaded with the low-order 32 bits. The EDX register
17058 // is loaded with the supported high-order bits of the counter.
17059 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
17060 DAG.getConstant(32, DL, MVT::i8));
17061 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
17062 Results.push_back(Chain);
17066 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
17067 SDValue Ops[] = { LO, HI };
17068 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
17069 Results.push_back(Pair);
17070 Results.push_back(Chain);
17073 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
17074 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
17075 // also used to custom lower READCYCLECOUNTER nodes.
17076 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
17077 SelectionDAG &DAG, const X86Subtarget *Subtarget,
17078 SmallVectorImpl<SDValue> &Results) {
17079 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17080 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
17083 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
17084 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
17085 // and the EAX register is loaded with the low-order 32 bits.
17086 if (Subtarget->is64Bit()) {
17087 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
17088 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
17091 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
17092 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
17095 SDValue Chain = HI.getValue(1);
17097 if (Opcode == X86ISD::RDTSCP_DAG) {
17098 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
17100 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
17101 // the ECX register. Add 'ecx' explicitly to the chain.
17102 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
17104 // Explicitly store the content of ECX at the location passed in input
17105 // to the 'rdtscp' intrinsic.
17106 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
17107 MachinePointerInfo(), false, false, 0);
17110 if (Subtarget->is64Bit()) {
17111 // The EDX register is loaded with the high-order 32 bits of the MSR, and
17112 // the EAX register is loaded with the low-order 32 bits.
17113 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
17114 DAG.getConstant(32, DL, MVT::i8));
17115 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
17116 Results.push_back(Chain);
17120 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
17121 SDValue Ops[] = { LO, HI };
17122 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
17123 Results.push_back(Pair);
17124 Results.push_back(Chain);
17127 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
17128 SelectionDAG &DAG) {
17129 SmallVector<SDValue, 2> Results;
17131 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
17133 return DAG.getMergeValues(Results, DL);
17136 static SDValue MarkEHRegistrationNode(SDValue Op, SelectionDAG &DAG) {
17137 MachineFunction &MF = DAG.getMachineFunction();
17138 SDValue Chain = Op.getOperand(0);
17139 SDValue RegNode = Op.getOperand(2);
17140 WinEHFuncInfo *EHInfo = MF.getWinEHFuncInfo();
17142 report_fatal_error("EH registrations only live in functions using WinEH");
17144 // Cast the operand to an alloca, and remember the frame index.
17145 auto *FINode = dyn_cast<FrameIndexSDNode>(RegNode);
17147 report_fatal_error("llvm.x86.seh.ehregnode expects a static alloca");
17148 EHInfo->EHRegNodeFrameIndex = FINode->getIndex();
17150 // Return the chain operand without making any DAG nodes.
17154 /// \brief Lower intrinsics for TRUNCATE_TO_MEM case
17155 /// return truncate Store/MaskedStore Node
17156 static SDValue LowerINTRINSIC_TRUNCATE_TO_MEM(const SDValue & Op,
17160 SDValue Mask = Op.getOperand(4);
17161 SDValue DataToTruncate = Op.getOperand(3);
17162 SDValue Addr = Op.getOperand(2);
17163 SDValue Chain = Op.getOperand(0);
17165 MVT VT = DataToTruncate.getSimpleValueType();
17166 MVT SVT = MVT::getVectorVT(ElementType, VT.getVectorNumElements());
17168 if (isAllOnesConstant(Mask)) // return just a truncate store
17169 return DAG.getTruncStore(Chain, dl, DataToTruncate, Addr,
17170 MachinePointerInfo(), SVT, false, false,
17171 SVT.getScalarSizeInBits()/8);
17173 MVT MaskVT = MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
17174 MVT BitcastVT = MVT::getVectorVT(MVT::i1,
17175 Mask.getSimpleValueType().getSizeInBits());
17176 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
17177 // are extracted by EXTRACT_SUBVECTOR.
17178 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
17179 DAG.getBitcast(BitcastVT, Mask),
17180 DAG.getIntPtrConstant(0, dl));
17182 MachineMemOperand *MMO = DAG.getMachineFunction().
17183 getMachineMemOperand(MachinePointerInfo(),
17184 MachineMemOperand::MOStore, SVT.getStoreSize(),
17185 SVT.getScalarSizeInBits()/8);
17187 return DAG.getMaskedStore(Chain, dl, DataToTruncate, Addr,
17188 VMask, SVT, MMO, true);
17191 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
17192 SelectionDAG &DAG) {
17193 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
17195 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
17197 if (IntNo == llvm::Intrinsic::x86_seh_ehregnode)
17198 return MarkEHRegistrationNode(Op, DAG);
17203 switch(IntrData->Type) {
17204 default: llvm_unreachable("Unknown Intrinsic Type");
17207 // Emit the node with the right value type.
17208 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
17209 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
17211 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
17212 // Otherwise return the value from Rand, which is always 0, casted to i32.
17213 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
17214 DAG.getConstant(1, dl, Op->getValueType(1)),
17215 DAG.getConstant(X86::COND_B, dl, MVT::i32),
17216 SDValue(Result.getNode(), 1) };
17217 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
17218 DAG.getVTList(Op->getValueType(1), MVT::Glue),
17221 // Return { result, isValid, chain }.
17222 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
17223 SDValue(Result.getNode(), 2));
17226 //gather(v1, mask, index, base, scale);
17227 SDValue Chain = Op.getOperand(0);
17228 SDValue Src = Op.getOperand(2);
17229 SDValue Base = Op.getOperand(3);
17230 SDValue Index = Op.getOperand(4);
17231 SDValue Mask = Op.getOperand(5);
17232 SDValue Scale = Op.getOperand(6);
17233 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale,
17237 //scatter(base, mask, index, v1, scale);
17238 SDValue Chain = Op.getOperand(0);
17239 SDValue Base = Op.getOperand(2);
17240 SDValue Mask = Op.getOperand(3);
17241 SDValue Index = Op.getOperand(4);
17242 SDValue Src = Op.getOperand(5);
17243 SDValue Scale = Op.getOperand(6);
17244 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index,
17248 SDValue Hint = Op.getOperand(6);
17249 unsigned HintVal = cast<ConstantSDNode>(Hint)->getZExtValue();
17250 assert(HintVal < 2 && "Wrong prefetch hint in intrinsic: should be 0 or 1");
17251 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
17252 SDValue Chain = Op.getOperand(0);
17253 SDValue Mask = Op.getOperand(2);
17254 SDValue Index = Op.getOperand(3);
17255 SDValue Base = Op.getOperand(4);
17256 SDValue Scale = Op.getOperand(5);
17257 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
17259 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
17261 SmallVector<SDValue, 2> Results;
17262 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget,
17264 return DAG.getMergeValues(Results, dl);
17266 // Read Performance Monitoring Counters.
17268 SmallVector<SDValue, 2> Results;
17269 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
17270 return DAG.getMergeValues(Results, dl);
17272 // XTEST intrinsics.
17274 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17275 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
17276 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17277 DAG.getConstant(X86::COND_NE, dl, MVT::i8),
17279 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
17280 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
17281 Ret, SDValue(InTrans.getNode(), 1));
17285 SmallVector<SDValue, 2> Results;
17286 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17287 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
17288 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
17289 DAG.getConstant(-1, dl, MVT::i8));
17290 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
17291 Op.getOperand(4), GenCF.getValue(1));
17292 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
17293 Op.getOperand(5), MachinePointerInfo(),
17295 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17296 DAG.getConstant(X86::COND_B, dl, MVT::i8),
17298 Results.push_back(SetCC);
17299 Results.push_back(Store);
17300 return DAG.getMergeValues(Results, dl);
17302 case COMPRESS_TO_MEM: {
17304 SDValue Mask = Op.getOperand(4);
17305 SDValue DataToCompress = Op.getOperand(3);
17306 SDValue Addr = Op.getOperand(2);
17307 SDValue Chain = Op.getOperand(0);
17309 MVT VT = DataToCompress.getSimpleValueType();
17310 if (isAllOnesConstant(Mask)) // return just a store
17311 return DAG.getStore(Chain, dl, DataToCompress, Addr,
17312 MachinePointerInfo(), false, false,
17313 VT.getScalarSizeInBits()/8);
17315 SDValue Compressed =
17316 getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, DataToCompress),
17317 Mask, DAG.getUNDEF(VT), Subtarget, DAG);
17318 return DAG.getStore(Chain, dl, Compressed, Addr,
17319 MachinePointerInfo(), false, false,
17320 VT.getScalarSizeInBits()/8);
17322 case TRUNCATE_TO_MEM_VI8:
17323 return LowerINTRINSIC_TRUNCATE_TO_MEM(Op, DAG, MVT::i8);
17324 case TRUNCATE_TO_MEM_VI16:
17325 return LowerINTRINSIC_TRUNCATE_TO_MEM(Op, DAG, MVT::i16);
17326 case TRUNCATE_TO_MEM_VI32:
17327 return LowerINTRINSIC_TRUNCATE_TO_MEM(Op, DAG, MVT::i32);
17328 case EXPAND_FROM_MEM: {
17330 SDValue Mask = Op.getOperand(4);
17331 SDValue PassThru = Op.getOperand(3);
17332 SDValue Addr = Op.getOperand(2);
17333 SDValue Chain = Op.getOperand(0);
17334 MVT VT = Op.getSimpleValueType();
17336 if (isAllOnesConstant(Mask)) // return just a load
17337 return DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(), false, false,
17338 false, VT.getScalarSizeInBits()/8);
17340 SDValue DataToExpand = DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(),
17341 false, false, false,
17342 VT.getScalarSizeInBits()/8);
17344 SDValue Results[] = {
17345 getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, DataToExpand),
17346 Mask, PassThru, Subtarget, DAG), Chain};
17347 return DAG.getMergeValues(Results, dl);
17352 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
17353 SelectionDAG &DAG) const {
17354 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
17355 MFI->setReturnAddressIsTaken(true);
17357 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
17360 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17362 EVT PtrVT = getPointerTy(DAG.getDataLayout());
17365 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
17366 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17367 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), dl, PtrVT);
17368 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17369 DAG.getNode(ISD::ADD, dl, PtrVT,
17370 FrameAddr, Offset),
17371 MachinePointerInfo(), false, false, false, 0);
17374 // Just load the return address.
17375 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
17376 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17377 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
17380 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
17381 MachineFunction &MF = DAG.getMachineFunction();
17382 MachineFrameInfo *MFI = MF.getFrameInfo();
17383 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
17384 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17385 EVT VT = Op.getValueType();
17387 MFI->setFrameAddressIsTaken(true);
17389 if (MF.getTarget().getMCAsmInfo()->usesWindowsCFI()) {
17390 // Depth > 0 makes no sense on targets which use Windows unwind codes. It
17391 // is not possible to crawl up the stack without looking at the unwind codes
17393 int FrameAddrIndex = FuncInfo->getFAIndex();
17394 if (!FrameAddrIndex) {
17395 // Set up a frame object for the return address.
17396 unsigned SlotSize = RegInfo->getSlotSize();
17397 FrameAddrIndex = MF.getFrameInfo()->CreateFixedObject(
17398 SlotSize, /*Offset=*/0, /*IsImmutable=*/false);
17399 FuncInfo->setFAIndex(FrameAddrIndex);
17401 return DAG.getFrameIndex(FrameAddrIndex, VT);
17404 unsigned FrameReg =
17405 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
17406 SDLoc dl(Op); // FIXME probably not meaningful
17407 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17408 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
17409 (FrameReg == X86::EBP && VT == MVT::i32)) &&
17410 "Invalid Frame Register!");
17411 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
17413 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
17414 MachinePointerInfo(),
17415 false, false, false, 0);
17419 // FIXME? Maybe this could be a TableGen attribute on some registers and
17420 // this table could be generated automatically from RegInfo.
17421 unsigned X86TargetLowering::getRegisterByName(const char* RegName, EVT VT,
17422 SelectionDAG &DAG) const {
17423 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
17424 const MachineFunction &MF = DAG.getMachineFunction();
17426 unsigned Reg = StringSwitch<unsigned>(RegName)
17427 .Case("esp", X86::ESP)
17428 .Case("rsp", X86::RSP)
17429 .Case("ebp", X86::EBP)
17430 .Case("rbp", X86::RBP)
17433 if (Reg == X86::EBP || Reg == X86::RBP) {
17434 if (!TFI.hasFP(MF))
17435 report_fatal_error("register " + StringRef(RegName) +
17436 " is allocatable: function has no frame pointer");
17439 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17440 unsigned FrameReg =
17441 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
17442 assert((FrameReg == X86::EBP || FrameReg == X86::RBP) &&
17443 "Invalid Frame Register!");
17451 report_fatal_error("Invalid register name global variable");
17454 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
17455 SelectionDAG &DAG) const {
17456 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17457 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize(), SDLoc(Op));
17460 unsigned X86TargetLowering::getExceptionPointerRegister(
17461 const Constant *PersonalityFn) const {
17462 if (classifyEHPersonality(PersonalityFn) == EHPersonality::CoreCLR)
17463 return Subtarget->isTarget64BitLP64() ? X86::RDX : X86::EDX;
17465 return Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX;
17468 unsigned X86TargetLowering::getExceptionSelectorRegister(
17469 const Constant *PersonalityFn) const {
17470 // Funclet personalities don't use selectors (the runtime does the selection).
17471 assert(!isFuncletEHPersonality(classifyEHPersonality(PersonalityFn)));
17472 return Subtarget->isTarget64BitLP64() ? X86::RDX : X86::EDX;
17475 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
17476 SDValue Chain = Op.getOperand(0);
17477 SDValue Offset = Op.getOperand(1);
17478 SDValue Handler = Op.getOperand(2);
17481 EVT PtrVT = getPointerTy(DAG.getDataLayout());
17482 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17483 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
17484 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
17485 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
17486 "Invalid Frame Register!");
17487 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
17488 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
17490 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
17491 DAG.getIntPtrConstant(RegInfo->getSlotSize(),
17493 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
17494 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
17496 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
17498 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
17499 DAG.getRegister(StoreAddrReg, PtrVT));
17502 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
17503 SelectionDAG &DAG) const {
17505 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
17506 DAG.getVTList(MVT::i32, MVT::Other),
17507 Op.getOperand(0), Op.getOperand(1));
17510 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
17511 SelectionDAG &DAG) const {
17513 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
17514 Op.getOperand(0), Op.getOperand(1));
17517 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
17518 return Op.getOperand(0);
17521 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
17522 SelectionDAG &DAG) const {
17523 SDValue Root = Op.getOperand(0);
17524 SDValue Trmp = Op.getOperand(1); // trampoline
17525 SDValue FPtr = Op.getOperand(2); // nested function
17526 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
17529 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
17530 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
17532 if (Subtarget->is64Bit()) {
17533 SDValue OutChains[6];
17535 // Large code-model.
17536 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
17537 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
17539 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
17540 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
17542 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
17544 // Load the pointer to the nested function into R11.
17545 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
17546 SDValue Addr = Trmp;
17547 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
17548 Addr, MachinePointerInfo(TrmpAddr),
17551 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17552 DAG.getConstant(2, dl, MVT::i64));
17553 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
17554 MachinePointerInfo(TrmpAddr, 2),
17557 // Load the 'nest' parameter value into R10.
17558 // R10 is specified in X86CallingConv.td
17559 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
17560 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17561 DAG.getConstant(10, dl, MVT::i64));
17562 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
17563 Addr, MachinePointerInfo(TrmpAddr, 10),
17566 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17567 DAG.getConstant(12, dl, MVT::i64));
17568 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
17569 MachinePointerInfo(TrmpAddr, 12),
17572 // Jump to the nested function.
17573 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
17574 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17575 DAG.getConstant(20, dl, MVT::i64));
17576 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
17577 Addr, MachinePointerInfo(TrmpAddr, 20),
17580 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
17581 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17582 DAG.getConstant(22, dl, MVT::i64));
17583 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, dl, MVT::i8),
17584 Addr, MachinePointerInfo(TrmpAddr, 22),
17587 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17589 const Function *Func =
17590 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
17591 CallingConv::ID CC = Func->getCallingConv();
17596 llvm_unreachable("Unsupported calling convention");
17597 case CallingConv::C:
17598 case CallingConv::X86_StdCall: {
17599 // Pass 'nest' parameter in ECX.
17600 // Must be kept in sync with X86CallingConv.td
17601 NestReg = X86::ECX;
17603 // Check that ECX wasn't needed by an 'inreg' parameter.
17604 FunctionType *FTy = Func->getFunctionType();
17605 const AttributeSet &Attrs = Func->getAttributes();
17607 if (!Attrs.isEmpty() && !Func->isVarArg()) {
17608 unsigned InRegCount = 0;
17611 for (FunctionType::param_iterator I = FTy->param_begin(),
17612 E = FTy->param_end(); I != E; ++I, ++Idx)
17613 if (Attrs.hasAttribute(Idx, Attribute::InReg)) {
17614 auto &DL = DAG.getDataLayout();
17615 // FIXME: should only count parameters that are lowered to integers.
17616 InRegCount += (DL.getTypeSizeInBits(*I) + 31) / 32;
17619 if (InRegCount > 2) {
17620 report_fatal_error("Nest register in use - reduce number of inreg"
17626 case CallingConv::X86_FastCall:
17627 case CallingConv::X86_ThisCall:
17628 case CallingConv::Fast:
17629 // Pass 'nest' parameter in EAX.
17630 // Must be kept in sync with X86CallingConv.td
17631 NestReg = X86::EAX;
17635 SDValue OutChains[4];
17636 SDValue Addr, Disp;
17638 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17639 DAG.getConstant(10, dl, MVT::i32));
17640 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
17642 // This is storing the opcode for MOV32ri.
17643 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
17644 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
17645 OutChains[0] = DAG.getStore(Root, dl,
17646 DAG.getConstant(MOV32ri|N86Reg, dl, MVT::i8),
17647 Trmp, MachinePointerInfo(TrmpAddr),
17650 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17651 DAG.getConstant(1, dl, MVT::i32));
17652 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
17653 MachinePointerInfo(TrmpAddr, 1),
17656 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
17657 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17658 DAG.getConstant(5, dl, MVT::i32));
17659 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, dl, MVT::i8),
17660 Addr, MachinePointerInfo(TrmpAddr, 5),
17663 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17664 DAG.getConstant(6, dl, MVT::i32));
17665 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
17666 MachinePointerInfo(TrmpAddr, 6),
17669 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17673 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
17674 SelectionDAG &DAG) const {
17676 The rounding mode is in bits 11:10 of FPSR, and has the following
17678 00 Round to nearest
17683 FLT_ROUNDS, on the other hand, expects the following:
17690 To perform the conversion, we do:
17691 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
17694 MachineFunction &MF = DAG.getMachineFunction();
17695 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
17696 unsigned StackAlignment = TFI.getStackAlignment();
17697 MVT VT = Op.getSimpleValueType();
17700 // Save FP Control Word to stack slot
17701 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
17702 SDValue StackSlot =
17703 DAG.getFrameIndex(SSFI, getPointerTy(DAG.getDataLayout()));
17705 MachineMemOperand *MMO =
17706 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, SSFI),
17707 MachineMemOperand::MOStore, 2, 2);
17709 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
17710 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
17711 DAG.getVTList(MVT::Other),
17712 Ops, MVT::i16, MMO);
17714 // Load FP Control Word from stack slot
17715 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
17716 MachinePointerInfo(), false, false, false, 0);
17718 // Transform as necessary
17720 DAG.getNode(ISD::SRL, DL, MVT::i16,
17721 DAG.getNode(ISD::AND, DL, MVT::i16,
17722 CWD, DAG.getConstant(0x800, DL, MVT::i16)),
17723 DAG.getConstant(11, DL, MVT::i8));
17725 DAG.getNode(ISD::SRL, DL, MVT::i16,
17726 DAG.getNode(ISD::AND, DL, MVT::i16,
17727 CWD, DAG.getConstant(0x400, DL, MVT::i16)),
17728 DAG.getConstant(9, DL, MVT::i8));
17731 DAG.getNode(ISD::AND, DL, MVT::i16,
17732 DAG.getNode(ISD::ADD, DL, MVT::i16,
17733 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
17734 DAG.getConstant(1, DL, MVT::i16)),
17735 DAG.getConstant(3, DL, MVT::i16));
17737 return DAG.getNode((VT.getSizeInBits() < 16 ?
17738 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
17741 /// \brief Lower a vector CTLZ using native supported vector CTLZ instruction.
17743 // 1. i32/i64 128/256-bit vector (native support require VLX) are expended
17744 // to 512-bit vector.
17745 // 2. i8/i16 vector implemented using dword LZCNT vector instruction
17746 // ( sub(trunc(lzcnt(zext32(x)))) ). In case zext32(x) is illegal,
17747 // split the vector, perform operation on it's Lo a Hi part and
17748 // concatenate the results.
17749 static SDValue LowerVectorCTLZ_AVX512(SDValue Op, SelectionDAG &DAG) {
17751 MVT VT = Op.getSimpleValueType();
17752 MVT EltVT = VT.getVectorElementType();
17753 unsigned NumElems = VT.getVectorNumElements();
17755 if (EltVT == MVT::i64 || EltVT == MVT::i32) {
17756 // Extend to 512 bit vector.
17757 assert((VT.is256BitVector() || VT.is128BitVector()) &&
17758 "Unsupported value type for operation");
17760 MVT NewVT = MVT::getVectorVT(EltVT, 512 / VT.getScalarSizeInBits());
17761 SDValue Vec512 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, NewVT,
17762 DAG.getUNDEF(NewVT),
17764 DAG.getIntPtrConstant(0, dl));
17765 SDValue CtlzNode = DAG.getNode(ISD::CTLZ, dl, NewVT, Vec512);
17767 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, CtlzNode,
17768 DAG.getIntPtrConstant(0, dl));
17771 assert((EltVT == MVT::i8 || EltVT == MVT::i16) &&
17772 "Unsupported element type");
17774 if (16 < NumElems) {
17775 // Split vector, it's Lo and Hi parts will be handled in next iteration.
17777 std::tie(Lo, Hi) = DAG.SplitVector(Op.getOperand(0), dl);
17778 MVT OutVT = MVT::getVectorVT(EltVT, NumElems/2);
17780 Lo = DAG.getNode(Op.getOpcode(), dl, OutVT, Lo);
17781 Hi = DAG.getNode(Op.getOpcode(), dl, OutVT, Hi);
17783 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Lo, Hi);
17786 MVT NewVT = MVT::getVectorVT(MVT::i32, NumElems);
17788 assert((NewVT.is256BitVector() || NewVT.is512BitVector()) &&
17789 "Unsupported value type for operation");
17791 // Use native supported vector instruction vplzcntd.
17792 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, NewVT, Op.getOperand(0));
17793 SDValue CtlzNode = DAG.getNode(ISD::CTLZ, dl, NewVT, Op);
17794 SDValue TruncNode = DAG.getNode(ISD::TRUNCATE, dl, VT, CtlzNode);
17795 SDValue Delta = DAG.getConstant(32 - EltVT.getSizeInBits(), dl, VT);
17797 return DAG.getNode(ISD::SUB, dl, VT, TruncNode, Delta);
17800 static SDValue LowerCTLZ(SDValue Op, const X86Subtarget *Subtarget,
17801 SelectionDAG &DAG) {
17802 MVT VT = Op.getSimpleValueType();
17804 unsigned NumBits = VT.getSizeInBits();
17807 if (VT.isVector() && Subtarget->hasAVX512())
17808 return LowerVectorCTLZ_AVX512(Op, DAG);
17810 Op = Op.getOperand(0);
17811 if (VT == MVT::i8) {
17812 // Zero extend to i32 since there is not an i8 bsr.
17814 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17817 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
17818 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17819 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17821 // If src is zero (i.e. bsr sets ZF), returns NumBits.
17824 DAG.getConstant(NumBits + NumBits - 1, dl, OpVT),
17825 DAG.getConstant(X86::COND_E, dl, MVT::i8),
17828 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
17830 // Finally xor with NumBits-1.
17831 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op,
17832 DAG.getConstant(NumBits - 1, dl, OpVT));
17835 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17839 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, const X86Subtarget *Subtarget,
17840 SelectionDAG &DAG) {
17841 MVT VT = Op.getSimpleValueType();
17843 unsigned NumBits = VT.getSizeInBits();
17846 if (VT.isVector() && Subtarget->hasAVX512())
17847 return LowerVectorCTLZ_AVX512(Op, DAG);
17849 Op = Op.getOperand(0);
17850 if (VT == MVT::i8) {
17851 // Zero extend to i32 since there is not an i8 bsr.
17853 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17856 // Issue a bsr (scan bits in reverse).
17857 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17858 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17860 // And xor with NumBits-1.
17861 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op,
17862 DAG.getConstant(NumBits - 1, dl, OpVT));
17865 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17869 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
17870 MVT VT = Op.getSimpleValueType();
17871 unsigned NumBits = VT.getScalarSizeInBits();
17874 if (VT.isVector()) {
17875 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17877 SDValue N0 = Op.getOperand(0);
17878 SDValue Zero = DAG.getConstant(0, dl, VT);
17880 // lsb(x) = (x & -x)
17881 SDValue LSB = DAG.getNode(ISD::AND, dl, VT, N0,
17882 DAG.getNode(ISD::SUB, dl, VT, Zero, N0));
17884 // cttz_undef(x) = (width - 1) - ctlz(lsb)
17885 if (Op.getOpcode() == ISD::CTTZ_ZERO_UNDEF &&
17886 TLI.isOperationLegal(ISD::CTLZ, VT)) {
17887 SDValue WidthMinusOne = DAG.getConstant(NumBits - 1, dl, VT);
17888 return DAG.getNode(ISD::SUB, dl, VT, WidthMinusOne,
17889 DAG.getNode(ISD::CTLZ, dl, VT, LSB));
17892 // cttz(x) = ctpop(lsb - 1)
17893 SDValue One = DAG.getConstant(1, dl, VT);
17894 return DAG.getNode(ISD::CTPOP, dl, VT,
17895 DAG.getNode(ISD::SUB, dl, VT, LSB, One));
17898 assert(Op.getOpcode() == ISD::CTTZ &&
17899 "Only scalar CTTZ requires custom lowering");
17901 // Issue a bsf (scan bits forward) which also sets EFLAGS.
17902 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
17903 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op.getOperand(0));
17905 // If src is zero (i.e. bsf sets ZF), returns NumBits.
17908 DAG.getConstant(NumBits, dl, VT),
17909 DAG.getConstant(X86::COND_E, dl, MVT::i8),
17912 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
17915 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
17916 // ones, and then concatenate the result back.
17917 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
17918 MVT VT = Op.getSimpleValueType();
17920 assert(VT.is256BitVector() && VT.isInteger() &&
17921 "Unsupported value type for operation");
17923 unsigned NumElems = VT.getVectorNumElements();
17926 // Extract the LHS vectors
17927 SDValue LHS = Op.getOperand(0);
17928 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
17929 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
17931 // Extract the RHS vectors
17932 SDValue RHS = Op.getOperand(1);
17933 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
17934 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
17936 MVT EltVT = VT.getVectorElementType();
17937 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
17939 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
17940 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
17941 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
17944 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
17945 if (Op.getValueType() == MVT::i1)
17946 return DAG.getNode(ISD::XOR, SDLoc(Op), Op.getValueType(),
17947 Op.getOperand(0), Op.getOperand(1));
17948 assert(Op.getSimpleValueType().is256BitVector() &&
17949 Op.getSimpleValueType().isInteger() &&
17950 "Only handle AVX 256-bit vector integer operation");
17951 return Lower256IntArith(Op, DAG);
17954 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
17955 if (Op.getValueType() == MVT::i1)
17956 return DAG.getNode(ISD::XOR, SDLoc(Op), Op.getValueType(),
17957 Op.getOperand(0), Op.getOperand(1));
17958 assert(Op.getSimpleValueType().is256BitVector() &&
17959 Op.getSimpleValueType().isInteger() &&
17960 "Only handle AVX 256-bit vector integer operation");
17961 return Lower256IntArith(Op, DAG);
17964 static SDValue LowerMINMAX(SDValue Op, SelectionDAG &DAG) {
17965 assert(Op.getSimpleValueType().is256BitVector() &&
17966 Op.getSimpleValueType().isInteger() &&
17967 "Only handle AVX 256-bit vector integer operation");
17968 return Lower256IntArith(Op, DAG);
17971 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
17972 SelectionDAG &DAG) {
17974 MVT VT = Op.getSimpleValueType();
17977 return DAG.getNode(ISD::AND, dl, VT, Op.getOperand(0), Op.getOperand(1));
17979 // Decompose 256-bit ops into smaller 128-bit ops.
17980 if (VT.is256BitVector() && !Subtarget->hasInt256())
17981 return Lower256IntArith(Op, DAG);
17983 SDValue A = Op.getOperand(0);
17984 SDValue B = Op.getOperand(1);
17986 // Lower v16i8/v32i8 mul as promotion to v8i16/v16i16 vector
17987 // pairs, multiply and truncate.
17988 if (VT == MVT::v16i8 || VT == MVT::v32i8) {
17989 if (Subtarget->hasInt256()) {
17990 if (VT == MVT::v32i8) {
17991 MVT SubVT = MVT::getVectorVT(MVT::i8, VT.getVectorNumElements() / 2);
17992 SDValue Lo = DAG.getIntPtrConstant(0, dl);
17993 SDValue Hi = DAG.getIntPtrConstant(VT.getVectorNumElements() / 2, dl);
17994 SDValue ALo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, A, Lo);
17995 SDValue BLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, B, Lo);
17996 SDValue AHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, A, Hi);
17997 SDValue BHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, B, Hi);
17998 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
17999 DAG.getNode(ISD::MUL, dl, SubVT, ALo, BLo),
18000 DAG.getNode(ISD::MUL, dl, SubVT, AHi, BHi));
18003 MVT ExVT = MVT::getVectorVT(MVT::i16, VT.getVectorNumElements());
18004 return DAG.getNode(
18005 ISD::TRUNCATE, dl, VT,
18006 DAG.getNode(ISD::MUL, dl, ExVT,
18007 DAG.getNode(ISD::SIGN_EXTEND, dl, ExVT, A),
18008 DAG.getNode(ISD::SIGN_EXTEND, dl, ExVT, B)));
18011 assert(VT == MVT::v16i8 &&
18012 "Pre-AVX2 support only supports v16i8 multiplication");
18013 MVT ExVT = MVT::v8i16;
18015 // Extract the lo parts and sign extend to i16
18017 if (Subtarget->hasSSE41()) {
18018 ALo = DAG.getNode(X86ISD::VSEXT, dl, ExVT, A);
18019 BLo = DAG.getNode(X86ISD::VSEXT, dl, ExVT, B);
18021 const int ShufMask[] = {-1, 0, -1, 1, -1, 2, -1, 3,
18022 -1, 4, -1, 5, -1, 6, -1, 7};
18023 ALo = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
18024 BLo = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
18025 ALo = DAG.getBitcast(ExVT, ALo);
18026 BLo = DAG.getBitcast(ExVT, BLo);
18027 ALo = DAG.getNode(ISD::SRA, dl, ExVT, ALo, DAG.getConstant(8, dl, ExVT));
18028 BLo = DAG.getNode(ISD::SRA, dl, ExVT, BLo, DAG.getConstant(8, dl, ExVT));
18031 // Extract the hi parts and sign extend to i16
18033 if (Subtarget->hasSSE41()) {
18034 const int ShufMask[] = {8, 9, 10, 11, 12, 13, 14, 15,
18035 -1, -1, -1, -1, -1, -1, -1, -1};
18036 AHi = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
18037 BHi = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
18038 AHi = DAG.getNode(X86ISD::VSEXT, dl, ExVT, AHi);
18039 BHi = DAG.getNode(X86ISD::VSEXT, dl, ExVT, BHi);
18041 const int ShufMask[] = {-1, 8, -1, 9, -1, 10, -1, 11,
18042 -1, 12, -1, 13, -1, 14, -1, 15};
18043 AHi = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
18044 BHi = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
18045 AHi = DAG.getBitcast(ExVT, AHi);
18046 BHi = DAG.getBitcast(ExVT, BHi);
18047 AHi = DAG.getNode(ISD::SRA, dl, ExVT, AHi, DAG.getConstant(8, dl, ExVT));
18048 BHi = DAG.getNode(ISD::SRA, dl, ExVT, BHi, DAG.getConstant(8, dl, ExVT));
18051 // Multiply, mask the lower 8bits of the lo/hi results and pack
18052 SDValue RLo = DAG.getNode(ISD::MUL, dl, ExVT, ALo, BLo);
18053 SDValue RHi = DAG.getNode(ISD::MUL, dl, ExVT, AHi, BHi);
18054 RLo = DAG.getNode(ISD::AND, dl, ExVT, RLo, DAG.getConstant(255, dl, ExVT));
18055 RHi = DAG.getNode(ISD::AND, dl, ExVT, RHi, DAG.getConstant(255, dl, ExVT));
18056 return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi);
18059 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
18060 if (VT == MVT::v4i32) {
18061 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
18062 "Should not custom lower when pmuldq is available!");
18064 // Extract the odd parts.
18065 static const int UnpackMask[] = { 1, -1, 3, -1 };
18066 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
18067 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
18069 // Multiply the even parts.
18070 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
18071 // Now multiply odd parts.
18072 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
18074 Evens = DAG.getBitcast(VT, Evens);
18075 Odds = DAG.getBitcast(VT, Odds);
18077 // Merge the two vectors back together with a shuffle. This expands into 2
18079 static const int ShufMask[] = { 0, 4, 2, 6 };
18080 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
18083 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
18084 "Only know how to lower V2I64/V4I64/V8I64 multiply");
18086 // Ahi = psrlqi(a, 32);
18087 // Bhi = psrlqi(b, 32);
18089 // AloBlo = pmuludq(a, b);
18090 // AloBhi = pmuludq(a, Bhi);
18091 // AhiBlo = pmuludq(Ahi, b);
18093 // AloBhi = psllqi(AloBhi, 32);
18094 // AhiBlo = psllqi(AhiBlo, 32);
18095 // return AloBlo + AloBhi + AhiBlo;
18097 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
18098 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
18100 SDValue AhiBlo = Ahi;
18101 SDValue AloBhi = Bhi;
18102 // Bit cast to 32-bit vectors for MULUDQ
18103 MVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
18104 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
18105 A = DAG.getBitcast(MulVT, A);
18106 B = DAG.getBitcast(MulVT, B);
18107 Ahi = DAG.getBitcast(MulVT, Ahi);
18108 Bhi = DAG.getBitcast(MulVT, Bhi);
18110 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
18111 // After shifting right const values the result may be all-zero.
18112 if (!ISD::isBuildVectorAllZeros(Ahi.getNode())) {
18113 AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
18114 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
18116 if (!ISD::isBuildVectorAllZeros(Bhi.getNode())) {
18117 AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
18118 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
18121 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
18122 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
18125 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
18126 assert(Subtarget->isTargetWin64() && "Unexpected target");
18127 EVT VT = Op.getValueType();
18128 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
18129 "Unexpected return type for lowering");
18133 switch (Op->getOpcode()) {
18134 default: llvm_unreachable("Unexpected request for libcall!");
18135 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
18136 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
18137 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
18138 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
18139 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
18140 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
18144 SDValue InChain = DAG.getEntryNode();
18146 TargetLowering::ArgListTy Args;
18147 TargetLowering::ArgListEntry Entry;
18148 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
18149 EVT ArgVT = Op->getOperand(i).getValueType();
18150 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
18151 "Unexpected argument type for lowering");
18152 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
18153 Entry.Node = StackPtr;
18154 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
18156 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
18157 Entry.Ty = PointerType::get(ArgTy,0);
18158 Entry.isSExt = false;
18159 Entry.isZExt = false;
18160 Args.push_back(Entry);
18163 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
18164 getPointerTy(DAG.getDataLayout()));
18166 TargetLowering::CallLoweringInfo CLI(DAG);
18167 CLI.setDebugLoc(dl).setChain(InChain)
18168 .setCallee(getLibcallCallingConv(LC),
18169 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
18170 Callee, std::move(Args), 0)
18171 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
18173 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
18174 return DAG.getBitcast(VT, CallInfo.first);
18177 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
18178 SelectionDAG &DAG) {
18179 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
18180 MVT VT = Op0.getSimpleValueType();
18183 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
18184 (VT == MVT::v8i32 && Subtarget->hasInt256()));
18186 // PMULxD operations multiply each even value (starting at 0) of LHS with
18187 // the related value of RHS and produce a widen result.
18188 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
18189 // => <2 x i64> <ae|cg>
18191 // In other word, to have all the results, we need to perform two PMULxD:
18192 // 1. one with the even values.
18193 // 2. one with the odd values.
18194 // To achieve #2, with need to place the odd values at an even position.
18196 // Place the odd value at an even position (basically, shift all values 1
18197 // step to the left):
18198 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
18199 // <a|b|c|d> => <b|undef|d|undef>
18200 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
18201 // <e|f|g|h> => <f|undef|h|undef>
18202 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
18204 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
18206 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
18207 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
18209 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
18210 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
18211 // => <2 x i64> <ae|cg>
18212 SDValue Mul1 = DAG.getBitcast(VT, DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
18213 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
18214 // => <2 x i64> <bf|dh>
18215 SDValue Mul2 = DAG.getBitcast(VT, DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
18217 // Shuffle it back into the right order.
18218 SDValue Highs, Lows;
18219 if (VT == MVT::v8i32) {
18220 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
18221 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
18222 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
18223 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
18225 const int HighMask[] = {1, 5, 3, 7};
18226 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
18227 const int LowMask[] = {0, 4, 2, 6};
18228 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
18231 // If we have a signed multiply but no PMULDQ fix up the high parts of a
18232 // unsigned multiply.
18233 if (IsSigned && !Subtarget->hasSSE41()) {
18234 SDValue ShAmt = DAG.getConstant(
18236 DAG.getTargetLoweringInfo().getShiftAmountTy(VT, DAG.getDataLayout()));
18237 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
18238 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
18239 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
18240 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
18242 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
18243 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
18246 // The first result of MUL_LOHI is actually the low value, followed by the
18248 SDValue Ops[] = {Lows, Highs};
18249 return DAG.getMergeValues(Ops, dl);
18252 // Return true if the required (according to Opcode) shift-imm form is natively
18253 // supported by the Subtarget
18254 static bool SupportedVectorShiftWithImm(MVT VT, const X86Subtarget *Subtarget,
18256 if (VT.getScalarSizeInBits() < 16)
18259 if (VT.is512BitVector() &&
18260 (VT.getScalarSizeInBits() > 16 || Subtarget->hasBWI()))
18263 bool LShift = VT.is128BitVector() ||
18264 (VT.is256BitVector() && Subtarget->hasInt256());
18266 bool AShift = LShift && (Subtarget->hasVLX() ||
18267 (VT != MVT::v2i64 && VT != MVT::v4i64));
18268 return (Opcode == ISD::SRA) ? AShift : LShift;
18271 // The shift amount is a variable, but it is the same for all vector lanes.
18272 // These instructions are defined together with shift-immediate.
18274 bool SupportedVectorShiftWithBaseAmnt(MVT VT, const X86Subtarget *Subtarget,
18276 return SupportedVectorShiftWithImm(VT, Subtarget, Opcode);
18279 // Return true if the required (according to Opcode) variable-shift form is
18280 // natively supported by the Subtarget
18281 static bool SupportedVectorVarShift(MVT VT, const X86Subtarget *Subtarget,
18284 if (!Subtarget->hasInt256() || VT.getScalarSizeInBits() < 16)
18287 // vXi16 supported only on AVX-512, BWI
18288 if (VT.getScalarSizeInBits() == 16 && !Subtarget->hasBWI())
18291 if (VT.is512BitVector() || Subtarget->hasVLX())
18294 bool LShift = VT.is128BitVector() || VT.is256BitVector();
18295 bool AShift = LShift && VT != MVT::v2i64 && VT != MVT::v4i64;
18296 return (Opcode == ISD::SRA) ? AShift : LShift;
18299 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
18300 const X86Subtarget *Subtarget) {
18301 MVT VT = Op.getSimpleValueType();
18303 SDValue R = Op.getOperand(0);
18304 SDValue Amt = Op.getOperand(1);
18306 unsigned X86Opc = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHLI :
18307 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRLI : X86ISD::VSRAI;
18309 auto ArithmeticShiftRight64 = [&](uint64_t ShiftAmt) {
18310 assert((VT == MVT::v2i64 || VT == MVT::v4i64) && "Unexpected SRA type");
18311 MVT ExVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() * 2);
18312 SDValue Ex = DAG.getBitcast(ExVT, R);
18314 if (ShiftAmt >= 32) {
18315 // Splat sign to upper i32 dst, and SRA upper i32 src to lower i32.
18317 getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex, 31, DAG);
18318 SDValue Lower = getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex,
18319 ShiftAmt - 32, DAG);
18320 if (VT == MVT::v2i64)
18321 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower, {5, 1, 7, 3});
18322 if (VT == MVT::v4i64)
18323 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower,
18324 {9, 1, 11, 3, 13, 5, 15, 7});
18326 // SRA upper i32, SHL whole i64 and select lower i32.
18327 SDValue Upper = getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex,
18330 getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt, DAG);
18331 Lower = DAG.getBitcast(ExVT, Lower);
18332 if (VT == MVT::v2i64)
18333 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower, {4, 1, 6, 3});
18334 if (VT == MVT::v4i64)
18335 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower,
18336 {8, 1, 10, 3, 12, 5, 14, 7});
18338 return DAG.getBitcast(VT, Ex);
18341 // Optimize shl/srl/sra with constant shift amount.
18342 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
18343 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
18344 uint64_t ShiftAmt = ShiftConst->getZExtValue();
18346 if (SupportedVectorShiftWithImm(VT, Subtarget, Op.getOpcode()))
18347 return getTargetVShiftByConstNode(X86Opc, dl, VT, R, ShiftAmt, DAG);
18349 // i64 SRA needs to be performed as partial shifts.
18350 if ((VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
18351 Op.getOpcode() == ISD::SRA && !Subtarget->hasXOP())
18352 return ArithmeticShiftRight64(ShiftAmt);
18354 if (VT == MVT::v16i8 || (Subtarget->hasInt256() && VT == MVT::v32i8)) {
18355 unsigned NumElts = VT.getVectorNumElements();
18356 MVT ShiftVT = MVT::getVectorVT(MVT::i16, NumElts / 2);
18358 // Simple i8 add case
18359 if (Op.getOpcode() == ISD::SHL && ShiftAmt == 1)
18360 return DAG.getNode(ISD::ADD, dl, VT, R, R);
18362 // ashr(R, 7) === cmp_slt(R, 0)
18363 if (Op.getOpcode() == ISD::SRA && ShiftAmt == 7) {
18364 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
18365 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
18368 // XOP can shift v16i8 directly instead of as shift v8i16 + mask.
18369 if (VT == MVT::v16i8 && Subtarget->hasXOP())
18372 if (Op.getOpcode() == ISD::SHL) {
18373 // Make a large shift.
18374 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, ShiftVT,
18376 SHL = DAG.getBitcast(VT, SHL);
18377 // Zero out the rightmost bits.
18378 SmallVector<SDValue, 32> V(
18379 NumElts, DAG.getConstant(uint8_t(-1U << ShiftAmt), dl, MVT::i8));
18380 return DAG.getNode(ISD::AND, dl, VT, SHL,
18381 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18383 if (Op.getOpcode() == ISD::SRL) {
18384 // Make a large shift.
18385 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, ShiftVT,
18387 SRL = DAG.getBitcast(VT, SRL);
18388 // Zero out the leftmost bits.
18389 SmallVector<SDValue, 32> V(
18390 NumElts, DAG.getConstant(uint8_t(-1U) >> ShiftAmt, dl, MVT::i8));
18391 return DAG.getNode(ISD::AND, dl, VT, SRL,
18392 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18394 if (Op.getOpcode() == ISD::SRA) {
18395 // ashr(R, Amt) === sub(xor(lshr(R, Amt), Mask), Mask)
18396 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18397 SmallVector<SDValue, 32> V(NumElts,
18398 DAG.getConstant(128 >> ShiftAmt, dl,
18400 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
18401 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
18402 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
18405 llvm_unreachable("Unknown shift opcode.");
18410 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18411 if (!Subtarget->is64Bit() && !Subtarget->hasXOP() &&
18412 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64))) {
18414 // Peek through any splat that was introduced for i64 shift vectorization.
18415 int SplatIndex = -1;
18416 if (ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Amt.getNode()))
18417 if (SVN->isSplat()) {
18418 SplatIndex = SVN->getSplatIndex();
18419 Amt = Amt.getOperand(0);
18420 assert(SplatIndex < (int)VT.getVectorNumElements() &&
18421 "Splat shuffle referencing second operand");
18424 if (Amt.getOpcode() != ISD::BITCAST ||
18425 Amt.getOperand(0).getOpcode() != ISD::BUILD_VECTOR)
18428 Amt = Amt.getOperand(0);
18429 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18430 VT.getVectorNumElements();
18431 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
18432 uint64_t ShiftAmt = 0;
18433 unsigned BaseOp = (SplatIndex < 0 ? 0 : SplatIndex * Ratio);
18434 for (unsigned i = 0; i != Ratio; ++i) {
18435 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i + BaseOp));
18439 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
18442 // Check remaining shift amounts (if not a splat).
18443 if (SplatIndex < 0) {
18444 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18445 uint64_t ShAmt = 0;
18446 for (unsigned j = 0; j != Ratio; ++j) {
18447 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
18451 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
18453 if (ShAmt != ShiftAmt)
18458 if (SupportedVectorShiftWithImm(VT, Subtarget, Op.getOpcode()))
18459 return getTargetVShiftByConstNode(X86Opc, dl, VT, R, ShiftAmt, DAG);
18461 if (Op.getOpcode() == ISD::SRA)
18462 return ArithmeticShiftRight64(ShiftAmt);
18468 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
18469 const X86Subtarget* Subtarget) {
18470 MVT VT = Op.getSimpleValueType();
18472 SDValue R = Op.getOperand(0);
18473 SDValue Amt = Op.getOperand(1);
18475 unsigned X86OpcI = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHLI :
18476 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRLI : X86ISD::VSRAI;
18478 unsigned X86OpcV = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHL :
18479 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRL : X86ISD::VSRA;
18481 if (SupportedVectorShiftWithBaseAmnt(VT, Subtarget, Op.getOpcode())) {
18483 MVT EltVT = VT.getVectorElementType();
18485 if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Amt)) {
18486 // Check if this build_vector node is doing a splat.
18487 // If so, then set BaseShAmt equal to the splat value.
18488 BaseShAmt = BV->getSplatValue();
18489 if (BaseShAmt && BaseShAmt.getOpcode() == ISD::UNDEF)
18490 BaseShAmt = SDValue();
18492 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
18493 Amt = Amt.getOperand(0);
18495 ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Amt);
18496 if (SVN && SVN->isSplat()) {
18497 unsigned SplatIdx = (unsigned)SVN->getSplatIndex();
18498 SDValue InVec = Amt.getOperand(0);
18499 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
18500 assert((SplatIdx < InVec.getSimpleValueType().getVectorNumElements()) &&
18501 "Unexpected shuffle index found!");
18502 BaseShAmt = InVec.getOperand(SplatIdx);
18503 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
18504 if (ConstantSDNode *C =
18505 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
18506 if (C->getZExtValue() == SplatIdx)
18507 BaseShAmt = InVec.getOperand(1);
18512 // Avoid introducing an extract element from a shuffle.
18513 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InVec,
18514 DAG.getIntPtrConstant(SplatIdx, dl));
18518 if (BaseShAmt.getNode()) {
18519 assert(EltVT.bitsLE(MVT::i64) && "Unexpected element type!");
18520 if (EltVT != MVT::i64 && EltVT.bitsGT(MVT::i32))
18521 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, BaseShAmt);
18522 else if (EltVT.bitsLT(MVT::i32))
18523 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
18525 return getTargetVShiftNode(X86OpcI, dl, VT, R, BaseShAmt, DAG);
18529 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18530 if (!Subtarget->is64Bit() && VT == MVT::v2i64 &&
18531 Amt.getOpcode() == ISD::BITCAST &&
18532 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
18533 Amt = Amt.getOperand(0);
18534 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18535 VT.getVectorNumElements();
18536 std::vector<SDValue> Vals(Ratio);
18537 for (unsigned i = 0; i != Ratio; ++i)
18538 Vals[i] = Amt.getOperand(i);
18539 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18540 for (unsigned j = 0; j != Ratio; ++j)
18541 if (Vals[j] != Amt.getOperand(i + j))
18545 if (SupportedVectorShiftWithBaseAmnt(VT, Subtarget, Op.getOpcode()))
18546 return DAG.getNode(X86OpcV, dl, VT, R, Op.getOperand(1));
18551 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
18552 SelectionDAG &DAG) {
18553 MVT VT = Op.getSimpleValueType();
18555 SDValue R = Op.getOperand(0);
18556 SDValue Amt = Op.getOperand(1);
18558 assert(VT.isVector() && "Custom lowering only for vector shifts!");
18559 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
18561 if (SDValue V = LowerScalarImmediateShift(Op, DAG, Subtarget))
18564 if (SDValue V = LowerScalarVariableShift(Op, DAG, Subtarget))
18567 if (SupportedVectorVarShift(VT, Subtarget, Op.getOpcode()))
18570 // XOP has 128-bit variable logical/arithmetic shifts.
18571 // +ve/-ve Amt = shift left/right.
18572 if (Subtarget->hasXOP() &&
18573 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
18574 VT == MVT::v8i16 || VT == MVT::v16i8)) {
18575 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SRA) {
18576 SDValue Zero = getZeroVector(VT, Subtarget, DAG, dl);
18577 Amt = DAG.getNode(ISD::SUB, dl, VT, Zero, Amt);
18579 if (Op.getOpcode() == ISD::SHL || Op.getOpcode() == ISD::SRL)
18580 return DAG.getNode(X86ISD::VPSHL, dl, VT, R, Amt);
18581 if (Op.getOpcode() == ISD::SRA)
18582 return DAG.getNode(X86ISD::VPSHA, dl, VT, R, Amt);
18585 // 2i64 vector logical shifts can efficiently avoid scalarization - do the
18586 // shifts per-lane and then shuffle the partial results back together.
18587 if (VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) {
18588 // Splat the shift amounts so the scalar shifts above will catch it.
18589 SDValue Amt0 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {0, 0});
18590 SDValue Amt1 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {1, 1});
18591 SDValue R0 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt0);
18592 SDValue R1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt1);
18593 return DAG.getVectorShuffle(VT, dl, R0, R1, {0, 3});
18596 // i64 vector arithmetic shift can be emulated with the transform:
18597 // M = lshr(SIGN_BIT, Amt)
18598 // ashr(R, Amt) === sub(xor(lshr(R, Amt), M), M)
18599 if ((VT == MVT::v2i64 || (VT == MVT::v4i64 && Subtarget->hasInt256())) &&
18600 Op.getOpcode() == ISD::SRA) {
18601 SDValue S = DAG.getConstant(APInt::getSignBit(64), dl, VT);
18602 SDValue M = DAG.getNode(ISD::SRL, dl, VT, S, Amt);
18603 R = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18604 R = DAG.getNode(ISD::XOR, dl, VT, R, M);
18605 R = DAG.getNode(ISD::SUB, dl, VT, R, M);
18609 // If possible, lower this packed shift into a vector multiply instead of
18610 // expanding it into a sequence of scalar shifts.
18611 // Do this only if the vector shift count is a constant build_vector.
18612 if (Op.getOpcode() == ISD::SHL &&
18613 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
18614 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
18615 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18616 SmallVector<SDValue, 8> Elts;
18617 MVT SVT = VT.getVectorElementType();
18618 unsigned SVTBits = SVT.getSizeInBits();
18619 APInt One(SVTBits, 1);
18620 unsigned NumElems = VT.getVectorNumElements();
18622 for (unsigned i=0; i !=NumElems; ++i) {
18623 SDValue Op = Amt->getOperand(i);
18624 if (Op->getOpcode() == ISD::UNDEF) {
18625 Elts.push_back(Op);
18629 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
18630 APInt C(SVTBits, ND->getAPIntValue().getZExtValue());
18631 uint64_t ShAmt = C.getZExtValue();
18632 if (ShAmt >= SVTBits) {
18633 Elts.push_back(DAG.getUNDEF(SVT));
18636 Elts.push_back(DAG.getConstant(One.shl(ShAmt), dl, SVT));
18638 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
18639 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
18642 // Lower SHL with variable shift amount.
18643 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
18644 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, dl, VT));
18646 Op = DAG.getNode(ISD::ADD, dl, VT, Op,
18647 DAG.getConstant(0x3f800000U, dl, VT));
18648 Op = DAG.getBitcast(MVT::v4f32, Op);
18649 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
18650 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
18653 // If possible, lower this shift as a sequence of two shifts by
18654 // constant plus a MOVSS/MOVSD instead of scalarizing it.
18656 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
18658 // Could be rewritten as:
18659 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
18661 // The advantage is that the two shifts from the example would be
18662 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
18663 // the vector shift into four scalar shifts plus four pairs of vector
18665 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
18666 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18667 unsigned TargetOpcode = X86ISD::MOVSS;
18668 bool CanBeSimplified;
18669 // The splat value for the first packed shift (the 'X' from the example).
18670 SDValue Amt1 = Amt->getOperand(0);
18671 // The splat value for the second packed shift (the 'Y' from the example).
18672 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
18673 Amt->getOperand(2);
18675 // See if it is possible to replace this node with a sequence of
18676 // two shifts followed by a MOVSS/MOVSD
18677 if (VT == MVT::v4i32) {
18678 // Check if it is legal to use a MOVSS.
18679 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
18680 Amt2 == Amt->getOperand(3);
18681 if (!CanBeSimplified) {
18682 // Otherwise, check if we can still simplify this node using a MOVSD.
18683 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
18684 Amt->getOperand(2) == Amt->getOperand(3);
18685 TargetOpcode = X86ISD::MOVSD;
18686 Amt2 = Amt->getOperand(2);
18689 // Do similar checks for the case where the machine value type
18691 CanBeSimplified = Amt1 == Amt->getOperand(1);
18692 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
18693 CanBeSimplified = Amt2 == Amt->getOperand(i);
18695 if (!CanBeSimplified) {
18696 TargetOpcode = X86ISD::MOVSD;
18697 CanBeSimplified = true;
18698 Amt2 = Amt->getOperand(4);
18699 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
18700 CanBeSimplified = Amt1 == Amt->getOperand(i);
18701 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
18702 CanBeSimplified = Amt2 == Amt->getOperand(j);
18706 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
18707 isa<ConstantSDNode>(Amt2)) {
18708 // Replace this node with two shifts followed by a MOVSS/MOVSD.
18709 MVT CastVT = MVT::v4i32;
18711 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), dl, VT);
18712 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
18714 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), dl, VT);
18715 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
18716 if (TargetOpcode == X86ISD::MOVSD)
18717 CastVT = MVT::v2i64;
18718 SDValue BitCast1 = DAG.getBitcast(CastVT, Shift1);
18719 SDValue BitCast2 = DAG.getBitcast(CastVT, Shift2);
18720 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
18722 return DAG.getBitcast(VT, Result);
18726 // v4i32 Non Uniform Shifts.
18727 // If the shift amount is constant we can shift each lane using the SSE2
18728 // immediate shifts, else we need to zero-extend each lane to the lower i64
18729 // and shift using the SSE2 variable shifts.
18730 // The separate results can then be blended together.
18731 if (VT == MVT::v4i32) {
18732 unsigned Opc = Op.getOpcode();
18733 SDValue Amt0, Amt1, Amt2, Amt3;
18734 if (ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18735 Amt0 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {0, 0, 0, 0});
18736 Amt1 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {1, 1, 1, 1});
18737 Amt2 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {2, 2, 2, 2});
18738 Amt3 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {3, 3, 3, 3});
18740 // ISD::SHL is handled above but we include it here for completeness.
18743 llvm_unreachable("Unknown target vector shift node");
18745 Opc = X86ISD::VSHL;
18748 Opc = X86ISD::VSRL;
18751 Opc = X86ISD::VSRA;
18754 // The SSE2 shifts use the lower i64 as the same shift amount for
18755 // all lanes and the upper i64 is ignored. These shuffle masks
18756 // optimally zero-extend each lanes on SSE2/SSE41/AVX targets.
18757 SDValue Z = getZeroVector(VT, Subtarget, DAG, dl);
18758 Amt0 = DAG.getVectorShuffle(VT, dl, Amt, Z, {0, 4, -1, -1});
18759 Amt1 = DAG.getVectorShuffle(VT, dl, Amt, Z, {1, 5, -1, -1});
18760 Amt2 = DAG.getVectorShuffle(VT, dl, Amt, Z, {2, 6, -1, -1});
18761 Amt3 = DAG.getVectorShuffle(VT, dl, Amt, Z, {3, 7, -1, -1});
18764 SDValue R0 = DAG.getNode(Opc, dl, VT, R, Amt0);
18765 SDValue R1 = DAG.getNode(Opc, dl, VT, R, Amt1);
18766 SDValue R2 = DAG.getNode(Opc, dl, VT, R, Amt2);
18767 SDValue R3 = DAG.getNode(Opc, dl, VT, R, Amt3);
18768 SDValue R02 = DAG.getVectorShuffle(VT, dl, R0, R2, {0, -1, 6, -1});
18769 SDValue R13 = DAG.getVectorShuffle(VT, dl, R1, R3, {-1, 1, -1, 7});
18770 return DAG.getVectorShuffle(VT, dl, R02, R13, {0, 5, 2, 7});
18773 if (VT == MVT::v16i8 ||
18774 (VT == MVT::v32i8 && Subtarget->hasInt256() && !Subtarget->hasXOP())) {
18775 MVT ExtVT = MVT::getVectorVT(MVT::i16, VT.getVectorNumElements() / 2);
18776 unsigned ShiftOpcode = Op->getOpcode();
18778 auto SignBitSelect = [&](MVT SelVT, SDValue Sel, SDValue V0, SDValue V1) {
18779 // On SSE41 targets we make use of the fact that VSELECT lowers
18780 // to PBLENDVB which selects bytes based just on the sign bit.
18781 if (Subtarget->hasSSE41()) {
18782 V0 = DAG.getBitcast(VT, V0);
18783 V1 = DAG.getBitcast(VT, V1);
18784 Sel = DAG.getBitcast(VT, Sel);
18785 return DAG.getBitcast(SelVT,
18786 DAG.getNode(ISD::VSELECT, dl, VT, Sel, V0, V1));
18788 // On pre-SSE41 targets we test for the sign bit by comparing to
18789 // zero - a negative value will set all bits of the lanes to true
18790 // and VSELECT uses that in its OR(AND(V0,C),AND(V1,~C)) lowering.
18791 SDValue Z = getZeroVector(SelVT, Subtarget, DAG, dl);
18792 SDValue C = DAG.getNode(X86ISD::PCMPGT, dl, SelVT, Z, Sel);
18793 return DAG.getNode(ISD::VSELECT, dl, SelVT, C, V0, V1);
18796 // Turn 'a' into a mask suitable for VSELECT: a = a << 5;
18797 // We can safely do this using i16 shifts as we're only interested in
18798 // the 3 lower bits of each byte.
18799 Amt = DAG.getBitcast(ExtVT, Amt);
18800 Amt = DAG.getNode(ISD::SHL, dl, ExtVT, Amt, DAG.getConstant(5, dl, ExtVT));
18801 Amt = DAG.getBitcast(VT, Amt);
18803 if (Op->getOpcode() == ISD::SHL || Op->getOpcode() == ISD::SRL) {
18804 // r = VSELECT(r, shift(r, 4), a);
18806 DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(4, dl, VT));
18807 R = SignBitSelect(VT, Amt, M, R);
18810 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18812 // r = VSELECT(r, shift(r, 2), a);
18813 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(2, dl, VT));
18814 R = SignBitSelect(VT, Amt, M, R);
18817 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18819 // return VSELECT(r, shift(r, 1), a);
18820 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(1, dl, VT));
18821 R = SignBitSelect(VT, Amt, M, R);
18825 if (Op->getOpcode() == ISD::SRA) {
18826 // For SRA we need to unpack each byte to the higher byte of a i16 vector
18827 // so we can correctly sign extend. We don't care what happens to the
18829 SDValue ALo = DAG.getNode(X86ISD::UNPCKL, dl, VT, DAG.getUNDEF(VT), Amt);
18830 SDValue AHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, DAG.getUNDEF(VT), Amt);
18831 SDValue RLo = DAG.getNode(X86ISD::UNPCKL, dl, VT, DAG.getUNDEF(VT), R);
18832 SDValue RHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, DAG.getUNDEF(VT), R);
18833 ALo = DAG.getBitcast(ExtVT, ALo);
18834 AHi = DAG.getBitcast(ExtVT, AHi);
18835 RLo = DAG.getBitcast(ExtVT, RLo);
18836 RHi = DAG.getBitcast(ExtVT, RHi);
18838 // r = VSELECT(r, shift(r, 4), a);
18839 SDValue MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
18840 DAG.getConstant(4, dl, ExtVT));
18841 SDValue MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
18842 DAG.getConstant(4, dl, ExtVT));
18843 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
18844 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
18847 ALo = DAG.getNode(ISD::ADD, dl, ExtVT, ALo, ALo);
18848 AHi = DAG.getNode(ISD::ADD, dl, ExtVT, AHi, AHi);
18850 // r = VSELECT(r, shift(r, 2), a);
18851 MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
18852 DAG.getConstant(2, dl, ExtVT));
18853 MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
18854 DAG.getConstant(2, dl, ExtVT));
18855 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
18856 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
18859 ALo = DAG.getNode(ISD::ADD, dl, ExtVT, ALo, ALo);
18860 AHi = DAG.getNode(ISD::ADD, dl, ExtVT, AHi, AHi);
18862 // r = VSELECT(r, shift(r, 1), a);
18863 MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
18864 DAG.getConstant(1, dl, ExtVT));
18865 MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
18866 DAG.getConstant(1, dl, ExtVT));
18867 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
18868 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
18870 // Logical shift the result back to the lower byte, leaving a zero upper
18872 // meaning that we can safely pack with PACKUSWB.
18874 DAG.getNode(ISD::SRL, dl, ExtVT, RLo, DAG.getConstant(8, dl, ExtVT));
18876 DAG.getNode(ISD::SRL, dl, ExtVT, RHi, DAG.getConstant(8, dl, ExtVT));
18877 return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi);
18881 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
18882 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
18883 // solution better.
18884 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
18885 MVT ExtVT = MVT::v8i32;
18887 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
18888 R = DAG.getNode(ExtOpc, dl, ExtVT, R);
18889 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, ExtVT, Amt);
18890 return DAG.getNode(ISD::TRUNCATE, dl, VT,
18891 DAG.getNode(Op.getOpcode(), dl, ExtVT, R, Amt));
18894 if (Subtarget->hasInt256() && !Subtarget->hasXOP() && VT == MVT::v16i16) {
18895 MVT ExtVT = MVT::v8i32;
18896 SDValue Z = getZeroVector(VT, Subtarget, DAG, dl);
18897 SDValue ALo = DAG.getNode(X86ISD::UNPCKL, dl, VT, Amt, Z);
18898 SDValue AHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, Amt, Z);
18899 SDValue RLo = DAG.getNode(X86ISD::UNPCKL, dl, VT, R, R);
18900 SDValue RHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, R, R);
18901 ALo = DAG.getBitcast(ExtVT, ALo);
18902 AHi = DAG.getBitcast(ExtVT, AHi);
18903 RLo = DAG.getBitcast(ExtVT, RLo);
18904 RHi = DAG.getBitcast(ExtVT, RHi);
18905 SDValue Lo = DAG.getNode(Op.getOpcode(), dl, ExtVT, RLo, ALo);
18906 SDValue Hi = DAG.getNode(Op.getOpcode(), dl, ExtVT, RHi, AHi);
18907 Lo = DAG.getNode(ISD::SRL, dl, ExtVT, Lo, DAG.getConstant(16, dl, ExtVT));
18908 Hi = DAG.getNode(ISD::SRL, dl, ExtVT, Hi, DAG.getConstant(16, dl, ExtVT));
18909 return DAG.getNode(X86ISD::PACKUS, dl, VT, Lo, Hi);
18912 if (VT == MVT::v8i16) {
18913 unsigned ShiftOpcode = Op->getOpcode();
18915 auto SignBitSelect = [&](SDValue Sel, SDValue V0, SDValue V1) {
18916 // On SSE41 targets we make use of the fact that VSELECT lowers
18917 // to PBLENDVB which selects bytes based just on the sign bit.
18918 if (Subtarget->hasSSE41()) {
18919 MVT ExtVT = MVT::getVectorVT(MVT::i8, VT.getVectorNumElements() * 2);
18920 V0 = DAG.getBitcast(ExtVT, V0);
18921 V1 = DAG.getBitcast(ExtVT, V1);
18922 Sel = DAG.getBitcast(ExtVT, Sel);
18923 return DAG.getBitcast(
18924 VT, DAG.getNode(ISD::VSELECT, dl, ExtVT, Sel, V0, V1));
18926 // On pre-SSE41 targets we splat the sign bit - a negative value will
18927 // set all bits of the lanes to true and VSELECT uses that in
18928 // its OR(AND(V0,C),AND(V1,~C)) lowering.
18930 DAG.getNode(ISD::SRA, dl, VT, Sel, DAG.getConstant(15, dl, VT));
18931 return DAG.getNode(ISD::VSELECT, dl, VT, C, V0, V1);
18934 // Turn 'a' into a mask suitable for VSELECT: a = a << 12;
18935 if (Subtarget->hasSSE41()) {
18936 // On SSE41 targets we need to replicate the shift mask in both
18937 // bytes for PBLENDVB.
18940 DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(4, dl, VT)),
18941 DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(12, dl, VT)));
18943 Amt = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(12, dl, VT));
18946 // r = VSELECT(r, shift(r, 8), a);
18947 SDValue M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(8, dl, VT));
18948 R = SignBitSelect(Amt, M, R);
18951 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18953 // r = VSELECT(r, shift(r, 4), a);
18954 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(4, dl, VT));
18955 R = SignBitSelect(Amt, M, R);
18958 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18960 // r = VSELECT(r, shift(r, 2), a);
18961 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(2, dl, VT));
18962 R = SignBitSelect(Amt, M, R);
18965 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18967 // return VSELECT(r, shift(r, 1), a);
18968 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(1, dl, VT));
18969 R = SignBitSelect(Amt, M, R);
18973 // Decompose 256-bit shifts into smaller 128-bit shifts.
18974 if (VT.is256BitVector()) {
18975 unsigned NumElems = VT.getVectorNumElements();
18976 MVT EltVT = VT.getVectorElementType();
18977 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18979 // Extract the two vectors
18980 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
18981 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
18983 // Recreate the shift amount vectors
18984 SDValue Amt1, Amt2;
18985 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
18986 // Constant shift amount
18987 SmallVector<SDValue, 8> Ops(Amt->op_begin(), Amt->op_begin() + NumElems);
18988 ArrayRef<SDValue> Amt1Csts = makeArrayRef(Ops).slice(0, NumElems / 2);
18989 ArrayRef<SDValue> Amt2Csts = makeArrayRef(Ops).slice(NumElems / 2);
18991 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
18992 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
18994 // Variable shift amount
18995 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
18996 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
18999 // Issue new vector shifts for the smaller types
19000 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
19001 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
19003 // Concatenate the result back
19004 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
19010 static SDValue LowerRotate(SDValue Op, const X86Subtarget *Subtarget,
19011 SelectionDAG &DAG) {
19012 MVT VT = Op.getSimpleValueType();
19014 SDValue R = Op.getOperand(0);
19015 SDValue Amt = Op.getOperand(1);
19017 assert(VT.isVector() && "Custom lowering only for vector rotates!");
19018 assert(Subtarget->hasXOP() && "XOP support required for vector rotates!");
19019 assert((Op.getOpcode() == ISD::ROTL) && "Only ROTL supported");
19021 // XOP has 128-bit vector variable + immediate rotates.
19022 // +ve/-ve Amt = rotate left/right.
19024 // Split 256-bit integers.
19025 if (VT.is256BitVector())
19026 return Lower256IntArith(Op, DAG);
19028 assert(VT.is128BitVector() && "Only rotate 128-bit vectors!");
19030 // Attempt to rotate by immediate.
19031 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
19032 if (auto *RotateConst = BVAmt->getConstantSplatNode()) {
19033 uint64_t RotateAmt = RotateConst->getAPIntValue().getZExtValue();
19034 assert(RotateAmt < VT.getScalarSizeInBits() && "Rotation out of range");
19035 return DAG.getNode(X86ISD::VPROTI, DL, VT, R,
19036 DAG.getConstant(RotateAmt, DL, MVT::i8));
19040 // Use general rotate by variable (per-element).
19041 return DAG.getNode(X86ISD::VPROT, DL, VT, R, Amt);
19044 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
19045 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
19046 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
19047 // looks for this combo and may remove the "setcc" instruction if the "setcc"
19048 // has only one use.
19049 SDNode *N = Op.getNode();
19050 SDValue LHS = N->getOperand(0);
19051 SDValue RHS = N->getOperand(1);
19052 unsigned BaseOp = 0;
19055 switch (Op.getOpcode()) {
19056 default: llvm_unreachable("Unknown ovf instruction!");
19058 // A subtract of one will be selected as a INC. Note that INC doesn't
19059 // set CF, so we can't do this for UADDO.
19060 if (isOneConstant(RHS)) {
19061 BaseOp = X86ISD::INC;
19062 Cond = X86::COND_O;
19065 BaseOp = X86ISD::ADD;
19066 Cond = X86::COND_O;
19069 BaseOp = X86ISD::ADD;
19070 Cond = X86::COND_B;
19073 // A subtract of one will be selected as a DEC. Note that DEC doesn't
19074 // set CF, so we can't do this for USUBO.
19075 if (isOneConstant(RHS)) {
19076 BaseOp = X86ISD::DEC;
19077 Cond = X86::COND_O;
19080 BaseOp = X86ISD::SUB;
19081 Cond = X86::COND_O;
19084 BaseOp = X86ISD::SUB;
19085 Cond = X86::COND_B;
19088 BaseOp = N->getValueType(0) == MVT::i8 ? X86ISD::SMUL8 : X86ISD::SMUL;
19089 Cond = X86::COND_O;
19091 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
19092 if (N->getValueType(0) == MVT::i8) {
19093 BaseOp = X86ISD::UMUL8;
19094 Cond = X86::COND_O;
19097 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
19099 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
19102 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
19103 DAG.getConstant(X86::COND_O, DL, MVT::i32),
19104 SDValue(Sum.getNode(), 2));
19106 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
19110 // Also sets EFLAGS.
19111 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
19112 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
19115 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
19116 DAG.getConstant(Cond, DL, MVT::i32),
19117 SDValue(Sum.getNode(), 1));
19119 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
19122 /// Returns true if the operand type is exactly twice the native width, and
19123 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
19124 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
19125 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
19126 bool X86TargetLowering::needsCmpXchgNb(Type *MemType) const {
19127 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
19130 return !Subtarget->is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
19131 else if (OpWidth == 128)
19132 return Subtarget->hasCmpxchg16b();
19137 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
19138 return needsCmpXchgNb(SI->getValueOperand()->getType());
19141 // Note: this turns large loads into lock cmpxchg8b/16b.
19142 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.
19143 TargetLowering::AtomicExpansionKind
19144 X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
19145 auto PTy = cast<PointerType>(LI->getPointerOperand()->getType());
19146 return needsCmpXchgNb(PTy->getElementType()) ? AtomicExpansionKind::CmpXChg
19147 : AtomicExpansionKind::None;
19150 TargetLowering::AtomicExpansionKind
19151 X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
19152 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
19153 Type *MemType = AI->getType();
19155 // If the operand is too big, we must see if cmpxchg8/16b is available
19156 // and default to library calls otherwise.
19157 if (MemType->getPrimitiveSizeInBits() > NativeWidth) {
19158 return needsCmpXchgNb(MemType) ? AtomicExpansionKind::CmpXChg
19159 : AtomicExpansionKind::None;
19162 AtomicRMWInst::BinOp Op = AI->getOperation();
19165 llvm_unreachable("Unknown atomic operation");
19166 case AtomicRMWInst::Xchg:
19167 case AtomicRMWInst::Add:
19168 case AtomicRMWInst::Sub:
19169 // It's better to use xadd, xsub or xchg for these in all cases.
19170 return AtomicExpansionKind::None;
19171 case AtomicRMWInst::Or:
19172 case AtomicRMWInst::And:
19173 case AtomicRMWInst::Xor:
19174 // If the atomicrmw's result isn't actually used, we can just add a "lock"
19175 // prefix to a normal instruction for these operations.
19176 return !AI->use_empty() ? AtomicExpansionKind::CmpXChg
19177 : AtomicExpansionKind::None;
19178 case AtomicRMWInst::Nand:
19179 case AtomicRMWInst::Max:
19180 case AtomicRMWInst::Min:
19181 case AtomicRMWInst::UMax:
19182 case AtomicRMWInst::UMin:
19183 // These always require a non-trivial set of data operations on x86. We must
19184 // use a cmpxchg loop.
19185 return AtomicExpansionKind::CmpXChg;
19189 static bool hasMFENCE(const X86Subtarget& Subtarget) {
19190 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
19191 // no-sse2). There isn't any reason to disable it if the target processor
19193 return Subtarget.hasSSE2() || Subtarget.is64Bit();
19197 X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
19198 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
19199 Type *MemType = AI->getType();
19200 // Accesses larger than the native width are turned into cmpxchg/libcalls, so
19201 // there is no benefit in turning such RMWs into loads, and it is actually
19202 // harmful as it introduces a mfence.
19203 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
19206 auto Builder = IRBuilder<>(AI);
19207 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
19208 auto SynchScope = AI->getSynchScope();
19209 // We must restrict the ordering to avoid generating loads with Release or
19210 // ReleaseAcquire orderings.
19211 auto Order = AtomicCmpXchgInst::getStrongestFailureOrdering(AI->getOrdering());
19212 auto Ptr = AI->getPointerOperand();
19214 // Before the load we need a fence. Here is an example lifted from
19215 // http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf showing why a fence
19218 // x.store(1, relaxed);
19219 // r1 = y.fetch_add(0, release);
19221 // y.fetch_add(42, acquire);
19222 // r2 = x.load(relaxed);
19223 // r1 = r2 = 0 is impossible, but becomes possible if the idempotent rmw is
19224 // lowered to just a load without a fence. A mfence flushes the store buffer,
19225 // making the optimization clearly correct.
19226 // FIXME: it is required if isAtLeastRelease(Order) but it is not clear
19227 // otherwise, we might be able to be more aggressive on relaxed idempotent
19228 // rmw. In practice, they do not look useful, so we don't try to be
19229 // especially clever.
19230 if (SynchScope == SingleThread)
19231 // FIXME: we could just insert an X86ISD::MEMBARRIER here, except we are at
19232 // the IR level, so we must wrap it in an intrinsic.
19235 if (!hasMFENCE(*Subtarget))
19236 // FIXME: it might make sense to use a locked operation here but on a
19237 // different cache-line to prevent cache-line bouncing. In practice it
19238 // is probably a small win, and x86 processors without mfence are rare
19239 // enough that we do not bother.
19243 llvm::Intrinsic::getDeclaration(M, Intrinsic::x86_sse2_mfence);
19244 Builder.CreateCall(MFence, {});
19246 // Finally we can emit the atomic load.
19247 LoadInst *Loaded = Builder.CreateAlignedLoad(Ptr,
19248 AI->getType()->getPrimitiveSizeInBits());
19249 Loaded->setAtomic(Order, SynchScope);
19250 AI->replaceAllUsesWith(Loaded);
19251 AI->eraseFromParent();
19255 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
19256 SelectionDAG &DAG) {
19258 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
19259 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
19260 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
19261 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
19263 // The only fence that needs an instruction is a sequentially-consistent
19264 // cross-thread fence.
19265 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
19266 if (hasMFENCE(*Subtarget))
19267 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
19269 SDValue Chain = Op.getOperand(0);
19270 SDValue Zero = DAG.getConstant(0, dl, MVT::i32);
19272 DAG.getRegister(X86::ESP, MVT::i32), // Base
19273 DAG.getTargetConstant(1, dl, MVT::i8), // Scale
19274 DAG.getRegister(0, MVT::i32), // Index
19275 DAG.getTargetConstant(0, dl, MVT::i32), // Disp
19276 DAG.getRegister(0, MVT::i32), // Segment.
19280 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
19281 return SDValue(Res, 0);
19284 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
19285 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
19288 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
19289 SelectionDAG &DAG) {
19290 MVT T = Op.getSimpleValueType();
19294 switch(T.SimpleTy) {
19295 default: llvm_unreachable("Invalid value type!");
19296 case MVT::i8: Reg = X86::AL; size = 1; break;
19297 case MVT::i16: Reg = X86::AX; size = 2; break;
19298 case MVT::i32: Reg = X86::EAX; size = 4; break;
19300 assert(Subtarget->is64Bit() && "Node not type legal!");
19301 Reg = X86::RAX; size = 8;
19304 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
19305 Op.getOperand(2), SDValue());
19306 SDValue Ops[] = { cpIn.getValue(0),
19309 DAG.getTargetConstant(size, DL, MVT::i8),
19310 cpIn.getValue(1) };
19311 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
19312 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
19313 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
19317 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
19318 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
19319 MVT::i32, cpOut.getValue(2));
19320 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
19321 DAG.getConstant(X86::COND_E, DL, MVT::i8),
19324 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
19325 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
19326 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
19330 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
19331 SelectionDAG &DAG) {
19332 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
19333 MVT DstVT = Op.getSimpleValueType();
19335 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
19336 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19337 if (DstVT != MVT::f64)
19338 // This conversion needs to be expanded.
19341 SDValue InVec = Op->getOperand(0);
19343 unsigned NumElts = SrcVT.getVectorNumElements();
19344 MVT SVT = SrcVT.getVectorElementType();
19346 // Widen the vector in input in the case of MVT::v2i32.
19347 // Example: from MVT::v2i32 to MVT::v4i32.
19348 SmallVector<SDValue, 16> Elts;
19349 for (unsigned i = 0, e = NumElts; i != e; ++i)
19350 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
19351 DAG.getIntPtrConstant(i, dl)));
19353 // Explicitly mark the extra elements as Undef.
19354 Elts.append(NumElts, DAG.getUNDEF(SVT));
19356 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
19357 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
19358 SDValue ToV2F64 = DAG.getBitcast(MVT::v2f64, BV);
19359 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
19360 DAG.getIntPtrConstant(0, dl));
19363 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
19364 Subtarget->hasMMX() && "Unexpected custom BITCAST");
19365 assert((DstVT == MVT::i64 ||
19366 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
19367 "Unexpected custom BITCAST");
19368 // i64 <=> MMX conversions are Legal.
19369 if (SrcVT==MVT::i64 && DstVT.isVector())
19371 if (DstVT==MVT::i64 && SrcVT.isVector())
19373 // MMX <=> MMX conversions are Legal.
19374 if (SrcVT.isVector() && DstVT.isVector())
19376 // All other conversions need to be expanded.
19380 /// Compute the horizontal sum of bytes in V for the elements of VT.
19382 /// Requires V to be a byte vector and VT to be an integer vector type with
19383 /// wider elements than V's type. The width of the elements of VT determines
19384 /// how many bytes of V are summed horizontally to produce each element of the
19386 static SDValue LowerHorizontalByteSum(SDValue V, MVT VT,
19387 const X86Subtarget *Subtarget,
19388 SelectionDAG &DAG) {
19390 MVT ByteVecVT = V.getSimpleValueType();
19391 MVT EltVT = VT.getVectorElementType();
19392 int NumElts = VT.getVectorNumElements();
19393 assert(ByteVecVT.getVectorElementType() == MVT::i8 &&
19394 "Expected value to have byte element type.");
19395 assert(EltVT != MVT::i8 &&
19396 "Horizontal byte sum only makes sense for wider elements!");
19397 unsigned VecSize = VT.getSizeInBits();
19398 assert(ByteVecVT.getSizeInBits() == VecSize && "Cannot change vector size!");
19400 // PSADBW instruction horizontally add all bytes and leave the result in i64
19401 // chunks, thus directly computes the pop count for v2i64 and v4i64.
19402 if (EltVT == MVT::i64) {
19403 SDValue Zeros = getZeroVector(ByteVecVT, Subtarget, DAG, DL);
19404 MVT SadVecVT = MVT::getVectorVT(MVT::i64, VecSize / 64);
19405 V = DAG.getNode(X86ISD::PSADBW, DL, SadVecVT, V, Zeros);
19406 return DAG.getBitcast(VT, V);
19409 if (EltVT == MVT::i32) {
19410 // We unpack the low half and high half into i32s interleaved with zeros so
19411 // that we can use PSADBW to horizontally sum them. The most useful part of
19412 // this is that it lines up the results of two PSADBW instructions to be
19413 // two v2i64 vectors which concatenated are the 4 population counts. We can
19414 // then use PACKUSWB to shrink and concatenate them into a v4i32 again.
19415 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, DL);
19416 SDValue Low = DAG.getNode(X86ISD::UNPCKL, DL, VT, V, Zeros);
19417 SDValue High = DAG.getNode(X86ISD::UNPCKH, DL, VT, V, Zeros);
19419 // Do the horizontal sums into two v2i64s.
19420 Zeros = getZeroVector(ByteVecVT, Subtarget, DAG, DL);
19421 MVT SadVecVT = MVT::getVectorVT(MVT::i64, VecSize / 64);
19422 Low = DAG.getNode(X86ISD::PSADBW, DL, SadVecVT,
19423 DAG.getBitcast(ByteVecVT, Low), Zeros);
19424 High = DAG.getNode(X86ISD::PSADBW, DL, SadVecVT,
19425 DAG.getBitcast(ByteVecVT, High), Zeros);
19427 // Merge them together.
19428 MVT ShortVecVT = MVT::getVectorVT(MVT::i16, VecSize / 16);
19429 V = DAG.getNode(X86ISD::PACKUS, DL, ByteVecVT,
19430 DAG.getBitcast(ShortVecVT, Low),
19431 DAG.getBitcast(ShortVecVT, High));
19433 return DAG.getBitcast(VT, V);
19436 // The only element type left is i16.
19437 assert(EltVT == MVT::i16 && "Unknown how to handle type");
19439 // To obtain pop count for each i16 element starting from the pop count for
19440 // i8 elements, shift the i16s left by 8, sum as i8s, and then shift as i16s
19441 // right by 8. It is important to shift as i16s as i8 vector shift isn't
19442 // directly supported.
19443 SmallVector<SDValue, 16> Shifters(NumElts, DAG.getConstant(8, DL, EltVT));
19444 SDValue Shifter = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Shifters);
19445 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, DAG.getBitcast(VT, V), Shifter);
19446 V = DAG.getNode(ISD::ADD, DL, ByteVecVT, DAG.getBitcast(ByteVecVT, Shl),
19447 DAG.getBitcast(ByteVecVT, V));
19448 return DAG.getNode(ISD::SRL, DL, VT, DAG.getBitcast(VT, V), Shifter);
19451 static SDValue LowerVectorCTPOPInRegLUT(SDValue Op, SDLoc DL,
19452 const X86Subtarget *Subtarget,
19453 SelectionDAG &DAG) {
19454 MVT VT = Op.getSimpleValueType();
19455 MVT EltVT = VT.getVectorElementType();
19456 unsigned VecSize = VT.getSizeInBits();
19458 // Implement a lookup table in register by using an algorithm based on:
19459 // http://wm.ite.pl/articles/sse-popcount.html
19461 // The general idea is that every lower byte nibble in the input vector is an
19462 // index into a in-register pre-computed pop count table. We then split up the
19463 // input vector in two new ones: (1) a vector with only the shifted-right
19464 // higher nibbles for each byte and (2) a vector with the lower nibbles (and
19465 // masked out higher ones) for each byte. PSHUB is used separately with both
19466 // to index the in-register table. Next, both are added and the result is a
19467 // i8 vector where each element contains the pop count for input byte.
19469 // To obtain the pop count for elements != i8, we follow up with the same
19470 // approach and use additional tricks as described below.
19472 const int LUT[16] = {/* 0 */ 0, /* 1 */ 1, /* 2 */ 1, /* 3 */ 2,
19473 /* 4 */ 1, /* 5 */ 2, /* 6 */ 2, /* 7 */ 3,
19474 /* 8 */ 1, /* 9 */ 2, /* a */ 2, /* b */ 3,
19475 /* c */ 2, /* d */ 3, /* e */ 3, /* f */ 4};
19477 int NumByteElts = VecSize / 8;
19478 MVT ByteVecVT = MVT::getVectorVT(MVT::i8, NumByteElts);
19479 SDValue In = DAG.getBitcast(ByteVecVT, Op);
19480 SmallVector<SDValue, 16> LUTVec;
19481 for (int i = 0; i < NumByteElts; ++i)
19482 LUTVec.push_back(DAG.getConstant(LUT[i % 16], DL, MVT::i8));
19483 SDValue InRegLUT = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, LUTVec);
19484 SmallVector<SDValue, 16> Mask0F(NumByteElts,
19485 DAG.getConstant(0x0F, DL, MVT::i8));
19486 SDValue M0F = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, Mask0F);
19489 SmallVector<SDValue, 16> Four(NumByteElts, DAG.getConstant(4, DL, MVT::i8));
19490 SDValue FourV = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, Four);
19491 SDValue HighNibbles = DAG.getNode(ISD::SRL, DL, ByteVecVT, In, FourV);
19494 SDValue LowNibbles = DAG.getNode(ISD::AND, DL, ByteVecVT, In, M0F);
19496 // The input vector is used as the shuffle mask that index elements into the
19497 // LUT. After counting low and high nibbles, add the vector to obtain the
19498 // final pop count per i8 element.
19499 SDValue HighPopCnt =
19500 DAG.getNode(X86ISD::PSHUFB, DL, ByteVecVT, InRegLUT, HighNibbles);
19501 SDValue LowPopCnt =
19502 DAG.getNode(X86ISD::PSHUFB, DL, ByteVecVT, InRegLUT, LowNibbles);
19503 SDValue PopCnt = DAG.getNode(ISD::ADD, DL, ByteVecVT, HighPopCnt, LowPopCnt);
19505 if (EltVT == MVT::i8)
19508 return LowerHorizontalByteSum(PopCnt, VT, Subtarget, DAG);
19511 static SDValue LowerVectorCTPOPBitmath(SDValue Op, SDLoc DL,
19512 const X86Subtarget *Subtarget,
19513 SelectionDAG &DAG) {
19514 MVT VT = Op.getSimpleValueType();
19515 assert(VT.is128BitVector() &&
19516 "Only 128-bit vector bitmath lowering supported.");
19518 int VecSize = VT.getSizeInBits();
19519 MVT EltVT = VT.getVectorElementType();
19520 int Len = EltVT.getSizeInBits();
19522 // This is the vectorized version of the "best" algorithm from
19523 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
19524 // with a minor tweak to use a series of adds + shifts instead of vector
19525 // multiplications. Implemented for all integer vector types. We only use
19526 // this when we don't have SSSE3 which allows a LUT-based lowering that is
19527 // much faster, even faster than using native popcnt instructions.
19529 auto GetShift = [&](unsigned OpCode, SDValue V, int Shifter) {
19530 MVT VT = V.getSimpleValueType();
19531 SmallVector<SDValue, 32> Shifters(
19532 VT.getVectorNumElements(),
19533 DAG.getConstant(Shifter, DL, VT.getVectorElementType()));
19534 return DAG.getNode(OpCode, DL, VT, V,
19535 DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Shifters));
19537 auto GetMask = [&](SDValue V, APInt Mask) {
19538 MVT VT = V.getSimpleValueType();
19539 SmallVector<SDValue, 32> Masks(
19540 VT.getVectorNumElements(),
19541 DAG.getConstant(Mask, DL, VT.getVectorElementType()));
19542 return DAG.getNode(ISD::AND, DL, VT, V,
19543 DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Masks));
19546 // We don't want to incur the implicit masks required to SRL vNi8 vectors on
19547 // x86, so set the SRL type to have elements at least i16 wide. This is
19548 // correct because all of our SRLs are followed immediately by a mask anyways
19549 // that handles any bits that sneak into the high bits of the byte elements.
19550 MVT SrlVT = Len > 8 ? VT : MVT::getVectorVT(MVT::i16, VecSize / 16);
19554 // v = v - ((v >> 1) & 0x55555555...)
19556 DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 1));
19557 SDValue And = GetMask(Srl, APInt::getSplat(Len, APInt(8, 0x55)));
19558 V = DAG.getNode(ISD::SUB, DL, VT, V, And);
19560 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
19561 SDValue AndLHS = GetMask(V, APInt::getSplat(Len, APInt(8, 0x33)));
19562 Srl = DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 2));
19563 SDValue AndRHS = GetMask(Srl, APInt::getSplat(Len, APInt(8, 0x33)));
19564 V = DAG.getNode(ISD::ADD, DL, VT, AndLHS, AndRHS);
19566 // v = (v + (v >> 4)) & 0x0F0F0F0F...
19567 Srl = DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 4));
19568 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, V, Srl);
19569 V = GetMask(Add, APInt::getSplat(Len, APInt(8, 0x0F)));
19571 // At this point, V contains the byte-wise population count, and we are
19572 // merely doing a horizontal sum if necessary to get the wider element
19574 if (EltVT == MVT::i8)
19577 return LowerHorizontalByteSum(
19578 DAG.getBitcast(MVT::getVectorVT(MVT::i8, VecSize / 8), V), VT, Subtarget,
19582 static SDValue LowerVectorCTPOP(SDValue Op, const X86Subtarget *Subtarget,
19583 SelectionDAG &DAG) {
19584 MVT VT = Op.getSimpleValueType();
19585 // FIXME: Need to add AVX-512 support here!
19586 assert((VT.is256BitVector() || VT.is128BitVector()) &&
19587 "Unknown CTPOP type to handle");
19588 SDLoc DL(Op.getNode());
19589 SDValue Op0 = Op.getOperand(0);
19591 if (!Subtarget->hasSSSE3()) {
19592 // We can't use the fast LUT approach, so fall back on vectorized bitmath.
19593 assert(VT.is128BitVector() && "Only 128-bit vectors supported in SSE!");
19594 return LowerVectorCTPOPBitmath(Op0, DL, Subtarget, DAG);
19597 if (VT.is256BitVector() && !Subtarget->hasInt256()) {
19598 unsigned NumElems = VT.getVectorNumElements();
19600 // Extract each 128-bit vector, compute pop count and concat the result.
19601 SDValue LHS = Extract128BitVector(Op0, 0, DAG, DL);
19602 SDValue RHS = Extract128BitVector(Op0, NumElems/2, DAG, DL);
19604 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT,
19605 LowerVectorCTPOPInRegLUT(LHS, DL, Subtarget, DAG),
19606 LowerVectorCTPOPInRegLUT(RHS, DL, Subtarget, DAG));
19609 return LowerVectorCTPOPInRegLUT(Op0, DL, Subtarget, DAG);
19612 static SDValue LowerCTPOP(SDValue Op, const X86Subtarget *Subtarget,
19613 SelectionDAG &DAG) {
19614 assert(Op.getSimpleValueType().isVector() &&
19615 "We only do custom lowering for vector population count.");
19616 return LowerVectorCTPOP(Op, Subtarget, DAG);
19619 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
19620 SDNode *Node = Op.getNode();
19622 EVT T = Node->getValueType(0);
19623 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
19624 DAG.getConstant(0, dl, T), Node->getOperand(2));
19625 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
19626 cast<AtomicSDNode>(Node)->getMemoryVT(),
19627 Node->getOperand(0),
19628 Node->getOperand(1), negOp,
19629 cast<AtomicSDNode>(Node)->getMemOperand(),
19630 cast<AtomicSDNode>(Node)->getOrdering(),
19631 cast<AtomicSDNode>(Node)->getSynchScope());
19634 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
19635 SDNode *Node = Op.getNode();
19637 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
19639 // Convert seq_cst store -> xchg
19640 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
19641 // FIXME: On 32-bit, store -> fist or movq would be more efficient
19642 // (The only way to get a 16-byte store is cmpxchg16b)
19643 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
19644 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
19645 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
19646 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
19647 cast<AtomicSDNode>(Node)->getMemoryVT(),
19648 Node->getOperand(0),
19649 Node->getOperand(1), Node->getOperand(2),
19650 cast<AtomicSDNode>(Node)->getMemOperand(),
19651 cast<AtomicSDNode>(Node)->getOrdering(),
19652 cast<AtomicSDNode>(Node)->getSynchScope());
19653 return Swap.getValue(1);
19655 // Other atomic stores have a simple pattern.
19659 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
19660 MVT VT = Op.getNode()->getSimpleValueType(0);
19662 // Let legalize expand this if it isn't a legal type yet.
19663 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
19666 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
19669 bool ExtraOp = false;
19670 switch (Op.getOpcode()) {
19671 default: llvm_unreachable("Invalid code");
19672 case ISD::ADDC: Opc = X86ISD::ADD; break;
19673 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
19674 case ISD::SUBC: Opc = X86ISD::SUB; break;
19675 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
19679 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19681 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19682 Op.getOperand(1), Op.getOperand(2));
19685 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
19686 SelectionDAG &DAG) {
19687 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
19689 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
19690 // which returns the values as { float, float } (in XMM0) or
19691 // { double, double } (which is returned in XMM0, XMM1).
19693 SDValue Arg = Op.getOperand(0);
19694 EVT ArgVT = Arg.getValueType();
19695 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
19697 TargetLowering::ArgListTy Args;
19698 TargetLowering::ArgListEntry Entry;
19702 Entry.isSExt = false;
19703 Entry.isZExt = false;
19704 Args.push_back(Entry);
19706 bool isF64 = ArgVT == MVT::f64;
19707 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
19708 // the small struct {f32, f32} is returned in (eax, edx). For f64,
19709 // the results are returned via SRet in memory.
19710 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
19711 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19713 DAG.getExternalSymbol(LibcallName, TLI.getPointerTy(DAG.getDataLayout()));
19715 Type *RetTy = isF64
19716 ? (Type*)StructType::get(ArgTy, ArgTy, nullptr)
19717 : (Type*)VectorType::get(ArgTy, 4);
19719 TargetLowering::CallLoweringInfo CLI(DAG);
19720 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
19721 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
19723 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
19726 // Returned in xmm0 and xmm1.
19727 return CallResult.first;
19729 // Returned in bits 0:31 and 32:64 xmm0.
19730 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19731 CallResult.first, DAG.getIntPtrConstant(0, dl));
19732 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19733 CallResult.first, DAG.getIntPtrConstant(1, dl));
19734 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
19735 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
19738 /// Widen a vector input to a vector of NVT. The
19739 /// input vector must have the same element type as NVT.
19740 static SDValue ExtendToType(SDValue InOp, MVT NVT, SelectionDAG &DAG,
19741 bool FillWithZeroes = false) {
19742 // Check if InOp already has the right width.
19743 MVT InVT = InOp.getSimpleValueType();
19747 if (InOp.isUndef())
19748 return DAG.getUNDEF(NVT);
19750 assert(InVT.getVectorElementType() == NVT.getVectorElementType() &&
19751 "input and widen element type must match");
19753 unsigned InNumElts = InVT.getVectorNumElements();
19754 unsigned WidenNumElts = NVT.getVectorNumElements();
19755 assert(WidenNumElts > InNumElts && WidenNumElts % InNumElts == 0 &&
19756 "Unexpected request for vector widening");
19758 EVT EltVT = NVT.getVectorElementType();
19761 if (InOp.getOpcode() == ISD::CONCAT_VECTORS &&
19762 InOp.getNumOperands() == 2) {
19763 SDValue N1 = InOp.getOperand(1);
19764 if ((ISD::isBuildVectorAllZeros(N1.getNode()) && FillWithZeroes) ||
19766 InOp = InOp.getOperand(0);
19767 InVT = InOp.getSimpleValueType();
19768 InNumElts = InVT.getVectorNumElements();
19771 if (ISD::isBuildVectorOfConstantSDNodes(InOp.getNode()) ||
19772 ISD::isBuildVectorOfConstantFPSDNodes(InOp.getNode())) {
19773 SmallVector<SDValue, 16> Ops;
19774 for (unsigned i = 0; i < InNumElts; ++i)
19775 Ops.push_back(InOp.getOperand(i));
19777 SDValue FillVal = FillWithZeroes ? DAG.getConstant(0, dl, EltVT) :
19778 DAG.getUNDEF(EltVT);
19779 for (unsigned i = 0; i < WidenNumElts - InNumElts; ++i)
19780 Ops.push_back(FillVal);
19781 return DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, Ops);
19783 SDValue FillVal = FillWithZeroes ? DAG.getConstant(0, dl, NVT) :
19785 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, NVT, FillVal,
19786 InOp, DAG.getIntPtrConstant(0, dl));
19789 static SDValue LowerMSCATTER(SDValue Op, const X86Subtarget *Subtarget,
19790 SelectionDAG &DAG) {
19791 assert(Subtarget->hasAVX512() &&
19792 "MGATHER/MSCATTER are supported on AVX-512 arch only");
19794 // X86 scatter kills mask register, so its type should be added to
19795 // the list of return values.
19796 // If the "scatter" has 2 return values, it is already handled.
19797 if (Op.getNode()->getNumValues() == 2)
19800 MaskedScatterSDNode *N = cast<MaskedScatterSDNode>(Op.getNode());
19801 SDValue Src = N->getValue();
19802 MVT VT = Src.getSimpleValueType();
19803 assert(VT.getScalarSizeInBits() >= 32 && "Unsupported scatter op");
19806 SDValue NewScatter;
19807 SDValue Index = N->getIndex();
19808 SDValue Mask = N->getMask();
19809 SDValue Chain = N->getChain();
19810 SDValue BasePtr = N->getBasePtr();
19811 MVT MemVT = N->getMemoryVT().getSimpleVT();
19812 MVT IndexVT = Index.getSimpleValueType();
19813 MVT MaskVT = Mask.getSimpleValueType();
19815 if (MemVT.getScalarSizeInBits() < VT.getScalarSizeInBits()) {
19816 // The v2i32 value was promoted to v2i64.
19817 // Now we "redo" the type legalizer's work and widen the original
19818 // v2i32 value to v4i32. The original v2i32 is retrieved from v2i64
19820 assert((MemVT == MVT::v2i32 && VT == MVT::v2i64) &&
19821 "Unexpected memory type");
19822 int ShuffleMask[] = {0, 2, -1, -1};
19823 Src = DAG.getVectorShuffle(MVT::v4i32, dl, DAG.getBitcast(MVT::v4i32, Src),
19824 DAG.getUNDEF(MVT::v4i32), ShuffleMask);
19825 // Now we have 4 elements instead of 2.
19826 // Expand the index.
19827 MVT NewIndexVT = MVT::getVectorVT(IndexVT.getScalarType(), 4);
19828 Index = ExtendToType(Index, NewIndexVT, DAG);
19830 // Expand the mask with zeroes
19831 // Mask may be <2 x i64> or <2 x i1> at this moment
19832 assert((MaskVT == MVT::v2i1 || MaskVT == MVT::v2i64) &&
19833 "Unexpected mask type");
19834 MVT ExtMaskVT = MVT::getVectorVT(MaskVT.getScalarType(), 4);
19835 Mask = ExtendToType(Mask, ExtMaskVT, DAG, true);
19839 unsigned NumElts = VT.getVectorNumElements();
19840 if (!Subtarget->hasVLX() && !VT.is512BitVector() &&
19841 !Index.getSimpleValueType().is512BitVector()) {
19842 // AVX512F supports only 512-bit vectors. Or data or index should
19843 // be 512 bit wide. If now the both index and data are 256-bit, but
19844 // the vector contains 8 elements, we just sign-extend the index
19845 if (IndexVT == MVT::v8i32)
19846 // Just extend index
19847 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
19849 // The minimal number of elts in scatter is 8
19852 MVT NewIndexVT = MVT::getVectorVT(IndexVT.getScalarType(), NumElts);
19853 // Use original index here, do not modify the index twice
19854 Index = ExtendToType(N->getIndex(), NewIndexVT, DAG);
19855 if (IndexVT.getScalarType() == MVT::i32)
19856 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
19859 // At this point we have promoted mask operand
19860 assert(MaskVT.getScalarSizeInBits() >= 32 && "unexpected mask type");
19861 MVT ExtMaskVT = MVT::getVectorVT(MaskVT.getScalarType(), NumElts);
19862 // Use the original mask here, do not modify the mask twice
19863 Mask = ExtendToType(N->getMask(), ExtMaskVT, DAG, true);
19865 // The value that should be stored
19866 MVT NewVT = MVT::getVectorVT(VT.getScalarType(), NumElts);
19867 Src = ExtendToType(Src, NewVT, DAG);
19870 // If the mask is "wide" at this point - truncate it to i1 vector
19871 MVT BitMaskVT = MVT::getVectorVT(MVT::i1, NumElts);
19872 Mask = DAG.getNode(ISD::TRUNCATE, dl, BitMaskVT, Mask);
19874 // The mask is killed by scatter, add it to the values
19875 SDVTList VTs = DAG.getVTList(BitMaskVT, MVT::Other);
19876 SDValue Ops[] = {Chain, Src, Mask, BasePtr, Index};
19877 NewScatter = DAG.getMaskedScatter(VTs, N->getMemoryVT(), dl, Ops,
19878 N->getMemOperand());
19879 DAG.ReplaceAllUsesWith(Op, SDValue(NewScatter.getNode(), 1));
19880 return SDValue(NewScatter.getNode(), 0);
19883 static SDValue LowerMLOAD(SDValue Op, const X86Subtarget *Subtarget,
19884 SelectionDAG &DAG) {
19886 MaskedLoadSDNode *N = cast<MaskedLoadSDNode>(Op.getNode());
19887 MVT VT = Op.getSimpleValueType();
19888 SDValue Mask = N->getMask();
19891 if (Subtarget->hasAVX512() && !Subtarget->hasVLX() &&
19892 !VT.is512BitVector() && Mask.getValueType() == MVT::v8i1) {
19893 // This operation is legal for targets with VLX, but without
19894 // VLX the vector should be widened to 512 bit
19895 unsigned NumEltsInWideVec = 512/VT.getScalarSizeInBits();
19896 MVT WideDataVT = MVT::getVectorVT(VT.getScalarType(), NumEltsInWideVec);
19897 MVT WideMaskVT = MVT::getVectorVT(MVT::i1, NumEltsInWideVec);
19898 SDValue Src0 = N->getSrc0();
19899 Src0 = ExtendToType(Src0, WideDataVT, DAG);
19900 Mask = ExtendToType(Mask, WideMaskVT, DAG, true);
19901 SDValue NewLoad = DAG.getMaskedLoad(WideDataVT, dl, N->getChain(),
19902 N->getBasePtr(), Mask, Src0,
19903 N->getMemoryVT(), N->getMemOperand(),
19904 N->getExtensionType());
19906 SDValue Exract = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
19907 NewLoad.getValue(0),
19908 DAG.getIntPtrConstant(0, dl));
19909 SDValue RetOps[] = {Exract, NewLoad.getValue(1)};
19910 return DAG.getMergeValues(RetOps, dl);
19915 static SDValue LowerMSTORE(SDValue Op, const X86Subtarget *Subtarget,
19916 SelectionDAG &DAG) {
19917 MaskedStoreSDNode *N = cast<MaskedStoreSDNode>(Op.getNode());
19918 SDValue DataToStore = N->getValue();
19919 MVT VT = DataToStore.getSimpleValueType();
19920 SDValue Mask = N->getMask();
19923 if (Subtarget->hasAVX512() && !Subtarget->hasVLX() &&
19924 !VT.is512BitVector() && Mask.getValueType() == MVT::v8i1) {
19925 // This operation is legal for targets with VLX, but without
19926 // VLX the vector should be widened to 512 bit
19927 unsigned NumEltsInWideVec = 512/VT.getScalarSizeInBits();
19928 MVT WideDataVT = MVT::getVectorVT(VT.getScalarType(), NumEltsInWideVec);
19929 MVT WideMaskVT = MVT::getVectorVT(MVT::i1, NumEltsInWideVec);
19930 DataToStore = ExtendToType(DataToStore, WideDataVT, DAG);
19931 Mask = ExtendToType(Mask, WideMaskVT, DAG, true);
19932 return DAG.getMaskedStore(N->getChain(), dl, DataToStore, N->getBasePtr(),
19933 Mask, N->getMemoryVT(), N->getMemOperand(),
19934 N->isTruncatingStore());
19939 static SDValue LowerMGATHER(SDValue Op, const X86Subtarget *Subtarget,
19940 SelectionDAG &DAG) {
19941 assert(Subtarget->hasAVX512() &&
19942 "MGATHER/MSCATTER are supported on AVX-512 arch only");
19944 MaskedGatherSDNode *N = cast<MaskedGatherSDNode>(Op.getNode());
19946 MVT VT = Op.getSimpleValueType();
19947 SDValue Index = N->getIndex();
19948 SDValue Mask = N->getMask();
19949 SDValue Src0 = N->getValue();
19950 MVT IndexVT = Index.getSimpleValueType();
19951 MVT MaskVT = Mask.getSimpleValueType();
19953 unsigned NumElts = VT.getVectorNumElements();
19954 assert(VT.getScalarSizeInBits() >= 32 && "Unsupported gather op");
19956 if (!Subtarget->hasVLX() && !VT.is512BitVector() &&
19957 !Index.getSimpleValueType().is512BitVector()) {
19958 // AVX512F supports only 512-bit vectors. Or data or index should
19959 // be 512 bit wide. If now the both index and data are 256-bit, but
19960 // the vector contains 8 elements, we just sign-extend the index
19961 if (NumElts == 8) {
19962 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
19963 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
19964 N->getOperand(3), Index };
19965 DAG.UpdateNodeOperands(N, Ops);
19969 // Minimal number of elements in Gather
19972 MVT NewIndexVT = MVT::getVectorVT(IndexVT.getScalarType(), NumElts);
19973 Index = ExtendToType(Index, NewIndexVT, DAG);
19974 if (IndexVT.getScalarType() == MVT::i32)
19975 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
19978 MVT MaskBitVT = MVT::getVectorVT(MVT::i1, NumElts);
19979 // At this point we have promoted mask operand
19980 assert(MaskVT.getScalarSizeInBits() >= 32 && "unexpected mask type");
19981 MVT ExtMaskVT = MVT::getVectorVT(MaskVT.getScalarType(), NumElts);
19982 Mask = ExtendToType(Mask, ExtMaskVT, DAG, true);
19983 Mask = DAG.getNode(ISD::TRUNCATE, dl, MaskBitVT, Mask);
19985 // The pass-thru value
19986 MVT NewVT = MVT::getVectorVT(VT.getScalarType(), NumElts);
19987 Src0 = ExtendToType(Src0, NewVT, DAG);
19989 SDValue Ops[] = { N->getChain(), Src0, Mask, N->getBasePtr(), Index };
19990 SDValue NewGather = DAG.getMaskedGather(DAG.getVTList(NewVT, MVT::Other),
19991 N->getMemoryVT(), dl, Ops,
19992 N->getMemOperand());
19993 SDValue Exract = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
19994 NewGather.getValue(0),
19995 DAG.getIntPtrConstant(0, dl));
19996 SDValue RetOps[] = {Exract, NewGather.getValue(1)};
19997 return DAG.getMergeValues(RetOps, dl);
20002 SDValue X86TargetLowering::LowerGC_TRANSITION_START(SDValue Op,
20003 SelectionDAG &DAG) const {
20004 // TODO: Eventually, the lowering of these nodes should be informed by or
20005 // deferred to the GC strategy for the function in which they appear. For
20006 // now, however, they must be lowered to something. Since they are logically
20007 // no-ops in the case of a null GC strategy (or a GC strategy which does not
20008 // require special handling for these nodes), lower them as literal NOOPs for
20010 SmallVector<SDValue, 2> Ops;
20012 Ops.push_back(Op.getOperand(0));
20013 if (Op->getGluedNode())
20014 Ops.push_back(Op->getOperand(Op->getNumOperands() - 1));
20017 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
20018 SDValue NOOP(DAG.getMachineNode(X86::NOOP, SDLoc(Op), VTs, Ops), 0);
20023 SDValue X86TargetLowering::LowerGC_TRANSITION_END(SDValue Op,
20024 SelectionDAG &DAG) const {
20025 // TODO: Eventually, the lowering of these nodes should be informed by or
20026 // deferred to the GC strategy for the function in which they appear. For
20027 // now, however, they must be lowered to something. Since they are logically
20028 // no-ops in the case of a null GC strategy (or a GC strategy which does not
20029 // require special handling for these nodes), lower them as literal NOOPs for
20031 SmallVector<SDValue, 2> Ops;
20033 Ops.push_back(Op.getOperand(0));
20034 if (Op->getGluedNode())
20035 Ops.push_back(Op->getOperand(Op->getNumOperands() - 1));
20038 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
20039 SDValue NOOP(DAG.getMachineNode(X86::NOOP, SDLoc(Op), VTs, Ops), 0);
20044 /// LowerOperation - Provide custom lowering hooks for some operations.
20046 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
20047 switch (Op.getOpcode()) {
20048 default: llvm_unreachable("Should not custom lower this!");
20049 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
20050 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
20051 return LowerCMP_SWAP(Op, Subtarget, DAG);
20052 case ISD::CTPOP: return LowerCTPOP(Op, Subtarget, DAG);
20053 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
20054 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
20055 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
20056 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, Subtarget, DAG);
20057 case ISD::VECTOR_SHUFFLE: return lowerVectorShuffle(Op, Subtarget, DAG);
20058 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
20059 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
20060 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
20061 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
20062 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
20063 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
20064 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
20065 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
20066 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
20067 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
20068 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
20069 case ISD::SHL_PARTS:
20070 case ISD::SRA_PARTS:
20071 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
20072 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
20073 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
20074 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
20075 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
20076 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
20077 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
20078 case ISD::SIGN_EXTEND_VECTOR_INREG:
20079 return LowerSIGN_EXTEND_VECTOR_INREG(Op, Subtarget, DAG);
20080 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
20081 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
20082 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
20083 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
20085 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
20086 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
20087 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
20088 case ISD::SETCC: return LowerSETCC(Op, DAG);
20089 case ISD::SETCCE: return LowerSETCCE(Op, DAG);
20090 case ISD::SELECT: return LowerSELECT(Op, DAG);
20091 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
20092 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
20093 case ISD::VASTART: return LowerVASTART(Op, DAG);
20094 case ISD::VAARG: return LowerVAARG(Op, DAG);
20095 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
20096 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, Subtarget, DAG);
20097 case ISD::INTRINSIC_VOID:
20098 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
20099 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
20100 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
20101 case ISD::FRAME_TO_ARGS_OFFSET:
20102 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
20103 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
20104 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
20105 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
20106 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
20107 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
20108 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
20109 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
20110 case ISD::CTLZ: return LowerCTLZ(Op, Subtarget, DAG);
20111 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, Subtarget, DAG);
20113 case ISD::CTTZ_ZERO_UNDEF: return LowerCTTZ(Op, DAG);
20114 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
20115 case ISD::UMUL_LOHI:
20116 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
20117 case ISD::ROTL: return LowerRotate(Op, Subtarget, DAG);
20120 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
20126 case ISD::UMULO: return LowerXALUO(Op, DAG);
20127 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
20128 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
20132 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
20133 case ISD::ADD: return LowerADD(Op, DAG);
20134 case ISD::SUB: return LowerSUB(Op, DAG);
20138 case ISD::UMIN: return LowerMINMAX(Op, DAG);
20139 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
20140 case ISD::MLOAD: return LowerMLOAD(Op, Subtarget, DAG);
20141 case ISD::MSTORE: return LowerMSTORE(Op, Subtarget, DAG);
20142 case ISD::MGATHER: return LowerMGATHER(Op, Subtarget, DAG);
20143 case ISD::MSCATTER: return LowerMSCATTER(Op, Subtarget, DAG);
20144 case ISD::GC_TRANSITION_START:
20145 return LowerGC_TRANSITION_START(Op, DAG);
20146 case ISD::GC_TRANSITION_END: return LowerGC_TRANSITION_END(Op, DAG);
20150 /// ReplaceNodeResults - Replace a node with an illegal result type
20151 /// with a new node built out of custom code.
20152 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
20153 SmallVectorImpl<SDValue>&Results,
20154 SelectionDAG &DAG) const {
20156 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20157 switch (N->getOpcode()) {
20159 llvm_unreachable("Do not know how to custom type legalize this operation!");
20160 case X86ISD::AVG: {
20161 // Legalize types for X86ISD::AVG by expanding vectors.
20162 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
20164 auto InVT = N->getValueType(0);
20165 auto InVTSize = InVT.getSizeInBits();
20166 const unsigned RegSize =
20167 (InVTSize > 128) ? ((InVTSize > 256) ? 512 : 256) : 128;
20168 assert((!Subtarget->hasAVX512() || RegSize < 512) &&
20169 "512-bit vector requires AVX512");
20170 assert((!Subtarget->hasAVX2() || RegSize < 256) &&
20171 "256-bit vector requires AVX2");
20173 auto ElemVT = InVT.getVectorElementType();
20174 auto RegVT = EVT::getVectorVT(*DAG.getContext(), ElemVT,
20175 RegSize / ElemVT.getSizeInBits());
20176 assert(RegSize % InVT.getSizeInBits() == 0);
20177 unsigned NumConcat = RegSize / InVT.getSizeInBits();
20179 SmallVector<SDValue, 16> Ops(NumConcat, DAG.getUNDEF(InVT));
20180 Ops[0] = N->getOperand(0);
20181 SDValue InVec0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, RegVT, Ops);
20182 Ops[0] = N->getOperand(1);
20183 SDValue InVec1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, RegVT, Ops);
20185 SDValue Res = DAG.getNode(X86ISD::AVG, dl, RegVT, InVec0, InVec1);
20186 Results.push_back(DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InVT, Res,
20187 DAG.getIntPtrConstant(0, dl)));
20190 // We might have generated v2f32 FMIN/FMAX operations. Widen them to v4f32.
20191 case X86ISD::FMINC:
20193 case X86ISD::FMAXC:
20194 case X86ISD::FMAX: {
20195 EVT VT = N->getValueType(0);
20196 assert(VT == MVT::v2f32 && "Unexpected type (!= v2f32) on FMIN/FMAX.");
20197 SDValue UNDEF = DAG.getUNDEF(VT);
20198 SDValue LHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
20199 N->getOperand(0), UNDEF);
20200 SDValue RHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
20201 N->getOperand(1), UNDEF);
20202 Results.push_back(DAG.getNode(N->getOpcode(), dl, MVT::v4f32, LHS, RHS));
20205 case ISD::SIGN_EXTEND_INREG:
20210 // We don't want to expand or promote these.
20217 case ISD::UDIVREM: {
20218 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
20219 Results.push_back(V);
20222 case ISD::FP_TO_SINT:
20223 case ISD::FP_TO_UINT: {
20224 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
20226 std::pair<SDValue,SDValue> Vals =
20227 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
20228 SDValue FIST = Vals.first, StackSlot = Vals.second;
20229 if (FIST.getNode()) {
20230 EVT VT = N->getValueType(0);
20231 // Return a load from the stack slot.
20232 if (StackSlot.getNode())
20233 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
20234 MachinePointerInfo(),
20235 false, false, false, 0));
20237 Results.push_back(FIST);
20241 case ISD::UINT_TO_FP: {
20242 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
20243 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
20244 N->getValueType(0) != MVT::v2f32)
20246 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
20248 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), dl,
20250 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
20251 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
20252 DAG.getBitcast(MVT::v2i64, VBias));
20253 Or = DAG.getBitcast(MVT::v2f64, Or);
20254 // TODO: Are there any fast-math-flags to propagate here?
20255 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
20256 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
20259 case ISD::FP_ROUND: {
20260 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
20262 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
20263 Results.push_back(V);
20266 case ISD::FP_EXTEND: {
20267 // Right now, only MVT::v2f32 has OperationAction for FP_EXTEND.
20268 // No other ValueType for FP_EXTEND should reach this point.
20269 assert(N->getValueType(0) == MVT::v2f32 &&
20270 "Do not know how to legalize this Node");
20273 case ISD::INTRINSIC_W_CHAIN: {
20274 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
20276 default : llvm_unreachable("Do not know how to custom type "
20277 "legalize this intrinsic operation!");
20278 case Intrinsic::x86_rdtsc:
20279 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
20281 case Intrinsic::x86_rdtscp:
20282 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
20284 case Intrinsic::x86_rdpmc:
20285 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
20288 case ISD::INTRINSIC_WO_CHAIN: {
20289 if (SDValue V = LowerINTRINSIC_WO_CHAIN(SDValue(N, 0), Subtarget, DAG))
20290 Results.push_back(V);
20293 case ISD::READCYCLECOUNTER: {
20294 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
20297 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
20298 EVT T = N->getValueType(0);
20299 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
20300 bool Regs64bit = T == MVT::i128;
20301 MVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
20302 SDValue cpInL, cpInH;
20303 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
20304 DAG.getConstant(0, dl, HalfT));
20305 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
20306 DAG.getConstant(1, dl, HalfT));
20307 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
20308 Regs64bit ? X86::RAX : X86::EAX,
20310 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
20311 Regs64bit ? X86::RDX : X86::EDX,
20312 cpInH, cpInL.getValue(1));
20313 SDValue swapInL, swapInH;
20314 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
20315 DAG.getConstant(0, dl, HalfT));
20316 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
20317 DAG.getConstant(1, dl, HalfT));
20318 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
20319 Regs64bit ? X86::RBX : X86::EBX,
20320 swapInL, cpInH.getValue(1));
20321 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
20322 Regs64bit ? X86::RCX : X86::ECX,
20323 swapInH, swapInL.getValue(1));
20324 SDValue Ops[] = { swapInH.getValue(0),
20326 swapInH.getValue(1) };
20327 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
20328 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
20329 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
20330 X86ISD::LCMPXCHG8_DAG;
20331 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
20332 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
20333 Regs64bit ? X86::RAX : X86::EAX,
20334 HalfT, Result.getValue(1));
20335 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
20336 Regs64bit ? X86::RDX : X86::EDX,
20337 HalfT, cpOutL.getValue(2));
20338 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
20340 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
20341 MVT::i32, cpOutH.getValue(2));
20343 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
20344 DAG.getConstant(X86::COND_E, dl, MVT::i8), EFLAGS);
20345 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
20347 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
20348 Results.push_back(Success);
20349 Results.push_back(EFLAGS.getValue(1));
20352 case ISD::ATOMIC_SWAP:
20353 case ISD::ATOMIC_LOAD_ADD:
20354 case ISD::ATOMIC_LOAD_SUB:
20355 case ISD::ATOMIC_LOAD_AND:
20356 case ISD::ATOMIC_LOAD_OR:
20357 case ISD::ATOMIC_LOAD_XOR:
20358 case ISD::ATOMIC_LOAD_NAND:
20359 case ISD::ATOMIC_LOAD_MIN:
20360 case ISD::ATOMIC_LOAD_MAX:
20361 case ISD::ATOMIC_LOAD_UMIN:
20362 case ISD::ATOMIC_LOAD_UMAX:
20363 case ISD::ATOMIC_LOAD: {
20364 // Delegate to generic TypeLegalization. Situations we can really handle
20365 // should have already been dealt with by AtomicExpandPass.cpp.
20368 case ISD::BITCAST: {
20369 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
20370 EVT DstVT = N->getValueType(0);
20371 EVT SrcVT = N->getOperand(0)->getValueType(0);
20373 if (SrcVT != MVT::f64 ||
20374 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
20377 unsigned NumElts = DstVT.getVectorNumElements();
20378 EVT SVT = DstVT.getVectorElementType();
20379 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
20380 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
20381 MVT::v2f64, N->getOperand(0));
20382 SDValue ToVecInt = DAG.getBitcast(WiderVT, Expanded);
20384 if (ExperimentalVectorWideningLegalization) {
20385 // If we are legalizing vectors by widening, we already have the desired
20386 // legal vector type, just return it.
20387 Results.push_back(ToVecInt);
20391 SmallVector<SDValue, 8> Elts;
20392 for (unsigned i = 0, e = NumElts; i != e; ++i)
20393 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
20394 ToVecInt, DAG.getIntPtrConstant(i, dl)));
20396 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
20401 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
20402 switch ((X86ISD::NodeType)Opcode) {
20403 case X86ISD::FIRST_NUMBER: break;
20404 case X86ISD::BSF: return "X86ISD::BSF";
20405 case X86ISD::BSR: return "X86ISD::BSR";
20406 case X86ISD::SHLD: return "X86ISD::SHLD";
20407 case X86ISD::SHRD: return "X86ISD::SHRD";
20408 case X86ISD::FAND: return "X86ISD::FAND";
20409 case X86ISD::FANDN: return "X86ISD::FANDN";
20410 case X86ISD::FOR: return "X86ISD::FOR";
20411 case X86ISD::FXOR: return "X86ISD::FXOR";
20412 case X86ISD::FILD: return "X86ISD::FILD";
20413 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
20414 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
20415 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
20416 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
20417 case X86ISD::FLD: return "X86ISD::FLD";
20418 case X86ISD::FST: return "X86ISD::FST";
20419 case X86ISD::CALL: return "X86ISD::CALL";
20420 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
20421 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
20422 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
20423 case X86ISD::BT: return "X86ISD::BT";
20424 case X86ISD::CMP: return "X86ISD::CMP";
20425 case X86ISD::COMI: return "X86ISD::COMI";
20426 case X86ISD::UCOMI: return "X86ISD::UCOMI";
20427 case X86ISD::CMPM: return "X86ISD::CMPM";
20428 case X86ISD::CMPMU: return "X86ISD::CMPMU";
20429 case X86ISD::CMPM_RND: return "X86ISD::CMPM_RND";
20430 case X86ISD::SETCC: return "X86ISD::SETCC";
20431 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
20432 case X86ISD::FSETCC: return "X86ISD::FSETCC";
20433 case X86ISD::FGETSIGNx86: return "X86ISD::FGETSIGNx86";
20434 case X86ISD::CMOV: return "X86ISD::CMOV";
20435 case X86ISD::BRCOND: return "X86ISD::BRCOND";
20436 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
20437 case X86ISD::IRET: return "X86ISD::IRET";
20438 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
20439 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
20440 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
20441 case X86ISD::Wrapper: return "X86ISD::Wrapper";
20442 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
20443 case X86ISD::MOVDQ2Q: return "X86ISD::MOVDQ2Q";
20444 case X86ISD::MMX_MOVD2W: return "X86ISD::MMX_MOVD2W";
20445 case X86ISD::MMX_MOVW2D: return "X86ISD::MMX_MOVW2D";
20446 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
20447 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
20448 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
20449 case X86ISD::PINSRB: return "X86ISD::PINSRB";
20450 case X86ISD::PINSRW: return "X86ISD::PINSRW";
20451 case X86ISD::MMX_PINSRW: return "X86ISD::MMX_PINSRW";
20452 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
20453 case X86ISD::ANDNP: return "X86ISD::ANDNP";
20454 case X86ISD::PSIGN: return "X86ISD::PSIGN";
20455 case X86ISD::BLENDI: return "X86ISD::BLENDI";
20456 case X86ISD::SHRUNKBLEND: return "X86ISD::SHRUNKBLEND";
20457 case X86ISD::ADDUS: return "X86ISD::ADDUS";
20458 case X86ISD::SUBUS: return "X86ISD::SUBUS";
20459 case X86ISD::HADD: return "X86ISD::HADD";
20460 case X86ISD::HSUB: return "X86ISD::HSUB";
20461 case X86ISD::FHADD: return "X86ISD::FHADD";
20462 case X86ISD::FHSUB: return "X86ISD::FHSUB";
20463 case X86ISD::ABS: return "X86ISD::ABS";
20464 case X86ISD::CONFLICT: return "X86ISD::CONFLICT";
20465 case X86ISD::FMAX: return "X86ISD::FMAX";
20466 case X86ISD::FMAX_RND: return "X86ISD::FMAX_RND";
20467 case X86ISD::FMIN: return "X86ISD::FMIN";
20468 case X86ISD::FMIN_RND: return "X86ISD::FMIN_RND";
20469 case X86ISD::FMAXC: return "X86ISD::FMAXC";
20470 case X86ISD::FMINC: return "X86ISD::FMINC";
20471 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
20472 case X86ISD::FRCP: return "X86ISD::FRCP";
20473 case X86ISD::EXTRQI: return "X86ISD::EXTRQI";
20474 case X86ISD::INSERTQI: return "X86ISD::INSERTQI";
20475 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
20476 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
20477 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
20478 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
20479 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
20480 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
20481 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
20482 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
20483 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
20484 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
20485 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
20486 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
20487 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
20488 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
20489 case X86ISD::VZEXT: return "X86ISD::VZEXT";
20490 case X86ISD::VSEXT: return "X86ISD::VSEXT";
20491 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
20492 case X86ISD::VTRUNCS: return "X86ISD::VTRUNCS";
20493 case X86ISD::VTRUNCUS: return "X86ISD::VTRUNCUS";
20494 case X86ISD::VINSERT: return "X86ISD::VINSERT";
20495 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
20496 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
20497 case X86ISD::CVTDQ2PD: return "X86ISD::CVTDQ2PD";
20498 case X86ISD::CVTUDQ2PD: return "X86ISD::CVTUDQ2PD";
20499 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
20500 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
20501 case X86ISD::VSHL: return "X86ISD::VSHL";
20502 case X86ISD::VSRL: return "X86ISD::VSRL";
20503 case X86ISD::VSRA: return "X86ISD::VSRA";
20504 case X86ISD::VSHLI: return "X86ISD::VSHLI";
20505 case X86ISD::VSRLI: return "X86ISD::VSRLI";
20506 case X86ISD::VSRAI: return "X86ISD::VSRAI";
20507 case X86ISD::CMPP: return "X86ISD::CMPP";
20508 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
20509 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
20510 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
20511 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
20512 case X86ISD::ADD: return "X86ISD::ADD";
20513 case X86ISD::SUB: return "X86ISD::SUB";
20514 case X86ISD::ADC: return "X86ISD::ADC";
20515 case X86ISD::SBB: return "X86ISD::SBB";
20516 case X86ISD::SMUL: return "X86ISD::SMUL";
20517 case X86ISD::UMUL: return "X86ISD::UMUL";
20518 case X86ISD::SMUL8: return "X86ISD::SMUL8";
20519 case X86ISD::UMUL8: return "X86ISD::UMUL8";
20520 case X86ISD::SDIVREM8_SEXT_HREG: return "X86ISD::SDIVREM8_SEXT_HREG";
20521 case X86ISD::UDIVREM8_ZEXT_HREG: return "X86ISD::UDIVREM8_ZEXT_HREG";
20522 case X86ISD::INC: return "X86ISD::INC";
20523 case X86ISD::DEC: return "X86ISD::DEC";
20524 case X86ISD::OR: return "X86ISD::OR";
20525 case X86ISD::XOR: return "X86ISD::XOR";
20526 case X86ISD::AND: return "X86ISD::AND";
20527 case X86ISD::BEXTR: return "X86ISD::BEXTR";
20528 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
20529 case X86ISD::PTEST: return "X86ISD::PTEST";
20530 case X86ISD::TESTP: return "X86ISD::TESTP";
20531 case X86ISD::TESTM: return "X86ISD::TESTM";
20532 case X86ISD::TESTNM: return "X86ISD::TESTNM";
20533 case X86ISD::KORTEST: return "X86ISD::KORTEST";
20534 case X86ISD::KTEST: return "X86ISD::KTEST";
20535 case X86ISD::PACKSS: return "X86ISD::PACKSS";
20536 case X86ISD::PACKUS: return "X86ISD::PACKUS";
20537 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
20538 case X86ISD::VALIGN: return "X86ISD::VALIGN";
20539 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
20540 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
20541 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
20542 case X86ISD::SHUFP: return "X86ISD::SHUFP";
20543 case X86ISD::SHUF128: return "X86ISD::SHUF128";
20544 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
20545 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
20546 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
20547 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
20548 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
20549 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
20550 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
20551 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
20552 case X86ISD::MOVSD: return "X86ISD::MOVSD";
20553 case X86ISD::MOVSS: return "X86ISD::MOVSS";
20554 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
20555 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
20556 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
20557 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
20558 case X86ISD::SUBV_BROADCAST: return "X86ISD::SUBV_BROADCAST";
20559 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
20560 case X86ISD::VPERMILPV: return "X86ISD::VPERMILPV";
20561 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
20562 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
20563 case X86ISD::VPERMV: return "X86ISD::VPERMV";
20564 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
20565 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
20566 case X86ISD::VPERMI: return "X86ISD::VPERMI";
20567 case X86ISD::VPTERNLOG: return "X86ISD::VPTERNLOG";
20568 case X86ISD::VFIXUPIMM: return "X86ISD::VFIXUPIMM";
20569 case X86ISD::VRANGE: return "X86ISD::VRANGE";
20570 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
20571 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
20572 case X86ISD::PSADBW: return "X86ISD::PSADBW";
20573 case X86ISD::DBPSADBW: return "X86ISD::DBPSADBW";
20574 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
20575 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
20576 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
20577 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
20578 case X86ISD::MFENCE: return "X86ISD::MFENCE";
20579 case X86ISD::SFENCE: return "X86ISD::SFENCE";
20580 case X86ISD::LFENCE: return "X86ISD::LFENCE";
20581 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
20582 case X86ISD::SAHF: return "X86ISD::SAHF";
20583 case X86ISD::RDRAND: return "X86ISD::RDRAND";
20584 case X86ISD::RDSEED: return "X86ISD::RDSEED";
20585 case X86ISD::VPMADDUBSW: return "X86ISD::VPMADDUBSW";
20586 case X86ISD::VPMADDWD: return "X86ISD::VPMADDWD";
20587 case X86ISD::VPROT: return "X86ISD::VPROT";
20588 case X86ISD::VPROTI: return "X86ISD::VPROTI";
20589 case X86ISD::VPSHA: return "X86ISD::VPSHA";
20590 case X86ISD::VPSHL: return "X86ISD::VPSHL";
20591 case X86ISD::VPCOM: return "X86ISD::VPCOM";
20592 case X86ISD::VPCOMU: return "X86ISD::VPCOMU";
20593 case X86ISD::FMADD: return "X86ISD::FMADD";
20594 case X86ISD::FMSUB: return "X86ISD::FMSUB";
20595 case X86ISD::FNMADD: return "X86ISD::FNMADD";
20596 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
20597 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
20598 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
20599 case X86ISD::FMADD_RND: return "X86ISD::FMADD_RND";
20600 case X86ISD::FNMADD_RND: return "X86ISD::FNMADD_RND";
20601 case X86ISD::FMSUB_RND: return "X86ISD::FMSUB_RND";
20602 case X86ISD::FNMSUB_RND: return "X86ISD::FNMSUB_RND";
20603 case X86ISD::FMADDSUB_RND: return "X86ISD::FMADDSUB_RND";
20604 case X86ISD::FMSUBADD_RND: return "X86ISD::FMSUBADD_RND";
20605 case X86ISD::VRNDSCALE: return "X86ISD::VRNDSCALE";
20606 case X86ISD::VREDUCE: return "X86ISD::VREDUCE";
20607 case X86ISD::VGETMANT: return "X86ISD::VGETMANT";
20608 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
20609 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
20610 case X86ISD::XTEST: return "X86ISD::XTEST";
20611 case X86ISD::COMPRESS: return "X86ISD::COMPRESS";
20612 case X86ISD::EXPAND: return "X86ISD::EXPAND";
20613 case X86ISD::SELECT: return "X86ISD::SELECT";
20614 case X86ISD::ADDSUB: return "X86ISD::ADDSUB";
20615 case X86ISD::RCP28: return "X86ISD::RCP28";
20616 case X86ISD::EXP2: return "X86ISD::EXP2";
20617 case X86ISD::RSQRT28: return "X86ISD::RSQRT28";
20618 case X86ISD::FADD_RND: return "X86ISD::FADD_RND";
20619 case X86ISD::FSUB_RND: return "X86ISD::FSUB_RND";
20620 case X86ISD::FMUL_RND: return "X86ISD::FMUL_RND";
20621 case X86ISD::FDIV_RND: return "X86ISD::FDIV_RND";
20622 case X86ISD::FSQRT_RND: return "X86ISD::FSQRT_RND";
20623 case X86ISD::FGETEXP_RND: return "X86ISD::FGETEXP_RND";
20624 case X86ISD::SCALEF: return "X86ISD::SCALEF";
20625 case X86ISD::ADDS: return "X86ISD::ADDS";
20626 case X86ISD::SUBS: return "X86ISD::SUBS";
20627 case X86ISD::AVG: return "X86ISD::AVG";
20628 case X86ISD::MULHRS: return "X86ISD::MULHRS";
20629 case X86ISD::SINT_TO_FP_RND: return "X86ISD::SINT_TO_FP_RND";
20630 case X86ISD::UINT_TO_FP_RND: return "X86ISD::UINT_TO_FP_RND";
20631 case X86ISD::FP_TO_SINT_RND: return "X86ISD::FP_TO_SINT_RND";
20632 case X86ISD::FP_TO_UINT_RND: return "X86ISD::FP_TO_UINT_RND";
20633 case X86ISD::VFPCLASS: return "X86ISD::VFPCLASS";
20634 case X86ISD::VFPCLASSS: return "X86ISD::VFPCLASSS";
20639 // isLegalAddressingMode - Return true if the addressing mode represented
20640 // by AM is legal for this target, for a load/store of the specified type.
20641 bool X86TargetLowering::isLegalAddressingMode(const DataLayout &DL,
20642 const AddrMode &AM, Type *Ty,
20643 unsigned AS) const {
20644 // X86 supports extremely general addressing modes.
20645 CodeModel::Model M = getTargetMachine().getCodeModel();
20646 Reloc::Model R = getTargetMachine().getRelocationModel();
20648 // X86 allows a sign-extended 32-bit immediate field as a displacement.
20649 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
20654 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
20656 // If a reference to this global requires an extra load, we can't fold it.
20657 if (isGlobalStubReference(GVFlags))
20660 // If BaseGV requires a register for the PIC base, we cannot also have a
20661 // BaseReg specified.
20662 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
20665 // If lower 4G is not available, then we must use rip-relative addressing.
20666 if ((M != CodeModel::Small || R != Reloc::Static) &&
20667 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
20671 switch (AM.Scale) {
20677 // These scales always work.
20682 // These scales are formed with basereg+scalereg. Only accept if there is
20687 default: // Other stuff never works.
20694 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
20695 unsigned Bits = Ty->getScalarSizeInBits();
20697 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
20698 // particularly cheaper than those without.
20702 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
20703 // variable shifts just as cheap as scalar ones.
20704 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
20707 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
20708 // fully general vector.
20712 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
20713 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
20715 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
20716 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
20717 return NumBits1 > NumBits2;
20720 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
20721 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
20724 if (!isTypeLegal(EVT::getEVT(Ty1)))
20727 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
20729 // Assuming the caller doesn't have a zeroext or signext return parameter,
20730 // truncation all the way down to i1 is valid.
20734 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
20735 return isInt<32>(Imm);
20738 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
20739 // Can also use sub to handle negated immediates.
20740 return isInt<32>(Imm);
20743 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
20744 if (!VT1.isInteger() || !VT2.isInteger())
20746 unsigned NumBits1 = VT1.getSizeInBits();
20747 unsigned NumBits2 = VT2.getSizeInBits();
20748 return NumBits1 > NumBits2;
20751 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
20752 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
20753 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
20756 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
20757 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
20758 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
20761 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
20762 EVT VT1 = Val.getValueType();
20763 if (isZExtFree(VT1, VT2))
20766 if (Val.getOpcode() != ISD::LOAD)
20769 if (!VT1.isSimple() || !VT1.isInteger() ||
20770 !VT2.isSimple() || !VT2.isInteger())
20773 switch (VT1.getSimpleVT().SimpleTy) {
20778 // X86 has 8, 16, and 32-bit zero-extending loads.
20785 bool X86TargetLowering::isVectorLoadExtDesirable(SDValue) const { return true; }
20788 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
20789 if (!Subtarget->hasAnyFMA())
20792 VT = VT.getScalarType();
20794 if (!VT.isSimple())
20797 switch (VT.getSimpleVT().SimpleTy) {
20808 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
20809 // i16 instructions are longer (0x66 prefix) and potentially slower.
20810 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
20813 /// isShuffleMaskLegal - Targets can use this to indicate that they only
20814 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
20815 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
20816 /// are assumed to be legal.
20818 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
20820 if (!VT.isSimple())
20823 // Not for i1 vectors
20824 if (VT.getSimpleVT().getScalarType() == MVT::i1)
20827 // Very little shuffling can be done for 64-bit vectors right now.
20828 if (VT.getSimpleVT().getSizeInBits() == 64)
20831 // We only care that the types being shuffled are legal. The lowering can
20832 // handle any possible shuffle mask that results.
20833 return isTypeLegal(VT.getSimpleVT());
20837 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
20839 // Just delegate to the generic legality, clear masks aren't special.
20840 return isShuffleMaskLegal(Mask, VT);
20843 //===----------------------------------------------------------------------===//
20844 // X86 Scheduler Hooks
20845 //===----------------------------------------------------------------------===//
20847 /// Utility function to emit xbegin specifying the start of an RTM region.
20848 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
20849 const TargetInstrInfo *TII) {
20850 DebugLoc DL = MI->getDebugLoc();
20852 const BasicBlock *BB = MBB->getBasicBlock();
20853 MachineFunction::iterator I = ++MBB->getIterator();
20855 // For the v = xbegin(), we generate
20866 MachineBasicBlock *thisMBB = MBB;
20867 MachineFunction *MF = MBB->getParent();
20868 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
20869 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
20870 MF->insert(I, mainMBB);
20871 MF->insert(I, sinkMBB);
20873 // Transfer the remainder of BB and its successor edges to sinkMBB.
20874 sinkMBB->splice(sinkMBB->begin(), MBB,
20875 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20876 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
20880 // # fallthrough to mainMBB
20881 // # abortion to sinkMBB
20882 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
20883 thisMBB->addSuccessor(mainMBB);
20884 thisMBB->addSuccessor(sinkMBB);
20888 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
20889 mainMBB->addSuccessor(sinkMBB);
20892 // EAX is live into the sinkMBB
20893 sinkMBB->addLiveIn(X86::EAX);
20894 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20895 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20898 MI->eraseFromParent();
20902 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
20903 // or XMM0_V32I8 in AVX all of this code can be replaced with that
20904 // in the .td file.
20905 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
20906 const TargetInstrInfo *TII) {
20908 switch (MI->getOpcode()) {
20909 default: llvm_unreachable("illegal opcode!");
20910 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
20911 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
20912 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
20913 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
20914 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
20915 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
20916 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
20917 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
20920 DebugLoc dl = MI->getDebugLoc();
20921 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
20923 unsigned NumArgs = MI->getNumOperands();
20924 for (unsigned i = 1; i < NumArgs; ++i) {
20925 MachineOperand &Op = MI->getOperand(i);
20926 if (!(Op.isReg() && Op.isImplicit()))
20927 MIB.addOperand(Op);
20929 if (MI->hasOneMemOperand())
20930 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
20932 BuildMI(*BB, MI, dl,
20933 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20934 .addReg(X86::XMM0);
20936 MI->eraseFromParent();
20940 // FIXME: Custom handling because TableGen doesn't support multiple implicit
20941 // defs in an instruction pattern
20942 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
20943 const TargetInstrInfo *TII) {
20945 switch (MI->getOpcode()) {
20946 default: llvm_unreachable("illegal opcode!");
20947 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
20948 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
20949 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
20950 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
20951 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
20952 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
20953 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
20954 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
20957 DebugLoc dl = MI->getDebugLoc();
20958 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
20960 unsigned NumArgs = MI->getNumOperands(); // remove the results
20961 for (unsigned i = 1; i < NumArgs; ++i) {
20962 MachineOperand &Op = MI->getOperand(i);
20963 if (!(Op.isReg() && Op.isImplicit()))
20964 MIB.addOperand(Op);
20966 if (MI->hasOneMemOperand())
20967 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
20969 BuildMI(*BB, MI, dl,
20970 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20973 MI->eraseFromParent();
20977 static MachineBasicBlock *EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
20978 const X86Subtarget *Subtarget) {
20979 DebugLoc dl = MI->getDebugLoc();
20980 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20981 // Address into RAX/EAX, other two args into ECX, EDX.
20982 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
20983 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
20984 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
20985 for (int i = 0; i < X86::AddrNumOperands; ++i)
20986 MIB.addOperand(MI->getOperand(i));
20988 unsigned ValOps = X86::AddrNumOperands;
20989 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
20990 .addReg(MI->getOperand(ValOps).getReg());
20991 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
20992 .addReg(MI->getOperand(ValOps+1).getReg());
20994 // The instruction doesn't actually take any operands though.
20995 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
20997 MI->eraseFromParent(); // The pseudo is gone now.
21001 MachineBasicBlock *
21002 X86TargetLowering::EmitVAARG64WithCustomInserter(MachineInstr *MI,
21003 MachineBasicBlock *MBB) const {
21004 // Emit va_arg instruction on X86-64.
21006 // Operands to this pseudo-instruction:
21007 // 0 ) Output : destination address (reg)
21008 // 1-5) Input : va_list address (addr, i64mem)
21009 // 6 ) ArgSize : Size (in bytes) of vararg type
21010 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
21011 // 8 ) Align : Alignment of type
21012 // 9 ) EFLAGS (implicit-def)
21014 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
21015 static_assert(X86::AddrNumOperands == 5,
21016 "VAARG_64 assumes 5 address operands");
21018 unsigned DestReg = MI->getOperand(0).getReg();
21019 MachineOperand &Base = MI->getOperand(1);
21020 MachineOperand &Scale = MI->getOperand(2);
21021 MachineOperand &Index = MI->getOperand(3);
21022 MachineOperand &Disp = MI->getOperand(4);
21023 MachineOperand &Segment = MI->getOperand(5);
21024 unsigned ArgSize = MI->getOperand(6).getImm();
21025 unsigned ArgMode = MI->getOperand(7).getImm();
21026 unsigned Align = MI->getOperand(8).getImm();
21028 // Memory Reference
21029 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
21030 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
21031 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
21033 // Machine Information
21034 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21035 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
21036 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
21037 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
21038 DebugLoc DL = MI->getDebugLoc();
21040 // struct va_list {
21043 // i64 overflow_area (address)
21044 // i64 reg_save_area (address)
21046 // sizeof(va_list) = 24
21047 // alignment(va_list) = 8
21049 unsigned TotalNumIntRegs = 6;
21050 unsigned TotalNumXMMRegs = 8;
21051 bool UseGPOffset = (ArgMode == 1);
21052 bool UseFPOffset = (ArgMode == 2);
21053 unsigned MaxOffset = TotalNumIntRegs * 8 +
21054 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
21056 /* Align ArgSize to a multiple of 8 */
21057 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
21058 bool NeedsAlign = (Align > 8);
21060 MachineBasicBlock *thisMBB = MBB;
21061 MachineBasicBlock *overflowMBB;
21062 MachineBasicBlock *offsetMBB;
21063 MachineBasicBlock *endMBB;
21065 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
21066 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
21067 unsigned OffsetReg = 0;
21069 if (!UseGPOffset && !UseFPOffset) {
21070 // If we only pull from the overflow region, we don't create a branch.
21071 // We don't need to alter control flow.
21072 OffsetDestReg = 0; // unused
21073 OverflowDestReg = DestReg;
21075 offsetMBB = nullptr;
21076 overflowMBB = thisMBB;
21079 // First emit code to check if gp_offset (or fp_offset) is below the bound.
21080 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
21081 // If not, pull from overflow_area. (branch to overflowMBB)
21086 // offsetMBB overflowMBB
21091 // Registers for the PHI in endMBB
21092 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
21093 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
21095 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
21096 MachineFunction *MF = MBB->getParent();
21097 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
21098 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
21099 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
21101 MachineFunction::iterator MBBIter = ++MBB->getIterator();
21103 // Insert the new basic blocks
21104 MF->insert(MBBIter, offsetMBB);
21105 MF->insert(MBBIter, overflowMBB);
21106 MF->insert(MBBIter, endMBB);
21108 // Transfer the remainder of MBB and its successor edges to endMBB.
21109 endMBB->splice(endMBB->begin(), thisMBB,
21110 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
21111 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
21113 // Make offsetMBB and overflowMBB successors of thisMBB
21114 thisMBB->addSuccessor(offsetMBB);
21115 thisMBB->addSuccessor(overflowMBB);
21117 // endMBB is a successor of both offsetMBB and overflowMBB
21118 offsetMBB->addSuccessor(endMBB);
21119 overflowMBB->addSuccessor(endMBB);
21121 // Load the offset value into a register
21122 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
21123 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
21127 .addDisp(Disp, UseFPOffset ? 4 : 0)
21128 .addOperand(Segment)
21129 .setMemRefs(MMOBegin, MMOEnd);
21131 // Check if there is enough room left to pull this argument.
21132 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
21134 .addImm(MaxOffset + 8 - ArgSizeA8);
21136 // Branch to "overflowMBB" if offset >= max
21137 // Fall through to "offsetMBB" otherwise
21138 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
21139 .addMBB(overflowMBB);
21142 // In offsetMBB, emit code to use the reg_save_area.
21144 assert(OffsetReg != 0);
21146 // Read the reg_save_area address.
21147 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
21148 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
21153 .addOperand(Segment)
21154 .setMemRefs(MMOBegin, MMOEnd);
21156 // Zero-extend the offset
21157 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
21158 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
21161 .addImm(X86::sub_32bit);
21163 // Add the offset to the reg_save_area to get the final address.
21164 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
21165 .addReg(OffsetReg64)
21166 .addReg(RegSaveReg);
21168 // Compute the offset for the next argument
21169 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
21170 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
21172 .addImm(UseFPOffset ? 16 : 8);
21174 // Store it back into the va_list.
21175 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
21179 .addDisp(Disp, UseFPOffset ? 4 : 0)
21180 .addOperand(Segment)
21181 .addReg(NextOffsetReg)
21182 .setMemRefs(MMOBegin, MMOEnd);
21185 BuildMI(offsetMBB, DL, TII->get(X86::JMP_1))
21190 // Emit code to use overflow area
21193 // Load the overflow_area address into a register.
21194 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
21195 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
21200 .addOperand(Segment)
21201 .setMemRefs(MMOBegin, MMOEnd);
21203 // If we need to align it, do so. Otherwise, just copy the address
21204 // to OverflowDestReg.
21206 // Align the overflow address
21207 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
21208 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
21210 // aligned_addr = (addr + (align-1)) & ~(align-1)
21211 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
21212 .addReg(OverflowAddrReg)
21215 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
21217 .addImm(~(uint64_t)(Align-1));
21219 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
21220 .addReg(OverflowAddrReg);
21223 // Compute the next overflow address after this argument.
21224 // (the overflow address should be kept 8-byte aligned)
21225 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
21226 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
21227 .addReg(OverflowDestReg)
21228 .addImm(ArgSizeA8);
21230 // Store the new overflow address.
21231 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
21236 .addOperand(Segment)
21237 .addReg(NextAddrReg)
21238 .setMemRefs(MMOBegin, MMOEnd);
21240 // If we branched, emit the PHI to the front of endMBB.
21242 BuildMI(*endMBB, endMBB->begin(), DL,
21243 TII->get(X86::PHI), DestReg)
21244 .addReg(OffsetDestReg).addMBB(offsetMBB)
21245 .addReg(OverflowDestReg).addMBB(overflowMBB);
21248 // Erase the pseudo instruction
21249 MI->eraseFromParent();
21254 MachineBasicBlock *
21255 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
21257 MachineBasicBlock *MBB) const {
21258 // Emit code to save XMM registers to the stack. The ABI says that the
21259 // number of registers to save is given in %al, so it's theoretically
21260 // possible to do an indirect jump trick to avoid saving all of them,
21261 // however this code takes a simpler approach and just executes all
21262 // of the stores if %al is non-zero. It's less code, and it's probably
21263 // easier on the hardware branch predictor, and stores aren't all that
21264 // expensive anyway.
21266 // Create the new basic blocks. One block contains all the XMM stores,
21267 // and one block is the final destination regardless of whether any
21268 // stores were performed.
21269 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
21270 MachineFunction *F = MBB->getParent();
21271 MachineFunction::iterator MBBIter = ++MBB->getIterator();
21272 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
21273 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
21274 F->insert(MBBIter, XMMSaveMBB);
21275 F->insert(MBBIter, EndMBB);
21277 // Transfer the remainder of MBB and its successor edges to EndMBB.
21278 EndMBB->splice(EndMBB->begin(), MBB,
21279 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
21280 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
21282 // The original block will now fall through to the XMM save block.
21283 MBB->addSuccessor(XMMSaveMBB);
21284 // The XMMSaveMBB will fall through to the end block.
21285 XMMSaveMBB->addSuccessor(EndMBB);
21287 // Now add the instructions.
21288 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21289 DebugLoc DL = MI->getDebugLoc();
21291 unsigned CountReg = MI->getOperand(0).getReg();
21292 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
21293 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
21295 if (!Subtarget->isCallingConvWin64(F->getFunction()->getCallingConv())) {
21296 // If %al is 0, branch around the XMM save block.
21297 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
21298 BuildMI(MBB, DL, TII->get(X86::JE_1)).addMBB(EndMBB);
21299 MBB->addSuccessor(EndMBB);
21302 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
21303 // that was just emitted, but clearly shouldn't be "saved".
21304 assert((MI->getNumOperands() <= 3 ||
21305 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
21306 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
21307 && "Expected last argument to be EFLAGS");
21308 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
21309 // In the XMM save block, save all the XMM argument registers.
21310 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
21311 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
21312 MachineMemOperand *MMO = F->getMachineMemOperand(
21313 MachinePointerInfo::getFixedStack(*F, RegSaveFrameIndex, Offset),
21314 MachineMemOperand::MOStore,
21315 /*Size=*/16, /*Align=*/16);
21316 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
21317 .addFrameIndex(RegSaveFrameIndex)
21318 .addImm(/*Scale=*/1)
21319 .addReg(/*IndexReg=*/0)
21320 .addImm(/*Disp=*/Offset)
21321 .addReg(/*Segment=*/0)
21322 .addReg(MI->getOperand(i).getReg())
21323 .addMemOperand(MMO);
21326 MI->eraseFromParent(); // The pseudo instruction is gone now.
21331 // The EFLAGS operand of SelectItr might be missing a kill marker
21332 // because there were multiple uses of EFLAGS, and ISel didn't know
21333 // which to mark. Figure out whether SelectItr should have had a
21334 // kill marker, and set it if it should. Returns the correct kill
21336 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
21337 MachineBasicBlock* BB,
21338 const TargetRegisterInfo* TRI) {
21339 // Scan forward through BB for a use/def of EFLAGS.
21340 MachineBasicBlock::iterator miI(std::next(SelectItr));
21341 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
21342 const MachineInstr& mi = *miI;
21343 if (mi.readsRegister(X86::EFLAGS))
21345 if (mi.definesRegister(X86::EFLAGS))
21346 break; // Should have kill-flag - update below.
21349 // If we hit the end of the block, check whether EFLAGS is live into a
21351 if (miI == BB->end()) {
21352 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
21353 sEnd = BB->succ_end();
21354 sItr != sEnd; ++sItr) {
21355 MachineBasicBlock* succ = *sItr;
21356 if (succ->isLiveIn(X86::EFLAGS))
21361 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
21362 // out. SelectMI should have a kill flag on EFLAGS.
21363 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
21367 // Return true if it is OK for this CMOV pseudo-opcode to be cascaded
21368 // together with other CMOV pseudo-opcodes into a single basic-block with
21369 // conditional jump around it.
21370 static bool isCMOVPseudo(MachineInstr *MI) {
21371 switch (MI->getOpcode()) {
21372 case X86::CMOV_FR32:
21373 case X86::CMOV_FR64:
21374 case X86::CMOV_GR8:
21375 case X86::CMOV_GR16:
21376 case X86::CMOV_GR32:
21377 case X86::CMOV_RFP32:
21378 case X86::CMOV_RFP64:
21379 case X86::CMOV_RFP80:
21380 case X86::CMOV_V2F64:
21381 case X86::CMOV_V2I64:
21382 case X86::CMOV_V4F32:
21383 case X86::CMOV_V4F64:
21384 case X86::CMOV_V4I64:
21385 case X86::CMOV_V16F32:
21386 case X86::CMOV_V8F32:
21387 case X86::CMOV_V8F64:
21388 case X86::CMOV_V8I64:
21389 case X86::CMOV_V8I1:
21390 case X86::CMOV_V16I1:
21391 case X86::CMOV_V32I1:
21392 case X86::CMOV_V64I1:
21400 MachineBasicBlock *
21401 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
21402 MachineBasicBlock *BB) const {
21403 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21404 DebugLoc DL = MI->getDebugLoc();
21406 // To "insert" a SELECT_CC instruction, we actually have to insert the
21407 // diamond control-flow pattern. The incoming instruction knows the
21408 // destination vreg to set, the condition code register to branch on, the
21409 // true/false values to select between, and a branch opcode to use.
21410 const BasicBlock *LLVM_BB = BB->getBasicBlock();
21411 MachineFunction::iterator It = ++BB->getIterator();
21416 // cmpTY ccX, r1, r2
21418 // fallthrough --> copy0MBB
21419 MachineBasicBlock *thisMBB = BB;
21420 MachineFunction *F = BB->getParent();
21422 // This code lowers all pseudo-CMOV instructions. Generally it lowers these
21423 // as described above, by inserting a BB, and then making a PHI at the join
21424 // point to select the true and false operands of the CMOV in the PHI.
21426 // The code also handles two different cases of multiple CMOV opcodes
21430 // In this case, there are multiple CMOVs in a row, all which are based on
21431 // the same condition setting (or the exact opposite condition setting).
21432 // In this case we can lower all the CMOVs using a single inserted BB, and
21433 // then make a number of PHIs at the join point to model the CMOVs. The only
21434 // trickiness here, is that in a case like:
21436 // t2 = CMOV cond1 t1, f1
21437 // t3 = CMOV cond1 t2, f2
21439 // when rewriting this into PHIs, we have to perform some renaming on the
21440 // temps since you cannot have a PHI operand refer to a PHI result earlier
21441 // in the same block. The "simple" but wrong lowering would be:
21443 // t2 = PHI t1(BB1), f1(BB2)
21444 // t3 = PHI t2(BB1), f2(BB2)
21446 // but clearly t2 is not defined in BB1, so that is incorrect. The proper
21447 // renaming is to note that on the path through BB1, t2 is really just a
21448 // copy of t1, and do that renaming, properly generating:
21450 // t2 = PHI t1(BB1), f1(BB2)
21451 // t3 = PHI t1(BB1), f2(BB2)
21453 // Case 2, we lower cascaded CMOVs such as
21455 // (CMOV (CMOV F, T, cc1), T, cc2)
21457 // to two successives branches. For that, we look for another CMOV as the
21458 // following instruction.
21460 // Without this, we would add a PHI between the two jumps, which ends up
21461 // creating a few copies all around. For instance, for
21463 // (sitofp (zext (fcmp une)))
21465 // we would generate:
21467 // ucomiss %xmm1, %xmm0
21468 // movss <1.0f>, %xmm0
21469 // movaps %xmm0, %xmm1
21471 // xorps %xmm1, %xmm1
21474 // movaps %xmm1, %xmm0
21478 // because this custom-inserter would have generated:
21490 // A: X = ...; Y = ...
21492 // C: Z = PHI [X, A], [Y, B]
21494 // E: PHI [X, C], [Z, D]
21496 // If we lower both CMOVs in a single step, we can instead generate:
21508 // A: X = ...; Y = ...
21510 // E: PHI [X, A], [X, C], [Y, D]
21512 // Which, in our sitofp/fcmp example, gives us something like:
21514 // ucomiss %xmm1, %xmm0
21515 // movss <1.0f>, %xmm0
21518 // xorps %xmm0, %xmm0
21522 MachineInstr *CascadedCMOV = nullptr;
21523 MachineInstr *LastCMOV = MI;
21524 X86::CondCode CC = X86::CondCode(MI->getOperand(3).getImm());
21525 X86::CondCode OppCC = X86::GetOppositeBranchCondition(CC);
21526 MachineBasicBlock::iterator NextMIIt =
21527 std::next(MachineBasicBlock::iterator(MI));
21529 // Check for case 1, where there are multiple CMOVs with the same condition
21530 // first. Of the two cases of multiple CMOV lowerings, case 1 reduces the
21531 // number of jumps the most.
21533 if (isCMOVPseudo(MI)) {
21534 // See if we have a string of CMOVS with the same condition.
21535 while (NextMIIt != BB->end() &&
21536 isCMOVPseudo(NextMIIt) &&
21537 (NextMIIt->getOperand(3).getImm() == CC ||
21538 NextMIIt->getOperand(3).getImm() == OppCC)) {
21539 LastCMOV = &*NextMIIt;
21544 // This checks for case 2, but only do this if we didn't already find
21545 // case 1, as indicated by LastCMOV == MI.
21546 if (LastCMOV == MI &&
21547 NextMIIt != BB->end() && NextMIIt->getOpcode() == MI->getOpcode() &&
21548 NextMIIt->getOperand(2).getReg() == MI->getOperand(2).getReg() &&
21549 NextMIIt->getOperand(1).getReg() == MI->getOperand(0).getReg()) {
21550 CascadedCMOV = &*NextMIIt;
21553 MachineBasicBlock *jcc1MBB = nullptr;
21555 // If we have a cascaded CMOV, we lower it to two successive branches to
21556 // the same block. EFLAGS is used by both, so mark it as live in the second.
21557 if (CascadedCMOV) {
21558 jcc1MBB = F->CreateMachineBasicBlock(LLVM_BB);
21559 F->insert(It, jcc1MBB);
21560 jcc1MBB->addLiveIn(X86::EFLAGS);
21563 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
21564 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
21565 F->insert(It, copy0MBB);
21566 F->insert(It, sinkMBB);
21568 // If the EFLAGS register isn't dead in the terminator, then claim that it's
21569 // live into the sink and copy blocks.
21570 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
21572 MachineInstr *LastEFLAGSUser = CascadedCMOV ? CascadedCMOV : LastCMOV;
21573 if (!LastEFLAGSUser->killsRegister(X86::EFLAGS) &&
21574 !checkAndUpdateEFLAGSKill(LastEFLAGSUser, BB, TRI)) {
21575 copy0MBB->addLiveIn(X86::EFLAGS);
21576 sinkMBB->addLiveIn(X86::EFLAGS);
21579 // Transfer the remainder of BB and its successor edges to sinkMBB.
21580 sinkMBB->splice(sinkMBB->begin(), BB,
21581 std::next(MachineBasicBlock::iterator(LastCMOV)), BB->end());
21582 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
21584 // Add the true and fallthrough blocks as its successors.
21585 if (CascadedCMOV) {
21586 // The fallthrough block may be jcc1MBB, if we have a cascaded CMOV.
21587 BB->addSuccessor(jcc1MBB);
21589 // In that case, jcc1MBB will itself fallthrough the copy0MBB, and
21590 // jump to the sinkMBB.
21591 jcc1MBB->addSuccessor(copy0MBB);
21592 jcc1MBB->addSuccessor(sinkMBB);
21594 BB->addSuccessor(copy0MBB);
21597 // The true block target of the first (or only) branch is always sinkMBB.
21598 BB->addSuccessor(sinkMBB);
21600 // Create the conditional branch instruction.
21601 unsigned Opc = X86::GetCondBranchFromCond(CC);
21602 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
21604 if (CascadedCMOV) {
21605 unsigned Opc2 = X86::GetCondBranchFromCond(
21606 (X86::CondCode)CascadedCMOV->getOperand(3).getImm());
21607 BuildMI(jcc1MBB, DL, TII->get(Opc2)).addMBB(sinkMBB);
21611 // %FalseValue = ...
21612 // # fallthrough to sinkMBB
21613 copy0MBB->addSuccessor(sinkMBB);
21616 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
21618 MachineBasicBlock::iterator MIItBegin = MachineBasicBlock::iterator(MI);
21619 MachineBasicBlock::iterator MIItEnd =
21620 std::next(MachineBasicBlock::iterator(LastCMOV));
21621 MachineBasicBlock::iterator SinkInsertionPoint = sinkMBB->begin();
21622 DenseMap<unsigned, std::pair<unsigned, unsigned>> RegRewriteTable;
21623 MachineInstrBuilder MIB;
21625 // As we are creating the PHIs, we have to be careful if there is more than
21626 // one. Later CMOVs may reference the results of earlier CMOVs, but later
21627 // PHIs have to reference the individual true/false inputs from earlier PHIs.
21628 // That also means that PHI construction must work forward from earlier to
21629 // later, and that the code must maintain a mapping from earlier PHI's
21630 // destination registers, and the registers that went into the PHI.
21632 for (MachineBasicBlock::iterator MIIt = MIItBegin; MIIt != MIItEnd; ++MIIt) {
21633 unsigned DestReg = MIIt->getOperand(0).getReg();
21634 unsigned Op1Reg = MIIt->getOperand(1).getReg();
21635 unsigned Op2Reg = MIIt->getOperand(2).getReg();
21637 // If this CMOV we are generating is the opposite condition from
21638 // the jump we generated, then we have to swap the operands for the
21639 // PHI that is going to be generated.
21640 if (MIIt->getOperand(3).getImm() == OppCC)
21641 std::swap(Op1Reg, Op2Reg);
21643 if (RegRewriteTable.find(Op1Reg) != RegRewriteTable.end())
21644 Op1Reg = RegRewriteTable[Op1Reg].first;
21646 if (RegRewriteTable.find(Op2Reg) != RegRewriteTable.end())
21647 Op2Reg = RegRewriteTable[Op2Reg].second;
21649 MIB = BuildMI(*sinkMBB, SinkInsertionPoint, DL,
21650 TII->get(X86::PHI), DestReg)
21651 .addReg(Op1Reg).addMBB(copy0MBB)
21652 .addReg(Op2Reg).addMBB(thisMBB);
21654 // Add this PHI to the rewrite table.
21655 RegRewriteTable[DestReg] = std::make_pair(Op1Reg, Op2Reg);
21658 // If we have a cascaded CMOV, the second Jcc provides the same incoming
21659 // value as the first Jcc (the True operand of the SELECT_CC/CMOV nodes).
21660 if (CascadedCMOV) {
21661 MIB.addReg(MI->getOperand(2).getReg()).addMBB(jcc1MBB);
21662 // Copy the PHI result to the register defined by the second CMOV.
21663 BuildMI(*sinkMBB, std::next(MachineBasicBlock::iterator(MIB.getInstr())),
21664 DL, TII->get(TargetOpcode::COPY),
21665 CascadedCMOV->getOperand(0).getReg())
21666 .addReg(MI->getOperand(0).getReg());
21667 CascadedCMOV->eraseFromParent();
21670 // Now remove the CMOV(s).
21671 for (MachineBasicBlock::iterator MIIt = MIItBegin; MIIt != MIItEnd; )
21672 (MIIt++)->eraseFromParent();
21677 MachineBasicBlock *
21678 X86TargetLowering::EmitLoweredAtomicFP(MachineInstr *MI,
21679 MachineBasicBlock *BB) const {
21680 // Combine the following atomic floating-point modification pattern:
21681 // a.store(reg OP a.load(acquire), release)
21682 // Transform them into:
21683 // OPss (%gpr), %xmm
21684 // movss %xmm, (%gpr)
21685 // Or sd equivalent for 64-bit operations.
21687 switch (MI->getOpcode()) {
21688 default: llvm_unreachable("unexpected instr type for EmitLoweredAtomicFP");
21689 case X86::RELEASE_FADD32mr: MOp = X86::MOVSSmr; FOp = X86::ADDSSrm; break;
21690 case X86::RELEASE_FADD64mr: MOp = X86::MOVSDmr; FOp = X86::ADDSDrm; break;
21692 const X86InstrInfo *TII = Subtarget->getInstrInfo();
21693 DebugLoc DL = MI->getDebugLoc();
21694 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
21695 MachineOperand MSrc = MI->getOperand(0);
21696 unsigned VSrc = MI->getOperand(5).getReg();
21697 const MachineOperand &Disp = MI->getOperand(3);
21698 MachineOperand ZeroDisp = MachineOperand::CreateImm(0);
21699 bool hasDisp = Disp.isGlobal() || Disp.isImm();
21700 if (hasDisp && MSrc.isReg())
21701 MSrc.setIsKill(false);
21702 MachineInstrBuilder MIM = BuildMI(*BB, MI, DL, TII->get(MOp))
21703 .addOperand(/*Base=*/MSrc)
21704 .addImm(/*Scale=*/1)
21705 .addReg(/*Index=*/0)
21706 .addDisp(hasDisp ? Disp : ZeroDisp, /*off=*/0)
21708 MachineInstr *MIO = BuildMI(*BB, (MachineInstr *)MIM, DL, TII->get(FOp),
21709 MRI.createVirtualRegister(MRI.getRegClass(VSrc)))
21711 .addOperand(/*Base=*/MSrc)
21712 .addImm(/*Scale=*/1)
21713 .addReg(/*Index=*/0)
21714 .addDisp(hasDisp ? Disp : ZeroDisp, /*off=*/0)
21715 .addReg(/*Segment=*/0);
21716 MIM.addReg(MIO->getOperand(0).getReg(), RegState::Kill);
21717 MI->eraseFromParent(); // The pseudo instruction is gone now.
21721 MachineBasicBlock *
21722 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
21723 MachineBasicBlock *BB) const {
21724 MachineFunction *MF = BB->getParent();
21725 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21726 DebugLoc DL = MI->getDebugLoc();
21727 const BasicBlock *LLVM_BB = BB->getBasicBlock();
21729 assert(MF->shouldSplitStack());
21731 const bool Is64Bit = Subtarget->is64Bit();
21732 const bool IsLP64 = Subtarget->isTarget64BitLP64();
21734 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
21735 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
21738 // ... [Till the alloca]
21739 // If stacklet is not large enough, jump to mallocMBB
21742 // Allocate by subtracting from RSP
21743 // Jump to continueMBB
21746 // Allocate by call to runtime
21750 // [rest of original BB]
21753 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
21754 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
21755 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
21757 MachineRegisterInfo &MRI = MF->getRegInfo();
21758 const TargetRegisterClass *AddrRegClass =
21759 getRegClassFor(getPointerTy(MF->getDataLayout()));
21761 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
21762 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
21763 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
21764 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
21765 sizeVReg = MI->getOperand(1).getReg(),
21766 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
21768 MachineFunction::iterator MBBIter = ++BB->getIterator();
21770 MF->insert(MBBIter, bumpMBB);
21771 MF->insert(MBBIter, mallocMBB);
21772 MF->insert(MBBIter, continueMBB);
21774 continueMBB->splice(continueMBB->begin(), BB,
21775 std::next(MachineBasicBlock::iterator(MI)), BB->end());
21776 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
21778 // Add code to the main basic block to check if the stack limit has been hit,
21779 // and if so, jump to mallocMBB otherwise to bumpMBB.
21780 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
21781 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
21782 .addReg(tmpSPVReg).addReg(sizeVReg);
21783 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
21784 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
21785 .addReg(SPLimitVReg);
21786 BuildMI(BB, DL, TII->get(X86::JG_1)).addMBB(mallocMBB);
21788 // bumpMBB simply decreases the stack pointer, since we know the current
21789 // stacklet has enough space.
21790 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
21791 .addReg(SPLimitVReg);
21792 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
21793 .addReg(SPLimitVReg);
21794 BuildMI(bumpMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
21796 // Calls into a routine in libgcc to allocate more space from the heap.
21797 const uint32_t *RegMask =
21798 Subtarget->getRegisterInfo()->getCallPreservedMask(*MF, CallingConv::C);
21800 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
21802 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
21803 .addExternalSymbol("__morestack_allocate_stack_space")
21804 .addRegMask(RegMask)
21805 .addReg(X86::RDI, RegState::Implicit)
21806 .addReg(X86::RAX, RegState::ImplicitDefine);
21807 } else if (Is64Bit) {
21808 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
21810 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
21811 .addExternalSymbol("__morestack_allocate_stack_space")
21812 .addRegMask(RegMask)
21813 .addReg(X86::EDI, RegState::Implicit)
21814 .addReg(X86::EAX, RegState::ImplicitDefine);
21816 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
21818 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
21819 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
21820 .addExternalSymbol("__morestack_allocate_stack_space")
21821 .addRegMask(RegMask)
21822 .addReg(X86::EAX, RegState::ImplicitDefine);
21826 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
21829 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
21830 .addReg(IsLP64 ? X86::RAX : X86::EAX);
21831 BuildMI(mallocMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
21833 // Set up the CFG correctly.
21834 BB->addSuccessor(bumpMBB);
21835 BB->addSuccessor(mallocMBB);
21836 mallocMBB->addSuccessor(continueMBB);
21837 bumpMBB->addSuccessor(continueMBB);
21839 // Take care of the PHI nodes.
21840 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
21841 MI->getOperand(0).getReg())
21842 .addReg(mallocPtrVReg).addMBB(mallocMBB)
21843 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
21845 // Delete the original pseudo instruction.
21846 MI->eraseFromParent();
21849 return continueMBB;
21852 MachineBasicBlock *
21853 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
21854 MachineBasicBlock *BB) const {
21855 assert(!Subtarget->isTargetMachO());
21856 DebugLoc DL = MI->getDebugLoc();
21857 MachineInstr *ResumeMI = Subtarget->getFrameLowering()->emitStackProbe(
21858 *BB->getParent(), *BB, MI, DL, false);
21859 MachineBasicBlock *ResumeBB = ResumeMI->getParent();
21860 MI->eraseFromParent(); // The pseudo instruction is gone now.
21864 MachineBasicBlock *
21865 X86TargetLowering::EmitLoweredCatchRet(MachineInstr *MI,
21866 MachineBasicBlock *BB) const {
21867 MachineFunction *MF = BB->getParent();
21868 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
21869 MachineBasicBlock *TargetMBB = MI->getOperand(0).getMBB();
21870 DebugLoc DL = MI->getDebugLoc();
21872 assert(!isAsynchronousEHPersonality(
21873 classifyEHPersonality(MF->getFunction()->getPersonalityFn())) &&
21874 "SEH does not use catchret!");
21876 // Only 32-bit EH needs to worry about manually restoring stack pointers.
21877 if (!Subtarget->is32Bit())
21880 // C++ EH creates a new target block to hold the restore code, and wires up
21881 // the new block to the return destination with a normal JMP_4.
21882 MachineBasicBlock *RestoreMBB =
21883 MF->CreateMachineBasicBlock(BB->getBasicBlock());
21884 assert(BB->succ_size() == 1);
21885 MF->insert(std::next(BB->getIterator()), RestoreMBB);
21886 RestoreMBB->transferSuccessorsAndUpdatePHIs(BB);
21887 BB->addSuccessor(RestoreMBB);
21888 MI->getOperand(0).setMBB(RestoreMBB);
21890 auto RestoreMBBI = RestoreMBB->begin();
21891 BuildMI(*RestoreMBB, RestoreMBBI, DL, TII.get(X86::EH_RESTORE));
21892 BuildMI(*RestoreMBB, RestoreMBBI, DL, TII.get(X86::JMP_4)).addMBB(TargetMBB);
21896 MachineBasicBlock *
21897 X86TargetLowering::EmitLoweredCatchPad(MachineInstr *MI,
21898 MachineBasicBlock *BB) const {
21899 MachineFunction *MF = BB->getParent();
21900 const Constant *PerFn = MF->getFunction()->getPersonalityFn();
21901 bool IsSEH = isAsynchronousEHPersonality(classifyEHPersonality(PerFn));
21902 // Only 32-bit SEH requires special handling for catchpad.
21903 if (IsSEH && Subtarget->is32Bit()) {
21904 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
21905 DebugLoc DL = MI->getDebugLoc();
21906 BuildMI(*BB, MI, DL, TII.get(X86::EH_RESTORE));
21908 MI->eraseFromParent();
21912 MachineBasicBlock *
21913 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
21914 MachineBasicBlock *BB) const {
21915 // This is pretty easy. We're taking the value that we received from
21916 // our load from the relocation, sticking it in either RDI (x86-64)
21917 // or EAX and doing an indirect call. The return value will then
21918 // be in the normal return register.
21919 MachineFunction *F = BB->getParent();
21920 const X86InstrInfo *TII = Subtarget->getInstrInfo();
21921 DebugLoc DL = MI->getDebugLoc();
21923 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
21924 assert(MI->getOperand(3).isGlobal() && "This should be a global");
21926 // Get a register mask for the lowered call.
21927 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
21928 // proper register mask.
21929 const uint32_t *RegMask =
21930 Subtarget->is64Bit() ?
21931 Subtarget->getRegisterInfo()->getDarwinTLSCallPreservedMask() :
21932 Subtarget->getRegisterInfo()->getCallPreservedMask(*F, CallingConv::C);
21933 if (Subtarget->is64Bit()) {
21934 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
21935 TII->get(X86::MOV64rm), X86::RDI)
21937 .addImm(0).addReg(0)
21938 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
21939 MI->getOperand(3).getTargetFlags())
21941 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
21942 addDirectMem(MIB, X86::RDI);
21943 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
21944 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
21945 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
21946 TII->get(X86::MOV32rm), X86::EAX)
21948 .addImm(0).addReg(0)
21949 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
21950 MI->getOperand(3).getTargetFlags())
21952 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
21953 addDirectMem(MIB, X86::EAX);
21954 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
21956 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
21957 TII->get(X86::MOV32rm), X86::EAX)
21958 .addReg(TII->getGlobalBaseReg(F))
21959 .addImm(0).addReg(0)
21960 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
21961 MI->getOperand(3).getTargetFlags())
21963 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
21964 addDirectMem(MIB, X86::EAX);
21965 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
21968 MI->eraseFromParent(); // The pseudo instruction is gone now.
21972 MachineBasicBlock *
21973 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
21974 MachineBasicBlock *MBB) const {
21975 DebugLoc DL = MI->getDebugLoc();
21976 MachineFunction *MF = MBB->getParent();
21977 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21978 MachineRegisterInfo &MRI = MF->getRegInfo();
21980 const BasicBlock *BB = MBB->getBasicBlock();
21981 MachineFunction::iterator I = ++MBB->getIterator();
21983 // Memory Reference
21984 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
21985 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
21988 unsigned MemOpndSlot = 0;
21990 unsigned CurOp = 0;
21992 DstReg = MI->getOperand(CurOp++).getReg();
21993 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
21994 assert(RC->hasType(MVT::i32) && "Invalid destination!");
21995 unsigned mainDstReg = MRI.createVirtualRegister(RC);
21996 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
21998 MemOpndSlot = CurOp;
22000 MVT PVT = getPointerTy(MF->getDataLayout());
22001 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
22002 "Invalid Pointer Size!");
22004 // For v = setjmp(buf), we generate
22007 // buf[LabelOffset] = restoreMBB <-- takes address of restoreMBB
22008 // SjLjSetup restoreMBB
22014 // v = phi(main, restore)
22017 // if base pointer being used, load it from frame
22020 MachineBasicBlock *thisMBB = MBB;
22021 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
22022 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
22023 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
22024 MF->insert(I, mainMBB);
22025 MF->insert(I, sinkMBB);
22026 MF->push_back(restoreMBB);
22027 restoreMBB->setHasAddressTaken();
22029 MachineInstrBuilder MIB;
22031 // Transfer the remainder of BB and its successor edges to sinkMBB.
22032 sinkMBB->splice(sinkMBB->begin(), MBB,
22033 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
22034 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
22037 unsigned PtrStoreOpc = 0;
22038 unsigned LabelReg = 0;
22039 const int64_t LabelOffset = 1 * PVT.getStoreSize();
22040 Reloc::Model RM = MF->getTarget().getRelocationModel();
22041 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
22042 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
22044 // Prepare IP either in reg or imm.
22045 if (!UseImmLabel) {
22046 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
22047 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
22048 LabelReg = MRI.createVirtualRegister(PtrRC);
22049 if (Subtarget->is64Bit()) {
22050 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
22054 .addMBB(restoreMBB)
22057 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
22058 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
22059 .addReg(XII->getGlobalBaseReg(MF))
22062 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
22066 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
22068 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
22069 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
22070 if (i == X86::AddrDisp)
22071 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
22073 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
22076 MIB.addReg(LabelReg);
22078 MIB.addMBB(restoreMBB);
22079 MIB.setMemRefs(MMOBegin, MMOEnd);
22081 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
22082 .addMBB(restoreMBB);
22084 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
22085 MIB.addRegMask(RegInfo->getNoPreservedMask());
22086 thisMBB->addSuccessor(mainMBB);
22087 thisMBB->addSuccessor(restoreMBB);
22091 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
22092 mainMBB->addSuccessor(sinkMBB);
22095 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
22096 TII->get(X86::PHI), DstReg)
22097 .addReg(mainDstReg).addMBB(mainMBB)
22098 .addReg(restoreDstReg).addMBB(restoreMBB);
22101 if (RegInfo->hasBasePointer(*MF)) {
22102 const bool Uses64BitFramePtr =
22103 Subtarget->isTarget64BitLP64() || Subtarget->isTargetNaCl64();
22104 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
22105 X86FI->setRestoreBasePointer(MF);
22106 unsigned FramePtr = RegInfo->getFrameRegister(*MF);
22107 unsigned BasePtr = RegInfo->getBaseRegister();
22108 unsigned Opm = Uses64BitFramePtr ? X86::MOV64rm : X86::MOV32rm;
22109 addRegOffset(BuildMI(restoreMBB, DL, TII->get(Opm), BasePtr),
22110 FramePtr, true, X86FI->getRestoreBasePointerOffset())
22111 .setMIFlag(MachineInstr::FrameSetup);
22113 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
22114 BuildMI(restoreMBB, DL, TII->get(X86::JMP_1)).addMBB(sinkMBB);
22115 restoreMBB->addSuccessor(sinkMBB);
22117 MI->eraseFromParent();
22121 MachineBasicBlock *
22122 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
22123 MachineBasicBlock *MBB) const {
22124 DebugLoc DL = MI->getDebugLoc();
22125 MachineFunction *MF = MBB->getParent();
22126 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
22127 MachineRegisterInfo &MRI = MF->getRegInfo();
22129 // Memory Reference
22130 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
22131 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
22133 MVT PVT = getPointerTy(MF->getDataLayout());
22134 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
22135 "Invalid Pointer Size!");
22137 const TargetRegisterClass *RC =
22138 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
22139 unsigned Tmp = MRI.createVirtualRegister(RC);
22140 // Since FP is only updated here but NOT referenced, it's treated as GPR.
22141 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
22142 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
22143 unsigned SP = RegInfo->getStackRegister();
22145 MachineInstrBuilder MIB;
22147 const int64_t LabelOffset = 1 * PVT.getStoreSize();
22148 const int64_t SPOffset = 2 * PVT.getStoreSize();
22150 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
22151 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
22154 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
22155 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
22156 MIB.addOperand(MI->getOperand(i));
22157 MIB.setMemRefs(MMOBegin, MMOEnd);
22159 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
22160 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
22161 if (i == X86::AddrDisp)
22162 MIB.addDisp(MI->getOperand(i), LabelOffset);
22164 MIB.addOperand(MI->getOperand(i));
22166 MIB.setMemRefs(MMOBegin, MMOEnd);
22168 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
22169 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
22170 if (i == X86::AddrDisp)
22171 MIB.addDisp(MI->getOperand(i), SPOffset);
22173 MIB.addOperand(MI->getOperand(i));
22175 MIB.setMemRefs(MMOBegin, MMOEnd);
22177 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
22179 MI->eraseFromParent();
22183 // Replace 213-type (isel default) FMA3 instructions with 231-type for
22184 // accumulator loops. Writing back to the accumulator allows the coalescer
22185 // to remove extra copies in the loop.
22186 // FIXME: Do this on AVX512. We don't support 231 variants yet (PR23937).
22187 MachineBasicBlock *
22188 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
22189 MachineBasicBlock *MBB) const {
22190 MachineOperand &AddendOp = MI->getOperand(3);
22192 // Bail out early if the addend isn't a register - we can't switch these.
22193 if (!AddendOp.isReg())
22196 MachineFunction &MF = *MBB->getParent();
22197 MachineRegisterInfo &MRI = MF.getRegInfo();
22199 // Check whether the addend is defined by a PHI:
22200 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
22201 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
22202 if (!AddendDef.isPHI())
22205 // Look for the following pattern:
22207 // %addend = phi [%entry, 0], [%loop, %result]
22209 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
22213 // %addend = phi [%entry, 0], [%loop, %result]
22215 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
22217 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
22218 assert(AddendDef.getOperand(i).isReg());
22219 MachineOperand PHISrcOp = AddendDef.getOperand(i);
22220 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
22221 if (&PHISrcInst == MI) {
22222 // Found a matching instruction.
22223 unsigned NewFMAOpc = 0;
22224 switch (MI->getOpcode()) {
22225 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
22226 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
22227 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
22228 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
22229 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
22230 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
22231 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
22232 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
22233 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
22234 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
22235 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
22236 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
22237 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
22238 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
22239 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
22240 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
22241 case X86::VFMADDSUBPDr213r: NewFMAOpc = X86::VFMADDSUBPDr231r; break;
22242 case X86::VFMADDSUBPSr213r: NewFMAOpc = X86::VFMADDSUBPSr231r; break;
22243 case X86::VFMSUBADDPDr213r: NewFMAOpc = X86::VFMSUBADDPDr231r; break;
22244 case X86::VFMSUBADDPSr213r: NewFMAOpc = X86::VFMSUBADDPSr231r; break;
22246 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
22247 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
22248 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
22249 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
22250 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
22251 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
22252 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
22253 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
22254 case X86::VFMADDSUBPDr213rY: NewFMAOpc = X86::VFMADDSUBPDr231rY; break;
22255 case X86::VFMADDSUBPSr213rY: NewFMAOpc = X86::VFMADDSUBPSr231rY; break;
22256 case X86::VFMSUBADDPDr213rY: NewFMAOpc = X86::VFMSUBADDPDr231rY; break;
22257 case X86::VFMSUBADDPSr213rY: NewFMAOpc = X86::VFMSUBADDPSr231rY; break;
22258 default: llvm_unreachable("Unrecognized FMA variant.");
22261 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
22262 MachineInstrBuilder MIB =
22263 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
22264 .addOperand(MI->getOperand(0))
22265 .addOperand(MI->getOperand(3))
22266 .addOperand(MI->getOperand(2))
22267 .addOperand(MI->getOperand(1));
22268 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
22269 MI->eraseFromParent();
22276 MachineBasicBlock *
22277 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
22278 MachineBasicBlock *BB) const {
22279 switch (MI->getOpcode()) {
22280 default: llvm_unreachable("Unexpected instr type to insert");
22281 case X86::TAILJMPd64:
22282 case X86::TAILJMPr64:
22283 case X86::TAILJMPm64:
22284 case X86::TAILJMPd64_REX:
22285 case X86::TAILJMPr64_REX:
22286 case X86::TAILJMPm64_REX:
22287 llvm_unreachable("TAILJMP64 would not be touched here.");
22288 case X86::TCRETURNdi64:
22289 case X86::TCRETURNri64:
22290 case X86::TCRETURNmi64:
22292 case X86::WIN_ALLOCA:
22293 return EmitLoweredWinAlloca(MI, BB);
22294 case X86::CATCHRET:
22295 return EmitLoweredCatchRet(MI, BB);
22296 case X86::CATCHPAD:
22297 return EmitLoweredCatchPad(MI, BB);
22298 case X86::SEG_ALLOCA_32:
22299 case X86::SEG_ALLOCA_64:
22300 return EmitLoweredSegAlloca(MI, BB);
22301 case X86::TLSCall_32:
22302 case X86::TLSCall_64:
22303 return EmitLoweredTLSCall(MI, BB);
22304 case X86::CMOV_FR32:
22305 case X86::CMOV_FR64:
22306 case X86::CMOV_FR128:
22307 case X86::CMOV_GR8:
22308 case X86::CMOV_GR16:
22309 case X86::CMOV_GR32:
22310 case X86::CMOV_RFP32:
22311 case X86::CMOV_RFP64:
22312 case X86::CMOV_RFP80:
22313 case X86::CMOV_V2F64:
22314 case X86::CMOV_V2I64:
22315 case X86::CMOV_V4F32:
22316 case X86::CMOV_V4F64:
22317 case X86::CMOV_V4I64:
22318 case X86::CMOV_V16F32:
22319 case X86::CMOV_V8F32:
22320 case X86::CMOV_V8F64:
22321 case X86::CMOV_V8I64:
22322 case X86::CMOV_V8I1:
22323 case X86::CMOV_V16I1:
22324 case X86::CMOV_V32I1:
22325 case X86::CMOV_V64I1:
22326 return EmitLoweredSelect(MI, BB);
22328 case X86::RELEASE_FADD32mr:
22329 case X86::RELEASE_FADD64mr:
22330 return EmitLoweredAtomicFP(MI, BB);
22332 case X86::FP32_TO_INT16_IN_MEM:
22333 case X86::FP32_TO_INT32_IN_MEM:
22334 case X86::FP32_TO_INT64_IN_MEM:
22335 case X86::FP64_TO_INT16_IN_MEM:
22336 case X86::FP64_TO_INT32_IN_MEM:
22337 case X86::FP64_TO_INT64_IN_MEM:
22338 case X86::FP80_TO_INT16_IN_MEM:
22339 case X86::FP80_TO_INT32_IN_MEM:
22340 case X86::FP80_TO_INT64_IN_MEM: {
22341 MachineFunction *F = BB->getParent();
22342 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
22343 DebugLoc DL = MI->getDebugLoc();
22345 // Change the floating point control register to use "round towards zero"
22346 // mode when truncating to an integer value.
22347 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
22348 addFrameReference(BuildMI(*BB, MI, DL,
22349 TII->get(X86::FNSTCW16m)), CWFrameIdx);
22351 // Load the old value of the high byte of the control word...
22353 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
22354 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
22357 // Set the high part to be round to zero...
22358 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
22361 // Reload the modified control word now...
22362 addFrameReference(BuildMI(*BB, MI, DL,
22363 TII->get(X86::FLDCW16m)), CWFrameIdx);
22365 // Restore the memory image of control word to original value
22366 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
22369 // Get the X86 opcode to use.
22371 switch (MI->getOpcode()) {
22372 default: llvm_unreachable("illegal opcode!");
22373 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
22374 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
22375 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
22376 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
22377 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
22378 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
22379 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
22380 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
22381 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
22385 MachineOperand &Op = MI->getOperand(0);
22387 AM.BaseType = X86AddressMode::RegBase;
22388 AM.Base.Reg = Op.getReg();
22390 AM.BaseType = X86AddressMode::FrameIndexBase;
22391 AM.Base.FrameIndex = Op.getIndex();
22393 Op = MI->getOperand(1);
22395 AM.Scale = Op.getImm();
22396 Op = MI->getOperand(2);
22398 AM.IndexReg = Op.getImm();
22399 Op = MI->getOperand(3);
22400 if (Op.isGlobal()) {
22401 AM.GV = Op.getGlobal();
22403 AM.Disp = Op.getImm();
22405 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
22406 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
22408 // Reload the original control word now.
22409 addFrameReference(BuildMI(*BB, MI, DL,
22410 TII->get(X86::FLDCW16m)), CWFrameIdx);
22412 MI->eraseFromParent(); // The pseudo instruction is gone now.
22415 // String/text processing lowering.
22416 case X86::PCMPISTRM128REG:
22417 case X86::VPCMPISTRM128REG:
22418 case X86::PCMPISTRM128MEM:
22419 case X86::VPCMPISTRM128MEM:
22420 case X86::PCMPESTRM128REG:
22421 case X86::VPCMPESTRM128REG:
22422 case X86::PCMPESTRM128MEM:
22423 case X86::VPCMPESTRM128MEM:
22424 assert(Subtarget->hasSSE42() &&
22425 "Target must have SSE4.2 or AVX features enabled");
22426 return EmitPCMPSTRM(MI, BB, Subtarget->getInstrInfo());
22428 // String/text processing lowering.
22429 case X86::PCMPISTRIREG:
22430 case X86::VPCMPISTRIREG:
22431 case X86::PCMPISTRIMEM:
22432 case X86::VPCMPISTRIMEM:
22433 case X86::PCMPESTRIREG:
22434 case X86::VPCMPESTRIREG:
22435 case X86::PCMPESTRIMEM:
22436 case X86::VPCMPESTRIMEM:
22437 assert(Subtarget->hasSSE42() &&
22438 "Target must have SSE4.2 or AVX features enabled");
22439 return EmitPCMPSTRI(MI, BB, Subtarget->getInstrInfo());
22441 // Thread synchronization.
22443 return EmitMonitor(MI, BB, Subtarget);
22447 return EmitXBegin(MI, BB, Subtarget->getInstrInfo());
22449 case X86::VASTART_SAVE_XMM_REGS:
22450 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
22452 case X86::VAARG_64:
22453 return EmitVAARG64WithCustomInserter(MI, BB);
22455 case X86::EH_SjLj_SetJmp32:
22456 case X86::EH_SjLj_SetJmp64:
22457 return emitEHSjLjSetJmp(MI, BB);
22459 case X86::EH_SjLj_LongJmp32:
22460 case X86::EH_SjLj_LongJmp64:
22461 return emitEHSjLjLongJmp(MI, BB);
22463 case TargetOpcode::STATEPOINT:
22464 // As an implementation detail, STATEPOINT shares the STACKMAP format at
22465 // this point in the process. We diverge later.
22466 return emitPatchPoint(MI, BB);
22468 case TargetOpcode::STACKMAP:
22469 case TargetOpcode::PATCHPOINT:
22470 return emitPatchPoint(MI, BB);
22472 case X86::VFMADDPDr213r:
22473 case X86::VFMADDPSr213r:
22474 case X86::VFMADDSDr213r:
22475 case X86::VFMADDSSr213r:
22476 case X86::VFMSUBPDr213r:
22477 case X86::VFMSUBPSr213r:
22478 case X86::VFMSUBSDr213r:
22479 case X86::VFMSUBSSr213r:
22480 case X86::VFNMADDPDr213r:
22481 case X86::VFNMADDPSr213r:
22482 case X86::VFNMADDSDr213r:
22483 case X86::VFNMADDSSr213r:
22484 case X86::VFNMSUBPDr213r:
22485 case X86::VFNMSUBPSr213r:
22486 case X86::VFNMSUBSDr213r:
22487 case X86::VFNMSUBSSr213r:
22488 case X86::VFMADDSUBPDr213r:
22489 case X86::VFMADDSUBPSr213r:
22490 case X86::VFMSUBADDPDr213r:
22491 case X86::VFMSUBADDPSr213r:
22492 case X86::VFMADDPDr213rY:
22493 case X86::VFMADDPSr213rY:
22494 case X86::VFMSUBPDr213rY:
22495 case X86::VFMSUBPSr213rY:
22496 case X86::VFNMADDPDr213rY:
22497 case X86::VFNMADDPSr213rY:
22498 case X86::VFNMSUBPDr213rY:
22499 case X86::VFNMSUBPSr213rY:
22500 case X86::VFMADDSUBPDr213rY:
22501 case X86::VFMADDSUBPSr213rY:
22502 case X86::VFMSUBADDPDr213rY:
22503 case X86::VFMSUBADDPSr213rY:
22504 return emitFMA3Instr(MI, BB);
22508 //===----------------------------------------------------------------------===//
22509 // X86 Optimization Hooks
22510 //===----------------------------------------------------------------------===//
22512 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
22515 const SelectionDAG &DAG,
22516 unsigned Depth) const {
22517 unsigned BitWidth = KnownZero.getBitWidth();
22518 unsigned Opc = Op.getOpcode();
22519 assert((Opc >= ISD::BUILTIN_OP_END ||
22520 Opc == ISD::INTRINSIC_WO_CHAIN ||
22521 Opc == ISD::INTRINSIC_W_CHAIN ||
22522 Opc == ISD::INTRINSIC_VOID) &&
22523 "Should use MaskedValueIsZero if you don't know whether Op"
22524 " is a target node!");
22526 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
22540 // These nodes' second result is a boolean.
22541 if (Op.getResNo() == 0)
22544 case X86ISD::SETCC:
22545 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
22547 case ISD::INTRINSIC_WO_CHAIN: {
22548 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
22549 unsigned NumLoBits = 0;
22552 case Intrinsic::x86_sse_movmsk_ps:
22553 case Intrinsic::x86_avx_movmsk_ps_256:
22554 case Intrinsic::x86_sse2_movmsk_pd:
22555 case Intrinsic::x86_avx_movmsk_pd_256:
22556 case Intrinsic::x86_mmx_pmovmskb:
22557 case Intrinsic::x86_sse2_pmovmskb_128:
22558 case Intrinsic::x86_avx2_pmovmskb: {
22559 // High bits of movmskp{s|d}, pmovmskb are known zero.
22561 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
22562 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
22563 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
22564 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
22565 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
22566 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
22567 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
22568 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
22570 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
22579 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
22581 const SelectionDAG &,
22582 unsigned Depth) const {
22583 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
22584 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
22585 return Op.getValueType().getScalarSizeInBits();
22591 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
22592 /// node is a GlobalAddress + offset.
22593 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
22594 const GlobalValue* &GA,
22595 int64_t &Offset) const {
22596 if (N->getOpcode() == X86ISD::Wrapper) {
22597 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
22598 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
22599 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
22603 return TargetLowering::isGAPlusOffset(N, GA, Offset);
22606 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
22607 /// same as extracting the high 128-bit part of 256-bit vector and then
22608 /// inserting the result into the low part of a new 256-bit vector
22609 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
22610 EVT VT = SVOp->getValueType(0);
22611 unsigned NumElems = VT.getVectorNumElements();
22613 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
22614 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
22615 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
22616 SVOp->getMaskElt(j) >= 0)
22622 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
22623 /// same as extracting the low 128-bit part of 256-bit vector and then
22624 /// inserting the result into the high part of a new 256-bit vector
22625 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
22626 EVT VT = SVOp->getValueType(0);
22627 unsigned NumElems = VT.getVectorNumElements();
22629 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
22630 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
22631 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
22632 SVOp->getMaskElt(j) >= 0)
22638 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
22639 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
22640 TargetLowering::DAGCombinerInfo &DCI,
22641 const X86Subtarget* Subtarget) {
22643 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
22644 SDValue V1 = SVOp->getOperand(0);
22645 SDValue V2 = SVOp->getOperand(1);
22646 MVT VT = SVOp->getSimpleValueType(0);
22647 unsigned NumElems = VT.getVectorNumElements();
22649 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
22650 V2.getOpcode() == ISD::CONCAT_VECTORS) {
22654 // V UNDEF BUILD_VECTOR UNDEF
22656 // CONCAT_VECTOR CONCAT_VECTOR
22659 // RESULT: V + zero extended
22661 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
22662 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
22663 V1.getOperand(1).getOpcode() != ISD::UNDEF)
22666 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
22669 // To match the shuffle mask, the first half of the mask should
22670 // be exactly the first vector, and all the rest a splat with the
22671 // first element of the second one.
22672 for (unsigned i = 0; i != NumElems/2; ++i)
22673 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
22674 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
22677 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
22678 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
22679 if (Ld->hasNUsesOfValue(1, 0)) {
22680 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
22681 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
22683 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
22685 Ld->getPointerInfo(),
22686 Ld->getAlignment(),
22687 false/*isVolatile*/, true/*ReadMem*/,
22688 false/*WriteMem*/);
22690 // Make sure the newly-created LOAD is in the same position as Ld in
22691 // terms of dependency. We create a TokenFactor for Ld and ResNode,
22692 // and update uses of Ld's output chain to use the TokenFactor.
22693 if (Ld->hasAnyUseOfValue(1)) {
22694 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
22695 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
22696 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
22697 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
22698 SDValue(ResNode.getNode(), 1));
22701 return DAG.getBitcast(VT, ResNode);
22705 // Emit a zeroed vector and insert the desired subvector on its
22707 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
22708 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
22709 return DCI.CombineTo(N, InsV);
22712 //===--------------------------------------------------------------------===//
22713 // Combine some shuffles into subvector extracts and inserts:
22716 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
22717 if (isShuffleHigh128VectorInsertLow(SVOp)) {
22718 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
22719 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
22720 return DCI.CombineTo(N, InsV);
22723 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
22724 if (isShuffleLow128VectorInsertHigh(SVOp)) {
22725 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
22726 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
22727 return DCI.CombineTo(N, InsV);
22733 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
22736 /// This is the leaf of the recursive combinine below. When we have found some
22737 /// chain of single-use x86 shuffle instructions and accumulated the combined
22738 /// shuffle mask represented by them, this will try to pattern match that mask
22739 /// into either a single instruction if there is a special purpose instruction
22740 /// for this operation, or into a PSHUFB instruction which is a fully general
22741 /// instruction but should only be used to replace chains over a certain depth.
22742 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
22743 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
22744 TargetLowering::DAGCombinerInfo &DCI,
22745 const X86Subtarget *Subtarget) {
22746 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
22748 // Find the operand that enters the chain. Note that multiple uses are OK
22749 // here, we're not going to remove the operand we find.
22750 SDValue Input = Op.getOperand(0);
22751 while (Input.getOpcode() == ISD::BITCAST)
22752 Input = Input.getOperand(0);
22754 MVT VT = Input.getSimpleValueType();
22755 MVT RootVT = Root.getSimpleValueType();
22758 if (Mask.size() == 1) {
22759 int Index = Mask[0];
22760 assert((Index >= 0 || Index == SM_SentinelUndef ||
22761 Index == SM_SentinelZero) &&
22762 "Invalid shuffle index found!");
22764 // We may end up with an accumulated mask of size 1 as a result of
22765 // widening of shuffle operands (see function canWidenShuffleElements).
22766 // If the only shuffle index is equal to SM_SentinelZero then propagate
22767 // a zero vector. Otherwise, the combine shuffle mask is a no-op shuffle
22768 // mask, and therefore the entire chain of shuffles can be folded away.
22769 if (Index == SM_SentinelZero)
22770 DCI.CombineTo(Root.getNode(), getZeroVector(RootVT, Subtarget, DAG, DL));
22772 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Input),
22777 // Use the float domain if the operand type is a floating point type.
22778 bool FloatDomain = VT.isFloatingPoint();
22780 // For floating point shuffles, we don't have free copies in the shuffle
22781 // instructions or the ability to load as part of the instruction, so
22782 // canonicalize their shuffles to UNPCK or MOV variants.
22784 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
22785 // vectors because it can have a load folded into it that UNPCK cannot. This
22786 // doesn't preclude something switching to the shorter encoding post-RA.
22788 // FIXME: Should teach these routines about AVX vector widths.
22789 if (FloatDomain && VT.is128BitVector()) {
22790 if (Mask.equals({0, 0}) || Mask.equals({1, 1})) {
22791 bool Lo = Mask.equals({0, 0});
22794 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
22795 // is no slower than UNPCKLPD but has the option to fold the input operand
22796 // into even an unaligned memory load.
22797 if (Lo && Subtarget->hasSSE3()) {
22798 Shuffle = X86ISD::MOVDDUP;
22799 ShuffleVT = MVT::v2f64;
22801 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
22802 // than the UNPCK variants.
22803 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
22804 ShuffleVT = MVT::v4f32;
22806 if (Depth == 1 && Root->getOpcode() == Shuffle)
22807 return false; // Nothing to do!
22808 Op = DAG.getBitcast(ShuffleVT, Input);
22809 DCI.AddToWorklist(Op.getNode());
22810 if (Shuffle == X86ISD::MOVDDUP)
22811 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
22813 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
22814 DCI.AddToWorklist(Op.getNode());
22815 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22819 if (Subtarget->hasSSE3() &&
22820 (Mask.equals({0, 0, 2, 2}) || Mask.equals({1, 1, 3, 3}))) {
22821 bool Lo = Mask.equals({0, 0, 2, 2});
22822 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
22823 MVT ShuffleVT = MVT::v4f32;
22824 if (Depth == 1 && Root->getOpcode() == Shuffle)
22825 return false; // Nothing to do!
22826 Op = DAG.getBitcast(ShuffleVT, Input);
22827 DCI.AddToWorklist(Op.getNode());
22828 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
22829 DCI.AddToWorklist(Op.getNode());
22830 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22834 if (Mask.equals({0, 0, 1, 1}) || Mask.equals({2, 2, 3, 3})) {
22835 bool Lo = Mask.equals({0, 0, 1, 1});
22836 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
22837 MVT ShuffleVT = MVT::v4f32;
22838 if (Depth == 1 && Root->getOpcode() == Shuffle)
22839 return false; // Nothing to do!
22840 Op = DAG.getBitcast(ShuffleVT, Input);
22841 DCI.AddToWorklist(Op.getNode());
22842 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
22843 DCI.AddToWorklist(Op.getNode());
22844 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22850 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
22851 // variants as none of these have single-instruction variants that are
22852 // superior to the UNPCK formulation.
22853 if (!FloatDomain && VT.is128BitVector() &&
22854 (Mask.equals({0, 0, 1, 1, 2, 2, 3, 3}) ||
22855 Mask.equals({4, 4, 5, 5, 6, 6, 7, 7}) ||
22856 Mask.equals({0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7}) ||
22858 {8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}))) {
22859 bool Lo = Mask[0] == 0;
22860 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
22861 if (Depth == 1 && Root->getOpcode() == Shuffle)
22862 return false; // Nothing to do!
22864 switch (Mask.size()) {
22866 ShuffleVT = MVT::v8i16;
22869 ShuffleVT = MVT::v16i8;
22872 llvm_unreachable("Impossible mask size!");
22874 Op = DAG.getBitcast(ShuffleVT, Input);
22875 DCI.AddToWorklist(Op.getNode());
22876 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
22877 DCI.AddToWorklist(Op.getNode());
22878 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22883 // Don't try to re-form single instruction chains under any circumstances now
22884 // that we've done encoding canonicalization for them.
22888 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
22889 // can replace them with a single PSHUFB instruction profitably. Intel's
22890 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
22891 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
22892 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
22893 SmallVector<SDValue, 16> PSHUFBMask;
22894 int NumBytes = VT.getSizeInBits() / 8;
22895 int Ratio = NumBytes / Mask.size();
22896 for (int i = 0; i < NumBytes; ++i) {
22897 if (Mask[i / Ratio] == SM_SentinelUndef) {
22898 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
22901 int M = Mask[i / Ratio] != SM_SentinelZero
22902 ? Ratio * Mask[i / Ratio] + i % Ratio
22904 PSHUFBMask.push_back(DAG.getConstant(M, DL, MVT::i8));
22906 MVT ByteVT = MVT::getVectorVT(MVT::i8, NumBytes);
22907 Op = DAG.getBitcast(ByteVT, Input);
22908 DCI.AddToWorklist(Op.getNode());
22909 SDValue PSHUFBMaskOp =
22910 DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVT, PSHUFBMask);
22911 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
22912 Op = DAG.getNode(X86ISD::PSHUFB, DL, ByteVT, Op, PSHUFBMaskOp);
22913 DCI.AddToWorklist(Op.getNode());
22914 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22919 // Failed to find any combines.
22923 /// \brief Fully generic combining of x86 shuffle instructions.
22925 /// This should be the last combine run over the x86 shuffle instructions. Once
22926 /// they have been fully optimized, this will recursively consider all chains
22927 /// of single-use shuffle instructions, build a generic model of the cumulative
22928 /// shuffle operation, and check for simpler instructions which implement this
22929 /// operation. We use this primarily for two purposes:
22931 /// 1) Collapse generic shuffles to specialized single instructions when
22932 /// equivalent. In most cases, this is just an encoding size win, but
22933 /// sometimes we will collapse multiple generic shuffles into a single
22934 /// special-purpose shuffle.
22935 /// 2) Look for sequences of shuffle instructions with 3 or more total
22936 /// instructions, and replace them with the slightly more expensive SSSE3
22937 /// PSHUFB instruction if available. We do this as the last combining step
22938 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
22939 /// a suitable short sequence of other instructions. The PHUFB will either
22940 /// use a register or have to read from memory and so is slightly (but only
22941 /// slightly) more expensive than the other shuffle instructions.
22943 /// Because this is inherently a quadratic operation (for each shuffle in
22944 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
22945 /// This should never be an issue in practice as the shuffle lowering doesn't
22946 /// produce sequences of more than 8 instructions.
22948 /// FIXME: We will currently miss some cases where the redundant shuffling
22949 /// would simplify under the threshold for PSHUFB formation because of
22950 /// combine-ordering. To fix this, we should do the redundant instruction
22951 /// combining in this recursive walk.
22952 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
22953 ArrayRef<int> RootMask,
22954 int Depth, bool HasPSHUFB,
22956 TargetLowering::DAGCombinerInfo &DCI,
22957 const X86Subtarget *Subtarget) {
22958 // Bound the depth of our recursive combine because this is ultimately
22959 // quadratic in nature.
22963 // Directly rip through bitcasts to find the underlying operand.
22964 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
22965 Op = Op.getOperand(0);
22967 MVT VT = Op.getSimpleValueType();
22968 if (!VT.isVector())
22969 return false; // Bail if we hit a non-vector.
22971 assert(Root.getSimpleValueType().isVector() &&
22972 "Shuffles operate on vector types!");
22973 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
22974 "Can only combine shuffles of the same vector register size.");
22976 if (!isTargetShuffle(Op.getOpcode()))
22978 SmallVector<int, 16> OpMask;
22980 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
22981 // We only can combine unary shuffles which we can decode the mask for.
22982 if (!HaveMask || !IsUnary)
22985 assert(VT.getVectorNumElements() == OpMask.size() &&
22986 "Different mask size from vector size!");
22987 assert(((RootMask.size() > OpMask.size() &&
22988 RootMask.size() % OpMask.size() == 0) ||
22989 (OpMask.size() > RootMask.size() &&
22990 OpMask.size() % RootMask.size() == 0) ||
22991 OpMask.size() == RootMask.size()) &&
22992 "The smaller number of elements must divide the larger.");
22993 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
22994 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
22995 assert(((RootRatio == 1 && OpRatio == 1) ||
22996 (RootRatio == 1) != (OpRatio == 1)) &&
22997 "Must not have a ratio for both incoming and op masks!");
22999 SmallVector<int, 16> Mask;
23000 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
23002 // Merge this shuffle operation's mask into our accumulated mask. Note that
23003 // this shuffle's mask will be the first applied to the input, followed by the
23004 // root mask to get us all the way to the root value arrangement. The reason
23005 // for this order is that we are recursing up the operation chain.
23006 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
23007 int RootIdx = i / RootRatio;
23008 if (RootMask[RootIdx] < 0) {
23009 // This is a zero or undef lane, we're done.
23010 Mask.push_back(RootMask[RootIdx]);
23014 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
23015 int OpIdx = RootMaskedIdx / OpRatio;
23016 if (OpMask[OpIdx] < 0) {
23017 // The incoming lanes are zero or undef, it doesn't matter which ones we
23019 Mask.push_back(OpMask[OpIdx]);
23023 // Ok, we have non-zero lanes, map them through.
23024 Mask.push_back(OpMask[OpIdx] * OpRatio +
23025 RootMaskedIdx % OpRatio);
23028 // See if we can recurse into the operand to combine more things.
23029 switch (Op.getOpcode()) {
23030 case X86ISD::PSHUFB:
23032 case X86ISD::PSHUFD:
23033 case X86ISD::PSHUFHW:
23034 case X86ISD::PSHUFLW:
23035 if (Op.getOperand(0).hasOneUse() &&
23036 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
23037 HasPSHUFB, DAG, DCI, Subtarget))
23041 case X86ISD::UNPCKL:
23042 case X86ISD::UNPCKH:
23043 assert(Op.getOperand(0) == Op.getOperand(1) &&
23044 "We only combine unary shuffles!");
23045 // We can't check for single use, we have to check that this shuffle is the
23047 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
23048 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
23049 HasPSHUFB, DAG, DCI, Subtarget))
23054 // Minor canonicalization of the accumulated shuffle mask to make it easier
23055 // to match below. All this does is detect masks with squential pairs of
23056 // elements, and shrink them to the half-width mask. It does this in a loop
23057 // so it will reduce the size of the mask to the minimal width mask which
23058 // performs an equivalent shuffle.
23059 SmallVector<int, 16> WidenedMask;
23060 while (Mask.size() > 1 && canWidenShuffleElements(Mask, WidenedMask)) {
23061 Mask = std::move(WidenedMask);
23062 WidenedMask.clear();
23065 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
23069 /// \brief Get the PSHUF-style mask from PSHUF node.
23071 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
23072 /// PSHUF-style masks that can be reused with such instructions.
23073 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
23074 MVT VT = N.getSimpleValueType();
23075 SmallVector<int, 4> Mask;
23077 bool HaveMask = getTargetShuffleMask(N.getNode(), VT, Mask, IsUnary);
23081 // If we have more than 128-bits, only the low 128-bits of shuffle mask
23082 // matter. Check that the upper masks are repeats and remove them.
23083 if (VT.getSizeInBits() > 128) {
23084 int LaneElts = 128 / VT.getScalarSizeInBits();
23086 for (int i = 1, NumLanes = VT.getSizeInBits() / 128; i < NumLanes; ++i)
23087 for (int j = 0; j < LaneElts; ++j)
23088 assert(Mask[j] == Mask[i * LaneElts + j] - (LaneElts * i) &&
23089 "Mask doesn't repeat in high 128-bit lanes!");
23091 Mask.resize(LaneElts);
23094 switch (N.getOpcode()) {
23095 case X86ISD::PSHUFD:
23097 case X86ISD::PSHUFLW:
23100 case X86ISD::PSHUFHW:
23101 Mask.erase(Mask.begin(), Mask.begin() + 4);
23102 for (int &M : Mask)
23106 llvm_unreachable("No valid shuffle instruction found!");
23110 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
23112 /// We walk up the chain and look for a combinable shuffle, skipping over
23113 /// shuffles that we could hoist this shuffle's transformation past without
23114 /// altering anything.
23116 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
23118 TargetLowering::DAGCombinerInfo &DCI) {
23119 assert(N.getOpcode() == X86ISD::PSHUFD &&
23120 "Called with something other than an x86 128-bit half shuffle!");
23123 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
23124 // of the shuffles in the chain so that we can form a fresh chain to replace
23126 SmallVector<SDValue, 8> Chain;
23127 SDValue V = N.getOperand(0);
23128 for (; V.hasOneUse(); V = V.getOperand(0)) {
23129 switch (V.getOpcode()) {
23131 return SDValue(); // Nothing combined!
23134 // Skip bitcasts as we always know the type for the target specific
23138 case X86ISD::PSHUFD:
23139 // Found another dword shuffle.
23142 case X86ISD::PSHUFLW:
23143 // Check that the low words (being shuffled) are the identity in the
23144 // dword shuffle, and the high words are self-contained.
23145 if (Mask[0] != 0 || Mask[1] != 1 ||
23146 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
23149 Chain.push_back(V);
23152 case X86ISD::PSHUFHW:
23153 // Check that the high words (being shuffled) are the identity in the
23154 // dword shuffle, and the low words are self-contained.
23155 if (Mask[2] != 2 || Mask[3] != 3 ||
23156 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
23159 Chain.push_back(V);
23162 case X86ISD::UNPCKL:
23163 case X86ISD::UNPCKH:
23164 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
23165 // shuffle into a preceding word shuffle.
23166 if (V.getSimpleValueType().getVectorElementType() != MVT::i8 &&
23167 V.getSimpleValueType().getVectorElementType() != MVT::i16)
23170 // Search for a half-shuffle which we can combine with.
23171 unsigned CombineOp =
23172 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
23173 if (V.getOperand(0) != V.getOperand(1) ||
23174 !V->isOnlyUserOf(V.getOperand(0).getNode()))
23176 Chain.push_back(V);
23177 V = V.getOperand(0);
23179 switch (V.getOpcode()) {
23181 return SDValue(); // Nothing to combine.
23183 case X86ISD::PSHUFLW:
23184 case X86ISD::PSHUFHW:
23185 if (V.getOpcode() == CombineOp)
23188 Chain.push_back(V);
23192 V = V.getOperand(0);
23196 } while (V.hasOneUse());
23199 // Break out of the loop if we break out of the switch.
23203 if (!V.hasOneUse())
23204 // We fell out of the loop without finding a viable combining instruction.
23207 // Merge this node's mask and our incoming mask.
23208 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
23209 for (int &M : Mask)
23211 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
23212 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
23214 // Rebuild the chain around this new shuffle.
23215 while (!Chain.empty()) {
23216 SDValue W = Chain.pop_back_val();
23218 if (V.getValueType() != W.getOperand(0).getValueType())
23219 V = DAG.getBitcast(W.getOperand(0).getValueType(), V);
23221 switch (W.getOpcode()) {
23223 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
23225 case X86ISD::UNPCKL:
23226 case X86ISD::UNPCKH:
23227 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
23230 case X86ISD::PSHUFD:
23231 case X86ISD::PSHUFLW:
23232 case X86ISD::PSHUFHW:
23233 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
23237 if (V.getValueType() != N.getValueType())
23238 V = DAG.getBitcast(N.getValueType(), V);
23240 // Return the new chain to replace N.
23244 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or
23247 /// We walk up the chain, skipping shuffles of the other half and looking
23248 /// through shuffles which switch halves trying to find a shuffle of the same
23249 /// pair of dwords.
23250 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
23252 TargetLowering::DAGCombinerInfo &DCI) {
23254 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
23255 "Called with something other than an x86 128-bit half shuffle!");
23257 unsigned CombineOpcode = N.getOpcode();
23259 // Walk up a single-use chain looking for a combinable shuffle.
23260 SDValue V = N.getOperand(0);
23261 for (; V.hasOneUse(); V = V.getOperand(0)) {
23262 switch (V.getOpcode()) {
23264 return false; // Nothing combined!
23267 // Skip bitcasts as we always know the type for the target specific
23271 case X86ISD::PSHUFLW:
23272 case X86ISD::PSHUFHW:
23273 if (V.getOpcode() == CombineOpcode)
23276 // Other-half shuffles are no-ops.
23279 // Break out of the loop if we break out of the switch.
23283 if (!V.hasOneUse())
23284 // We fell out of the loop without finding a viable combining instruction.
23287 // Combine away the bottom node as its shuffle will be accumulated into
23288 // a preceding shuffle.
23289 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
23291 // Record the old value.
23294 // Merge this node's mask and our incoming mask (adjusted to account for all
23295 // the pshufd instructions encountered).
23296 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
23297 for (int &M : Mask)
23299 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
23300 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
23302 // Check that the shuffles didn't cancel each other out. If not, we need to
23303 // combine to the new one.
23305 // Replace the combinable shuffle with the combined one, updating all users
23306 // so that we re-evaluate the chain here.
23307 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
23312 /// \brief Try to combine x86 target specific shuffles.
23313 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
23314 TargetLowering::DAGCombinerInfo &DCI,
23315 const X86Subtarget *Subtarget) {
23317 MVT VT = N.getSimpleValueType();
23318 SmallVector<int, 4> Mask;
23320 switch (N.getOpcode()) {
23321 case X86ISD::PSHUFD:
23322 case X86ISD::PSHUFLW:
23323 case X86ISD::PSHUFHW:
23324 Mask = getPSHUFShuffleMask(N);
23325 assert(Mask.size() == 4);
23327 case X86ISD::UNPCKL: {
23328 // Combine X86ISD::UNPCKL and ISD::VECTOR_SHUFFLE into X86ISD::UNPCKH, in
23329 // which X86ISD::UNPCKL has a ISD::UNDEF operand, and ISD::VECTOR_SHUFFLE
23330 // moves upper half elements into the lower half part. For example:
23332 // t2: v16i8 = vector_shuffle<8,9,10,11,12,13,14,15,u,u,u,u,u,u,u,u> t1,
23334 // t3: v16i8 = X86ISD::UNPCKL undef:v16i8, t2
23336 // will be combined to:
23338 // t3: v16i8 = X86ISD::UNPCKH undef:v16i8, t1
23340 // This is only for 128-bit vectors. From SSE4.1 onward this combine may not
23341 // happen due to advanced instructions.
23342 if (!VT.is128BitVector())
23345 auto Op0 = N.getOperand(0);
23346 auto Op1 = N.getOperand(1);
23347 if (Op0.getOpcode() == ISD::UNDEF &&
23348 Op1.getNode()->getOpcode() == ISD::VECTOR_SHUFFLE) {
23349 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Op1.getNode())->getMask();
23351 unsigned NumElts = VT.getVectorNumElements();
23352 SmallVector<int, 8> ExpectedMask(NumElts, -1);
23353 std::iota(ExpectedMask.begin(), ExpectedMask.begin() + NumElts / 2,
23356 auto ShufOp = Op1.getOperand(0);
23357 if (isShuffleEquivalent(Op1, ShufOp, Mask, ExpectedMask))
23358 return DAG.getNode(X86ISD::UNPCKH, DL, VT, N.getOperand(0), ShufOp);
23366 // Nuke no-op shuffles that show up after combining.
23367 if (isNoopShuffleMask(Mask))
23368 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
23370 // Look for simplifications involving one or two shuffle instructions.
23371 SDValue V = N.getOperand(0);
23372 switch (N.getOpcode()) {
23375 case X86ISD::PSHUFLW:
23376 case X86ISD::PSHUFHW:
23377 assert(VT.getVectorElementType() == MVT::i16 && "Bad word shuffle type!");
23379 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
23380 return SDValue(); // We combined away this shuffle, so we're done.
23382 // See if this reduces to a PSHUFD which is no more expensive and can
23383 // combine with more operations. Note that it has to at least flip the
23384 // dwords as otherwise it would have been removed as a no-op.
23385 if (makeArrayRef(Mask).equals({2, 3, 0, 1})) {
23386 int DMask[] = {0, 1, 2, 3};
23387 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
23388 DMask[DOffset + 0] = DOffset + 1;
23389 DMask[DOffset + 1] = DOffset + 0;
23390 MVT DVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
23391 V = DAG.getBitcast(DVT, V);
23392 DCI.AddToWorklist(V.getNode());
23393 V = DAG.getNode(X86ISD::PSHUFD, DL, DVT, V,
23394 getV4X86ShuffleImm8ForMask(DMask, DL, DAG));
23395 DCI.AddToWorklist(V.getNode());
23396 return DAG.getBitcast(VT, V);
23399 // Look for shuffle patterns which can be implemented as a single unpack.
23400 // FIXME: This doesn't handle the location of the PSHUFD generically, and
23401 // only works when we have a PSHUFD followed by two half-shuffles.
23402 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
23403 (V.getOpcode() == X86ISD::PSHUFLW ||
23404 V.getOpcode() == X86ISD::PSHUFHW) &&
23405 V.getOpcode() != N.getOpcode() &&
23407 SDValue D = V.getOperand(0);
23408 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
23409 D = D.getOperand(0);
23410 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
23411 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
23412 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
23413 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
23414 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
23416 for (int i = 0; i < 4; ++i) {
23417 WordMask[i + NOffset] = Mask[i] + NOffset;
23418 WordMask[i + VOffset] = VMask[i] + VOffset;
23420 // Map the word mask through the DWord mask.
23422 for (int i = 0; i < 8; ++i)
23423 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
23424 if (makeArrayRef(MappedMask).equals({0, 0, 1, 1, 2, 2, 3, 3}) ||
23425 makeArrayRef(MappedMask).equals({4, 4, 5, 5, 6, 6, 7, 7})) {
23426 // We can replace all three shuffles with an unpack.
23427 V = DAG.getBitcast(VT, D.getOperand(0));
23428 DCI.AddToWorklist(V.getNode());
23429 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
23438 case X86ISD::PSHUFD:
23439 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
23448 /// \brief Try to combine a shuffle into a target-specific add-sub node.
23450 /// We combine this directly on the abstract vector shuffle nodes so it is
23451 /// easier to generically match. We also insert dummy vector shuffle nodes for
23452 /// the operands which explicitly discard the lanes which are unused by this
23453 /// operation to try to flow through the rest of the combiner the fact that
23454 /// they're unused.
23455 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
23457 EVT VT = N->getValueType(0);
23459 // We only handle target-independent shuffles.
23460 // FIXME: It would be easy and harmless to use the target shuffle mask
23461 // extraction tool to support more.
23462 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
23465 auto *SVN = cast<ShuffleVectorSDNode>(N);
23466 SmallVector<int, 8> Mask;
23467 for (int M : SVN->getMask())
23470 SDValue V1 = N->getOperand(0);
23471 SDValue V2 = N->getOperand(1);
23473 // We require the first shuffle operand to be the FSUB node, and the second to
23474 // be the FADD node.
23475 if (V1.getOpcode() == ISD::FADD && V2.getOpcode() == ISD::FSUB) {
23476 ShuffleVectorSDNode::commuteMask(Mask);
23478 } else if (V1.getOpcode() != ISD::FSUB || V2.getOpcode() != ISD::FADD)
23481 // If there are other uses of these operations we can't fold them.
23482 if (!V1->hasOneUse() || !V2->hasOneUse())
23485 // Ensure that both operations have the same operands. Note that we can
23486 // commute the FADD operands.
23487 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
23488 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
23489 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
23492 // We're looking for blends between FADD and FSUB nodes. We insist on these
23493 // nodes being lined up in a specific expected pattern.
23494 if (!(isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
23495 isShuffleEquivalent(V1, V2, Mask, {0, 5, 2, 7}) ||
23496 isShuffleEquivalent(V1, V2, Mask, {0, 9, 2, 11, 4, 13, 6, 15})))
23499 // Only specific types are legal at this point, assert so we notice if and
23500 // when these change.
23501 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
23502 VT == MVT::v4f64) &&
23503 "Unknown vector type encountered!");
23505 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
23508 /// PerformShuffleCombine - Performs several different shuffle combines.
23509 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
23510 TargetLowering::DAGCombinerInfo &DCI,
23511 const X86Subtarget *Subtarget) {
23513 SDValue N0 = N->getOperand(0);
23514 SDValue N1 = N->getOperand(1);
23515 EVT VT = N->getValueType(0);
23517 // Don't create instructions with illegal types after legalize types has run.
23518 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23519 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
23522 // If we have legalized the vector types, look for blends of FADD and FSUB
23523 // nodes that we can fuse into an ADDSUB node.
23524 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
23525 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
23528 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
23529 if (TLI.isTypeLegal(VT) && Subtarget->hasFp256() && VT.is256BitVector() &&
23530 N->getOpcode() == ISD::VECTOR_SHUFFLE)
23531 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
23533 // During Type Legalization, when promoting illegal vector types,
23534 // the backend might introduce new shuffle dag nodes and bitcasts.
23536 // This code performs the following transformation:
23537 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
23538 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
23540 // We do this only if both the bitcast and the BINOP dag nodes have
23541 // one use. Also, perform this transformation only if the new binary
23542 // operation is legal. This is to avoid introducing dag nodes that
23543 // potentially need to be further expanded (or custom lowered) into a
23544 // less optimal sequence of dag nodes.
23545 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
23546 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
23547 N0.getOpcode() == ISD::BITCAST) {
23548 SDValue BC0 = N0.getOperand(0);
23549 EVT SVT = BC0.getValueType();
23550 unsigned Opcode = BC0.getOpcode();
23551 unsigned NumElts = VT.getVectorNumElements();
23553 if (BC0.hasOneUse() && SVT.isVector() &&
23554 SVT.getVectorNumElements() * 2 == NumElts &&
23555 TLI.isOperationLegal(Opcode, VT)) {
23556 bool CanFold = false;
23568 unsigned SVTNumElts = SVT.getVectorNumElements();
23569 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
23570 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
23571 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
23572 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
23573 CanFold = SVOp->getMaskElt(i) < 0;
23576 SDValue BC00 = DAG.getBitcast(VT, BC0.getOperand(0));
23577 SDValue BC01 = DAG.getBitcast(VT, BC0.getOperand(1));
23578 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
23579 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
23584 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
23585 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
23586 // consecutive, non-overlapping, and in the right order.
23587 SmallVector<SDValue, 16> Elts;
23588 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
23589 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
23591 if (SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true))
23594 if (isTargetShuffle(N->getOpcode())) {
23596 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
23597 if (Shuffle.getNode())
23600 // Try recursively combining arbitrary sequences of x86 shuffle
23601 // instructions into higher-order shuffles. We do this after combining
23602 // specific PSHUF instruction sequences into their minimal form so that we
23603 // can evaluate how many specialized shuffle instructions are involved in
23604 // a particular chain.
23605 SmallVector<int, 1> NonceMask; // Just a placeholder.
23606 NonceMask.push_back(0);
23607 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
23608 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
23610 return SDValue(); // This routine will use CombineTo to replace N.
23616 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
23617 /// specific shuffle of a load can be folded into a single element load.
23618 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
23619 /// shuffles have been custom lowered so we need to handle those here.
23620 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
23621 TargetLowering::DAGCombinerInfo &DCI) {
23622 if (DCI.isBeforeLegalizeOps())
23625 SDValue InVec = N->getOperand(0);
23626 SDValue EltNo = N->getOperand(1);
23628 if (!isa<ConstantSDNode>(EltNo))
23631 EVT OriginalVT = InVec.getValueType();
23633 if (InVec.getOpcode() == ISD::BITCAST) {
23634 // Don't duplicate a load with other uses.
23635 if (!InVec.hasOneUse())
23637 EVT BCVT = InVec.getOperand(0).getValueType();
23638 if (!BCVT.isVector() ||
23639 BCVT.getVectorNumElements() != OriginalVT.getVectorNumElements())
23641 InVec = InVec.getOperand(0);
23644 EVT CurrentVT = InVec.getValueType();
23646 if (!isTargetShuffle(InVec.getOpcode()))
23649 // Don't duplicate a load with other uses.
23650 if (!InVec.hasOneUse())
23653 SmallVector<int, 16> ShuffleMask;
23655 if (!getTargetShuffleMask(InVec.getNode(), CurrentVT.getSimpleVT(),
23656 ShuffleMask, UnaryShuffle))
23659 // Select the input vector, guarding against out of range extract vector.
23660 unsigned NumElems = CurrentVT.getVectorNumElements();
23661 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
23662 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
23663 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
23664 : InVec.getOperand(1);
23666 // If inputs to shuffle are the same for both ops, then allow 2 uses
23667 unsigned AllowedUses = InVec.getNumOperands() > 1 &&
23668 InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
23670 if (LdNode.getOpcode() == ISD::BITCAST) {
23671 // Don't duplicate a load with other uses.
23672 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
23675 AllowedUses = 1; // only allow 1 load use if we have a bitcast
23676 LdNode = LdNode.getOperand(0);
23679 if (!ISD::isNormalLoad(LdNode.getNode()))
23682 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
23684 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
23687 EVT EltVT = N->getValueType(0);
23688 // If there's a bitcast before the shuffle, check if the load type and
23689 // alignment is valid.
23690 unsigned Align = LN0->getAlignment();
23691 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23692 unsigned NewAlign = DAG.getDataLayout().getABITypeAlignment(
23693 EltVT.getTypeForEVT(*DAG.getContext()));
23695 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
23698 // All checks match so transform back to vector_shuffle so that DAG combiner
23699 // can finish the job
23702 // Create shuffle node taking into account the case that its a unary shuffle
23703 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(CurrentVT)
23704 : InVec.getOperand(1);
23705 Shuffle = DAG.getVectorShuffle(CurrentVT, dl,
23706 InVec.getOperand(0), Shuffle,
23708 Shuffle = DAG.getBitcast(OriginalVT, Shuffle);
23709 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
23713 static SDValue PerformBITCASTCombine(SDNode *N, SelectionDAG &DAG,
23714 const X86Subtarget *Subtarget) {
23715 SDValue N0 = N->getOperand(0);
23716 EVT VT = N->getValueType(0);
23718 // Detect bitcasts between i32 to x86mmx low word. Since MMX types are
23719 // special and don't usually play with other vector types, it's better to
23720 // handle them early to be sure we emit efficient code by avoiding
23721 // store-load conversions.
23722 if (VT == MVT::x86mmx && N0.getOpcode() == ISD::BUILD_VECTOR &&
23723 N0.getValueType() == MVT::v2i32 &&
23724 isNullConstant(N0.getOperand(1))) {
23725 SDValue N00 = N0->getOperand(0);
23726 if (N00.getValueType() == MVT::i32)
23727 return DAG.getNode(X86ISD::MMX_MOVW2D, SDLoc(N00), VT, N00);
23730 // Convert a bitcasted integer logic operation that has one bitcasted
23731 // floating-point operand and one constant operand into a floating-point
23732 // logic operation. This may create a load of the constant, but that is
23733 // cheaper than materializing the constant in an integer register and
23734 // transferring it to an SSE register or transferring the SSE operand to
23735 // integer register and back.
23737 switch (N0.getOpcode()) {
23738 case ISD::AND: FPOpcode = X86ISD::FAND; break;
23739 case ISD::OR: FPOpcode = X86ISD::FOR; break;
23740 case ISD::XOR: FPOpcode = X86ISD::FXOR; break;
23741 default: return SDValue();
23743 if (((Subtarget->hasSSE1() && VT == MVT::f32) ||
23744 (Subtarget->hasSSE2() && VT == MVT::f64)) &&
23745 isa<ConstantSDNode>(N0.getOperand(1)) &&
23746 N0.getOperand(0).getOpcode() == ISD::BITCAST &&
23747 N0.getOperand(0).getOperand(0).getValueType() == VT) {
23748 SDValue N000 = N0.getOperand(0).getOperand(0);
23749 SDValue FPConst = DAG.getBitcast(VT, N0.getOperand(1));
23750 return DAG.getNode(FPOpcode, SDLoc(N0), VT, N000, FPConst);
23756 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
23757 /// generation and convert it from being a bunch of shuffles and extracts
23758 /// into a somewhat faster sequence. For i686, the best sequence is apparently
23759 /// storing the value and loading scalars back, while for x64 we should
23760 /// use 64-bit extracts and shifts.
23761 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
23762 TargetLowering::DAGCombinerInfo &DCI) {
23763 if (SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI))
23766 SDValue InputVector = N->getOperand(0);
23767 SDLoc dl(InputVector);
23768 // Detect mmx to i32 conversion through a v2i32 elt extract.
23769 if (InputVector.getOpcode() == ISD::BITCAST && InputVector.hasOneUse() &&
23770 N->getValueType(0) == MVT::i32 &&
23771 InputVector.getValueType() == MVT::v2i32) {
23773 // The bitcast source is a direct mmx result.
23774 SDValue MMXSrc = InputVector.getNode()->getOperand(0);
23775 if (MMXSrc.getValueType() == MVT::x86mmx)
23776 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
23777 N->getValueType(0),
23778 InputVector.getNode()->getOperand(0));
23780 // The mmx is indirect: (i64 extract_elt (v1i64 bitcast (x86mmx ...))).
23781 if (MMXSrc.getOpcode() == ISD::EXTRACT_VECTOR_ELT && MMXSrc.hasOneUse() &&
23782 MMXSrc.getValueType() == MVT::i64) {
23783 SDValue MMXSrcOp = MMXSrc.getOperand(0);
23784 if (MMXSrcOp.hasOneUse() && MMXSrcOp.getOpcode() == ISD::BITCAST &&
23785 MMXSrcOp.getValueType() == MVT::v1i64 &&
23786 MMXSrcOp.getOperand(0).getValueType() == MVT::x86mmx)
23787 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
23788 N->getValueType(0), MMXSrcOp.getOperand(0));
23792 EVT VT = N->getValueType(0);
23794 if (VT == MVT::i1 && isa<ConstantSDNode>(N->getOperand(1)) &&
23795 InputVector.getOpcode() == ISD::BITCAST &&
23796 isa<ConstantSDNode>(InputVector.getOperand(0))) {
23797 uint64_t ExtractedElt =
23798 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
23799 uint64_t InputValue =
23800 cast<ConstantSDNode>(InputVector.getOperand(0))->getZExtValue();
23801 uint64_t Res = (InputValue >> ExtractedElt) & 1;
23802 return DAG.getConstant(Res, dl, MVT::i1);
23804 // Only operate on vectors of 4 elements, where the alternative shuffling
23805 // gets to be more expensive.
23806 if (InputVector.getValueType() != MVT::v4i32)
23809 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
23810 // single use which is a sign-extend or zero-extend, and all elements are
23812 SmallVector<SDNode *, 4> Uses;
23813 unsigned ExtractedElements = 0;
23814 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
23815 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
23816 if (UI.getUse().getResNo() != InputVector.getResNo())
23819 SDNode *Extract = *UI;
23820 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
23823 if (Extract->getValueType(0) != MVT::i32)
23825 if (!Extract->hasOneUse())
23827 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
23828 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
23830 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
23833 // Record which element was extracted.
23834 ExtractedElements |=
23835 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
23837 Uses.push_back(Extract);
23840 // If not all the elements were used, this may not be worthwhile.
23841 if (ExtractedElements != 15)
23844 // Ok, we've now decided to do the transformation.
23845 // If 64-bit shifts are legal, use the extract-shift sequence,
23846 // otherwise bounce the vector off the cache.
23847 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23850 if (TLI.isOperationLegal(ISD::SRA, MVT::i64)) {
23851 SDValue Cst = DAG.getBitcast(MVT::v2i64, InputVector);
23852 auto &DL = DAG.getDataLayout();
23853 EVT VecIdxTy = DAG.getTargetLoweringInfo().getVectorIdxTy(DL);
23854 SDValue BottomHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
23855 DAG.getConstant(0, dl, VecIdxTy));
23856 SDValue TopHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
23857 DAG.getConstant(1, dl, VecIdxTy));
23859 SDValue ShAmt = DAG.getConstant(
23860 32, dl, DAG.getTargetLoweringInfo().getShiftAmountTy(MVT::i64, DL));
23861 Vals[0] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BottomHalf);
23862 Vals[1] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
23863 DAG.getNode(ISD::SRA, dl, MVT::i64, BottomHalf, ShAmt));
23864 Vals[2] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, TopHalf);
23865 Vals[3] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
23866 DAG.getNode(ISD::SRA, dl, MVT::i64, TopHalf, ShAmt));
23868 // Store the value to a temporary stack slot.
23869 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
23870 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
23871 MachinePointerInfo(), false, false, 0);
23873 EVT ElementType = InputVector.getValueType().getVectorElementType();
23874 unsigned EltSize = ElementType.getSizeInBits() / 8;
23876 // Replace each use (extract) with a load of the appropriate element.
23877 for (unsigned i = 0; i < 4; ++i) {
23878 uint64_t Offset = EltSize * i;
23879 auto PtrVT = TLI.getPointerTy(DAG.getDataLayout());
23880 SDValue OffsetVal = DAG.getConstant(Offset, dl, PtrVT);
23882 SDValue ScalarAddr =
23883 DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, OffsetVal);
23885 // Load the scalar.
23886 Vals[i] = DAG.getLoad(ElementType, dl, Ch,
23887 ScalarAddr, MachinePointerInfo(),
23888 false, false, false, 0);
23893 // Replace the extracts
23894 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
23895 UE = Uses.end(); UI != UE; ++UI) {
23896 SDNode *Extract = *UI;
23898 SDValue Idx = Extract->getOperand(1);
23899 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
23900 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), Vals[IdxVal]);
23903 // The replacement was made in place; don't return anything.
23908 transformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
23909 const X86Subtarget *Subtarget) {
23911 SDValue Cond = N->getOperand(0);
23912 SDValue LHS = N->getOperand(1);
23913 SDValue RHS = N->getOperand(2);
23915 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
23916 SDValue CondSrc = Cond->getOperand(0);
23917 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
23918 Cond = CondSrc->getOperand(0);
23921 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
23924 // A vselect where all conditions and data are constants can be optimized into
23925 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
23926 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
23927 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
23930 unsigned MaskValue = 0;
23931 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
23934 MVT VT = N->getSimpleValueType(0);
23935 unsigned NumElems = VT.getVectorNumElements();
23936 SmallVector<int, 8> ShuffleMask(NumElems, -1);
23937 for (unsigned i = 0; i < NumElems; ++i) {
23938 // Be sure we emit undef where we can.
23939 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
23940 ShuffleMask[i] = -1;
23942 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
23945 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23946 if (!TLI.isShuffleMaskLegal(ShuffleMask, VT))
23948 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
23951 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
23953 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
23954 TargetLowering::DAGCombinerInfo &DCI,
23955 const X86Subtarget *Subtarget) {
23957 SDValue Cond = N->getOperand(0);
23958 // Get the LHS/RHS of the select.
23959 SDValue LHS = N->getOperand(1);
23960 SDValue RHS = N->getOperand(2);
23961 EVT VT = LHS.getValueType();
23962 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23964 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
23965 // instructions match the semantics of the common C idiom x<y?x:y but not
23966 // x<=y?x:y, because of how they handle negative zero (which can be
23967 // ignored in unsafe-math mode).
23968 // We also try to create v2f32 min/max nodes, which we later widen to v4f32.
23969 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
23970 VT != MVT::f80 && VT != MVT::f128 &&
23971 (TLI.isTypeLegal(VT) || VT == MVT::v2f32) &&
23972 (Subtarget->hasSSE2() ||
23973 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
23974 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23976 unsigned Opcode = 0;
23977 // Check for x CC y ? x : y.
23978 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
23979 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
23983 // Converting this to a min would handle NaNs incorrectly, and swapping
23984 // the operands would cause it to handle comparisons between positive
23985 // and negative zero incorrectly.
23986 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
23987 if (!DAG.getTarget().Options.UnsafeFPMath &&
23988 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
23990 std::swap(LHS, RHS);
23992 Opcode = X86ISD::FMIN;
23995 // Converting this to a min would handle comparisons between positive
23996 // and negative zero incorrectly.
23997 if (!DAG.getTarget().Options.UnsafeFPMath &&
23998 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
24000 Opcode = X86ISD::FMIN;
24003 // Converting this to a min would handle both negative zeros and NaNs
24004 // incorrectly, but we can swap the operands to fix both.
24005 std::swap(LHS, RHS);
24009 Opcode = X86ISD::FMIN;
24013 // Converting this to a max would handle comparisons between positive
24014 // and negative zero incorrectly.
24015 if (!DAG.getTarget().Options.UnsafeFPMath &&
24016 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
24018 Opcode = X86ISD::FMAX;
24021 // Converting this to a max would handle NaNs incorrectly, and swapping
24022 // the operands would cause it to handle comparisons between positive
24023 // and negative zero incorrectly.
24024 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
24025 if (!DAG.getTarget().Options.UnsafeFPMath &&
24026 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
24028 std::swap(LHS, RHS);
24030 Opcode = X86ISD::FMAX;
24033 // Converting this to a max would handle both negative zeros and NaNs
24034 // incorrectly, but we can swap the operands to fix both.
24035 std::swap(LHS, RHS);
24039 Opcode = X86ISD::FMAX;
24042 // Check for x CC y ? y : x -- a min/max with reversed arms.
24043 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
24044 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
24048 // Converting this to a min would handle comparisons between positive
24049 // and negative zero incorrectly, and swapping the operands would
24050 // cause it to handle NaNs incorrectly.
24051 if (!DAG.getTarget().Options.UnsafeFPMath &&
24052 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
24053 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
24055 std::swap(LHS, RHS);
24057 Opcode = X86ISD::FMIN;
24060 // Converting this to a min would handle NaNs incorrectly.
24061 if (!DAG.getTarget().Options.UnsafeFPMath &&
24062 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
24064 Opcode = X86ISD::FMIN;
24067 // Converting this to a min would handle both negative zeros and NaNs
24068 // incorrectly, but we can swap the operands to fix both.
24069 std::swap(LHS, RHS);
24073 Opcode = X86ISD::FMIN;
24077 // Converting this to a max would handle NaNs incorrectly.
24078 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
24080 Opcode = X86ISD::FMAX;
24083 // Converting this to a max would handle comparisons between positive
24084 // and negative zero incorrectly, and swapping the operands would
24085 // cause it to handle NaNs incorrectly.
24086 if (!DAG.getTarget().Options.UnsafeFPMath &&
24087 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
24088 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
24090 std::swap(LHS, RHS);
24092 Opcode = X86ISD::FMAX;
24095 // Converting this to a max would handle both negative zeros and NaNs
24096 // incorrectly, but we can swap the operands to fix both.
24097 std::swap(LHS, RHS);
24101 Opcode = X86ISD::FMAX;
24107 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
24110 EVT CondVT = Cond.getValueType();
24111 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
24112 CondVT.getVectorElementType() == MVT::i1) {
24113 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
24114 // lowering on KNL. In this case we convert it to
24115 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
24116 // The same situation for all 128 and 256-bit vectors of i8 and i16.
24117 // Since SKX these selects have a proper lowering.
24118 EVT OpVT = LHS.getValueType();
24119 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
24120 (OpVT.getVectorElementType() == MVT::i8 ||
24121 OpVT.getVectorElementType() == MVT::i16) &&
24122 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
24123 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
24124 DCI.AddToWorklist(Cond.getNode());
24125 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
24128 // If this is a select between two integer constants, try to do some
24130 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
24131 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
24132 // Don't do this for crazy integer types.
24133 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
24134 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
24135 // so that TrueC (the true value) is larger than FalseC.
24136 bool NeedsCondInvert = false;
24138 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
24139 // Efficiently invertible.
24140 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
24141 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
24142 isa<ConstantSDNode>(Cond.getOperand(1))))) {
24143 NeedsCondInvert = true;
24144 std::swap(TrueC, FalseC);
24147 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
24148 if (FalseC->getAPIntValue() == 0 &&
24149 TrueC->getAPIntValue().isPowerOf2()) {
24150 if (NeedsCondInvert) // Invert the condition if needed.
24151 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
24152 DAG.getConstant(1, DL, Cond.getValueType()));
24154 // Zero extend the condition if needed.
24155 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
24157 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
24158 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
24159 DAG.getConstant(ShAmt, DL, MVT::i8));
24162 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
24163 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
24164 if (NeedsCondInvert) // Invert the condition if needed.
24165 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
24166 DAG.getConstant(1, DL, Cond.getValueType()));
24168 // Zero extend the condition if needed.
24169 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
24170 FalseC->getValueType(0), Cond);
24171 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
24172 SDValue(FalseC, 0));
24175 // Optimize cases that will turn into an LEA instruction. This requires
24176 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
24177 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
24178 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
24179 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
24181 bool isFastMultiplier = false;
24183 switch ((unsigned char)Diff) {
24185 case 1: // result = add base, cond
24186 case 2: // result = lea base( , cond*2)
24187 case 3: // result = lea base(cond, cond*2)
24188 case 4: // result = lea base( , cond*4)
24189 case 5: // result = lea base(cond, cond*4)
24190 case 8: // result = lea base( , cond*8)
24191 case 9: // result = lea base(cond, cond*8)
24192 isFastMultiplier = true;
24197 if (isFastMultiplier) {
24198 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
24199 if (NeedsCondInvert) // Invert the condition if needed.
24200 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
24201 DAG.getConstant(1, DL, Cond.getValueType()));
24203 // Zero extend the condition if needed.
24204 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
24206 // Scale the condition by the difference.
24208 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
24209 DAG.getConstant(Diff, DL,
24210 Cond.getValueType()));
24212 // Add the base if non-zero.
24213 if (FalseC->getAPIntValue() != 0)
24214 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
24215 SDValue(FalseC, 0));
24222 // Canonicalize max and min:
24223 // (x > y) ? x : y -> (x >= y) ? x : y
24224 // (x < y) ? x : y -> (x <= y) ? x : y
24225 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
24226 // the need for an extra compare
24227 // against zero. e.g.
24228 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
24230 // testl %edi, %edi
24232 // cmovgl %edi, %eax
24236 // cmovsl %eax, %edi
24237 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
24238 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
24239 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
24240 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
24245 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
24246 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
24247 Cond.getOperand(0), Cond.getOperand(1), NewCC);
24248 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
24253 // Early exit check
24254 if (!TLI.isTypeLegal(VT))
24257 // Match VSELECTs into subs with unsigned saturation.
24258 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
24259 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
24260 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
24261 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
24262 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
24264 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
24265 // left side invert the predicate to simplify logic below.
24267 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
24269 CC = ISD::getSetCCInverse(CC, true);
24270 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
24274 if (Other.getNode() && Other->getNumOperands() == 2 &&
24275 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
24276 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
24277 SDValue CondRHS = Cond->getOperand(1);
24279 // Look for a general sub with unsigned saturation first.
24280 // x >= y ? x-y : 0 --> subus x, y
24281 // x > y ? x-y : 0 --> subus x, y
24282 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
24283 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
24284 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
24286 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
24287 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
24288 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
24289 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
24290 // If the RHS is a constant we have to reverse the const
24291 // canonicalization.
24292 // x > C-1 ? x+-C : 0 --> subus x, C
24293 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
24294 CondRHSConst->getAPIntValue() ==
24295 (-OpRHSConst->getAPIntValue() - 1))
24296 return DAG.getNode(
24297 X86ISD::SUBUS, DL, VT, OpLHS,
24298 DAG.getConstant(-OpRHSConst->getAPIntValue(), DL, VT));
24300 // Another special case: If C was a sign bit, the sub has been
24301 // canonicalized into a xor.
24302 // FIXME: Would it be better to use computeKnownBits to determine
24303 // whether it's safe to decanonicalize the xor?
24304 // x s< 0 ? x^C : 0 --> subus x, C
24305 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
24306 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
24307 OpRHSConst->getAPIntValue().isSignBit())
24308 // Note that we have to rebuild the RHS constant here to ensure we
24309 // don't rely on particular values of undef lanes.
24310 return DAG.getNode(
24311 X86ISD::SUBUS, DL, VT, OpLHS,
24312 DAG.getConstant(OpRHSConst->getAPIntValue(), DL, VT));
24317 // Simplify vector selection if condition value type matches vselect
24319 if (N->getOpcode() == ISD::VSELECT && CondVT == VT) {
24320 assert(Cond.getValueType().isVector() &&
24321 "vector select expects a vector selector!");
24323 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
24324 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
24326 // Try invert the condition if true value is not all 1s and false value
24328 if (!TValIsAllOnes && !FValIsAllZeros &&
24329 // Check if the selector will be produced by CMPP*/PCMP*
24330 Cond.getOpcode() == ISD::SETCC &&
24331 // Check if SETCC has already been promoted
24332 TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT) ==
24334 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
24335 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
24337 if (TValIsAllZeros || FValIsAllOnes) {
24338 SDValue CC = Cond.getOperand(2);
24339 ISD::CondCode NewCC =
24340 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
24341 Cond.getOperand(0).getValueType().isInteger());
24342 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
24343 std::swap(LHS, RHS);
24344 TValIsAllOnes = FValIsAllOnes;
24345 FValIsAllZeros = TValIsAllZeros;
24349 if (TValIsAllOnes || FValIsAllZeros) {
24352 if (TValIsAllOnes && FValIsAllZeros)
24354 else if (TValIsAllOnes)
24356 DAG.getNode(ISD::OR, DL, CondVT, Cond, DAG.getBitcast(CondVT, RHS));
24357 else if (FValIsAllZeros)
24358 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
24359 DAG.getBitcast(CondVT, LHS));
24361 return DAG.getBitcast(VT, Ret);
24365 // We should generate an X86ISD::BLENDI from a vselect if its argument
24366 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
24367 // constants. This specific pattern gets generated when we split a
24368 // selector for a 512 bit vector in a machine without AVX512 (but with
24369 // 256-bit vectors), during legalization:
24371 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
24373 // Iff we find this pattern and the build_vectors are built from
24374 // constants, we translate the vselect into a shuffle_vector that we
24375 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
24376 if ((N->getOpcode() == ISD::VSELECT ||
24377 N->getOpcode() == X86ISD::SHRUNKBLEND) &&
24378 !DCI.isBeforeLegalize() && !VT.is512BitVector()) {
24379 SDValue Shuffle = transformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
24380 if (Shuffle.getNode())
24384 // If this is a *dynamic* select (non-constant condition) and we can match
24385 // this node with one of the variable blend instructions, restructure the
24386 // condition so that the blends can use the high bit of each element and use
24387 // SimplifyDemandedBits to simplify the condition operand.
24388 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
24389 !DCI.isBeforeLegalize() &&
24390 !ISD::isBuildVectorOfConstantSDNodes(Cond.getNode())) {
24391 unsigned BitWidth = Cond.getValueType().getScalarSizeInBits();
24393 // Don't optimize vector selects that map to mask-registers.
24397 // We can only handle the cases where VSELECT is directly legal on the
24398 // subtarget. We custom lower VSELECT nodes with constant conditions and
24399 // this makes it hard to see whether a dynamic VSELECT will correctly
24400 // lower, so we both check the operation's status and explicitly handle the
24401 // cases where a *dynamic* blend will fail even though a constant-condition
24402 // blend could be custom lowered.
24403 // FIXME: We should find a better way to handle this class of problems.
24404 // Potentially, we should combine constant-condition vselect nodes
24405 // pre-legalization into shuffles and not mark as many types as custom
24407 if (!TLI.isOperationLegalOrCustom(ISD::VSELECT, VT))
24409 // FIXME: We don't support i16-element blends currently. We could and
24410 // should support them by making *all* the bits in the condition be set
24411 // rather than just the high bit and using an i8-element blend.
24412 if (VT.getVectorElementType() == MVT::i16)
24414 // Dynamic blending was only available from SSE4.1 onward.
24415 if (VT.is128BitVector() && !Subtarget->hasSSE41())
24417 // Byte blends are only available in AVX2
24418 if (VT == MVT::v32i8 && !Subtarget->hasAVX2())
24421 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
24422 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
24424 APInt KnownZero, KnownOne;
24425 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
24426 DCI.isBeforeLegalizeOps());
24427 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
24428 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne,
24430 // If we changed the computation somewhere in the DAG, this change
24431 // will affect all users of Cond.
24432 // Make sure it is fine and update all the nodes so that we do not
24433 // use the generic VSELECT anymore. Otherwise, we may perform
24434 // wrong optimizations as we messed up with the actual expectation
24435 // for the vector boolean values.
24436 if (Cond != TLO.Old) {
24437 // Check all uses of that condition operand to check whether it will be
24438 // consumed by non-BLEND instructions, which may depend on all bits are
24440 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
24442 if (I->getOpcode() != ISD::VSELECT)
24443 // TODO: Add other opcodes eventually lowered into BLEND.
24446 // Update all the users of the condition, before committing the change,
24447 // so that the VSELECT optimizations that expect the correct vector
24448 // boolean value will not be triggered.
24449 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
24451 DAG.ReplaceAllUsesOfValueWith(
24453 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(*I), I->getValueType(0),
24454 Cond, I->getOperand(1), I->getOperand(2)));
24455 DCI.CommitTargetLoweringOpt(TLO);
24458 // At this point, only Cond is changed. Change the condition
24459 // just for N to keep the opportunity to optimize all other
24460 // users their own way.
24461 DAG.ReplaceAllUsesOfValueWith(
24463 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(N), N->getValueType(0),
24464 TLO.New, N->getOperand(1), N->getOperand(2)));
24472 // Check whether a boolean test is testing a boolean value generated by
24473 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
24476 // Simplify the following patterns:
24477 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
24478 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
24479 // to (Op EFLAGS Cond)
24481 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
24482 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
24483 // to (Op EFLAGS !Cond)
24485 // where Op could be BRCOND or CMOV.
24487 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
24488 // Quit if not CMP and SUB with its value result used.
24489 if (Cmp.getOpcode() != X86ISD::CMP &&
24490 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
24493 // Quit if not used as a boolean value.
24494 if (CC != X86::COND_E && CC != X86::COND_NE)
24497 // Check CMP operands. One of them should be 0 or 1 and the other should be
24498 // an SetCC or extended from it.
24499 SDValue Op1 = Cmp.getOperand(0);
24500 SDValue Op2 = Cmp.getOperand(1);
24503 const ConstantSDNode* C = nullptr;
24504 bool needOppositeCond = (CC == X86::COND_E);
24505 bool checkAgainstTrue = false; // Is it a comparison against 1?
24507 if ((C = dyn_cast<ConstantSDNode>(Op1)))
24509 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
24511 else // Quit if all operands are not constants.
24514 if (C->getZExtValue() == 1) {
24515 needOppositeCond = !needOppositeCond;
24516 checkAgainstTrue = true;
24517 } else if (C->getZExtValue() != 0)
24518 // Quit if the constant is neither 0 or 1.
24521 bool truncatedToBoolWithAnd = false;
24522 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
24523 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
24524 SetCC.getOpcode() == ISD::TRUNCATE ||
24525 SetCC.getOpcode() == ISD::AND) {
24526 if (SetCC.getOpcode() == ISD::AND) {
24528 if (isOneConstant(SetCC.getOperand(0)))
24530 if (isOneConstant(SetCC.getOperand(1)))
24534 SetCC = SetCC.getOperand(OpIdx);
24535 truncatedToBoolWithAnd = true;
24537 SetCC = SetCC.getOperand(0);
24540 switch (SetCC.getOpcode()) {
24541 case X86ISD::SETCC_CARRY:
24542 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
24543 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
24544 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
24545 // truncated to i1 using 'and'.
24546 if (checkAgainstTrue && !truncatedToBoolWithAnd)
24548 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
24549 "Invalid use of SETCC_CARRY!");
24551 case X86ISD::SETCC:
24552 // Set the condition code or opposite one if necessary.
24553 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
24554 if (needOppositeCond)
24555 CC = X86::GetOppositeBranchCondition(CC);
24556 return SetCC.getOperand(1);
24557 case X86ISD::CMOV: {
24558 // Check whether false/true value has canonical one, i.e. 0 or 1.
24559 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
24560 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
24561 // Quit if true value is not a constant.
24564 // Quit if false value is not a constant.
24566 SDValue Op = SetCC.getOperand(0);
24567 // Skip 'zext' or 'trunc' node.
24568 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
24569 Op.getOpcode() == ISD::TRUNCATE)
24570 Op = Op.getOperand(0);
24571 // A special case for rdrand/rdseed, where 0 is set if false cond is
24573 if ((Op.getOpcode() != X86ISD::RDRAND &&
24574 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
24577 // Quit if false value is not the constant 0 or 1.
24578 bool FValIsFalse = true;
24579 if (FVal && FVal->getZExtValue() != 0) {
24580 if (FVal->getZExtValue() != 1)
24582 // If FVal is 1, opposite cond is needed.
24583 needOppositeCond = !needOppositeCond;
24584 FValIsFalse = false;
24586 // Quit if TVal is not the constant opposite of FVal.
24587 if (FValIsFalse && TVal->getZExtValue() != 1)
24589 if (!FValIsFalse && TVal->getZExtValue() != 0)
24591 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
24592 if (needOppositeCond)
24593 CC = X86::GetOppositeBranchCondition(CC);
24594 return SetCC.getOperand(3);
24601 /// Check whether Cond is an AND/OR of SETCCs off of the same EFLAGS.
24603 /// (X86or (X86setcc) (X86setcc))
24604 /// (X86cmp (and (X86setcc) (X86setcc)), 0)
24605 static bool checkBoolTestAndOrSetCCCombine(SDValue Cond, X86::CondCode &CC0,
24606 X86::CondCode &CC1, SDValue &Flags,
24608 if (Cond->getOpcode() == X86ISD::CMP) {
24609 if (!isNullConstant(Cond->getOperand(1)))
24612 Cond = Cond->getOperand(0);
24617 SDValue SetCC0, SetCC1;
24618 switch (Cond->getOpcode()) {
24619 default: return false;
24626 SetCC0 = Cond->getOperand(0);
24627 SetCC1 = Cond->getOperand(1);
24631 // Make sure we have SETCC nodes, using the same flags value.
24632 if (SetCC0.getOpcode() != X86ISD::SETCC ||
24633 SetCC1.getOpcode() != X86ISD::SETCC ||
24634 SetCC0->getOperand(1) != SetCC1->getOperand(1))
24637 CC0 = (X86::CondCode)SetCC0->getConstantOperandVal(0);
24638 CC1 = (X86::CondCode)SetCC1->getConstantOperandVal(0);
24639 Flags = SetCC0->getOperand(1);
24643 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
24644 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
24645 TargetLowering::DAGCombinerInfo &DCI,
24646 const X86Subtarget *Subtarget) {
24649 // If the flag operand isn't dead, don't touch this CMOV.
24650 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
24653 SDValue FalseOp = N->getOperand(0);
24654 SDValue TrueOp = N->getOperand(1);
24655 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
24656 SDValue Cond = N->getOperand(3);
24658 if (CC == X86::COND_E || CC == X86::COND_NE) {
24659 switch (Cond.getOpcode()) {
24663 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
24664 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
24665 return (CC == X86::COND_E) ? FalseOp : TrueOp;
24671 Flags = checkBoolTestSetCCCombine(Cond, CC);
24672 if (Flags.getNode() &&
24673 // Extra check as FCMOV only supports a subset of X86 cond.
24674 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
24675 SDValue Ops[] = { FalseOp, TrueOp,
24676 DAG.getConstant(CC, DL, MVT::i8), Flags };
24677 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
24680 // If this is a select between two integer constants, try to do some
24681 // optimizations. Note that the operands are ordered the opposite of SELECT
24683 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
24684 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
24685 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
24686 // larger than FalseC (the false value).
24687 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
24688 CC = X86::GetOppositeBranchCondition(CC);
24689 std::swap(TrueC, FalseC);
24690 std::swap(TrueOp, FalseOp);
24693 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
24694 // This is efficient for any integer data type (including i8/i16) and
24696 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
24697 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
24698 DAG.getConstant(CC, DL, MVT::i8), Cond);
24700 // Zero extend the condition if needed.
24701 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
24703 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
24704 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
24705 DAG.getConstant(ShAmt, DL, MVT::i8));
24706 if (N->getNumValues() == 2) // Dead flag value?
24707 return DCI.CombineTo(N, Cond, SDValue());
24711 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
24712 // for any integer data type, including i8/i16.
24713 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
24714 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
24715 DAG.getConstant(CC, DL, MVT::i8), Cond);
24717 // Zero extend the condition if needed.
24718 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
24719 FalseC->getValueType(0), Cond);
24720 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
24721 SDValue(FalseC, 0));
24723 if (N->getNumValues() == 2) // Dead flag value?
24724 return DCI.CombineTo(N, Cond, SDValue());
24728 // Optimize cases that will turn into an LEA instruction. This requires
24729 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
24730 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
24731 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
24732 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
24734 bool isFastMultiplier = false;
24736 switch ((unsigned char)Diff) {
24738 case 1: // result = add base, cond
24739 case 2: // result = lea base( , cond*2)
24740 case 3: // result = lea base(cond, cond*2)
24741 case 4: // result = lea base( , cond*4)
24742 case 5: // result = lea base(cond, cond*4)
24743 case 8: // result = lea base( , cond*8)
24744 case 9: // result = lea base(cond, cond*8)
24745 isFastMultiplier = true;
24750 if (isFastMultiplier) {
24751 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
24752 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
24753 DAG.getConstant(CC, DL, MVT::i8), Cond);
24754 // Zero extend the condition if needed.
24755 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
24757 // Scale the condition by the difference.
24759 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
24760 DAG.getConstant(Diff, DL, Cond.getValueType()));
24762 // Add the base if non-zero.
24763 if (FalseC->getAPIntValue() != 0)
24764 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
24765 SDValue(FalseC, 0));
24766 if (N->getNumValues() == 2) // Dead flag value?
24767 return DCI.CombineTo(N, Cond, SDValue());
24774 // Handle these cases:
24775 // (select (x != c), e, c) -> select (x != c), e, x),
24776 // (select (x == c), c, e) -> select (x == c), x, e)
24777 // where the c is an integer constant, and the "select" is the combination
24778 // of CMOV and CMP.
24780 // The rationale for this change is that the conditional-move from a constant
24781 // needs two instructions, however, conditional-move from a register needs
24782 // only one instruction.
24784 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
24785 // some instruction-combining opportunities. This opt needs to be
24786 // postponed as late as possible.
24788 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
24789 // the DCI.xxxx conditions are provided to postpone the optimization as
24790 // late as possible.
24792 ConstantSDNode *CmpAgainst = nullptr;
24793 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
24794 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
24795 !isa<ConstantSDNode>(Cond.getOperand(0))) {
24797 if (CC == X86::COND_NE &&
24798 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
24799 CC = X86::GetOppositeBranchCondition(CC);
24800 std::swap(TrueOp, FalseOp);
24803 if (CC == X86::COND_E &&
24804 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
24805 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
24806 DAG.getConstant(CC, DL, MVT::i8), Cond };
24807 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
24812 // Fold and/or of setcc's to double CMOV:
24813 // (CMOV F, T, ((cc1 | cc2) != 0)) -> (CMOV (CMOV F, T, cc1), T, cc2)
24814 // (CMOV F, T, ((cc1 & cc2) != 0)) -> (CMOV (CMOV T, F, !cc1), F, !cc2)
24816 // This combine lets us generate:
24817 // cmovcc1 (jcc1 if we don't have CMOV)
24823 // cmovne (jne if we don't have CMOV)
24824 // When we can't use the CMOV instruction, it might increase branch
24826 // When we can use CMOV, or when there is no mispredict, this improves
24827 // throughput and reduces register pressure.
24829 if (CC == X86::COND_NE) {
24831 X86::CondCode CC0, CC1;
24833 if (checkBoolTestAndOrSetCCCombine(Cond, CC0, CC1, Flags, isAndSetCC)) {
24835 std::swap(FalseOp, TrueOp);
24836 CC0 = X86::GetOppositeBranchCondition(CC0);
24837 CC1 = X86::GetOppositeBranchCondition(CC1);
24840 SDValue LOps[] = {FalseOp, TrueOp, DAG.getConstant(CC0, DL, MVT::i8),
24842 SDValue LCMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), LOps);
24843 SDValue Ops[] = {LCMOV, TrueOp, DAG.getConstant(CC1, DL, MVT::i8), Flags};
24844 SDValue CMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
24845 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SDValue(CMOV.getNode(), 1));
24853 /// PerformMulCombine - Optimize a single multiply with constant into two
24854 /// in order to implement it with two cheaper instructions, e.g.
24855 /// LEA + SHL, LEA + LEA.
24856 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
24857 TargetLowering::DAGCombinerInfo &DCI) {
24858 // An imul is usually smaller than the alternative sequence.
24859 if (DAG.getMachineFunction().getFunction()->optForMinSize())
24862 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
24865 EVT VT = N->getValueType(0);
24866 if (VT != MVT::i64 && VT != MVT::i32)
24869 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
24872 uint64_t MulAmt = C->getZExtValue();
24873 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
24876 uint64_t MulAmt1 = 0;
24877 uint64_t MulAmt2 = 0;
24878 if ((MulAmt % 9) == 0) {
24880 MulAmt2 = MulAmt / 9;
24881 } else if ((MulAmt % 5) == 0) {
24883 MulAmt2 = MulAmt / 5;
24884 } else if ((MulAmt % 3) == 0) {
24886 MulAmt2 = MulAmt / 3;
24892 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
24894 if (isPowerOf2_64(MulAmt2) &&
24895 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
24896 // If second multiplifer is pow2, issue it first. We want the multiply by
24897 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
24899 std::swap(MulAmt1, MulAmt2);
24901 if (isPowerOf2_64(MulAmt1))
24902 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
24903 DAG.getConstant(Log2_64(MulAmt1), DL, MVT::i8));
24905 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
24906 DAG.getConstant(MulAmt1, DL, VT));
24908 if (isPowerOf2_64(MulAmt2))
24909 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
24910 DAG.getConstant(Log2_64(MulAmt2), DL, MVT::i8));
24912 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
24913 DAG.getConstant(MulAmt2, DL, VT));
24917 assert(MulAmt != 0 && MulAmt != (VT == MVT::i64 ? UINT64_MAX : UINT32_MAX)
24918 && "Both cases that could cause potential overflows should have "
24919 "already been handled.");
24920 if (isPowerOf2_64(MulAmt - 1))
24921 // (mul x, 2^N + 1) => (add (shl x, N), x)
24922 NewMul = DAG.getNode(ISD::ADD, DL, VT, N->getOperand(0),
24923 DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
24924 DAG.getConstant(Log2_64(MulAmt - 1), DL,
24927 else if (isPowerOf2_64(MulAmt + 1))
24928 // (mul x, 2^N - 1) => (sub (shl x, N), x)
24929 NewMul = DAG.getNode(ISD::SUB, DL, VT, DAG.getNode(ISD::SHL, DL, VT,
24931 DAG.getConstant(Log2_64(MulAmt + 1),
24932 DL, MVT::i8)), N->getOperand(0));
24936 // Do not add new nodes to DAG combiner worklist.
24937 DCI.CombineTo(N, NewMul, false);
24942 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
24943 SDValue N0 = N->getOperand(0);
24944 SDValue N1 = N->getOperand(1);
24945 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
24946 EVT VT = N0.getValueType();
24948 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
24949 // since the result of setcc_c is all zero's or all ones.
24950 if (VT.isInteger() && !VT.isVector() &&
24951 N1C && N0.getOpcode() == ISD::AND &&
24952 N0.getOperand(1).getOpcode() == ISD::Constant) {
24953 SDValue N00 = N0.getOperand(0);
24954 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
24955 APInt ShAmt = N1C->getAPIntValue();
24956 Mask = Mask.shl(ShAmt);
24957 bool MaskOK = false;
24958 // We can handle cases concerning bit-widening nodes containing setcc_c if
24959 // we carefully interrogate the mask to make sure we are semantics
24961 // The transform is not safe if the result of C1 << C2 exceeds the bitwidth
24962 // of the underlying setcc_c operation if the setcc_c was zero extended.
24963 // Consider the following example:
24964 // zext(setcc_c) -> i32 0x0000FFFF
24965 // c1 -> i32 0x0000FFFF
24966 // c2 -> i32 0x00000001
24967 // (shl (and (setcc_c), c1), c2) -> i32 0x0001FFFE
24968 // (and setcc_c, (c1 << c2)) -> i32 0x0000FFFE
24969 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
24971 } else if (N00.getOpcode() == ISD::SIGN_EXTEND &&
24972 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
24974 } else if ((N00.getOpcode() == ISD::ZERO_EXTEND ||
24975 N00.getOpcode() == ISD::ANY_EXTEND) &&
24976 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
24977 MaskOK = Mask.isIntN(N00.getOperand(0).getValueSizeInBits());
24979 if (MaskOK && Mask != 0) {
24981 return DAG.getNode(ISD::AND, DL, VT, N00, DAG.getConstant(Mask, DL, VT));
24985 // Hardware support for vector shifts is sparse which makes us scalarize the
24986 // vector operations in many cases. Also, on sandybridge ADD is faster than
24988 // (shl V, 1) -> add V,V
24989 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
24990 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
24991 assert(N0.getValueType().isVector() && "Invalid vector shift type");
24992 // We shift all of the values by one. In many cases we do not have
24993 // hardware support for this operation. This is better expressed as an ADD
24995 if (N1SplatC->getAPIntValue() == 1)
24996 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
25002 static SDValue PerformSRACombine(SDNode *N, SelectionDAG &DAG) {
25003 SDValue N0 = N->getOperand(0);
25004 SDValue N1 = N->getOperand(1);
25005 EVT VT = N0.getValueType();
25006 unsigned Size = VT.getSizeInBits();
25008 // fold (ashr (shl, a, [56,48,32,24,16]), SarConst)
25009 // into (shl, (sext (a), [56,48,32,24,16] - SarConst)) or
25010 // into (lshr, (sext (a), SarConst - [56,48,32,24,16]))
25011 // depending on sign of (SarConst - [56,48,32,24,16])
25013 // sexts in X86 are MOVs. The MOVs have the same code size
25014 // as above SHIFTs (only SHIFT on 1 has lower code size).
25015 // However the MOVs have 2 advantages to a SHIFT:
25016 // 1. MOVs can write to a register that differs from source
25017 // 2. MOVs accept memory operands
25019 if (!VT.isInteger() || VT.isVector() || N1.getOpcode() != ISD::Constant ||
25020 N0.getOpcode() != ISD::SHL || !N0.hasOneUse() ||
25021 N0.getOperand(1).getOpcode() != ISD::Constant)
25024 SDValue N00 = N0.getOperand(0);
25025 SDValue N01 = N0.getOperand(1);
25026 APInt ShlConst = (cast<ConstantSDNode>(N01))->getAPIntValue();
25027 APInt SarConst = (cast<ConstantSDNode>(N1))->getAPIntValue();
25028 EVT CVT = N1.getValueType();
25030 if (SarConst.isNegative())
25033 for (MVT SVT : MVT::integer_valuetypes()) {
25034 unsigned ShiftSize = SVT.getSizeInBits();
25035 // skipping types without corresponding sext/zext and
25036 // ShlConst that is not one of [56,48,32,24,16]
25037 if (ShiftSize < 8 || ShiftSize > 64 || ShlConst != Size - ShiftSize)
25041 DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, N00, DAG.getValueType(SVT));
25042 SarConst = SarConst - (Size - ShiftSize);
25045 else if (SarConst.isNegative())
25046 return DAG.getNode(ISD::SHL, DL, VT, NN,
25047 DAG.getConstant(-SarConst, DL, CVT));
25049 return DAG.getNode(ISD::SRA, DL, VT, NN,
25050 DAG.getConstant(SarConst, DL, CVT));
25055 /// \brief Returns a vector of 0s if the node in input is a vector logical
25056 /// shift by a constant amount which is known to be bigger than or equal
25057 /// to the vector element size in bits.
25058 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
25059 const X86Subtarget *Subtarget) {
25060 EVT VT = N->getValueType(0);
25062 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
25063 (!Subtarget->hasInt256() ||
25064 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
25067 SDValue Amt = N->getOperand(1);
25069 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
25070 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
25071 APInt ShiftAmt = AmtSplat->getAPIntValue();
25072 unsigned MaxAmount =
25073 VT.getSimpleVT().getVectorElementType().getSizeInBits();
25075 // SSE2/AVX2 logical shifts always return a vector of 0s
25076 // if the shift amount is bigger than or equal to
25077 // the element size. The constant shift amount will be
25078 // encoded as a 8-bit immediate.
25079 if (ShiftAmt.trunc(8).uge(MaxAmount))
25080 return getZeroVector(VT.getSimpleVT(), Subtarget, DAG, DL);
25086 /// PerformShiftCombine - Combine shifts.
25087 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
25088 TargetLowering::DAGCombinerInfo &DCI,
25089 const X86Subtarget *Subtarget) {
25090 if (N->getOpcode() == ISD::SHL)
25091 if (SDValue V = PerformSHLCombine(N, DAG))
25094 if (N->getOpcode() == ISD::SRA)
25095 if (SDValue V = PerformSRACombine(N, DAG))
25098 // Try to fold this logical shift into a zero vector.
25099 if (N->getOpcode() != ISD::SRA)
25100 if (SDValue V = performShiftToAllZeros(N, DAG, Subtarget))
25106 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
25107 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
25108 // and friends. Likewise for OR -> CMPNEQSS.
25109 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
25110 TargetLowering::DAGCombinerInfo &DCI,
25111 const X86Subtarget *Subtarget) {
25114 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
25115 // we're requiring SSE2 for both.
25116 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
25117 SDValue N0 = N->getOperand(0);
25118 SDValue N1 = N->getOperand(1);
25119 SDValue CMP0 = N0->getOperand(1);
25120 SDValue CMP1 = N1->getOperand(1);
25123 // The SETCCs should both refer to the same CMP.
25124 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
25127 SDValue CMP00 = CMP0->getOperand(0);
25128 SDValue CMP01 = CMP0->getOperand(1);
25129 EVT VT = CMP00.getValueType();
25131 if (VT == MVT::f32 || VT == MVT::f64) {
25132 bool ExpectingFlags = false;
25133 // Check for any users that want flags:
25134 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
25135 !ExpectingFlags && UI != UE; ++UI)
25136 switch (UI->getOpcode()) {
25141 ExpectingFlags = true;
25143 case ISD::CopyToReg:
25144 case ISD::SIGN_EXTEND:
25145 case ISD::ZERO_EXTEND:
25146 case ISD::ANY_EXTEND:
25150 if (!ExpectingFlags) {
25151 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
25152 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
25154 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
25155 X86::CondCode tmp = cc0;
25160 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
25161 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
25162 // FIXME: need symbolic constants for these magic numbers.
25163 // See X86ATTInstPrinter.cpp:printSSECC().
25164 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
25165 if (Subtarget->hasAVX512()) {
25166 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
25168 DAG.getConstant(x86cc, DL, MVT::i8));
25169 if (N->getValueType(0) != MVT::i1)
25170 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
25174 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
25175 CMP00.getValueType(), CMP00, CMP01,
25176 DAG.getConstant(x86cc, DL,
25179 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
25180 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
25182 if (is64BitFP && !Subtarget->is64Bit()) {
25183 // On a 32-bit target, we cannot bitcast the 64-bit float to a
25184 // 64-bit integer, since that's not a legal type. Since
25185 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
25186 // bits, but can do this little dance to extract the lowest 32 bits
25187 // and work with those going forward.
25188 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
25190 SDValue Vector32 = DAG.getBitcast(MVT::v4f32, Vector64);
25191 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
25192 Vector32, DAG.getIntPtrConstant(0, DL));
25196 SDValue OnesOrZeroesI = DAG.getBitcast(IntVT, OnesOrZeroesF);
25197 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
25198 DAG.getConstant(1, DL, IntVT));
25199 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8,
25201 return OneBitOfTruth;
25209 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
25210 /// so it can be folded inside ANDNP.
25211 static bool CanFoldXORWithAllOnes(const SDNode *N) {
25212 EVT VT = N->getValueType(0);
25214 // Match direct AllOnes for 128 and 256-bit vectors
25215 if (ISD::isBuildVectorAllOnes(N))
25218 // Look through a bit convert.
25219 if (N->getOpcode() == ISD::BITCAST)
25220 N = N->getOperand(0).getNode();
25222 // Sometimes the operand may come from a insert_subvector building a 256-bit
25224 if (VT.is256BitVector() &&
25225 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
25226 SDValue V1 = N->getOperand(0);
25227 SDValue V2 = N->getOperand(1);
25229 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
25230 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
25231 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
25232 ISD::isBuildVectorAllOnes(V2.getNode()))
25239 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
25240 // register. In most cases we actually compare or select YMM-sized registers
25241 // and mixing the two types creates horrible code. This method optimizes
25242 // some of the transition sequences.
25243 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
25244 TargetLowering::DAGCombinerInfo &DCI,
25245 const X86Subtarget *Subtarget) {
25246 EVT VT = N->getValueType(0);
25247 if (!VT.is256BitVector())
25250 assert((N->getOpcode() == ISD::ANY_EXTEND ||
25251 N->getOpcode() == ISD::ZERO_EXTEND ||
25252 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
25254 SDValue Narrow = N->getOperand(0);
25255 EVT NarrowVT = Narrow->getValueType(0);
25256 if (!NarrowVT.is128BitVector())
25259 if (Narrow->getOpcode() != ISD::XOR &&
25260 Narrow->getOpcode() != ISD::AND &&
25261 Narrow->getOpcode() != ISD::OR)
25264 SDValue N0 = Narrow->getOperand(0);
25265 SDValue N1 = Narrow->getOperand(1);
25268 // The Left side has to be a trunc.
25269 if (N0.getOpcode() != ISD::TRUNCATE)
25272 // The type of the truncated inputs.
25273 EVT WideVT = N0->getOperand(0)->getValueType(0);
25277 // The right side has to be a 'trunc' or a constant vector.
25278 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
25279 ConstantSDNode *RHSConstSplat = nullptr;
25280 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
25281 RHSConstSplat = RHSBV->getConstantSplatNode();
25282 if (!RHSTrunc && !RHSConstSplat)
25285 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25287 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
25290 // Set N0 and N1 to hold the inputs to the new wide operation.
25291 N0 = N0->getOperand(0);
25292 if (RHSConstSplat) {
25293 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getVectorElementType(),
25294 SDValue(RHSConstSplat, 0));
25295 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
25296 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
25297 } else if (RHSTrunc) {
25298 N1 = N1->getOperand(0);
25301 // Generate the wide operation.
25302 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
25303 unsigned Opcode = N->getOpcode();
25305 case ISD::ANY_EXTEND:
25307 case ISD::ZERO_EXTEND: {
25308 unsigned InBits = NarrowVT.getScalarSizeInBits();
25309 APInt Mask = APInt::getAllOnesValue(InBits);
25310 Mask = Mask.zext(VT.getScalarSizeInBits());
25311 return DAG.getNode(ISD::AND, DL, VT,
25312 Op, DAG.getConstant(Mask, DL, VT));
25314 case ISD::SIGN_EXTEND:
25315 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
25316 Op, DAG.getValueType(NarrowVT));
25318 llvm_unreachable("Unexpected opcode");
25322 static SDValue VectorZextCombine(SDNode *N, SelectionDAG &DAG,
25323 TargetLowering::DAGCombinerInfo &DCI,
25324 const X86Subtarget *Subtarget) {
25325 SDValue N0 = N->getOperand(0);
25326 SDValue N1 = N->getOperand(1);
25329 // A vector zext_in_reg may be represented as a shuffle,
25330 // feeding into a bitcast (this represents anyext) feeding into
25331 // an and with a mask.
25332 // We'd like to try to combine that into a shuffle with zero
25333 // plus a bitcast, removing the and.
25334 if (N0.getOpcode() != ISD::BITCAST ||
25335 N0.getOperand(0).getOpcode() != ISD::VECTOR_SHUFFLE)
25338 // The other side of the AND should be a splat of 2^C, where C
25339 // is the number of bits in the source type.
25340 if (N1.getOpcode() == ISD::BITCAST)
25341 N1 = N1.getOperand(0);
25342 if (N1.getOpcode() != ISD::BUILD_VECTOR)
25344 BuildVectorSDNode *Vector = cast<BuildVectorSDNode>(N1);
25346 ShuffleVectorSDNode *Shuffle = cast<ShuffleVectorSDNode>(N0.getOperand(0));
25347 EVT SrcType = Shuffle->getValueType(0);
25349 // We expect a single-source shuffle
25350 if (Shuffle->getOperand(1)->getOpcode() != ISD::UNDEF)
25353 unsigned SrcSize = SrcType.getScalarSizeInBits();
25355 APInt SplatValue, SplatUndef;
25356 unsigned SplatBitSize;
25358 if (!Vector->isConstantSplat(SplatValue, SplatUndef,
25359 SplatBitSize, HasAnyUndefs))
25362 unsigned ResSize = N1.getValueType().getScalarSizeInBits();
25363 // Make sure the splat matches the mask we expect
25364 if (SplatBitSize > ResSize ||
25365 (SplatValue + 1).exactLogBase2() != (int)SrcSize)
25368 // Make sure the input and output size make sense
25369 if (SrcSize >= ResSize || ResSize % SrcSize)
25372 // We expect a shuffle of the form <0, u, u, u, 1, u, u, u...>
25373 // The number of u's between each two values depends on the ratio between
25374 // the source and dest type.
25375 unsigned ZextRatio = ResSize / SrcSize;
25376 bool IsZext = true;
25377 for (unsigned i = 0; i < SrcType.getVectorNumElements(); ++i) {
25378 if (i % ZextRatio) {
25379 if (Shuffle->getMaskElt(i) > 0) {
25385 if (Shuffle->getMaskElt(i) != (int)(i / ZextRatio)) {
25386 // Expected element number
25396 // Ok, perform the transformation - replace the shuffle with
25397 // a shuffle of the form <0, k, k, k, 1, k, k, k> with zero
25398 // (instead of undef) where the k elements come from the zero vector.
25399 SmallVector<int, 8> Mask;
25400 unsigned NumElems = SrcType.getVectorNumElements();
25401 for (unsigned i = 0; i < NumElems; ++i)
25403 Mask.push_back(NumElems);
25405 Mask.push_back(i / ZextRatio);
25407 SDValue NewShuffle = DAG.getVectorShuffle(Shuffle->getValueType(0), DL,
25408 Shuffle->getOperand(0), DAG.getConstant(0, DL, SrcType), Mask);
25409 return DAG.getBitcast(N0.getValueType(), NewShuffle);
25412 /// If both input operands of a logic op are being cast from floating point
25413 /// types, try to convert this into a floating point logic node to avoid
25414 /// unnecessary moves from SSE to integer registers.
25415 static SDValue convertIntLogicToFPLogic(SDNode *N, SelectionDAG &DAG,
25416 const X86Subtarget *Subtarget) {
25417 unsigned FPOpcode = ISD::DELETED_NODE;
25418 if (N->getOpcode() == ISD::AND)
25419 FPOpcode = X86ISD::FAND;
25420 else if (N->getOpcode() == ISD::OR)
25421 FPOpcode = X86ISD::FOR;
25422 else if (N->getOpcode() == ISD::XOR)
25423 FPOpcode = X86ISD::FXOR;
25425 assert(FPOpcode != ISD::DELETED_NODE &&
25426 "Unexpected input node for FP logic conversion");
25428 EVT VT = N->getValueType(0);
25429 SDValue N0 = N->getOperand(0);
25430 SDValue N1 = N->getOperand(1);
25432 if (N0.getOpcode() == ISD::BITCAST && N1.getOpcode() == ISD::BITCAST &&
25433 ((Subtarget->hasSSE1() && VT == MVT::i32) ||
25434 (Subtarget->hasSSE2() && VT == MVT::i64))) {
25435 SDValue N00 = N0.getOperand(0);
25436 SDValue N10 = N1.getOperand(0);
25437 EVT N00Type = N00.getValueType();
25438 EVT N10Type = N10.getValueType();
25439 if (N00Type.isFloatingPoint() && N10Type.isFloatingPoint()) {
25440 SDValue FPLogic = DAG.getNode(FPOpcode, DL, N00Type, N00, N10);
25441 return DAG.getBitcast(VT, FPLogic);
25447 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
25448 TargetLowering::DAGCombinerInfo &DCI,
25449 const X86Subtarget *Subtarget) {
25450 if (DCI.isBeforeLegalizeOps())
25453 if (SDValue Zext = VectorZextCombine(N, DAG, DCI, Subtarget))
25456 if (SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget))
25459 if (SDValue FPLogic = convertIntLogicToFPLogic(N, DAG, Subtarget))
25462 EVT VT = N->getValueType(0);
25463 SDValue N0 = N->getOperand(0);
25464 SDValue N1 = N->getOperand(1);
25467 // Create BEXTR instructions
25468 // BEXTR is ((X >> imm) & (2**size-1))
25469 if (VT == MVT::i32 || VT == MVT::i64) {
25470 // Check for BEXTR.
25471 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
25472 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
25473 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
25474 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
25475 if (MaskNode && ShiftNode) {
25476 uint64_t Mask = MaskNode->getZExtValue();
25477 uint64_t Shift = ShiftNode->getZExtValue();
25478 if (isMask_64(Mask)) {
25479 uint64_t MaskSize = countPopulation(Mask);
25480 if (Shift + MaskSize <= VT.getSizeInBits())
25481 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
25482 DAG.getConstant(Shift | (MaskSize << 8), DL,
25491 // Want to form ANDNP nodes:
25492 // 1) In the hopes of then easily combining them with OR and AND nodes
25493 // to form PBLEND/PSIGN.
25494 // 2) To match ANDN packed intrinsics
25495 if (VT != MVT::v2i64 && VT != MVT::v4i64)
25498 // Check LHS for vnot
25499 if (N0.getOpcode() == ISD::XOR &&
25500 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
25501 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
25502 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
25504 // Check RHS for vnot
25505 if (N1.getOpcode() == ISD::XOR &&
25506 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
25507 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
25508 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
25513 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
25514 TargetLowering::DAGCombinerInfo &DCI,
25515 const X86Subtarget *Subtarget) {
25516 if (DCI.isBeforeLegalizeOps())
25519 if (SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget))
25522 if (SDValue FPLogic = convertIntLogicToFPLogic(N, DAG, Subtarget))
25525 SDValue N0 = N->getOperand(0);
25526 SDValue N1 = N->getOperand(1);
25527 EVT VT = N->getValueType(0);
25529 // look for psign/blend
25530 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
25531 if (!Subtarget->hasSSSE3() ||
25532 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
25535 // Canonicalize pandn to RHS
25536 if (N0.getOpcode() == X86ISD::ANDNP)
25538 // or (and (m, y), (pandn m, x))
25539 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
25540 SDValue Mask = N1.getOperand(0);
25541 SDValue X = N1.getOperand(1);
25543 if (N0.getOperand(0) == Mask)
25544 Y = N0.getOperand(1);
25545 if (N0.getOperand(1) == Mask)
25546 Y = N0.getOperand(0);
25548 // Check to see if the mask appeared in both the AND and ANDNP and
25552 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
25553 // Look through mask bitcast.
25554 if (Mask.getOpcode() == ISD::BITCAST)
25555 Mask = Mask.getOperand(0);
25556 if (X.getOpcode() == ISD::BITCAST)
25557 X = X.getOperand(0);
25558 if (Y.getOpcode() == ISD::BITCAST)
25559 Y = Y.getOperand(0);
25561 EVT MaskVT = Mask.getValueType();
25563 // Validate that the Mask operand is a vector sra node.
25564 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
25565 // there is no psrai.b
25566 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
25567 unsigned SraAmt = ~0;
25568 if (Mask.getOpcode() == ISD::SRA) {
25569 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
25570 if (auto *AmtConst = AmtBV->getConstantSplatNode())
25571 SraAmt = AmtConst->getZExtValue();
25572 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
25573 SDValue SraC = Mask.getOperand(1);
25574 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
25576 if ((SraAmt + 1) != EltBits)
25581 // Now we know we at least have a plendvb with the mask val. See if
25582 // we can form a psignb/w/d.
25583 // psign = x.type == y.type == mask.type && y = sub(0, x);
25584 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
25585 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
25586 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
25587 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
25588 "Unsupported VT for PSIGN");
25589 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
25590 return DAG.getBitcast(VT, Mask);
25592 // PBLENDVB only available on SSE 4.1
25593 if (!Subtarget->hasSSE41())
25596 MVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
25598 X = DAG.getBitcast(BlendVT, X);
25599 Y = DAG.getBitcast(BlendVT, Y);
25600 Mask = DAG.getBitcast(BlendVT, Mask);
25601 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
25602 return DAG.getBitcast(VT, Mask);
25606 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
25609 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
25610 bool OptForSize = DAG.getMachineFunction().getFunction()->optForSize();
25612 // SHLD/SHRD instructions have lower register pressure, but on some
25613 // platforms they have higher latency than the equivalent
25614 // series of shifts/or that would otherwise be generated.
25615 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
25616 // have higher latencies and we are not optimizing for size.
25617 if (!OptForSize && Subtarget->isSHLDSlow())
25620 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
25622 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
25624 if (!N0.hasOneUse() || !N1.hasOneUse())
25627 SDValue ShAmt0 = N0.getOperand(1);
25628 if (ShAmt0.getValueType() != MVT::i8)
25630 SDValue ShAmt1 = N1.getOperand(1);
25631 if (ShAmt1.getValueType() != MVT::i8)
25633 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
25634 ShAmt0 = ShAmt0.getOperand(0);
25635 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
25636 ShAmt1 = ShAmt1.getOperand(0);
25639 unsigned Opc = X86ISD::SHLD;
25640 SDValue Op0 = N0.getOperand(0);
25641 SDValue Op1 = N1.getOperand(0);
25642 if (ShAmt0.getOpcode() == ISD::SUB) {
25643 Opc = X86ISD::SHRD;
25644 std::swap(Op0, Op1);
25645 std::swap(ShAmt0, ShAmt1);
25648 unsigned Bits = VT.getSizeInBits();
25649 if (ShAmt1.getOpcode() == ISD::SUB) {
25650 SDValue Sum = ShAmt1.getOperand(0);
25651 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
25652 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
25653 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
25654 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
25655 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
25656 return DAG.getNode(Opc, DL, VT,
25658 DAG.getNode(ISD::TRUNCATE, DL,
25661 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
25662 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
25664 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
25665 return DAG.getNode(Opc, DL, VT,
25666 N0.getOperand(0), N1.getOperand(0),
25667 DAG.getNode(ISD::TRUNCATE, DL,
25674 // Generate NEG and CMOV for integer abs.
25675 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
25676 EVT VT = N->getValueType(0);
25678 // Since X86 does not have CMOV for 8-bit integer, we don't convert
25679 // 8-bit integer abs to NEG and CMOV.
25680 if (VT.isInteger() && VT.getSizeInBits() == 8)
25683 SDValue N0 = N->getOperand(0);
25684 SDValue N1 = N->getOperand(1);
25687 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
25688 // and change it to SUB and CMOV.
25689 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
25690 N0.getOpcode() == ISD::ADD &&
25691 N0.getOperand(1) == N1 &&
25692 N1.getOpcode() == ISD::SRA &&
25693 N1.getOperand(0) == N0.getOperand(0))
25694 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
25695 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
25696 // Generate SUB & CMOV.
25697 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
25698 DAG.getConstant(0, DL, VT), N0.getOperand(0));
25700 SDValue Ops[] = { N0.getOperand(0), Neg,
25701 DAG.getConstant(X86::COND_GE, DL, MVT::i8),
25702 SDValue(Neg.getNode(), 1) };
25703 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
25708 // Try to turn tests against the signbit in the form of:
25709 // XOR(TRUNCATE(SRL(X, size(X)-1)), 1)
25712 static SDValue foldXorTruncShiftIntoCmp(SDNode *N, SelectionDAG &DAG) {
25713 // This is only worth doing if the output type is i8.
25714 if (N->getValueType(0) != MVT::i8)
25717 SDValue N0 = N->getOperand(0);
25718 SDValue N1 = N->getOperand(1);
25720 // We should be performing an xor against a truncated shift.
25721 if (N0.getOpcode() != ISD::TRUNCATE || !N0.hasOneUse())
25724 // Make sure we are performing an xor against one.
25725 if (!isOneConstant(N1))
25728 // SetCC on x86 zero extends so only act on this if it's a logical shift.
25729 SDValue Shift = N0.getOperand(0);
25730 if (Shift.getOpcode() != ISD::SRL || !Shift.hasOneUse())
25733 // Make sure we are truncating from one of i16, i32 or i64.
25734 EVT ShiftTy = Shift.getValueType();
25735 if (ShiftTy != MVT::i16 && ShiftTy != MVT::i32 && ShiftTy != MVT::i64)
25738 // Make sure the shift amount extracts the sign bit.
25739 if (!isa<ConstantSDNode>(Shift.getOperand(1)) ||
25740 Shift.getConstantOperandVal(1) != ShiftTy.getSizeInBits() - 1)
25743 // Create a greater-than comparison against -1.
25744 // N.B. Using SETGE against 0 works but we want a canonical looking
25745 // comparison, using SETGT matches up with what TranslateX86CC.
25747 SDValue ShiftOp = Shift.getOperand(0);
25748 EVT ShiftOpTy = ShiftOp.getValueType();
25749 SDValue Cond = DAG.getSetCC(DL, MVT::i8, ShiftOp,
25750 DAG.getConstant(-1, DL, ShiftOpTy), ISD::SETGT);
25754 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
25755 TargetLowering::DAGCombinerInfo &DCI,
25756 const X86Subtarget *Subtarget) {
25757 if (DCI.isBeforeLegalizeOps())
25760 if (SDValue RV = foldXorTruncShiftIntoCmp(N, DAG))
25763 if (Subtarget->hasCMov())
25764 if (SDValue RV = performIntegerAbsCombine(N, DAG))
25767 if (SDValue FPLogic = convertIntLogicToFPLogic(N, DAG, Subtarget))
25773 /// This function detects the AVG pattern between vectors of unsigned i8/i16,
25774 /// which is c = (a + b + 1) / 2, and replace this operation with the efficient
25775 /// X86ISD::AVG instruction.
25776 static SDValue detectAVGPattern(SDValue In, EVT VT, SelectionDAG &DAG,
25777 const X86Subtarget *Subtarget, SDLoc DL) {
25778 if (!VT.isVector() || !VT.isSimple())
25780 EVT InVT = In.getValueType();
25781 unsigned NumElems = VT.getVectorNumElements();
25783 EVT ScalarVT = VT.getVectorElementType();
25784 if (!((ScalarVT == MVT::i8 || ScalarVT == MVT::i16) &&
25785 isPowerOf2_32(NumElems)))
25788 // InScalarVT is the intermediate type in AVG pattern and it should be greater
25789 // than the original input type (i8/i16).
25790 EVT InScalarVT = InVT.getVectorElementType();
25791 if (InScalarVT.getSizeInBits() <= ScalarVT.getSizeInBits())
25794 if (Subtarget->hasAVX512()) {
25795 if (VT.getSizeInBits() > 512)
25797 } else if (Subtarget->hasAVX2()) {
25798 if (VT.getSizeInBits() > 256)
25801 if (VT.getSizeInBits() > 128)
25805 // Detect the following pattern:
25807 // %1 = zext <N x i8> %a to <N x i32>
25808 // %2 = zext <N x i8> %b to <N x i32>
25809 // %3 = add nuw nsw <N x i32> %1, <i32 1 x N>
25810 // %4 = add nuw nsw <N x i32> %3, %2
25811 // %5 = lshr <N x i32> %N, <i32 1 x N>
25812 // %6 = trunc <N x i32> %5 to <N x i8>
25814 // In AVX512, the last instruction can also be a trunc store.
25816 if (In.getOpcode() != ISD::SRL)
25819 // A lambda checking the given SDValue is a constant vector and each element
25820 // is in the range [Min, Max].
25821 auto IsConstVectorInRange = [](SDValue V, unsigned Min, unsigned Max) {
25822 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(V);
25823 if (!BV || !BV->isConstant())
25825 for (unsigned i = 0, e = V.getNumOperands(); i < e; i++) {
25826 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V.getOperand(i));
25829 uint64_t Val = C->getZExtValue();
25830 if (Val < Min || Val > Max)
25836 // Check if each element of the vector is left-shifted by one.
25837 auto LHS = In.getOperand(0);
25838 auto RHS = In.getOperand(1);
25839 if (!IsConstVectorInRange(RHS, 1, 1))
25841 if (LHS.getOpcode() != ISD::ADD)
25844 // Detect a pattern of a + b + 1 where the order doesn't matter.
25845 SDValue Operands[3];
25846 Operands[0] = LHS.getOperand(0);
25847 Operands[1] = LHS.getOperand(1);
25849 // Take care of the case when one of the operands is a constant vector whose
25850 // element is in the range [1, 256].
25851 if (IsConstVectorInRange(Operands[1], 1, ScalarVT == MVT::i8 ? 256 : 65536) &&
25852 Operands[0].getOpcode() == ISD::ZERO_EXTEND &&
25853 Operands[0].getOperand(0).getValueType() == VT) {
25854 // The pattern is detected. Subtract one from the constant vector, then
25855 // demote it and emit X86ISD::AVG instruction.
25856 SDValue One = DAG.getConstant(1, DL, InScalarVT);
25857 SDValue Ones = DAG.getNode(ISD::BUILD_VECTOR, DL, InVT,
25858 SmallVector<SDValue, 8>(NumElems, One));
25859 Operands[1] = DAG.getNode(ISD::SUB, DL, InVT, Operands[1], Ones);
25860 Operands[1] = DAG.getNode(ISD::TRUNCATE, DL, VT, Operands[1]);
25861 return DAG.getNode(X86ISD::AVG, DL, VT, Operands[0].getOperand(0),
25865 if (Operands[0].getOpcode() == ISD::ADD)
25866 std::swap(Operands[0], Operands[1]);
25867 else if (Operands[1].getOpcode() != ISD::ADD)
25869 Operands[2] = Operands[1].getOperand(0);
25870 Operands[1] = Operands[1].getOperand(1);
25872 // Now we have three operands of two additions. Check that one of them is a
25873 // constant vector with ones, and the other two are promoted from i8/i16.
25874 for (int i = 0; i < 3; ++i) {
25875 if (!IsConstVectorInRange(Operands[i], 1, 1))
25877 std::swap(Operands[i], Operands[2]);
25879 // Check if Operands[0] and Operands[1] are results of type promotion.
25880 for (int j = 0; j < 2; ++j)
25881 if (Operands[j].getOpcode() != ISD::ZERO_EXTEND ||
25882 Operands[j].getOperand(0).getValueType() != VT)
25885 // The pattern is detected, emit X86ISD::AVG instruction.
25886 return DAG.getNode(X86ISD::AVG, DL, VT, Operands[0].getOperand(0),
25887 Operands[1].getOperand(0));
25893 static SDValue PerformTRUNCATECombine(SDNode *N, SelectionDAG &DAG,
25894 const X86Subtarget *Subtarget) {
25895 return detectAVGPattern(N->getOperand(0), N->getValueType(0), DAG, Subtarget,
25899 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
25900 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
25901 TargetLowering::DAGCombinerInfo &DCI,
25902 const X86Subtarget *Subtarget) {
25903 LoadSDNode *Ld = cast<LoadSDNode>(N);
25904 EVT RegVT = Ld->getValueType(0);
25905 EVT MemVT = Ld->getMemoryVT();
25907 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25909 // For chips with slow 32-byte unaligned loads, break the 32-byte operation
25910 // into two 16-byte operations.
25911 ISD::LoadExtType Ext = Ld->getExtensionType();
25913 unsigned AddressSpace = Ld->getAddressSpace();
25914 unsigned Alignment = Ld->getAlignment();
25915 if (RegVT.is256BitVector() && !DCI.isBeforeLegalizeOps() &&
25916 Ext == ISD::NON_EXTLOAD &&
25917 TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), RegVT,
25918 AddressSpace, Alignment, &Fast) && !Fast) {
25919 unsigned NumElems = RegVT.getVectorNumElements();
25923 SDValue Ptr = Ld->getBasePtr();
25924 SDValue Increment =
25925 DAG.getConstant(16, dl, TLI.getPointerTy(DAG.getDataLayout()));
25927 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
25929 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
25930 Ld->getPointerInfo(), Ld->isVolatile(),
25931 Ld->isNonTemporal(), Ld->isInvariant(),
25933 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
25934 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
25935 Ld->getPointerInfo(), Ld->isVolatile(),
25936 Ld->isNonTemporal(), Ld->isInvariant(),
25937 std::min(16U, Alignment));
25938 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
25940 Load2.getValue(1));
25942 SDValue NewVec = DAG.getUNDEF(RegVT);
25943 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
25944 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
25945 return DCI.CombineTo(N, NewVec, TF, true);
25951 /// PerformMLOADCombine - Resolve extending loads
25952 static SDValue PerformMLOADCombine(SDNode *N, SelectionDAG &DAG,
25953 TargetLowering::DAGCombinerInfo &DCI,
25954 const X86Subtarget *Subtarget) {
25955 MaskedLoadSDNode *Mld = cast<MaskedLoadSDNode>(N);
25956 if (Mld->getExtensionType() != ISD::SEXTLOAD)
25959 EVT VT = Mld->getValueType(0);
25960 unsigned NumElems = VT.getVectorNumElements();
25961 EVT LdVT = Mld->getMemoryVT();
25964 assert(LdVT != VT && "Cannot extend to the same type");
25965 unsigned ToSz = VT.getVectorElementType().getSizeInBits();
25966 unsigned FromSz = LdVT.getVectorElementType().getSizeInBits();
25967 // From, To sizes and ElemCount must be pow of two
25968 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
25969 "Unexpected size for extending masked load");
25971 unsigned SizeRatio = ToSz / FromSz;
25972 assert(SizeRatio * NumElems * FromSz == VT.getSizeInBits());
25974 // Create a type on which we perform the shuffle
25975 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
25976 LdVT.getScalarType(), NumElems*SizeRatio);
25977 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
25979 // Convert Src0 value
25980 SDValue WideSrc0 = DAG.getBitcast(WideVecVT, Mld->getSrc0());
25981 if (Mld->getSrc0().getOpcode() != ISD::UNDEF) {
25982 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
25983 for (unsigned i = 0; i != NumElems; ++i)
25984 ShuffleVec[i] = i * SizeRatio;
25986 // Can't shuffle using an illegal type.
25987 assert(DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT) &&
25988 "WideVecVT should be legal");
25989 WideSrc0 = DAG.getVectorShuffle(WideVecVT, dl, WideSrc0,
25990 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
25992 // Prepare the new mask
25994 SDValue Mask = Mld->getMask();
25995 if (Mask.getValueType() == VT) {
25996 // Mask and original value have the same type
25997 NewMask = DAG.getBitcast(WideVecVT, Mask);
25998 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
25999 for (unsigned i = 0; i != NumElems; ++i)
26000 ShuffleVec[i] = i * SizeRatio;
26001 for (unsigned i = NumElems; i != NumElems * SizeRatio; ++i)
26002 ShuffleVec[i] = NumElems * SizeRatio;
26003 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
26004 DAG.getConstant(0, dl, WideVecVT),
26008 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
26009 unsigned WidenNumElts = NumElems*SizeRatio;
26010 unsigned MaskNumElts = VT.getVectorNumElements();
26011 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
26014 unsigned NumConcat = WidenNumElts / MaskNumElts;
26015 SmallVector<SDValue, 16> Ops(NumConcat);
26016 SDValue ZeroVal = DAG.getConstant(0, dl, Mask.getValueType());
26018 for (unsigned i = 1; i != NumConcat; ++i)
26021 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
26024 SDValue WideLd = DAG.getMaskedLoad(WideVecVT, dl, Mld->getChain(),
26025 Mld->getBasePtr(), NewMask, WideSrc0,
26026 Mld->getMemoryVT(), Mld->getMemOperand(),
26028 SDValue NewVec = DAG.getNode(X86ISD::VSEXT, dl, VT, WideLd);
26029 return DCI.CombineTo(N, NewVec, WideLd.getValue(1), true);
26031 /// PerformMSTORECombine - Resolve truncating stores
26032 static SDValue PerformMSTORECombine(SDNode *N, SelectionDAG &DAG,
26033 const X86Subtarget *Subtarget) {
26034 MaskedStoreSDNode *Mst = cast<MaskedStoreSDNode>(N);
26035 if (!Mst->isTruncatingStore())
26038 EVT VT = Mst->getValue().getValueType();
26039 unsigned NumElems = VT.getVectorNumElements();
26040 EVT StVT = Mst->getMemoryVT();
26043 assert(StVT != VT && "Cannot truncate to the same type");
26044 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
26045 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
26047 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
26049 // The truncating store is legal in some cases. For example
26050 // vpmovqb, vpmovqw, vpmovqd, vpmovdb, vpmovdw
26051 // are designated for truncate store.
26052 // In this case we don't need any further transformations.
26053 if (TLI.isTruncStoreLegal(VT, StVT))
26056 // From, To sizes and ElemCount must be pow of two
26057 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
26058 "Unexpected size for truncating masked store");
26059 // We are going to use the original vector elt for storing.
26060 // Accumulated smaller vector elements must be a multiple of the store size.
26061 assert (((NumElems * FromSz) % ToSz) == 0 &&
26062 "Unexpected ratio for truncating masked store");
26064 unsigned SizeRatio = FromSz / ToSz;
26065 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
26067 // Create a type on which we perform the shuffle
26068 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
26069 StVT.getScalarType(), NumElems*SizeRatio);
26071 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
26073 SDValue WideVec = DAG.getBitcast(WideVecVT, Mst->getValue());
26074 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
26075 for (unsigned i = 0; i != NumElems; ++i)
26076 ShuffleVec[i] = i * SizeRatio;
26078 // Can't shuffle using an illegal type.
26079 assert(DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT) &&
26080 "WideVecVT should be legal");
26082 SDValue TruncatedVal = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
26083 DAG.getUNDEF(WideVecVT),
26087 SDValue Mask = Mst->getMask();
26088 if (Mask.getValueType() == VT) {
26089 // Mask and original value have the same type
26090 NewMask = DAG.getBitcast(WideVecVT, Mask);
26091 for (unsigned i = 0; i != NumElems; ++i)
26092 ShuffleVec[i] = i * SizeRatio;
26093 for (unsigned i = NumElems; i != NumElems*SizeRatio; ++i)
26094 ShuffleVec[i] = NumElems*SizeRatio;
26095 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
26096 DAG.getConstant(0, dl, WideVecVT),
26100 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
26101 unsigned WidenNumElts = NumElems*SizeRatio;
26102 unsigned MaskNumElts = VT.getVectorNumElements();
26103 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
26106 unsigned NumConcat = WidenNumElts / MaskNumElts;
26107 SmallVector<SDValue, 16> Ops(NumConcat);
26108 SDValue ZeroVal = DAG.getConstant(0, dl, Mask.getValueType());
26110 for (unsigned i = 1; i != NumConcat; ++i)
26113 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
26116 return DAG.getMaskedStore(Mst->getChain(), dl, TruncatedVal,
26117 Mst->getBasePtr(), NewMask, StVT,
26118 Mst->getMemOperand(), false);
26120 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
26121 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
26122 const X86Subtarget *Subtarget) {
26123 StoreSDNode *St = cast<StoreSDNode>(N);
26124 EVT VT = St->getValue().getValueType();
26125 EVT StVT = St->getMemoryVT();
26127 SDValue StoredVal = St->getOperand(1);
26128 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
26130 // If we are saving a concatenation of two XMM registers and 32-byte stores
26131 // are slow, such as on Sandy Bridge, perform two 16-byte stores.
26133 unsigned AddressSpace = St->getAddressSpace();
26134 unsigned Alignment = St->getAlignment();
26135 if (VT.is256BitVector() && StVT == VT &&
26136 TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), VT,
26137 AddressSpace, Alignment, &Fast) && !Fast) {
26138 unsigned NumElems = VT.getVectorNumElements();
26142 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
26143 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
26146 DAG.getConstant(16, dl, TLI.getPointerTy(DAG.getDataLayout()));
26147 SDValue Ptr0 = St->getBasePtr();
26148 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
26150 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
26151 St->getPointerInfo(), St->isVolatile(),
26152 St->isNonTemporal(), Alignment);
26153 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
26154 St->getPointerInfo(), St->isVolatile(),
26155 St->isNonTemporal(),
26156 std::min(16U, Alignment));
26157 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
26160 // Optimize trunc store (of multiple scalars) to shuffle and store.
26161 // First, pack all of the elements in one place. Next, store to memory
26162 // in fewer chunks.
26163 if (St->isTruncatingStore() && VT.isVector()) {
26164 // Check if we can detect an AVG pattern from the truncation. If yes,
26165 // replace the trunc store by a normal store with the result of X86ISD::AVG
26168 detectAVGPattern(St->getValue(), St->getMemoryVT(), DAG, Subtarget, dl);
26170 return DAG.getStore(St->getChain(), dl, Avg, St->getBasePtr(),
26171 St->getPointerInfo(), St->isVolatile(),
26172 St->isNonTemporal(), St->getAlignment());
26174 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
26175 unsigned NumElems = VT.getVectorNumElements();
26176 assert(StVT != VT && "Cannot truncate to the same type");
26177 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
26178 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
26180 // The truncating store is legal in some cases. For example
26181 // vpmovqb, vpmovqw, vpmovqd, vpmovdb, vpmovdw
26182 // are designated for truncate store.
26183 // In this case we don't need any further transformations.
26184 if (TLI.isTruncStoreLegal(VT, StVT))
26187 // From, To sizes and ElemCount must be pow of two
26188 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
26189 // We are going to use the original vector elt for storing.
26190 // Accumulated smaller vector elements must be a multiple of the store size.
26191 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
26193 unsigned SizeRatio = FromSz / ToSz;
26195 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
26197 // Create a type on which we perform the shuffle
26198 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
26199 StVT.getScalarType(), NumElems*SizeRatio);
26201 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
26203 SDValue WideVec = DAG.getBitcast(WideVecVT, St->getValue());
26204 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
26205 for (unsigned i = 0; i != NumElems; ++i)
26206 ShuffleVec[i] = i * SizeRatio;
26208 // Can't shuffle using an illegal type.
26209 if (!TLI.isTypeLegal(WideVecVT))
26212 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
26213 DAG.getUNDEF(WideVecVT),
26215 // At this point all of the data is stored at the bottom of the
26216 // register. We now need to save it to mem.
26218 // Find the largest store unit
26219 MVT StoreType = MVT::i8;
26220 for (MVT Tp : MVT::integer_valuetypes()) {
26221 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
26225 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
26226 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
26227 (64 <= NumElems * ToSz))
26228 StoreType = MVT::f64;
26230 // Bitcast the original vector into a vector of store-size units
26231 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
26232 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
26233 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
26234 SDValue ShuffWide = DAG.getBitcast(StoreVecVT, Shuff);
26235 SmallVector<SDValue, 8> Chains;
26236 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits() / 8, dl,
26237 TLI.getPointerTy(DAG.getDataLayout()));
26238 SDValue Ptr = St->getBasePtr();
26240 // Perform one or more big stores into memory.
26241 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
26242 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
26243 StoreType, ShuffWide,
26244 DAG.getIntPtrConstant(i, dl));
26245 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
26246 St->getPointerInfo(), St->isVolatile(),
26247 St->isNonTemporal(), St->getAlignment());
26248 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
26249 Chains.push_back(Ch);
26252 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
26255 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
26256 // the FP state in cases where an emms may be missing.
26257 // A preferable solution to the general problem is to figure out the right
26258 // places to insert EMMS. This qualifies as a quick hack.
26260 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
26261 if (VT.getSizeInBits() != 64)
26264 const Function *F = DAG.getMachineFunction().getFunction();
26265 bool NoImplicitFloatOps = F->hasFnAttribute(Attribute::NoImplicitFloat);
26267 !Subtarget->useSoftFloat() && !NoImplicitFloatOps && Subtarget->hasSSE2();
26268 if ((VT.isVector() ||
26269 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
26270 isa<LoadSDNode>(St->getValue()) &&
26271 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
26272 St->getChain().hasOneUse() && !St->isVolatile()) {
26273 SDNode* LdVal = St->getValue().getNode();
26274 LoadSDNode *Ld = nullptr;
26275 int TokenFactorIndex = -1;
26276 SmallVector<SDValue, 8> Ops;
26277 SDNode* ChainVal = St->getChain().getNode();
26278 // Must be a store of a load. We currently handle two cases: the load
26279 // is a direct child, and it's under an intervening TokenFactor. It is
26280 // possible to dig deeper under nested TokenFactors.
26281 if (ChainVal == LdVal)
26282 Ld = cast<LoadSDNode>(St->getChain());
26283 else if (St->getValue().hasOneUse() &&
26284 ChainVal->getOpcode() == ISD::TokenFactor) {
26285 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
26286 if (ChainVal->getOperand(i).getNode() == LdVal) {
26287 TokenFactorIndex = i;
26288 Ld = cast<LoadSDNode>(St->getValue());
26290 Ops.push_back(ChainVal->getOperand(i));
26294 if (!Ld || !ISD::isNormalLoad(Ld))
26297 // If this is not the MMX case, i.e. we are just turning i64 load/store
26298 // into f64 load/store, avoid the transformation if there are multiple
26299 // uses of the loaded value.
26300 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
26305 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
26306 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
26308 if (Subtarget->is64Bit() || F64IsLegal) {
26309 MVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
26310 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
26311 Ld->getPointerInfo(), Ld->isVolatile(),
26312 Ld->isNonTemporal(), Ld->isInvariant(),
26313 Ld->getAlignment());
26314 SDValue NewChain = NewLd.getValue(1);
26315 if (TokenFactorIndex != -1) {
26316 Ops.push_back(NewChain);
26317 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
26319 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
26320 St->getPointerInfo(),
26321 St->isVolatile(), St->isNonTemporal(),
26322 St->getAlignment());
26325 // Otherwise, lower to two pairs of 32-bit loads / stores.
26326 SDValue LoAddr = Ld->getBasePtr();
26327 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
26328 DAG.getConstant(4, LdDL, MVT::i32));
26330 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
26331 Ld->getPointerInfo(),
26332 Ld->isVolatile(), Ld->isNonTemporal(),
26333 Ld->isInvariant(), Ld->getAlignment());
26334 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
26335 Ld->getPointerInfo().getWithOffset(4),
26336 Ld->isVolatile(), Ld->isNonTemporal(),
26338 MinAlign(Ld->getAlignment(), 4));
26340 SDValue NewChain = LoLd.getValue(1);
26341 if (TokenFactorIndex != -1) {
26342 Ops.push_back(LoLd);
26343 Ops.push_back(HiLd);
26344 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
26347 LoAddr = St->getBasePtr();
26348 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
26349 DAG.getConstant(4, StDL, MVT::i32));
26351 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
26352 St->getPointerInfo(),
26353 St->isVolatile(), St->isNonTemporal(),
26354 St->getAlignment());
26355 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
26356 St->getPointerInfo().getWithOffset(4),
26358 St->isNonTemporal(),
26359 MinAlign(St->getAlignment(), 4));
26360 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
26363 // This is similar to the above case, but here we handle a scalar 64-bit
26364 // integer store that is extracted from a vector on a 32-bit target.
26365 // If we have SSE2, then we can treat it like a floating-point double
26366 // to get past legalization. The execution dependencies fixup pass will
26367 // choose the optimal machine instruction for the store if this really is
26368 // an integer or v2f32 rather than an f64.
26369 if (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit() &&
26370 St->getOperand(1).getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
26371 SDValue OldExtract = St->getOperand(1);
26372 SDValue ExtOp0 = OldExtract.getOperand(0);
26373 unsigned VecSize = ExtOp0.getValueSizeInBits();
26374 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, VecSize / 64);
26375 SDValue BitCast = DAG.getBitcast(VecVT, ExtOp0);
26376 SDValue NewExtract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
26377 BitCast, OldExtract.getOperand(1));
26378 return DAG.getStore(St->getChain(), dl, NewExtract, St->getBasePtr(),
26379 St->getPointerInfo(), St->isVolatile(),
26380 St->isNonTemporal(), St->getAlignment());
26386 /// Return 'true' if this vector operation is "horizontal"
26387 /// and return the operands for the horizontal operation in LHS and RHS. A
26388 /// horizontal operation performs the binary operation on successive elements
26389 /// of its first operand, then on successive elements of its second operand,
26390 /// returning the resulting values in a vector. For example, if
26391 /// A = < float a0, float a1, float a2, float a3 >
26393 /// B = < float b0, float b1, float b2, float b3 >
26394 /// then the result of doing a horizontal operation on A and B is
26395 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
26396 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
26397 /// A horizontal-op B, for some already available A and B, and if so then LHS is
26398 /// set to A, RHS to B, and the routine returns 'true'.
26399 /// Note that the binary operation should have the property that if one of the
26400 /// operands is UNDEF then the result is UNDEF.
26401 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
26402 // Look for the following pattern: if
26403 // A = < float a0, float a1, float a2, float a3 >
26404 // B = < float b0, float b1, float b2, float b3 >
26406 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
26407 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
26408 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
26409 // which is A horizontal-op B.
26411 // At least one of the operands should be a vector shuffle.
26412 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
26413 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
26416 MVT VT = LHS.getSimpleValueType();
26418 assert((VT.is128BitVector() || VT.is256BitVector()) &&
26419 "Unsupported vector type for horizontal add/sub");
26421 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
26422 // operate independently on 128-bit lanes.
26423 unsigned NumElts = VT.getVectorNumElements();
26424 unsigned NumLanes = VT.getSizeInBits()/128;
26425 unsigned NumLaneElts = NumElts / NumLanes;
26426 assert((NumLaneElts % 2 == 0) &&
26427 "Vector type should have an even number of elements in each lane");
26428 unsigned HalfLaneElts = NumLaneElts/2;
26430 // View LHS in the form
26431 // LHS = VECTOR_SHUFFLE A, B, LMask
26432 // If LHS is not a shuffle then pretend it is the shuffle
26433 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
26434 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
26437 SmallVector<int, 16> LMask(NumElts);
26438 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
26439 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
26440 A = LHS.getOperand(0);
26441 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
26442 B = LHS.getOperand(1);
26443 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
26444 std::copy(Mask.begin(), Mask.end(), LMask.begin());
26446 if (LHS.getOpcode() != ISD::UNDEF)
26448 for (unsigned i = 0; i != NumElts; ++i)
26452 // Likewise, view RHS in the form
26453 // RHS = VECTOR_SHUFFLE C, D, RMask
26455 SmallVector<int, 16> RMask(NumElts);
26456 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
26457 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
26458 C = RHS.getOperand(0);
26459 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
26460 D = RHS.getOperand(1);
26461 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
26462 std::copy(Mask.begin(), Mask.end(), RMask.begin());
26464 if (RHS.getOpcode() != ISD::UNDEF)
26466 for (unsigned i = 0; i != NumElts; ++i)
26470 // Check that the shuffles are both shuffling the same vectors.
26471 if (!(A == C && B == D) && !(A == D && B == C))
26474 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
26475 if (!A.getNode() && !B.getNode())
26478 // If A and B occur in reverse order in RHS, then "swap" them (which means
26479 // rewriting the mask).
26481 ShuffleVectorSDNode::commuteMask(RMask);
26483 // At this point LHS and RHS are equivalent to
26484 // LHS = VECTOR_SHUFFLE A, B, LMask
26485 // RHS = VECTOR_SHUFFLE A, B, RMask
26486 // Check that the masks correspond to performing a horizontal operation.
26487 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
26488 for (unsigned i = 0; i != NumLaneElts; ++i) {
26489 int LIdx = LMask[i+l], RIdx = RMask[i+l];
26491 // Ignore any UNDEF components.
26492 if (LIdx < 0 || RIdx < 0 ||
26493 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
26494 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
26497 // Check that successive elements are being operated on. If not, this is
26498 // not a horizontal operation.
26499 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
26500 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
26501 if (!(LIdx == Index && RIdx == Index + 1) &&
26502 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
26507 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
26508 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
26512 /// Do target-specific dag combines on floating point adds.
26513 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
26514 const X86Subtarget *Subtarget) {
26515 EVT VT = N->getValueType(0);
26516 SDValue LHS = N->getOperand(0);
26517 SDValue RHS = N->getOperand(1);
26519 // Try to synthesize horizontal adds from adds of shuffles.
26520 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
26521 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
26522 isHorizontalBinOp(LHS, RHS, true))
26523 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
26527 /// Do target-specific dag combines on floating point subs.
26528 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
26529 const X86Subtarget *Subtarget) {
26530 EVT VT = N->getValueType(0);
26531 SDValue LHS = N->getOperand(0);
26532 SDValue RHS = N->getOperand(1);
26534 // Try to synthesize horizontal subs from subs of shuffles.
26535 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
26536 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
26537 isHorizontalBinOp(LHS, RHS, false))
26538 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
26542 /// Do target-specific dag combines on floating point negations.
26543 static SDValue PerformFNEGCombine(SDNode *N, SelectionDAG &DAG,
26544 const X86Subtarget *Subtarget) {
26545 EVT VT = N->getValueType(0);
26546 EVT SVT = VT.getScalarType();
26547 SDValue Arg = N->getOperand(0);
26550 // Let legalize expand this if it isn't a legal type yet.
26551 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
26554 // If we're negating a FMUL node on a target with FMA, then we can avoid the
26555 // use of a constant by performing (-0 - A*B) instead.
26556 // FIXME: Check rounding control flags as well once it becomes available.
26557 if (Arg.getOpcode() == ISD::FMUL && (SVT == MVT::f32 || SVT == MVT::f64) &&
26558 Arg->getFlags()->hasNoSignedZeros() && Subtarget->hasAnyFMA()) {
26559 SDValue Zero = DAG.getConstantFP(0.0, DL, VT);
26560 return DAG.getNode(X86ISD::FNMSUB, DL, VT, Arg.getOperand(0),
26561 Arg.getOperand(1), Zero);
26564 // If we're negating a FMA node, then we can adjust the
26565 // instruction to include the extra negation.
26566 if (Arg.hasOneUse()) {
26567 switch (Arg.getOpcode()) {
26568 case X86ISD::FMADD:
26569 return DAG.getNode(X86ISD::FNMSUB, DL, VT, Arg.getOperand(0),
26570 Arg.getOperand(1), Arg.getOperand(2));
26571 case X86ISD::FMSUB:
26572 return DAG.getNode(X86ISD::FNMADD, DL, VT, Arg.getOperand(0),
26573 Arg.getOperand(1), Arg.getOperand(2));
26574 case X86ISD::FNMADD:
26575 return DAG.getNode(X86ISD::FMSUB, DL, VT, Arg.getOperand(0),
26576 Arg.getOperand(1), Arg.getOperand(2));
26577 case X86ISD::FNMSUB:
26578 return DAG.getNode(X86ISD::FMADD, DL, VT, Arg.getOperand(0),
26579 Arg.getOperand(1), Arg.getOperand(2));
26585 static SDValue lowerX86FPLogicOp(SDNode *N, SelectionDAG &DAG,
26586 const X86Subtarget *Subtarget) {
26587 EVT VT = N->getValueType(0);
26588 if (VT.is512BitVector() && !Subtarget->hasDQI()) {
26589 // VXORPS, VORPS, VANDPS, VANDNPS are supported only under DQ extention.
26590 // These logic operations may be executed in the integer domain.
26592 MVT IntScalar = MVT::getIntegerVT(VT.getScalarSizeInBits());
26593 MVT IntVT = MVT::getVectorVT(IntScalar, VT.getVectorNumElements());
26595 SDValue Op0 = DAG.getNode(ISD::BITCAST, dl, IntVT, N->getOperand(0));
26596 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, IntVT, N->getOperand(1));
26597 unsigned IntOpcode = 0;
26598 switch (N->getOpcode()) {
26599 default: llvm_unreachable("Unexpected FP logic op");
26600 case X86ISD::FOR: IntOpcode = ISD::OR; break;
26601 case X86ISD::FXOR: IntOpcode = ISD::XOR; break;
26602 case X86ISD::FAND: IntOpcode = ISD::AND; break;
26603 case X86ISD::FANDN: IntOpcode = X86ISD::ANDNP; break;
26605 SDValue IntOp = DAG.getNode(IntOpcode, dl, IntVT, Op0, Op1);
26606 return DAG.getNode(ISD::BITCAST, dl, VT, IntOp);
26610 /// Do target-specific dag combines on X86ISD::FOR and X86ISD::FXOR nodes.
26611 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG,
26612 const X86Subtarget *Subtarget) {
26613 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
26615 // F[X]OR(0.0, x) -> x
26616 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
26617 if (C->getValueAPF().isPosZero())
26618 return N->getOperand(1);
26620 // F[X]OR(x, 0.0) -> x
26621 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
26622 if (C->getValueAPF().isPosZero())
26623 return N->getOperand(0);
26625 return lowerX86FPLogicOp(N, DAG, Subtarget);
26628 /// Do target-specific dag combines on X86ISD::FMIN and X86ISD::FMAX nodes.
26629 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
26630 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
26632 // Only perform optimizations if UnsafeMath is used.
26633 if (!DAG.getTarget().Options.UnsafeFPMath)
26636 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
26637 // into FMINC and FMAXC, which are Commutative operations.
26638 unsigned NewOp = 0;
26639 switch (N->getOpcode()) {
26640 default: llvm_unreachable("unknown opcode");
26641 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
26642 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
26645 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
26646 N->getOperand(0), N->getOperand(1));
26649 static SDValue performFMaxNumCombine(SDNode *N, SelectionDAG &DAG,
26650 const X86Subtarget *Subtarget) {
26651 // This takes at least 3 instructions, so favor a library call when
26652 // minimizing code size.
26653 if (DAG.getMachineFunction().getFunction()->optForMinSize())
26656 EVT VT = N->getValueType(0);
26658 // TODO: Check for global or instruction-level "nnan". In that case, we
26659 // should be able to lower to FMAX/FMIN alone.
26660 // TODO: If an operand is already known to be a NaN or not a NaN, this
26661 // should be an optional swap and FMAX/FMIN.
26662 // TODO: Allow f64, vectors, and fminnum.
26664 if (VT != MVT::f32 || !Subtarget->hasSSE1() || Subtarget->useSoftFloat())
26667 SDValue Op0 = N->getOperand(0);
26668 SDValue Op1 = N->getOperand(1);
26670 EVT SetCCType = DAG.getTargetLoweringInfo().getSetCCResultType(
26671 DAG.getDataLayout(), *DAG.getContext(), VT);
26673 // There are 4 possibilities involving NaN inputs, and these are the required
26677 // ----------------
26678 // Num | Max | Op0 |
26679 // Op0 ----------------
26680 // NaN | Op1 | NaN |
26681 // ----------------
26683 // The SSE FP max/min instructions were not designed for this case, but rather
26685 // Max = Op1 > Op0 ? Op1 : Op0
26687 // So they always return Op0 if either input is a NaN. However, we can still
26688 // use those instructions for fmaxnum by selecting away a NaN input.
26690 // If either operand is NaN, the 2nd source operand (Op0) is passed through.
26691 SDValue Max = DAG.getNode(X86ISD::FMAX, DL, VT, Op1, Op0);
26692 SDValue IsOp0Nan = DAG.getSetCC(DL, SetCCType , Op0, Op0, ISD::SETUO);
26694 // If Op0 is a NaN, select Op1. Otherwise, select the max. If both operands
26695 // are NaN, the NaN value of Op1 is the result.
26696 return DAG.getNode(ISD::SELECT, DL, VT, IsOp0Nan, Op1, Max);
26699 /// Do target-specific dag combines on X86ISD::FAND nodes.
26700 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG,
26701 const X86Subtarget *Subtarget) {
26702 // FAND(0.0, x) -> 0.0
26703 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
26704 if (C->getValueAPF().isPosZero())
26705 return N->getOperand(0);
26707 // FAND(x, 0.0) -> 0.0
26708 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
26709 if (C->getValueAPF().isPosZero())
26710 return N->getOperand(1);
26712 return lowerX86FPLogicOp(N, DAG, Subtarget);
26715 /// Do target-specific dag combines on X86ISD::FANDN nodes
26716 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG,
26717 const X86Subtarget *Subtarget) {
26718 // FANDN(0.0, x) -> x
26719 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
26720 if (C->getValueAPF().isPosZero())
26721 return N->getOperand(1);
26723 // FANDN(x, 0.0) -> 0.0
26724 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
26725 if (C->getValueAPF().isPosZero())
26726 return N->getOperand(1);
26728 return lowerX86FPLogicOp(N, DAG, Subtarget);
26731 static SDValue PerformBTCombine(SDNode *N,
26733 TargetLowering::DAGCombinerInfo &DCI) {
26734 // BT ignores high bits in the bit index operand.
26735 SDValue Op1 = N->getOperand(1);
26736 if (Op1.hasOneUse()) {
26737 unsigned BitWidth = Op1.getValueSizeInBits();
26738 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
26739 APInt KnownZero, KnownOne;
26740 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
26741 !DCI.isBeforeLegalizeOps());
26742 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
26743 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
26744 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
26745 DCI.CommitTargetLoweringOpt(TLO);
26750 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
26751 SDValue Op = N->getOperand(0);
26752 if (Op.getOpcode() == ISD::BITCAST)
26753 Op = Op.getOperand(0);
26754 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
26755 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
26756 VT.getVectorElementType().getSizeInBits() ==
26757 OpVT.getVectorElementType().getSizeInBits()) {
26758 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
26763 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
26764 const X86Subtarget *Subtarget) {
26765 EVT VT = N->getValueType(0);
26766 if (!VT.isVector())
26769 SDValue N0 = N->getOperand(0);
26770 SDValue N1 = N->getOperand(1);
26771 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
26774 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
26775 // both SSE and AVX2 since there is no sign-extended shift right
26776 // operation on a vector with 64-bit elements.
26777 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
26778 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
26779 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
26780 N0.getOpcode() == ISD::SIGN_EXTEND)) {
26781 SDValue N00 = N0.getOperand(0);
26783 // EXTLOAD has a better solution on AVX2,
26784 // it may be replaced with X86ISD::VSEXT node.
26785 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
26786 if (!ISD::isNormalLoad(N00.getNode()))
26789 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
26790 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
26792 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
26798 /// sext(add_nsw(x, C)) --> add(sext(x), C_sext)
26799 /// Promoting a sign extension ahead of an 'add nsw' exposes opportunities
26800 /// to combine math ops, use an LEA, or use a complex addressing mode. This can
26801 /// eliminate extend, add, and shift instructions.
26802 static SDValue promoteSextBeforeAddNSW(SDNode *Sext, SelectionDAG &DAG,
26803 const X86Subtarget *Subtarget) {
26804 // TODO: This should be valid for other integer types.
26805 EVT VT = Sext->getValueType(0);
26806 if (VT != MVT::i64)
26809 // We need an 'add nsw' feeding into the 'sext'.
26810 SDValue Add = Sext->getOperand(0);
26811 if (Add.getOpcode() != ISD::ADD || !Add->getFlags()->hasNoSignedWrap())
26814 // Having a constant operand to the 'add' ensures that we are not increasing
26815 // the instruction count because the constant is extended for free below.
26816 // A constant operand can also become the displacement field of an LEA.
26817 auto *AddOp1 = dyn_cast<ConstantSDNode>(Add.getOperand(1));
26821 // Don't make the 'add' bigger if there's no hope of combining it with some
26822 // other 'add' or 'shl' instruction.
26823 // TODO: It may be profitable to generate simpler LEA instructions in place
26824 // of single 'add' instructions, but the cost model for selecting an LEA
26825 // currently has a high threshold.
26826 bool HasLEAPotential = false;
26827 for (auto *User : Sext->uses()) {
26828 if (User->getOpcode() == ISD::ADD || User->getOpcode() == ISD::SHL) {
26829 HasLEAPotential = true;
26833 if (!HasLEAPotential)
26836 // Everything looks good, so pull the 'sext' ahead of the 'add'.
26837 int64_t AddConstant = AddOp1->getSExtValue();
26838 SDValue AddOp0 = Add.getOperand(0);
26839 SDValue NewSext = DAG.getNode(ISD::SIGN_EXTEND, SDLoc(Sext), VT, AddOp0);
26840 SDValue NewConstant = DAG.getConstant(AddConstant, SDLoc(Add), VT);
26842 // The wider add is guaranteed to not wrap because both operands are
26845 Flags.setNoSignedWrap(true);
26846 return DAG.getNode(ISD::ADD, SDLoc(Add), VT, NewSext, NewConstant, &Flags);
26849 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
26850 TargetLowering::DAGCombinerInfo &DCI,
26851 const X86Subtarget *Subtarget) {
26852 SDValue N0 = N->getOperand(0);
26853 EVT VT = N->getValueType(0);
26854 EVT SVT = VT.getScalarType();
26855 EVT InVT = N0.getValueType();
26856 EVT InSVT = InVT.getScalarType();
26859 // (i8,i32 sext (sdivrem (i8 x, i8 y)) ->
26860 // (i8,i32 (sdivrem_sext_hreg (i8 x, i8 y)
26861 // This exposes the sext to the sdivrem lowering, so that it directly extends
26862 // from AH (which we otherwise need to do contortions to access).
26863 if (N0.getOpcode() == ISD::SDIVREM && N0.getResNo() == 1 &&
26864 InVT == MVT::i8 && VT == MVT::i32) {
26865 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
26866 SDValue R = DAG.getNode(X86ISD::SDIVREM8_SEXT_HREG, DL, NodeTys,
26867 N0.getOperand(0), N0.getOperand(1));
26868 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
26869 return R.getValue(1);
26872 if (!DCI.isBeforeLegalizeOps()) {
26873 if (InVT == MVT::i1) {
26874 SDValue Zero = DAG.getConstant(0, DL, VT);
26876 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), DL, VT);
26877 return DAG.getNode(ISD::SELECT, DL, VT, N0, AllOnes, Zero);
26882 if (VT.isVector() && Subtarget->hasSSE2()) {
26883 auto ExtendVecSize = [&DAG](SDLoc DL, SDValue N, unsigned Size) {
26884 EVT InVT = N.getValueType();
26885 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), InVT.getScalarType(),
26886 Size / InVT.getScalarSizeInBits());
26887 SmallVector<SDValue, 8> Opnds(Size / InVT.getSizeInBits(),
26888 DAG.getUNDEF(InVT));
26890 return DAG.getNode(ISD::CONCAT_VECTORS, DL, OutVT, Opnds);
26893 // If target-size is less than 128-bits, extend to a type that would extend
26894 // to 128 bits, extend that and extract the original target vector.
26895 if (VT.getSizeInBits() < 128 && !(128 % VT.getSizeInBits()) &&
26896 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
26897 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
26898 unsigned Scale = 128 / VT.getSizeInBits();
26900 EVT::getVectorVT(*DAG.getContext(), SVT, 128 / SVT.getSizeInBits());
26901 SDValue Ex = ExtendVecSize(DL, N0, Scale * InVT.getSizeInBits());
26902 SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND, DL, ExVT, Ex);
26903 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, SExt,
26904 DAG.getIntPtrConstant(0, DL));
26907 // If target-size is 128-bits, then convert to ISD::SIGN_EXTEND_VECTOR_INREG
26908 // which ensures lowering to X86ISD::VSEXT (pmovsx*).
26909 if (VT.getSizeInBits() == 128 &&
26910 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
26911 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
26912 SDValue ExOp = ExtendVecSize(DL, N0, 128);
26913 return DAG.getSignExtendVectorInReg(ExOp, DL, VT);
26916 // On pre-AVX2 targets, split into 128-bit nodes of
26917 // ISD::SIGN_EXTEND_VECTOR_INREG.
26918 if (!Subtarget->hasInt256() && !(VT.getSizeInBits() % 128) &&
26919 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
26920 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
26921 unsigned NumVecs = VT.getSizeInBits() / 128;
26922 unsigned NumSubElts = 128 / SVT.getSizeInBits();
26923 EVT SubVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumSubElts);
26924 EVT InSubVT = EVT::getVectorVT(*DAG.getContext(), InSVT, NumSubElts);
26926 SmallVector<SDValue, 8> Opnds;
26927 for (unsigned i = 0, Offset = 0; i != NumVecs;
26928 ++i, Offset += NumSubElts) {
26929 SDValue SrcVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InSubVT, N0,
26930 DAG.getIntPtrConstant(Offset, DL));
26931 SrcVec = ExtendVecSize(DL, SrcVec, 128);
26932 SrcVec = DAG.getSignExtendVectorInReg(SrcVec, DL, SubVT);
26933 Opnds.push_back(SrcVec);
26935 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Opnds);
26939 if (Subtarget->hasAVX() && VT.is256BitVector())
26940 if (SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget))
26943 if (SDValue NewAdd = promoteSextBeforeAddNSW(N, DAG, Subtarget))
26949 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
26950 const X86Subtarget* Subtarget) {
26952 EVT VT = N->getValueType(0);
26954 // Let legalize expand this if it isn't a legal type yet.
26955 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
26958 EVT ScalarVT = VT.getScalarType();
26959 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) || !Subtarget->hasAnyFMA())
26962 SDValue A = N->getOperand(0);
26963 SDValue B = N->getOperand(1);
26964 SDValue C = N->getOperand(2);
26966 bool NegA = (A.getOpcode() == ISD::FNEG);
26967 bool NegB = (B.getOpcode() == ISD::FNEG);
26968 bool NegC = (C.getOpcode() == ISD::FNEG);
26970 // Negative multiplication when NegA xor NegB
26971 bool NegMul = (NegA != NegB);
26973 A = A.getOperand(0);
26975 B = B.getOperand(0);
26977 C = C.getOperand(0);
26981 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
26983 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
26985 return DAG.getNode(Opcode, dl, VT, A, B, C);
26988 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
26989 TargetLowering::DAGCombinerInfo &DCI,
26990 const X86Subtarget *Subtarget) {
26991 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
26992 // (and (i32 x86isd::setcc_carry), 1)
26993 // This eliminates the zext. This transformation is necessary because
26994 // ISD::SETCC is always legalized to i8.
26996 SDValue N0 = N->getOperand(0);
26997 EVT VT = N->getValueType(0);
26999 if (N0.getOpcode() == ISD::AND &&
27001 N0.getOperand(0).hasOneUse()) {
27002 SDValue N00 = N0.getOperand(0);
27003 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
27004 if (!isOneConstant(N0.getOperand(1)))
27006 return DAG.getNode(ISD::AND, dl, VT,
27007 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
27008 N00.getOperand(0), N00.getOperand(1)),
27009 DAG.getConstant(1, dl, VT));
27013 if (N0.getOpcode() == ISD::TRUNCATE &&
27015 N0.getOperand(0).hasOneUse()) {
27016 SDValue N00 = N0.getOperand(0);
27017 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
27018 return DAG.getNode(ISD::AND, dl, VT,
27019 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
27020 N00.getOperand(0), N00.getOperand(1)),
27021 DAG.getConstant(1, dl, VT));
27025 if (VT.is256BitVector())
27026 if (SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget))
27029 // (i8,i32 zext (udivrem (i8 x, i8 y)) ->
27030 // (i8,i32 (udivrem_zext_hreg (i8 x, i8 y)
27031 // This exposes the zext to the udivrem lowering, so that it directly extends
27032 // from AH (which we otherwise need to do contortions to access).
27033 if (N0.getOpcode() == ISD::UDIVREM &&
27034 N0.getResNo() == 1 && N0.getValueType() == MVT::i8 &&
27035 (VT == MVT::i32 || VT == MVT::i64)) {
27036 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
27037 SDValue R = DAG.getNode(X86ISD::UDIVREM8_ZEXT_HREG, dl, NodeTys,
27038 N0.getOperand(0), N0.getOperand(1));
27039 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
27040 return R.getValue(1);
27046 // Optimize x == -y --> x+y == 0
27047 // x != -y --> x+y != 0
27048 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
27049 const X86Subtarget* Subtarget) {
27050 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
27051 SDValue LHS = N->getOperand(0);
27052 SDValue RHS = N->getOperand(1);
27053 EVT VT = N->getValueType(0);
27056 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
27057 if (isNullConstant(LHS.getOperand(0)) && LHS.hasOneUse()) {
27058 SDValue addV = DAG.getNode(ISD::ADD, DL, LHS.getValueType(), RHS,
27059 LHS.getOperand(1));
27060 return DAG.getSetCC(DL, N->getValueType(0), addV,
27061 DAG.getConstant(0, DL, addV.getValueType()), CC);
27063 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
27064 if (isNullConstant(RHS.getOperand(0)) && RHS.hasOneUse()) {
27065 SDValue addV = DAG.getNode(ISD::ADD, DL, RHS.getValueType(), LHS,
27066 RHS.getOperand(1));
27067 return DAG.getSetCC(DL, N->getValueType(0), addV,
27068 DAG.getConstant(0, DL, addV.getValueType()), CC);
27071 if (VT.getScalarType() == MVT::i1 &&
27072 (CC == ISD::SETNE || CC == ISD::SETEQ || ISD::isSignedIntSetCC(CC))) {
27074 (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
27075 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
27076 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
27078 if (!IsSEXT0 || !IsVZero1) {
27079 // Swap the operands and update the condition code.
27080 std::swap(LHS, RHS);
27081 CC = ISD::getSetCCSwappedOperands(CC);
27083 IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
27084 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
27085 IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
27088 if (IsSEXT0 && IsVZero1) {
27089 assert(VT == LHS.getOperand(0).getValueType() &&
27090 "Uexpected operand type");
27091 if (CC == ISD::SETGT)
27092 return DAG.getConstant(0, DL, VT);
27093 if (CC == ISD::SETLE)
27094 return DAG.getConstant(1, DL, VT);
27095 if (CC == ISD::SETEQ || CC == ISD::SETGE)
27096 return DAG.getNOT(DL, LHS.getOperand(0), VT);
27098 assert((CC == ISD::SETNE || CC == ISD::SETLT) &&
27099 "Unexpected condition code!");
27100 return LHS.getOperand(0);
27107 static SDValue PerformBLENDICombine(SDNode *N, SelectionDAG &DAG) {
27108 SDValue V0 = N->getOperand(0);
27109 SDValue V1 = N->getOperand(1);
27111 EVT VT = N->getValueType(0);
27113 // Canonicalize a v2f64 blend with a mask of 2 by swapping the vector
27114 // operands and changing the mask to 1. This saves us a bunch of
27115 // pattern-matching possibilities related to scalar math ops in SSE/AVX.
27116 // x86InstrInfo knows how to commute this back after instruction selection
27117 // if it would help register allocation.
27119 // TODO: If optimizing for size or a processor that doesn't suffer from
27120 // partial register update stalls, this should be transformed into a MOVSD
27121 // instruction because a MOVSD is 1-2 bytes smaller than a BLENDPD.
27123 if (VT == MVT::v2f64)
27124 if (auto *Mask = dyn_cast<ConstantSDNode>(N->getOperand(2)))
27125 if (Mask->getZExtValue() == 2 && !isShuffleFoldableLoad(V0)) {
27126 SDValue NewMask = DAG.getConstant(1, DL, MVT::i8);
27127 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V0, NewMask);
27133 static SDValue PerformGatherScatterCombine(SDNode *N, SelectionDAG &DAG) {
27135 // Gather and Scatter instructions use k-registers for masks. The type of
27136 // the masks is v*i1. So the mask will be truncated anyway.
27137 // The SIGN_EXTEND_INREG my be dropped.
27138 SDValue Mask = N->getOperand(2);
27139 if (Mask.getOpcode() == ISD::SIGN_EXTEND_INREG) {
27140 SmallVector<SDValue, 5> NewOps(N->op_begin(), N->op_end());
27141 NewOps[2] = Mask.getOperand(0);
27142 DAG.UpdateNodeOperands(N, NewOps);
27147 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
27148 // as "sbb reg,reg", since it can be extended without zext and produces
27149 // an all-ones bit which is more useful than 0/1 in some cases.
27150 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
27153 return DAG.getNode(ISD::AND, DL, VT,
27154 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
27155 DAG.getConstant(X86::COND_B, DL, MVT::i8),
27157 DAG.getConstant(1, DL, VT));
27158 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
27159 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
27160 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
27161 DAG.getConstant(X86::COND_B, DL, MVT::i8),
27165 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
27166 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
27167 TargetLowering::DAGCombinerInfo &DCI,
27168 const X86Subtarget *Subtarget) {
27170 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
27171 SDValue EFLAGS = N->getOperand(1);
27173 if (CC == X86::COND_A) {
27174 // Try to convert COND_A into COND_B in an attempt to facilitate
27175 // materializing "setb reg".
27177 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
27178 // cannot take an immediate as its first operand.
27180 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
27181 EFLAGS.getValueType().isInteger() &&
27182 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
27183 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
27184 EFLAGS.getNode()->getVTList(),
27185 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
27186 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
27187 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
27191 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
27192 // a zext and produces an all-ones bit which is more useful than 0/1 in some
27194 if (CC == X86::COND_B)
27195 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
27197 if (SDValue Flags = checkBoolTestSetCCCombine(EFLAGS, CC)) {
27198 SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
27199 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
27205 // Optimize branch condition evaluation.
27207 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
27208 TargetLowering::DAGCombinerInfo &DCI,
27209 const X86Subtarget *Subtarget) {
27211 SDValue Chain = N->getOperand(0);
27212 SDValue Dest = N->getOperand(1);
27213 SDValue EFLAGS = N->getOperand(3);
27214 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
27216 if (SDValue Flags = checkBoolTestSetCCCombine(EFLAGS, CC)) {
27217 SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
27218 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
27225 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
27226 SelectionDAG &DAG) {
27227 // Take advantage of vector comparisons producing 0 or -1 in each lane to
27228 // optimize away operation when it's from a constant.
27230 // The general transformation is:
27231 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
27232 // AND(VECTOR_CMP(x,y), constant2)
27233 // constant2 = UNARYOP(constant)
27235 // Early exit if this isn't a vector operation, the operand of the
27236 // unary operation isn't a bitwise AND, or if the sizes of the operations
27237 // aren't the same.
27238 EVT VT = N->getValueType(0);
27239 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
27240 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
27241 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
27244 // Now check that the other operand of the AND is a constant. We could
27245 // make the transformation for non-constant splats as well, but it's unclear
27246 // that would be a benefit as it would not eliminate any operations, just
27247 // perform one more step in scalar code before moving to the vector unit.
27248 if (BuildVectorSDNode *BV =
27249 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
27250 // Bail out if the vector isn't a constant.
27251 if (!BV->isConstant())
27254 // Everything checks out. Build up the new and improved node.
27256 EVT IntVT = BV->getValueType(0);
27257 // Create a new constant of the appropriate type for the transformed
27259 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
27260 // The AND node needs bitcasts to/from an integer vector type around it.
27261 SDValue MaskConst = DAG.getBitcast(IntVT, SourceConst);
27262 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
27263 N->getOperand(0)->getOperand(0), MaskConst);
27264 SDValue Res = DAG.getBitcast(VT, NewAnd);
27271 static SDValue PerformUINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
27272 const X86Subtarget *Subtarget) {
27273 SDValue Op0 = N->getOperand(0);
27274 EVT VT = N->getValueType(0);
27275 EVT InVT = Op0.getValueType();
27276 EVT InSVT = InVT.getScalarType();
27277 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
27279 // UINT_TO_FP(vXi8) -> SINT_TO_FP(ZEXT(vXi8 to vXi32))
27280 // UINT_TO_FP(vXi16) -> SINT_TO_FP(ZEXT(vXi16 to vXi32))
27281 if (InVT.isVector() && (InSVT == MVT::i8 || InSVT == MVT::i16)) {
27283 EVT DstVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
27284 InVT.getVectorNumElements());
27285 SDValue P = DAG.getNode(ISD::ZERO_EXTEND, dl, DstVT, Op0);
27287 if (TLI.isOperationLegal(ISD::UINT_TO_FP, DstVT))
27288 return DAG.getNode(ISD::UINT_TO_FP, dl, VT, P);
27290 return DAG.getNode(ISD::SINT_TO_FP, dl, VT, P);
27296 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
27297 const X86Subtarget *Subtarget) {
27298 // First try to optimize away the conversion entirely when it's
27299 // conditionally from a constant. Vectors only.
27300 if (SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG))
27303 // Now move on to more general possibilities.
27304 SDValue Op0 = N->getOperand(0);
27305 EVT VT = N->getValueType(0);
27306 EVT InVT = Op0.getValueType();
27307 EVT InSVT = InVT.getScalarType();
27309 // SINT_TO_FP(vXi8) -> SINT_TO_FP(SEXT(vXi8 to vXi32))
27310 // SINT_TO_FP(vXi16) -> SINT_TO_FP(SEXT(vXi16 to vXi32))
27311 if (InVT.isVector() && (InSVT == MVT::i8 || InSVT == MVT::i16)) {
27313 EVT DstVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
27314 InVT.getVectorNumElements());
27315 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
27316 return DAG.getNode(ISD::SINT_TO_FP, dl, VT, P);
27319 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
27320 // a 32-bit target where SSE doesn't support i64->FP operations.
27321 if (!Subtarget->useSoftFloat() && Op0.getOpcode() == ISD::LOAD) {
27322 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
27323 EVT LdVT = Ld->getValueType(0);
27325 // This transformation is not supported if the result type is f16
27326 if (VT == MVT::f16)
27329 if (!Ld->isVolatile() && !VT.isVector() &&
27330 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
27331 !Subtarget->is64Bit() && LdVT == MVT::i64) {
27332 SDValue FILDChain = Subtarget->getTargetLowering()->BuildFILD(
27333 SDValue(N, 0), LdVT, Ld->getChain(), Op0, DAG);
27334 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
27341 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
27342 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
27343 X86TargetLowering::DAGCombinerInfo &DCI) {
27344 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
27345 // the result is either zero or one (depending on the input carry bit).
27346 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
27347 if (X86::isZeroNode(N->getOperand(0)) &&
27348 X86::isZeroNode(N->getOperand(1)) &&
27349 // We don't have a good way to replace an EFLAGS use, so only do this when
27351 SDValue(N, 1).use_empty()) {
27353 EVT VT = N->getValueType(0);
27354 SDValue CarryOut = DAG.getConstant(0, DL, N->getValueType(1));
27355 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
27356 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
27357 DAG.getConstant(X86::COND_B, DL,
27360 DAG.getConstant(1, DL, VT));
27361 return DCI.CombineTo(N, Res1, CarryOut);
27367 // fold (add Y, (sete X, 0)) -> adc 0, Y
27368 // (add Y, (setne X, 0)) -> sbb -1, Y
27369 // (sub (sete X, 0), Y) -> sbb 0, Y
27370 // (sub (setne X, 0), Y) -> adc -1, Y
27371 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
27374 // Look through ZExts.
27375 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
27376 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
27379 SDValue SetCC = Ext.getOperand(0);
27380 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
27383 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
27384 if (CC != X86::COND_E && CC != X86::COND_NE)
27387 SDValue Cmp = SetCC.getOperand(1);
27388 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
27389 !X86::isZeroNode(Cmp.getOperand(1)) ||
27390 !Cmp.getOperand(0).getValueType().isInteger())
27393 SDValue CmpOp0 = Cmp.getOperand(0);
27394 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
27395 DAG.getConstant(1, DL, CmpOp0.getValueType()));
27397 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
27398 if (CC == X86::COND_NE)
27399 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
27400 DL, OtherVal.getValueType(), OtherVal,
27401 DAG.getConstant(-1ULL, DL, OtherVal.getValueType()),
27403 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
27404 DL, OtherVal.getValueType(), OtherVal,
27405 DAG.getConstant(0, DL, OtherVal.getValueType()), NewCmp);
27408 /// PerformADDCombine - Do target-specific dag combines on integer adds.
27409 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
27410 const X86Subtarget *Subtarget) {
27411 EVT VT = N->getValueType(0);
27412 SDValue Op0 = N->getOperand(0);
27413 SDValue Op1 = N->getOperand(1);
27415 // Try to synthesize horizontal adds from adds of shuffles.
27416 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
27417 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
27418 isHorizontalBinOp(Op0, Op1, true))
27419 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
27421 return OptimizeConditionalInDecrement(N, DAG);
27424 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
27425 const X86Subtarget *Subtarget) {
27426 SDValue Op0 = N->getOperand(0);
27427 SDValue Op1 = N->getOperand(1);
27429 // X86 can't encode an immediate LHS of a sub. See if we can push the
27430 // negation into a preceding instruction.
27431 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
27432 // If the RHS of the sub is a XOR with one use and a constant, invert the
27433 // immediate. Then add one to the LHS of the sub so we can turn
27434 // X-Y -> X+~Y+1, saving one register.
27435 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
27436 isa<ConstantSDNode>(Op1.getOperand(1))) {
27437 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
27438 EVT VT = Op0.getValueType();
27439 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
27441 DAG.getConstant(~XorC, SDLoc(Op1), VT));
27442 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
27443 DAG.getConstant(C->getAPIntValue() + 1, SDLoc(N), VT));
27447 // Try to synthesize horizontal adds from adds of shuffles.
27448 EVT VT = N->getValueType(0);
27449 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
27450 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
27451 isHorizontalBinOp(Op0, Op1, true))
27452 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
27454 return OptimizeConditionalInDecrement(N, DAG);
27457 /// performVZEXTCombine - Performs build vector combines
27458 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
27459 TargetLowering::DAGCombinerInfo &DCI,
27460 const X86Subtarget *Subtarget) {
27462 MVT VT = N->getSimpleValueType(0);
27463 SDValue Op = N->getOperand(0);
27464 MVT OpVT = Op.getSimpleValueType();
27465 MVT OpEltVT = OpVT.getVectorElementType();
27466 unsigned InputBits = OpEltVT.getSizeInBits() * VT.getVectorNumElements();
27468 // (vzext (bitcast (vzext (x)) -> (vzext x)
27470 while (V.getOpcode() == ISD::BITCAST)
27471 V = V.getOperand(0);
27473 if (V != Op && V.getOpcode() == X86ISD::VZEXT) {
27474 MVT InnerVT = V.getSimpleValueType();
27475 MVT InnerEltVT = InnerVT.getVectorElementType();
27477 // If the element sizes match exactly, we can just do one larger vzext. This
27478 // is always an exact type match as vzext operates on integer types.
27479 if (OpEltVT == InnerEltVT) {
27480 assert(OpVT == InnerVT && "Types must match for vzext!");
27481 return DAG.getNode(X86ISD::VZEXT, DL, VT, V.getOperand(0));
27484 // The only other way we can combine them is if only a single element of the
27485 // inner vzext is used in the input to the outer vzext.
27486 if (InnerEltVT.getSizeInBits() < InputBits)
27489 // In this case, the inner vzext is completely dead because we're going to
27490 // only look at bits inside of the low element. Just do the outer vzext on
27491 // a bitcast of the input to the inner.
27492 return DAG.getNode(X86ISD::VZEXT, DL, VT, DAG.getBitcast(OpVT, V));
27495 // Check if we can bypass extracting and re-inserting an element of an input
27496 // vector. Essentially:
27497 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
27498 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR &&
27499 V.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
27500 V.getOperand(0).getSimpleValueType().getSizeInBits() == InputBits) {
27501 SDValue ExtractedV = V.getOperand(0);
27502 SDValue OrigV = ExtractedV.getOperand(0);
27503 if (isNullConstant(ExtractedV.getOperand(1))) {
27504 MVT OrigVT = OrigV.getSimpleValueType();
27505 // Extract a subvector if necessary...
27506 if (OrigVT.getSizeInBits() > OpVT.getSizeInBits()) {
27507 int Ratio = OrigVT.getSizeInBits() / OpVT.getSizeInBits();
27508 OrigVT = MVT::getVectorVT(OrigVT.getVectorElementType(),
27509 OrigVT.getVectorNumElements() / Ratio);
27510 OrigV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigVT, OrigV,
27511 DAG.getIntPtrConstant(0, DL));
27513 Op = DAG.getBitcast(OpVT, OrigV);
27514 return DAG.getNode(X86ISD::VZEXT, DL, VT, Op);
27521 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
27522 DAGCombinerInfo &DCI) const {
27523 SelectionDAG &DAG = DCI.DAG;
27524 switch (N->getOpcode()) {
27526 case ISD::EXTRACT_VECTOR_ELT:
27527 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
27530 case X86ISD::SHRUNKBLEND:
27531 return PerformSELECTCombine(N, DAG, DCI, Subtarget);
27532 case ISD::BITCAST: return PerformBITCASTCombine(N, DAG, Subtarget);
27533 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
27534 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
27535 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
27536 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
27537 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
27540 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
27541 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
27542 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
27543 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
27544 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
27545 case ISD::MLOAD: return PerformMLOADCombine(N, DAG, DCI, Subtarget);
27546 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
27547 case ISD::MSTORE: return PerformMSTORECombine(N, DAG, Subtarget);
27548 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, Subtarget);
27549 case ISD::UINT_TO_FP: return PerformUINT_TO_FPCombine(N, DAG, Subtarget);
27550 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
27551 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
27552 case ISD::FNEG: return PerformFNEGCombine(N, DAG, Subtarget);
27553 case ISD::TRUNCATE: return PerformTRUNCATECombine(N, DAG, Subtarget);
27555 case X86ISD::FOR: return PerformFORCombine(N, DAG, Subtarget);
27557 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
27558 case ISD::FMAXNUM: return performFMaxNumCombine(N, DAG, Subtarget);
27559 case X86ISD::FAND: return PerformFANDCombine(N, DAG, Subtarget);
27560 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG, Subtarget);
27561 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
27562 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
27563 case ISD::ANY_EXTEND:
27564 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
27565 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
27566 case ISD::SIGN_EXTEND_INREG:
27567 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
27568 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
27569 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
27570 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
27571 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
27572 case X86ISD::SHUFP: // Handle all target specific shuffles
27573 case X86ISD::PALIGNR:
27574 case X86ISD::UNPCKH:
27575 case X86ISD::UNPCKL:
27576 case X86ISD::MOVHLPS:
27577 case X86ISD::MOVLHPS:
27578 case X86ISD::PSHUFB:
27579 case X86ISD::PSHUFD:
27580 case X86ISD::PSHUFHW:
27581 case X86ISD::PSHUFLW:
27582 case X86ISD::MOVSS:
27583 case X86ISD::MOVSD:
27584 case X86ISD::VPERMILPI:
27585 case X86ISD::VPERM2X128:
27586 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
27587 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
27588 case X86ISD::BLENDI: return PerformBLENDICombine(N, DAG);
27590 case ISD::MSCATTER: return PerformGatherScatterCombine(N, DAG);
27596 /// isTypeDesirableForOp - Return true if the target has native support for
27597 /// the specified value type and it is 'desirable' to use the type for the
27598 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
27599 /// instruction encodings are longer and some i16 instructions are slow.
27600 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
27601 if (!isTypeLegal(VT))
27603 if (VT != MVT::i16)
27610 case ISD::SIGN_EXTEND:
27611 case ISD::ZERO_EXTEND:
27612 case ISD::ANY_EXTEND:
27625 /// IsDesirableToPromoteOp - This method query the target whether it is
27626 /// beneficial for dag combiner to promote the specified node. If true, it
27627 /// should return the desired promotion type by reference.
27628 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
27629 EVT VT = Op.getValueType();
27630 if (VT != MVT::i16)
27633 bool Promote = false;
27634 bool Commute = false;
27635 switch (Op.getOpcode()) {
27638 LoadSDNode *LD = cast<LoadSDNode>(Op);
27639 // If the non-extending load has a single use and it's not live out, then it
27640 // might be folded.
27641 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
27642 Op.hasOneUse()*/) {
27643 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
27644 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
27645 // The only case where we'd want to promote LOAD (rather then it being
27646 // promoted as an operand is when it's only use is liveout.
27647 if (UI->getOpcode() != ISD::CopyToReg)
27654 case ISD::SIGN_EXTEND:
27655 case ISD::ZERO_EXTEND:
27656 case ISD::ANY_EXTEND:
27661 SDValue N0 = Op.getOperand(0);
27662 // Look out for (store (shl (load), x)).
27663 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
27676 SDValue N0 = Op.getOperand(0);
27677 SDValue N1 = Op.getOperand(1);
27678 if (!Commute && MayFoldLoad(N1))
27680 // Avoid disabling potential load folding opportunities.
27681 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
27683 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
27693 //===----------------------------------------------------------------------===//
27694 // X86 Inline Assembly Support
27695 //===----------------------------------------------------------------------===//
27697 // Helper to match a string separated by whitespace.
27698 static bool matchAsm(StringRef S, ArrayRef<const char *> Pieces) {
27699 S = S.substr(S.find_first_not_of(" \t")); // Skip leading whitespace.
27701 for (StringRef Piece : Pieces) {
27702 if (!S.startswith(Piece)) // Check if the piece matches.
27705 S = S.substr(Piece.size());
27706 StringRef::size_type Pos = S.find_first_not_of(" \t");
27707 if (Pos == 0) // We matched a prefix.
27716 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
27718 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
27719 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
27720 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
27721 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
27723 if (AsmPieces.size() == 3)
27725 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
27732 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
27733 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
27735 std::string AsmStr = IA->getAsmString();
27737 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
27738 if (!Ty || Ty->getBitWidth() % 16 != 0)
27741 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
27742 SmallVector<StringRef, 4> AsmPieces;
27743 SplitString(AsmStr, AsmPieces, ";\n");
27745 switch (AsmPieces.size()) {
27746 default: return false;
27748 // FIXME: this should verify that we are targeting a 486 or better. If not,
27749 // we will turn this bswap into something that will be lowered to logical
27750 // ops instead of emitting the bswap asm. For now, we don't support 486 or
27751 // lower so don't worry about this.
27753 if (matchAsm(AsmPieces[0], {"bswap", "$0"}) ||
27754 matchAsm(AsmPieces[0], {"bswapl", "$0"}) ||
27755 matchAsm(AsmPieces[0], {"bswapq", "$0"}) ||
27756 matchAsm(AsmPieces[0], {"bswap", "${0:q}"}) ||
27757 matchAsm(AsmPieces[0], {"bswapl", "${0:q}"}) ||
27758 matchAsm(AsmPieces[0], {"bswapq", "${0:q}"})) {
27759 // No need to check constraints, nothing other than the equivalent of
27760 // "=r,0" would be valid here.
27761 return IntrinsicLowering::LowerToByteSwap(CI);
27764 // rorw $$8, ${0:w} --> llvm.bswap.i16
27765 if (CI->getType()->isIntegerTy(16) &&
27766 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
27767 (matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) ||
27768 matchAsm(AsmPieces[0], {"rolw", "$$8,", "${0:w}"}))) {
27770 StringRef ConstraintsStr = IA->getConstraintString();
27771 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
27772 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
27773 if (clobbersFlagRegisters(AsmPieces))
27774 return IntrinsicLowering::LowerToByteSwap(CI);
27778 if (CI->getType()->isIntegerTy(32) &&
27779 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
27780 matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) &&
27781 matchAsm(AsmPieces[1], {"rorl", "$$16,", "$0"}) &&
27782 matchAsm(AsmPieces[2], {"rorw", "$$8,", "${0:w}"})) {
27784 StringRef ConstraintsStr = IA->getConstraintString();
27785 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
27786 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
27787 if (clobbersFlagRegisters(AsmPieces))
27788 return IntrinsicLowering::LowerToByteSwap(CI);
27791 if (CI->getType()->isIntegerTy(64)) {
27792 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
27793 if (Constraints.size() >= 2 &&
27794 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
27795 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
27796 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
27797 if (matchAsm(AsmPieces[0], {"bswap", "%eax"}) &&
27798 matchAsm(AsmPieces[1], {"bswap", "%edx"}) &&
27799 matchAsm(AsmPieces[2], {"xchgl", "%eax,", "%edx"}))
27800 return IntrinsicLowering::LowerToByteSwap(CI);
27808 /// getConstraintType - Given a constraint letter, return the type of
27809 /// constraint it is for this target.
27810 X86TargetLowering::ConstraintType
27811 X86TargetLowering::getConstraintType(StringRef Constraint) const {
27812 if (Constraint.size() == 1) {
27813 switch (Constraint[0]) {
27824 return C_RegisterClass;
27848 return TargetLowering::getConstraintType(Constraint);
27851 /// Examine constraint type and operand type and determine a weight value.
27852 /// This object must already have been set up with the operand type
27853 /// and the current alternative constraint selected.
27854 TargetLowering::ConstraintWeight
27855 X86TargetLowering::getSingleConstraintMatchWeight(
27856 AsmOperandInfo &info, const char *constraint) const {
27857 ConstraintWeight weight = CW_Invalid;
27858 Value *CallOperandVal = info.CallOperandVal;
27859 // If we don't have a value, we can't do a match,
27860 // but allow it at the lowest weight.
27861 if (!CallOperandVal)
27863 Type *type = CallOperandVal->getType();
27864 // Look at the constraint type.
27865 switch (*constraint) {
27867 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
27878 if (CallOperandVal->getType()->isIntegerTy())
27879 weight = CW_SpecificReg;
27884 if (type->isFloatingPointTy())
27885 weight = CW_SpecificReg;
27888 if (type->isX86_MMXTy() && Subtarget->hasMMX())
27889 weight = CW_SpecificReg;
27893 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
27894 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
27895 weight = CW_Register;
27898 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
27899 if (C->getZExtValue() <= 31)
27900 weight = CW_Constant;
27904 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27905 if (C->getZExtValue() <= 63)
27906 weight = CW_Constant;
27910 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27911 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
27912 weight = CW_Constant;
27916 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27917 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
27918 weight = CW_Constant;
27922 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27923 if (C->getZExtValue() <= 3)
27924 weight = CW_Constant;
27928 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27929 if (C->getZExtValue() <= 0xff)
27930 weight = CW_Constant;
27935 if (isa<ConstantFP>(CallOperandVal)) {
27936 weight = CW_Constant;
27940 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27941 if ((C->getSExtValue() >= -0x80000000LL) &&
27942 (C->getSExtValue() <= 0x7fffffffLL))
27943 weight = CW_Constant;
27947 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27948 if (C->getZExtValue() <= 0xffffffff)
27949 weight = CW_Constant;
27956 /// LowerXConstraint - try to replace an X constraint, which matches anything,
27957 /// with another that has more specific requirements based on the type of the
27958 /// corresponding operand.
27959 const char *X86TargetLowering::
27960 LowerXConstraint(EVT ConstraintVT) const {
27961 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
27962 // 'f' like normal targets.
27963 if (ConstraintVT.isFloatingPoint()) {
27964 if (Subtarget->hasSSE2())
27966 if (Subtarget->hasSSE1())
27970 return TargetLowering::LowerXConstraint(ConstraintVT);
27973 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
27974 /// vector. If it is invalid, don't add anything to Ops.
27975 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
27976 std::string &Constraint,
27977 std::vector<SDValue>&Ops,
27978 SelectionDAG &DAG) const {
27981 // Only support length 1 constraints for now.
27982 if (Constraint.length() > 1) return;
27984 char ConstraintLetter = Constraint[0];
27985 switch (ConstraintLetter) {
27988 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27989 if (C->getZExtValue() <= 31) {
27990 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27991 Op.getValueType());
27997 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27998 if (C->getZExtValue() <= 63) {
27999 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
28000 Op.getValueType());
28006 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
28007 if (isInt<8>(C->getSExtValue())) {
28008 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
28009 Op.getValueType());
28015 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
28016 if (C->getZExtValue() == 0xff || C->getZExtValue() == 0xffff ||
28017 (Subtarget->is64Bit() && C->getZExtValue() == 0xffffffff)) {
28018 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op),
28019 Op.getValueType());
28025 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
28026 if (C->getZExtValue() <= 3) {
28027 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
28028 Op.getValueType());
28034 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
28035 if (C->getZExtValue() <= 255) {
28036 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
28037 Op.getValueType());
28043 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
28044 if (C->getZExtValue() <= 127) {
28045 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
28046 Op.getValueType());
28052 // 32-bit signed value
28053 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
28054 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
28055 C->getSExtValue())) {
28056 // Widen to 64 bits here to get it sign extended.
28057 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op), MVT::i64);
28060 // FIXME gcc accepts some relocatable values here too, but only in certain
28061 // memory models; it's complicated.
28066 // 32-bit unsigned value
28067 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
28068 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
28069 C->getZExtValue())) {
28070 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
28071 Op.getValueType());
28075 // FIXME gcc accepts some relocatable values here too, but only in certain
28076 // memory models; it's complicated.
28080 // Literal immediates are always ok.
28081 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
28082 // Widen to 64 bits here to get it sign extended.
28083 Result = DAG.getTargetConstant(CST->getSExtValue(), SDLoc(Op), MVT::i64);
28087 // In any sort of PIC mode addresses need to be computed at runtime by
28088 // adding in a register or some sort of table lookup. These can't
28089 // be used as immediates.
28090 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
28093 // If we are in non-pic codegen mode, we allow the address of a global (with
28094 // an optional displacement) to be used with 'i'.
28095 GlobalAddressSDNode *GA = nullptr;
28096 int64_t Offset = 0;
28098 // Match either (GA), (GA+C), (GA+C1+C2), etc.
28100 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
28101 Offset += GA->getOffset();
28103 } else if (Op.getOpcode() == ISD::ADD) {
28104 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
28105 Offset += C->getZExtValue();
28106 Op = Op.getOperand(0);
28109 } else if (Op.getOpcode() == ISD::SUB) {
28110 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
28111 Offset += -C->getZExtValue();
28112 Op = Op.getOperand(0);
28117 // Otherwise, this isn't something we can handle, reject it.
28121 const GlobalValue *GV = GA->getGlobal();
28122 // If we require an extra load to get this address, as in PIC mode, we
28123 // can't accept it.
28124 if (isGlobalStubReference(
28125 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
28128 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
28129 GA->getValueType(0), Offset);
28134 if (Result.getNode()) {
28135 Ops.push_back(Result);
28138 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
28141 std::pair<unsigned, const TargetRegisterClass *>
28142 X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
28143 StringRef Constraint,
28145 // First, see if this is a constraint that directly corresponds to an LLVM
28147 if (Constraint.size() == 1) {
28148 // GCC Constraint Letters
28149 switch (Constraint[0]) {
28151 // TODO: Slight differences here in allocation order and leaving
28152 // RIP in the class. Do they matter any more here than they do
28153 // in the normal allocation?
28154 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
28155 if (Subtarget->is64Bit()) {
28156 if (VT == MVT::i32 || VT == MVT::f32)
28157 return std::make_pair(0U, &X86::GR32RegClass);
28158 if (VT == MVT::i16)
28159 return std::make_pair(0U, &X86::GR16RegClass);
28160 if (VT == MVT::i8 || VT == MVT::i1)
28161 return std::make_pair(0U, &X86::GR8RegClass);
28162 if (VT == MVT::i64 || VT == MVT::f64)
28163 return std::make_pair(0U, &X86::GR64RegClass);
28166 // 32-bit fallthrough
28167 case 'Q': // Q_REGS
28168 if (VT == MVT::i32 || VT == MVT::f32)
28169 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
28170 if (VT == MVT::i16)
28171 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
28172 if (VT == MVT::i8 || VT == MVT::i1)
28173 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
28174 if (VT == MVT::i64)
28175 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
28177 case 'r': // GENERAL_REGS
28178 case 'l': // INDEX_REGS
28179 if (VT == MVT::i8 || VT == MVT::i1)
28180 return std::make_pair(0U, &X86::GR8RegClass);
28181 if (VT == MVT::i16)
28182 return std::make_pair(0U, &X86::GR16RegClass);
28183 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
28184 return std::make_pair(0U, &X86::GR32RegClass);
28185 return std::make_pair(0U, &X86::GR64RegClass);
28186 case 'R': // LEGACY_REGS
28187 if (VT == MVT::i8 || VT == MVT::i1)
28188 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
28189 if (VT == MVT::i16)
28190 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
28191 if (VT == MVT::i32 || !Subtarget->is64Bit())
28192 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
28193 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
28194 case 'f': // FP Stack registers.
28195 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
28196 // value to the correct fpstack register class.
28197 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
28198 return std::make_pair(0U, &X86::RFP32RegClass);
28199 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
28200 return std::make_pair(0U, &X86::RFP64RegClass);
28201 return std::make_pair(0U, &X86::RFP80RegClass);
28202 case 'y': // MMX_REGS if MMX allowed.
28203 if (!Subtarget->hasMMX()) break;
28204 return std::make_pair(0U, &X86::VR64RegClass);
28205 case 'Y': // SSE_REGS if SSE2 allowed
28206 if (!Subtarget->hasSSE2()) break;
28208 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
28209 if (!Subtarget->hasSSE1()) break;
28211 switch (VT.SimpleTy) {
28213 // Scalar SSE types.
28216 return std::make_pair(0U, &X86::FR32RegClass);
28219 return std::make_pair(0U, &X86::FR64RegClass);
28220 // TODO: Handle f128 and i128 in FR128RegClass after it is tested well.
28228 return std::make_pair(0U, &X86::VR128RegClass);
28236 return std::make_pair(0U, &X86::VR256RegClass);
28241 return std::make_pair(0U, &X86::VR512RegClass);
28247 // Use the default implementation in TargetLowering to convert the register
28248 // constraint into a member of a register class.
28249 std::pair<unsigned, const TargetRegisterClass*> Res;
28250 Res = TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
28252 // Not found as a standard register?
28254 // Map st(0) -> st(7) -> ST0
28255 if (Constraint.size() == 7 && Constraint[0] == '{' &&
28256 tolower(Constraint[1]) == 's' &&
28257 tolower(Constraint[2]) == 't' &&
28258 Constraint[3] == '(' &&
28259 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
28260 Constraint[5] == ')' &&
28261 Constraint[6] == '}') {
28263 Res.first = X86::FP0+Constraint[4]-'0';
28264 Res.second = &X86::RFP80RegClass;
28268 // GCC allows "st(0)" to be called just plain "st".
28269 if (StringRef("{st}").equals_lower(Constraint)) {
28270 Res.first = X86::FP0;
28271 Res.second = &X86::RFP80RegClass;
28276 if (StringRef("{flags}").equals_lower(Constraint)) {
28277 Res.first = X86::EFLAGS;
28278 Res.second = &X86::CCRRegClass;
28282 // 'A' means EAX + EDX.
28283 if (Constraint == "A") {
28284 Res.first = X86::EAX;
28285 Res.second = &X86::GR32_ADRegClass;
28291 // Otherwise, check to see if this is a register class of the wrong value
28292 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
28293 // turn into {ax},{dx}.
28294 // MVT::Other is used to specify clobber names.
28295 if (Res.second->hasType(VT) || VT == MVT::Other)
28296 return Res; // Correct type already, nothing to do.
28298 // Get a matching integer of the correct size. i.e. "ax" with MVT::32 should
28299 // return "eax". This should even work for things like getting 64bit integer
28300 // registers when given an f64 type.
28301 const TargetRegisterClass *Class = Res.second;
28302 if (Class == &X86::GR8RegClass || Class == &X86::GR16RegClass ||
28303 Class == &X86::GR32RegClass || Class == &X86::GR64RegClass) {
28304 unsigned Size = VT.getSizeInBits();
28305 MVT::SimpleValueType SimpleTy = Size == 1 || Size == 8 ? MVT::i8
28306 : Size == 16 ? MVT::i16
28307 : Size == 32 ? MVT::i32
28308 : Size == 64 ? MVT::i64
28310 unsigned DestReg = getX86SubSuperRegisterOrZero(Res.first, SimpleTy);
28312 Res.first = DestReg;
28313 Res.second = SimpleTy == MVT::i8 ? &X86::GR8RegClass
28314 : SimpleTy == MVT::i16 ? &X86::GR16RegClass
28315 : SimpleTy == MVT::i32 ? &X86::GR32RegClass
28316 : &X86::GR64RegClass;
28317 assert(Res.second->contains(Res.first) && "Register in register class");
28319 // No register found/type mismatch.
28321 Res.second = nullptr;
28323 } else if (Class == &X86::FR32RegClass || Class == &X86::FR64RegClass ||
28324 Class == &X86::VR128RegClass || Class == &X86::VR256RegClass ||
28325 Class == &X86::FR32XRegClass || Class == &X86::FR64XRegClass ||
28326 Class == &X86::VR128XRegClass || Class == &X86::VR256XRegClass ||
28327 Class == &X86::VR512RegClass) {
28328 // Handle references to XMM physical registers that got mapped into the
28329 // wrong class. This can happen with constraints like {xmm0} where the
28330 // target independent register mapper will just pick the first match it can
28331 // find, ignoring the required type.
28333 // TODO: Handle f128 and i128 in FR128RegClass after it is tested well.
28334 if (VT == MVT::f32 || VT == MVT::i32)
28335 Res.second = &X86::FR32RegClass;
28336 else if (VT == MVT::f64 || VT == MVT::i64)
28337 Res.second = &X86::FR64RegClass;
28338 else if (X86::VR128RegClass.hasType(VT))
28339 Res.second = &X86::VR128RegClass;
28340 else if (X86::VR256RegClass.hasType(VT))
28341 Res.second = &X86::VR256RegClass;
28342 else if (X86::VR512RegClass.hasType(VT))
28343 Res.second = &X86::VR512RegClass;
28345 // Type mismatch and not a clobber: Return an error;
28347 Res.second = nullptr;
28354 int X86TargetLowering::getScalingFactorCost(const DataLayout &DL,
28355 const AddrMode &AM, Type *Ty,
28356 unsigned AS) const {
28357 // Scaling factors are not free at all.
28358 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
28359 // will take 2 allocations in the out of order engine instead of 1
28360 // for plain addressing mode, i.e. inst (reg1).
28362 // vaddps (%rsi,%drx), %ymm0, %ymm1
28363 // Requires two allocations (one for the load, one for the computation)
28365 // vaddps (%rsi), %ymm0, %ymm1
28366 // Requires just 1 allocation, i.e., freeing allocations for other operations
28367 // and having less micro operations to execute.
28369 // For some X86 architectures, this is even worse because for instance for
28370 // stores, the complex addressing mode forces the instruction to use the
28371 // "load" ports instead of the dedicated "store" port.
28372 // E.g., on Haswell:
28373 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
28374 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
28375 if (isLegalAddressingMode(DL, AM, Ty, AS))
28376 // Scale represents reg2 * scale, thus account for 1
28377 // as soon as we use a second register.
28378 return AM.Scale != 0;
28382 bool X86TargetLowering::isIntDivCheap(EVT VT, AttributeSet Attr) const {
28383 // Integer division on x86 is expensive. However, when aggressively optimizing
28384 // for code size, we prefer to use a div instruction, as it is usually smaller
28385 // than the alternative sequence.
28386 // The exception to this is vector division. Since x86 doesn't have vector
28387 // integer division, leaving the division as-is is a loss even in terms of
28388 // size, because it will have to be scalarized, while the alternative code
28389 // sequence can be performed in vector form.
28390 bool OptSize = Attr.hasAttribute(AttributeSet::FunctionIndex,
28391 Attribute::MinSize);
28392 return OptSize && !VT.isVector();
28395 void X86TargetLowering::markInRegArguments(SelectionDAG &DAG,
28396 TargetLowering::ArgListTy& Args) const {
28397 // The MCU psABI requires some arguments to be passed in-register.
28398 // For regular calls, the inreg arguments are marked by the front-end.
28399 // However, for compiler generated library calls, we have to patch this
28401 if (!Subtarget->isTargetMCU() || !Args.size())
28404 unsigned FreeRegs = 3;
28405 for (auto &Arg : Args) {
28406 // For library functions, we do not expect any fancy types.
28407 unsigned Size = DAG.getDataLayout().getTypeSizeInBits(Arg.Ty);
28408 unsigned SizeInRegs = (Size + 31) / 32;
28409 if (SizeInRegs > 2 || SizeInRegs > FreeRegs)
28412 Arg.isInReg = true;
28413 FreeRegs -= SizeInRegs;