1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
16 #include "X86InstrBuilder.h"
17 #include "X86ISelLowering.h"
18 #include "X86TargetMachine.h"
19 #include "X86TargetObjectFile.h"
20 #include "llvm/CallingConv.h"
21 #include "llvm/Constants.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/GlobalAlias.h"
24 #include "llvm/GlobalVariable.h"
25 #include "llvm/Function.h"
26 #include "llvm/Instructions.h"
27 #include "llvm/Intrinsics.h"
28 #include "llvm/LLVMContext.h"
29 #include "llvm/ADT/BitVector.h"
30 #include "llvm/ADT/VectorExtras.h"
31 #include "llvm/CodeGen/MachineFrameInfo.h"
32 #include "llvm/CodeGen/MachineFunction.h"
33 #include "llvm/CodeGen/MachineInstrBuilder.h"
34 #include "llvm/CodeGen/MachineModuleInfo.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/PseudoSourceValue.h"
37 #include "llvm/Support/MathExtras.h"
38 #include "llvm/Support/Debug.h"
39 #include "llvm/Support/ErrorHandling.h"
40 #include "llvm/Target/TargetOptions.h"
41 #include "llvm/ADT/SmallSet.h"
42 #include "llvm/ADT/StringExtras.h"
43 #include "llvm/Support/CommandLine.h"
44 #include "llvm/Support/raw_ostream.h"
48 DisableMMX("disable-mmx", cl::Hidden, cl::desc("Disable use of MMX"));
50 // Disable16Bit - 16-bit operations typically have a larger encoding than
51 // corresponding 32-bit instructions, and 16-bit code is slow on some
52 // processors. This is an experimental flag to disable 16-bit operations
53 // (which forces them to be Legalized to 32-bit operations).
55 Disable16Bit("disable-16bit", cl::Hidden,
56 cl::desc("Disable use of 16-bit instructions"));
58 // Forward declarations.
59 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
62 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
63 switch (TM.getSubtarget<X86Subtarget>().TargetType) {
64 default: llvm_unreachable("unknown subtarget type");
65 case X86Subtarget::isDarwin:
66 if (TM.getSubtarget<X86Subtarget>().is64Bit())
67 return new X8664_MachoTargetObjectFile();
68 return new X8632_MachoTargetObjectFile();
69 case X86Subtarget::isELF:
70 return new TargetLoweringObjectFileELF();
71 case X86Subtarget::isMingw:
72 case X86Subtarget::isCygwin:
73 case X86Subtarget::isWindows:
74 return new TargetLoweringObjectFileCOFF();
79 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
80 : TargetLowering(TM, createTLOF(TM)) {
81 Subtarget = &TM.getSubtarget<X86Subtarget>();
82 X86ScalarSSEf64 = Subtarget->hasSSE2();
83 X86ScalarSSEf32 = Subtarget->hasSSE1();
84 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
86 RegInfo = TM.getRegisterInfo();
89 // Set up the TargetLowering object.
91 // X86 is weird, it always uses i8 for shift amounts and setcc results.
92 setShiftAmountType(MVT::i8);
93 setBooleanContents(ZeroOrOneBooleanContent);
94 setSchedulingPreference(SchedulingForRegPressure);
95 setStackPointerRegisterToSaveRestore(X86StackPtr);
97 if (Subtarget->isTargetDarwin()) {
98 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
99 setUseUnderscoreSetJmp(false);
100 setUseUnderscoreLongJmp(false);
101 } else if (Subtarget->isTargetMingw()) {
102 // MS runtime is weird: it exports _setjmp, but longjmp!
103 setUseUnderscoreSetJmp(true);
104 setUseUnderscoreLongJmp(false);
106 setUseUnderscoreSetJmp(true);
107 setUseUnderscoreLongJmp(true);
110 // Set up the register classes.
111 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
113 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
114 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
115 if (Subtarget->is64Bit())
116 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
118 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
120 // We don't accept any truncstore of integer registers.
121 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
123 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
124 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
126 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
127 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
128 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
130 // SETOEQ and SETUNE require checking two conditions.
131 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
132 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
133 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
134 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
135 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
136 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
138 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
140 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
141 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
142 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
144 if (Subtarget->is64Bit()) {
145 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
146 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand);
147 } else if (!UseSoftFloat) {
148 if (X86ScalarSSEf64) {
149 // We have an impenetrably clever algorithm for ui64->double only.
150 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
152 // We have an algorithm for SSE2, and we turn this into a 64-bit
153 // FILD for other targets.
154 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
157 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
159 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
160 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
163 // SSE has no i16 to fp conversion, only i32
164 if (X86ScalarSSEf32) {
165 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
166 // f32 and f64 cases are Legal, f80 case is not
167 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
169 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
170 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
173 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
174 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
177 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
178 // are Legal, f80 is custom lowered.
179 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
180 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
182 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
184 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
185 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
187 if (X86ScalarSSEf32) {
188 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
189 // f32 and f64 cases are Legal, f80 case is not
190 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
192 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
193 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
196 // Handle FP_TO_UINT by promoting the destination to a larger signed
198 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
199 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
200 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
202 if (Subtarget->is64Bit()) {
203 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
204 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
205 } else if (!UseSoftFloat) {
206 if (X86ScalarSSEf32 && !Subtarget->hasSSE3())
207 // Expand FP_TO_UINT into a select.
208 // FIXME: We would like to use a Custom expander here eventually to do
209 // the optimal thing for SSE vs. the default expansion in the legalizer.
210 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
212 // With SSE3 we can use fisttpll to convert to a signed i64; without
213 // SSE, we're stuck with a fistpll.
214 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
217 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
218 if (!X86ScalarSSEf64) {
219 setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand);
220 setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand);
223 // Scalar integer divide and remainder are lowered to use operations that
224 // produce two results, to match the available instructions. This exposes
225 // the two-result form to trivial CSE, which is able to combine x/y and x%y
226 // into a single instruction.
228 // Scalar integer multiply-high is also lowered to use two-result
229 // operations, to match the available instructions. However, plain multiply
230 // (low) operations are left as Legal, as there are single-result
231 // instructions for this in x86. Using the two-result multiply instructions
232 // when both high and low results are needed must be arranged by dagcombine.
233 setOperationAction(ISD::MULHS , MVT::i8 , Expand);
234 setOperationAction(ISD::MULHU , MVT::i8 , Expand);
235 setOperationAction(ISD::SDIV , MVT::i8 , Expand);
236 setOperationAction(ISD::UDIV , MVT::i8 , Expand);
237 setOperationAction(ISD::SREM , MVT::i8 , Expand);
238 setOperationAction(ISD::UREM , MVT::i8 , Expand);
239 setOperationAction(ISD::MULHS , MVT::i16 , Expand);
240 setOperationAction(ISD::MULHU , MVT::i16 , Expand);
241 setOperationAction(ISD::SDIV , MVT::i16 , Expand);
242 setOperationAction(ISD::UDIV , MVT::i16 , Expand);
243 setOperationAction(ISD::SREM , MVT::i16 , Expand);
244 setOperationAction(ISD::UREM , MVT::i16 , Expand);
245 setOperationAction(ISD::MULHS , MVT::i32 , Expand);
246 setOperationAction(ISD::MULHU , MVT::i32 , Expand);
247 setOperationAction(ISD::SDIV , MVT::i32 , Expand);
248 setOperationAction(ISD::UDIV , MVT::i32 , Expand);
249 setOperationAction(ISD::SREM , MVT::i32 , Expand);
250 setOperationAction(ISD::UREM , MVT::i32 , Expand);
251 setOperationAction(ISD::MULHS , MVT::i64 , Expand);
252 setOperationAction(ISD::MULHU , MVT::i64 , Expand);
253 setOperationAction(ISD::SDIV , MVT::i64 , Expand);
254 setOperationAction(ISD::UDIV , MVT::i64 , Expand);
255 setOperationAction(ISD::SREM , MVT::i64 , Expand);
256 setOperationAction(ISD::UREM , MVT::i64 , Expand);
258 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
259 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
260 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
261 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
262 if (Subtarget->is64Bit())
263 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
264 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
265 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
266 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
267 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
268 setOperationAction(ISD::FREM , MVT::f32 , Expand);
269 setOperationAction(ISD::FREM , MVT::f64 , Expand);
270 setOperationAction(ISD::FREM , MVT::f80 , Expand);
271 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
273 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
274 setOperationAction(ISD::CTTZ , MVT::i8 , Custom);
275 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
276 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
278 setOperationAction(ISD::CTTZ , MVT::i16 , Expand);
279 setOperationAction(ISD::CTLZ , MVT::i16 , Expand);
281 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
282 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
284 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
285 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
286 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
287 if (Subtarget->is64Bit()) {
288 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
289 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
290 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
293 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
294 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
296 // These should be promoted to a larger select which is supported.
297 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
298 // X86 wants to expand cmov itself.
299 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
301 setOperationAction(ISD::SELECT , MVT::i16 , Expand);
303 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
304 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
305 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
306 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
307 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
308 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
310 setOperationAction(ISD::SETCC , MVT::i16 , Expand);
312 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
313 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
314 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
315 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
316 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
317 if (Subtarget->is64Bit()) {
318 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
319 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
321 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
324 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
325 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
326 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
327 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
328 if (Subtarget->is64Bit())
329 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
330 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
331 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
332 if (Subtarget->is64Bit()) {
333 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
334 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
335 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
336 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
337 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
339 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
340 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
341 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
342 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
343 if (Subtarget->is64Bit()) {
344 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
345 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
346 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
349 if (Subtarget->hasSSE1())
350 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
352 if (!Subtarget->hasSSE2())
353 setOperationAction(ISD::MEMBARRIER , MVT::Other, Expand);
355 // Expand certain atomics
356 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i8, Custom);
357 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i16, Custom);
358 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom);
359 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom);
361 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i8, Custom);
362 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i16, Custom);
363 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Custom);
364 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
366 if (!Subtarget->is64Bit()) {
367 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
368 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
369 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
370 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
371 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
372 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
373 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
376 // FIXME - use subtarget debug flags
377 if (!Subtarget->isTargetDarwin() &&
378 !Subtarget->isTargetELF() &&
379 !Subtarget->isTargetCygMing()) {
380 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
383 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
384 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
385 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
386 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
387 if (Subtarget->is64Bit()) {
388 setExceptionPointerRegister(X86::RAX);
389 setExceptionSelectorRegister(X86::RDX);
391 setExceptionPointerRegister(X86::EAX);
392 setExceptionSelectorRegister(X86::EDX);
394 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
395 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
397 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom);
399 setOperationAction(ISD::TRAP, MVT::Other, Legal);
401 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
402 setOperationAction(ISD::VASTART , MVT::Other, Custom);
403 setOperationAction(ISD::VAEND , MVT::Other, Expand);
404 if (Subtarget->is64Bit()) {
405 setOperationAction(ISD::VAARG , MVT::Other, Custom);
406 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
408 setOperationAction(ISD::VAARG , MVT::Other, Expand);
409 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
412 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
413 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
414 if (Subtarget->is64Bit())
415 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
416 if (Subtarget->isTargetCygMing())
417 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
419 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
421 if (!UseSoftFloat && X86ScalarSSEf64) {
422 // f32 and f64 use SSE.
423 // Set up the FP register classes.
424 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
425 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
427 // Use ANDPD to simulate FABS.
428 setOperationAction(ISD::FABS , MVT::f64, Custom);
429 setOperationAction(ISD::FABS , MVT::f32, Custom);
431 // Use XORP to simulate FNEG.
432 setOperationAction(ISD::FNEG , MVT::f64, Custom);
433 setOperationAction(ISD::FNEG , MVT::f32, Custom);
435 // Use ANDPD and ORPD to simulate FCOPYSIGN.
436 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
437 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
439 // We don't support sin/cos/fmod
440 setOperationAction(ISD::FSIN , MVT::f64, Expand);
441 setOperationAction(ISD::FCOS , MVT::f64, Expand);
442 setOperationAction(ISD::FSIN , MVT::f32, Expand);
443 setOperationAction(ISD::FCOS , MVT::f32, Expand);
445 // Expand FP immediates into loads from the stack, except for the special
447 addLegalFPImmediate(APFloat(+0.0)); // xorpd
448 addLegalFPImmediate(APFloat(+0.0f)); // xorps
449 } else if (!UseSoftFloat && X86ScalarSSEf32) {
450 // Use SSE for f32, x87 for f64.
451 // Set up the FP register classes.
452 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
453 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
455 // Use ANDPS to simulate FABS.
456 setOperationAction(ISD::FABS , MVT::f32, Custom);
458 // Use XORP to simulate FNEG.
459 setOperationAction(ISD::FNEG , MVT::f32, Custom);
461 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
463 // Use ANDPS and ORPS to simulate FCOPYSIGN.
464 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
465 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
467 // We don't support sin/cos/fmod
468 setOperationAction(ISD::FSIN , MVT::f32, Expand);
469 setOperationAction(ISD::FCOS , MVT::f32, Expand);
471 // Special cases we handle for FP constants.
472 addLegalFPImmediate(APFloat(+0.0f)); // xorps
473 addLegalFPImmediate(APFloat(+0.0)); // FLD0
474 addLegalFPImmediate(APFloat(+1.0)); // FLD1
475 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
476 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
479 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
480 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
482 } else if (!UseSoftFloat) {
483 // f32 and f64 in x87.
484 // Set up the FP register classes.
485 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
486 addRegisterClass(MVT::f32, X86::RFP32RegisterClass);
488 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
489 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
490 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
491 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
494 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
495 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
497 addLegalFPImmediate(APFloat(+0.0)); // FLD0
498 addLegalFPImmediate(APFloat(+1.0)); // FLD1
499 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
500 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
501 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
502 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
503 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
504 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
507 // Long double always uses X87.
509 addRegisterClass(MVT::f80, X86::RFP80RegisterClass);
510 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
511 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
514 APFloat TmpFlt(+0.0);
515 TmpFlt.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
517 addLegalFPImmediate(TmpFlt); // FLD0
519 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
520 APFloat TmpFlt2(+1.0);
521 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
523 addLegalFPImmediate(TmpFlt2); // FLD1
524 TmpFlt2.changeSign();
525 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
529 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
530 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
534 // Always use a library call for pow.
535 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
536 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
537 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
539 setOperationAction(ISD::FLOG, MVT::f80, Expand);
540 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
541 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
542 setOperationAction(ISD::FEXP, MVT::f80, Expand);
543 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
545 // First set operation action for all vector types to either promote
546 // (for widening) or expand (for scalarization). Then we will selectively
547 // turn on ones that can be effectively codegen'd.
548 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
549 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
550 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
551 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
552 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
553 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
554 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
555 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
556 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
557 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
558 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
559 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
560 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
561 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
562 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
563 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
564 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
565 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
566 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
567 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
568 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
569 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
570 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
571 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
572 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
573 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
574 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
575 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
576 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
577 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
578 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
579 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
580 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
581 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
582 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
583 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
584 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
585 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
586 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
587 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
588 setOperationAction(ISD::VSETCC, (MVT::SimpleValueType)VT, Expand);
589 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
590 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
591 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
592 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand);
593 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand);
594 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand);
595 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand);
596 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
597 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
598 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand);
599 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand);
600 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand);
601 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand);
602 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand);
603 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
604 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
605 setTruncStoreAction((MVT::SimpleValueType)VT,
606 (MVT::SimpleValueType)InnerVT, Expand);
607 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
608 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
609 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
612 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
613 // with -msoft-float, disable use of MMX as well.
614 if (!UseSoftFloat && !DisableMMX && Subtarget->hasMMX()) {
615 addRegisterClass(MVT::v8i8, X86::VR64RegisterClass);
616 addRegisterClass(MVT::v4i16, X86::VR64RegisterClass);
617 addRegisterClass(MVT::v2i32, X86::VR64RegisterClass);
618 addRegisterClass(MVT::v2f32, X86::VR64RegisterClass);
619 addRegisterClass(MVT::v1i64, X86::VR64RegisterClass);
621 setOperationAction(ISD::ADD, MVT::v8i8, Legal);
622 setOperationAction(ISD::ADD, MVT::v4i16, Legal);
623 setOperationAction(ISD::ADD, MVT::v2i32, Legal);
624 setOperationAction(ISD::ADD, MVT::v1i64, Legal);
626 setOperationAction(ISD::SUB, MVT::v8i8, Legal);
627 setOperationAction(ISD::SUB, MVT::v4i16, Legal);
628 setOperationAction(ISD::SUB, MVT::v2i32, Legal);
629 setOperationAction(ISD::SUB, MVT::v1i64, Legal);
631 setOperationAction(ISD::MULHS, MVT::v4i16, Legal);
632 setOperationAction(ISD::MUL, MVT::v4i16, Legal);
634 setOperationAction(ISD::AND, MVT::v8i8, Promote);
635 AddPromotedToType (ISD::AND, MVT::v8i8, MVT::v1i64);
636 setOperationAction(ISD::AND, MVT::v4i16, Promote);
637 AddPromotedToType (ISD::AND, MVT::v4i16, MVT::v1i64);
638 setOperationAction(ISD::AND, MVT::v2i32, Promote);
639 AddPromotedToType (ISD::AND, MVT::v2i32, MVT::v1i64);
640 setOperationAction(ISD::AND, MVT::v1i64, Legal);
642 setOperationAction(ISD::OR, MVT::v8i8, Promote);
643 AddPromotedToType (ISD::OR, MVT::v8i8, MVT::v1i64);
644 setOperationAction(ISD::OR, MVT::v4i16, Promote);
645 AddPromotedToType (ISD::OR, MVT::v4i16, MVT::v1i64);
646 setOperationAction(ISD::OR, MVT::v2i32, Promote);
647 AddPromotedToType (ISD::OR, MVT::v2i32, MVT::v1i64);
648 setOperationAction(ISD::OR, MVT::v1i64, Legal);
650 setOperationAction(ISD::XOR, MVT::v8i8, Promote);
651 AddPromotedToType (ISD::XOR, MVT::v8i8, MVT::v1i64);
652 setOperationAction(ISD::XOR, MVT::v4i16, Promote);
653 AddPromotedToType (ISD::XOR, MVT::v4i16, MVT::v1i64);
654 setOperationAction(ISD::XOR, MVT::v2i32, Promote);
655 AddPromotedToType (ISD::XOR, MVT::v2i32, MVT::v1i64);
656 setOperationAction(ISD::XOR, MVT::v1i64, Legal);
658 setOperationAction(ISD::LOAD, MVT::v8i8, Promote);
659 AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v1i64);
660 setOperationAction(ISD::LOAD, MVT::v4i16, Promote);
661 AddPromotedToType (ISD::LOAD, MVT::v4i16, MVT::v1i64);
662 setOperationAction(ISD::LOAD, MVT::v2i32, Promote);
663 AddPromotedToType (ISD::LOAD, MVT::v2i32, MVT::v1i64);
664 setOperationAction(ISD::LOAD, MVT::v2f32, Promote);
665 AddPromotedToType (ISD::LOAD, MVT::v2f32, MVT::v1i64);
666 setOperationAction(ISD::LOAD, MVT::v1i64, Legal);
668 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Custom);
669 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom);
670 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Custom);
671 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f32, Custom);
672 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i64, Custom);
674 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom);
675 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
676 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i32, Custom);
677 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v1i64, Custom);
679 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f32, Custom);
680 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Custom);
681 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Custom);
682 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Custom);
684 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i16, Custom);
686 setOperationAction(ISD::SELECT, MVT::v8i8, Promote);
687 setOperationAction(ISD::SELECT, MVT::v4i16, Promote);
688 setOperationAction(ISD::SELECT, MVT::v2i32, Promote);
689 setOperationAction(ISD::SELECT, MVT::v1i64, Custom);
690 setOperationAction(ISD::VSETCC, MVT::v8i8, Custom);
691 setOperationAction(ISD::VSETCC, MVT::v4i16, Custom);
692 setOperationAction(ISD::VSETCC, MVT::v2i32, Custom);
695 if (!UseSoftFloat && Subtarget->hasSSE1()) {
696 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
698 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
699 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
700 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
701 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
702 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
703 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
704 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
705 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
706 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
707 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
708 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
709 setOperationAction(ISD::VSETCC, MVT::v4f32, Custom);
712 if (!UseSoftFloat && Subtarget->hasSSE2()) {
713 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
715 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
716 // registers cannot be used even for integer operations.
717 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
718 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
719 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
720 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
722 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
723 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
724 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
725 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
726 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
727 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
728 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
729 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
730 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
731 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
732 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
733 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
734 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
735 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
736 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
737 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
739 setOperationAction(ISD::VSETCC, MVT::v2f64, Custom);
740 setOperationAction(ISD::VSETCC, MVT::v16i8, Custom);
741 setOperationAction(ISD::VSETCC, MVT::v8i16, Custom);
742 setOperationAction(ISD::VSETCC, MVT::v4i32, Custom);
744 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
745 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
746 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
747 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
748 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
750 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
751 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) {
752 EVT VT = (MVT::SimpleValueType)i;
753 // Do not attempt to custom lower non-power-of-2 vectors
754 if (!isPowerOf2_32(VT.getVectorNumElements()))
756 // Do not attempt to custom lower non-128-bit vectors
757 if (!VT.is128BitVector())
759 setOperationAction(ISD::BUILD_VECTOR,
760 VT.getSimpleVT().SimpleTy, Custom);
761 setOperationAction(ISD::VECTOR_SHUFFLE,
762 VT.getSimpleVT().SimpleTy, Custom);
763 setOperationAction(ISD::EXTRACT_VECTOR_ELT,
764 VT.getSimpleVT().SimpleTy, Custom);
767 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
768 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
769 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
770 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
771 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
772 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
774 if (Subtarget->is64Bit()) {
775 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
776 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
779 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
780 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) {
781 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
784 // Do not attempt to promote non-128-bit vectors
785 if (!VT.is128BitVector()) {
788 setOperationAction(ISD::AND, SVT, Promote);
789 AddPromotedToType (ISD::AND, SVT, MVT::v2i64);
790 setOperationAction(ISD::OR, SVT, Promote);
791 AddPromotedToType (ISD::OR, SVT, MVT::v2i64);
792 setOperationAction(ISD::XOR, SVT, Promote);
793 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64);
794 setOperationAction(ISD::LOAD, SVT, Promote);
795 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64);
796 setOperationAction(ISD::SELECT, SVT, Promote);
797 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64);
800 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
802 // Custom lower v2i64 and v2f64 selects.
803 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
804 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
805 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
806 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
808 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
809 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
810 if (!DisableMMX && Subtarget->hasMMX()) {
811 setOperationAction(ISD::FP_TO_SINT, MVT::v2i32, Custom);
812 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
816 if (Subtarget->hasSSE41()) {
817 // FIXME: Do we need to handle scalar-to-vector here?
818 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
820 // i8 and i16 vectors are custom , because the source register and source
821 // source memory operand types are not the same width. f32 vectors are
822 // custom since the immediate controlling the insert encodes additional
824 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
825 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
826 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
827 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
829 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
830 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
831 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
832 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
834 if (Subtarget->is64Bit()) {
835 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal);
836 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal);
840 if (Subtarget->hasSSE42()) {
841 setOperationAction(ISD::VSETCC, MVT::v2i64, Custom);
844 if (!UseSoftFloat && Subtarget->hasAVX()) {
845 addRegisterClass(MVT::v8f32, X86::VR256RegisterClass);
846 addRegisterClass(MVT::v4f64, X86::VR256RegisterClass);
847 addRegisterClass(MVT::v8i32, X86::VR256RegisterClass);
848 addRegisterClass(MVT::v4i64, X86::VR256RegisterClass);
850 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
851 setOperationAction(ISD::LOAD, MVT::v8i32, Legal);
852 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
853 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
854 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
855 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
856 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
857 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
858 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
859 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
860 //setOperationAction(ISD::BUILD_VECTOR, MVT::v8f32, Custom);
861 //setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Custom);
862 //setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8f32, Custom);
863 //setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
864 //setOperationAction(ISD::VSETCC, MVT::v8f32, Custom);
866 // Operations to consider commented out -v16i16 v32i8
867 //setOperationAction(ISD::ADD, MVT::v16i16, Legal);
868 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
869 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
870 //setOperationAction(ISD::SUB, MVT::v32i8, Legal);
871 //setOperationAction(ISD::SUB, MVT::v16i16, Legal);
872 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
873 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
874 //setOperationAction(ISD::MUL, MVT::v16i16, Legal);
875 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
876 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
877 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
878 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
879 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
880 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
882 setOperationAction(ISD::VSETCC, MVT::v4f64, Custom);
883 // setOperationAction(ISD::VSETCC, MVT::v32i8, Custom);
884 // setOperationAction(ISD::VSETCC, MVT::v16i16, Custom);
885 setOperationAction(ISD::VSETCC, MVT::v8i32, Custom);
887 // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v32i8, Custom);
888 // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i16, Custom);
889 // setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i16, Custom);
890 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i32, Custom);
891 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8f32, Custom);
893 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f64, Custom);
894 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i64, Custom);
895 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f64, Custom);
896 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i64, Custom);
897 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f64, Custom);
898 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f64, Custom);
901 // Not sure we want to do this since there are no 256-bit integer
904 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
905 // This includes 256-bit vectors
906 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; ++i) {
907 EVT VT = (MVT::SimpleValueType)i;
909 // Do not attempt to custom lower non-power-of-2 vectors
910 if (!isPowerOf2_32(VT.getVectorNumElements()))
913 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
914 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
915 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
918 if (Subtarget->is64Bit()) {
919 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i64, Custom);
920 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i64, Custom);
925 // Not sure we want to do this since there are no 256-bit integer
928 // Promote v32i8, v16i16, v8i32 load, select, and, or, xor to v4i64.
929 // Including 256-bit vectors
930 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; i++) {
931 EVT VT = (MVT::SimpleValueType)i;
933 if (!VT.is256BitVector()) {
936 setOperationAction(ISD::AND, VT, Promote);
937 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
938 setOperationAction(ISD::OR, VT, Promote);
939 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
940 setOperationAction(ISD::XOR, VT, Promote);
941 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
942 setOperationAction(ISD::LOAD, VT, Promote);
943 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
944 setOperationAction(ISD::SELECT, VT, Promote);
945 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
948 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
952 // We want to custom lower some of our intrinsics.
953 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
955 // Add/Sub/Mul with overflow operations are custom lowered.
956 setOperationAction(ISD::SADDO, MVT::i32, Custom);
957 setOperationAction(ISD::SADDO, MVT::i64, Custom);
958 setOperationAction(ISD::UADDO, MVT::i32, Custom);
959 setOperationAction(ISD::UADDO, MVT::i64, Custom);
960 setOperationAction(ISD::SSUBO, MVT::i32, Custom);
961 setOperationAction(ISD::SSUBO, MVT::i64, Custom);
962 setOperationAction(ISD::USUBO, MVT::i32, Custom);
963 setOperationAction(ISD::USUBO, MVT::i64, Custom);
964 setOperationAction(ISD::SMULO, MVT::i32, Custom);
965 setOperationAction(ISD::SMULO, MVT::i64, Custom);
967 if (!Subtarget->is64Bit()) {
968 // These libcalls are not available in 32-bit.
969 setLibcallName(RTLIB::SHL_I128, 0);
970 setLibcallName(RTLIB::SRL_I128, 0);
971 setLibcallName(RTLIB::SRA_I128, 0);
974 // We have target-specific dag combine patterns for the following nodes:
975 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
976 setTargetDAGCombine(ISD::BUILD_VECTOR);
977 setTargetDAGCombine(ISD::SELECT);
978 setTargetDAGCombine(ISD::SHL);
979 setTargetDAGCombine(ISD::SRA);
980 setTargetDAGCombine(ISD::SRL);
981 setTargetDAGCombine(ISD::OR);
982 setTargetDAGCombine(ISD::STORE);
983 setTargetDAGCombine(ISD::MEMBARRIER);
984 setTargetDAGCombine(ISD::ZERO_EXTEND);
985 if (Subtarget->is64Bit())
986 setTargetDAGCombine(ISD::MUL);
988 computeRegisterProperties();
990 // Divide and reminder operations have no vector equivalent and can
991 // trap. Do a custom widening for these operations in which we never
992 // generate more divides/remainder than the original vector width.
993 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
994 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
995 if (!isTypeLegal((MVT::SimpleValueType)VT)) {
996 setOperationAction(ISD::SDIV, (MVT::SimpleValueType) VT, Custom);
997 setOperationAction(ISD::UDIV, (MVT::SimpleValueType) VT, Custom);
998 setOperationAction(ISD::SREM, (MVT::SimpleValueType) VT, Custom);
999 setOperationAction(ISD::UREM, (MVT::SimpleValueType) VT, Custom);
1003 // FIXME: These should be based on subtarget info. Plus, the values should
1004 // be smaller when we are in optimizing for size mode.
1005 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1006 maxStoresPerMemcpy = 16; // For @llvm.memcpy -> sequence of stores
1007 maxStoresPerMemmove = 3; // For @llvm.memmove -> sequence of stores
1008 setPrefLoopAlignment(16);
1009 benefitFromCodePlacementOpt = true;
1013 MVT::SimpleValueType X86TargetLowering::getSetCCResultType(EVT VT) const {
1018 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1019 /// the desired ByVal argument alignment.
1020 static void getMaxByValAlign(const Type *Ty, unsigned &MaxAlign) {
1023 if (const VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1024 if (VTy->getBitWidth() == 128)
1026 } else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1027 unsigned EltAlign = 0;
1028 getMaxByValAlign(ATy->getElementType(), EltAlign);
1029 if (EltAlign > MaxAlign)
1030 MaxAlign = EltAlign;
1031 } else if (const StructType *STy = dyn_cast<StructType>(Ty)) {
1032 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1033 unsigned EltAlign = 0;
1034 getMaxByValAlign(STy->getElementType(i), EltAlign);
1035 if (EltAlign > MaxAlign)
1036 MaxAlign = EltAlign;
1044 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1045 /// function arguments in the caller parameter area. For X86, aggregates
1046 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1047 /// are at 4-byte boundaries.
1048 unsigned X86TargetLowering::getByValTypeAlignment(const Type *Ty) const {
1049 if (Subtarget->is64Bit()) {
1050 // Max of 8 and alignment of type.
1051 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1058 if (Subtarget->hasSSE1())
1059 getMaxByValAlign(Ty, Align);
1063 /// getOptimalMemOpType - Returns the target specific optimal type for load
1064 /// and store operations as a result of memset, memcpy, and memmove
1065 /// lowering. It returns MVT::iAny if SelectionDAG should be responsible for
1068 X86TargetLowering::getOptimalMemOpType(uint64_t Size, unsigned Align,
1069 bool isSrcConst, bool isSrcStr,
1070 SelectionDAG &DAG) const {
1071 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like
1072 // linux. This is because the stack realignment code can't handle certain
1073 // cases like PR2962. This should be removed when PR2962 is fixed.
1074 const Function *F = DAG.getMachineFunction().getFunction();
1075 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
1076 if (!NoImplicitFloatOps && Subtarget->getStackAlignment() >= 16) {
1077 if ((isSrcConst || isSrcStr) && Subtarget->hasSSE2() && Size >= 16)
1079 if ((isSrcConst || isSrcStr) && Subtarget->hasSSE1() && Size >= 16)
1082 if (Subtarget->is64Bit() && Size >= 8)
1087 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1089 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1090 SelectionDAG &DAG) const {
1091 if (usesGlobalOffsetTable())
1092 return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy());
1093 if (!Subtarget->is64Bit())
1094 // This doesn't have DebugLoc associated with it, but is not really the
1095 // same as a Register.
1096 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc::getUnknownLoc(),
1101 /// getFunctionAlignment - Return the Log2 alignment of this function.
1102 unsigned X86TargetLowering::getFunctionAlignment(const Function *F) const {
1103 return F->hasFnAttr(Attribute::OptimizeForSize) ? 0 : 4;
1106 //===----------------------------------------------------------------------===//
1107 // Return Value Calling Convention Implementation
1108 //===----------------------------------------------------------------------===//
1110 #include "X86GenCallingConv.inc"
1113 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
1114 const SmallVectorImpl<EVT> &OutTys,
1115 const SmallVectorImpl<ISD::ArgFlagsTy> &ArgsFlags,
1116 SelectionDAG &DAG) {
1117 SmallVector<CCValAssign, 16> RVLocs;
1118 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1119 RVLocs, *DAG.getContext());
1120 return CCInfo.CheckReturn(OutTys, ArgsFlags, RetCC_X86);
1124 X86TargetLowering::LowerReturn(SDValue Chain,
1125 CallingConv::ID CallConv, bool isVarArg,
1126 const SmallVectorImpl<ISD::OutputArg> &Outs,
1127 DebugLoc dl, SelectionDAG &DAG) {
1129 SmallVector<CCValAssign, 16> RVLocs;
1130 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1131 RVLocs, *DAG.getContext());
1132 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1134 // If this is the first return lowered for this function, add the regs to the
1135 // liveout set for the function.
1136 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1137 for (unsigned i = 0; i != RVLocs.size(); ++i)
1138 if (RVLocs[i].isRegLoc())
1139 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1144 SmallVector<SDValue, 6> RetOps;
1145 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1146 // Operand #1 = Bytes To Pop
1147 RetOps.push_back(DAG.getTargetConstant(getBytesToPopOnReturn(), MVT::i16));
1149 // Copy the result values into the output registers.
1150 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1151 CCValAssign &VA = RVLocs[i];
1152 assert(VA.isRegLoc() && "Can only return in registers!");
1153 SDValue ValToCopy = Outs[i].Val;
1155 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1156 // the RET instruction and handled by the FP Stackifier.
1157 if (VA.getLocReg() == X86::ST0 ||
1158 VA.getLocReg() == X86::ST1) {
1159 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1160 // change the value to the FP stack register class.
1161 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1162 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1163 RetOps.push_back(ValToCopy);
1164 // Don't emit a copytoreg.
1168 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1169 // which is returned in RAX / RDX.
1170 if (Subtarget->is64Bit()) {
1171 EVT ValVT = ValToCopy.getValueType();
1172 if (ValVT.isVector() && ValVT.getSizeInBits() == 64) {
1173 ValToCopy = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, ValToCopy);
1174 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1)
1175 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, ValToCopy);
1179 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1180 Flag = Chain.getValue(1);
1183 // The x86-64 ABI for returning structs by value requires that we copy
1184 // the sret argument into %rax for the return. We saved the argument into
1185 // a virtual register in the entry block, so now we copy the value out
1187 if (Subtarget->is64Bit() &&
1188 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1189 MachineFunction &MF = DAG.getMachineFunction();
1190 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1191 unsigned Reg = FuncInfo->getSRetReturnReg();
1193 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1194 FuncInfo->setSRetReturnReg(Reg);
1196 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1198 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag);
1199 Flag = Chain.getValue(1);
1201 // RAX now acts like a return value.
1202 MF.getRegInfo().addLiveOut(X86::RAX);
1205 RetOps[0] = Chain; // Update chain.
1207 // Add the flag if we have it.
1209 RetOps.push_back(Flag);
1211 return DAG.getNode(X86ISD::RET_FLAG, dl,
1212 MVT::Other, &RetOps[0], RetOps.size());
1215 /// LowerCallResult - Lower the result values of a call into the
1216 /// appropriate copies out of appropriate physical registers.
1219 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1220 CallingConv::ID CallConv, bool isVarArg,
1221 const SmallVectorImpl<ISD::InputArg> &Ins,
1222 DebugLoc dl, SelectionDAG &DAG,
1223 SmallVectorImpl<SDValue> &InVals) {
1225 // Assign locations to each value returned by this call.
1226 SmallVector<CCValAssign, 16> RVLocs;
1227 bool Is64Bit = Subtarget->is64Bit();
1228 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1229 RVLocs, *DAG.getContext());
1230 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1232 // Copy all of the result registers out of their specified physreg.
1233 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1234 CCValAssign &VA = RVLocs[i];
1235 EVT CopyVT = VA.getValVT();
1237 // If this is x86-64, and we disabled SSE, we can't return FP values
1238 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1239 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
1240 llvm_report_error("SSE register return with SSE disabled");
1243 // If this is a call to a function that returns an fp value on the floating
1244 // point stack, but where we prefer to use the value in xmm registers, copy
1245 // it out as F80 and use a truncate to move it from fp stack reg to xmm reg.
1246 if ((VA.getLocReg() == X86::ST0 ||
1247 VA.getLocReg() == X86::ST1) &&
1248 isScalarFPTypeInSSEReg(VA.getValVT())) {
1253 if (Is64Bit && CopyVT.isVector() && CopyVT.getSizeInBits() == 64) {
1254 // For x86-64, MMX values are returned in XMM0 / XMM1 except for v1i64.
1255 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1256 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1257 MVT::v2i64, InFlag).getValue(1);
1258 Val = Chain.getValue(0);
1259 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64,
1260 Val, DAG.getConstant(0, MVT::i64));
1262 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1263 MVT::i64, InFlag).getValue(1);
1264 Val = Chain.getValue(0);
1266 Val = DAG.getNode(ISD::BIT_CONVERT, dl, CopyVT, Val);
1268 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1269 CopyVT, InFlag).getValue(1);
1270 Val = Chain.getValue(0);
1272 InFlag = Chain.getValue(2);
1274 if (CopyVT != VA.getValVT()) {
1275 // Round the F80 the right size, which also moves to the appropriate xmm
1277 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1278 // This truncation won't change the value.
1279 DAG.getIntPtrConstant(1));
1282 InVals.push_back(Val);
1289 //===----------------------------------------------------------------------===//
1290 // C & StdCall & Fast Calling Convention implementation
1291 //===----------------------------------------------------------------------===//
1292 // StdCall calling convention seems to be standard for many Windows' API
1293 // routines and around. It differs from C calling convention just a little:
1294 // callee should clean up the stack, not caller. Symbols should be also
1295 // decorated in some fancy way :) It doesn't support any vector arguments.
1296 // For info on fast calling convention see Fast Calling Convention (tail call)
1297 // implementation LowerX86_32FastCCCallTo.
1299 /// CallIsStructReturn - Determines whether a call uses struct return
1301 static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
1305 return Outs[0].Flags.isSRet();
1308 /// ArgsAreStructReturn - Determines whether a function uses struct
1309 /// return semantics.
1311 ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
1315 return Ins[0].Flags.isSRet();
1318 /// IsCalleePop - Determines whether the callee is required to pop its
1319 /// own arguments. Callee pop is necessary to support tail calls.
1320 bool X86TargetLowering::IsCalleePop(bool IsVarArg, CallingConv::ID CallingConv){
1324 switch (CallingConv) {
1327 case CallingConv::X86_StdCall:
1328 return !Subtarget->is64Bit();
1329 case CallingConv::X86_FastCall:
1330 return !Subtarget->is64Bit();
1331 case CallingConv::Fast:
1332 return PerformTailCallOpt;
1336 /// CCAssignFnForNode - Selects the correct CCAssignFn for a the
1337 /// given CallingConvention value.
1338 CCAssignFn *X86TargetLowering::CCAssignFnForNode(CallingConv::ID CC) const {
1339 if (Subtarget->is64Bit()) {
1340 if (Subtarget->isTargetWin64())
1341 return CC_X86_Win64_C;
1346 if (CC == CallingConv::X86_FastCall)
1347 return CC_X86_32_FastCall;
1348 else if (CC == CallingConv::Fast)
1349 return CC_X86_32_FastCC;
1354 /// NameDecorationForCallConv - Selects the appropriate decoration to
1355 /// apply to a MachineFunction containing a given calling convention.
1357 X86TargetLowering::NameDecorationForCallConv(CallingConv::ID CallConv) {
1358 if (CallConv == CallingConv::X86_FastCall)
1360 else if (CallConv == CallingConv::X86_StdCall)
1366 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1367 /// by "Src" to address "Dst" with size and alignment information specified by
1368 /// the specific parameter attribute. The copy will be passed as a byval
1369 /// function parameter.
1371 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1372 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1374 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1375 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1376 /*AlwaysInline=*/true, NULL, 0, NULL, 0);
1380 X86TargetLowering::LowerMemArgument(SDValue Chain,
1381 CallingConv::ID CallConv,
1382 const SmallVectorImpl<ISD::InputArg> &Ins,
1383 DebugLoc dl, SelectionDAG &DAG,
1384 const CCValAssign &VA,
1385 MachineFrameInfo *MFI,
1388 // Create the nodes corresponding to a load from this parameter slot.
1389 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1390 bool AlwaysUseMutable = (CallConv==CallingConv::Fast) && PerformTailCallOpt;
1391 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1394 // If value is passed by pointer we have address passed instead of the value
1396 if (VA.getLocInfo() == CCValAssign::Indirect)
1397 ValVT = VA.getLocVT();
1399 ValVT = VA.getValVT();
1401 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1402 // changed with more analysis.
1403 // In case of tail call optimization mark all arguments mutable. Since they
1404 // could be overwritten by lowering of arguments in case of a tail call.
1405 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
1406 VA.getLocMemOffset(), isImmutable, false);
1407 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1408 if (Flags.isByVal())
1410 return DAG.getLoad(ValVT, dl, Chain, FIN,
1411 PseudoSourceValue::getFixedStack(FI), 0);
1415 X86TargetLowering::LowerFormalArguments(SDValue Chain,
1416 CallingConv::ID CallConv,
1418 const SmallVectorImpl<ISD::InputArg> &Ins,
1421 SmallVectorImpl<SDValue> &InVals) {
1423 MachineFunction &MF = DAG.getMachineFunction();
1424 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1426 const Function* Fn = MF.getFunction();
1427 if (Fn->hasExternalLinkage() &&
1428 Subtarget->isTargetCygMing() &&
1429 Fn->getName() == "main")
1430 FuncInfo->setForceFramePointer(true);
1432 // Decorate the function name.
1433 FuncInfo->setDecorationStyle(NameDecorationForCallConv(CallConv));
1435 MachineFrameInfo *MFI = MF.getFrameInfo();
1436 bool Is64Bit = Subtarget->is64Bit();
1437 bool IsWin64 = Subtarget->isTargetWin64();
1439 assert(!(isVarArg && CallConv == CallingConv::Fast) &&
1440 "Var args not supported with calling convention fastcc");
1442 // Assign locations to all of the incoming arguments.
1443 SmallVector<CCValAssign, 16> ArgLocs;
1444 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1445 ArgLocs, *DAG.getContext());
1446 CCInfo.AnalyzeFormalArguments(Ins, CCAssignFnForNode(CallConv));
1448 unsigned LastVal = ~0U;
1450 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1451 CCValAssign &VA = ArgLocs[i];
1452 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1454 assert(VA.getValNo() != LastVal &&
1455 "Don't support value assigned to multiple locs yet");
1456 LastVal = VA.getValNo();
1458 if (VA.isRegLoc()) {
1459 EVT RegVT = VA.getLocVT();
1460 TargetRegisterClass *RC = NULL;
1461 if (RegVT == MVT::i32)
1462 RC = X86::GR32RegisterClass;
1463 else if (Is64Bit && RegVT == MVT::i64)
1464 RC = X86::GR64RegisterClass;
1465 else if (RegVT == MVT::f32)
1466 RC = X86::FR32RegisterClass;
1467 else if (RegVT == MVT::f64)
1468 RC = X86::FR64RegisterClass;
1469 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128)
1470 RC = X86::VR128RegisterClass;
1471 else if (RegVT.isVector() && RegVT.getSizeInBits() == 64)
1472 RC = X86::VR64RegisterClass;
1474 llvm_unreachable("Unknown argument type!");
1476 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1477 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1479 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1480 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1482 if (VA.getLocInfo() == CCValAssign::SExt)
1483 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1484 DAG.getValueType(VA.getValVT()));
1485 else if (VA.getLocInfo() == CCValAssign::ZExt)
1486 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1487 DAG.getValueType(VA.getValVT()));
1488 else if (VA.getLocInfo() == CCValAssign::BCvt)
1489 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue);
1491 if (VA.isExtInLoc()) {
1492 // Handle MMX values passed in XMM regs.
1493 if (RegVT.isVector()) {
1494 ArgValue = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64,
1495 ArgValue, DAG.getConstant(0, MVT::i64));
1496 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue);
1498 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1501 assert(VA.isMemLoc());
1502 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
1505 // If value is passed via pointer - do a load.
1506 if (VA.getLocInfo() == CCValAssign::Indirect)
1507 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue, NULL, 0);
1509 InVals.push_back(ArgValue);
1512 // The x86-64 ABI for returning structs by value requires that we copy
1513 // the sret argument into %rax for the return. Save the argument into
1514 // a virtual register so that we can access it from the return points.
1515 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) {
1516 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1517 unsigned Reg = FuncInfo->getSRetReturnReg();
1519 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1520 FuncInfo->setSRetReturnReg(Reg);
1522 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
1523 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
1526 unsigned StackSize = CCInfo.getNextStackOffset();
1527 // align stack specially for tail calls
1528 if (PerformTailCallOpt && CallConv == CallingConv::Fast)
1529 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1531 // If the function takes variable number of arguments, make a frame index for
1532 // the start of the first vararg value... for expansion of llvm.va_start.
1534 if (Is64Bit || CallConv != CallingConv::X86_FastCall) {
1535 VarArgsFrameIndex = MFI->CreateFixedObject(1, StackSize, true, false);
1538 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
1540 // FIXME: We should really autogenerate these arrays
1541 static const unsigned GPR64ArgRegsWin64[] = {
1542 X86::RCX, X86::RDX, X86::R8, X86::R9
1544 static const unsigned XMMArgRegsWin64[] = {
1545 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
1547 static const unsigned GPR64ArgRegs64Bit[] = {
1548 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1550 static const unsigned XMMArgRegs64Bit[] = {
1551 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1552 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1554 const unsigned *GPR64ArgRegs, *XMMArgRegs;
1557 TotalNumIntRegs = 4; TotalNumXMMRegs = 4;
1558 GPR64ArgRegs = GPR64ArgRegsWin64;
1559 XMMArgRegs = XMMArgRegsWin64;
1561 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
1562 GPR64ArgRegs = GPR64ArgRegs64Bit;
1563 XMMArgRegs = XMMArgRegs64Bit;
1565 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
1567 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs,
1570 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat);
1571 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
1572 "SSE register cannot be used when SSE is disabled!");
1573 assert(!(NumXMMRegs && UseSoftFloat && NoImplicitFloatOps) &&
1574 "SSE register cannot be used when SSE is disabled!");
1575 if (UseSoftFloat || NoImplicitFloatOps || !Subtarget->hasSSE1())
1576 // Kernel mode asks for SSE to be disabled, so don't push them
1578 TotalNumXMMRegs = 0;
1580 // For X86-64, if there are vararg parameters that are passed via
1581 // registers, then we must store them to their spots on the stack so they
1582 // may be loaded by deferencing the result of va_next.
1583 VarArgsGPOffset = NumIntRegs * 8;
1584 VarArgsFPOffset = TotalNumIntRegs * 8 + NumXMMRegs * 16;
1585 RegSaveFrameIndex = MFI->CreateStackObject(TotalNumIntRegs * 8 +
1586 TotalNumXMMRegs * 16, 16,
1589 // Store the integer parameter registers.
1590 SmallVector<SDValue, 8> MemOps;
1591 SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
1592 unsigned Offset = VarArgsGPOffset;
1593 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
1594 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
1595 DAG.getIntPtrConstant(Offset));
1596 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
1597 X86::GR64RegisterClass);
1598 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
1600 DAG.getStore(Val.getValue(1), dl, Val, FIN,
1601 PseudoSourceValue::getFixedStack(RegSaveFrameIndex),
1603 MemOps.push_back(Store);
1607 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
1608 // Now store the XMM (fp + vector) parameter registers.
1609 SmallVector<SDValue, 11> SaveXMMOps;
1610 SaveXMMOps.push_back(Chain);
1612 unsigned AL = MF.addLiveIn(X86::AL, X86::GR8RegisterClass);
1613 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
1614 SaveXMMOps.push_back(ALVal);
1616 SaveXMMOps.push_back(DAG.getIntPtrConstant(RegSaveFrameIndex));
1617 SaveXMMOps.push_back(DAG.getIntPtrConstant(VarArgsFPOffset));
1619 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
1620 unsigned VReg = MF.addLiveIn(XMMArgRegs[NumXMMRegs],
1621 X86::VR128RegisterClass);
1622 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
1623 SaveXMMOps.push_back(Val);
1625 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
1627 &SaveXMMOps[0], SaveXMMOps.size()));
1630 if (!MemOps.empty())
1631 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1632 &MemOps[0], MemOps.size());
1636 // Some CCs need callee pop.
1637 if (IsCalleePop(isVarArg, CallConv)) {
1638 BytesToPopOnReturn = StackSize; // Callee pops everything.
1639 BytesCallerReserves = 0;
1641 BytesToPopOnReturn = 0; // Callee pops nothing.
1642 // If this is an sret function, the return should pop the hidden pointer.
1643 if (!Is64Bit && CallConv != CallingConv::Fast && ArgsAreStructReturn(Ins))
1644 BytesToPopOnReturn = 4;
1645 BytesCallerReserves = StackSize;
1649 RegSaveFrameIndex = 0xAAAAAAA; // RegSaveFrameIndex is X86-64 only.
1650 if (CallConv == CallingConv::X86_FastCall)
1651 VarArgsFrameIndex = 0xAAAAAAA; // fastcc functions can't have varargs.
1654 FuncInfo->setBytesToPopOnReturn(BytesToPopOnReturn);
1660 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
1661 SDValue StackPtr, SDValue Arg,
1662 DebugLoc dl, SelectionDAG &DAG,
1663 const CCValAssign &VA,
1664 ISD::ArgFlagsTy Flags) {
1665 const unsigned FirstStackArgOffset = (Subtarget->isTargetWin64() ? 32 : 0);
1666 unsigned LocMemOffset = FirstStackArgOffset + VA.getLocMemOffset();
1667 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1668 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1669 if (Flags.isByVal()) {
1670 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
1672 return DAG.getStore(Chain, dl, Arg, PtrOff,
1673 PseudoSourceValue::getStack(), LocMemOffset);
1676 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
1677 /// optimization is performed and it is required.
1679 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
1680 SDValue &OutRetAddr,
1686 if (!IsTailCall || FPDiff==0) return Chain;
1688 // Adjust the Return address stack slot.
1689 EVT VT = getPointerTy();
1690 OutRetAddr = getReturnAddressFrameIndex(DAG);
1692 // Load the "old" Return address.
1693 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, NULL, 0);
1694 return SDValue(OutRetAddr.getNode(), 1);
1697 /// EmitTailCallStoreRetAddr - Emit a store of the return adress if tail call
1698 /// optimization is performed and it is required (FPDiff!=0).
1700 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
1701 SDValue Chain, SDValue RetAddrFrIdx,
1702 bool Is64Bit, int FPDiff, DebugLoc dl) {
1703 // Store the return address to the appropriate stack slot.
1704 if (!FPDiff) return Chain;
1705 // Calculate the new stack slot for the return address.
1706 int SlotSize = Is64Bit ? 8 : 4;
1707 int NewReturnAddrFI =
1708 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize,
1710 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
1711 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
1712 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
1713 PseudoSourceValue::getFixedStack(NewReturnAddrFI), 0);
1718 X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
1719 CallingConv::ID CallConv, bool isVarArg,
1721 const SmallVectorImpl<ISD::OutputArg> &Outs,
1722 const SmallVectorImpl<ISD::InputArg> &Ins,
1723 DebugLoc dl, SelectionDAG &DAG,
1724 SmallVectorImpl<SDValue> &InVals) {
1726 MachineFunction &MF = DAG.getMachineFunction();
1727 bool Is64Bit = Subtarget->is64Bit();
1728 bool IsStructRet = CallIsStructReturn(Outs);
1730 assert((!isTailCall ||
1731 (CallConv == CallingConv::Fast && PerformTailCallOpt)) &&
1732 "IsEligibleForTailCallOptimization missed a case!");
1733 assert(!(isVarArg && CallConv == CallingConv::Fast) &&
1734 "Var args not supported with calling convention fastcc");
1736 // Analyze operands of the call, assigning locations to each operand.
1737 SmallVector<CCValAssign, 16> ArgLocs;
1738 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1739 ArgLocs, *DAG.getContext());
1740 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForNode(CallConv));
1742 // Get a count of how many bytes are to be pushed on the stack.
1743 unsigned NumBytes = CCInfo.getNextStackOffset();
1744 if (PerformTailCallOpt && CallConv == CallingConv::Fast)
1745 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
1749 // Lower arguments at fp - stackoffset + fpdiff.
1750 unsigned NumBytesCallerPushed =
1751 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
1752 FPDiff = NumBytesCallerPushed - NumBytes;
1754 // Set the delta of movement of the returnaddr stackslot.
1755 // But only set if delta is greater than previous delta.
1756 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
1757 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
1760 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
1762 SDValue RetAddrFrIdx;
1763 // Load return adress for tail calls.
1764 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall, Is64Bit,
1767 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
1768 SmallVector<SDValue, 8> MemOpChains;
1771 // Walk the register/memloc assignments, inserting copies/loads. In the case
1772 // of tail call optimization arguments are handle later.
1773 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1774 CCValAssign &VA = ArgLocs[i];
1775 EVT RegVT = VA.getLocVT();
1776 SDValue Arg = Outs[i].Val;
1777 ISD::ArgFlagsTy Flags = Outs[i].Flags;
1778 bool isByVal = Flags.isByVal();
1780 // Promote the value if needed.
1781 switch (VA.getLocInfo()) {
1782 default: llvm_unreachable("Unknown loc info!");
1783 case CCValAssign::Full: break;
1784 case CCValAssign::SExt:
1785 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
1787 case CCValAssign::ZExt:
1788 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
1790 case CCValAssign::AExt:
1791 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) {
1792 // Special case: passing MMX values in XMM registers.
1793 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, Arg);
1794 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
1795 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
1797 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
1799 case CCValAssign::BCvt:
1800 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, RegVT, Arg);
1802 case CCValAssign::Indirect: {
1803 // Store the argument.
1804 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
1805 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
1806 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
1807 PseudoSourceValue::getFixedStack(FI), 0);
1813 if (VA.isRegLoc()) {
1814 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1816 if (!isTailCall || (isTailCall && isByVal)) {
1817 assert(VA.isMemLoc());
1818 if (StackPtr.getNode() == 0)
1819 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy());
1821 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
1822 dl, DAG, VA, Flags));
1827 if (!MemOpChains.empty())
1828 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1829 &MemOpChains[0], MemOpChains.size());
1831 // Build a sequence of copy-to-reg nodes chained together with token chain
1832 // and flag operands which copy the outgoing args into registers.
1834 // Tail call byval lowering might overwrite argument registers so in case of
1835 // tail call optimization the copies to registers are lowered later.
1837 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1838 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1839 RegsToPass[i].second, InFlag);
1840 InFlag = Chain.getValue(1);
1844 if (Subtarget->isPICStyleGOT()) {
1845 // ELF / PIC requires GOT in the EBX register before function calls via PLT
1848 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX,
1849 DAG.getNode(X86ISD::GlobalBaseReg,
1850 DebugLoc::getUnknownLoc(),
1853 InFlag = Chain.getValue(1);
1855 // If we are tail calling and generating PIC/GOT style code load the
1856 // address of the callee into ECX. The value in ecx is used as target of
1857 // the tail jump. This is done to circumvent the ebx/callee-saved problem
1858 // for tail calls on PIC/GOT architectures. Normally we would just put the
1859 // address of GOT into ebx and then call target@PLT. But for tail calls
1860 // ebx would be restored (since ebx is callee saved) before jumping to the
1863 // Note: The actual moving to ECX is done further down.
1864 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
1865 if (G && !G->getGlobal()->hasHiddenVisibility() &&
1866 !G->getGlobal()->hasProtectedVisibility())
1867 Callee = LowerGlobalAddress(Callee, DAG);
1868 else if (isa<ExternalSymbolSDNode>(Callee))
1869 Callee = LowerExternalSymbol(Callee, DAG);
1873 if (Is64Bit && isVarArg) {
1874 // From AMD64 ABI document:
1875 // For calls that may call functions that use varargs or stdargs
1876 // (prototype-less calls or calls to functions containing ellipsis (...) in
1877 // the declaration) %al is used as hidden argument to specify the number
1878 // of SSE registers used. The contents of %al do not need to match exactly
1879 // the number of registers, but must be an ubound on the number of SSE
1880 // registers used and is in the range 0 - 8 inclusive.
1882 // FIXME: Verify this on Win64
1883 // Count the number of XMM registers allocated.
1884 static const unsigned XMMArgRegs[] = {
1885 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1886 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1888 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
1889 assert((Subtarget->hasSSE1() || !NumXMMRegs)
1890 && "SSE registers cannot be used when SSE is disabled");
1892 Chain = DAG.getCopyToReg(Chain, dl, X86::AL,
1893 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
1894 InFlag = Chain.getValue(1);
1898 // For tail calls lower the arguments to the 'real' stack slot.
1900 // Force all the incoming stack arguments to be loaded from the stack
1901 // before any new outgoing arguments are stored to the stack, because the
1902 // outgoing stack slots may alias the incoming argument stack slots, and
1903 // the alias isn't otherwise explicit. This is slightly more conservative
1904 // than necessary, because it means that each store effectively depends
1905 // on every argument instead of just those arguments it would clobber.
1906 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
1908 SmallVector<SDValue, 8> MemOpChains2;
1911 // Do not flag preceeding copytoreg stuff together with the following stuff.
1913 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1914 CCValAssign &VA = ArgLocs[i];
1915 if (!VA.isRegLoc()) {
1916 assert(VA.isMemLoc());
1917 SDValue Arg = Outs[i].Val;
1918 ISD::ArgFlagsTy Flags = Outs[i].Flags;
1919 // Create frame index.
1920 int32_t Offset = VA.getLocMemOffset()+FPDiff;
1921 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
1922 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true, false);
1923 FIN = DAG.getFrameIndex(FI, getPointerTy());
1925 if (Flags.isByVal()) {
1926 // Copy relative to framepointer.
1927 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
1928 if (StackPtr.getNode() == 0)
1929 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr,
1931 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
1933 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
1937 // Store relative to framepointer.
1938 MemOpChains2.push_back(
1939 DAG.getStore(ArgChain, dl, Arg, FIN,
1940 PseudoSourceValue::getFixedStack(FI), 0));
1945 if (!MemOpChains2.empty())
1946 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1947 &MemOpChains2[0], MemOpChains2.size());
1949 // Copy arguments to their registers.
1950 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1951 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1952 RegsToPass[i].second, InFlag);
1953 InFlag = Chain.getValue(1);
1957 // Store the return address to the appropriate stack slot.
1958 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
1962 bool WasGlobalOrExternal = false;
1963 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
1964 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
1965 // In the 64-bit large code model, we have to make all calls
1966 // through a register, since the call instruction's 32-bit
1967 // pc-relative offset may not be large enough to hold the whole
1969 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1970 WasGlobalOrExternal = true;
1971 // If the callee is a GlobalAddress node (quite common, every direct call
1972 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
1975 // We should use extra load for direct calls to dllimported functions in
1977 GlobalValue *GV = G->getGlobal();
1978 if (!GV->hasDLLImportLinkage()) {
1979 unsigned char OpFlags = 0;
1981 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
1982 // external symbols most go through the PLT in PIC mode. If the symbol
1983 // has hidden or protected visibility, or if it is static or local, then
1984 // we don't need to use the PLT - we can directly call it.
1985 if (Subtarget->isTargetELF() &&
1986 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1987 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
1988 OpFlags = X86II::MO_PLT;
1989 } else if (Subtarget->isPICStyleStubAny() &&
1990 (GV->isDeclaration() || GV->isWeakForLinker()) &&
1991 Subtarget->getDarwinVers() < 9) {
1992 // PC-relative references to external symbols should go through $stub,
1993 // unless we're building with the leopard linker or later, which
1994 // automatically synthesizes these stubs.
1995 OpFlags = X86II::MO_DARWIN_STUB;
1998 Callee = DAG.getTargetGlobalAddress(GV, getPointerTy(),
1999 G->getOffset(), OpFlags);
2001 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2002 WasGlobalOrExternal = true;
2003 unsigned char OpFlags = 0;
2005 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to external
2006 // symbols should go through the PLT.
2007 if (Subtarget->isTargetELF() &&
2008 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2009 OpFlags = X86II::MO_PLT;
2010 } else if (Subtarget->isPICStyleStubAny() &&
2011 Subtarget->getDarwinVers() < 9) {
2012 // PC-relative references to external symbols should go through $stub,
2013 // unless we're building with the leopard linker or later, which
2014 // automatically synthesizes these stubs.
2015 OpFlags = X86II::MO_DARWIN_STUB;
2018 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2022 if (isTailCall && !WasGlobalOrExternal) {
2023 unsigned Opc = Is64Bit ? X86::R11 : X86::EAX;
2025 Chain = DAG.getCopyToReg(Chain, dl,
2026 DAG.getRegister(Opc, getPointerTy()),
2028 Callee = DAG.getRegister(Opc, getPointerTy());
2029 // Add register as live out.
2030 MF.getRegInfo().addLiveOut(Opc);
2033 // Returns a chain & a flag for retval copy to use.
2034 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
2035 SmallVector<SDValue, 8> Ops;
2038 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2039 DAG.getIntPtrConstant(0, true), InFlag);
2040 InFlag = Chain.getValue(1);
2043 Ops.push_back(Chain);
2044 Ops.push_back(Callee);
2047 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2049 // Add argument registers to the end of the list so that they are known live
2051 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2052 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2053 RegsToPass[i].second.getValueType()));
2055 // Add an implicit use GOT pointer in EBX.
2056 if (!isTailCall && Subtarget->isPICStyleGOT())
2057 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
2059 // Add an implicit use of AL for x86 vararg functions.
2060 if (Is64Bit && isVarArg)
2061 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
2063 if (InFlag.getNode())
2064 Ops.push_back(InFlag);
2067 // If this is the first return lowered for this function, add the regs
2068 // to the liveout set for the function.
2069 if (MF.getRegInfo().liveout_empty()) {
2070 SmallVector<CCValAssign, 16> RVLocs;
2071 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs,
2073 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2074 for (unsigned i = 0; i != RVLocs.size(); ++i)
2075 if (RVLocs[i].isRegLoc())
2076 MF.getRegInfo().addLiveOut(RVLocs[i].getLocReg());
2079 assert(((Callee.getOpcode() == ISD::Register &&
2080 (cast<RegisterSDNode>(Callee)->getReg() == X86::EAX ||
2081 cast<RegisterSDNode>(Callee)->getReg() == X86::R9)) ||
2082 Callee.getOpcode() == ISD::TargetExternalSymbol ||
2083 Callee.getOpcode() == ISD::TargetGlobalAddress) &&
2084 "Expecting an global address, external symbol, or register");
2086 return DAG.getNode(X86ISD::TC_RETURN, dl,
2087 NodeTys, &Ops[0], Ops.size());
2090 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2091 InFlag = Chain.getValue(1);
2093 // Create the CALLSEQ_END node.
2094 unsigned NumBytesForCalleeToPush;
2095 if (IsCalleePop(isVarArg, CallConv))
2096 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2097 else if (!Is64Bit && CallConv != CallingConv::Fast && IsStructRet)
2098 // If this is is a call to a struct-return function, the callee
2099 // pops the hidden struct pointer, so we have to push it back.
2100 // This is common for Darwin/X86, Linux & Mingw32 targets.
2101 NumBytesForCalleeToPush = 4;
2103 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2105 // Returns a flag for retval copy to use.
2106 Chain = DAG.getCALLSEQ_END(Chain,
2107 DAG.getIntPtrConstant(NumBytes, true),
2108 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2111 InFlag = Chain.getValue(1);
2113 // Handle result values, copying them out of physregs into vregs that we
2115 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2116 Ins, dl, DAG, InVals);
2120 //===----------------------------------------------------------------------===//
2121 // Fast Calling Convention (tail call) implementation
2122 //===----------------------------------------------------------------------===//
2124 // Like std call, callee cleans arguments, convention except that ECX is
2125 // reserved for storing the tail called function address. Only 2 registers are
2126 // free for argument passing (inreg). Tail call optimization is performed
2128 // * tailcallopt is enabled
2129 // * caller/callee are fastcc
2130 // On X86_64 architecture with GOT-style position independent code only local
2131 // (within module) calls are supported at the moment.
2132 // To keep the stack aligned according to platform abi the function
2133 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2134 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2135 // If a tail called function callee has more arguments than the caller the
2136 // caller needs to make sure that there is room to move the RETADDR to. This is
2137 // achieved by reserving an area the size of the argument delta right after the
2138 // original REtADDR, but before the saved framepointer or the spilled registers
2139 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2151 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2152 /// for a 16 byte align requirement.
2153 unsigned X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2154 SelectionDAG& DAG) {
2155 MachineFunction &MF = DAG.getMachineFunction();
2156 const TargetMachine &TM = MF.getTarget();
2157 const TargetFrameInfo &TFI = *TM.getFrameInfo();
2158 unsigned StackAlignment = TFI.getStackAlignment();
2159 uint64_t AlignMask = StackAlignment - 1;
2160 int64_t Offset = StackSize;
2161 uint64_t SlotSize = TD->getPointerSize();
2162 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2163 // Number smaller than 12 so just add the difference.
2164 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2166 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2167 Offset = ((~AlignMask) & Offset) + StackAlignment +
2168 (StackAlignment-SlotSize);
2173 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2174 /// for tail call optimization. Targets which want to do tail call
2175 /// optimization should implement this function.
2177 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2178 CallingConv::ID CalleeCC,
2180 const SmallVectorImpl<ISD::InputArg> &Ins,
2181 SelectionDAG& DAG) const {
2182 MachineFunction &MF = DAG.getMachineFunction();
2183 CallingConv::ID CallerCC = MF.getFunction()->getCallingConv();
2184 return CalleeCC == CallingConv::Fast && CallerCC == CalleeCC;
2188 X86TargetLowering::createFastISel(MachineFunction &mf,
2189 MachineModuleInfo *mmo,
2191 DenseMap<const Value *, unsigned> &vm,
2192 DenseMap<const BasicBlock *,
2193 MachineBasicBlock *> &bm,
2194 DenseMap<const AllocaInst *, int> &am
2196 , SmallSet<Instruction*, 8> &cil
2199 return X86::createFastISel(mf, mmo, dw, vm, bm, am
2207 //===----------------------------------------------------------------------===//
2208 // Other Lowering Hooks
2209 //===----------------------------------------------------------------------===//
2212 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) {
2213 MachineFunction &MF = DAG.getMachineFunction();
2214 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2215 int ReturnAddrIndex = FuncInfo->getRAIndex();
2217 if (ReturnAddrIndex == 0) {
2218 // Set up a frame object for the return address.
2219 uint64_t SlotSize = TD->getPointerSize();
2220 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
2222 FuncInfo->setRAIndex(ReturnAddrIndex);
2225 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
2229 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
2230 bool hasSymbolicDisplacement) {
2231 // Offset should fit into 32 bit immediate field.
2232 if (!isInt32(Offset))
2235 // If we don't have a symbolic displacement - we don't have any extra
2237 if (!hasSymbolicDisplacement)
2240 // FIXME: Some tweaks might be needed for medium code model.
2241 if (M != CodeModel::Small && M != CodeModel::Kernel)
2244 // For small code model we assume that latest object is 16MB before end of 31
2245 // bits boundary. We may also accept pretty large negative constants knowing
2246 // that all objects are in the positive half of address space.
2247 if (M == CodeModel::Small && Offset < 16*1024*1024)
2250 // For kernel code model we know that all object resist in the negative half
2251 // of 32bits address space. We may not accept negative offsets, since they may
2252 // be just off and we may accept pretty large positive ones.
2253 if (M == CodeModel::Kernel && Offset > 0)
2259 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
2260 /// specific condition code, returning the condition code and the LHS/RHS of the
2261 /// comparison to make.
2262 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
2263 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
2265 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
2266 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
2267 // X > -1 -> X == 0, jump !sign.
2268 RHS = DAG.getConstant(0, RHS.getValueType());
2269 return X86::COND_NS;
2270 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
2271 // X < 0 -> X == 0, jump on sign.
2273 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
2275 RHS = DAG.getConstant(0, RHS.getValueType());
2276 return X86::COND_LE;
2280 switch (SetCCOpcode) {
2281 default: llvm_unreachable("Invalid integer condition!");
2282 case ISD::SETEQ: return X86::COND_E;
2283 case ISD::SETGT: return X86::COND_G;
2284 case ISD::SETGE: return X86::COND_GE;
2285 case ISD::SETLT: return X86::COND_L;
2286 case ISD::SETLE: return X86::COND_LE;
2287 case ISD::SETNE: return X86::COND_NE;
2288 case ISD::SETULT: return X86::COND_B;
2289 case ISD::SETUGT: return X86::COND_A;
2290 case ISD::SETULE: return X86::COND_BE;
2291 case ISD::SETUGE: return X86::COND_AE;
2295 // First determine if it is required or is profitable to flip the operands.
2297 // If LHS is a foldable load, but RHS is not, flip the condition.
2298 if ((ISD::isNON_EXTLoad(LHS.getNode()) && LHS.hasOneUse()) &&
2299 !(ISD::isNON_EXTLoad(RHS.getNode()) && RHS.hasOneUse())) {
2300 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
2301 std::swap(LHS, RHS);
2304 switch (SetCCOpcode) {
2310 std::swap(LHS, RHS);
2314 // On a floating point condition, the flags are set as follows:
2316 // 0 | 0 | 0 | X > Y
2317 // 0 | 0 | 1 | X < Y
2318 // 1 | 0 | 0 | X == Y
2319 // 1 | 1 | 1 | unordered
2320 switch (SetCCOpcode) {
2321 default: llvm_unreachable("Condcode should be pre-legalized away");
2323 case ISD::SETEQ: return X86::COND_E;
2324 case ISD::SETOLT: // flipped
2326 case ISD::SETGT: return X86::COND_A;
2327 case ISD::SETOLE: // flipped
2329 case ISD::SETGE: return X86::COND_AE;
2330 case ISD::SETUGT: // flipped
2332 case ISD::SETLT: return X86::COND_B;
2333 case ISD::SETUGE: // flipped
2335 case ISD::SETLE: return X86::COND_BE;
2337 case ISD::SETNE: return X86::COND_NE;
2338 case ISD::SETUO: return X86::COND_P;
2339 case ISD::SETO: return X86::COND_NP;
2341 case ISD::SETUNE: return X86::COND_INVALID;
2345 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
2346 /// code. Current x86 isa includes the following FP cmov instructions:
2347 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
2348 static bool hasFPCMov(unsigned X86CC) {
2364 /// isFPImmLegal - Returns true if the target can instruction select the
2365 /// specified FP immediate natively. If false, the legalizer will
2366 /// materialize the FP immediate as a load from a constant pool.
2367 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
2368 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
2369 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
2375 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
2376 /// the specified range (L, H].
2377 static bool isUndefOrInRange(int Val, int Low, int Hi) {
2378 return (Val < 0) || (Val >= Low && Val < Hi);
2381 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
2382 /// specified value.
2383 static bool isUndefOrEqual(int Val, int CmpVal) {
2384 if (Val < 0 || Val == CmpVal)
2389 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
2390 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
2391 /// the second operand.
2392 static bool isPSHUFDMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2393 if (VT == MVT::v4f32 || VT == MVT::v4i32 || VT == MVT::v4i16)
2394 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
2395 if (VT == MVT::v2f64 || VT == MVT::v2i64)
2396 return (Mask[0] < 2 && Mask[1] < 2);
2400 bool X86::isPSHUFDMask(ShuffleVectorSDNode *N) {
2401 SmallVector<int, 8> M;
2403 return ::isPSHUFDMask(M, N->getValueType(0));
2406 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
2407 /// is suitable for input to PSHUFHW.
2408 static bool isPSHUFHWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2409 if (VT != MVT::v8i16)
2412 // Lower quadword copied in order or undef.
2413 for (int i = 0; i != 4; ++i)
2414 if (Mask[i] >= 0 && Mask[i] != i)
2417 // Upper quadword shuffled.
2418 for (int i = 4; i != 8; ++i)
2419 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7))
2425 bool X86::isPSHUFHWMask(ShuffleVectorSDNode *N) {
2426 SmallVector<int, 8> M;
2428 return ::isPSHUFHWMask(M, N->getValueType(0));
2431 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
2432 /// is suitable for input to PSHUFLW.
2433 static bool isPSHUFLWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2434 if (VT != MVT::v8i16)
2437 // Upper quadword copied in order.
2438 for (int i = 4; i != 8; ++i)
2439 if (Mask[i] >= 0 && Mask[i] != i)
2442 // Lower quadword shuffled.
2443 for (int i = 0; i != 4; ++i)
2450 bool X86::isPSHUFLWMask(ShuffleVectorSDNode *N) {
2451 SmallVector<int, 8> M;
2453 return ::isPSHUFLWMask(M, N->getValueType(0));
2456 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
2457 /// is suitable for input to PALIGNR.
2458 static bool isPALIGNRMask(const SmallVectorImpl<int> &Mask, EVT VT,
2460 int i, e = VT.getVectorNumElements();
2462 // Do not handle v2i64 / v2f64 shuffles with palignr.
2463 if (e < 4 || !hasSSSE3)
2466 for (i = 0; i != e; ++i)
2470 // All undef, not a palignr.
2474 // Determine if it's ok to perform a palignr with only the LHS, since we
2475 // don't have access to the actual shuffle elements to see if RHS is undef.
2476 bool Unary = Mask[i] < (int)e;
2477 bool NeedsUnary = false;
2479 int s = Mask[i] - i;
2481 // Check the rest of the elements to see if they are consecutive.
2482 for (++i; i != e; ++i) {
2487 Unary = Unary && (m < (int)e);
2488 NeedsUnary = NeedsUnary || (m < s);
2490 if (NeedsUnary && !Unary)
2492 if (Unary && m != ((s+i) & (e-1)))
2494 if (!Unary && m != (s+i))
2500 bool X86::isPALIGNRMask(ShuffleVectorSDNode *N) {
2501 SmallVector<int, 8> M;
2503 return ::isPALIGNRMask(M, N->getValueType(0), true);
2506 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
2507 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
2508 static bool isSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2509 int NumElems = VT.getVectorNumElements();
2510 if (NumElems != 2 && NumElems != 4)
2513 int Half = NumElems / 2;
2514 for (int i = 0; i < Half; ++i)
2515 if (!isUndefOrInRange(Mask[i], 0, NumElems))
2517 for (int i = Half; i < NumElems; ++i)
2518 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
2524 bool X86::isSHUFPMask(ShuffleVectorSDNode *N) {
2525 SmallVector<int, 8> M;
2527 return ::isSHUFPMask(M, N->getValueType(0));
2530 /// isCommutedSHUFP - Returns true if the shuffle mask is exactly
2531 /// the reverse of what x86 shuffles want. x86 shuffles requires the lower
2532 /// half elements to come from vector 1 (which would equal the dest.) and
2533 /// the upper half to come from vector 2.
2534 static bool isCommutedSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2535 int NumElems = VT.getVectorNumElements();
2537 if (NumElems != 2 && NumElems != 4)
2540 int Half = NumElems / 2;
2541 for (int i = 0; i < Half; ++i)
2542 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
2544 for (int i = Half; i < NumElems; ++i)
2545 if (!isUndefOrInRange(Mask[i], 0, NumElems))
2550 static bool isCommutedSHUFP(ShuffleVectorSDNode *N) {
2551 SmallVector<int, 8> M;
2553 return isCommutedSHUFPMask(M, N->getValueType(0));
2556 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
2557 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
2558 bool X86::isMOVHLPSMask(ShuffleVectorSDNode *N) {
2559 if (N->getValueType(0).getVectorNumElements() != 4)
2562 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
2563 return isUndefOrEqual(N->getMaskElt(0), 6) &&
2564 isUndefOrEqual(N->getMaskElt(1), 7) &&
2565 isUndefOrEqual(N->getMaskElt(2), 2) &&
2566 isUndefOrEqual(N->getMaskElt(3), 3);
2569 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
2570 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
2572 bool X86::isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N) {
2573 unsigned NumElems = N->getValueType(0).getVectorNumElements();
2578 return isUndefOrEqual(N->getMaskElt(0), 2) &&
2579 isUndefOrEqual(N->getMaskElt(1), 3) &&
2580 isUndefOrEqual(N->getMaskElt(2), 2) &&
2581 isUndefOrEqual(N->getMaskElt(3), 3);
2584 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
2585 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
2586 bool X86::isMOVLPMask(ShuffleVectorSDNode *N) {
2587 unsigned NumElems = N->getValueType(0).getVectorNumElements();
2589 if (NumElems != 2 && NumElems != 4)
2592 for (unsigned i = 0; i < NumElems/2; ++i)
2593 if (!isUndefOrEqual(N->getMaskElt(i), i + NumElems))
2596 for (unsigned i = NumElems/2; i < NumElems; ++i)
2597 if (!isUndefOrEqual(N->getMaskElt(i), i))
2603 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
2604 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
2605 bool X86::isMOVLHPSMask(ShuffleVectorSDNode *N) {
2606 unsigned NumElems = N->getValueType(0).getVectorNumElements();
2608 if (NumElems != 2 && NumElems != 4)
2611 for (unsigned i = 0; i < NumElems/2; ++i)
2612 if (!isUndefOrEqual(N->getMaskElt(i), i))
2615 for (unsigned i = 0; i < NumElems/2; ++i)
2616 if (!isUndefOrEqual(N->getMaskElt(i + NumElems/2), i + NumElems))
2622 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
2623 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
2624 static bool isUNPCKLMask(const SmallVectorImpl<int> &Mask, EVT VT,
2625 bool V2IsSplat = false) {
2626 int NumElts = VT.getVectorNumElements();
2627 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
2630 for (int i = 0, j = 0; i != NumElts; i += 2, ++j) {
2632 int BitI1 = Mask[i+1];
2633 if (!isUndefOrEqual(BitI, j))
2636 if (!isUndefOrEqual(BitI1, NumElts))
2639 if (!isUndefOrEqual(BitI1, j + NumElts))
2646 bool X86::isUNPCKLMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
2647 SmallVector<int, 8> M;
2649 return ::isUNPCKLMask(M, N->getValueType(0), V2IsSplat);
2652 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
2653 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
2654 static bool isUNPCKHMask(const SmallVectorImpl<int> &Mask, EVT VT,
2655 bool V2IsSplat = false) {
2656 int NumElts = VT.getVectorNumElements();
2657 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
2660 for (int i = 0, j = 0; i != NumElts; i += 2, ++j) {
2662 int BitI1 = Mask[i+1];
2663 if (!isUndefOrEqual(BitI, j + NumElts/2))
2666 if (isUndefOrEqual(BitI1, NumElts))
2669 if (!isUndefOrEqual(BitI1, j + NumElts/2 + NumElts))
2676 bool X86::isUNPCKHMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
2677 SmallVector<int, 8> M;
2679 return ::isUNPCKHMask(M, N->getValueType(0), V2IsSplat);
2682 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
2683 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
2685 static bool isUNPCKL_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) {
2686 int NumElems = VT.getVectorNumElements();
2687 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
2690 for (int i = 0, j = 0; i != NumElems; i += 2, ++j) {
2692 int BitI1 = Mask[i+1];
2693 if (!isUndefOrEqual(BitI, j))
2695 if (!isUndefOrEqual(BitI1, j))
2701 bool X86::isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N) {
2702 SmallVector<int, 8> M;
2704 return ::isUNPCKL_v_undef_Mask(M, N->getValueType(0));
2707 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
2708 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
2710 static bool isUNPCKH_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) {
2711 int NumElems = VT.getVectorNumElements();
2712 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
2715 for (int i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) {
2717 int BitI1 = Mask[i+1];
2718 if (!isUndefOrEqual(BitI, j))
2720 if (!isUndefOrEqual(BitI1, j))
2726 bool X86::isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N) {
2727 SmallVector<int, 8> M;
2729 return ::isUNPCKH_v_undef_Mask(M, N->getValueType(0));
2732 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
2733 /// specifies a shuffle of elements that is suitable for input to MOVSS,
2734 /// MOVSD, and MOVD, i.e. setting the lowest element.
2735 static bool isMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2736 if (VT.getVectorElementType().getSizeInBits() < 32)
2739 int NumElts = VT.getVectorNumElements();
2741 if (!isUndefOrEqual(Mask[0], NumElts))
2744 for (int i = 1; i < NumElts; ++i)
2745 if (!isUndefOrEqual(Mask[i], i))
2751 bool X86::isMOVLMask(ShuffleVectorSDNode *N) {
2752 SmallVector<int, 8> M;
2754 return ::isMOVLMask(M, N->getValueType(0));
2757 /// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
2758 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
2759 /// element of vector 2 and the other elements to come from vector 1 in order.
2760 static bool isCommutedMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT,
2761 bool V2IsSplat = false, bool V2IsUndef = false) {
2762 int NumOps = VT.getVectorNumElements();
2763 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
2766 if (!isUndefOrEqual(Mask[0], 0))
2769 for (int i = 1; i < NumOps; ++i)
2770 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
2771 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
2772 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
2778 static bool isCommutedMOVL(ShuffleVectorSDNode *N, bool V2IsSplat = false,
2779 bool V2IsUndef = false) {
2780 SmallVector<int, 8> M;
2782 return isCommutedMOVLMask(M, N->getValueType(0), V2IsSplat, V2IsUndef);
2785 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2786 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
2787 bool X86::isMOVSHDUPMask(ShuffleVectorSDNode *N) {
2788 if (N->getValueType(0).getVectorNumElements() != 4)
2791 // Expect 1, 1, 3, 3
2792 for (unsigned i = 0; i < 2; ++i) {
2793 int Elt = N->getMaskElt(i);
2794 if (Elt >= 0 && Elt != 1)
2799 for (unsigned i = 2; i < 4; ++i) {
2800 int Elt = N->getMaskElt(i);
2801 if (Elt >= 0 && Elt != 3)
2806 // Don't use movshdup if it can be done with a shufps.
2807 // FIXME: verify that matching u, u, 3, 3 is what we want.
2811 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2812 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
2813 bool X86::isMOVSLDUPMask(ShuffleVectorSDNode *N) {
2814 if (N->getValueType(0).getVectorNumElements() != 4)
2817 // Expect 0, 0, 2, 2
2818 for (unsigned i = 0; i < 2; ++i)
2819 if (N->getMaskElt(i) > 0)
2823 for (unsigned i = 2; i < 4; ++i) {
2824 int Elt = N->getMaskElt(i);
2825 if (Elt >= 0 && Elt != 2)
2830 // Don't use movsldup if it can be done with a shufps.
2834 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2835 /// specifies a shuffle of elements that is suitable for input to MOVDDUP.
2836 bool X86::isMOVDDUPMask(ShuffleVectorSDNode *N) {
2837 int e = N->getValueType(0).getVectorNumElements() / 2;
2839 for (int i = 0; i < e; ++i)
2840 if (!isUndefOrEqual(N->getMaskElt(i), i))
2842 for (int i = 0; i < e; ++i)
2843 if (!isUndefOrEqual(N->getMaskElt(e+i), i))
2848 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
2849 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
2850 unsigned X86::getShuffleSHUFImmediate(SDNode *N) {
2851 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
2852 int NumOperands = SVOp->getValueType(0).getVectorNumElements();
2854 unsigned Shift = (NumOperands == 4) ? 2 : 1;
2856 for (int i = 0; i < NumOperands; ++i) {
2857 int Val = SVOp->getMaskElt(NumOperands-i-1);
2858 if (Val < 0) Val = 0;
2859 if (Val >= NumOperands) Val -= NumOperands;
2861 if (i != NumOperands - 1)
2867 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
2868 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
2869 unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
2870 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
2872 // 8 nodes, but we only care about the last 4.
2873 for (unsigned i = 7; i >= 4; --i) {
2874 int Val = SVOp->getMaskElt(i);
2883 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
2884 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
2885 unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
2886 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
2888 // 8 nodes, but we only care about the first 4.
2889 for (int i = 3; i >= 0; --i) {
2890 int Val = SVOp->getMaskElt(i);
2899 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
2900 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
2901 unsigned X86::getShufflePALIGNRImmediate(SDNode *N) {
2902 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
2903 EVT VVT = N->getValueType(0);
2904 unsigned EltSize = VVT.getVectorElementType().getSizeInBits() >> 3;
2908 for (i = 0, e = VVT.getVectorNumElements(); i != e; ++i) {
2909 Val = SVOp->getMaskElt(i);
2913 return (Val - i) * EltSize;
2916 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
2918 bool X86::isZeroNode(SDValue Elt) {
2919 return ((isa<ConstantSDNode>(Elt) &&
2920 cast<ConstantSDNode>(Elt)->getZExtValue() == 0) ||
2921 (isa<ConstantFPSDNode>(Elt) &&
2922 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
2925 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
2926 /// their permute mask.
2927 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
2928 SelectionDAG &DAG) {
2929 EVT VT = SVOp->getValueType(0);
2930 unsigned NumElems = VT.getVectorNumElements();
2931 SmallVector<int, 8> MaskVec;
2933 for (unsigned i = 0; i != NumElems; ++i) {
2934 int idx = SVOp->getMaskElt(i);
2936 MaskVec.push_back(idx);
2937 else if (idx < (int)NumElems)
2938 MaskVec.push_back(idx + NumElems);
2940 MaskVec.push_back(idx - NumElems);
2942 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1),
2943 SVOp->getOperand(0), &MaskVec[0]);
2946 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
2947 /// the two vector operands have swapped position.
2948 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, EVT VT) {
2949 unsigned NumElems = VT.getVectorNumElements();
2950 for (unsigned i = 0; i != NumElems; ++i) {
2954 else if (idx < (int)NumElems)
2955 Mask[i] = idx + NumElems;
2957 Mask[i] = idx - NumElems;
2961 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
2962 /// match movhlps. The lower half elements should come from upper half of
2963 /// V1 (and in order), and the upper half elements should come from the upper
2964 /// half of V2 (and in order).
2965 static bool ShouldXformToMOVHLPS(ShuffleVectorSDNode *Op) {
2966 if (Op->getValueType(0).getVectorNumElements() != 4)
2968 for (unsigned i = 0, e = 2; i != e; ++i)
2969 if (!isUndefOrEqual(Op->getMaskElt(i), i+2))
2971 for (unsigned i = 2; i != 4; ++i)
2972 if (!isUndefOrEqual(Op->getMaskElt(i), i+4))
2977 /// isScalarLoadToVector - Returns true if the node is a scalar load that
2978 /// is promoted to a vector. It also returns the LoadSDNode by reference if
2980 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
2981 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
2983 N = N->getOperand(0).getNode();
2984 if (!ISD::isNON_EXTLoad(N))
2987 *LD = cast<LoadSDNode>(N);
2991 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
2992 /// match movlp{s|d}. The lower half elements should come from lower half of
2993 /// V1 (and in order), and the upper half elements should come from the upper
2994 /// half of V2 (and in order). And since V1 will become the source of the
2995 /// MOVLP, it must be either a vector load or a scalar load to vector.
2996 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
2997 ShuffleVectorSDNode *Op) {
2998 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
3000 // Is V2 is a vector load, don't do this transformation. We will try to use
3001 // load folding shufps op.
3002 if (ISD::isNON_EXTLoad(V2))
3005 unsigned NumElems = Op->getValueType(0).getVectorNumElements();
3007 if (NumElems != 2 && NumElems != 4)
3009 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3010 if (!isUndefOrEqual(Op->getMaskElt(i), i))
3012 for (unsigned i = NumElems/2; i != NumElems; ++i)
3013 if (!isUndefOrEqual(Op->getMaskElt(i), i+NumElems))
3018 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
3020 static bool isSplatVector(SDNode *N) {
3021 if (N->getOpcode() != ISD::BUILD_VECTOR)
3024 SDValue SplatValue = N->getOperand(0);
3025 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
3026 if (N->getOperand(i) != SplatValue)
3031 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
3032 /// to an zero vector.
3033 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
3034 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
3035 SDValue V1 = N->getOperand(0);
3036 SDValue V2 = N->getOperand(1);
3037 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3038 for (unsigned i = 0; i != NumElems; ++i) {
3039 int Idx = N->getMaskElt(i);
3040 if (Idx >= (int)NumElems) {
3041 unsigned Opc = V2.getOpcode();
3042 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
3044 if (Opc != ISD::BUILD_VECTOR ||
3045 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
3047 } else if (Idx >= 0) {
3048 unsigned Opc = V1.getOpcode();
3049 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
3051 if (Opc != ISD::BUILD_VECTOR ||
3052 !X86::isZeroNode(V1.getOperand(Idx)))
3059 /// getZeroVector - Returns a vector of specified type with all zero elements.
3061 static SDValue getZeroVector(EVT VT, bool HasSSE2, SelectionDAG &DAG,
3063 assert(VT.isVector() && "Expected a vector type");
3065 // Always build zero vectors as <4 x i32> or <2 x i32> bitcasted to their dest
3066 // type. This ensures they get CSE'd.
3068 if (VT.getSizeInBits() == 64) { // MMX
3069 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
3070 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
3071 } else if (HasSSE2) { // SSE2
3072 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
3073 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
3075 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
3076 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
3078 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
3081 /// getOnesVector - Returns a vector of specified type with all bits set.
3083 static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
3084 assert(VT.isVector() && "Expected a vector type");
3086 // Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest
3087 // type. This ensures they get CSE'd.
3088 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
3090 if (VT.getSizeInBits() == 64) // MMX
3091 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
3093 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
3094 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
3098 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
3099 /// that point to V2 points to its first element.
3100 static SDValue NormalizeMask(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
3101 EVT VT = SVOp->getValueType(0);
3102 unsigned NumElems = VT.getVectorNumElements();
3104 bool Changed = false;
3105 SmallVector<int, 8> MaskVec;
3106 SVOp->getMask(MaskVec);
3108 for (unsigned i = 0; i != NumElems; ++i) {
3109 if (MaskVec[i] > (int)NumElems) {
3110 MaskVec[i] = NumElems;
3115 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(0),
3116 SVOp->getOperand(1), &MaskVec[0]);
3117 return SDValue(SVOp, 0);
3120 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
3121 /// operation of specified width.
3122 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3124 unsigned NumElems = VT.getVectorNumElements();
3125 SmallVector<int, 8> Mask;
3126 Mask.push_back(NumElems);
3127 for (unsigned i = 1; i != NumElems; ++i)
3129 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3132 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
3133 static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3135 unsigned NumElems = VT.getVectorNumElements();
3136 SmallVector<int, 8> Mask;
3137 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
3139 Mask.push_back(i + NumElems);
3141 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3144 /// getUnpackhMask - Returns a vector_shuffle node for an unpackh operation.
3145 static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3147 unsigned NumElems = VT.getVectorNumElements();
3148 unsigned Half = NumElems/2;
3149 SmallVector<int, 8> Mask;
3150 for (unsigned i = 0; i != Half; ++i) {
3151 Mask.push_back(i + Half);
3152 Mask.push_back(i + NumElems + Half);
3154 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3157 /// PromoteSplat - Promote a splat of v4f32, v8i16 or v16i8 to v4i32.
3158 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG,
3160 if (SV->getValueType(0).getVectorNumElements() <= 4)
3161 return SDValue(SV, 0);
3163 EVT PVT = MVT::v4f32;
3164 EVT VT = SV->getValueType(0);
3165 DebugLoc dl = SV->getDebugLoc();
3166 SDValue V1 = SV->getOperand(0);
3167 int NumElems = VT.getVectorNumElements();
3168 int EltNo = SV->getSplatIndex();
3170 // unpack elements to the correct location
3171 while (NumElems > 4) {
3172 if (EltNo < NumElems/2) {
3173 V1 = getUnpackl(DAG, dl, VT, V1, V1);
3175 V1 = getUnpackh(DAG, dl, VT, V1, V1);
3176 EltNo -= NumElems/2;
3181 // Perform the splat.
3182 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
3183 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, PVT, V1);
3184 V1 = DAG.getVectorShuffle(PVT, dl, V1, DAG.getUNDEF(PVT), &SplatMask[0]);
3185 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, V1);
3188 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
3189 /// vector of zero or undef vector. This produces a shuffle where the low
3190 /// element of V2 is swizzled into the zero/undef vector, landing at element
3191 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
3192 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
3193 bool isZero, bool HasSSE2,
3194 SelectionDAG &DAG) {
3195 EVT VT = V2.getValueType();
3197 ? getZeroVector(VT, HasSSE2, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT);
3198 unsigned NumElems = VT.getVectorNumElements();
3199 SmallVector<int, 16> MaskVec;
3200 for (unsigned i = 0; i != NumElems; ++i)
3201 // If this is the insertion idx, put the low elt of V2 here.
3202 MaskVec.push_back(i == Idx ? NumElems : i);
3203 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]);
3206 /// getNumOfConsecutiveZeros - Return the number of elements in a result of
3207 /// a shuffle that is zero.
3209 unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp, int NumElems,
3210 bool Low, SelectionDAG &DAG) {
3211 unsigned NumZeros = 0;
3212 for (int i = 0; i < NumElems; ++i) {
3213 unsigned Index = Low ? i : NumElems-i-1;
3214 int Idx = SVOp->getMaskElt(Index);
3219 SDValue Elt = DAG.getShuffleScalarElt(SVOp, Index);
3220 if (Elt.getNode() && X86::isZeroNode(Elt))
3228 /// isVectorShift - Returns true if the shuffle can be implemented as a
3229 /// logical left or right shift of a vector.
3230 /// FIXME: split into pslldqi, psrldqi, palignr variants.
3231 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
3232 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
3233 int NumElems = SVOp->getValueType(0).getVectorNumElements();
3236 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, true, DAG);
3239 NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, false, DAG);
3243 bool SeenV1 = false;
3244 bool SeenV2 = false;
3245 for (int i = NumZeros; i < NumElems; ++i) {
3246 int Val = isLeft ? (i - NumZeros) : i;
3247 int Idx = SVOp->getMaskElt(isLeft ? i : (i - NumZeros));
3259 if (SeenV1 && SeenV2)
3262 ShVal = SeenV1 ? SVOp->getOperand(0) : SVOp->getOperand(1);
3268 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
3270 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
3271 unsigned NumNonZero, unsigned NumZero,
3272 SelectionDAG &DAG, TargetLowering &TLI) {
3276 DebugLoc dl = Op.getDebugLoc();
3279 for (unsigned i = 0; i < 16; ++i) {
3280 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
3281 if (ThisIsNonZero && First) {
3283 V = getZeroVector(MVT::v8i16, true, DAG, dl);
3285 V = DAG.getUNDEF(MVT::v8i16);
3290 SDValue ThisElt(0, 0), LastElt(0, 0);
3291 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
3292 if (LastIsNonZero) {
3293 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
3294 MVT::i16, Op.getOperand(i-1));
3296 if (ThisIsNonZero) {
3297 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
3298 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
3299 ThisElt, DAG.getConstant(8, MVT::i8));
3301 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
3305 if (ThisElt.getNode())
3306 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
3307 DAG.getIntPtrConstant(i/2));
3311 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V);
3314 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
3316 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
3317 unsigned NumNonZero, unsigned NumZero,
3318 SelectionDAG &DAG, TargetLowering &TLI) {
3322 DebugLoc dl = Op.getDebugLoc();
3325 for (unsigned i = 0; i < 8; ++i) {
3326 bool isNonZero = (NonZeros & (1 << i)) != 0;
3330 V = getZeroVector(MVT::v8i16, true, DAG, dl);
3332 V = DAG.getUNDEF(MVT::v8i16);
3335 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
3336 MVT::v8i16, V, Op.getOperand(i),
3337 DAG.getIntPtrConstant(i));
3344 /// getVShift - Return a vector logical shift node.
3346 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
3347 unsigned NumBits, SelectionDAG &DAG,
3348 const TargetLowering &TLI, DebugLoc dl) {
3349 bool isMMX = VT.getSizeInBits() == 64;
3350 EVT ShVT = isMMX ? MVT::v1i64 : MVT::v2i64;
3351 unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL;
3352 SrcOp = DAG.getNode(ISD::BIT_CONVERT, dl, ShVT, SrcOp);
3353 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
3354 DAG.getNode(Opc, dl, ShVT, SrcOp,
3355 DAG.getConstant(NumBits, TLI.getShiftAmountTy())));
3359 X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
3360 SelectionDAG &DAG) {
3362 // Check if the scalar load can be widened into a vector load. And if
3363 // the address is "base + cst" see if the cst can be "absorbed" into
3364 // the shuffle mask.
3365 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
3366 SDValue Ptr = LD->getBasePtr();
3367 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
3369 EVT PVT = LD->getValueType(0);
3370 if (PVT != MVT::i32 && PVT != MVT::f32)
3375 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
3376 FI = FINode->getIndex();
3378 } else if (Ptr.getOpcode() == ISD::ADD &&
3379 isa<ConstantSDNode>(Ptr.getOperand(1)) &&
3380 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
3381 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
3382 Offset = Ptr.getConstantOperandVal(1);
3383 Ptr = Ptr.getOperand(0);
3388 SDValue Chain = LD->getChain();
3389 // Make sure the stack object alignment is at least 16.
3390 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
3391 if (DAG.InferPtrAlignment(Ptr) < 16) {
3392 if (MFI->isFixedObjectIndex(FI)) {
3393 // Can't change the alignment. Reference stack + offset explicitly
3394 // if stack pointer is at least 16-byte aligned.
3395 unsigned StackAlign = Subtarget->getStackAlignment();
3396 if (StackAlign < 16)
3398 Offset = MFI->getObjectOffset(FI) + Offset;
3399 SDValue StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr,
3401 Ptr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr,
3402 DAG.getConstant(Offset & ~15, getPointerTy()));
3405 MFI->setObjectAlignment(FI, 16);
3409 // (Offset % 16) must be multiple of 4. Then address is then
3410 // Ptr + (Offset & ~15).
3413 if ((Offset % 16) & 3)
3415 int64_t StartOffset = Offset & ~15;
3417 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(),
3418 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
3420 int EltNo = (Offset - StartOffset) >> 2;
3421 int Mask[4] = { EltNo, EltNo, EltNo, EltNo };
3422 EVT VT = (PVT == MVT::i32) ? MVT::v4i32 : MVT::v4f32;
3423 SDValue V1 = DAG.getLoad(VT, dl, Chain, Ptr,LD->getSrcValue(),0);
3424 // Canonicalize it to a v4i32 shuffle.
3425 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32, V1);
3426 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
3427 DAG.getVectorShuffle(MVT::v4i32, dl, V1,
3428 DAG.getUNDEF(MVT::v4i32), &Mask[0]));
3435 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
3436 DebugLoc dl = Op.getDebugLoc();
3437 // All zero's are handled with pxor, all one's are handled with pcmpeqd.
3438 if (ISD::isBuildVectorAllZeros(Op.getNode())
3439 || ISD::isBuildVectorAllOnes(Op.getNode())) {
3440 // Canonicalize this to either <4 x i32> or <2 x i32> (SSE vs MMX) to
3441 // 1) ensure the zero vectors are CSE'd, and 2) ensure that i64 scalars are
3442 // eliminated on x86-32 hosts.
3443 if (Op.getValueType() == MVT::v4i32 || Op.getValueType() == MVT::v2i32)
3446 if (ISD::isBuildVectorAllOnes(Op.getNode()))
3447 return getOnesVector(Op.getValueType(), DAG, dl);
3448 return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(), DAG, dl);
3451 EVT VT = Op.getValueType();
3452 EVT ExtVT = VT.getVectorElementType();
3453 unsigned EVTBits = ExtVT.getSizeInBits();
3455 unsigned NumElems = Op.getNumOperands();
3456 unsigned NumZero = 0;
3457 unsigned NumNonZero = 0;
3458 unsigned NonZeros = 0;
3459 bool IsAllConstants = true;
3460 SmallSet<SDValue, 8> Values;
3461 for (unsigned i = 0; i < NumElems; ++i) {
3462 SDValue Elt = Op.getOperand(i);
3463 if (Elt.getOpcode() == ISD::UNDEF)
3466 if (Elt.getOpcode() != ISD::Constant &&
3467 Elt.getOpcode() != ISD::ConstantFP)
3468 IsAllConstants = false;
3469 if (X86::isZeroNode(Elt))
3472 NonZeros |= (1 << i);
3477 if (NumNonZero == 0) {
3478 // All undef vector. Return an UNDEF. All zero vectors were handled above.
3479 return DAG.getUNDEF(VT);
3482 // Special case for single non-zero, non-undef, element.
3483 if (NumNonZero == 1) {
3484 unsigned Idx = CountTrailingZeros_32(NonZeros);
3485 SDValue Item = Op.getOperand(Idx);
3487 // If this is an insertion of an i64 value on x86-32, and if the top bits of
3488 // the value are obviously zero, truncate the value to i32 and do the
3489 // insertion that way. Only do this if the value is non-constant or if the
3490 // value is a constant being inserted into element 0. It is cheaper to do
3491 // a constant pool load than it is to do a movd + shuffle.
3492 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
3493 (!IsAllConstants || Idx == 0)) {
3494 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
3495 // Handle MMX and SSE both.
3496 EVT VecVT = VT == MVT::v2i64 ? MVT::v4i32 : MVT::v2i32;
3497 unsigned VecElts = VT == MVT::v2i64 ? 4 : 2;
3499 // Truncate the value (which may itself be a constant) to i32, and
3500 // convert it to a vector with movd (S2V+shuffle to zero extend).
3501 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
3502 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
3503 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
3504 Subtarget->hasSSE2(), DAG);
3506 // Now we have our 32-bit value zero extended in the low element of
3507 // a vector. If Idx != 0, swizzle it into place.
3509 SmallVector<int, 4> Mask;
3510 Mask.push_back(Idx);
3511 for (unsigned i = 1; i != VecElts; ++i)
3513 Item = DAG.getVectorShuffle(VecVT, dl, Item,
3514 DAG.getUNDEF(Item.getValueType()),
3517 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Item);
3521 // If we have a constant or non-constant insertion into the low element of
3522 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
3523 // the rest of the elements. This will be matched as movd/movq/movss/movsd
3524 // depending on what the source datatype is.
3527 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
3528 } else if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
3529 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
3530 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
3531 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
3532 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget->hasSSE2(),
3534 } else if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
3535 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
3536 EVT MiddleVT = VT.getSizeInBits() == 64 ? MVT::v2i32 : MVT::v4i32;
3537 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MiddleVT, Item);
3538 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
3539 Subtarget->hasSSE2(), DAG);
3540 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Item);
3544 // Is it a vector logical left shift?
3545 if (NumElems == 2 && Idx == 1 &&
3546 X86::isZeroNode(Op.getOperand(0)) &&
3547 !X86::isZeroNode(Op.getOperand(1))) {
3548 unsigned NumBits = VT.getSizeInBits();
3549 return getVShift(true, VT,
3550 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
3551 VT, Op.getOperand(1)),
3552 NumBits/2, DAG, *this, dl);
3555 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
3558 // Otherwise, if this is a vector with i32 or f32 elements, and the element
3559 // is a non-constant being inserted into an element other than the low one,
3560 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
3561 // movd/movss) to move this into the low element, then shuffle it into
3563 if (EVTBits == 32) {
3564 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
3566 // Turn it into a shuffle of zero and zero-extended scalar to vector.
3567 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0,
3568 Subtarget->hasSSE2(), DAG);
3569 SmallVector<int, 8> MaskVec;
3570 for (unsigned i = 0; i < NumElems; i++)
3571 MaskVec.push_back(i == Idx ? 0 : 1);
3572 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
3576 // Splat is obviously ok. Let legalizer expand it to a shuffle.
3577 if (Values.size() == 1) {
3578 if (EVTBits == 32) {
3579 // Instead of a shuffle like this:
3580 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
3581 // Check if it's possible to issue this instead.
3582 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
3583 unsigned Idx = CountTrailingZeros_32(NonZeros);
3584 SDValue Item = Op.getOperand(Idx);
3585 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
3586 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
3591 // A vector full of immediates; various special cases are already
3592 // handled, so this is best done with a single constant-pool load.
3596 // Let legalizer expand 2-wide build_vectors.
3597 if (EVTBits == 64) {
3598 if (NumNonZero == 1) {
3599 // One half is zero or undef.
3600 unsigned Idx = CountTrailingZeros_32(NonZeros);
3601 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
3602 Op.getOperand(Idx));
3603 return getShuffleVectorZeroOrUndef(V2, Idx, true,
3604 Subtarget->hasSSE2(), DAG);
3609 // If element VT is < 32 bits, convert it to inserts into a zero vector.
3610 if (EVTBits == 8 && NumElems == 16) {
3611 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
3613 if (V.getNode()) return V;
3616 if (EVTBits == 16 && NumElems == 8) {
3617 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
3619 if (V.getNode()) return V;
3622 // If element VT is == 32 bits, turn it into a number of shuffles.
3623 SmallVector<SDValue, 8> V;
3625 if (NumElems == 4 && NumZero > 0) {
3626 for (unsigned i = 0; i < 4; ++i) {
3627 bool isZero = !(NonZeros & (1 << i));
3629 V[i] = getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
3631 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
3634 for (unsigned i = 0; i < 2; ++i) {
3635 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
3638 V[i] = V[i*2]; // Must be a zero vector.
3641 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
3644 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
3647 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
3652 SmallVector<int, 8> MaskVec;
3653 bool Reverse = (NonZeros & 0x3) == 2;
3654 for (unsigned i = 0; i < 2; ++i)
3655 MaskVec.push_back(Reverse ? 1-i : i);
3656 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2;
3657 for (unsigned i = 0; i < 2; ++i)
3658 MaskVec.push_back(Reverse ? 1-i+NumElems : i+NumElems);
3659 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
3662 if (Values.size() > 2) {
3663 // If we have SSE 4.1, Expand into a number of inserts unless the number of
3664 // values to be inserted is equal to the number of elements, in which case
3665 // use the unpack code below in the hopes of matching the consecutive elts
3666 // load merge pattern for shuffles.
3667 // FIXME: We could probably just check that here directly.
3668 if (Values.size() < NumElems && VT.getSizeInBits() == 128 &&
3669 getSubtarget()->hasSSE41()) {
3670 V[0] = DAG.getUNDEF(VT);
3671 for (unsigned i = 0; i < NumElems; ++i)
3672 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
3673 V[0] = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, V[0],
3674 Op.getOperand(i), DAG.getIntPtrConstant(i));
3677 // Expand into a number of unpckl*.
3679 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
3680 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
3681 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
3682 for (unsigned i = 0; i < NumElems; ++i)
3683 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
3685 while (NumElems != 0) {
3686 for (unsigned i = 0; i < NumElems; ++i)
3687 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + NumElems]);
3696 // v8i16 shuffles - Prefer shuffles in the following order:
3697 // 1. [all] pshuflw, pshufhw, optional move
3698 // 2. [ssse3] 1 x pshufb
3699 // 3. [ssse3] 2 x pshufb + 1 x por
3700 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
3702 SDValue LowerVECTOR_SHUFFLEv8i16(ShuffleVectorSDNode *SVOp,
3703 SelectionDAG &DAG, X86TargetLowering &TLI) {
3704 SDValue V1 = SVOp->getOperand(0);
3705 SDValue V2 = SVOp->getOperand(1);
3706 DebugLoc dl = SVOp->getDebugLoc();
3707 SmallVector<int, 8> MaskVals;
3709 // Determine if more than 1 of the words in each of the low and high quadwords
3710 // of the result come from the same quadword of one of the two inputs. Undef
3711 // mask values count as coming from any quadword, for better codegen.
3712 SmallVector<unsigned, 4> LoQuad(4);
3713 SmallVector<unsigned, 4> HiQuad(4);
3714 BitVector InputQuads(4);
3715 for (unsigned i = 0; i < 8; ++i) {
3716 SmallVectorImpl<unsigned> &Quad = i < 4 ? LoQuad : HiQuad;
3717 int EltIdx = SVOp->getMaskElt(i);
3718 MaskVals.push_back(EltIdx);
3727 InputQuads.set(EltIdx / 4);
3730 int BestLoQuad = -1;
3731 unsigned MaxQuad = 1;
3732 for (unsigned i = 0; i < 4; ++i) {
3733 if (LoQuad[i] > MaxQuad) {
3735 MaxQuad = LoQuad[i];
3739 int BestHiQuad = -1;
3741 for (unsigned i = 0; i < 4; ++i) {
3742 if (HiQuad[i] > MaxQuad) {
3744 MaxQuad = HiQuad[i];
3748 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
3749 // of the two input vectors, shuffle them into one input vector so only a
3750 // single pshufb instruction is necessary. If There are more than 2 input
3751 // quads, disable the next transformation since it does not help SSSE3.
3752 bool V1Used = InputQuads[0] || InputQuads[1];
3753 bool V2Used = InputQuads[2] || InputQuads[3];
3754 if (TLI.getSubtarget()->hasSSSE3()) {
3755 if (InputQuads.count() == 2 && V1Used && V2Used) {
3756 BestLoQuad = InputQuads.find_first();
3757 BestHiQuad = InputQuads.find_next(BestLoQuad);
3759 if (InputQuads.count() > 2) {
3765 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
3766 // the shuffle mask. If a quad is scored as -1, that means that it contains
3767 // words from all 4 input quadwords.
3769 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
3770 SmallVector<int, 8> MaskV;
3771 MaskV.push_back(BestLoQuad < 0 ? 0 : BestLoQuad);
3772 MaskV.push_back(BestHiQuad < 0 ? 1 : BestHiQuad);
3773 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
3774 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V1),
3775 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V2), &MaskV[0]);
3776 NewV = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, NewV);
3778 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
3779 // source words for the shuffle, to aid later transformations.
3780 bool AllWordsInNewV = true;
3781 bool InOrder[2] = { true, true };
3782 for (unsigned i = 0; i != 8; ++i) {
3783 int idx = MaskVals[i];
3785 InOrder[i/4] = false;
3786 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
3788 AllWordsInNewV = false;
3792 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
3793 if (AllWordsInNewV) {
3794 for (int i = 0; i != 8; ++i) {
3795 int idx = MaskVals[i];
3798 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
3799 if ((idx != i) && idx < 4)
3801 if ((idx != i) && idx > 3)
3810 // If we've eliminated the use of V2, and the new mask is a pshuflw or
3811 // pshufhw, that's as cheap as it gets. Return the new shuffle.
3812 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
3813 return DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
3814 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
3818 // If we have SSSE3, and all words of the result are from 1 input vector,
3819 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
3820 // is present, fall back to case 4.
3821 if (TLI.getSubtarget()->hasSSSE3()) {
3822 SmallVector<SDValue,16> pshufbMask;
3824 // If we have elements from both input vectors, set the high bit of the
3825 // shuffle mask element to zero out elements that come from V2 in the V1
3826 // mask, and elements that come from V1 in the V2 mask, so that the two
3827 // results can be OR'd together.
3828 bool TwoInputs = V1Used && V2Used;
3829 for (unsigned i = 0; i != 8; ++i) {
3830 int EltIdx = MaskVals[i] * 2;
3831 if (TwoInputs && (EltIdx >= 16)) {
3832 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
3833 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
3836 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
3837 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8));
3839 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V1);
3840 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
3841 DAG.getNode(ISD::BUILD_VECTOR, dl,
3842 MVT::v16i8, &pshufbMask[0], 16));
3844 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
3846 // Calculate the shuffle mask for the second input, shuffle it, and
3847 // OR it with the first shuffled input.
3849 for (unsigned i = 0; i != 8; ++i) {
3850 int EltIdx = MaskVals[i] * 2;
3852 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
3853 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
3856 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
3857 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8));
3859 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V2);
3860 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
3861 DAG.getNode(ISD::BUILD_VECTOR, dl,
3862 MVT::v16i8, &pshufbMask[0], 16));
3863 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
3864 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
3867 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
3868 // and update MaskVals with new element order.
3869 BitVector InOrder(8);
3870 if (BestLoQuad >= 0) {
3871 SmallVector<int, 8> MaskV;
3872 for (int i = 0; i != 4; ++i) {
3873 int idx = MaskVals[i];
3875 MaskV.push_back(-1);
3877 } else if ((idx / 4) == BestLoQuad) {
3878 MaskV.push_back(idx & 3);
3881 MaskV.push_back(-1);
3884 for (unsigned i = 4; i != 8; ++i)
3886 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
3890 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
3891 // and update MaskVals with the new element order.
3892 if (BestHiQuad >= 0) {
3893 SmallVector<int, 8> MaskV;
3894 for (unsigned i = 0; i != 4; ++i)
3896 for (unsigned i = 4; i != 8; ++i) {
3897 int idx = MaskVals[i];
3899 MaskV.push_back(-1);
3901 } else if ((idx / 4) == BestHiQuad) {
3902 MaskV.push_back((idx & 3) + 4);
3905 MaskV.push_back(-1);
3908 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
3912 // In case BestHi & BestLo were both -1, which means each quadword has a word
3913 // from each of the four input quadwords, calculate the InOrder bitvector now
3914 // before falling through to the insert/extract cleanup.
3915 if (BestLoQuad == -1 && BestHiQuad == -1) {
3917 for (int i = 0; i != 8; ++i)
3918 if (MaskVals[i] < 0 || MaskVals[i] == i)
3922 // The other elements are put in the right place using pextrw and pinsrw.
3923 for (unsigned i = 0; i != 8; ++i) {
3926 int EltIdx = MaskVals[i];
3929 SDValue ExtOp = (EltIdx < 8)
3930 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
3931 DAG.getIntPtrConstant(EltIdx))
3932 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
3933 DAG.getIntPtrConstant(EltIdx - 8));
3934 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
3935 DAG.getIntPtrConstant(i));
3940 // v16i8 shuffles - Prefer shuffles in the following order:
3941 // 1. [ssse3] 1 x pshufb
3942 // 2. [ssse3] 2 x pshufb + 1 x por
3943 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
3945 SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
3946 SelectionDAG &DAG, X86TargetLowering &TLI) {
3947 SDValue V1 = SVOp->getOperand(0);
3948 SDValue V2 = SVOp->getOperand(1);
3949 DebugLoc dl = SVOp->getDebugLoc();
3950 SmallVector<int, 16> MaskVals;
3951 SVOp->getMask(MaskVals);
3953 // If we have SSSE3, case 1 is generated when all result bytes come from
3954 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
3955 // present, fall back to case 3.
3956 // FIXME: kill V2Only once shuffles are canonizalized by getNode.
3959 for (unsigned i = 0; i < 16; ++i) {
3960 int EltIdx = MaskVals[i];
3969 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
3970 if (TLI.getSubtarget()->hasSSSE3()) {
3971 SmallVector<SDValue,16> pshufbMask;
3973 // If all result elements are from one input vector, then only translate
3974 // undef mask values to 0x80 (zero out result) in the pshufb mask.
3976 // Otherwise, we have elements from both input vectors, and must zero out
3977 // elements that come from V2 in the first mask, and V1 in the second mask
3978 // so that we can OR them together.
3979 bool TwoInputs = !(V1Only || V2Only);
3980 for (unsigned i = 0; i != 16; ++i) {
3981 int EltIdx = MaskVals[i];
3982 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) {
3983 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
3986 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
3988 // If all the elements are from V2, assign it to V1 and return after
3989 // building the first pshufb.
3992 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
3993 DAG.getNode(ISD::BUILD_VECTOR, dl,
3994 MVT::v16i8, &pshufbMask[0], 16));
3998 // Calculate the shuffle mask for the second input, shuffle it, and
3999 // OR it with the first shuffled input.
4001 for (unsigned i = 0; i != 16; ++i) {
4002 int EltIdx = MaskVals[i];
4004 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4007 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
4009 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
4010 DAG.getNode(ISD::BUILD_VECTOR, dl,
4011 MVT::v16i8, &pshufbMask[0], 16));
4012 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
4015 // No SSSE3 - Calculate in place words and then fix all out of place words
4016 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
4017 // the 16 different words that comprise the two doublequadword input vectors.
4018 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
4019 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V2);
4020 SDValue NewV = V2Only ? V2 : V1;
4021 for (int i = 0; i != 8; ++i) {
4022 int Elt0 = MaskVals[i*2];
4023 int Elt1 = MaskVals[i*2+1];
4025 // This word of the result is all undef, skip it.
4026 if (Elt0 < 0 && Elt1 < 0)
4029 // This word of the result is already in the correct place, skip it.
4030 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1))
4032 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17))
4035 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
4036 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
4039 // If Elt0 and Elt1 are defined, are consecutive, and can be load
4040 // using a single extract together, load it and store it.
4041 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
4042 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
4043 DAG.getIntPtrConstant(Elt1 / 2));
4044 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
4045 DAG.getIntPtrConstant(i));
4049 // If Elt1 is defined, extract it from the appropriate source. If the
4050 // source byte is not also odd, shift the extracted word left 8 bits
4051 // otherwise clear the bottom 8 bits if we need to do an or.
4053 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
4054 DAG.getIntPtrConstant(Elt1 / 2));
4055 if ((Elt1 & 1) == 0)
4056 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
4057 DAG.getConstant(8, TLI.getShiftAmountTy()));
4059 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
4060 DAG.getConstant(0xFF00, MVT::i16));
4062 // If Elt0 is defined, extract it from the appropriate source. If the
4063 // source byte is not also even, shift the extracted word right 8 bits. If
4064 // Elt1 was also defined, OR the extracted values together before
4065 // inserting them in the result.
4067 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
4068 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
4069 if ((Elt0 & 1) != 0)
4070 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
4071 DAG.getConstant(8, TLI.getShiftAmountTy()));
4073 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
4074 DAG.getConstant(0x00FF, MVT::i16));
4075 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
4078 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
4079 DAG.getIntPtrConstant(i));
4081 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, NewV);
4084 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
4085 /// ones, or rewriting v4i32 / v2f32 as 2 wide ones if possible. This can be
4086 /// done when every pair / quad of shuffle mask elements point to elements in
4087 /// the right sequence. e.g.
4088 /// vector_shuffle <>, <>, < 3, 4, | 10, 11, | 0, 1, | 14, 15>
4090 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
4092 TargetLowering &TLI, DebugLoc dl) {
4093 EVT VT = SVOp->getValueType(0);
4094 SDValue V1 = SVOp->getOperand(0);
4095 SDValue V2 = SVOp->getOperand(1);
4096 unsigned NumElems = VT.getVectorNumElements();
4097 unsigned NewWidth = (NumElems == 4) ? 2 : 4;
4098 EVT MaskVT = MVT::getIntVectorWithNumElements(NewWidth);
4099 EVT MaskEltVT = MaskVT.getVectorElementType();
4101 switch (VT.getSimpleVT().SimpleTy) {
4102 default: assert(false && "Unexpected!");
4103 case MVT::v4f32: NewVT = MVT::v2f64; break;
4104 case MVT::v4i32: NewVT = MVT::v2i64; break;
4105 case MVT::v8i16: NewVT = MVT::v4i32; break;
4106 case MVT::v16i8: NewVT = MVT::v4i32; break;
4109 if (NewWidth == 2) {
4115 int Scale = NumElems / NewWidth;
4116 SmallVector<int, 8> MaskVec;
4117 for (unsigned i = 0; i < NumElems; i += Scale) {
4119 for (int j = 0; j < Scale; ++j) {
4120 int EltIdx = SVOp->getMaskElt(i+j);
4124 StartIdx = EltIdx - (EltIdx % Scale);
4125 if (EltIdx != StartIdx + j)
4129 MaskVec.push_back(-1);
4131 MaskVec.push_back(StartIdx / Scale);
4134 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V1);
4135 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V2);
4136 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
4139 /// getVZextMovL - Return a zero-extending vector move low node.
4141 static SDValue getVZextMovL(EVT VT, EVT OpVT,
4142 SDValue SrcOp, SelectionDAG &DAG,
4143 const X86Subtarget *Subtarget, DebugLoc dl) {
4144 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
4145 LoadSDNode *LD = NULL;
4146 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
4147 LD = dyn_cast<LoadSDNode>(SrcOp);
4149 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
4151 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
4152 if ((ExtVT.SimpleTy != MVT::i64 || Subtarget->is64Bit()) &&
4153 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
4154 SrcOp.getOperand(0).getOpcode() == ISD::BIT_CONVERT &&
4155 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
4157 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
4158 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
4159 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
4160 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
4168 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
4169 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
4170 DAG.getNode(ISD::BIT_CONVERT, dl,
4174 /// LowerVECTOR_SHUFFLE_4wide - Handle all 4 wide cases with a number of
4177 LowerVECTOR_SHUFFLE_4wide(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
4178 SDValue V1 = SVOp->getOperand(0);
4179 SDValue V2 = SVOp->getOperand(1);
4180 DebugLoc dl = SVOp->getDebugLoc();
4181 EVT VT = SVOp->getValueType(0);
4183 SmallVector<std::pair<int, int>, 8> Locs;
4185 SmallVector<int, 8> Mask1(4U, -1);
4186 SmallVector<int, 8> PermMask;
4187 SVOp->getMask(PermMask);
4191 for (unsigned i = 0; i != 4; ++i) {
4192 int Idx = PermMask[i];
4194 Locs[i] = std::make_pair(-1, -1);
4196 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
4198 Locs[i] = std::make_pair(0, NumLo);
4202 Locs[i] = std::make_pair(1, NumHi);
4204 Mask1[2+NumHi] = Idx;
4210 if (NumLo <= 2 && NumHi <= 2) {
4211 // If no more than two elements come from either vector. This can be
4212 // implemented with two shuffles. First shuffle gather the elements.
4213 // The second shuffle, which takes the first shuffle as both of its
4214 // vector operands, put the elements into the right order.
4215 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
4217 SmallVector<int, 8> Mask2(4U, -1);
4219 for (unsigned i = 0; i != 4; ++i) {
4220 if (Locs[i].first == -1)
4223 unsigned Idx = (i < 2) ? 0 : 4;
4224 Idx += Locs[i].first * 2 + Locs[i].second;
4229 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
4230 } else if (NumLo == 3 || NumHi == 3) {
4231 // Otherwise, we must have three elements from one vector, call it X, and
4232 // one element from the other, call it Y. First, use a shufps to build an
4233 // intermediate vector with the one element from Y and the element from X
4234 // that will be in the same half in the final destination (the indexes don't
4235 // matter). Then, use a shufps to build the final vector, taking the half
4236 // containing the element from Y from the intermediate, and the other half
4239 // Normalize it so the 3 elements come from V1.
4240 CommuteVectorShuffleMask(PermMask, VT);
4244 // Find the element from V2.
4246 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
4247 int Val = PermMask[HiIndex];
4254 Mask1[0] = PermMask[HiIndex];
4256 Mask1[2] = PermMask[HiIndex^1];
4258 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
4261 Mask1[0] = PermMask[0];
4262 Mask1[1] = PermMask[1];
4263 Mask1[2] = HiIndex & 1 ? 6 : 4;
4264 Mask1[3] = HiIndex & 1 ? 4 : 6;
4265 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
4267 Mask1[0] = HiIndex & 1 ? 2 : 0;
4268 Mask1[1] = HiIndex & 1 ? 0 : 2;
4269 Mask1[2] = PermMask[2];
4270 Mask1[3] = PermMask[3];
4275 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
4279 // Break it into (shuffle shuffle_hi, shuffle_lo).
4281 SmallVector<int,8> LoMask(4U, -1);
4282 SmallVector<int,8> HiMask(4U, -1);
4284 SmallVector<int,8> *MaskPtr = &LoMask;
4285 unsigned MaskIdx = 0;
4288 for (unsigned i = 0; i != 4; ++i) {
4295 int Idx = PermMask[i];
4297 Locs[i] = std::make_pair(-1, -1);
4298 } else if (Idx < 4) {
4299 Locs[i] = std::make_pair(MaskIdx, LoIdx);
4300 (*MaskPtr)[LoIdx] = Idx;
4303 Locs[i] = std::make_pair(MaskIdx, HiIdx);
4304 (*MaskPtr)[HiIdx] = Idx;
4309 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
4310 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
4311 SmallVector<int, 8> MaskOps;
4312 for (unsigned i = 0; i != 4; ++i) {
4313 if (Locs[i].first == -1) {
4314 MaskOps.push_back(-1);
4316 unsigned Idx = Locs[i].first * 4 + Locs[i].second;
4317 MaskOps.push_back(Idx);
4320 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
4324 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
4325 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
4326 SDValue V1 = Op.getOperand(0);
4327 SDValue V2 = Op.getOperand(1);
4328 EVT VT = Op.getValueType();
4329 DebugLoc dl = Op.getDebugLoc();
4330 unsigned NumElems = VT.getVectorNumElements();
4331 bool isMMX = VT.getSizeInBits() == 64;
4332 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
4333 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
4334 bool V1IsSplat = false;
4335 bool V2IsSplat = false;
4337 if (isZeroShuffle(SVOp))
4338 return getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
4340 // Promote splats to v4f32.
4341 if (SVOp->isSplat()) {
4342 if (isMMX || NumElems < 4)
4344 return PromoteSplat(SVOp, DAG, Subtarget->hasSSE2());
4347 // If the shuffle can be profitably rewritten as a narrower shuffle, then
4349 if (VT == MVT::v8i16 || VT == MVT::v16i8) {
4350 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl);
4351 if (NewOp.getNode())
4352 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
4353 LowerVECTOR_SHUFFLE(NewOp, DAG));
4354 } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
4355 // FIXME: Figure out a cleaner way to do this.
4356 // Try to make use of movq to zero out the top part.
4357 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
4358 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl);
4359 if (NewOp.getNode()) {
4360 if (isCommutedMOVL(cast<ShuffleVectorSDNode>(NewOp), true, false))
4361 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(0),
4362 DAG, Subtarget, dl);
4364 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
4365 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl);
4366 if (NewOp.getNode() && X86::isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)))
4367 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1),
4368 DAG, Subtarget, dl);
4372 if (X86::isPSHUFDMask(SVOp))
4375 // Check if this can be converted into a logical shift.
4376 bool isLeft = false;
4379 bool isShift = getSubtarget()->hasSSE2() &&
4380 isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
4381 if (isShift && ShVal.hasOneUse()) {
4382 // If the shifted value has multiple uses, it may be cheaper to use
4383 // v_set0 + movlhps or movhlps, etc.
4384 EVT EltVT = VT.getVectorElementType();
4385 ShAmt *= EltVT.getSizeInBits();
4386 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
4389 if (X86::isMOVLMask(SVOp)) {
4392 if (ISD::isBuildVectorAllZeros(V1.getNode()))
4393 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
4398 // FIXME: fold these into legal mask.
4399 if (!isMMX && (X86::isMOVSHDUPMask(SVOp) ||
4400 X86::isMOVSLDUPMask(SVOp) ||
4401 X86::isMOVHLPSMask(SVOp) ||
4402 X86::isMOVLHPSMask(SVOp) ||
4403 X86::isMOVLPMask(SVOp)))
4406 if (ShouldXformToMOVHLPS(SVOp) ||
4407 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), SVOp))
4408 return CommuteVectorShuffle(SVOp, DAG);
4411 // No better options. Use a vshl / vsrl.
4412 EVT EltVT = VT.getVectorElementType();
4413 ShAmt *= EltVT.getSizeInBits();
4414 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
4417 bool Commuted = false;
4418 // FIXME: This should also accept a bitcast of a splat? Be careful, not
4419 // 1,1,1,1 -> v8i16 though.
4420 V1IsSplat = isSplatVector(V1.getNode());
4421 V2IsSplat = isSplatVector(V2.getNode());
4423 // Canonicalize the splat or undef, if present, to be on the RHS.
4424 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) {
4425 Op = CommuteVectorShuffle(SVOp, DAG);
4426 SVOp = cast<ShuffleVectorSDNode>(Op);
4427 V1 = SVOp->getOperand(0);
4428 V2 = SVOp->getOperand(1);
4429 std::swap(V1IsSplat, V2IsSplat);
4430 std::swap(V1IsUndef, V2IsUndef);
4434 if (isCommutedMOVL(SVOp, V2IsSplat, V2IsUndef)) {
4435 // Shuffling low element of v1 into undef, just return v1.
4438 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
4439 // the instruction selector will not match, so get a canonical MOVL with
4440 // swapped operands to undo the commute.
4441 return getMOVL(DAG, dl, VT, V2, V1);
4444 if (X86::isUNPCKL_v_undef_Mask(SVOp) ||
4445 X86::isUNPCKH_v_undef_Mask(SVOp) ||
4446 X86::isUNPCKLMask(SVOp) ||
4447 X86::isUNPCKHMask(SVOp))
4451 // Normalize mask so all entries that point to V2 points to its first
4452 // element then try to match unpck{h|l} again. If match, return a
4453 // new vector_shuffle with the corrected mask.
4454 SDValue NewMask = NormalizeMask(SVOp, DAG);
4455 ShuffleVectorSDNode *NSVOp = cast<ShuffleVectorSDNode>(NewMask);
4456 if (NSVOp != SVOp) {
4457 if (X86::isUNPCKLMask(NSVOp, true)) {
4459 } else if (X86::isUNPCKHMask(NSVOp, true)) {
4466 // Commute is back and try unpck* again.
4467 // FIXME: this seems wrong.
4468 SDValue NewOp = CommuteVectorShuffle(SVOp, DAG);
4469 ShuffleVectorSDNode *NewSVOp = cast<ShuffleVectorSDNode>(NewOp);
4470 if (X86::isUNPCKL_v_undef_Mask(NewSVOp) ||
4471 X86::isUNPCKH_v_undef_Mask(NewSVOp) ||
4472 X86::isUNPCKLMask(NewSVOp) ||
4473 X86::isUNPCKHMask(NewSVOp))
4477 // FIXME: for mmx, bitcast v2i32 to v4i16 for shuffle.
4479 // Normalize the node to match x86 shuffle ops if needed
4480 if (!isMMX && V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(SVOp))
4481 return CommuteVectorShuffle(SVOp, DAG);
4483 // Check for legal shuffle and return?
4484 SmallVector<int, 16> PermMask;
4485 SVOp->getMask(PermMask);
4486 if (isShuffleMaskLegal(PermMask, VT))
4489 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
4490 if (VT == MVT::v8i16) {
4491 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(SVOp, DAG, *this);
4492 if (NewOp.getNode())
4496 if (VT == MVT::v16i8) {
4497 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this);
4498 if (NewOp.getNode())
4502 // Handle all 4 wide cases with a number of shuffles except for MMX.
4503 if (NumElems == 4 && !isMMX)
4504 return LowerVECTOR_SHUFFLE_4wide(SVOp, DAG);
4510 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
4511 SelectionDAG &DAG) {
4512 EVT VT = Op.getValueType();
4513 DebugLoc dl = Op.getDebugLoc();
4514 if (VT.getSizeInBits() == 8) {
4515 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
4516 Op.getOperand(0), Op.getOperand(1));
4517 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
4518 DAG.getValueType(VT));
4519 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
4520 } else if (VT.getSizeInBits() == 16) {
4521 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4522 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
4524 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
4525 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
4526 DAG.getNode(ISD::BIT_CONVERT, dl,
4530 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
4531 Op.getOperand(0), Op.getOperand(1));
4532 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
4533 DAG.getValueType(VT));
4534 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
4535 } else if (VT == MVT::f32) {
4536 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
4537 // the result back to FR32 register. It's only worth matching if the
4538 // result has a single use which is a store or a bitcast to i32. And in
4539 // the case of a store, it's not worth it if the index is a constant 0,
4540 // because a MOVSSmr can be used instead, which is smaller and faster.
4541 if (!Op.hasOneUse())
4543 SDNode *User = *Op.getNode()->use_begin();
4544 if ((User->getOpcode() != ISD::STORE ||
4545 (isa<ConstantSDNode>(Op.getOperand(1)) &&
4546 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
4547 (User->getOpcode() != ISD::BIT_CONVERT ||
4548 User->getValueType(0) != MVT::i32))
4550 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
4551 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32,
4554 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Extract);
4555 } else if (VT == MVT::i32) {
4556 // ExtractPS works with constant index.
4557 if (isa<ConstantSDNode>(Op.getOperand(1)))
4565 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
4566 if (!isa<ConstantSDNode>(Op.getOperand(1)))
4569 if (Subtarget->hasSSE41()) {
4570 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
4575 EVT VT = Op.getValueType();
4576 DebugLoc dl = Op.getDebugLoc();
4577 // TODO: handle v16i8.
4578 if (VT.getSizeInBits() == 16) {
4579 SDValue Vec = Op.getOperand(0);
4580 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4582 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
4583 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
4584 DAG.getNode(ISD::BIT_CONVERT, dl,
4587 // Transform it so it match pextrw which produces a 32-bit result.
4588 EVT EltVT = MVT::i32;
4589 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
4590 Op.getOperand(0), Op.getOperand(1));
4591 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
4592 DAG.getValueType(VT));
4593 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
4594 } else if (VT.getSizeInBits() == 32) {
4595 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4599 // SHUFPS the element to the lowest double word, then movss.
4600 int Mask[4] = { Idx, -1, -1, -1 };
4601 EVT VVT = Op.getOperand(0).getValueType();
4602 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
4603 DAG.getUNDEF(VVT), Mask);
4604 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
4605 DAG.getIntPtrConstant(0));
4606 } else if (VT.getSizeInBits() == 64) {
4607 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
4608 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
4609 // to match extract_elt for f64.
4610 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4614 // UNPCKHPD the element to the lowest double word, then movsd.
4615 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
4616 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
4617 int Mask[2] = { 1, -1 };
4618 EVT VVT = Op.getOperand(0).getValueType();
4619 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
4620 DAG.getUNDEF(VVT), Mask);
4621 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
4622 DAG.getIntPtrConstant(0));
4629 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG){
4630 EVT VT = Op.getValueType();
4631 EVT EltVT = VT.getVectorElementType();
4632 DebugLoc dl = Op.getDebugLoc();
4634 SDValue N0 = Op.getOperand(0);
4635 SDValue N1 = Op.getOperand(1);
4636 SDValue N2 = Op.getOperand(2);
4638 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
4639 isa<ConstantSDNode>(N2)) {
4640 unsigned Opc = (EltVT.getSizeInBits() == 8) ? X86ISD::PINSRB
4642 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
4644 if (N1.getValueType() != MVT::i32)
4645 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
4646 if (N2.getValueType() != MVT::i32)
4647 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
4648 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
4649 } else if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
4650 // Bits [7:6] of the constant are the source select. This will always be
4651 // zero here. The DAG Combiner may combine an extract_elt index into these
4652 // bits. For example (insert (extract, 3), 2) could be matched by putting
4653 // the '3' into bits [7:6] of X86ISD::INSERTPS.
4654 // Bits [5:4] of the constant are the destination select. This is the
4655 // value of the incoming immediate.
4656 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
4657 // combine either bitwise AND or insert of float 0.0 to set these bits.
4658 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
4659 // Create this as a scalar to vector..
4660 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
4661 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
4662 } else if (EltVT == MVT::i32 && isa<ConstantSDNode>(N2)) {
4663 // PINSR* works with constant index.
4670 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
4671 EVT VT = Op.getValueType();
4672 EVT EltVT = VT.getVectorElementType();
4674 if (Subtarget->hasSSE41())
4675 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
4677 if (EltVT == MVT::i8)
4680 DebugLoc dl = Op.getDebugLoc();
4681 SDValue N0 = Op.getOperand(0);
4682 SDValue N1 = Op.getOperand(1);
4683 SDValue N2 = Op.getOperand(2);
4685 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
4686 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
4687 // as its second argument.
4688 if (N1.getValueType() != MVT::i32)
4689 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
4690 if (N2.getValueType() != MVT::i32)
4691 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
4692 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
4698 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
4699 DebugLoc dl = Op.getDebugLoc();
4700 if (Op.getValueType() == MVT::v2f32)
4701 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f32,
4702 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i32,
4703 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32,
4704 Op.getOperand(0))));
4706 if (Op.getValueType() == MVT::v1i64 && Op.getOperand(0).getValueType() == MVT::i64)
4707 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
4709 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
4710 EVT VT = MVT::v2i32;
4711 switch (Op.getValueType().getSimpleVT().SimpleTy) {
4718 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(),
4719 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, AnyExt));
4722 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
4723 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
4724 // one of the above mentioned nodes. It has to be wrapped because otherwise
4725 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
4726 // be used to form addressing mode. These wrapped nodes will be selected
4729 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
4730 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
4732 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
4734 unsigned char OpFlag = 0;
4735 unsigned WrapperKind = X86ISD::Wrapper;
4736 CodeModel::Model M = getTargetMachine().getCodeModel();
4738 if (Subtarget->isPICStyleRIPRel() &&
4739 (M == CodeModel::Small || M == CodeModel::Kernel))
4740 WrapperKind = X86ISD::WrapperRIP;
4741 else if (Subtarget->isPICStyleGOT())
4742 OpFlag = X86II::MO_GOTOFF;
4743 else if (Subtarget->isPICStyleStubPIC())
4744 OpFlag = X86II::MO_PIC_BASE_OFFSET;
4746 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
4748 CP->getOffset(), OpFlag);
4749 DebugLoc DL = CP->getDebugLoc();
4750 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
4751 // With PIC, the address is actually $g + Offset.
4753 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
4754 DAG.getNode(X86ISD::GlobalBaseReg,
4755 DebugLoc::getUnknownLoc(), getPointerTy()),
4762 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) {
4763 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
4765 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
4767 unsigned char OpFlag = 0;
4768 unsigned WrapperKind = X86ISD::Wrapper;
4769 CodeModel::Model M = getTargetMachine().getCodeModel();
4771 if (Subtarget->isPICStyleRIPRel() &&
4772 (M == CodeModel::Small || M == CodeModel::Kernel))
4773 WrapperKind = X86ISD::WrapperRIP;
4774 else if (Subtarget->isPICStyleGOT())
4775 OpFlag = X86II::MO_GOTOFF;
4776 else if (Subtarget->isPICStyleStubPIC())
4777 OpFlag = X86II::MO_PIC_BASE_OFFSET;
4779 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
4781 DebugLoc DL = JT->getDebugLoc();
4782 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
4784 // With PIC, the address is actually $g + Offset.
4786 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
4787 DAG.getNode(X86ISD::GlobalBaseReg,
4788 DebugLoc::getUnknownLoc(), getPointerTy()),
4796 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) {
4797 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
4799 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
4801 unsigned char OpFlag = 0;
4802 unsigned WrapperKind = X86ISD::Wrapper;
4803 CodeModel::Model M = getTargetMachine().getCodeModel();
4805 if (Subtarget->isPICStyleRIPRel() &&
4806 (M == CodeModel::Small || M == CodeModel::Kernel))
4807 WrapperKind = X86ISD::WrapperRIP;
4808 else if (Subtarget->isPICStyleGOT())
4809 OpFlag = X86II::MO_GOTOFF;
4810 else if (Subtarget->isPICStyleStubPIC())
4811 OpFlag = X86II::MO_PIC_BASE_OFFSET;
4813 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
4815 DebugLoc DL = Op.getDebugLoc();
4816 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
4819 // With PIC, the address is actually $g + Offset.
4820 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
4821 !Subtarget->is64Bit()) {
4822 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
4823 DAG.getNode(X86ISD::GlobalBaseReg,
4824 DebugLoc::getUnknownLoc(),
4833 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) {
4834 // Create the TargetBlockAddressAddress node.
4835 unsigned char OpFlags =
4836 Subtarget->ClassifyBlockAddressReference();
4837 CodeModel::Model M = getTargetMachine().getCodeModel();
4838 BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
4839 DebugLoc dl = Op.getDebugLoc();
4840 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(),
4841 /*isTarget=*/true, OpFlags);
4843 if (Subtarget->isPICStyleRIPRel() &&
4844 (M == CodeModel::Small || M == CodeModel::Kernel))
4845 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
4847 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
4849 // With PIC, the address is actually $g + Offset.
4850 if (isGlobalRelativeToPICBase(OpFlags)) {
4851 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
4852 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
4860 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
4862 SelectionDAG &DAG) const {
4863 // Create the TargetGlobalAddress node, folding in the constant
4864 // offset if it is legal.
4865 unsigned char OpFlags =
4866 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
4867 CodeModel::Model M = getTargetMachine().getCodeModel();
4869 if (OpFlags == X86II::MO_NO_FLAG &&
4870 X86::isOffsetSuitableForCodeModel(Offset, M)) {
4871 // A direct static reference to a global.
4872 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), Offset);
4875 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), 0, OpFlags);
4878 if (Subtarget->isPICStyleRIPRel() &&
4879 (M == CodeModel::Small || M == CodeModel::Kernel))
4880 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
4882 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
4884 // With PIC, the address is actually $g + Offset.
4885 if (isGlobalRelativeToPICBase(OpFlags)) {
4886 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
4887 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
4891 // For globals that require a load from a stub to get the address, emit the
4893 if (isGlobalStubReference(OpFlags))
4894 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
4895 PseudoSourceValue::getGOT(), 0);
4897 // If there was a non-zero offset that we didn't fold, create an explicit
4900 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
4901 DAG.getConstant(Offset, getPointerTy()));
4907 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) {
4908 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
4909 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
4910 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
4914 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
4915 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
4916 unsigned char OperandFlags) {
4917 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4918 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
4919 DebugLoc dl = GA->getDebugLoc();
4920 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
4921 GA->getValueType(0),
4925 SDValue Ops[] = { Chain, TGA, *InFlag };
4926 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3);
4928 SDValue Ops[] = { Chain, TGA };
4929 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2);
4932 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
4933 MFI->setHasCalls(true);
4935 SDValue Flag = Chain.getValue(1);
4936 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
4939 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
4941 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
4944 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
4945 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
4946 DAG.getNode(X86ISD::GlobalBaseReg,
4947 DebugLoc::getUnknownLoc(),
4949 InFlag = Chain.getValue(1);
4951 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
4954 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
4956 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
4958 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
4959 X86::RAX, X86II::MO_TLSGD);
4962 // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
4963 // "local exec" model.
4964 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
4965 const EVT PtrVT, TLSModel::Model model,
4967 DebugLoc dl = GA->getDebugLoc();
4968 // Get the Thread Pointer
4969 SDValue Base = DAG.getNode(X86ISD::SegmentBaseAddress,
4970 DebugLoc::getUnknownLoc(), PtrVT,
4971 DAG.getRegister(is64Bit? X86::FS : X86::GS,
4974 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Base,
4977 unsigned char OperandFlags = 0;
4978 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
4980 unsigned WrapperKind = X86ISD::Wrapper;
4981 if (model == TLSModel::LocalExec) {
4982 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
4983 } else if (is64Bit) {
4984 assert(model == TLSModel::InitialExec);
4985 OperandFlags = X86II::MO_GOTTPOFF;
4986 WrapperKind = X86ISD::WrapperRIP;
4988 assert(model == TLSModel::InitialExec);
4989 OperandFlags = X86II::MO_INDNTPOFF;
4992 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
4994 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), GA->getValueType(0),
4995 GA->getOffset(), OperandFlags);
4996 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
4998 if (model == TLSModel::InitialExec)
4999 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
5000 PseudoSourceValue::getGOT(), 0);
5002 // The address of the thread local variable is the add of the thread
5003 // pointer with the offset of the variable.
5004 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
5008 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) {
5009 // TODO: implement the "local dynamic" model
5010 // TODO: implement the "initial exec"model for pic executables
5011 assert(Subtarget->isTargetELF() &&
5012 "TLS not implemented for non-ELF targets");
5013 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
5014 const GlobalValue *GV = GA->getGlobal();
5016 // If GV is an alias then use the aliasee for determining
5017 // thread-localness.
5018 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
5019 GV = GA->resolveAliasedGlobal(false);
5021 TLSModel::Model model = getTLSModel(GV,
5022 getTargetMachine().getRelocationModel());
5025 case TLSModel::GeneralDynamic:
5026 case TLSModel::LocalDynamic: // not implemented
5027 if (Subtarget->is64Bit())
5028 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
5029 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
5031 case TLSModel::InitialExec:
5032 case TLSModel::LocalExec:
5033 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
5034 Subtarget->is64Bit());
5037 llvm_unreachable("Unreachable");
5042 /// LowerShift - Lower SRA_PARTS and friends, which return two i32 values and
5043 /// take a 2 x i32 value to shift plus a shift amount.
5044 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) {
5045 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
5046 EVT VT = Op.getValueType();
5047 unsigned VTBits = VT.getSizeInBits();
5048 DebugLoc dl = Op.getDebugLoc();
5049 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
5050 SDValue ShOpLo = Op.getOperand(0);
5051 SDValue ShOpHi = Op.getOperand(1);
5052 SDValue ShAmt = Op.getOperand(2);
5053 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
5054 DAG.getConstant(VTBits - 1, MVT::i8))
5055 : DAG.getConstant(0, VT);
5058 if (Op.getOpcode() == ISD::SHL_PARTS) {
5059 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
5060 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
5062 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
5063 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
5066 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
5067 DAG.getConstant(VTBits, MVT::i8));
5068 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, VT,
5069 AndNode, DAG.getConstant(0, MVT::i8));
5072 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
5073 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
5074 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
5076 if (Op.getOpcode() == ISD::SHL_PARTS) {
5077 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
5078 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
5080 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
5081 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
5084 SDValue Ops[2] = { Lo, Hi };
5085 return DAG.getMergeValues(Ops, 2, dl);
5088 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
5089 EVT SrcVT = Op.getOperand(0).getValueType();
5091 if (SrcVT.isVector()) {
5092 if (SrcVT == MVT::v2i32 && Op.getValueType() == MVT::v2f64) {
5098 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
5099 "Unknown SINT_TO_FP to lower!");
5101 // These are really Legal; return the operand so the caller accepts it as
5103 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
5105 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
5106 Subtarget->is64Bit()) {
5110 DebugLoc dl = Op.getDebugLoc();
5111 unsigned Size = SrcVT.getSizeInBits()/8;
5112 MachineFunction &MF = DAG.getMachineFunction();
5113 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
5114 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5115 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
5117 PseudoSourceValue::getFixedStack(SSFI), 0);
5118 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
5121 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
5123 SelectionDAG &DAG) {
5125 DebugLoc dl = Op.getDebugLoc();
5127 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
5129 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag);
5131 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
5132 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
5133 SDValue Result = DAG.getNode(useSSE ? X86ISD::FILD_FLAG : X86ISD::FILD, dl,
5134 Tys, Ops, array_lengthof(Ops));
5137 Chain = Result.getValue(1);
5138 SDValue InFlag = Result.getValue(2);
5140 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
5141 // shouldn't be necessary except that RFP cannot be live across
5142 // multiple blocks. When stackifier is fixed, they can be uncoupled.
5143 MachineFunction &MF = DAG.getMachineFunction();
5144 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
5145 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5146 Tys = DAG.getVTList(MVT::Other);
5148 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
5150 Chain = DAG.getNode(X86ISD::FST, dl, Tys, Ops, array_lengthof(Ops));
5151 Result = DAG.getLoad(Op.getValueType(), dl, Chain, StackSlot,
5152 PseudoSourceValue::getFixedStack(SSFI), 0);
5158 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
5159 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) {
5160 // This algorithm is not obvious. Here it is in C code, more or less:
5162 double uint64_to_double( uint32_t hi, uint32_t lo ) {
5163 static const __m128i exp = { 0x4330000045300000ULL, 0 };
5164 static const __m128d bias = { 0x1.0p84, 0x1.0p52 };
5166 // Copy ints to xmm registers.
5167 __m128i xh = _mm_cvtsi32_si128( hi );
5168 __m128i xl = _mm_cvtsi32_si128( lo );
5170 // Combine into low half of a single xmm register.
5171 __m128i x = _mm_unpacklo_epi32( xh, xl );
5175 // Merge in appropriate exponents to give the integer bits the right
5177 x = _mm_unpacklo_epi32( x, exp );
5179 // Subtract away the biases to deal with the IEEE-754 double precision
5181 d = _mm_sub_pd( (__m128d) x, bias );
5183 // All conversions up to here are exact. The correctly rounded result is
5184 // calculated using the current rounding mode using the following
5186 d = _mm_add_sd( d, _mm_unpackhi_pd( d, d ) );
5187 _mm_store_sd( &sd, d ); // Because we are returning doubles in XMM, this
5188 // store doesn't really need to be here (except
5189 // maybe to zero the other double)
5194 DebugLoc dl = Op.getDebugLoc();
5195 LLVMContext *Context = DAG.getContext();
5197 // Build some magic constants.
5198 std::vector<Constant*> CV0;
5199 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x45300000)));
5200 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x43300000)));
5201 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
5202 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
5203 Constant *C0 = ConstantVector::get(CV0);
5204 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
5206 std::vector<Constant*> CV1;
5208 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL))));
5210 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL))));
5211 Constant *C1 = ConstantVector::get(CV1);
5212 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
5214 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
5215 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
5217 DAG.getIntPtrConstant(1)));
5218 SDValue XR2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
5219 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
5221 DAG.getIntPtrConstant(0)));
5222 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, XR1, XR2);
5223 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
5224 PseudoSourceValue::getConstantPool(), 0,
5226 SDValue Unpck2 = getUnpackl(DAG, dl, MVT::v4i32, Unpck1, CLod0);
5227 SDValue XR2F = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Unpck2);
5228 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
5229 PseudoSourceValue::getConstantPool(), 0,
5231 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
5233 // Add the halves; easiest way is to swap them into another reg first.
5234 int ShufMask[2] = { 1, -1 };
5235 SDValue Shuf = DAG.getVectorShuffle(MVT::v2f64, dl, Sub,
5236 DAG.getUNDEF(MVT::v2f64), ShufMask);
5237 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::v2f64, Shuf, Sub);
5238 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Add,
5239 DAG.getIntPtrConstant(0));
5242 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
5243 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) {
5244 DebugLoc dl = Op.getDebugLoc();
5245 // FP constant to bias correct the final result.
5246 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
5249 // Load the 32-bit value into an XMM register.
5250 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
5251 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
5253 DAG.getIntPtrConstant(0)));
5255 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
5256 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Load),
5257 DAG.getIntPtrConstant(0));
5259 // Or the load with the bias.
5260 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
5261 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
5262 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5264 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
5265 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5266 MVT::v2f64, Bias)));
5267 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
5268 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Or),
5269 DAG.getIntPtrConstant(0));
5271 // Subtract the bias.
5272 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
5274 // Handle final rounding.
5275 EVT DestVT = Op.getValueType();
5277 if (DestVT.bitsLT(MVT::f64)) {
5278 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
5279 DAG.getIntPtrConstant(0));
5280 } else if (DestVT.bitsGT(MVT::f64)) {
5281 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
5284 // Handle final rounding.
5288 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
5289 SDValue N0 = Op.getOperand(0);
5290 DebugLoc dl = Op.getDebugLoc();
5292 // Now not UINT_TO_FP is legal (it's marked custom), dag combiner won't
5293 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
5294 // the optimization here.
5295 if (DAG.SignBitIsZero(N0))
5296 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
5298 EVT SrcVT = N0.getValueType();
5299 if (SrcVT == MVT::i64) {
5300 // We only handle SSE2 f64 target here; caller can expand the rest.
5301 if (Op.getValueType() != MVT::f64 || !X86ScalarSSEf64)
5304 return LowerUINT_TO_FP_i64(Op, DAG);
5305 } else if (SrcVT == MVT::i32 && X86ScalarSSEf64) {
5306 return LowerUINT_TO_FP_i32(Op, DAG);
5309 assert(SrcVT == MVT::i32 && "Unknown UINT_TO_FP to lower!");
5311 // Make a 64-bit buffer, and use it to build an FILD.
5312 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
5313 SDValue WordOff = DAG.getConstant(4, getPointerTy());
5314 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
5315 getPointerTy(), StackSlot, WordOff);
5316 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
5317 StackSlot, NULL, 0);
5318 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
5319 OffsetSlot, NULL, 0);
5320 return BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
5323 std::pair<SDValue,SDValue> X86TargetLowering::
5324 FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) {
5325 DebugLoc dl = Op.getDebugLoc();
5327 EVT DstTy = Op.getValueType();
5330 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
5334 assert(DstTy.getSimpleVT() <= MVT::i64 &&
5335 DstTy.getSimpleVT() >= MVT::i16 &&
5336 "Unknown FP_TO_SINT to lower!");
5338 // These are really Legal.
5339 if (DstTy == MVT::i32 &&
5340 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
5341 return std::make_pair(SDValue(), SDValue());
5342 if (Subtarget->is64Bit() &&
5343 DstTy == MVT::i64 &&
5344 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
5345 return std::make_pair(SDValue(), SDValue());
5347 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
5349 MachineFunction &MF = DAG.getMachineFunction();
5350 unsigned MemSize = DstTy.getSizeInBits()/8;
5351 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
5352 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5355 switch (DstTy.getSimpleVT().SimpleTy) {
5356 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
5357 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
5358 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
5359 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
5362 SDValue Chain = DAG.getEntryNode();
5363 SDValue Value = Op.getOperand(0);
5364 if (isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) {
5365 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
5366 Chain = DAG.getStore(Chain, dl, Value, StackSlot,
5367 PseudoSourceValue::getFixedStack(SSFI), 0);
5368 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
5370 Chain, StackSlot, DAG.getValueType(Op.getOperand(0).getValueType())
5372 Value = DAG.getNode(X86ISD::FLD, dl, Tys, Ops, 3);
5373 Chain = Value.getValue(1);
5374 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
5375 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5378 // Build the FP_TO_INT*_IN_MEM
5379 SDValue Ops[] = { Chain, Value, StackSlot };
5380 SDValue FIST = DAG.getNode(Opc, dl, MVT::Other, Ops, 3);
5382 return std::make_pair(FIST, StackSlot);
5385 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) {
5386 if (Op.getValueType().isVector()) {
5387 if (Op.getValueType() == MVT::v2i32 &&
5388 Op.getOperand(0).getValueType() == MVT::v2f64) {
5394 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, true);
5395 SDValue FIST = Vals.first, StackSlot = Vals.second;
5396 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
5397 if (FIST.getNode() == 0) return Op;
5400 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
5401 FIST, StackSlot, NULL, 0);
5404 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) {
5405 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, false);
5406 SDValue FIST = Vals.first, StackSlot = Vals.second;
5407 assert(FIST.getNode() && "Unexpected failure");
5410 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
5411 FIST, StackSlot, NULL, 0);
5414 SDValue X86TargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) {
5415 LLVMContext *Context = DAG.getContext();
5416 DebugLoc dl = Op.getDebugLoc();
5417 EVT VT = Op.getValueType();
5420 EltVT = VT.getVectorElementType();
5421 std::vector<Constant*> CV;
5422 if (EltVT == MVT::f64) {
5423 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))));
5427 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))));
5433 Constant *C = ConstantVector::get(CV);
5434 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5435 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
5436 PseudoSourceValue::getConstantPool(), 0,
5438 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
5441 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) {
5442 LLVMContext *Context = DAG.getContext();
5443 DebugLoc dl = Op.getDebugLoc();
5444 EVT VT = Op.getValueType();
5447 EltVT = VT.getVectorElementType();
5448 std::vector<Constant*> CV;
5449 if (EltVT == MVT::f64) {
5450 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)));
5454 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)));
5460 Constant *C = ConstantVector::get(CV);
5461 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5462 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
5463 PseudoSourceValue::getConstantPool(), 0,
5465 if (VT.isVector()) {
5466 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
5467 DAG.getNode(ISD::XOR, dl, MVT::v2i64,
5468 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
5470 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, Mask)));
5472 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
5476 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
5477 LLVMContext *Context = DAG.getContext();
5478 SDValue Op0 = Op.getOperand(0);
5479 SDValue Op1 = Op.getOperand(1);
5480 DebugLoc dl = Op.getDebugLoc();
5481 EVT VT = Op.getValueType();
5482 EVT SrcVT = Op1.getValueType();
5484 // If second operand is smaller, extend it first.
5485 if (SrcVT.bitsLT(VT)) {
5486 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
5489 // And if it is bigger, shrink it first.
5490 if (SrcVT.bitsGT(VT)) {
5491 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
5495 // At this point the operands and the result should have the same
5496 // type, and that won't be f80 since that is not custom lowered.
5498 // First get the sign bit of second operand.
5499 std::vector<Constant*> CV;
5500 if (SrcVT == MVT::f64) {
5501 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))));
5502 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
5504 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))));
5505 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5506 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5507 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5509 Constant *C = ConstantVector::get(CV);
5510 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5511 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
5512 PseudoSourceValue::getConstantPool(), 0,
5514 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
5516 // Shift sign bit right or left if the two operands have different types.
5517 if (SrcVT.bitsGT(VT)) {
5518 // Op0 is MVT::f32, Op1 is MVT::f64.
5519 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
5520 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
5521 DAG.getConstant(32, MVT::i32));
5522 SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4f32, SignBit);
5523 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
5524 DAG.getIntPtrConstant(0));
5527 // Clear first operand sign bit.
5529 if (VT == MVT::f64) {
5530 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
5531 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
5533 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
5534 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5535 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5536 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5538 C = ConstantVector::get(CV);
5539 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5540 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
5541 PseudoSourceValue::getConstantPool(), 0,
5543 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
5545 // Or the value with the sign bit.
5546 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
5549 /// Emit nodes that will be selected as "test Op0,Op0", or something
5551 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
5552 SelectionDAG &DAG) {
5553 DebugLoc dl = Op.getDebugLoc();
5555 // CF and OF aren't always set the way we want. Determine which
5556 // of these we need.
5557 bool NeedCF = false;
5558 bool NeedOF = false;
5560 case X86::COND_A: case X86::COND_AE:
5561 case X86::COND_B: case X86::COND_BE:
5564 case X86::COND_G: case X86::COND_GE:
5565 case X86::COND_L: case X86::COND_LE:
5566 case X86::COND_O: case X86::COND_NO:
5572 // See if we can use the EFLAGS value from the operand instead of
5573 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
5574 // we prove that the arithmetic won't overflow, we can't use OF or CF.
5575 if (Op.getResNo() == 0 && !NeedOF && !NeedCF) {
5576 unsigned Opcode = 0;
5577 unsigned NumOperands = 0;
5578 switch (Op.getNode()->getOpcode()) {
5580 // Due to an isel shortcoming, be conservative if this add is likely to
5581 // be selected as part of a load-modify-store instruction. When the root
5582 // node in a match is a store, isel doesn't know how to remap non-chain
5583 // non-flag uses of other nodes in the match, such as the ADD in this
5584 // case. This leads to the ADD being left around and reselected, with
5585 // the result being two adds in the output.
5586 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
5587 UE = Op.getNode()->use_end(); UI != UE; ++UI)
5588 if (UI->getOpcode() == ISD::STORE)
5590 if (ConstantSDNode *C =
5591 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) {
5592 // An add of one will be selected as an INC.
5593 if (C->getAPIntValue() == 1) {
5594 Opcode = X86ISD::INC;
5598 // An add of negative one (subtract of one) will be selected as a DEC.
5599 if (C->getAPIntValue().isAllOnesValue()) {
5600 Opcode = X86ISD::DEC;
5605 // Otherwise use a regular EFLAGS-setting add.
5606 Opcode = X86ISD::ADD;
5610 // If the primary and result isn't used, don't bother using X86ISD::AND,
5611 // because a TEST instruction will be better.
5612 bool NonFlagUse = false;
5613 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
5614 UE = Op.getNode()->use_end(); UI != UE; ++UI)
5615 if (UI->getOpcode() != ISD::BRCOND &&
5616 (UI->getOpcode() != ISD::SELECT || UI.getOperandNo() != 0) &&
5617 UI->getOpcode() != ISD::SETCC) {
5628 // Due to the ISEL shortcoming noted above, be conservative if this op is
5629 // likely to be selected as part of a load-modify-store instruction.
5630 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
5631 UE = Op.getNode()->use_end(); UI != UE; ++UI)
5632 if (UI->getOpcode() == ISD::STORE)
5634 // Otherwise use a regular EFLAGS-setting instruction.
5635 switch (Op.getNode()->getOpcode()) {
5636 case ISD::SUB: Opcode = X86ISD::SUB; break;
5637 case ISD::OR: Opcode = X86ISD::OR; break;
5638 case ISD::XOR: Opcode = X86ISD::XOR; break;
5639 case ISD::AND: Opcode = X86ISD::AND; break;
5640 default: llvm_unreachable("unexpected operator!");
5651 return SDValue(Op.getNode(), 1);
5657 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
5658 SmallVector<SDValue, 4> Ops;
5659 for (unsigned i = 0; i != NumOperands; ++i)
5660 Ops.push_back(Op.getOperand(i));
5661 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
5662 DAG.ReplaceAllUsesWith(Op, New);
5663 return SDValue(New.getNode(), 1);
5667 // Otherwise just emit a CMP with 0, which is the TEST pattern.
5668 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
5669 DAG.getConstant(0, Op.getValueType()));
5672 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
5674 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
5675 SelectionDAG &DAG) {
5676 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
5677 if (C->getAPIntValue() == 0)
5678 return EmitTest(Op0, X86CC, DAG);
5680 DebugLoc dl = Op0.getDebugLoc();
5681 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
5684 static SDValue LowerToBT(SDValue Op0, SDValue Op1, ISD::CondCode CC,
5685 DebugLoc dl, SelectionDAG &DAG) {
5686 // Lower (X & (1 << N)) == 0 to BT(X, N).
5687 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
5688 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
5689 if (Op0.getOpcode() == ISD::AND &&
5691 Op1.getOpcode() == ISD::Constant &&
5692 cast<ConstantSDNode>(Op1)->getZExtValue() == 0 &&
5693 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
5695 if (Op0.getOperand(1).getOpcode() == ISD::SHL) {
5696 if (ConstantSDNode *Op010C =
5697 dyn_cast<ConstantSDNode>(Op0.getOperand(1).getOperand(0)))
5698 if (Op010C->getZExtValue() == 1) {
5699 LHS = Op0.getOperand(0);
5700 RHS = Op0.getOperand(1).getOperand(1);
5702 } else if (Op0.getOperand(0).getOpcode() == ISD::SHL) {
5703 if (ConstantSDNode *Op000C =
5704 dyn_cast<ConstantSDNode>(Op0.getOperand(0).getOperand(0)))
5705 if (Op000C->getZExtValue() == 1) {
5706 LHS = Op0.getOperand(1);
5707 RHS = Op0.getOperand(0).getOperand(1);
5709 } else if (Op0.getOperand(1).getOpcode() == ISD::Constant) {
5710 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op0.getOperand(1));
5711 SDValue AndLHS = Op0.getOperand(0);
5712 if (AndRHS->getZExtValue() == 1 && AndLHS.getOpcode() == ISD::SRL) {
5713 LHS = AndLHS.getOperand(0);
5714 RHS = AndLHS.getOperand(1);
5718 if (LHS.getNode()) {
5719 // If LHS is i8, promote it to i16 with any_extend. There is no i8 BT
5720 // instruction. Since the shift amount is in-range-or-undefined, we know
5721 // that doing a bittest on the i16 value is ok. We extend to i32 because
5722 // the encoding for the i16 version is larger than the i32 version.
5723 if (LHS.getValueType() == MVT::i8)
5724 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
5726 // If the operand types disagree, extend the shift amount to match. Since
5727 // BT ignores high bits (like shifts) we can use anyextend.
5728 if (LHS.getValueType() != RHS.getValueType())
5729 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
5731 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
5732 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
5733 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
5734 DAG.getConstant(Cond, MVT::i8), BT);
5741 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) {
5742 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
5743 SDValue Op0 = Op.getOperand(0);
5744 SDValue Op1 = Op.getOperand(1);
5745 DebugLoc dl = Op.getDebugLoc();
5746 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
5748 // Optimize to BT if possible.
5749 SDValue NewCond = LowerToBT(Op0, Op1, CC, dl, DAG);
5750 if (NewCond.getNode())
5753 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
5754 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
5755 if (X86CC == X86::COND_INVALID)
5758 SDValue Cond = EmitCmp(Op0, Op1, X86CC, DAG);
5760 // Use sbb x, x to materialize carry bit into a GPR.
5761 if (X86CC == X86::COND_B)
5762 return DAG.getNode(ISD::AND, dl, MVT::i8,
5763 DAG.getNode(X86ISD::SETCC_CARRY, dl, MVT::i8,
5764 DAG.getConstant(X86CC, MVT::i8), Cond),
5765 DAG.getConstant(1, MVT::i8));
5767 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
5768 DAG.getConstant(X86CC, MVT::i8), Cond);
5771 SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
5773 SDValue Op0 = Op.getOperand(0);
5774 SDValue Op1 = Op.getOperand(1);
5775 SDValue CC = Op.getOperand(2);
5776 EVT VT = Op.getValueType();
5777 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
5778 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
5779 DebugLoc dl = Op.getDebugLoc();
5783 EVT VT0 = Op0.getValueType();
5784 assert(VT0 == MVT::v4f32 || VT0 == MVT::v2f64);
5785 unsigned Opc = VT0 == MVT::v4f32 ? X86ISD::CMPPS : X86ISD::CMPPD;
5788 switch (SetCCOpcode) {
5791 case ISD::SETEQ: SSECC = 0; break;
5793 case ISD::SETGT: Swap = true; // Fallthrough
5795 case ISD::SETOLT: SSECC = 1; break;
5797 case ISD::SETGE: Swap = true; // Fallthrough
5799 case ISD::SETOLE: SSECC = 2; break;
5800 case ISD::SETUO: SSECC = 3; break;
5802 case ISD::SETNE: SSECC = 4; break;
5803 case ISD::SETULE: Swap = true;
5804 case ISD::SETUGE: SSECC = 5; break;
5805 case ISD::SETULT: Swap = true;
5806 case ISD::SETUGT: SSECC = 6; break;
5807 case ISD::SETO: SSECC = 7; break;
5810 std::swap(Op0, Op1);
5812 // In the two special cases we can't handle, emit two comparisons.
5814 if (SetCCOpcode == ISD::SETUEQ) {
5816 UNORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(3, MVT::i8));
5817 EQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(0, MVT::i8));
5818 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ);
5820 else if (SetCCOpcode == ISD::SETONE) {
5822 ORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(7, MVT::i8));
5823 NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, MVT::i8));
5824 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ);
5826 llvm_unreachable("Illegal FP comparison");
5828 // Handle all other FP comparisons here.
5829 return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8));
5832 // We are handling one of the integer comparisons here. Since SSE only has
5833 // GT and EQ comparisons for integer, swapping operands and multiple
5834 // operations may be required for some comparisons.
5835 unsigned Opc = 0, EQOpc = 0, GTOpc = 0;
5836 bool Swap = false, Invert = false, FlipSigns = false;
5838 switch (VT.getSimpleVT().SimpleTy) {
5841 case MVT::v16i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break;
5843 case MVT::v8i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break;
5845 case MVT::v4i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break;
5846 case MVT::v2i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break;
5849 switch (SetCCOpcode) {
5851 case ISD::SETNE: Invert = true;
5852 case ISD::SETEQ: Opc = EQOpc; break;
5853 case ISD::SETLT: Swap = true;
5854 case ISD::SETGT: Opc = GTOpc; break;
5855 case ISD::SETGE: Swap = true;
5856 case ISD::SETLE: Opc = GTOpc; Invert = true; break;
5857 case ISD::SETULT: Swap = true;
5858 case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break;
5859 case ISD::SETUGE: Swap = true;
5860 case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break;
5863 std::swap(Op0, Op1);
5865 // Since SSE has no unsigned integer comparisons, we need to flip the sign
5866 // bits of the inputs before performing those operations.
5868 EVT EltVT = VT.getVectorElementType();
5869 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
5871 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
5872 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
5874 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
5875 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
5878 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
5880 // If the logical-not of the result is required, perform that now.
5882 Result = DAG.getNOT(dl, Result, VT);
5887 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
5888 static bool isX86LogicalCmp(SDValue Op) {
5889 unsigned Opc = Op.getNode()->getOpcode();
5890 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI)
5892 if (Op.getResNo() == 1 &&
5893 (Opc == X86ISD::ADD ||
5894 Opc == X86ISD::SUB ||
5895 Opc == X86ISD::SMUL ||
5896 Opc == X86ISD::UMUL ||
5897 Opc == X86ISD::INC ||
5898 Opc == X86ISD::DEC ||
5899 Opc == X86ISD::OR ||
5900 Opc == X86ISD::XOR ||
5901 Opc == X86ISD::AND))
5907 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) {
5908 bool addTest = true;
5909 SDValue Cond = Op.getOperand(0);
5910 DebugLoc dl = Op.getDebugLoc();
5913 if (Cond.getOpcode() == ISD::SETCC) {
5914 SDValue NewCond = LowerSETCC(Cond, DAG);
5915 if (NewCond.getNode())
5919 // Look pass (and (setcc_carry (cmp ...)), 1).
5920 if (Cond.getOpcode() == ISD::AND &&
5921 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
5922 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
5923 if (C && C->getAPIntValue() == 1)
5924 Cond = Cond.getOperand(0);
5927 // If condition flag is set by a X86ISD::CMP, then use it as the condition
5928 // setting operand in place of the X86ISD::SETCC.
5929 if (Cond.getOpcode() == X86ISD::SETCC ||
5930 Cond.getOpcode() == X86ISD::SETCC_CARRY) {
5931 CC = Cond.getOperand(0);
5933 SDValue Cmp = Cond.getOperand(1);
5934 unsigned Opc = Cmp.getOpcode();
5935 EVT VT = Op.getValueType();
5937 bool IllegalFPCMov = false;
5938 if (VT.isFloatingPoint() && !VT.isVector() &&
5939 !isScalarFPTypeInSSEReg(VT)) // FPStack?
5940 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
5942 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
5943 Opc == X86ISD::BT) { // FIXME
5950 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
5951 Cond = EmitTest(Cond, X86::COND_NE, DAG);
5954 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag);
5955 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
5956 // condition is true.
5957 SDValue Ops[] = { Op.getOperand(2), Op.getOperand(1), CC, Cond };
5958 return DAG.getNode(X86ISD::CMOV, dl, VTs, Ops, array_lengthof(Ops));
5961 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
5962 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
5963 // from the AND / OR.
5964 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
5965 Opc = Op.getOpcode();
5966 if (Opc != ISD::OR && Opc != ISD::AND)
5968 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
5969 Op.getOperand(0).hasOneUse() &&
5970 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
5971 Op.getOperand(1).hasOneUse());
5974 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
5975 // 1 and that the SETCC node has a single use.
5976 static bool isXor1OfSetCC(SDValue Op) {
5977 if (Op.getOpcode() != ISD::XOR)
5979 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
5980 if (N1C && N1C->getAPIntValue() == 1) {
5981 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
5982 Op.getOperand(0).hasOneUse();
5987 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) {
5988 bool addTest = true;
5989 SDValue Chain = Op.getOperand(0);
5990 SDValue Cond = Op.getOperand(1);
5991 SDValue Dest = Op.getOperand(2);
5992 DebugLoc dl = Op.getDebugLoc();
5995 if (Cond.getOpcode() == ISD::SETCC) {
5996 SDValue NewCond = LowerSETCC(Cond, DAG);
5997 if (NewCond.getNode())
6001 // FIXME: LowerXALUO doesn't handle these!!
6002 else if (Cond.getOpcode() == X86ISD::ADD ||
6003 Cond.getOpcode() == X86ISD::SUB ||
6004 Cond.getOpcode() == X86ISD::SMUL ||
6005 Cond.getOpcode() == X86ISD::UMUL)
6006 Cond = LowerXALUO(Cond, DAG);
6009 // Look pass (and (setcc_carry (cmp ...)), 1).
6010 if (Cond.getOpcode() == ISD::AND &&
6011 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
6012 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
6013 if (C && C->getAPIntValue() == 1)
6014 Cond = Cond.getOperand(0);
6017 // If condition flag is set by a X86ISD::CMP, then use it as the condition
6018 // setting operand in place of the X86ISD::SETCC.
6019 if (Cond.getOpcode() == X86ISD::SETCC ||
6020 Cond.getOpcode() == X86ISD::SETCC_CARRY) {
6021 CC = Cond.getOperand(0);
6023 SDValue Cmp = Cond.getOperand(1);
6024 unsigned Opc = Cmp.getOpcode();
6025 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
6026 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
6030 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
6034 // These can only come from an arithmetic instruction with overflow,
6035 // e.g. SADDO, UADDO.
6036 Cond = Cond.getNode()->getOperand(1);
6043 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
6044 SDValue Cmp = Cond.getOperand(0).getOperand(1);
6045 if (CondOpc == ISD::OR) {
6046 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
6047 // two branches instead of an explicit OR instruction with a
6049 if (Cmp == Cond.getOperand(1).getOperand(1) &&
6050 isX86LogicalCmp(Cmp)) {
6051 CC = Cond.getOperand(0).getOperand(0);
6052 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
6053 Chain, Dest, CC, Cmp);
6054 CC = Cond.getOperand(1).getOperand(0);
6058 } else { // ISD::AND
6059 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
6060 // two branches instead of an explicit AND instruction with a
6061 // separate test. However, we only do this if this block doesn't
6062 // have a fall-through edge, because this requires an explicit
6063 // jmp when the condition is false.
6064 if (Cmp == Cond.getOperand(1).getOperand(1) &&
6065 isX86LogicalCmp(Cmp) &&
6066 Op.getNode()->hasOneUse()) {
6067 X86::CondCode CCode =
6068 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
6069 CCode = X86::GetOppositeBranchCondition(CCode);
6070 CC = DAG.getConstant(CCode, MVT::i8);
6071 SDValue User = SDValue(*Op.getNode()->use_begin(), 0);
6072 // Look for an unconditional branch following this conditional branch.
6073 // We need this because we need to reverse the successors in order
6074 // to implement FCMP_OEQ.
6075 if (User.getOpcode() == ISD::BR) {
6076 SDValue FalseBB = User.getOperand(1);
6078 DAG.UpdateNodeOperands(User, User.getOperand(0), Dest);
6079 assert(NewBR == User);
6082 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
6083 Chain, Dest, CC, Cmp);
6084 X86::CondCode CCode =
6085 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
6086 CCode = X86::GetOppositeBranchCondition(CCode);
6087 CC = DAG.getConstant(CCode, MVT::i8);
6093 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
6094 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
6095 // It should be transformed during dag combiner except when the condition
6096 // is set by a arithmetics with overflow node.
6097 X86::CondCode CCode =
6098 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
6099 CCode = X86::GetOppositeBranchCondition(CCode);
6100 CC = DAG.getConstant(CCode, MVT::i8);
6101 Cond = Cond.getOperand(0).getOperand(1);
6107 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
6108 Cond = EmitTest(Cond, X86::COND_NE, DAG);
6110 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
6111 Chain, Dest, CC, Cond);
6115 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
6116 // Calls to _alloca is needed to probe the stack when allocating more than 4k
6117 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
6118 // that the guard pages used by the OS virtual memory manager are allocated in
6119 // correct sequence.
6121 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
6122 SelectionDAG &DAG) {
6123 assert(Subtarget->isTargetCygMing() &&
6124 "This should be used only on Cygwin/Mingw targets");
6125 DebugLoc dl = Op.getDebugLoc();
6128 SDValue Chain = Op.getOperand(0);
6129 SDValue Size = Op.getOperand(1);
6130 // FIXME: Ensure alignment here
6134 EVT IntPtr = getPointerTy();
6135 EVT SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32;
6137 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
6139 Chain = DAG.getCopyToReg(Chain, dl, X86::EAX, Size, Flag);
6140 Flag = Chain.getValue(1);
6142 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
6143 SDValue Ops[] = { Chain,
6144 DAG.getTargetExternalSymbol("_alloca", IntPtr),
6145 DAG.getRegister(X86::EAX, IntPtr),
6146 DAG.getRegister(X86StackPtr, SPTy),
6148 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops, 5);
6149 Flag = Chain.getValue(1);
6151 Chain = DAG.getCALLSEQ_END(Chain,
6152 DAG.getIntPtrConstant(0, true),
6153 DAG.getIntPtrConstant(0, true),
6156 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1);
6158 SDValue Ops1[2] = { Chain.getValue(0), Chain };
6159 return DAG.getMergeValues(Ops1, 2, dl);
6163 X86TargetLowering::EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl,
6165 SDValue Dst, SDValue Src,
6166 SDValue Size, unsigned Align,
6168 uint64_t DstSVOff) {
6169 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
6171 // If not DWORD aligned or size is more than the threshold, call the library.
6172 // The libc version is likely to be faster for these cases. It can use the
6173 // address value and run time information about the CPU.
6174 if ((Align & 3) != 0 ||
6176 ConstantSize->getZExtValue() >
6177 getSubtarget()->getMaxInlineSizeThreshold()) {
6178 SDValue InFlag(0, 0);
6180 // Check to see if there is a specialized entry-point for memory zeroing.
6181 ConstantSDNode *V = dyn_cast<ConstantSDNode>(Src);
6183 if (const char *bzeroEntry = V &&
6184 V->isNullValue() ? Subtarget->getBZeroEntry() : 0) {
6185 EVT IntPtr = getPointerTy();
6186 const Type *IntPtrTy = TD->getIntPtrType(*DAG.getContext());
6187 TargetLowering::ArgListTy Args;
6188 TargetLowering::ArgListEntry Entry;
6190 Entry.Ty = IntPtrTy;
6191 Args.push_back(Entry);
6193 Args.push_back(Entry);
6194 std::pair<SDValue,SDValue> CallResult =
6195 LowerCallTo(Chain, Type::getVoidTy(*DAG.getContext()),
6196 false, false, false, false,
6197 0, CallingConv::C, false, /*isReturnValueUsed=*/false,
6198 DAG.getExternalSymbol(bzeroEntry, IntPtr), Args, DAG, dl,
6199 DAG.GetOrdering(Chain.getNode()));
6200 return CallResult.second;
6203 // Otherwise have the target-independent code call memset.
6207 uint64_t SizeVal = ConstantSize->getZExtValue();
6208 SDValue InFlag(0, 0);
6211 ConstantSDNode *ValC = dyn_cast<ConstantSDNode>(Src);
6212 unsigned BytesLeft = 0;
6213 bool TwoRepStos = false;
6216 uint64_t Val = ValC->getZExtValue() & 255;
6218 // If the value is a constant, then we can potentially use larger sets.
6219 switch (Align & 3) {
6220 case 2: // WORD aligned
6223 Val = (Val << 8) | Val;
6225 case 0: // DWORD aligned
6228 Val = (Val << 8) | Val;
6229 Val = (Val << 16) | Val;
6230 if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) { // QWORD aligned
6233 Val = (Val << 32) | Val;
6236 default: // Byte aligned
6239 Count = DAG.getIntPtrConstant(SizeVal);
6243 if (AVT.bitsGT(MVT::i8)) {
6244 unsigned UBytes = AVT.getSizeInBits() / 8;
6245 Count = DAG.getIntPtrConstant(SizeVal / UBytes);
6246 BytesLeft = SizeVal % UBytes;
6249 Chain = DAG.getCopyToReg(Chain, dl, ValReg, DAG.getConstant(Val, AVT),
6251 InFlag = Chain.getValue(1);
6254 Count = DAG.getIntPtrConstant(SizeVal);
6255 Chain = DAG.getCopyToReg(Chain, dl, X86::AL, Src, InFlag);
6256 InFlag = Chain.getValue(1);
6259 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RCX :
6262 InFlag = Chain.getValue(1);
6263 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RDI :
6266 InFlag = Chain.getValue(1);
6268 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6269 SDValue Ops[] = { Chain, DAG.getValueType(AVT), InFlag };
6270 Chain = DAG.getNode(X86ISD::REP_STOS, dl, Tys, Ops, array_lengthof(Ops));
6273 InFlag = Chain.getValue(1);
6275 EVT CVT = Count.getValueType();
6276 SDValue Left = DAG.getNode(ISD::AND, dl, CVT, Count,
6277 DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT));
6278 Chain = DAG.getCopyToReg(Chain, dl, (CVT == MVT::i64) ? X86::RCX :
6281 InFlag = Chain.getValue(1);
6282 Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6283 SDValue Ops[] = { Chain, DAG.getValueType(MVT::i8), InFlag };
6284 Chain = DAG.getNode(X86ISD::REP_STOS, dl, Tys, Ops, array_lengthof(Ops));
6285 } else if (BytesLeft) {
6286 // Handle the last 1 - 7 bytes.
6287 unsigned Offset = SizeVal - BytesLeft;
6288 EVT AddrVT = Dst.getValueType();
6289 EVT SizeVT = Size.getValueType();
6291 Chain = DAG.getMemset(Chain, dl,
6292 DAG.getNode(ISD::ADD, dl, AddrVT, Dst,
6293 DAG.getConstant(Offset, AddrVT)),
6295 DAG.getConstant(BytesLeft, SizeVT),
6296 Align, DstSV, DstSVOff + Offset);
6299 // TODO: Use a Tokenfactor, as in memcpy, instead of a single chain.
6304 X86TargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
6305 SDValue Chain, SDValue Dst, SDValue Src,
6306 SDValue Size, unsigned Align,
6308 const Value *DstSV, uint64_t DstSVOff,
6309 const Value *SrcSV, uint64_t SrcSVOff) {
6310 // This requires the copy size to be a constant, preferrably
6311 // within a subtarget-specific limit.
6312 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
6315 uint64_t SizeVal = ConstantSize->getZExtValue();
6316 if (!AlwaysInline && SizeVal > getSubtarget()->getMaxInlineSizeThreshold())
6319 /// If not DWORD aligned, call the library.
6320 if ((Align & 3) != 0)
6325 if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) // QWORD aligned
6328 unsigned UBytes = AVT.getSizeInBits() / 8;
6329 unsigned CountVal = SizeVal / UBytes;
6330 SDValue Count = DAG.getIntPtrConstant(CountVal);
6331 unsigned BytesLeft = SizeVal % UBytes;
6333 SDValue InFlag(0, 0);
6334 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RCX :
6337 InFlag = Chain.getValue(1);
6338 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RDI :
6341 InFlag = Chain.getValue(1);
6342 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RSI :
6345 InFlag = Chain.getValue(1);
6347 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6348 SDValue Ops[] = { Chain, DAG.getValueType(AVT), InFlag };
6349 SDValue RepMovs = DAG.getNode(X86ISD::REP_MOVS, dl, Tys, Ops,
6350 array_lengthof(Ops));
6352 SmallVector<SDValue, 4> Results;
6353 Results.push_back(RepMovs);
6355 // Handle the last 1 - 7 bytes.
6356 unsigned Offset = SizeVal - BytesLeft;
6357 EVT DstVT = Dst.getValueType();
6358 EVT SrcVT = Src.getValueType();
6359 EVT SizeVT = Size.getValueType();
6360 Results.push_back(DAG.getMemcpy(Chain, dl,
6361 DAG.getNode(ISD::ADD, dl, DstVT, Dst,
6362 DAG.getConstant(Offset, DstVT)),
6363 DAG.getNode(ISD::ADD, dl, SrcVT, Src,
6364 DAG.getConstant(Offset, SrcVT)),
6365 DAG.getConstant(BytesLeft, SizeVT),
6366 Align, AlwaysInline,
6367 DstSV, DstSVOff + Offset,
6368 SrcSV, SrcSVOff + Offset));
6371 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
6372 &Results[0], Results.size());
6375 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) {
6376 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
6377 DebugLoc dl = Op.getDebugLoc();
6379 if (!Subtarget->is64Bit()) {
6380 // vastart just stores the address of the VarArgsFrameIndex slot into the
6381 // memory location argument.
6382 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
6383 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0);
6387 // gp_offset (0 - 6 * 8)
6388 // fp_offset (48 - 48 + 8 * 16)
6389 // overflow_arg_area (point to parameters coming in memory).
6391 SmallVector<SDValue, 8> MemOps;
6392 SDValue FIN = Op.getOperand(1);
6394 SDValue Store = DAG.getStore(Op.getOperand(0), dl,
6395 DAG.getConstant(VarArgsGPOffset, MVT::i32),
6397 MemOps.push_back(Store);
6400 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6401 FIN, DAG.getIntPtrConstant(4));
6402 Store = DAG.getStore(Op.getOperand(0), dl,
6403 DAG.getConstant(VarArgsFPOffset, MVT::i32),
6405 MemOps.push_back(Store);
6407 // Store ptr to overflow_arg_area
6408 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6409 FIN, DAG.getIntPtrConstant(4));
6410 SDValue OVFIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
6411 Store = DAG.getStore(Op.getOperand(0), dl, OVFIN, FIN, SV, 0);
6412 MemOps.push_back(Store);
6414 // Store ptr to reg_save_area.
6415 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6416 FIN, DAG.getIntPtrConstant(8));
6417 SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
6418 Store = DAG.getStore(Op.getOperand(0), dl, RSFIN, FIN, SV, 0);
6419 MemOps.push_back(Store);
6420 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
6421 &MemOps[0], MemOps.size());
6424 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) {
6425 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
6426 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_arg!");
6427 SDValue Chain = Op.getOperand(0);
6428 SDValue SrcPtr = Op.getOperand(1);
6429 SDValue SrcSV = Op.getOperand(2);
6431 llvm_report_error("VAArgInst is not yet implemented for x86-64!");
6435 SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) {
6436 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
6437 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
6438 SDValue Chain = Op.getOperand(0);
6439 SDValue DstPtr = Op.getOperand(1);
6440 SDValue SrcPtr = Op.getOperand(2);
6441 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
6442 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
6443 DebugLoc dl = Op.getDebugLoc();
6445 return DAG.getMemcpy(Chain, dl, DstPtr, SrcPtr,
6446 DAG.getIntPtrConstant(24), 8, false,
6447 DstSV, 0, SrcSV, 0);
6451 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
6452 DebugLoc dl = Op.getDebugLoc();
6453 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
6455 default: return SDValue(); // Don't custom lower most intrinsics.
6456 // Comparison intrinsics.
6457 case Intrinsic::x86_sse_comieq_ss:
6458 case Intrinsic::x86_sse_comilt_ss:
6459 case Intrinsic::x86_sse_comile_ss:
6460 case Intrinsic::x86_sse_comigt_ss:
6461 case Intrinsic::x86_sse_comige_ss:
6462 case Intrinsic::x86_sse_comineq_ss:
6463 case Intrinsic::x86_sse_ucomieq_ss:
6464 case Intrinsic::x86_sse_ucomilt_ss:
6465 case Intrinsic::x86_sse_ucomile_ss:
6466 case Intrinsic::x86_sse_ucomigt_ss:
6467 case Intrinsic::x86_sse_ucomige_ss:
6468 case Intrinsic::x86_sse_ucomineq_ss:
6469 case Intrinsic::x86_sse2_comieq_sd:
6470 case Intrinsic::x86_sse2_comilt_sd:
6471 case Intrinsic::x86_sse2_comile_sd:
6472 case Intrinsic::x86_sse2_comigt_sd:
6473 case Intrinsic::x86_sse2_comige_sd:
6474 case Intrinsic::x86_sse2_comineq_sd:
6475 case Intrinsic::x86_sse2_ucomieq_sd:
6476 case Intrinsic::x86_sse2_ucomilt_sd:
6477 case Intrinsic::x86_sse2_ucomile_sd:
6478 case Intrinsic::x86_sse2_ucomigt_sd:
6479 case Intrinsic::x86_sse2_ucomige_sd:
6480 case Intrinsic::x86_sse2_ucomineq_sd: {
6482 ISD::CondCode CC = ISD::SETCC_INVALID;
6485 case Intrinsic::x86_sse_comieq_ss:
6486 case Intrinsic::x86_sse2_comieq_sd:
6490 case Intrinsic::x86_sse_comilt_ss:
6491 case Intrinsic::x86_sse2_comilt_sd:
6495 case Intrinsic::x86_sse_comile_ss:
6496 case Intrinsic::x86_sse2_comile_sd:
6500 case Intrinsic::x86_sse_comigt_ss:
6501 case Intrinsic::x86_sse2_comigt_sd:
6505 case Intrinsic::x86_sse_comige_ss:
6506 case Intrinsic::x86_sse2_comige_sd:
6510 case Intrinsic::x86_sse_comineq_ss:
6511 case Intrinsic::x86_sse2_comineq_sd:
6515 case Intrinsic::x86_sse_ucomieq_ss:
6516 case Intrinsic::x86_sse2_ucomieq_sd:
6517 Opc = X86ISD::UCOMI;
6520 case Intrinsic::x86_sse_ucomilt_ss:
6521 case Intrinsic::x86_sse2_ucomilt_sd:
6522 Opc = X86ISD::UCOMI;
6525 case Intrinsic::x86_sse_ucomile_ss:
6526 case Intrinsic::x86_sse2_ucomile_sd:
6527 Opc = X86ISD::UCOMI;
6530 case Intrinsic::x86_sse_ucomigt_ss:
6531 case Intrinsic::x86_sse2_ucomigt_sd:
6532 Opc = X86ISD::UCOMI;
6535 case Intrinsic::x86_sse_ucomige_ss:
6536 case Intrinsic::x86_sse2_ucomige_sd:
6537 Opc = X86ISD::UCOMI;
6540 case Intrinsic::x86_sse_ucomineq_ss:
6541 case Intrinsic::x86_sse2_ucomineq_sd:
6542 Opc = X86ISD::UCOMI;
6547 SDValue LHS = Op.getOperand(1);
6548 SDValue RHS = Op.getOperand(2);
6549 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
6550 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
6551 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
6552 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
6553 DAG.getConstant(X86CC, MVT::i8), Cond);
6554 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
6556 // ptest intrinsics. The intrinsic these come from are designed to return
6557 // an integer value, not just an instruction so lower it to the ptest
6558 // pattern and a setcc for the result.
6559 case Intrinsic::x86_sse41_ptestz:
6560 case Intrinsic::x86_sse41_ptestc:
6561 case Intrinsic::x86_sse41_ptestnzc:{
6564 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
6565 case Intrinsic::x86_sse41_ptestz:
6567 X86CC = X86::COND_E;
6569 case Intrinsic::x86_sse41_ptestc:
6571 X86CC = X86::COND_B;
6573 case Intrinsic::x86_sse41_ptestnzc:
6575 X86CC = X86::COND_A;
6579 SDValue LHS = Op.getOperand(1);
6580 SDValue RHS = Op.getOperand(2);
6581 SDValue Test = DAG.getNode(X86ISD::PTEST, dl, MVT::i32, LHS, RHS);
6582 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
6583 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
6584 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
6587 // Fix vector shift instructions where the last operand is a non-immediate
6589 case Intrinsic::x86_sse2_pslli_w:
6590 case Intrinsic::x86_sse2_pslli_d:
6591 case Intrinsic::x86_sse2_pslli_q:
6592 case Intrinsic::x86_sse2_psrli_w:
6593 case Intrinsic::x86_sse2_psrli_d:
6594 case Intrinsic::x86_sse2_psrli_q:
6595 case Intrinsic::x86_sse2_psrai_w:
6596 case Intrinsic::x86_sse2_psrai_d:
6597 case Intrinsic::x86_mmx_pslli_w:
6598 case Intrinsic::x86_mmx_pslli_d:
6599 case Intrinsic::x86_mmx_pslli_q:
6600 case Intrinsic::x86_mmx_psrli_w:
6601 case Intrinsic::x86_mmx_psrli_d:
6602 case Intrinsic::x86_mmx_psrli_q:
6603 case Intrinsic::x86_mmx_psrai_w:
6604 case Intrinsic::x86_mmx_psrai_d: {
6605 SDValue ShAmt = Op.getOperand(2);
6606 if (isa<ConstantSDNode>(ShAmt))
6609 unsigned NewIntNo = 0;
6610 EVT ShAmtVT = MVT::v4i32;
6612 case Intrinsic::x86_sse2_pslli_w:
6613 NewIntNo = Intrinsic::x86_sse2_psll_w;
6615 case Intrinsic::x86_sse2_pslli_d:
6616 NewIntNo = Intrinsic::x86_sse2_psll_d;
6618 case Intrinsic::x86_sse2_pslli_q:
6619 NewIntNo = Intrinsic::x86_sse2_psll_q;
6621 case Intrinsic::x86_sse2_psrli_w:
6622 NewIntNo = Intrinsic::x86_sse2_psrl_w;
6624 case Intrinsic::x86_sse2_psrli_d:
6625 NewIntNo = Intrinsic::x86_sse2_psrl_d;
6627 case Intrinsic::x86_sse2_psrli_q:
6628 NewIntNo = Intrinsic::x86_sse2_psrl_q;
6630 case Intrinsic::x86_sse2_psrai_w:
6631 NewIntNo = Intrinsic::x86_sse2_psra_w;
6633 case Intrinsic::x86_sse2_psrai_d:
6634 NewIntNo = Intrinsic::x86_sse2_psra_d;
6637 ShAmtVT = MVT::v2i32;
6639 case Intrinsic::x86_mmx_pslli_w:
6640 NewIntNo = Intrinsic::x86_mmx_psll_w;
6642 case Intrinsic::x86_mmx_pslli_d:
6643 NewIntNo = Intrinsic::x86_mmx_psll_d;
6645 case Intrinsic::x86_mmx_pslli_q:
6646 NewIntNo = Intrinsic::x86_mmx_psll_q;
6648 case Intrinsic::x86_mmx_psrli_w:
6649 NewIntNo = Intrinsic::x86_mmx_psrl_w;
6651 case Intrinsic::x86_mmx_psrli_d:
6652 NewIntNo = Intrinsic::x86_mmx_psrl_d;
6654 case Intrinsic::x86_mmx_psrli_q:
6655 NewIntNo = Intrinsic::x86_mmx_psrl_q;
6657 case Intrinsic::x86_mmx_psrai_w:
6658 NewIntNo = Intrinsic::x86_mmx_psra_w;
6660 case Intrinsic::x86_mmx_psrai_d:
6661 NewIntNo = Intrinsic::x86_mmx_psra_d;
6663 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
6669 // The vector shift intrinsics with scalars uses 32b shift amounts but
6670 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
6674 ShOps[1] = DAG.getConstant(0, MVT::i32);
6675 if (ShAmtVT == MVT::v4i32) {
6676 ShOps[2] = DAG.getUNDEF(MVT::i32);
6677 ShOps[3] = DAG.getUNDEF(MVT::i32);
6678 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 4);
6680 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2);
6683 EVT VT = Op.getValueType();
6684 ShAmt = DAG.getNode(ISD::BIT_CONVERT, dl, VT, ShAmt);
6685 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6686 DAG.getConstant(NewIntNo, MVT::i32),
6687 Op.getOperand(1), ShAmt);
6692 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) {
6693 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
6694 DebugLoc dl = Op.getDebugLoc();
6697 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
6699 DAG.getConstant(TD->getPointerSize(),
6700 Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
6701 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
6702 DAG.getNode(ISD::ADD, dl, getPointerTy(),
6707 // Just load the return address.
6708 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
6709 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
6710 RetAddrFI, NULL, 0);
6713 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) {
6714 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
6715 MFI->setFrameAddressIsTaken(true);
6716 EVT VT = Op.getValueType();
6717 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
6718 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
6719 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
6720 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
6722 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, NULL, 0);
6726 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
6727 SelectionDAG &DAG) {
6728 return DAG.getIntPtrConstant(2*TD->getPointerSize());
6731 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG)
6733 MachineFunction &MF = DAG.getMachineFunction();
6734 SDValue Chain = Op.getOperand(0);
6735 SDValue Offset = Op.getOperand(1);
6736 SDValue Handler = Op.getOperand(2);
6737 DebugLoc dl = Op.getDebugLoc();
6739 SDValue Frame = DAG.getRegister(Subtarget->is64Bit() ? X86::RBP : X86::EBP,
6741 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
6743 SDValue StoreAddr = DAG.getNode(ISD::SUB, dl, getPointerTy(), Frame,
6744 DAG.getIntPtrConstant(-TD->getPointerSize()));
6745 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
6746 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, NULL, 0);
6747 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
6748 MF.getRegInfo().addLiveOut(StoreAddrReg);
6750 return DAG.getNode(X86ISD::EH_RETURN, dl,
6752 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
6755 SDValue X86TargetLowering::LowerTRAMPOLINE(SDValue Op,
6756 SelectionDAG &DAG) {
6757 SDValue Root = Op.getOperand(0);
6758 SDValue Trmp = Op.getOperand(1); // trampoline
6759 SDValue FPtr = Op.getOperand(2); // nested function
6760 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
6761 DebugLoc dl = Op.getDebugLoc();
6763 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
6765 const X86InstrInfo *TII =
6766 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
6768 if (Subtarget->is64Bit()) {
6769 SDValue OutChains[6];
6771 // Large code-model.
6773 const unsigned char JMP64r = TII->getBaseOpcodeFor(X86::JMP64r);
6774 const unsigned char MOV64ri = TII->getBaseOpcodeFor(X86::MOV64ri);
6776 const unsigned char N86R10 = RegInfo->getX86RegNum(X86::R10);
6777 const unsigned char N86R11 = RegInfo->getX86RegNum(X86::R11);
6779 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
6781 // Load the pointer to the nested function into R11.
6782 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
6783 SDValue Addr = Trmp;
6784 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
6787 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
6788 DAG.getConstant(2, MVT::i64));
6789 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr, TrmpAddr, 2, false, 2);
6791 // Load the 'nest' parameter value into R10.
6792 // R10 is specified in X86CallingConv.td
6793 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
6794 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
6795 DAG.getConstant(10, MVT::i64));
6796 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
6797 Addr, TrmpAddr, 10);
6799 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
6800 DAG.getConstant(12, MVT::i64));
6801 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 12, false, 2);
6803 // Jump to the nested function.
6804 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
6805 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
6806 DAG.getConstant(20, MVT::i64));
6807 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
6808 Addr, TrmpAddr, 20);
6810 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
6811 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
6812 DAG.getConstant(22, MVT::i64));
6813 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
6817 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6) };
6818 return DAG.getMergeValues(Ops, 2, dl);
6820 const Function *Func =
6821 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
6822 CallingConv::ID CC = Func->getCallingConv();
6827 llvm_unreachable("Unsupported calling convention");
6828 case CallingConv::C:
6829 case CallingConv::X86_StdCall: {
6830 // Pass 'nest' parameter in ECX.
6831 // Must be kept in sync with X86CallingConv.td
6834 // Check that ECX wasn't needed by an 'inreg' parameter.
6835 const FunctionType *FTy = Func->getFunctionType();
6836 const AttrListPtr &Attrs = Func->getAttributes();
6838 if (!Attrs.isEmpty() && !Func->isVarArg()) {
6839 unsigned InRegCount = 0;
6842 for (FunctionType::param_iterator I = FTy->param_begin(),
6843 E = FTy->param_end(); I != E; ++I, ++Idx)
6844 if (Attrs.paramHasAttr(Idx, Attribute::InReg))
6845 // FIXME: should only count parameters that are lowered to integers.
6846 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
6848 if (InRegCount > 2) {
6849 llvm_report_error("Nest register in use - reduce number of inreg parameters!");
6854 case CallingConv::X86_FastCall:
6855 case CallingConv::Fast:
6856 // Pass 'nest' parameter in EAX.
6857 // Must be kept in sync with X86CallingConv.td
6862 SDValue OutChains[4];
6865 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
6866 DAG.getConstant(10, MVT::i32));
6867 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
6869 const unsigned char MOV32ri = TII->getBaseOpcodeFor(X86::MOV32ri);
6870 const unsigned char N86Reg = RegInfo->getX86RegNum(NestReg);
6871 OutChains[0] = DAG.getStore(Root, dl,
6872 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
6875 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
6876 DAG.getConstant(1, MVT::i32));
6877 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 1, false, 1);
6879 const unsigned char JMP = TII->getBaseOpcodeFor(X86::JMP);
6880 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
6881 DAG.getConstant(5, MVT::i32));
6882 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
6883 TrmpAddr, 5, false, 1);
6885 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
6886 DAG.getConstant(6, MVT::i32));
6887 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr, TrmpAddr, 6, false, 1);
6890 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4) };
6891 return DAG.getMergeValues(Ops, 2, dl);
6895 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) {
6897 The rounding mode is in bits 11:10 of FPSR, and has the following
6904 FLT_ROUNDS, on the other hand, expects the following:
6911 To perform the conversion, we do:
6912 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
6915 MachineFunction &MF = DAG.getMachineFunction();
6916 const TargetMachine &TM = MF.getTarget();
6917 const TargetFrameInfo &TFI = *TM.getFrameInfo();
6918 unsigned StackAlignment = TFI.getStackAlignment();
6919 EVT VT = Op.getValueType();
6920 DebugLoc dl = Op.getDebugLoc();
6922 // Save FP Control Word to stack slot
6923 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
6924 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
6926 SDValue Chain = DAG.getNode(X86ISD::FNSTCW16m, dl, MVT::Other,
6927 DAG.getEntryNode(), StackSlot);
6929 // Load FP Control Word from stack slot
6930 SDValue CWD = DAG.getLoad(MVT::i16, dl, Chain, StackSlot, NULL, 0);
6932 // Transform as necessary
6934 DAG.getNode(ISD::SRL, dl, MVT::i16,
6935 DAG.getNode(ISD::AND, dl, MVT::i16,
6936 CWD, DAG.getConstant(0x800, MVT::i16)),
6937 DAG.getConstant(11, MVT::i8));
6939 DAG.getNode(ISD::SRL, dl, MVT::i16,
6940 DAG.getNode(ISD::AND, dl, MVT::i16,
6941 CWD, DAG.getConstant(0x400, MVT::i16)),
6942 DAG.getConstant(9, MVT::i8));
6945 DAG.getNode(ISD::AND, dl, MVT::i16,
6946 DAG.getNode(ISD::ADD, dl, MVT::i16,
6947 DAG.getNode(ISD::OR, dl, MVT::i16, CWD1, CWD2),
6948 DAG.getConstant(1, MVT::i16)),
6949 DAG.getConstant(3, MVT::i16));
6952 return DAG.getNode((VT.getSizeInBits() < 16 ?
6953 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
6956 SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
6957 EVT VT = Op.getValueType();
6959 unsigned NumBits = VT.getSizeInBits();
6960 DebugLoc dl = Op.getDebugLoc();
6962 Op = Op.getOperand(0);
6963 if (VT == MVT::i8) {
6964 // Zero extend to i32 since there is not an i8 bsr.
6966 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
6969 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
6970 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
6971 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
6973 // If src is zero (i.e. bsr sets ZF), returns NumBits.
6976 DAG.getConstant(NumBits+NumBits-1, OpVT),
6977 DAG.getConstant(X86::COND_E, MVT::i8),
6980 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
6982 // Finally xor with NumBits-1.
6983 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
6986 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
6990 SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
6991 EVT VT = Op.getValueType();
6993 unsigned NumBits = VT.getSizeInBits();
6994 DebugLoc dl = Op.getDebugLoc();
6996 Op = Op.getOperand(0);
6997 if (VT == MVT::i8) {
6999 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
7002 // Issue a bsf (scan bits forward) which also sets EFLAGS.
7003 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
7004 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
7006 // If src is zero (i.e. bsf sets ZF), returns NumBits.
7009 DAG.getConstant(NumBits, OpVT),
7010 DAG.getConstant(X86::COND_E, MVT::i8),
7013 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
7016 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
7020 SDValue X86TargetLowering::LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG) {
7021 EVT VT = Op.getValueType();
7022 assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply");
7023 DebugLoc dl = Op.getDebugLoc();
7025 // ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32);
7026 // ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32);
7027 // ulong2 AloBlo = __builtin_ia32_pmuludq128( a, b );
7028 // ulong2 AloBhi = __builtin_ia32_pmuludq128( a, Bhi );
7029 // ulong2 AhiBlo = __builtin_ia32_pmuludq128( Ahi, b );
7031 // AloBhi = __builtin_ia32_psllqi128( AloBhi, 32 );
7032 // AhiBlo = __builtin_ia32_psllqi128( AhiBlo, 32 );
7033 // return AloBlo + AloBhi + AhiBlo;
7035 SDValue A = Op.getOperand(0);
7036 SDValue B = Op.getOperand(1);
7038 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7039 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
7040 A, DAG.getConstant(32, MVT::i32));
7041 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7042 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
7043 B, DAG.getConstant(32, MVT::i32));
7044 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7045 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
7047 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7048 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
7050 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7051 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
7053 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7054 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
7055 AloBhi, DAG.getConstant(32, MVT::i32));
7056 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7057 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
7058 AhiBlo, DAG.getConstant(32, MVT::i32));
7059 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
7060 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
7065 SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) {
7066 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
7067 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
7068 // looks for this combo and may remove the "setcc" instruction if the "setcc"
7069 // has only one use.
7070 SDNode *N = Op.getNode();
7071 SDValue LHS = N->getOperand(0);
7072 SDValue RHS = N->getOperand(1);
7073 unsigned BaseOp = 0;
7075 DebugLoc dl = Op.getDebugLoc();
7077 switch (Op.getOpcode()) {
7078 default: llvm_unreachable("Unknown ovf instruction!");
7080 // A subtract of one will be selected as a INC. Note that INC doesn't
7081 // set CF, so we can't do this for UADDO.
7082 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
7083 if (C->getAPIntValue() == 1) {
7084 BaseOp = X86ISD::INC;
7088 BaseOp = X86ISD::ADD;
7092 BaseOp = X86ISD::ADD;
7096 // A subtract of one will be selected as a DEC. Note that DEC doesn't
7097 // set CF, so we can't do this for USUBO.
7098 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
7099 if (C->getAPIntValue() == 1) {
7100 BaseOp = X86ISD::DEC;
7104 BaseOp = X86ISD::SUB;
7108 BaseOp = X86ISD::SUB;
7112 BaseOp = X86ISD::SMUL;
7116 BaseOp = X86ISD::UMUL;
7121 // Also sets EFLAGS.
7122 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
7123 SDValue Sum = DAG.getNode(BaseOp, dl, VTs, LHS, RHS);
7126 DAG.getNode(X86ISD::SETCC, dl, N->getValueType(1),
7127 DAG.getConstant(Cond, MVT::i32), SDValue(Sum.getNode(), 1));
7129 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SetCC);
7133 SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) {
7134 EVT T = Op.getValueType();
7135 DebugLoc dl = Op.getDebugLoc();
7138 switch(T.getSimpleVT().SimpleTy) {
7140 assert(false && "Invalid value type!");
7141 case MVT::i8: Reg = X86::AL; size = 1; break;
7142 case MVT::i16: Reg = X86::AX; size = 2; break;
7143 case MVT::i32: Reg = X86::EAX; size = 4; break;
7145 assert(Subtarget->is64Bit() && "Node not type legal!");
7146 Reg = X86::RAX; size = 8;
7149 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), dl, Reg,
7150 Op.getOperand(2), SDValue());
7151 SDValue Ops[] = { cpIn.getValue(0),
7154 DAG.getTargetConstant(size, MVT::i8),
7156 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
7157 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG_DAG, dl, Tys, Ops, 5);
7159 DAG.getCopyFromReg(Result.getValue(0), dl, Reg, T, Result.getValue(1));
7163 SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
7164 SelectionDAG &DAG) {
7165 assert(Subtarget->is64Bit() && "Result not type legalized?");
7166 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
7167 SDValue TheChain = Op.getOperand(0);
7168 DebugLoc dl = Op.getDebugLoc();
7169 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
7170 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
7171 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
7173 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
7174 DAG.getConstant(32, MVT::i8));
7176 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
7179 return DAG.getMergeValues(Ops, 2, dl);
7182 SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
7183 SDNode *Node = Op.getNode();
7184 DebugLoc dl = Node->getDebugLoc();
7185 EVT T = Node->getValueType(0);
7186 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
7187 DAG.getConstant(0, T), Node->getOperand(2));
7188 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
7189 cast<AtomicSDNode>(Node)->getMemoryVT(),
7190 Node->getOperand(0),
7191 Node->getOperand(1), negOp,
7192 cast<AtomicSDNode>(Node)->getSrcValue(),
7193 cast<AtomicSDNode>(Node)->getAlignment());
7196 /// LowerOperation - Provide custom lowering hooks for some operations.
7198 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
7199 switch (Op.getOpcode()) {
7200 default: llvm_unreachable("Should not custom lower this!");
7201 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG);
7202 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
7203 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
7204 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
7205 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
7206 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
7207 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
7208 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
7209 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
7210 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
7211 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
7212 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
7213 case ISD::SHL_PARTS:
7214 case ISD::SRA_PARTS:
7215 case ISD::SRL_PARTS: return LowerShift(Op, DAG);
7216 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
7217 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
7218 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
7219 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
7220 case ISD::FABS: return LowerFABS(Op, DAG);
7221 case ISD::FNEG: return LowerFNEG(Op, DAG);
7222 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
7223 case ISD::SETCC: return LowerSETCC(Op, DAG);
7224 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
7225 case ISD::SELECT: return LowerSELECT(Op, DAG);
7226 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
7227 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
7228 case ISD::VASTART: return LowerVASTART(Op, DAG);
7229 case ISD::VAARG: return LowerVAARG(Op, DAG);
7230 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
7231 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
7232 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
7233 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
7234 case ISD::FRAME_TO_ARGS_OFFSET:
7235 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
7236 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
7237 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
7238 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG);
7239 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
7240 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
7241 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
7242 case ISD::MUL: return LowerMUL_V2I64(Op, DAG);
7248 case ISD::UMULO: return LowerXALUO(Op, DAG);
7249 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
7253 void X86TargetLowering::
7254 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
7255 SelectionDAG &DAG, unsigned NewOp) {
7256 EVT T = Node->getValueType(0);
7257 DebugLoc dl = Node->getDebugLoc();
7258 assert (T == MVT::i64 && "Only know how to expand i64 atomics");
7260 SDValue Chain = Node->getOperand(0);
7261 SDValue In1 = Node->getOperand(1);
7262 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
7263 Node->getOperand(2), DAG.getIntPtrConstant(0));
7264 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
7265 Node->getOperand(2), DAG.getIntPtrConstant(1));
7266 SDValue Ops[] = { Chain, In1, In2L, In2H };
7267 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
7269 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64,
7270 cast<MemSDNode>(Node)->getMemOperand());
7271 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
7272 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
7273 Results.push_back(Result.getValue(2));
7276 /// ReplaceNodeResults - Replace a node with an illegal result type
7277 /// with a new node built out of custom code.
7278 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
7279 SmallVectorImpl<SDValue>&Results,
7280 SelectionDAG &DAG) {
7281 DebugLoc dl = N->getDebugLoc();
7282 switch (N->getOpcode()) {
7284 assert(false && "Do not know how to custom type legalize this operation!");
7286 case ISD::FP_TO_SINT: {
7287 std::pair<SDValue,SDValue> Vals =
7288 FP_TO_INTHelper(SDValue(N, 0), DAG, true);
7289 SDValue FIST = Vals.first, StackSlot = Vals.second;
7290 if (FIST.getNode() != 0) {
7291 EVT VT = N->getValueType(0);
7292 // Return a load from the stack slot.
7293 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot, NULL, 0));
7297 case ISD::READCYCLECOUNTER: {
7298 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
7299 SDValue TheChain = N->getOperand(0);
7300 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
7301 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
7303 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
7305 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
7306 SDValue Ops[] = { eax, edx };
7307 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
7308 Results.push_back(edx.getValue(1));
7315 EVT WidenVT = getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
7316 Results.push_back(DAG.UnrollVectorOp(N, WidenVT.getVectorNumElements()));
7319 case ISD::ATOMIC_CMP_SWAP: {
7320 EVT T = N->getValueType(0);
7321 assert (T == MVT::i64 && "Only know how to expand i64 Cmp and Swap");
7322 SDValue cpInL, cpInH;
7323 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
7324 DAG.getConstant(0, MVT::i32));
7325 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
7326 DAG.getConstant(1, MVT::i32));
7327 cpInL = DAG.getCopyToReg(N->getOperand(0), dl, X86::EAX, cpInL, SDValue());
7328 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl, X86::EDX, cpInH,
7330 SDValue swapInL, swapInH;
7331 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
7332 DAG.getConstant(0, MVT::i32));
7333 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
7334 DAG.getConstant(1, MVT::i32));
7335 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl, X86::EBX, swapInL,
7337 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl, X86::ECX, swapInH,
7338 swapInL.getValue(1));
7339 SDValue Ops[] = { swapInH.getValue(0),
7341 swapInH.getValue(1) };
7342 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
7343 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG8_DAG, dl, Tys, Ops, 3);
7344 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl, X86::EAX,
7345 MVT::i32, Result.getValue(1));
7346 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl, X86::EDX,
7347 MVT::i32, cpOutL.getValue(2));
7348 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
7349 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
7350 Results.push_back(cpOutH.getValue(1));
7353 case ISD::ATOMIC_LOAD_ADD:
7354 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG);
7356 case ISD::ATOMIC_LOAD_AND:
7357 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG);
7359 case ISD::ATOMIC_LOAD_NAND:
7360 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG);
7362 case ISD::ATOMIC_LOAD_OR:
7363 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG);
7365 case ISD::ATOMIC_LOAD_SUB:
7366 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG);
7368 case ISD::ATOMIC_LOAD_XOR:
7369 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG);
7371 case ISD::ATOMIC_SWAP:
7372 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG);
7377 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
7379 default: return NULL;
7380 case X86ISD::BSF: return "X86ISD::BSF";
7381 case X86ISD::BSR: return "X86ISD::BSR";
7382 case X86ISD::SHLD: return "X86ISD::SHLD";
7383 case X86ISD::SHRD: return "X86ISD::SHRD";
7384 case X86ISD::FAND: return "X86ISD::FAND";
7385 case X86ISD::FOR: return "X86ISD::FOR";
7386 case X86ISD::FXOR: return "X86ISD::FXOR";
7387 case X86ISD::FSRL: return "X86ISD::FSRL";
7388 case X86ISD::FILD: return "X86ISD::FILD";
7389 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
7390 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
7391 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
7392 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
7393 case X86ISD::FLD: return "X86ISD::FLD";
7394 case X86ISD::FST: return "X86ISD::FST";
7395 case X86ISD::CALL: return "X86ISD::CALL";
7396 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
7397 case X86ISD::BT: return "X86ISD::BT";
7398 case X86ISD::CMP: return "X86ISD::CMP";
7399 case X86ISD::COMI: return "X86ISD::COMI";
7400 case X86ISD::UCOMI: return "X86ISD::UCOMI";
7401 case X86ISD::SETCC: return "X86ISD::SETCC";
7402 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
7403 case X86ISD::CMOV: return "X86ISD::CMOV";
7404 case X86ISD::BRCOND: return "X86ISD::BRCOND";
7405 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
7406 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
7407 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
7408 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
7409 case X86ISD::Wrapper: return "X86ISD::Wrapper";
7410 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
7411 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
7412 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
7413 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
7414 case X86ISD::PINSRB: return "X86ISD::PINSRB";
7415 case X86ISD::PINSRW: return "X86ISD::PINSRW";
7416 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
7417 case X86ISD::FMAX: return "X86ISD::FMAX";
7418 case X86ISD::FMIN: return "X86ISD::FMIN";
7419 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
7420 case X86ISD::FRCP: return "X86ISD::FRCP";
7421 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
7422 case X86ISD::SegmentBaseAddress: return "X86ISD::SegmentBaseAddress";
7423 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
7424 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
7425 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
7426 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
7427 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
7428 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
7429 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
7430 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
7431 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
7432 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
7433 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
7434 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
7435 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
7436 case X86ISD::VSHL: return "X86ISD::VSHL";
7437 case X86ISD::VSRL: return "X86ISD::VSRL";
7438 case X86ISD::CMPPD: return "X86ISD::CMPPD";
7439 case X86ISD::CMPPS: return "X86ISD::CMPPS";
7440 case X86ISD::PCMPEQB: return "X86ISD::PCMPEQB";
7441 case X86ISD::PCMPEQW: return "X86ISD::PCMPEQW";
7442 case X86ISD::PCMPEQD: return "X86ISD::PCMPEQD";
7443 case X86ISD::PCMPEQQ: return "X86ISD::PCMPEQQ";
7444 case X86ISD::PCMPGTB: return "X86ISD::PCMPGTB";
7445 case X86ISD::PCMPGTW: return "X86ISD::PCMPGTW";
7446 case X86ISD::PCMPGTD: return "X86ISD::PCMPGTD";
7447 case X86ISD::PCMPGTQ: return "X86ISD::PCMPGTQ";
7448 case X86ISD::ADD: return "X86ISD::ADD";
7449 case X86ISD::SUB: return "X86ISD::SUB";
7450 case X86ISD::SMUL: return "X86ISD::SMUL";
7451 case X86ISD::UMUL: return "X86ISD::UMUL";
7452 case X86ISD::INC: return "X86ISD::INC";
7453 case X86ISD::DEC: return "X86ISD::DEC";
7454 case X86ISD::OR: return "X86ISD::OR";
7455 case X86ISD::XOR: return "X86ISD::XOR";
7456 case X86ISD::AND: return "X86ISD::AND";
7457 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
7458 case X86ISD::PTEST: return "X86ISD::PTEST";
7459 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
7463 // isLegalAddressingMode - Return true if the addressing mode represented
7464 // by AM is legal for this target, for a load/store of the specified type.
7465 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
7466 const Type *Ty) const {
7467 // X86 supports extremely general addressing modes.
7468 CodeModel::Model M = getTargetMachine().getCodeModel();
7470 // X86 allows a sign-extended 32-bit immediate field as a displacement.
7471 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
7476 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
7478 // If a reference to this global requires an extra load, we can't fold it.
7479 if (isGlobalStubReference(GVFlags))
7482 // If BaseGV requires a register for the PIC base, we cannot also have a
7483 // BaseReg specified.
7484 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
7487 // If lower 4G is not available, then we must use rip-relative addressing.
7488 if (Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
7498 // These scales always work.
7503 // These scales are formed with basereg+scalereg. Only accept if there is
7508 default: // Other stuff never works.
7516 bool X86TargetLowering::isTruncateFree(const Type *Ty1, const Type *Ty2) const {
7517 if (!Ty1->isInteger() || !Ty2->isInteger())
7519 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
7520 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
7521 if (NumBits1 <= NumBits2)
7523 return Subtarget->is64Bit() || NumBits1 < 64;
7526 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
7527 if (!VT1.isInteger() || !VT2.isInteger())
7529 unsigned NumBits1 = VT1.getSizeInBits();
7530 unsigned NumBits2 = VT2.getSizeInBits();
7531 if (NumBits1 <= NumBits2)
7533 return Subtarget->is64Bit() || NumBits1 < 64;
7536 bool X86TargetLowering::isZExtFree(const Type *Ty1, const Type *Ty2) const {
7537 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
7538 return Ty1->isInteger(64) && Ty2->isInteger(64) && Subtarget->is64Bit();
7541 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
7542 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
7543 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
7546 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
7547 // i16 instructions are longer (0x66 prefix) and potentially slower.
7548 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
7551 /// isShuffleMaskLegal - Targets can use this to indicate that they only
7552 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
7553 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
7554 /// are assumed to be legal.
7556 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
7558 // Only do shuffles on 128-bit vector types for now.
7559 if (VT.getSizeInBits() == 64)
7562 // FIXME: pshufb, blends, shifts.
7563 return (VT.getVectorNumElements() == 2 ||
7564 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
7565 isMOVLMask(M, VT) ||
7566 isSHUFPMask(M, VT) ||
7567 isPSHUFDMask(M, VT) ||
7568 isPSHUFHWMask(M, VT) ||
7569 isPSHUFLWMask(M, VT) ||
7570 isPALIGNRMask(M, VT, Subtarget->hasSSSE3()) ||
7571 isUNPCKLMask(M, VT) ||
7572 isUNPCKHMask(M, VT) ||
7573 isUNPCKL_v_undef_Mask(M, VT) ||
7574 isUNPCKH_v_undef_Mask(M, VT));
7578 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
7580 unsigned NumElts = VT.getVectorNumElements();
7581 // FIXME: This collection of masks seems suspect.
7584 if (NumElts == 4 && VT.getSizeInBits() == 128) {
7585 return (isMOVLMask(Mask, VT) ||
7586 isCommutedMOVLMask(Mask, VT, true) ||
7587 isSHUFPMask(Mask, VT) ||
7588 isCommutedSHUFPMask(Mask, VT));
7593 //===----------------------------------------------------------------------===//
7594 // X86 Scheduler Hooks
7595 //===----------------------------------------------------------------------===//
7597 // private utility function
7599 X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
7600 MachineBasicBlock *MBB,
7608 TargetRegisterClass *RC,
7609 bool invSrc) const {
7610 // For the atomic bitwise operator, we generate
7613 // ld t1 = [bitinstr.addr]
7614 // op t2 = t1, [bitinstr.val]
7616 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
7618 // fallthrough -->nextMBB
7619 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7620 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
7621 MachineFunction::iterator MBBIter = MBB;
7624 /// First build the CFG
7625 MachineFunction *F = MBB->getParent();
7626 MachineBasicBlock *thisMBB = MBB;
7627 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
7628 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
7629 F->insert(MBBIter, newMBB);
7630 F->insert(MBBIter, nextMBB);
7632 // Move all successors to thisMBB to nextMBB
7633 nextMBB->transferSuccessors(thisMBB);
7635 // Update thisMBB to fall through to newMBB
7636 thisMBB->addSuccessor(newMBB);
7638 // newMBB jumps to itself and fall through to nextMBB
7639 newMBB->addSuccessor(nextMBB);
7640 newMBB->addSuccessor(newMBB);
7642 // Insert instructions into newMBB based on incoming instruction
7643 assert(bInstr->getNumOperands() < X86AddrNumOperands + 4 &&
7644 "unexpected number of operands");
7645 DebugLoc dl = bInstr->getDebugLoc();
7646 MachineOperand& destOper = bInstr->getOperand(0);
7647 MachineOperand* argOpers[2 + X86AddrNumOperands];
7648 int numArgs = bInstr->getNumOperands() - 1;
7649 for (int i=0; i < numArgs; ++i)
7650 argOpers[i] = &bInstr->getOperand(i+1);
7652 // x86 address has 4 operands: base, index, scale, and displacement
7653 int lastAddrIndx = X86AddrNumOperands - 1; // [0,3]
7654 int valArgIndx = lastAddrIndx + 1;
7656 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
7657 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1);
7658 for (int i=0; i <= lastAddrIndx; ++i)
7659 (*MIB).addOperand(*argOpers[i]);
7661 unsigned tt = F->getRegInfo().createVirtualRegister(RC);
7663 MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1);
7668 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
7669 assert((argOpers[valArgIndx]->isReg() ||
7670 argOpers[valArgIndx]->isImm()) &&
7672 if (argOpers[valArgIndx]->isReg())
7673 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2);
7675 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2);
7677 (*MIB).addOperand(*argOpers[valArgIndx]);
7679 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), EAXreg);
7682 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc));
7683 for (int i=0; i <= lastAddrIndx; ++i)
7684 (*MIB).addOperand(*argOpers[i]);
7686 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
7687 (*MIB).setMemRefs(bInstr->memoperands_begin(),
7688 bInstr->memoperands_end());
7690 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), destOper.getReg());
7694 BuildMI(newMBB, dl, TII->get(X86::JNE)).addMBB(newMBB);
7696 F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now.
7700 // private utility function: 64 bit atomics on 32 bit host.
7702 X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
7703 MachineBasicBlock *MBB,
7708 bool invSrc) const {
7709 // For the atomic bitwise operator, we generate
7710 // thisMBB (instructions are in pairs, except cmpxchg8b)
7711 // ld t1,t2 = [bitinstr.addr]
7713 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4)
7714 // op t5, t6 <- out1, out2, [bitinstr.val]
7715 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val])
7716 // mov ECX, EBX <- t5, t6
7717 // mov EAX, EDX <- t1, t2
7718 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit]
7719 // mov t3, t4 <- EAX, EDX
7721 // result in out1, out2
7722 // fallthrough -->nextMBB
7724 const TargetRegisterClass *RC = X86::GR32RegisterClass;
7725 const unsigned LoadOpc = X86::MOV32rm;
7726 const unsigned copyOpc = X86::MOV32rr;
7727 const unsigned NotOpc = X86::NOT32r;
7728 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7729 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
7730 MachineFunction::iterator MBBIter = MBB;
7733 /// First build the CFG
7734 MachineFunction *F = MBB->getParent();
7735 MachineBasicBlock *thisMBB = MBB;
7736 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
7737 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
7738 F->insert(MBBIter, newMBB);
7739 F->insert(MBBIter, nextMBB);
7741 // Move all successors to thisMBB to nextMBB
7742 nextMBB->transferSuccessors(thisMBB);
7744 // Update thisMBB to fall through to newMBB
7745 thisMBB->addSuccessor(newMBB);
7747 // newMBB jumps to itself and fall through to nextMBB
7748 newMBB->addSuccessor(nextMBB);
7749 newMBB->addSuccessor(newMBB);
7751 DebugLoc dl = bInstr->getDebugLoc();
7752 // Insert instructions into newMBB based on incoming instruction
7753 // There are 8 "real" operands plus 9 implicit def/uses, ignored here.
7754 assert(bInstr->getNumOperands() < X86AddrNumOperands + 14 &&
7755 "unexpected number of operands");
7756 MachineOperand& dest1Oper = bInstr->getOperand(0);
7757 MachineOperand& dest2Oper = bInstr->getOperand(1);
7758 MachineOperand* argOpers[2 + X86AddrNumOperands];
7759 for (int i=0; i < 2 + X86AddrNumOperands; ++i)
7760 argOpers[i] = &bInstr->getOperand(i+2);
7762 // x86 address has 4 operands: base, index, scale, and displacement
7763 int lastAddrIndx = X86AddrNumOperands - 1; // [0,3]
7765 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
7766 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1);
7767 for (int i=0; i <= lastAddrIndx; ++i)
7768 (*MIB).addOperand(*argOpers[i]);
7769 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
7770 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2);
7771 // add 4 to displacement.
7772 for (int i=0; i <= lastAddrIndx-2; ++i)
7773 (*MIB).addOperand(*argOpers[i]);
7774 MachineOperand newOp3 = *(argOpers[3]);
7776 newOp3.setImm(newOp3.getImm()+4);
7778 newOp3.setOffset(newOp3.getOffset()+4);
7779 (*MIB).addOperand(newOp3);
7780 (*MIB).addOperand(*argOpers[lastAddrIndx]);
7782 // t3/4 are defined later, at the bottom of the loop
7783 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
7784 unsigned t4 = F->getRegInfo().createVirtualRegister(RC);
7785 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg())
7786 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB);
7787 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg())
7788 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB);
7790 unsigned tt1 = F->getRegInfo().createVirtualRegister(RC);
7791 unsigned tt2 = F->getRegInfo().createVirtualRegister(RC);
7793 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), tt1).addReg(t1);
7794 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), tt2).addReg(t2);
7800 int valArgIndx = lastAddrIndx + 1;
7801 assert((argOpers[valArgIndx]->isReg() ||
7802 argOpers[valArgIndx]->isImm()) &&
7804 unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
7805 unsigned t6 = F->getRegInfo().createVirtualRegister(RC);
7806 if (argOpers[valArgIndx]->isReg())
7807 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5);
7809 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5);
7810 if (regOpcL != X86::MOV32rr)
7812 (*MIB).addOperand(*argOpers[valArgIndx]);
7813 assert(argOpers[valArgIndx + 1]->isReg() ==
7814 argOpers[valArgIndx]->isReg());
7815 assert(argOpers[valArgIndx + 1]->isImm() ==
7816 argOpers[valArgIndx]->isImm());
7817 if (argOpers[valArgIndx + 1]->isReg())
7818 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6);
7820 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6);
7821 if (regOpcH != X86::MOV32rr)
7823 (*MIB).addOperand(*argOpers[valArgIndx + 1]);
7825 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EAX);
7827 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EDX);
7830 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EBX);
7832 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::ECX);
7835 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B));
7836 for (int i=0; i <= lastAddrIndx; ++i)
7837 (*MIB).addOperand(*argOpers[i]);
7839 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
7840 (*MIB).setMemRefs(bInstr->memoperands_begin(),
7841 bInstr->memoperands_end());
7843 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), t3);
7844 MIB.addReg(X86::EAX);
7845 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), t4);
7846 MIB.addReg(X86::EDX);
7849 BuildMI(newMBB, dl, TII->get(X86::JNE)).addMBB(newMBB);
7851 F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now.
7855 // private utility function
7857 X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
7858 MachineBasicBlock *MBB,
7859 unsigned cmovOpc) const {
7860 // For the atomic min/max operator, we generate
7863 // ld t1 = [min/max.addr]
7864 // mov t2 = [min/max.val]
7866 // cmov[cond] t2 = t1
7868 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
7870 // fallthrough -->nextMBB
7872 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7873 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
7874 MachineFunction::iterator MBBIter = MBB;
7877 /// First build the CFG
7878 MachineFunction *F = MBB->getParent();
7879 MachineBasicBlock *thisMBB = MBB;
7880 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
7881 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
7882 F->insert(MBBIter, newMBB);
7883 F->insert(MBBIter, nextMBB);
7885 // Move all successors of thisMBB to nextMBB
7886 nextMBB->transferSuccessors(thisMBB);
7888 // Update thisMBB to fall through to newMBB
7889 thisMBB->addSuccessor(newMBB);
7891 // newMBB jumps to newMBB and fall through to nextMBB
7892 newMBB->addSuccessor(nextMBB);
7893 newMBB->addSuccessor(newMBB);
7895 DebugLoc dl = mInstr->getDebugLoc();
7896 // Insert instructions into newMBB based on incoming instruction
7897 assert(mInstr->getNumOperands() < X86AddrNumOperands + 4 &&
7898 "unexpected number of operands");
7899 MachineOperand& destOper = mInstr->getOperand(0);
7900 MachineOperand* argOpers[2 + X86AddrNumOperands];
7901 int numArgs = mInstr->getNumOperands() - 1;
7902 for (int i=0; i < numArgs; ++i)
7903 argOpers[i] = &mInstr->getOperand(i+1);
7905 // x86 address has 4 operands: base, index, scale, and displacement
7906 int lastAddrIndx = X86AddrNumOperands - 1; // [0,3]
7907 int valArgIndx = lastAddrIndx + 1;
7909 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
7910 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1);
7911 for (int i=0; i <= lastAddrIndx; ++i)
7912 (*MIB).addOperand(*argOpers[i]);
7914 // We only support register and immediate values
7915 assert((argOpers[valArgIndx]->isReg() ||
7916 argOpers[valArgIndx]->isImm()) &&
7919 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
7920 if (argOpers[valArgIndx]->isReg())
7921 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
7923 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
7924 (*MIB).addOperand(*argOpers[valArgIndx]);
7926 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), X86::EAX);
7929 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr));
7934 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
7935 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3);
7939 // Cmp and exchange if none has modified the memory location
7940 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32));
7941 for (int i=0; i <= lastAddrIndx; ++i)
7942 (*MIB).addOperand(*argOpers[i]);
7944 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
7945 (*MIB).setMemRefs(mInstr->memoperands_begin(),
7946 mInstr->memoperands_end());
7948 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), destOper.getReg());
7949 MIB.addReg(X86::EAX);
7952 BuildMI(newMBB, dl, TII->get(X86::JNE)).addMBB(newMBB);
7954 F->DeleteMachineInstr(mInstr); // The pseudo instruction is gone now.
7958 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
7959 // all of this code can be replaced with that in the .td file.
7961 X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB,
7962 unsigned numArgs, bool memArg) const {
7964 MachineFunction *F = BB->getParent();
7965 DebugLoc dl = MI->getDebugLoc();
7966 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7970 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm;
7972 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr;
7974 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(Opc));
7976 for (unsigned i = 0; i < numArgs; ++i) {
7977 MachineOperand &Op = MI->getOperand(i+1);
7979 if (!(Op.isReg() && Op.isImplicit()))
7983 BuildMI(BB, dl, TII->get(X86::MOVAPSrr), MI->getOperand(0).getReg())
7986 F->DeleteMachineInstr(MI);
7992 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
7994 MachineBasicBlock *MBB) const {
7995 // Emit code to save XMM registers to the stack. The ABI says that the
7996 // number of registers to save is given in %al, so it's theoretically
7997 // possible to do an indirect jump trick to avoid saving all of them,
7998 // however this code takes a simpler approach and just executes all
7999 // of the stores if %al is non-zero. It's less code, and it's probably
8000 // easier on the hardware branch predictor, and stores aren't all that
8001 // expensive anyway.
8003 // Create the new basic blocks. One block contains all the XMM stores,
8004 // and one block is the final destination regardless of whether any
8005 // stores were performed.
8006 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
8007 MachineFunction *F = MBB->getParent();
8008 MachineFunction::iterator MBBIter = MBB;
8010 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
8011 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
8012 F->insert(MBBIter, XMMSaveMBB);
8013 F->insert(MBBIter, EndMBB);
8016 // Move any original successors of MBB to the end block.
8017 EndMBB->transferSuccessors(MBB);
8018 // The original block will now fall through to the XMM save block.
8019 MBB->addSuccessor(XMMSaveMBB);
8020 // The XMMSaveMBB will fall through to the end block.
8021 XMMSaveMBB->addSuccessor(EndMBB);
8023 // Now add the instructions.
8024 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8025 DebugLoc DL = MI->getDebugLoc();
8027 unsigned CountReg = MI->getOperand(0).getReg();
8028 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
8029 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
8031 if (!Subtarget->isTargetWin64()) {
8032 // If %al is 0, branch around the XMM save block.
8033 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
8034 BuildMI(MBB, DL, TII->get(X86::JE)).addMBB(EndMBB);
8035 MBB->addSuccessor(EndMBB);
8038 // In the XMM save block, save all the XMM argument registers.
8039 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
8040 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
8041 MachineMemOperand *MMO =
8042 F->getMachineMemOperand(
8043 PseudoSourceValue::getFixedStack(RegSaveFrameIndex),
8044 MachineMemOperand::MOStore, Offset,
8045 /*Size=*/16, /*Align=*/16);
8046 BuildMI(XMMSaveMBB, DL, TII->get(X86::MOVAPSmr))
8047 .addFrameIndex(RegSaveFrameIndex)
8048 .addImm(/*Scale=*/1)
8049 .addReg(/*IndexReg=*/0)
8050 .addImm(/*Disp=*/Offset)
8051 .addReg(/*Segment=*/0)
8052 .addReg(MI->getOperand(i).getReg())
8053 .addMemOperand(MMO);
8056 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
8062 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
8063 MachineBasicBlock *BB,
8064 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const {
8065 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8066 DebugLoc DL = MI->getDebugLoc();
8068 // To "insert" a SELECT_CC instruction, we actually have to insert the
8069 // diamond control-flow pattern. The incoming instruction knows the
8070 // destination vreg to set, the condition code register to branch on, the
8071 // true/false values to select between, and a branch opcode to use.
8072 const BasicBlock *LLVM_BB = BB->getBasicBlock();
8073 MachineFunction::iterator It = BB;
8079 // cmpTY ccX, r1, r2
8081 // fallthrough --> copy0MBB
8082 MachineBasicBlock *thisMBB = BB;
8083 MachineFunction *F = BB->getParent();
8084 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
8085 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
8087 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
8088 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
8089 F->insert(It, copy0MBB);
8090 F->insert(It, sinkMBB);
8091 // Update machine-CFG edges by first adding all successors of the current
8092 // block to the new block which will contain the Phi node for the select.
8093 // Also inform sdisel of the edge changes.
8094 for (MachineBasicBlock::succ_iterator I = BB->succ_begin(),
8095 E = BB->succ_end(); I != E; ++I) {
8096 EM->insert(std::make_pair(*I, sinkMBB));
8097 sinkMBB->addSuccessor(*I);
8099 // Next, remove all successors of the current block, and add the true
8100 // and fallthrough blocks as its successors.
8101 while (!BB->succ_empty())
8102 BB->removeSuccessor(BB->succ_begin());
8103 // Add the true and fallthrough blocks as its successors.
8104 BB->addSuccessor(copy0MBB);
8105 BB->addSuccessor(sinkMBB);
8108 // %FalseValue = ...
8109 // # fallthrough to sinkMBB
8112 // Update machine-CFG edges
8113 BB->addSuccessor(sinkMBB);
8116 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
8119 BuildMI(BB, DL, TII->get(X86::PHI), MI->getOperand(0).getReg())
8120 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
8121 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
8123 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
8129 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
8130 MachineBasicBlock *BB,
8131 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const {
8132 switch (MI->getOpcode()) {
8133 default: assert(false && "Unexpected instr type to insert");
8135 case X86::CMOV_V1I64:
8136 case X86::CMOV_FR32:
8137 case X86::CMOV_FR64:
8138 case X86::CMOV_V4F32:
8139 case X86::CMOV_V2F64:
8140 case X86::CMOV_V2I64:
8141 return EmitLoweredSelect(MI, BB, EM);
8143 case X86::FP32_TO_INT16_IN_MEM:
8144 case X86::FP32_TO_INT32_IN_MEM:
8145 case X86::FP32_TO_INT64_IN_MEM:
8146 case X86::FP64_TO_INT16_IN_MEM:
8147 case X86::FP64_TO_INT32_IN_MEM:
8148 case X86::FP64_TO_INT64_IN_MEM:
8149 case X86::FP80_TO_INT16_IN_MEM:
8150 case X86::FP80_TO_INT32_IN_MEM:
8151 case X86::FP80_TO_INT64_IN_MEM: {
8152 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8153 DebugLoc DL = MI->getDebugLoc();
8155 // Change the floating point control register to use "round towards zero"
8156 // mode when truncating to an integer value.
8157 MachineFunction *F = BB->getParent();
8158 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
8159 addFrameReference(BuildMI(BB, DL, TII->get(X86::FNSTCW16m)), CWFrameIdx);
8161 // Load the old value of the high byte of the control word...
8163 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass);
8164 addFrameReference(BuildMI(BB, DL, TII->get(X86::MOV16rm), OldCW),
8167 // Set the high part to be round to zero...
8168 addFrameReference(BuildMI(BB, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
8171 // Reload the modified control word now...
8172 addFrameReference(BuildMI(BB, DL, TII->get(X86::FLDCW16m)), CWFrameIdx);
8174 // Restore the memory image of control word to original value
8175 addFrameReference(BuildMI(BB, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
8178 // Get the X86 opcode to use.
8180 switch (MI->getOpcode()) {
8181 default: llvm_unreachable("illegal opcode!");
8182 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
8183 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
8184 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
8185 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
8186 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
8187 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
8188 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
8189 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
8190 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
8194 MachineOperand &Op = MI->getOperand(0);
8196 AM.BaseType = X86AddressMode::RegBase;
8197 AM.Base.Reg = Op.getReg();
8199 AM.BaseType = X86AddressMode::FrameIndexBase;
8200 AM.Base.FrameIndex = Op.getIndex();
8202 Op = MI->getOperand(1);
8204 AM.Scale = Op.getImm();
8205 Op = MI->getOperand(2);
8207 AM.IndexReg = Op.getImm();
8208 Op = MI->getOperand(3);
8209 if (Op.isGlobal()) {
8210 AM.GV = Op.getGlobal();
8212 AM.Disp = Op.getImm();
8214 addFullAddress(BuildMI(BB, DL, TII->get(Opc)), AM)
8215 .addReg(MI->getOperand(X86AddrNumOperands).getReg());
8217 // Reload the original control word now.
8218 addFrameReference(BuildMI(BB, DL, TII->get(X86::FLDCW16m)), CWFrameIdx);
8220 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
8223 // String/text processing lowering.
8224 case X86::PCMPISTRM128REG:
8225 return EmitPCMP(MI, BB, 3, false /* in-mem */);
8226 case X86::PCMPISTRM128MEM:
8227 return EmitPCMP(MI, BB, 3, true /* in-mem */);
8228 case X86::PCMPESTRM128REG:
8229 return EmitPCMP(MI, BB, 5, false /* in mem */);
8230 case X86::PCMPESTRM128MEM:
8231 return EmitPCMP(MI, BB, 5, true /* in mem */);
8234 case X86::ATOMAND32:
8235 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
8236 X86::AND32ri, X86::MOV32rm,
8237 X86::LCMPXCHG32, X86::MOV32rr,
8238 X86::NOT32r, X86::EAX,
8239 X86::GR32RegisterClass);
8241 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
8242 X86::OR32ri, X86::MOV32rm,
8243 X86::LCMPXCHG32, X86::MOV32rr,
8244 X86::NOT32r, X86::EAX,
8245 X86::GR32RegisterClass);
8246 case X86::ATOMXOR32:
8247 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
8248 X86::XOR32ri, X86::MOV32rm,
8249 X86::LCMPXCHG32, X86::MOV32rr,
8250 X86::NOT32r, X86::EAX,
8251 X86::GR32RegisterClass);
8252 case X86::ATOMNAND32:
8253 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
8254 X86::AND32ri, X86::MOV32rm,
8255 X86::LCMPXCHG32, X86::MOV32rr,
8256 X86::NOT32r, X86::EAX,
8257 X86::GR32RegisterClass, true);
8258 case X86::ATOMMIN32:
8259 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
8260 case X86::ATOMMAX32:
8261 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
8262 case X86::ATOMUMIN32:
8263 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
8264 case X86::ATOMUMAX32:
8265 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
8267 case X86::ATOMAND16:
8268 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
8269 X86::AND16ri, X86::MOV16rm,
8270 X86::LCMPXCHG16, X86::MOV16rr,
8271 X86::NOT16r, X86::AX,
8272 X86::GR16RegisterClass);
8274 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
8275 X86::OR16ri, X86::MOV16rm,
8276 X86::LCMPXCHG16, X86::MOV16rr,
8277 X86::NOT16r, X86::AX,
8278 X86::GR16RegisterClass);
8279 case X86::ATOMXOR16:
8280 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr,
8281 X86::XOR16ri, X86::MOV16rm,
8282 X86::LCMPXCHG16, X86::MOV16rr,
8283 X86::NOT16r, X86::AX,
8284 X86::GR16RegisterClass);
8285 case X86::ATOMNAND16:
8286 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
8287 X86::AND16ri, X86::MOV16rm,
8288 X86::LCMPXCHG16, X86::MOV16rr,
8289 X86::NOT16r, X86::AX,
8290 X86::GR16RegisterClass, true);
8291 case X86::ATOMMIN16:
8292 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr);
8293 case X86::ATOMMAX16:
8294 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr);
8295 case X86::ATOMUMIN16:
8296 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr);
8297 case X86::ATOMUMAX16:
8298 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr);
8301 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
8302 X86::AND8ri, X86::MOV8rm,
8303 X86::LCMPXCHG8, X86::MOV8rr,
8304 X86::NOT8r, X86::AL,
8305 X86::GR8RegisterClass);
8307 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
8308 X86::OR8ri, X86::MOV8rm,
8309 X86::LCMPXCHG8, X86::MOV8rr,
8310 X86::NOT8r, X86::AL,
8311 X86::GR8RegisterClass);
8313 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr,
8314 X86::XOR8ri, X86::MOV8rm,
8315 X86::LCMPXCHG8, X86::MOV8rr,
8316 X86::NOT8r, X86::AL,
8317 X86::GR8RegisterClass);
8318 case X86::ATOMNAND8:
8319 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
8320 X86::AND8ri, X86::MOV8rm,
8321 X86::LCMPXCHG8, X86::MOV8rr,
8322 X86::NOT8r, X86::AL,
8323 X86::GR8RegisterClass, true);
8324 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
8325 // This group is for 64-bit host.
8326 case X86::ATOMAND64:
8327 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
8328 X86::AND64ri32, X86::MOV64rm,
8329 X86::LCMPXCHG64, X86::MOV64rr,
8330 X86::NOT64r, X86::RAX,
8331 X86::GR64RegisterClass);
8333 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
8334 X86::OR64ri32, X86::MOV64rm,
8335 X86::LCMPXCHG64, X86::MOV64rr,
8336 X86::NOT64r, X86::RAX,
8337 X86::GR64RegisterClass);
8338 case X86::ATOMXOR64:
8339 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr,
8340 X86::XOR64ri32, X86::MOV64rm,
8341 X86::LCMPXCHG64, X86::MOV64rr,
8342 X86::NOT64r, X86::RAX,
8343 X86::GR64RegisterClass);
8344 case X86::ATOMNAND64:
8345 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
8346 X86::AND64ri32, X86::MOV64rm,
8347 X86::LCMPXCHG64, X86::MOV64rr,
8348 X86::NOT64r, X86::RAX,
8349 X86::GR64RegisterClass, true);
8350 case X86::ATOMMIN64:
8351 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr);
8352 case X86::ATOMMAX64:
8353 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr);
8354 case X86::ATOMUMIN64:
8355 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr);
8356 case X86::ATOMUMAX64:
8357 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr);
8359 // This group does 64-bit operations on a 32-bit host.
8360 case X86::ATOMAND6432:
8361 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8362 X86::AND32rr, X86::AND32rr,
8363 X86::AND32ri, X86::AND32ri,
8365 case X86::ATOMOR6432:
8366 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8367 X86::OR32rr, X86::OR32rr,
8368 X86::OR32ri, X86::OR32ri,
8370 case X86::ATOMXOR6432:
8371 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8372 X86::XOR32rr, X86::XOR32rr,
8373 X86::XOR32ri, X86::XOR32ri,
8375 case X86::ATOMNAND6432:
8376 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8377 X86::AND32rr, X86::AND32rr,
8378 X86::AND32ri, X86::AND32ri,
8380 case X86::ATOMADD6432:
8381 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8382 X86::ADD32rr, X86::ADC32rr,
8383 X86::ADD32ri, X86::ADC32ri,
8385 case X86::ATOMSUB6432:
8386 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8387 X86::SUB32rr, X86::SBB32rr,
8388 X86::SUB32ri, X86::SBB32ri,
8390 case X86::ATOMSWAP6432:
8391 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8392 X86::MOV32rr, X86::MOV32rr,
8393 X86::MOV32ri, X86::MOV32ri,
8395 case X86::VASTART_SAVE_XMM_REGS:
8396 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
8400 //===----------------------------------------------------------------------===//
8401 // X86 Optimization Hooks
8402 //===----------------------------------------------------------------------===//
8404 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
8408 const SelectionDAG &DAG,
8409 unsigned Depth) const {
8410 unsigned Opc = Op.getOpcode();
8411 assert((Opc >= ISD::BUILTIN_OP_END ||
8412 Opc == ISD::INTRINSIC_WO_CHAIN ||
8413 Opc == ISD::INTRINSIC_W_CHAIN ||
8414 Opc == ISD::INTRINSIC_VOID) &&
8415 "Should use MaskedValueIsZero if you don't know whether Op"
8416 " is a target node!");
8418 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything.
8430 // These nodes' second result is a boolean.
8431 if (Op.getResNo() == 0)
8435 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(),
8436 Mask.getBitWidth() - 1);
8441 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
8442 /// node is a GlobalAddress + offset.
8443 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
8444 GlobalValue* &GA, int64_t &Offset) const{
8445 if (N->getOpcode() == X86ISD::Wrapper) {
8446 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
8447 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
8448 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
8452 return TargetLowering::isGAPlusOffset(N, GA, Offset);
8455 static bool EltsFromConsecutiveLoads(ShuffleVectorSDNode *N, unsigned NumElems,
8456 EVT EltVT, LoadSDNode *&LDBase,
8457 unsigned &LastLoadedElt,
8458 SelectionDAG &DAG, MachineFrameInfo *MFI,
8459 const TargetLowering &TLI) {
8461 LastLoadedElt = -1U;
8462 for (unsigned i = 0; i < NumElems; ++i) {
8463 if (N->getMaskElt(i) < 0) {
8469 SDValue Elt = DAG.getShuffleScalarElt(N, i);
8470 if (!Elt.getNode() ||
8471 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
8474 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
8476 LDBase = cast<LoadSDNode>(Elt.getNode());
8480 if (Elt.getOpcode() == ISD::UNDEF)
8483 LoadSDNode *LD = cast<LoadSDNode>(Elt);
8484 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
8491 /// PerformShuffleCombine - Combine a vector_shuffle that is equal to
8492 /// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load
8493 /// if the load addresses are consecutive, non-overlapping, and in the right
8494 /// order. In the case of v2i64, it will see if it can rewrite the
8495 /// shuffle to be an appropriate build vector so it can take advantage of
8496 // performBuildVectorCombine.
8497 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
8498 const TargetLowering &TLI) {
8499 DebugLoc dl = N->getDebugLoc();
8500 EVT VT = N->getValueType(0);
8501 EVT EltVT = VT.getVectorElementType();
8502 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
8503 unsigned NumElems = VT.getVectorNumElements();
8505 if (VT.getSizeInBits() != 128)
8508 // Try to combine a vector_shuffle into a 128-bit load.
8509 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
8510 LoadSDNode *LD = NULL;
8511 unsigned LastLoadedElt;
8512 if (!EltsFromConsecutiveLoads(SVN, NumElems, EltVT, LD, LastLoadedElt, DAG,
8516 if (LastLoadedElt == NumElems - 1) {
8517 if (DAG.InferPtrAlignment(LD->getBasePtr()) >= 16)
8518 return DAG.getLoad(VT, dl, LD->getChain(), LD->getBasePtr(),
8519 LD->getSrcValue(), LD->getSrcValueOffset(),
8521 return DAG.getLoad(VT, dl, LD->getChain(), LD->getBasePtr(),
8522 LD->getSrcValue(), LD->getSrcValueOffset(),
8523 LD->isVolatile(), LD->getAlignment());
8524 } else if (NumElems == 4 && LastLoadedElt == 1) {
8525 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
8526 SDValue Ops[] = { LD->getChain(), LD->getBasePtr() };
8527 SDValue ResNode = DAG.getNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2);
8528 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, ResNode);
8533 /// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes.
8534 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
8535 const X86Subtarget *Subtarget) {
8536 DebugLoc DL = N->getDebugLoc();
8537 SDValue Cond = N->getOperand(0);
8538 // Get the LHS/RHS of the select.
8539 SDValue LHS = N->getOperand(1);
8540 SDValue RHS = N->getOperand(2);
8542 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
8543 // instructions have the peculiarity that if either operand is a NaN,
8544 // they chose what we call the RHS operand (and as such are not symmetric).
8545 // It happens that this matches the semantics of the common C idiom
8546 // x<y?x:y and related forms, so we can recognize these cases.
8547 if (Subtarget->hasSSE2() &&
8548 (LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64) &&
8549 Cond.getOpcode() == ISD::SETCC) {
8550 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
8552 unsigned Opcode = 0;
8553 // Check for x CC y ? x : y.
8554 if (LHS == Cond.getOperand(0) && RHS == Cond.getOperand(1)) {
8558 // This can be a min if we can prove that at least one of the operands
8560 if (!FiniteOnlyFPMath()) {
8561 if (DAG.isKnownNeverNaN(RHS)) {
8562 // Put the potential NaN in the RHS so that SSE will preserve it.
8563 std::swap(LHS, RHS);
8564 } else if (!DAG.isKnownNeverNaN(LHS))
8567 Opcode = X86ISD::FMIN;
8570 // This can be a min if we can prove that at least one of the operands
8572 if (!FiniteOnlyFPMath()) {
8573 if (DAG.isKnownNeverNaN(LHS)) {
8574 // Put the potential NaN in the RHS so that SSE will preserve it.
8575 std::swap(LHS, RHS);
8576 } else if (!DAG.isKnownNeverNaN(RHS))
8579 Opcode = X86ISD::FMIN;
8582 // This can be a min, but if either operand is a NaN we need it to
8583 // preserve the original LHS.
8584 std::swap(LHS, RHS);
8588 Opcode = X86ISD::FMIN;
8592 // This can be a max if we can prove that at least one of the operands
8594 if (!FiniteOnlyFPMath()) {
8595 if (DAG.isKnownNeverNaN(LHS)) {
8596 // Put the potential NaN in the RHS so that SSE will preserve it.
8597 std::swap(LHS, RHS);
8598 } else if (!DAG.isKnownNeverNaN(RHS))
8601 Opcode = X86ISD::FMAX;
8604 // This can be a max if we can prove that at least one of the operands
8606 if (!FiniteOnlyFPMath()) {
8607 if (DAG.isKnownNeverNaN(RHS)) {
8608 // Put the potential NaN in the RHS so that SSE will preserve it.
8609 std::swap(LHS, RHS);
8610 } else if (!DAG.isKnownNeverNaN(LHS))
8613 Opcode = X86ISD::FMAX;
8616 // This can be a max, but if either operand is a NaN we need it to
8617 // preserve the original LHS.
8618 std::swap(LHS, RHS);
8622 Opcode = X86ISD::FMAX;
8625 // Check for x CC y ? y : x -- a min/max with reversed arms.
8626 } else if (LHS == Cond.getOperand(1) && RHS == Cond.getOperand(0)) {
8630 // This can be a min if we can prove that at least one of the operands
8632 if (!FiniteOnlyFPMath()) {
8633 if (DAG.isKnownNeverNaN(RHS)) {
8634 // Put the potential NaN in the RHS so that SSE will preserve it.
8635 std::swap(LHS, RHS);
8636 } else if (!DAG.isKnownNeverNaN(LHS))
8639 Opcode = X86ISD::FMIN;
8642 // This can be a min if we can prove that at least one of the operands
8644 if (!FiniteOnlyFPMath()) {
8645 if (DAG.isKnownNeverNaN(LHS)) {
8646 // Put the potential NaN in the RHS so that SSE will preserve it.
8647 std::swap(LHS, RHS);
8648 } else if (!DAG.isKnownNeverNaN(RHS))
8651 Opcode = X86ISD::FMIN;
8654 // This can be a min, but if either operand is a NaN we need it to
8655 // preserve the original LHS.
8656 std::swap(LHS, RHS);
8660 Opcode = X86ISD::FMIN;
8664 // This can be a max if we can prove that at least one of the operands
8666 if (!FiniteOnlyFPMath()) {
8667 if (DAG.isKnownNeverNaN(LHS)) {
8668 // Put the potential NaN in the RHS so that SSE will preserve it.
8669 std::swap(LHS, RHS);
8670 } else if (!DAG.isKnownNeverNaN(RHS))
8673 Opcode = X86ISD::FMAX;
8676 // This can be a max if we can prove that at least one of the operands
8678 if (!FiniteOnlyFPMath()) {
8679 if (DAG.isKnownNeverNaN(RHS)) {
8680 // Put the potential NaN in the RHS so that SSE will preserve it.
8681 std::swap(LHS, RHS);
8682 } else if (!DAG.isKnownNeverNaN(LHS))
8685 Opcode = X86ISD::FMAX;
8688 // This can be a max, but if either operand is a NaN we need it to
8689 // preserve the original LHS.
8690 std::swap(LHS, RHS);
8694 Opcode = X86ISD::FMAX;
8700 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
8703 // If this is a select between two integer constants, try to do some
8705 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
8706 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
8707 // Don't do this for crazy integer types.
8708 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
8709 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
8710 // so that TrueC (the true value) is larger than FalseC.
8711 bool NeedsCondInvert = false;
8713 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
8714 // Efficiently invertible.
8715 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
8716 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
8717 isa<ConstantSDNode>(Cond.getOperand(1))))) {
8718 NeedsCondInvert = true;
8719 std::swap(TrueC, FalseC);
8722 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
8723 if (FalseC->getAPIntValue() == 0 &&
8724 TrueC->getAPIntValue().isPowerOf2()) {
8725 if (NeedsCondInvert) // Invert the condition if needed.
8726 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
8727 DAG.getConstant(1, Cond.getValueType()));
8729 // Zero extend the condition if needed.
8730 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
8732 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
8733 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
8734 DAG.getConstant(ShAmt, MVT::i8));
8737 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
8738 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
8739 if (NeedsCondInvert) // Invert the condition if needed.
8740 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
8741 DAG.getConstant(1, Cond.getValueType()));
8743 // Zero extend the condition if needed.
8744 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
8745 FalseC->getValueType(0), Cond);
8746 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
8747 SDValue(FalseC, 0));
8750 // Optimize cases that will turn into an LEA instruction. This requires
8751 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
8752 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
8753 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
8754 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
8756 bool isFastMultiplier = false;
8758 switch ((unsigned char)Diff) {
8760 case 1: // result = add base, cond
8761 case 2: // result = lea base( , cond*2)
8762 case 3: // result = lea base(cond, cond*2)
8763 case 4: // result = lea base( , cond*4)
8764 case 5: // result = lea base(cond, cond*4)
8765 case 8: // result = lea base( , cond*8)
8766 case 9: // result = lea base(cond, cond*8)
8767 isFastMultiplier = true;
8772 if (isFastMultiplier) {
8773 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
8774 if (NeedsCondInvert) // Invert the condition if needed.
8775 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
8776 DAG.getConstant(1, Cond.getValueType()));
8778 // Zero extend the condition if needed.
8779 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
8781 // Scale the condition by the difference.
8783 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
8784 DAG.getConstant(Diff, Cond.getValueType()));
8786 // Add the base if non-zero.
8787 if (FalseC->getAPIntValue() != 0)
8788 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
8789 SDValue(FalseC, 0));
8799 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
8800 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
8801 TargetLowering::DAGCombinerInfo &DCI) {
8802 DebugLoc DL = N->getDebugLoc();
8804 // If the flag operand isn't dead, don't touch this CMOV.
8805 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
8808 // If this is a select between two integer constants, try to do some
8809 // optimizations. Note that the operands are ordered the opposite of SELECT
8811 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
8812 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
8813 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
8814 // larger than FalseC (the false value).
8815 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
8817 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
8818 CC = X86::GetOppositeBranchCondition(CC);
8819 std::swap(TrueC, FalseC);
8822 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
8823 // This is efficient for any integer data type (including i8/i16) and
8825 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
8826 SDValue Cond = N->getOperand(3);
8827 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
8828 DAG.getConstant(CC, MVT::i8), Cond);
8830 // Zero extend the condition if needed.
8831 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
8833 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
8834 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
8835 DAG.getConstant(ShAmt, MVT::i8));
8836 if (N->getNumValues() == 2) // Dead flag value?
8837 return DCI.CombineTo(N, Cond, SDValue());
8841 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
8842 // for any integer data type, including i8/i16.
8843 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
8844 SDValue Cond = N->getOperand(3);
8845 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
8846 DAG.getConstant(CC, MVT::i8), Cond);
8848 // Zero extend the condition if needed.
8849 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
8850 FalseC->getValueType(0), Cond);
8851 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
8852 SDValue(FalseC, 0));
8854 if (N->getNumValues() == 2) // Dead flag value?
8855 return DCI.CombineTo(N, Cond, SDValue());
8859 // Optimize cases that will turn into an LEA instruction. This requires
8860 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
8861 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
8862 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
8863 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
8865 bool isFastMultiplier = false;
8867 switch ((unsigned char)Diff) {
8869 case 1: // result = add base, cond
8870 case 2: // result = lea base( , cond*2)
8871 case 3: // result = lea base(cond, cond*2)
8872 case 4: // result = lea base( , cond*4)
8873 case 5: // result = lea base(cond, cond*4)
8874 case 8: // result = lea base( , cond*8)
8875 case 9: // result = lea base(cond, cond*8)
8876 isFastMultiplier = true;
8881 if (isFastMultiplier) {
8882 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
8883 SDValue Cond = N->getOperand(3);
8884 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
8885 DAG.getConstant(CC, MVT::i8), Cond);
8886 // Zero extend the condition if needed.
8887 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
8889 // Scale the condition by the difference.
8891 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
8892 DAG.getConstant(Diff, Cond.getValueType()));
8894 // Add the base if non-zero.
8895 if (FalseC->getAPIntValue() != 0)
8896 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
8897 SDValue(FalseC, 0));
8898 if (N->getNumValues() == 2) // Dead flag value?
8899 return DCI.CombineTo(N, Cond, SDValue());
8909 /// PerformMulCombine - Optimize a single multiply with constant into two
8910 /// in order to implement it with two cheaper instructions, e.g.
8911 /// LEA + SHL, LEA + LEA.
8912 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
8913 TargetLowering::DAGCombinerInfo &DCI) {
8914 if (DAG.getMachineFunction().
8915 getFunction()->hasFnAttr(Attribute::OptimizeForSize))
8918 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
8921 EVT VT = N->getValueType(0);
8925 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
8928 uint64_t MulAmt = C->getZExtValue();
8929 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
8932 uint64_t MulAmt1 = 0;
8933 uint64_t MulAmt2 = 0;
8934 if ((MulAmt % 9) == 0) {
8936 MulAmt2 = MulAmt / 9;
8937 } else if ((MulAmt % 5) == 0) {
8939 MulAmt2 = MulAmt / 5;
8940 } else if ((MulAmt % 3) == 0) {
8942 MulAmt2 = MulAmt / 3;
8945 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
8946 DebugLoc DL = N->getDebugLoc();
8948 if (isPowerOf2_64(MulAmt2) &&
8949 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
8950 // If second multiplifer is pow2, issue it first. We want the multiply by
8951 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
8953 std::swap(MulAmt1, MulAmt2);
8956 if (isPowerOf2_64(MulAmt1))
8957 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
8958 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
8960 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
8961 DAG.getConstant(MulAmt1, VT));
8963 if (isPowerOf2_64(MulAmt2))
8964 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
8965 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
8967 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
8968 DAG.getConstant(MulAmt2, VT));
8970 // Do not add new nodes to DAG combiner worklist.
8971 DCI.CombineTo(N, NewMul, false);
8976 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
8977 SDValue N0 = N->getOperand(0);
8978 SDValue N1 = N->getOperand(1);
8979 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
8980 EVT VT = N0.getValueType();
8982 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
8983 // since the result of setcc_c is all zero's or all ones.
8984 if (N1C && N0.getOpcode() == ISD::AND &&
8985 N0.getOperand(1).getOpcode() == ISD::Constant) {
8986 SDValue N00 = N0.getOperand(0);
8987 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
8988 ((N00.getOpcode() == ISD::ANY_EXTEND ||
8989 N00.getOpcode() == ISD::ZERO_EXTEND) &&
8990 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
8991 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
8992 APInt ShAmt = N1C->getAPIntValue();
8993 Mask = Mask.shl(ShAmt);
8995 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
8996 N00, DAG.getConstant(Mask, VT));
9003 /// PerformShiftCombine - Transforms vector shift nodes to use vector shifts
9005 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
9006 const X86Subtarget *Subtarget) {
9007 EVT VT = N->getValueType(0);
9008 if (!VT.isVector() && VT.isInteger() &&
9009 N->getOpcode() == ISD::SHL)
9010 return PerformSHLCombine(N, DAG);
9012 // On X86 with SSE2 support, we can transform this to a vector shift if
9013 // all elements are shifted by the same amount. We can't do this in legalize
9014 // because the a constant vector is typically transformed to a constant pool
9015 // so we have no knowledge of the shift amount.
9016 if (!Subtarget->hasSSE2())
9019 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
9022 SDValue ShAmtOp = N->getOperand(1);
9023 EVT EltVT = VT.getVectorElementType();
9024 DebugLoc DL = N->getDebugLoc();
9025 SDValue BaseShAmt = SDValue();
9026 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
9027 unsigned NumElts = VT.getVectorNumElements();
9029 for (; i != NumElts; ++i) {
9030 SDValue Arg = ShAmtOp.getOperand(i);
9031 if (Arg.getOpcode() == ISD::UNDEF) continue;
9035 for (; i != NumElts; ++i) {
9036 SDValue Arg = ShAmtOp.getOperand(i);
9037 if (Arg.getOpcode() == ISD::UNDEF) continue;
9038 if (Arg != BaseShAmt) {
9042 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
9043 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) {
9044 SDValue InVec = ShAmtOp.getOperand(0);
9045 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
9046 unsigned NumElts = InVec.getValueType().getVectorNumElements();
9048 for (; i != NumElts; ++i) {
9049 SDValue Arg = InVec.getOperand(i);
9050 if (Arg.getOpcode() == ISD::UNDEF) continue;
9054 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
9055 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
9056 unsigned SplatIdx = cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex();
9057 if (C->getZExtValue() == SplatIdx)
9058 BaseShAmt = InVec.getOperand(1);
9061 if (BaseShAmt.getNode() == 0)
9062 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
9063 DAG.getIntPtrConstant(0));
9067 // The shift amount is an i32.
9068 if (EltVT.bitsGT(MVT::i32))
9069 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt);
9070 else if (EltVT.bitsLT(MVT::i32))
9071 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt);
9073 // The shift amount is identical so we can do a vector shift.
9074 SDValue ValOp = N->getOperand(0);
9075 switch (N->getOpcode()) {
9077 llvm_unreachable("Unknown shift opcode!");
9080 if (VT == MVT::v2i64)
9081 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9082 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
9084 if (VT == MVT::v4i32)
9085 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9086 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
9088 if (VT == MVT::v8i16)
9089 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9090 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
9094 if (VT == MVT::v4i32)
9095 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9096 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32),
9098 if (VT == MVT::v8i16)
9099 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9100 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32),
9104 if (VT == MVT::v2i64)
9105 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9106 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
9108 if (VT == MVT::v4i32)
9109 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9110 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32),
9112 if (VT == MVT::v8i16)
9113 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9114 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32),
9121 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
9122 const X86Subtarget *Subtarget) {
9123 EVT VT = N->getValueType(0);
9124 if (VT != MVT::i64 || !Subtarget->is64Bit())
9127 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
9128 SDValue N0 = N->getOperand(0);
9129 SDValue N1 = N->getOperand(1);
9130 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
9132 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
9135 SDValue ShAmt0 = N0.getOperand(1);
9136 if (ShAmt0.getValueType() != MVT::i8)
9138 SDValue ShAmt1 = N1.getOperand(1);
9139 if (ShAmt1.getValueType() != MVT::i8)
9141 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
9142 ShAmt0 = ShAmt0.getOperand(0);
9143 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
9144 ShAmt1 = ShAmt1.getOperand(0);
9146 DebugLoc DL = N->getDebugLoc();
9147 unsigned Opc = X86ISD::SHLD;
9148 SDValue Op0 = N0.getOperand(0);
9149 SDValue Op1 = N1.getOperand(0);
9150 if (ShAmt0.getOpcode() == ISD::SUB) {
9152 std::swap(Op0, Op1);
9153 std::swap(ShAmt0, ShAmt1);
9156 if (ShAmt1.getOpcode() == ISD::SUB) {
9157 SDValue Sum = ShAmt1.getOperand(0);
9158 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
9159 if (SumC->getSExtValue() == 64 &&
9160 ShAmt1.getOperand(1) == ShAmt0)
9161 return DAG.getNode(Opc, DL, VT,
9163 DAG.getNode(ISD::TRUNCATE, DL,
9166 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
9167 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
9169 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == 64)
9170 return DAG.getNode(Opc, DL, VT,
9171 N0.getOperand(0), N1.getOperand(0),
9172 DAG.getNode(ISD::TRUNCATE, DL,
9179 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
9180 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
9181 const X86Subtarget *Subtarget) {
9182 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
9183 // the FP state in cases where an emms may be missing.
9184 // A preferable solution to the general problem is to figure out the right
9185 // places to insert EMMS. This qualifies as a quick hack.
9187 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
9188 StoreSDNode *St = cast<StoreSDNode>(N);
9189 EVT VT = St->getValue().getValueType();
9190 if (VT.getSizeInBits() != 64)
9193 const Function *F = DAG.getMachineFunction().getFunction();
9194 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
9195 bool F64IsLegal = !UseSoftFloat && !NoImplicitFloatOps
9196 && Subtarget->hasSSE2();
9197 if ((VT.isVector() ||
9198 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
9199 isa<LoadSDNode>(St->getValue()) &&
9200 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
9201 St->getChain().hasOneUse() && !St->isVolatile()) {
9202 SDNode* LdVal = St->getValue().getNode();
9204 int TokenFactorIndex = -1;
9205 SmallVector<SDValue, 8> Ops;
9206 SDNode* ChainVal = St->getChain().getNode();
9207 // Must be a store of a load. We currently handle two cases: the load
9208 // is a direct child, and it's under an intervening TokenFactor. It is
9209 // possible to dig deeper under nested TokenFactors.
9210 if (ChainVal == LdVal)
9211 Ld = cast<LoadSDNode>(St->getChain());
9212 else if (St->getValue().hasOneUse() &&
9213 ChainVal->getOpcode() == ISD::TokenFactor) {
9214 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) {
9215 if (ChainVal->getOperand(i).getNode() == LdVal) {
9216 TokenFactorIndex = i;
9217 Ld = cast<LoadSDNode>(St->getValue());
9219 Ops.push_back(ChainVal->getOperand(i));
9223 if (!Ld || !ISD::isNormalLoad(Ld))
9226 // If this is not the MMX case, i.e. we are just turning i64 load/store
9227 // into f64 load/store, avoid the transformation if there are multiple
9228 // uses of the loaded value.
9229 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
9232 DebugLoc LdDL = Ld->getDebugLoc();
9233 DebugLoc StDL = N->getDebugLoc();
9234 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
9235 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
9237 if (Subtarget->is64Bit() || F64IsLegal) {
9238 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
9239 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(),
9240 Ld->getBasePtr(), Ld->getSrcValue(),
9241 Ld->getSrcValueOffset(), Ld->isVolatile(),
9242 Ld->getAlignment());
9243 SDValue NewChain = NewLd.getValue(1);
9244 if (TokenFactorIndex != -1) {
9245 Ops.push_back(NewChain);
9246 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
9249 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
9250 St->getSrcValue(), St->getSrcValueOffset(),
9251 St->isVolatile(), St->getAlignment());
9254 // Otherwise, lower to two pairs of 32-bit loads / stores.
9255 SDValue LoAddr = Ld->getBasePtr();
9256 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
9257 DAG.getConstant(4, MVT::i32));
9259 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
9260 Ld->getSrcValue(), Ld->getSrcValueOffset(),
9261 Ld->isVolatile(), Ld->getAlignment());
9262 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
9263 Ld->getSrcValue(), Ld->getSrcValueOffset()+4,
9265 MinAlign(Ld->getAlignment(), 4));
9267 SDValue NewChain = LoLd.getValue(1);
9268 if (TokenFactorIndex != -1) {
9269 Ops.push_back(LoLd);
9270 Ops.push_back(HiLd);
9271 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
9275 LoAddr = St->getBasePtr();
9276 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
9277 DAG.getConstant(4, MVT::i32));
9279 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
9280 St->getSrcValue(), St->getSrcValueOffset(),
9281 St->isVolatile(), St->getAlignment());
9282 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
9284 St->getSrcValueOffset() + 4,
9286 MinAlign(St->getAlignment(), 4));
9287 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
9292 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
9293 /// X86ISD::FXOR nodes.
9294 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
9295 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
9296 // F[X]OR(0.0, x) -> x
9297 // F[X]OR(x, 0.0) -> x
9298 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
9299 if (C->getValueAPF().isPosZero())
9300 return N->getOperand(1);
9301 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
9302 if (C->getValueAPF().isPosZero())
9303 return N->getOperand(0);
9307 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
9308 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
9309 // FAND(0.0, x) -> 0.0
9310 // FAND(x, 0.0) -> 0.0
9311 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
9312 if (C->getValueAPF().isPosZero())
9313 return N->getOperand(0);
9314 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
9315 if (C->getValueAPF().isPosZero())
9316 return N->getOperand(1);
9320 static SDValue PerformBTCombine(SDNode *N,
9322 TargetLowering::DAGCombinerInfo &DCI) {
9323 // BT ignores high bits in the bit index operand.
9324 SDValue Op1 = N->getOperand(1);
9325 if (Op1.hasOneUse()) {
9326 unsigned BitWidth = Op1.getValueSizeInBits();
9327 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
9328 APInt KnownZero, KnownOne;
9329 TargetLowering::TargetLoweringOpt TLO(DAG);
9330 TargetLowering &TLI = DAG.getTargetLoweringInfo();
9331 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
9332 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
9333 DCI.CommitTargetLoweringOpt(TLO);
9338 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
9339 SDValue Op = N->getOperand(0);
9340 if (Op.getOpcode() == ISD::BIT_CONVERT)
9341 Op = Op.getOperand(0);
9342 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
9343 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
9344 VT.getVectorElementType().getSizeInBits() ==
9345 OpVT.getVectorElementType().getSizeInBits()) {
9346 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, Op);
9351 // On X86 and X86-64, atomic operations are lowered to locked instructions.
9352 // Locked instructions, in turn, have implicit fence semantics (all memory
9353 // operations are flushed before issuing the locked instruction, and the
9354 // are not buffered), so we can fold away the common pattern of
9355 // fence-atomic-fence.
9356 static SDValue PerformMEMBARRIERCombine(SDNode* N, SelectionDAG &DAG) {
9357 SDValue atomic = N->getOperand(0);
9358 switch (atomic.getOpcode()) {
9359 case ISD::ATOMIC_CMP_SWAP:
9360 case ISD::ATOMIC_SWAP:
9361 case ISD::ATOMIC_LOAD_ADD:
9362 case ISD::ATOMIC_LOAD_SUB:
9363 case ISD::ATOMIC_LOAD_AND:
9364 case ISD::ATOMIC_LOAD_OR:
9365 case ISD::ATOMIC_LOAD_XOR:
9366 case ISD::ATOMIC_LOAD_NAND:
9367 case ISD::ATOMIC_LOAD_MIN:
9368 case ISD::ATOMIC_LOAD_MAX:
9369 case ISD::ATOMIC_LOAD_UMIN:
9370 case ISD::ATOMIC_LOAD_UMAX:
9376 SDValue fence = atomic.getOperand(0);
9377 if (fence.getOpcode() != ISD::MEMBARRIER)
9380 switch (atomic.getOpcode()) {
9381 case ISD::ATOMIC_CMP_SWAP:
9382 return DAG.UpdateNodeOperands(atomic, fence.getOperand(0),
9383 atomic.getOperand(1), atomic.getOperand(2),
9384 atomic.getOperand(3));
9385 case ISD::ATOMIC_SWAP:
9386 case ISD::ATOMIC_LOAD_ADD:
9387 case ISD::ATOMIC_LOAD_SUB:
9388 case ISD::ATOMIC_LOAD_AND:
9389 case ISD::ATOMIC_LOAD_OR:
9390 case ISD::ATOMIC_LOAD_XOR:
9391 case ISD::ATOMIC_LOAD_NAND:
9392 case ISD::ATOMIC_LOAD_MIN:
9393 case ISD::ATOMIC_LOAD_MAX:
9394 case ISD::ATOMIC_LOAD_UMIN:
9395 case ISD::ATOMIC_LOAD_UMAX:
9396 return DAG.UpdateNodeOperands(atomic, fence.getOperand(0),
9397 atomic.getOperand(1), atomic.getOperand(2));
9403 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG) {
9404 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
9405 // (and (i32 x86isd::setcc_carry), 1)
9406 // This eliminates the zext. This transformation is necessary because
9407 // ISD::SETCC is always legalized to i8.
9408 DebugLoc dl = N->getDebugLoc();
9409 SDValue N0 = N->getOperand(0);
9410 EVT VT = N->getValueType(0);
9411 if (N0.getOpcode() == ISD::AND &&
9413 N0.getOperand(0).hasOneUse()) {
9414 SDValue N00 = N0.getOperand(0);
9415 if (N00.getOpcode() != X86ISD::SETCC_CARRY)
9417 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
9418 if (!C || C->getZExtValue() != 1)
9420 return DAG.getNode(ISD::AND, dl, VT,
9421 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
9422 N00.getOperand(0), N00.getOperand(1)),
9423 DAG.getConstant(1, VT));
9429 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
9430 DAGCombinerInfo &DCI) const {
9431 SelectionDAG &DAG = DCI.DAG;
9432 switch (N->getOpcode()) {
9434 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, *this);
9435 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget);
9436 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI);
9437 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
9440 case ISD::SRL: return PerformShiftCombine(N, DAG, Subtarget);
9441 case ISD::OR: return PerformOrCombine(N, DAG, Subtarget);
9442 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
9444 case X86ISD::FOR: return PerformFORCombine(N, DAG);
9445 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
9446 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
9447 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
9448 case ISD::MEMBARRIER: return PerformMEMBARRIERCombine(N, DAG);
9449 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG);
9455 //===----------------------------------------------------------------------===//
9456 // X86 Inline Assembly Support
9457 //===----------------------------------------------------------------------===//
9459 static bool LowerToBSwap(CallInst *CI) {
9460 // FIXME: this should verify that we are targetting a 486 or better. If not,
9461 // we will turn this bswap into something that will be lowered to logical ops
9462 // instead of emitting the bswap asm. For now, we don't support 486 or lower
9463 // so don't worry about this.
9465 // Verify this is a simple bswap.
9466 if (CI->getNumOperands() != 2 ||
9467 CI->getType() != CI->getOperand(1)->getType() ||
9468 !CI->getType()->isInteger())
9471 const IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
9472 if (!Ty || Ty->getBitWidth() % 16 != 0)
9475 // Okay, we can do this xform, do so now.
9476 const Type *Tys[] = { Ty };
9477 Module *M = CI->getParent()->getParent()->getParent();
9478 Constant *Int = Intrinsic::getDeclaration(M, Intrinsic::bswap, Tys, 1);
9480 Value *Op = CI->getOperand(1);
9481 Op = CallInst::Create(Int, Op, CI->getName(), CI);
9483 CI->replaceAllUsesWith(Op);
9484 CI->eraseFromParent();
9488 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
9489 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
9490 std::vector<InlineAsm::ConstraintInfo> Constraints = IA->ParseConstraints();
9492 std::string AsmStr = IA->getAsmString();
9494 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
9495 std::vector<std::string> AsmPieces;
9496 SplitString(AsmStr, AsmPieces, "\n"); // ; as separator?
9498 switch (AsmPieces.size()) {
9499 default: return false;
9501 AsmStr = AsmPieces[0];
9503 SplitString(AsmStr, AsmPieces, " \t"); // Split with whitespace.
9506 if (AsmPieces.size() == 2 &&
9507 (AsmPieces[0] == "bswap" ||
9508 AsmPieces[0] == "bswapq" ||
9509 AsmPieces[0] == "bswapl") &&
9510 (AsmPieces[1] == "$0" ||
9511 AsmPieces[1] == "${0:q}")) {
9512 // No need to check constraints, nothing other than the equivalent of
9513 // "=r,0" would be valid here.
9514 return LowerToBSwap(CI);
9516 // rorw $$8, ${0:w} --> llvm.bswap.i16
9517 if (CI->getType()->isInteger(16) &&
9518 AsmPieces.size() == 3 &&
9519 AsmPieces[0] == "rorw" &&
9520 AsmPieces[1] == "$$8," &&
9521 AsmPieces[2] == "${0:w}" &&
9522 IA->getConstraintString() == "=r,0,~{dirflag},~{fpsr},~{flags},~{cc}") {
9523 return LowerToBSwap(CI);
9527 if (CI->getType()->isInteger(64) &&
9528 Constraints.size() >= 2 &&
9529 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
9530 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
9531 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
9532 std::vector<std::string> Words;
9533 SplitString(AsmPieces[0], Words, " \t");
9534 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%eax") {
9536 SplitString(AsmPieces[1], Words, " \t");
9537 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%edx") {
9539 SplitString(AsmPieces[2], Words, " \t,");
9540 if (Words.size() == 3 && Words[0] == "xchgl" && Words[1] == "%eax" &&
9541 Words[2] == "%edx") {
9542 return LowerToBSwap(CI);
9554 /// getConstraintType - Given a constraint letter, return the type of
9555 /// constraint it is for this target.
9556 X86TargetLowering::ConstraintType
9557 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
9558 if (Constraint.size() == 1) {
9559 switch (Constraint[0]) {
9571 return C_RegisterClass;
9579 return TargetLowering::getConstraintType(Constraint);
9582 /// LowerXConstraint - try to replace an X constraint, which matches anything,
9583 /// with another that has more specific requirements based on the type of the
9584 /// corresponding operand.
9585 const char *X86TargetLowering::
9586 LowerXConstraint(EVT ConstraintVT) const {
9587 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
9588 // 'f' like normal targets.
9589 if (ConstraintVT.isFloatingPoint()) {
9590 if (Subtarget->hasSSE2())
9592 if (Subtarget->hasSSE1())
9596 return TargetLowering::LowerXConstraint(ConstraintVT);
9599 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
9600 /// vector. If it is invalid, don't add anything to Ops.
9601 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
9604 std::vector<SDValue>&Ops,
9605 SelectionDAG &DAG) const {
9606 SDValue Result(0, 0);
9608 switch (Constraint) {
9611 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
9612 if (C->getZExtValue() <= 31) {
9613 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
9619 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
9620 if (C->getZExtValue() <= 63) {
9621 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
9627 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
9628 if ((int8_t)C->getSExtValue() == C->getSExtValue()) {
9629 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
9635 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
9636 if (C->getZExtValue() <= 255) {
9637 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
9643 // 32-bit signed value
9644 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
9645 const ConstantInt *CI = C->getConstantIntValue();
9646 if (CI->isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
9647 C->getSExtValue())) {
9648 // Widen to 64 bits here to get it sign extended.
9649 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
9652 // FIXME gcc accepts some relocatable values here too, but only in certain
9653 // memory models; it's complicated.
9658 // 32-bit unsigned value
9659 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
9660 const ConstantInt *CI = C->getConstantIntValue();
9661 if (CI->isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
9662 C->getZExtValue())) {
9663 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
9667 // FIXME gcc accepts some relocatable values here too, but only in certain
9668 // memory models; it's complicated.
9672 // Literal immediates are always ok.
9673 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
9674 // Widen to 64 bits here to get it sign extended.
9675 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
9679 // If we are in non-pic codegen mode, we allow the address of a global (with
9680 // an optional displacement) to be used with 'i'.
9681 GlobalAddressSDNode *GA = 0;
9684 // Match either (GA), (GA+C), (GA+C1+C2), etc.
9686 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
9687 Offset += GA->getOffset();
9689 } else if (Op.getOpcode() == ISD::ADD) {
9690 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
9691 Offset += C->getZExtValue();
9692 Op = Op.getOperand(0);
9695 } else if (Op.getOpcode() == ISD::SUB) {
9696 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
9697 Offset += -C->getZExtValue();
9698 Op = Op.getOperand(0);
9703 // Otherwise, this isn't something we can handle, reject it.
9707 GlobalValue *GV = GA->getGlobal();
9708 // If we require an extra load to get this address, as in PIC mode, we
9710 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
9711 getTargetMachine())))
9715 Op = LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
9717 Op = DAG.getTargetGlobalAddress(GV, GA->getValueType(0), Offset);
9723 if (Result.getNode()) {
9724 Ops.push_back(Result);
9727 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, hasMemory,
9731 std::vector<unsigned> X86TargetLowering::
9732 getRegClassForInlineAsmConstraint(const std::string &Constraint,
9734 if (Constraint.size() == 1) {
9735 // FIXME: not handling fp-stack yet!
9736 switch (Constraint[0]) { // GCC X86 Constraint Letters
9737 default: break; // Unknown constraint letter
9738 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
9739 if (Subtarget->is64Bit()) {
9741 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX,
9742 X86::ESI, X86::EDI, X86::R8D, X86::R9D,
9743 X86::R10D,X86::R11D,X86::R12D,
9744 X86::R13D,X86::R14D,X86::R15D,
9745 X86::EBP, X86::ESP, 0);
9746 else if (VT == MVT::i16)
9747 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX,
9748 X86::SI, X86::DI, X86::R8W,X86::R9W,
9749 X86::R10W,X86::R11W,X86::R12W,
9750 X86::R13W,X86::R14W,X86::R15W,
9751 X86::BP, X86::SP, 0);
9752 else if (VT == MVT::i8)
9753 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL,
9754 X86::SIL, X86::DIL, X86::R8B,X86::R9B,
9755 X86::R10B,X86::R11B,X86::R12B,
9756 X86::R13B,X86::R14B,X86::R15B,
9757 X86::BPL, X86::SPL, 0);
9759 else if (VT == MVT::i64)
9760 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX,
9761 X86::RSI, X86::RDI, X86::R8, X86::R9,
9762 X86::R10, X86::R11, X86::R12,
9763 X86::R13, X86::R14, X86::R15,
9764 X86::RBP, X86::RSP, 0);
9768 // 32-bit fallthrough
9771 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0);
9772 else if (VT == MVT::i16)
9773 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0);
9774 else if (VT == MVT::i8)
9775 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 0);
9776 else if (VT == MVT::i64)
9777 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, 0);
9782 return std::vector<unsigned>();
9785 std::pair<unsigned, const TargetRegisterClass*>
9786 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
9788 // First, see if this is a constraint that directly corresponds to an LLVM
9790 if (Constraint.size() == 1) {
9791 // GCC Constraint Letters
9792 switch (Constraint[0]) {
9794 case 'r': // GENERAL_REGS
9795 case 'l': // INDEX_REGS
9797 return std::make_pair(0U, X86::GR8RegisterClass);
9799 return std::make_pair(0U, X86::GR16RegisterClass);
9800 if (VT == MVT::i32 || !Subtarget->is64Bit())
9801 return std::make_pair(0U, X86::GR32RegisterClass);
9802 return std::make_pair(0U, X86::GR64RegisterClass);
9803 case 'R': // LEGACY_REGS
9805 return std::make_pair(0U, X86::GR8_NOREXRegisterClass);
9807 return std::make_pair(0U, X86::GR16_NOREXRegisterClass);
9808 if (VT == MVT::i32 || !Subtarget->is64Bit())
9809 return std::make_pair(0U, X86::GR32_NOREXRegisterClass);
9810 return std::make_pair(0U, X86::GR64_NOREXRegisterClass);
9811 case 'f': // FP Stack registers.
9812 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
9813 // value to the correct fpstack register class.
9814 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
9815 return std::make_pair(0U, X86::RFP32RegisterClass);
9816 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
9817 return std::make_pair(0U, X86::RFP64RegisterClass);
9818 return std::make_pair(0U, X86::RFP80RegisterClass);
9819 case 'y': // MMX_REGS if MMX allowed.
9820 if (!Subtarget->hasMMX()) break;
9821 return std::make_pair(0U, X86::VR64RegisterClass);
9822 case 'Y': // SSE_REGS if SSE2 allowed
9823 if (!Subtarget->hasSSE2()) break;
9825 case 'x': // SSE_REGS if SSE1 allowed
9826 if (!Subtarget->hasSSE1()) break;
9828 switch (VT.getSimpleVT().SimpleTy) {
9830 // Scalar SSE types.
9833 return std::make_pair(0U, X86::FR32RegisterClass);
9836 return std::make_pair(0U, X86::FR64RegisterClass);
9844 return std::make_pair(0U, X86::VR128RegisterClass);
9850 // Use the default implementation in TargetLowering to convert the register
9851 // constraint into a member of a register class.
9852 std::pair<unsigned, const TargetRegisterClass*> Res;
9853 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
9855 // Not found as a standard register?
9856 if (Res.second == 0) {
9857 // Map st(0) -> st(7) -> ST0
9858 if (Constraint.size() == 7 && Constraint[0] == '{' &&
9859 tolower(Constraint[1]) == 's' &&
9860 tolower(Constraint[2]) == 't' &&
9861 Constraint[3] == '(' &&
9862 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
9863 Constraint[5] == ')' &&
9864 Constraint[6] == '}') {
9866 Res.first = X86::ST0+Constraint[4]-'0';
9867 Res.second = X86::RFP80RegisterClass;
9871 // GCC allows "st(0)" to be called just plain "st".
9872 if (StringRef("{st}").equals_lower(Constraint)) {
9873 Res.first = X86::ST0;
9874 Res.second = X86::RFP80RegisterClass;
9879 if (StringRef("{flags}").equals_lower(Constraint)) {
9880 Res.first = X86::EFLAGS;
9881 Res.second = X86::CCRRegisterClass;
9885 // 'A' means EAX + EDX.
9886 if (Constraint == "A") {
9887 Res.first = X86::EAX;
9888 Res.second = X86::GR32_ADRegisterClass;
9894 // Otherwise, check to see if this is a register class of the wrong value
9895 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
9896 // turn into {ax},{dx}.
9897 if (Res.second->hasType(VT))
9898 return Res; // Correct type already, nothing to do.
9900 // All of the single-register GCC register classes map their values onto
9901 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
9902 // really want an 8-bit or 32-bit register, map to the appropriate register
9903 // class and return the appropriate register.
9904 if (Res.second == X86::GR16RegisterClass) {
9905 if (VT == MVT::i8) {
9906 unsigned DestReg = 0;
9907 switch (Res.first) {
9909 case X86::AX: DestReg = X86::AL; break;
9910 case X86::DX: DestReg = X86::DL; break;
9911 case X86::CX: DestReg = X86::CL; break;
9912 case X86::BX: DestReg = X86::BL; break;
9915 Res.first = DestReg;
9916 Res.second = X86::GR8RegisterClass;
9918 } else if (VT == MVT::i32) {
9919 unsigned DestReg = 0;
9920 switch (Res.first) {
9922 case X86::AX: DestReg = X86::EAX; break;
9923 case X86::DX: DestReg = X86::EDX; break;
9924 case X86::CX: DestReg = X86::ECX; break;
9925 case X86::BX: DestReg = X86::EBX; break;
9926 case X86::SI: DestReg = X86::ESI; break;
9927 case X86::DI: DestReg = X86::EDI; break;
9928 case X86::BP: DestReg = X86::EBP; break;
9929 case X86::SP: DestReg = X86::ESP; break;
9932 Res.first = DestReg;
9933 Res.second = X86::GR32RegisterClass;
9935 } else if (VT == MVT::i64) {
9936 unsigned DestReg = 0;
9937 switch (Res.first) {
9939 case X86::AX: DestReg = X86::RAX; break;
9940 case X86::DX: DestReg = X86::RDX; break;
9941 case X86::CX: DestReg = X86::RCX; break;
9942 case X86::BX: DestReg = X86::RBX; break;
9943 case X86::SI: DestReg = X86::RSI; break;
9944 case X86::DI: DestReg = X86::RDI; break;
9945 case X86::BP: DestReg = X86::RBP; break;
9946 case X86::SP: DestReg = X86::RSP; break;
9949 Res.first = DestReg;
9950 Res.second = X86::GR64RegisterClass;
9953 } else if (Res.second == X86::FR32RegisterClass ||
9954 Res.second == X86::FR64RegisterClass ||
9955 Res.second == X86::VR128RegisterClass) {
9956 // Handle references to XMM physical registers that got mapped into the
9957 // wrong class. This can happen with constraints like {xmm0} where the
9958 // target independent register mapper will just pick the first match it can
9959 // find, ignoring the required type.
9961 Res.second = X86::FR32RegisterClass;
9962 else if (VT == MVT::f64)
9963 Res.second = X86::FR64RegisterClass;
9964 else if (X86::VR128RegisterClass->hasType(VT))
9965 Res.second = X86::VR128RegisterClass;
9971 //===----------------------------------------------------------------------===//
9972 // X86 Widen vector type
9973 //===----------------------------------------------------------------------===//
9975 /// getWidenVectorType: given a vector type, returns the type to widen
9976 /// to (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself.
9977 /// If there is no vector type that we want to widen to, returns MVT::Other
9978 /// When and where to widen is target dependent based on the cost of
9979 /// scalarizing vs using the wider vector type.
9981 EVT X86TargetLowering::getWidenVectorType(EVT VT) const {
9982 assert(VT.isVector());
9983 if (isTypeLegal(VT))
9986 // TODO: In computeRegisterProperty, we can compute the list of legal vector
9987 // type based on element type. This would speed up our search (though
9988 // it may not be worth it since the size of the list is relatively
9990 EVT EltVT = VT.getVectorElementType();
9991 unsigned NElts = VT.getVectorNumElements();
9993 // On X86, it make sense to widen any vector wider than 1
9997 for (unsigned nVT = MVT::FIRST_VECTOR_VALUETYPE;
9998 nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
9999 EVT SVT = (MVT::SimpleValueType)nVT;
10001 if (isTypeLegal(SVT) &&
10002 SVT.getVectorElementType() == EltVT &&
10003 SVT.getVectorNumElements() > NElts)